diff --git a/CMakePresets.json b/CMakePresets.json index 832c952..b3b4444 100644 --- a/CMakePresets.json +++ b/CMakePresets.json @@ -45,7 +45,7 @@ "USE_LUA_ST": true, "USE_TALNET": true, "USE_LWIP": true, - //"USE_PRINT": true, + "USE_PRINT": true, "PRINT_ID": "3", "USE_FREERTOS": true } diff --git a/Core/Src/main.c b/Core/Src/main.c index 9980fe1..5523f39 100644 --- a/Core/Src/main.c +++ b/Core/Src/main.c @@ -263,7 +263,7 @@ void MPU_Config(void) /** Initializes and configures the Region and the memory to be protected */ MPU_InitStruct.Number = MPU_REGION_NUMBER2; - MPU_InitStruct.BaseAddress = 0x30004000; + MPU_InitStruct.BaseAddress = 0x30008000; MPU_InitStruct.Size = MPU_REGION_SIZE_16KB; MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1; MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE; diff --git a/LWIP/Target/lwipopts.h b/LWIP/Target/lwipopts.h index ea3098e..8f69b04 100644 --- a/LWIP/Target/lwipopts.h +++ b/LWIP/Target/lwipopts.h @@ -52,7 +52,7 @@ /*----- Value in opt.h for MEM_ALIGNMENT: 1 -----*/ #define MEM_ALIGNMENT 4 /*----- Default Value for H7 devices: 0x30004000 -----*/ -#define LWIP_RAM_HEAP_POINTER 0x30004000 +#define LWIP_RAM_HEAP_POINTER 0x30008000 /*----- Value supported for H7 devices: 1 -----*/ #define LWIP_SUPPORT_CUSTOM_PBUF 1 /*----- Value in opt.h for LWIP_ETHERNET: LWIP_ARP || PPPOE_SUPPORT -*/ diff --git a/STM32H743XG_FLASH.ld b/STM32H743XG_FLASH.ld index 228a3af..d89208b 100644 --- a/STM32H743XG_FLASH.ld +++ b/STM32H743XG_FLASH.ld @@ -251,6 +251,10 @@ SECTIONS . = ABSOLUTE(0x30000100); *(.Rx_PoolSection) + + . = ABSOLUTE(0x30008000); + *(.LwipHeapSection) + *(.LwipHeapSection*) } >RAM_D2 .dma_buffer (NOLOAD) : diff --git a/robot b/robot index 07ad6cb..2904dc2 160000 --- a/robot +++ b/robot @@ -1 +1 @@ -Subproject commit 07ad6cb9308feb5b96ee8c341b0de719a7d87cea +Subproject commit 2904dc28a06b327f139a121bc01afb01740f446f diff --git a/robot_h743.ioc b/robot_h743.ioc index 593ca6f..6d9151e 100644 --- a/robot_h743.ioc +++ b/robot_h743.ioc @@ -17,7 +17,7 @@ CORTEX_M7.AccessPermission-Cortex_Memory_Protection_Unit_Region2_Settings=MPU_RE CORTEX_M7.AccessPermission-Cortex_Memory_Protection_Unit_Region3_Settings=MPU_REGION_FULL_ACCESS CORTEX_M7.BaseAddress-Cortex_Memory_Protection_Unit_Region0_Settings=0 CORTEX_M7.BaseAddress-Cortex_Memory_Protection_Unit_Region1_Settings=0x30000000 -CORTEX_M7.BaseAddress-Cortex_Memory_Protection_Unit_Region2_Settings=0x30004000 +CORTEX_M7.BaseAddress-Cortex_Memory_Protection_Unit_Region2_Settings=0x30008000 CORTEX_M7.BaseAddress-Cortex_Memory_Protection_Unit_Region3_Settings=0x24000000 CORTEX_M7.CPU_DCache=Enabled CORTEX_M7.CPU_ICache=Enabled @@ -364,10 +364,11 @@ LWIP.DEFAULT_ACCEPTMBOX_SIZE=6 LWIP.DEFAULT_TCP_RECVMBOX_SIZE=6 LWIP.ETHARP_DEBUG=LWIP_DBG_OFF LWIP.GATEWAY_ADDRESS=192.168.001.001 -LWIP.IPParameters=LWIP_DHCP,IP_ADDRESS,NETMASK_ADDRESS,GATEWAY_ADDRESS,LWIP_STATS,LWIP_STATS_DISPLAY,TCPIP_THREAD_STACKSIZE,TCP_DEBUG,SOCKETS_DEBUG,NETIF_DEBUG,ETHARP_DEBUG,LWIP_DBG_TYPES_ON,DEFAULT_ACCEPTMBOX_SIZE,DEFAULT_TCP_RECVMBOX_SIZE +LWIP.IPParameters=LWIP_DHCP,IP_ADDRESS,NETMASK_ADDRESS,GATEWAY_ADDRESS,LWIP_STATS,LWIP_STATS_DISPLAY,TCPIP_THREAD_STACKSIZE,TCP_DEBUG,SOCKETS_DEBUG,NETIF_DEBUG,ETHARP_DEBUG,LWIP_DBG_TYPES_ON,DEFAULT_ACCEPTMBOX_SIZE,DEFAULT_TCP_RECVMBOX_SIZE,LWIP_RAM_HEAP_POINTER LWIP.IP_ADDRESS=192.168.001.098 LWIP.LWIP_DBG_TYPES_ON=LWIP_DBG_OFF LWIP.LWIP_DHCP=0 +LWIP.LWIP_RAM_HEAP_POINTER=0x30008000 LWIP.LWIP_STATS=1 LWIP.LWIP_STATS_DISPLAY=1 LWIP.NETIF_DEBUG=LWIP_DBG_OFF