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解决485_1不进中断问题

master
Lizongdi 1 day ago
parent
0fbb972600
commit
9629be1657
6 changed files with 59 additions and 118 deletions
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  1. 1
      Core/Inc/stm32h7xx_it.h
  2. 3
      Core/Src/dma.c
  3. 15
      Core/Src/stm32h7xx_it.c
  4. 20
      Core/Src/usart.c
  5. 2
      robot
  6. 136
      robot_h743.ioc

1
Core/Inc/stm32h7xx_it.h
View File

@ -72,7 +72,6 @@ void UART4_IRQHandler(void);
void UART5_IRQHandler(void);
void DMA2_Stream0_IRQHandler(void);
void DMA2_Stream1_IRQHandler(void);
void DMA2_Stream2_IRQHandler(void);
void DMA2_Stream3_IRQHandler(void);
void DMA2_Stream4_IRQHandler(void);
void ETH_IRQHandler(void);

3
Core/Src/dma.c
View File

@ -74,9 +74,6 @@ void MX_DMA_Init(void)
/* DMA2_Stream1_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DMA2_Stream1_IRQn, 5, 0);
HAL_NVIC_EnableIRQ(DMA2_Stream1_IRQn);
/* DMA2_Stream2_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DMA2_Stream2_IRQn, 5, 0);
HAL_NVIC_EnableIRQ(DMA2_Stream2_IRQn);
/* DMA2_Stream3_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DMA2_Stream3_IRQn, 5, 0);
HAL_NVIC_EnableIRQ(DMA2_Stream3_IRQn);

15
Core/Src/stm32h7xx_it.c
View File

@ -67,7 +67,6 @@ extern DMA_HandleTypeDef hdma_uart5_rx;
extern DMA_HandleTypeDef hdma_uart7_tx;
extern DMA_HandleTypeDef hdma_uart7_rx;
extern DMA_HandleTypeDef hdma_usart1_tx;
extern DMA_HandleTypeDef hdma_usart1_rx;
extern DMA_HandleTypeDef hdma_usart2_tx;
extern DMA_HandleTypeDef hdma_usart2_rx;
extern DMA_HandleTypeDef hdma_usart3_tx;
@ -473,20 +472,6 @@ void DMA2_Stream1_IRQHandler(void)
/* USER CODE END DMA2_Stream1_IRQn 1 */
}
/**
* @brief This function handles DMA2 stream2 global interrupt.
*/
void DMA2_Stream2_IRQHandler(void)
{
/* USER CODE BEGIN DMA2_Stream2_IRQn 0 */
/* USER CODE END DMA2_Stream2_IRQn 0 */
HAL_DMA_IRQHandler(&hdma_usart1_rx);
/* USER CODE BEGIN DMA2_Stream2_IRQn 1 */
/* USER CODE END DMA2_Stream2_IRQn 1 */
}
/**
* @brief This function handles DMA2 stream3 global interrupt.
*/

20
Core/Src/usart.c
View File

@ -39,7 +39,6 @@ DMA_HandleTypeDef hdma_uart5_rx;
DMA_HandleTypeDef hdma_uart7_tx;
DMA_HandleTypeDef hdma_uart7_rx;
DMA_HandleTypeDef hdma_usart1_tx;
DMA_HandleTypeDef hdma_usart1_rx;
DMA_HandleTypeDef hdma_usart2_tx;
DMA_HandleTypeDef hdma_usart2_rx;
DMA_HandleTypeDef hdma_usart3_tx;
@ -758,24 +757,6 @@ void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle)
__HAL_LINKDMA(uartHandle,hdmatx,hdma_usart1_tx);
/* USART1_RX Init */
hdma_usart1_rx.Instance = DMA2_Stream2;
hdma_usart1_rx.Init.Request = DMA_REQUEST_USART1_RX;
hdma_usart1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
hdma_usart1_rx.Init.PeriphInc = DMA_PINC_DISABLE;
hdma_usart1_rx.Init.MemInc = DMA_MINC_ENABLE;
hdma_usart1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
hdma_usart1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
hdma_usart1_rx.Init.Mode = DMA_CIRCULAR;
hdma_usart1_rx.Init.Priority = DMA_PRIORITY_LOW;
hdma_usart1_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
if (HAL_DMA_Init(&hdma_usart1_rx) != HAL_OK)
{
Error_Handler();
}
__HAL_LINKDMA(uartHandle,hdmarx,hdma_usart1_rx);
/* USART1 interrupt Init */
HAL_NVIC_SetPriority(USART1_IRQn, 5, 0);
HAL_NVIC_EnableIRQ(USART1_IRQn);
@ -1141,7 +1122,6 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle)
/* USART1 DMA DeInit */
HAL_DMA_DeInit(uartHandle->hdmatx);
HAL_DMA_DeInit(uartHandle->hdmarx);
/* USART1 interrupt Deinit */
HAL_NVIC_DisableIRQ(USART1_IRQn);

2
robot

@ -1 +1 @@
Subproject commit b32de2c39bb63c74ce20bf2ed13a51a193426b98
Subproject commit db022dec1c99e06ed2c094cc2e97f3e6acf4ee2b

136
robot_h743.ioc
View File

@ -46,10 +46,9 @@ CORTEX_M7.TypeExtField-Cortex_Memory_Protection_Unit_Region1_Settings=MPU_TEX_LE
CORTEX_M7.TypeExtField-Cortex_Memory_Protection_Unit_Region2_Settings=MPU_TEX_LEVEL1
Dma.Request0=UART4_TX
Dma.Request1=USART1_TX
Dma.Request10=USART1_RX
Dma.Request11=USART2_RX
Dma.Request12=USART3_RX
Dma.Request13=USART6_RX
Dma.Request10=USART2_RX
Dma.Request11=USART3_RX
Dma.Request12=USART6_RX
Dma.Request2=UART5_TX
Dma.Request3=USART2_TX
Dma.Request4=USART3_TX
@ -58,7 +57,7 @@ Dma.Request6=UART7_TX
Dma.Request7=UART4_RX
Dma.Request8=UART5_RX
Dma.Request9=UART7_RX
Dma.RequestsNb=14
Dma.RequestsNb=13
Dma.UART4_RX.7.Direction=DMA_PERIPH_TO_MEMORY
Dma.UART4_RX.7.EventEnable=DISABLE
Dma.UART4_RX.7.FIFOMode=DMA_FIFOMODE_DISABLE
@ -170,24 +169,6 @@ Dma.UART7_TX.6.SyncEnable=DISABLE
Dma.UART7_TX.6.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
Dma.UART7_TX.6.SyncRequestNumber=1
Dma.UART7_TX.6.SyncSignalID=NONE
Dma.USART1_RX.10.Direction=DMA_PERIPH_TO_MEMORY
Dma.USART1_RX.10.EventEnable=DISABLE
Dma.USART1_RX.10.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.USART1_RX.10.Instance=DMA2_Stream2
Dma.USART1_RX.10.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.USART1_RX.10.MemInc=DMA_MINC_ENABLE
Dma.USART1_RX.10.Mode=DMA_CIRCULAR
Dma.USART1_RX.10.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.USART1_RX.10.PeriphInc=DMA_PINC_DISABLE
Dma.USART1_RX.10.Polarity=HAL_DMAMUX_REQ_GEN_RISING
Dma.USART1_RX.10.Priority=DMA_PRIORITY_LOW
Dma.USART1_RX.10.RequestNumber=1
Dma.USART1_RX.10.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
Dma.USART1_RX.10.SignalID=NONE
Dma.USART1_RX.10.SyncEnable=DISABLE
Dma.USART1_RX.10.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
Dma.USART1_RX.10.SyncRequestNumber=1
Dma.USART1_RX.10.SyncSignalID=NONE
Dma.USART1_TX.1.Direction=DMA_MEMORY_TO_PERIPH
Dma.USART1_TX.1.EventEnable=DISABLE
Dma.USART1_TX.1.FIFOMode=DMA_FIFOMODE_ENABLE
@ -209,24 +190,24 @@ Dma.USART1_TX.1.SyncEnable=DISABLE
Dma.USART1_TX.1.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
Dma.USART1_TX.1.SyncRequestNumber=1
Dma.USART1_TX.1.SyncSignalID=NONE
Dma.USART2_RX.11.Direction=DMA_PERIPH_TO_MEMORY
Dma.USART2_RX.11.EventEnable=DISABLE
Dma.USART2_RX.11.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.USART2_RX.11.Instance=DMA2_Stream3
Dma.USART2_RX.11.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.USART2_RX.11.MemInc=DMA_MINC_ENABLE
Dma.USART2_RX.11.Mode=DMA_CIRCULAR
Dma.USART2_RX.11.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.USART2_RX.11.PeriphInc=DMA_PINC_DISABLE
Dma.USART2_RX.11.Polarity=HAL_DMAMUX_REQ_GEN_RISING
Dma.USART2_RX.11.Priority=DMA_PRIORITY_LOW
Dma.USART2_RX.11.RequestNumber=1
Dma.USART2_RX.11.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
Dma.USART2_RX.11.SignalID=NONE
Dma.USART2_RX.11.SyncEnable=DISABLE
Dma.USART2_RX.11.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
Dma.USART2_RX.11.SyncRequestNumber=1
Dma.USART2_RX.11.SyncSignalID=NONE
Dma.USART2_RX.10.Direction=DMA_PERIPH_TO_MEMORY
Dma.USART2_RX.10.EventEnable=DISABLE
Dma.USART2_RX.10.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.USART2_RX.10.Instance=DMA2_Stream3
Dma.USART2_RX.10.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.USART2_RX.10.MemInc=DMA_MINC_ENABLE
Dma.USART2_RX.10.Mode=DMA_CIRCULAR
Dma.USART2_RX.10.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.USART2_RX.10.PeriphInc=DMA_PINC_DISABLE
Dma.USART2_RX.10.Polarity=HAL_DMAMUX_REQ_GEN_RISING
Dma.USART2_RX.10.Priority=DMA_PRIORITY_LOW
Dma.USART2_RX.10.RequestNumber=1
Dma.USART2_RX.10.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
Dma.USART2_RX.10.SignalID=NONE
Dma.USART2_RX.10.SyncEnable=DISABLE
Dma.USART2_RX.10.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
Dma.USART2_RX.10.SyncRequestNumber=1
Dma.USART2_RX.10.SyncSignalID=NONE
Dma.USART2_TX.3.Direction=DMA_MEMORY_TO_PERIPH
Dma.USART2_TX.3.EventEnable=DISABLE
Dma.USART2_TX.3.FIFOMode=DMA_FIFOMODE_DISABLE
@ -245,24 +226,24 @@ Dma.USART2_TX.3.SyncEnable=DISABLE
Dma.USART2_TX.3.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
Dma.USART2_TX.3.SyncRequestNumber=1
Dma.USART2_TX.3.SyncSignalID=NONE
Dma.USART3_RX.12.Direction=DMA_PERIPH_TO_MEMORY
Dma.USART3_RX.12.EventEnable=DISABLE
Dma.USART3_RX.12.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.USART3_RX.12.Instance=DMA2_Stream4
Dma.USART3_RX.12.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.USART3_RX.12.MemInc=DMA_MINC_ENABLE
Dma.USART3_RX.12.Mode=DMA_CIRCULAR
Dma.USART3_RX.12.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.USART3_RX.12.PeriphInc=DMA_PINC_DISABLE
Dma.USART3_RX.12.Polarity=HAL_DMAMUX_REQ_GEN_RISING
Dma.USART3_RX.12.Priority=DMA_PRIORITY_LOW
Dma.USART3_RX.12.RequestNumber=1
Dma.USART3_RX.12.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
Dma.USART3_RX.12.SignalID=NONE
Dma.USART3_RX.12.SyncEnable=DISABLE
Dma.USART3_RX.12.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
Dma.USART3_RX.12.SyncRequestNumber=1
Dma.USART3_RX.12.SyncSignalID=NONE
Dma.USART3_RX.11.Direction=DMA_PERIPH_TO_MEMORY
Dma.USART3_RX.11.EventEnable=DISABLE
Dma.USART3_RX.11.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.USART3_RX.11.Instance=DMA2_Stream4
Dma.USART3_RX.11.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.USART3_RX.11.MemInc=DMA_MINC_ENABLE
Dma.USART3_RX.11.Mode=DMA_CIRCULAR
Dma.USART3_RX.11.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.USART3_RX.11.PeriphInc=DMA_PINC_DISABLE
Dma.USART3_RX.11.Polarity=HAL_DMAMUX_REQ_GEN_RISING
Dma.USART3_RX.11.Priority=DMA_PRIORITY_LOW
Dma.USART3_RX.11.RequestNumber=1
Dma.USART3_RX.11.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
Dma.USART3_RX.11.SignalID=NONE
Dma.USART3_RX.11.SyncEnable=DISABLE
Dma.USART3_RX.11.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
Dma.USART3_RX.11.SyncRequestNumber=1
Dma.USART3_RX.11.SyncSignalID=NONE
Dma.USART3_TX.4.Direction=DMA_MEMORY_TO_PERIPH
Dma.USART3_TX.4.EventEnable=DISABLE
Dma.USART3_TX.4.FIFOMode=DMA_FIFOMODE_DISABLE
@ -281,24 +262,24 @@ Dma.USART3_TX.4.SyncEnable=DISABLE
Dma.USART3_TX.4.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
Dma.USART3_TX.4.SyncRequestNumber=1
Dma.USART3_TX.4.SyncSignalID=NONE
Dma.USART6_RX.13.Direction=DMA_PERIPH_TO_MEMORY
Dma.USART6_RX.13.EventEnable=DISABLE
Dma.USART6_RX.13.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.USART6_RX.13.Instance=DMA2_Stream5
Dma.USART6_RX.13.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.USART6_RX.13.MemInc=DMA_MINC_ENABLE
Dma.USART6_RX.13.Mode=DMA_CIRCULAR
Dma.USART6_RX.13.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.USART6_RX.13.PeriphInc=DMA_PINC_DISABLE
Dma.USART6_RX.13.Polarity=HAL_DMAMUX_REQ_GEN_RISING
Dma.USART6_RX.13.Priority=DMA_PRIORITY_LOW
Dma.USART6_RX.13.RequestNumber=1
Dma.USART6_RX.13.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
Dma.USART6_RX.13.SignalID=NONE
Dma.USART6_RX.13.SyncEnable=DISABLE
Dma.USART6_RX.13.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
Dma.USART6_RX.13.SyncRequestNumber=1
Dma.USART6_RX.13.SyncSignalID=NONE
Dma.USART6_RX.12.Direction=DMA_PERIPH_TO_MEMORY
Dma.USART6_RX.12.EventEnable=DISABLE
Dma.USART6_RX.12.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.USART6_RX.12.Instance=DMA2_Stream5
Dma.USART6_RX.12.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.USART6_RX.12.MemInc=DMA_MINC_ENABLE
Dma.USART6_RX.12.Mode=DMA_CIRCULAR
Dma.USART6_RX.12.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.USART6_RX.12.PeriphInc=DMA_PINC_DISABLE
Dma.USART6_RX.12.Polarity=HAL_DMAMUX_REQ_GEN_RISING
Dma.USART6_RX.12.Priority=DMA_PRIORITY_LOW
Dma.USART6_RX.12.RequestNumber=1
Dma.USART6_RX.12.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
Dma.USART6_RX.12.SignalID=NONE
Dma.USART6_RX.12.SyncEnable=DISABLE
Dma.USART6_RX.12.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
Dma.USART6_RX.12.SyncRequestNumber=1
Dma.USART6_RX.12.SyncSignalID=NONE
Dma.USART6_TX.5.Direction=DMA_MEMORY_TO_PERIPH
Dma.USART6_TX.5.EventEnable=DISABLE
Dma.USART6_TX.5.FIFOMode=DMA_FIFOMODE_DISABLE
@ -517,7 +498,6 @@ NVIC.DMA1_Stream6_IRQn=true\:5\:0\:true\:false\:true\:true\:false\:true\:true
NVIC.DMA1_Stream7_IRQn=true\:5\:0\:true\:false\:true\:true\:false\:true\:true
NVIC.DMA2_Stream0_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
NVIC.DMA2_Stream1_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
NVIC.DMA2_Stream2_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
NVIC.DMA2_Stream3_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
NVIC.DMA2_Stream4_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
NVIC.DMA2_Stream5_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true

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