From b19bfb5c80eb07b8ae554359e4e2eb5098560ce8 Mon Sep 17 00:00:00 2001 From: Lizongdi <1210855344@qq.com> Date: Thu, 18 Jun 2026 16:30:43 +0800 Subject: [PATCH] =?UTF-8?q?=E8=B0=83=E6=95=B4=E4=BC=98=E5=85=88=E7=BA=A7?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- Core/Inc/stm32h7xx_hal_conf.h | 2 +- Core/Src/dma.c | 14 ++++++------ Core/Src/fdcan.c | 4 ++-- Core/Src/tim.c | 4 ++-- Core/Src/usart.c | 16 ++++++------- LWIP/Target/ethernetif.c | 2 +- robot_old.ioc | 42 +++++++++++++++++------------------ 7 files changed, 42 insertions(+), 42 deletions(-) diff --git a/Core/Inc/stm32h7xx_hal_conf.h b/Core/Inc/stm32h7xx_hal_conf.h index 1aa9f8f..5088052 100644 --- a/Core/Inc/stm32h7xx_hal_conf.h +++ b/Core/Inc/stm32h7xx_hal_conf.h @@ -165,7 +165,7 @@ * @brief This is the HAL system configuration section */ #define VDD_VALUE (3300UL) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY (15UL) /*!< tick interrupt priority */ +#define TICK_INT_PRIORITY (0UL) /*!< tick interrupt priority */ #define USE_RTOS 0 #define USE_SD_TRANSCEIVER 0U /*!< use uSD Transceiver */ #define USE_SPI_CRC 0U /*!< use CRC in SPI */ diff --git a/Core/Src/dma.c b/Core/Src/dma.c index b0354ba..61942a5 100644 --- a/Core/Src/dma.c +++ b/Core/Src/dma.c @@ -44,25 +44,25 @@ void MX_DMA_Init(void) /* DMA interrupt init */ /* DMA1_Stream0_IRQn interrupt configuration */ - HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 5, 0); + HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 3, 0); HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn); /* DMA1_Stream1_IRQn interrupt configuration */ - HAL_NVIC_SetPriority(DMA1_Stream1_IRQn, 5, 0); + HAL_NVIC_SetPriority(DMA1_Stream1_IRQn, 3, 0); HAL_NVIC_EnableIRQ(DMA1_Stream1_IRQn); /* DMA1_Stream2_IRQn interrupt configuration */ - HAL_NVIC_SetPriority(DMA1_Stream2_IRQn, 5, 0); + HAL_NVIC_SetPriority(DMA1_Stream2_IRQn, 3, 0); HAL_NVIC_EnableIRQ(DMA1_Stream2_IRQn); /* DMA1_Stream3_IRQn interrupt configuration */ - HAL_NVIC_SetPriority(DMA1_Stream3_IRQn, 5, 0); + HAL_NVIC_SetPriority(DMA1_Stream3_IRQn, 3, 0); HAL_NVIC_EnableIRQ(DMA1_Stream3_IRQn); /* DMA1_Stream5_IRQn interrupt configuration */ - HAL_NVIC_SetPriority(DMA1_Stream5_IRQn, 5, 0); + HAL_NVIC_SetPriority(DMA1_Stream5_IRQn, 3, 0); HAL_NVIC_EnableIRQ(DMA1_Stream5_IRQn); /* DMA1_Stream6_IRQn interrupt configuration */ - HAL_NVIC_SetPriority(DMA1_Stream6_IRQn, 5, 0); + HAL_NVIC_SetPriority(DMA1_Stream6_IRQn, 3, 0); HAL_NVIC_EnableIRQ(DMA1_Stream6_IRQn); /* DMA1_Stream7_IRQn interrupt configuration */ - HAL_NVIC_SetPriority(DMA1_Stream7_IRQn, 5, 0); + HAL_NVIC_SetPriority(DMA1_Stream7_IRQn, 3, 0); HAL_NVIC_EnableIRQ(DMA1_Stream7_IRQn); } diff --git a/Core/Src/fdcan.c b/Core/Src/fdcan.c index 0d5782f..e4259e6 100644 --- a/Core/Src/fdcan.c +++ b/Core/Src/fdcan.c @@ -165,7 +165,7 @@ void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef* fdcanHandle) HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); /* FDCAN1 interrupt Init */ - HAL_NVIC_SetPriority(FDCAN1_IT0_IRQn, 5, 0); + HAL_NVIC_SetPriority(FDCAN1_IT0_IRQn, 2, 0); HAL_NVIC_EnableIRQ(FDCAN1_IT0_IRQn); /* USER CODE BEGIN FDCAN1_MspInit 1 */ @@ -205,7 +205,7 @@ void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef* fdcanHandle) HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); /* FDCAN2 interrupt Init */ - HAL_NVIC_SetPriority(FDCAN2_IT0_IRQn, 5, 0); + HAL_NVIC_SetPriority(FDCAN2_IT0_IRQn, 2, 0); HAL_NVIC_EnableIRQ(FDCAN2_IT0_IRQn); /* USER CODE BEGIN FDCAN2_MspInit 1 */ diff --git a/Core/Src/tim.c b/Core/Src/tim.c index b802d67..f568905 100644 --- a/Core/Src/tim.c +++ b/Core/Src/tim.c @@ -124,7 +124,7 @@ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle) __HAL_RCC_TIM1_CLK_ENABLE(); /* TIM1 interrupt Init */ - HAL_NVIC_SetPriority(TIM1_UP_IRQn, 5, 0); + HAL_NVIC_SetPriority(TIM1_UP_IRQn, 1, 0); HAL_NVIC_EnableIRQ(TIM1_UP_IRQn); /* USER CODE BEGIN TIM1_MspInit 1 */ @@ -139,7 +139,7 @@ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle) __HAL_RCC_TIM8_CLK_ENABLE(); /* TIM8 interrupt Init */ - HAL_NVIC_SetPriority(TIM8_UP_TIM13_IRQn, 5, 0); + HAL_NVIC_SetPriority(TIM8_UP_TIM13_IRQn, 0, 0); HAL_NVIC_EnableIRQ(TIM8_UP_TIM13_IRQn); /* USER CODE BEGIN TIM8_MspInit 1 */ diff --git a/Core/Src/usart.c b/Core/Src/usart.c index 4e2b1ea..14b78ee 100644 --- a/Core/Src/usart.c +++ b/Core/Src/usart.c @@ -439,7 +439,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); /* LPUART1 interrupt Init */ - HAL_NVIC_SetPriority(LPUART1_IRQn, 5, 0); + HAL_NVIC_SetPriority(LPUART1_IRQn, 4, 0); HAL_NVIC_EnableIRQ(LPUART1_IRQn); /* USER CODE BEGIN LPUART1_MspInit 1 */ @@ -505,7 +505,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) __HAL_LINKDMA(uartHandle,hdmatx,hdma_uart4_tx); /* UART4 interrupt Init */ - HAL_NVIC_SetPriority(UART4_IRQn, 5, 0); + HAL_NVIC_SetPriority(UART4_IRQn, 4, 0); HAL_NVIC_EnableIRQ(UART4_IRQn); /* USER CODE BEGIN UART4_MspInit 1 */ @@ -569,7 +569,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) __HAL_LINKDMA(uartHandle,hdmatx,hdma_uart5_tx); /* UART5 interrupt Init */ - HAL_NVIC_SetPriority(UART5_IRQn, 5, 0); + HAL_NVIC_SetPriority(UART5_IRQn, 4, 0); HAL_NVIC_EnableIRQ(UART5_IRQn); /* USER CODE BEGIN UART5_MspInit 1 */ @@ -632,7 +632,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) __HAL_LINKDMA(uartHandle,hdmatx,hdma_uart7_tx); /* UART7 interrupt Init */ - HAL_NVIC_SetPriority(UART7_IRQn, 5, 0); + HAL_NVIC_SetPriority(UART7_IRQn, 4, 0); HAL_NVIC_EnableIRQ(UART7_IRQn); /* USER CODE BEGIN UART7_MspInit 1 */ @@ -698,7 +698,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart1_tx); /* USART1 interrupt Init */ - HAL_NVIC_SetPriority(USART1_IRQn, 5, 0); + HAL_NVIC_SetPriority(USART1_IRQn, 4, 0); HAL_NVIC_EnableIRQ(USART1_IRQn); /* USER CODE BEGIN USART1_MspInit 1 */ @@ -761,7 +761,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart2_tx); /* USART2 interrupt Init */ - HAL_NVIC_SetPriority(USART2_IRQn, 5, 0); + HAL_NVIC_SetPriority(USART2_IRQn, 4, 0); HAL_NVIC_EnableIRQ(USART2_IRQn); /* USER CODE BEGIN USART2_MspInit 1 */ @@ -824,7 +824,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart3_tx); /* USART3 interrupt Init */ - HAL_NVIC_SetPriority(USART3_IRQn, 0, 0); + HAL_NVIC_SetPriority(USART3_IRQn, 4, 0); HAL_NVIC_EnableIRQ(USART3_IRQn); /* USER CODE BEGIN USART3_MspInit 1 */ @@ -887,7 +887,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart6_tx); /* USART6 interrupt Init */ - HAL_NVIC_SetPriority(USART6_IRQn, 5, 0); + HAL_NVIC_SetPriority(USART6_IRQn, 4, 0); HAL_NVIC_EnableIRQ(USART6_IRQn); /* USER CODE BEGIN USART6_MspInit 1 */ diff --git a/LWIP/Target/ethernetif.c b/LWIP/Target/ethernetif.c index a5a4e2e..a8294ea 100644 --- a/LWIP/Target/ethernetif.c +++ b/LWIP/Target/ethernetif.c @@ -523,7 +523,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* ethHandle) HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); /* Peripheral interrupt init */ - HAL_NVIC_SetPriority(ETH_IRQn, 5, 0); + HAL_NVIC_SetPriority(ETH_IRQn, 4, 0); HAL_NVIC_EnableIRQ(ETH_IRQn); HAL_NVIC_SetPriority(ETH_WKUP_IRQn, 5, 0); HAL_NVIC_EnableIRQ(ETH_WKUP_IRQn); diff --git a/robot_old.ioc b/robot_old.ioc index 65cc540..80a92dd 100644 --- a/robot_old.ioc +++ b/robot_old.ioc @@ -355,38 +355,38 @@ Mcu.UserName=STM32H743VGTx MxCube.Version=6.17.0 MxDb.Version=DB.6.0.170 NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false -NVIC.DMA1_Stream0_IRQn=true\:5\:0\:true\:false\:true\:false\:true\:true -NVIC.DMA1_Stream1_IRQn=true\:5\:0\:true\:false\:true\:false\:true\:true -NVIC.DMA1_Stream2_IRQn=true\:5\:0\:true\:false\:true\:false\:true\:true -NVIC.DMA1_Stream3_IRQn=true\:5\:0\:true\:false\:true\:false\:true\:true -NVIC.DMA1_Stream5_IRQn=true\:5\:0\:true\:false\:true\:false\:true\:true -NVIC.DMA1_Stream6_IRQn=true\:5\:0\:true\:false\:true\:false\:true\:true -NVIC.DMA1_Stream7_IRQn=true\:5\:0\:true\:false\:true\:false\:true\:true +NVIC.DMA1_Stream0_IRQn=true\:3\:0\:true\:false\:true\:false\:true\:true +NVIC.DMA1_Stream1_IRQn=true\:3\:0\:true\:false\:true\:false\:true\:true +NVIC.DMA1_Stream2_IRQn=true\:3\:0\:true\:false\:true\:false\:true\:true +NVIC.DMA1_Stream3_IRQn=true\:3\:0\:true\:false\:true\:false\:true\:true +NVIC.DMA1_Stream5_IRQn=true\:3\:0\:true\:false\:true\:false\:true\:true +NVIC.DMA1_Stream6_IRQn=true\:3\:0\:true\:false\:true\:false\:true\:true +NVIC.DMA1_Stream7_IRQn=true\:3\:0\:true\:false\:true\:false\:true\:true NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false -NVIC.ETH_IRQn=true\:5\:0\:true\:false\:true\:true\:true\:true +NVIC.ETH_IRQn=true\:4\:0\:true\:false\:true\:true\:true\:true NVIC.ETH_WKUP_IRQn=true\:5\:0\:true\:false\:true\:true\:true\:true -NVIC.FDCAN1_IT0_IRQn=true\:5\:0\:true\:false\:true\:true\:true\:true -NVIC.FDCAN2_IT0_IRQn=true\:5\:0\:true\:false\:true\:true\:true\:true +NVIC.FDCAN1_IT0_IRQn=true\:2\:0\:true\:false\:true\:true\:true\:true +NVIC.FDCAN2_IT0_IRQn=true\:2\:0\:true\:false\:true\:true\:true\:true NVIC.ForceEnableDMAVector=true NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.I2C4_ER_IRQn=true\:15\:0\:true\:false\:true\:true\:true\:true NVIC.I2C4_EV_IRQn=true\:15\:0\:true\:false\:true\:true\:true\:true -NVIC.LPUART1_IRQn=true\:5\:0\:true\:false\:true\:true\:true\:true +NVIC.LPUART1_IRQn=true\:4\:0\:true\:false\:true\:true\:true\:true NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:false NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false -NVIC.SysTick_IRQn=true\:15\:0\:true\:false\:true\:false\:true\:false -NVIC.TIM1_UP_IRQn=true\:5\:0\:true\:false\:true\:true\:true\:true -NVIC.TIM8_UP_TIM13_IRQn=true\:5\:0\:true\:false\:true\:true\:true\:true -NVIC.UART4_IRQn=true\:5\:0\:true\:false\:true\:true\:true\:true -NVIC.UART5_IRQn=true\:5\:0\:true\:false\:true\:true\:true\:true -NVIC.UART7_IRQn=true\:5\:0\:true\:false\:true\:true\:true\:true -NVIC.USART1_IRQn=true\:5\:0\:true\:false\:true\:true\:true\:true -NVIC.USART2_IRQn=true\:5\:0\:true\:false\:true\:true\:true\:true -NVIC.USART3_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true -NVIC.USART6_IRQn=true\:5\:0\:true\:false\:true\:true\:true\:true +NVIC.SysTick_IRQn=true\:0\:0\:true\:false\:true\:false\:true\:false +NVIC.TIM1_UP_IRQn=true\:1\:0\:true\:false\:true\:true\:true\:true +NVIC.TIM8_UP_TIM13_IRQn=true\:0\:0\:true\:false\:true\:true\:true\:true +NVIC.UART4_IRQn=true\:4\:0\:true\:false\:true\:true\:true\:true +NVIC.UART5_IRQn=true\:4\:0\:true\:false\:true\:true\:true\:true +NVIC.UART7_IRQn=true\:4\:0\:true\:false\:true\:true\:true\:true +NVIC.USART1_IRQn=true\:4\:0\:true\:false\:true\:true\:true\:true +NVIC.USART2_IRQn=true\:4\:0\:true\:false\:true\:true\:true\:true +NVIC.USART3_IRQn=true\:4\:0\:true\:false\:true\:true\:true\:true +NVIC.USART6_IRQn=true\:4\:0\:true\:false\:true\:true\:true\:true NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false PA0.GPIOParameters=GPIO_Label,PinAttribute PA0.GPIO_Label=OUT_2