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diff --git a/Debug/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3.elf b/Debug/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3.elf
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index 0000000..ba58fa9
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diff --git a/Debug/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3.hex b/Debug/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3.hex
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diff --git a/Debug/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3.list b/Debug/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3.list
new file mode 100644
index 0000000..d44993d
--- /dev/null
+++ b/Debug/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3.list
@@ -0,0 +1,78569 @@
+
+BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3.elf:     file format elf32-littlearm
+
+Sections:
+Idx Name          Size      VMA       LMA       File off  Algn
+  0 .isr_vector   00000298  08020000  08020000  00001000  2**0
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+  1 .text         00020be4  080202a0  080202a0  000012a0  2**4
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  2 .rodata       00000fc8  08040e88  08040e88  00021e88  2**3
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+  3 .ARM          00000008  08041e50  08041e50  00022e50  2**2
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+  4 .init_array   00000004  08041e58  08041e58  00022e58  2**2
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+  5 .fini_array   00000004  08041e5c  08041e5c  00022e5c  2**2
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+  6 .data         0000018c  24000000  08041e60  00023000  2**3
+                  CONTENTS, ALLOC, LOAD, DATA
+  7 .RxDecripSection 00000060  2400018c  08041fec  0002318c  2**2
+                  CONTENTS, ALLOC, LOAD, DATA
+  8 .TxDecripSection 00000060  240001ec  0804204c  000231ec  2**2
+                  CONTENTS, ALLOC, LOAD, DATA
+  9 .bss          0000b174  24000250  080420ac  00023250  2**3
+                  ALLOC
+ 10 ._user_heap_stack 00002804  2400b3c4  080420ac  000233c4  2**0
+                  ALLOC
+ 11 .ARM.attributes 0000002e  00000000  00000000  0002324c  2**0
+                  CONTENTS, READONLY
+ 12 .debug_info   0004d691  00000000  00000000  0002327a  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 13 .debug_abbrev 00009af9  00000000  00000000  0007090b  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 14 .debug_aranges 00002ea8  00000000  00000000  0007a408  2**3
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 15 .debug_macro  00049d01  00000000  00000000  0007d2b0  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 16 .debug_line   00054c1e  00000000  00000000  000c6fb1  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 17 .debug_str    0019fddb  00000000  00000000  0011bbcf  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 18 .comment      00000043  00000000  00000000  002bb9aa  2**0
+                  CONTENTS, READONLY
+ 19 .debug_rnglists 000023c1  00000000  00000000  002bb9ed  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 20 .debug_frame  0000c344  00000000  00000000  002bddb0  2**2
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 21 .debug_line_str 0000006c  00000000  00000000  002ca0f4  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+
+Disassembly of section .text:
+
+080202a0 <__do_global_dtors_aux>:
+ 80202a0:	b510      	push	{r4, lr}
+ 80202a2:	4c05      	ldr	r4, [pc, #20]	@ (80202b8 <__do_global_dtors_aux+0x18>)
+ 80202a4:	7823      	ldrb	r3, [r4, #0]
+ 80202a6:	b933      	cbnz	r3, 80202b6 <__do_global_dtors_aux+0x16>
+ 80202a8:	4b04      	ldr	r3, [pc, #16]	@ (80202bc <__do_global_dtors_aux+0x1c>)
+ 80202aa:	b113      	cbz	r3, 80202b2 <__do_global_dtors_aux+0x12>
+ 80202ac:	4804      	ldr	r0, [pc, #16]	@ (80202c0 <__do_global_dtors_aux+0x20>)
+ 80202ae:	f3af 8000 	nop.w
+ 80202b2:	2301      	movs	r3, #1
+ 80202b4:	7023      	strb	r3, [r4, #0]
+ 80202b6:	bd10      	pop	{r4, pc}
+ 80202b8:	24000250 	.word	0x24000250
+ 80202bc:	00000000 	.word	0x00000000
+ 80202c0:	08040e6c 	.word	0x08040e6c
+
+080202c4 <frame_dummy>:
+ 80202c4:	b508      	push	{r3, lr}
+ 80202c6:	4b03      	ldr	r3, [pc, #12]	@ (80202d4 <frame_dummy+0x10>)
+ 80202c8:	b11b      	cbz	r3, 80202d2 <frame_dummy+0xe>
+ 80202ca:	4903      	ldr	r1, [pc, #12]	@ (80202d8 <frame_dummy+0x14>)
+ 80202cc:	4803      	ldr	r0, [pc, #12]	@ (80202dc <frame_dummy+0x18>)
+ 80202ce:	f3af 8000 	nop.w
+ 80202d2:	bd08      	pop	{r3, pc}
+ 80202d4:	00000000 	.word	0x00000000
+ 80202d8:	24000254 	.word	0x24000254
+ 80202dc:	08040e6c 	.word	0x08040e6c
+
+080202e0 <strcmp>:
+ 80202e0:	f810 2b01 	ldrb.w	r2, [r0], #1
+ 80202e4:	f811 3b01 	ldrb.w	r3, [r1], #1
+ 80202e8:	2a01      	cmp	r2, #1
+ 80202ea:	bf28      	it	cs
+ 80202ec:	429a      	cmpcs	r2, r3
+ 80202ee:	d0f7      	beq.n	80202e0 <strcmp>
+ 80202f0:	1ad0      	subs	r0, r2, r3
+ 80202f2:	4770      	bx	lr
+
+080202f4 <strlen>:
+ 80202f4:	4603      	mov	r3, r0
+ 80202f6:	f813 2b01 	ldrb.w	r2, [r3], #1
+ 80202fa:	2a00      	cmp	r2, #0
+ 80202fc:	d1fb      	bne.n	80202f6 <strlen+0x2>
+ 80202fe:	1a18      	subs	r0, r3, r0
+ 8020300:	3801      	subs	r0, #1
+ 8020302:	4770      	bx	lr
+	...
+
+08020310 <memchr>:
+ 8020310:	f001 01ff 	and.w	r1, r1, #255	@ 0xff
+ 8020314:	2a10      	cmp	r2, #16
+ 8020316:	db2b      	blt.n	8020370 <memchr+0x60>
+ 8020318:	f010 0f07 	tst.w	r0, #7
+ 802031c:	d008      	beq.n	8020330 <memchr+0x20>
+ 802031e:	f810 3b01 	ldrb.w	r3, [r0], #1
+ 8020322:	3a01      	subs	r2, #1
+ 8020324:	428b      	cmp	r3, r1
+ 8020326:	d02d      	beq.n	8020384 <memchr+0x74>
+ 8020328:	f010 0f07 	tst.w	r0, #7
+ 802032c:	b342      	cbz	r2, 8020380 <memchr+0x70>
+ 802032e:	d1f6      	bne.n	802031e <memchr+0xe>
+ 8020330:	b4f0      	push	{r4, r5, r6, r7}
+ 8020332:	ea41 2101 	orr.w	r1, r1, r1, lsl #8
+ 8020336:	ea41 4101 	orr.w	r1, r1, r1, lsl #16
+ 802033a:	f022 0407 	bic.w	r4, r2, #7
+ 802033e:	f07f 0700 	mvns.w	r7, #0
+ 8020342:	2300      	movs	r3, #0
+ 8020344:	e8f0 5602 	ldrd	r5, r6, [r0], #8
+ 8020348:	3c08      	subs	r4, #8
+ 802034a:	ea85 0501 	eor.w	r5, r5, r1
+ 802034e:	ea86 0601 	eor.w	r6, r6, r1
+ 8020352:	fa85 f547 	uadd8	r5, r5, r7
+ 8020356:	faa3 f587 	sel	r5, r3, r7
+ 802035a:	fa86 f647 	uadd8	r6, r6, r7
+ 802035e:	faa5 f687 	sel	r6, r5, r7
+ 8020362:	b98e      	cbnz	r6, 8020388 <memchr+0x78>
+ 8020364:	d1ee      	bne.n	8020344 <memchr+0x34>
+ 8020366:	bcf0      	pop	{r4, r5, r6, r7}
+ 8020368:	f001 01ff 	and.w	r1, r1, #255	@ 0xff
+ 802036c:	f002 0207 	and.w	r2, r2, #7
+ 8020370:	b132      	cbz	r2, 8020380 <memchr+0x70>
+ 8020372:	f810 3b01 	ldrb.w	r3, [r0], #1
+ 8020376:	3a01      	subs	r2, #1
+ 8020378:	ea83 0301 	eor.w	r3, r3, r1
+ 802037c:	b113      	cbz	r3, 8020384 <memchr+0x74>
+ 802037e:	d1f8      	bne.n	8020372 <memchr+0x62>
+ 8020380:	2000      	movs	r0, #0
+ 8020382:	4770      	bx	lr
+ 8020384:	3801      	subs	r0, #1
+ 8020386:	4770      	bx	lr
+ 8020388:	2d00      	cmp	r5, #0
+ 802038a:	bf06      	itte	eq
+ 802038c:	4635      	moveq	r5, r6
+ 802038e:	3803      	subeq	r0, #3
+ 8020390:	3807      	subne	r0, #7
+ 8020392:	f015 0f01 	tst.w	r5, #1
+ 8020396:	d107      	bne.n	80203a8 <memchr+0x98>
+ 8020398:	3001      	adds	r0, #1
+ 802039a:	f415 7f80 	tst.w	r5, #256	@ 0x100
+ 802039e:	bf02      	ittt	eq
+ 80203a0:	3001      	addeq	r0, #1
+ 80203a2:	f415 3fc0 	tsteq.w	r5, #98304	@ 0x18000
+ 80203a6:	3001      	addeq	r0, #1
+ 80203a8:	bcf0      	pop	{r4, r5, r6, r7}
+ 80203aa:	3801      	subs	r0, #1
+ 80203ac:	4770      	bx	lr
+ 80203ae:	bf00      	nop
+
+080203b0 <__aeabi_uldivmod>:
+ 80203b0:	b953      	cbnz	r3, 80203c8 <__aeabi_uldivmod+0x18>
+ 80203b2:	b94a      	cbnz	r2, 80203c8 <__aeabi_uldivmod+0x18>
+ 80203b4:	2900      	cmp	r1, #0
+ 80203b6:	bf08      	it	eq
+ 80203b8:	2800      	cmpeq	r0, #0
+ 80203ba:	bf1c      	itt	ne
+ 80203bc:	f04f 31ff 	movne.w	r1, #4294967295
+ 80203c0:	f04f 30ff 	movne.w	r0, #4294967295
+ 80203c4:	f000 b96a 	b.w	802069c <__aeabi_idiv0>
+ 80203c8:	f1ad 0c08 	sub.w	ip, sp, #8
+ 80203cc:	e96d ce04 	strd	ip, lr, [sp, #-16]!
+ 80203d0:	f000 f806 	bl	80203e0 <__udivmoddi4>
+ 80203d4:	f8dd e004 	ldr.w	lr, [sp, #4]
+ 80203d8:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
+ 80203dc:	b004      	add	sp, #16
+ 80203de:	4770      	bx	lr
+
+080203e0 <__udivmoddi4>:
+ 80203e0:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
+ 80203e4:	9d08      	ldr	r5, [sp, #32]
+ 80203e6:	460c      	mov	r4, r1
+ 80203e8:	2b00      	cmp	r3, #0
+ 80203ea:	d14e      	bne.n	802048a <__udivmoddi4+0xaa>
+ 80203ec:	4694      	mov	ip, r2
+ 80203ee:	458c      	cmp	ip, r1
+ 80203f0:	4686      	mov	lr, r0
+ 80203f2:	fab2 f282 	clz	r2, r2
+ 80203f6:	d962      	bls.n	80204be <__udivmoddi4+0xde>
+ 80203f8:	b14a      	cbz	r2, 802040e <__udivmoddi4+0x2e>
+ 80203fa:	f1c2 0320 	rsb	r3, r2, #32
+ 80203fe:	4091      	lsls	r1, r2
+ 8020400:	fa20 f303 	lsr.w	r3, r0, r3
+ 8020404:	fa0c fc02 	lsl.w	ip, ip, r2
+ 8020408:	4319      	orrs	r1, r3
+ 802040a:	fa00 fe02 	lsl.w	lr, r0, r2
+ 802040e:	ea4f 471c 	mov.w	r7, ip, lsr #16
+ 8020412:	fa1f f68c 	uxth.w	r6, ip
+ 8020416:	fbb1 f4f7 	udiv	r4, r1, r7
+ 802041a:	ea4f 431e 	mov.w	r3, lr, lsr #16
+ 802041e:	fb07 1114 	mls	r1, r7, r4, r1
+ 8020422:	ea43 4301 	orr.w	r3, r3, r1, lsl #16
+ 8020426:	fb04 f106 	mul.w	r1, r4, r6
+ 802042a:	4299      	cmp	r1, r3
+ 802042c:	d90a      	bls.n	8020444 <__udivmoddi4+0x64>
+ 802042e:	eb1c 0303 	adds.w	r3, ip, r3
+ 8020432:	f104 30ff 	add.w	r0, r4, #4294967295
+ 8020436:	f080 8112 	bcs.w	802065e <__udivmoddi4+0x27e>
+ 802043a:	4299      	cmp	r1, r3
+ 802043c:	f240 810f 	bls.w	802065e <__udivmoddi4+0x27e>
+ 8020440:	3c02      	subs	r4, #2
+ 8020442:	4463      	add	r3, ip
+ 8020444:	1a59      	subs	r1, r3, r1
+ 8020446:	fa1f f38e 	uxth.w	r3, lr
+ 802044a:	fbb1 f0f7 	udiv	r0, r1, r7
+ 802044e:	fb07 1110 	mls	r1, r7, r0, r1
+ 8020452:	ea43 4301 	orr.w	r3, r3, r1, lsl #16
+ 8020456:	fb00 f606 	mul.w	r6, r0, r6
+ 802045a:	429e      	cmp	r6, r3
+ 802045c:	d90a      	bls.n	8020474 <__udivmoddi4+0x94>
+ 802045e:	eb1c 0303 	adds.w	r3, ip, r3
+ 8020462:	f100 31ff 	add.w	r1, r0, #4294967295
+ 8020466:	f080 80fc 	bcs.w	8020662 <__udivmoddi4+0x282>
+ 802046a:	429e      	cmp	r6, r3
+ 802046c:	f240 80f9 	bls.w	8020662 <__udivmoddi4+0x282>
+ 8020470:	4463      	add	r3, ip
+ 8020472:	3802      	subs	r0, #2
+ 8020474:	1b9b      	subs	r3, r3, r6
+ 8020476:	ea40 4004 	orr.w	r0, r0, r4, lsl #16
+ 802047a:	2100      	movs	r1, #0
+ 802047c:	b11d      	cbz	r5, 8020486 <__udivmoddi4+0xa6>
+ 802047e:	40d3      	lsrs	r3, r2
+ 8020480:	2200      	movs	r2, #0
+ 8020482:	e9c5 3200 	strd	r3, r2, [r5]
+ 8020486:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
+ 802048a:	428b      	cmp	r3, r1
+ 802048c:	d905      	bls.n	802049a <__udivmoddi4+0xba>
+ 802048e:	b10d      	cbz	r5, 8020494 <__udivmoddi4+0xb4>
+ 8020490:	e9c5 0100 	strd	r0, r1, [r5]
+ 8020494:	2100      	movs	r1, #0
+ 8020496:	4608      	mov	r0, r1
+ 8020498:	e7f5      	b.n	8020486 <__udivmoddi4+0xa6>
+ 802049a:	fab3 f183 	clz	r1, r3
+ 802049e:	2900      	cmp	r1, #0
+ 80204a0:	d146      	bne.n	8020530 <__udivmoddi4+0x150>
+ 80204a2:	42a3      	cmp	r3, r4
+ 80204a4:	d302      	bcc.n	80204ac <__udivmoddi4+0xcc>
+ 80204a6:	4290      	cmp	r0, r2
+ 80204a8:	f0c0 80f0 	bcc.w	802068c <__udivmoddi4+0x2ac>
+ 80204ac:	1a86      	subs	r6, r0, r2
+ 80204ae:	eb64 0303 	sbc.w	r3, r4, r3
+ 80204b2:	2001      	movs	r0, #1
+ 80204b4:	2d00      	cmp	r5, #0
+ 80204b6:	d0e6      	beq.n	8020486 <__udivmoddi4+0xa6>
+ 80204b8:	e9c5 6300 	strd	r6, r3, [r5]
+ 80204bc:	e7e3      	b.n	8020486 <__udivmoddi4+0xa6>
+ 80204be:	2a00      	cmp	r2, #0
+ 80204c0:	f040 8090 	bne.w	80205e4 <__udivmoddi4+0x204>
+ 80204c4:	eba1 040c 	sub.w	r4, r1, ip
+ 80204c8:	ea4f 481c 	mov.w	r8, ip, lsr #16
+ 80204cc:	fa1f f78c 	uxth.w	r7, ip
+ 80204d0:	2101      	movs	r1, #1
+ 80204d2:	fbb4 f6f8 	udiv	r6, r4, r8
+ 80204d6:	ea4f 431e 	mov.w	r3, lr, lsr #16
+ 80204da:	fb08 4416 	mls	r4, r8, r6, r4
+ 80204de:	ea43 4304 	orr.w	r3, r3, r4, lsl #16
+ 80204e2:	fb07 f006 	mul.w	r0, r7, r6
+ 80204e6:	4298      	cmp	r0, r3
+ 80204e8:	d908      	bls.n	80204fc <__udivmoddi4+0x11c>
+ 80204ea:	eb1c 0303 	adds.w	r3, ip, r3
+ 80204ee:	f106 34ff 	add.w	r4, r6, #4294967295
+ 80204f2:	d202      	bcs.n	80204fa <__udivmoddi4+0x11a>
+ 80204f4:	4298      	cmp	r0, r3
+ 80204f6:	f200 80cd 	bhi.w	8020694 <__udivmoddi4+0x2b4>
+ 80204fa:	4626      	mov	r6, r4
+ 80204fc:	1a1c      	subs	r4, r3, r0
+ 80204fe:	fa1f f38e 	uxth.w	r3, lr
+ 8020502:	fbb4 f0f8 	udiv	r0, r4, r8
+ 8020506:	fb08 4410 	mls	r4, r8, r0, r4
+ 802050a:	ea43 4304 	orr.w	r3, r3, r4, lsl #16
+ 802050e:	fb00 f707 	mul.w	r7, r0, r7
+ 8020512:	429f      	cmp	r7, r3
+ 8020514:	d908      	bls.n	8020528 <__udivmoddi4+0x148>
+ 8020516:	eb1c 0303 	adds.w	r3, ip, r3
+ 802051a:	f100 34ff 	add.w	r4, r0, #4294967295
+ 802051e:	d202      	bcs.n	8020526 <__udivmoddi4+0x146>
+ 8020520:	429f      	cmp	r7, r3
+ 8020522:	f200 80b0 	bhi.w	8020686 <__udivmoddi4+0x2a6>
+ 8020526:	4620      	mov	r0, r4
+ 8020528:	1bdb      	subs	r3, r3, r7
+ 802052a:	ea40 4006 	orr.w	r0, r0, r6, lsl #16
+ 802052e:	e7a5      	b.n	802047c <__udivmoddi4+0x9c>
+ 8020530:	f1c1 0620 	rsb	r6, r1, #32
+ 8020534:	408b      	lsls	r3, r1
+ 8020536:	fa22 f706 	lsr.w	r7, r2, r6
+ 802053a:	431f      	orrs	r7, r3
+ 802053c:	fa20 fc06 	lsr.w	ip, r0, r6
+ 8020540:	fa04 f301 	lsl.w	r3, r4, r1
+ 8020544:	ea43 030c 	orr.w	r3, r3, ip
+ 8020548:	40f4      	lsrs	r4, r6
+ 802054a:	fa00 f801 	lsl.w	r8, r0, r1
+ 802054e:	0c38      	lsrs	r0, r7, #16
+ 8020550:	ea4f 4913 	mov.w	r9, r3, lsr #16
+ 8020554:	fbb4 fef0 	udiv	lr, r4, r0
+ 8020558:	fa1f fc87 	uxth.w	ip, r7
+ 802055c:	fb00 441e 	mls	r4, r0, lr, r4
+ 8020560:	ea49 4404 	orr.w	r4, r9, r4, lsl #16
+ 8020564:	fb0e f90c 	mul.w	r9, lr, ip
+ 8020568:	45a1      	cmp	r9, r4
+ 802056a:	fa02 f201 	lsl.w	r2, r2, r1
+ 802056e:	d90a      	bls.n	8020586 <__udivmoddi4+0x1a6>
+ 8020570:	193c      	adds	r4, r7, r4
+ 8020572:	f10e 3aff 	add.w	sl, lr, #4294967295
+ 8020576:	f080 8084 	bcs.w	8020682 <__udivmoddi4+0x2a2>
+ 802057a:	45a1      	cmp	r9, r4
+ 802057c:	f240 8081 	bls.w	8020682 <__udivmoddi4+0x2a2>
+ 8020580:	f1ae 0e02 	sub.w	lr, lr, #2
+ 8020584:	443c      	add	r4, r7
+ 8020586:	eba4 0409 	sub.w	r4, r4, r9
+ 802058a:	fa1f f983 	uxth.w	r9, r3
+ 802058e:	fbb4 f3f0 	udiv	r3, r4, r0
+ 8020592:	fb00 4413 	mls	r4, r0, r3, r4
+ 8020596:	ea49 4404 	orr.w	r4, r9, r4, lsl #16
+ 802059a:	fb03 fc0c 	mul.w	ip, r3, ip
+ 802059e:	45a4      	cmp	ip, r4
+ 80205a0:	d907      	bls.n	80205b2 <__udivmoddi4+0x1d2>
+ 80205a2:	193c      	adds	r4, r7, r4
+ 80205a4:	f103 30ff 	add.w	r0, r3, #4294967295
+ 80205a8:	d267      	bcs.n	802067a <__udivmoddi4+0x29a>
+ 80205aa:	45a4      	cmp	ip, r4
+ 80205ac:	d965      	bls.n	802067a <__udivmoddi4+0x29a>
+ 80205ae:	3b02      	subs	r3, #2
+ 80205b0:	443c      	add	r4, r7
+ 80205b2:	ea43 400e 	orr.w	r0, r3, lr, lsl #16
+ 80205b6:	fba0 9302 	umull	r9, r3, r0, r2
+ 80205ba:	eba4 040c 	sub.w	r4, r4, ip
+ 80205be:	429c      	cmp	r4, r3
+ 80205c0:	46ce      	mov	lr, r9
+ 80205c2:	469c      	mov	ip, r3
+ 80205c4:	d351      	bcc.n	802066a <__udivmoddi4+0x28a>
+ 80205c6:	d04e      	beq.n	8020666 <__udivmoddi4+0x286>
+ 80205c8:	b155      	cbz	r5, 80205e0 <__udivmoddi4+0x200>
+ 80205ca:	ebb8 030e 	subs.w	r3, r8, lr
+ 80205ce:	eb64 040c 	sbc.w	r4, r4, ip
+ 80205d2:	fa04 f606 	lsl.w	r6, r4, r6
+ 80205d6:	40cb      	lsrs	r3, r1
+ 80205d8:	431e      	orrs	r6, r3
+ 80205da:	40cc      	lsrs	r4, r1
+ 80205dc:	e9c5 6400 	strd	r6, r4, [r5]
+ 80205e0:	2100      	movs	r1, #0
+ 80205e2:	e750      	b.n	8020486 <__udivmoddi4+0xa6>
+ 80205e4:	f1c2 0320 	rsb	r3, r2, #32
+ 80205e8:	fa20 f103 	lsr.w	r1, r0, r3
+ 80205ec:	fa0c fc02 	lsl.w	ip, ip, r2
+ 80205f0:	fa24 f303 	lsr.w	r3, r4, r3
+ 80205f4:	4094      	lsls	r4, r2
+ 80205f6:	430c      	orrs	r4, r1
+ 80205f8:	ea4f 481c 	mov.w	r8, ip, lsr #16
+ 80205fc:	fa00 fe02 	lsl.w	lr, r0, r2
+ 8020600:	fa1f f78c 	uxth.w	r7, ip
+ 8020604:	fbb3 f0f8 	udiv	r0, r3, r8
+ 8020608:	fb08 3110 	mls	r1, r8, r0, r3
+ 802060c:	0c23      	lsrs	r3, r4, #16
+ 802060e:	ea43 4301 	orr.w	r3, r3, r1, lsl #16
+ 8020612:	fb00 f107 	mul.w	r1, r0, r7
+ 8020616:	4299      	cmp	r1, r3
+ 8020618:	d908      	bls.n	802062c <__udivmoddi4+0x24c>
+ 802061a:	eb1c 0303 	adds.w	r3, ip, r3
+ 802061e:	f100 36ff 	add.w	r6, r0, #4294967295
+ 8020622:	d22c      	bcs.n	802067e <__udivmoddi4+0x29e>
+ 8020624:	4299      	cmp	r1, r3
+ 8020626:	d92a      	bls.n	802067e <__udivmoddi4+0x29e>
+ 8020628:	3802      	subs	r0, #2
+ 802062a:	4463      	add	r3, ip
+ 802062c:	1a5b      	subs	r3, r3, r1
+ 802062e:	b2a4      	uxth	r4, r4
+ 8020630:	fbb3 f1f8 	udiv	r1, r3, r8
+ 8020634:	fb08 3311 	mls	r3, r8, r1, r3
+ 8020638:	ea44 4403 	orr.w	r4, r4, r3, lsl #16
+ 802063c:	fb01 f307 	mul.w	r3, r1, r7
+ 8020640:	42a3      	cmp	r3, r4
+ 8020642:	d908      	bls.n	8020656 <__udivmoddi4+0x276>
+ 8020644:	eb1c 0404 	adds.w	r4, ip, r4
+ 8020648:	f101 36ff 	add.w	r6, r1, #4294967295
+ 802064c:	d213      	bcs.n	8020676 <__udivmoddi4+0x296>
+ 802064e:	42a3      	cmp	r3, r4
+ 8020650:	d911      	bls.n	8020676 <__udivmoddi4+0x296>
+ 8020652:	3902      	subs	r1, #2
+ 8020654:	4464      	add	r4, ip
+ 8020656:	1ae4      	subs	r4, r4, r3
+ 8020658:	ea41 4100 	orr.w	r1, r1, r0, lsl #16
+ 802065c:	e739      	b.n	80204d2 <__udivmoddi4+0xf2>
+ 802065e:	4604      	mov	r4, r0
+ 8020660:	e6f0      	b.n	8020444 <__udivmoddi4+0x64>
+ 8020662:	4608      	mov	r0, r1
+ 8020664:	e706      	b.n	8020474 <__udivmoddi4+0x94>
+ 8020666:	45c8      	cmp	r8, r9
+ 8020668:	d2ae      	bcs.n	80205c8 <__udivmoddi4+0x1e8>
+ 802066a:	ebb9 0e02 	subs.w	lr, r9, r2
+ 802066e:	eb63 0c07 	sbc.w	ip, r3, r7
+ 8020672:	3801      	subs	r0, #1
+ 8020674:	e7a8      	b.n	80205c8 <__udivmoddi4+0x1e8>
+ 8020676:	4631      	mov	r1, r6
+ 8020678:	e7ed      	b.n	8020656 <__udivmoddi4+0x276>
+ 802067a:	4603      	mov	r3, r0
+ 802067c:	e799      	b.n	80205b2 <__udivmoddi4+0x1d2>
+ 802067e:	4630      	mov	r0, r6
+ 8020680:	e7d4      	b.n	802062c <__udivmoddi4+0x24c>
+ 8020682:	46d6      	mov	lr, sl
+ 8020684:	e77f      	b.n	8020586 <__udivmoddi4+0x1a6>
+ 8020686:	4463      	add	r3, ip
+ 8020688:	3802      	subs	r0, #2
+ 802068a:	e74d      	b.n	8020528 <__udivmoddi4+0x148>
+ 802068c:	4606      	mov	r6, r0
+ 802068e:	4623      	mov	r3, r4
+ 8020690:	4608      	mov	r0, r1
+ 8020692:	e70f      	b.n	80204b4 <__udivmoddi4+0xd4>
+ 8020694:	3e02      	subs	r6, #2
+ 8020696:	4463      	add	r3, ip
+ 8020698:	e730      	b.n	80204fc <__udivmoddi4+0x11c>
+ 802069a:	bf00      	nop
+
+0802069c <__aeabi_idiv0>:
+ 802069c:	4770      	bx	lr
+ 802069e:	bf00      	nop
+
+080206a0 <SET_BIT_1>:
+IV_struct_define IV ={ 0 };
+
+
+
+void SET_BIT_1(int32_t* num,int32_t k)
+{
+ 80206a0:	b480      	push	{r7}
+ 80206a2:	b083      	sub	sp, #12
+ 80206a4:	af00      	add	r7, sp, #0
+ 80206a6:	6078      	str	r0, [r7, #4]
+ 80206a8:	6039      	str	r1, [r7, #0]
+	*num=((*num) | (1 << (k)));
+ 80206aa:	687b      	ldr	r3, [r7, #4]
+ 80206ac:	681a      	ldr	r2, [r3, #0]
+ 80206ae:	2101      	movs	r1, #1
+ 80206b0:	683b      	ldr	r3, [r7, #0]
+ 80206b2:	fa01 f303 	lsl.w	r3, r1, r3
+ 80206b6:	431a      	orrs	r2, r3
+ 80206b8:	687b      	ldr	r3, [r7, #4]
+ 80206ba:	601a      	str	r2, [r3, #0]
+}
+ 80206bc:	bf00      	nop
+ 80206be:	370c      	adds	r7, #12
+ 80206c0:	46bd      	mov	sp, r7
+ 80206c2:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80206c6:	4770      	bx	lr
+
+080206c8 <SET_BIT_0>:
+void SET_BIT_0(int32_t* num,int32_t k)
+{
+ 80206c8:	b480      	push	{r7}
+ 80206ca:	b083      	sub	sp, #12
+ 80206cc:	af00      	add	r7, sp, #0
+ 80206ce:	6078      	str	r0, [r7, #4]
+ 80206d0:	6039      	str	r1, [r7, #0]
+	*num=((*num) & ~(1 << (k)));
+ 80206d2:	687b      	ldr	r3, [r7, #4]
+ 80206d4:	681a      	ldr	r2, [r3, #0]
+ 80206d6:	2101      	movs	r1, #1
+ 80206d8:	683b      	ldr	r3, [r7, #0]
+ 80206da:	fa01 f303 	lsl.w	r3, r1, r3
+ 80206de:	43db      	mvns	r3, r3
+ 80206e0:	401a      	ands	r2, r3
+ 80206e2:	687b      	ldr	r3, [r7, #4]
+ 80206e4:	601a      	str	r2, [r3, #0]
+}
+ 80206e6:	bf00      	nop
+ 80206e8:	370c      	adds	r7, #12
+ 80206ea:	46bd      	mov	sp, r7
+ 80206ec:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80206f0:	4770      	bx	lr
+
+080206f2 <Get_BIT>:
+int32_t Get_BIT(int32_t* num,int32_t k)
+{
+ 80206f2:	b480      	push	{r7}
+ 80206f4:	b083      	sub	sp, #12
+ 80206f6:	af00      	add	r7, sp, #0
+ 80206f8:	6078      	str	r0, [r7, #4]
+ 80206fa:	6039      	str	r1, [r7, #0]
+   return (*num >> (k)) & 1;
+ 80206fc:	687b      	ldr	r3, [r7, #4]
+ 80206fe:	681a      	ldr	r2, [r3, #0]
+ 8020700:	683b      	ldr	r3, [r7, #0]
+ 8020702:	fa42 f303 	asr.w	r3, r2, r3
+ 8020706:	f003 0301 	and.w	r3, r3, #1
+}
+ 802070a:	4618      	mov	r0, r3
+ 802070c:	370c      	adds	r7, #12
+ 802070e:	46bd      	mov	sp, r7
+ 8020710:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8020714:	4770      	bx	lr
+	...
+
+08020718 <SystemTimer_Intialize>:
+
+
+
+void SystemTimer_Intialize()
+{
+ 8020718:	b580      	push	{r7, lr}
+ 802071a:	af00      	add	r7, sp, #0
+	SystemTimeMiliCount=0;
+ 802071c:	4b04      	ldr	r3, [pc, #16]	@ (8020730 <SystemTimer_Intialize+0x18>)
+ 802071e:	2200      	movs	r2, #0
+ 8020720:	601a      	str	r2, [r3, #0]
+	GF_BSP_Interrupt_Add_CallBack(
+ 8020722:	4904      	ldr	r1, [pc, #16]	@ (8020734 <SystemTimer_Intialize+0x1c>)
+ 8020724:	200a      	movs	r0, #10
+ 8020726:	f000 fde3 	bl	80212f0 <GF_BSP_Interrupt_Add_CallBack>
+			DF_BSP_InterCall_TIM8_2ms_PeriodElapsedCallback, GF_Timer_Count);
+}
+ 802072a:	bf00      	nop
+ 802072c:	bd80      	pop	{r7, pc}
+ 802072e:	bf00      	nop
+ 8020730:	24000288 	.word	0x24000288
+ 8020734:	08020739 	.word	0x08020739
+
+08020738 <GF_Timer_Count>:
+
+void GF_Timer_Count()
+{
+ 8020738:	b480      	push	{r7}
+ 802073a:	af00      	add	r7, sp, #0
+	SystemTimeMiliCount++;
+ 802073c:	4b04      	ldr	r3, [pc, #16]	@ (8020750 <GF_Timer_Count+0x18>)
+ 802073e:	681b      	ldr	r3, [r3, #0]
+ 8020740:	3301      	adds	r3, #1
+ 8020742:	4a03      	ldr	r2, [pc, #12]	@ (8020750 <GF_Timer_Count+0x18>)
+ 8020744:	6013      	str	r3, [r2, #0]
+}
+ 8020746:	bf00      	nop
+ 8020748:	46bd      	mov	sp, r7
+ 802074a:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 802074e:	4770      	bx	lr
+ 8020750:	24000288 	.word	0x24000288
+
+08020754 <dLT_Log_intialize>:
+struct UARTHandler *dLT_Log_UART_Handler;
+
+
+
+void dLT_Log_intialize(struct UARTHandler *Handler)
+{
+ 8020754:	b580      	push	{r7, lr}
+ 8020756:	b082      	sub	sp, #8
+ 8020758:	af00      	add	r7, sp, #0
+ 802075a:	6078      	str	r0, [r7, #4]
+
+	dLT_Log_UART_Handler = Handler;
+ 802075c:	4a11      	ldr	r2, [pc, #68]	@ (80207a4 <dLT_Log_intialize+0x50>)
+ 802075e:	687b      	ldr	r3, [r7, #4]
+ 8020760:	6013      	str	r3, [r2, #0]
+	dLT_Log_UART_Handler->Wait_time=40;
+ 8020762:	4b10      	ldr	r3, [pc, #64]	@ (80207a4 <dLT_Log_intialize+0x50>)
+ 8020764:	681b      	ldr	r3, [r3, #0]
+ 8020766:	2228      	movs	r2, #40	@ 0x28
+ 8020768:	609a      	str	r2, [r3, #8]
+	Handler->dispacherController->Dispacher_Enable=1;
+ 802076a:	687b      	ldr	r3, [r7, #4]
+ 802076c:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8020770:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 8020772:	2201      	movs	r2, #1
+ 8020774:	81da      	strh	r2, [r3, #14]
+	//log_info("angle_encoder_intialize");
+	dLT_Log_UART_Handler->UART_Decode = DLT_DataReceiveEndCallback;
+ 8020776:	4b0b      	ldr	r3, [pc, #44]	@ (80207a4 <dLT_Log_intialize+0x50>)
+ 8020778:	681b      	ldr	r3, [r3, #0]
+ 802077a:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 802077e:	461a      	mov	r2, r3
+ 8020780:	4b09      	ldr	r3, [pc, #36]	@ (80207a8 <dLT_Log_intialize+0x54>)
+ 8020782:	6313      	str	r3, [r2, #48]	@ 0x30
+	/*Register Low Level Transmit/Receive functions for DLTuc Library*/
+	DLTuc_RegisterTransmitSerialDataFunction(DLT_DataTransmit);
+ 8020784:	4809      	ldr	r0, [pc, #36]	@ (80207ac <dLT_Log_intialize+0x58>)
+ 8020786:	f005 fcc9 	bl	802611c <DLTuc_RegisterTransmitSerialDataFunction>
+	DLTuc_RegisterReceiveSerialDataFunction(DLT_LowLevelReceiveDmaToIdle);
+ 802078a:	4809      	ldr	r0, [pc, #36]	@ (80207b0 <dLT_Log_intialize+0x5c>)
+ 802078c:	f005 fcae 	bl	80260ec <DLTuc_RegisterReceiveSerialDataFunction>
+
+	DLTuc_RegisterGetTimeStampMsCallback(GetSysTime); /*Register GetSysTime function*/
+ 8020790:	4808      	ldr	r0, [pc, #32]	@ (80207b4 <dLT_Log_intialize+0x60>)
+ 8020792:	f005 fdeb 	bl	802636c <DLTuc_RegisterGetTimeStampMsCallback>
+	/*The function "GetSysTime" must return the time in ms*/
+
+	DLTuc_RegisterInjectionDataReceivedCb(DltInjectDataRcvd);
+ 8020796:	4808      	ldr	r0, [pc, #32]	@ (80207b8 <dLT_Log_intialize+0x64>)
+ 8020798:	f005 fc98 	bl	80260cc <DLTuc_RegisterInjectionDataReceivedCb>
+}
+ 802079c:	bf00      	nop
+ 802079e:	3708      	adds	r7, #8
+ 80207a0:	46bd      	mov	sp, r7
+ 80207a2:	bd80      	pop	{r7, pc}
+ 80207a4:	24000614 	.word	0x24000614
+ 80207a8:	080207f5 	.word	0x080207f5
+ 80207ac:	080207bd 	.word	0x080207bd
+ 80207b0:	08020811 	.word	0x08020811
+ 80207b4:	0802089d 	.word	0x0802089d
+ 80207b8:	08020839 	.word	0x08020839
+
+080207bc <DLT_DataTransmit>:
+
+/*This CallBack was registered in main function using function: DLTuc_RegisterTransmitSerialDataFunction*/
+void DLT_DataTransmit(uint8_t *DltLogData, uint8_t Size)
+{
+ 80207bc:	b590      	push	{r4, r7, lr}
+ 80207be:	b085      	sub	sp, #20
+ 80207c0:	af02      	add	r7, sp, #8
+ 80207c2:	6078      	str	r0, [r7, #4]
+ 80207c4:	460b      	mov	r3, r1
+ 80207c6:	70fb      	strb	r3, [r7, #3]
+
+	dLT_Log_UART_Handler->AddSendList(dLT_Log_UART_Handler,DltLogData,Size,100,NULL);
+ 80207c8:	4b09      	ldr	r3, [pc, #36]	@ (80207f0 <DLT_DataTransmit+0x34>)
+ 80207ca:	681b      	ldr	r3, [r3, #0]
+ 80207cc:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 80207d0:	6b9c      	ldr	r4, [r3, #56]	@ 0x38
+ 80207d2:	4b07      	ldr	r3, [pc, #28]	@ (80207f0 <DLT_DataTransmit+0x34>)
+ 80207d4:	6818      	ldr	r0, [r3, #0]
+ 80207d6:	78fb      	ldrb	r3, [r7, #3]
+ 80207d8:	b29a      	uxth	r2, r3
+ 80207da:	2300      	movs	r3, #0
+ 80207dc:	9300      	str	r3, [sp, #0]
+ 80207de:	2364      	movs	r3, #100	@ 0x64
+ 80207e0:	6879      	ldr	r1, [r7, #4]
+ 80207e2:	47a0      	blx	r4
+
+	DLTuc_MessageTransmitDone();
+ 80207e4:	f005 fccc 	bl	8026180 <DLTuc_MessageTransmitDone>
+
+}
+ 80207e8:	bf00      	nop
+ 80207ea:	370c      	adds	r7, #12
+ 80207ec:	46bd      	mov	sp, r7
+ 80207ee:	bd90      	pop	{r4, r7, pc}
+ 80207f0:	24000614 	.word	0x24000614
+
+080207f4 <DLT_DataReceiveEndCallback>:
+/*CallBacks used by ucDltLibrary section end..*/
+
+void DLT_DataReceiveEndCallback(uint8_t *rxBuf, uint16_t Size)
+{
+ 80207f4:	b580      	push	{r7, lr}
+ 80207f6:	b082      	sub	sp, #8
+ 80207f8:	af00      	add	r7, sp, #0
+ 80207fa:	6078      	str	r0, [r7, #4]
+ 80207fc:	460b      	mov	r3, r1
+ 80207fe:	807b      	strh	r3, [r7, #2]
+//		else
+//		{
+//			DLT_LOG_ENABLE_LEVEL=0;
+//		}
+	}
+	DLTuc_RawDataReceiveDone(Size);
+ 8020800:	887b      	ldrh	r3, [r7, #2]
+ 8020802:	4618      	mov	r0, r3
+ 8020804:	f005 fb0a 	bl	8025e1c <DLTuc_RawDataReceiveDone>
+	/*
+	 *In case of STM32 HAL lib, you have to subsitute this function using:
+	 *void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size)
+	 */
+}
+ 8020808:	bf00      	nop
+ 802080a:	3708      	adds	r7, #8
+ 802080c:	46bd      	mov	sp, r7
+ 802080e:	bd80      	pop	{r7, pc}
+
+08020810 <DLT_LowLevelReceiveDmaToIdle>:
+//HAL_UARTEx_RxEventCallback
+void DLT_LowLevelReceiveDmaToIdle(uint8_t *rxBuf, uint16_t Size)
+{
+ 8020810:	b580      	push	{r7, lr}
+ 8020812:	b082      	sub	sp, #8
+ 8020814:	af00      	add	r7, sp, #0
+ 8020816:	6078      	str	r0, [r7, #4]
+ 8020818:	460b      	mov	r3, r1
+ 802081a:	807b      	strh	r3, [r7, #2]
+
+	memcpy(rxBuf, dLT_Log_UART_Handler->Rx_Buf, Size);
+ 802081c:	4b05      	ldr	r3, [pc, #20]	@ (8020834 <DLT_LowLevelReceiveDmaToIdle+0x24>)
+ 802081e:	681b      	ldr	r3, [r3, #0]
+ 8020820:	3321      	adds	r3, #33	@ 0x21
+ 8020822:	887a      	ldrh	r2, [r7, #2]
+ 8020824:	4619      	mov	r1, r3
+ 8020826:	6878      	ldr	r0, [r7, #4]
+ 8020828:	f01f fdc8 	bl	80403bc <memcpy>
+
+}
+ 802082c:	bf00      	nop
+ 802082e:	3708      	adds	r7, #8
+ 8020830:	46bd      	mov	sp, r7
+ 8020832:	bd80      	pop	{r7, pc}
+ 8020834:	24000614 	.word	0x24000614
+
+08020838 <DltInjectDataRcvd>:
+
+void DltInjectDataRcvd(uint32_t AppId, uint32_t ConId, uint32_t ServId,
+		uint8_t *Data, uint16_t Size)
+{
+ 8020838:	b580      	push	{r7, lr}
+ 802083a:	b088      	sub	sp, #32
+ 802083c:	af04      	add	r7, sp, #16
+ 802083e:	60f8      	str	r0, [r7, #12]
+ 8020840:	60b9      	str	r1, [r7, #8]
+ 8020842:	607a      	str	r2, [r7, #4]
+ 8020844:	603b      	str	r3, [r7, #0]
+	LOG("RecInjectionData: %s, ServId: %d Size: %d", Data, ServId, Size)
+ 8020846:	4b13      	ldr	r3, [pc, #76]	@ (8020894 <DltInjectDataRcvd+0x5c>)
+ 8020848:	781b      	ldrb	r3, [r3, #0]
+ 802084a:	2b03      	cmp	r3, #3
+ 802084c:	d91e      	bls.n	802088c <DltInjectDataRcvd+0x54>
+ 802084e:	234e      	movs	r3, #78	@ 0x4e
+ 8020850:	061a      	lsls	r2, r3, #24
+ 8020852:	2355      	movs	r3, #85	@ 0x55
+ 8020854:	041b      	lsls	r3, r3, #16
+ 8020856:	431a      	orrs	r2, r3
+ 8020858:	234d      	movs	r3, #77	@ 0x4d
+ 802085a:	021b      	lsls	r3, r3, #8
+ 802085c:	4313      	orrs	r3, r2
+ 802085e:	2231      	movs	r2, #49	@ 0x31
+ 8020860:	ea43 0102 	orr.w	r1, r3, r2
+ 8020864:	234d      	movs	r3, #77	@ 0x4d
+ 8020866:	061a      	lsls	r2, r3, #24
+ 8020868:	2341      	movs	r3, #65	@ 0x41
+ 802086a:	041b      	lsls	r3, r3, #16
+ 802086c:	431a      	orrs	r2, r3
+ 802086e:	2349      	movs	r3, #73	@ 0x49
+ 8020870:	021b      	lsls	r3, r3, #8
+ 8020872:	4313      	orrs	r3, r2
+ 8020874:	224e      	movs	r2, #78	@ 0x4e
+ 8020876:	431a      	orrs	r2, r3
+ 8020878:	8b3b      	ldrh	r3, [r7, #24]
+ 802087a:	9302      	str	r3, [sp, #8]
+ 802087c:	687b      	ldr	r3, [r7, #4]
+ 802087e:	9301      	str	r3, [sp, #4]
+ 8020880:	683b      	ldr	r3, [r7, #0]
+ 8020882:	9300      	str	r3, [sp, #0]
+ 8020884:	4b04      	ldr	r3, [pc, #16]	@ (8020898 <DltInjectDataRcvd+0x60>)
+ 8020886:	2004      	movs	r0, #4
+ 8020888:	f005 fcd4 	bl	8026234 <DLTuc_LogOutVarArgs>
+
+}
+ 802088c:	bf00      	nop
+ 802088e:	3710      	adds	r7, #16
+ 8020890:	46bd      	mov	sp, r7
+ 8020892:	bd80      	pop	{r7, pc}
+ 8020894:	24009110 	.word	0x24009110
+ 8020898:	08040e88 	.word	0x08040e88
+
+0802089c <GetSysTime>:
+
+
+uint32_t GetSysTime(void)
+{
+ 802089c:	b580      	push	{r7, lr}
+ 802089e:	af00      	add	r7, sp, #0
+	return HAL_GetTick();
+ 80208a0:	f011 f846 	bl	8031930 <HAL_GetTick>
+ 80208a4:	4603      	mov	r3, r0
+}
+ 80208a6:	4618      	mov	r0, r3
+ 80208a8:	bd80      	pop	{r7, pc}
+
+080208aa <GF_BSP_EEPROM_Init>:
+#define I2C_SCL_READ()  ((I2C_SCL_GPIO->IDR & I2C_SCL_PIN) != 0)	/* 读SCL口线状态 */
+
+
+
+uint8_t GF_BSP_EEPROM_Init(void)
+{
+ 80208aa:	b580      	push	{r7, lr}
+ 80208ac:	af00      	add	r7, sp, #0
+	bsp_InitI2C();
+ 80208ae:	f000 f805 	bl	80208bc <bsp_InitI2C>
+	return(GF_BSP_EEPROM_CheckOK());
+ 80208b2:	f000 f94f 	bl	8020b54 <GF_BSP_EEPROM_CheckOK>
+ 80208b6:	4603      	mov	r3, r0
+}
+ 80208b8:	4618      	mov	r0, r3
+ 80208ba:	bd80      	pop	{r7, pc}
+
+080208bc <bsp_InitI2C>:
+*	形    参:  无
+*	返 回 值: 无
+*********************************************************************************************************
+*/
+void bsp_InitI2C(void)
+{
+ 80208bc:	b580      	push	{r7, lr}
+ 80208be:	b086      	sub	sp, #24
+ 80208c0:	af00      	add	r7, sp, #0
+	GPIO_InitTypeDef gpio_init;
+
+	
+	gpio_init.Mode = GPIO_MODE_OUTPUT_OD;	/* 设置开漏输出 */
+ 80208c2:	2311      	movs	r3, #17
+ 80208c4:	60bb      	str	r3, [r7, #8]
+	gpio_init.Pull = GPIO_NOPULL;			/* 上下拉电阻不使能 */
+ 80208c6:	2300      	movs	r3, #0
+ 80208c8:	60fb      	str	r3, [r7, #12]
+	gpio_init.Speed = GPIO_SPEED_FREQ_LOW;	// GPIO_SPEED_FREQ_HIGH;  /* GPIO速度等级 */
+ 80208ca:	2300      	movs	r3, #0
+ 80208cc:	613b      	str	r3, [r7, #16]
+	
+	gpio_init.Pin = I2C_SCL_PIN;	
+ 80208ce:	f44f 5380 	mov.w	r3, #4096	@ 0x1000
+ 80208d2:	607b      	str	r3, [r7, #4]
+	HAL_GPIO_Init(I2C_SCL_GPIO, &gpio_init);	
+ 80208d4:	1d3b      	adds	r3, r7, #4
+ 80208d6:	4619      	mov	r1, r3
+ 80208d8:	4808      	ldr	r0, [pc, #32]	@ (80208fc <bsp_InitI2C+0x40>)
+ 80208da:	f016 fe7f 	bl	80375dc <HAL_GPIO_Init>
+	
+	gpio_init.Pin = I2C_SDA_PIN;	
+ 80208de:	f44f 5300 	mov.w	r3, #8192	@ 0x2000
+ 80208e2:	607b      	str	r3, [r7, #4]
+	HAL_GPIO_Init(I2C_SDA_GPIO, &gpio_init);	
+ 80208e4:	1d3b      	adds	r3, r7, #4
+ 80208e6:	4619      	mov	r1, r3
+ 80208e8:	4804      	ldr	r0, [pc, #16]	@ (80208fc <bsp_InitI2C+0x40>)
+ 80208ea:	f016 fe77 	bl	80375dc <HAL_GPIO_Init>
+
+	/* 给一个停止信号, 复位I2C总线上的所有设备到待机模式 */
+	i2c_Stop();
+ 80208ee:	f000 f82b 	bl	8020948 <i2c_Stop>
+}
+ 80208f2:	bf00      	nop
+ 80208f4:	3718      	adds	r7, #24
+ 80208f6:	46bd      	mov	sp, r7
+ 80208f8:	bd80      	pop	{r7, pc}
+ 80208fa:	bf00      	nop
+ 80208fc:	58021000 	.word	0x58021000
+
+08020900 <i2c_Delay>:
+*	形    参:  无
+*	返 回 值: 无
+*********************************************************************************************************
+*/
+static void i2c_Delay(void)
+{
+ 8020900:	b580      	push	{r7, lr}
+ 8020902:	af00      	add	r7, sp, #0
+	GF_BSP_TIMER_DelayUS(2);
+ 8020904:	2002      	movs	r0, #2
+ 8020906:	f000 fdc5 	bl	8021494 <GF_BSP_TIMER_DelayUS>
+}
+ 802090a:	bf00      	nop
+ 802090c:	bd80      	pop	{r7, pc}
+	...
+
+08020910 <i2c_Start>:
+*	形    参:  无
+*	返 回 值: 无
+*********************************************************************************************************
+*/
+void i2c_Start(void)
+{
+ 8020910:	b580      	push	{r7, lr}
+ 8020912:	af00      	add	r7, sp, #0
+	/* 当SCL高电平时，SDA出现一个下跳沿表示I2C总线启动信号 */
+	I2C_SDA_1();
+ 8020914:	4b0b      	ldr	r3, [pc, #44]	@ (8020944 <i2c_Start+0x34>)
+ 8020916:	f44f 5200 	mov.w	r2, #8192	@ 0x2000
+ 802091a:	619a      	str	r2, [r3, #24]
+	I2C_SCL_1();
+ 802091c:	4b09      	ldr	r3, [pc, #36]	@ (8020944 <i2c_Start+0x34>)
+ 802091e:	f44f 5280 	mov.w	r2, #4096	@ 0x1000
+ 8020922:	619a      	str	r2, [r3, #24]
+	i2c_Delay();
+ 8020924:	f7ff ffec 	bl	8020900 <i2c_Delay>
+	I2C_SDA_0();
+ 8020928:	4b06      	ldr	r3, [pc, #24]	@ (8020944 <i2c_Start+0x34>)
+ 802092a:	f04f 5200 	mov.w	r2, #536870912	@ 0x20000000
+ 802092e:	619a      	str	r2, [r3, #24]
+	i2c_Delay();
+ 8020930:	f7ff ffe6 	bl	8020900 <i2c_Delay>
+	
+	I2C_SCL_0();
+ 8020934:	4b03      	ldr	r3, [pc, #12]	@ (8020944 <i2c_Start+0x34>)
+ 8020936:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
+ 802093a:	619a      	str	r2, [r3, #24]
+	i2c_Delay();
+ 802093c:	f7ff ffe0 	bl	8020900 <i2c_Delay>
+}
+ 8020940:	bf00      	nop
+ 8020942:	bd80      	pop	{r7, pc}
+ 8020944:	58021000 	.word	0x58021000
+
+08020948 <i2c_Stop>:
+*	形    参:  无
+*	返 回 值: 无
+*********************************************************************************************************
+*/
+void i2c_Stop(void)
+{
+ 8020948:	b580      	push	{r7, lr}
+ 802094a:	af00      	add	r7, sp, #0
+	/* 当SCL高电平时，SDA出现一个上跳沿表示I2C总线停止信号 */
+	I2C_SDA_0();
+ 802094c:	4b09      	ldr	r3, [pc, #36]	@ (8020974 <i2c_Stop+0x2c>)
+ 802094e:	f04f 5200 	mov.w	r2, #536870912	@ 0x20000000
+ 8020952:	619a      	str	r2, [r3, #24]
+	i2c_Delay();
+ 8020954:	f7ff ffd4 	bl	8020900 <i2c_Delay>
+	I2C_SCL_1();
+ 8020958:	4b06      	ldr	r3, [pc, #24]	@ (8020974 <i2c_Stop+0x2c>)
+ 802095a:	f44f 5280 	mov.w	r2, #4096	@ 0x1000
+ 802095e:	619a      	str	r2, [r3, #24]
+	i2c_Delay();
+ 8020960:	f7ff ffce 	bl	8020900 <i2c_Delay>
+	I2C_SDA_1();
+ 8020964:	4b03      	ldr	r3, [pc, #12]	@ (8020974 <i2c_Stop+0x2c>)
+ 8020966:	f44f 5200 	mov.w	r2, #8192	@ 0x2000
+ 802096a:	619a      	str	r2, [r3, #24]
+	i2c_Delay();
+ 802096c:	f7ff ffc8 	bl	8020900 <i2c_Delay>
+}
+ 8020970:	bf00      	nop
+ 8020972:	bd80      	pop	{r7, pc}
+ 8020974:	58021000 	.word	0x58021000
+
+08020978 <i2c_SendByte>:
+*	形    参:  _ucByte ： 等待发送的字节
+*	返 回 值: 无
+*********************************************************************************************************
+*/
+void i2c_SendByte(uint8_t _ucByte)
+{
+ 8020978:	b580      	push	{r7, lr}
+ 802097a:	b084      	sub	sp, #16
+ 802097c:	af00      	add	r7, sp, #0
+ 802097e:	4603      	mov	r3, r0
+ 8020980:	71fb      	strb	r3, [r7, #7]
+	uint8_t i;
+
+	/* 先发送字节的高位bit7 */
+	for (i = 0; i < 8; i++)
+ 8020982:	2300      	movs	r3, #0
+ 8020984:	73fb      	strb	r3, [r7, #15]
+ 8020986:	e029      	b.n	80209dc <i2c_SendByte+0x64>
+	{
+		if (_ucByte & 0x80)
+ 8020988:	f997 3007 	ldrsb.w	r3, [r7, #7]
+ 802098c:	2b00      	cmp	r3, #0
+ 802098e:	da04      	bge.n	802099a <i2c_SendByte+0x22>
+		{
+			I2C_SDA_1();
+ 8020990:	4b16      	ldr	r3, [pc, #88]	@ (80209ec <i2c_SendByte+0x74>)
+ 8020992:	f44f 5200 	mov.w	r2, #8192	@ 0x2000
+ 8020996:	619a      	str	r2, [r3, #24]
+ 8020998:	e003      	b.n	80209a2 <i2c_SendByte+0x2a>
+		}
+		else
+		{
+			I2C_SDA_0();
+ 802099a:	4b14      	ldr	r3, [pc, #80]	@ (80209ec <i2c_SendByte+0x74>)
+ 802099c:	f04f 5200 	mov.w	r2, #536870912	@ 0x20000000
+ 80209a0:	619a      	str	r2, [r3, #24]
+		}
+		i2c_Delay();
+ 80209a2:	f7ff ffad 	bl	8020900 <i2c_Delay>
+		I2C_SCL_1();
+ 80209a6:	4b11      	ldr	r3, [pc, #68]	@ (80209ec <i2c_SendByte+0x74>)
+ 80209a8:	f44f 5280 	mov.w	r2, #4096	@ 0x1000
+ 80209ac:	619a      	str	r2, [r3, #24]
+		i2c_Delay();
+ 80209ae:	f7ff ffa7 	bl	8020900 <i2c_Delay>
+		I2C_SCL_0();
+ 80209b2:	4b0e      	ldr	r3, [pc, #56]	@ (80209ec <i2c_SendByte+0x74>)
+ 80209b4:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
+ 80209b8:	619a      	str	r2, [r3, #24]
+		I2C_SCL_0();	/* 2019-03-14 针对GT811电容触摸，添加一行，相当于延迟几十ns */
+ 80209ba:	4b0c      	ldr	r3, [pc, #48]	@ (80209ec <i2c_SendByte+0x74>)
+ 80209bc:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
+ 80209c0:	619a      	str	r2, [r3, #24]
+		if (i == 7)
+ 80209c2:	7bfb      	ldrb	r3, [r7, #15]
+ 80209c4:	2b07      	cmp	r3, #7
+ 80209c6:	d103      	bne.n	80209d0 <i2c_SendByte+0x58>
+		{
+			 I2C_SDA_1(); // 释放总线
+ 80209c8:	4b08      	ldr	r3, [pc, #32]	@ (80209ec <i2c_SendByte+0x74>)
+ 80209ca:	f44f 5200 	mov.w	r2, #8192	@ 0x2000
+ 80209ce:	619a      	str	r2, [r3, #24]
+		}
+		_ucByte <<= 1;	/* 左移一个bit */	
+ 80209d0:	79fb      	ldrb	r3, [r7, #7]
+ 80209d2:	005b      	lsls	r3, r3, #1
+ 80209d4:	71fb      	strb	r3, [r7, #7]
+	for (i = 0; i < 8; i++)
+ 80209d6:	7bfb      	ldrb	r3, [r7, #15]
+ 80209d8:	3301      	adds	r3, #1
+ 80209da:	73fb      	strb	r3, [r7, #15]
+ 80209dc:	7bfb      	ldrb	r3, [r7, #15]
+ 80209de:	2b07      	cmp	r3, #7
+ 80209e0:	d9d2      	bls.n	8020988 <i2c_SendByte+0x10>
+	}
+}
+ 80209e2:	bf00      	nop
+ 80209e4:	bf00      	nop
+ 80209e6:	3710      	adds	r7, #16
+ 80209e8:	46bd      	mov	sp, r7
+ 80209ea:	bd80      	pop	{r7, pc}
+ 80209ec:	58021000 	.word	0x58021000
+
+080209f0 <i2c_ReadByte>:
+*	形    参:  无
+*	返 回 值: 读到的数据
+*********************************************************************************************************
+*/
+uint8_t i2c_ReadByte(void)
+{
+ 80209f0:	b580      	push	{r7, lr}
+ 80209f2:	b082      	sub	sp, #8
+ 80209f4:	af00      	add	r7, sp, #0
+	uint8_t i;
+	uint8_t value;
+
+	/* 读到第1个bit为数据的bit7 */
+	value = 0;
+ 80209f6:	2300      	movs	r3, #0
+ 80209f8:	71bb      	strb	r3, [r7, #6]
+	for (i = 0; i < 8; i++)
+ 80209fa:	2300      	movs	r3, #0
+ 80209fc:	71fb      	strb	r3, [r7, #7]
+ 80209fe:	e01a      	b.n	8020a36 <i2c_ReadByte+0x46>
+	{
+		value <<= 1;
+ 8020a00:	79bb      	ldrb	r3, [r7, #6]
+ 8020a02:	005b      	lsls	r3, r3, #1
+ 8020a04:	71bb      	strb	r3, [r7, #6]
+		I2C_SCL_1();
+ 8020a06:	4b10      	ldr	r3, [pc, #64]	@ (8020a48 <i2c_ReadByte+0x58>)
+ 8020a08:	f44f 5280 	mov.w	r2, #4096	@ 0x1000
+ 8020a0c:	619a      	str	r2, [r3, #24]
+		i2c_Delay();
+ 8020a0e:	f7ff ff77 	bl	8020900 <i2c_Delay>
+		if (I2C_SDA_READ())
+ 8020a12:	4b0d      	ldr	r3, [pc, #52]	@ (8020a48 <i2c_ReadByte+0x58>)
+ 8020a14:	691b      	ldr	r3, [r3, #16]
+ 8020a16:	f403 5300 	and.w	r3, r3, #8192	@ 0x2000
+ 8020a1a:	2b00      	cmp	r3, #0
+ 8020a1c:	d002      	beq.n	8020a24 <i2c_ReadByte+0x34>
+		{
+			value++;
+ 8020a1e:	79bb      	ldrb	r3, [r7, #6]
+ 8020a20:	3301      	adds	r3, #1
+ 8020a22:	71bb      	strb	r3, [r7, #6]
+		}
+		I2C_SCL_0();
+ 8020a24:	4b08      	ldr	r3, [pc, #32]	@ (8020a48 <i2c_ReadByte+0x58>)
+ 8020a26:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
+ 8020a2a:	619a      	str	r2, [r3, #24]
+		i2c_Delay();
+ 8020a2c:	f7ff ff68 	bl	8020900 <i2c_Delay>
+	for (i = 0; i < 8; i++)
+ 8020a30:	79fb      	ldrb	r3, [r7, #7]
+ 8020a32:	3301      	adds	r3, #1
+ 8020a34:	71fb      	strb	r3, [r7, #7]
+ 8020a36:	79fb      	ldrb	r3, [r7, #7]
+ 8020a38:	2b07      	cmp	r3, #7
+ 8020a3a:	d9e1      	bls.n	8020a00 <i2c_ReadByte+0x10>
+	}
+	return value;
+ 8020a3c:	79bb      	ldrb	r3, [r7, #6]
+}
+ 8020a3e:	4618      	mov	r0, r3
+ 8020a40:	3708      	adds	r7, #8
+ 8020a42:	46bd      	mov	sp, r7
+ 8020a44:	bd80      	pop	{r7, pc}
+ 8020a46:	bf00      	nop
+ 8020a48:	58021000 	.word	0x58021000
+
+08020a4c <i2c_WaitAck>:
+*	形    参:  无
+*	返 回 值: 返回0表示正确应答，1表示无器件响应
+*********************************************************************************************************
+*/
+uint8_t i2c_WaitAck(void)
+{
+ 8020a4c:	b580      	push	{r7, lr}
+ 8020a4e:	b082      	sub	sp, #8
+ 8020a50:	af00      	add	r7, sp, #0
+	uint8_t re;
+
+	I2C_SDA_1();	/* CPU释放SDA总线 */
+ 8020a52:	4b11      	ldr	r3, [pc, #68]	@ (8020a98 <i2c_WaitAck+0x4c>)
+ 8020a54:	f44f 5200 	mov.w	r2, #8192	@ 0x2000
+ 8020a58:	619a      	str	r2, [r3, #24]
+	i2c_Delay();
+ 8020a5a:	f7ff ff51 	bl	8020900 <i2c_Delay>
+	I2C_SCL_1();	/* CPU驱动SCL = 1, 此时器件会返回ACK应答 */
+ 8020a5e:	4b0e      	ldr	r3, [pc, #56]	@ (8020a98 <i2c_WaitAck+0x4c>)
+ 8020a60:	f44f 5280 	mov.w	r2, #4096	@ 0x1000
+ 8020a64:	619a      	str	r2, [r3, #24]
+	i2c_Delay();
+ 8020a66:	f7ff ff4b 	bl	8020900 <i2c_Delay>
+	if (I2C_SDA_READ())	/* CPU读取SDA口线状态 */
+ 8020a6a:	4b0b      	ldr	r3, [pc, #44]	@ (8020a98 <i2c_WaitAck+0x4c>)
+ 8020a6c:	691b      	ldr	r3, [r3, #16]
+ 8020a6e:	f403 5300 	and.w	r3, r3, #8192	@ 0x2000
+ 8020a72:	2b00      	cmp	r3, #0
+ 8020a74:	d002      	beq.n	8020a7c <i2c_WaitAck+0x30>
+	{
+		re = 1;
+ 8020a76:	2301      	movs	r3, #1
+ 8020a78:	71fb      	strb	r3, [r7, #7]
+ 8020a7a:	e001      	b.n	8020a80 <i2c_WaitAck+0x34>
+	}
+	else
+	{
+		re = 0;
+ 8020a7c:	2300      	movs	r3, #0
+ 8020a7e:	71fb      	strb	r3, [r7, #7]
+	}
+	I2C_SCL_0();
+ 8020a80:	4b05      	ldr	r3, [pc, #20]	@ (8020a98 <i2c_WaitAck+0x4c>)
+ 8020a82:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
+ 8020a86:	619a      	str	r2, [r3, #24]
+	i2c_Delay();
+ 8020a88:	f7ff ff3a 	bl	8020900 <i2c_Delay>
+	return re;
+ 8020a8c:	79fb      	ldrb	r3, [r7, #7]
+}
+ 8020a8e:	4618      	mov	r0, r3
+ 8020a90:	3708      	adds	r7, #8
+ 8020a92:	46bd      	mov	sp, r7
+ 8020a94:	bd80      	pop	{r7, pc}
+ 8020a96:	bf00      	nop
+ 8020a98:	58021000 	.word	0x58021000
+
+08020a9c <i2c_Ack>:
+*	形    参:  无
+*	返 回 值: 无
+*********************************************************************************************************
+*/
+void i2c_Ack(void)
+{
+ 8020a9c:	b580      	push	{r7, lr}
+ 8020a9e:	af00      	add	r7, sp, #0
+	I2C_SDA_0();	/* CPU驱动SDA = 0 */
+ 8020aa0:	4b0c      	ldr	r3, [pc, #48]	@ (8020ad4 <i2c_Ack+0x38>)
+ 8020aa2:	f04f 5200 	mov.w	r2, #536870912	@ 0x20000000
+ 8020aa6:	619a      	str	r2, [r3, #24]
+	i2c_Delay();
+ 8020aa8:	f7ff ff2a 	bl	8020900 <i2c_Delay>
+	I2C_SCL_1();	/* CPU产生1个时钟 */
+ 8020aac:	4b09      	ldr	r3, [pc, #36]	@ (8020ad4 <i2c_Ack+0x38>)
+ 8020aae:	f44f 5280 	mov.w	r2, #4096	@ 0x1000
+ 8020ab2:	619a      	str	r2, [r3, #24]
+	i2c_Delay();
+ 8020ab4:	f7ff ff24 	bl	8020900 <i2c_Delay>
+	I2C_SCL_0();
+ 8020ab8:	4b06      	ldr	r3, [pc, #24]	@ (8020ad4 <i2c_Ack+0x38>)
+ 8020aba:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
+ 8020abe:	619a      	str	r2, [r3, #24]
+	i2c_Delay();
+ 8020ac0:	f7ff ff1e 	bl	8020900 <i2c_Delay>
+	I2C_SDA_1();	/* CPU释放SDA总线 */
+ 8020ac4:	4b03      	ldr	r3, [pc, #12]	@ (8020ad4 <i2c_Ack+0x38>)
+ 8020ac6:	f44f 5200 	mov.w	r2, #8192	@ 0x2000
+ 8020aca:	619a      	str	r2, [r3, #24]
+	
+	i2c_Delay();
+ 8020acc:	f7ff ff18 	bl	8020900 <i2c_Delay>
+}
+ 8020ad0:	bf00      	nop
+ 8020ad2:	bd80      	pop	{r7, pc}
+ 8020ad4:	58021000 	.word	0x58021000
+
+08020ad8 <i2c_NAck>:
+*	形    参:  无
+*	返 回 值: 无
+*********************************************************************************************************
+*/
+void i2c_NAck(void)
+{
+ 8020ad8:	b580      	push	{r7, lr}
+ 8020ada:	af00      	add	r7, sp, #0
+	I2C_SDA_1();	/* CPU驱动SDA = 1 */
+ 8020adc:	4b09      	ldr	r3, [pc, #36]	@ (8020b04 <i2c_NAck+0x2c>)
+ 8020ade:	f44f 5200 	mov.w	r2, #8192	@ 0x2000
+ 8020ae2:	619a      	str	r2, [r3, #24]
+	i2c_Delay();
+ 8020ae4:	f7ff ff0c 	bl	8020900 <i2c_Delay>
+	I2C_SCL_1();	/* CPU产生1个时钟 */
+ 8020ae8:	4b06      	ldr	r3, [pc, #24]	@ (8020b04 <i2c_NAck+0x2c>)
+ 8020aea:	f44f 5280 	mov.w	r2, #4096	@ 0x1000
+ 8020aee:	619a      	str	r2, [r3, #24]
+	i2c_Delay();
+ 8020af0:	f7ff ff06 	bl	8020900 <i2c_Delay>
+	I2C_SCL_0();
+ 8020af4:	4b03      	ldr	r3, [pc, #12]	@ (8020b04 <i2c_NAck+0x2c>)
+ 8020af6:	f04f 5280 	mov.w	r2, #268435456	@ 0x10000000
+ 8020afa:	619a      	str	r2, [r3, #24]
+	i2c_Delay();
+ 8020afc:	f7ff ff00 	bl	8020900 <i2c_Delay>
+}
+ 8020b00:	bf00      	nop
+ 8020b02:	bd80      	pop	{r7, pc}
+ 8020b04:	58021000 	.word	0x58021000
+
+08020b08 <i2c_CheckDevice>:
+*	形    参:  _Address：设备的I2C总线地址
+*	返 回 值: 返回值 0 表示正确， 返回1表示未探测到
+*********************************************************************************************************
+*/
+uint8_t i2c_CheckDevice(uint8_t _Address)
+{
+ 8020b08:	b580      	push	{r7, lr}
+ 8020b0a:	b084      	sub	sp, #16
+ 8020b0c:	af00      	add	r7, sp, #0
+ 8020b0e:	4603      	mov	r3, r0
+ 8020b10:	71fb      	strb	r3, [r7, #7]
+	uint8_t ucAck;
+
+	if (I2C_SDA_READ() && I2C_SCL_READ())
+ 8020b12:	4b0f      	ldr	r3, [pc, #60]	@ (8020b50 <i2c_CheckDevice+0x48>)
+ 8020b14:	691b      	ldr	r3, [r3, #16]
+ 8020b16:	f403 5300 	and.w	r3, r3, #8192	@ 0x2000
+ 8020b1a:	2b00      	cmp	r3, #0
+ 8020b1c:	d013      	beq.n	8020b46 <i2c_CheckDevice+0x3e>
+ 8020b1e:	4b0c      	ldr	r3, [pc, #48]	@ (8020b50 <i2c_CheckDevice+0x48>)
+ 8020b20:	691b      	ldr	r3, [r3, #16]
+ 8020b22:	f403 5380 	and.w	r3, r3, #4096	@ 0x1000
+ 8020b26:	2b00      	cmp	r3, #0
+ 8020b28:	d00d      	beq.n	8020b46 <i2c_CheckDevice+0x3e>
+	{
+		i2c_Start();		/* 发送启动信号 */
+ 8020b2a:	f7ff fef1 	bl	8020910 <i2c_Start>
+
+		/* 发送设备地址+读写控制bit（0 = w， 1 = r) bit7 先传 */
+		i2c_SendByte(_Address | I2C_WR);
+ 8020b2e:	79fb      	ldrb	r3, [r7, #7]
+ 8020b30:	4618      	mov	r0, r3
+ 8020b32:	f7ff ff21 	bl	8020978 <i2c_SendByte>
+		ucAck = i2c_WaitAck();	/* 检测设备的ACK应答 */
+ 8020b36:	f7ff ff89 	bl	8020a4c <i2c_WaitAck>
+ 8020b3a:	4603      	mov	r3, r0
+ 8020b3c:	73fb      	strb	r3, [r7, #15]
+
+		i2c_Stop();			/* 发送停止信号 */
+ 8020b3e:	f7ff ff03 	bl	8020948 <i2c_Stop>
+
+		return ucAck;
+ 8020b42:	7bfb      	ldrb	r3, [r7, #15]
+ 8020b44:	e000      	b.n	8020b48 <i2c_CheckDevice+0x40>
+	}
+	return 1;	/* I2C总线异常 */
+ 8020b46:	2301      	movs	r3, #1
+}
+ 8020b48:	4618      	mov	r0, r3
+ 8020b4a:	3710      	adds	r7, #16
+ 8020b4c:	46bd      	mov	sp, r7
+ 8020b4e:	bd80      	pop	{r7, pc}
+ 8020b50:	58021000 	.word	0x58021000
+
+08020b54 <GF_BSP_EEPROM_CheckOK>:
+*	形    参:  无
+*	返 回 值: 1 表示正常， 0 表示不正常
+*********************************************************************************************************
+*/
+uint8_t GF_BSP_EEPROM_CheckOK(void)
+{
+ 8020b54:	b580      	push	{r7, lr}
+ 8020b56:	af00      	add	r7, sp, #0
+	if (i2c_CheckDevice(EE_DEV_ADDR) == 0)
+ 8020b58:	20a0      	movs	r0, #160	@ 0xa0
+ 8020b5a:	f7ff ffd5 	bl	8020b08 <i2c_CheckDevice>
+ 8020b5e:	4603      	mov	r3, r0
+ 8020b60:	2b00      	cmp	r3, #0
+ 8020b62:	d101      	bne.n	8020b68 <GF_BSP_EEPROM_CheckOK+0x14>
+	{
+		return 1;
+ 8020b64:	2301      	movs	r3, #1
+ 8020b66:	e002      	b.n	8020b6e <GF_BSP_EEPROM_CheckOK+0x1a>
+	}
+	else
+	{
+		/* 失败后，切记发送I2C总线停止信号 */
+		i2c_Stop();
+ 8020b68:	f7ff feee 	bl	8020948 <i2c_Stop>
+		return 0;
+ 8020b6c:	2300      	movs	r3, #0
+	}
+}
+ 8020b6e:	4618      	mov	r0, r3
+ 8020b70:	bd80      	pop	{r7, pc}
+
+08020b72 <GF_BSP_EEPROM_ReadBytes>:
+*			 _pReadBuf : 存放读到的数据的缓冲区指针
+*	返 回 值: 0 表示失败，1表示成功
+*********************************************************************************************************
+*/
+uint8_t GF_BSP_EEPROM_ReadBytes(uint8_t *_pReadBuf, uint16_t _usAddress, uint16_t _usSize)
+{
+ 8020b72:	b590      	push	{r4, r7, lr}
+ 8020b74:	b085      	sub	sp, #20
+ 8020b76:	af00      	add	r7, sp, #0
+ 8020b78:	6078      	str	r0, [r7, #4]
+ 8020b7a:	460b      	mov	r3, r1
+ 8020b7c:	807b      	strh	r3, [r7, #2]
+ 8020b7e:	4613      	mov	r3, r2
+ 8020b80:	803b      	strh	r3, [r7, #0]
+	uint16_t i;
+
+	/* 采用串行EEPROM随即读取指令序列，连续读取若干字节 */
+
+	/* 第1步：发起I2C总线启动信号 */
+	i2c_Start();
+ 8020b82:	f7ff fec5 	bl	8020910 <i2c_Start>
+
+	/* 第2步：发起控制字节，高7bit是地址，bit0是读写控制位，0表示写，1表示读 */
+	i2c_SendByte(EE_DEV_ADDR | I2C_WR);	/* 此处是写指令 */
+ 8020b86:	20a0      	movs	r0, #160	@ 0xa0
+ 8020b88:	f7ff fef6 	bl	8020978 <i2c_SendByte>
+
+	/* 第3步：发送ACK */
+	if (i2c_WaitAck() != 0)
+ 8020b8c:	f7ff ff5e 	bl	8020a4c <i2c_WaitAck>
+ 8020b90:	4603      	mov	r3, r0
+ 8020b92:	2b00      	cmp	r3, #0
+ 8020b94:	d13e      	bne.n	8020c14 <GF_BSP_EEPROM_ReadBytes+0xa2>
+			goto cmd_fail;	/* EEPROM器件无应答 */
+		}
+	}
+	else
+	{
+		i2c_SendByte(_usAddress >> 8);
+ 8020b96:	887b      	ldrh	r3, [r7, #2]
+ 8020b98:	0a1b      	lsrs	r3, r3, #8
+ 8020b9a:	b29b      	uxth	r3, r3
+ 8020b9c:	b2db      	uxtb	r3, r3
+ 8020b9e:	4618      	mov	r0, r3
+ 8020ba0:	f7ff feea 	bl	8020978 <i2c_SendByte>
+		if (i2c_WaitAck() != 0)
+ 8020ba4:	f7ff ff52 	bl	8020a4c <i2c_WaitAck>
+ 8020ba8:	4603      	mov	r3, r0
+ 8020baa:	2b00      	cmp	r3, #0
+ 8020bac:	d134      	bne.n	8020c18 <GF_BSP_EEPROM_ReadBytes+0xa6>
+		{
+			goto cmd_fail;	/* EEPROM器件无应答 */
+		}
+
+		i2c_SendByte(_usAddress&0xff);
+ 8020bae:	887b      	ldrh	r3, [r7, #2]
+ 8020bb0:	b2db      	uxtb	r3, r3
+ 8020bb2:	4618      	mov	r0, r3
+ 8020bb4:	f7ff fee0 	bl	8020978 <i2c_SendByte>
+		if (i2c_WaitAck() != 0)
+ 8020bb8:	f7ff ff48 	bl	8020a4c <i2c_WaitAck>
+ 8020bbc:	4603      	mov	r3, r0
+ 8020bbe:	2b00      	cmp	r3, #0
+ 8020bc0:	d12c      	bne.n	8020c1c <GF_BSP_EEPROM_ReadBytes+0xaa>
+			goto cmd_fail;	/* EEPROM器件无应答 */
+		}
+	}
+
+	/* 第6步：重新启动I2C总线。下面开始读取数据 */
+	i2c_Start();
+ 8020bc2:	f7ff fea5 	bl	8020910 <i2c_Start>
+
+	/* 第7步：发起控制字节，高7bit是地址，bit0是读写控制位，0表示写，1表示读 */
+	i2c_SendByte(EE_DEV_ADDR | I2C_RD);	/* 此处是读指令 */
+ 8020bc6:	20a1      	movs	r0, #161	@ 0xa1
+ 8020bc8:	f7ff fed6 	bl	8020978 <i2c_SendByte>
+
+	/* 第8步：发送ACK */
+	if (i2c_WaitAck() != 0)
+ 8020bcc:	f7ff ff3e 	bl	8020a4c <i2c_WaitAck>
+ 8020bd0:	4603      	mov	r3, r0
+ 8020bd2:	2b00      	cmp	r3, #0
+ 8020bd4:	d124      	bne.n	8020c20 <GF_BSP_EEPROM_ReadBytes+0xae>
+	{
+		goto cmd_fail;	/* EEPROM器件无应答 */
+	}
+
+	/* 第9步：循环读取数据 */
+	for (i = 0; i < _usSize; i++)
+ 8020bd6:	2300      	movs	r3, #0
+ 8020bd8:	81fb      	strh	r3, [r7, #14]
+ 8020bda:	e013      	b.n	8020c04 <GF_BSP_EEPROM_ReadBytes+0x92>
+	{
+		_pReadBuf[i] = i2c_ReadByte();	/* 读1个字节 */
+ 8020bdc:	89fb      	ldrh	r3, [r7, #14]
+ 8020bde:	687a      	ldr	r2, [r7, #4]
+ 8020be0:	18d4      	adds	r4, r2, r3
+ 8020be2:	f7ff ff05 	bl	80209f0 <i2c_ReadByte>
+ 8020be6:	4603      	mov	r3, r0
+ 8020be8:	7023      	strb	r3, [r4, #0]
+
+		/* 每读完1个字节后，需要发送Ack， 最后一个字节不需要Ack，发Nack */
+		if (i != _usSize - 1)
+ 8020bea:	89fa      	ldrh	r2, [r7, #14]
+ 8020bec:	883b      	ldrh	r3, [r7, #0]
+ 8020bee:	3b01      	subs	r3, #1
+ 8020bf0:	429a      	cmp	r2, r3
+ 8020bf2:	d002      	beq.n	8020bfa <GF_BSP_EEPROM_ReadBytes+0x88>
+		{
+			i2c_Ack();	/* 中间字节读完后，CPU产生ACK信号(驱动SDA = 0) */
+ 8020bf4:	f7ff ff52 	bl	8020a9c <i2c_Ack>
+ 8020bf8:	e001      	b.n	8020bfe <GF_BSP_EEPROM_ReadBytes+0x8c>
+		}
+		else
+		{
+			i2c_NAck();	/* 最后1个字节读完后，CPU产生NACK信号(驱动SDA = 1) */
+ 8020bfa:	f7ff ff6d 	bl	8020ad8 <i2c_NAck>
+	for (i = 0; i < _usSize; i++)
+ 8020bfe:	89fb      	ldrh	r3, [r7, #14]
+ 8020c00:	3301      	adds	r3, #1
+ 8020c02:	81fb      	strh	r3, [r7, #14]
+ 8020c04:	89fa      	ldrh	r2, [r7, #14]
+ 8020c06:	883b      	ldrh	r3, [r7, #0]
+ 8020c08:	429a      	cmp	r2, r3
+ 8020c0a:	d3e7      	bcc.n	8020bdc <GF_BSP_EEPROM_ReadBytes+0x6a>
+		}
+	}
+	/* 发送I2C总线停止信号 */
+	i2c_Stop();
+ 8020c0c:	f7ff fe9c 	bl	8020948 <i2c_Stop>
+	return 1;	/* 执行成功 */
+ 8020c10:	2301      	movs	r3, #1
+ 8020c12:	e009      	b.n	8020c28 <GF_BSP_EEPROM_ReadBytes+0xb6>
+		goto cmd_fail;	/* EEPROM器件无应答 */
+ 8020c14:	bf00      	nop
+ 8020c16:	e004      	b.n	8020c22 <GF_BSP_EEPROM_ReadBytes+0xb0>
+			goto cmd_fail;	/* EEPROM器件无应答 */
+ 8020c18:	bf00      	nop
+ 8020c1a:	e002      	b.n	8020c22 <GF_BSP_EEPROM_ReadBytes+0xb0>
+			goto cmd_fail;	/* EEPROM器件无应答 */
+ 8020c1c:	bf00      	nop
+ 8020c1e:	e000      	b.n	8020c22 <GF_BSP_EEPROM_ReadBytes+0xb0>
+		goto cmd_fail;	/* EEPROM器件无应答 */
+ 8020c20:	bf00      	nop
+
+cmd_fail: /* 命令执行失败后，切记发送停止信号，避免影响I2C总线上其他设备 */
+	/* 发送I2C总线停止信号 */
+	i2c_Stop();
+ 8020c22:	f7ff fe91 	bl	8020948 <i2c_Stop>
+	return 0;
+ 8020c26:	2300      	movs	r3, #0
+}
+ 8020c28:	4618      	mov	r0, r3
+ 8020c2a:	3714      	adds	r7, #20
+ 8020c2c:	46bd      	mov	sp, r7
+ 8020c2e:	bd90      	pop	{r4, r7, pc}
+
+08020c30 <GF_BSP_EEPROM_Get_CV>:
+	i2c_Stop();
+	return 0;
+}
+
+CV_struct_define GF_BSP_EEPROM_Get_CV(void)
+{
+ 8020c30:	b580      	push	{r7, lr}
+ 8020c32:	b0aa      	sub	sp, #168	@ 0xa8
+ 8020c34:	af00      	add	r7, sp, #0
+ 8020c36:	6078      	str	r0, [r7, #4]
+	CV_struct_define cv= {0};
+ 8020c38:	f107 030c 	add.w	r3, r7, #12
+ 8020c3c:	229c      	movs	r2, #156	@ 0x9c
+ 8020c3e:	2100      	movs	r1, #0
+ 8020c40:	4618      	mov	r0, r3
+ 8020c42:	f01f fb51 	bl	80402e8 <memset>
+	//char buffer[sizeof(CV_struct_define)];
+    GF_BSP_EEPROM_ReadBytes(&cv, GF_BSP_EEPROM_CV_struct_define_Start_Address, sizeof(CV_struct_define));
+ 8020c46:	f107 030c 	add.w	r3, r7, #12
+ 8020c4a:	229c      	movs	r2, #156	@ 0x9c
+ 8020c4c:	2100      	movs	r1, #0
+ 8020c4e:	4618      	mov	r0, r3
+ 8020c50:	f7ff ff8f 	bl	8020b72 <GF_BSP_EEPROM_ReadBytes>
+    return cv;
+ 8020c54:	687b      	ldr	r3, [r7, #4]
+ 8020c56:	4618      	mov	r0, r3
+ 8020c58:	f107 030c 	add.w	r3, r7, #12
+ 8020c5c:	229c      	movs	r2, #156	@ 0x9c
+ 8020c5e:	4619      	mov	r1, r3
+ 8020c60:	f01f fbac 	bl	80403bc <memcpy>
+
+}
+ 8020c64:	6878      	ldr	r0, [r7, #4]
+ 8020c66:	37a8      	adds	r7, #168	@ 0xa8
+ 8020c68:	46bd      	mov	sp, r7
+ 8020c6a:	bd80      	pop	{r7, pc}
+
+08020c6c <Error_Detect_Intialzie>:
+#include "bsp_Error_Detect.h"
+void ErrorDetect();
+HardWareController *HardWareErrorController;
+char Error_Detect_Enable=1;
+void Error_Detect_Intialzie(uint16_t DispacherPeriod)
+{
+ 8020c6c:	b580      	push	{r7, lr}
+ 8020c6e:	b082      	sub	sp, #8
+ 8020c70:	af00      	add	r7, sp, #0
+ 8020c72:	4603      	mov	r3, r0
+ 8020c74:	80fb      	strh	r3, [r7, #6]
+	HardWareErrorController = (HardWareController*) malloc(
+ 8020c76:	2018      	movs	r0, #24
+ 8020c78:	f01f f9ac 	bl	803ffd4 <malloc>
+ 8020c7c:	4603      	mov	r3, r0
+ 8020c7e:	461a      	mov	r2, r3
+ 8020c80:	4b10      	ldr	r3, [pc, #64]	@ (8020cc4 <Error_Detect_Intialzie+0x58>)
+ 8020c82:	601a      	str	r2, [r3, #0]
+				sizeof(HardWareController));
+	HardWareErrorController->pComHWHead = NULL;
+ 8020c84:	4b0f      	ldr	r3, [pc, #60]	@ (8020cc4 <Error_Detect_Intialzie+0x58>)
+ 8020c86:	681b      	ldr	r3, [r3, #0]
+ 8020c88:	2200      	movs	r2, #0
+ 8020c8a:	601a      	str	r2, [r3, #0]
+	HardWareErrorController->pComHWTail = NULL;
+ 8020c8c:	4b0d      	ldr	r3, [pc, #52]	@ (8020cc4 <Error_Detect_Intialzie+0x58>)
+ 8020c8e:	681b      	ldr	r3, [r3, #0]
+ 8020c90:	2200      	movs	r2, #0
+ 8020c92:	605a      	str	r2, [r3, #4]
+	HardWareErrorController->Add_PCOMHardWare = ComHardWare_List_Add_t;
+ 8020c94:	4b0b      	ldr	r3, [pc, #44]	@ (8020cc4 <Error_Detect_Intialzie+0x58>)
+ 8020c96:	681b      	ldr	r3, [r3, #0]
+ 8020c98:	4a0b      	ldr	r2, [pc, #44]	@ (8020cc8 <Error_Detect_Intialzie+0x5c>)
+ 8020c9a:	60da      	str	r2, [r3, #12]
+	HardWareErrorController->Set_PCOMHardWare = Set_PCOMHardWare_t;
+ 8020c9c:	4b09      	ldr	r3, [pc, #36]	@ (8020cc4 <Error_Detect_Intialzie+0x58>)
+ 8020c9e:	681b      	ldr	r3, [r3, #0]
+ 8020ca0:	4a0a      	ldr	r2, [pc, #40]	@ (8020ccc <Error_Detect_Intialzie+0x60>)
+ 8020ca2:	615a      	str	r2, [r3, #20]
+	HardWareErrorController->PCOMHardWare_Check = PCOMHardWare_Check_t;
+ 8020ca4:	4b07      	ldr	r3, [pc, #28]	@ (8020cc4 <Error_Detect_Intialzie+0x58>)
+ 8020ca6:	681b      	ldr	r3, [r3, #0]
+ 8020ca8:	4a09      	ldr	r2, [pc, #36]	@ (8020cd0 <Error_Detect_Intialzie+0x64>)
+ 8020caa:	611a      	str	r2, [r3, #16]
+	HardWareErrorController->DispacherCallTime = DispacherPeriod;//check the communicaton every 50ms
+ 8020cac:	4b05      	ldr	r3, [pc, #20]	@ (8020cc4 <Error_Detect_Intialzie+0x58>)
+ 8020cae:	681b      	ldr	r3, [r3, #0]
+ 8020cb0:	88fa      	ldrh	r2, [r7, #6]
+ 8020cb2:	815a      	strh	r2, [r3, #10]
+	GF_BSP_Interrupt_Add_CallBack(
+ 8020cb4:	4907      	ldr	r1, [pc, #28]	@ (8020cd4 <Error_Detect_Intialzie+0x68>)
+ 8020cb6:	200a      	movs	r0, #10
+ 8020cb8:	f000 fb1a 	bl	80212f0 <GF_BSP_Interrupt_Add_CallBack>
+				DF_BSP_InterCall_TIM8_2ms_PeriodElapsedCallback, ErrorDetect);
+}
+ 8020cbc:	bf00      	nop
+ 8020cbe:	3708      	adds	r7, #8
+ 8020cc0:	46bd      	mov	sp, r7
+ 8020cc2:	bd80      	pop	{r7, pc}
+ 8020cc4:	24000618 	.word	0x24000618
+ 8020cc8:	0802231d 	.word	0x0802231d
+ 8020ccc:	08022515 	.word	0x08022515
+ 8020cd0:	080223f1 	.word	0x080223f1
+ 8020cd4:	08020cd9 	.word	0x08020cd9
+
+08020cd8 <ErrorDetect>:
+void ErrorDetect()
+{
+ 8020cd8:	b580      	push	{r7, lr}
+ 8020cda:	af00      	add	r7, sp, #0
+	if(Error_Detect_Enable==1)
+ 8020cdc:	4b06      	ldr	r3, [pc, #24]	@ (8020cf8 <ErrorDetect+0x20>)
+ 8020cde:	781b      	ldrb	r3, [r3, #0]
+ 8020ce0:	2b01      	cmp	r3, #1
+ 8020ce2:	d106      	bne.n	8020cf2 <ErrorDetect+0x1a>
+	{
+		HardWareErrorController->PCOMHardWare_Check(HardWareErrorController);
+ 8020ce4:	4b05      	ldr	r3, [pc, #20]	@ (8020cfc <ErrorDetect+0x24>)
+ 8020ce6:	681b      	ldr	r3, [r3, #0]
+ 8020ce8:	691b      	ldr	r3, [r3, #16]
+ 8020cea:	4a04      	ldr	r2, [pc, #16]	@ (8020cfc <ErrorDetect+0x24>)
+ 8020cec:	6812      	ldr	r2, [r2, #0]
+ 8020cee:	4610      	mov	r0, r2
+ 8020cf0:	4798      	blx	r3
+	}
+
+}
+ 8020cf2:	bf00      	nop
+ 8020cf4:	bd80      	pop	{r7, pc}
+ 8020cf6:	bf00      	nop
+ 8020cf8:	24000000 	.word	0x24000000
+ 8020cfc:	24000618 	.word	0x24000618
+
+08020d00 <GF_BSP_FDCAN_Init>:
+
+int32_t CAN_ID;
+int32_t CAN_ID_2;
+
+uint8_t GF_BSP_FDCAN_Init(void)
+{
+ 8020d00:	b580      	push	{r7, lr}
+ 8020d02:	af00      	add	r7, sp, #0
+	if (HAL_FDCAN_ActivateNotification(&hfdcan1, FDCAN_IT_RX_FIFO0_NEW_MESSAGE,
+ 8020d04:	2200      	movs	r2, #0
+ 8020d06:	2101      	movs	r1, #1
+ 8020d08:	4818      	ldr	r0, [pc, #96]	@ (8020d6c <GF_BSP_FDCAN_Init+0x6c>)
+ 8020d0a:	f015 fefd 	bl	8036b08 <HAL_FDCAN_ActivateNotification>
+ 8020d0e:	4603      	mov	r3, r0
+ 8020d10:	2b00      	cmp	r3, #0
+ 8020d12:	d001      	beq.n	8020d18 <GF_BSP_FDCAN_Init+0x18>
+			0) != HAL_OK)
+	{
+		Error_Handler();
+ 8020d14:	f00e feb8 	bl	802fa88 <Error_Handler>
+	}
+
+	if (HAL_FDCAN_ActivateNotification(&hfdcan1, FDCAN_IT_BUS_OFF, 0) != HAL_OK)
+ 8020d18:	2200      	movs	r2, #0
+ 8020d1a:	f04f 7100 	mov.w	r1, #33554432	@ 0x2000000
+ 8020d1e:	4813      	ldr	r0, [pc, #76]	@ (8020d6c <GF_BSP_FDCAN_Init+0x6c>)
+ 8020d20:	f015 fef2 	bl	8036b08 <HAL_FDCAN_ActivateNotification>
+ 8020d24:	4603      	mov	r3, r0
+ 8020d26:	2b00      	cmp	r3, #0
+ 8020d28:	d001      	beq.n	8020d2e <GF_BSP_FDCAN_Init+0x2e>
+	{
+		Error_Handler();
+ 8020d2a:	f00e fead 	bl	802fa88 <Error_Handler>
+	}
+
+	HAL_FDCAN_Start(&hfdcan1);
+ 8020d2e:	480f      	ldr	r0, [pc, #60]	@ (8020d6c <GF_BSP_FDCAN_Init+0x6c>)
+ 8020d30:	f015 fcf8 	bl	8036724 <HAL_FDCAN_Start>
+
+	if (HAL_FDCAN_ActivateNotification(&hfdcan2, FDCAN_IT_RX_FIFO0_NEW_MESSAGE,
+ 8020d34:	2200      	movs	r2, #0
+ 8020d36:	2101      	movs	r1, #1
+ 8020d38:	480d      	ldr	r0, [pc, #52]	@ (8020d70 <GF_BSP_FDCAN_Init+0x70>)
+ 8020d3a:	f015 fee5 	bl	8036b08 <HAL_FDCAN_ActivateNotification>
+ 8020d3e:	4603      	mov	r3, r0
+ 8020d40:	2b00      	cmp	r3, #0
+ 8020d42:	d001      	beq.n	8020d48 <GF_BSP_FDCAN_Init+0x48>
+			0) != HAL_OK)
+	{
+		Error_Handler();
+ 8020d44:	f00e fea0 	bl	802fa88 <Error_Handler>
+	}
+
+	if (HAL_FDCAN_ActivateNotification(&hfdcan2, FDCAN_IT_BUS_OFF, 0) != HAL_OK)
+ 8020d48:	2200      	movs	r2, #0
+ 8020d4a:	f04f 7100 	mov.w	r1, #33554432	@ 0x2000000
+ 8020d4e:	4808      	ldr	r0, [pc, #32]	@ (8020d70 <GF_BSP_FDCAN_Init+0x70>)
+ 8020d50:	f015 feda 	bl	8036b08 <HAL_FDCAN_ActivateNotification>
+ 8020d54:	4603      	mov	r3, r0
+ 8020d56:	2b00      	cmp	r3, #0
+ 8020d58:	d001      	beq.n	8020d5e <GF_BSP_FDCAN_Init+0x5e>
+	{
+		Error_Handler();
+ 8020d5a:	f00e fe95 	bl	802fa88 <Error_Handler>
+	}
+
+	HAL_FDCAN_Start(&hfdcan2);
+ 8020d5e:	4804      	ldr	r0, [pc, #16]	@ (8020d70 <GF_BSP_FDCAN_Init+0x70>)
+ 8020d60:	f015 fce0 	bl	8036724 <HAL_FDCAN_Start>
+
+	return 1;
+ 8020d64:	2301      	movs	r3, #1
+}
+ 8020d66:	4618      	mov	r0, r3
+ 8020d68:	bd80      	pop	{r7, pc}
+ 8020d6a:	bf00      	nop
+ 8020d6c:	2400a578 	.word	0x2400a578
+ 8020d70:	2400a618 	.word	0x2400a618
+
+08020d74 <HAL_FDCAN_ErrorStatusCallback>:
+
+void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan,
+		uint32_t ErrorStatusITs)
+{
+ 8020d74:	b580      	push	{r7, lr}
+ 8020d76:	b082      	sub	sp, #8
+ 8020d78:	af00      	add	r7, sp, #0
+ 8020d7a:	6078      	str	r0, [r7, #4]
+ 8020d7c:	6039      	str	r1, [r7, #0]
+	if (hfdcan->Instance == FDCAN1)
+ 8020d7e:	687b      	ldr	r3, [r7, #4]
+ 8020d80:	681b      	ldr	r3, [r3, #0]
+ 8020d82:	4a08      	ldr	r2, [pc, #32]	@ (8020da4 <HAL_FDCAN_ErrorStatusCallback+0x30>)
+ 8020d84:	4293      	cmp	r3, r2
+ 8020d86:	d101      	bne.n	8020d8c <HAL_FDCAN_ErrorStatusCallback+0x18>
+	{
+		MX_FDCAN1_Init();
+ 8020d88:	f008 f9ee 	bl	8029168 <MX_FDCAN1_Init>
+	}
+	if (hfdcan->Instance == FDCAN2)
+ 8020d8c:	687b      	ldr	r3, [r7, #4]
+ 8020d8e:	681b      	ldr	r3, [r3, #0]
+ 8020d90:	4a05      	ldr	r2, [pc, #20]	@ (8020da8 <HAL_FDCAN_ErrorStatusCallback+0x34>)
+ 8020d92:	4293      	cmp	r3, r2
+ 8020d94:	d101      	bne.n	8020d9a <HAL_FDCAN_ErrorStatusCallback+0x26>
+	{
+		MX_FDCAN2_Init();
+ 8020d96:	f008 fa4b 	bl	8029230 <MX_FDCAN2_Init>
+	}
+}
+ 8020d9a:	bf00      	nop
+ 8020d9c:	3708      	adds	r7, #8
+ 8020d9e:	46bd      	mov	sp, r7
+ 8020da0:	bd80      	pop	{r7, pc}
+ 8020da2:	bf00      	nop
+ 8020da4:	4000a000 	.word	0x4000a000
+ 8020da8:	4000a400 	.word	0x4000a400
+
+08020dac <HAL_FDCAN_RxFifo0Callback>:
+
+void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs)
+{
+ 8020dac:	b580      	push	{r7, lr}
+ 8020dae:	b082      	sub	sp, #8
+ 8020db0:	af00      	add	r7, sp, #0
+ 8020db2:	6078      	str	r0, [r7, #4]
+ 8020db4:	6039      	str	r1, [r7, #0]
+	if (hfdcan->Instance == FDCAN1)
+ 8020db6:	687b      	ldr	r3, [r7, #4]
+ 8020db8:	681b      	ldr	r3, [r3, #0]
+ 8020dba:	4a30      	ldr	r2, [pc, #192]	@ (8020e7c <HAL_FDCAN_RxFifo0Callback+0xd0>)
+ 8020dbc:	4293      	cmp	r3, r2
+ 8020dbe:	d12a      	bne.n	8020e16 <HAL_FDCAN_RxFifo0Callback+0x6a>
+	{
+		if (HAL_FDCAN_GetRxMessage(hfdcan, FDCAN_RX_FIFO0, &CAN_RX_HDR, CAN_Buf)
+ 8020dc0:	4b2f      	ldr	r3, [pc, #188]	@ (8020e80 <HAL_FDCAN_RxFifo0Callback+0xd4>)
+ 8020dc2:	4a30      	ldr	r2, [pc, #192]	@ (8020e84 <HAL_FDCAN_RxFifo0Callback+0xd8>)
+ 8020dc4:	2140      	movs	r1, #64	@ 0x40
+ 8020dc6:	6878      	ldr	r0, [r7, #4]
+ 8020dc8:	f015 fd32 	bl	8036830 <HAL_FDCAN_GetRxMessage>
+ 8020dcc:	4603      	mov	r3, r0
+ 8020dce:	2b00      	cmp	r3, #0
+ 8020dd0:	d150      	bne.n	8020e74 <HAL_FDCAN_RxFifo0Callback+0xc8>
+				== HAL_OK)
+		{
+			CAN_ID = FD_CAN_1_Handler.ReceivedFrameID =
+					(uint32_t) CAN_RX_HDR.Identifier;
+ 8020dd2:	4b2c      	ldr	r3, [pc, #176]	@ (8020e84 <HAL_FDCAN_RxFifo0Callback+0xd8>)
+ 8020dd4:	681b      	ldr	r3, [r3, #0]
+			CAN_ID = FD_CAN_1_Handler.ReceivedFrameID =
+ 8020dd6:	4a2c      	ldr	r2, [pc, #176]	@ (8020e88 <HAL_FDCAN_RxFifo0Callback+0xdc>)
+ 8020dd8:	f8c2 3130 	str.w	r3, [r2, #304]	@ 0x130
+ 8020ddc:	4b2a      	ldr	r3, [pc, #168]	@ (8020e88 <HAL_FDCAN_RxFifo0Callback+0xdc>)
+ 8020dde:	f8d3 3130 	ldr.w	r3, [r3, #304]	@ 0x130
+ 8020de2:	461a      	mov	r2, r3
+ 8020de4:	4b29      	ldr	r3, [pc, #164]	@ (8020e8c <HAL_FDCAN_RxFifo0Callback+0xe0>)
+ 8020de6:	601a      	str	r2, [r3, #0]
+
+	#if NewCANSendVersion
+			FD_CAN_1_Handler.ReceivedLength = (uint32_t) CAN_RX_HDR.DataLength;
+ 8020de8:	4b26      	ldr	r3, [pc, #152]	@ (8020e84 <HAL_FDCAN_RxFifo0Callback+0xd8>)
+ 8020dea:	68db      	ldr	r3, [r3, #12]
+ 8020dec:	4a26      	ldr	r2, [pc, #152]	@ (8020e88 <HAL_FDCAN_RxFifo0Callback+0xdc>)
+ 8020dee:	f8c2 3128 	str.w	r3, [r2, #296]	@ 0x128
+	#else
+			FD_CAN_1_Handler.ReceivedLength = (uint32_t) CAN_RX_HDR.DataLength>>16;
+	#endif
+
+			if (FD_CAN_1_Handler.CAN_Decode != NULL  )
+ 8020df2:	4b25      	ldr	r3, [pc, #148]	@ (8020e88 <HAL_FDCAN_RxFifo0Callback+0xdc>)
+ 8020df4:	69db      	ldr	r3, [r3, #28]
+ 8020df6:	2b00      	cmp	r3, #0
+ 8020df8:	d009      	beq.n	8020e0e <HAL_FDCAN_RxFifo0Callback+0x62>
+			{
+				FD_CAN_1_Handler.CAN_Decode(FD_CAN_1_Handler.ReceivedFrameID,
+ 8020dfa:	4b23      	ldr	r3, [pc, #140]	@ (8020e88 <HAL_FDCAN_RxFifo0Callback+0xdc>)
+ 8020dfc:	69db      	ldr	r3, [r3, #28]
+ 8020dfe:	4a22      	ldr	r2, [pc, #136]	@ (8020e88 <HAL_FDCAN_RxFifo0Callback+0xdc>)
+ 8020e00:	f8d2 0130 	ldr.w	r0, [r2, #304]	@ 0x130
+ 8020e04:	4a20      	ldr	r2, [pc, #128]	@ (8020e88 <HAL_FDCAN_RxFifo0Callback+0xdc>)
+ 8020e06:	f8d2 2128 	ldr.w	r2, [r2, #296]	@ 0x128
+ 8020e0a:	491d      	ldr	r1, [pc, #116]	@ (8020e80 <HAL_FDCAN_RxFifo0Callback+0xd4>)
+ 8020e0c:	4798      	blx	r3
+						CAN_Buf, FD_CAN_1_Handler.ReceivedLength);
+			}
+			GF_BSP_Interrupt_Run_CallBack(DF_BSP_InterCall_FDCAN1_RxFifo0Callback);
+ 8020e0e:	2000      	movs	r0, #0
+ 8020e10:	f000 faac 	bl	802136c <GF_BSP_Interrupt_Run_CallBack>
+			}
+			GF_BSP_Interrupt_Run_CallBack(DF_BSP_InterCall_FDCAN2_RxFifo0Callback);
+		}
+
+	}
+}
+ 8020e14:	e02e      	b.n	8020e74 <HAL_FDCAN_RxFifo0Callback+0xc8>
+	} else if (hfdcan->Instance == FDCAN2)
+ 8020e16:	687b      	ldr	r3, [r7, #4]
+ 8020e18:	681b      	ldr	r3, [r3, #0]
+ 8020e1a:	4a1d      	ldr	r2, [pc, #116]	@ (8020e90 <HAL_FDCAN_RxFifo0Callback+0xe4>)
+ 8020e1c:	4293      	cmp	r3, r2
+ 8020e1e:	d129      	bne.n	8020e74 <HAL_FDCAN_RxFifo0Callback+0xc8>
+		if (HAL_FDCAN_GetRxMessage(hfdcan, FDCAN_RX_FIFO0, &CAN_RX_HDR,
+ 8020e20:	4b1c      	ldr	r3, [pc, #112]	@ (8020e94 <HAL_FDCAN_RxFifo0Callback+0xe8>)
+ 8020e22:	4a18      	ldr	r2, [pc, #96]	@ (8020e84 <HAL_FDCAN_RxFifo0Callback+0xd8>)
+ 8020e24:	2140      	movs	r1, #64	@ 0x40
+ 8020e26:	6878      	ldr	r0, [r7, #4]
+ 8020e28:	f015 fd02 	bl	8036830 <HAL_FDCAN_GetRxMessage>
+ 8020e2c:	4603      	mov	r3, r0
+ 8020e2e:	2b00      	cmp	r3, #0
+ 8020e30:	d120      	bne.n	8020e74 <HAL_FDCAN_RxFifo0Callback+0xc8>
+					(uint32_t) CAN_RX_HDR.Identifier;
+ 8020e32:	4b14      	ldr	r3, [pc, #80]	@ (8020e84 <HAL_FDCAN_RxFifo0Callback+0xd8>)
+ 8020e34:	681b      	ldr	r3, [r3, #0]
+			CAN_ID_2 = FD_CAN_2_Handler.ReceivedFrameID =
+ 8020e36:	4a18      	ldr	r2, [pc, #96]	@ (8020e98 <HAL_FDCAN_RxFifo0Callback+0xec>)
+ 8020e38:	f8c2 3130 	str.w	r3, [r2, #304]	@ 0x130
+ 8020e3c:	4b16      	ldr	r3, [pc, #88]	@ (8020e98 <HAL_FDCAN_RxFifo0Callback+0xec>)
+ 8020e3e:	f8d3 3130 	ldr.w	r3, [r3, #304]	@ 0x130
+ 8020e42:	461a      	mov	r2, r3
+ 8020e44:	4b15      	ldr	r3, [pc, #84]	@ (8020e9c <HAL_FDCAN_RxFifo0Callback+0xf0>)
+ 8020e46:	601a      	str	r2, [r3, #0]
+		FD_CAN_2_Handler.ReceivedLength = (uint32_t) CAN_RX_HDR.DataLength;
+ 8020e48:	4b0e      	ldr	r3, [pc, #56]	@ (8020e84 <HAL_FDCAN_RxFifo0Callback+0xd8>)
+ 8020e4a:	68db      	ldr	r3, [r3, #12]
+ 8020e4c:	4a12      	ldr	r2, [pc, #72]	@ (8020e98 <HAL_FDCAN_RxFifo0Callback+0xec>)
+ 8020e4e:	f8c2 3128 	str.w	r3, [r2, #296]	@ 0x128
+			if (FD_CAN_2_Handler.CAN_Decode != NULL)
+ 8020e52:	4b11      	ldr	r3, [pc, #68]	@ (8020e98 <HAL_FDCAN_RxFifo0Callback+0xec>)
+ 8020e54:	69db      	ldr	r3, [r3, #28]
+ 8020e56:	2b00      	cmp	r3, #0
+ 8020e58:	d009      	beq.n	8020e6e <HAL_FDCAN_RxFifo0Callback+0xc2>
+				FD_CAN_2_Handler.CAN_Decode(FD_CAN_2_Handler.ReceivedFrameID,
+ 8020e5a:	4b0f      	ldr	r3, [pc, #60]	@ (8020e98 <HAL_FDCAN_RxFifo0Callback+0xec>)
+ 8020e5c:	69db      	ldr	r3, [r3, #28]
+ 8020e5e:	4a0e      	ldr	r2, [pc, #56]	@ (8020e98 <HAL_FDCAN_RxFifo0Callback+0xec>)
+ 8020e60:	f8d2 0130 	ldr.w	r0, [r2, #304]	@ 0x130
+ 8020e64:	4a0c      	ldr	r2, [pc, #48]	@ (8020e98 <HAL_FDCAN_RxFifo0Callback+0xec>)
+ 8020e66:	f8d2 2128 	ldr.w	r2, [r2, #296]	@ 0x128
+ 8020e6a:	490a      	ldr	r1, [pc, #40]	@ (8020e94 <HAL_FDCAN_RxFifo0Callback+0xe8>)
+ 8020e6c:	4798      	blx	r3
+			GF_BSP_Interrupt_Run_CallBack(DF_BSP_InterCall_FDCAN2_RxFifo0Callback);
+ 8020e6e:	2001      	movs	r0, #1
+ 8020e70:	f000 fa7c 	bl	802136c <GF_BSP_Interrupt_Run_CallBack>
+}
+ 8020e74:	bf00      	nop
+ 8020e76:	3708      	adds	r7, #8
+ 8020e78:	46bd      	mov	sp, r7
+ 8020e7a:	bd80      	pop	{r7, pc}
+ 8020e7c:	4000a000 	.word	0x4000a000
+ 8020e80:	240008b4 	.word	0x240008b4
+ 8020e84:	2400088c 	.word	0x2400088c
+ 8020e88:	2400061c 	.word	0x2400061c
+ 8020e8c:	240008c4 	.word	0x240008c4
+ 8020e90:	4000a400 	.word	0x4000a400
+ 8020e94:	240008bc 	.word	0x240008bc
+ 8020e98:	24000754 	.word	0x24000754
+ 8020e9c:	240008c8 	.word	0x240008c8
+
+08020ea0 <GF_BSP_CANHandler_Init>:
+		HAL_FDCAN_AddMessageToTxFifoQ(&hfdcan2, &TXHeader2, Txdata);
+	}
+}
+void GF_BSP_CANHandler_Init(int can1_sendListPeriod, int can1_DispacherPeriod,
+		int can2_sendListPeriod, int can2_DispacherPeriod)
+{
+ 8020ea0:	b580      	push	{r7, lr}
+ 8020ea2:	b084      	sub	sp, #16
+ 8020ea4:	af00      	add	r7, sp, #0
+ 8020ea6:	60f8      	str	r0, [r7, #12]
+ 8020ea8:	60b9      	str	r1, [r7, #8]
+ 8020eaa:	607a      	str	r2, [r7, #4]
+ 8020eac:	603b      	str	r3, [r7, #0]
+
+
+	GF_BSP_CANHandler_Init_CAN(&FD_CAN_1_Handler, &hfdcan1, can1_sendListPeriod,
+ 8020eae:	68bb      	ldr	r3, [r7, #8]
+ 8020eb0:	68fa      	ldr	r2, [r7, #12]
+ 8020eb2:	4909      	ldr	r1, [pc, #36]	@ (8020ed8 <GF_BSP_CANHandler_Init+0x38>)
+ 8020eb4:	4809      	ldr	r0, [pc, #36]	@ (8020edc <GF_BSP_CANHandler_Init+0x3c>)
+ 8020eb6:	f000 f819 	bl	8020eec <GF_BSP_CANHandler_Init_CAN>
+			can1_DispacherPeriod);
+	GF_BSP_CANHandler_Init_CAN(&FD_CAN_2_Handler, &hfdcan2, can2_sendListPeriod,
+ 8020eba:	683b      	ldr	r3, [r7, #0]
+ 8020ebc:	687a      	ldr	r2, [r7, #4]
+ 8020ebe:	4908      	ldr	r1, [pc, #32]	@ (8020ee0 <GF_BSP_CANHandler_Init+0x40>)
+ 8020ec0:	4808      	ldr	r0, [pc, #32]	@ (8020ee4 <GF_BSP_CANHandler_Init+0x44>)
+ 8020ec2:	f000 f813 	bl	8020eec <GF_BSP_CANHandler_Init_CAN>
+			can2_DispacherPeriod);
+
+	GF_BSP_Interrupt_Add_CallBack(
+ 8020ec6:	4908      	ldr	r1, [pc, #32]	@ (8020ee8 <GF_BSP_CANHandler_Init+0x48>)
+ 8020ec8:	200a      	movs	r0, #10
+ 8020eca:	f000 fa11 	bl	80212f0 <GF_BSP_Interrupt_Add_CallBack>
+			DF_BSP_InterCall_TIM8_2ms_PeriodElapsedCallback, GF_BSP_CAN_Timer);
+}
+ 8020ece:	bf00      	nop
+ 8020ed0:	3710      	adds	r7, #16
+ 8020ed2:	46bd      	mov	sp, r7
+ 8020ed4:	bd80      	pop	{r7, pc}
+ 8020ed6:	bf00      	nop
+ 8020ed8:	2400a578 	.word	0x2400a578
+ 8020edc:	2400061c 	.word	0x2400061c
+ 8020ee0:	2400a618 	.word	0x2400a618
+ 8020ee4:	24000754 	.word	0x24000754
+ 8020ee8:	08020f91 	.word	0x08020f91
+
+08020eec <GF_BSP_CANHandler_Init_CAN>:
+
+void GF_BSP_CANHandler_Init_CAN(FDCANHandler *handler,
+		FDCAN_HandleTypeDef *canfd, int sendListPeriod, int DispacherPeriod)
+{
+ 8020eec:	b580      	push	{r7, lr}
+ 8020eee:	b084      	sub	sp, #16
+ 8020ef0:	af00      	add	r7, sp, #0
+ 8020ef2:	60f8      	str	r0, [r7, #12]
+ 8020ef4:	60b9      	str	r1, [r7, #8]
+ 8020ef6:	607a      	str	r2, [r7, #4]
+ 8020ef8:	603b      	str	r3, [r7, #0]
+	handler->canfd = canfd;
+ 8020efa:	68fb      	ldr	r3, [r7, #12]
+ 8020efc:	68ba      	ldr	r2, [r7, #8]
+ 8020efe:	601a      	str	r2, [r3, #0]
+	handler->dispacherController = (DispacherController*) malloc(
+ 8020f00:	2018      	movs	r0, #24
+ 8020f02:	f01f f867 	bl	803ffd4 <malloc>
+ 8020f06:	4603      	mov	r3, r0
+ 8020f08:	461a      	mov	r2, r3
+ 8020f0a:	68fb      	ldr	r3, [r7, #12]
+ 8020f0c:	605a      	str	r2, [r3, #4]
+			sizeof(DispacherController));
+
+
+	handler->dispacherController->pHead = NULL;
+ 8020f0e:	68fb      	ldr	r3, [r7, #12]
+ 8020f10:	685b      	ldr	r3, [r3, #4]
+ 8020f12:	2200      	movs	r2, #0
+ 8020f14:	601a      	str	r2, [r3, #0]
+	handler->dispacherController->pTail = NULL;
+ 8020f16:	68fb      	ldr	r3, [r7, #12]
+ 8020f18:	685b      	ldr	r3, [r3, #4]
+ 8020f1a:	2200      	movs	r2, #0
+ 8020f1c:	605a      	str	r2, [r3, #4]
+	handler->dispacherController->Dispacher_Enable = 1;
+ 8020f1e:	68fb      	ldr	r3, [r7, #12]
+ 8020f20:	685b      	ldr	r3, [r3, #4]
+ 8020f22:	2201      	movs	r2, #1
+ 8020f24:	81da      	strh	r2, [r3, #14]
+	handler->dispacherController->DispacherCallTime = DispacherPeriod ; // call the function every 50 ms
+ 8020f26:	68fb      	ldr	r3, [r7, #12]
+ 8020f28:	685b      	ldr	r3, [r3, #4]
+ 8020f2a:	683a      	ldr	r2, [r7, #0]
+ 8020f2c:	b292      	uxth	r2, r2
+ 8020f2e:	815a      	strh	r2, [r3, #10]
+	handler->dispacherController->Dispacher_Counter = 0;
+ 8020f30:	68fb      	ldr	r3, [r7, #12]
+ 8020f32:	685b      	ldr	r3, [r3, #4]
+ 8020f34:	2200      	movs	r2, #0
+ 8020f36:	819a      	strh	r2, [r3, #12]
+	handler->dispacherController->DispacherNumber = 0;
+ 8020f38:	68fb      	ldr	r3, [r7, #12]
+ 8020f3a:	685b      	ldr	r3, [r3, #4]
+ 8020f3c:	2200      	movs	r2, #0
+ 8020f3e:	811a      	strh	r2, [r3, #8]
+	handler->dispacherController->Add_Dispatcher_List = Dispatcher_List_Add_t;
+ 8020f40:	68fb      	ldr	r3, [r7, #12]
+ 8020f42:	685b      	ldr	r3, [r3, #4]
+ 8020f44:	4a0d      	ldr	r2, [pc, #52]	@ (8020f7c <GF_BSP_CANHandler_Init_CAN+0x90>)
+ 8020f46:	611a      	str	r2, [r3, #16]
+	handler->dispacherController->Dispatcher_Run = Dispatch_t;
+ 8020f48:	68fb      	ldr	r3, [r7, #12]
+ 8020f4a:	685b      	ldr	r3, [r3, #4]
+ 8020f4c:	4a0c      	ldr	r2, [pc, #48]	@ (8020f80 <GF_BSP_CANHandler_Init_CAN+0x94>)
+ 8020f4e:	615a      	str	r2, [r3, #20]
+
+	handler->timeSpan = 2;
+ 8020f50:	68fb      	ldr	r3, [r7, #12]
+ 8020f52:	2202      	movs	r2, #2
+ 8020f54:	721a      	strb	r2, [r3, #8]
+	handler->SendList_time_Count = 0;
+ 8020f56:	68fb      	ldr	r3, [r7, #12]
+ 8020f58:	2200      	movs	r2, #0
+ 8020f5a:	611a      	str	r2, [r3, #16]
+	handler->AddCANSendList = CANHandlerAddTxList;
+ 8020f5c:	68fb      	ldr	r3, [r7, #12]
+ 8020f5e:	4a09      	ldr	r2, [pc, #36]	@ (8020f84 <GF_BSP_CANHandler_Init_CAN+0x98>)
+ 8020f60:	619a      	str	r2, [r3, #24]
+	handler->SendList_Period = sendListPeriod;
+ 8020f62:	687a      	ldr	r2, [r7, #4]
+ 8020f64:	68fb      	ldr	r3, [r7, #12]
+ 8020f66:	60da      	str	r2, [r3, #12]
+
+	handler->CAN_Send = CAN_Send_t;
+ 8020f68:	68fb      	ldr	r3, [r7, #12]
+ 8020f6a:	4a07      	ldr	r2, [pc, #28]	@ (8020f88 <GF_BSP_CANHandler_Init_CAN+0x9c>)
+ 8020f6c:	621a      	str	r2, [r3, #32]
+	handler->CAN_Send_Data = CAN_Send_Data_t;
+ 8020f6e:	68fb      	ldr	r3, [r7, #12]
+ 8020f70:	4a06      	ldr	r2, [pc, #24]	@ (8020f8c <GF_BSP_CANHandler_Init_CAN+0xa0>)
+ 8020f72:	625a      	str	r2, [r3, #36]	@ 0x24
+
+}
+ 8020f74:	bf00      	nop
+ 8020f76:	3710      	adds	r7, #16
+ 8020f78:	46bd      	mov	sp, r7
+ 8020f7a:	bd80      	pop	{r7, pc}
+ 8020f7c:	0802227b 	.word	0x0802227b
+ 8020f80:	08022209 	.word	0x08022209
+ 8020f84:	0802118d 	.word	0x0802118d
+ 8020f88:	080210c1 	.word	0x080210c1
+ 8020f8c:	08021165 	.word	0x08021165
+
+08020f90 <GF_BSP_CAN_Timer>:
+
+DispacherController *can_dispacherController;
+HardWareController *can_HardWareController;
+void GF_BSP_CAN_Timer()
+{
+ 8020f90:	b580      	push	{r7, lr}
+ 8020f92:	af00      	add	r7, sp, #0
+	can_dispacherController = FD_CAN_1_Handler.dispacherController;
+ 8020f94:	4b15      	ldr	r3, [pc, #84]	@ (8020fec <GF_BSP_CAN_Timer+0x5c>)
+ 8020f96:	685b      	ldr	r3, [r3, #4]
+ 8020f98:	4a15      	ldr	r2, [pc, #84]	@ (8020ff0 <GF_BSP_CAN_Timer+0x60>)
+ 8020f9a:	6013      	str	r3, [r2, #0]
+
+	if (FD_CAN_1_Handler.pCurrentCANSendHadler != NULL)
+ 8020f9c:	4b13      	ldr	r3, [pc, #76]	@ (8020fec <GF_BSP_CAN_Timer+0x5c>)
+ 8020f9e:	695b      	ldr	r3, [r3, #20]
+ 8020fa0:	2b00      	cmp	r3, #0
+ 8020fa2:	d003      	beq.n	8020fac <GF_BSP_CAN_Timer+0x1c>
+	{
+		GF_CAN_Send_List_Send(&FD_CAN_1_Handler);
+ 8020fa4:	4811      	ldr	r0, [pc, #68]	@ (8020fec <GF_BSP_CAN_Timer+0x5c>)
+ 8020fa6:	f000 f827 	bl	8020ff8 <GF_CAN_Send_List_Send>
+ 8020faa:	e00a      	b.n	8020fc2 <GF_BSP_CAN_Timer+0x32>
+
+	} else
+	{
+		can_dispacherController = FD_CAN_1_Handler.dispacherController;
+ 8020fac:	4b0f      	ldr	r3, [pc, #60]	@ (8020fec <GF_BSP_CAN_Timer+0x5c>)
+ 8020fae:	685b      	ldr	r3, [r3, #4]
+ 8020fb0:	4a0f      	ldr	r2, [pc, #60]	@ (8020ff0 <GF_BSP_CAN_Timer+0x60>)
+ 8020fb2:	6013      	str	r3, [r2, #0]
+		can_dispacherController->Dispatcher_Run(can_dispacherController);
+ 8020fb4:	4b0e      	ldr	r3, [pc, #56]	@ (8020ff0 <GF_BSP_CAN_Timer+0x60>)
+ 8020fb6:	681b      	ldr	r3, [r3, #0]
+ 8020fb8:	695b      	ldr	r3, [r3, #20]
+ 8020fba:	4a0d      	ldr	r2, [pc, #52]	@ (8020ff0 <GF_BSP_CAN_Timer+0x60>)
+ 8020fbc:	6812      	ldr	r2, [r2, #0]
+ 8020fbe:	4610      	mov	r0, r2
+ 8020fc0:	4798      	blx	r3
+	}
+	if (FD_CAN_2_Handler.pCurrentCANSendHadler != NULL)
+ 8020fc2:	4b0c      	ldr	r3, [pc, #48]	@ (8020ff4 <GF_BSP_CAN_Timer+0x64>)
+ 8020fc4:	695b      	ldr	r3, [r3, #20]
+ 8020fc6:	2b00      	cmp	r3, #0
+ 8020fc8:	d003      	beq.n	8020fd2 <GF_BSP_CAN_Timer+0x42>
+	{
+		GF_CAN_Send_List_Send(&FD_CAN_2_Handler);
+ 8020fca:	480a      	ldr	r0, [pc, #40]	@ (8020ff4 <GF_BSP_CAN_Timer+0x64>)
+ 8020fcc:	f000 f814 	bl	8020ff8 <GF_CAN_Send_List_Send>
+		can_dispacherController = FD_CAN_2_Handler.dispacherController;
+		can_dispacherController->Dispatcher_Run(can_dispacherController);
+
+	}
+
+}
+ 8020fd0:	e00a      	b.n	8020fe8 <GF_BSP_CAN_Timer+0x58>
+		can_dispacherController = FD_CAN_2_Handler.dispacherController;
+ 8020fd2:	4b08      	ldr	r3, [pc, #32]	@ (8020ff4 <GF_BSP_CAN_Timer+0x64>)
+ 8020fd4:	685b      	ldr	r3, [r3, #4]
+ 8020fd6:	4a06      	ldr	r2, [pc, #24]	@ (8020ff0 <GF_BSP_CAN_Timer+0x60>)
+ 8020fd8:	6013      	str	r3, [r2, #0]
+		can_dispacherController->Dispatcher_Run(can_dispacherController);
+ 8020fda:	4b05      	ldr	r3, [pc, #20]	@ (8020ff0 <GF_BSP_CAN_Timer+0x60>)
+ 8020fdc:	681b      	ldr	r3, [r3, #0]
+ 8020fde:	695b      	ldr	r3, [r3, #20]
+ 8020fe0:	4a03      	ldr	r2, [pc, #12]	@ (8020ff0 <GF_BSP_CAN_Timer+0x60>)
+ 8020fe2:	6812      	ldr	r2, [r2, #0]
+ 8020fe4:	4610      	mov	r0, r2
+ 8020fe6:	4798      	blx	r3
+}
+ 8020fe8:	bf00      	nop
+ 8020fea:	bd80      	pop	{r7, pc}
+ 8020fec:	2400061c 	.word	0x2400061c
+ 8020ff0:	24000914 	.word	0x24000914
+ 8020ff4:	24000754 	.word	0x24000754
+
+08020ff8 <GF_CAN_Send_List_Send>:
+
+void GF_CAN_Send_List_Send(FDCANHandler *handler)
+{
+ 8020ff8:	b580      	push	{r7, lr}
+ 8020ffa:	b084      	sub	sp, #16
+ 8020ffc:	af00      	add	r7, sp, #0
+ 8020ffe:	6078      	str	r0, [r7, #4]
+
+	handler->SendList_time_Count++;
+ 8021000:	687b      	ldr	r3, [r7, #4]
+ 8021002:	691b      	ldr	r3, [r3, #16]
+ 8021004:	1c5a      	adds	r2, r3, #1
+ 8021006:	687b      	ldr	r3, [r7, #4]
+ 8021008:	611a      	str	r2, [r3, #16]
+	if (handler->timeSpan * handler->SendList_time_Count
+ 802100a:	687b      	ldr	r3, [r7, #4]
+ 802100c:	7a1b      	ldrb	r3, [r3, #8]
+ 802100e:	461a      	mov	r2, r3
+ 8021010:	687b      	ldr	r3, [r7, #4]
+ 8021012:	691b      	ldr	r3, [r3, #16]
+ 8021014:	fb03 f202 	mul.w	r2, r3, r2
+			>= handler->SendList_Period)
+ 8021018:	687b      	ldr	r3, [r7, #4]
+ 802101a:	68db      	ldr	r3, [r3, #12]
+	if (handler->timeSpan * handler->SendList_time_Count
+ 802101c:	429a      	cmp	r2, r3
+ 802101e:	d34a      	bcc.n	80210b6 <GF_CAN_Send_List_Send+0xbe>
+	{
+		handler->SendList_time_Count = 0;
+ 8021020:	687b      	ldr	r3, [r7, #4]
+ 8021022:	2200      	movs	r2, #0
+ 8021024:	611a      	str	r2, [r3, #16]
+		handler->SendListExists = 1;
+ 8021026:	687b      	ldr	r3, [r7, #4]
+ 8021028:	2201      	movs	r2, #1
+ 802102a:	725a      	strb	r2, [r3, #9]
+		if (handler->pCurrentCANSendHadler != NULL)
+ 802102c:	687b      	ldr	r3, [r7, #4]
+ 802102e:	695b      	ldr	r3, [r3, #20]
+ 8021030:	2b00      	cmp	r3, #0
+ 8021032:	d03d      	beq.n	80210b0 <GF_CAN_Send_List_Send+0xb8>
+		{
+			//拷贝数据到相关的代码中，然后发送
+
+			handler->SendFrameID=handler->pCurrentCANSendHadler->CAN_ID;
+ 8021034:	687b      	ldr	r3, [r7, #4]
+ 8021036:	695b      	ldr	r3, [r3, #20]
+ 8021038:	681a      	ldr	r2, [r3, #0]
+ 802103a:	687b      	ldr	r3, [r7, #4]
+ 802103c:	f8c3 2134 	str.w	r2, [r3, #308]	@ 0x134
+			//handler->CAN_Decode = handler->pCurrentCANSendHadler->CAN_Decode; //
+			memcpy(handler->Tx_Buf, handler->pCurrentCANSendHadler->Tx_Buf,
+ 8021040:	687b      	ldr	r3, [r7, #4]
+ 8021042:	f103 00a8 	add.w	r0, r3, #168	@ 0xa8
+ 8021046:	687b      	ldr	r3, [r7, #4]
+ 8021048:	695b      	ldr	r3, [r3, #20]
+ 802104a:	f103 0109 	add.w	r1, r3, #9
+					handler->pCurrentCANSendHadler->SendLength);
+ 802104e:	687b      	ldr	r3, [r7, #4]
+ 8021050:	695b      	ldr	r3, [r3, #20]
+ 8021052:	7a1b      	ldrb	r3, [r3, #8]
+			memcpy(handler->Tx_Buf, handler->pCurrentCANSendHadler->Tx_Buf,
+ 8021054:	461a      	mov	r2, r3
+ 8021056:	f01f f9b1 	bl	80403bc <memcpy>
+			handler->SendList_Period=handler->pCurrentCANSendHadler->SendListTimePeriod;
+ 802105a:	687b      	ldr	r3, [r7, #4]
+ 802105c:	695b      	ldr	r3, [r3, #20]
+ 802105e:	685a      	ldr	r2, [r3, #4]
+ 8021060:	687b      	ldr	r3, [r7, #4]
+ 8021062:	60da      	str	r2, [r3, #12]
+			handler->SendLength = handler->pCurrentCANSendHadler->SendLength;
+ 8021064:	687b      	ldr	r3, [r7, #4]
+ 8021066:	695b      	ldr	r3, [r3, #20]
+ 8021068:	7a1b      	ldrb	r3, [r3, #8]
+ 802106a:	461a      	mov	r2, r3
+ 802106c:	687b      	ldr	r3, [r7, #4]
+ 802106e:	f8c3 212c 	str.w	r2, [r3, #300]	@ 0x12c
+			handler->CAN_Send_Data(handler);
+ 8021072:	687b      	ldr	r3, [r7, #4]
+ 8021074:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 8021076:	6878      	ldr	r0, [r7, #4]
+ 8021078:	4798      	blx	r3
+
+			if (handler->pCurrentCANSendHadler->pNext != NULL)
+ 802107a:	687b      	ldr	r3, [r7, #4]
+ 802107c:	695b      	ldr	r3, [r3, #20]
+ 802107e:	699b      	ldr	r3, [r3, #24]
+ 8021080:	2b00      	cmp	r3, #0
+ 8021082:	d00c      	beq.n	802109e <GF_CAN_Send_List_Send+0xa6>
+			{
+				CANSendHandler *temp = handler->pCurrentCANSendHadler->pNext;
+ 8021084:	687b      	ldr	r3, [r7, #4]
+ 8021086:	695b      	ldr	r3, [r3, #20]
+ 8021088:	699b      	ldr	r3, [r3, #24]
+ 802108a:	60fb      	str	r3, [r7, #12]
+				free(handler->pCurrentCANSendHadler); //清除内存
+ 802108c:	687b      	ldr	r3, [r7, #4]
+ 802108e:	695b      	ldr	r3, [r3, #20]
+ 8021090:	4618      	mov	r0, r3
+ 8021092:	f01e ffa7 	bl	803ffe4 <free>
+				handler->pCurrentCANSendHadler = temp;
+ 8021096:	687b      	ldr	r3, [r7, #4]
+ 8021098:	68fa      	ldr	r2, [r7, #12]
+ 802109a:	615a      	str	r2, [r3, #20]
+
+		}
+
+	}
+
+}
+ 802109c:	e00b      	b.n	80210b6 <GF_CAN_Send_List_Send+0xbe>
+				free(handler->pCurrentCANSendHadler); //清除内存
+ 802109e:	687b      	ldr	r3, [r7, #4]
+ 80210a0:	695b      	ldr	r3, [r3, #20]
+ 80210a2:	4618      	mov	r0, r3
+ 80210a4:	f01e ff9e 	bl	803ffe4 <free>
+				handler->pCurrentCANSendHadler = NULL;
+ 80210a8:	687b      	ldr	r3, [r7, #4]
+ 80210aa:	2200      	movs	r2, #0
+ 80210ac:	615a      	str	r2, [r3, #20]
+}
+ 80210ae:	e002      	b.n	80210b6 <GF_CAN_Send_List_Send+0xbe>
+			handler->SendListExists = 0;
+ 80210b0:	687b      	ldr	r3, [r7, #4]
+ 80210b2:	2200      	movs	r2, #0
+ 80210b4:	725a      	strb	r2, [r3, #9]
+}
+ 80210b6:	bf00      	nop
+ 80210b8:	3710      	adds	r7, #16
+ 80210ba:	46bd      	mov	sp, r7
+ 80210bc:	bd80      	pop	{r7, pc}
+	...
+
+080210c0 <CAN_Send_t>:
+
+void CAN_Send_t(struct _FDCANHandler *fd, uint32_t FrameID, uint8_t DataLength,
+		uint8_t *Txdata)
+{
+ 80210c0:	b580      	push	{r7, lr}
+ 80210c2:	b084      	sub	sp, #16
+ 80210c4:	af00      	add	r7, sp, #0
+ 80210c6:	60f8      	str	r0, [r7, #12]
+ 80210c8:	60b9      	str	r1, [r7, #8]
+ 80210ca:	603b      	str	r3, [r7, #0]
+ 80210cc:	4613      	mov	r3, r2
+ 80210ce:	71fb      	strb	r3, [r7, #7]
+
+//	Function_code=Txdata[0];
+
+	if (DataLength > 8)
+ 80210d0:	79fb      	ldrb	r3, [r7, #7]
+ 80210d2:	2b08      	cmp	r3, #8
+ 80210d4:	d839      	bhi.n	802114a <CAN_Send_t+0x8a>
+	{
+		return;
+	}
+	if (fd->canfd == &hfdcan1)
+ 80210d6:	68fb      	ldr	r3, [r7, #12]
+ 80210d8:	681b      	ldr	r3, [r3, #0]
+ 80210da:	4a1e      	ldr	r2, [pc, #120]	@ (8021154 <CAN_Send_t+0x94>)
+ 80210dc:	4293      	cmp	r3, r2
+ 80210de:	d117      	bne.n	8021110 <CAN_Send_t+0x50>
+	{
+		TXHeader1.BitRateSwitch = FDCAN_BRS_OFF;
+ 80210e0:	4b1d      	ldr	r3, [pc, #116]	@ (8021158 <CAN_Send_t+0x98>)
+ 80210e2:	2200      	movs	r2, #0
+ 80210e4:	615a      	str	r2, [r3, #20]
+
+	#if NewCANSendVersion
+		TXHeader1.DataLength = (uint32_t) DataLength ;
+ 80210e6:	79fb      	ldrb	r3, [r7, #7]
+ 80210e8:	4a1b      	ldr	r2, [pc, #108]	@ (8021158 <CAN_Send_t+0x98>)
+ 80210ea:	60d3      	str	r3, [r2, #12]
+	#else
+		TXHeader1.DataLength = (uint32_t) DataLength << 16; //数据长度大于8的话会有错误
+	#endif
+
+
+		TXHeader1.FDFormat = FDCAN_CLASSIC_CAN;
+ 80210ec:	4b1a      	ldr	r3, [pc, #104]	@ (8021158 <CAN_Send_t+0x98>)
+ 80210ee:	2200      	movs	r2, #0
+ 80210f0:	619a      	str	r2, [r3, #24]
+		TXHeader1.IdType = FDCAN_STANDARD_ID;
+ 80210f2:	4b19      	ldr	r3, [pc, #100]	@ (8021158 <CAN_Send_t+0x98>)
+ 80210f4:	2200      	movs	r2, #0
+ 80210f6:	605a      	str	r2, [r3, #4]
+		TXHeader1.Identifier = FrameID;
+ 80210f8:	4a17      	ldr	r2, [pc, #92]	@ (8021158 <CAN_Send_t+0x98>)
+ 80210fa:	68bb      	ldr	r3, [r7, #8]
+ 80210fc:	6013      	str	r3, [r2, #0]
+		TXHeader1.TxFrameType = FDCAN_DATA_FRAME;
+ 80210fe:	4b16      	ldr	r3, [pc, #88]	@ (8021158 <CAN_Send_t+0x98>)
+ 8021100:	2200      	movs	r2, #0
+ 8021102:	609a      	str	r2, [r3, #8]
+		HAL_FDCAN_AddMessageToTxFifoQ(&hfdcan1, &TXHeader1, Txdata);
+ 8021104:	683a      	ldr	r2, [r7, #0]
+ 8021106:	4914      	ldr	r1, [pc, #80]	@ (8021158 <CAN_Send_t+0x98>)
+ 8021108:	4812      	ldr	r0, [pc, #72]	@ (8021154 <CAN_Send_t+0x94>)
+ 802110a:	f015 fb36 	bl	803677a <HAL_FDCAN_AddMessageToTxFifoQ>
+ 802110e:	e01d      	b.n	802114c <CAN_Send_t+0x8c>
+	} else if (fd->canfd == &hfdcan2)
+ 8021110:	68fb      	ldr	r3, [r7, #12]
+ 8021112:	681b      	ldr	r3, [r3, #0]
+ 8021114:	4a11      	ldr	r2, [pc, #68]	@ (802115c <CAN_Send_t+0x9c>)
+ 8021116:	4293      	cmp	r3, r2
+ 8021118:	d118      	bne.n	802114c <CAN_Send_t+0x8c>
+	{
+		TXHeader2.BitRateSwitch = FDCAN_BRS_OFF;
+ 802111a:	4b11      	ldr	r3, [pc, #68]	@ (8021160 <CAN_Send_t+0xa0>)
+ 802111c:	2200      	movs	r2, #0
+ 802111e:	615a      	str	r2, [r3, #20]
+
+	#if NewCANSendVersion
+			TXHeader2.DataLength = (uint32_t) DataLength ;
+ 8021120:	79fb      	ldrb	r3, [r7, #7]
+ 8021122:	4a0f      	ldr	r2, [pc, #60]	@ (8021160 <CAN_Send_t+0xa0>)
+ 8021124:	60d3      	str	r3, [r2, #12]
+		#else
+			TXHeader2.DataLength = (uint32_t) DataLength << 16; //数据长度大于8的话会有错误
+		#endif
+		//TXHeader2.DataLength = (uint32_t) DataLength << 16; //数据长度大于8的话会有错误
+		TXHeader2.FDFormat = FDCAN_CLASSIC_CAN;
+ 8021126:	4b0e      	ldr	r3, [pc, #56]	@ (8021160 <CAN_Send_t+0xa0>)
+ 8021128:	2200      	movs	r2, #0
+ 802112a:	619a      	str	r2, [r3, #24]
+		TXHeader2.IdType = FDCAN_STANDARD_ID;
+ 802112c:	4b0c      	ldr	r3, [pc, #48]	@ (8021160 <CAN_Send_t+0xa0>)
+ 802112e:	2200      	movs	r2, #0
+ 8021130:	605a      	str	r2, [r3, #4]
+		TXHeader2.Identifier = FrameID;
+ 8021132:	4a0b      	ldr	r2, [pc, #44]	@ (8021160 <CAN_Send_t+0xa0>)
+ 8021134:	68bb      	ldr	r3, [r7, #8]
+ 8021136:	6013      	str	r3, [r2, #0]
+		TXHeader2.TxFrameType = FDCAN_DATA_FRAME;
+ 8021138:	4b09      	ldr	r3, [pc, #36]	@ (8021160 <CAN_Send_t+0xa0>)
+ 802113a:	2200      	movs	r2, #0
+ 802113c:	609a      	str	r2, [r3, #8]
+		HAL_FDCAN_AddMessageToTxFifoQ(&hfdcan2, &TXHeader2, Txdata);
+ 802113e:	683a      	ldr	r2, [r7, #0]
+ 8021140:	4907      	ldr	r1, [pc, #28]	@ (8021160 <CAN_Send_t+0xa0>)
+ 8021142:	4806      	ldr	r0, [pc, #24]	@ (802115c <CAN_Send_t+0x9c>)
+ 8021144:	f015 fb19 	bl	803677a <HAL_FDCAN_AddMessageToTxFifoQ>
+ 8021148:	e000      	b.n	802114c <CAN_Send_t+0x8c>
+		return;
+ 802114a:	bf00      	nop
+	}
+}
+ 802114c:	3710      	adds	r7, #16
+ 802114e:	46bd      	mov	sp, r7
+ 8021150:	bd80      	pop	{r7, pc}
+ 8021152:	bf00      	nop
+ 8021154:	2400a578 	.word	0x2400a578
+ 8021158:	240008cc 	.word	0x240008cc
+ 802115c:	2400a618 	.word	0x2400a618
+ 8021160:	240008f0 	.word	0x240008f0
+
+08021164 <CAN_Send_Data_t>:
+
+void CAN_Send_Data_t(struct _FDCANHandler *fd)
+{
+ 8021164:	b580      	push	{r7, lr}
+ 8021166:	b082      	sub	sp, #8
+ 8021168:	af00      	add	r7, sp, #0
+ 802116a:	6078      	str	r0, [r7, #4]
+	CAN_Send_t(fd, fd->SendFrameID, fd->SendLength, fd->Tx_Buf);
+ 802116c:	687b      	ldr	r3, [r7, #4]
+ 802116e:	f8d3 1134 	ldr.w	r1, [r3, #308]	@ 0x134
+ 8021172:	687b      	ldr	r3, [r7, #4]
+ 8021174:	f8d3 312c 	ldr.w	r3, [r3, #300]	@ 0x12c
+ 8021178:	b2da      	uxtb	r2, r3
+ 802117a:	687b      	ldr	r3, [r7, #4]
+ 802117c:	33a8      	adds	r3, #168	@ 0xa8
+ 802117e:	6878      	ldr	r0, [r7, #4]
+ 8021180:	f7ff ff9e 	bl	80210c0 <CAN_Send_t>
+}
+ 8021184:	bf00      	nop
+ 8021186:	3708      	adds	r7, #8
+ 8021188:	46bd      	mov	sp, r7
+ 802118a:	bd80      	pop	{r7, pc}
+
+0802118c <CANHandlerAddTxList>:
+
+void CANHandlerAddTxList(FDCANHandler *handler, uint32_t CAN_ID,
+		uint8_t SendLength, uint8_t *Tx_Buf,uint32_t sendListTimePeriod,
+		void (*CAN_Decode)(uint32_t, uint8_t*, uint32_t))
+{
+ 802118c:	b580      	push	{r7, lr}
+ 802118e:	b088      	sub	sp, #32
+ 8021190:	af00      	add	r7, sp, #0
+ 8021192:	60f8      	str	r0, [r7, #12]
+ 8021194:	60b9      	str	r1, [r7, #8]
+ 8021196:	603b      	str	r3, [r7, #0]
+ 8021198:	4613      	mov	r3, r2
+ 802119a:	71fb      	strb	r3, [r7, #7]
+
+	CANSendHandler *pTmp = NULL; //临时指针
+ 802119c:	2300      	movs	r3, #0
+ 802119e:	617b      	str	r3, [r7, #20]
+
+	//临时指针2用于逐个申请内存
+	pTmp = (CANSendHandler*) malloc(sizeof(CANSendHandler));
+ 80211a0:	201c      	movs	r0, #28
+ 80211a2:	f01e ff17 	bl	803ffd4 <malloc>
+ 80211a6:	4603      	mov	r3, r0
+ 80211a8:	617b      	str	r3, [r7, #20]
+	memcpy(pTmp->Tx_Buf, Tx_Buf, SendLength);
+ 80211aa:	697b      	ldr	r3, [r7, #20]
+ 80211ac:	3309      	adds	r3, #9
+ 80211ae:	79fa      	ldrb	r2, [r7, #7]
+ 80211b0:	6839      	ldr	r1, [r7, #0]
+ 80211b2:	4618      	mov	r0, r3
+ 80211b4:	f01f f902 	bl	80403bc <memcpy>
+	pTmp->pNext = NULL;
+ 80211b8:	697b      	ldr	r3, [r7, #20]
+ 80211ba:	2200      	movs	r2, #0
+ 80211bc:	619a      	str	r2, [r3, #24]
+	pTmp->CAN_ID=CAN_ID;
+ 80211be:	697b      	ldr	r3, [r7, #20]
+ 80211c0:	68ba      	ldr	r2, [r7, #8]
+ 80211c2:	601a      	str	r2, [r3, #0]
+	pTmp->SendLength = SendLength;
+ 80211c4:	697b      	ldr	r3, [r7, #20]
+ 80211c6:	79fa      	ldrb	r2, [r7, #7]
+ 80211c8:	721a      	strb	r2, [r3, #8]
+	//pTmp->CAN_Decode = CAN_Decode;
+	pTmp->SendListTimePeriod=sendListTimePeriod;
+ 80211ca:	697b      	ldr	r3, [r7, #20]
+ 80211cc:	6aba      	ldr	r2, [r7, #40]	@ 0x28
+ 80211ce:	605a      	str	r2, [r3, #4]
+
+
+//if NULL, call intialize one
+	if (handler->pCurrentCANSendHadler == NULL)
+ 80211d0:	68fb      	ldr	r3, [r7, #12]
+ 80211d2:	695b      	ldr	r3, [r3, #20]
+ 80211d4:	2b00      	cmp	r3, #0
+ 80211d6:	d103      	bne.n	80211e0 <CANHandlerAddTxList+0x54>
+	{
+		handler->pCurrentCANSendHadler = pTmp; //空链表
+ 80211d8:	68fb      	ldr	r3, [r7, #12]
+ 80211da:	697a      	ldr	r2, [r7, #20]
+ 80211dc:	615a      	str	r2, [r3, #20]
+		}
+		phead->pNext = pTmp;
+
+	}
+
+}
+ 80211de:	e014      	b.n	802120a <CANHandlerAddTxList+0x7e>
+		char i = 0;
+ 80211e0:	2300      	movs	r3, #0
+ 80211e2:	77fb      	strb	r3, [r7, #31]
+		CANSendHandler *phead = NULL;
+ 80211e4:	2300      	movs	r3, #0
+ 80211e6:	61bb      	str	r3, [r7, #24]
+		phead = handler->pCurrentCANSendHadler;
+ 80211e8:	68fb      	ldr	r3, [r7, #12]
+ 80211ea:	695b      	ldr	r3, [r3, #20]
+ 80211ec:	61bb      	str	r3, [r7, #24]
+		while (phead->pNext != NULL)
+ 80211ee:	e005      	b.n	80211fc <CANHandlerAddTxList+0x70>
+			i++;
+ 80211f0:	7ffb      	ldrb	r3, [r7, #31]
+ 80211f2:	3301      	adds	r3, #1
+ 80211f4:	77fb      	strb	r3, [r7, #31]
+			phead = phead->pNext;
+ 80211f6:	69bb      	ldr	r3, [r7, #24]
+ 80211f8:	699b      	ldr	r3, [r3, #24]
+ 80211fa:	61bb      	str	r3, [r7, #24]
+		while (phead->pNext != NULL)
+ 80211fc:	69bb      	ldr	r3, [r7, #24]
+ 80211fe:	699b      	ldr	r3, [r3, #24]
+ 8021200:	2b00      	cmp	r3, #0
+ 8021202:	d1f5      	bne.n	80211f0 <CANHandlerAddTxList+0x64>
+		phead->pNext = pTmp;
+ 8021204:	69bb      	ldr	r3, [r7, #24]
+ 8021206:	697a      	ldr	r2, [r7, #20]
+ 8021208:	619a      	str	r2, [r3, #24]
+}
+ 802120a:	bf00      	nop
+ 802120c:	3720      	adds	r7, #32
+ 802120e:	46bd      	mov	sp, r7
+ 8021210:	bd80      	pop	{r7, pc}
+	...
+
+08021214 <GF_BSP_GPIO_SetIO>:
+
+	return 1;
+}
+
+void GF_BSP_GPIO_SetIO(uint8_t IO_Index,uint8_t Level)
+{
+ 8021214:	b580      	push	{r7, lr}
+ 8021216:	b084      	sub	sp, #16
+ 8021218:	af00      	add	r7, sp, #0
+ 802121a:	4603      	mov	r3, r0
+ 802121c:	460a      	mov	r2, r1
+ 802121e:	71fb      	strb	r3, [r7, #7]
+ 8021220:	4613      	mov	r3, r2
+ 8021222:	71bb      	strb	r3, [r7, #6]
+	GPIO_PinState PinState;
+	if(Level == 0)
+ 8021224:	79bb      	ldrb	r3, [r7, #6]
+ 8021226:	2b00      	cmp	r3, #0
+ 8021228:	d102      	bne.n	8021230 <GF_BSP_GPIO_SetIO+0x1c>
+		PinState=GPIO_PIN_RESET;
+ 802122a:	2300      	movs	r3, #0
+ 802122c:	73fb      	strb	r3, [r7, #15]
+ 802122e:	e001      	b.n	8021234 <GF_BSP_GPIO_SetIO+0x20>
+	else
+		PinState=GPIO_PIN_SET;
+ 8021230:	2301      	movs	r3, #1
+ 8021232:	73fb      	strb	r3, [r7, #15]
+
+	switch(IO_Index)
+ 8021234:	79fb      	ldrb	r3, [r7, #7]
+ 8021236:	2b05      	cmp	r3, #5
+ 8021238:	d850      	bhi.n	80212dc <GF_BSP_GPIO_SetIO+0xc8>
+ 802123a:	a201      	add	r2, pc, #4	@ (adr r2, 8021240 <GF_BSP_GPIO_SetIO+0x2c>)
+ 802123c:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 8021240:	08021259 	.word	0x08021259
+ 8021244:	0802126f 	.word	0x0802126f
+ 8021248:	08021285 	.word	0x08021285
+ 802124c:	0802129b 	.word	0x0802129b
+ 8021250:	080212b1 	.word	0x080212b1
+ 8021254:	080212c7 	.word	0x080212c7
+	{
+	case 0:
+		HAL_GPIO_WritePin(OUT_0_GPIO_Port, OUT_0_Pin, PinState);
+ 8021258:	7bfb      	ldrb	r3, [r7, #15]
+ 802125a:	461a      	mov	r2, r3
+ 802125c:	2104      	movs	r1, #4
+ 802125e:	4821      	ldr	r0, [pc, #132]	@ (80212e4 <GF_BSP_GPIO_SetIO+0xd0>)
+ 8021260:	f016 fb6c 	bl	803793c <HAL_GPIO_WritePin>
+		GV.IO.DO0=PinState;
+ 8021264:	7bfb      	ldrb	r3, [r7, #15]
+ 8021266:	4a20      	ldr	r2, [pc, #128]	@ (80212e8 <GF_BSP_GPIO_SetIO+0xd4>)
+ 8021268:	f8c2 31e4 	str.w	r3, [r2, #484]	@ 0x1e4
+		break;
+ 802126c:	e036      	b.n	80212dc <GF_BSP_GPIO_SetIO+0xc8>
+	case 1:
+		HAL_GPIO_WritePin(OUT_1_GPIO_Port, OUT_1_Pin, PinState);
+ 802126e:	7bfb      	ldrb	r3, [r7, #15]
+ 8021270:	461a      	mov	r2, r3
+ 8021272:	2108      	movs	r1, #8
+ 8021274:	481b      	ldr	r0, [pc, #108]	@ (80212e4 <GF_BSP_GPIO_SetIO+0xd0>)
+ 8021276:	f016 fb61 	bl	803793c <HAL_GPIO_WritePin>
+		GV.IO.DO1=PinState;
+ 802127a:	7bfb      	ldrb	r3, [r7, #15]
+ 802127c:	4a1a      	ldr	r2, [pc, #104]	@ (80212e8 <GF_BSP_GPIO_SetIO+0xd4>)
+ 802127e:	f8c2 31e8 	str.w	r3, [r2, #488]	@ 0x1e8
+		break;
+ 8021282:	e02b      	b.n	80212dc <GF_BSP_GPIO_SetIO+0xc8>
+	case 2:
+		HAL_GPIO_WritePin(OUT_2_GPIO_Port, OUT_2_Pin, PinState);
+ 8021284:	7bfb      	ldrb	r3, [r7, #15]
+ 8021286:	461a      	mov	r2, r3
+ 8021288:	2101      	movs	r1, #1
+ 802128a:	4818      	ldr	r0, [pc, #96]	@ (80212ec <GF_BSP_GPIO_SetIO+0xd8>)
+ 802128c:	f016 fb56 	bl	803793c <HAL_GPIO_WritePin>
+		GV.IO.DO2=PinState;
+ 8021290:	7bfb      	ldrb	r3, [r7, #15]
+ 8021292:	4a15      	ldr	r2, [pc, #84]	@ (80212e8 <GF_BSP_GPIO_SetIO+0xd4>)
+ 8021294:	f8c2 31ec 	str.w	r3, [r2, #492]	@ 0x1ec
+		break;
+ 8021298:	e020      	b.n	80212dc <GF_BSP_GPIO_SetIO+0xc8>
+	case 3:
+		HAL_GPIO_WritePin(OUT_3_GPIO_Port, OUT_3_Pin, PinState);
+ 802129a:	7bfb      	ldrb	r3, [r7, #15]
+ 802129c:	461a      	mov	r2, r3
+ 802129e:	2108      	movs	r1, #8
+ 80212a0:	4812      	ldr	r0, [pc, #72]	@ (80212ec <GF_BSP_GPIO_SetIO+0xd8>)
+ 80212a2:	f016 fb4b 	bl	803793c <HAL_GPIO_WritePin>
+		GV.IO.DO3=PinState;
+ 80212a6:	7bfb      	ldrb	r3, [r7, #15]
+ 80212a8:	4a0f      	ldr	r2, [pc, #60]	@ (80212e8 <GF_BSP_GPIO_SetIO+0xd4>)
+ 80212aa:	f8c2 31f0 	str.w	r3, [r2, #496]	@ 0x1f0
+		break;
+ 80212ae:	e015      	b.n	80212dc <GF_BSP_GPIO_SetIO+0xc8>
+	case 4:
+		HAL_GPIO_WritePin(OUT_4_GPIO_Port, OUT_4_Pin, PinState);
+ 80212b0:	7bfb      	ldrb	r3, [r7, #15]
+ 80212b2:	461a      	mov	r2, r3
+ 80212b4:	2110      	movs	r1, #16
+ 80212b6:	480d      	ldr	r0, [pc, #52]	@ (80212ec <GF_BSP_GPIO_SetIO+0xd8>)
+ 80212b8:	f016 fb40 	bl	803793c <HAL_GPIO_WritePin>
+		GV.IO.DO4=PinState;
+ 80212bc:	7bfb      	ldrb	r3, [r7, #15]
+ 80212be:	4a0a      	ldr	r2, [pc, #40]	@ (80212e8 <GF_BSP_GPIO_SetIO+0xd4>)
+ 80212c0:	f8c2 31f4 	str.w	r3, [r2, #500]	@ 0x1f4
+		break;
+ 80212c4:	e00a      	b.n	80212dc <GF_BSP_GPIO_SetIO+0xc8>
+	case 5:
+		HAL_GPIO_WritePin(OUT_5_GPIO_Port, OUT_5_Pin, PinState);
+ 80212c6:	7bfb      	ldrb	r3, [r7, #15]
+ 80212c8:	461a      	mov	r2, r3
+ 80212ca:	2120      	movs	r1, #32
+ 80212cc:	4807      	ldr	r0, [pc, #28]	@ (80212ec <GF_BSP_GPIO_SetIO+0xd8>)
+ 80212ce:	f016 fb35 	bl	803793c <HAL_GPIO_WritePin>
+		GV.IO.DO5=PinState;
+ 80212d2:	7bfb      	ldrb	r3, [r7, #15]
+ 80212d4:	4a04      	ldr	r2, [pc, #16]	@ (80212e8 <GF_BSP_GPIO_SetIO+0xd4>)
+ 80212d6:	f8c2 31f8 	str.w	r3, [r2, #504]	@ 0x1f8
+		break;
+ 80212da:	bf00      	nop
+	}
+}
+ 80212dc:	bf00      	nop
+ 80212de:	3710      	adds	r7, #16
+ 80212e0:	46bd      	mov	sp, r7
+ 80212e2:	bd80      	pop	{r7, pc}
+ 80212e4:	58020800 	.word	0x58020800
+ 80212e8:	24000340 	.word	0x24000340
+ 80212ec:	58020000 	.word	0x58020000
+
+080212f0 <GF_BSP_Interrupt_Add_CallBack>:
+SD_BSP_InterCall V_BSP_InterCall_Array[DF_BSP_InterCall_Type_Num] = {0};
+
+//给中断函数链接一个回调函数，直接添加空函数指针
+//返回值1表示添加成功，返回值0表示添加失败
+uint8_t GF_BSP_Interrupt_Add_CallBack(enum DF_BSP_InterCall_Type _type,void(*_fn)(void))
+{
+ 80212f0:	b480      	push	{r7}
+ 80212f2:	b083      	sub	sp, #12
+ 80212f4:	af00      	add	r7, sp, #0
+ 80212f6:	4603      	mov	r3, r0
+ 80212f8:	6039      	str	r1, [r7, #0]
+ 80212fa:	71fb      	strb	r3, [r7, #7]
+    V_BSP_InterCall_Array[_type].num++;
+ 80212fc:	79fb      	ldrb	r3, [r7, #7]
+ 80212fe:	491a      	ldr	r1, [pc, #104]	@ (8021368 <GF_BSP_Interrupt_Add_CallBack+0x78>)
+ 8021300:	2254      	movs	r2, #84	@ 0x54
+ 8021302:	fb03 f202 	mul.w	r2, r3, r2
+ 8021306:	440a      	add	r2, r1
+ 8021308:	7812      	ldrb	r2, [r2, #0]
+ 802130a:	3201      	adds	r2, #1
+ 802130c:	b2d0      	uxtb	r0, r2
+ 802130e:	4a16      	ldr	r2, [pc, #88]	@ (8021368 <GF_BSP_Interrupt_Add_CallBack+0x78>)
+ 8021310:	2154      	movs	r1, #84	@ 0x54
+ 8021312:	fb01 f303 	mul.w	r3, r1, r3
+ 8021316:	4413      	add	r3, r2
+ 8021318:	4602      	mov	r2, r0
+ 802131a:	701a      	strb	r2, [r3, #0]
+    if(V_BSP_InterCall_Array[_type].num>=DF_BSP_InterCall_Num)
+ 802131c:	79fb      	ldrb	r3, [r7, #7]
+ 802131e:	4a12      	ldr	r2, [pc, #72]	@ (8021368 <GF_BSP_Interrupt_Add_CallBack+0x78>)
+ 8021320:	2154      	movs	r1, #84	@ 0x54
+ 8021322:	fb01 f303 	mul.w	r3, r1, r3
+ 8021326:	4413      	add	r3, r2
+ 8021328:	781b      	ldrb	r3, [r3, #0]
+ 802132a:	2b13      	cmp	r3, #19
+ 802132c:	d901      	bls.n	8021332 <GF_BSP_Interrupt_Add_CallBack+0x42>
+    {
+    	return 0;
+ 802132e:	2300      	movs	r3, #0
+ 8021330:	e014      	b.n	802135c <GF_BSP_Interrupt_Add_CallBack+0x6c>
+    }
+    V_BSP_InterCall_Array[_type].fn[V_BSP_InterCall_Array[_type].num-1]=_fn;
+ 8021332:	79fa      	ldrb	r2, [r7, #7]
+ 8021334:	79fb      	ldrb	r3, [r7, #7]
+ 8021336:	490c      	ldr	r1, [pc, #48]	@ (8021368 <GF_BSP_Interrupt_Add_CallBack+0x78>)
+ 8021338:	2054      	movs	r0, #84	@ 0x54
+ 802133a:	fb00 f303 	mul.w	r3, r0, r3
+ 802133e:	440b      	add	r3, r1
+ 8021340:	781b      	ldrb	r3, [r3, #0]
+ 8021342:	1e59      	subs	r1, r3, #1
+ 8021344:	4808      	ldr	r0, [pc, #32]	@ (8021368 <GF_BSP_Interrupt_Add_CallBack+0x78>)
+ 8021346:	4613      	mov	r3, r2
+ 8021348:	005b      	lsls	r3, r3, #1
+ 802134a:	4413      	add	r3, r2
+ 802134c:	00da      	lsls	r2, r3, #3
+ 802134e:	1ad2      	subs	r2, r2, r3
+ 8021350:	1853      	adds	r3, r2, r1
+ 8021352:	009b      	lsls	r3, r3, #2
+ 8021354:	4403      	add	r3, r0
+ 8021356:	683a      	ldr	r2, [r7, #0]
+ 8021358:	605a      	str	r2, [r3, #4]
+    return 1;
+ 802135a:	2301      	movs	r3, #1
+}
+ 802135c:	4618      	mov	r0, r3
+ 802135e:	370c      	adds	r7, #12
+ 8021360:	46bd      	mov	sp, r7
+ 8021362:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8021366:	4770      	bx	lr
+ 8021368:	24000918 	.word	0x24000918
+
+0802136c <GF_BSP_Interrupt_Run_CallBack>:
+
+//放到中断函数中，运行相应的回调函数，有几个运行几个
+void GF_BSP_Interrupt_Run_CallBack(enum DF_BSP_InterCall_Type _type)
+{
+ 802136c:	b580      	push	{r7, lr}
+ 802136e:	b084      	sub	sp, #16
+ 8021370:	af00      	add	r7, sp, #0
+ 8021372:	4603      	mov	r3, r0
+ 8021374:	71fb      	strb	r3, [r7, #7]
+    uint8_t i=0;
+ 8021376:	2300      	movs	r3, #0
+ 8021378:	73fb      	strb	r3, [r7, #15]
+    if(V_BSP_InterCall_Array[_type].num>0)
+ 802137a:	79fb      	ldrb	r3, [r7, #7]
+ 802137c:	4a14      	ldr	r2, [pc, #80]	@ (80213d0 <GF_BSP_Interrupt_Run_CallBack+0x64>)
+ 802137e:	2154      	movs	r1, #84	@ 0x54
+ 8021380:	fb01 f303 	mul.w	r3, r1, r3
+ 8021384:	4413      	add	r3, r2
+ 8021386:	781b      	ldrb	r3, [r3, #0]
+ 8021388:	2b00      	cmp	r3, #0
+ 802138a:	d01c      	beq.n	80213c6 <GF_BSP_Interrupt_Run_CallBack+0x5a>
+    {
+        for(i=0;i<V_BSP_InterCall_Array[_type].num;i++)
+ 802138c:	2300      	movs	r3, #0
+ 802138e:	73fb      	strb	r3, [r7, #15]
+ 8021390:	e00f      	b.n	80213b2 <GF_BSP_Interrupt_Run_CallBack+0x46>
+        {
+            (*(V_BSP_InterCall_Array[_type].fn[i]))();
+ 8021392:	79fa      	ldrb	r2, [r7, #7]
+ 8021394:	7bf9      	ldrb	r1, [r7, #15]
+ 8021396:	480e      	ldr	r0, [pc, #56]	@ (80213d0 <GF_BSP_Interrupt_Run_CallBack+0x64>)
+ 8021398:	4613      	mov	r3, r2
+ 802139a:	005b      	lsls	r3, r3, #1
+ 802139c:	4413      	add	r3, r2
+ 802139e:	00da      	lsls	r2, r3, #3
+ 80213a0:	1ad2      	subs	r2, r2, r3
+ 80213a2:	1853      	adds	r3, r2, r1
+ 80213a4:	009b      	lsls	r3, r3, #2
+ 80213a6:	4403      	add	r3, r0
+ 80213a8:	685b      	ldr	r3, [r3, #4]
+ 80213aa:	4798      	blx	r3
+        for(i=0;i<V_BSP_InterCall_Array[_type].num;i++)
+ 80213ac:	7bfb      	ldrb	r3, [r7, #15]
+ 80213ae:	3301      	adds	r3, #1
+ 80213b0:	73fb      	strb	r3, [r7, #15]
+ 80213b2:	79fb      	ldrb	r3, [r7, #7]
+ 80213b4:	4a06      	ldr	r2, [pc, #24]	@ (80213d0 <GF_BSP_Interrupt_Run_CallBack+0x64>)
+ 80213b6:	2154      	movs	r1, #84	@ 0x54
+ 80213b8:	fb01 f303 	mul.w	r3, r1, r3
+ 80213bc:	4413      	add	r3, r2
+ 80213be:	781b      	ldrb	r3, [r3, #0]
+ 80213c0:	7bfa      	ldrb	r2, [r7, #15]
+ 80213c2:	429a      	cmp	r2, r3
+ 80213c4:	d3e5      	bcc.n	8021392 <GF_BSP_Interrupt_Run_CallBack+0x26>
+        }
+    }
+}
+ 80213c6:	bf00      	nop
+ 80213c8:	3710      	adds	r7, #16
+ 80213ca:	46bd      	mov	sp, r7
+ 80213cc:	bd80      	pop	{r7, pc}
+ 80213ce:	bf00      	nop
+ 80213d0:	24000918 	.word	0x24000918
+
+080213d4 <MB_CRC16>:
+ * 输入参数: pushMsg:待计算的数据首地址,usDataLen:数据长度
+ * 返 回 值: CRC16 计算结果
+ * 说    明: 计算结果是高位在前,需要转换才能发送
+ */
+uint16_t MB_CRC16(uint8_t *pushMsg, uint16_t usDataLen)
+{
+ 80213d4:	b480      	push	{r7}
+ 80213d6:	b085      	sub	sp, #20
+ 80213d8:	af00      	add	r7, sp, #0
+ 80213da:	6078      	str	r0, [r7, #4]
+ 80213dc:	460b      	mov	r3, r1
+ 80213de:	807b      	strh	r3, [r7, #2]
+	uint8_t uchCRCHi = 0xFF;
+ 80213e0:	23ff      	movs	r3, #255	@ 0xff
+ 80213e2:	73fb      	strb	r3, [r7, #15]
+	uint8_t uchCRCLo = 0xFF;
+ 80213e4:	23ff      	movs	r3, #255	@ 0xff
+ 80213e6:	73bb      	strb	r3, [r7, #14]
+	uint16_t uIndex;
+	while (usDataLen--)
+ 80213e8:	e011      	b.n	802140e <MB_CRC16+0x3a>
+	{
+		uIndex = uchCRCLo ^ *pushMsg++;
+ 80213ea:	687b      	ldr	r3, [r7, #4]
+ 80213ec:	1c5a      	adds	r2, r3, #1
+ 80213ee:	607a      	str	r2, [r7, #4]
+ 80213f0:	781a      	ldrb	r2, [r3, #0]
+ 80213f2:	7bbb      	ldrb	r3, [r7, #14]
+ 80213f4:	4053      	eors	r3, r2
+ 80213f6:	b2db      	uxtb	r3, r3
+ 80213f8:	81bb      	strh	r3, [r7, #12]
+		uchCRCLo = uchCRCHi ^ auchCRCHi[uIndex];
+ 80213fa:	89bb      	ldrh	r3, [r7, #12]
+ 80213fc:	4a0d      	ldr	r2, [pc, #52]	@ (8021434 <MB_CRC16+0x60>)
+ 80213fe:	5cd2      	ldrb	r2, [r2, r3]
+ 8021400:	7bfb      	ldrb	r3, [r7, #15]
+ 8021402:	4053      	eors	r3, r2
+ 8021404:	73bb      	strb	r3, [r7, #14]
+		uchCRCHi = auchCRCLo[uIndex];
+ 8021406:	89bb      	ldrh	r3, [r7, #12]
+ 8021408:	4a0b      	ldr	r2, [pc, #44]	@ (8021438 <MB_CRC16+0x64>)
+ 802140a:	5cd3      	ldrb	r3, [r2, r3]
+ 802140c:	73fb      	strb	r3, [r7, #15]
+	while (usDataLen--)
+ 802140e:	887b      	ldrh	r3, [r7, #2]
+ 8021410:	1e5a      	subs	r2, r3, #1
+ 8021412:	807a      	strh	r2, [r7, #2]
+ 8021414:	2b00      	cmp	r3, #0
+ 8021416:	d1e8      	bne.n	80213ea <MB_CRC16+0x16>
+	}
+	return (uchCRCHi << 8 | uchCRCLo);
+ 8021418:	7bfb      	ldrb	r3, [r7, #15]
+ 802141a:	021b      	lsls	r3, r3, #8
+ 802141c:	b21a      	sxth	r2, r3
+ 802141e:	7bbb      	ldrb	r3, [r7, #14]
+ 8021420:	b21b      	sxth	r3, r3
+ 8021422:	4313      	orrs	r3, r2
+ 8021424:	b21b      	sxth	r3, r3
+ 8021426:	b29b      	uxth	r3, r3
+}
+ 8021428:	4618      	mov	r0, r3
+ 802142a:	3714      	adds	r7, #20
+ 802142c:	46bd      	mov	sp, r7
+ 802142e:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8021432:	4770      	bx	lr
+ 8021434:	080419d4 	.word	0x080419d4
+ 8021438:	08041ad4 	.word	0x08041ad4
+
+0802143c <GF_BSP_TIMER_Init>:
+#include "BSP/bsp_TIMER.h"
+
+
+//返回值：：1-正常；0-错误
+uint8_t GF_BSP_TIMER_Init()
+{
+ 802143c:	b580      	push	{r7, lr}
+ 802143e:	af00      	add	r7, sp, #0
+    HAL_TIM_Base_Start_IT(&htim1);
+ 8021440:	4804      	ldr	r0, [pc, #16]	@ (8021454 <GF_BSP_TIMER_Init+0x18>)
+ 8021442:	f01b fb75 	bl	803cb30 <HAL_TIM_Base_Start_IT>
+	HAL_TIM_Base_Start_IT(&htim8);
+ 8021446:	4804      	ldr	r0, [pc, #16]	@ (8021458 <GF_BSP_TIMER_Init+0x1c>)
+ 8021448:	f01b fb72 	bl	803cb30 <HAL_TIM_Base_Start_IT>
+    return 1;
+ 802144c:	2301      	movs	r3, #1
+}
+ 802144e:	4618      	mov	r0, r3
+ 8021450:	bd80      	pop	{r7, pc}
+ 8021452:	bf00      	nop
+ 8021454:	2400a9f8 	.word	0x2400a9f8
+ 8021458:	2400aa44 	.word	0x2400aa44
+
+0802145c <HAL_TIM_PeriodElapsedCallback>:
+
+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
+{
+ 802145c:	b580      	push	{r7, lr}
+ 802145e:	b082      	sub	sp, #8
+ 8021460:	af00      	add	r7, sp, #0
+ 8021462:	6078      	str	r0, [r7, #4]
+	//100ms - WatchDog
+	if(htim->Instance == TIM1)//APB2=200Mhz,htim1.Init.Prescaler = 2000-1;htim1.Init.Period = 10000-1;  TIM1=100ms
+ 8021464:	687b      	ldr	r3, [r7, #4]
+ 8021466:	681b      	ldr	r3, [r3, #0]
+ 8021468:	4a08      	ldr	r2, [pc, #32]	@ (802148c <HAL_TIM_PeriodElapsedCallback+0x30>)
+ 802146a:	4293      	cmp	r3, r2
+ 802146c:	d102      	bne.n	8021474 <HAL_TIM_PeriodElapsedCallback+0x18>
+	{
+		GF_BSP_Interrupt_Run_CallBack(DF_BSP_InterCall_TIM1_100ms_PeriodElapsedCallback);
+ 802146e:	2009      	movs	r0, #9
+ 8021470:	f7ff ff7c 	bl	802136c <GF_BSP_Interrupt_Run_CallBack>
+
+	}
+	//2ms - MainLoop
+	if(htim->Instance == TIM8)//APB2=200Mhz,htim8.Init.Prescaler = 2000-1;htim8.Init.Period = 200-1;  TIM8=2ms
+ 8021474:	687b      	ldr	r3, [r7, #4]
+ 8021476:	681b      	ldr	r3, [r3, #0]
+ 8021478:	4a05      	ldr	r2, [pc, #20]	@ (8021490 <HAL_TIM_PeriodElapsedCallback+0x34>)
+ 802147a:	4293      	cmp	r3, r2
+ 802147c:	d102      	bne.n	8021484 <HAL_TIM_PeriodElapsedCallback+0x28>
+	{
+		GF_BSP_Interrupt_Run_CallBack(DF_BSP_InterCall_TIM8_2ms_PeriodElapsedCallback);
+ 802147e:	200a      	movs	r0, #10
+ 8021480:	f7ff ff74 	bl	802136c <GF_BSP_Interrupt_Run_CallBack>
+		//bsp_mqtt_test();
+	}
+}
+ 8021484:	bf00      	nop
+ 8021486:	3708      	adds	r7, #8
+ 8021488:	46bd      	mov	sp, r7
+ 802148a:	bd80      	pop	{r7, pc}
+ 802148c:	40010000 	.word	0x40010000
+ 8021490:	40010400 	.word	0x40010400
+
+08021494 <GF_BSP_TIMER_DelayUS>:
+
+void GF_BSP_TIMER_DelayUS(uint32_t n)
+{
+ 8021494:	b480      	push	{r7}
+ 8021496:	b089      	sub	sp, #36	@ 0x24
+ 8021498:	af00      	add	r7, sp, #0
+ 802149a:	6078      	str	r0, [r7, #4]
+    uint32_t ticks;
+    uint32_t told;
+    uint32_t tnow;
+    uint32_t tcnt = 0;
+ 802149c:	2300      	movs	r3, #0
+ 802149e:	61bb      	str	r3, [r7, #24]
+    uint32_t reload;
+
+	reload = SysTick->LOAD;
+ 80214a0:	4b1c      	ldr	r3, [pc, #112]	@ (8021514 <GF_BSP_TIMER_DelayUS+0x80>)
+ 80214a2:	685b      	ldr	r3, [r3, #4]
+ 80214a4:	617b      	str	r3, [r7, #20]
+    ticks = n * (SystemCoreClock / 1000000);
+ 80214a6:	4b1c      	ldr	r3, [pc, #112]	@ (8021518 <GF_BSP_TIMER_DelayUS+0x84>)
+ 80214a8:	681b      	ldr	r3, [r3, #0]
+ 80214aa:	4a1c      	ldr	r2, [pc, #112]	@ (802151c <GF_BSP_TIMER_DelayUS+0x88>)
+ 80214ac:	fba2 2303 	umull	r2, r3, r2, r3
+ 80214b0:	0c9a      	lsrs	r2, r3, #18
+ 80214b2:	687b      	ldr	r3, [r7, #4]
+ 80214b4:	fb02 f303 	mul.w	r3, r2, r3
+ 80214b8:	613b      	str	r3, [r7, #16]
+
+    tcnt = 0;
+ 80214ba:	2300      	movs	r3, #0
+ 80214bc:	61bb      	str	r3, [r7, #24]
+    told = SysTick->VAL;
+ 80214be:	4b15      	ldr	r3, [pc, #84]	@ (8021514 <GF_BSP_TIMER_DelayUS+0x80>)
+ 80214c0:	689b      	ldr	r3, [r3, #8]
+ 80214c2:	61fb      	str	r3, [r7, #28]
+
+    while (1)
+    {
+        tnow = SysTick->VAL;
+ 80214c4:	4b13      	ldr	r3, [pc, #76]	@ (8021514 <GF_BSP_TIMER_DelayUS+0x80>)
+ 80214c6:	689b      	ldr	r3, [r3, #8]
+ 80214c8:	60fb      	str	r3, [r7, #12]
+        if (tnow != told)
+ 80214ca:	68fa      	ldr	r2, [r7, #12]
+ 80214cc:	69fb      	ldr	r3, [r7, #28]
+ 80214ce:	429a      	cmp	r2, r3
+ 80214d0:	d0f8      	beq.n	80214c4 <GF_BSP_TIMER_DelayUS+0x30>
+        {
+            if (tnow < told)
+ 80214d2:	68fa      	ldr	r2, [r7, #12]
+ 80214d4:	69fb      	ldr	r3, [r7, #28]
+ 80214d6:	429a      	cmp	r2, r3
+ 80214d8:	d206      	bcs.n	80214e8 <GF_BSP_TIMER_DelayUS+0x54>
+            {
+                tcnt += told - tnow;
+ 80214da:	69fa      	ldr	r2, [r7, #28]
+ 80214dc:	68fb      	ldr	r3, [r7, #12]
+ 80214de:	1ad3      	subs	r3, r2, r3
+ 80214e0:	69ba      	ldr	r2, [r7, #24]
+ 80214e2:	4413      	add	r3, r2
+ 80214e4:	61bb      	str	r3, [r7, #24]
+ 80214e6:	e007      	b.n	80214f8 <GF_BSP_TIMER_DelayUS+0x64>
+            }
+            else
+            {
+                tcnt += reload - tnow + told;
+ 80214e8:	697a      	ldr	r2, [r7, #20]
+ 80214ea:	68fb      	ldr	r3, [r7, #12]
+ 80214ec:	1ad2      	subs	r2, r2, r3
+ 80214ee:	69fb      	ldr	r3, [r7, #28]
+ 80214f0:	4413      	add	r3, r2
+ 80214f2:	69ba      	ldr	r2, [r7, #24]
+ 80214f4:	4413      	add	r3, r2
+ 80214f6:	61bb      	str	r3, [r7, #24]
+            }
+            told = tnow;
+ 80214f8:	68fb      	ldr	r3, [r7, #12]
+ 80214fa:	61fb      	str	r3, [r7, #28]
+            if (tcnt >= ticks)
+ 80214fc:	69ba      	ldr	r2, [r7, #24]
+ 80214fe:	693b      	ldr	r3, [r7, #16]
+ 8021500:	429a      	cmp	r2, r3
+ 8021502:	d200      	bcs.n	8021506 <GF_BSP_TIMER_DelayUS+0x72>
+        tnow = SysTick->VAL;
+ 8021504:	e7de      	b.n	80214c4 <GF_BSP_TIMER_DelayUS+0x30>
+            {
+            	break;
+ 8021506:	bf00      	nop
+            }
+        }
+    }
+}
+ 8021508:	bf00      	nop
+ 802150a:	3724      	adds	r7, #36	@ 0x24
+ 802150c:	46bd      	mov	sp, r7
+ 802150e:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8021512:	4770      	bx	lr
+ 8021514:	e000e010 	.word	0xe000e010
+ 8021518:	2400012c 	.word	0x2400012c
+ 802151c:	431bde83 	.word	0x431bde83
+
+08021520 <GF_BSP_UARTHandlers_Intialize>:
+		int32_t LTE_7S0_Serial_Dispacher_Time,
+		int32_t InterCall_DEBUG_Dispacher_Time,
+		int32_t E28_SBUS_Dispacher_Time,
+		int32_t LPUART1_UART_Dispacher_Time
+)
+{
+ 8021520:	b580      	push	{r7, lr}
+ 8021522:	b086      	sub	sp, #24
+ 8021524:	af02      	add	r7, sp, #8
+ 8021526:	60f8      	str	r0, [r7, #12]
+ 8021528:	60b9      	str	r1, [r7, #8]
+ 802152a:	607a      	str	r2, [r7, #4]
+ 802152c:	603b      	str	r3, [r7, #0]
+
+	IntializeUARTHandler(&RS_485_1_UART_Handler, &RS485_1_UART, RS485_1_WaitTime, 2,RS485_1_Dispacher_Time);
+ 802152e:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 8021530:	9300      	str	r3, [sp, #0]
+ 8021532:	2302      	movs	r3, #2
+ 8021534:	68fa      	ldr	r2, [r7, #12]
+ 8021536:	493e      	ldr	r1, [pc, #248]	@ (8021630 <GF_BSP_UARTHandlers_Intialize+0x110>)
+ 8021538:	483e      	ldr	r0, [pc, #248]	@ (8021634 <GF_BSP_UARTHandlers_Intialize+0x114>)
+ 802153a:	f000 fa7f 	bl	8021a3c <IntializeUARTHandler>
+	IntializeUARTHandler(&RS_485_2_UART_Handler, &RS485_2_UART, RS485_2_WaitTime, 2,RS485_2_Dispacher_Time);
+ 802153e:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
+ 8021540:	9300      	str	r3, [sp, #0]
+ 8021542:	2302      	movs	r3, #2
+ 8021544:	68ba      	ldr	r2, [r7, #8]
+ 8021546:	493c      	ldr	r1, [pc, #240]	@ (8021638 <GF_BSP_UARTHandlers_Intialize+0x118>)
+ 8021548:	483c      	ldr	r0, [pc, #240]	@ (802163c <GF_BSP_UARTHandlers_Intialize+0x11c>)
+ 802154a:	f000 fa77 	bl	8021a3c <IntializeUARTHandler>
+	IntializeUARTHandler(&RS_485_3_UART_Handler, &RS485_3_UART, RS485_3_WaitTime, 2,RS485_3_Dispacher_Time);
+ 802154e:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
+ 8021550:	9300      	str	r3, [sp, #0]
+ 8021552:	2302      	movs	r3, #2
+ 8021554:	687a      	ldr	r2, [r7, #4]
+ 8021556:	493a      	ldr	r1, [pc, #232]	@ (8021640 <GF_BSP_UARTHandlers_Intialize+0x120>)
+ 8021558:	483a      	ldr	r0, [pc, #232]	@ (8021644 <GF_BSP_UARTHandlers_Intialize+0x124>)
+ 802155a:	f000 fa6f 	bl	8021a3c <IntializeUARTHandler>
+	IntializeUARTHandler(&RS_485_4_UART_Handler, &RS485_4_UART, RS485_4_WaitTime, 2,RS485_4_Dispacher_Time);
+ 802155e:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
+ 8021560:	9300      	str	r3, [sp, #0]
+ 8021562:	2302      	movs	r3, #2
+ 8021564:	683a      	ldr	r2, [r7, #0]
+ 8021566:	4938      	ldr	r1, [pc, #224]	@ (8021648 <GF_BSP_UARTHandlers_Intialize+0x128>)
+ 8021568:	4838      	ldr	r0, [pc, #224]	@ (802164c <GF_BSP_UARTHandlers_Intialize+0x12c>)
+ 802156a:	f000 fa67 	bl	8021a3c <IntializeUARTHandler>
+	IntializeUARTHandler(&LTE_7S0_Serial_UART_Handler, &LTE_7S0_Serial_UART, LTE_7S0_Serial_WaitTime, 2,LTE_7S0_Serial_Dispacher_Time);
+ 802156e:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 8021570:	9300      	str	r3, [sp, #0]
+ 8021572:	2302      	movs	r3, #2
+ 8021574:	69ba      	ldr	r2, [r7, #24]
+ 8021576:	4936      	ldr	r1, [pc, #216]	@ (8021650 <GF_BSP_UARTHandlers_Intialize+0x130>)
+ 8021578:	4836      	ldr	r0, [pc, #216]	@ (8021654 <GF_BSP_UARTHandlers_Intialize+0x134>)
+ 802157a:	f000 fa5f 	bl	8021a3c <IntializeUARTHandler>
+	IntializeUARTHandler(&InterCall_DEBUG_UART_Handler, &InterCall_DEBUG_UART, InterCall_DEBUG_WaitTime, 2,InterCall_DEBUG_Dispacher_Time);
+ 802157e:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
+ 8021580:	9300      	str	r3, [sp, #0]
+ 8021582:	2302      	movs	r3, #2
+ 8021584:	69fa      	ldr	r2, [r7, #28]
+ 8021586:	4934      	ldr	r1, [pc, #208]	@ (8021658 <GF_BSP_UARTHandlers_Intialize+0x138>)
+ 8021588:	4834      	ldr	r0, [pc, #208]	@ (802165c <GF_BSP_UARTHandlers_Intialize+0x13c>)
+ 802158a:	f000 fa57 	bl	8021a3c <IntializeUARTHandler>
+	IntializeUARTHandler(&E28_SBUS_UART_Handler, &E28_SBUS_UART, E28_SBUS_WaitTime, 2,E28_SBUS_Dispacher_Time);
+ 802158e:	6c3b      	ldr	r3, [r7, #64]	@ 0x40
+ 8021590:	9300      	str	r3, [sp, #0]
+ 8021592:	2302      	movs	r3, #2
+ 8021594:	6a3a      	ldr	r2, [r7, #32]
+ 8021596:	4932      	ldr	r1, [pc, #200]	@ (8021660 <GF_BSP_UARTHandlers_Intialize+0x140>)
+ 8021598:	4832      	ldr	r0, [pc, #200]	@ (8021664 <GF_BSP_UARTHandlers_Intialize+0x144>)
+ 802159a:	f000 fa4f 	bl	8021a3c <IntializeUARTHandler>
+
+
+	HAL_UART_Receive_IT((E28_SBUS_UART_Handler.uart),
+ 802159e:	4b31      	ldr	r3, [pc, #196]	@ (8021664 <GF_BSP_UARTHandlers_Intialize+0x144>)
+ 80215a0:	69db      	ldr	r3, [r3, #28]
+ 80215a2:	2201      	movs	r2, #1
+ 80215a4:	4930      	ldr	r1, [pc, #192]	@ (8021668 <GF_BSP_UARTHandlers_Intialize+0x148>)
+ 80215a6:	4618      	mov	r0, r3
+ 80215a8:	f01c f830 	bl	803d60c <HAL_UART_Receive_IT>
+				(uint8_t*) &E28_SBUS_UART_Handler.tmp_Rx_Buf, 1);
+
+
+	HAL_UART_Receive_IT((InterCall_DEBUG_UART_Handler.uart),
+ 80215ac:	4b2b      	ldr	r3, [pc, #172]	@ (802165c <GF_BSP_UARTHandlers_Intialize+0x13c>)
+ 80215ae:	69db      	ldr	r3, [r3, #28]
+ 80215b0:	2201      	movs	r2, #1
+ 80215b2:	492e      	ldr	r1, [pc, #184]	@ (802166c <GF_BSP_UARTHandlers_Intialize+0x14c>)
+ 80215b4:	4618      	mov	r0, r3
+ 80215b6:	f01c f829 	bl	803d60c <HAL_UART_Receive_IT>
+			(uint8_t*) &InterCall_DEBUG_UART_Handler.tmp_Rx_Buf, 1);
+	HAL_UART_Receive_IT((RS_485_1_UART_Handler.uart),
+ 80215ba:	4b1e      	ldr	r3, [pc, #120]	@ (8021634 <GF_BSP_UARTHandlers_Intialize+0x114>)
+ 80215bc:	69db      	ldr	r3, [r3, #28]
+ 80215be:	2201      	movs	r2, #1
+ 80215c0:	492b      	ldr	r1, [pc, #172]	@ (8021670 <GF_BSP_UARTHandlers_Intialize+0x150>)
+ 80215c2:	4618      	mov	r0, r3
+ 80215c4:	f01c f822 	bl	803d60c <HAL_UART_Receive_IT>
+			(uint8_t*) &RS_485_1_UART_Handler.tmp_Rx_Buf, 1);
+
+	HAL_UART_Receive_IT((RS_485_2_UART_Handler.uart),
+ 80215c8:	4b1c      	ldr	r3, [pc, #112]	@ (802163c <GF_BSP_UARTHandlers_Intialize+0x11c>)
+ 80215ca:	69db      	ldr	r3, [r3, #28]
+ 80215cc:	2201      	movs	r2, #1
+ 80215ce:	4929      	ldr	r1, [pc, #164]	@ (8021674 <GF_BSP_UARTHandlers_Intialize+0x154>)
+ 80215d0:	4618      	mov	r0, r3
+ 80215d2:	f01c f81b 	bl	803d60c <HAL_UART_Receive_IT>
+			(uint8_t*) &RS_485_2_UART_Handler.tmp_Rx_Buf, 1);
+
+	HAL_UART_Receive_IT((RS_485_3_UART_Handler.uart),
+ 80215d6:	4b1b      	ldr	r3, [pc, #108]	@ (8021644 <GF_BSP_UARTHandlers_Intialize+0x124>)
+ 80215d8:	69db      	ldr	r3, [r3, #28]
+ 80215da:	2201      	movs	r2, #1
+ 80215dc:	4926      	ldr	r1, [pc, #152]	@ (8021678 <GF_BSP_UARTHandlers_Intialize+0x158>)
+ 80215de:	4618      	mov	r0, r3
+ 80215e0:	f01c f814 	bl	803d60c <HAL_UART_Receive_IT>
+			(uint8_t*) &RS_485_3_UART_Handler.tmp_Rx_Buf, 1);
+
+	HAL_UART_Receive_IT((RS_485_4_UART_Handler.uart),
+ 80215e4:	4b19      	ldr	r3, [pc, #100]	@ (802164c <GF_BSP_UARTHandlers_Intialize+0x12c>)
+ 80215e6:	69db      	ldr	r3, [r3, #28]
+ 80215e8:	2201      	movs	r2, #1
+ 80215ea:	4924      	ldr	r1, [pc, #144]	@ (802167c <GF_BSP_UARTHandlers_Intialize+0x15c>)
+ 80215ec:	4618      	mov	r0, r3
+ 80215ee:	f01c f80d 	bl	803d60c <HAL_UART_Receive_IT>
+			(uint8_t*) &RS_485_4_UART_Handler.tmp_Rx_Buf, 1);
+
+	HAL_UART_Receive_IT((LTE_7S0_Serial_UART_Handler.uart),
+ 80215f2:	4b18      	ldr	r3, [pc, #96]	@ (8021654 <GF_BSP_UARTHandlers_Intialize+0x134>)
+ 80215f4:	69db      	ldr	r3, [r3, #28]
+ 80215f6:	2201      	movs	r2, #1
+ 80215f8:	4921      	ldr	r1, [pc, #132]	@ (8021680 <GF_BSP_UARTHandlers_Intialize+0x160>)
+ 80215fa:	4618      	mov	r0, r3
+ 80215fc:	f01c f806 	bl	803d60c <HAL_UART_Receive_IT>
+
+
+
+
+#if defined (hlpuart1Exit)
+	IntializeUARTHandler(&LPUART1_UART_Handler, &LPUART1UART, LPUART1_UART_WaitTime, 2,LPUART1_UART_Dispacher_Time); //10ms 剩余2ms
+ 8021600:	6c7b      	ldr	r3, [r7, #68]	@ 0x44
+ 8021602:	9300      	str	r3, [sp, #0]
+ 8021604:	2302      	movs	r3, #2
+ 8021606:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
+ 8021608:	491e      	ldr	r1, [pc, #120]	@ (8021684 <GF_BSP_UARTHandlers_Intialize+0x164>)
+ 802160a:	481f      	ldr	r0, [pc, #124]	@ (8021688 <GF_BSP_UARTHandlers_Intialize+0x168>)
+ 802160c:	f000 fa16 	bl	8021a3c <IntializeUARTHandler>
+	HAL_UART_Receive_IT((LPUART1_UART_Handler.uart),
+ 8021610:	4b1d      	ldr	r3, [pc, #116]	@ (8021688 <GF_BSP_UARTHandlers_Intialize+0x168>)
+ 8021612:	69db      	ldr	r3, [r3, #28]
+ 8021614:	2201      	movs	r2, #1
+ 8021616:	491d      	ldr	r1, [pc, #116]	@ (802168c <GF_BSP_UARTHandlers_Intialize+0x16c>)
+ 8021618:	4618      	mov	r0, r3
+ 802161a:	f01b fff7 	bl	803d60c <HAL_UART_Receive_IT>
+#endif
+
+
+
+
+	GF_BSP_Interrupt_Add_CallBack(
+ 802161e:	491c      	ldr	r1, [pc, #112]	@ (8021690 <GF_BSP_UARTHandlers_Intialize+0x170>)
+ 8021620:	200a      	movs	r0, #10
+ 8021622:	f7ff fe65 	bl	80212f0 <GF_BSP_Interrupt_Add_CallBack>
+			DF_BSP_InterCall_TIM8_2ms_PeriodElapsedCallback, GF_BSP_UART_Timer);
+
+	//RS_485_2_UART_Handler.send_finished=1;
+}
+ 8021626:	bf00      	nop
+ 8021628:	3710      	adds	r7, #16
+ 802162a:	46bd      	mov	sp, r7
+ 802162c:	bd80      	pop	{r7, pc}
+ 802162e:	bf00      	nop
+ 8021630:	2400ace0 	.word	0x2400ace0
+ 8021634:	24000cb4 	.word	0x24000cb4
+ 8021638:	2400ae08 	.word	0x2400ae08
+ 802163c:	24001cf4 	.word	0x24001cf4
+ 8021640:	2400ae9c 	.word	0x2400ae9c
+ 8021644:	24002d34 	.word	0x24002d34
+ 8021648:	2400ac4c 	.word	0x2400ac4c
+ 802164c:	24003d74 	.word	0x24003d74
+ 8021650:	2400ad74 	.word	0x2400ad74
+ 8021654:	24006e34 	.word	0x24006e34
+ 8021658:	2400ab24 	.word	0x2400ab24
+ 802165c:	24004db4 	.word	0x24004db4
+ 8021660:	2400abb8 	.word	0x2400abb8
+ 8021664:	24005df4 	.word	0x24005df4
+ 8021668:	24005df7 	.word	0x24005df7
+ 802166c:	24004db7 	.word	0x24004db7
+ 8021670:	24000cb7 	.word	0x24000cb7
+ 8021674:	24001cf7 	.word	0x24001cf7
+ 8021678:	24002d37 	.word	0x24002d37
+ 802167c:	24003d77 	.word	0x24003d77
+ 8021680:	24006e37 	.word	0x24006e37
+ 8021684:	2400aa90 	.word	0x2400aa90
+ 8021688:	24007e74 	.word	0x24007e74
+ 802168c:	24007e77 	.word	0x24007e77
+ 8021690:	08021695 	.word	0x08021695
+
+08021694 <GF_BSP_UART_Timer>:
+//Count Every 2 ms
+void GF_BSP_UART_Timer()
+{
+ 8021694:	b580      	push	{r7, lr}
+ 8021696:	af00      	add	r7, sp, #0
+	Counting(&RS_485_1_UART_Handler);
+ 8021698:	480c      	ldr	r0, [pc, #48]	@ (80216cc <GF_BSP_UART_Timer+0x38>)
+ 802169a:	f000 fa43 	bl	8021b24 <Counting>
+	Counting(&RS_485_2_UART_Handler);
+ 802169e:	480c      	ldr	r0, [pc, #48]	@ (80216d0 <GF_BSP_UART_Timer+0x3c>)
+ 80216a0:	f000 fa40 	bl	8021b24 <Counting>
+	Counting(&RS_485_3_UART_Handler);
+ 80216a4:	480b      	ldr	r0, [pc, #44]	@ (80216d4 <GF_BSP_UART_Timer+0x40>)
+ 80216a6:	f000 fa3d 	bl	8021b24 <Counting>
+	Counting(&RS_485_4_UART_Handler);
+ 80216aa:	480b      	ldr	r0, [pc, #44]	@ (80216d8 <GF_BSP_UART_Timer+0x44>)
+ 80216ac:	f000 fa3a 	bl	8021b24 <Counting>
+	Counting(&LTE_7S0_Serial_UART_Handler);
+ 80216b0:	480a      	ldr	r0, [pc, #40]	@ (80216dc <GF_BSP_UART_Timer+0x48>)
+ 80216b2:	f000 fa37 	bl	8021b24 <Counting>
+	Counting(&InterCall_DEBUG_UART_Handler);
+ 80216b6:	480a      	ldr	r0, [pc, #40]	@ (80216e0 <GF_BSP_UART_Timer+0x4c>)
+ 80216b8:	f000 fa34 	bl	8021b24 <Counting>
+	Counting(&E28_SBUS_UART_Handler);
+ 80216bc:	4809      	ldr	r0, [pc, #36]	@ (80216e4 <GF_BSP_UART_Timer+0x50>)
+ 80216be:	f000 fa31 	bl	8021b24 <Counting>
+
+#if defined (hlpuart1Exit)
+ 	Counting(&LPUART1_UART_Handler);
+ 80216c2:	4809      	ldr	r0, [pc, #36]	@ (80216e8 <GF_BSP_UART_Timer+0x54>)
+ 80216c4:	f000 fa2e 	bl	8021b24 <Counting>
+#endif
+
+
+
+}
+ 80216c8:	bf00      	nop
+ 80216ca:	bd80      	pop	{r7, pc}
+ 80216cc:	24000cb4 	.word	0x24000cb4
+ 80216d0:	24001cf4 	.word	0x24001cf4
+ 80216d4:	24002d34 	.word	0x24002d34
+ 80216d8:	24003d74 	.word	0x24003d74
+ 80216dc:	24006e34 	.word	0x24006e34
+ 80216e0:	24004db4 	.word	0x24004db4
+ 80216e4:	24005df4 	.word	0x24005df4
+ 80216e8:	24007e74 	.word	0x24007e74
+
+080216ec <UARTHandlerAddTxList>:
+
+void UARTHandlerAddTxList(struct UARTHandler *uartHandler, uint8_t *data,
+		uint16_t length, uint32_t txListTimePeriod, void (*UART_Decode)(uint8_t*, uint16_t))
+{
+ 80216ec:	b580      	push	{r7, lr}
+ 80216ee:	b088      	sub	sp, #32
+ 80216f0:	af00      	add	r7, sp, #0
+ 80216f2:	60f8      	str	r0, [r7, #12]
+ 80216f4:	60b9      	str	r1, [r7, #8]
+ 80216f6:	603b      	str	r3, [r7, #0]
+ 80216f8:	4613      	mov	r3, r2
+ 80216fa:	80fb      	strh	r3, [r7, #6]
+
+	UARTSendHandler *pTmp = NULL; //临时指针
+ 80216fc:	2300      	movs	r3, #0
+ 80216fe:	617b      	str	r3, [r7, #20]
+	//临时指针2用于逐个申请内存
+	pTmp = (UARTSendHandler*) malloc(sizeof(UARTSendHandler));
+ 8021700:	f44f 7001 	mov.w	r0, #516	@ 0x204
+ 8021704:	f01e fc66 	bl	803ffd4 <malloc>
+ 8021708:	4603      	mov	r3, r0
+ 802170a:	617b      	str	r3, [r7, #20]
+	memcpy(pTmp->Tx_Buf, data, length);
+ 802170c:	697b      	ldr	r3, [r7, #20]
+ 802170e:	3304      	adds	r3, #4
+ 8021710:	88fa      	ldrh	r2, [r7, #6]
+ 8021712:	68b9      	ldr	r1, [r7, #8]
+ 8021714:	4618      	mov	r0, r3
+ 8021716:	f01e fe51 	bl	80403bc <memcpy>
+	pTmp->pNext = NULL;
+ 802171a:	697b      	ldr	r3, [r7, #20]
+ 802171c:	2200      	movs	r2, #0
+ 802171e:	f8c3 2200 	str.w	r2, [r3, #512]	@ 0x200
+	pTmp->SendListTimePeriod=txListTimePeriod;
+ 8021722:	683b      	ldr	r3, [r7, #0]
+ 8021724:	b29a      	uxth	r2, r3
+ 8021726:	697b      	ldr	r3, [r7, #20]
+ 8021728:	805a      	strh	r2, [r3, #2]
+	pTmp->SendLength = length;
+ 802172a:	697b      	ldr	r3, [r7, #20]
+ 802172c:	88fa      	ldrh	r2, [r7, #6]
+ 802172e:	801a      	strh	r2, [r3, #0]
+	pTmp->UART_Decode = UART_Decode;
+ 8021730:	697b      	ldr	r3, [r7, #20]
+ 8021732:	6aba      	ldr	r2, [r7, #40]	@ 0x28
+ 8021734:	f8c3 21fc 	str.w	r2, [r3, #508]	@ 0x1fc
+
+//if NULL, call intialize one
+	if (uartHandler->pCurrentUARTSendHadler == NULL)
+ 8021738:	68fb      	ldr	r3, [r7, #12]
+ 802173a:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 802173e:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
+ 8021740:	2b00      	cmp	r3, #0
+ 8021742:	d106      	bne.n	8021752 <UARTHandlerAddTxList+0x66>
+	{
+		uartHandler->pCurrentUARTSendHadler = pTmp; //空链表
+ 8021744:	68fb      	ldr	r3, [r7, #12]
+ 8021746:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 802174a:	461a      	mov	r2, r3
+ 802174c:	697b      	ldr	r3, [r7, #20]
+ 802174e:	6353      	str	r3, [r2, #52]	@ 0x34
+		}
+		phead->pNext = pTmp;
+
+	}
+
+}
+ 8021750:	e019      	b.n	8021786 <UARTHandlerAddTxList+0x9a>
+		char i = 0;
+ 8021752:	2300      	movs	r3, #0
+ 8021754:	77fb      	strb	r3, [r7, #31]
+		UARTSendHandler *phead = NULL;
+ 8021756:	2300      	movs	r3, #0
+ 8021758:	61bb      	str	r3, [r7, #24]
+		phead = uartHandler->pCurrentUARTSendHadler;
+ 802175a:	68fb      	ldr	r3, [r7, #12]
+ 802175c:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8021760:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
+ 8021762:	61bb      	str	r3, [r7, #24]
+		while (phead->pNext != NULL)
+ 8021764:	e006      	b.n	8021774 <UARTHandlerAddTxList+0x88>
+			i++;
+ 8021766:	7ffb      	ldrb	r3, [r7, #31]
+ 8021768:	3301      	adds	r3, #1
+ 802176a:	77fb      	strb	r3, [r7, #31]
+			phead = phead->pNext;
+ 802176c:	69bb      	ldr	r3, [r7, #24]
+ 802176e:	f8d3 3200 	ldr.w	r3, [r3, #512]	@ 0x200
+ 8021772:	61bb      	str	r3, [r7, #24]
+		while (phead->pNext != NULL)
+ 8021774:	69bb      	ldr	r3, [r7, #24]
+ 8021776:	f8d3 3200 	ldr.w	r3, [r3, #512]	@ 0x200
+ 802177a:	2b00      	cmp	r3, #0
+ 802177c:	d1f3      	bne.n	8021766 <UARTHandlerAddTxList+0x7a>
+		phead->pNext = pTmp;
+ 802177e:	69bb      	ldr	r3, [r7, #24]
+ 8021780:	697a      	ldr	r2, [r7, #20]
+ 8021782:	f8c3 2200 	str.w	r2, [r3, #512]	@ 0x200
+}
+ 8021786:	bf00      	nop
+ 8021788:	3720      	adds	r7, #32
+ 802178a:	46bd      	mov	sp, r7
+ 802178c:	bd80      	pop	{r7, pc}
+	...
+
+08021790 <UARTHandlerTx>:
+
+void UARTHandlerTx(struct UARTHandler *uartHandler)
+{
+ 8021790:	b580      	push	{r7, lr}
+ 8021792:	b08a      	sub	sp, #40	@ 0x28
+ 8021794:	af04      	add	r7, sp, #16
+ 8021796:	6078      	str	r0, [r7, #4]
+
+	if (uartHandler->uart == NULL)
+ 8021798:	687b      	ldr	r3, [r7, #4]
+ 802179a:	69db      	ldr	r3, [r3, #28]
+ 802179c:	2b00      	cmp	r3, #0
+ 802179e:	d124      	bne.n	80217ea <UARTHandlerTx+0x5a>
+	{
+		LOGFF(DL_ERROR,
+ 80217a0:	4b78      	ldr	r3, [pc, #480]	@ (8021984 <UARTHandlerTx+0x1f4>)
+ 80217a2:	781b      	ldrb	r3, [r3, #0]
+ 80217a4:	2b01      	cmp	r3, #1
+ 80217a6:	f240 80e8 	bls.w	802197a <UARTHandlerTx+0x1ea>
+ 80217aa:	2330      	movs	r3, #48	@ 0x30
+ 80217ac:	061a      	lsls	r2, r3, #24
+ 80217ae:	2330      	movs	r3, #48	@ 0x30
+ 80217b0:	041b      	lsls	r3, r3, #16
+ 80217b2:	431a      	orrs	r2, r3
+ 80217b4:	2330      	movs	r3, #48	@ 0x30
+ 80217b6:	021b      	lsls	r3, r3, #8
+ 80217b8:	4313      	orrs	r3, r2
+ 80217ba:	2230      	movs	r2, #48	@ 0x30
+ 80217bc:	ea43 0102 	orr.w	r1, r3, r2
+ 80217c0:	2344      	movs	r3, #68	@ 0x44
+ 80217c2:	061a      	lsls	r2, r3, #24
+ 80217c4:	2346      	movs	r3, #70	@ 0x46
+ 80217c6:	041b      	lsls	r3, r3, #16
+ 80217c8:	431a      	orrs	r2, r3
+ 80217ca:	234c      	movs	r3, #76	@ 0x4c
+ 80217cc:	021b      	lsls	r3, r3, #8
+ 80217ce:	4313      	orrs	r3, r2
+ 80217d0:	2254      	movs	r2, #84	@ 0x54
+ 80217d2:	431a      	orrs	r2, r3
+ 80217d4:	4b6c      	ldr	r3, [pc, #432]	@ (8021988 <UARTHandlerTx+0x1f8>)
+ 80217d6:	9302      	str	r3, [sp, #8]
+ 80217d8:	23b6      	movs	r3, #182	@ 0xb6
+ 80217da:	9301      	str	r3, [sp, #4]
+ 80217dc:	4b6b      	ldr	r3, [pc, #428]	@ (802198c <UARTHandlerTx+0x1fc>)
+ 80217de:	9300      	str	r3, [sp, #0]
+ 80217e0:	4b6b      	ldr	r3, [pc, #428]	@ (8021990 <UARTHandlerTx+0x200>)
+ 80217e2:	2002      	movs	r0, #2
+ 80217e4:	f004 fd26 	bl	8026234 <DLTuc_LogOutVarArgs>
+				"the UART Hardware did  not intialize,check the setting");
+		return;
+ 80217e8:	e0c7      	b.n	802197a <UARTHandlerTx+0x1ea>
+	}
+
+	uartHandler->RxCount=0;//设定RxCount为0
+ 80217ea:	687b      	ldr	r3, [r7, #4]
+ 80217ec:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 80217f0:	2200      	movs	r2, #0
+ 80217f2:	849a      	strh	r2, [r3, #36]	@ 0x24
+#if defined (hlpuart1Exit)
+		if(uartHandler->uart->Instance == LPUART1)
+ 80217f4:	687b      	ldr	r3, [r7, #4]
+ 80217f6:	69db      	ldr	r3, [r3, #28]
+ 80217f8:	681b      	ldr	r3, [r3, #0]
+ 80217fa:	4a66      	ldr	r2, [pc, #408]	@ (8021994 <UARTHandlerTx+0x204>)
+ 80217fc:	4293      	cmp	r3, r2
+ 80217fe:	d10c      	bne.n	802181a <UARTHandlerTx+0x8a>
+		{
+
+			HAL_UART_Transmit(uartHandler->uart, uartHandler->Tx_Buf,
+ 8021800:	687b      	ldr	r3, [r7, #4]
+ 8021802:	69d8      	ldr	r0, [r3, #28]
+ 8021804:	687b      	ldr	r3, [r7, #4]
+ 8021806:	f603 0121 	addw	r1, r3, #2081	@ 0x821
+ 802180a:	687b      	ldr	r3, [r7, #4]
+ 802180c:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8021810:	8c5a      	ldrh	r2, [r3, #34]	@ 0x22
+ 8021812:	2364      	movs	r3, #100	@ 0x64
+ 8021814:	f01b fe6c 	bl	803d4f0 <HAL_UART_Transmit>
+ 8021818:	e075      	b.n	8021906 <UARTHandlerTx+0x176>
+						uartHandler->TxCount,100);
+		}else
+		{
+#endif
+
+		if (uartHandler->uart->Instance == UART4)			//**DEBUG
+ 802181a:	687b      	ldr	r3, [r7, #4]
+ 802181c:	69db      	ldr	r3, [r3, #28]
+ 802181e:	681b      	ldr	r3, [r3, #0]
+ 8021820:	4a5d      	ldr	r2, [pc, #372]	@ (8021998 <UARTHandlerTx+0x208>)
+ 8021822:	4293      	cmp	r3, r2
+ 8021824:	d038      	beq.n	8021898 <UARTHandlerTx+0x108>
+			{
+
+			} else if (uartHandler->uart->Instance == USART1)		//**RS485_1
+ 8021826:	687b      	ldr	r3, [r7, #4]
+ 8021828:	69db      	ldr	r3, [r3, #28]
+ 802182a:	681b      	ldr	r3, [r3, #0]
+ 802182c:	4a5b      	ldr	r2, [pc, #364]	@ (802199c <UARTHandlerTx+0x20c>)
+ 802182e:	4293      	cmp	r3, r2
+ 8021830:	d106      	bne.n	8021840 <UARTHandlerTx+0xb0>
+			{
+
+				HAL_GPIO_WritePin(RS485_1_DIR_GPIO_Port, RS485_1_DIR_Pin, GPIO_PIN_SET);
+ 8021832:	2201      	movs	r2, #1
+ 8021834:	f44f 6180 	mov.w	r1, #1024	@ 0x400
+ 8021838:	4859      	ldr	r0, [pc, #356]	@ (80219a0 <UARTHandlerTx+0x210>)
+ 802183a:	f016 f87f 	bl	803793c <HAL_GPIO_WritePin>
+ 802183e:	e02b      	b.n	8021898 <UARTHandlerTx+0x108>
+
+			} else if (uartHandler->uart->Instance == USART3)		//**RS485_2
+ 8021840:	687b      	ldr	r3, [r7, #4]
+ 8021842:	69db      	ldr	r3, [r3, #28]
+ 8021844:	681b      	ldr	r3, [r3, #0]
+ 8021846:	4a57      	ldr	r2, [pc, #348]	@ (80219a4 <UARTHandlerTx+0x214>)
+ 8021848:	4293      	cmp	r3, r2
+ 802184a:	d106      	bne.n	802185a <UARTHandlerTx+0xca>
+			{
+
+				HAL_GPIO_WritePin(RS485_2_DIR_GPIO_Port, RS485_2_DIR_Pin, GPIO_PIN_SET);
+ 802184c:	2201      	movs	r2, #1
+ 802184e:	f44f 6100 	mov.w	r1, #2048	@ 0x800
+ 8021852:	4853      	ldr	r0, [pc, #332]	@ (80219a0 <UARTHandlerTx+0x210>)
+ 8021854:	f016 f872 	bl	803793c <HAL_GPIO_WritePin>
+ 8021858:	e01e      	b.n	8021898 <UARTHandlerTx+0x108>
+
+			} else if (uartHandler->uart->Instance == USART6)		//**RS485_3
+ 802185a:	687b      	ldr	r3, [r7, #4]
+ 802185c:	69db      	ldr	r3, [r3, #28]
+ 802185e:	681b      	ldr	r3, [r3, #0]
+ 8021860:	4a51      	ldr	r2, [pc, #324]	@ (80219a8 <UARTHandlerTx+0x218>)
+ 8021862:	4293      	cmp	r3, r2
+ 8021864:	d106      	bne.n	8021874 <UARTHandlerTx+0xe4>
+			{
+
+				HAL_GPIO_WritePin(RS485_3_DIR_GPIO_Port, RS485_3_DIR_Pin, GPIO_PIN_SET);
+ 8021866:	2201      	movs	r2, #1
+ 8021868:	f44f 7180 	mov.w	r1, #256	@ 0x100
+ 802186c:	484f      	ldr	r0, [pc, #316]	@ (80219ac <UARTHandlerTx+0x21c>)
+ 802186e:	f016 f865 	bl	803793c <HAL_GPIO_WritePin>
+ 8021872:	e011      	b.n	8021898 <UARTHandlerTx+0x108>
+
+			} else if (uartHandler->uart->Instance == UART7)		//**RS485_4
+ 8021874:	687b      	ldr	r3, [r7, #4]
+ 8021876:	69db      	ldr	r3, [r3, #28]
+ 8021878:	681b      	ldr	r3, [r3, #0]
+ 802187a:	4a4d      	ldr	r2, [pc, #308]	@ (80219b0 <UARTHandlerTx+0x220>)
+ 802187c:	4293      	cmp	r3, r2
+ 802187e:	d106      	bne.n	802188e <UARTHandlerTx+0xfe>
+			{
+				HAL_GPIO_WritePin(RS485_4_DIR_GPIO_Port, RS485_4_DIR_Pin, GPIO_PIN_SET);
+ 8021880:	2201      	movs	r2, #1
+ 8021882:	f44f 7100 	mov.w	r1, #512	@ 0x200
+ 8021886:	4849      	ldr	r0, [pc, #292]	@ (80219ac <UARTHandlerTx+0x21c>)
+ 8021888:	f016 f858 	bl	803793c <HAL_GPIO_WritePin>
+ 802188c:	e004      	b.n	8021898 <UARTHandlerTx+0x108>
+
+			} else if (uartHandler->uart->Instance == USART2)//**E22	// External serial port
+ 802188e:	687b      	ldr	r3, [r7, #4]
+ 8021890:	69db      	ldr	r3, [r3, #28]
+ 8021892:	681b      	ldr	r3, [r3, #0]
+ 8021894:	4a47      	ldr	r2, [pc, #284]	@ (80219b4 <UARTHandlerTx+0x224>)
+ 8021896:	4293      	cmp	r3, r2
+			} else if (uartHandler->uart->Instance == UART5)	//**E28	// SBUS
+			{
+
+			}
+
+			SCB_CleanInvalidateDCache_by_Addr((uint32_t*) uartHandler->Tx_Buf,
+ 8021898:	687b      	ldr	r3, [r7, #4]
+ 802189a:	f603 0321 	addw	r3, r3, #2081	@ 0x821
+					uartHandler->TxCount);
+ 802189e:	687a      	ldr	r2, [r7, #4]
+ 80218a0:	f502 5280 	add.w	r2, r2, #4096	@ 0x1000
+ 80218a4:	8c52      	ldrh	r2, [r2, #34]	@ 0x22
+ 80218a6:	617b      	str	r3, [r7, #20]
+ 80218a8:	613a      	str	r2, [r7, #16]
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    if ( dsize > 0 ) { 
+ 80218aa:	693b      	ldr	r3, [r7, #16]
+ 80218ac:	2b00      	cmp	r3, #0
+ 80218ae:	dd1d      	ble.n	80218ec <UARTHandlerTx+0x15c>
+       int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
+ 80218b0:	697b      	ldr	r3, [r7, #20]
+ 80218b2:	f003 021f 	and.w	r2, r3, #31
+ 80218b6:	693b      	ldr	r3, [r7, #16]
+ 80218b8:	4413      	add	r3, r2
+ 80218ba:	60fb      	str	r3, [r7, #12]
+      uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
+ 80218bc:	697b      	ldr	r3, [r7, #20]
+ 80218be:	60bb      	str	r3, [r7, #8]
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+__STATIC_FORCEINLINE void __DSB(void)
+{
+  __ASM volatile ("dsb 0xF":::"memory");
+ 80218c0:	f3bf 8f4f 	dsb	sy
+}
+ 80218c4:	bf00      	nop
+    
+      __DSB();
+
+      do {
+        SCB->DCCIMVAC = op_addr;            /* register accepts only 32byte aligned values, only bits 31..5 are valid */
+ 80218c6:	4a3c      	ldr	r2, [pc, #240]	@ (80219b8 <UARTHandlerTx+0x228>)
+ 80218c8:	68bb      	ldr	r3, [r7, #8]
+ 80218ca:	f8c2 3270 	str.w	r3, [r2, #624]	@ 0x270
+        op_addr +=          __SCB_DCACHE_LINE_SIZE;
+ 80218ce:	68bb      	ldr	r3, [r7, #8]
+ 80218d0:	3320      	adds	r3, #32
+ 80218d2:	60bb      	str	r3, [r7, #8]
+        op_size -=          __SCB_DCACHE_LINE_SIZE;
+ 80218d4:	68fb      	ldr	r3, [r7, #12]
+ 80218d6:	3b20      	subs	r3, #32
+ 80218d8:	60fb      	str	r3, [r7, #12]
+      } while ( op_size > 0 );
+ 80218da:	68fb      	ldr	r3, [r7, #12]
+ 80218dc:	2b00      	cmp	r3, #0
+ 80218de:	dcf2      	bgt.n	80218c6 <UARTHandlerTx+0x136>
+  __ASM volatile ("dsb 0xF":::"memory");
+ 80218e0:	f3bf 8f4f 	dsb	sy
+}
+ 80218e4:	bf00      	nop
+  __ASM volatile ("isb 0xF":::"memory");
+ 80218e6:	f3bf 8f6f 	isb	sy
+}
+ 80218ea:	bf00      	nop
+
+      __DSB();
+      __ISB();
+    }
+  #endif
+}
+ 80218ec:	bf00      	nop
+
+			HAL_UART_Transmit_DMA(uartHandler->uart, uartHandler->Tx_Buf,
+ 80218ee:	687b      	ldr	r3, [r7, #4]
+ 80218f0:	69d8      	ldr	r0, [r3, #28]
+ 80218f2:	687b      	ldr	r3, [r7, #4]
+ 80218f4:	f603 0121 	addw	r1, r3, #2081	@ 0x821
+ 80218f8:	687b      	ldr	r3, [r7, #4]
+ 80218fa:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 80218fe:	8c5b      	ldrh	r3, [r3, #34]	@ 0x22
+ 8021900:	461a      	mov	r2, r3
+ 8021902:	f01b fecf 	bl	803d6a4 <HAL_UART_Transmit_DMA>
+#if defined (hlpuart1Exit)
+		}
+#endif
+
+
+	if (uartHandler->uart == UART4)			//**DEBUG
+ 8021906:	687b      	ldr	r3, [r7, #4]
+ 8021908:	69db      	ldr	r3, [r3, #28]
+ 802190a:	4a23      	ldr	r2, [pc, #140]	@ (8021998 <UARTHandlerTx+0x208>)
+ 802190c:	4293      	cmp	r3, r2
+ 802190e:	d035      	beq.n	802197c <UARTHandlerTx+0x1ec>
+	{
+
+	} else if (uartHandler->uart == USART1)		//**RS485_1
+ 8021910:	687b      	ldr	r3, [r7, #4]
+ 8021912:	69db      	ldr	r3, [r3, #28]
+ 8021914:	4a21      	ldr	r2, [pc, #132]	@ (802199c <UARTHandlerTx+0x20c>)
+ 8021916:	4293      	cmp	r3, r2
+ 8021918:	d106      	bne.n	8021928 <UARTHandlerTx+0x198>
+	{
+		HAL_GPIO_WritePin(RS485_1_DIR_GPIO_Port, RS485_1_DIR_Pin,
+ 802191a:	2200      	movs	r2, #0
+ 802191c:	f44f 6180 	mov.w	r1, #1024	@ 0x400
+ 8021920:	481f      	ldr	r0, [pc, #124]	@ (80219a0 <UARTHandlerTx+0x210>)
+ 8021922:	f016 f80b 	bl	803793c <HAL_GPIO_WritePin>
+ 8021926:	e029      	b.n	802197c <UARTHandlerTx+0x1ec>
+				GPIO_PIN_RESET);
+	} else if (uartHandler->uart == USART3)		//**RS485_2
+ 8021928:	687b      	ldr	r3, [r7, #4]
+ 802192a:	69db      	ldr	r3, [r3, #28]
+ 802192c:	4a1d      	ldr	r2, [pc, #116]	@ (80219a4 <UARTHandlerTx+0x214>)
+ 802192e:	4293      	cmp	r3, r2
+ 8021930:	d106      	bne.n	8021940 <UARTHandlerTx+0x1b0>
+	{
+		HAL_GPIO_WritePin(RS485_2_DIR_GPIO_Port, RS485_2_DIR_Pin,
+ 8021932:	2200      	movs	r2, #0
+ 8021934:	f44f 6100 	mov.w	r1, #2048	@ 0x800
+ 8021938:	4819      	ldr	r0, [pc, #100]	@ (80219a0 <UARTHandlerTx+0x210>)
+ 802193a:	f015 ffff 	bl	803793c <HAL_GPIO_WritePin>
+ 802193e:	e01d      	b.n	802197c <UARTHandlerTx+0x1ec>
+				GPIO_PIN_RESET);
+	} else if (uartHandler->uart == USART6)		//**RS485_3
+ 8021940:	687b      	ldr	r3, [r7, #4]
+ 8021942:	69db      	ldr	r3, [r3, #28]
+ 8021944:	4a18      	ldr	r2, [pc, #96]	@ (80219a8 <UARTHandlerTx+0x218>)
+ 8021946:	4293      	cmp	r3, r2
+ 8021948:	d106      	bne.n	8021958 <UARTHandlerTx+0x1c8>
+	{
+		HAL_GPIO_WritePin(RS485_3_DIR_GPIO_Port,
+ 802194a:	2200      	movs	r2, #0
+ 802194c:	f44f 7180 	mov.w	r1, #256	@ 0x100
+ 8021950:	4816      	ldr	r0, [pc, #88]	@ (80219ac <UARTHandlerTx+0x21c>)
+ 8021952:	f015 fff3 	bl	803793c <HAL_GPIO_WritePin>
+ 8021956:	e011      	b.n	802197c <UARTHandlerTx+0x1ec>
+		RS485_3_DIR_Pin, GPIO_PIN_RESET);
+	} else if (uartHandler->uart == UART7)		//**RS485_4
+ 8021958:	687b      	ldr	r3, [r7, #4]
+ 802195a:	69db      	ldr	r3, [r3, #28]
+ 802195c:	4a14      	ldr	r2, [pc, #80]	@ (80219b0 <UARTHandlerTx+0x220>)
+ 802195e:	4293      	cmp	r3, r2
+ 8021960:	d106      	bne.n	8021970 <UARTHandlerTx+0x1e0>
+	{
+		HAL_GPIO_WritePin(RS485_4_DIR_GPIO_Port,
+ 8021962:	2200      	movs	r2, #0
+ 8021964:	f44f 7100 	mov.w	r1, #512	@ 0x200
+ 8021968:	4810      	ldr	r0, [pc, #64]	@ (80219ac <UARTHandlerTx+0x21c>)
+ 802196a:	f015 ffe7 	bl	803793c <HAL_GPIO_WritePin>
+ 802196e:	e005      	b.n	802197c <UARTHandlerTx+0x1ec>
+		RS485_4_DIR_Pin, GPIO_PIN_RESET);
+	} else if (uartHandler->uart == USART2)	//**E22	// External serial port
+ 8021970:	687b      	ldr	r3, [r7, #4]
+ 8021972:	69db      	ldr	r3, [r3, #28]
+ 8021974:	4a0f      	ldr	r2, [pc, #60]	@ (80219b4 <UARTHandlerTx+0x224>)
+ 8021976:	4293      	cmp	r3, r2
+ 8021978:	e000      	b.n	802197c <UARTHandlerTx+0x1ec>
+		return;
+ 802197a:	bf00      	nop
+
+	} else if (uartHandler->uart == UART5)	//**E28	// SBUS
+	{
+
+	}
+}
+ 802197c:	3718      	adds	r7, #24
+ 802197e:	46bd      	mov	sp, r7
+ 8021980:	bd80      	pop	{r7, pc}
+ 8021982:	bf00      	nop
+ 8021984:	24009110 	.word	0x24009110
+ 8021988:	08041bd4 	.word	0x08041bd4
+ 802198c:	08040f08 	.word	0x08040f08
+ 8021990:	08040eb4 	.word	0x08040eb4
+ 8021994:	58000c00 	.word	0x58000c00
+ 8021998:	40004c00 	.word	0x40004c00
+ 802199c:	40011000 	.word	0x40011000
+ 80219a0:	58020c00 	.word	0x58020c00
+ 80219a4:	40004800 	.word	0x40004800
+ 80219a8:	40011400 	.word	0x40011400
+ 80219ac:	58020800 	.word	0x58020800
+ 80219b0:	40007800 	.word	0x40007800
+ 80219b4:	40004400 	.word	0x40004400
+ 80219b8:	e000ed00 	.word	0xe000ed00
+
+080219bc <UARTHandlerRX>:
+void UARTHandlerRX(struct UARTHandler *uartHandler)
+{
+ 80219bc:	b580      	push	{r7, lr}
+ 80219be:	b082      	sub	sp, #8
+ 80219c0:	af00      	add	r7, sp, #0
+ 80219c2:	6078      	str	r0, [r7, #4]
+	//uartHandler->Wait_Time_Count = 0;
+	if (uartHandler->startCountFlag == 0)
+ 80219c4:	687b      	ldr	r3, [r7, #4]
+ 80219c6:	781b      	ldrb	r3, [r3, #0]
+ 80219c8:	2b00      	cmp	r3, #0
+ 80219ca:	d107      	bne.n	80219dc <UARTHandlerRX+0x20>
+	{
+		uartHandler->startCountFlag = 1;
+ 80219cc:	687b      	ldr	r3, [r7, #4]
+ 80219ce:	2201      	movs	r2, #1
+ 80219d0:	701a      	strb	r2, [r3, #0]
+		uartHandler->RxCount = 0;
+ 80219d2:	687b      	ldr	r3, [r7, #4]
+ 80219d4:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 80219d8:	2200      	movs	r2, #0
+ 80219da:	849a      	strh	r2, [r3, #36]	@ 0x24
+	}
+
+	uartHandler->Rx_Buf[uartHandler->RxCount] = uartHandler->tmp_Rx_Buf[0];
+ 80219dc:	687b      	ldr	r3, [r7, #4]
+ 80219de:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 80219e2:	8c9b      	ldrh	r3, [r3, #36]	@ 0x24
+ 80219e4:	4619      	mov	r1, r3
+ 80219e6:	687b      	ldr	r3, [r7, #4]
+ 80219e8:	78da      	ldrb	r2, [r3, #3]
+ 80219ea:	687b      	ldr	r3, [r7, #4]
+ 80219ec:	440b      	add	r3, r1
+ 80219ee:	f883 2021 	strb.w	r2, [r3, #33]	@ 0x21
+	uartHandler->RxCount++;
+ 80219f2:	687b      	ldr	r3, [r7, #4]
+ 80219f4:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 80219f8:	8c9b      	ldrh	r3, [r3, #36]	@ 0x24
+ 80219fa:	3301      	adds	r3, #1
+ 80219fc:	b29a      	uxth	r2, r3
+ 80219fe:	687b      	ldr	r3, [r7, #4]
+ 8021a00:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8021a04:	849a      	strh	r2, [r3, #36]	@ 0x24
+
+	HAL_UART_Receive_IT(uartHandler->uart, uartHandler->tmp_Rx_Buf, 1);
+ 8021a06:	687b      	ldr	r3, [r7, #4]
+ 8021a08:	69d8      	ldr	r0, [r3, #28]
+ 8021a0a:	687b      	ldr	r3, [r7, #4]
+ 8021a0c:	3303      	adds	r3, #3
+ 8021a0e:	2201      	movs	r2, #1
+ 8021a10:	4619      	mov	r1, r3
+ 8021a12:	f01b fdfb 	bl	803d60c <HAL_UART_Receive_IT>
+
+	uartHandler->Wait_Time_Count = 0;
+ 8021a16:	687b      	ldr	r3, [r7, #4]
+ 8021a18:	2200      	movs	r2, #0
+ 8021a1a:	60da      	str	r2, [r3, #12]
+	if(uartHandler->RxCount>=1024)//接收数据过多，直接抛弃
+ 8021a1c:	687b      	ldr	r3, [r7, #4]
+ 8021a1e:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8021a22:	8c9b      	ldrh	r3, [r3, #36]	@ 0x24
+ 8021a24:	f5b3 6f80 	cmp.w	r3, #1024	@ 0x400
+ 8021a28:	d304      	bcc.n	8021a34 <UARTHandlerRX+0x78>
+	{
+		uartHandler->RxCount=0;
+ 8021a2a:	687b      	ldr	r3, [r7, #4]
+ 8021a2c:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8021a30:	2200      	movs	r2, #0
+ 8021a32:	849a      	strh	r2, [r3, #36]	@ 0x24
+	}
+	//HAL_UART_Receive_IT(uartHandler->uart, RS_485_2_UART_Handler.tmp_Rx_Buf, 1);
+}
+ 8021a34:	bf00      	nop
+ 8021a36:	3708      	adds	r7, #8
+ 8021a38:	46bd      	mov	sp, r7
+ 8021a3a:	bd80      	pop	{r7, pc}
+
+08021a3c <IntializeUARTHandler>:
+
+void IntializeUARTHandler(struct UARTHandler *uartHandler,
+		UART_HandleTypeDef *uart, int32_t WaitTime, unsigned char timeSpan,int32_t Dispacher_Time)
+{
+ 8021a3c:	b580      	push	{r7, lr}
+ 8021a3e:	b084      	sub	sp, #16
+ 8021a40:	af00      	add	r7, sp, #0
+ 8021a42:	60f8      	str	r0, [r7, #12]
+ 8021a44:	60b9      	str	r1, [r7, #8]
+ 8021a46:	607a      	str	r2, [r7, #4]
+ 8021a48:	70fb      	strb	r3, [r7, #3]
+	uartHandler->Wait_Time_Count = 0;
+ 8021a4a:	68fb      	ldr	r3, [r7, #12]
+ 8021a4c:	2200      	movs	r2, #0
+ 8021a4e:	60da      	str	r2, [r3, #12]
+	uartHandler->Wait_time = WaitTime;
+ 8021a50:	687a      	ldr	r2, [r7, #4]
+ 8021a52:	68fb      	ldr	r3, [r7, #12]
+ 8021a54:	609a      	str	r2, [r3, #8]
+
+	uartHandler->uart = uart;
+ 8021a56:	68fb      	ldr	r3, [r7, #12]
+ 8021a58:	68ba      	ldr	r2, [r7, #8]
+ 8021a5a:	61da      	str	r2, [r3, #28]
+	uartHandler->UART_Rx = UARTHandlerRX;
+ 8021a5c:	68fb      	ldr	r3, [r7, #12]
+ 8021a5e:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8021a62:	461a      	mov	r2, r3
+ 8021a64:	4b2a      	ldr	r3, [pc, #168]	@ (8021b10 <IntializeUARTHandler+0xd4>)
+ 8021a66:	62d3      	str	r3, [r2, #44]	@ 0x2c
+	uartHandler->UART_Tx = UARTHandlerTx;
+ 8021a68:	68fb      	ldr	r3, [r7, #12]
+ 8021a6a:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8021a6e:	461a      	mov	r2, r3
+ 8021a70:	4b28      	ldr	r3, [pc, #160]	@ (8021b14 <IntializeUARTHandler+0xd8>)
+ 8021a72:	6293      	str	r3, [r2, #40]	@ 0x28
+	uartHandler->AddSendList = UARTHandlerAddTxList;
+ 8021a74:	68fb      	ldr	r3, [r7, #12]
+ 8021a76:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8021a7a:	461a      	mov	r2, r3
+ 8021a7c:	4b26      	ldr	r3, [pc, #152]	@ (8021b18 <IntializeUARTHandler+0xdc>)
+ 8021a7e:	6393      	str	r3, [r2, #56]	@ 0x38
+
+	uartHandler->dispacherController = (DispacherController*) malloc(
+ 8021a80:	2018      	movs	r0, #24
+ 8021a82:	f01e faa7 	bl	803ffd4 <malloc>
+ 8021a86:	4603      	mov	r3, r0
+ 8021a88:	461a      	mov	r2, r3
+ 8021a8a:	68fb      	ldr	r3, [r7, #12]
+ 8021a8c:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8021a90:	63da      	str	r2, [r3, #60]	@ 0x3c
+			sizeof(DispacherController));
+
+	uartHandler->dispacherController->pHead = NULL;
+ 8021a92:	68fb      	ldr	r3, [r7, #12]
+ 8021a94:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8021a98:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 8021a9a:	2200      	movs	r2, #0
+ 8021a9c:	601a      	str	r2, [r3, #0]
+	uartHandler->dispacherController->pTail = NULL;
+ 8021a9e:	68fb      	ldr	r3, [r7, #12]
+ 8021aa0:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8021aa4:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 8021aa6:	2200      	movs	r2, #0
+ 8021aa8:	605a      	str	r2, [r3, #4]
+	uartHandler->dispacherController->Dispacher_Enable = 0;
+ 8021aaa:	68fb      	ldr	r3, [r7, #12]
+ 8021aac:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8021ab0:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 8021ab2:	2200      	movs	r2, #0
+ 8021ab4:	81da      	strh	r2, [r3, #14]
+	uartHandler->dispacherController->DispacherCallTime = Dispacher_Time ; // call the function every 50 ms
+ 8021ab6:	68fb      	ldr	r3, [r7, #12]
+ 8021ab8:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8021abc:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 8021abe:	69ba      	ldr	r2, [r7, #24]
+ 8021ac0:	b292      	uxth	r2, r2
+ 8021ac2:	815a      	strh	r2, [r3, #10]
+	uartHandler->dispacherController->Dispacher_Counter = 0;
+ 8021ac4:	68fb      	ldr	r3, [r7, #12]
+ 8021ac6:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8021aca:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 8021acc:	2200      	movs	r2, #0
+ 8021ace:	819a      	strh	r2, [r3, #12]
+	uartHandler->dispacherController->DispacherNumber = 0;
+ 8021ad0:	68fb      	ldr	r3, [r7, #12]
+ 8021ad2:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8021ad6:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 8021ad8:	2200      	movs	r2, #0
+ 8021ada:	811a      	strh	r2, [r3, #8]
+	uartHandler->dispacherController->Add_Dispatcher_List = Dispatcher_List_Add_t;
+ 8021adc:	68fb      	ldr	r3, [r7, #12]
+ 8021ade:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8021ae2:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 8021ae4:	4a0d      	ldr	r2, [pc, #52]	@ (8021b1c <IntializeUARTHandler+0xe0>)
+ 8021ae6:	611a      	str	r2, [r3, #16]
+	uartHandler->dispacherController->Dispatcher_Run = Dispatch_t;
+ 8021ae8:	68fb      	ldr	r3, [r7, #12]
+ 8021aea:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8021aee:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 8021af0:	4a0b      	ldr	r2, [pc, #44]	@ (8021b20 <IntializeUARTHandler+0xe4>)
+ 8021af2:	615a      	str	r2, [r3, #20]
+
+	uartHandler->timeSpan = 2;
+ 8021af4:	68fb      	ldr	r3, [r7, #12]
+ 8021af6:	2202      	movs	r2, #2
+ 8021af8:	f883 2020 	strb.w	r2, [r3, #32]
+	uartHandler->SendList_time_Count = 0;
+ 8021afc:	68fb      	ldr	r3, [r7, #12]
+ 8021afe:	2200      	movs	r2, #0
+ 8021b00:	611a      	str	r2, [r3, #16]
+	uartHandler->SendList_Period = 100;
+ 8021b02:	68fb      	ldr	r3, [r7, #12]
+ 8021b04:	2264      	movs	r2, #100	@ 0x64
+ 8021b06:	615a      	str	r2, [r3, #20]
+
+}
+ 8021b08:	bf00      	nop
+ 8021b0a:	3710      	adds	r7, #16
+ 8021b0c:	46bd      	mov	sp, r7
+ 8021b0e:	bd80      	pop	{r7, pc}
+ 8021b10:	080219bd 	.word	0x080219bd
+ 8021b14:	08021791 	.word	0x08021791
+ 8021b18:	080216ed 	.word	0x080216ed
+ 8021b1c:	0802227b 	.word	0x0802227b
+ 8021b20:	08022209 	.word	0x08022209
+
+08021b24 <Counting>:
+
+void Counting(struct UARTHandler *uartHandler)
+{
+ 8021b24:	b580      	push	{r7, lr}
+ 8021b26:	b082      	sub	sp, #8
+ 8021b28:	af00      	add	r7, sp, #0
+ 8021b2a:	6078      	str	r0, [r7, #4]
+
+	if (uartHandler->UART_Decode == NULL) //不解析，直接返回true
+ 8021b2c:	687b      	ldr	r3, [r7, #4]
+ 8021b2e:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8021b32:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
+ 8021b34:	2b00      	cmp	r3, #0
+ 8021b36:	d103      	bne.n	8021b40 <Counting+0x1c>
+	{
+		uartHandler->decode_finished = 1;
+ 8021b38:	687b      	ldr	r3, [r7, #4]
+ 8021b3a:	2201      	movs	r2, #1
+ 8021b3c:	709a      	strb	r2, [r3, #2]
+ 8021b3e:	e032      	b.n	8021ba6 <Counting+0x82>
+	} else
+	{
+		if (uartHandler->startCountFlag == 1)
+ 8021b40:	687b      	ldr	r3, [r7, #4]
+ 8021b42:	781b      	ldrb	r3, [r3, #0]
+ 8021b44:	2b01      	cmp	r3, #1
+ 8021b46:	d12e      	bne.n	8021ba6 <Counting+0x82>
+		{
+			uartHandler->Wait_Time_Count++;
+ 8021b48:	687b      	ldr	r3, [r7, #4]
+ 8021b4a:	68db      	ldr	r3, [r3, #12]
+ 8021b4c:	1c5a      	adds	r2, r3, #1
+ 8021b4e:	687b      	ldr	r3, [r7, #4]
+ 8021b50:	60da      	str	r2, [r3, #12]
+			if (uartHandler->timeSpan * uartHandler->Wait_Time_Count
+ 8021b52:	687b      	ldr	r3, [r7, #4]
+ 8021b54:	f893 3020 	ldrb.w	r3, [r3, #32]
+ 8021b58:	461a      	mov	r2, r3
+ 8021b5a:	687b      	ldr	r3, [r7, #4]
+ 8021b5c:	68db      	ldr	r3, [r3, #12]
+ 8021b5e:	fb03 f202 	mul.w	r2, r3, r2
+					>= uartHandler->Wait_time)
+ 8021b62:	687b      	ldr	r3, [r7, #4]
+ 8021b64:	689b      	ldr	r3, [r3, #8]
+			if (uartHandler->timeSpan * uartHandler->Wait_Time_Count
+ 8021b66:	429a      	cmp	r2, r3
+ 8021b68:	d31d      	bcc.n	8021ba6 <Counting+0x82>
+			{
+				uartHandler->Wait_Time_Count = 0;
+ 8021b6a:	687b      	ldr	r3, [r7, #4]
+ 8021b6c:	2200      	movs	r2, #0
+ 8021b6e:	60da      	str	r2, [r3, #12]
+				uartHandler->startCountFlag = 0;
+ 8021b70:	687b      	ldr	r3, [r7, #4]
+ 8021b72:	2200      	movs	r2, #0
+ 8021b74:	701a      	strb	r2, [r3, #0]
+				//启动解析函数
+				if (uartHandler->RxCount >= 1)
+ 8021b76:	687b      	ldr	r3, [r7, #4]
+ 8021b78:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8021b7c:	8c9b      	ldrh	r3, [r3, #36]	@ 0x24
+ 8021b7e:	2b00      	cmp	r3, #0
+ 8021b80:	d011      	beq.n	8021ba6 <Counting+0x82>
+				{
+					uartHandler->UART_Decode(uartHandler->Rx_Buf,
+ 8021b82:	687b      	ldr	r3, [r7, #4]
+ 8021b84:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8021b88:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
+ 8021b8a:	687a      	ldr	r2, [r7, #4]
+ 8021b8c:	f102 0021 	add.w	r0, r2, #33	@ 0x21
+ 8021b90:	687a      	ldr	r2, [r7, #4]
+ 8021b92:	f502 5280 	add.w	r2, r2, #4096	@ 0x1000
+ 8021b96:	8c92      	ldrh	r2, [r2, #36]	@ 0x24
+ 8021b98:	4611      	mov	r1, r2
+ 8021b9a:	4798      	blx	r3
+							uartHandler->RxCount);
+					uartHandler->RxCount = 0;
+ 8021b9c:	687b      	ldr	r3, [r7, #4]
+ 8021b9e:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8021ba2:	2200      	movs	r2, #0
+ 8021ba4:	849a      	strh	r2, [r3, #36]	@ 0x24
+			}
+
+		}
+	}
+
+	if (uartHandler->pCurrentUARTSendHadler != NULL)
+ 8021ba6:	687b      	ldr	r3, [r7, #4]
+ 8021ba8:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8021bac:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
+ 8021bae:	2b00      	cmp	r3, #0
+ 8021bb0:	d003      	beq.n	8021bba <Counting+0x96>
+	{
+
+		GF_UART_Send_List_Send(uartHandler);
+ 8021bb2:	6878      	ldr	r0, [r7, #4]
+ 8021bb4:	f000 f8d0 	bl	8021d58 <GF_UART_Send_List_Send>
+//
+//		}
+//
+//	}
+
+}
+ 8021bb8:	e00a      	b.n	8021bd0 <Counting+0xac>
+		uartHandler->dispacherController->Dispatcher_Run(
+ 8021bba:	687b      	ldr	r3, [r7, #4]
+ 8021bbc:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8021bc0:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 8021bc2:	695b      	ldr	r3, [r3, #20]
+ 8021bc4:	687a      	ldr	r2, [r7, #4]
+ 8021bc6:	f502 5280 	add.w	r2, r2, #4096	@ 0x1000
+ 8021bca:	6bd2      	ldr	r2, [r2, #60]	@ 0x3c
+ 8021bcc:	4610      	mov	r0, r2
+ 8021bce:	4798      	blx	r3
+}
+ 8021bd0:	bf00      	nop
+ 8021bd2:	3708      	adds	r7, #8
+ 8021bd4:	46bd      	mov	sp, r7
+ 8021bd6:	bd80      	pop	{r7, pc}
+
+08021bd8 <HAL_UART_RxCpltCallback>:
+//_weak
+void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
+{
+ 8021bd8:	b580      	push	{r7, lr}
+ 8021bda:	b082      	sub	sp, #8
+ 8021bdc:	af00      	add	r7, sp, #0
+ 8021bde:	6078      	str	r0, [r7, #4]
+	if (huart->Instance == UART4)			//**DEBUG
+ 8021be0:	687b      	ldr	r3, [r7, #4]
+ 8021be2:	681b      	ldr	r3, [r3, #0]
+ 8021be4:	4a24      	ldr	r2, [pc, #144]	@ (8021c78 <HAL_UART_RxCpltCallback+0xa0>)
+ 8021be6:	4293      	cmp	r3, r2
+ 8021be8:	d103      	bne.n	8021bf2 <HAL_UART_RxCpltCallback+0x1a>
+	{
+		UARTHandlerRX(&InterCall_DEBUG_UART_Handler);
+ 8021bea:	4824      	ldr	r0, [pc, #144]	@ (8021c7c <HAL_UART_RxCpltCallback+0xa4>)
+ 8021bec:	f7ff fee6 	bl	80219bc <UARTHandlerRX>
+			UARTHandlerRX(&LPUART1_UART_Handler);
+		}
+
+
+ #endif
+}
+ 8021bf0:	e03d      	b.n	8021c6e <HAL_UART_RxCpltCallback+0x96>
+	} else if (huart->Instance == USART1)		//**RS485_1
+ 8021bf2:	687b      	ldr	r3, [r7, #4]
+ 8021bf4:	681b      	ldr	r3, [r3, #0]
+ 8021bf6:	4a22      	ldr	r2, [pc, #136]	@ (8021c80 <HAL_UART_RxCpltCallback+0xa8>)
+ 8021bf8:	4293      	cmp	r3, r2
+ 8021bfa:	d103      	bne.n	8021c04 <HAL_UART_RxCpltCallback+0x2c>
+		UARTHandlerRX(&RS_485_1_UART_Handler);
+ 8021bfc:	4821      	ldr	r0, [pc, #132]	@ (8021c84 <HAL_UART_RxCpltCallback+0xac>)
+ 8021bfe:	f7ff fedd 	bl	80219bc <UARTHandlerRX>
+}
+ 8021c02:	e034      	b.n	8021c6e <HAL_UART_RxCpltCallback+0x96>
+	} else if (huart->Instance == USART3)		//**RS485_2
+ 8021c04:	687b      	ldr	r3, [r7, #4]
+ 8021c06:	681b      	ldr	r3, [r3, #0]
+ 8021c08:	4a1f      	ldr	r2, [pc, #124]	@ (8021c88 <HAL_UART_RxCpltCallback+0xb0>)
+ 8021c0a:	4293      	cmp	r3, r2
+ 8021c0c:	d103      	bne.n	8021c16 <HAL_UART_RxCpltCallback+0x3e>
+		GF_BSP_Interrupt_Run_CallBack(DF_BSP_InterCall_RS485_2_RxCpltCallback);
+ 8021c0e:	2003      	movs	r0, #3
+ 8021c10:	f7ff fbac 	bl	802136c <GF_BSP_Interrupt_Run_CallBack>
+}
+ 8021c14:	e02b      	b.n	8021c6e <HAL_UART_RxCpltCallback+0x96>
+	} else if (huart->Instance == USART6)		//**RS485_3
+ 8021c16:	687b      	ldr	r3, [r7, #4]
+ 8021c18:	681b      	ldr	r3, [r3, #0]
+ 8021c1a:	4a1c      	ldr	r2, [pc, #112]	@ (8021c8c <HAL_UART_RxCpltCallback+0xb4>)
+ 8021c1c:	4293      	cmp	r3, r2
+ 8021c1e:	d103      	bne.n	8021c28 <HAL_UART_RxCpltCallback+0x50>
+		UARTHandlerRX(&RS_485_3_UART_Handler);
+ 8021c20:	481b      	ldr	r0, [pc, #108]	@ (8021c90 <HAL_UART_RxCpltCallback+0xb8>)
+ 8021c22:	f7ff fecb 	bl	80219bc <UARTHandlerRX>
+}
+ 8021c26:	e022      	b.n	8021c6e <HAL_UART_RxCpltCallback+0x96>
+	} else if (huart->Instance == UART7)		//**RS485_4
+ 8021c28:	687b      	ldr	r3, [r7, #4]
+ 8021c2a:	681b      	ldr	r3, [r3, #0]
+ 8021c2c:	4a19      	ldr	r2, [pc, #100]	@ (8021c94 <HAL_UART_RxCpltCallback+0xbc>)
+ 8021c2e:	4293      	cmp	r3, r2
+ 8021c30:	d103      	bne.n	8021c3a <HAL_UART_RxCpltCallback+0x62>
+		UARTHandlerRX(&RS_485_4_UART_Handler);
+ 8021c32:	4819      	ldr	r0, [pc, #100]	@ (8021c98 <HAL_UART_RxCpltCallback+0xc0>)
+ 8021c34:	f7ff fec2 	bl	80219bc <UARTHandlerRX>
+}
+ 8021c38:	e019      	b.n	8021c6e <HAL_UART_RxCpltCallback+0x96>
+	} else if (huart->Instance == USART2)		//**E22	// External serial port
+ 8021c3a:	687b      	ldr	r3, [r7, #4]
+ 8021c3c:	681b      	ldr	r3, [r3, #0]
+ 8021c3e:	4a17      	ldr	r2, [pc, #92]	@ (8021c9c <HAL_UART_RxCpltCallback+0xc4>)
+ 8021c40:	4293      	cmp	r3, r2
+ 8021c42:	d103      	bne.n	8021c4c <HAL_UART_RxCpltCallback+0x74>
+		UARTHandlerRX(&LTE_7S0_Serial_UART_Handler);
+ 8021c44:	4816      	ldr	r0, [pc, #88]	@ (8021ca0 <HAL_UART_RxCpltCallback+0xc8>)
+ 8021c46:	f7ff feb9 	bl	80219bc <UARTHandlerRX>
+}
+ 8021c4a:	e010      	b.n	8021c6e <HAL_UART_RxCpltCallback+0x96>
+	} else if (huart->Instance == UART5)		//**E28	// SBUS
+ 8021c4c:	687b      	ldr	r3, [r7, #4]
+ 8021c4e:	681b      	ldr	r3, [r3, #0]
+ 8021c50:	4a14      	ldr	r2, [pc, #80]	@ (8021ca4 <HAL_UART_RxCpltCallback+0xcc>)
+ 8021c52:	4293      	cmp	r3, r2
+ 8021c54:	d103      	bne.n	8021c5e <HAL_UART_RxCpltCallback+0x86>
+		UARTHandlerRX(&E28_SBUS_UART_Handler);
+ 8021c56:	4814      	ldr	r0, [pc, #80]	@ (8021ca8 <HAL_UART_RxCpltCallback+0xd0>)
+ 8021c58:	f7ff feb0 	bl	80219bc <UARTHandlerRX>
+}
+ 8021c5c:	e007      	b.n	8021c6e <HAL_UART_RxCpltCallback+0x96>
+	else if (huart->Instance == LPUART1)		//**E28	// SBUS
+ 8021c5e:	687b      	ldr	r3, [r7, #4]
+ 8021c60:	681b      	ldr	r3, [r3, #0]
+ 8021c62:	4a12      	ldr	r2, [pc, #72]	@ (8021cac <HAL_UART_RxCpltCallback+0xd4>)
+ 8021c64:	4293      	cmp	r3, r2
+ 8021c66:	d102      	bne.n	8021c6e <HAL_UART_RxCpltCallback+0x96>
+			UARTHandlerRX(&LPUART1_UART_Handler);
+ 8021c68:	4811      	ldr	r0, [pc, #68]	@ (8021cb0 <HAL_UART_RxCpltCallback+0xd8>)
+ 8021c6a:	f7ff fea7 	bl	80219bc <UARTHandlerRX>
+}
+ 8021c6e:	bf00      	nop
+ 8021c70:	3708      	adds	r7, #8
+ 8021c72:	46bd      	mov	sp, r7
+ 8021c74:	bd80      	pop	{r7, pc}
+ 8021c76:	bf00      	nop
+ 8021c78:	40004c00 	.word	0x40004c00
+ 8021c7c:	24004db4 	.word	0x24004db4
+ 8021c80:	40011000 	.word	0x40011000
+ 8021c84:	24000cb4 	.word	0x24000cb4
+ 8021c88:	40004800 	.word	0x40004800
+ 8021c8c:	40011400 	.word	0x40011400
+ 8021c90:	24002d34 	.word	0x24002d34
+ 8021c94:	40007800 	.word	0x40007800
+ 8021c98:	24003d74 	.word	0x24003d74
+ 8021c9c:	40004400 	.word	0x40004400
+ 8021ca0:	24006e34 	.word	0x24006e34
+ 8021ca4:	40005000 	.word	0x40005000
+ 8021ca8:	24005df4 	.word	0x24005df4
+ 8021cac:	58000c00 	.word	0x58000c00
+ 8021cb0:	24007e74 	.word	0x24007e74
+
+08021cb4 <HAL_UART_TxCpltCallback>:
+
+void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
+{
+ 8021cb4:	b580      	push	{r7, lr}
+ 8021cb6:	b082      	sub	sp, #8
+ 8021cb8:	af00      	add	r7, sp, #0
+ 8021cba:	6078      	str	r0, [r7, #4]
+
+	if (huart->Instance == UART4)			//**DEBUG
+ 8021cbc:	687b      	ldr	r3, [r7, #4]
+ 8021cbe:	681b      	ldr	r3, [r3, #0]
+ 8021cc0:	4a1d      	ldr	r2, [pc, #116]	@ (8021d38 <HAL_UART_TxCpltCallback+0x84>)
+ 8021cc2:	4293      	cmp	r3, r2
+ 8021cc4:	d033      	beq.n	8021d2e <HAL_UART_TxCpltCallback+0x7a>
+	{
+
+	} else if (huart->Instance == USART1)		//**RS485_1
+ 8021cc6:	687b      	ldr	r3, [r7, #4]
+ 8021cc8:	681b      	ldr	r3, [r3, #0]
+ 8021cca:	4a1c      	ldr	r2, [pc, #112]	@ (8021d3c <HAL_UART_TxCpltCallback+0x88>)
+ 8021ccc:	4293      	cmp	r3, r2
+ 8021cce:	d106      	bne.n	8021cde <HAL_UART_TxCpltCallback+0x2a>
+	{
+		HAL_GPIO_WritePin(RS485_1_DIR_GPIO_Port, RS485_1_DIR_Pin,
+ 8021cd0:	2200      	movs	r2, #0
+ 8021cd2:	f44f 6180 	mov.w	r1, #1024	@ 0x400
+ 8021cd6:	481a      	ldr	r0, [pc, #104]	@ (8021d40 <HAL_UART_TxCpltCallback+0x8c>)
+ 8021cd8:	f015 fe30 	bl	803793c <HAL_GPIO_WritePin>
+	} else if (huart->Instance == UART5)	//**E28	// SBUS
+	{
+
+	}
+
+}
+ 8021cdc:	e027      	b.n	8021d2e <HAL_UART_TxCpltCallback+0x7a>
+	} else if (huart->Instance == USART3)		//**RS485_2
+ 8021cde:	687b      	ldr	r3, [r7, #4]
+ 8021ce0:	681b      	ldr	r3, [r3, #0]
+ 8021ce2:	4a18      	ldr	r2, [pc, #96]	@ (8021d44 <HAL_UART_TxCpltCallback+0x90>)
+ 8021ce4:	4293      	cmp	r3, r2
+ 8021ce6:	d106      	bne.n	8021cf6 <HAL_UART_TxCpltCallback+0x42>
+		HAL_GPIO_WritePin(RS485_2_DIR_GPIO_Port, RS485_2_DIR_Pin,
+ 8021ce8:	2200      	movs	r2, #0
+ 8021cea:	f44f 6100 	mov.w	r1, #2048	@ 0x800
+ 8021cee:	4814      	ldr	r0, [pc, #80]	@ (8021d40 <HAL_UART_TxCpltCallback+0x8c>)
+ 8021cf0:	f015 fe24 	bl	803793c <HAL_GPIO_WritePin>
+}
+ 8021cf4:	e01b      	b.n	8021d2e <HAL_UART_TxCpltCallback+0x7a>
+	} else if (huart->Instance == USART6)		//**RS485_3
+ 8021cf6:	687b      	ldr	r3, [r7, #4]
+ 8021cf8:	681b      	ldr	r3, [r3, #0]
+ 8021cfa:	4a13      	ldr	r2, [pc, #76]	@ (8021d48 <HAL_UART_TxCpltCallback+0x94>)
+ 8021cfc:	4293      	cmp	r3, r2
+ 8021cfe:	d106      	bne.n	8021d0e <HAL_UART_TxCpltCallback+0x5a>
+		HAL_GPIO_WritePin(RS485_3_DIR_GPIO_Port,
+ 8021d00:	2200      	movs	r2, #0
+ 8021d02:	f44f 7180 	mov.w	r1, #256	@ 0x100
+ 8021d06:	4811      	ldr	r0, [pc, #68]	@ (8021d4c <HAL_UART_TxCpltCallback+0x98>)
+ 8021d08:	f015 fe18 	bl	803793c <HAL_GPIO_WritePin>
+}
+ 8021d0c:	e00f      	b.n	8021d2e <HAL_UART_TxCpltCallback+0x7a>
+	} else if (huart->Instance == UART7)		//**RS485_4
+ 8021d0e:	687b      	ldr	r3, [r7, #4]
+ 8021d10:	681b      	ldr	r3, [r3, #0]
+ 8021d12:	4a0f      	ldr	r2, [pc, #60]	@ (8021d50 <HAL_UART_TxCpltCallback+0x9c>)
+ 8021d14:	4293      	cmp	r3, r2
+ 8021d16:	d106      	bne.n	8021d26 <HAL_UART_TxCpltCallback+0x72>
+		HAL_GPIO_WritePin(RS485_4_DIR_GPIO_Port,
+ 8021d18:	2200      	movs	r2, #0
+ 8021d1a:	f44f 7100 	mov.w	r1, #512	@ 0x200
+ 8021d1e:	480b      	ldr	r0, [pc, #44]	@ (8021d4c <HAL_UART_TxCpltCallback+0x98>)
+ 8021d20:	f015 fe0c 	bl	803793c <HAL_GPIO_WritePin>
+}
+ 8021d24:	e003      	b.n	8021d2e <HAL_UART_TxCpltCallback+0x7a>
+	} else if (huart->Instance == USART2)	//**E22	// External serial port
+ 8021d26:	687b      	ldr	r3, [r7, #4]
+ 8021d28:	681b      	ldr	r3, [r3, #0]
+ 8021d2a:	4a0a      	ldr	r2, [pc, #40]	@ (8021d54 <HAL_UART_TxCpltCallback+0xa0>)
+ 8021d2c:	4293      	cmp	r3, r2
+}
+ 8021d2e:	bf00      	nop
+ 8021d30:	3708      	adds	r7, #8
+ 8021d32:	46bd      	mov	sp, r7
+ 8021d34:	bd80      	pop	{r7, pc}
+ 8021d36:	bf00      	nop
+ 8021d38:	40004c00 	.word	0x40004c00
+ 8021d3c:	40011000 	.word	0x40011000
+ 8021d40:	58020c00 	.word	0x58020c00
+ 8021d44:	40004800 	.word	0x40004800
+ 8021d48:	40011400 	.word	0x40011400
+ 8021d4c:	58020800 	.word	0x58020800
+ 8021d50:	40007800 	.word	0x40007800
+ 8021d54:	40004400 	.word	0x40004400
+
+08021d58 <GF_UART_Send_List_Send>:
+//		uartHandler->pTail = pTmp; //set pTail the last node of this ring
+//		uartHandler->DispacherNumber++;
+//	}
+//}
+void GF_UART_Send_List_Send(struct UARTHandler *handler)
+{
+ 8021d58:	b580      	push	{r7, lr}
+ 8021d5a:	b084      	sub	sp, #16
+ 8021d5c:	af00      	add	r7, sp, #0
+ 8021d5e:	6078      	str	r0, [r7, #4]
+
+	handler->SendList_time_Count++;
+ 8021d60:	687b      	ldr	r3, [r7, #4]
+ 8021d62:	691b      	ldr	r3, [r3, #16]
+ 8021d64:	1c5a      	adds	r2, r3, #1
+ 8021d66:	687b      	ldr	r3, [r7, #4]
+ 8021d68:	611a      	str	r2, [r3, #16]
+	if (handler->timeSpan * handler->SendList_time_Count
+ 8021d6a:	687b      	ldr	r3, [r7, #4]
+ 8021d6c:	f893 3020 	ldrb.w	r3, [r3, #32]
+ 8021d70:	461a      	mov	r2, r3
+ 8021d72:	687b      	ldr	r3, [r7, #4]
+ 8021d74:	691b      	ldr	r3, [r3, #16]
+ 8021d76:	fb03 f202 	mul.w	r2, r3, r2
+			>= handler->SendList_Period)
+ 8021d7a:	687b      	ldr	r3, [r7, #4]
+ 8021d7c:	695b      	ldr	r3, [r3, #20]
+	if (handler->timeSpan * handler->SendList_time_Count
+ 8021d7e:	429a      	cmp	r2, r3
+ 8021d80:	d360      	bcc.n	8021e44 <GF_UART_Send_List_Send+0xec>
+	{
+		handler->SendList_time_Count = 0;
+ 8021d82:	687b      	ldr	r3, [r7, #4]
+ 8021d84:	2200      	movs	r2, #0
+ 8021d86:	611a      	str	r2, [r3, #16]
+		handler->SendListExists = 1;
+ 8021d88:	687b      	ldr	r3, [r7, #4]
+ 8021d8a:	2201      	movs	r2, #1
+ 8021d8c:	761a      	strb	r2, [r3, #24]
+		if (handler->pCurrentUARTSendHadler != NULL)
+ 8021d8e:	687b      	ldr	r3, [r7, #4]
+ 8021d90:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8021d94:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
+ 8021d96:	2b00      	cmp	r3, #0
+ 8021d98:	d051      	beq.n	8021e3e <GF_UART_Send_List_Send+0xe6>
+		{
+			//拷贝数据到相关的代码中，然后发送
+
+			//handler->CAN_Decode = handler->pCurrentCANSendHadler->CAN_Decode; //
+			memcpy(handler->Tx_Buf, handler->pCurrentUARTSendHadler->Tx_Buf,
+ 8021d9a:	687b      	ldr	r3, [r7, #4]
+ 8021d9c:	f603 0021 	addw	r0, r3, #2081	@ 0x821
+ 8021da0:	687b      	ldr	r3, [r7, #4]
+ 8021da2:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8021da6:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
+ 8021da8:	1d19      	adds	r1, r3, #4
+					handler->pCurrentUARTSendHadler->SendLength);
+ 8021daa:	687b      	ldr	r3, [r7, #4]
+ 8021dac:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8021db0:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
+ 8021db2:	881b      	ldrh	r3, [r3, #0]
+			memcpy(handler->Tx_Buf, handler->pCurrentUARTSendHadler->Tx_Buf,
+ 8021db4:	461a      	mov	r2, r3
+ 8021db6:	f01e fb01 	bl	80403bc <memcpy>
+			handler->SendList_Period =
+					handler->pCurrentUARTSendHadler->SendListTimePeriod;
+ 8021dba:	687b      	ldr	r3, [r7, #4]
+ 8021dbc:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8021dc0:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
+ 8021dc2:	885b      	ldrh	r3, [r3, #2]
+ 8021dc4:	461a      	mov	r2, r3
+			handler->SendList_Period =
+ 8021dc6:	687b      	ldr	r3, [r7, #4]
+ 8021dc8:	615a      	str	r2, [r3, #20]
+			handler->TxCount = handler->pCurrentUARTSendHadler->SendLength;
+ 8021dca:	687b      	ldr	r3, [r7, #4]
+ 8021dcc:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8021dd0:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
+ 8021dd2:	881a      	ldrh	r2, [r3, #0]
+ 8021dd4:	687b      	ldr	r3, [r7, #4]
+ 8021dd6:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8021dda:	845a      	strh	r2, [r3, #34]	@ 0x22
+			handler->UART_Tx(handler);
+ 8021ddc:	687b      	ldr	r3, [r7, #4]
+ 8021dde:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8021de2:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 8021de4:	6878      	ldr	r0, [r7, #4]
+ 8021de6:	4798      	blx	r3
+
+			if (handler->pCurrentUARTSendHadler->pNext != NULL)
+ 8021de8:	687b      	ldr	r3, [r7, #4]
+ 8021dea:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8021dee:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
+ 8021df0:	f8d3 3200 	ldr.w	r3, [r3, #512]	@ 0x200
+ 8021df4:	2b00      	cmp	r3, #0
+ 8021df6:	d014      	beq.n	8021e22 <GF_UART_Send_List_Send+0xca>
+			{
+				UARTSendHandler *temp = handler->pCurrentUARTSendHadler->pNext;
+ 8021df8:	687b      	ldr	r3, [r7, #4]
+ 8021dfa:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8021dfe:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
+ 8021e00:	f8d3 3200 	ldr.w	r3, [r3, #512]	@ 0x200
+ 8021e04:	60fb      	str	r3, [r7, #12]
+				free(handler->pCurrentUARTSendHadler); //清除内存
+ 8021e06:	687b      	ldr	r3, [r7, #4]
+ 8021e08:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8021e0c:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
+ 8021e0e:	4618      	mov	r0, r3
+ 8021e10:	f01e f8e8 	bl	803ffe4 <free>
+				handler->pCurrentUARTSendHadler = temp;
+ 8021e14:	687b      	ldr	r3, [r7, #4]
+ 8021e16:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8021e1a:	461a      	mov	r2, r3
+ 8021e1c:	68fb      	ldr	r3, [r7, #12]
+ 8021e1e:	6353      	str	r3, [r2, #52]	@ 0x34
+
+		}
+
+	}
+
+}
+ 8021e20:	e010      	b.n	8021e44 <GF_UART_Send_List_Send+0xec>
+				free(handler->pCurrentUARTSendHadler); //清除内存
+ 8021e22:	687b      	ldr	r3, [r7, #4]
+ 8021e24:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8021e28:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
+ 8021e2a:	4618      	mov	r0, r3
+ 8021e2c:	f01e f8da 	bl	803ffe4 <free>
+				handler->pCurrentUARTSendHadler = NULL;
+ 8021e30:	687b      	ldr	r3, [r7, #4]
+ 8021e32:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8021e36:	461a      	mov	r2, r3
+ 8021e38:	2300      	movs	r3, #0
+ 8021e3a:	6353      	str	r3, [r2, #52]	@ 0x34
+}
+ 8021e3c:	e002      	b.n	8021e44 <GF_UART_Send_List_Send+0xec>
+			handler->SendListExists = 0;
+ 8021e3e:	687b      	ldr	r3, [r7, #4]
+ 8021e40:	2200      	movs	r2, #0
+ 8021e42:	761a      	strb	r2, [r3, #24]
+}
+ 8021e44:	bf00      	nop
+ 8021e46:	3710      	adds	r7, #16
+ 8021e48:	46bd      	mov	sp, r7
+ 8021e4a:	bd80      	pop	{r7, pc}
+
+08021e4c <upper_Computer_UART_Handler_intialize>:
+#include "bsp_decode_command.h"
+void decode_command_from_computer(uint8_t *buffer, uint16_t length);
+struct UARTHandler *desulfurizer_message_UART_Handler;
+
+void upper_Computer_UART_Handler_intialize(struct UARTHandler *Handler)
+{
+ 8021e4c:	b480      	push	{r7}
+ 8021e4e:	b083      	sub	sp, #12
+ 8021e50:	af00      	add	r7, sp, #0
+ 8021e52:	6078      	str	r0, [r7, #4]
+
+	//LOG("desulfurizer_message_UART_Handler_intialize");
+	desulfurizer_message_UART_Handler = Handler;
+ 8021e54:	4a0d      	ldr	r2, [pc, #52]	@ (8021e8c <upper_Computer_UART_Handler_intialize+0x40>)
+ 8021e56:	687b      	ldr	r3, [r7, #4]
+ 8021e58:	6013      	str	r3, [r2, #0]
+	desulfurizer_message_UART_Handler->dispacherController->Dispacher_Enable=0;//不周期性发送
+ 8021e5a:	4b0c      	ldr	r3, [pc, #48]	@ (8021e8c <upper_Computer_UART_Handler_intialize+0x40>)
+ 8021e5c:	681b      	ldr	r3, [r3, #0]
+ 8021e5e:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8021e62:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 8021e64:	2200      	movs	r2, #0
+ 8021e66:	81da      	strh	r2, [r3, #14]
+	desulfurizer_message_UART_Handler->Wait_time=10;
+ 8021e68:	4b08      	ldr	r3, [pc, #32]	@ (8021e8c <upper_Computer_UART_Handler_intialize+0x40>)
+ 8021e6a:	681b      	ldr	r3, [r3, #0]
+ 8021e6c:	220a      	movs	r2, #10
+ 8021e6e:	609a      	str	r2, [r3, #8]
+	desulfurizer_message_UART_Handler->UART_Decode =
+ 8021e70:	4b06      	ldr	r3, [pc, #24]	@ (8021e8c <upper_Computer_UART_Handler_intialize+0x40>)
+ 8021e72:	681b      	ldr	r3, [r3, #0]
+ 8021e74:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8021e78:	461a      	mov	r2, r3
+ 8021e7a:	4b05      	ldr	r3, [pc, #20]	@ (8021e90 <upper_Computer_UART_Handler_intialize+0x44>)
+ 8021e7c:	6313      	str	r3, [r2, #48]	@ 0x30
+			decode_command_from_computer; //indicate that there is no need to listen
+	//desulfurizer_message_UART_Handler->DispacherCallPeriod=200;
+
+	//desulfurizer_message_UART_Handler->Add_Dispatcher_List(desulfurizer_message_UART_Handler,steering_set_angle);
+	}
+ 8021e7e:	bf00      	nop
+ 8021e80:	370c      	adds	r7, #12
+ 8021e82:	46bd      	mov	sp, r7
+ 8021e84:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8021e88:	4770      	bx	lr
+ 8021e8a:	bf00      	nop
+ 8021e8c:	24008eb4 	.word	0x24008eb4
+ 8021e90:	08021e95 	.word	0x08021e95
+
+08021e94 <decode_command_from_computer>:
+
+
+
+
+void decode_command_from_computer(uint8_t *buffer, uint16_t length)
+{
+ 8021e94:	b580      	push	{r7, lr}
+ 8021e96:	b082      	sub	sp, #8
+ 8021e98:	af00      	add	r7, sp, #0
+ 8021e9a:	6078      	str	r0, [r7, #4]
+ 8021e9c:	460b      	mov	r3, r1
+ 8021e9e:	807b      	strh	r3, [r7, #2]
+
+	if(*buffer==0x55 && *(buffer+1)==0x55 && length>=3)
+ 8021ea0:	687b      	ldr	r3, [r7, #4]
+ 8021ea2:	781b      	ldrb	r3, [r3, #0]
+ 8021ea4:	2b55      	cmp	r3, #85	@ 0x55
+ 8021ea6:	d111      	bne.n	8021ecc <decode_command_from_computer+0x38>
+ 8021ea8:	687b      	ldr	r3, [r7, #4]
+ 8021eaa:	3301      	adds	r3, #1
+ 8021eac:	781b      	ldrb	r3, [r3, #0]
+ 8021eae:	2b55      	cmp	r3, #85	@ 0x55
+ 8021eb0:	d10c      	bne.n	8021ecc <decode_command_from_computer+0x38>
+ 8021eb2:	887b      	ldrh	r3, [r7, #2]
+ 8021eb4:	2b02      	cmp	r3, #2
+ 8021eb6:	d909      	bls.n	8021ecc <decode_command_from_computer+0x38>
+	{
+		 decode_command_and_feedback(buffer+2,  length-2, 0,
+ 8021eb8:	687b      	ldr	r3, [r7, #4]
+ 8021eba:	1c98      	adds	r0, r3, #2
+ 8021ebc:	887b      	ldrh	r3, [r7, #2]
+ 8021ebe:	3b02      	subs	r3, #2
+ 8021ec0:	b299      	uxth	r1, r3
+ 8021ec2:	4b04      	ldr	r3, [pc, #16]	@ (8021ed4 <decode_command_from_computer+0x40>)
+ 8021ec4:	681b      	ldr	r3, [r3, #0]
+ 8021ec6:	2200      	movs	r2, #0
+ 8021ec8:	f000 fb50 	bl	802256c <decode_command_and_feedback>
+				 desulfurizer_message_UART_Handler);//0代表非mqtt
+	}
+
+}
+ 8021ecc:	bf00      	nop
+ 8021ece:	3708      	adds	r7, #8
+ 8021ed0:	46bd      	mov	sp, r7
+ 8021ed2:	bd80      	pop	{r7, pc}
+ 8021ed4:	24008eb4 	.word	0x24008eb4
+
+08021ed8 <client_setting_intialize>:
+
+struct UARTHandler *client_setting_Handler;
+DispacherController *client_setting_dispacher;
+
+void client_setting_intialize(struct UARTHandler *Handler)
+{
+ 8021ed8:	b590      	push	{r4, r7, lr}
+ 8021eda:	b083      	sub	sp, #12
+ 8021edc:	af00      	add	r7, sp, #0
+ 8021ede:	6078      	str	r0, [r7, #4]
+
+	client_setting_Handler = Handler;
+ 8021ee0:	4a27      	ldr	r2, [pc, #156]	@ (8021f80 <client_setting_intialize+0xa8>)
+ 8021ee2:	687b      	ldr	r3, [r7, #4]
+ 8021ee4:	6013      	str	r3, [r2, #0]
+	client_setting_Handler->Wait_time = 6; //  最低不要低于4；
+ 8021ee6:	4b26      	ldr	r3, [pc, #152]	@ (8021f80 <client_setting_intialize+0xa8>)
+ 8021ee8:	681b      	ldr	r3, [r3, #0]
+ 8021eea:	2206      	movs	r2, #6
+ 8021eec:	609a      	str	r2, [r3, #8]
+
+	client_setting_dispacher = Handler->dispacherController;
+ 8021eee:	687b      	ldr	r3, [r7, #4]
+ 8021ef0:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8021ef4:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 8021ef6:	4a23      	ldr	r2, [pc, #140]	@ (8021f84 <client_setting_intialize+0xac>)
+ 8021ef8:	6013      	str	r3, [r2, #0]
+	client_setting_dispacher->Add_Dispatcher_List(client_setting_dispacher,
+ 8021efa:	4b22      	ldr	r3, [pc, #136]	@ (8021f84 <client_setting_intialize+0xac>)
+ 8021efc:	681b      	ldr	r3, [r3, #0]
+ 8021efe:	691b      	ldr	r3, [r3, #16]
+ 8021f00:	4a20      	ldr	r2, [pc, #128]	@ (8021f84 <client_setting_intialize+0xac>)
+ 8021f02:	6812      	ldr	r2, [r2, #0]
+ 8021f04:	4920      	ldr	r1, [pc, #128]	@ (8021f88 <client_setting_intialize+0xb0>)
+ 8021f06:	4610      	mov	r0, r2
+ 8021f08:	4798      	blx	r3
+	        UpdateIV);
+	client_setting_dispacher->DispacherCallTime = 500;
+ 8021f0a:	4b1e      	ldr	r3, [pc, #120]	@ (8021f84 <client_setting_intialize+0xac>)
+ 8021f0c:	681b      	ldr	r3, [r3, #0]
+ 8021f0e:	f44f 72fa 	mov.w	r2, #500	@ 0x1f4
+ 8021f12:	815a      	strh	r2, [r3, #10]
+	client_setting_dispacher->Dispacher_Enable=1;//不周期性发送
+ 8021f14:	4b1b      	ldr	r3, [pc, #108]	@ (8021f84 <client_setting_intialize+0xac>)
+ 8021f16:	681b      	ldr	r3, [r3, #0]
+ 8021f18:	2201      	movs	r2, #1
+ 8021f1a:	81da      	strh	r2, [r3, #14]
+	LOG("client_setting_intialize");
+ 8021f1c:	4b1b      	ldr	r3, [pc, #108]	@ (8021f8c <client_setting_intialize+0xb4>)
+ 8021f1e:	781b      	ldrb	r3, [r3, #0]
+ 8021f20:	2b03      	cmp	r3, #3
+ 8021f22:	d918      	bls.n	8021f56 <client_setting_intialize+0x7e>
+ 8021f24:	2330      	movs	r3, #48	@ 0x30
+ 8021f26:	061a      	lsls	r2, r3, #24
+ 8021f28:	2330      	movs	r3, #48	@ 0x30
+ 8021f2a:	041b      	lsls	r3, r3, #16
+ 8021f2c:	431a      	orrs	r2, r3
+ 8021f2e:	2330      	movs	r3, #48	@ 0x30
+ 8021f30:	021b      	lsls	r3, r3, #8
+ 8021f32:	4313      	orrs	r3, r2
+ 8021f34:	2230      	movs	r2, #48	@ 0x30
+ 8021f36:	ea43 0102 	orr.w	r1, r3, r2
+ 8021f3a:	2344      	movs	r3, #68	@ 0x44
+ 8021f3c:	061a      	lsls	r2, r3, #24
+ 8021f3e:	2346      	movs	r3, #70	@ 0x46
+ 8021f40:	041b      	lsls	r3, r3, #16
+ 8021f42:	431a      	orrs	r2, r3
+ 8021f44:	234c      	movs	r3, #76	@ 0x4c
+ 8021f46:	021b      	lsls	r3, r3, #8
+ 8021f48:	4313      	orrs	r3, r2
+ 8021f4a:	2254      	movs	r2, #84	@ 0x54
+ 8021f4c:	431a      	orrs	r2, r3
+ 8021f4e:	4b10      	ldr	r3, [pc, #64]	@ (8021f90 <client_setting_intialize+0xb8>)
+ 8021f50:	2004      	movs	r0, #4
+ 8021f52:	f004 f96f 	bl	8026234 <DLTuc_LogOutVarArgs>
+
+
+	HardWareErrorController->Add_PCOMHardWare(HardWareErrorController,"MK32_Serial",0,ComError_MK32_Serial);
+ 8021f56:	4b0f      	ldr	r3, [pc, #60]	@ (8021f94 <client_setting_intialize+0xbc>)
+ 8021f58:	681b      	ldr	r3, [r3, #0]
+ 8021f5a:	68dc      	ldr	r4, [r3, #12]
+ 8021f5c:	4b0d      	ldr	r3, [pc, #52]	@ (8021f94 <client_setting_intialize+0xbc>)
+ 8021f5e:	6818      	ldr	r0, [r3, #0]
+ 8021f60:	2301      	movs	r3, #1
+ 8021f62:	2200      	movs	r2, #0
+ 8021f64:	490c      	ldr	r1, [pc, #48]	@ (8021f98 <client_setting_intialize+0xc0>)
+ 8021f66:	47a0      	blx	r4
+
+	client_setting_Handler->UART_Decode = decode_received_data_from_client; //indicate that there is no need to listen
+ 8021f68:	4b05      	ldr	r3, [pc, #20]	@ (8021f80 <client_setting_intialize+0xa8>)
+ 8021f6a:	681b      	ldr	r3, [r3, #0]
+ 8021f6c:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8021f70:	461a      	mov	r2, r3
+ 8021f72:	4b0a      	ldr	r3, [pc, #40]	@ (8021f9c <client_setting_intialize+0xc4>)
+ 8021f74:	6313      	str	r3, [r2, #48]	@ 0x30
+
+}
+ 8021f76:	bf00      	nop
+ 8021f78:	370c      	adds	r7, #12
+ 8021f7a:	46bd      	mov	sp, r7
+ 8021f7c:	bd90      	pop	{r4, r7, pc}
+ 8021f7e:	bf00      	nop
+ 8021f80:	24008eb8 	.word	0x24008eb8
+ 8021f84:	24008ebc 	.word	0x24008ebc
+ 8021f88:	08021fa1 	.word	0x08021fa1
+ 8021f8c:	24009110 	.word	0x24009110
+ 8021f90:	08040f28 	.word	0x08040f28
+ 8021f94:	24000618 	.word	0x24000618
+ 8021f98:	08040f44 	.word	0x08040f44
+ 8021f9c:	0802205d 	.word	0x0802205d
+
+08021fa0 <UpdateIV>:
+
+void UpdateIV()
+{
+ 8021fa0:	b580      	push	{r7, lr}
+ 8021fa2:	b086      	sub	sp, #24
+ 8021fa4:	af00      	add	r7, sp, #0
+
+	pb_ostream_t IV_o_stream = pb_ostream_from_buffer(
+	        &client_setting_Handler->Tx_Buf[2],
+ 8021fa6:	4b2a      	ldr	r3, [pc, #168]	@ (8022050 <UpdateIV+0xb0>)
+ 8021fa8:	681b      	ldr	r3, [r3, #0]
+ 8021faa:	f603 0123 	addw	r1, r3, #2083	@ 0x823
+	pb_ostream_t IV_o_stream = pb_ostream_from_buffer(
+ 8021fae:	463b      	mov	r3, r7
+ 8021fb0:	f240 72fe 	movw	r2, #2046	@ 0x7fe
+ 8021fb4:	4618      	mov	r0, r3
+ 8021fb6:	f002 fca1 	bl	80248fc <pb_ostream_from_buffer>
+	        sizeof(client_setting_Handler->Tx_Buf) - 2);
+	pb_encode(&IV_o_stream, IV_struct_define_fields, &IV);
+ 8021fba:	463b      	mov	r3, r7
+ 8021fbc:	4a25      	ldr	r2, [pc, #148]	@ (8022054 <UpdateIV+0xb4>)
+ 8021fbe:	4926      	ldr	r1, [pc, #152]	@ (8022058 <UpdateIV+0xb8>)
+ 8021fc0:	4618      	mov	r0, r3
+ 8021fc2:	f003 f908 	bl	80251d6 <pb_encode>
+
+	client_setting_Handler->Tx_Buf[0] = 0x55;
+ 8021fc6:	4b22      	ldr	r3, [pc, #136]	@ (8022050 <UpdateIV+0xb0>)
+ 8021fc8:	681b      	ldr	r3, [r3, #0]
+ 8021fca:	2255      	movs	r2, #85	@ 0x55
+ 8021fcc:	f883 2821 	strb.w	r2, [r3, #2081]	@ 0x821
+	client_setting_Handler->Tx_Buf[1] = 0x55;
+ 8021fd0:	4b1f      	ldr	r3, [pc, #124]	@ (8022050 <UpdateIV+0xb0>)
+ 8021fd2:	681b      	ldr	r3, [r3, #0]
+ 8021fd4:	2255      	movs	r2, #85	@ 0x55
+ 8021fd6:	f883 2822 	strb.w	r2, [r3, #2082]	@ 0x822
+	client_setting_Handler->TxCount = IV_o_stream.bytes_written + 4;
+ 8021fda:	68fb      	ldr	r3, [r7, #12]
+ 8021fdc:	b29a      	uxth	r2, r3
+ 8021fde:	4b1c      	ldr	r3, [pc, #112]	@ (8022050 <UpdateIV+0xb0>)
+ 8021fe0:	681b      	ldr	r3, [r3, #0]
+ 8021fe2:	3204      	adds	r2, #4
+ 8021fe4:	b292      	uxth	r2, r2
+ 8021fe6:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8021fea:	845a      	strh	r2, [r3, #34]	@ 0x22
+
+	uint16_t crc=MB_CRC16(&(client_setting_Handler->Tx_Buf[0]),  IV_o_stream.bytes_written + 2);
+ 8021fec:	4b18      	ldr	r3, [pc, #96]	@ (8022050 <UpdateIV+0xb0>)
+ 8021fee:	681b      	ldr	r3, [r3, #0]
+ 8021ff0:	f603 0221 	addw	r2, r3, #2081	@ 0x821
+ 8021ff4:	68fb      	ldr	r3, [r7, #12]
+ 8021ff6:	b29b      	uxth	r3, r3
+ 8021ff8:	3302      	adds	r3, #2
+ 8021ffa:	b29b      	uxth	r3, r3
+ 8021ffc:	4619      	mov	r1, r3
+ 8021ffe:	4610      	mov	r0, r2
+ 8022000:	f7ff f9e8 	bl	80213d4 <MB_CRC16>
+ 8022004:	4603      	mov	r3, r0
+ 8022006:	82fb      	strh	r3, [r7, #22]
+
+	client_setting_Handler->Tx_Buf[IV_o_stream.bytes_written + 2] = (crc>>8) &0xff;
+ 8022008:	8afb      	ldrh	r3, [r7, #22]
+ 802200a:	0a1b      	lsrs	r3, r3, #8
+ 802200c:	b299      	uxth	r1, r3
+ 802200e:	4b10      	ldr	r3, [pc, #64]	@ (8022050 <UpdateIV+0xb0>)
+ 8022010:	681a      	ldr	r2, [r3, #0]
+ 8022012:	68fb      	ldr	r3, [r7, #12]
+ 8022014:	3302      	adds	r3, #2
+ 8022016:	b2c9      	uxtb	r1, r1
+ 8022018:	4413      	add	r3, r2
+ 802201a:	460a      	mov	r2, r1
+ 802201c:	f883 2821 	strb.w	r2, [r3, #2081]	@ 0x821
+	client_setting_Handler->Tx_Buf[IV_o_stream.bytes_written + 3] =  crc & 0xff;;
+ 8022020:	4b0b      	ldr	r3, [pc, #44]	@ (8022050 <UpdateIV+0xb0>)
+ 8022022:	681a      	ldr	r2, [r3, #0]
+ 8022024:	68fb      	ldr	r3, [r7, #12]
+ 8022026:	3303      	adds	r3, #3
+ 8022028:	8af9      	ldrh	r1, [r7, #22]
+ 802202a:	b2c9      	uxtb	r1, r1
+ 802202c:	4413      	add	r3, r2
+ 802202e:	460a      	mov	r2, r1
+ 8022030:	f883 2821 	strb.w	r2, [r3, #2081]	@ 0x821
+
+
+	client_setting_Handler->UART_Tx(client_setting_Handler);
+ 8022034:	4b06      	ldr	r3, [pc, #24]	@ (8022050 <UpdateIV+0xb0>)
+ 8022036:	681b      	ldr	r3, [r3, #0]
+ 8022038:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 802203c:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 802203e:	4a04      	ldr	r2, [pc, #16]	@ (8022050 <UpdateIV+0xb0>)
+ 8022040:	6812      	ldr	r2, [r2, #0]
+ 8022042:	4610      	mov	r0, r2
+ 8022044:	4798      	blx	r3
+}
+ 8022046:	bf00      	nop
+ 8022048:	3718      	adds	r7, #24
+ 802204a:	46bd      	mov	sp, r7
+ 802204c:	bd80      	pop	{r7, pc}
+ 802204e:	bf00      	nop
+ 8022050:	24008eb8 	.word	0x24008eb8
+ 8022054:	240005e0 	.word	0x240005e0
+ 8022058:	08041748 	.word	0x08041748
+
+0802205c <decode_received_data_from_client>:
+
+void decode_received_data_from_client(uint8_t *buffer, uint16_t length)
+{
+ 802205c:	b5b0      	push	{r4, r5, r7, lr}
+ 802205e:	b0b8      	sub	sp, #224	@ 0xe0
+ 8022060:	af04      	add	r7, sp, #16
+ 8022062:	6178      	str	r0, [r7, #20]
+ 8022064:	460b      	mov	r3, r1
+ 8022066:	827b      	strh	r3, [r7, #18]
+	if(length>100)
+ 8022068:	8a7b      	ldrh	r3, [r7, #18]
+ 802206a:	2b64      	cmp	r3, #100	@ 0x64
+ 802206c:	f200 80b7 	bhi.w	80221de <decode_received_data_from_client+0x182>
+	{
+		return;
+	}
+	uint8_t data[100];
+	memcpy(data,buffer,length);
+ 8022070:	8a7a      	ldrh	r2, [r7, #18]
+ 8022072:	f107 0368 	add.w	r3, r7, #104	@ 0x68
+ 8022076:	6979      	ldr	r1, [r7, #20]
+ 8022078:	4618      	mov	r0, r3
+ 802207a:	f01e f99f 	bl	80403bc <memcpy>
+
+	//if (*buffer == 0x55 && *(buffer + 1) == 0x55 && length >= 4)
+	if (buffer[0] == 0x55 && buffer[1] == 0x55 && length >= 4)
+ 802207e:	697b      	ldr	r3, [r7, #20]
+ 8022080:	781b      	ldrb	r3, [r3, #0]
+ 8022082:	2b55      	cmp	r3, #85	@ 0x55
+ 8022084:	f040 80ac 	bne.w	80221e0 <decode_received_data_from_client+0x184>
+ 8022088:	697b      	ldr	r3, [r7, #20]
+ 802208a:	3301      	adds	r3, #1
+ 802208c:	781b      	ldrb	r3, [r3, #0]
+ 802208e:	2b55      	cmp	r3, #85	@ 0x55
+ 8022090:	f040 80a6 	bne.w	80221e0 <decode_received_data_from_client+0x184>
+ 8022094:	8a7b      	ldrh	r3, [r7, #18]
+ 8022096:	2b03      	cmp	r3, #3
+ 8022098:	f240 80a2 	bls.w	80221e0 <decode_received_data_from_client+0x184>
+	{
+		uint16_t crc_check = ((buffer[length - 1] << 8) | buffer[length - 2]);
+ 802209c:	8a7b      	ldrh	r3, [r7, #18]
+ 802209e:	3b01      	subs	r3, #1
+ 80220a0:	697a      	ldr	r2, [r7, #20]
+ 80220a2:	4413      	add	r3, r2
+ 80220a4:	781b      	ldrb	r3, [r3, #0]
+ 80220a6:	021b      	lsls	r3, r3, #8
+ 80220a8:	b21a      	sxth	r2, r3
+ 80220aa:	8a7b      	ldrh	r3, [r7, #18]
+ 80220ac:	3b02      	subs	r3, #2
+ 80220ae:	6979      	ldr	r1, [r7, #20]
+ 80220b0:	440b      	add	r3, r1
+ 80220b2:	781b      	ldrb	r3, [r3, #0]
+ 80220b4:	b21b      	sxth	r3, r3
+ 80220b6:	4313      	orrs	r3, r2
+ 80220b8:	b21b      	sxth	r3, r3
+ 80220ba:	f8a7 30ce 	strh.w	r3, [r7, #206]	@ 0xce
+		uint16_t crc_check1 = MB_CRC16(buffer, length - 2);
+ 80220be:	8a7b      	ldrh	r3, [r7, #18]
+ 80220c0:	3b02      	subs	r3, #2
+ 80220c2:	b29b      	uxth	r3, r3
+ 80220c4:	4619      	mov	r1, r3
+ 80220c6:	6978      	ldr	r0, [r7, #20]
+ 80220c8:	f7ff f984 	bl	80213d4 <MB_CRC16>
+ 80220cc:	4603      	mov	r3, r0
+ 80220ce:	f8a7 30cc 	strh.w	r3, [r7, #204]	@ 0xcc
+		/* CRC 校验正确 */
+		if (crc_check == MB_CRC16(buffer, length - 2))
+ 80220d2:	8a7b      	ldrh	r3, [r7, #18]
+ 80220d4:	3b02      	subs	r3, #2
+ 80220d6:	b29b      	uxth	r3, r3
+ 80220d8:	4619      	mov	r1, r3
+ 80220da:	6978      	ldr	r0, [r7, #20]
+ 80220dc:	f7ff f97a 	bl	80213d4 <MB_CRC16>
+ 80220e0:	4603      	mov	r3, r0
+ 80220e2:	461a      	mov	r2, r3
+ 80220e4:	f8b7 30ce 	ldrh.w	r3, [r7, #206]	@ 0xce
+ 80220e8:	4293      	cmp	r3, r2
+ 80220ea:	d154      	bne.n	8022196 <decode_received_data_from_client+0x13a>
+		{
+			//if (*(buffer + 2) == 0x01 && *(buffer + 3) == 0x01) //01 01 设置PV
+			if (buffer[2] == 0x01 && buffer[3] == 0x01) //01 01 设置PV
+ 80220ec:	697b      	ldr	r3, [r7, #20]
+ 80220ee:	3302      	adds	r3, #2
+ 80220f0:	781b      	ldrb	r3, [r3, #0]
+ 80220f2:	2b01      	cmp	r3, #1
+ 80220f4:	d146      	bne.n	8022184 <decode_received_data_from_client+0x128>
+ 80220f6:	697b      	ldr	r3, [r7, #20]
+ 80220f8:	3303      	adds	r3, #3
+ 80220fa:	781b      	ldrb	r3, [r3, #0]
+ 80220fc:	2b01      	cmp	r3, #1
+ 80220fe:	d133      	bne.n	8022168 <decode_received_data_from_client+0x10c>
+			{
+				PV_struct_define decoded_PV = PV_struct_define_init_default;
+ 8022100:	f107 0318 	add.w	r3, r7, #24
+ 8022104:	2240      	movs	r2, #64	@ 0x40
+ 8022106:	2100      	movs	r1, #0
+ 8022108:	4618      	mov	r0, r3
+ 802210a:	f01e f8ed 	bl	80402e8 <memset>
+				pb_istream_t i_pv_stream =
+ 802210e:	f107 0358 	add.w	r3, r7, #88	@ 0x58
+ 8022112:	2200      	movs	r2, #0
+ 8022114:	601a      	str	r2, [r3, #0]
+ 8022116:	605a      	str	r2, [r3, #4]
+ 8022118:	609a      	str	r2, [r3, #8]
+ 802211a:	60da      	str	r2, [r3, #12]
+				{ 0 };
+
+				i_pv_stream = pb_istream_from_buffer(&buffer[4], length - 4);
+ 802211c:	697b      	ldr	r3, [r7, #20]
+ 802211e:	1d19      	adds	r1, r3, #4
+ 8022120:	8a7b      	ldrh	r3, [r7, #18]
+ 8022122:	3b04      	subs	r3, #4
+ 8022124:	461a      	mov	r2, r3
+ 8022126:	463b      	mov	r3, r7
+ 8022128:	4618      	mov	r0, r3
+ 802212a:	f000 fedb 	bl	8022ee4 <pb_istream_from_buffer>
+ 802212e:	f107 0458 	add.w	r4, r7, #88	@ 0x58
+ 8022132:	463b      	mov	r3, r7
+ 8022134:	cb0f      	ldmia	r3, {r0, r1, r2, r3}
+ 8022136:	e884 000f 	stmia.w	r4, {r0, r1, r2, r3}
+				pb_decode(&i_pv_stream, PV_struct_define_fields, &decoded_PV);
+ 802213a:	f107 0218 	add.w	r2, r7, #24
+ 802213e:	f107 0358 	add.w	r3, r7, #88	@ 0x58
+ 8022142:	4929      	ldr	r1, [pc, #164]	@ (80221e8 <decode_received_data_from_client+0x18c>)
+ 8022144:	4618      	mov	r0, r3
+ 8022146:	f002 f807 	bl	8024158 <pb_decode>
+				//将CV写入EEPROM
+				//CV_struct_define saved_cV = GF_BSP_EEPROM_Get_CV();
+				CV.PV = decoded_PV;
+ 802214a:	4b28      	ldr	r3, [pc, #160]	@ (80221ec <decode_received_data_from_client+0x190>)
+ 802214c:	1d1c      	adds	r4, r3, #4
+ 802214e:	f107 0518 	add.w	r5, r7, #24
+ 8022152:	cd0f      	ldmia	r5!, {r0, r1, r2, r3}
+ 8022154:	c40f      	stmia	r4!, {r0, r1, r2, r3}
+ 8022156:	cd0f      	ldmia	r5!, {r0, r1, r2, r3}
+ 8022158:	c40f      	stmia	r4!, {r0, r1, r2, r3}
+ 802215a:	cd0f      	ldmia	r5!, {r0, r1, r2, r3}
+ 802215c:	c40f      	stmia	r4!, {r0, r1, r2, r3}
+ 802215e:	e895 000f 	ldmia.w	r5, {r0, r1, r2, r3}
+ 8022162:	e884 000f 	stmia.w	r4, {r0, r1, r2, r3}
+ 8022166:	e00d      	b.n	8022184 <decode_received_data_from_client+0x128>
+				//GF_BSP_EEPROM_Set_CV(CV);
+			}
+			else if (*(buffer + 2) == 0x02 && *(buffer + 3) == 0x01) //设置PV
+ 8022168:	697b      	ldr	r3, [r7, #20]
+ 802216a:	3302      	adds	r3, #2
+ 802216c:	781b      	ldrb	r3, [r3, #0]
+ 802216e:	2b02      	cmp	r3, #2
+ 8022170:	d108      	bne.n	8022184 <decode_received_data_from_client+0x128>
+ 8022172:	697b      	ldr	r3, [r7, #20]
+ 8022174:	3303      	adds	r3, #3
+ 8022176:	781b      	ldrb	r3, [r3, #0]
+ 8022178:	2b01      	cmp	r3, #1
+ 802217a:	d003      	beq.n	8022184 <decode_received_data_from_client+0x128>
+			{
+
+			}
+			else if (*(buffer + 2) == 0x03 && *(buffer + 3) == 0x01) //返回IV
+ 802217c:	697b      	ldr	r3, [r7, #20]
+ 802217e:	3302      	adds	r3, #2
+ 8022180:	781b      	ldrb	r3, [r3, #0]
+ 8022182:	2b03      	cmp	r3, #3
+
+			}
+			else
+			{
+			}
+			HardWareErrorController->Set_PCOMHardWare(HardWareErrorController, "MK32_Serial", 1);
+ 8022184:	4b1a      	ldr	r3, [pc, #104]	@ (80221f0 <decode_received_data_from_client+0x194>)
+ 8022186:	681b      	ldr	r3, [r3, #0]
+ 8022188:	695b      	ldr	r3, [r3, #20]
+ 802218a:	4a19      	ldr	r2, [pc, #100]	@ (80221f0 <decode_received_data_from_client+0x194>)
+ 802218c:	6810      	ldr	r0, [r2, #0]
+ 802218e:	2201      	movs	r2, #1
+ 8022190:	4918      	ldr	r1, [pc, #96]	@ (80221f4 <decode_received_data_from_client+0x198>)
+ 8022192:	4798      	blx	r3
+ 8022194:	e024      	b.n	80221e0 <decode_received_data_from_client+0x184>
+		}
+		else
+		{
+			//Decode Error；
+			//log_error("wire sensor decoding failed");
+			LOGFF(DL_ERROR, "androidd decoding failed");
+ 8022196:	4b18      	ldr	r3, [pc, #96]	@ (80221f8 <decode_received_data_from_client+0x19c>)
+ 8022198:	781b      	ldrb	r3, [r3, #0]
+ 802219a:	2b01      	cmp	r3, #1
+ 802219c:	d920      	bls.n	80221e0 <decode_received_data_from_client+0x184>
+ 802219e:	2330      	movs	r3, #48	@ 0x30
+ 80221a0:	061a      	lsls	r2, r3, #24
+ 80221a2:	2330      	movs	r3, #48	@ 0x30
+ 80221a4:	041b      	lsls	r3, r3, #16
+ 80221a6:	431a      	orrs	r2, r3
+ 80221a8:	2330      	movs	r3, #48	@ 0x30
+ 80221aa:	021b      	lsls	r3, r3, #8
+ 80221ac:	4313      	orrs	r3, r2
+ 80221ae:	2230      	movs	r2, #48	@ 0x30
+ 80221b0:	ea43 0102 	orr.w	r1, r3, r2
+ 80221b4:	2344      	movs	r3, #68	@ 0x44
+ 80221b6:	061a      	lsls	r2, r3, #24
+ 80221b8:	2346      	movs	r3, #70	@ 0x46
+ 80221ba:	041b      	lsls	r3, r3, #16
+ 80221bc:	431a      	orrs	r2, r3
+ 80221be:	234c      	movs	r3, #76	@ 0x4c
+ 80221c0:	021b      	lsls	r3, r3, #8
+ 80221c2:	4313      	orrs	r3, r2
+ 80221c4:	2254      	movs	r2, #84	@ 0x54
+ 80221c6:	431a      	orrs	r2, r3
+ 80221c8:	4b0c      	ldr	r3, [pc, #48]	@ (80221fc <decode_received_data_from_client+0x1a0>)
+ 80221ca:	9302      	str	r3, [sp, #8]
+ 80221cc:	236d      	movs	r3, #109	@ 0x6d
+ 80221ce:	9301      	str	r3, [sp, #4]
+ 80221d0:	4b0b      	ldr	r3, [pc, #44]	@ (8022200 <decode_received_data_from_client+0x1a4>)
+ 80221d2:	9300      	str	r3, [sp, #0]
+ 80221d4:	4b0b      	ldr	r3, [pc, #44]	@ (8022204 <decode_received_data_from_client+0x1a8>)
+ 80221d6:	2002      	movs	r0, #2
+ 80221d8:	f004 f82c 	bl	8026234 <DLTuc_LogOutVarArgs>
+ 80221dc:	e000      	b.n	80221e0 <decode_received_data_from_client+0x184>
+		return;
+ 80221de:	bf00      	nop
+
+		}
+
+	}
+
+}
+ 80221e0:	37d0      	adds	r7, #208	@ 0xd0
+ 80221e2:	46bd      	mov	sp, r7
+ 80221e4:	bdb0      	pop	{r4, r5, r7, pc}
+ 80221e6:	bf00      	nop
+ 80221e8:	080417a8 	.word	0x080417a8
+ 80221ec:	240002a0 	.word	0x240002a0
+ 80221f0:	24000618 	.word	0x24000618
+ 80221f4:	08040f44 	.word	0x08040f44
+ 80221f8:	24009110 	.word	0x24009110
+ 80221fc:	08041be4 	.word	0x08041be4
+ 8022200:	08040f88 	.word	0x08040f88
+ 8022204:	08040f50 	.word	0x08040f50
+
+08022208 <Dispatch_t>:
+#include <stdlib.h>
+#include "DLTuc.h"
+#include "BHBF_ROBOT.h"
+
+void Dispatch_t(DispacherController *uartHandler)
+{
+ 8022208:	b580      	push	{r7, lr}
+ 802220a:	b082      	sub	sp, #8
+ 802220c:	af00      	add	r7, sp, #0
+ 802220e:	6078      	str	r0, [r7, #4]
+//2ms
+
+	if (uartHandler->Dispacher_Enable == 1)
+ 8022210:	687b      	ldr	r3, [r7, #4]
+ 8022212:	89db      	ldrh	r3, [r3, #14]
+ 8022214:	2b01      	cmp	r3, #1
+ 8022216:	d12c      	bne.n	8022272 <Dispatch_t+0x6a>
+	{
+		if (uartHandler->DispacherNumber > 0) //列表中有数据
+ 8022218:	687b      	ldr	r3, [r7, #4]
+ 802221a:	891b      	ldrh	r3, [r3, #8]
+ 802221c:	2b00      	cmp	r3, #0
+ 802221e:	d028      	beq.n	8022272 <Dispatch_t+0x6a>
+		{
+			uartHandler->Dispacher_Counter++;
+ 8022220:	687b      	ldr	r3, [r7, #4]
+ 8022222:	899b      	ldrh	r3, [r3, #12]
+ 8022224:	3301      	adds	r3, #1
+ 8022226:	b29a      	uxth	r2, r3
+ 8022228:	687b      	ldr	r3, [r7, #4]
+ 802222a:	819a      	strh	r2, [r3, #12]
+
+			if (uartHandler->Dispacher_Counter
+ 802222c:	687b      	ldr	r3, [r7, #4]
+ 802222e:	899b      	ldrh	r3, [r3, #12]
+ 8022230:	461a      	mov	r2, r3
+					>= uartHandler->DispacherCallTime / 2
+ 8022232:	687b      	ldr	r3, [r7, #4]
+ 8022234:	895b      	ldrh	r3, [r3, #10]
+ 8022236:	085b      	lsrs	r3, r3, #1
+ 8022238:	b29b      	uxth	r3, r3
+ 802223a:	4619      	mov	r1, r3
+							/ (uartHandler->DispacherNumber)) //多长时间运行一次
+ 802223c:	687b      	ldr	r3, [r7, #4]
+ 802223e:	891b      	ldrh	r3, [r3, #8]
+ 8022240:	fb91 f3f3 	sdiv	r3, r1, r3
+			if (uartHandler->Dispacher_Counter
+ 8022244:	429a      	cmp	r2, r3
+ 8022246:	db14      	blt.n	8022272 <Dispatch_t+0x6a>
+			{
+				uartHandler->Dispacher_Counter = 0;
+ 8022248:	687b      	ldr	r3, [r7, #4]
+ 802224a:	2200      	movs	r2, #0
+ 802224c:	819a      	strh	r2, [r3, #12]
+				if (uartHandler->pHead != NULL
+ 802224e:	687b      	ldr	r3, [r7, #4]
+ 8022250:	681b      	ldr	r3, [r3, #0]
+ 8022252:	2b00      	cmp	r3, #0
+ 8022254:	d00d      	beq.n	8022272 <Dispatch_t+0x6a>
+						&& uartHandler->pHead->pNext != NULL)
+ 8022256:	687b      	ldr	r3, [r7, #4]
+ 8022258:	681b      	ldr	r3, [r3, #0]
+ 802225a:	685b      	ldr	r3, [r3, #4]
+ 802225c:	2b00      	cmp	r3, #0
+ 802225e:	d008      	beq.n	8022272 <Dispatch_t+0x6a>
+				{
+
+					uartHandler->pHead->dispache();
+ 8022260:	687b      	ldr	r3, [r7, #4]
+ 8022262:	681b      	ldr	r3, [r3, #0]
+ 8022264:	681b      	ldr	r3, [r3, #0]
+ 8022266:	4798      	blx	r3
+
+					uartHandler->pHead = uartHandler->pHead->pNext;
+ 8022268:	687b      	ldr	r3, [r7, #4]
+ 802226a:	681b      	ldr	r3, [r3, #0]
+ 802226c:	685a      	ldr	r2, [r3, #4]
+ 802226e:	687b      	ldr	r3, [r7, #4]
+ 8022270:	601a      	str	r2, [r3, #0]
+				}
+			}
+		}
+
+	}
+}
+ 8022272:	bf00      	nop
+ 8022274:	3708      	adds	r7, #8
+ 8022276:	46bd      	mov	sp, r7
+ 8022278:	bd80      	pop	{r7, pc}
+
+0802227a <Dispatcher_List_Add_t>:
+
+void Dispatcher_List_Add_t(DispacherController *uartHandler,
+		void (*dispache)(void))
+{
+ 802227a:	b580      	push	{r7, lr}
+ 802227c:	b084      	sub	sp, #16
+ 802227e:	af00      	add	r7, sp, #0
+ 8022280:	6078      	str	r0, [r7, #4]
+ 8022282:	6039      	str	r1, [r7, #0]
+	Dispatcher *pTmp = NULL; //临时指针2
+ 8022284:	2300      	movs	r3, #0
+ 8022286:	60fb      	str	r3, [r7, #12]
+
+	if (uartHandler->pHead == NULL && uartHandler->pTail == NULL) //头尾部都为空
+ 8022288:	687b      	ldr	r3, [r7, #4]
+ 802228a:	681b      	ldr	r3, [r3, #0]
+ 802228c:	2b00      	cmp	r3, #0
+ 802228e:	d127      	bne.n	80222e0 <Dispatcher_List_Add_t+0x66>
+ 8022290:	687b      	ldr	r3, [r7, #4]
+ 8022292:	685b      	ldr	r3, [r3, #4]
+ 8022294:	2b00      	cmp	r3, #0
+ 8022296:	d123      	bne.n	80222e0 <Dispatcher_List_Add_t+0x66>
+	{
+		uartHandler->pHead = uartHandler->pTail = (Dispatcher*) malloc(
+ 8022298:	2008      	movs	r0, #8
+ 802229a:	f01d fe9b 	bl	803ffd4 <malloc>
+ 802229e:	4603      	mov	r3, r0
+ 80222a0:	461a      	mov	r2, r3
+ 80222a2:	687b      	ldr	r3, [r7, #4]
+ 80222a4:	605a      	str	r2, [r3, #4]
+ 80222a6:	687b      	ldr	r3, [r7, #4]
+ 80222a8:	685a      	ldr	r2, [r3, #4]
+ 80222aa:	687b      	ldr	r3, [r7, #4]
+ 80222ac:	601a      	str	r2, [r3, #0]
+				sizeof(Dispatcher));
+		uartHandler->pHead->dispache = dispache;
+ 80222ae:	687b      	ldr	r3, [r7, #4]
+ 80222b0:	681b      	ldr	r3, [r3, #0]
+ 80222b2:	683a      	ldr	r2, [r7, #0]
+ 80222b4:	601a      	str	r2, [r3, #0]
+		uartHandler->pTail->dispache = dispache;
+ 80222b6:	687b      	ldr	r3, [r7, #4]
+ 80222b8:	685b      	ldr	r3, [r3, #4]
+ 80222ba:	683a      	ldr	r2, [r7, #0]
+ 80222bc:	601a      	str	r2, [r3, #0]
+
+
+
+		uartHandler->pHead->pNext = uartHandler->pTail;
+ 80222be:	687b      	ldr	r3, [r7, #4]
+ 80222c0:	681b      	ldr	r3, [r3, #0]
+ 80222c2:	687a      	ldr	r2, [r7, #4]
+ 80222c4:	6852      	ldr	r2, [r2, #4]
+ 80222c6:	605a      	str	r2, [r3, #4]
+
+		uartHandler->pTail->pNext = uartHandler->pHead;
+ 80222c8:	687b      	ldr	r3, [r7, #4]
+ 80222ca:	685b      	ldr	r3, [r3, #4]
+ 80222cc:	687a      	ldr	r2, [r7, #4]
+ 80222ce:	6812      	ldr	r2, [r2, #0]
+ 80222d0:	605a      	str	r2, [r3, #4]
+		uartHandler->DispacherNumber++;
+ 80222d2:	687b      	ldr	r3, [r7, #4]
+ 80222d4:	891b      	ldrh	r3, [r3, #8]
+ 80222d6:	3301      	adds	r3, #1
+ 80222d8:	b29a      	uxth	r2, r3
+ 80222da:	687b      	ldr	r3, [r7, #4]
+ 80222dc:	811a      	strh	r2, [r3, #8]
+ 80222de:	e019      	b.n	8022314 <Dispatcher_List_Add_t+0x9a>
+	} else
+	{
+		//临时指针2用于逐个申请内存
+		pTmp = (Dispatcher*) malloc(sizeof(Dispatcher));
+ 80222e0:	2008      	movs	r0, #8
+ 80222e2:	f01d fe77 	bl	803ffd4 <malloc>
+ 80222e6:	4603      	mov	r3, r0
+ 80222e8:	60fb      	str	r3, [r7, #12]
+		pTmp->dispache = dispache;
+ 80222ea:	68fb      	ldr	r3, [r7, #12]
+ 80222ec:	683a      	ldr	r2, [r7, #0]
+ 80222ee:	601a      	str	r2, [r3, #0]
+
+
+		pTmp->pNext = uartHandler->pHead; //set the new dispatcher .next to the header, thus make it a circle
+ 80222f0:	687b      	ldr	r3, [r7, #4]
+ 80222f2:	681a      	ldr	r2, [r3, #0]
+ 80222f4:	68fb      	ldr	r3, [r7, #12]
+ 80222f6:	605a      	str	r2, [r3, #4]
+
+		//临时指针1的next指向刚分配内存的临时指针2
+		uartHandler->pTail->pNext = pTmp;
+ 80222f8:	687b      	ldr	r3, [r7, #4]
+ 80222fa:	685b      	ldr	r3, [r3, #4]
+ 80222fc:	68fa      	ldr	r2, [r7, #12]
+ 80222fe:	605a      	str	r2, [r3, #4]
+
+		uartHandler->pTail = pTmp; //set pTail the last node of this ring
+ 8022300:	687b      	ldr	r3, [r7, #4]
+ 8022302:	68fa      	ldr	r2, [r7, #12]
+ 8022304:	605a      	str	r2, [r3, #4]
+		uartHandler->DispacherNumber++;
+ 8022306:	687b      	ldr	r3, [r7, #4]
+ 8022308:	891b      	ldrh	r3, [r3, #8]
+ 802230a:	3301      	adds	r3, #1
+ 802230c:	b29a      	uxth	r2, r3
+ 802230e:	687b      	ldr	r3, [r7, #4]
+ 8022310:	811a      	strh	r2, [r3, #8]
+	}
+}
+ 8022312:	bf00      	nop
+ 8022314:	bf00      	nop
+ 8022316:	3710      	adds	r7, #16
+ 8022318:	46bd      	mov	sp, r7
+ 802231a:	bd80      	pop	{r7, pc}
+
+0802231c <ComHardWare_List_Add_t>:
+
+void ComHardWare_List_Add_t(HardWareController *uartHandler, char *name,
+		char value,uint32_t bitFlag)
+{
+ 802231c:	b590      	push	{r4, r7, lr}
+ 802231e:	b087      	sub	sp, #28
+ 8022320:	af00      	add	r7, sp, #0
+ 8022322:	60f8      	str	r0, [r7, #12]
+ 8022324:	60b9      	str	r1, [r7, #8]
+ 8022326:	603b      	str	r3, [r7, #0]
+ 8022328:	4613      	mov	r3, r2
+ 802232a:	71fb      	strb	r3, [r7, #7]
+
+	ComHardWare *pTmp = NULL; //临时指针2
+ 802232c:	2300      	movs	r3, #0
+ 802232e:	617b      	str	r3, [r7, #20]
+	if (uartHandler->pComHWHead == NULL && uartHandler->pComHWTail == NULL) //头尾部都为空
+ 8022330:	68fb      	ldr	r3, [r7, #12]
+ 8022332:	681b      	ldr	r3, [r3, #0]
+ 8022334:	2b00      	cmp	r3, #0
+ 8022336:	d12f      	bne.n	8022398 <ComHardWare_List_Add_t+0x7c>
+ 8022338:	68fb      	ldr	r3, [r7, #12]
+ 802233a:	685b      	ldr	r3, [r3, #4]
+ 802233c:	2b00      	cmp	r3, #0
+ 802233e:	d12b      	bne.n	8022398 <ComHardWare_List_Add_t+0x7c>
+	{
+		uartHandler->pComHWHead = uartHandler->pComHWTail =
+				(ComHardWare*) malloc(sizeof(ComHardWare));
+ 8022340:	203c      	movs	r0, #60	@ 0x3c
+ 8022342:	f01d fe47 	bl	803ffd4 <malloc>
+ 8022346:	4603      	mov	r3, r0
+ 8022348:	461a      	mov	r2, r3
+		uartHandler->pComHWHead = uartHandler->pComHWTail =
+ 802234a:	68fb      	ldr	r3, [r7, #12]
+ 802234c:	605a      	str	r2, [r3, #4]
+ 802234e:	68fb      	ldr	r3, [r7, #12]
+ 8022350:	685a      	ldr	r2, [r3, #4]
+ 8022352:	68fb      	ldr	r3, [r7, #12]
+ 8022354:	601a      	str	r2, [r3, #0]
+
+		memset(uartHandler->pComHWHead->Name, '\0',
+ 8022356:	68fb      	ldr	r3, [r7, #12]
+ 8022358:	681b      	ldr	r3, [r3, #0]
+ 802235a:	2232      	movs	r2, #50	@ 0x32
+ 802235c:	2100      	movs	r1, #0
+ 802235e:	4618      	mov	r0, r3
+ 8022360:	f01d ffc2 	bl	80402e8 <memset>
+				sizeof(uartHandler->pComHWHead->Name));
+		memcpy(uartHandler->pComHWHead->Name, name, strlen(name));
+ 8022364:	68fb      	ldr	r3, [r7, #12]
+ 8022366:	681b      	ldr	r3, [r3, #0]
+ 8022368:	461c      	mov	r4, r3
+ 802236a:	68b8      	ldr	r0, [r7, #8]
+ 802236c:	f7fd ffc2 	bl	80202f4 <strlen>
+ 8022370:	4603      	mov	r3, r0
+ 8022372:	461a      	mov	r2, r3
+ 8022374:	68b9      	ldr	r1, [r7, #8]
+ 8022376:	4620      	mov	r0, r4
+ 8022378:	f01e f820 	bl	80403bc <memcpy>
+		uartHandler->pComHWHead->IsOnline = value;
+ 802237c:	68fb      	ldr	r3, [r7, #12]
+ 802237e:	681b      	ldr	r3, [r3, #0]
+ 8022380:	79fa      	ldrb	r2, [r7, #7]
+ 8022382:	f883 2032 	strb.w	r2, [r3, #50]	@ 0x32
+		uartHandler->pComHWHead->BitFlag = bitFlag;
+ 8022386:	68fb      	ldr	r3, [r7, #12]
+ 8022388:	681b      	ldr	r3, [r3, #0]
+ 802238a:	683a      	ldr	r2, [r7, #0]
+ 802238c:	635a      	str	r2, [r3, #52]	@ 0x34
+		uartHandler->pComHWHead->pNext = NULL;
+ 802238e:	68fb      	ldr	r3, [r7, #12]
+ 8022390:	681b      	ldr	r3, [r3, #0]
+ 8022392:	2200      	movs	r2, #0
+ 8022394:	639a      	str	r2, [r3, #56]	@ 0x38
+ 8022396:	e026      	b.n	80223e6 <ComHardWare_List_Add_t+0xca>
+	} else
+	{
+
+		pTmp = (ComHardWare*) malloc(sizeof(ComHardWare));
+ 8022398:	203c      	movs	r0, #60	@ 0x3c
+ 802239a:	f01d fe1b 	bl	803ffd4 <malloc>
+ 802239e:	4603      	mov	r3, r0
+ 80223a0:	617b      	str	r3, [r7, #20]
+		memset(pTmp->Name, '\0', sizeof(pTmp->Name));
+ 80223a2:	697b      	ldr	r3, [r7, #20]
+ 80223a4:	2232      	movs	r2, #50	@ 0x32
+ 80223a6:	2100      	movs	r1, #0
+ 80223a8:	4618      	mov	r0, r3
+ 80223aa:	f01d ff9d 	bl	80402e8 <memset>
+		memcpy(pTmp->Name, name, strlen(name));
+ 80223ae:	697c      	ldr	r4, [r7, #20]
+ 80223b0:	68b8      	ldr	r0, [r7, #8]
+ 80223b2:	f7fd ff9f 	bl	80202f4 <strlen>
+ 80223b6:	4603      	mov	r3, r0
+ 80223b8:	461a      	mov	r2, r3
+ 80223ba:	68b9      	ldr	r1, [r7, #8]
+ 80223bc:	4620      	mov	r0, r4
+ 80223be:	f01d fffd 	bl	80403bc <memcpy>
+
+		pTmp->BitFlag = bitFlag;
+ 80223c2:	697b      	ldr	r3, [r7, #20]
+ 80223c4:	683a      	ldr	r2, [r7, #0]
+ 80223c6:	635a      	str	r2, [r3, #52]	@ 0x34
+		pTmp->IsOnline = value;
+ 80223c8:	697b      	ldr	r3, [r7, #20]
+ 80223ca:	79fa      	ldrb	r2, [r7, #7]
+ 80223cc:	f883 2032 	strb.w	r2, [r3, #50]	@ 0x32
+		pTmp->pNext = NULL; //set the new dispatcher .next to the header, thus make it a circle
+ 80223d0:	697b      	ldr	r3, [r7, #20]
+ 80223d2:	2200      	movs	r2, #0
+ 80223d4:	639a      	str	r2, [r3, #56]	@ 0x38
+		uartHandler->pComHWTail->pNext = pTmp;
+ 80223d6:	68fb      	ldr	r3, [r7, #12]
+ 80223d8:	685b      	ldr	r3, [r3, #4]
+ 80223da:	697a      	ldr	r2, [r7, #20]
+ 80223dc:	639a      	str	r2, [r3, #56]	@ 0x38
+		uartHandler->pComHWTail = pTmp;
+ 80223de:	68fb      	ldr	r3, [r7, #12]
+ 80223e0:	697a      	ldr	r2, [r7, #20]
+ 80223e2:	605a      	str	r2, [r3, #4]
+
+	}
+
+}
+ 80223e4:	bf00      	nop
+ 80223e6:	bf00      	nop
+ 80223e8:	371c      	adds	r7, #28
+ 80223ea:	46bd      	mov	sp, r7
+ 80223ec:	bd90      	pop	{r4, r7, pc}
+	...
+
+080223f0 <PCOMHardWare_Check_t>:
+char str1[50] = "\0";
+void PCOMHardWare_Check_t(HardWareController *uartHandler)
+{
+ 80223f0:	b590      	push	{r4, r7, lr}
+ 80223f2:	b089      	sub	sp, #36	@ 0x24
+ 80223f4:	af04      	add	r7, sp, #16
+ 80223f6:	6078      	str	r0, [r7, #4]
+	uartHandler->HardWare_Check_Counter++;
+ 80223f8:	687b      	ldr	r3, [r7, #4]
+ 80223fa:	891b      	ldrh	r3, [r3, #8]
+ 80223fc:	3301      	adds	r3, #1
+ 80223fe:	b29a      	uxth	r2, r3
+ 8022400:	687b      	ldr	r3, [r7, #4]
+ 8022402:	811a      	strh	r2, [r3, #8]
+//	if (uartHandler->HardWare_Check_Counter*2
+//			>= uartHandler->DispacherCallTime * 6)	//make sure every
+	if (uartHandler->HardWare_Check_Counter * 2 >= uartHandler->DispacherCallTime)	//make sure every
+ 8022404:	687b      	ldr	r3, [r7, #4]
+ 8022406:	891b      	ldrh	r3, [r3, #8]
+ 8022408:	005b      	lsls	r3, r3, #1
+ 802240a:	687a      	ldr	r2, [r7, #4]
+ 802240c:	8952      	ldrh	r2, [r2, #10]
+ 802240e:	4293      	cmp	r3, r2
+ 8022410:	db70      	blt.n	80224f4 <PCOMHardWare_Check_t+0x104>
+	{
+		ComHardWare *ptr = uartHandler->pComHWHead;
+ 8022412:	687b      	ldr	r3, [r7, #4]
+ 8022414:	681b      	ldr	r3, [r3, #0]
+ 8022416:	60fb      	str	r3, [r7, #12]
+
+		if (!ptr)
+ 8022418:	68fb      	ldr	r3, [r7, #12]
+ 802241a:	2b00      	cmp	r3, #0
+ 802241c:	d103      	bne.n	8022426 <PCOMHardWare_Check_t+0x36>
+		{
+			uartHandler->HardWare_Check_Counter = 0;
+ 802241e:	687b      	ldr	r3, [r7, #4]
+ 8022420:	2200      	movs	r2, #0
+ 8022422:	811a      	strh	r2, [r3, #8]
+			//printf("链表为空\n");
+			return;
+ 8022424:	e066      	b.n	80224f4 <PCOMHardWare_Check_t+0x104>
+		}
+		char IsAbnornalStatus = 0;
+ 8022426:	2300      	movs	r3, #0
+ 8022428:	72fb      	strb	r3, [r7, #11]
+
+		//check invalid state
+		while (ptr != NULL)
+ 802242a:	e04f      	b.n	80224cc <PCOMHardWare_Check_t+0xdc>
+		{
+			if (ptr->IsOnline != 1)
+ 802242c:	68fb      	ldr	r3, [r7, #12]
+ 802242e:	f893 3032 	ldrb.w	r3, [r3, #50]	@ 0x32
+ 8022432:	2b01      	cmp	r3, #1
+ 8022434:	d03f      	beq.n	80224b6 <PCOMHardWare_Check_t+0xc6>
+			{
+				memset(str1, '\0', 50);
+ 8022436:	2232      	movs	r2, #50	@ 0x32
+ 8022438:	2100      	movs	r1, #0
+ 802243a:	4830      	ldr	r0, [pc, #192]	@ (80224fc <PCOMHardWare_Check_t+0x10c>)
+ 802243c:	f01d ff54 	bl	80402e8 <memset>
+				memcpy(str1, ptr->Name, strlen(ptr->Name));
+ 8022440:	68fc      	ldr	r4, [r7, #12]
+ 8022442:	68fb      	ldr	r3, [r7, #12]
+ 8022444:	4618      	mov	r0, r3
+ 8022446:	f7fd ff55 	bl	80202f4 <strlen>
+ 802244a:	4603      	mov	r3, r0
+ 802244c:	461a      	mov	r2, r3
+ 802244e:	4621      	mov	r1, r4
+ 8022450:	482a      	ldr	r0, [pc, #168]	@ (80224fc <PCOMHardWare_Check_t+0x10c>)
+ 8022452:	f01d ffb3 	bl	80403bc <memcpy>
+				LOGFF(DL_ERROR, "connecting Error %s", ptr->Name);
+ 8022456:	4b2a      	ldr	r3, [pc, #168]	@ (8022500 <PCOMHardWare_Check_t+0x110>)
+ 8022458:	781b      	ldrb	r3, [r3, #0]
+ 802245a:	2b01      	cmp	r3, #1
+ 802245c:	d920      	bls.n	80224a0 <PCOMHardWare_Check_t+0xb0>
+ 802245e:	2330      	movs	r3, #48	@ 0x30
+ 8022460:	061a      	lsls	r2, r3, #24
+ 8022462:	2330      	movs	r3, #48	@ 0x30
+ 8022464:	041b      	lsls	r3, r3, #16
+ 8022466:	431a      	orrs	r2, r3
+ 8022468:	2330      	movs	r3, #48	@ 0x30
+ 802246a:	021b      	lsls	r3, r3, #8
+ 802246c:	4313      	orrs	r3, r2
+ 802246e:	2230      	movs	r2, #48	@ 0x30
+ 8022470:	ea43 0102 	orr.w	r1, r3, r2
+ 8022474:	2344      	movs	r3, #68	@ 0x44
+ 8022476:	061a      	lsls	r2, r3, #24
+ 8022478:	2346      	movs	r3, #70	@ 0x46
+ 802247a:	041b      	lsls	r3, r3, #16
+ 802247c:	431a      	orrs	r2, r3
+ 802247e:	234c      	movs	r3, #76	@ 0x4c
+ 8022480:	021b      	lsls	r3, r3, #8
+ 8022482:	4313      	orrs	r3, r2
+ 8022484:	2254      	movs	r2, #84	@ 0x54
+ 8022486:	431a      	orrs	r2, r3
+ 8022488:	68fb      	ldr	r3, [r7, #12]
+ 802248a:	9303      	str	r3, [sp, #12]
+ 802248c:	4b1d      	ldr	r3, [pc, #116]	@ (8022504 <PCOMHardWare_Check_t+0x114>)
+ 802248e:	9302      	str	r3, [sp, #8]
+ 8022490:	2389      	movs	r3, #137	@ 0x89
+ 8022492:	9301      	str	r3, [sp, #4]
+ 8022494:	4b1c      	ldr	r3, [pc, #112]	@ (8022508 <PCOMHardWare_Check_t+0x118>)
+ 8022496:	9300      	str	r3, [sp, #0]
+ 8022498:	4b1c      	ldr	r3, [pc, #112]	@ (802250c <PCOMHardWare_Check_t+0x11c>)
+ 802249a:	2002      	movs	r0, #2
+ 802249c:	f003 feca 	bl	8026234 <DLTuc_LogOutVarArgs>
+				SET_BIT_1(SystemErrorCode,ptr->BitFlag);
+ 80224a0:	4b1b      	ldr	r3, [pc, #108]	@ (8022510 <PCOMHardWare_Check_t+0x120>)
+ 80224a2:	681a      	ldr	r2, [r3, #0]
+ 80224a4:	68fb      	ldr	r3, [r7, #12]
+ 80224a6:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
+ 80224a8:	4619      	mov	r1, r3
+ 80224aa:	4610      	mov	r0, r2
+ 80224ac:	f7fe f8f8 	bl	80206a0 <SET_BIT_1>
+				//*SystemErrorCode=*SystemErrorCode|(1<<ptr->BitFlag);
+				IsAbnornalStatus = 1;
+ 80224b0:	2301      	movs	r3, #1
+ 80224b2:	72fb      	strb	r3, [r7, #11]
+ 80224b4:	e007      	b.n	80224c6 <PCOMHardWare_Check_t+0xd6>
+			}else
+			{
+				//*SystemErrorCode=*SystemErrorCode|(1<<ptr->BitFlag);
+				SET_BIT_0(SystemErrorCode,ptr->BitFlag);
+ 80224b6:	4b16      	ldr	r3, [pc, #88]	@ (8022510 <PCOMHardWare_Check_t+0x120>)
+ 80224b8:	681a      	ldr	r2, [r3, #0]
+ 80224ba:	68fb      	ldr	r3, [r7, #12]
+ 80224bc:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
+ 80224be:	4619      	mov	r1, r3
+ 80224c0:	4610      	mov	r0, r2
+ 80224c2:	f7fe f901 	bl	80206c8 <SET_BIT_0>
+			}
+			ptr = ptr->pNext;
+ 80224c6:	68fb      	ldr	r3, [r7, #12]
+ 80224c8:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
+ 80224ca:	60fb      	str	r3, [r7, #12]
+		while (ptr != NULL)
+ 80224cc:	68fb      	ldr	r3, [r7, #12]
+ 80224ce:	2b00      	cmp	r3, #0
+ 80224d0:	d1ac      	bne.n	802242c <PCOMHardWare_Check_t+0x3c>
+		}
+
+		//set invalid state
+		ptr = uartHandler->pComHWHead;
+ 80224d2:	687b      	ldr	r3, [r7, #4]
+ 80224d4:	681b      	ldr	r3, [r3, #0]
+ 80224d6:	60fb      	str	r3, [r7, #12]
+		while (ptr != NULL)
+ 80224d8:	e006      	b.n	80224e8 <PCOMHardWare_Check_t+0xf8>
+		{
+			ptr->IsOnline = 0;
+ 80224da:	68fb      	ldr	r3, [r7, #12]
+ 80224dc:	2200      	movs	r2, #0
+ 80224de:	f883 2032 	strb.w	r2, [r3, #50]	@ 0x32
+			ptr = ptr->pNext;
+ 80224e2:	68fb      	ldr	r3, [r7, #12]
+ 80224e4:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
+ 80224e6:	60fb      	str	r3, [r7, #12]
+		while (ptr != NULL)
+ 80224e8:	68fb      	ldr	r3, [r7, #12]
+ 80224ea:	2b00      	cmp	r3, #0
+ 80224ec:	d1f5      	bne.n	80224da <PCOMHardWare_Check_t+0xea>
+		}
+		uartHandler->HardWare_Check_Counter = 0;//perform the check of connection
+ 80224ee:	687b      	ldr	r3, [r7, #4]
+ 80224f0:	2200      	movs	r2, #0
+ 80224f2:	811a      	strh	r2, [r3, #8]
+	}
+}
+ 80224f4:	3714      	adds	r7, #20
+ 80224f6:	46bd      	mov	sp, r7
+ 80224f8:	bd90      	pop	{r4, r7, pc}
+ 80224fa:	bf00      	nop
+ 80224fc:	24008ec0 	.word	0x24008ec0
+ 8022500:	24009110 	.word	0x24009110
+ 8022504:	08041c08 	.word	0x08041c08
+ 8022508:	08040fe8 	.word	0x08040fe8
+ 802250c:	08040fb4 	.word	0x08040fb4
+ 8022510:	2400028c 	.word	0x2400028c
+
+08022514 <Set_PCOMHardWare_t>:
+
+int Set_PCOMHardWare_t(HardWareController *uartHandler, char *name, char value)
+{
+ 8022514:	b580      	push	{r7, lr}
+ 8022516:	b086      	sub	sp, #24
+ 8022518:	af00      	add	r7, sp, #0
+ 802251a:	60f8      	str	r0, [r7, #12]
+ 802251c:	60b9      	str	r1, [r7, #8]
+ 802251e:	4613      	mov	r3, r2
+ 8022520:	71fb      	strb	r3, [r7, #7]
+
+	ComHardWare *ptr = uartHandler->pComHWHead;
+ 8022522:	68fb      	ldr	r3, [r7, #12]
+ 8022524:	681b      	ldr	r3, [r3, #0]
+ 8022526:	617b      	str	r3, [r7, #20]
+	char finddata = 0;
+ 8022528:	2300      	movs	r3, #0
+ 802252a:	74fb      	strb	r3, [r7, #19]
+
+	if (ptr == NULL)
+ 802252c:	697b      	ldr	r3, [r7, #20]
+ 802252e:	2b00      	cmp	r3, #0
+ 8022530:	d114      	bne.n	802255c <Set_PCOMHardWare_t+0x48>
+	{
+
+		return 0;
+ 8022532:	2300      	movs	r3, #0
+ 8022534:	e016      	b.n	8022564 <Set_PCOMHardWare_t+0x50>
+	}
+
+	while (ptr != NULL)
+	{
+		if (strcmp(ptr->Name, name) == 0)
+ 8022536:	697b      	ldr	r3, [r7, #20]
+ 8022538:	68b9      	ldr	r1, [r7, #8]
+ 802253a:	4618      	mov	r0, r3
+ 802253c:	f7fd fed0 	bl	80202e0 <strcmp>
+ 8022540:	4603      	mov	r3, r0
+ 8022542:	2b00      	cmp	r3, #0
+ 8022544:	d107      	bne.n	8022556 <Set_PCOMHardWare_t+0x42>
+		{
+			ptr->IsOnline = value;
+ 8022546:	697b      	ldr	r3, [r7, #20]
+ 8022548:	79fa      	ldrb	r2, [r7, #7]
+ 802254a:	f883 2032 	strb.w	r2, [r3, #50]	@ 0x32
+			finddata = 1;
+ 802254e:	2301      	movs	r3, #1
+ 8022550:	74fb      	strb	r3, [r7, #19]
+			return finddata;
+ 8022552:	7cfb      	ldrb	r3, [r7, #19]
+ 8022554:	e006      	b.n	8022564 <Set_PCOMHardWare_t+0x50>
+		} else
+		{
+			ptr = ptr->pNext;
+ 8022556:	697b      	ldr	r3, [r7, #20]
+ 8022558:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
+ 802255a:	617b      	str	r3, [r7, #20]
+	while (ptr != NULL)
+ 802255c:	697b      	ldr	r3, [r7, #20]
+ 802255e:	2b00      	cmp	r3, #0
+ 8022560:	d1e9      	bne.n	8022536 <Set_PCOMHardWare_t+0x22>
+		}
+
+	}
+	return finddata;
+ 8022562:	7cfb      	ldrb	r3, [r7, #19]
+
+}
+ 8022564:	4618      	mov	r0, r3
+ 8022566:	3718      	adds	r7, #24
+ 8022568:	46bd      	mov	sp, r7
+ 802256a:	bd80      	pop	{r7, pc}
+
+0802256c <decode_command_and_feedback>:
+static uint16_t calbriation;
+static uint16_t length_count;
+
+void decode_command_and_feedback(uint8_t *buffer, uint16_t length, char isMqtt,
+        struct UARTHandler *send_Handler)
+{
+ 802256c:	b480      	push	{r7}
+ 802256e:	b085      	sub	sp, #20
+ 8022570:	af00      	add	r7, sp, #0
+ 8022572:	60f8      	str	r0, [r7, #12]
+ 8022574:	607b      	str	r3, [r7, #4]
+ 8022576:	460b      	mov	r3, r1
+ 8022578:	817b      	strh	r3, [r7, #10]
+ 802257a:	4613      	mov	r3, r2
+ 802257c:	727b      	strb	r3, [r7, #9]
+//	else
+//	{
+//
+//	}
+
+}
+ 802257e:	bf00      	nop
+ 8022580:	3714      	adds	r7, #20
+ 8022582:	46bd      	mov	sp, r7
+ 8022584:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8022588:	4770      	bx	lr
+	...
+
+0802258c <WrapInCmdAndSend>:
+void WrapInCmdAndSend(ReCmd send_Cmd, uint8_t *buf, char isMqtt,
+        struct UARTHandler *send_Handler)
+{
+ 802258c:	b084      	sub	sp, #16
+ 802258e:	b5b0      	push	{r4, r5, r7, lr}
+ 8022590:	b08c      	sub	sp, #48	@ 0x30
+ 8022592:	af00      	add	r7, sp, #0
+ 8022594:	f107 0440 	add.w	r4, r7, #64	@ 0x40
+ 8022598:	e884 000f 	stmia.w	r4, {r0, r1, r2, r3}
+
+	memcpy(send_Cmd.Buff_Data, buf, send_Cmd.Buff_Data_Length);
+ 802259c:	6dbb      	ldr	r3, [r7, #88]	@ 0x58
+ 802259e:	461a      	mov	r2, r3
+ 80225a0:	f107 035c 	add.w	r3, r7, #92	@ 0x5c
+ 80225a4:	f8d7 125c 	ldr.w	r1, [r7, #604]	@ 0x25c
+ 80225a8:	4618      	mov	r0, r3
+ 80225aa:	f01d ff07 	bl	80403bc <memcpy>
+	pb_ostream_t ReCmd_out_stream =
+ 80225ae:	f107 031c 	add.w	r3, r7, #28
+ 80225b2:	2200      	movs	r2, #0
+ 80225b4:	601a      	str	r2, [r3, #0]
+ 80225b6:	605a      	str	r2, [r3, #4]
+ 80225b8:	609a      	str	r2, [r3, #8]
+ 80225ba:	60da      	str	r2, [r3, #12]
+ 80225bc:	611a      	str	r2, [r3, #16]
+	{ 0 };
+
+	if (isMqtt == 1)
+ 80225be:	f897 3260 	ldrb.w	r3, [r7, #608]	@ 0x260
+ 80225c2:	2b01      	cmp	r3, #1
+ 80225c4:	d13e      	bne.n	8022644 <WrapInCmdAndSend+0xb8>
+	{
+		ReCmd_out_stream = pb_ostream_from_buffer(&send_Handler->Tx_Buf[4],
+ 80225c6:	f8d7 3264 	ldr.w	r3, [r7, #612]	@ 0x264
+ 80225ca:	f603 0125 	addw	r1, r3, #2085	@ 0x825
+ 80225ce:	463b      	mov	r3, r7
+ 80225d0:	f240 72fc 	movw	r2, #2044	@ 0x7fc
+ 80225d4:	4618      	mov	r0, r3
+ 80225d6:	f002 f991 	bl	80248fc <pb_ostream_from_buffer>
+ 80225da:	f107 041c 	add.w	r4, r7, #28
+ 80225de:	463d      	mov	r5, r7
+ 80225e0:	cd0f      	ldmia	r5!, {r0, r1, r2, r3}
+ 80225e2:	c40f      	stmia	r4!, {r0, r1, r2, r3}
+ 80225e4:	682b      	ldr	r3, [r5, #0]
+ 80225e6:	6023      	str	r3, [r4, #0]
+		        sizeof(send_Handler->Tx_Buf) - 4);
+		pb_encode(&ReCmd_out_stream, ReCmd_fields, &send_Cmd); //encode to buffer
+ 80225e8:	f107 031c 	add.w	r3, r7, #28
+ 80225ec:	f107 0240 	add.w	r2, r7, #64	@ 0x40
+ 80225f0:	4932      	ldr	r1, [pc, #200]	@ (80226bc <WrapInCmdAndSend+0x130>)
+ 80225f2:	4618      	mov	r0, r3
+ 80225f4:	f002 fdef 	bl	80251d6 <pb_encode>
+
+		send_Handler->Tx_Buf[0] = '3';
+ 80225f8:	f8d7 3264 	ldr.w	r3, [r7, #612]	@ 0x264
+ 80225fc:	2233      	movs	r2, #51	@ 0x33
+ 80225fe:	f883 2821 	strb.w	r2, [r3, #2081]	@ 0x821
+		send_Handler->Tx_Buf[1] = ',';
+ 8022602:	f8d7 3264 	ldr.w	r3, [r7, #612]	@ 0x264
+ 8022606:	222c      	movs	r2, #44	@ 0x2c
+ 8022608:	f883 2822 	strb.w	r2, [r3, #2082]	@ 0x822
+		send_Handler->Tx_Buf[2] = 0xfe;
+ 802260c:	f8d7 3264 	ldr.w	r3, [r7, #612]	@ 0x264
+ 8022610:	22fe      	movs	r2, #254	@ 0xfe
+ 8022612:	f883 2823 	strb.w	r2, [r3, #2083]	@ 0x823
+		send_Handler->Tx_Buf[3] = 0xfe;
+ 8022616:	f8d7 3264 	ldr.w	r3, [r7, #612]	@ 0x264
+ 802261a:	22fe      	movs	r2, #254	@ 0xfe
+ 802261c:	f883 2824 	strb.w	r2, [r3, #2084]	@ 0x824
+		send_Handler->TxCount = ReCmd_out_stream.bytes_written + 4;
+ 8022620:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 8022622:	b29b      	uxth	r3, r3
+ 8022624:	3304      	adds	r3, #4
+ 8022626:	b29a      	uxth	r2, r3
+ 8022628:	f8d7 3264 	ldr.w	r3, [r7, #612]	@ 0x264
+ 802262c:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8022630:	845a      	strh	r2, [r3, #34]	@ 0x22
+		send_Handler->UART_Tx(send_Handler);
+ 8022632:	f8d7 3264 	ldr.w	r3, [r7, #612]	@ 0x264
+ 8022636:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 802263a:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 802263c:	f8d7 0264 	ldr.w	r0, [r7, #612]	@ 0x264
+ 8022640:	4798      	blx	r3
+		send_Handler->TxCount = ReCmd_out_stream.bytes_written + 2;
+		//send_Handler->TxCount = 200;
+		send_Handler->UART_Tx(send_Handler);
+	}
+
+}
+ 8022642:	e033      	b.n	80226ac <WrapInCmdAndSend+0x120>
+		ReCmd_out_stream = pb_ostream_from_buffer(&send_Handler->Tx_Buf[2],
+ 8022644:	f8d7 3264 	ldr.w	r3, [r7, #612]	@ 0x264
+ 8022648:	f603 0123 	addw	r1, r3, #2083	@ 0x823
+ 802264c:	463b      	mov	r3, r7
+ 802264e:	f240 72fe 	movw	r2, #2046	@ 0x7fe
+ 8022652:	4618      	mov	r0, r3
+ 8022654:	f002 f952 	bl	80248fc <pb_ostream_from_buffer>
+ 8022658:	f107 041c 	add.w	r4, r7, #28
+ 802265c:	463d      	mov	r5, r7
+ 802265e:	cd0f      	ldmia	r5!, {r0, r1, r2, r3}
+ 8022660:	c40f      	stmia	r4!, {r0, r1, r2, r3}
+ 8022662:	682b      	ldr	r3, [r5, #0]
+ 8022664:	6023      	str	r3, [r4, #0]
+		pb_encode(&ReCmd_out_stream, ReCmd_fields, &send_Cmd); //encode to buffer
+ 8022666:	f107 031c 	add.w	r3, r7, #28
+ 802266a:	f107 0240 	add.w	r2, r7, #64	@ 0x40
+ 802266e:	4913      	ldr	r1, [pc, #76]	@ (80226bc <WrapInCmdAndSend+0x130>)
+ 8022670:	4618      	mov	r0, r3
+ 8022672:	f002 fdb0 	bl	80251d6 <pb_encode>
+		send_Handler->Tx_Buf[0] = 0xfe;
+ 8022676:	f8d7 3264 	ldr.w	r3, [r7, #612]	@ 0x264
+ 802267a:	22fe      	movs	r2, #254	@ 0xfe
+ 802267c:	f883 2821 	strb.w	r2, [r3, #2081]	@ 0x821
+		send_Handler->Tx_Buf[1] = 0xfe;
+ 8022680:	f8d7 3264 	ldr.w	r3, [r7, #612]	@ 0x264
+ 8022684:	22fe      	movs	r2, #254	@ 0xfe
+ 8022686:	f883 2822 	strb.w	r2, [r3, #2082]	@ 0x822
+		send_Handler->TxCount = ReCmd_out_stream.bytes_written + 2;
+ 802268a:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 802268c:	b29b      	uxth	r3, r3
+ 802268e:	3302      	adds	r3, #2
+ 8022690:	b29a      	uxth	r2, r3
+ 8022692:	f8d7 3264 	ldr.w	r3, [r7, #612]	@ 0x264
+ 8022696:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 802269a:	845a      	strh	r2, [r3, #34]	@ 0x22
+		send_Handler->UART_Tx(send_Handler);
+ 802269c:	f8d7 3264 	ldr.w	r3, [r7, #612]	@ 0x264
+ 80226a0:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 80226a4:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 80226a6:	f8d7 0264 	ldr.w	r0, [r7, #612]	@ 0x264
+ 80226aa:	4798      	blx	r3
+}
+ 80226ac:	bf00      	nop
+ 80226ae:	3730      	adds	r7, #48	@ 0x30
+ 80226b0:	46bd      	mov	sp, r7
+ 80226b2:	e8bd 40b0 	ldmia.w	sp!, {r4, r5, r7, lr}
+ 80226b6:	b004      	add	sp, #16
+ 80226b8:	4770      	bx	lr
+ 80226ba:	bf00      	nop
+ 80226bc:	08041808 	.word	0x08041808
+
+080226c0 <send_received_data_to_upper_computer>:
+	send_Cmd.Buff_Data_Length = strlen(buf);
+	WrapInCmdAndSend(send_Cmd, buf, isMqtt, send_Handler);
+}
+
+void send_received_data_to_upper_computer(uint8_t *buffer, uint16_t length)
+{
+ 80226c0:	b590      	push	{r4, r7, lr}
+ 80226c2:	f5ad 7d09 	sub.w	sp, sp, #548	@ 0x224
+ 80226c6:	af86      	add	r7, sp, #536	@ 0x218
+ 80226c8:	6078      	str	r0, [r7, #4]
+ 80226ca:	460b      	mov	r3, r1
+ 80226cc:	807b      	strh	r3, [r7, #2]
+	send_Cmd.CommadNum = 12; //定义12为设定Mqtt透传向上返回的数据
+ 80226ce:	4b0f      	ldr	r3, [pc, #60]	@ (802270c <send_received_data_to_upper_computer+0x4c>)
+ 80226d0:	220c      	movs	r2, #12
+ 80226d2:	601a      	str	r2, [r3, #0]
+	send_Cmd.Buff_Data_Length = length;
+ 80226d4:	887b      	ldrh	r3, [r7, #2]
+ 80226d6:	4a0d      	ldr	r2, [pc, #52]	@ (802270c <send_received_data_to_upper_computer+0x4c>)
+ 80226d8:	6193      	str	r3, [r2, #24]
+
+	WrapInCmdAndSend(send_Cmd, buffer, 0, desulfurizer_message_UART_Handler);
+ 80226da:	4b0d      	ldr	r3, [pc, #52]	@ (8022710 <send_received_data_to_upper_computer+0x50>)
+ 80226dc:	681b      	ldr	r3, [r3, #0]
+ 80226de:	4c0b      	ldr	r4, [pc, #44]	@ (802270c <send_received_data_to_upper_computer+0x4c>)
+ 80226e0:	9385      	str	r3, [sp, #532]	@ 0x214
+ 80226e2:	2300      	movs	r3, #0
+ 80226e4:	9384      	str	r3, [sp, #528]	@ 0x210
+ 80226e6:	687b      	ldr	r3, [r7, #4]
+ 80226e8:	9383      	str	r3, [sp, #524]	@ 0x20c
+ 80226ea:	4668      	mov	r0, sp
+ 80226ec:	f104 0310 	add.w	r3, r4, #16
+ 80226f0:	f44f 7203 	mov.w	r2, #524	@ 0x20c
+ 80226f4:	4619      	mov	r1, r3
+ 80226f6:	f01d fe61 	bl	80403bc <memcpy>
+ 80226fa:	e894 000f 	ldmia.w	r4, {r0, r1, r2, r3}
+ 80226fe:	f7ff ff45 	bl	802258c <WrapInCmdAndSend>
+
+}
+ 8022702:	bf00      	nop
+ 8022704:	370c      	adds	r7, #12
+ 8022706:	46bd      	mov	sp, r7
+ 8022708:	bd90      	pop	{r4, r7, pc}
+ 802270a:	bf00      	nop
+ 802270c:	24008ef4 	.word	0x24008ef4
+ 8022710:	24008eb4 	.word	0x24008eb4
+
+08022714 <load_descriptor_values>:
+ */
+
+#include "pb_common.h"
+
+static bool load_descriptor_values(pb_field_iter_t *iter)
+{
+ 8022714:	b480      	push	{r7}
+ 8022716:	b08f      	sub	sp, #60	@ 0x3c
+ 8022718:	af00      	add	r7, sp, #0
+ 802271a:	6078      	str	r0, [r7, #4]
+    uint32_t word0;
+    uint32_t data_offset;
+    int_least8_t size_offset;
+
+    if (iter->index >= iter->descriptor->field_count)
+ 802271c:	687b      	ldr	r3, [r7, #4]
+ 802271e:	891a      	ldrh	r2, [r3, #8]
+ 8022720:	687b      	ldr	r3, [r7, #4]
+ 8022722:	681b      	ldr	r3, [r3, #0]
+ 8022724:	8a1b      	ldrh	r3, [r3, #16]
+ 8022726:	429a      	cmp	r2, r3
+ 8022728:	d301      	bcc.n	802272e <load_descriptor_values+0x1a>
+        return false;
+ 802272a:	2300      	movs	r3, #0
+ 802272c:	e156      	b.n	80229dc <load_descriptor_values+0x2c8>
+
+    word0 = PB_PROGMEM_READU32(iter->descriptor->field_info[iter->field_info_index]);
+ 802272e:	687b      	ldr	r3, [r7, #4]
+ 8022730:	681b      	ldr	r3, [r3, #0]
+ 8022732:	681a      	ldr	r2, [r3, #0]
+ 8022734:	687b      	ldr	r3, [r7, #4]
+ 8022736:	895b      	ldrh	r3, [r3, #10]
+ 8022738:	009b      	lsls	r3, r3, #2
+ 802273a:	4413      	add	r3, r2
+ 802273c:	681b      	ldr	r3, [r3, #0]
+ 802273e:	62fb      	str	r3, [r7, #44]	@ 0x2c
+    iter->type = (pb_type_t)((word0 >> 8) & 0xFF);
+ 8022740:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
+ 8022742:	0a1b      	lsrs	r3, r3, #8
+ 8022744:	b2da      	uxtb	r2, r3
+ 8022746:	687b      	ldr	r3, [r7, #4]
+ 8022748:	759a      	strb	r2, [r3, #22]
+
+    switch(word0 & 3)
+ 802274a:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
+ 802274c:	f003 0303 	and.w	r3, r3, #3
+ 8022750:	2b02      	cmp	r3, #2
+ 8022752:	d05a      	beq.n	802280a <load_descriptor_values+0xf6>
+ 8022754:	2b02      	cmp	r3, #2
+ 8022756:	f200 8094 	bhi.w	8022882 <load_descriptor_values+0x16e>
+ 802275a:	2b00      	cmp	r3, #0
+ 802275c:	d002      	beq.n	8022764 <load_descriptor_values+0x50>
+ 802275e:	2b01      	cmp	r3, #1
+ 8022760:	d01f      	beq.n	80227a2 <load_descriptor_values+0x8e>
+ 8022762:	e08e      	b.n	8022882 <load_descriptor_values+0x16e>
+    {
+        case 0: {
+            /* 1-word format */
+            iter->array_size = 1;
+ 8022764:	687b      	ldr	r3, [r7, #4]
+ 8022766:	2201      	movs	r2, #1
+ 8022768:	829a      	strh	r2, [r3, #20]
+            iter->tag = (pb_size_t)((word0 >> 2) & 0x3F);
+ 802276a:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
+ 802276c:	089b      	lsrs	r3, r3, #2
+ 802276e:	b29b      	uxth	r3, r3
+ 8022770:	f003 033f 	and.w	r3, r3, #63	@ 0x3f
+ 8022774:	b29a      	uxth	r2, r3
+ 8022776:	687b      	ldr	r3, [r7, #4]
+ 8022778:	821a      	strh	r2, [r3, #16]
+            size_offset = (int_least8_t)((word0 >> 24) & 0x0F);
+ 802277a:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
+ 802277c:	0e1b      	lsrs	r3, r3, #24
+ 802277e:	b25b      	sxtb	r3, r3
+ 8022780:	f003 030f 	and.w	r3, r3, #15
+ 8022784:	f887 3033 	strb.w	r3, [r7, #51]	@ 0x33
+            data_offset = (word0 >> 16) & 0xFF;
+ 8022788:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
+ 802278a:	0c1b      	lsrs	r3, r3, #16
+ 802278c:	b2db      	uxtb	r3, r3
+ 802278e:	637b      	str	r3, [r7, #52]	@ 0x34
+            iter->data_size = (pb_size_t)((word0 >> 28) & 0x0F);
+ 8022790:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
+ 8022792:	0f1b      	lsrs	r3, r3, #28
+ 8022794:	b29b      	uxth	r3, r3
+ 8022796:	f003 030f 	and.w	r3, r3, #15
+ 802279a:	b29a      	uxth	r2, r3
+ 802279c:	687b      	ldr	r3, [r7, #4]
+ 802279e:	825a      	strh	r2, [r3, #18]
+            break;
+ 80227a0:	e0b4      	b.n	802290c <load_descriptor_values+0x1f8>
+        }
+
+        case 1: {
+            /* 2-word format */
+            uint32_t word1 = PB_PROGMEM_READU32(iter->descriptor->field_info[iter->field_info_index + 1]);
+ 80227a2:	687b      	ldr	r3, [r7, #4]
+ 80227a4:	681b      	ldr	r3, [r3, #0]
+ 80227a6:	681a      	ldr	r2, [r3, #0]
+ 80227a8:	687b      	ldr	r3, [r7, #4]
+ 80227aa:	895b      	ldrh	r3, [r3, #10]
+ 80227ac:	3301      	adds	r3, #1
+ 80227ae:	009b      	lsls	r3, r3, #2
+ 80227b0:	4413      	add	r3, r2
+ 80227b2:	681b      	ldr	r3, [r3, #0]
+ 80227b4:	61fb      	str	r3, [r7, #28]
+
+            iter->array_size = (pb_size_t)((word0 >> 16) & 0x0FFF);
+ 80227b6:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
+ 80227b8:	0c1b      	lsrs	r3, r3, #16
+ 80227ba:	b29b      	uxth	r3, r3
+ 80227bc:	f3c3 030b 	ubfx	r3, r3, #0, #12
+ 80227c0:	b29a      	uxth	r2, r3
+ 80227c2:	687b      	ldr	r3, [r7, #4]
+ 80227c4:	829a      	strh	r2, [r3, #20]
+            iter->tag = (pb_size_t)(((word0 >> 2) & 0x3F) | ((word1 >> 28) << 6));
+ 80227c6:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
+ 80227c8:	089b      	lsrs	r3, r3, #2
+ 80227ca:	b29b      	uxth	r3, r3
+ 80227cc:	f003 033f 	and.w	r3, r3, #63	@ 0x3f
+ 80227d0:	b29a      	uxth	r2, r3
+ 80227d2:	69fb      	ldr	r3, [r7, #28]
+ 80227d4:	0f1b      	lsrs	r3, r3, #28
+ 80227d6:	b29b      	uxth	r3, r3
+ 80227d8:	019b      	lsls	r3, r3, #6
+ 80227da:	b29b      	uxth	r3, r3
+ 80227dc:	4313      	orrs	r3, r2
+ 80227de:	b29a      	uxth	r2, r3
+ 80227e0:	687b      	ldr	r3, [r7, #4]
+ 80227e2:	821a      	strh	r2, [r3, #16]
+            size_offset = (int_least8_t)((word0 >> 28) & 0x0F);
+ 80227e4:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
+ 80227e6:	0f1b      	lsrs	r3, r3, #28
+ 80227e8:	b25b      	sxtb	r3, r3
+ 80227ea:	f003 030f 	and.w	r3, r3, #15
+ 80227ee:	f887 3033 	strb.w	r3, [r7, #51]	@ 0x33
+            data_offset = word1 & 0xFFFF;
+ 80227f2:	69fb      	ldr	r3, [r7, #28]
+ 80227f4:	b29b      	uxth	r3, r3
+ 80227f6:	637b      	str	r3, [r7, #52]	@ 0x34
+            iter->data_size = (pb_size_t)((word1 >> 16) & 0x0FFF);
+ 80227f8:	69fb      	ldr	r3, [r7, #28]
+ 80227fa:	0c1b      	lsrs	r3, r3, #16
+ 80227fc:	b29b      	uxth	r3, r3
+ 80227fe:	f3c3 030b 	ubfx	r3, r3, #0, #12
+ 8022802:	b29a      	uxth	r2, r3
+ 8022804:	687b      	ldr	r3, [r7, #4]
+ 8022806:	825a      	strh	r2, [r3, #18]
+            break;
+ 8022808:	e080      	b.n	802290c <load_descriptor_values+0x1f8>
+        }
+
+        case 2: {
+            /* 4-word format */
+            uint32_t word1 = PB_PROGMEM_READU32(iter->descriptor->field_info[iter->field_info_index + 1]);
+ 802280a:	687b      	ldr	r3, [r7, #4]
+ 802280c:	681b      	ldr	r3, [r3, #0]
+ 802280e:	681a      	ldr	r2, [r3, #0]
+ 8022810:	687b      	ldr	r3, [r7, #4]
+ 8022812:	895b      	ldrh	r3, [r3, #10]
+ 8022814:	3301      	adds	r3, #1
+ 8022816:	009b      	lsls	r3, r3, #2
+ 8022818:	4413      	add	r3, r2
+ 802281a:	681b      	ldr	r3, [r3, #0]
+ 802281c:	62bb      	str	r3, [r7, #40]	@ 0x28
+            uint32_t word2 = PB_PROGMEM_READU32(iter->descriptor->field_info[iter->field_info_index + 2]);
+ 802281e:	687b      	ldr	r3, [r7, #4]
+ 8022820:	681b      	ldr	r3, [r3, #0]
+ 8022822:	681a      	ldr	r2, [r3, #0]
+ 8022824:	687b      	ldr	r3, [r7, #4]
+ 8022826:	895b      	ldrh	r3, [r3, #10]
+ 8022828:	3302      	adds	r3, #2
+ 802282a:	009b      	lsls	r3, r3, #2
+ 802282c:	4413      	add	r3, r2
+ 802282e:	681b      	ldr	r3, [r3, #0]
+ 8022830:	627b      	str	r3, [r7, #36]	@ 0x24
+            uint32_t word3 = PB_PROGMEM_READU32(iter->descriptor->field_info[iter->field_info_index + 3]);
+ 8022832:	687b      	ldr	r3, [r7, #4]
+ 8022834:	681b      	ldr	r3, [r3, #0]
+ 8022836:	681a      	ldr	r2, [r3, #0]
+ 8022838:	687b      	ldr	r3, [r7, #4]
+ 802283a:	895b      	ldrh	r3, [r3, #10]
+ 802283c:	3303      	adds	r3, #3
+ 802283e:	009b      	lsls	r3, r3, #2
+ 8022840:	4413      	add	r3, r2
+ 8022842:	681b      	ldr	r3, [r3, #0]
+ 8022844:	623b      	str	r3, [r7, #32]
+
+            iter->array_size = (pb_size_t)(word0 >> 16);
+ 8022846:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
+ 8022848:	0c1b      	lsrs	r3, r3, #16
+ 802284a:	b29a      	uxth	r2, r3
+ 802284c:	687b      	ldr	r3, [r7, #4]
+ 802284e:	829a      	strh	r2, [r3, #20]
+            iter->tag = (pb_size_t)(((word0 >> 2) & 0x3F) | ((word1 >> 8) << 6));
+ 8022850:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
+ 8022852:	089b      	lsrs	r3, r3, #2
+ 8022854:	b29b      	uxth	r3, r3
+ 8022856:	f003 033f 	and.w	r3, r3, #63	@ 0x3f
+ 802285a:	b29a      	uxth	r2, r3
+ 802285c:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 802285e:	0a1b      	lsrs	r3, r3, #8
+ 8022860:	b29b      	uxth	r3, r3
+ 8022862:	019b      	lsls	r3, r3, #6
+ 8022864:	b29b      	uxth	r3, r3
+ 8022866:	4313      	orrs	r3, r2
+ 8022868:	b29a      	uxth	r2, r3
+ 802286a:	687b      	ldr	r3, [r7, #4]
+ 802286c:	821a      	strh	r2, [r3, #16]
+            size_offset = (int_least8_t)(word1 & 0xFF);
+ 802286e:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 8022870:	f887 3033 	strb.w	r3, [r7, #51]	@ 0x33
+            data_offset = word2;
+ 8022874:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 8022876:	637b      	str	r3, [r7, #52]	@ 0x34
+            iter->data_size = (pb_size_t)word3;
+ 8022878:	6a3b      	ldr	r3, [r7, #32]
+ 802287a:	b29a      	uxth	r2, r3
+ 802287c:	687b      	ldr	r3, [r7, #4]
+ 802287e:	825a      	strh	r2, [r3, #18]
+            break;
+ 8022880:	e044      	b.n	802290c <load_descriptor_values+0x1f8>
+        }
+
+        default: {
+            /* 8-word format */
+            uint32_t word1 = PB_PROGMEM_READU32(iter->descriptor->field_info[iter->field_info_index + 1]);
+ 8022882:	687b      	ldr	r3, [r7, #4]
+ 8022884:	681b      	ldr	r3, [r3, #0]
+ 8022886:	681a      	ldr	r2, [r3, #0]
+ 8022888:	687b      	ldr	r3, [r7, #4]
+ 802288a:	895b      	ldrh	r3, [r3, #10]
+ 802288c:	3301      	adds	r3, #1
+ 802288e:	009b      	lsls	r3, r3, #2
+ 8022890:	4413      	add	r3, r2
+ 8022892:	681b      	ldr	r3, [r3, #0]
+ 8022894:	61bb      	str	r3, [r7, #24]
+            uint32_t word2 = PB_PROGMEM_READU32(iter->descriptor->field_info[iter->field_info_index + 2]);
+ 8022896:	687b      	ldr	r3, [r7, #4]
+ 8022898:	681b      	ldr	r3, [r3, #0]
+ 802289a:	681a      	ldr	r2, [r3, #0]
+ 802289c:	687b      	ldr	r3, [r7, #4]
+ 802289e:	895b      	ldrh	r3, [r3, #10]
+ 80228a0:	3302      	adds	r3, #2
+ 80228a2:	009b      	lsls	r3, r3, #2
+ 80228a4:	4413      	add	r3, r2
+ 80228a6:	681b      	ldr	r3, [r3, #0]
+ 80228a8:	617b      	str	r3, [r7, #20]
+            uint32_t word3 = PB_PROGMEM_READU32(iter->descriptor->field_info[iter->field_info_index + 3]);
+ 80228aa:	687b      	ldr	r3, [r7, #4]
+ 80228ac:	681b      	ldr	r3, [r3, #0]
+ 80228ae:	681a      	ldr	r2, [r3, #0]
+ 80228b0:	687b      	ldr	r3, [r7, #4]
+ 80228b2:	895b      	ldrh	r3, [r3, #10]
+ 80228b4:	3303      	adds	r3, #3
+ 80228b6:	009b      	lsls	r3, r3, #2
+ 80228b8:	4413      	add	r3, r2
+ 80228ba:	681b      	ldr	r3, [r3, #0]
+ 80228bc:	613b      	str	r3, [r7, #16]
+            uint32_t word4 = PB_PROGMEM_READU32(iter->descriptor->field_info[iter->field_info_index + 4]);
+ 80228be:	687b      	ldr	r3, [r7, #4]
+ 80228c0:	681b      	ldr	r3, [r3, #0]
+ 80228c2:	681a      	ldr	r2, [r3, #0]
+ 80228c4:	687b      	ldr	r3, [r7, #4]
+ 80228c6:	895b      	ldrh	r3, [r3, #10]
+ 80228c8:	3304      	adds	r3, #4
+ 80228ca:	009b      	lsls	r3, r3, #2
+ 80228cc:	4413      	add	r3, r2
+ 80228ce:	681b      	ldr	r3, [r3, #0]
+ 80228d0:	60fb      	str	r3, [r7, #12]
+
+            iter->array_size = (pb_size_t)word4;
+ 80228d2:	68fb      	ldr	r3, [r7, #12]
+ 80228d4:	b29a      	uxth	r2, r3
+ 80228d6:	687b      	ldr	r3, [r7, #4]
+ 80228d8:	829a      	strh	r2, [r3, #20]
+            iter->tag = (pb_size_t)(((word0 >> 2) & 0x3F) | ((word1 >> 8) << 6));
+ 80228da:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
+ 80228dc:	089b      	lsrs	r3, r3, #2
+ 80228de:	b29b      	uxth	r3, r3
+ 80228e0:	f003 033f 	and.w	r3, r3, #63	@ 0x3f
+ 80228e4:	b29a      	uxth	r2, r3
+ 80228e6:	69bb      	ldr	r3, [r7, #24]
+ 80228e8:	0a1b      	lsrs	r3, r3, #8
+ 80228ea:	b29b      	uxth	r3, r3
+ 80228ec:	019b      	lsls	r3, r3, #6
+ 80228ee:	b29b      	uxth	r3, r3
+ 80228f0:	4313      	orrs	r3, r2
+ 80228f2:	b29a      	uxth	r2, r3
+ 80228f4:	687b      	ldr	r3, [r7, #4]
+ 80228f6:	821a      	strh	r2, [r3, #16]
+            size_offset = (int_least8_t)(word1 & 0xFF);
+ 80228f8:	69bb      	ldr	r3, [r7, #24]
+ 80228fa:	f887 3033 	strb.w	r3, [r7, #51]	@ 0x33
+            data_offset = word2;
+ 80228fe:	697b      	ldr	r3, [r7, #20]
+ 8022900:	637b      	str	r3, [r7, #52]	@ 0x34
+            iter->data_size = (pb_size_t)word3;
+ 8022902:	693b      	ldr	r3, [r7, #16]
+ 8022904:	b29a      	uxth	r2, r3
+ 8022906:	687b      	ldr	r3, [r7, #4]
+ 8022908:	825a      	strh	r2, [r3, #18]
+            break;
+ 802290a:	bf00      	nop
+        }
+    }
+
+    if (!iter->message)
+ 802290c:	687b      	ldr	r3, [r7, #4]
+ 802290e:	685b      	ldr	r3, [r3, #4]
+ 8022910:	2b00      	cmp	r3, #0
+ 8022912:	d106      	bne.n	8022922 <load_descriptor_values+0x20e>
+    {
+        /* Avoid doing arithmetic on null pointers, it is undefined */
+        iter->pField = NULL;
+ 8022914:	687b      	ldr	r3, [r7, #4]
+ 8022916:	2200      	movs	r2, #0
+ 8022918:	619a      	str	r2, [r3, #24]
+        iter->pSize = NULL;
+ 802291a:	687b      	ldr	r3, [r7, #4]
+ 802291c:	2200      	movs	r2, #0
+ 802291e:	621a      	str	r2, [r3, #32]
+ 8022920:	e041      	b.n	80229a6 <load_descriptor_values+0x292>
+    }
+    else
+    {
+        iter->pField = (char*)iter->message + data_offset;
+ 8022922:	687b      	ldr	r3, [r7, #4]
+ 8022924:	685a      	ldr	r2, [r3, #4]
+ 8022926:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
+ 8022928:	441a      	add	r2, r3
+ 802292a:	687b      	ldr	r3, [r7, #4]
+ 802292c:	619a      	str	r2, [r3, #24]
+
+        if (size_offset)
+ 802292e:	f997 3033 	ldrsb.w	r3, [r7, #51]	@ 0x33
+ 8022932:	2b00      	cmp	r3, #0
+ 8022934:	d008      	beq.n	8022948 <load_descriptor_values+0x234>
+        {
+            iter->pSize = (char*)iter->pField - size_offset;
+ 8022936:	687b      	ldr	r3, [r7, #4]
+ 8022938:	699a      	ldr	r2, [r3, #24]
+ 802293a:	f997 3033 	ldrsb.w	r3, [r7, #51]	@ 0x33
+ 802293e:	425b      	negs	r3, r3
+ 8022940:	441a      	add	r2, r3
+ 8022942:	687b      	ldr	r3, [r7, #4]
+ 8022944:	621a      	str	r2, [r3, #32]
+ 8022946:	e01a      	b.n	802297e <load_descriptor_values+0x26a>
+        }
+        else if (PB_HTYPE(iter->type) == PB_HTYPE_REPEATED &&
+ 8022948:	687b      	ldr	r3, [r7, #4]
+ 802294a:	7d9b      	ldrb	r3, [r3, #22]
+ 802294c:	f003 0330 	and.w	r3, r3, #48	@ 0x30
+ 8022950:	2b20      	cmp	r3, #32
+ 8022952:	d111      	bne.n	8022978 <load_descriptor_values+0x264>
+                 (PB_ATYPE(iter->type) == PB_ATYPE_STATIC ||
+ 8022954:	687b      	ldr	r3, [r7, #4]
+ 8022956:	7d9b      	ldrb	r3, [r3, #22]
+ 8022958:	f003 03c0 	and.w	r3, r3, #192	@ 0xc0
+        else if (PB_HTYPE(iter->type) == PB_HTYPE_REPEATED &&
+ 802295c:	2b00      	cmp	r3, #0
+ 802295e:	d005      	beq.n	802296c <load_descriptor_values+0x258>
+                  PB_ATYPE(iter->type) == PB_ATYPE_POINTER))
+ 8022960:	687b      	ldr	r3, [r7, #4]
+ 8022962:	7d9b      	ldrb	r3, [r3, #22]
+ 8022964:	f003 03c0 	and.w	r3, r3, #192	@ 0xc0
+                 (PB_ATYPE(iter->type) == PB_ATYPE_STATIC ||
+ 8022968:	2b80      	cmp	r3, #128	@ 0x80
+ 802296a:	d105      	bne.n	8022978 <load_descriptor_values+0x264>
+        {
+            /* Fixed count array */
+            iter->pSize = &iter->array_size;
+ 802296c:	687b      	ldr	r3, [r7, #4]
+ 802296e:	f103 0214 	add.w	r2, r3, #20
+ 8022972:	687b      	ldr	r3, [r7, #4]
+ 8022974:	621a      	str	r2, [r3, #32]
+ 8022976:	e002      	b.n	802297e <load_descriptor_values+0x26a>
+        }
+        else
+        {
+            iter->pSize = NULL;
+ 8022978:	687b      	ldr	r3, [r7, #4]
+ 802297a:	2200      	movs	r2, #0
+ 802297c:	621a      	str	r2, [r3, #32]
+        }
+
+        if (PB_ATYPE(iter->type) == PB_ATYPE_POINTER && iter->pField != NULL)
+ 802297e:	687b      	ldr	r3, [r7, #4]
+ 8022980:	7d9b      	ldrb	r3, [r3, #22]
+ 8022982:	f003 03c0 	and.w	r3, r3, #192	@ 0xc0
+ 8022986:	2b80      	cmp	r3, #128	@ 0x80
+ 8022988:	d109      	bne.n	802299e <load_descriptor_values+0x28a>
+ 802298a:	687b      	ldr	r3, [r7, #4]
+ 802298c:	699b      	ldr	r3, [r3, #24]
+ 802298e:	2b00      	cmp	r3, #0
+ 8022990:	d005      	beq.n	802299e <load_descriptor_values+0x28a>
+        {
+            iter->pData = *(void**)iter->pField;
+ 8022992:	687b      	ldr	r3, [r7, #4]
+ 8022994:	699b      	ldr	r3, [r3, #24]
+ 8022996:	681a      	ldr	r2, [r3, #0]
+ 8022998:	687b      	ldr	r3, [r7, #4]
+ 802299a:	61da      	str	r2, [r3, #28]
+ 802299c:	e003      	b.n	80229a6 <load_descriptor_values+0x292>
+        }
+        else
+        {
+            iter->pData = iter->pField;
+ 802299e:	687b      	ldr	r3, [r7, #4]
+ 80229a0:	699a      	ldr	r2, [r3, #24]
+ 80229a2:	687b      	ldr	r3, [r7, #4]
+ 80229a4:	61da      	str	r2, [r3, #28]
+        }
+    }
+
+    if (PB_LTYPE_IS_SUBMSG(iter->type))
+ 80229a6:	687b      	ldr	r3, [r7, #4]
+ 80229a8:	7d9b      	ldrb	r3, [r3, #22]
+ 80229aa:	f003 030f 	and.w	r3, r3, #15
+ 80229ae:	2b08      	cmp	r3, #8
+ 80229b0:	d005      	beq.n	80229be <load_descriptor_values+0x2aa>
+ 80229b2:	687b      	ldr	r3, [r7, #4]
+ 80229b4:	7d9b      	ldrb	r3, [r3, #22]
+ 80229b6:	f003 030f 	and.w	r3, r3, #15
+ 80229ba:	2b09      	cmp	r3, #9
+ 80229bc:	d10a      	bne.n	80229d4 <load_descriptor_values+0x2c0>
+    {
+        iter->submsg_desc = iter->descriptor->submsg_info[iter->submessage_index];
+ 80229be:	687b      	ldr	r3, [r7, #4]
+ 80229c0:	681b      	ldr	r3, [r3, #0]
+ 80229c2:	685a      	ldr	r2, [r3, #4]
+ 80229c4:	687b      	ldr	r3, [r7, #4]
+ 80229c6:	89db      	ldrh	r3, [r3, #14]
+ 80229c8:	009b      	lsls	r3, r3, #2
+ 80229ca:	4413      	add	r3, r2
+ 80229cc:	681a      	ldr	r2, [r3, #0]
+ 80229ce:	687b      	ldr	r3, [r7, #4]
+ 80229d0:	625a      	str	r2, [r3, #36]	@ 0x24
+ 80229d2:	e002      	b.n	80229da <load_descriptor_values+0x2c6>
+    }
+    else
+    {
+        iter->submsg_desc = NULL;
+ 80229d4:	687b      	ldr	r3, [r7, #4]
+ 80229d6:	2200      	movs	r2, #0
+ 80229d8:	625a      	str	r2, [r3, #36]	@ 0x24
+    }
+
+    return true;
+ 80229da:	2301      	movs	r3, #1
+}
+ 80229dc:	4618      	mov	r0, r3
+ 80229de:	373c      	adds	r7, #60	@ 0x3c
+ 80229e0:	46bd      	mov	sp, r7
+ 80229e2:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80229e6:	4770      	bx	lr
+
+080229e8 <advance_iterator>:
+
+static void advance_iterator(pb_field_iter_t *iter)
+{
+ 80229e8:	b480      	push	{r7}
+ 80229ea:	b085      	sub	sp, #20
+ 80229ec:	af00      	add	r7, sp, #0
+ 80229ee:	6078      	str	r0, [r7, #4]
+    iter->index++;
+ 80229f0:	687b      	ldr	r3, [r7, #4]
+ 80229f2:	891b      	ldrh	r3, [r3, #8]
+ 80229f4:	3301      	adds	r3, #1
+ 80229f6:	b29a      	uxth	r2, r3
+ 80229f8:	687b      	ldr	r3, [r7, #4]
+ 80229fa:	811a      	strh	r2, [r3, #8]
+
+    if (iter->index >= iter->descriptor->field_count)
+ 80229fc:	687b      	ldr	r3, [r7, #4]
+ 80229fe:	891a      	ldrh	r2, [r3, #8]
+ 8022a00:	687b      	ldr	r3, [r7, #4]
+ 8022a02:	681b      	ldr	r3, [r3, #0]
+ 8022a04:	8a1b      	ldrh	r3, [r3, #16]
+ 8022a06:	429a      	cmp	r2, r3
+ 8022a08:	d30c      	bcc.n	8022a24 <advance_iterator+0x3c>
+    {
+        /* Restart */
+        iter->index = 0;
+ 8022a0a:	687b      	ldr	r3, [r7, #4]
+ 8022a0c:	2200      	movs	r2, #0
+ 8022a0e:	811a      	strh	r2, [r3, #8]
+        iter->field_info_index = 0;
+ 8022a10:	687b      	ldr	r3, [r7, #4]
+ 8022a12:	2200      	movs	r2, #0
+ 8022a14:	815a      	strh	r2, [r3, #10]
+        iter->submessage_index = 0;
+ 8022a16:	687b      	ldr	r3, [r7, #4]
+ 8022a18:	2200      	movs	r2, #0
+ 8022a1a:	81da      	strh	r2, [r3, #14]
+        iter->required_field_index = 0;
+ 8022a1c:	687b      	ldr	r3, [r7, #4]
+ 8022a1e:	2200      	movs	r2, #0
+ 8022a20:	819a      	strh	r2, [r3, #12]
+         */
+        iter->field_info_index = (pb_size_t)(iter->field_info_index + descriptor_len);
+        iter->required_field_index = (pb_size_t)(iter->required_field_index + (PB_HTYPE(prev_type) == PB_HTYPE_REQUIRED));
+        iter->submessage_index = (pb_size_t)(iter->submessage_index + PB_LTYPE_IS_SUBMSG(prev_type));
+    }
+}
+ 8022a22:	e03b      	b.n	8022a9c <advance_iterator+0xb4>
+        uint32_t prev_descriptor = PB_PROGMEM_READU32(iter->descriptor->field_info[iter->field_info_index]);
+ 8022a24:	687b      	ldr	r3, [r7, #4]
+ 8022a26:	681b      	ldr	r3, [r3, #0]
+ 8022a28:	681a      	ldr	r2, [r3, #0]
+ 8022a2a:	687b      	ldr	r3, [r7, #4]
+ 8022a2c:	895b      	ldrh	r3, [r3, #10]
+ 8022a2e:	009b      	lsls	r3, r3, #2
+ 8022a30:	4413      	add	r3, r2
+ 8022a32:	681b      	ldr	r3, [r3, #0]
+ 8022a34:	60fb      	str	r3, [r7, #12]
+        pb_type_t prev_type = (prev_descriptor >> 8) & 0xFF;
+ 8022a36:	68fb      	ldr	r3, [r7, #12]
+ 8022a38:	0a1b      	lsrs	r3, r3, #8
+ 8022a3a:	72fb      	strb	r3, [r7, #11]
+        pb_size_t descriptor_len = (pb_size_t)(1 << (prev_descriptor & 3));
+ 8022a3c:	68fb      	ldr	r3, [r7, #12]
+ 8022a3e:	f003 0303 	and.w	r3, r3, #3
+ 8022a42:	2201      	movs	r2, #1
+ 8022a44:	fa02 f303 	lsl.w	r3, r2, r3
+ 8022a48:	813b      	strh	r3, [r7, #8]
+        iter->field_info_index = (pb_size_t)(iter->field_info_index + descriptor_len);
+ 8022a4a:	687b      	ldr	r3, [r7, #4]
+ 8022a4c:	895a      	ldrh	r2, [r3, #10]
+ 8022a4e:	893b      	ldrh	r3, [r7, #8]
+ 8022a50:	4413      	add	r3, r2
+ 8022a52:	b29a      	uxth	r2, r3
+ 8022a54:	687b      	ldr	r3, [r7, #4]
+ 8022a56:	815a      	strh	r2, [r3, #10]
+        iter->required_field_index = (pb_size_t)(iter->required_field_index + (PB_HTYPE(prev_type) == PB_HTYPE_REQUIRED));
+ 8022a58:	687b      	ldr	r3, [r7, #4]
+ 8022a5a:	899b      	ldrh	r3, [r3, #12]
+ 8022a5c:	7afa      	ldrb	r2, [r7, #11]
+ 8022a5e:	f002 0230 	and.w	r2, r2, #48	@ 0x30
+ 8022a62:	2a00      	cmp	r2, #0
+ 8022a64:	bf0c      	ite	eq
+ 8022a66:	2201      	moveq	r2, #1
+ 8022a68:	2200      	movne	r2, #0
+ 8022a6a:	b2d2      	uxtb	r2, r2
+ 8022a6c:	4413      	add	r3, r2
+ 8022a6e:	b29a      	uxth	r2, r3
+ 8022a70:	687b      	ldr	r3, [r7, #4]
+ 8022a72:	819a      	strh	r2, [r3, #12]
+        iter->submessage_index = (pb_size_t)(iter->submessage_index + PB_LTYPE_IS_SUBMSG(prev_type));
+ 8022a74:	687b      	ldr	r3, [r7, #4]
+ 8022a76:	89da      	ldrh	r2, [r3, #14]
+ 8022a78:	7afb      	ldrb	r3, [r7, #11]
+ 8022a7a:	f003 030f 	and.w	r3, r3, #15
+ 8022a7e:	2b08      	cmp	r3, #8
+ 8022a80:	d004      	beq.n	8022a8c <advance_iterator+0xa4>
+ 8022a82:	7afb      	ldrb	r3, [r7, #11]
+ 8022a84:	f003 030f 	and.w	r3, r3, #15
+ 8022a88:	2b09      	cmp	r3, #9
+ 8022a8a:	d101      	bne.n	8022a90 <advance_iterator+0xa8>
+ 8022a8c:	2301      	movs	r3, #1
+ 8022a8e:	e000      	b.n	8022a92 <advance_iterator+0xaa>
+ 8022a90:	2300      	movs	r3, #0
+ 8022a92:	b29b      	uxth	r3, r3
+ 8022a94:	4413      	add	r3, r2
+ 8022a96:	b29a      	uxth	r2, r3
+ 8022a98:	687b      	ldr	r3, [r7, #4]
+ 8022a9a:	81da      	strh	r2, [r3, #14]
+}
+ 8022a9c:	bf00      	nop
+ 8022a9e:	3714      	adds	r7, #20
+ 8022aa0:	46bd      	mov	sp, r7
+ 8022aa2:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8022aa6:	4770      	bx	lr
+
+08022aa8 <pb_field_iter_begin>:
+
+bool pb_field_iter_begin(pb_field_iter_t *iter, const pb_msgdesc_t *desc, void *message)
+{
+ 8022aa8:	b580      	push	{r7, lr}
+ 8022aaa:	b084      	sub	sp, #16
+ 8022aac:	af00      	add	r7, sp, #0
+ 8022aae:	60f8      	str	r0, [r7, #12]
+ 8022ab0:	60b9      	str	r1, [r7, #8]
+ 8022ab2:	607a      	str	r2, [r7, #4]
+    memset(iter, 0, sizeof(*iter));
+ 8022ab4:	2228      	movs	r2, #40	@ 0x28
+ 8022ab6:	2100      	movs	r1, #0
+ 8022ab8:	68f8      	ldr	r0, [r7, #12]
+ 8022aba:	f01d fc15 	bl	80402e8 <memset>
+
+    iter->descriptor = desc;
+ 8022abe:	68fb      	ldr	r3, [r7, #12]
+ 8022ac0:	68ba      	ldr	r2, [r7, #8]
+ 8022ac2:	601a      	str	r2, [r3, #0]
+    iter->message = message;
+ 8022ac4:	68fb      	ldr	r3, [r7, #12]
+ 8022ac6:	687a      	ldr	r2, [r7, #4]
+ 8022ac8:	605a      	str	r2, [r3, #4]
+
+    return load_descriptor_values(iter);
+ 8022aca:	68f8      	ldr	r0, [r7, #12]
+ 8022acc:	f7ff fe22 	bl	8022714 <load_descriptor_values>
+ 8022ad0:	4603      	mov	r3, r0
+}
+ 8022ad2:	4618      	mov	r0, r3
+ 8022ad4:	3710      	adds	r7, #16
+ 8022ad6:	46bd      	mov	sp, r7
+ 8022ad8:	bd80      	pop	{r7, pc}
+
+08022ada <pb_field_iter_begin_extension>:
+
+bool pb_field_iter_begin_extension(pb_field_iter_t *iter, pb_extension_t *extension)
+{
+ 8022ada:	b580      	push	{r7, lr}
+ 8022adc:	b086      	sub	sp, #24
+ 8022ade:	af00      	add	r7, sp, #0
+ 8022ae0:	6078      	str	r0, [r7, #4]
+ 8022ae2:	6039      	str	r1, [r7, #0]
+    const pb_msgdesc_t *msg = (const pb_msgdesc_t*)extension->type->arg;
+ 8022ae4:	683b      	ldr	r3, [r7, #0]
+ 8022ae6:	681b      	ldr	r3, [r3, #0]
+ 8022ae8:	689b      	ldr	r3, [r3, #8]
+ 8022aea:	613b      	str	r3, [r7, #16]
+    bool status;
+
+    uint32_t word0 = PB_PROGMEM_READU32(msg->field_info[0]);
+ 8022aec:	693b      	ldr	r3, [r7, #16]
+ 8022aee:	681b      	ldr	r3, [r3, #0]
+ 8022af0:	681b      	ldr	r3, [r3, #0]
+ 8022af2:	60fb      	str	r3, [r7, #12]
+    if (PB_ATYPE(word0 >> 8) == PB_ATYPE_POINTER)
+ 8022af4:	68fb      	ldr	r3, [r7, #12]
+ 8022af6:	0a1b      	lsrs	r3, r3, #8
+ 8022af8:	f003 03c0 	and.w	r3, r3, #192	@ 0xc0
+ 8022afc:	2b80      	cmp	r3, #128	@ 0x80
+ 8022afe:	d109      	bne.n	8022b14 <pb_field_iter_begin_extension+0x3a>
+    {
+        /* For pointer extensions, the pointer is stored directly
+         * in the extension structure. This avoids having an extra
+         * indirection. */
+        status = pb_field_iter_begin(iter, msg, &extension->dest);
+ 8022b00:	683b      	ldr	r3, [r7, #0]
+ 8022b02:	3304      	adds	r3, #4
+ 8022b04:	461a      	mov	r2, r3
+ 8022b06:	6939      	ldr	r1, [r7, #16]
+ 8022b08:	6878      	ldr	r0, [r7, #4]
+ 8022b0a:	f7ff ffcd 	bl	8022aa8 <pb_field_iter_begin>
+ 8022b0e:	4603      	mov	r3, r0
+ 8022b10:	75fb      	strb	r3, [r7, #23]
+ 8022b12:	e008      	b.n	8022b26 <pb_field_iter_begin_extension+0x4c>
+    }
+    else
+    {
+        status = pb_field_iter_begin(iter, msg, extension->dest);
+ 8022b14:	683b      	ldr	r3, [r7, #0]
+ 8022b16:	685b      	ldr	r3, [r3, #4]
+ 8022b18:	461a      	mov	r2, r3
+ 8022b1a:	6939      	ldr	r1, [r7, #16]
+ 8022b1c:	6878      	ldr	r0, [r7, #4]
+ 8022b1e:	f7ff ffc3 	bl	8022aa8 <pb_field_iter_begin>
+ 8022b22:	4603      	mov	r3, r0
+ 8022b24:	75fb      	strb	r3, [r7, #23]
+    }
+
+    iter->pSize = &extension->found;
+ 8022b26:	683b      	ldr	r3, [r7, #0]
+ 8022b28:	f103 020c 	add.w	r2, r3, #12
+ 8022b2c:	687b      	ldr	r3, [r7, #4]
+ 8022b2e:	621a      	str	r2, [r3, #32]
+    return status;
+ 8022b30:	7dfb      	ldrb	r3, [r7, #23]
+}
+ 8022b32:	4618      	mov	r0, r3
+ 8022b34:	3718      	adds	r7, #24
+ 8022b36:	46bd      	mov	sp, r7
+ 8022b38:	bd80      	pop	{r7, pc}
+
+08022b3a <pb_field_iter_next>:
+
+bool pb_field_iter_next(pb_field_iter_t *iter)
+{
+ 8022b3a:	b580      	push	{r7, lr}
+ 8022b3c:	b082      	sub	sp, #8
+ 8022b3e:	af00      	add	r7, sp, #0
+ 8022b40:	6078      	str	r0, [r7, #4]
+    advance_iterator(iter);
+ 8022b42:	6878      	ldr	r0, [r7, #4]
+ 8022b44:	f7ff ff50 	bl	80229e8 <advance_iterator>
+    (void)load_descriptor_values(iter);
+ 8022b48:	6878      	ldr	r0, [r7, #4]
+ 8022b4a:	f7ff fde3 	bl	8022714 <load_descriptor_values>
+    return iter->index != 0;
+ 8022b4e:	687b      	ldr	r3, [r7, #4]
+ 8022b50:	891b      	ldrh	r3, [r3, #8]
+ 8022b52:	2b00      	cmp	r3, #0
+ 8022b54:	bf14      	ite	ne
+ 8022b56:	2301      	movne	r3, #1
+ 8022b58:	2300      	moveq	r3, #0
+ 8022b5a:	b2db      	uxtb	r3, r3
+}
+ 8022b5c:	4618      	mov	r0, r3
+ 8022b5e:	3708      	adds	r7, #8
+ 8022b60:	46bd      	mov	sp, r7
+ 8022b62:	bd80      	pop	{r7, pc}
+
+08022b64 <pb_field_iter_find>:
+
+bool pb_field_iter_find(pb_field_iter_t *iter, uint32_t tag)
+{
+ 8022b64:	b580      	push	{r7, lr}
+ 8022b66:	b084      	sub	sp, #16
+ 8022b68:	af00      	add	r7, sp, #0
+ 8022b6a:	6078      	str	r0, [r7, #4]
+ 8022b6c:	6039      	str	r1, [r7, #0]
+    if (iter->tag == tag)
+ 8022b6e:	687b      	ldr	r3, [r7, #4]
+ 8022b70:	8a1b      	ldrh	r3, [r3, #16]
+ 8022b72:	461a      	mov	r2, r3
+ 8022b74:	683b      	ldr	r3, [r7, #0]
+ 8022b76:	4293      	cmp	r3, r2
+ 8022b78:	d101      	bne.n	8022b7e <pb_field_iter_find+0x1a>
+    {
+        return true; /* Nothing to do, correct field already. */
+ 8022b7a:	2301      	movs	r3, #1
+ 8022b7c:	e044      	b.n	8022c08 <pb_field_iter_find+0xa4>
+    }
+    else if (tag > iter->descriptor->largest_tag)
+ 8022b7e:	687b      	ldr	r3, [r7, #4]
+ 8022b80:	681b      	ldr	r3, [r3, #0]
+ 8022b82:	8a9b      	ldrh	r3, [r3, #20]
+ 8022b84:	461a      	mov	r2, r3
+ 8022b86:	683b      	ldr	r3, [r7, #0]
+ 8022b88:	4293      	cmp	r3, r2
+ 8022b8a:	d901      	bls.n	8022b90 <pb_field_iter_find+0x2c>
+    {
+        return false;
+ 8022b8c:	2300      	movs	r3, #0
+ 8022b8e:	e03b      	b.n	8022c08 <pb_field_iter_find+0xa4>
+    }
+    else
+    {
+        pb_size_t start = iter->index;
+ 8022b90:	687b      	ldr	r3, [r7, #4]
+ 8022b92:	891b      	ldrh	r3, [r3, #8]
+ 8022b94:	81fb      	strh	r3, [r7, #14]
+        uint32_t fieldinfo;
+
+        if (tag < iter->tag)
+ 8022b96:	687b      	ldr	r3, [r7, #4]
+ 8022b98:	8a1b      	ldrh	r3, [r3, #16]
+ 8022b9a:	461a      	mov	r2, r3
+ 8022b9c:	683b      	ldr	r3, [r7, #0]
+ 8022b9e:	4293      	cmp	r3, r2
+ 8022ba0:	d204      	bcs.n	8022bac <pb_field_iter_find+0x48>
+        {
+            /* Fields are in tag number order, so we know that tag is between
+             * 0 and our start position. Setting index to end forces
+             * advance_iterator() call below to restart from beginning. */
+            iter->index = iter->descriptor->field_count;
+ 8022ba2:	687b      	ldr	r3, [r7, #4]
+ 8022ba4:	681b      	ldr	r3, [r3, #0]
+ 8022ba6:	8a1a      	ldrh	r2, [r3, #16]
+ 8022ba8:	687b      	ldr	r3, [r7, #4]
+ 8022baa:	811a      	strh	r2, [r3, #8]
+        }
+
+        do
+        {
+            /* Advance iterator but don't load values yet */
+            advance_iterator(iter);
+ 8022bac:	6878      	ldr	r0, [r7, #4]
+ 8022bae:	f7ff ff1b 	bl	80229e8 <advance_iterator>
+
+            /* Do fast check for tag number match */
+            fieldinfo = PB_PROGMEM_READU32(iter->descriptor->field_info[iter->field_info_index]);
+ 8022bb2:	687b      	ldr	r3, [r7, #4]
+ 8022bb4:	681b      	ldr	r3, [r3, #0]
+ 8022bb6:	681a      	ldr	r2, [r3, #0]
+ 8022bb8:	687b      	ldr	r3, [r7, #4]
+ 8022bba:	895b      	ldrh	r3, [r3, #10]
+ 8022bbc:	009b      	lsls	r3, r3, #2
+ 8022bbe:	4413      	add	r3, r2
+ 8022bc0:	681b      	ldr	r3, [r3, #0]
+ 8022bc2:	60bb      	str	r3, [r7, #8]
+
+            if (((fieldinfo >> 2) & 0x3F) == (tag & 0x3F))
+ 8022bc4:	68bb      	ldr	r3, [r7, #8]
+ 8022bc6:	089a      	lsrs	r2, r3, #2
+ 8022bc8:	683b      	ldr	r3, [r7, #0]
+ 8022bca:	4053      	eors	r3, r2
+ 8022bcc:	f003 033f 	and.w	r3, r3, #63	@ 0x3f
+ 8022bd0:	2b00      	cmp	r3, #0
+ 8022bd2:	d110      	bne.n	8022bf6 <pb_field_iter_find+0x92>
+            {
+                /* Good candidate, check further */
+                (void)load_descriptor_values(iter);
+ 8022bd4:	6878      	ldr	r0, [r7, #4]
+ 8022bd6:	f7ff fd9d 	bl	8022714 <load_descriptor_values>
+
+                if (iter->tag == tag &&
+ 8022bda:	687b      	ldr	r3, [r7, #4]
+ 8022bdc:	8a1b      	ldrh	r3, [r3, #16]
+ 8022bde:	461a      	mov	r2, r3
+ 8022be0:	683b      	ldr	r3, [r7, #0]
+ 8022be2:	4293      	cmp	r3, r2
+ 8022be4:	d107      	bne.n	8022bf6 <pb_field_iter_find+0x92>
+                    PB_LTYPE(iter->type) != PB_LTYPE_EXTENSION)
+ 8022be6:	687b      	ldr	r3, [r7, #4]
+ 8022be8:	7d9b      	ldrb	r3, [r3, #22]
+ 8022bea:	f003 030f 	and.w	r3, r3, #15
+                if (iter->tag == tag &&
+ 8022bee:	2b0a      	cmp	r3, #10
+ 8022bf0:	d001      	beq.n	8022bf6 <pb_field_iter_find+0x92>
+                {
+                    /* Found it */
+                    return true;
+ 8022bf2:	2301      	movs	r3, #1
+ 8022bf4:	e008      	b.n	8022c08 <pb_field_iter_find+0xa4>
+                }
+            }
+        } while (iter->index != start);
+ 8022bf6:	687b      	ldr	r3, [r7, #4]
+ 8022bf8:	891b      	ldrh	r3, [r3, #8]
+ 8022bfa:	89fa      	ldrh	r2, [r7, #14]
+ 8022bfc:	429a      	cmp	r2, r3
+ 8022bfe:	d1d5      	bne.n	8022bac <pb_field_iter_find+0x48>
+
+        /* Searched all the way back to start, and found nothing. */
+        (void)load_descriptor_values(iter);
+ 8022c00:	6878      	ldr	r0, [r7, #4]
+ 8022c02:	f7ff fd87 	bl	8022714 <load_descriptor_values>
+        return false;
+ 8022c06:	2300      	movs	r3, #0
+    }
+}
+ 8022c08:	4618      	mov	r0, r3
+ 8022c0a:	3710      	adds	r7, #16
+ 8022c0c:	46bd      	mov	sp, r7
+ 8022c0e:	bd80      	pop	{r7, pc}
+
+08022c10 <pb_field_iter_find_extension>:
+
+bool pb_field_iter_find_extension(pb_field_iter_t *iter)
+{
+ 8022c10:	b580      	push	{r7, lr}
+ 8022c12:	b084      	sub	sp, #16
+ 8022c14:	af00      	add	r7, sp, #0
+ 8022c16:	6078      	str	r0, [r7, #4]
+    if (PB_LTYPE(iter->type) == PB_LTYPE_EXTENSION)
+ 8022c18:	687b      	ldr	r3, [r7, #4]
+ 8022c1a:	7d9b      	ldrb	r3, [r3, #22]
+ 8022c1c:	f003 030f 	and.w	r3, r3, #15
+ 8022c20:	2b0a      	cmp	r3, #10
+ 8022c22:	d101      	bne.n	8022c28 <pb_field_iter_find_extension+0x18>
+    {
+        return true;
+ 8022c24:	2301      	movs	r3, #1
+ 8022c26:	e022      	b.n	8022c6e <pb_field_iter_find_extension+0x5e>
+    }
+    else
+    {
+        pb_size_t start = iter->index;
+ 8022c28:	687b      	ldr	r3, [r7, #4]
+ 8022c2a:	891b      	ldrh	r3, [r3, #8]
+ 8022c2c:	81fb      	strh	r3, [r7, #14]
+        uint32_t fieldinfo;
+
+        do
+        {
+            /* Advance iterator but don't load values yet */
+            advance_iterator(iter);
+ 8022c2e:	6878      	ldr	r0, [r7, #4]
+ 8022c30:	f7ff feda 	bl	80229e8 <advance_iterator>
+
+            /* Do fast check for field type */
+            fieldinfo = PB_PROGMEM_READU32(iter->descriptor->field_info[iter->field_info_index]);
+ 8022c34:	687b      	ldr	r3, [r7, #4]
+ 8022c36:	681b      	ldr	r3, [r3, #0]
+ 8022c38:	681a      	ldr	r2, [r3, #0]
+ 8022c3a:	687b      	ldr	r3, [r7, #4]
+ 8022c3c:	895b      	ldrh	r3, [r3, #10]
+ 8022c3e:	009b      	lsls	r3, r3, #2
+ 8022c40:	4413      	add	r3, r2
+ 8022c42:	681b      	ldr	r3, [r3, #0]
+ 8022c44:	60bb      	str	r3, [r7, #8]
+
+            if (PB_LTYPE((fieldinfo >> 8) & 0xFF) == PB_LTYPE_EXTENSION)
+ 8022c46:	68bb      	ldr	r3, [r7, #8]
+ 8022c48:	0a1b      	lsrs	r3, r3, #8
+ 8022c4a:	f003 030f 	and.w	r3, r3, #15
+ 8022c4e:	2b0a      	cmp	r3, #10
+ 8022c50:	d104      	bne.n	8022c5c <pb_field_iter_find_extension+0x4c>
+            {
+                return load_descriptor_values(iter);
+ 8022c52:	6878      	ldr	r0, [r7, #4]
+ 8022c54:	f7ff fd5e 	bl	8022714 <load_descriptor_values>
+ 8022c58:	4603      	mov	r3, r0
+ 8022c5a:	e008      	b.n	8022c6e <pb_field_iter_find_extension+0x5e>
+            }
+        } while (iter->index != start);
+ 8022c5c:	687b      	ldr	r3, [r7, #4]
+ 8022c5e:	891b      	ldrh	r3, [r3, #8]
+ 8022c60:	89fa      	ldrh	r2, [r7, #14]
+ 8022c62:	429a      	cmp	r2, r3
+ 8022c64:	d1e3      	bne.n	8022c2e <pb_field_iter_find_extension+0x1e>
+
+        /* Searched all the way back to start, and found nothing. */
+        (void)load_descriptor_values(iter);
+ 8022c66:	6878      	ldr	r0, [r7, #4]
+ 8022c68:	f7ff fd54 	bl	8022714 <load_descriptor_values>
+        return false;
+ 8022c6c:	2300      	movs	r3, #0
+    }
+}
+ 8022c6e:	4618      	mov	r0, r3
+ 8022c70:	3710      	adds	r7, #16
+ 8022c72:	46bd      	mov	sp, r7
+ 8022c74:	bd80      	pop	{r7, pc}
+
+08022c76 <pb_const_cast>:
+
+static void *pb_const_cast(const void *p)
+{
+ 8022c76:	b480      	push	{r7}
+ 8022c78:	b085      	sub	sp, #20
+ 8022c7a:	af00      	add	r7, sp, #0
+ 8022c7c:	6078      	str	r0, [r7, #4]
+     * to avoid spurious compiler warnings. */
+    union {
+        void *p1;
+        const void *p2;
+    } t;
+    t.p2 = p;
+ 8022c7e:	687b      	ldr	r3, [r7, #4]
+ 8022c80:	60fb      	str	r3, [r7, #12]
+    return t.p1;
+ 8022c82:	68fb      	ldr	r3, [r7, #12]
+}
+ 8022c84:	4618      	mov	r0, r3
+ 8022c86:	3714      	adds	r7, #20
+ 8022c88:	46bd      	mov	sp, r7
+ 8022c8a:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8022c8e:	4770      	bx	lr
+
+08022c90 <pb_field_iter_begin_const>:
+
+bool pb_field_iter_begin_const(pb_field_iter_t *iter, const pb_msgdesc_t *desc, const void *message)
+{
+ 8022c90:	b580      	push	{r7, lr}
+ 8022c92:	b084      	sub	sp, #16
+ 8022c94:	af00      	add	r7, sp, #0
+ 8022c96:	60f8      	str	r0, [r7, #12]
+ 8022c98:	60b9      	str	r1, [r7, #8]
+ 8022c9a:	607a      	str	r2, [r7, #4]
+    return pb_field_iter_begin(iter, desc, pb_const_cast(message));
+ 8022c9c:	6878      	ldr	r0, [r7, #4]
+ 8022c9e:	f7ff ffea 	bl	8022c76 <pb_const_cast>
+ 8022ca2:	4603      	mov	r3, r0
+ 8022ca4:	461a      	mov	r2, r3
+ 8022ca6:	68b9      	ldr	r1, [r7, #8]
+ 8022ca8:	68f8      	ldr	r0, [r7, #12]
+ 8022caa:	f7ff fefd 	bl	8022aa8 <pb_field_iter_begin>
+ 8022cae:	4603      	mov	r3, r0
+}
+ 8022cb0:	4618      	mov	r0, r3
+ 8022cb2:	3710      	adds	r7, #16
+ 8022cb4:	46bd      	mov	sp, r7
+ 8022cb6:	bd80      	pop	{r7, pc}
+
+08022cb8 <pb_field_iter_begin_extension_const>:
+
+bool pb_field_iter_begin_extension_const(pb_field_iter_t *iter, const pb_extension_t *extension)
+{
+ 8022cb8:	b580      	push	{r7, lr}
+ 8022cba:	b082      	sub	sp, #8
+ 8022cbc:	af00      	add	r7, sp, #0
+ 8022cbe:	6078      	str	r0, [r7, #4]
+ 8022cc0:	6039      	str	r1, [r7, #0]
+    return pb_field_iter_begin_extension(iter, (pb_extension_t*)pb_const_cast(extension));
+ 8022cc2:	6838      	ldr	r0, [r7, #0]
+ 8022cc4:	f7ff ffd7 	bl	8022c76 <pb_const_cast>
+ 8022cc8:	4603      	mov	r3, r0
+ 8022cca:	4619      	mov	r1, r3
+ 8022ccc:	6878      	ldr	r0, [r7, #4]
+ 8022cce:	f7ff ff04 	bl	8022ada <pb_field_iter_begin_extension>
+ 8022cd2:	4603      	mov	r3, r0
+}
+ 8022cd4:	4618      	mov	r0, r3
+ 8022cd6:	3708      	adds	r7, #8
+ 8022cd8:	46bd      	mov	sp, r7
+ 8022cda:	bd80      	pop	{r7, pc}
+
+08022cdc <pb_default_field_callback>:
+
+bool pb_default_field_callback(pb_istream_t *istream, pb_ostream_t *ostream, const pb_field_t *field)
+{
+ 8022cdc:	b580      	push	{r7, lr}
+ 8022cde:	b086      	sub	sp, #24
+ 8022ce0:	af00      	add	r7, sp, #0
+ 8022ce2:	60f8      	str	r0, [r7, #12]
+ 8022ce4:	60b9      	str	r1, [r7, #8]
+ 8022ce6:	607a      	str	r2, [r7, #4]
+    if (field->data_size == sizeof(pb_callback_t))
+ 8022ce8:	687b      	ldr	r3, [r7, #4]
+ 8022cea:	8a5b      	ldrh	r3, [r3, #18]
+ 8022cec:	2b08      	cmp	r3, #8
+ 8022cee:	d125      	bne.n	8022d3c <pb_default_field_callback+0x60>
+    {
+        pb_callback_t *pCallback = (pb_callback_t*)field->pData;
+ 8022cf0:	687b      	ldr	r3, [r7, #4]
+ 8022cf2:	69db      	ldr	r3, [r3, #28]
+ 8022cf4:	617b      	str	r3, [r7, #20]
+
+        if (pCallback != NULL)
+ 8022cf6:	697b      	ldr	r3, [r7, #20]
+ 8022cf8:	2b00      	cmp	r3, #0
+ 8022cfa:	d01f      	beq.n	8022d3c <pb_default_field_callback+0x60>
+        {
+            if (istream != NULL && pCallback->funcs.decode != NULL)
+ 8022cfc:	68fb      	ldr	r3, [r7, #12]
+ 8022cfe:	2b00      	cmp	r3, #0
+ 8022d00:	d00c      	beq.n	8022d1c <pb_default_field_callback+0x40>
+ 8022d02:	697b      	ldr	r3, [r7, #20]
+ 8022d04:	681b      	ldr	r3, [r3, #0]
+ 8022d06:	2b00      	cmp	r3, #0
+ 8022d08:	d008      	beq.n	8022d1c <pb_default_field_callback+0x40>
+            {
+                return pCallback->funcs.decode(istream, field, &pCallback->arg);
+ 8022d0a:	697b      	ldr	r3, [r7, #20]
+ 8022d0c:	681b      	ldr	r3, [r3, #0]
+ 8022d0e:	697a      	ldr	r2, [r7, #20]
+ 8022d10:	3204      	adds	r2, #4
+ 8022d12:	6879      	ldr	r1, [r7, #4]
+ 8022d14:	68f8      	ldr	r0, [r7, #12]
+ 8022d16:	4798      	blx	r3
+ 8022d18:	4603      	mov	r3, r0
+ 8022d1a:	e010      	b.n	8022d3e <pb_default_field_callback+0x62>
+            }
+
+            if (ostream != NULL && pCallback->funcs.encode != NULL)
+ 8022d1c:	68bb      	ldr	r3, [r7, #8]
+ 8022d1e:	2b00      	cmp	r3, #0
+ 8022d20:	d00c      	beq.n	8022d3c <pb_default_field_callback+0x60>
+ 8022d22:	697b      	ldr	r3, [r7, #20]
+ 8022d24:	681b      	ldr	r3, [r3, #0]
+ 8022d26:	2b00      	cmp	r3, #0
+ 8022d28:	d008      	beq.n	8022d3c <pb_default_field_callback+0x60>
+            {
+                return pCallback->funcs.encode(ostream, field, &pCallback->arg);
+ 8022d2a:	697b      	ldr	r3, [r7, #20]
+ 8022d2c:	681b      	ldr	r3, [r3, #0]
+ 8022d2e:	697a      	ldr	r2, [r7, #20]
+ 8022d30:	3204      	adds	r2, #4
+ 8022d32:	6879      	ldr	r1, [r7, #4]
+ 8022d34:	68b8      	ldr	r0, [r7, #8]
+ 8022d36:	4798      	blx	r3
+ 8022d38:	4603      	mov	r3, r0
+ 8022d3a:	e000      	b.n	8022d3e <pb_default_field_callback+0x62>
+            }
+        }
+    }
+
+    return true; /* Success, but didn't do anything */
+ 8022d3c:	2301      	movs	r3, #1
+
+}
+ 8022d3e:	4618      	mov	r0, r3
+ 8022d40:	3718      	adds	r7, #24
+ 8022d42:	46bd      	mov	sp, r7
+ 8022d44:	bd80      	pop	{r7, pc}
+
+08022d46 <buf_read>:
+/*******************************
+ * pb_istream_t implementation *
+ *******************************/
+
+static bool checkreturn buf_read(pb_istream_t *stream, pb_byte_t *buf, size_t count)
+{
+ 8022d46:	b580      	push	{r7, lr}
+ 8022d48:	b086      	sub	sp, #24
+ 8022d4a:	af00      	add	r7, sp, #0
+ 8022d4c:	60f8      	str	r0, [r7, #12]
+ 8022d4e:	60b9      	str	r1, [r7, #8]
+ 8022d50:	607a      	str	r2, [r7, #4]
+    const pb_byte_t *source = (const pb_byte_t*)stream->state;
+ 8022d52:	68fb      	ldr	r3, [r7, #12]
+ 8022d54:	685b      	ldr	r3, [r3, #4]
+ 8022d56:	617b      	str	r3, [r7, #20]
+    stream->state = (pb_byte_t*)stream->state + count;
+ 8022d58:	68fb      	ldr	r3, [r7, #12]
+ 8022d5a:	685a      	ldr	r2, [r3, #4]
+ 8022d5c:	687b      	ldr	r3, [r7, #4]
+ 8022d5e:	441a      	add	r2, r3
+ 8022d60:	68fb      	ldr	r3, [r7, #12]
+ 8022d62:	605a      	str	r2, [r3, #4]
+    
+    if (buf != NULL)
+ 8022d64:	68bb      	ldr	r3, [r7, #8]
+ 8022d66:	2b00      	cmp	r3, #0
+ 8022d68:	d004      	beq.n	8022d74 <buf_read+0x2e>
+    {
+        memcpy(buf, source, count * sizeof(pb_byte_t));
+ 8022d6a:	687a      	ldr	r2, [r7, #4]
+ 8022d6c:	6979      	ldr	r1, [r7, #20]
+ 8022d6e:	68b8      	ldr	r0, [r7, #8]
+ 8022d70:	f01d fb24 	bl	80403bc <memcpy>
+    }
+    
+    return true;
+ 8022d74:	2301      	movs	r3, #1
+}
+ 8022d76:	4618      	mov	r0, r3
+ 8022d78:	3718      	adds	r7, #24
+ 8022d7a:	46bd      	mov	sp, r7
+ 8022d7c:	bd80      	pop	{r7, pc}
+	...
+
+08022d80 <pb_read>:
+
+bool checkreturn pb_read(pb_istream_t *stream, pb_byte_t *buf, size_t count)
+{
+ 8022d80:	b580      	push	{r7, lr}
+ 8022d82:	b088      	sub	sp, #32
+ 8022d84:	af00      	add	r7, sp, #0
+ 8022d86:	60f8      	str	r0, [r7, #12]
+ 8022d88:	60b9      	str	r1, [r7, #8]
+ 8022d8a:	607a      	str	r2, [r7, #4]
+    if (count == 0)
+ 8022d8c:	687b      	ldr	r3, [r7, #4]
+ 8022d8e:	2b00      	cmp	r3, #0
+ 8022d90:	d101      	bne.n	8022d96 <pb_read+0x16>
+        return true;
+ 8022d92:	2301      	movs	r3, #1
+ 8022d94:	e05f      	b.n	8022e56 <pb_read+0xd6>
+
+#ifndef PB_BUFFER_ONLY
+	if (buf == NULL && stream->callback != buf_read)
+ 8022d96:	68bb      	ldr	r3, [r7, #8]
+ 8022d98:	2b00      	cmp	r3, #0
+ 8022d9a:	d123      	bne.n	8022de4 <pb_read+0x64>
+ 8022d9c:	68fb      	ldr	r3, [r7, #12]
+ 8022d9e:	681b      	ldr	r3, [r3, #0]
+ 8022da0:	4a2f      	ldr	r2, [pc, #188]	@ (8022e60 <pb_read+0xe0>)
+ 8022da2:	4293      	cmp	r3, r2
+ 8022da4:	d01e      	beq.n	8022de4 <pb_read+0x64>
+	{
+		/* Skip input bytes */
+		pb_byte_t tmp[16];
+		while (count > 16)
+ 8022da6:	e011      	b.n	8022dcc <pb_read+0x4c>
+		{
+			if (!pb_read(stream, tmp, 16))
+ 8022da8:	f107 0310 	add.w	r3, r7, #16
+ 8022dac:	2210      	movs	r2, #16
+ 8022dae:	4619      	mov	r1, r3
+ 8022db0:	68f8      	ldr	r0, [r7, #12]
+ 8022db2:	f7ff ffe5 	bl	8022d80 <pb_read>
+ 8022db6:	4603      	mov	r3, r0
+ 8022db8:	f083 0301 	eor.w	r3, r3, #1
+ 8022dbc:	b2db      	uxtb	r3, r3
+ 8022dbe:	2b00      	cmp	r3, #0
+ 8022dc0:	d001      	beq.n	8022dc6 <pb_read+0x46>
+				return false;
+ 8022dc2:	2300      	movs	r3, #0
+ 8022dc4:	e047      	b.n	8022e56 <pb_read+0xd6>
+			
+			count -= 16;
+ 8022dc6:	687b      	ldr	r3, [r7, #4]
+ 8022dc8:	3b10      	subs	r3, #16
+ 8022dca:	607b      	str	r3, [r7, #4]
+		while (count > 16)
+ 8022dcc:	687b      	ldr	r3, [r7, #4]
+ 8022dce:	2b10      	cmp	r3, #16
+ 8022dd0:	d8ea      	bhi.n	8022da8 <pb_read+0x28>
+		}
+		
+		return pb_read(stream, tmp, count);
+ 8022dd2:	f107 0310 	add.w	r3, r7, #16
+ 8022dd6:	687a      	ldr	r2, [r7, #4]
+ 8022dd8:	4619      	mov	r1, r3
+ 8022dda:	68f8      	ldr	r0, [r7, #12]
+ 8022ddc:	f7ff ffd0 	bl	8022d80 <pb_read>
+ 8022de0:	4603      	mov	r3, r0
+ 8022de2:	e038      	b.n	8022e56 <pb_read+0xd6>
+	}
+#endif
+
+    if (stream->bytes_left < count)
+ 8022de4:	68fb      	ldr	r3, [r7, #12]
+ 8022de6:	689b      	ldr	r3, [r3, #8]
+ 8022de8:	687a      	ldr	r2, [r7, #4]
+ 8022dea:	429a      	cmp	r2, r3
+ 8022dec:	d90b      	bls.n	8022e06 <pb_read+0x86>
+        PB_RETURN_ERROR(stream, "end-of-stream");
+ 8022dee:	68fb      	ldr	r3, [r7, #12]
+ 8022df0:	68db      	ldr	r3, [r3, #12]
+ 8022df2:	2b00      	cmp	r3, #0
+ 8022df4:	d002      	beq.n	8022dfc <pb_read+0x7c>
+ 8022df6:	68fb      	ldr	r3, [r7, #12]
+ 8022df8:	68db      	ldr	r3, [r3, #12]
+ 8022dfa:	e000      	b.n	8022dfe <pb_read+0x7e>
+ 8022dfc:	4b19      	ldr	r3, [pc, #100]	@ (8022e64 <pb_read+0xe4>)
+ 8022dfe:	68fa      	ldr	r2, [r7, #12]
+ 8022e00:	60d3      	str	r3, [r2, #12]
+ 8022e02:	2300      	movs	r3, #0
+ 8022e04:	e027      	b.n	8022e56 <pb_read+0xd6>
+    
+#ifndef PB_BUFFER_ONLY
+    if (!stream->callback(stream, buf, count))
+ 8022e06:	68fb      	ldr	r3, [r7, #12]
+ 8022e08:	681b      	ldr	r3, [r3, #0]
+ 8022e0a:	687a      	ldr	r2, [r7, #4]
+ 8022e0c:	68b9      	ldr	r1, [r7, #8]
+ 8022e0e:	68f8      	ldr	r0, [r7, #12]
+ 8022e10:	4798      	blx	r3
+ 8022e12:	4603      	mov	r3, r0
+ 8022e14:	f083 0301 	eor.w	r3, r3, #1
+ 8022e18:	b2db      	uxtb	r3, r3
+ 8022e1a:	2b00      	cmp	r3, #0
+ 8022e1c:	d00b      	beq.n	8022e36 <pb_read+0xb6>
+        PB_RETURN_ERROR(stream, "io error");
+ 8022e1e:	68fb      	ldr	r3, [r7, #12]
+ 8022e20:	68db      	ldr	r3, [r3, #12]
+ 8022e22:	2b00      	cmp	r3, #0
+ 8022e24:	d002      	beq.n	8022e2c <pb_read+0xac>
+ 8022e26:	68fb      	ldr	r3, [r7, #12]
+ 8022e28:	68db      	ldr	r3, [r3, #12]
+ 8022e2a:	e000      	b.n	8022e2e <pb_read+0xae>
+ 8022e2c:	4b0e      	ldr	r3, [pc, #56]	@ (8022e68 <pb_read+0xe8>)
+ 8022e2e:	68fa      	ldr	r2, [r7, #12]
+ 8022e30:	60d3      	str	r3, [r2, #12]
+ 8022e32:	2300      	movs	r3, #0
+ 8022e34:	e00f      	b.n	8022e56 <pb_read+0xd6>
+#else
+    if (!buf_read(stream, buf, count))
+        return false;
+#endif
+    
+    if (stream->bytes_left < count)
+ 8022e36:	68fb      	ldr	r3, [r7, #12]
+ 8022e38:	689b      	ldr	r3, [r3, #8]
+ 8022e3a:	687a      	ldr	r2, [r7, #4]
+ 8022e3c:	429a      	cmp	r2, r3
+ 8022e3e:	d903      	bls.n	8022e48 <pb_read+0xc8>
+        stream->bytes_left = 0;
+ 8022e40:	68fb      	ldr	r3, [r7, #12]
+ 8022e42:	2200      	movs	r2, #0
+ 8022e44:	609a      	str	r2, [r3, #8]
+ 8022e46:	e005      	b.n	8022e54 <pb_read+0xd4>
+    else
+        stream->bytes_left -= count;
+ 8022e48:	68fb      	ldr	r3, [r7, #12]
+ 8022e4a:	689a      	ldr	r2, [r3, #8]
+ 8022e4c:	687b      	ldr	r3, [r7, #4]
+ 8022e4e:	1ad2      	subs	r2, r2, r3
+ 8022e50:	68fb      	ldr	r3, [r7, #12]
+ 8022e52:	609a      	str	r2, [r3, #8]
+
+    return true;
+ 8022e54:	2301      	movs	r3, #1
+}
+ 8022e56:	4618      	mov	r0, r3
+ 8022e58:	3720      	adds	r7, #32
+ 8022e5a:	46bd      	mov	sp, r7
+ 8022e5c:	bd80      	pop	{r7, pc}
+ 8022e5e:	bf00      	nop
+ 8022e60:	08022d47 	.word	0x08022d47
+ 8022e64:	08041010 	.word	0x08041010
+ 8022e68:	08041020 	.word	0x08041020
+
+08022e6c <pb_readbyte>:
+
+/* Read a single byte from input stream. buf may not be NULL.
+ * This is an optimization for the varint decoding. */
+static bool checkreturn pb_readbyte(pb_istream_t *stream, pb_byte_t *buf)
+{
+ 8022e6c:	b580      	push	{r7, lr}
+ 8022e6e:	b082      	sub	sp, #8
+ 8022e70:	af00      	add	r7, sp, #0
+ 8022e72:	6078      	str	r0, [r7, #4]
+ 8022e74:	6039      	str	r1, [r7, #0]
+    if (stream->bytes_left == 0)
+ 8022e76:	687b      	ldr	r3, [r7, #4]
+ 8022e78:	689b      	ldr	r3, [r3, #8]
+ 8022e7a:	2b00      	cmp	r3, #0
+ 8022e7c:	d10b      	bne.n	8022e96 <pb_readbyte+0x2a>
+        PB_RETURN_ERROR(stream, "end-of-stream");
+ 8022e7e:	687b      	ldr	r3, [r7, #4]
+ 8022e80:	68db      	ldr	r3, [r3, #12]
+ 8022e82:	2b00      	cmp	r3, #0
+ 8022e84:	d002      	beq.n	8022e8c <pb_readbyte+0x20>
+ 8022e86:	687b      	ldr	r3, [r7, #4]
+ 8022e88:	68db      	ldr	r3, [r3, #12]
+ 8022e8a:	e000      	b.n	8022e8e <pb_readbyte+0x22>
+ 8022e8c:	4b13      	ldr	r3, [pc, #76]	@ (8022edc <pb_readbyte+0x70>)
+ 8022e8e:	687a      	ldr	r2, [r7, #4]
+ 8022e90:	60d3      	str	r3, [r2, #12]
+ 8022e92:	2300      	movs	r3, #0
+ 8022e94:	e01d      	b.n	8022ed2 <pb_readbyte+0x66>
+
+#ifndef PB_BUFFER_ONLY
+    if (!stream->callback(stream, buf, 1))
+ 8022e96:	687b      	ldr	r3, [r7, #4]
+ 8022e98:	681b      	ldr	r3, [r3, #0]
+ 8022e9a:	2201      	movs	r2, #1
+ 8022e9c:	6839      	ldr	r1, [r7, #0]
+ 8022e9e:	6878      	ldr	r0, [r7, #4]
+ 8022ea0:	4798      	blx	r3
+ 8022ea2:	4603      	mov	r3, r0
+ 8022ea4:	f083 0301 	eor.w	r3, r3, #1
+ 8022ea8:	b2db      	uxtb	r3, r3
+ 8022eaa:	2b00      	cmp	r3, #0
+ 8022eac:	d00b      	beq.n	8022ec6 <pb_readbyte+0x5a>
+        PB_RETURN_ERROR(stream, "io error");
+ 8022eae:	687b      	ldr	r3, [r7, #4]
+ 8022eb0:	68db      	ldr	r3, [r3, #12]
+ 8022eb2:	2b00      	cmp	r3, #0
+ 8022eb4:	d002      	beq.n	8022ebc <pb_readbyte+0x50>
+ 8022eb6:	687b      	ldr	r3, [r7, #4]
+ 8022eb8:	68db      	ldr	r3, [r3, #12]
+ 8022eba:	e000      	b.n	8022ebe <pb_readbyte+0x52>
+ 8022ebc:	4b08      	ldr	r3, [pc, #32]	@ (8022ee0 <pb_readbyte+0x74>)
+ 8022ebe:	687a      	ldr	r2, [r7, #4]
+ 8022ec0:	60d3      	str	r3, [r2, #12]
+ 8022ec2:	2300      	movs	r3, #0
+ 8022ec4:	e005      	b.n	8022ed2 <pb_readbyte+0x66>
+#else
+    *buf = *(const pb_byte_t*)stream->state;
+    stream->state = (pb_byte_t*)stream->state + 1;
+#endif
+
+    stream->bytes_left--;
+ 8022ec6:	687b      	ldr	r3, [r7, #4]
+ 8022ec8:	689b      	ldr	r3, [r3, #8]
+ 8022eca:	1e5a      	subs	r2, r3, #1
+ 8022ecc:	687b      	ldr	r3, [r7, #4]
+ 8022ece:	609a      	str	r2, [r3, #8]
+    
+    return true;    
+ 8022ed0:	2301      	movs	r3, #1
+}
+ 8022ed2:	4618      	mov	r0, r3
+ 8022ed4:	3708      	adds	r7, #8
+ 8022ed6:	46bd      	mov	sp, r7
+ 8022ed8:	bd80      	pop	{r7, pc}
+ 8022eda:	bf00      	nop
+ 8022edc:	08041010 	.word	0x08041010
+ 8022ee0:	08041020 	.word	0x08041020
+
+08022ee4 <pb_istream_from_buffer>:
+
+pb_istream_t pb_istream_from_buffer(const pb_byte_t *buf, size_t msglen)
+{
+ 8022ee4:	b490      	push	{r4, r7}
+ 8022ee6:	b08a      	sub	sp, #40	@ 0x28
+ 8022ee8:	af00      	add	r7, sp, #0
+ 8022eea:	60f8      	str	r0, [r7, #12]
+ 8022eec:	60b9      	str	r1, [r7, #8]
+ 8022eee:	607a      	str	r2, [r7, #4]
+        const void *c_state;
+    } state;
+#ifdef PB_BUFFER_ONLY
+    stream.callback = NULL;
+#else
+    stream.callback = &buf_read;
+ 8022ef0:	4b0a      	ldr	r3, [pc, #40]	@ (8022f1c <pb_istream_from_buffer+0x38>)
+ 8022ef2:	61bb      	str	r3, [r7, #24]
+#endif
+    state.c_state = buf;
+ 8022ef4:	68bb      	ldr	r3, [r7, #8]
+ 8022ef6:	617b      	str	r3, [r7, #20]
+    stream.state = state.state;
+ 8022ef8:	697b      	ldr	r3, [r7, #20]
+ 8022efa:	61fb      	str	r3, [r7, #28]
+    stream.bytes_left = msglen;
+ 8022efc:	687b      	ldr	r3, [r7, #4]
+ 8022efe:	623b      	str	r3, [r7, #32]
+#ifndef PB_NO_ERRMSG
+    stream.errmsg = NULL;
+ 8022f00:	2300      	movs	r3, #0
+ 8022f02:	627b      	str	r3, [r7, #36]	@ 0x24
+#endif
+    return stream;
+ 8022f04:	68fb      	ldr	r3, [r7, #12]
+ 8022f06:	461c      	mov	r4, r3
+ 8022f08:	f107 0318 	add.w	r3, r7, #24
+ 8022f0c:	cb0f      	ldmia	r3, {r0, r1, r2, r3}
+ 8022f0e:	e884 000f 	stmia.w	r4, {r0, r1, r2, r3}
+}
+ 8022f12:	68f8      	ldr	r0, [r7, #12]
+ 8022f14:	3728      	adds	r7, #40	@ 0x28
+ 8022f16:	46bd      	mov	sp, r7
+ 8022f18:	bc90      	pop	{r4, r7}
+ 8022f1a:	4770      	bx	lr
+ 8022f1c:	08022d47 	.word	0x08022d47
+
+08022f20 <pb_decode_varint32_eof>:
+/********************
+ * Helper functions *
+ ********************/
+
+static bool checkreturn pb_decode_varint32_eof(pb_istream_t *stream, uint32_t *dest, bool *eof)
+{
+ 8022f20:	b580      	push	{r7, lr}
+ 8022f22:	b088      	sub	sp, #32
+ 8022f24:	af00      	add	r7, sp, #0
+ 8022f26:	60f8      	str	r0, [r7, #12]
+ 8022f28:	60b9      	str	r1, [r7, #8]
+ 8022f2a:	607a      	str	r2, [r7, #4]
+    pb_byte_t byte;
+    uint32_t result;
+    
+    if (!pb_readbyte(stream, &byte))
+ 8022f2c:	f107 0315 	add.w	r3, r7, #21
+ 8022f30:	4619      	mov	r1, r3
+ 8022f32:	68f8      	ldr	r0, [r7, #12]
+ 8022f34:	f7ff ff9a 	bl	8022e6c <pb_readbyte>
+ 8022f38:	4603      	mov	r3, r0
+ 8022f3a:	f083 0301 	eor.w	r3, r3, #1
+ 8022f3e:	b2db      	uxtb	r3, r3
+ 8022f40:	2b00      	cmp	r3, #0
+ 8022f42:	d00b      	beq.n	8022f5c <pb_decode_varint32_eof+0x3c>
+    {
+        if (stream->bytes_left == 0)
+ 8022f44:	68fb      	ldr	r3, [r7, #12]
+ 8022f46:	689b      	ldr	r3, [r3, #8]
+ 8022f48:	2b00      	cmp	r3, #0
+ 8022f4a:	d105      	bne.n	8022f58 <pb_decode_varint32_eof+0x38>
+        {
+            if (eof)
+ 8022f4c:	687b      	ldr	r3, [r7, #4]
+ 8022f4e:	2b00      	cmp	r3, #0
+ 8022f50:	d002      	beq.n	8022f58 <pb_decode_varint32_eof+0x38>
+            {
+                *eof = true;
+ 8022f52:	687b      	ldr	r3, [r7, #4]
+ 8022f54:	2201      	movs	r2, #1
+ 8022f56:	701a      	strb	r2, [r3, #0]
+            }
+        }
+
+        return false;
+ 8022f58:	2300      	movs	r3, #0
+ 8022f5a:	e084      	b.n	8023066 <pb_decode_varint32_eof+0x146>
+    }
+    
+    if ((byte & 0x80) == 0)
+ 8022f5c:	7d7b      	ldrb	r3, [r7, #21]
+ 8022f5e:	b25b      	sxtb	r3, r3
+ 8022f60:	2b00      	cmp	r3, #0
+ 8022f62:	db02      	blt.n	8022f6a <pb_decode_varint32_eof+0x4a>
+    {
+        /* Quick case, 1 byte value */
+        result = byte;
+ 8022f64:	7d7b      	ldrb	r3, [r7, #21]
+ 8022f66:	61fb      	str	r3, [r7, #28]
+ 8022f68:	e079      	b.n	802305e <pb_decode_varint32_eof+0x13e>
+    }
+    else
+    {
+        /* Multibyte case */
+        uint_fast8_t bitpos = 7;
+ 8022f6a:	2307      	movs	r3, #7
+ 8022f6c:	61bb      	str	r3, [r7, #24]
+        result = byte & 0x7F;
+ 8022f6e:	7d7b      	ldrb	r3, [r7, #21]
+ 8022f70:	f003 037f 	and.w	r3, r3, #127	@ 0x7f
+ 8022f74:	61fb      	str	r3, [r7, #28]
+        
+        do
+        {
+            if (!pb_readbyte(stream, &byte))
+ 8022f76:	f107 0315 	add.w	r3, r7, #21
+ 8022f7a:	4619      	mov	r1, r3
+ 8022f7c:	68f8      	ldr	r0, [r7, #12]
+ 8022f7e:	f7ff ff75 	bl	8022e6c <pb_readbyte>
+ 8022f82:	4603      	mov	r3, r0
+ 8022f84:	f083 0301 	eor.w	r3, r3, #1
+ 8022f88:	b2db      	uxtb	r3, r3
+ 8022f8a:	2b00      	cmp	r3, #0
+ 8022f8c:	d001      	beq.n	8022f92 <pb_decode_varint32_eof+0x72>
+                return false;
+ 8022f8e:	2300      	movs	r3, #0
+ 8022f90:	e069      	b.n	8023066 <pb_decode_varint32_eof+0x146>
+            
+            if (bitpos >= 32)
+ 8022f92:	69bb      	ldr	r3, [r7, #24]
+ 8022f94:	2b1f      	cmp	r3, #31
+ 8022f96:	d92f      	bls.n	8022ff8 <pb_decode_varint32_eof+0xd8>
+            {
+                /* Note: The varint could have trailing 0x80 bytes, or 0xFF for negative. */
+                pb_byte_t sign_extension = (bitpos < 63) ? 0xFF : 0x01;
+ 8022f98:	69bb      	ldr	r3, [r7, #24]
+ 8022f9a:	2b3e      	cmp	r3, #62	@ 0x3e
+ 8022f9c:	d801      	bhi.n	8022fa2 <pb_decode_varint32_eof+0x82>
+ 8022f9e:	23ff      	movs	r3, #255	@ 0xff
+ 8022fa0:	e000      	b.n	8022fa4 <pb_decode_varint32_eof+0x84>
+ 8022fa2:	2301      	movs	r3, #1
+ 8022fa4:	75fb      	strb	r3, [r7, #23]
+                bool valid_extension = ((byte & 0x7F) == 0x00 ||
+ 8022fa6:	7d7b      	ldrb	r3, [r7, #21]
+ 8022fa8:	f003 037f 	and.w	r3, r3, #127	@ 0x7f
+ 8022fac:	2b00      	cmp	r3, #0
+ 8022fae:	d006      	beq.n	8022fbe <pb_decode_varint32_eof+0x9e>
+                         ((result >> 31) != 0 && byte == sign_extension));
+ 8022fb0:	69fb      	ldr	r3, [r7, #28]
+                bool valid_extension = ((byte & 0x7F) == 0x00 ||
+ 8022fb2:	2b00      	cmp	r3, #0
+ 8022fb4:	da05      	bge.n	8022fc2 <pb_decode_varint32_eof+0xa2>
+                         ((result >> 31) != 0 && byte == sign_extension));
+ 8022fb6:	7d7b      	ldrb	r3, [r7, #21]
+ 8022fb8:	7dfa      	ldrb	r2, [r7, #23]
+ 8022fba:	429a      	cmp	r2, r3
+ 8022fbc:	d101      	bne.n	8022fc2 <pb_decode_varint32_eof+0xa2>
+                bool valid_extension = ((byte & 0x7F) == 0x00 ||
+ 8022fbe:	2301      	movs	r3, #1
+ 8022fc0:	e000      	b.n	8022fc4 <pb_decode_varint32_eof+0xa4>
+ 8022fc2:	2300      	movs	r3, #0
+ 8022fc4:	75bb      	strb	r3, [r7, #22]
+ 8022fc6:	7dbb      	ldrb	r3, [r7, #22]
+ 8022fc8:	f003 0301 	and.w	r3, r3, #1
+ 8022fcc:	75bb      	strb	r3, [r7, #22]
+
+                if (bitpos >= 64 || !valid_extension)
+ 8022fce:	69bb      	ldr	r3, [r7, #24]
+ 8022fd0:	2b3f      	cmp	r3, #63	@ 0x3f
+ 8022fd2:	d805      	bhi.n	8022fe0 <pb_decode_varint32_eof+0xc0>
+ 8022fd4:	7dbb      	ldrb	r3, [r7, #22]
+ 8022fd6:	f083 0301 	eor.w	r3, r3, #1
+ 8022fda:	b2db      	uxtb	r3, r3
+ 8022fdc:	2b00      	cmp	r3, #0
+ 8022fde:	d037      	beq.n	8023050 <pb_decode_varint32_eof+0x130>
+                {
+                    PB_RETURN_ERROR(stream, "varint overflow");
+ 8022fe0:	68fb      	ldr	r3, [r7, #12]
+ 8022fe2:	68db      	ldr	r3, [r3, #12]
+ 8022fe4:	2b00      	cmp	r3, #0
+ 8022fe6:	d002      	beq.n	8022fee <pb_decode_varint32_eof+0xce>
+ 8022fe8:	68fb      	ldr	r3, [r7, #12]
+ 8022fea:	68db      	ldr	r3, [r3, #12]
+ 8022fec:	e000      	b.n	8022ff0 <pb_decode_varint32_eof+0xd0>
+ 8022fee:	4b20      	ldr	r3, [pc, #128]	@ (8023070 <pb_decode_varint32_eof+0x150>)
+ 8022ff0:	68fa      	ldr	r2, [r7, #12]
+ 8022ff2:	60d3      	str	r3, [r2, #12]
+ 8022ff4:	2300      	movs	r3, #0
+ 8022ff6:	e036      	b.n	8023066 <pb_decode_varint32_eof+0x146>
+                }
+            }
+            else if (bitpos == 28)
+ 8022ff8:	69bb      	ldr	r3, [r7, #24]
+ 8022ffa:	2b1c      	cmp	r3, #28
+ 8022ffc:	d11f      	bne.n	802303e <pb_decode_varint32_eof+0x11e>
+            {
+                if ((byte & 0x70) != 0 && (byte & 0x78) != 0x78)
+ 8022ffe:	7d7b      	ldrb	r3, [r7, #21]
+ 8023000:	f003 0370 	and.w	r3, r3, #112	@ 0x70
+ 8023004:	2b00      	cmp	r3, #0
+ 8023006:	d010      	beq.n	802302a <pb_decode_varint32_eof+0x10a>
+ 8023008:	7d7b      	ldrb	r3, [r7, #21]
+ 802300a:	f003 0378 	and.w	r3, r3, #120	@ 0x78
+ 802300e:	2b78      	cmp	r3, #120	@ 0x78
+ 8023010:	d00b      	beq.n	802302a <pb_decode_varint32_eof+0x10a>
+                {
+                    PB_RETURN_ERROR(stream, "varint overflow");
+ 8023012:	68fb      	ldr	r3, [r7, #12]
+ 8023014:	68db      	ldr	r3, [r3, #12]
+ 8023016:	2b00      	cmp	r3, #0
+ 8023018:	d002      	beq.n	8023020 <pb_decode_varint32_eof+0x100>
+ 802301a:	68fb      	ldr	r3, [r7, #12]
+ 802301c:	68db      	ldr	r3, [r3, #12]
+ 802301e:	e000      	b.n	8023022 <pb_decode_varint32_eof+0x102>
+ 8023020:	4b13      	ldr	r3, [pc, #76]	@ (8023070 <pb_decode_varint32_eof+0x150>)
+ 8023022:	68fa      	ldr	r2, [r7, #12]
+ 8023024:	60d3      	str	r3, [r2, #12]
+ 8023026:	2300      	movs	r3, #0
+ 8023028:	e01d      	b.n	8023066 <pb_decode_varint32_eof+0x146>
+                }
+                result |= (uint32_t)(byte & 0x0F) << bitpos;
+ 802302a:	7d7b      	ldrb	r3, [r7, #21]
+ 802302c:	f003 020f 	and.w	r2, r3, #15
+ 8023030:	69bb      	ldr	r3, [r7, #24]
+ 8023032:	fa02 f303 	lsl.w	r3, r2, r3
+ 8023036:	69fa      	ldr	r2, [r7, #28]
+ 8023038:	4313      	orrs	r3, r2
+ 802303a:	61fb      	str	r3, [r7, #28]
+ 802303c:	e008      	b.n	8023050 <pb_decode_varint32_eof+0x130>
+            }
+            else
+            {
+                result |= (uint32_t)(byte & 0x7F) << bitpos;
+ 802303e:	7d7b      	ldrb	r3, [r7, #21]
+ 8023040:	f003 027f 	and.w	r2, r3, #127	@ 0x7f
+ 8023044:	69bb      	ldr	r3, [r7, #24]
+ 8023046:	fa02 f303 	lsl.w	r3, r2, r3
+ 802304a:	69fa      	ldr	r2, [r7, #28]
+ 802304c:	4313      	orrs	r3, r2
+ 802304e:	61fb      	str	r3, [r7, #28]
+            }
+            bitpos = (uint_fast8_t)(bitpos + 7);
+ 8023050:	69bb      	ldr	r3, [r7, #24]
+ 8023052:	3307      	adds	r3, #7
+ 8023054:	61bb      	str	r3, [r7, #24]
+        } while (byte & 0x80);
+ 8023056:	7d7b      	ldrb	r3, [r7, #21]
+ 8023058:	b25b      	sxtb	r3, r3
+ 802305a:	2b00      	cmp	r3, #0
+ 802305c:	db8b      	blt.n	8022f76 <pb_decode_varint32_eof+0x56>
+   }
+   
+   *dest = result;
+ 802305e:	68bb      	ldr	r3, [r7, #8]
+ 8023060:	69fa      	ldr	r2, [r7, #28]
+ 8023062:	601a      	str	r2, [r3, #0]
+   return true;
+ 8023064:	2301      	movs	r3, #1
+}
+ 8023066:	4618      	mov	r0, r3
+ 8023068:	3720      	adds	r7, #32
+ 802306a:	46bd      	mov	sp, r7
+ 802306c:	bd80      	pop	{r7, pc}
+ 802306e:	bf00      	nop
+ 8023070:	0804102c 	.word	0x0804102c
+
+08023074 <pb_decode_varint32>:
+
+bool checkreturn pb_decode_varint32(pb_istream_t *stream, uint32_t *dest)
+{
+ 8023074:	b580      	push	{r7, lr}
+ 8023076:	b082      	sub	sp, #8
+ 8023078:	af00      	add	r7, sp, #0
+ 802307a:	6078      	str	r0, [r7, #4]
+ 802307c:	6039      	str	r1, [r7, #0]
+    return pb_decode_varint32_eof(stream, dest, NULL);
+ 802307e:	2200      	movs	r2, #0
+ 8023080:	6839      	ldr	r1, [r7, #0]
+ 8023082:	6878      	ldr	r0, [r7, #4]
+ 8023084:	f7ff ff4c 	bl	8022f20 <pb_decode_varint32_eof>
+ 8023088:	4603      	mov	r3, r0
+}
+ 802308a:	4618      	mov	r0, r3
+ 802308c:	3708      	adds	r7, #8
+ 802308e:	46bd      	mov	sp, r7
+ 8023090:	bd80      	pop	{r7, pc}
+	...
+
+08023094 <pb_decode_varint>:
+
+#ifndef PB_WITHOUT_64BIT
+bool checkreturn pb_decode_varint(pb_istream_t *stream, uint64_t *dest)
+{
+ 8023094:	e92d 4fb0 	stmdb	sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
+ 8023098:	b08a      	sub	sp, #40	@ 0x28
+ 802309a:	af00      	add	r7, sp, #0
+ 802309c:	60f8      	str	r0, [r7, #12]
+ 802309e:	60b9      	str	r1, [r7, #8]
+    pb_byte_t byte;
+    uint_fast8_t bitpos = 0;
+ 80230a0:	2300      	movs	r3, #0
+ 80230a2:	627b      	str	r3, [r7, #36]	@ 0x24
+    uint64_t result = 0;
+ 80230a4:	f04f 0200 	mov.w	r2, #0
+ 80230a8:	f04f 0300 	mov.w	r3, #0
+ 80230ac:	e9c7 2306 	strd	r2, r3, [r7, #24]
+    
+    do
+    {
+        if (!pb_readbyte(stream, &byte))
+ 80230b0:	f107 0317 	add.w	r3, r7, #23
+ 80230b4:	4619      	mov	r1, r3
+ 80230b6:	68f8      	ldr	r0, [r7, #12]
+ 80230b8:	f7ff fed8 	bl	8022e6c <pb_readbyte>
+ 80230bc:	4603      	mov	r3, r0
+ 80230be:	f083 0301 	eor.w	r3, r3, #1
+ 80230c2:	b2db      	uxtb	r3, r3
+ 80230c4:	2b00      	cmp	r3, #0
+ 80230c6:	d001      	beq.n	80230cc <pb_decode_varint+0x38>
+            return false;
+ 80230c8:	2300      	movs	r3, #0
+ 80230ca:	e041      	b.n	8023150 <pb_decode_varint+0xbc>
+
+        if (bitpos >= 63 && (byte & 0xFE) != 0)
+ 80230cc:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 80230ce:	2b3e      	cmp	r3, #62	@ 0x3e
+ 80230d0:	d910      	bls.n	80230f4 <pb_decode_varint+0x60>
+ 80230d2:	7dfb      	ldrb	r3, [r7, #23]
+ 80230d4:	f003 03fe 	and.w	r3, r3, #254	@ 0xfe
+ 80230d8:	2b00      	cmp	r3, #0
+ 80230da:	d00b      	beq.n	80230f4 <pb_decode_varint+0x60>
+            PB_RETURN_ERROR(stream, "varint overflow");
+ 80230dc:	68fb      	ldr	r3, [r7, #12]
+ 80230de:	68db      	ldr	r3, [r3, #12]
+ 80230e0:	2b00      	cmp	r3, #0
+ 80230e2:	d002      	beq.n	80230ea <pb_decode_varint+0x56>
+ 80230e4:	68fb      	ldr	r3, [r7, #12]
+ 80230e6:	68db      	ldr	r3, [r3, #12]
+ 80230e8:	e000      	b.n	80230ec <pb_decode_varint+0x58>
+ 80230ea:	4b1c      	ldr	r3, [pc, #112]	@ (802315c <pb_decode_varint+0xc8>)
+ 80230ec:	68fa      	ldr	r2, [r7, #12]
+ 80230ee:	60d3      	str	r3, [r2, #12]
+ 80230f0:	2300      	movs	r3, #0
+ 80230f2:	e02d      	b.n	8023150 <pb_decode_varint+0xbc>
+
+        result |= (uint64_t)(byte & 0x7F) << bitpos;
+ 80230f4:	7dfb      	ldrb	r3, [r7, #23]
+ 80230f6:	b2db      	uxtb	r3, r3
+ 80230f8:	2200      	movs	r2, #0
+ 80230fa:	603b      	str	r3, [r7, #0]
+ 80230fc:	607a      	str	r2, [r7, #4]
+ 80230fe:	683b      	ldr	r3, [r7, #0]
+ 8023100:	f003 087f 	and.w	r8, r3, #127	@ 0x7f
+ 8023104:	f04f 0900 	mov.w	r9, #0
+ 8023108:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 802310a:	f1a3 0120 	sub.w	r1, r3, #32
+ 802310e:	f1c3 0220 	rsb	r2, r3, #32
+ 8023112:	fa09 f503 	lsl.w	r5, r9, r3
+ 8023116:	fa08 f101 	lsl.w	r1, r8, r1
+ 802311a:	430d      	orrs	r5, r1
+ 802311c:	fa28 f202 	lsr.w	r2, r8, r2
+ 8023120:	4315      	orrs	r5, r2
+ 8023122:	fa08 f403 	lsl.w	r4, r8, r3
+ 8023126:	e9d7 2306 	ldrd	r2, r3, [r7, #24]
+ 802312a:	ea42 0a04 	orr.w	sl, r2, r4
+ 802312e:	ea43 0b05 	orr.w	fp, r3, r5
+ 8023132:	e9c7 ab06 	strd	sl, fp, [r7, #24]
+        bitpos = (uint_fast8_t)(bitpos + 7);
+ 8023136:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 8023138:	3307      	adds	r3, #7
+ 802313a:	627b      	str	r3, [r7, #36]	@ 0x24
+    } while (byte & 0x80);
+ 802313c:	7dfb      	ldrb	r3, [r7, #23]
+ 802313e:	b25b      	sxtb	r3, r3
+ 8023140:	2b00      	cmp	r3, #0
+ 8023142:	dbb5      	blt.n	80230b0 <pb_decode_varint+0x1c>
+    
+    *dest = result;
+ 8023144:	68b9      	ldr	r1, [r7, #8]
+ 8023146:	e9d7 2306 	ldrd	r2, r3, [r7, #24]
+ 802314a:	e9c1 2300 	strd	r2, r3, [r1]
+    return true;
+ 802314e:	2301      	movs	r3, #1
+}
+ 8023150:	4618      	mov	r0, r3
+ 8023152:	3728      	adds	r7, #40	@ 0x28
+ 8023154:	46bd      	mov	sp, r7
+ 8023156:	e8bd 8fb0 	ldmia.w	sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
+ 802315a:	bf00      	nop
+ 802315c:	0804102c 	.word	0x0804102c
+
+08023160 <pb_skip_varint>:
+#endif
+
+bool checkreturn pb_skip_varint(pb_istream_t *stream)
+{
+ 8023160:	b580      	push	{r7, lr}
+ 8023162:	b084      	sub	sp, #16
+ 8023164:	af00      	add	r7, sp, #0
+ 8023166:	6078      	str	r0, [r7, #4]
+    pb_byte_t byte;
+    do
+    {
+        if (!pb_read(stream, &byte, 1))
+ 8023168:	f107 030f 	add.w	r3, r7, #15
+ 802316c:	2201      	movs	r2, #1
+ 802316e:	4619      	mov	r1, r3
+ 8023170:	6878      	ldr	r0, [r7, #4]
+ 8023172:	f7ff fe05 	bl	8022d80 <pb_read>
+ 8023176:	4603      	mov	r3, r0
+ 8023178:	f083 0301 	eor.w	r3, r3, #1
+ 802317c:	b2db      	uxtb	r3, r3
+ 802317e:	2b00      	cmp	r3, #0
+ 8023180:	d001      	beq.n	8023186 <pb_skip_varint+0x26>
+            return false;
+ 8023182:	2300      	movs	r3, #0
+ 8023184:	e004      	b.n	8023190 <pb_skip_varint+0x30>
+    } while (byte & 0x80);
+ 8023186:	7bfb      	ldrb	r3, [r7, #15]
+ 8023188:	b25b      	sxtb	r3, r3
+ 802318a:	2b00      	cmp	r3, #0
+ 802318c:	dbec      	blt.n	8023168 <pb_skip_varint+0x8>
+    return true;
+ 802318e:	2301      	movs	r3, #1
+}
+ 8023190:	4618      	mov	r0, r3
+ 8023192:	3710      	adds	r7, #16
+ 8023194:	46bd      	mov	sp, r7
+ 8023196:	bd80      	pop	{r7, pc}
+
+08023198 <pb_skip_string>:
+
+bool checkreturn pb_skip_string(pb_istream_t *stream)
+{
+ 8023198:	b580      	push	{r7, lr}
+ 802319a:	b084      	sub	sp, #16
+ 802319c:	af00      	add	r7, sp, #0
+ 802319e:	6078      	str	r0, [r7, #4]
+    uint32_t length;
+    if (!pb_decode_varint32(stream, &length))
+ 80231a0:	f107 030c 	add.w	r3, r7, #12
+ 80231a4:	4619      	mov	r1, r3
+ 80231a6:	6878      	ldr	r0, [r7, #4]
+ 80231a8:	f7ff ff64 	bl	8023074 <pb_decode_varint32>
+ 80231ac:	4603      	mov	r3, r0
+ 80231ae:	f083 0301 	eor.w	r3, r3, #1
+ 80231b2:	b2db      	uxtb	r3, r3
+ 80231b4:	2b00      	cmp	r3, #0
+ 80231b6:	d001      	beq.n	80231bc <pb_skip_string+0x24>
+        return false;
+ 80231b8:	2300      	movs	r3, #0
+ 80231ba:	e006      	b.n	80231ca <pb_skip_string+0x32>
+    if ((size_t)length != length)
+    {
+        PB_RETURN_ERROR(stream, "size too large");
+    }
+
+    return pb_read(stream, NULL, (size_t)length);
+ 80231bc:	68fb      	ldr	r3, [r7, #12]
+ 80231be:	461a      	mov	r2, r3
+ 80231c0:	2100      	movs	r1, #0
+ 80231c2:	6878      	ldr	r0, [r7, #4]
+ 80231c4:	f7ff fddc 	bl	8022d80 <pb_read>
+ 80231c8:	4603      	mov	r3, r0
+}
+ 80231ca:	4618      	mov	r0, r3
+ 80231cc:	3710      	adds	r7, #16
+ 80231ce:	46bd      	mov	sp, r7
+ 80231d0:	bd80      	pop	{r7, pc}
+
+080231d2 <pb_decode_tag>:
+
+bool checkreturn pb_decode_tag(pb_istream_t *stream, pb_wire_type_t *wire_type, uint32_t *tag, bool *eof)
+{
+ 80231d2:	b580      	push	{r7, lr}
+ 80231d4:	b086      	sub	sp, #24
+ 80231d6:	af00      	add	r7, sp, #0
+ 80231d8:	60f8      	str	r0, [r7, #12]
+ 80231da:	60b9      	str	r1, [r7, #8]
+ 80231dc:	607a      	str	r2, [r7, #4]
+ 80231de:	603b      	str	r3, [r7, #0]
+    uint32_t temp;
+    *eof = false;
+ 80231e0:	683b      	ldr	r3, [r7, #0]
+ 80231e2:	2200      	movs	r2, #0
+ 80231e4:	701a      	strb	r2, [r3, #0]
+    *wire_type = (pb_wire_type_t) 0;
+ 80231e6:	68bb      	ldr	r3, [r7, #8]
+ 80231e8:	2200      	movs	r2, #0
+ 80231ea:	701a      	strb	r2, [r3, #0]
+    *tag = 0;
+ 80231ec:	687b      	ldr	r3, [r7, #4]
+ 80231ee:	2200      	movs	r2, #0
+ 80231f0:	601a      	str	r2, [r3, #0]
+    
+    if (!pb_decode_varint32_eof(stream, &temp, eof))
+ 80231f2:	f107 0314 	add.w	r3, r7, #20
+ 80231f6:	683a      	ldr	r2, [r7, #0]
+ 80231f8:	4619      	mov	r1, r3
+ 80231fa:	68f8      	ldr	r0, [r7, #12]
+ 80231fc:	f7ff fe90 	bl	8022f20 <pb_decode_varint32_eof>
+ 8023200:	4603      	mov	r3, r0
+ 8023202:	f083 0301 	eor.w	r3, r3, #1
+ 8023206:	b2db      	uxtb	r3, r3
+ 8023208:	2b00      	cmp	r3, #0
+ 802320a:	d001      	beq.n	8023210 <pb_decode_tag+0x3e>
+    {
+        return false;
+ 802320c:	2300      	movs	r3, #0
+ 802320e:	e00b      	b.n	8023228 <pb_decode_tag+0x56>
+    }
+    
+    *tag = temp >> 3;
+ 8023210:	697b      	ldr	r3, [r7, #20]
+ 8023212:	08da      	lsrs	r2, r3, #3
+ 8023214:	687b      	ldr	r3, [r7, #4]
+ 8023216:	601a      	str	r2, [r3, #0]
+    *wire_type = (pb_wire_type_t)(temp & 7);
+ 8023218:	697b      	ldr	r3, [r7, #20]
+ 802321a:	b2db      	uxtb	r3, r3
+ 802321c:	f003 0307 	and.w	r3, r3, #7
+ 8023220:	b2da      	uxtb	r2, r3
+ 8023222:	68bb      	ldr	r3, [r7, #8]
+ 8023224:	701a      	strb	r2, [r3, #0]
+    return true;
+ 8023226:	2301      	movs	r3, #1
+}
+ 8023228:	4618      	mov	r0, r3
+ 802322a:	3718      	adds	r7, #24
+ 802322c:	46bd      	mov	sp, r7
+ 802322e:	bd80      	pop	{r7, pc}
+
+08023230 <pb_skip_field>:
+
+bool checkreturn pb_skip_field(pb_istream_t *stream, pb_wire_type_t wire_type)
+{
+ 8023230:	b580      	push	{r7, lr}
+ 8023232:	b082      	sub	sp, #8
+ 8023234:	af00      	add	r7, sp, #0
+ 8023236:	6078      	str	r0, [r7, #4]
+ 8023238:	460b      	mov	r3, r1
+ 802323a:	70fb      	strb	r3, [r7, #3]
+    switch (wire_type)
+ 802323c:	78fb      	ldrb	r3, [r7, #3]
+ 802323e:	2b05      	cmp	r3, #5
+ 8023240:	d826      	bhi.n	8023290 <pb_skip_field+0x60>
+ 8023242:	a201      	add	r2, pc, #4	@ (adr r2, 8023248 <pb_skip_field+0x18>)
+ 8023244:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 8023248:	08023261 	.word	0x08023261
+ 802324c:	0802326b 	.word	0x0802326b
+ 8023250:	08023279 	.word	0x08023279
+ 8023254:	08023291 	.word	0x08023291
+ 8023258:	08023291 	.word	0x08023291
+ 802325c:	08023283 	.word	0x08023283
+    {
+        case PB_WT_VARINT: return pb_skip_varint(stream);
+ 8023260:	6878      	ldr	r0, [r7, #4]
+ 8023262:	f7ff ff7d 	bl	8023160 <pb_skip_varint>
+ 8023266:	4603      	mov	r3, r0
+ 8023268:	e01d      	b.n	80232a6 <pb_skip_field+0x76>
+        case PB_WT_64BIT: return pb_read(stream, NULL, 8);
+ 802326a:	2208      	movs	r2, #8
+ 802326c:	2100      	movs	r1, #0
+ 802326e:	6878      	ldr	r0, [r7, #4]
+ 8023270:	f7ff fd86 	bl	8022d80 <pb_read>
+ 8023274:	4603      	mov	r3, r0
+ 8023276:	e016      	b.n	80232a6 <pb_skip_field+0x76>
+        case PB_WT_STRING: return pb_skip_string(stream);
+ 8023278:	6878      	ldr	r0, [r7, #4]
+ 802327a:	f7ff ff8d 	bl	8023198 <pb_skip_string>
+ 802327e:	4603      	mov	r3, r0
+ 8023280:	e011      	b.n	80232a6 <pb_skip_field+0x76>
+        case PB_WT_32BIT: return pb_read(stream, NULL, 4);
+ 8023282:	2204      	movs	r2, #4
+ 8023284:	2100      	movs	r1, #0
+ 8023286:	6878      	ldr	r0, [r7, #4]
+ 8023288:	f7ff fd7a 	bl	8022d80 <pb_read>
+ 802328c:	4603      	mov	r3, r0
+ 802328e:	e00a      	b.n	80232a6 <pb_skip_field+0x76>
+        default: PB_RETURN_ERROR(stream, "invalid wire_type");
+ 8023290:	687b      	ldr	r3, [r7, #4]
+ 8023292:	68db      	ldr	r3, [r3, #12]
+ 8023294:	2b00      	cmp	r3, #0
+ 8023296:	d002      	beq.n	802329e <pb_skip_field+0x6e>
+ 8023298:	687b      	ldr	r3, [r7, #4]
+ 802329a:	68db      	ldr	r3, [r3, #12]
+ 802329c:	e000      	b.n	80232a0 <pb_skip_field+0x70>
+ 802329e:	4b04      	ldr	r3, [pc, #16]	@ (80232b0 <pb_skip_field+0x80>)
+ 80232a0:	687a      	ldr	r2, [r7, #4]
+ 80232a2:	60d3      	str	r3, [r2, #12]
+ 80232a4:	2300      	movs	r3, #0
+    }
+}
+ 80232a6:	4618      	mov	r0, r3
+ 80232a8:	3708      	adds	r7, #8
+ 80232aa:	46bd      	mov	sp, r7
+ 80232ac:	bd80      	pop	{r7, pc}
+ 80232ae:	bf00      	nop
+ 80232b0:	0804103c 	.word	0x0804103c
+
+080232b4 <read_raw_value>:
+
+/* Read a raw value to buffer, for the purpose of passing it to callback as
+ * a substream. Size is maximum size on call, and actual size on return.
+ */
+static bool checkreturn read_raw_value(pb_istream_t *stream, pb_wire_type_t wire_type, pb_byte_t *buf, size_t *size)
+{
+ 80232b4:	b580      	push	{r7, lr}
+ 80232b6:	b086      	sub	sp, #24
+ 80232b8:	af00      	add	r7, sp, #0
+ 80232ba:	60f8      	str	r0, [r7, #12]
+ 80232bc:	607a      	str	r2, [r7, #4]
+ 80232be:	603b      	str	r3, [r7, #0]
+ 80232c0:	460b      	mov	r3, r1
+ 80232c2:	72fb      	strb	r3, [r7, #11]
+    size_t max_size = *size;
+ 80232c4:	683b      	ldr	r3, [r7, #0]
+ 80232c6:	681b      	ldr	r3, [r3, #0]
+ 80232c8:	617b      	str	r3, [r7, #20]
+    switch (wire_type)
+ 80232ca:	7afb      	ldrb	r3, [r7, #11]
+ 80232cc:	2b05      	cmp	r3, #5
+ 80232ce:	d03f      	beq.n	8023350 <read_raw_value+0x9c>
+ 80232d0:	2b05      	cmp	r3, #5
+ 80232d2:	dc47      	bgt.n	8023364 <read_raw_value+0xb0>
+ 80232d4:	2b00      	cmp	r3, #0
+ 80232d6:	d002      	beq.n	80232de <read_raw_value+0x2a>
+ 80232d8:	2b01      	cmp	r3, #1
+ 80232da:	d02f      	beq.n	802333c <read_raw_value+0x88>
+ 80232dc:	e042      	b.n	8023364 <read_raw_value+0xb0>
+    {
+        case PB_WT_VARINT:
+            *size = 0;
+ 80232de:	683b      	ldr	r3, [r7, #0]
+ 80232e0:	2200      	movs	r2, #0
+ 80232e2:	601a      	str	r2, [r3, #0]
+            do
+            {
+                (*size)++;
+ 80232e4:	683b      	ldr	r3, [r7, #0]
+ 80232e6:	681b      	ldr	r3, [r3, #0]
+ 80232e8:	1c5a      	adds	r2, r3, #1
+ 80232ea:	683b      	ldr	r3, [r7, #0]
+ 80232ec:	601a      	str	r2, [r3, #0]
+                if (*size > max_size)
+ 80232ee:	683b      	ldr	r3, [r7, #0]
+ 80232f0:	681b      	ldr	r3, [r3, #0]
+ 80232f2:	697a      	ldr	r2, [r7, #20]
+ 80232f4:	429a      	cmp	r2, r3
+ 80232f6:	d20b      	bcs.n	8023310 <read_raw_value+0x5c>
+                    PB_RETURN_ERROR(stream, "varint overflow");
+ 80232f8:	68fb      	ldr	r3, [r7, #12]
+ 80232fa:	68db      	ldr	r3, [r3, #12]
+ 80232fc:	2b00      	cmp	r3, #0
+ 80232fe:	d002      	beq.n	8023306 <read_raw_value+0x52>
+ 8023300:	68fb      	ldr	r3, [r7, #12]
+ 8023302:	68db      	ldr	r3, [r3, #12]
+ 8023304:	e000      	b.n	8023308 <read_raw_value+0x54>
+ 8023306:	4b1f      	ldr	r3, [pc, #124]	@ (8023384 <read_raw_value+0xd0>)
+ 8023308:	68fa      	ldr	r2, [r7, #12]
+ 802330a:	60d3      	str	r3, [r2, #12]
+ 802330c:	2300      	movs	r3, #0
+ 802330e:	e034      	b.n	802337a <read_raw_value+0xc6>
+
+                if (!pb_read(stream, buf, 1))
+ 8023310:	2201      	movs	r2, #1
+ 8023312:	6879      	ldr	r1, [r7, #4]
+ 8023314:	68f8      	ldr	r0, [r7, #12]
+ 8023316:	f7ff fd33 	bl	8022d80 <pb_read>
+ 802331a:	4603      	mov	r3, r0
+ 802331c:	f083 0301 	eor.w	r3, r3, #1
+ 8023320:	b2db      	uxtb	r3, r3
+ 8023322:	2b00      	cmp	r3, #0
+ 8023324:	d001      	beq.n	802332a <read_raw_value+0x76>
+                    return false;
+ 8023326:	2300      	movs	r3, #0
+ 8023328:	e027      	b.n	802337a <read_raw_value+0xc6>
+            } while (*buf++ & 0x80);
+ 802332a:	687b      	ldr	r3, [r7, #4]
+ 802332c:	1c5a      	adds	r2, r3, #1
+ 802332e:	607a      	str	r2, [r7, #4]
+ 8023330:	781b      	ldrb	r3, [r3, #0]
+ 8023332:	b25b      	sxtb	r3, r3
+ 8023334:	2b00      	cmp	r3, #0
+ 8023336:	dbd5      	blt.n	80232e4 <read_raw_value+0x30>
+            return true;
+ 8023338:	2301      	movs	r3, #1
+ 802333a:	e01e      	b.n	802337a <read_raw_value+0xc6>
+            
+        case PB_WT_64BIT:
+            *size = 8;
+ 802333c:	683b      	ldr	r3, [r7, #0]
+ 802333e:	2208      	movs	r2, #8
+ 8023340:	601a      	str	r2, [r3, #0]
+            return pb_read(stream, buf, 8);
+ 8023342:	2208      	movs	r2, #8
+ 8023344:	6879      	ldr	r1, [r7, #4]
+ 8023346:	68f8      	ldr	r0, [r7, #12]
+ 8023348:	f7ff fd1a 	bl	8022d80 <pb_read>
+ 802334c:	4603      	mov	r3, r0
+ 802334e:	e014      	b.n	802337a <read_raw_value+0xc6>
+        
+        case PB_WT_32BIT:
+            *size = 4;
+ 8023350:	683b      	ldr	r3, [r7, #0]
+ 8023352:	2204      	movs	r2, #4
+ 8023354:	601a      	str	r2, [r3, #0]
+            return pb_read(stream, buf, 4);
+ 8023356:	2204      	movs	r2, #4
+ 8023358:	6879      	ldr	r1, [r7, #4]
+ 802335a:	68f8      	ldr	r0, [r7, #12]
+ 802335c:	f7ff fd10 	bl	8022d80 <pb_read>
+ 8023360:	4603      	mov	r3, r0
+ 8023362:	e00a      	b.n	802337a <read_raw_value+0xc6>
+            /* Calling read_raw_value with a PB_WT_STRING is an error.
+             * Explicitly handle this case and fallthrough to default to avoid
+             * compiler warnings.
+             */
+
+        default: PB_RETURN_ERROR(stream, "invalid wire_type");
+ 8023364:	68fb      	ldr	r3, [r7, #12]
+ 8023366:	68db      	ldr	r3, [r3, #12]
+ 8023368:	2b00      	cmp	r3, #0
+ 802336a:	d002      	beq.n	8023372 <read_raw_value+0xbe>
+ 802336c:	68fb      	ldr	r3, [r7, #12]
+ 802336e:	68db      	ldr	r3, [r3, #12]
+ 8023370:	e000      	b.n	8023374 <read_raw_value+0xc0>
+ 8023372:	4b05      	ldr	r3, [pc, #20]	@ (8023388 <read_raw_value+0xd4>)
+ 8023374:	68fa      	ldr	r2, [r7, #12]
+ 8023376:	60d3      	str	r3, [r2, #12]
+ 8023378:	2300      	movs	r3, #0
+    }
+}
+ 802337a:	4618      	mov	r0, r3
+ 802337c:	3718      	adds	r7, #24
+ 802337e:	46bd      	mov	sp, r7
+ 8023380:	bd80      	pop	{r7, pc}
+ 8023382:	bf00      	nop
+ 8023384:	0804102c 	.word	0x0804102c
+ 8023388:	0804103c 	.word	0x0804103c
+
+0802338c <pb_make_string_substream>:
+
+/* Decode string length from stream and return a substream with limited length.
+ * Remember to close the substream using pb_close_string_substream().
+ */
+bool checkreturn pb_make_string_substream(pb_istream_t *stream, pb_istream_t *substream)
+{
+ 802338c:	b590      	push	{r4, r7, lr}
+ 802338e:	b085      	sub	sp, #20
+ 8023390:	af00      	add	r7, sp, #0
+ 8023392:	6078      	str	r0, [r7, #4]
+ 8023394:	6039      	str	r1, [r7, #0]
+    uint32_t size;
+    if (!pb_decode_varint32(stream, &size))
+ 8023396:	f107 030c 	add.w	r3, r7, #12
+ 802339a:	4619      	mov	r1, r3
+ 802339c:	6878      	ldr	r0, [r7, #4]
+ 802339e:	f7ff fe69 	bl	8023074 <pb_decode_varint32>
+ 80233a2:	4603      	mov	r3, r0
+ 80233a4:	f083 0301 	eor.w	r3, r3, #1
+ 80233a8:	b2db      	uxtb	r3, r3
+ 80233aa:	2b00      	cmp	r3, #0
+ 80233ac:	d001      	beq.n	80233b2 <pb_make_string_substream+0x26>
+        return false;
+ 80233ae:	2300      	movs	r3, #0
+ 80233b0:	e020      	b.n	80233f4 <pb_make_string_substream+0x68>
+    
+    *substream = *stream;
+ 80233b2:	683a      	ldr	r2, [r7, #0]
+ 80233b4:	687b      	ldr	r3, [r7, #4]
+ 80233b6:	4614      	mov	r4, r2
+ 80233b8:	cb0f      	ldmia	r3, {r0, r1, r2, r3}
+ 80233ba:	e884 000f 	stmia.w	r4, {r0, r1, r2, r3}
+    if (substream->bytes_left < size)
+ 80233be:	683b      	ldr	r3, [r7, #0]
+ 80233c0:	689a      	ldr	r2, [r3, #8]
+ 80233c2:	68fb      	ldr	r3, [r7, #12]
+ 80233c4:	429a      	cmp	r2, r3
+ 80233c6:	d20b      	bcs.n	80233e0 <pb_make_string_substream+0x54>
+        PB_RETURN_ERROR(stream, "parent stream too short");
+ 80233c8:	687b      	ldr	r3, [r7, #4]
+ 80233ca:	68db      	ldr	r3, [r3, #12]
+ 80233cc:	2b00      	cmp	r3, #0
+ 80233ce:	d002      	beq.n	80233d6 <pb_make_string_substream+0x4a>
+ 80233d0:	687b      	ldr	r3, [r7, #4]
+ 80233d2:	68db      	ldr	r3, [r3, #12]
+ 80233d4:	e000      	b.n	80233d8 <pb_make_string_substream+0x4c>
+ 80233d6:	4b09      	ldr	r3, [pc, #36]	@ (80233fc <pb_make_string_substream+0x70>)
+ 80233d8:	687a      	ldr	r2, [r7, #4]
+ 80233da:	60d3      	str	r3, [r2, #12]
+ 80233dc:	2300      	movs	r3, #0
+ 80233de:	e009      	b.n	80233f4 <pb_make_string_substream+0x68>
+    
+    substream->bytes_left = (size_t)size;
+ 80233e0:	68fa      	ldr	r2, [r7, #12]
+ 80233e2:	683b      	ldr	r3, [r7, #0]
+ 80233e4:	609a      	str	r2, [r3, #8]
+    stream->bytes_left -= (size_t)size;
+ 80233e6:	687b      	ldr	r3, [r7, #4]
+ 80233e8:	689a      	ldr	r2, [r3, #8]
+ 80233ea:	68fb      	ldr	r3, [r7, #12]
+ 80233ec:	1ad2      	subs	r2, r2, r3
+ 80233ee:	687b      	ldr	r3, [r7, #4]
+ 80233f0:	609a      	str	r2, [r3, #8]
+    return true;
+ 80233f2:	2301      	movs	r3, #1
+}
+ 80233f4:	4618      	mov	r0, r3
+ 80233f6:	3714      	adds	r7, #20
+ 80233f8:	46bd      	mov	sp, r7
+ 80233fa:	bd90      	pop	{r4, r7, pc}
+ 80233fc:	08041050 	.word	0x08041050
+
+08023400 <pb_close_string_substream>:
+
+bool checkreturn pb_close_string_substream(pb_istream_t *stream, pb_istream_t *substream)
+{
+ 8023400:	b580      	push	{r7, lr}
+ 8023402:	b082      	sub	sp, #8
+ 8023404:	af00      	add	r7, sp, #0
+ 8023406:	6078      	str	r0, [r7, #4]
+ 8023408:	6039      	str	r1, [r7, #0]
+    if (substream->bytes_left) {
+ 802340a:	683b      	ldr	r3, [r7, #0]
+ 802340c:	689b      	ldr	r3, [r3, #8]
+ 802340e:	2b00      	cmp	r3, #0
+ 8023410:	d00e      	beq.n	8023430 <pb_close_string_substream+0x30>
+        if (!pb_read(substream, NULL, substream->bytes_left))
+ 8023412:	683b      	ldr	r3, [r7, #0]
+ 8023414:	689b      	ldr	r3, [r3, #8]
+ 8023416:	461a      	mov	r2, r3
+ 8023418:	2100      	movs	r1, #0
+ 802341a:	6838      	ldr	r0, [r7, #0]
+ 802341c:	f7ff fcb0 	bl	8022d80 <pb_read>
+ 8023420:	4603      	mov	r3, r0
+ 8023422:	f083 0301 	eor.w	r3, r3, #1
+ 8023426:	b2db      	uxtb	r3, r3
+ 8023428:	2b00      	cmp	r3, #0
+ 802342a:	d001      	beq.n	8023430 <pb_close_string_substream+0x30>
+            return false;
+ 802342c:	2300      	movs	r3, #0
+ 802342e:	e008      	b.n	8023442 <pb_close_string_substream+0x42>
+    }
+
+    stream->state = substream->state;
+ 8023430:	683b      	ldr	r3, [r7, #0]
+ 8023432:	685a      	ldr	r2, [r3, #4]
+ 8023434:	687b      	ldr	r3, [r7, #4]
+ 8023436:	605a      	str	r2, [r3, #4]
+
+#ifndef PB_NO_ERRMSG
+    stream->errmsg = substream->errmsg;
+ 8023438:	683b      	ldr	r3, [r7, #0]
+ 802343a:	68da      	ldr	r2, [r3, #12]
+ 802343c:	687b      	ldr	r3, [r7, #4]
+ 802343e:	60da      	str	r2, [r3, #12]
+#endif
+    return true;
+ 8023440:	2301      	movs	r3, #1
+}
+ 8023442:	4618      	mov	r0, r3
+ 8023444:	3708      	adds	r7, #8
+ 8023446:	46bd      	mov	sp, r7
+ 8023448:	bd80      	pop	{r7, pc}
+	...
+
+0802344c <decode_basic_field>:
+/*************************
+ * Decode a single field *
+ *************************/
+
+static bool checkreturn decode_basic_field(pb_istream_t *stream, pb_wire_type_t wire_type, pb_field_iter_t *field)
+{
+ 802344c:	b580      	push	{r7, lr}
+ 802344e:	b084      	sub	sp, #16
+ 8023450:	af00      	add	r7, sp, #0
+ 8023452:	60f8      	str	r0, [r7, #12]
+ 8023454:	460b      	mov	r3, r1
+ 8023456:	607a      	str	r2, [r7, #4]
+ 8023458:	72fb      	strb	r3, [r7, #11]
+    switch (PB_LTYPE(field->type))
+ 802345a:	687b      	ldr	r3, [r7, #4]
+ 802345c:	7d9b      	ldrb	r3, [r3, #22]
+ 802345e:	f003 030f 	and.w	r3, r3, #15
+ 8023462:	2b0b      	cmp	r3, #11
+ 8023464:	f200 80d4 	bhi.w	8023610 <decode_basic_field+0x1c4>
+ 8023468:	a201      	add	r2, pc, #4	@ (adr r2, 8023470 <decode_basic_field+0x24>)
+ 802346a:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 802346e:	bf00      	nop
+ 8023470:	080234a1 	.word	0x080234a1
+ 8023474:	080234d1 	.word	0x080234d1
+ 8023478:	080234d1 	.word	0x080234d1
+ 802347c:	080234d1 	.word	0x080234d1
+ 8023480:	08023501 	.word	0x08023501
+ 8023484:	08023535 	.word	0x08023535
+ 8023488:	08023569 	.word	0x08023569
+ 802348c:	08023593 	.word	0x08023593
+ 8023490:	080235bd 	.word	0x080235bd
+ 8023494:	080235bd 	.word	0x080235bd
+ 8023498:	08023611 	.word	0x08023611
+ 802349c:	080235e7 	.word	0x080235e7
+    {
+        case PB_LTYPE_BOOL:
+            if (wire_type != PB_WT_VARINT && wire_type != PB_WT_PACKED)
+ 80234a0:	7afb      	ldrb	r3, [r7, #11]
+ 80234a2:	2b00      	cmp	r3, #0
+ 80234a4:	d00e      	beq.n	80234c4 <decode_basic_field+0x78>
+ 80234a6:	7afb      	ldrb	r3, [r7, #11]
+ 80234a8:	2bff      	cmp	r3, #255	@ 0xff
+ 80234aa:	d00b      	beq.n	80234c4 <decode_basic_field+0x78>
+                PB_RETURN_ERROR(stream, "wrong wire type");
+ 80234ac:	68fb      	ldr	r3, [r7, #12]
+ 80234ae:	68db      	ldr	r3, [r3, #12]
+ 80234b0:	2b00      	cmp	r3, #0
+ 80234b2:	d002      	beq.n	80234ba <decode_basic_field+0x6e>
+ 80234b4:	68fb      	ldr	r3, [r7, #12]
+ 80234b6:	68db      	ldr	r3, [r3, #12]
+ 80234b8:	e000      	b.n	80234bc <decode_basic_field+0x70>
+ 80234ba:	4b5d      	ldr	r3, [pc, #372]	@ (8023630 <decode_basic_field+0x1e4>)
+ 80234bc:	68fa      	ldr	r2, [r7, #12]
+ 80234be:	60d3      	str	r3, [r2, #12]
+ 80234c0:	2300      	movs	r3, #0
+ 80234c2:	e0b0      	b.n	8023626 <decode_basic_field+0x1da>
+
+            return pb_dec_bool(stream, field);
+ 80234c4:	6879      	ldr	r1, [r7, #4]
+ 80234c6:	68f8      	ldr	r0, [r7, #12]
+ 80234c8:	f000 fef6 	bl	80242b8 <pb_dec_bool>
+ 80234cc:	4603      	mov	r3, r0
+ 80234ce:	e0aa      	b.n	8023626 <decode_basic_field+0x1da>
+
+        case PB_LTYPE_VARINT:
+        case PB_LTYPE_UVARINT:
+        case PB_LTYPE_SVARINT:
+            if (wire_type != PB_WT_VARINT && wire_type != PB_WT_PACKED)
+ 80234d0:	7afb      	ldrb	r3, [r7, #11]
+ 80234d2:	2b00      	cmp	r3, #0
+ 80234d4:	d00e      	beq.n	80234f4 <decode_basic_field+0xa8>
+ 80234d6:	7afb      	ldrb	r3, [r7, #11]
+ 80234d8:	2bff      	cmp	r3, #255	@ 0xff
+ 80234da:	d00b      	beq.n	80234f4 <decode_basic_field+0xa8>
+                PB_RETURN_ERROR(stream, "wrong wire type");
+ 80234dc:	68fb      	ldr	r3, [r7, #12]
+ 80234de:	68db      	ldr	r3, [r3, #12]
+ 80234e0:	2b00      	cmp	r3, #0
+ 80234e2:	d002      	beq.n	80234ea <decode_basic_field+0x9e>
+ 80234e4:	68fb      	ldr	r3, [r7, #12]
+ 80234e6:	68db      	ldr	r3, [r3, #12]
+ 80234e8:	e000      	b.n	80234ec <decode_basic_field+0xa0>
+ 80234ea:	4b51      	ldr	r3, [pc, #324]	@ (8023630 <decode_basic_field+0x1e4>)
+ 80234ec:	68fa      	ldr	r2, [r7, #12]
+ 80234ee:	60d3      	str	r3, [r2, #12]
+ 80234f0:	2300      	movs	r3, #0
+ 80234f2:	e098      	b.n	8023626 <decode_basic_field+0x1da>
+
+            return pb_dec_varint(stream, field);
+ 80234f4:	6879      	ldr	r1, [r7, #4]
+ 80234f6:	68f8      	ldr	r0, [r7, #12]
+ 80234f8:	f000 feee 	bl	80242d8 <pb_dec_varint>
+ 80234fc:	4603      	mov	r3, r0
+ 80234fe:	e092      	b.n	8023626 <decode_basic_field+0x1da>
+
+        case PB_LTYPE_FIXED32:
+            if (wire_type != PB_WT_32BIT && wire_type != PB_WT_PACKED)
+ 8023500:	7afb      	ldrb	r3, [r7, #11]
+ 8023502:	2b05      	cmp	r3, #5
+ 8023504:	d00e      	beq.n	8023524 <decode_basic_field+0xd8>
+ 8023506:	7afb      	ldrb	r3, [r7, #11]
+ 8023508:	2bff      	cmp	r3, #255	@ 0xff
+ 802350a:	d00b      	beq.n	8023524 <decode_basic_field+0xd8>
+                PB_RETURN_ERROR(stream, "wrong wire type");
+ 802350c:	68fb      	ldr	r3, [r7, #12]
+ 802350e:	68db      	ldr	r3, [r3, #12]
+ 8023510:	2b00      	cmp	r3, #0
+ 8023512:	d002      	beq.n	802351a <decode_basic_field+0xce>
+ 8023514:	68fb      	ldr	r3, [r7, #12]
+ 8023516:	68db      	ldr	r3, [r3, #12]
+ 8023518:	e000      	b.n	802351c <decode_basic_field+0xd0>
+ 802351a:	4b45      	ldr	r3, [pc, #276]	@ (8023630 <decode_basic_field+0x1e4>)
+ 802351c:	68fa      	ldr	r2, [r7, #12]
+ 802351e:	60d3      	str	r3, [r2, #12]
+ 8023520:	2300      	movs	r3, #0
+ 8023522:	e080      	b.n	8023626 <decode_basic_field+0x1da>
+
+            return pb_decode_fixed32(stream, field->pData);
+ 8023524:	687b      	ldr	r3, [r7, #4]
+ 8023526:	69db      	ldr	r3, [r3, #28]
+ 8023528:	4619      	mov	r1, r3
+ 802352a:	68f8      	ldr	r0, [r7, #12]
+ 802352c:	f000 fe8a 	bl	8024244 <pb_decode_fixed32>
+ 8023530:	4603      	mov	r3, r0
+ 8023532:	e078      	b.n	8023626 <decode_basic_field+0x1da>
+
+        case PB_LTYPE_FIXED64:
+            if (wire_type != PB_WT_64BIT && wire_type != PB_WT_PACKED)
+ 8023534:	7afb      	ldrb	r3, [r7, #11]
+ 8023536:	2b01      	cmp	r3, #1
+ 8023538:	d00e      	beq.n	8023558 <decode_basic_field+0x10c>
+ 802353a:	7afb      	ldrb	r3, [r7, #11]
+ 802353c:	2bff      	cmp	r3, #255	@ 0xff
+ 802353e:	d00b      	beq.n	8023558 <decode_basic_field+0x10c>
+                PB_RETURN_ERROR(stream, "wrong wire type");
+ 8023540:	68fb      	ldr	r3, [r7, #12]
+ 8023542:	68db      	ldr	r3, [r3, #12]
+ 8023544:	2b00      	cmp	r3, #0
+ 8023546:	d002      	beq.n	802354e <decode_basic_field+0x102>
+ 8023548:	68fb      	ldr	r3, [r7, #12]
+ 802354a:	68db      	ldr	r3, [r3, #12]
+ 802354c:	e000      	b.n	8023550 <decode_basic_field+0x104>
+ 802354e:	4b38      	ldr	r3, [pc, #224]	@ (8023630 <decode_basic_field+0x1e4>)
+ 8023550:	68fa      	ldr	r2, [r7, #12]
+ 8023552:	60d3      	str	r3, [r2, #12]
+ 8023554:	2300      	movs	r3, #0
+ 8023556:	e066      	b.n	8023626 <decode_basic_field+0x1da>
+#endif
+
+#ifdef PB_WITHOUT_64BIT
+            PB_RETURN_ERROR(stream, "invalid data_size");
+#else
+            return pb_decode_fixed64(stream, field->pData);
+ 8023558:	687b      	ldr	r3, [r7, #4]
+ 802355a:	69db      	ldr	r3, [r3, #28]
+ 802355c:	4619      	mov	r1, r3
+ 802355e:	68f8      	ldr	r0, [r7, #12]
+ 8023560:	f000 fe8c 	bl	802427c <pb_decode_fixed64>
+ 8023564:	4603      	mov	r3, r0
+ 8023566:	e05e      	b.n	8023626 <decode_basic_field+0x1da>
+#endif
+
+        case PB_LTYPE_BYTES:
+            if (wire_type != PB_WT_STRING)
+ 8023568:	7afb      	ldrb	r3, [r7, #11]
+ 802356a:	2b02      	cmp	r3, #2
+ 802356c:	d00b      	beq.n	8023586 <decode_basic_field+0x13a>
+                PB_RETURN_ERROR(stream, "wrong wire type");
+ 802356e:	68fb      	ldr	r3, [r7, #12]
+ 8023570:	68db      	ldr	r3, [r3, #12]
+ 8023572:	2b00      	cmp	r3, #0
+ 8023574:	d002      	beq.n	802357c <decode_basic_field+0x130>
+ 8023576:	68fb      	ldr	r3, [r7, #12]
+ 8023578:	68db      	ldr	r3, [r3, #12]
+ 802357a:	e000      	b.n	802357e <decode_basic_field+0x132>
+ 802357c:	4b2c      	ldr	r3, [pc, #176]	@ (8023630 <decode_basic_field+0x1e4>)
+ 802357e:	68fa      	ldr	r2, [r7, #12]
+ 8023580:	60d3      	str	r3, [r2, #12]
+ 8023582:	2300      	movs	r3, #0
+ 8023584:	e04f      	b.n	8023626 <decode_basic_field+0x1da>
+
+            return pb_dec_bytes(stream, field);
+ 8023586:	6879      	ldr	r1, [r7, #4]
+ 8023588:	68f8      	ldr	r0, [r7, #12]
+ 802358a:	f000 ffd1 	bl	8024530 <pb_dec_bytes>
+ 802358e:	4603      	mov	r3, r0
+ 8023590:	e049      	b.n	8023626 <decode_basic_field+0x1da>
+
+        case PB_LTYPE_STRING:
+            if (wire_type != PB_WT_STRING)
+ 8023592:	7afb      	ldrb	r3, [r7, #11]
+ 8023594:	2b02      	cmp	r3, #2
+ 8023596:	d00b      	beq.n	80235b0 <decode_basic_field+0x164>
+                PB_RETURN_ERROR(stream, "wrong wire type");
+ 8023598:	68fb      	ldr	r3, [r7, #12]
+ 802359a:	68db      	ldr	r3, [r3, #12]
+ 802359c:	2b00      	cmp	r3, #0
+ 802359e:	d002      	beq.n	80235a6 <decode_basic_field+0x15a>
+ 80235a0:	68fb      	ldr	r3, [r7, #12]
+ 80235a2:	68db      	ldr	r3, [r3, #12]
+ 80235a4:	e000      	b.n	80235a8 <decode_basic_field+0x15c>
+ 80235a6:	4b22      	ldr	r3, [pc, #136]	@ (8023630 <decode_basic_field+0x1e4>)
+ 80235a8:	68fa      	ldr	r2, [r7, #12]
+ 80235aa:	60d3      	str	r3, [r2, #12]
+ 80235ac:	2300      	movs	r3, #0
+ 80235ae:	e03a      	b.n	8023626 <decode_basic_field+0x1da>
+
+            return pb_dec_string(stream, field);
+ 80235b0:	6879      	ldr	r1, [r7, #4]
+ 80235b2:	68f8      	ldr	r0, [r7, #12]
+ 80235b4:	f001 f830 	bl	8024618 <pb_dec_string>
+ 80235b8:	4603      	mov	r3, r0
+ 80235ba:	e034      	b.n	8023626 <decode_basic_field+0x1da>
+
+        case PB_LTYPE_SUBMESSAGE:
+        case PB_LTYPE_SUBMSG_W_CB:
+            if (wire_type != PB_WT_STRING)
+ 80235bc:	7afb      	ldrb	r3, [r7, #11]
+ 80235be:	2b02      	cmp	r3, #2
+ 80235c0:	d00b      	beq.n	80235da <decode_basic_field+0x18e>
+                PB_RETURN_ERROR(stream, "wrong wire type");
+ 80235c2:	68fb      	ldr	r3, [r7, #12]
+ 80235c4:	68db      	ldr	r3, [r3, #12]
+ 80235c6:	2b00      	cmp	r3, #0
+ 80235c8:	d002      	beq.n	80235d0 <decode_basic_field+0x184>
+ 80235ca:	68fb      	ldr	r3, [r7, #12]
+ 80235cc:	68db      	ldr	r3, [r3, #12]
+ 80235ce:	e000      	b.n	80235d2 <decode_basic_field+0x186>
+ 80235d0:	4b17      	ldr	r3, [pc, #92]	@ (8023630 <decode_basic_field+0x1e4>)
+ 80235d2:	68fa      	ldr	r2, [r7, #12]
+ 80235d4:	60d3      	str	r3, [r2, #12]
+ 80235d6:	2300      	movs	r3, #0
+ 80235d8:	e025      	b.n	8023626 <decode_basic_field+0x1da>
+
+            return pb_dec_submessage(stream, field);
+ 80235da:	6879      	ldr	r1, [r7, #4]
+ 80235dc:	68f8      	ldr	r0, [r7, #12]
+ 80235de:	f001 f897 	bl	8024710 <pb_dec_submessage>
+ 80235e2:	4603      	mov	r3, r0
+ 80235e4:	e01f      	b.n	8023626 <decode_basic_field+0x1da>
+
+        case PB_LTYPE_FIXED_LENGTH_BYTES:
+            if (wire_type != PB_WT_STRING)
+ 80235e6:	7afb      	ldrb	r3, [r7, #11]
+ 80235e8:	2b02      	cmp	r3, #2
+ 80235ea:	d00b      	beq.n	8023604 <decode_basic_field+0x1b8>
+                PB_RETURN_ERROR(stream, "wrong wire type");
+ 80235ec:	68fb      	ldr	r3, [r7, #12]
+ 80235ee:	68db      	ldr	r3, [r3, #12]
+ 80235f0:	2b00      	cmp	r3, #0
+ 80235f2:	d002      	beq.n	80235fa <decode_basic_field+0x1ae>
+ 80235f4:	68fb      	ldr	r3, [r7, #12]
+ 80235f6:	68db      	ldr	r3, [r3, #12]
+ 80235f8:	e000      	b.n	80235fc <decode_basic_field+0x1b0>
+ 80235fa:	4b0d      	ldr	r3, [pc, #52]	@ (8023630 <decode_basic_field+0x1e4>)
+ 80235fc:	68fa      	ldr	r2, [r7, #12]
+ 80235fe:	60d3      	str	r3, [r2, #12]
+ 8023600:	2300      	movs	r3, #0
+ 8023602:	e010      	b.n	8023626 <decode_basic_field+0x1da>
+
+            return pb_dec_fixed_length_bytes(stream, field);
+ 8023604:	6879      	ldr	r1, [r7, #4]
+ 8023606:	68f8      	ldr	r0, [r7, #12]
+ 8023608:	f001 f90c 	bl	8024824 <pb_dec_fixed_length_bytes>
+ 802360c:	4603      	mov	r3, r0
+ 802360e:	e00a      	b.n	8023626 <decode_basic_field+0x1da>
+
+        default:
+            PB_RETURN_ERROR(stream, "invalid field type");
+ 8023610:	68fb      	ldr	r3, [r7, #12]
+ 8023612:	68db      	ldr	r3, [r3, #12]
+ 8023614:	2b00      	cmp	r3, #0
+ 8023616:	d002      	beq.n	802361e <decode_basic_field+0x1d2>
+ 8023618:	68fb      	ldr	r3, [r7, #12]
+ 802361a:	68db      	ldr	r3, [r3, #12]
+ 802361c:	e000      	b.n	8023620 <decode_basic_field+0x1d4>
+ 802361e:	4b05      	ldr	r3, [pc, #20]	@ (8023634 <decode_basic_field+0x1e8>)
+ 8023620:	68fa      	ldr	r2, [r7, #12]
+ 8023622:	60d3      	str	r3, [r2, #12]
+ 8023624:	2300      	movs	r3, #0
+    }
+}
+ 8023626:	4618      	mov	r0, r3
+ 8023628:	3710      	adds	r7, #16
+ 802362a:	46bd      	mov	sp, r7
+ 802362c:	bd80      	pop	{r7, pc}
+ 802362e:	bf00      	nop
+ 8023630:	08041068 	.word	0x08041068
+ 8023634:	08041078 	.word	0x08041078
+
+08023638 <decode_static_field>:
+
+static bool checkreturn decode_static_field(pb_istream_t *stream, pb_wire_type_t wire_type, pb_field_iter_t *field)
+{
+ 8023638:	b580      	push	{r7, lr}
+ 802363a:	b096      	sub	sp, #88	@ 0x58
+ 802363c:	af00      	add	r7, sp, #0
+ 802363e:	60f8      	str	r0, [r7, #12]
+ 8023640:	460b      	mov	r3, r1
+ 8023642:	607a      	str	r2, [r7, #4]
+ 8023644:	72fb      	strb	r3, [r7, #11]
+    switch (PB_HTYPE(field->type))
+ 8023646:	687b      	ldr	r3, [r7, #4]
+ 8023648:	7d9b      	ldrb	r3, [r3, #22]
+ 802364a:	f003 0330 	and.w	r3, r3, #48	@ 0x30
+ 802364e:	2b30      	cmp	r3, #48	@ 0x30
+ 8023650:	f000 80c2 	beq.w	80237d8 <decode_static_field+0x1a0>
+ 8023654:	2b30      	cmp	r3, #48	@ 0x30
+ 8023656:	f200 811a 	bhi.w	802388e <decode_static_field+0x256>
+ 802365a:	2b20      	cmp	r3, #32
+ 802365c:	d01f      	beq.n	802369e <decode_static_field+0x66>
+ 802365e:	2b20      	cmp	r3, #32
+ 8023660:	f200 8115 	bhi.w	802388e <decode_static_field+0x256>
+ 8023664:	2b00      	cmp	r3, #0
+ 8023666:	d002      	beq.n	802366e <decode_static_field+0x36>
+ 8023668:	2b10      	cmp	r3, #16
+ 802366a:	d008      	beq.n	802367e <decode_static_field+0x46>
+ 802366c:	e10f      	b.n	802388e <decode_static_field+0x256>
+    {
+        case PB_HTYPE_REQUIRED:
+            return decode_basic_field(stream, wire_type, field);
+ 802366e:	7afb      	ldrb	r3, [r7, #11]
+ 8023670:	687a      	ldr	r2, [r7, #4]
+ 8023672:	4619      	mov	r1, r3
+ 8023674:	68f8      	ldr	r0, [r7, #12]
+ 8023676:	f7ff fee9 	bl	802344c <decode_basic_field>
+ 802367a:	4603      	mov	r3, r0
+ 802367c:	e112      	b.n	80238a4 <decode_static_field+0x26c>
+            
+        case PB_HTYPE_OPTIONAL:
+            if (field->pSize != NULL)
+ 802367e:	687b      	ldr	r3, [r7, #4]
+ 8023680:	6a1b      	ldr	r3, [r3, #32]
+ 8023682:	2b00      	cmp	r3, #0
+ 8023684:	d003      	beq.n	802368e <decode_static_field+0x56>
+                *(bool*)field->pSize = true;
+ 8023686:	687b      	ldr	r3, [r7, #4]
+ 8023688:	6a1b      	ldr	r3, [r3, #32]
+ 802368a:	2201      	movs	r2, #1
+ 802368c:	701a      	strb	r2, [r3, #0]
+            return decode_basic_field(stream, wire_type, field);
+ 802368e:	7afb      	ldrb	r3, [r7, #11]
+ 8023690:	687a      	ldr	r2, [r7, #4]
+ 8023692:	4619      	mov	r1, r3
+ 8023694:	68f8      	ldr	r0, [r7, #12]
+ 8023696:	f7ff fed9 	bl	802344c <decode_basic_field>
+ 802369a:	4603      	mov	r3, r0
+ 802369c:	e102      	b.n	80238a4 <decode_static_field+0x26c>
+    
+        case PB_HTYPE_REPEATED:
+            if (wire_type == PB_WT_STRING
+ 802369e:	7afb      	ldrb	r3, [r7, #11]
+ 80236a0:	2b02      	cmp	r3, #2
+ 80236a2:	d16c      	bne.n	802377e <decode_static_field+0x146>
+                && PB_LTYPE(field->type) <= PB_LTYPE_LAST_PACKABLE)
+ 80236a4:	687b      	ldr	r3, [r7, #4]
+ 80236a6:	7d9b      	ldrb	r3, [r3, #22]
+ 80236a8:	f003 030f 	and.w	r3, r3, #15
+ 80236ac:	2b05      	cmp	r3, #5
+ 80236ae:	d866      	bhi.n	802377e <decode_static_field+0x146>
+            {
+                /* Packed array */
+                bool status = true;
+ 80236b0:	2301      	movs	r3, #1
+ 80236b2:	f887 3057 	strb.w	r3, [r7, #87]	@ 0x57
+                pb_istream_t substream;
+                pb_size_t *size = (pb_size_t*)field->pSize;
+ 80236b6:	687b      	ldr	r3, [r7, #4]
+ 80236b8:	6a1b      	ldr	r3, [r3, #32]
+ 80236ba:	653b      	str	r3, [r7, #80]	@ 0x50
+                field->pData = (char*)field->pField + field->data_size * (*size);
+ 80236bc:	687b      	ldr	r3, [r7, #4]
+ 80236be:	699b      	ldr	r3, [r3, #24]
+ 80236c0:	687a      	ldr	r2, [r7, #4]
+ 80236c2:	8a52      	ldrh	r2, [r2, #18]
+ 80236c4:	4611      	mov	r1, r2
+ 80236c6:	6d3a      	ldr	r2, [r7, #80]	@ 0x50
+ 80236c8:	8812      	ldrh	r2, [r2, #0]
+ 80236ca:	fb01 f202 	mul.w	r2, r1, r2
+ 80236ce:	441a      	add	r2, r3
+ 80236d0:	687b      	ldr	r3, [r7, #4]
+ 80236d2:	61da      	str	r2, [r3, #28]
+
+                if (!pb_make_string_substream(stream, &substream))
+ 80236d4:	f107 033c 	add.w	r3, r7, #60	@ 0x3c
+ 80236d8:	4619      	mov	r1, r3
+ 80236da:	68f8      	ldr	r0, [r7, #12]
+ 80236dc:	f7ff fe56 	bl	802338c <pb_make_string_substream>
+ 80236e0:	4603      	mov	r3, r0
+ 80236e2:	f083 0301 	eor.w	r3, r3, #1
+ 80236e6:	b2db      	uxtb	r3, r3
+ 80236e8:	2b00      	cmp	r3, #0
+ 80236ea:	d01f      	beq.n	802372c <decode_static_field+0xf4>
+                    return false;
+ 80236ec:	2300      	movs	r3, #0
+ 80236ee:	e0d9      	b.n	80238a4 <decode_static_field+0x26c>
+
+                while (substream.bytes_left > 0 && *size < field->array_size)
+                {
+                    if (!decode_basic_field(&substream, PB_WT_PACKED, field))
+ 80236f0:	f107 033c 	add.w	r3, r7, #60	@ 0x3c
+ 80236f4:	687a      	ldr	r2, [r7, #4]
+ 80236f6:	21ff      	movs	r1, #255	@ 0xff
+ 80236f8:	4618      	mov	r0, r3
+ 80236fa:	f7ff fea7 	bl	802344c <decode_basic_field>
+ 80236fe:	4603      	mov	r3, r0
+ 8023700:	f083 0301 	eor.w	r3, r3, #1
+ 8023704:	b2db      	uxtb	r3, r3
+ 8023706:	2b00      	cmp	r3, #0
+ 8023708:	d003      	beq.n	8023712 <decode_static_field+0xda>
+                    {
+                        status = false;
+ 802370a:	2300      	movs	r3, #0
+ 802370c:	f887 3057 	strb.w	r3, [r7, #87]	@ 0x57
+                        break;
+ 8023710:	e015      	b.n	802373e <decode_static_field+0x106>
+                    }
+                    (*size)++;
+ 8023712:	6d3b      	ldr	r3, [r7, #80]	@ 0x50
+ 8023714:	881b      	ldrh	r3, [r3, #0]
+ 8023716:	3301      	adds	r3, #1
+ 8023718:	b29a      	uxth	r2, r3
+ 802371a:	6d3b      	ldr	r3, [r7, #80]	@ 0x50
+ 802371c:	801a      	strh	r2, [r3, #0]
+                    field->pData = (char*)field->pData + field->data_size;
+ 802371e:	687b      	ldr	r3, [r7, #4]
+ 8023720:	69db      	ldr	r3, [r3, #28]
+ 8023722:	687a      	ldr	r2, [r7, #4]
+ 8023724:	8a52      	ldrh	r2, [r2, #18]
+ 8023726:	441a      	add	r2, r3
+ 8023728:	687b      	ldr	r3, [r7, #4]
+ 802372a:	61da      	str	r2, [r3, #28]
+                while (substream.bytes_left > 0 && *size < field->array_size)
+ 802372c:	6c7b      	ldr	r3, [r7, #68]	@ 0x44
+ 802372e:	2b00      	cmp	r3, #0
+ 8023730:	d005      	beq.n	802373e <decode_static_field+0x106>
+ 8023732:	6d3b      	ldr	r3, [r7, #80]	@ 0x50
+ 8023734:	881a      	ldrh	r2, [r3, #0]
+ 8023736:	687b      	ldr	r3, [r7, #4]
+ 8023738:	8a9b      	ldrh	r3, [r3, #20]
+ 802373a:	429a      	cmp	r2, r3
+ 802373c:	d3d8      	bcc.n	80236f0 <decode_static_field+0xb8>
+                }
+
+                if (substream.bytes_left != 0)
+ 802373e:	6c7b      	ldr	r3, [r7, #68]	@ 0x44
+ 8023740:	2b00      	cmp	r3, #0
+ 8023742:	d00b      	beq.n	802375c <decode_static_field+0x124>
+                    PB_RETURN_ERROR(stream, "array overflow");
+ 8023744:	68fb      	ldr	r3, [r7, #12]
+ 8023746:	68db      	ldr	r3, [r3, #12]
+ 8023748:	2b00      	cmp	r3, #0
+ 802374a:	d002      	beq.n	8023752 <decode_static_field+0x11a>
+ 802374c:	68fb      	ldr	r3, [r7, #12]
+ 802374e:	68db      	ldr	r3, [r3, #12]
+ 8023750:	e000      	b.n	8023754 <decode_static_field+0x11c>
+ 8023752:	4b56      	ldr	r3, [pc, #344]	@ (80238ac <decode_static_field+0x274>)
+ 8023754:	68fa      	ldr	r2, [r7, #12]
+ 8023756:	60d3      	str	r3, [r2, #12]
+ 8023758:	2300      	movs	r3, #0
+ 802375a:	e0a3      	b.n	80238a4 <decode_static_field+0x26c>
+                if (!pb_close_string_substream(stream, &substream))
+ 802375c:	f107 033c 	add.w	r3, r7, #60	@ 0x3c
+ 8023760:	4619      	mov	r1, r3
+ 8023762:	68f8      	ldr	r0, [r7, #12]
+ 8023764:	f7ff fe4c 	bl	8023400 <pb_close_string_substream>
+ 8023768:	4603      	mov	r3, r0
+ 802376a:	f083 0301 	eor.w	r3, r3, #1
+ 802376e:	b2db      	uxtb	r3, r3
+ 8023770:	2b00      	cmp	r3, #0
+ 8023772:	d001      	beq.n	8023778 <decode_static_field+0x140>
+                    return false;
+ 8023774:	2300      	movs	r3, #0
+ 8023776:	e095      	b.n	80238a4 <decode_static_field+0x26c>
+
+                return status;
+ 8023778:	f897 3057 	ldrb.w	r3, [r7, #87]	@ 0x57
+ 802377c:	e092      	b.n	80238a4 <decode_static_field+0x26c>
+            }
+            else
+            {
+                /* Repeated field */
+                pb_size_t *size = (pb_size_t*)field->pSize;
+ 802377e:	687b      	ldr	r3, [r7, #4]
+ 8023780:	6a1b      	ldr	r3, [r3, #32]
+ 8023782:	64fb      	str	r3, [r7, #76]	@ 0x4c
+                field->pData = (char*)field->pField + field->data_size * (*size);
+ 8023784:	687b      	ldr	r3, [r7, #4]
+ 8023786:	699b      	ldr	r3, [r3, #24]
+ 8023788:	687a      	ldr	r2, [r7, #4]
+ 802378a:	8a52      	ldrh	r2, [r2, #18]
+ 802378c:	4611      	mov	r1, r2
+ 802378e:	6cfa      	ldr	r2, [r7, #76]	@ 0x4c
+ 8023790:	8812      	ldrh	r2, [r2, #0]
+ 8023792:	fb01 f202 	mul.w	r2, r1, r2
+ 8023796:	441a      	add	r2, r3
+ 8023798:	687b      	ldr	r3, [r7, #4]
+ 802379a:	61da      	str	r2, [r3, #28]
+
+                if ((*size)++ >= field->array_size)
+ 802379c:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
+ 802379e:	881b      	ldrh	r3, [r3, #0]
+ 80237a0:	1c5a      	adds	r2, r3, #1
+ 80237a2:	b291      	uxth	r1, r2
+ 80237a4:	6cfa      	ldr	r2, [r7, #76]	@ 0x4c
+ 80237a6:	8011      	strh	r1, [r2, #0]
+ 80237a8:	687a      	ldr	r2, [r7, #4]
+ 80237aa:	8a92      	ldrh	r2, [r2, #20]
+ 80237ac:	4293      	cmp	r3, r2
+ 80237ae:	d30b      	bcc.n	80237c8 <decode_static_field+0x190>
+                    PB_RETURN_ERROR(stream, "array overflow");
+ 80237b0:	68fb      	ldr	r3, [r7, #12]
+ 80237b2:	68db      	ldr	r3, [r3, #12]
+ 80237b4:	2b00      	cmp	r3, #0
+ 80237b6:	d002      	beq.n	80237be <decode_static_field+0x186>
+ 80237b8:	68fb      	ldr	r3, [r7, #12]
+ 80237ba:	68db      	ldr	r3, [r3, #12]
+ 80237bc:	e000      	b.n	80237c0 <decode_static_field+0x188>
+ 80237be:	4b3b      	ldr	r3, [pc, #236]	@ (80238ac <decode_static_field+0x274>)
+ 80237c0:	68fa      	ldr	r2, [r7, #12]
+ 80237c2:	60d3      	str	r3, [r2, #12]
+ 80237c4:	2300      	movs	r3, #0
+ 80237c6:	e06d      	b.n	80238a4 <decode_static_field+0x26c>
+
+                return decode_basic_field(stream, wire_type, field);
+ 80237c8:	7afb      	ldrb	r3, [r7, #11]
+ 80237ca:	687a      	ldr	r2, [r7, #4]
+ 80237cc:	4619      	mov	r1, r3
+ 80237ce:	68f8      	ldr	r0, [r7, #12]
+ 80237d0:	f7ff fe3c 	bl	802344c <decode_basic_field>
+ 80237d4:	4603      	mov	r3, r0
+ 80237d6:	e065      	b.n	80238a4 <decode_static_field+0x26c>
+            }
+
+        case PB_HTYPE_ONEOF:
+            if (PB_LTYPE_IS_SUBMSG(field->type) &&
+ 80237d8:	687b      	ldr	r3, [r7, #4]
+ 80237da:	7d9b      	ldrb	r3, [r3, #22]
+ 80237dc:	f003 030f 	and.w	r3, r3, #15
+ 80237e0:	2b08      	cmp	r3, #8
+ 80237e2:	d005      	beq.n	80237f0 <decode_static_field+0x1b8>
+ 80237e4:	687b      	ldr	r3, [r7, #4]
+ 80237e6:	7d9b      	ldrb	r3, [r3, #22]
+ 80237e8:	f003 030f 	and.w	r3, r3, #15
+ 80237ec:	2b09      	cmp	r3, #9
+ 80237ee:	d141      	bne.n	8023874 <decode_static_field+0x23c>
+                *(pb_size_t*)field->pSize != field->tag)
+ 80237f0:	687b      	ldr	r3, [r7, #4]
+ 80237f2:	6a1b      	ldr	r3, [r3, #32]
+ 80237f4:	881a      	ldrh	r2, [r3, #0]
+ 80237f6:	687b      	ldr	r3, [r7, #4]
+ 80237f8:	8a1b      	ldrh	r3, [r3, #16]
+            if (PB_LTYPE_IS_SUBMSG(field->type) &&
+ 80237fa:	429a      	cmp	r2, r3
+ 80237fc:	d03a      	beq.n	8023874 <decode_static_field+0x23c>
+                 * from some other union field.
+                 * If callbacks are needed inside oneof field, use .proto
+                 * option submsg_callback to have a separate callback function
+                 * that can set the fields before submessage is decoded.
+                 * pb_dec_submessage() will set any default values. */
+                memset(field->pData, 0, (size_t)field->data_size);
+ 80237fe:	687b      	ldr	r3, [r7, #4]
+ 8023800:	69d8      	ldr	r0, [r3, #28]
+ 8023802:	687b      	ldr	r3, [r7, #4]
+ 8023804:	8a5b      	ldrh	r3, [r3, #18]
+ 8023806:	461a      	mov	r2, r3
+ 8023808:	2100      	movs	r1, #0
+ 802380a:	f01c fd6d 	bl	80402e8 <memset>
+
+                /* Set default values for the submessage fields. */
+                if (field->submsg_desc->default_value != NULL ||
+ 802380e:	687b      	ldr	r3, [r7, #4]
+ 8023810:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 8023812:	689b      	ldr	r3, [r3, #8]
+ 8023814:	2b00      	cmp	r3, #0
+ 8023816:	d10a      	bne.n	802382e <decode_static_field+0x1f6>
+                    field->submsg_desc->field_callback != NULL ||
+ 8023818:	687b      	ldr	r3, [r7, #4]
+ 802381a:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 802381c:	68db      	ldr	r3, [r3, #12]
+                if (field->submsg_desc->default_value != NULL ||
+ 802381e:	2b00      	cmp	r3, #0
+ 8023820:	d105      	bne.n	802382e <decode_static_field+0x1f6>
+                    field->submsg_desc->submsg_info[0] != NULL)
+ 8023822:	687b      	ldr	r3, [r7, #4]
+ 8023824:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 8023826:	685b      	ldr	r3, [r3, #4]
+ 8023828:	681b      	ldr	r3, [r3, #0]
+                    field->submsg_desc->field_callback != NULL ||
+ 802382a:	2b00      	cmp	r3, #0
+ 802382c:	d022      	beq.n	8023874 <decode_static_field+0x23c>
+                {
+                    pb_field_iter_t submsg_iter;
+                    if (pb_field_iter_begin(&submsg_iter, field->submsg_desc, field->pData))
+ 802382e:	687b      	ldr	r3, [r7, #4]
+ 8023830:	6a59      	ldr	r1, [r3, #36]	@ 0x24
+ 8023832:	687b      	ldr	r3, [r7, #4]
+ 8023834:	69da      	ldr	r2, [r3, #28]
+ 8023836:	f107 0314 	add.w	r3, r7, #20
+ 802383a:	4618      	mov	r0, r3
+ 802383c:	f7ff f934 	bl	8022aa8 <pb_field_iter_begin>
+ 8023840:	4603      	mov	r3, r0
+ 8023842:	2b00      	cmp	r3, #0
+ 8023844:	d016      	beq.n	8023874 <decode_static_field+0x23c>
+                    {
+                        if (!pb_message_set_to_defaults(&submsg_iter))
+ 8023846:	f107 0314 	add.w	r3, r7, #20
+ 802384a:	4618      	mov	r0, r3
+ 802384c:	f000 fa4d 	bl	8023cea <pb_message_set_to_defaults>
+ 8023850:	4603      	mov	r3, r0
+ 8023852:	f083 0301 	eor.w	r3, r3, #1
+ 8023856:	b2db      	uxtb	r3, r3
+ 8023858:	2b00      	cmp	r3, #0
+ 802385a:	d00b      	beq.n	8023874 <decode_static_field+0x23c>
+                            PB_RETURN_ERROR(stream, "failed to set defaults");
+ 802385c:	68fb      	ldr	r3, [r7, #12]
+ 802385e:	68db      	ldr	r3, [r3, #12]
+ 8023860:	2b00      	cmp	r3, #0
+ 8023862:	d002      	beq.n	802386a <decode_static_field+0x232>
+ 8023864:	68fb      	ldr	r3, [r7, #12]
+ 8023866:	68db      	ldr	r3, [r3, #12]
+ 8023868:	e000      	b.n	802386c <decode_static_field+0x234>
+ 802386a:	4b11      	ldr	r3, [pc, #68]	@ (80238b0 <decode_static_field+0x278>)
+ 802386c:	68fa      	ldr	r2, [r7, #12]
+ 802386e:	60d3      	str	r3, [r2, #12]
+ 8023870:	2300      	movs	r3, #0
+ 8023872:	e017      	b.n	80238a4 <decode_static_field+0x26c>
+                    }
+                }
+            }
+            *(pb_size_t*)field->pSize = field->tag;
+ 8023874:	687b      	ldr	r3, [r7, #4]
+ 8023876:	6a1b      	ldr	r3, [r3, #32]
+ 8023878:	687a      	ldr	r2, [r7, #4]
+ 802387a:	8a12      	ldrh	r2, [r2, #16]
+ 802387c:	801a      	strh	r2, [r3, #0]
+
+            return decode_basic_field(stream, wire_type, field);
+ 802387e:	7afb      	ldrb	r3, [r7, #11]
+ 8023880:	687a      	ldr	r2, [r7, #4]
+ 8023882:	4619      	mov	r1, r3
+ 8023884:	68f8      	ldr	r0, [r7, #12]
+ 8023886:	f7ff fde1 	bl	802344c <decode_basic_field>
+ 802388a:	4603      	mov	r3, r0
+ 802388c:	e00a      	b.n	80238a4 <decode_static_field+0x26c>
+
+        default:
+            PB_RETURN_ERROR(stream, "invalid field type");
+ 802388e:	68fb      	ldr	r3, [r7, #12]
+ 8023890:	68db      	ldr	r3, [r3, #12]
+ 8023892:	2b00      	cmp	r3, #0
+ 8023894:	d002      	beq.n	802389c <decode_static_field+0x264>
+ 8023896:	68fb      	ldr	r3, [r7, #12]
+ 8023898:	68db      	ldr	r3, [r3, #12]
+ 802389a:	e000      	b.n	802389e <decode_static_field+0x266>
+ 802389c:	4b05      	ldr	r3, [pc, #20]	@ (80238b4 <decode_static_field+0x27c>)
+ 802389e:	68fa      	ldr	r2, [r7, #12]
+ 80238a0:	60d3      	str	r3, [r2, #12]
+ 80238a2:	2300      	movs	r3, #0
+    }
+}
+ 80238a4:	4618      	mov	r0, r3
+ 80238a6:	3758      	adds	r7, #88	@ 0x58
+ 80238a8:	46bd      	mov	sp, r7
+ 80238aa:	bd80      	pop	{r7, pc}
+ 80238ac:	0804108c 	.word	0x0804108c
+ 80238b0:	0804109c 	.word	0x0804109c
+ 80238b4:	08041078 	.word	0x08041078
+
+080238b8 <decode_pointer_field>:
+    }
+}
+#endif
+
+static bool checkreturn decode_pointer_field(pb_istream_t *stream, pb_wire_type_t wire_type, pb_field_iter_t *field)
+{
+ 80238b8:	b480      	push	{r7}
+ 80238ba:	b085      	sub	sp, #20
+ 80238bc:	af00      	add	r7, sp, #0
+ 80238be:	60f8      	str	r0, [r7, #12]
+ 80238c0:	460b      	mov	r3, r1
+ 80238c2:	607a      	str	r2, [r7, #4]
+ 80238c4:	72fb      	strb	r3, [r7, #11]
+#ifndef PB_ENABLE_MALLOC
+    PB_UNUSED(wire_type);
+    PB_UNUSED(field);
+    PB_RETURN_ERROR(stream, "no malloc support");
+ 80238c6:	68fb      	ldr	r3, [r7, #12]
+ 80238c8:	68db      	ldr	r3, [r3, #12]
+ 80238ca:	2b00      	cmp	r3, #0
+ 80238cc:	d002      	beq.n	80238d4 <decode_pointer_field+0x1c>
+ 80238ce:	68fb      	ldr	r3, [r7, #12]
+ 80238d0:	68db      	ldr	r3, [r3, #12]
+ 80238d2:	e000      	b.n	80238d6 <decode_pointer_field+0x1e>
+ 80238d4:	4b04      	ldr	r3, [pc, #16]	@ (80238e8 <decode_pointer_field+0x30>)
+ 80238d6:	68fa      	ldr	r2, [r7, #12]
+ 80238d8:	60d3      	str	r3, [r2, #12]
+ 80238da:	2300      	movs	r3, #0
+
+        default:
+            PB_RETURN_ERROR(stream, "invalid field type");
+    }
+#endif
+}
+ 80238dc:	4618      	mov	r0, r3
+ 80238de:	3714      	adds	r7, #20
+ 80238e0:	46bd      	mov	sp, r7
+ 80238e2:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80238e6:	4770      	bx	lr
+ 80238e8:	080410b4 	.word	0x080410b4
+
+080238ec <decode_callback_field>:
+
+static bool checkreturn decode_callback_field(pb_istream_t *stream, pb_wire_type_t wire_type, pb_field_iter_t *field)
+{
+ 80238ec:	b590      	push	{r4, r7, lr}
+ 80238ee:	b097      	sub	sp, #92	@ 0x5c
+ 80238f0:	af00      	add	r7, sp, #0
+ 80238f2:	61f8      	str	r0, [r7, #28]
+ 80238f4:	460b      	mov	r3, r1
+ 80238f6:	617a      	str	r2, [r7, #20]
+ 80238f8:	76fb      	strb	r3, [r7, #27]
+    if (!field->descriptor->field_callback)
+ 80238fa:	697b      	ldr	r3, [r7, #20]
+ 80238fc:	681b      	ldr	r3, [r3, #0]
+ 80238fe:	68db      	ldr	r3, [r3, #12]
+ 8023900:	2b00      	cmp	r3, #0
+ 8023902:	d106      	bne.n	8023912 <decode_callback_field+0x26>
+        return pb_skip_field(stream, wire_type);
+ 8023904:	7efb      	ldrb	r3, [r7, #27]
+ 8023906:	4619      	mov	r1, r3
+ 8023908:	69f8      	ldr	r0, [r7, #28]
+ 802390a:	f7ff fc91 	bl	8023230 <pb_skip_field>
+ 802390e:	4603      	mov	r3, r0
+ 8023910:	e070      	b.n	80239f4 <decode_callback_field+0x108>
+
+    if (wire_type == PB_WT_STRING)
+ 8023912:	7efb      	ldrb	r3, [r7, #27]
+ 8023914:	2b02      	cmp	r3, #2
+ 8023916:	d145      	bne.n	80239a4 <decode_callback_field+0xb8>
+    {
+        pb_istream_t substream;
+        size_t prev_bytes_left;
+        
+        if (!pb_make_string_substream(stream, &substream))
+ 8023918:	f107 0344 	add.w	r3, r7, #68	@ 0x44
+ 802391c:	4619      	mov	r1, r3
+ 802391e:	69f8      	ldr	r0, [r7, #28]
+ 8023920:	f7ff fd34 	bl	802338c <pb_make_string_substream>
+ 8023924:	4603      	mov	r3, r0
+ 8023926:	f083 0301 	eor.w	r3, r3, #1
+ 802392a:	b2db      	uxtb	r3, r3
+ 802392c:	2b00      	cmp	r3, #0
+ 802392e:	d001      	beq.n	8023934 <decode_callback_field+0x48>
+            return false;
+ 8023930:	2300      	movs	r3, #0
+ 8023932:	e05f      	b.n	80239f4 <decode_callback_field+0x108>
+        
+        do
+        {
+            prev_bytes_left = substream.bytes_left;
+ 8023934:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
+ 8023936:	657b      	str	r3, [r7, #84]	@ 0x54
+            if (!field->descriptor->field_callback(&substream, NULL, field))
+ 8023938:	697b      	ldr	r3, [r7, #20]
+ 802393a:	681b      	ldr	r3, [r3, #0]
+ 802393c:	68db      	ldr	r3, [r3, #12]
+ 802393e:	f107 0044 	add.w	r0, r7, #68	@ 0x44
+ 8023942:	697a      	ldr	r2, [r7, #20]
+ 8023944:	2100      	movs	r1, #0
+ 8023946:	4798      	blx	r3
+ 8023948:	4603      	mov	r3, r0
+ 802394a:	f083 0301 	eor.w	r3, r3, #1
+ 802394e:	b2db      	uxtb	r3, r3
+ 8023950:	2b00      	cmp	r3, #0
+ 8023952:	d010      	beq.n	8023976 <decode_callback_field+0x8a>
+            {
+                PB_SET_ERROR(stream, substream.errmsg ? substream.errmsg : "callback failed");
+ 8023954:	69fb      	ldr	r3, [r7, #28]
+ 8023956:	68db      	ldr	r3, [r3, #12]
+ 8023958:	2b00      	cmp	r3, #0
+ 802395a:	d002      	beq.n	8023962 <decode_callback_field+0x76>
+ 802395c:	69fb      	ldr	r3, [r7, #28]
+ 802395e:	68db      	ldr	r3, [r3, #12]
+ 8023960:	e005      	b.n	802396e <decode_callback_field+0x82>
+ 8023962:	6d3b      	ldr	r3, [r7, #80]	@ 0x50
+ 8023964:	2b00      	cmp	r3, #0
+ 8023966:	d001      	beq.n	802396c <decode_callback_field+0x80>
+ 8023968:	6d3b      	ldr	r3, [r7, #80]	@ 0x50
+ 802396a:	e000      	b.n	802396e <decode_callback_field+0x82>
+ 802396c:	4b23      	ldr	r3, [pc, #140]	@ (80239fc <decode_callback_field+0x110>)
+ 802396e:	69fa      	ldr	r2, [r7, #28]
+ 8023970:	60d3      	str	r3, [r2, #12]
+                return false;
+ 8023972:	2300      	movs	r3, #0
+ 8023974:	e03e      	b.n	80239f4 <decode_callback_field+0x108>
+            }
+        } while (substream.bytes_left > 0 && substream.bytes_left < prev_bytes_left);
+ 8023976:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
+ 8023978:	2b00      	cmp	r3, #0
+ 802397a:	d003      	beq.n	8023984 <decode_callback_field+0x98>
+ 802397c:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
+ 802397e:	6d7a      	ldr	r2, [r7, #84]	@ 0x54
+ 8023980:	429a      	cmp	r2, r3
+ 8023982:	d8d7      	bhi.n	8023934 <decode_callback_field+0x48>
+        
+        if (!pb_close_string_substream(stream, &substream))
+ 8023984:	f107 0344 	add.w	r3, r7, #68	@ 0x44
+ 8023988:	4619      	mov	r1, r3
+ 802398a:	69f8      	ldr	r0, [r7, #28]
+ 802398c:	f7ff fd38 	bl	8023400 <pb_close_string_substream>
+ 8023990:	4603      	mov	r3, r0
+ 8023992:	f083 0301 	eor.w	r3, r3, #1
+ 8023996:	b2db      	uxtb	r3, r3
+ 8023998:	2b00      	cmp	r3, #0
+ 802399a:	d001      	beq.n	80239a0 <decode_callback_field+0xb4>
+            return false;
+ 802399c:	2300      	movs	r3, #0
+ 802399e:	e029      	b.n	80239f4 <decode_callback_field+0x108>
+
+        return true;
+ 80239a0:	2301      	movs	r3, #1
+ 80239a2:	e027      	b.n	80239f4 <decode_callback_field+0x108>
+         * This is required so that we can limit the stream length,
+         * which in turn allows to use same callback for packed and
+         * not-packed fields. */
+        pb_istream_t substream;
+        pb_byte_t buffer[10];
+        size_t size = sizeof(buffer);
+ 80239a4:	230a      	movs	r3, #10
+ 80239a6:	627b      	str	r3, [r7, #36]	@ 0x24
+        
+        if (!read_raw_value(stream, wire_type, buffer, &size))
+ 80239a8:	f107 0324 	add.w	r3, r7, #36	@ 0x24
+ 80239ac:	f107 0228 	add.w	r2, r7, #40	@ 0x28
+ 80239b0:	7ef9      	ldrb	r1, [r7, #27]
+ 80239b2:	69f8      	ldr	r0, [r7, #28]
+ 80239b4:	f7ff fc7e 	bl	80232b4 <read_raw_value>
+ 80239b8:	4603      	mov	r3, r0
+ 80239ba:	f083 0301 	eor.w	r3, r3, #1
+ 80239be:	b2db      	uxtb	r3, r3
+ 80239c0:	2b00      	cmp	r3, #0
+ 80239c2:	d001      	beq.n	80239c8 <decode_callback_field+0xdc>
+            return false;
+ 80239c4:	2300      	movs	r3, #0
+ 80239c6:	e015      	b.n	80239f4 <decode_callback_field+0x108>
+        substream = pb_istream_from_buffer(buffer, size);
+ 80239c8:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
+ 80239ca:	463b      	mov	r3, r7
+ 80239cc:	f107 0128 	add.w	r1, r7, #40	@ 0x28
+ 80239d0:	4618      	mov	r0, r3
+ 80239d2:	f7ff fa87 	bl	8022ee4 <pb_istream_from_buffer>
+ 80239d6:	f107 0434 	add.w	r4, r7, #52	@ 0x34
+ 80239da:	463b      	mov	r3, r7
+ 80239dc:	cb0f      	ldmia	r3, {r0, r1, r2, r3}
+ 80239de:	e884 000f 	stmia.w	r4, {r0, r1, r2, r3}
+        
+        return field->descriptor->field_callback(&substream, NULL, field);
+ 80239e2:	697b      	ldr	r3, [r7, #20]
+ 80239e4:	681b      	ldr	r3, [r3, #0]
+ 80239e6:	68db      	ldr	r3, [r3, #12]
+ 80239e8:	f107 0034 	add.w	r0, r7, #52	@ 0x34
+ 80239ec:	697a      	ldr	r2, [r7, #20]
+ 80239ee:	2100      	movs	r1, #0
+ 80239f0:	4798      	blx	r3
+ 80239f2:	4603      	mov	r3, r0
+    }
+}
+ 80239f4:	4618      	mov	r0, r3
+ 80239f6:	375c      	adds	r7, #92	@ 0x5c
+ 80239f8:	46bd      	mov	sp, r7
+ 80239fa:	bd90      	pop	{r4, r7, pc}
+ 80239fc:	080410c8 	.word	0x080410c8
+
+08023a00 <decode_field>:
+
+static bool checkreturn decode_field(pb_istream_t *stream, pb_wire_type_t wire_type, pb_field_iter_t *field)
+{
+ 8023a00:	b580      	push	{r7, lr}
+ 8023a02:	b084      	sub	sp, #16
+ 8023a04:	af00      	add	r7, sp, #0
+ 8023a06:	60f8      	str	r0, [r7, #12]
+ 8023a08:	460b      	mov	r3, r1
+ 8023a0a:	607a      	str	r2, [r7, #4]
+ 8023a0c:	72fb      	strb	r3, [r7, #11]
+        if (!pb_release_union_field(stream, field))
+            return false;
+    }
+#endif
+
+    switch (PB_ATYPE(field->type))
+ 8023a0e:	687b      	ldr	r3, [r7, #4]
+ 8023a10:	7d9b      	ldrb	r3, [r3, #22]
+ 8023a12:	f003 03c0 	and.w	r3, r3, #192	@ 0xc0
+ 8023a16:	2b80      	cmp	r3, #128	@ 0x80
+ 8023a18:	d00e      	beq.n	8023a38 <decode_field+0x38>
+ 8023a1a:	2b80      	cmp	r3, #128	@ 0x80
+ 8023a1c:	d81c      	bhi.n	8023a58 <decode_field+0x58>
+ 8023a1e:	2b00      	cmp	r3, #0
+ 8023a20:	d002      	beq.n	8023a28 <decode_field+0x28>
+ 8023a22:	2b40      	cmp	r3, #64	@ 0x40
+ 8023a24:	d010      	beq.n	8023a48 <decode_field+0x48>
+ 8023a26:	e017      	b.n	8023a58 <decode_field+0x58>
+    {
+        case PB_ATYPE_STATIC:
+            return decode_static_field(stream, wire_type, field);
+ 8023a28:	7afb      	ldrb	r3, [r7, #11]
+ 8023a2a:	687a      	ldr	r2, [r7, #4]
+ 8023a2c:	4619      	mov	r1, r3
+ 8023a2e:	68f8      	ldr	r0, [r7, #12]
+ 8023a30:	f7ff fe02 	bl	8023638 <decode_static_field>
+ 8023a34:	4603      	mov	r3, r0
+ 8023a36:	e01a      	b.n	8023a6e <decode_field+0x6e>
+        
+        case PB_ATYPE_POINTER:
+            return decode_pointer_field(stream, wire_type, field);
+ 8023a38:	7afb      	ldrb	r3, [r7, #11]
+ 8023a3a:	687a      	ldr	r2, [r7, #4]
+ 8023a3c:	4619      	mov	r1, r3
+ 8023a3e:	68f8      	ldr	r0, [r7, #12]
+ 8023a40:	f7ff ff3a 	bl	80238b8 <decode_pointer_field>
+ 8023a44:	4603      	mov	r3, r0
+ 8023a46:	e012      	b.n	8023a6e <decode_field+0x6e>
+        
+        case PB_ATYPE_CALLBACK:
+            return decode_callback_field(stream, wire_type, field);
+ 8023a48:	7afb      	ldrb	r3, [r7, #11]
+ 8023a4a:	687a      	ldr	r2, [r7, #4]
+ 8023a4c:	4619      	mov	r1, r3
+ 8023a4e:	68f8      	ldr	r0, [r7, #12]
+ 8023a50:	f7ff ff4c 	bl	80238ec <decode_callback_field>
+ 8023a54:	4603      	mov	r3, r0
+ 8023a56:	e00a      	b.n	8023a6e <decode_field+0x6e>
+        
+        default:
+            PB_RETURN_ERROR(stream, "invalid field type");
+ 8023a58:	68fb      	ldr	r3, [r7, #12]
+ 8023a5a:	68db      	ldr	r3, [r3, #12]
+ 8023a5c:	2b00      	cmp	r3, #0
+ 8023a5e:	d002      	beq.n	8023a66 <decode_field+0x66>
+ 8023a60:	68fb      	ldr	r3, [r7, #12]
+ 8023a62:	68db      	ldr	r3, [r3, #12]
+ 8023a64:	e000      	b.n	8023a68 <decode_field+0x68>
+ 8023a66:	4b04      	ldr	r3, [pc, #16]	@ (8023a78 <decode_field+0x78>)
+ 8023a68:	68fa      	ldr	r2, [r7, #12]
+ 8023a6a:	60d3      	str	r3, [r2, #12]
+ 8023a6c:	2300      	movs	r3, #0
+    }
+}
+ 8023a6e:	4618      	mov	r0, r3
+ 8023a70:	3710      	adds	r7, #16
+ 8023a72:	46bd      	mov	sp, r7
+ 8023a74:	bd80      	pop	{r7, pc}
+ 8023a76:	bf00      	nop
+ 8023a78:	08041078 	.word	0x08041078
+
+08023a7c <default_extension_decoder>:
+/* Default handler for extension fields. Expects to have a pb_msgdesc_t
+ * pointer in the extension->type->arg field, pointing to a message with
+ * only one field in it.  */
+static bool checkreturn default_extension_decoder(pb_istream_t *stream,
+    pb_extension_t *extension, uint32_t tag, pb_wire_type_t wire_type)
+{
+ 8023a7c:	b580      	push	{r7, lr}
+ 8023a7e:	b08e      	sub	sp, #56	@ 0x38
+ 8023a80:	af00      	add	r7, sp, #0
+ 8023a82:	60f8      	str	r0, [r7, #12]
+ 8023a84:	60b9      	str	r1, [r7, #8]
+ 8023a86:	607a      	str	r2, [r7, #4]
+ 8023a88:	70fb      	strb	r3, [r7, #3]
+    pb_field_iter_t iter;
+
+    if (!pb_field_iter_begin_extension(&iter, extension))
+ 8023a8a:	f107 0310 	add.w	r3, r7, #16
+ 8023a8e:	68b9      	ldr	r1, [r7, #8]
+ 8023a90:	4618      	mov	r0, r3
+ 8023a92:	f7ff f822 	bl	8022ada <pb_field_iter_begin_extension>
+ 8023a96:	4603      	mov	r3, r0
+ 8023a98:	f083 0301 	eor.w	r3, r3, #1
+ 8023a9c:	b2db      	uxtb	r3, r3
+ 8023a9e:	2b00      	cmp	r3, #0
+ 8023aa0:	d00b      	beq.n	8023aba <default_extension_decoder+0x3e>
+        PB_RETURN_ERROR(stream, "invalid extension");
+ 8023aa2:	68fb      	ldr	r3, [r7, #12]
+ 8023aa4:	68db      	ldr	r3, [r3, #12]
+ 8023aa6:	2b00      	cmp	r3, #0
+ 8023aa8:	d002      	beq.n	8023ab0 <default_extension_decoder+0x34>
+ 8023aaa:	68fb      	ldr	r3, [r7, #12]
+ 8023aac:	68db      	ldr	r3, [r3, #12]
+ 8023aae:	e000      	b.n	8023ab2 <default_extension_decoder+0x36>
+ 8023ab0:	4b0e      	ldr	r3, [pc, #56]	@ (8023aec <default_extension_decoder+0x70>)
+ 8023ab2:	68fa      	ldr	r2, [r7, #12]
+ 8023ab4:	60d3      	str	r3, [r2, #12]
+ 8023ab6:	2300      	movs	r3, #0
+ 8023ab8:	e014      	b.n	8023ae4 <default_extension_decoder+0x68>
+
+    if (iter.tag != tag || !iter.message)
+ 8023aba:	8c3b      	ldrh	r3, [r7, #32]
+ 8023abc:	461a      	mov	r2, r3
+ 8023abe:	687b      	ldr	r3, [r7, #4]
+ 8023ac0:	4293      	cmp	r3, r2
+ 8023ac2:	d102      	bne.n	8023aca <default_extension_decoder+0x4e>
+ 8023ac4:	697b      	ldr	r3, [r7, #20]
+ 8023ac6:	2b00      	cmp	r3, #0
+ 8023ac8:	d101      	bne.n	8023ace <default_extension_decoder+0x52>
+        return true;
+ 8023aca:	2301      	movs	r3, #1
+ 8023acc:	e00a      	b.n	8023ae4 <default_extension_decoder+0x68>
+
+    extension->found = true;
+ 8023ace:	68bb      	ldr	r3, [r7, #8]
+ 8023ad0:	2201      	movs	r2, #1
+ 8023ad2:	731a      	strb	r2, [r3, #12]
+    return decode_field(stream, wire_type, &iter);
+ 8023ad4:	f107 0210 	add.w	r2, r7, #16
+ 8023ad8:	78fb      	ldrb	r3, [r7, #3]
+ 8023ada:	4619      	mov	r1, r3
+ 8023adc:	68f8      	ldr	r0, [r7, #12]
+ 8023ade:	f7ff ff8f 	bl	8023a00 <decode_field>
+ 8023ae2:	4603      	mov	r3, r0
+}
+ 8023ae4:	4618      	mov	r0, r3
+ 8023ae6:	3738      	adds	r7, #56	@ 0x38
+ 8023ae8:	46bd      	mov	sp, r7
+ 8023aea:	bd80      	pop	{r7, pc}
+ 8023aec:	080410d8 	.word	0x080410d8
+
+08023af0 <decode_extension>:
+
+/* Try to decode an unknown field as an extension field. Tries each extension
+ * decoder in turn, until one of them handles the field or loop ends. */
+static bool checkreturn decode_extension(pb_istream_t *stream,
+    uint32_t tag, pb_wire_type_t wire_type, pb_extension_t *extension)
+{
+ 8023af0:	b590      	push	{r4, r7, lr}
+ 8023af2:	b087      	sub	sp, #28
+ 8023af4:	af00      	add	r7, sp, #0
+ 8023af6:	60f8      	str	r0, [r7, #12]
+ 8023af8:	60b9      	str	r1, [r7, #8]
+ 8023afa:	603b      	str	r3, [r7, #0]
+ 8023afc:	4613      	mov	r3, r2
+ 8023afe:	71fb      	strb	r3, [r7, #7]
+    size_t pos = stream->bytes_left;
+ 8023b00:	68fb      	ldr	r3, [r7, #12]
+ 8023b02:	689b      	ldr	r3, [r3, #8]
+ 8023b04:	613b      	str	r3, [r7, #16]
+    
+    while (extension != NULL && pos == stream->bytes_left)
+ 8023b06:	e022      	b.n	8023b4e <decode_extension+0x5e>
+    {
+        bool status;
+        if (extension->type->decode)
+ 8023b08:	683b      	ldr	r3, [r7, #0]
+ 8023b0a:	681b      	ldr	r3, [r3, #0]
+ 8023b0c:	681b      	ldr	r3, [r3, #0]
+ 8023b0e:	2b00      	cmp	r3, #0
+ 8023b10:	d00a      	beq.n	8023b28 <decode_extension+0x38>
+            status = extension->type->decode(stream, extension, tag, wire_type);
+ 8023b12:	683b      	ldr	r3, [r7, #0]
+ 8023b14:	681b      	ldr	r3, [r3, #0]
+ 8023b16:	681c      	ldr	r4, [r3, #0]
+ 8023b18:	79fb      	ldrb	r3, [r7, #7]
+ 8023b1a:	68ba      	ldr	r2, [r7, #8]
+ 8023b1c:	6839      	ldr	r1, [r7, #0]
+ 8023b1e:	68f8      	ldr	r0, [r7, #12]
+ 8023b20:	47a0      	blx	r4
+ 8023b22:	4603      	mov	r3, r0
+ 8023b24:	75fb      	strb	r3, [r7, #23]
+ 8023b26:	e007      	b.n	8023b38 <decode_extension+0x48>
+        else
+            status = default_extension_decoder(stream, extension, tag, wire_type);
+ 8023b28:	79fb      	ldrb	r3, [r7, #7]
+ 8023b2a:	68ba      	ldr	r2, [r7, #8]
+ 8023b2c:	6839      	ldr	r1, [r7, #0]
+ 8023b2e:	68f8      	ldr	r0, [r7, #12]
+ 8023b30:	f7ff ffa4 	bl	8023a7c <default_extension_decoder>
+ 8023b34:	4603      	mov	r3, r0
+ 8023b36:	75fb      	strb	r3, [r7, #23]
+
+        if (!status)
+ 8023b38:	7dfb      	ldrb	r3, [r7, #23]
+ 8023b3a:	f083 0301 	eor.w	r3, r3, #1
+ 8023b3e:	b2db      	uxtb	r3, r3
+ 8023b40:	2b00      	cmp	r3, #0
+ 8023b42:	d001      	beq.n	8023b48 <decode_extension+0x58>
+            return false;
+ 8023b44:	2300      	movs	r3, #0
+ 8023b46:	e00b      	b.n	8023b60 <decode_extension+0x70>
+        
+        extension = extension->next;
+ 8023b48:	683b      	ldr	r3, [r7, #0]
+ 8023b4a:	689b      	ldr	r3, [r3, #8]
+ 8023b4c:	603b      	str	r3, [r7, #0]
+    while (extension != NULL && pos == stream->bytes_left)
+ 8023b4e:	683b      	ldr	r3, [r7, #0]
+ 8023b50:	2b00      	cmp	r3, #0
+ 8023b52:	d004      	beq.n	8023b5e <decode_extension+0x6e>
+ 8023b54:	68fb      	ldr	r3, [r7, #12]
+ 8023b56:	689b      	ldr	r3, [r3, #8]
+ 8023b58:	693a      	ldr	r2, [r7, #16]
+ 8023b5a:	429a      	cmp	r2, r3
+ 8023b5c:	d0d4      	beq.n	8023b08 <decode_extension+0x18>
+    }
+    
+    return true;
+ 8023b5e:	2301      	movs	r3, #1
+}
+ 8023b60:	4618      	mov	r0, r3
+ 8023b62:	371c      	adds	r7, #28
+ 8023b64:	46bd      	mov	sp, r7
+ 8023b66:	bd90      	pop	{r4, r7, pc}
+
+08023b68 <pb_field_set_to_default>:
+
+/* Initialize message fields to default values, recursively */
+static bool pb_field_set_to_default(pb_field_iter_t *field)
+{
+ 8023b68:	b580      	push	{r7, lr}
+ 8023b6a:	b08e      	sub	sp, #56	@ 0x38
+ 8023b6c:	af00      	add	r7, sp, #0
+ 8023b6e:	6078      	str	r0, [r7, #4]
+    pb_type_t type;
+    type = field->type;
+ 8023b70:	687b      	ldr	r3, [r7, #4]
+ 8023b72:	7d9b      	ldrb	r3, [r3, #22]
+ 8023b74:	f887 3032 	strb.w	r3, [r7, #50]	@ 0x32
+
+    if (PB_LTYPE(type) == PB_LTYPE_EXTENSION)
+ 8023b78:	f897 3032 	ldrb.w	r3, [r7, #50]	@ 0x32
+ 8023b7c:	f003 030f 	and.w	r3, r3, #15
+ 8023b80:	2b0a      	cmp	r3, #10
+ 8023b82:	d124      	bne.n	8023bce <pb_field_set_to_default+0x66>
+    {
+        pb_extension_t *ext = *(pb_extension_t* const *)field->pData;
+ 8023b84:	687b      	ldr	r3, [r7, #4]
+ 8023b86:	69db      	ldr	r3, [r3, #28]
+ 8023b88:	681b      	ldr	r3, [r3, #0]
+ 8023b8a:	637b      	str	r3, [r7, #52]	@ 0x34
+        while (ext != NULL)
+ 8023b8c:	e01b      	b.n	8023bc6 <pb_field_set_to_default+0x5e>
+        {
+            pb_field_iter_t ext_iter;
+            if (pb_field_iter_begin_extension(&ext_iter, ext))
+ 8023b8e:	f107 0308 	add.w	r3, r7, #8
+ 8023b92:	6b79      	ldr	r1, [r7, #52]	@ 0x34
+ 8023b94:	4618      	mov	r0, r3
+ 8023b96:	f7fe ffa0 	bl	8022ada <pb_field_iter_begin_extension>
+ 8023b9a:	4603      	mov	r3, r0
+ 8023b9c:	2b00      	cmp	r3, #0
+ 8023b9e:	d00f      	beq.n	8023bc0 <pb_field_set_to_default+0x58>
+            {
+                ext->found = false;
+ 8023ba0:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
+ 8023ba2:	2200      	movs	r2, #0
+ 8023ba4:	731a      	strb	r2, [r3, #12]
+                if (!pb_message_set_to_defaults(&ext_iter))
+ 8023ba6:	f107 0308 	add.w	r3, r7, #8
+ 8023baa:	4618      	mov	r0, r3
+ 8023bac:	f000 f89d 	bl	8023cea <pb_message_set_to_defaults>
+ 8023bb0:	4603      	mov	r3, r0
+ 8023bb2:	f083 0301 	eor.w	r3, r3, #1
+ 8023bb6:	b2db      	uxtb	r3, r3
+ 8023bb8:	2b00      	cmp	r3, #0
+ 8023bba:	d001      	beq.n	8023bc0 <pb_field_set_to_default+0x58>
+                    return false;
+ 8023bbc:	2300      	movs	r3, #0
+ 8023bbe:	e090      	b.n	8023ce2 <pb_field_set_to_default+0x17a>
+            }
+            ext = ext->next;
+ 8023bc0:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
+ 8023bc2:	689b      	ldr	r3, [r3, #8]
+ 8023bc4:	637b      	str	r3, [r7, #52]	@ 0x34
+        while (ext != NULL)
+ 8023bc6:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
+ 8023bc8:	2b00      	cmp	r3, #0
+ 8023bca:	d1e0      	bne.n	8023b8e <pb_field_set_to_default+0x26>
+ 8023bcc:	e088      	b.n	8023ce0 <pb_field_set_to_default+0x178>
+        }
+    }
+    else if (PB_ATYPE(type) == PB_ATYPE_STATIC)
+ 8023bce:	f897 3032 	ldrb.w	r3, [r7, #50]	@ 0x32
+ 8023bd2:	f003 03c0 	and.w	r3, r3, #192	@ 0xc0
+ 8023bd6:	2b00      	cmp	r3, #0
+ 8023bd8:	d166      	bne.n	8023ca8 <pb_field_set_to_default+0x140>
+    {
+        bool init_data = true;
+ 8023bda:	2301      	movs	r3, #1
+ 8023bdc:	f887 3033 	strb.w	r3, [r7, #51]	@ 0x33
+        if (PB_HTYPE(type) == PB_HTYPE_OPTIONAL && field->pSize != NULL)
+ 8023be0:	f897 3032 	ldrb.w	r3, [r7, #50]	@ 0x32
+ 8023be4:	f003 0330 	and.w	r3, r3, #48	@ 0x30
+ 8023be8:	2b10      	cmp	r3, #16
+ 8023bea:	d108      	bne.n	8023bfe <pb_field_set_to_default+0x96>
+ 8023bec:	687b      	ldr	r3, [r7, #4]
+ 8023bee:	6a1b      	ldr	r3, [r3, #32]
+ 8023bf0:	2b00      	cmp	r3, #0
+ 8023bf2:	d004      	beq.n	8023bfe <pb_field_set_to_default+0x96>
+        {
+            /* Set has_field to false. Still initialize the optional field
+             * itself also. */
+            *(bool*)field->pSize = false;
+ 8023bf4:	687b      	ldr	r3, [r7, #4]
+ 8023bf6:	6a1b      	ldr	r3, [r3, #32]
+ 8023bf8:	2200      	movs	r2, #0
+ 8023bfa:	701a      	strb	r2, [r3, #0]
+ 8023bfc:	e012      	b.n	8023c24 <pb_field_set_to_default+0xbc>
+        }
+        else if (PB_HTYPE(type) == PB_HTYPE_REPEATED ||
+ 8023bfe:	f897 3032 	ldrb.w	r3, [r7, #50]	@ 0x32
+ 8023c02:	f003 0330 	and.w	r3, r3, #48	@ 0x30
+ 8023c06:	2b20      	cmp	r3, #32
+ 8023c08:	d005      	beq.n	8023c16 <pb_field_set_to_default+0xae>
+                 PB_HTYPE(type) == PB_HTYPE_ONEOF)
+ 8023c0a:	f897 3032 	ldrb.w	r3, [r7, #50]	@ 0x32
+ 8023c0e:	f003 0330 	and.w	r3, r3, #48	@ 0x30
+        else if (PB_HTYPE(type) == PB_HTYPE_REPEATED ||
+ 8023c12:	2b30      	cmp	r3, #48	@ 0x30
+ 8023c14:	d106      	bne.n	8023c24 <pb_field_set_to_default+0xbc>
+        {
+            /* REPEATED: Set array count to 0, no need to initialize contents.
+               ONEOF: Set which_field to 0. */
+            *(pb_size_t*)field->pSize = 0;
+ 8023c16:	687b      	ldr	r3, [r7, #4]
+ 8023c18:	6a1b      	ldr	r3, [r3, #32]
+ 8023c1a:	2200      	movs	r2, #0
+ 8023c1c:	801a      	strh	r2, [r3, #0]
+            init_data = false;
+ 8023c1e:	2300      	movs	r3, #0
+ 8023c20:	f887 3033 	strb.w	r3, [r7, #51]	@ 0x33
+        }
+
+        if (init_data)
+ 8023c24:	f897 3033 	ldrb.w	r3, [r7, #51]	@ 0x33
+ 8023c28:	2b00      	cmp	r3, #0
+ 8023c2a:	d059      	beq.n	8023ce0 <pb_field_set_to_default+0x178>
+        {
+            if (PB_LTYPE_IS_SUBMSG(field->type) &&
+ 8023c2c:	687b      	ldr	r3, [r7, #4]
+ 8023c2e:	7d9b      	ldrb	r3, [r3, #22]
+ 8023c30:	f003 030f 	and.w	r3, r3, #15
+ 8023c34:	2b08      	cmp	r3, #8
+ 8023c36:	d005      	beq.n	8023c44 <pb_field_set_to_default+0xdc>
+ 8023c38:	687b      	ldr	r3, [r7, #4]
+ 8023c3a:	7d9b      	ldrb	r3, [r3, #22]
+ 8023c3c:	f003 030f 	and.w	r3, r3, #15
+ 8023c40:	2b09      	cmp	r3, #9
+ 8023c42:	d128      	bne.n	8023c96 <pb_field_set_to_default+0x12e>
+                (field->submsg_desc->default_value != NULL ||
+ 8023c44:	687b      	ldr	r3, [r7, #4]
+ 8023c46:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 8023c48:	689b      	ldr	r3, [r3, #8]
+            if (PB_LTYPE_IS_SUBMSG(field->type) &&
+ 8023c4a:	2b00      	cmp	r3, #0
+ 8023c4c:	d10a      	bne.n	8023c64 <pb_field_set_to_default+0xfc>
+                 field->submsg_desc->field_callback != NULL ||
+ 8023c4e:	687b      	ldr	r3, [r7, #4]
+ 8023c50:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 8023c52:	68db      	ldr	r3, [r3, #12]
+                (field->submsg_desc->default_value != NULL ||
+ 8023c54:	2b00      	cmp	r3, #0
+ 8023c56:	d105      	bne.n	8023c64 <pb_field_set_to_default+0xfc>
+                 field->submsg_desc->submsg_info[0] != NULL))
+ 8023c58:	687b      	ldr	r3, [r7, #4]
+ 8023c5a:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 8023c5c:	685b      	ldr	r3, [r3, #4]
+ 8023c5e:	681b      	ldr	r3, [r3, #0]
+                 field->submsg_desc->field_callback != NULL ||
+ 8023c60:	2b00      	cmp	r3, #0
+ 8023c62:	d018      	beq.n	8023c96 <pb_field_set_to_default+0x12e>
+            {
+                /* Initialize submessage to defaults.
+                 * Only needed if it has default values
+                 * or callback/submessage fields. */
+                pb_field_iter_t submsg_iter;
+                if (pb_field_iter_begin(&submsg_iter, field->submsg_desc, field->pData))
+ 8023c64:	687b      	ldr	r3, [r7, #4]
+ 8023c66:	6a59      	ldr	r1, [r3, #36]	@ 0x24
+ 8023c68:	687b      	ldr	r3, [r7, #4]
+ 8023c6a:	69da      	ldr	r2, [r3, #28]
+ 8023c6c:	f107 0308 	add.w	r3, r7, #8
+ 8023c70:	4618      	mov	r0, r3
+ 8023c72:	f7fe ff19 	bl	8022aa8 <pb_field_iter_begin>
+ 8023c76:	4603      	mov	r3, r0
+ 8023c78:	2b00      	cmp	r3, #0
+ 8023c7a:	d030      	beq.n	8023cde <pb_field_set_to_default+0x176>
+                {
+                    if (!pb_message_set_to_defaults(&submsg_iter))
+ 8023c7c:	f107 0308 	add.w	r3, r7, #8
+ 8023c80:	4618      	mov	r0, r3
+ 8023c82:	f000 f832 	bl	8023cea <pb_message_set_to_defaults>
+ 8023c86:	4603      	mov	r3, r0
+ 8023c88:	f083 0301 	eor.w	r3, r3, #1
+ 8023c8c:	b2db      	uxtb	r3, r3
+ 8023c8e:	2b00      	cmp	r3, #0
+ 8023c90:	d025      	beq.n	8023cde <pb_field_set_to_default+0x176>
+                        return false;
+ 8023c92:	2300      	movs	r3, #0
+ 8023c94:	e025      	b.n	8023ce2 <pb_field_set_to_default+0x17a>
+                }
+            }
+            else
+            {
+                /* Initialize to zeros */
+                memset(field->pData, 0, (size_t)field->data_size);
+ 8023c96:	687b      	ldr	r3, [r7, #4]
+ 8023c98:	69d8      	ldr	r0, [r3, #28]
+ 8023c9a:	687b      	ldr	r3, [r7, #4]
+ 8023c9c:	8a5b      	ldrh	r3, [r3, #18]
+ 8023c9e:	461a      	mov	r2, r3
+ 8023ca0:	2100      	movs	r1, #0
+ 8023ca2:	f01c fb21 	bl	80402e8 <memset>
+ 8023ca6:	e01b      	b.n	8023ce0 <pb_field_set_to_default+0x178>
+            }
+        }
+    }
+    else if (PB_ATYPE(type) == PB_ATYPE_POINTER)
+ 8023ca8:	f897 3032 	ldrb.w	r3, [r7, #50]	@ 0x32
+ 8023cac:	f003 03c0 	and.w	r3, r3, #192	@ 0xc0
+ 8023cb0:	2b80      	cmp	r3, #128	@ 0x80
+ 8023cb2:	d115      	bne.n	8023ce0 <pb_field_set_to_default+0x178>
+    {
+        /* Initialize the pointer to NULL. */
+        *(void**)field->pField = NULL;
+ 8023cb4:	687b      	ldr	r3, [r7, #4]
+ 8023cb6:	699b      	ldr	r3, [r3, #24]
+ 8023cb8:	2200      	movs	r2, #0
+ 8023cba:	601a      	str	r2, [r3, #0]
+
+        /* Initialize array count to 0. */
+        if (PB_HTYPE(type) == PB_HTYPE_REPEATED ||
+ 8023cbc:	f897 3032 	ldrb.w	r3, [r7, #50]	@ 0x32
+ 8023cc0:	f003 0330 	and.w	r3, r3, #48	@ 0x30
+ 8023cc4:	2b20      	cmp	r3, #32
+ 8023cc6:	d005      	beq.n	8023cd4 <pb_field_set_to_default+0x16c>
+            PB_HTYPE(type) == PB_HTYPE_ONEOF)
+ 8023cc8:	f897 3032 	ldrb.w	r3, [r7, #50]	@ 0x32
+ 8023ccc:	f003 0330 	and.w	r3, r3, #48	@ 0x30
+        if (PB_HTYPE(type) == PB_HTYPE_REPEATED ||
+ 8023cd0:	2b30      	cmp	r3, #48	@ 0x30
+ 8023cd2:	d105      	bne.n	8023ce0 <pb_field_set_to_default+0x178>
+        {
+            *(pb_size_t*)field->pSize = 0;
+ 8023cd4:	687b      	ldr	r3, [r7, #4]
+ 8023cd6:	6a1b      	ldr	r3, [r3, #32]
+ 8023cd8:	2200      	movs	r2, #0
+ 8023cda:	801a      	strh	r2, [r3, #0]
+ 8023cdc:	e000      	b.n	8023ce0 <pb_field_set_to_default+0x178>
+            {
+ 8023cde:	bf00      	nop
+    else if (PB_ATYPE(type) == PB_ATYPE_CALLBACK)
+    {
+        /* Don't overwrite callback */
+    }
+
+    return true;
+ 8023ce0:	2301      	movs	r3, #1
+}
+ 8023ce2:	4618      	mov	r0, r3
+ 8023ce4:	3738      	adds	r7, #56	@ 0x38
+ 8023ce6:	46bd      	mov	sp, r7
+ 8023ce8:	bd80      	pop	{r7, pc}
+
+08023cea <pb_message_set_to_defaults>:
+
+static bool pb_message_set_to_defaults(pb_field_iter_t *iter)
+{
+ 8023cea:	b590      	push	{r4, r7, lr}
+ 8023cec:	b08d      	sub	sp, #52	@ 0x34
+ 8023cee:	af00      	add	r7, sp, #0
+ 8023cf0:	6178      	str	r0, [r7, #20]
+    pb_istream_t defstream = PB_ISTREAM_EMPTY;
+ 8023cf2:	f107 0320 	add.w	r3, r7, #32
+ 8023cf6:	2200      	movs	r2, #0
+ 8023cf8:	601a      	str	r2, [r3, #0]
+ 8023cfa:	605a      	str	r2, [r3, #4]
+ 8023cfc:	609a      	str	r2, [r3, #8]
+ 8023cfe:	60da      	str	r2, [r3, #12]
+    uint32_t tag = 0;
+ 8023d00:	2300      	movs	r3, #0
+ 8023d02:	61fb      	str	r3, [r7, #28]
+    pb_wire_type_t wire_type = PB_WT_VARINT;
+ 8023d04:	2300      	movs	r3, #0
+ 8023d06:	76fb      	strb	r3, [r7, #27]
+    bool eof;
+
+    if (iter->descriptor->default_value)
+ 8023d08:	697b      	ldr	r3, [r7, #20]
+ 8023d0a:	681b      	ldr	r3, [r3, #0]
+ 8023d0c:	689b      	ldr	r3, [r3, #8]
+ 8023d0e:	2b00      	cmp	r3, #0
+ 8023d10:	d020      	beq.n	8023d54 <pb_message_set_to_defaults+0x6a>
+    {
+        defstream = pb_istream_from_buffer(iter->descriptor->default_value, (size_t)-1);
+ 8023d12:	697b      	ldr	r3, [r7, #20]
+ 8023d14:	681b      	ldr	r3, [r3, #0]
+ 8023d16:	6899      	ldr	r1, [r3, #8]
+ 8023d18:	463b      	mov	r3, r7
+ 8023d1a:	f04f 32ff 	mov.w	r2, #4294967295
+ 8023d1e:	4618      	mov	r0, r3
+ 8023d20:	f7ff f8e0 	bl	8022ee4 <pb_istream_from_buffer>
+ 8023d24:	f107 0420 	add.w	r4, r7, #32
+ 8023d28:	463b      	mov	r3, r7
+ 8023d2a:	cb0f      	ldmia	r3, {r0, r1, r2, r3}
+ 8023d2c:	e884 000f 	stmia.w	r4, {r0, r1, r2, r3}
+        if (!pb_decode_tag(&defstream, &wire_type, &tag, &eof))
+ 8023d30:	f107 031a 	add.w	r3, r7, #26
+ 8023d34:	f107 021c 	add.w	r2, r7, #28
+ 8023d38:	f107 011b 	add.w	r1, r7, #27
+ 8023d3c:	f107 0020 	add.w	r0, r7, #32
+ 8023d40:	f7ff fa47 	bl	80231d2 <pb_decode_tag>
+ 8023d44:	4603      	mov	r3, r0
+ 8023d46:	f083 0301 	eor.w	r3, r3, #1
+ 8023d4a:	b2db      	uxtb	r3, r3
+ 8023d4c:	2b00      	cmp	r3, #0
+ 8023d4e:	d001      	beq.n	8023d54 <pb_message_set_to_defaults+0x6a>
+            return false;
+ 8023d50:	2300      	movs	r3, #0
+ 8023d52:	e043      	b.n	8023ddc <pb_message_set_to_defaults+0xf2>
+    }
+
+    do
+    {
+        if (!pb_field_set_to_default(iter))
+ 8023d54:	6978      	ldr	r0, [r7, #20]
+ 8023d56:	f7ff ff07 	bl	8023b68 <pb_field_set_to_default>
+ 8023d5a:	4603      	mov	r3, r0
+ 8023d5c:	f083 0301 	eor.w	r3, r3, #1
+ 8023d60:	b2db      	uxtb	r3, r3
+ 8023d62:	2b00      	cmp	r3, #0
+ 8023d64:	d001      	beq.n	8023d6a <pb_message_set_to_defaults+0x80>
+            return false;
+ 8023d66:	2300      	movs	r3, #0
+ 8023d68:	e038      	b.n	8023ddc <pb_message_set_to_defaults+0xf2>
+
+        if (tag != 0 && iter->tag == tag)
+ 8023d6a:	69fb      	ldr	r3, [r7, #28]
+ 8023d6c:	2b00      	cmp	r3, #0
+ 8023d6e:	d02e      	beq.n	8023dce <pb_message_set_to_defaults+0xe4>
+ 8023d70:	697b      	ldr	r3, [r7, #20]
+ 8023d72:	8a1b      	ldrh	r3, [r3, #16]
+ 8023d74:	461a      	mov	r2, r3
+ 8023d76:	69fb      	ldr	r3, [r7, #28]
+ 8023d78:	429a      	cmp	r2, r3
+ 8023d7a:	d128      	bne.n	8023dce <pb_message_set_to_defaults+0xe4>
+        {
+            /* We have a default value for this field in the defstream */
+            if (!decode_field(&defstream, wire_type, iter))
+ 8023d7c:	7ef9      	ldrb	r1, [r7, #27]
+ 8023d7e:	f107 0320 	add.w	r3, r7, #32
+ 8023d82:	697a      	ldr	r2, [r7, #20]
+ 8023d84:	4618      	mov	r0, r3
+ 8023d86:	f7ff fe3b 	bl	8023a00 <decode_field>
+ 8023d8a:	4603      	mov	r3, r0
+ 8023d8c:	f083 0301 	eor.w	r3, r3, #1
+ 8023d90:	b2db      	uxtb	r3, r3
+ 8023d92:	2b00      	cmp	r3, #0
+ 8023d94:	d001      	beq.n	8023d9a <pb_message_set_to_defaults+0xb0>
+                return false;
+ 8023d96:	2300      	movs	r3, #0
+ 8023d98:	e020      	b.n	8023ddc <pb_message_set_to_defaults+0xf2>
+            if (!pb_decode_tag(&defstream, &wire_type, &tag, &eof))
+ 8023d9a:	f107 031a 	add.w	r3, r7, #26
+ 8023d9e:	f107 021c 	add.w	r2, r7, #28
+ 8023da2:	f107 011b 	add.w	r1, r7, #27
+ 8023da6:	f107 0020 	add.w	r0, r7, #32
+ 8023daa:	f7ff fa12 	bl	80231d2 <pb_decode_tag>
+ 8023dae:	4603      	mov	r3, r0
+ 8023db0:	f083 0301 	eor.w	r3, r3, #1
+ 8023db4:	b2db      	uxtb	r3, r3
+ 8023db6:	2b00      	cmp	r3, #0
+ 8023db8:	d001      	beq.n	8023dbe <pb_message_set_to_defaults+0xd4>
+                return false;
+ 8023dba:	2300      	movs	r3, #0
+ 8023dbc:	e00e      	b.n	8023ddc <pb_message_set_to_defaults+0xf2>
+
+            if (iter->pSize)
+ 8023dbe:	697b      	ldr	r3, [r7, #20]
+ 8023dc0:	6a1b      	ldr	r3, [r3, #32]
+ 8023dc2:	2b00      	cmp	r3, #0
+ 8023dc4:	d003      	beq.n	8023dce <pb_message_set_to_defaults+0xe4>
+                *(bool*)iter->pSize = false;
+ 8023dc6:	697b      	ldr	r3, [r7, #20]
+ 8023dc8:	6a1b      	ldr	r3, [r3, #32]
+ 8023dca:	2200      	movs	r2, #0
+ 8023dcc:	701a      	strb	r2, [r3, #0]
+        }
+    } while (pb_field_iter_next(iter));
+ 8023dce:	6978      	ldr	r0, [r7, #20]
+ 8023dd0:	f7fe feb3 	bl	8022b3a <pb_field_iter_next>
+ 8023dd4:	4603      	mov	r3, r0
+ 8023dd6:	2b00      	cmp	r3, #0
+ 8023dd8:	d1bc      	bne.n	8023d54 <pb_message_set_to_defaults+0x6a>
+
+    return true;
+ 8023dda:	2301      	movs	r3, #1
+}
+ 8023ddc:	4618      	mov	r0, r3
+ 8023dde:	3734      	adds	r7, #52	@ 0x34
+ 8023de0:	46bd      	mov	sp, r7
+ 8023de2:	bd90      	pop	{r4, r7, pc}
+
+08023de4 <pb_decode_inner>:
+/*********************
+ * Decode all fields *
+ *********************/
+
+static bool checkreturn pb_decode_inner(pb_istream_t *stream, const pb_msgdesc_t *fields, void *dest_struct, unsigned int flags)
+{
+ 8023de4:	b580      	push	{r7, lr}
+ 8023de6:	b09a      	sub	sp, #104	@ 0x68
+ 8023de8:	af00      	add	r7, sp, #0
+ 8023dea:	60f8      	str	r0, [r7, #12]
+ 8023dec:	60b9      	str	r1, [r7, #8]
+ 8023dee:	607a      	str	r2, [r7, #4]
+ 8023df0:	603b      	str	r3, [r7, #0]
+    uint32_t extension_range_start = 0;
+ 8023df2:	2300      	movs	r3, #0
+ 8023df4:	667b      	str	r3, [r7, #100]	@ 0x64
+    pb_extension_t *extensions = NULL;
+ 8023df6:	2300      	movs	r3, #0
+ 8023df8:	663b      	str	r3, [r7, #96]	@ 0x60
+
+    /* 'fixed_count_field' and 'fixed_count_size' track position of a repeated fixed
+     * count field. This can only handle _one_ repeated fixed count field that
+     * is unpacked and unordered among other (non repeated fixed count) fields.
+     */
+    pb_size_t fixed_count_field = PB_SIZE_MAX;
+ 8023dfa:	f64f 73ff 	movw	r3, #65535	@ 0xffff
+ 8023dfe:	f8a7 305e 	strh.w	r3, [r7, #94]	@ 0x5e
+    pb_size_t fixed_count_size = 0;
+ 8023e02:	2300      	movs	r3, #0
+ 8023e04:	f8a7 304a 	strh.w	r3, [r7, #74]	@ 0x4a
+    pb_size_t fixed_count_total_size = 0;
+ 8023e08:	2300      	movs	r3, #0
+ 8023e0a:	f8a7 305c 	strh.w	r3, [r7, #92]	@ 0x5c
+
+    pb_fields_seen_t fields_seen = {{0, 0}};
+ 8023e0e:	2300      	movs	r3, #0
+ 8023e10:	643b      	str	r3, [r7, #64]	@ 0x40
+ 8023e12:	2300      	movs	r3, #0
+ 8023e14:	647b      	str	r3, [r7, #68]	@ 0x44
+    const uint32_t allbits = ~(uint32_t)0;
+ 8023e16:	f04f 33ff 	mov.w	r3, #4294967295
+ 8023e1a:	657b      	str	r3, [r7, #84]	@ 0x54
+    pb_field_iter_t iter;
+
+    if (pb_field_iter_begin(&iter, fields, dest_struct))
+ 8023e1c:	f107 0318 	add.w	r3, r7, #24
+ 8023e20:	687a      	ldr	r2, [r7, #4]
+ 8023e22:	68b9      	ldr	r1, [r7, #8]
+ 8023e24:	4618      	mov	r0, r3
+ 8023e26:	f7fe fe3f 	bl	8022aa8 <pb_field_iter_begin>
+ 8023e2a:	4603      	mov	r3, r0
+ 8023e2c:	2b00      	cmp	r3, #0
+ 8023e2e:	f000 8102 	beq.w	8024036 <pb_decode_inner+0x252>
+    {
+        if ((flags & PB_DECODE_NOINIT) == 0)
+ 8023e32:	683b      	ldr	r3, [r7, #0]
+ 8023e34:	f003 0301 	and.w	r3, r3, #1
+ 8023e38:	2b00      	cmp	r3, #0
+ 8023e3a:	f040 80fc 	bne.w	8024036 <pb_decode_inner+0x252>
+        {
+            if (!pb_message_set_to_defaults(&iter))
+ 8023e3e:	f107 0318 	add.w	r3, r7, #24
+ 8023e42:	4618      	mov	r0, r3
+ 8023e44:	f7ff ff51 	bl	8023cea <pb_message_set_to_defaults>
+ 8023e48:	4603      	mov	r3, r0
+ 8023e4a:	f083 0301 	eor.w	r3, r3, #1
+ 8023e4e:	b2db      	uxtb	r3, r3
+ 8023e50:	2b00      	cmp	r3, #0
+ 8023e52:	f000 80f0 	beq.w	8024036 <pb_decode_inner+0x252>
+                PB_RETURN_ERROR(stream, "failed to set defaults");
+ 8023e56:	68fb      	ldr	r3, [r7, #12]
+ 8023e58:	68db      	ldr	r3, [r3, #12]
+ 8023e5a:	2b00      	cmp	r3, #0
+ 8023e5c:	d002      	beq.n	8023e64 <pb_decode_inner+0x80>
+ 8023e5e:	68fb      	ldr	r3, [r7, #12]
+ 8023e60:	68db      	ldr	r3, [r3, #12]
+ 8023e62:	e000      	b.n	8023e66 <pb_decode_inner+0x82>
+ 8023e64:	4b99      	ldr	r3, [pc, #612]	@ (80240cc <pb_decode_inner+0x2e8>)
+ 8023e66:	68fa      	ldr	r2, [r7, #12]
+ 8023e68:	60d3      	str	r3, [r2, #12]
+ 8023e6a:	2300      	movs	r3, #0
+ 8023e6c:	e16d      	b.n	802414a <pb_decode_inner+0x366>
+    {
+        uint32_t tag;
+        pb_wire_type_t wire_type;
+        bool eof;
+
+        if (!pb_decode_tag(stream, &wire_type, &tag, &eof))
+ 8023e6e:	f107 0312 	add.w	r3, r7, #18
+ 8023e72:	f107 0214 	add.w	r2, r7, #20
+ 8023e76:	f107 0113 	add.w	r1, r7, #19
+ 8023e7a:	68f8      	ldr	r0, [r7, #12]
+ 8023e7c:	f7ff f9a9 	bl	80231d2 <pb_decode_tag>
+ 8023e80:	4603      	mov	r3, r0
+ 8023e82:	f083 0301 	eor.w	r3, r3, #1
+ 8023e86:	b2db      	uxtb	r3, r3
+ 8023e88:	2b00      	cmp	r3, #0
+ 8023e8a:	d005      	beq.n	8023e98 <pb_decode_inner+0xb4>
+        {
+            if (eof)
+ 8023e8c:	7cbb      	ldrb	r3, [r7, #18]
+ 8023e8e:	2b00      	cmp	r3, #0
+ 8023e90:	f040 80d7 	bne.w	8024042 <pb_decode_inner+0x25e>
+                break;
+            else
+                return false;
+ 8023e94:	2300      	movs	r3, #0
+ 8023e96:	e158      	b.n	802414a <pb_decode_inner+0x366>
+        }
+
+        if (tag == 0)
+ 8023e98:	697b      	ldr	r3, [r7, #20]
+ 8023e9a:	2b00      	cmp	r3, #0
+ 8023e9c:	d111      	bne.n	8023ec2 <pb_decode_inner+0xde>
+        {
+          if (flags & PB_DECODE_NULLTERMINATED)
+ 8023e9e:	683b      	ldr	r3, [r7, #0]
+ 8023ea0:	f003 0304 	and.w	r3, r3, #4
+ 8023ea4:	2b00      	cmp	r3, #0
+ 8023ea6:	f040 80ce 	bne.w	8024046 <pb_decode_inner+0x262>
+          {
+            break;
+          }
+          else
+          {
+            PB_RETURN_ERROR(stream, "zero tag");
+ 8023eaa:	68fb      	ldr	r3, [r7, #12]
+ 8023eac:	68db      	ldr	r3, [r3, #12]
+ 8023eae:	2b00      	cmp	r3, #0
+ 8023eb0:	d002      	beq.n	8023eb8 <pb_decode_inner+0xd4>
+ 8023eb2:	68fb      	ldr	r3, [r7, #12]
+ 8023eb4:	68db      	ldr	r3, [r3, #12]
+ 8023eb6:	e000      	b.n	8023eba <pb_decode_inner+0xd6>
+ 8023eb8:	4b85      	ldr	r3, [pc, #532]	@ (80240d0 <pb_decode_inner+0x2ec>)
+ 8023eba:	68fa      	ldr	r2, [r7, #12]
+ 8023ebc:	60d3      	str	r3, [r2, #12]
+ 8023ebe:	2300      	movs	r3, #0
+ 8023ec0:	e143      	b.n	802414a <pb_decode_inner+0x366>
+          }
+        }
+
+        if (!pb_field_iter_find(&iter, tag) || PB_LTYPE(iter.type) == PB_LTYPE_EXTENSION)
+ 8023ec2:	697a      	ldr	r2, [r7, #20]
+ 8023ec4:	f107 0318 	add.w	r3, r7, #24
+ 8023ec8:	4611      	mov	r1, r2
+ 8023eca:	4618      	mov	r0, r3
+ 8023ecc:	f7fe fe4a 	bl	8022b64 <pb_field_iter_find>
+ 8023ed0:	4603      	mov	r3, r0
+ 8023ed2:	f083 0301 	eor.w	r3, r3, #1
+ 8023ed6:	b2db      	uxtb	r3, r3
+ 8023ed8:	2b00      	cmp	r3, #0
+ 8023eda:	d105      	bne.n	8023ee8 <pb_decode_inner+0x104>
+ 8023edc:	f897 302e 	ldrb.w	r3, [r7, #46]	@ 0x2e
+ 8023ee0:	f003 030f 	and.w	r3, r3, #15
+ 8023ee4:	2b0a      	cmp	r3, #10
+ 8023ee6:	d13c      	bne.n	8023f62 <pb_decode_inner+0x17e>
+        {
+            /* No match found, check if it matches an extension. */
+            if (extension_range_start == 0)
+ 8023ee8:	6e7b      	ldr	r3, [r7, #100]	@ 0x64
+ 8023eea:	2b00      	cmp	r3, #0
+ 8023eec:	d112      	bne.n	8023f14 <pb_decode_inner+0x130>
+            {
+                if (pb_field_iter_find_extension(&iter))
+ 8023eee:	f107 0318 	add.w	r3, r7, #24
+ 8023ef2:	4618      	mov	r0, r3
+ 8023ef4:	f7fe fe8c 	bl	8022c10 <pb_field_iter_find_extension>
+ 8023ef8:	4603      	mov	r3, r0
+ 8023efa:	2b00      	cmp	r3, #0
+ 8023efc:	d004      	beq.n	8023f08 <pb_decode_inner+0x124>
+                {
+                    extensions = *(pb_extension_t* const *)iter.pData;
+ 8023efe:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
+ 8023f00:	681b      	ldr	r3, [r3, #0]
+ 8023f02:	663b      	str	r3, [r7, #96]	@ 0x60
+                    extension_range_start = iter.tag;
+ 8023f04:	8d3b      	ldrh	r3, [r7, #40]	@ 0x28
+ 8023f06:	667b      	str	r3, [r7, #100]	@ 0x64
+                }
+
+                if (!extensions)
+ 8023f08:	6e3b      	ldr	r3, [r7, #96]	@ 0x60
+ 8023f0a:	2b00      	cmp	r3, #0
+ 8023f0c:	d102      	bne.n	8023f14 <pb_decode_inner+0x130>
+                {
+                    extension_range_start = (uint32_t)-1;
+ 8023f0e:	f04f 33ff 	mov.w	r3, #4294967295
+ 8023f12:	667b      	str	r3, [r7, #100]	@ 0x64
+                }
+            }
+
+            if (tag >= extension_range_start)
+ 8023f14:	697b      	ldr	r3, [r7, #20]
+ 8023f16:	6e7a      	ldr	r2, [r7, #100]	@ 0x64
+ 8023f18:	429a      	cmp	r2, r3
+ 8023f1a:	d815      	bhi.n	8023f48 <pb_decode_inner+0x164>
+            {
+                size_t pos = stream->bytes_left;
+ 8023f1c:	68fb      	ldr	r3, [r7, #12]
+ 8023f1e:	689b      	ldr	r3, [r3, #8]
+ 8023f20:	64fb      	str	r3, [r7, #76]	@ 0x4c
+
+                if (!decode_extension(stream, tag, wire_type, extensions))
+ 8023f22:	6979      	ldr	r1, [r7, #20]
+ 8023f24:	7cfa      	ldrb	r2, [r7, #19]
+ 8023f26:	6e3b      	ldr	r3, [r7, #96]	@ 0x60
+ 8023f28:	68f8      	ldr	r0, [r7, #12]
+ 8023f2a:	f7ff fde1 	bl	8023af0 <decode_extension>
+ 8023f2e:	4603      	mov	r3, r0
+ 8023f30:	f083 0301 	eor.w	r3, r3, #1
+ 8023f34:	b2db      	uxtb	r3, r3
+ 8023f36:	2b00      	cmp	r3, #0
+ 8023f38:	d001      	beq.n	8023f3e <pb_decode_inner+0x15a>
+                    return false;
+ 8023f3a:	2300      	movs	r3, #0
+ 8023f3c:	e105      	b.n	802414a <pb_decode_inner+0x366>
+
+                if (pos != stream->bytes_left)
+ 8023f3e:	68fb      	ldr	r3, [r7, #12]
+ 8023f40:	689b      	ldr	r3, [r3, #8]
+ 8023f42:	6cfa      	ldr	r2, [r7, #76]	@ 0x4c
+ 8023f44:	429a      	cmp	r2, r3
+ 8023f46:	d173      	bne.n	8024030 <pb_decode_inner+0x24c>
+                    continue;
+                }
+            }
+
+            /* No match found, skip data */
+            if (!pb_skip_field(stream, wire_type))
+ 8023f48:	7cfb      	ldrb	r3, [r7, #19]
+ 8023f4a:	4619      	mov	r1, r3
+ 8023f4c:	68f8      	ldr	r0, [r7, #12]
+ 8023f4e:	f7ff f96f 	bl	8023230 <pb_skip_field>
+ 8023f52:	4603      	mov	r3, r0
+ 8023f54:	f083 0301 	eor.w	r3, r3, #1
+ 8023f58:	b2db      	uxtb	r3, r3
+ 8023f5a:	2b00      	cmp	r3, #0
+ 8023f5c:	d06a      	beq.n	8024034 <pb_decode_inner+0x250>
+                return false;
+ 8023f5e:	2300      	movs	r3, #0
+ 8023f60:	e0f3      	b.n	802414a <pb_decode_inner+0x366>
+        }
+
+        /* If a repeated fixed count field was found, get size from
+         * 'fixed_count_field' as there is no counter contained in the struct.
+         */
+        if (PB_HTYPE(iter.type) == PB_HTYPE_REPEATED && iter.pSize == &iter.array_size)
+ 8023f62:	f897 302e 	ldrb.w	r3, [r7, #46]	@ 0x2e
+ 8023f66:	f003 0330 	and.w	r3, r3, #48	@ 0x30
+ 8023f6a:	2b20      	cmp	r3, #32
+ 8023f6c:	d12e      	bne.n	8023fcc <pb_decode_inner+0x1e8>
+ 8023f6e:	6bba      	ldr	r2, [r7, #56]	@ 0x38
+ 8023f70:	f107 0318 	add.w	r3, r7, #24
+ 8023f74:	3314      	adds	r3, #20
+ 8023f76:	429a      	cmp	r2, r3
+ 8023f78:	d128      	bne.n	8023fcc <pb_decode_inner+0x1e8>
+        {
+            if (fixed_count_field != iter.index) {
+ 8023f7a:	8c3b      	ldrh	r3, [r7, #32]
+ 8023f7c:	f8b7 205e 	ldrh.w	r2, [r7, #94]	@ 0x5e
+ 8023f80:	429a      	cmp	r2, r3
+ 8023f82:	d020      	beq.n	8023fc6 <pb_decode_inner+0x1e2>
+                /* If the new fixed count field does not match the previous one,
+                 * check that the previous one is NULL or that it finished
+                 * receiving all the expected data.
+                 */
+                if (fixed_count_field != PB_SIZE_MAX &&
+ 8023f84:	f8b7 305e 	ldrh.w	r3, [r7, #94]	@ 0x5e
+ 8023f88:	f64f 72ff 	movw	r2, #65535	@ 0xffff
+ 8023f8c:	4293      	cmp	r3, r2
+ 8023f8e:	d011      	beq.n	8023fb4 <pb_decode_inner+0x1d0>
+                    fixed_count_size != fixed_count_total_size)
+ 8023f90:	f8b7 304a 	ldrh.w	r3, [r7, #74]	@ 0x4a
+                if (fixed_count_field != PB_SIZE_MAX &&
+ 8023f94:	f8b7 205c 	ldrh.w	r2, [r7, #92]	@ 0x5c
+ 8023f98:	429a      	cmp	r2, r3
+ 8023f9a:	d00b      	beq.n	8023fb4 <pb_decode_inner+0x1d0>
+                {
+                    PB_RETURN_ERROR(stream, "wrong size for fixed count field");
+ 8023f9c:	68fb      	ldr	r3, [r7, #12]
+ 8023f9e:	68db      	ldr	r3, [r3, #12]
+ 8023fa0:	2b00      	cmp	r3, #0
+ 8023fa2:	d002      	beq.n	8023faa <pb_decode_inner+0x1c6>
+ 8023fa4:	68fb      	ldr	r3, [r7, #12]
+ 8023fa6:	68db      	ldr	r3, [r3, #12]
+ 8023fa8:	e000      	b.n	8023fac <pb_decode_inner+0x1c8>
+ 8023faa:	4b4a      	ldr	r3, [pc, #296]	@ (80240d4 <pb_decode_inner+0x2f0>)
+ 8023fac:	68fa      	ldr	r2, [r7, #12]
+ 8023fae:	60d3      	str	r3, [r2, #12]
+ 8023fb0:	2300      	movs	r3, #0
+ 8023fb2:	e0ca      	b.n	802414a <pb_decode_inner+0x366>
+                }
+
+                fixed_count_field = iter.index;
+ 8023fb4:	8c3b      	ldrh	r3, [r7, #32]
+ 8023fb6:	f8a7 305e 	strh.w	r3, [r7, #94]	@ 0x5e
+                fixed_count_size = 0;
+ 8023fba:	2300      	movs	r3, #0
+ 8023fbc:	f8a7 304a 	strh.w	r3, [r7, #74]	@ 0x4a
+                fixed_count_total_size = iter.array_size;
+ 8023fc0:	8dbb      	ldrh	r3, [r7, #44]	@ 0x2c
+ 8023fc2:	f8a7 305c 	strh.w	r3, [r7, #92]	@ 0x5c
+            }
+
+            iter.pSize = &fixed_count_size;
+ 8023fc6:	f107 034a 	add.w	r3, r7, #74	@ 0x4a
+ 8023fca:	63bb      	str	r3, [r7, #56]	@ 0x38
+        }
+
+        if (PB_HTYPE(iter.type) == PB_HTYPE_REQUIRED
+ 8023fcc:	f897 302e 	ldrb.w	r3, [r7, #46]	@ 0x2e
+ 8023fd0:	f003 0330 	and.w	r3, r3, #48	@ 0x30
+ 8023fd4:	2b00      	cmp	r3, #0
+ 8023fd6:	d11c      	bne.n	8024012 <pb_decode_inner+0x22e>
+            && iter.required_field_index < PB_MAX_REQUIRED_FIELDS)
+ 8023fd8:	8cbb      	ldrh	r3, [r7, #36]	@ 0x24
+ 8023fda:	2b3f      	cmp	r3, #63	@ 0x3f
+ 8023fdc:	d819      	bhi.n	8024012 <pb_decode_inner+0x22e>
+        {
+            uint32_t tmp = ((uint32_t)1 << (iter.required_field_index & 31));
+ 8023fde:	8cbb      	ldrh	r3, [r7, #36]	@ 0x24
+ 8023fe0:	f003 031f 	and.w	r3, r3, #31
+ 8023fe4:	2201      	movs	r2, #1
+ 8023fe6:	fa02 f303 	lsl.w	r3, r2, r3
+ 8023fea:	653b      	str	r3, [r7, #80]	@ 0x50
+            fields_seen.bitfield[iter.required_field_index >> 5] |= tmp;
+ 8023fec:	8cbb      	ldrh	r3, [r7, #36]	@ 0x24
+ 8023fee:	095b      	lsrs	r3, r3, #5
+ 8023ff0:	b29b      	uxth	r3, r3
+ 8023ff2:	009b      	lsls	r3, r3, #2
+ 8023ff4:	3368      	adds	r3, #104	@ 0x68
+ 8023ff6:	443b      	add	r3, r7
+ 8023ff8:	f853 2c28 	ldr.w	r2, [r3, #-40]
+ 8023ffc:	8cbb      	ldrh	r3, [r7, #36]	@ 0x24
+ 8023ffe:	095b      	lsrs	r3, r3, #5
+ 8024000:	b29b      	uxth	r3, r3
+ 8024002:	4619      	mov	r1, r3
+ 8024004:	6d3b      	ldr	r3, [r7, #80]	@ 0x50
+ 8024006:	431a      	orrs	r2, r3
+ 8024008:	008b      	lsls	r3, r1, #2
+ 802400a:	3368      	adds	r3, #104	@ 0x68
+ 802400c:	443b      	add	r3, r7
+ 802400e:	f843 2c28 	str.w	r2, [r3, #-40]
+        }
+
+        if (!decode_field(stream, wire_type, &iter))
+ 8024012:	7cfb      	ldrb	r3, [r7, #19]
+ 8024014:	f107 0218 	add.w	r2, r7, #24
+ 8024018:	4619      	mov	r1, r3
+ 802401a:	68f8      	ldr	r0, [r7, #12]
+ 802401c:	f7ff fcf0 	bl	8023a00 <decode_field>
+ 8024020:	4603      	mov	r3, r0
+ 8024022:	f083 0301 	eor.w	r3, r3, #1
+ 8024026:	b2db      	uxtb	r3, r3
+ 8024028:	2b00      	cmp	r3, #0
+ 802402a:	d004      	beq.n	8024036 <pb_decode_inner+0x252>
+            return false;
+ 802402c:	2300      	movs	r3, #0
+ 802402e:	e08c      	b.n	802414a <pb_decode_inner+0x366>
+                    continue;
+ 8024030:	bf00      	nop
+ 8024032:	e000      	b.n	8024036 <pb_decode_inner+0x252>
+            continue;
+ 8024034:	bf00      	nop
+    while (stream->bytes_left)
+ 8024036:	68fb      	ldr	r3, [r7, #12]
+ 8024038:	689b      	ldr	r3, [r3, #8]
+ 802403a:	2b00      	cmp	r3, #0
+ 802403c:	f47f af17 	bne.w	8023e6e <pb_decode_inner+0x8a>
+ 8024040:	e002      	b.n	8024048 <pb_decode_inner+0x264>
+                break;
+ 8024042:	bf00      	nop
+ 8024044:	e000      	b.n	8024048 <pb_decode_inner+0x264>
+            break;
+ 8024046:	bf00      	nop
+    }
+
+    /* Check that all elements of the last decoded fixed count field were present. */
+    if (fixed_count_field != PB_SIZE_MAX &&
+ 8024048:	f8b7 305e 	ldrh.w	r3, [r7, #94]	@ 0x5e
+ 802404c:	f64f 72ff 	movw	r2, #65535	@ 0xffff
+ 8024050:	4293      	cmp	r3, r2
+ 8024052:	d011      	beq.n	8024078 <pb_decode_inner+0x294>
+        fixed_count_size != fixed_count_total_size)
+ 8024054:	f8b7 304a 	ldrh.w	r3, [r7, #74]	@ 0x4a
+    if (fixed_count_field != PB_SIZE_MAX &&
+ 8024058:	f8b7 205c 	ldrh.w	r2, [r7, #92]	@ 0x5c
+ 802405c:	429a      	cmp	r2, r3
+ 802405e:	d00b      	beq.n	8024078 <pb_decode_inner+0x294>
+    {
+        PB_RETURN_ERROR(stream, "wrong size for fixed count field");
+ 8024060:	68fb      	ldr	r3, [r7, #12]
+ 8024062:	68db      	ldr	r3, [r3, #12]
+ 8024064:	2b00      	cmp	r3, #0
+ 8024066:	d002      	beq.n	802406e <pb_decode_inner+0x28a>
+ 8024068:	68fb      	ldr	r3, [r7, #12]
+ 802406a:	68db      	ldr	r3, [r3, #12]
+ 802406c:	e000      	b.n	8024070 <pb_decode_inner+0x28c>
+ 802406e:	4b19      	ldr	r3, [pc, #100]	@ (80240d4 <pb_decode_inner+0x2f0>)
+ 8024070:	68fa      	ldr	r2, [r7, #12]
+ 8024072:	60d3      	str	r3, [r2, #12]
+ 8024074:	2300      	movs	r3, #0
+ 8024076:	e068      	b.n	802414a <pb_decode_inner+0x366>
+    }
+
+    /* Check that all required fields were present. */
+    {
+        pb_size_t req_field_count = iter.descriptor->required_field_count;
+ 8024078:	69bb      	ldr	r3, [r7, #24]
+ 802407a:	8a5b      	ldrh	r3, [r3, #18]
+ 802407c:	f8a7 305a 	strh.w	r3, [r7, #90]	@ 0x5a
+
+        if (req_field_count > 0)
+ 8024080:	f8b7 305a 	ldrh.w	r3, [r7, #90]	@ 0x5a
+ 8024084:	2b00      	cmp	r3, #0
+ 8024086:	d05f      	beq.n	8024148 <pb_decode_inner+0x364>
+        {
+            pb_size_t i;
+
+            if (req_field_count > PB_MAX_REQUIRED_FIELDS)
+ 8024088:	f8b7 305a 	ldrh.w	r3, [r7, #90]	@ 0x5a
+ 802408c:	2b40      	cmp	r3, #64	@ 0x40
+ 802408e:	d902      	bls.n	8024096 <pb_decode_inner+0x2b2>
+                req_field_count = PB_MAX_REQUIRED_FIELDS;
+ 8024090:	2340      	movs	r3, #64	@ 0x40
+ 8024092:	f8a7 305a 	strh.w	r3, [r7, #90]	@ 0x5a
+
+            /* Check the whole words */
+            for (i = 0; i < (req_field_count >> 5); i++)
+ 8024096:	2300      	movs	r3, #0
+ 8024098:	f8a7 3058 	strh.w	r3, [r7, #88]	@ 0x58
+ 802409c:	e023      	b.n	80240e6 <pb_decode_inner+0x302>
+            {
+                if (fields_seen.bitfield[i] != allbits)
+ 802409e:	f8b7 3058 	ldrh.w	r3, [r7, #88]	@ 0x58
+ 80240a2:	009b      	lsls	r3, r3, #2
+ 80240a4:	3368      	adds	r3, #104	@ 0x68
+ 80240a6:	443b      	add	r3, r7
+ 80240a8:	f853 3c28 	ldr.w	r3, [r3, #-40]
+ 80240ac:	6d7a      	ldr	r2, [r7, #84]	@ 0x54
+ 80240ae:	429a      	cmp	r2, r3
+ 80240b0:	d014      	beq.n	80240dc <pb_decode_inner+0x2f8>
+                    PB_RETURN_ERROR(stream, "missing required field");
+ 80240b2:	68fb      	ldr	r3, [r7, #12]
+ 80240b4:	68db      	ldr	r3, [r3, #12]
+ 80240b6:	2b00      	cmp	r3, #0
+ 80240b8:	d002      	beq.n	80240c0 <pb_decode_inner+0x2dc>
+ 80240ba:	68fb      	ldr	r3, [r7, #12]
+ 80240bc:	68db      	ldr	r3, [r3, #12]
+ 80240be:	e000      	b.n	80240c2 <pb_decode_inner+0x2de>
+ 80240c0:	4b05      	ldr	r3, [pc, #20]	@ (80240d8 <pb_decode_inner+0x2f4>)
+ 80240c2:	68fa      	ldr	r2, [r7, #12]
+ 80240c4:	60d3      	str	r3, [r2, #12]
+ 80240c6:	2300      	movs	r3, #0
+ 80240c8:	e03f      	b.n	802414a <pb_decode_inner+0x366>
+ 80240ca:	bf00      	nop
+ 80240cc:	0804109c 	.word	0x0804109c
+ 80240d0:	080410ec 	.word	0x080410ec
+ 80240d4:	080410f8 	.word	0x080410f8
+ 80240d8:	0804111c 	.word	0x0804111c
+            for (i = 0; i < (req_field_count >> 5); i++)
+ 80240dc:	f8b7 3058 	ldrh.w	r3, [r7, #88]	@ 0x58
+ 80240e0:	3301      	adds	r3, #1
+ 80240e2:	f8a7 3058 	strh.w	r3, [r7, #88]	@ 0x58
+ 80240e6:	f8b7 305a 	ldrh.w	r3, [r7, #90]	@ 0x5a
+ 80240ea:	095b      	lsrs	r3, r3, #5
+ 80240ec:	b29b      	uxth	r3, r3
+ 80240ee:	f8b7 2058 	ldrh.w	r2, [r7, #88]	@ 0x58
+ 80240f2:	429a      	cmp	r2, r3
+ 80240f4:	d3d3      	bcc.n	802409e <pb_decode_inner+0x2ba>
+            }
+
+            /* Check the remaining bits (if any) */
+            if ((req_field_count & 31) != 0)
+ 80240f6:	f8b7 305a 	ldrh.w	r3, [r7, #90]	@ 0x5a
+ 80240fa:	f003 031f 	and.w	r3, r3, #31
+ 80240fe:	2b00      	cmp	r3, #0
+ 8024100:	d022      	beq.n	8024148 <pb_decode_inner+0x364>
+            {
+                if (fields_seen.bitfield[req_field_count >> 5] !=
+ 8024102:	f8b7 305a 	ldrh.w	r3, [r7, #90]	@ 0x5a
+ 8024106:	095b      	lsrs	r3, r3, #5
+ 8024108:	b29b      	uxth	r3, r3
+ 802410a:	009b      	lsls	r3, r3, #2
+ 802410c:	3368      	adds	r3, #104	@ 0x68
+ 802410e:	443b      	add	r3, r7
+ 8024110:	f853 2c28 	ldr.w	r2, [r3, #-40]
+                    (allbits >> (uint_least8_t)(32 - (req_field_count & 31))))
+ 8024114:	f8b7 305a 	ldrh.w	r3, [r7, #90]	@ 0x5a
+ 8024118:	b2db      	uxtb	r3, r3
+ 802411a:	f003 031f 	and.w	r3, r3, #31
+ 802411e:	b2db      	uxtb	r3, r3
+ 8024120:	f1c3 0320 	rsb	r3, r3, #32
+ 8024124:	b2db      	uxtb	r3, r3
+ 8024126:	4619      	mov	r1, r3
+ 8024128:	6d7b      	ldr	r3, [r7, #84]	@ 0x54
+ 802412a:	40cb      	lsrs	r3, r1
+                if (fields_seen.bitfield[req_field_count >> 5] !=
+ 802412c:	429a      	cmp	r2, r3
+ 802412e:	d00b      	beq.n	8024148 <pb_decode_inner+0x364>
+                {
+                    PB_RETURN_ERROR(stream, "missing required field");
+ 8024130:	68fb      	ldr	r3, [r7, #12]
+ 8024132:	68db      	ldr	r3, [r3, #12]
+ 8024134:	2b00      	cmp	r3, #0
+ 8024136:	d002      	beq.n	802413e <pb_decode_inner+0x35a>
+ 8024138:	68fb      	ldr	r3, [r7, #12]
+ 802413a:	68db      	ldr	r3, [r3, #12]
+ 802413c:	e000      	b.n	8024140 <pb_decode_inner+0x35c>
+ 802413e:	4b05      	ldr	r3, [pc, #20]	@ (8024154 <pb_decode_inner+0x370>)
+ 8024140:	68fa      	ldr	r2, [r7, #12]
+ 8024142:	60d3      	str	r3, [r2, #12]
+ 8024144:	2300      	movs	r3, #0
+ 8024146:	e000      	b.n	802414a <pb_decode_inner+0x366>
+                }
+            }
+        }
+    }
+
+    return true;
+ 8024148:	2301      	movs	r3, #1
+}
+ 802414a:	4618      	mov	r0, r3
+ 802414c:	3768      	adds	r7, #104	@ 0x68
+ 802414e:	46bd      	mov	sp, r7
+ 8024150:	bd80      	pop	{r7, pc}
+ 8024152:	bf00      	nop
+ 8024154:	0804111c 	.word	0x0804111c
+
+08024158 <pb_decode>:
+    
+    return status;
+}
+
+bool checkreturn pb_decode(pb_istream_t *stream, const pb_msgdesc_t *fields, void *dest_struct)
+{
+ 8024158:	b580      	push	{r7, lr}
+ 802415a:	b086      	sub	sp, #24
+ 802415c:	af00      	add	r7, sp, #0
+ 802415e:	60f8      	str	r0, [r7, #12]
+ 8024160:	60b9      	str	r1, [r7, #8]
+ 8024162:	607a      	str	r2, [r7, #4]
+    bool status;
+
+    status = pb_decode_inner(stream, fields, dest_struct, 0);
+ 8024164:	2300      	movs	r3, #0
+ 8024166:	687a      	ldr	r2, [r7, #4]
+ 8024168:	68b9      	ldr	r1, [r7, #8]
+ 802416a:	68f8      	ldr	r0, [r7, #12]
+ 802416c:	f7ff fe3a 	bl	8023de4 <pb_decode_inner>
+ 8024170:	4603      	mov	r3, r0
+ 8024172:	75fb      	strb	r3, [r7, #23]
+#ifdef PB_ENABLE_MALLOC
+    if (!status)
+        pb_release(fields, dest_struct);
+#endif
+
+    return status;
+ 8024174:	7dfb      	ldrb	r3, [r7, #23]
+}
+ 8024176:	4618      	mov	r0, r3
+ 8024178:	3718      	adds	r7, #24
+ 802417a:	46bd      	mov	sp, r7
+ 802417c:	bd80      	pop	{r7, pc}
+
+0802417e <pb_decode_bool>:
+#endif
+
+/* Field decoders */
+
+bool pb_decode_bool(pb_istream_t *stream, bool *dest)
+{
+ 802417e:	b580      	push	{r7, lr}
+ 8024180:	b084      	sub	sp, #16
+ 8024182:	af00      	add	r7, sp, #0
+ 8024184:	6078      	str	r0, [r7, #4]
+ 8024186:	6039      	str	r1, [r7, #0]
+    uint32_t value;
+    if (!pb_decode_varint32(stream, &value))
+ 8024188:	f107 030c 	add.w	r3, r7, #12
+ 802418c:	4619      	mov	r1, r3
+ 802418e:	6878      	ldr	r0, [r7, #4]
+ 8024190:	f7fe ff70 	bl	8023074 <pb_decode_varint32>
+ 8024194:	4603      	mov	r3, r0
+ 8024196:	f083 0301 	eor.w	r3, r3, #1
+ 802419a:	b2db      	uxtb	r3, r3
+ 802419c:	2b00      	cmp	r3, #0
+ 802419e:	d001      	beq.n	80241a4 <pb_decode_bool+0x26>
+        return false;
+ 80241a0:	2300      	movs	r3, #0
+ 80241a2:	e008      	b.n	80241b6 <pb_decode_bool+0x38>
+
+    *(bool*)dest = (value != 0);
+ 80241a4:	68fb      	ldr	r3, [r7, #12]
+ 80241a6:	2b00      	cmp	r3, #0
+ 80241a8:	bf14      	ite	ne
+ 80241aa:	2301      	movne	r3, #1
+ 80241ac:	2300      	moveq	r3, #0
+ 80241ae:	b2da      	uxtb	r2, r3
+ 80241b0:	683b      	ldr	r3, [r7, #0]
+ 80241b2:	701a      	strb	r2, [r3, #0]
+    return true;
+ 80241b4:	2301      	movs	r3, #1
+}
+ 80241b6:	4618      	mov	r0, r3
+ 80241b8:	3710      	adds	r7, #16
+ 80241ba:	46bd      	mov	sp, r7
+ 80241bc:	bd80      	pop	{r7, pc}
+
+080241be <pb_decode_svarint>:
+
+bool pb_decode_svarint(pb_istream_t *stream, pb_int64_t *dest)
+{
+ 80241be:	e92d 43b0 	stmdb	sp!, {r4, r5, r7, r8, r9, lr}
+ 80241c2:	b084      	sub	sp, #16
+ 80241c4:	af00      	add	r7, sp, #0
+ 80241c6:	6078      	str	r0, [r7, #4]
+ 80241c8:	6039      	str	r1, [r7, #0]
+    pb_uint64_t value;
+    if (!pb_decode_varint(stream, &value))
+ 80241ca:	f107 0308 	add.w	r3, r7, #8
+ 80241ce:	4619      	mov	r1, r3
+ 80241d0:	6878      	ldr	r0, [r7, #4]
+ 80241d2:	f7fe ff5f 	bl	8023094 <pb_decode_varint>
+ 80241d6:	4603      	mov	r3, r0
+ 80241d8:	f083 0301 	eor.w	r3, r3, #1
+ 80241dc:	b2db      	uxtb	r3, r3
+ 80241de:	2b00      	cmp	r3, #0
+ 80241e0:	d001      	beq.n	80241e6 <pb_decode_svarint+0x28>
+        return false;
+ 80241e2:	2300      	movs	r3, #0
+ 80241e4:	e029      	b.n	802423a <pb_decode_svarint+0x7c>
+    
+    if (value & 1)
+ 80241e6:	e9d7 2302 	ldrd	r2, r3, [r7, #8]
+ 80241ea:	f002 0401 	and.w	r4, r2, #1
+ 80241ee:	2500      	movs	r5, #0
+ 80241f0:	ea54 0305 	orrs.w	r3, r4, r5
+ 80241f4:	d013      	beq.n	802421e <pb_decode_svarint+0x60>
+        *dest = (pb_int64_t)(~(value >> 1));
+ 80241f6:	e9d7 0102 	ldrd	r0, r1, [r7, #8]
+ 80241fa:	f04f 0200 	mov.w	r2, #0
+ 80241fe:	f04f 0300 	mov.w	r3, #0
+ 8024202:	0842      	lsrs	r2, r0, #1
+ 8024204:	ea42 72c1 	orr.w	r2, r2, r1, lsl #31
+ 8024208:	084b      	lsrs	r3, r1, #1
+ 802420a:	ea6f 0802 	mvn.w	r8, r2
+ 802420e:	ea6f 0903 	mvn.w	r9, r3
+ 8024212:	4642      	mov	r2, r8
+ 8024214:	464b      	mov	r3, r9
+ 8024216:	6839      	ldr	r1, [r7, #0]
+ 8024218:	e9c1 2300 	strd	r2, r3, [r1]
+ 802421c:	e00c      	b.n	8024238 <pb_decode_svarint+0x7a>
+    else
+        *dest = (pb_int64_t)(value >> 1);
+ 802421e:	e9d7 0102 	ldrd	r0, r1, [r7, #8]
+ 8024222:	f04f 0200 	mov.w	r2, #0
+ 8024226:	f04f 0300 	mov.w	r3, #0
+ 802422a:	0842      	lsrs	r2, r0, #1
+ 802422c:	ea42 72c1 	orr.w	r2, r2, r1, lsl #31
+ 8024230:	084b      	lsrs	r3, r1, #1
+ 8024232:	6839      	ldr	r1, [r7, #0]
+ 8024234:	e9c1 2300 	strd	r2, r3, [r1]
+    
+    return true;
+ 8024238:	2301      	movs	r3, #1
+}
+ 802423a:	4618      	mov	r0, r3
+ 802423c:	3710      	adds	r7, #16
+ 802423e:	46bd      	mov	sp, r7
+ 8024240:	e8bd 83b0 	ldmia.w	sp!, {r4, r5, r7, r8, r9, pc}
+
+08024244 <pb_decode_fixed32>:
+
+bool pb_decode_fixed32(pb_istream_t *stream, void *dest)
+{
+ 8024244:	b580      	push	{r7, lr}
+ 8024246:	b084      	sub	sp, #16
+ 8024248:	af00      	add	r7, sp, #0
+ 802424a:	6078      	str	r0, [r7, #4]
+ 802424c:	6039      	str	r1, [r7, #0]
+    union {
+        uint32_t fixed32;
+        pb_byte_t bytes[4];
+    } u;
+
+    if (!pb_read(stream, u.bytes, 4))
+ 802424e:	f107 030c 	add.w	r3, r7, #12
+ 8024252:	2204      	movs	r2, #4
+ 8024254:	4619      	mov	r1, r3
+ 8024256:	6878      	ldr	r0, [r7, #4]
+ 8024258:	f7fe fd92 	bl	8022d80 <pb_read>
+ 802425c:	4603      	mov	r3, r0
+ 802425e:	f083 0301 	eor.w	r3, r3, #1
+ 8024262:	b2db      	uxtb	r3, r3
+ 8024264:	2b00      	cmp	r3, #0
+ 8024266:	d001      	beq.n	802426c <pb_decode_fixed32+0x28>
+        return false;
+ 8024268:	2300      	movs	r3, #0
+ 802426a:	e003      	b.n	8024274 <pb_decode_fixed32+0x30>
+
+#if defined(PB_LITTLE_ENDIAN_8BIT) && PB_LITTLE_ENDIAN_8BIT == 1
+    /* fast path - if we know that we're on little endian, assign directly */
+    *(uint32_t*)dest = u.fixed32;
+ 802426c:	68fa      	ldr	r2, [r7, #12]
+ 802426e:	683b      	ldr	r3, [r7, #0]
+ 8024270:	601a      	str	r2, [r3, #0]
+    *(uint32_t*)dest = ((uint32_t)u.bytes[0] << 0) |
+                       ((uint32_t)u.bytes[1] << 8) |
+                       ((uint32_t)u.bytes[2] << 16) |
+                       ((uint32_t)u.bytes[3] << 24);
+#endif
+    return true;
+ 8024272:	2301      	movs	r3, #1
+}
+ 8024274:	4618      	mov	r0, r3
+ 8024276:	3710      	adds	r7, #16
+ 8024278:	46bd      	mov	sp, r7
+ 802427a:	bd80      	pop	{r7, pc}
+
+0802427c <pb_decode_fixed64>:
+
+#ifndef PB_WITHOUT_64BIT
+bool pb_decode_fixed64(pb_istream_t *stream, void *dest)
+{
+ 802427c:	b580      	push	{r7, lr}
+ 802427e:	b084      	sub	sp, #16
+ 8024280:	af00      	add	r7, sp, #0
+ 8024282:	6078      	str	r0, [r7, #4]
+ 8024284:	6039      	str	r1, [r7, #0]
+    union {
+        uint64_t fixed64;
+        pb_byte_t bytes[8];
+    } u;
+
+    if (!pb_read(stream, u.bytes, 8))
+ 8024286:	f107 0308 	add.w	r3, r7, #8
+ 802428a:	2208      	movs	r2, #8
+ 802428c:	4619      	mov	r1, r3
+ 802428e:	6878      	ldr	r0, [r7, #4]
+ 8024290:	f7fe fd76 	bl	8022d80 <pb_read>
+ 8024294:	4603      	mov	r3, r0
+ 8024296:	f083 0301 	eor.w	r3, r3, #1
+ 802429a:	b2db      	uxtb	r3, r3
+ 802429c:	2b00      	cmp	r3, #0
+ 802429e:	d001      	beq.n	80242a4 <pb_decode_fixed64+0x28>
+        return false;
+ 80242a0:	2300      	movs	r3, #0
+ 80242a2:	e005      	b.n	80242b0 <pb_decode_fixed64+0x34>
+
+#if defined(PB_LITTLE_ENDIAN_8BIT) && PB_LITTLE_ENDIAN_8BIT == 1
+    /* fast path - if we know that we're on little endian, assign directly */
+    *(uint64_t*)dest = u.fixed64;
+ 80242a4:	e9d7 2302 	ldrd	r2, r3, [r7, #8]
+ 80242a8:	6839      	ldr	r1, [r7, #0]
+ 80242aa:	e9c1 2300 	strd	r2, r3, [r1]
+                       ((uint64_t)u.bytes[4] << 32) |
+                       ((uint64_t)u.bytes[5] << 40) |
+                       ((uint64_t)u.bytes[6] << 48) |
+                       ((uint64_t)u.bytes[7] << 56);
+#endif
+    return true;
+ 80242ae:	2301      	movs	r3, #1
+}
+ 80242b0:	4618      	mov	r0, r3
+ 80242b2:	3710      	adds	r7, #16
+ 80242b4:	46bd      	mov	sp, r7
+ 80242b6:	bd80      	pop	{r7, pc}
+
+080242b8 <pb_dec_bool>:
+#endif
+
+static bool checkreturn pb_dec_bool(pb_istream_t *stream, const pb_field_iter_t *field)
+{
+ 80242b8:	b580      	push	{r7, lr}
+ 80242ba:	b082      	sub	sp, #8
+ 80242bc:	af00      	add	r7, sp, #0
+ 80242be:	6078      	str	r0, [r7, #4]
+ 80242c0:	6039      	str	r1, [r7, #0]
+    return pb_decode_bool(stream, (bool*)field->pData);
+ 80242c2:	683b      	ldr	r3, [r7, #0]
+ 80242c4:	69db      	ldr	r3, [r3, #28]
+ 80242c6:	4619      	mov	r1, r3
+ 80242c8:	6878      	ldr	r0, [r7, #4]
+ 80242ca:	f7ff ff58 	bl	802417e <pb_decode_bool>
+ 80242ce:	4603      	mov	r3, r0
+}
+ 80242d0:	4618      	mov	r0, r3
+ 80242d2:	3708      	adds	r7, #8
+ 80242d4:	46bd      	mov	sp, r7
+ 80242d6:	bd80      	pop	{r7, pc}
+
+080242d8 <pb_dec_varint>:
+
+static bool checkreturn pb_dec_varint(pb_istream_t *stream, const pb_field_iter_t *field)
+{
+ 80242d8:	e92d 4fb0 	stmdb	sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
+ 80242dc:	b094      	sub	sp, #80	@ 0x50
+ 80242de:	af00      	add	r7, sp, #0
+ 80242e0:	6278      	str	r0, [r7, #36]	@ 0x24
+ 80242e2:	6239      	str	r1, [r7, #32]
+    if (PB_LTYPE(field->type) == PB_LTYPE_UVARINT)
+ 80242e4:	6a3b      	ldr	r3, [r7, #32]
+ 80242e6:	7d9b      	ldrb	r3, [r3, #22]
+ 80242e8:	f003 030f 	and.w	r3, r3, #15
+ 80242ec:	2b02      	cmp	r3, #2
+ 80242ee:	d179      	bne.n	80243e4 <pb_dec_varint+0x10c>
+    {
+        pb_uint64_t value, clamped;
+        if (!pb_decode_varint(stream, &value))
+ 80242f0:	f107 0338 	add.w	r3, r7, #56	@ 0x38
+ 80242f4:	4619      	mov	r1, r3
+ 80242f6:	6a78      	ldr	r0, [r7, #36]	@ 0x24
+ 80242f8:	f7fe fecc 	bl	8023094 <pb_decode_varint>
+ 80242fc:	4603      	mov	r3, r0
+ 80242fe:	f083 0301 	eor.w	r3, r3, #1
+ 8024302:	b2db      	uxtb	r3, r3
+ 8024304:	2b00      	cmp	r3, #0
+ 8024306:	d001      	beq.n	802430c <pb_dec_varint+0x34>
+            return false;
+ 8024308:	2300      	movs	r3, #0
+ 802430a:	e107      	b.n	802451c <pb_dec_varint+0x244>
+
+        /* Cast to the proper field size, while checking for overflows */
+        if (field->data_size == sizeof(pb_uint64_t))
+ 802430c:	6a3b      	ldr	r3, [r7, #32]
+ 802430e:	8a5b      	ldrh	r3, [r3, #18]
+ 8024310:	2b08      	cmp	r3, #8
+ 8024312:	d10a      	bne.n	802432a <pb_dec_varint+0x52>
+            clamped = *(pb_uint64_t*)field->pData = value;
+ 8024314:	6a3b      	ldr	r3, [r7, #32]
+ 8024316:	69d9      	ldr	r1, [r3, #28]
+ 8024318:	e9d7 230e 	ldrd	r2, r3, [r7, #56]	@ 0x38
+ 802431c:	e9c1 2300 	strd	r2, r3, [r1]
+ 8024320:	e9d1 2300 	ldrd	r2, r3, [r1]
+ 8024324:	e9c7 2312 	strd	r2, r3, [r7, #72]	@ 0x48
+ 8024328:	e046      	b.n	80243b8 <pb_dec_varint+0xe0>
+        else if (field->data_size == sizeof(uint32_t))
+ 802432a:	6a3b      	ldr	r3, [r7, #32]
+ 802432c:	8a5b      	ldrh	r3, [r3, #18]
+ 802432e:	2b04      	cmp	r3, #4
+ 8024330:	d10e      	bne.n	8024350 <pb_dec_varint+0x78>
+            clamped = *(uint32_t*)field->pData = (uint32_t)value;
+ 8024332:	e9d7 010e 	ldrd	r0, r1, [r7, #56]	@ 0x38
+ 8024336:	6a3b      	ldr	r3, [r7, #32]
+ 8024338:	69db      	ldr	r3, [r3, #28]
+ 802433a:	4602      	mov	r2, r0
+ 802433c:	601a      	str	r2, [r3, #0]
+ 802433e:	681b      	ldr	r3, [r3, #0]
+ 8024340:	2200      	movs	r2, #0
+ 8024342:	613b      	str	r3, [r7, #16]
+ 8024344:	617a      	str	r2, [r7, #20]
+ 8024346:	e9d7 3404 	ldrd	r3, r4, [r7, #16]
+ 802434a:	e9c7 3412 	strd	r3, r4, [r7, #72]	@ 0x48
+ 802434e:	e033      	b.n	80243b8 <pb_dec_varint+0xe0>
+        else if (field->data_size == sizeof(uint_least16_t))
+ 8024350:	6a3b      	ldr	r3, [r7, #32]
+ 8024352:	8a5b      	ldrh	r3, [r3, #18]
+ 8024354:	2b02      	cmp	r3, #2
+ 8024356:	d10f      	bne.n	8024378 <pb_dec_varint+0xa0>
+            clamped = *(uint_least16_t*)field->pData = (uint_least16_t)value;
+ 8024358:	e9d7 010e 	ldrd	r0, r1, [r7, #56]	@ 0x38
+ 802435c:	6a3b      	ldr	r3, [r7, #32]
+ 802435e:	69db      	ldr	r3, [r3, #28]
+ 8024360:	b282      	uxth	r2, r0
+ 8024362:	801a      	strh	r2, [r3, #0]
+ 8024364:	881b      	ldrh	r3, [r3, #0]
+ 8024366:	b29b      	uxth	r3, r3
+ 8024368:	2200      	movs	r2, #0
+ 802436a:	60bb      	str	r3, [r7, #8]
+ 802436c:	60fa      	str	r2, [r7, #12]
+ 802436e:	e9d7 3402 	ldrd	r3, r4, [r7, #8]
+ 8024372:	e9c7 3412 	strd	r3, r4, [r7, #72]	@ 0x48
+ 8024376:	e01f      	b.n	80243b8 <pb_dec_varint+0xe0>
+        else if (field->data_size == sizeof(uint_least8_t))
+ 8024378:	6a3b      	ldr	r3, [r7, #32]
+ 802437a:	8a5b      	ldrh	r3, [r3, #18]
+ 802437c:	2b01      	cmp	r3, #1
+ 802437e:	d10f      	bne.n	80243a0 <pb_dec_varint+0xc8>
+            clamped = *(uint_least8_t*)field->pData = (uint_least8_t)value;
+ 8024380:	e9d7 010e 	ldrd	r0, r1, [r7, #56]	@ 0x38
+ 8024384:	6a3b      	ldr	r3, [r7, #32]
+ 8024386:	69db      	ldr	r3, [r3, #28]
+ 8024388:	b2c2      	uxtb	r2, r0
+ 802438a:	701a      	strb	r2, [r3, #0]
+ 802438c:	781b      	ldrb	r3, [r3, #0]
+ 802438e:	b2db      	uxtb	r3, r3
+ 8024390:	2200      	movs	r2, #0
+ 8024392:	603b      	str	r3, [r7, #0]
+ 8024394:	607a      	str	r2, [r7, #4]
+ 8024396:	e9d7 3400 	ldrd	r3, r4, [r7]
+ 802439a:	e9c7 3412 	strd	r3, r4, [r7, #72]	@ 0x48
+ 802439e:	e00b      	b.n	80243b8 <pb_dec_varint+0xe0>
+        else
+            PB_RETURN_ERROR(stream, "invalid data_size");
+ 80243a0:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 80243a2:	68db      	ldr	r3, [r3, #12]
+ 80243a4:	2b00      	cmp	r3, #0
+ 80243a6:	d002      	beq.n	80243ae <pb_dec_varint+0xd6>
+ 80243a8:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 80243aa:	68db      	ldr	r3, [r3, #12]
+ 80243ac:	e000      	b.n	80243b0 <pb_dec_varint+0xd8>
+ 80243ae:	4b5e      	ldr	r3, [pc, #376]	@ (8024528 <pb_dec_varint+0x250>)
+ 80243b0:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
+ 80243b2:	60d3      	str	r3, [r2, #12]
+ 80243b4:	2300      	movs	r3, #0
+ 80243b6:	e0b1      	b.n	802451c <pb_dec_varint+0x244>
+
+        if (clamped != value)
+ 80243b8:	e9d7 230e 	ldrd	r2, r3, [r7, #56]	@ 0x38
+ 80243bc:	e9d7 0112 	ldrd	r0, r1, [r7, #72]	@ 0x48
+ 80243c0:	4299      	cmp	r1, r3
+ 80243c2:	bf08      	it	eq
+ 80243c4:	4290      	cmpeq	r0, r2
+ 80243c6:	d00b      	beq.n	80243e0 <pb_dec_varint+0x108>
+            PB_RETURN_ERROR(stream, "integer too large");
+ 80243c8:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 80243ca:	68db      	ldr	r3, [r3, #12]
+ 80243cc:	2b00      	cmp	r3, #0
+ 80243ce:	d002      	beq.n	80243d6 <pb_dec_varint+0xfe>
+ 80243d0:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 80243d2:	68db      	ldr	r3, [r3, #12]
+ 80243d4:	e000      	b.n	80243d8 <pb_dec_varint+0x100>
+ 80243d6:	4b55      	ldr	r3, [pc, #340]	@ (802452c <pb_dec_varint+0x254>)
+ 80243d8:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
+ 80243da:	60d3      	str	r3, [r2, #12]
+ 80243dc:	2300      	movs	r3, #0
+ 80243de:	e09d      	b.n	802451c <pb_dec_varint+0x244>
+
+        return true;
+ 80243e0:	2301      	movs	r3, #1
+ 80243e2:	e09b      	b.n	802451c <pb_dec_varint+0x244>
+    {
+        pb_uint64_t value;
+        pb_int64_t svalue;
+        pb_int64_t clamped;
+
+        if (PB_LTYPE(field->type) == PB_LTYPE_SVARINT)
+ 80243e4:	6a3b      	ldr	r3, [r7, #32]
+ 80243e6:	7d9b      	ldrb	r3, [r3, #22]
+ 80243e8:	f003 030f 	and.w	r3, r3, #15
+ 80243ec:	2b03      	cmp	r3, #3
+ 80243ee:	d10d      	bne.n	802440c <pb_dec_varint+0x134>
+        {
+            if (!pb_decode_svarint(stream, &svalue))
+ 80243f0:	f107 0328 	add.w	r3, r7, #40	@ 0x28
+ 80243f4:	4619      	mov	r1, r3
+ 80243f6:	6a78      	ldr	r0, [r7, #36]	@ 0x24
+ 80243f8:	f7ff fee1 	bl	80241be <pb_decode_svarint>
+ 80243fc:	4603      	mov	r3, r0
+ 80243fe:	f083 0301 	eor.w	r3, r3, #1
+ 8024402:	b2db      	uxtb	r3, r3
+ 8024404:	2b00      	cmp	r3, #0
+ 8024406:	d022      	beq.n	802444e <pb_dec_varint+0x176>
+                return false;
+ 8024408:	2300      	movs	r3, #0
+ 802440a:	e087      	b.n	802451c <pb_dec_varint+0x244>
+        }
+        else
+        {
+            if (!pb_decode_varint(stream, &value))
+ 802440c:	f107 0330 	add.w	r3, r7, #48	@ 0x30
+ 8024410:	4619      	mov	r1, r3
+ 8024412:	6a78      	ldr	r0, [r7, #36]	@ 0x24
+ 8024414:	f7fe fe3e 	bl	8023094 <pb_decode_varint>
+ 8024418:	4603      	mov	r3, r0
+ 802441a:	f083 0301 	eor.w	r3, r3, #1
+ 802441e:	b2db      	uxtb	r3, r3
+ 8024420:	2b00      	cmp	r3, #0
+ 8024422:	d001      	beq.n	8024428 <pb_dec_varint+0x150>
+                return false;
+ 8024424:	2300      	movs	r3, #0
+ 8024426:	e079      	b.n	802451c <pb_dec_varint+0x244>
+            * be cast as int32_t, instead of the int64_t that should be used when
+            * encoding. Nanopb versions before 0.2.5 had a bug in encoding. In order to
+            * not break decoding of such messages, we cast <=32 bit fields to
+            * int32_t first to get the sign correct.
+            */
+            if (field->data_size == sizeof(pb_int64_t))
+ 8024428:	6a3b      	ldr	r3, [r7, #32]
+ 802442a:	8a5b      	ldrh	r3, [r3, #18]
+ 802442c:	2b08      	cmp	r3, #8
+ 802442e:	d104      	bne.n	802443a <pb_dec_varint+0x162>
+                svalue = (pb_int64_t)value;
+ 8024430:	e9d7 230c 	ldrd	r2, r3, [r7, #48]	@ 0x30
+ 8024434:	e9c7 230a 	strd	r2, r3, [r7, #40]	@ 0x28
+ 8024438:	e009      	b.n	802444e <pb_dec_varint+0x176>
+            else
+                svalue = (int32_t)value;
+ 802443a:	e9d7 230c 	ldrd	r2, r3, [r7, #48]	@ 0x30
+ 802443e:	4613      	mov	r3, r2
+ 8024440:	17da      	asrs	r2, r3, #31
+ 8024442:	61bb      	str	r3, [r7, #24]
+ 8024444:	61fa      	str	r2, [r7, #28]
+ 8024446:	e9d7 2306 	ldrd	r2, r3, [r7, #24]
+ 802444a:	e9c7 230a 	strd	r2, r3, [r7, #40]	@ 0x28
+        }
+
+        /* Cast to the proper field size, while checking for overflows */
+        if (field->data_size == sizeof(pb_int64_t))
+ 802444e:	6a3b      	ldr	r3, [r7, #32]
+ 8024450:	8a5b      	ldrh	r3, [r3, #18]
+ 8024452:	2b08      	cmp	r3, #8
+ 8024454:	d10a      	bne.n	802446c <pb_dec_varint+0x194>
+            clamped = *(pb_int64_t*)field->pData = svalue;
+ 8024456:	6a3b      	ldr	r3, [r7, #32]
+ 8024458:	69d9      	ldr	r1, [r3, #28]
+ 802445a:	e9d7 230a 	ldrd	r2, r3, [r7, #40]	@ 0x28
+ 802445e:	e9c1 2300 	strd	r2, r3, [r1]
+ 8024462:	e9d1 2300 	ldrd	r2, r3, [r1]
+ 8024466:	e9c7 2310 	strd	r2, r3, [r7, #64]	@ 0x40
+ 802446a:	e042      	b.n	80244f2 <pb_dec_varint+0x21a>
+        else if (field->data_size == sizeof(int32_t))
+ 802446c:	6a3b      	ldr	r3, [r7, #32]
+ 802446e:	8a5b      	ldrh	r3, [r3, #18]
+ 8024470:	2b04      	cmp	r3, #4
+ 8024472:	d10c      	bne.n	802448e <pb_dec_varint+0x1b6>
+            clamped = *(int32_t*)field->pData = (int32_t)svalue;
+ 8024474:	e9d7 010a 	ldrd	r0, r1, [r7, #40]	@ 0x28
+ 8024478:	6a3b      	ldr	r3, [r7, #32]
+ 802447a:	69db      	ldr	r3, [r3, #28]
+ 802447c:	4602      	mov	r2, r0
+ 802447e:	601a      	str	r2, [r3, #0]
+ 8024480:	681b      	ldr	r3, [r3, #0]
+ 8024482:	17da      	asrs	r2, r3, #31
+ 8024484:	469a      	mov	sl, r3
+ 8024486:	4693      	mov	fp, r2
+ 8024488:	e9c7 ab10 	strd	sl, fp, [r7, #64]	@ 0x40
+ 802448c:	e031      	b.n	80244f2 <pb_dec_varint+0x21a>
+        else if (field->data_size == sizeof(int_least16_t))
+ 802448e:	6a3b      	ldr	r3, [r7, #32]
+ 8024490:	8a5b      	ldrh	r3, [r3, #18]
+ 8024492:	2b02      	cmp	r3, #2
+ 8024494:	d10e      	bne.n	80244b4 <pb_dec_varint+0x1dc>
+            clamped = *(int_least16_t*)field->pData = (int_least16_t)svalue;
+ 8024496:	e9d7 010a 	ldrd	r0, r1, [r7, #40]	@ 0x28
+ 802449a:	6a3b      	ldr	r3, [r7, #32]
+ 802449c:	69db      	ldr	r3, [r3, #28]
+ 802449e:	b202      	sxth	r2, r0
+ 80244a0:	801a      	strh	r2, [r3, #0]
+ 80244a2:	f9b3 3000 	ldrsh.w	r3, [r3]
+ 80244a6:	b21b      	sxth	r3, r3
+ 80244a8:	17da      	asrs	r2, r3, #31
+ 80244aa:	4698      	mov	r8, r3
+ 80244ac:	4691      	mov	r9, r2
+ 80244ae:	e9c7 8910 	strd	r8, r9, [r7, #64]	@ 0x40
+ 80244b2:	e01e      	b.n	80244f2 <pb_dec_varint+0x21a>
+        else if (field->data_size == sizeof(int_least8_t))
+ 80244b4:	6a3b      	ldr	r3, [r7, #32]
+ 80244b6:	8a5b      	ldrh	r3, [r3, #18]
+ 80244b8:	2b01      	cmp	r3, #1
+ 80244ba:	d10e      	bne.n	80244da <pb_dec_varint+0x202>
+            clamped = *(int_least8_t*)field->pData = (int_least8_t)svalue;
+ 80244bc:	e9d7 010a 	ldrd	r0, r1, [r7, #40]	@ 0x28
+ 80244c0:	6a3b      	ldr	r3, [r7, #32]
+ 80244c2:	69db      	ldr	r3, [r3, #28]
+ 80244c4:	b242      	sxtb	r2, r0
+ 80244c6:	701a      	strb	r2, [r3, #0]
+ 80244c8:	f993 3000 	ldrsb.w	r3, [r3]
+ 80244cc:	b25b      	sxtb	r3, r3
+ 80244ce:	17da      	asrs	r2, r3, #31
+ 80244d0:	461c      	mov	r4, r3
+ 80244d2:	4615      	mov	r5, r2
+ 80244d4:	e9c7 4510 	strd	r4, r5, [r7, #64]	@ 0x40
+ 80244d8:	e00b      	b.n	80244f2 <pb_dec_varint+0x21a>
+        else
+            PB_RETURN_ERROR(stream, "invalid data_size");
+ 80244da:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 80244dc:	68db      	ldr	r3, [r3, #12]
+ 80244de:	2b00      	cmp	r3, #0
+ 80244e0:	d002      	beq.n	80244e8 <pb_dec_varint+0x210>
+ 80244e2:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 80244e4:	68db      	ldr	r3, [r3, #12]
+ 80244e6:	e000      	b.n	80244ea <pb_dec_varint+0x212>
+ 80244e8:	4b0f      	ldr	r3, [pc, #60]	@ (8024528 <pb_dec_varint+0x250>)
+ 80244ea:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
+ 80244ec:	60d3      	str	r3, [r2, #12]
+ 80244ee:	2300      	movs	r3, #0
+ 80244f0:	e014      	b.n	802451c <pb_dec_varint+0x244>
+
+        if (clamped != svalue)
+ 80244f2:	e9d7 230a 	ldrd	r2, r3, [r7, #40]	@ 0x28
+ 80244f6:	e9d7 0110 	ldrd	r0, r1, [r7, #64]	@ 0x40
+ 80244fa:	4299      	cmp	r1, r3
+ 80244fc:	bf08      	it	eq
+ 80244fe:	4290      	cmpeq	r0, r2
+ 8024500:	d00b      	beq.n	802451a <pb_dec_varint+0x242>
+            PB_RETURN_ERROR(stream, "integer too large");
+ 8024502:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 8024504:	68db      	ldr	r3, [r3, #12]
+ 8024506:	2b00      	cmp	r3, #0
+ 8024508:	d002      	beq.n	8024510 <pb_dec_varint+0x238>
+ 802450a:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 802450c:	68db      	ldr	r3, [r3, #12]
+ 802450e:	e000      	b.n	8024512 <pb_dec_varint+0x23a>
+ 8024510:	4b06      	ldr	r3, [pc, #24]	@ (802452c <pb_dec_varint+0x254>)
+ 8024512:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
+ 8024514:	60d3      	str	r3, [r2, #12]
+ 8024516:	2300      	movs	r3, #0
+ 8024518:	e000      	b.n	802451c <pb_dec_varint+0x244>
+
+        return true;
+ 802451a:	2301      	movs	r3, #1
+    }
+}
+ 802451c:	4618      	mov	r0, r3
+ 802451e:	3750      	adds	r7, #80	@ 0x50
+ 8024520:	46bd      	mov	sp, r7
+ 8024522:	e8bd 8fb0 	ldmia.w	sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
+ 8024526:	bf00      	nop
+ 8024528:	08041134 	.word	0x08041134
+ 802452c:	08041148 	.word	0x08041148
+
+08024530 <pb_dec_bytes>:
+
+static bool checkreturn pb_dec_bytes(pb_istream_t *stream, const pb_field_iter_t *field)
+{
+ 8024530:	b580      	push	{r7, lr}
+ 8024532:	b086      	sub	sp, #24
+ 8024534:	af00      	add	r7, sp, #0
+ 8024536:	6078      	str	r0, [r7, #4]
+ 8024538:	6039      	str	r1, [r7, #0]
+    uint32_t size;
+    size_t alloc_size;
+    pb_bytes_array_t *dest;
+    
+    if (!pb_decode_varint32(stream, &size))
+ 802453a:	f107 030c 	add.w	r3, r7, #12
+ 802453e:	4619      	mov	r1, r3
+ 8024540:	6878      	ldr	r0, [r7, #4]
+ 8024542:	f7fe fd97 	bl	8023074 <pb_decode_varint32>
+ 8024546:	4603      	mov	r3, r0
+ 8024548:	f083 0301 	eor.w	r3, r3, #1
+ 802454c:	b2db      	uxtb	r3, r3
+ 802454e:	2b00      	cmp	r3, #0
+ 8024550:	d001      	beq.n	8024556 <pb_dec_bytes+0x26>
+        return false;
+ 8024552:	2300      	movs	r3, #0
+ 8024554:	e055      	b.n	8024602 <pb_dec_bytes+0xd2>
+    
+    if (size > PB_SIZE_MAX)
+ 8024556:	68fb      	ldr	r3, [r7, #12]
+ 8024558:	f5b3 3f80 	cmp.w	r3, #65536	@ 0x10000
+ 802455c:	d30b      	bcc.n	8024576 <pb_dec_bytes+0x46>
+        PB_RETURN_ERROR(stream, "bytes overflow");
+ 802455e:	687b      	ldr	r3, [r7, #4]
+ 8024560:	68db      	ldr	r3, [r3, #12]
+ 8024562:	2b00      	cmp	r3, #0
+ 8024564:	d002      	beq.n	802456c <pb_dec_bytes+0x3c>
+ 8024566:	687b      	ldr	r3, [r7, #4]
+ 8024568:	68db      	ldr	r3, [r3, #12]
+ 802456a:	e000      	b.n	802456e <pb_dec_bytes+0x3e>
+ 802456c:	4b27      	ldr	r3, [pc, #156]	@ (802460c <pb_dec_bytes+0xdc>)
+ 802456e:	687a      	ldr	r2, [r7, #4]
+ 8024570:	60d3      	str	r3, [r2, #12]
+ 8024572:	2300      	movs	r3, #0
+ 8024574:	e045      	b.n	8024602 <pb_dec_bytes+0xd2>
+    
+    alloc_size = PB_BYTES_ARRAY_T_ALLOCSIZE(size);
+ 8024576:	68fb      	ldr	r3, [r7, #12]
+ 8024578:	3302      	adds	r3, #2
+ 802457a:	617b      	str	r3, [r7, #20]
+    if (size > alloc_size)
+ 802457c:	68fb      	ldr	r3, [r7, #12]
+ 802457e:	697a      	ldr	r2, [r7, #20]
+ 8024580:	429a      	cmp	r2, r3
+ 8024582:	d20b      	bcs.n	802459c <pb_dec_bytes+0x6c>
+        PB_RETURN_ERROR(stream, "size too large");
+ 8024584:	687b      	ldr	r3, [r7, #4]
+ 8024586:	68db      	ldr	r3, [r3, #12]
+ 8024588:	2b00      	cmp	r3, #0
+ 802458a:	d002      	beq.n	8024592 <pb_dec_bytes+0x62>
+ 802458c:	687b      	ldr	r3, [r7, #4]
+ 802458e:	68db      	ldr	r3, [r3, #12]
+ 8024590:	e000      	b.n	8024594 <pb_dec_bytes+0x64>
+ 8024592:	4b1f      	ldr	r3, [pc, #124]	@ (8024610 <pb_dec_bytes+0xe0>)
+ 8024594:	687a      	ldr	r2, [r7, #4]
+ 8024596:	60d3      	str	r3, [r2, #12]
+ 8024598:	2300      	movs	r3, #0
+ 802459a:	e032      	b.n	8024602 <pb_dec_bytes+0xd2>
+    
+    if (PB_ATYPE(field->type) == PB_ATYPE_POINTER)
+ 802459c:	683b      	ldr	r3, [r7, #0]
+ 802459e:	7d9b      	ldrb	r3, [r3, #22]
+ 80245a0:	f003 03c0 	and.w	r3, r3, #192	@ 0xc0
+ 80245a4:	2b80      	cmp	r3, #128	@ 0x80
+ 80245a6:	d10b      	bne.n	80245c0 <pb_dec_bytes+0x90>
+    {
+#ifndef PB_ENABLE_MALLOC
+        PB_RETURN_ERROR(stream, "no malloc support");
+ 80245a8:	687b      	ldr	r3, [r7, #4]
+ 80245aa:	68db      	ldr	r3, [r3, #12]
+ 80245ac:	2b00      	cmp	r3, #0
+ 80245ae:	d002      	beq.n	80245b6 <pb_dec_bytes+0x86>
+ 80245b0:	687b      	ldr	r3, [r7, #4]
+ 80245b2:	68db      	ldr	r3, [r3, #12]
+ 80245b4:	e000      	b.n	80245b8 <pb_dec_bytes+0x88>
+ 80245b6:	4b17      	ldr	r3, [pc, #92]	@ (8024614 <pb_dec_bytes+0xe4>)
+ 80245b8:	687a      	ldr	r2, [r7, #4]
+ 80245ba:	60d3      	str	r3, [r2, #12]
+ 80245bc:	2300      	movs	r3, #0
+ 80245be:	e020      	b.n	8024602 <pb_dec_bytes+0xd2>
+        dest = *(pb_bytes_array_t**)field->pData;
+#endif
+    }
+    else
+    {
+        if (alloc_size > field->data_size)
+ 80245c0:	683b      	ldr	r3, [r7, #0]
+ 80245c2:	8a5b      	ldrh	r3, [r3, #18]
+ 80245c4:	461a      	mov	r2, r3
+ 80245c6:	697b      	ldr	r3, [r7, #20]
+ 80245c8:	4293      	cmp	r3, r2
+ 80245ca:	d90b      	bls.n	80245e4 <pb_dec_bytes+0xb4>
+            PB_RETURN_ERROR(stream, "bytes overflow");
+ 80245cc:	687b      	ldr	r3, [r7, #4]
+ 80245ce:	68db      	ldr	r3, [r3, #12]
+ 80245d0:	2b00      	cmp	r3, #0
+ 80245d2:	d002      	beq.n	80245da <pb_dec_bytes+0xaa>
+ 80245d4:	687b      	ldr	r3, [r7, #4]
+ 80245d6:	68db      	ldr	r3, [r3, #12]
+ 80245d8:	e000      	b.n	80245dc <pb_dec_bytes+0xac>
+ 80245da:	4b0c      	ldr	r3, [pc, #48]	@ (802460c <pb_dec_bytes+0xdc>)
+ 80245dc:	687a      	ldr	r2, [r7, #4]
+ 80245de:	60d3      	str	r3, [r2, #12]
+ 80245e0:	2300      	movs	r3, #0
+ 80245e2:	e00e      	b.n	8024602 <pb_dec_bytes+0xd2>
+        dest = (pb_bytes_array_t*)field->pData;
+ 80245e4:	683b      	ldr	r3, [r7, #0]
+ 80245e6:	69db      	ldr	r3, [r3, #28]
+ 80245e8:	613b      	str	r3, [r7, #16]
+    }
+
+    dest->size = (pb_size_t)size;
+ 80245ea:	68fb      	ldr	r3, [r7, #12]
+ 80245ec:	b29a      	uxth	r2, r3
+ 80245ee:	693b      	ldr	r3, [r7, #16]
+ 80245f0:	801a      	strh	r2, [r3, #0]
+    return pb_read(stream, dest->bytes, (size_t)size);
+ 80245f2:	693b      	ldr	r3, [r7, #16]
+ 80245f4:	3302      	adds	r3, #2
+ 80245f6:	68fa      	ldr	r2, [r7, #12]
+ 80245f8:	4619      	mov	r1, r3
+ 80245fa:	6878      	ldr	r0, [r7, #4]
+ 80245fc:	f7fe fbc0 	bl	8022d80 <pb_read>
+ 8024600:	4603      	mov	r3, r0
+}
+ 8024602:	4618      	mov	r0, r3
+ 8024604:	3718      	adds	r7, #24
+ 8024606:	46bd      	mov	sp, r7
+ 8024608:	bd80      	pop	{r7, pc}
+ 802460a:	bf00      	nop
+ 802460c:	0804115c 	.word	0x0804115c
+ 8024610:	0804116c 	.word	0x0804116c
+ 8024614:	080410b4 	.word	0x080410b4
+
+08024618 <pb_dec_string>:
+
+static bool checkreturn pb_dec_string(pb_istream_t *stream, const pb_field_iter_t *field)
+{
+ 8024618:	b580      	push	{r7, lr}
+ 802461a:	b086      	sub	sp, #24
+ 802461c:	af00      	add	r7, sp, #0
+ 802461e:	6078      	str	r0, [r7, #4]
+ 8024620:	6039      	str	r1, [r7, #0]
+    uint32_t size;
+    size_t alloc_size;
+    pb_byte_t *dest = (pb_byte_t*)field->pData;
+ 8024622:	683b      	ldr	r3, [r7, #0]
+ 8024624:	69db      	ldr	r3, [r3, #28]
+ 8024626:	617b      	str	r3, [r7, #20]
+
+    if (!pb_decode_varint32(stream, &size))
+ 8024628:	f107 030c 	add.w	r3, r7, #12
+ 802462c:	4619      	mov	r1, r3
+ 802462e:	6878      	ldr	r0, [r7, #4]
+ 8024630:	f7fe fd20 	bl	8023074 <pb_decode_varint32>
+ 8024634:	4603      	mov	r3, r0
+ 8024636:	f083 0301 	eor.w	r3, r3, #1
+ 802463a:	b2db      	uxtb	r3, r3
+ 802463c:	2b00      	cmp	r3, #0
+ 802463e:	d001      	beq.n	8024644 <pb_dec_string+0x2c>
+        return false;
+ 8024640:	2300      	movs	r3, #0
+ 8024642:	e05a      	b.n	80246fa <pb_dec_string+0xe2>
+
+    if (size == (uint32_t)-1)
+ 8024644:	68fb      	ldr	r3, [r7, #12]
+ 8024646:	f1b3 3fff 	cmp.w	r3, #4294967295
+ 802464a:	d10b      	bne.n	8024664 <pb_dec_string+0x4c>
+        PB_RETURN_ERROR(stream, "size too large");
+ 802464c:	687b      	ldr	r3, [r7, #4]
+ 802464e:	68db      	ldr	r3, [r3, #12]
+ 8024650:	2b00      	cmp	r3, #0
+ 8024652:	d002      	beq.n	802465a <pb_dec_string+0x42>
+ 8024654:	687b      	ldr	r3, [r7, #4]
+ 8024656:	68db      	ldr	r3, [r3, #12]
+ 8024658:	e000      	b.n	802465c <pb_dec_string+0x44>
+ 802465a:	4b2a      	ldr	r3, [pc, #168]	@ (8024704 <pb_dec_string+0xec>)
+ 802465c:	687a      	ldr	r2, [r7, #4]
+ 802465e:	60d3      	str	r3, [r2, #12]
+ 8024660:	2300      	movs	r3, #0
+ 8024662:	e04a      	b.n	80246fa <pb_dec_string+0xe2>
+
+    /* Space for null terminator */
+    alloc_size = (size_t)(size + 1);
+ 8024664:	68fb      	ldr	r3, [r7, #12]
+ 8024666:	3301      	adds	r3, #1
+ 8024668:	613b      	str	r3, [r7, #16]
+
+    if (alloc_size < size)
+ 802466a:	68fb      	ldr	r3, [r7, #12]
+ 802466c:	693a      	ldr	r2, [r7, #16]
+ 802466e:	429a      	cmp	r2, r3
+ 8024670:	d20b      	bcs.n	802468a <pb_dec_string+0x72>
+        PB_RETURN_ERROR(stream, "size too large");
+ 8024672:	687b      	ldr	r3, [r7, #4]
+ 8024674:	68db      	ldr	r3, [r3, #12]
+ 8024676:	2b00      	cmp	r3, #0
+ 8024678:	d002      	beq.n	8024680 <pb_dec_string+0x68>
+ 802467a:	687b      	ldr	r3, [r7, #4]
+ 802467c:	68db      	ldr	r3, [r3, #12]
+ 802467e:	e000      	b.n	8024682 <pb_dec_string+0x6a>
+ 8024680:	4b20      	ldr	r3, [pc, #128]	@ (8024704 <pb_dec_string+0xec>)
+ 8024682:	687a      	ldr	r2, [r7, #4]
+ 8024684:	60d3      	str	r3, [r2, #12]
+ 8024686:	2300      	movs	r3, #0
+ 8024688:	e037      	b.n	80246fa <pb_dec_string+0xe2>
+
+    if (PB_ATYPE(field->type) == PB_ATYPE_POINTER)
+ 802468a:	683b      	ldr	r3, [r7, #0]
+ 802468c:	7d9b      	ldrb	r3, [r3, #22]
+ 802468e:	f003 03c0 	and.w	r3, r3, #192	@ 0xc0
+ 8024692:	2b80      	cmp	r3, #128	@ 0x80
+ 8024694:	d10b      	bne.n	80246ae <pb_dec_string+0x96>
+    {
+#ifndef PB_ENABLE_MALLOC
+        PB_RETURN_ERROR(stream, "no malloc support");
+ 8024696:	687b      	ldr	r3, [r7, #4]
+ 8024698:	68db      	ldr	r3, [r3, #12]
+ 802469a:	2b00      	cmp	r3, #0
+ 802469c:	d002      	beq.n	80246a4 <pb_dec_string+0x8c>
+ 802469e:	687b      	ldr	r3, [r7, #4]
+ 80246a0:	68db      	ldr	r3, [r3, #12]
+ 80246a2:	e000      	b.n	80246a6 <pb_dec_string+0x8e>
+ 80246a4:	4b18      	ldr	r3, [pc, #96]	@ (8024708 <pb_dec_string+0xf0>)
+ 80246a6:	687a      	ldr	r2, [r7, #4]
+ 80246a8:	60d3      	str	r3, [r2, #12]
+ 80246aa:	2300      	movs	r3, #0
+ 80246ac:	e025      	b.n	80246fa <pb_dec_string+0xe2>
+        dest = *(pb_byte_t**)field->pData;
+#endif
+    }
+    else
+    {
+        if (alloc_size > field->data_size)
+ 80246ae:	683b      	ldr	r3, [r7, #0]
+ 80246b0:	8a5b      	ldrh	r3, [r3, #18]
+ 80246b2:	461a      	mov	r2, r3
+ 80246b4:	693b      	ldr	r3, [r7, #16]
+ 80246b6:	4293      	cmp	r3, r2
+ 80246b8:	d90b      	bls.n	80246d2 <pb_dec_string+0xba>
+            PB_RETURN_ERROR(stream, "string overflow");
+ 80246ba:	687b      	ldr	r3, [r7, #4]
+ 80246bc:	68db      	ldr	r3, [r3, #12]
+ 80246be:	2b00      	cmp	r3, #0
+ 80246c0:	d002      	beq.n	80246c8 <pb_dec_string+0xb0>
+ 80246c2:	687b      	ldr	r3, [r7, #4]
+ 80246c4:	68db      	ldr	r3, [r3, #12]
+ 80246c6:	e000      	b.n	80246ca <pb_dec_string+0xb2>
+ 80246c8:	4b10      	ldr	r3, [pc, #64]	@ (802470c <pb_dec_string+0xf4>)
+ 80246ca:	687a      	ldr	r2, [r7, #4]
+ 80246cc:	60d3      	str	r3, [r2, #12]
+ 80246ce:	2300      	movs	r3, #0
+ 80246d0:	e013      	b.n	80246fa <pb_dec_string+0xe2>
+    }
+    
+    dest[size] = 0;
+ 80246d2:	68fb      	ldr	r3, [r7, #12]
+ 80246d4:	697a      	ldr	r2, [r7, #20]
+ 80246d6:	4413      	add	r3, r2
+ 80246d8:	2200      	movs	r2, #0
+ 80246da:	701a      	strb	r2, [r3, #0]
+
+    if (!pb_read(stream, dest, (size_t)size))
+ 80246dc:	68fb      	ldr	r3, [r7, #12]
+ 80246de:	461a      	mov	r2, r3
+ 80246e0:	6979      	ldr	r1, [r7, #20]
+ 80246e2:	6878      	ldr	r0, [r7, #4]
+ 80246e4:	f7fe fb4c 	bl	8022d80 <pb_read>
+ 80246e8:	4603      	mov	r3, r0
+ 80246ea:	f083 0301 	eor.w	r3, r3, #1
+ 80246ee:	b2db      	uxtb	r3, r3
+ 80246f0:	2b00      	cmp	r3, #0
+ 80246f2:	d001      	beq.n	80246f8 <pb_dec_string+0xe0>
+        return false;
+ 80246f4:	2300      	movs	r3, #0
+ 80246f6:	e000      	b.n	80246fa <pb_dec_string+0xe2>
+#ifdef PB_VALIDATE_UTF8
+    if (!pb_validate_utf8((const char*)dest))
+        PB_RETURN_ERROR(stream, "invalid utf8");
+#endif
+
+    return true;
+ 80246f8:	2301      	movs	r3, #1
+}
+ 80246fa:	4618      	mov	r0, r3
+ 80246fc:	3718      	adds	r7, #24
+ 80246fe:	46bd      	mov	sp, r7
+ 8024700:	bd80      	pop	{r7, pc}
+ 8024702:	bf00      	nop
+ 8024704:	0804116c 	.word	0x0804116c
+ 8024708:	080410b4 	.word	0x080410b4
+ 802470c:	0804117c 	.word	0x0804117c
+
+08024710 <pb_dec_submessage>:
+
+static bool checkreturn pb_dec_submessage(pb_istream_t *stream, const pb_field_iter_t *field)
+{
+ 8024710:	b580      	push	{r7, lr}
+ 8024712:	b08a      	sub	sp, #40	@ 0x28
+ 8024714:	af00      	add	r7, sp, #0
+ 8024716:	6078      	str	r0, [r7, #4]
+ 8024718:	6039      	str	r1, [r7, #0]
+    bool status = true;
+ 802471a:	2301      	movs	r3, #1
+ 802471c:	f887 3027 	strb.w	r3, [r7, #39]	@ 0x27
+    bool submsg_consumed = false;
+ 8024720:	2300      	movs	r3, #0
+ 8024722:	f887 3026 	strb.w	r3, [r7, #38]	@ 0x26
+    pb_istream_t substream;
+
+    if (!pb_make_string_substream(stream, &substream))
+ 8024726:	f107 030c 	add.w	r3, r7, #12
+ 802472a:	4619      	mov	r1, r3
+ 802472c:	6878      	ldr	r0, [r7, #4]
+ 802472e:	f7fe fe2d 	bl	802338c <pb_make_string_substream>
+ 8024732:	4603      	mov	r3, r0
+ 8024734:	f083 0301 	eor.w	r3, r3, #1
+ 8024738:	b2db      	uxtb	r3, r3
+ 802473a:	2b00      	cmp	r3, #0
+ 802473c:	d001      	beq.n	8024742 <pb_dec_submessage+0x32>
+        return false;
+ 802473e:	2300      	movs	r3, #0
+ 8024740:	e069      	b.n	8024816 <pb_dec_submessage+0x106>
+    
+    if (field->submsg_desc == NULL)
+ 8024742:	683b      	ldr	r3, [r7, #0]
+ 8024744:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 8024746:	2b00      	cmp	r3, #0
+ 8024748:	d10b      	bne.n	8024762 <pb_dec_submessage+0x52>
+        PB_RETURN_ERROR(stream, "invalid field descriptor");
+ 802474a:	687b      	ldr	r3, [r7, #4]
+ 802474c:	68db      	ldr	r3, [r3, #12]
+ 802474e:	2b00      	cmp	r3, #0
+ 8024750:	d002      	beq.n	8024758 <pb_dec_submessage+0x48>
+ 8024752:	687b      	ldr	r3, [r7, #4]
+ 8024754:	68db      	ldr	r3, [r3, #12]
+ 8024756:	e000      	b.n	802475a <pb_dec_submessage+0x4a>
+ 8024758:	4b31      	ldr	r3, [pc, #196]	@ (8024820 <pb_dec_submessage+0x110>)
+ 802475a:	687a      	ldr	r2, [r7, #4]
+ 802475c:	60d3      	str	r3, [r2, #12]
+ 802475e:	2300      	movs	r3, #0
+ 8024760:	e059      	b.n	8024816 <pb_dec_submessage+0x106>
+    
+    /* Submessages can have a separate message-level callback that is called
+     * before decoding the message. Typically it is used to set callback fields
+     * inside oneofs. */
+    if (PB_LTYPE(field->type) == PB_LTYPE_SUBMSG_W_CB && field->pSize != NULL)
+ 8024762:	683b      	ldr	r3, [r7, #0]
+ 8024764:	7d9b      	ldrb	r3, [r3, #22]
+ 8024766:	f003 030f 	and.w	r3, r3, #15
+ 802476a:	2b09      	cmp	r3, #9
+ 802476c:	d11c      	bne.n	80247a8 <pb_dec_submessage+0x98>
+ 802476e:	683b      	ldr	r3, [r7, #0]
+ 8024770:	6a1b      	ldr	r3, [r3, #32]
+ 8024772:	2b00      	cmp	r3, #0
+ 8024774:	d018      	beq.n	80247a8 <pb_dec_submessage+0x98>
+    {
+        /* Message callback is stored right before pSize. */
+        pb_callback_t *callback = (pb_callback_t*)field->pSize - 1;
+ 8024776:	683b      	ldr	r3, [r7, #0]
+ 8024778:	6a1b      	ldr	r3, [r3, #32]
+ 802477a:	3b08      	subs	r3, #8
+ 802477c:	61fb      	str	r3, [r7, #28]
+        if (callback->funcs.decode)
+ 802477e:	69fb      	ldr	r3, [r7, #28]
+ 8024780:	681b      	ldr	r3, [r3, #0]
+ 8024782:	2b00      	cmp	r3, #0
+ 8024784:	d010      	beq.n	80247a8 <pb_dec_submessage+0x98>
+        {
+            status = callback->funcs.decode(&substream, field, &callback->arg);
+ 8024786:	69fb      	ldr	r3, [r7, #28]
+ 8024788:	681b      	ldr	r3, [r3, #0]
+ 802478a:	69fa      	ldr	r2, [r7, #28]
+ 802478c:	3204      	adds	r2, #4
+ 802478e:	f107 000c 	add.w	r0, r7, #12
+ 8024792:	6839      	ldr	r1, [r7, #0]
+ 8024794:	4798      	blx	r3
+ 8024796:	4603      	mov	r3, r0
+ 8024798:	f887 3027 	strb.w	r3, [r7, #39]	@ 0x27
+
+            if (substream.bytes_left == 0)
+ 802479c:	697b      	ldr	r3, [r7, #20]
+ 802479e:	2b00      	cmp	r3, #0
+ 80247a0:	d102      	bne.n	80247a8 <pb_dec_submessage+0x98>
+            {
+                submsg_consumed = true;
+ 80247a2:	2301      	movs	r3, #1
+ 80247a4:	f887 3026 	strb.w	r3, [r7, #38]	@ 0x26
+            }
+        }
+    }
+
+    /* Now decode the submessage contents */
+    if (status && !submsg_consumed)
+ 80247a8:	f897 3027 	ldrb.w	r3, [r7, #39]	@ 0x27
+ 80247ac:	2b00      	cmp	r3, #0
+ 80247ae:	d022      	beq.n	80247f6 <pb_dec_submessage+0xe6>
+ 80247b0:	f897 3026 	ldrb.w	r3, [r7, #38]	@ 0x26
+ 80247b4:	f083 0301 	eor.w	r3, r3, #1
+ 80247b8:	b2db      	uxtb	r3, r3
+ 80247ba:	2b00      	cmp	r3, #0
+ 80247bc:	d01b      	beq.n	80247f6 <pb_dec_submessage+0xe6>
+    {
+        unsigned int flags = 0;
+ 80247be:	2300      	movs	r3, #0
+ 80247c0:	623b      	str	r3, [r7, #32]
+
+        /* Static required/optional fields are already initialized by top-level
+         * pb_decode(), no need to initialize them again. */
+        if (PB_ATYPE(field->type) == PB_ATYPE_STATIC &&
+ 80247c2:	683b      	ldr	r3, [r7, #0]
+ 80247c4:	7d9b      	ldrb	r3, [r3, #22]
+ 80247c6:	f003 03c0 	and.w	r3, r3, #192	@ 0xc0
+ 80247ca:	2b00      	cmp	r3, #0
+ 80247cc:	d107      	bne.n	80247de <pb_dec_submessage+0xce>
+            PB_HTYPE(field->type) != PB_HTYPE_REPEATED)
+ 80247ce:	683b      	ldr	r3, [r7, #0]
+ 80247d0:	7d9b      	ldrb	r3, [r3, #22]
+ 80247d2:	f003 0330 	and.w	r3, r3, #48	@ 0x30
+        if (PB_ATYPE(field->type) == PB_ATYPE_STATIC &&
+ 80247d6:	2b20      	cmp	r3, #32
+ 80247d8:	d001      	beq.n	80247de <pb_dec_submessage+0xce>
+        {
+            flags = PB_DECODE_NOINIT;
+ 80247da:	2301      	movs	r3, #1
+ 80247dc:	623b      	str	r3, [r7, #32]
+        }
+
+        status = pb_decode_inner(&substream, field->submsg_desc, field->pData, flags);
+ 80247de:	683b      	ldr	r3, [r7, #0]
+ 80247e0:	6a59      	ldr	r1, [r3, #36]	@ 0x24
+ 80247e2:	683b      	ldr	r3, [r7, #0]
+ 80247e4:	69da      	ldr	r2, [r3, #28]
+ 80247e6:	f107 000c 	add.w	r0, r7, #12
+ 80247ea:	6a3b      	ldr	r3, [r7, #32]
+ 80247ec:	f7ff fafa 	bl	8023de4 <pb_decode_inner>
+ 80247f0:	4603      	mov	r3, r0
+ 80247f2:	f887 3027 	strb.w	r3, [r7, #39]	@ 0x27
+    }
+    
+    if (!pb_close_string_substream(stream, &substream))
+ 80247f6:	f107 030c 	add.w	r3, r7, #12
+ 80247fa:	4619      	mov	r1, r3
+ 80247fc:	6878      	ldr	r0, [r7, #4]
+ 80247fe:	f7fe fdff 	bl	8023400 <pb_close_string_substream>
+ 8024802:	4603      	mov	r3, r0
+ 8024804:	f083 0301 	eor.w	r3, r3, #1
+ 8024808:	b2db      	uxtb	r3, r3
+ 802480a:	2b00      	cmp	r3, #0
+ 802480c:	d001      	beq.n	8024812 <pb_dec_submessage+0x102>
+        return false;
+ 802480e:	2300      	movs	r3, #0
+ 8024810:	e001      	b.n	8024816 <pb_dec_submessage+0x106>
+
+    return status;
+ 8024812:	f897 3027 	ldrb.w	r3, [r7, #39]	@ 0x27
+}
+ 8024816:	4618      	mov	r0, r3
+ 8024818:	3728      	adds	r7, #40	@ 0x28
+ 802481a:	46bd      	mov	sp, r7
+ 802481c:	bd80      	pop	{r7, pc}
+ 802481e:	bf00      	nop
+ 8024820:	0804118c 	.word	0x0804118c
+
+08024824 <pb_dec_fixed_length_bytes>:
+
+static bool checkreturn pb_dec_fixed_length_bytes(pb_istream_t *stream, const pb_field_iter_t *field)
+{
+ 8024824:	b580      	push	{r7, lr}
+ 8024826:	b084      	sub	sp, #16
+ 8024828:	af00      	add	r7, sp, #0
+ 802482a:	6078      	str	r0, [r7, #4]
+ 802482c:	6039      	str	r1, [r7, #0]
+    uint32_t size;
+
+    if (!pb_decode_varint32(stream, &size))
+ 802482e:	f107 030c 	add.w	r3, r7, #12
+ 8024832:	4619      	mov	r1, r3
+ 8024834:	6878      	ldr	r0, [r7, #4]
+ 8024836:	f7fe fc1d 	bl	8023074 <pb_decode_varint32>
+ 802483a:	4603      	mov	r3, r0
+ 802483c:	f083 0301 	eor.w	r3, r3, #1
+ 8024840:	b2db      	uxtb	r3, r3
+ 8024842:	2b00      	cmp	r3, #0
+ 8024844:	d001      	beq.n	802484a <pb_dec_fixed_length_bytes+0x26>
+        return false;
+ 8024846:	2300      	movs	r3, #0
+ 8024848:	e037      	b.n	80248ba <pb_dec_fixed_length_bytes+0x96>
+
+    if (size > PB_SIZE_MAX)
+ 802484a:	68fb      	ldr	r3, [r7, #12]
+ 802484c:	f5b3 3f80 	cmp.w	r3, #65536	@ 0x10000
+ 8024850:	d30b      	bcc.n	802486a <pb_dec_fixed_length_bytes+0x46>
+        PB_RETURN_ERROR(stream, "bytes overflow");
+ 8024852:	687b      	ldr	r3, [r7, #4]
+ 8024854:	68db      	ldr	r3, [r3, #12]
+ 8024856:	2b00      	cmp	r3, #0
+ 8024858:	d002      	beq.n	8024860 <pb_dec_fixed_length_bytes+0x3c>
+ 802485a:	687b      	ldr	r3, [r7, #4]
+ 802485c:	68db      	ldr	r3, [r3, #12]
+ 802485e:	e000      	b.n	8024862 <pb_dec_fixed_length_bytes+0x3e>
+ 8024860:	4b18      	ldr	r3, [pc, #96]	@ (80248c4 <pb_dec_fixed_length_bytes+0xa0>)
+ 8024862:	687a      	ldr	r2, [r7, #4]
+ 8024864:	60d3      	str	r3, [r2, #12]
+ 8024866:	2300      	movs	r3, #0
+ 8024868:	e027      	b.n	80248ba <pb_dec_fixed_length_bytes+0x96>
+
+    if (size == 0)
+ 802486a:	68fb      	ldr	r3, [r7, #12]
+ 802486c:	2b00      	cmp	r3, #0
+ 802486e:	d109      	bne.n	8024884 <pb_dec_fixed_length_bytes+0x60>
+    {
+        /* As a special case, treat empty bytes string as all zeros for fixed_length_bytes. */
+        memset(field->pData, 0, (size_t)field->data_size);
+ 8024870:	683b      	ldr	r3, [r7, #0]
+ 8024872:	69d8      	ldr	r0, [r3, #28]
+ 8024874:	683b      	ldr	r3, [r7, #0]
+ 8024876:	8a5b      	ldrh	r3, [r3, #18]
+ 8024878:	461a      	mov	r2, r3
+ 802487a:	2100      	movs	r1, #0
+ 802487c:	f01b fd34 	bl	80402e8 <memset>
+        return true;
+ 8024880:	2301      	movs	r3, #1
+ 8024882:	e01a      	b.n	80248ba <pb_dec_fixed_length_bytes+0x96>
+    }
+
+    if (size != field->data_size)
+ 8024884:	683b      	ldr	r3, [r7, #0]
+ 8024886:	8a5b      	ldrh	r3, [r3, #18]
+ 8024888:	461a      	mov	r2, r3
+ 802488a:	68fb      	ldr	r3, [r7, #12]
+ 802488c:	429a      	cmp	r2, r3
+ 802488e:	d00b      	beq.n	80248a8 <pb_dec_fixed_length_bytes+0x84>
+        PB_RETURN_ERROR(stream, "incorrect fixed length bytes size");
+ 8024890:	687b      	ldr	r3, [r7, #4]
+ 8024892:	68db      	ldr	r3, [r3, #12]
+ 8024894:	2b00      	cmp	r3, #0
+ 8024896:	d002      	beq.n	802489e <pb_dec_fixed_length_bytes+0x7a>
+ 8024898:	687b      	ldr	r3, [r7, #4]
+ 802489a:	68db      	ldr	r3, [r3, #12]
+ 802489c:	e000      	b.n	80248a0 <pb_dec_fixed_length_bytes+0x7c>
+ 802489e:	4b0a      	ldr	r3, [pc, #40]	@ (80248c8 <pb_dec_fixed_length_bytes+0xa4>)
+ 80248a0:	687a      	ldr	r2, [r7, #4]
+ 80248a2:	60d3      	str	r3, [r2, #12]
+ 80248a4:	2300      	movs	r3, #0
+ 80248a6:	e008      	b.n	80248ba <pb_dec_fixed_length_bytes+0x96>
+
+    return pb_read(stream, (pb_byte_t*)field->pData, (size_t)field->data_size);
+ 80248a8:	683b      	ldr	r3, [r7, #0]
+ 80248aa:	69d9      	ldr	r1, [r3, #28]
+ 80248ac:	683b      	ldr	r3, [r7, #0]
+ 80248ae:	8a5b      	ldrh	r3, [r3, #18]
+ 80248b0:	461a      	mov	r2, r3
+ 80248b2:	6878      	ldr	r0, [r7, #4]
+ 80248b4:	f7fe fa64 	bl	8022d80 <pb_read>
+ 80248b8:	4603      	mov	r3, r0
+}
+ 80248ba:	4618      	mov	r0, r3
+ 80248bc:	3710      	adds	r7, #16
+ 80248be:	46bd      	mov	sp, r7
+ 80248c0:	bd80      	pop	{r7, pc}
+ 80248c2:	bf00      	nop
+ 80248c4:	0804115c 	.word	0x0804115c
+ 80248c8:	080411a8 	.word	0x080411a8
+
+080248cc <buf_write>:
+/*******************************
+ * pb_ostream_t implementation *
+ *******************************/
+
+static bool checkreturn buf_write(pb_ostream_t *stream, const pb_byte_t *buf, size_t count)
+{
+ 80248cc:	b580      	push	{r7, lr}
+ 80248ce:	b086      	sub	sp, #24
+ 80248d0:	af00      	add	r7, sp, #0
+ 80248d2:	60f8      	str	r0, [r7, #12]
+ 80248d4:	60b9      	str	r1, [r7, #8]
+ 80248d6:	607a      	str	r2, [r7, #4]
+    pb_byte_t *dest = (pb_byte_t*)stream->state;
+ 80248d8:	68fb      	ldr	r3, [r7, #12]
+ 80248da:	685b      	ldr	r3, [r3, #4]
+ 80248dc:	617b      	str	r3, [r7, #20]
+    stream->state = dest + count;
+ 80248de:	697a      	ldr	r2, [r7, #20]
+ 80248e0:	687b      	ldr	r3, [r7, #4]
+ 80248e2:	441a      	add	r2, r3
+ 80248e4:	68fb      	ldr	r3, [r7, #12]
+ 80248e6:	605a      	str	r2, [r3, #4]
+    
+    memcpy(dest, buf, count * sizeof(pb_byte_t));
+ 80248e8:	687a      	ldr	r2, [r7, #4]
+ 80248ea:	68b9      	ldr	r1, [r7, #8]
+ 80248ec:	6978      	ldr	r0, [r7, #20]
+ 80248ee:	f01b fd65 	bl	80403bc <memcpy>
+    
+    return true;
+ 80248f2:	2301      	movs	r3, #1
+}
+ 80248f4:	4618      	mov	r0, r3
+ 80248f6:	3718      	adds	r7, #24
+ 80248f8:	46bd      	mov	sp, r7
+ 80248fa:	bd80      	pop	{r7, pc}
+
+080248fc <pb_ostream_from_buffer>:
+
+pb_ostream_t pb_ostream_from_buffer(pb_byte_t *buf, size_t bufsize)
+{
+ 80248fc:	b4b0      	push	{r4, r5, r7}
+ 80248fe:	b08b      	sub	sp, #44	@ 0x2c
+ 8024900:	af00      	add	r7, sp, #0
+ 8024902:	60f8      	str	r0, [r7, #12]
+ 8024904:	60b9      	str	r1, [r7, #8]
+ 8024906:	607a      	str	r2, [r7, #4]
+     * NULL pointer marks a sizing field, so put a non-NULL value to mark a buffer stream.
+     */
+    static const int marker = 0;
+    stream.callback = &marker;
+#else
+    stream.callback = &buf_write;
+ 8024908:	4b0b      	ldr	r3, [pc, #44]	@ (8024938 <pb_ostream_from_buffer+0x3c>)
+ 802490a:	617b      	str	r3, [r7, #20]
+#endif
+    stream.state = buf;
+ 802490c:	68bb      	ldr	r3, [r7, #8]
+ 802490e:	61bb      	str	r3, [r7, #24]
+    stream.max_size = bufsize;
+ 8024910:	687b      	ldr	r3, [r7, #4]
+ 8024912:	61fb      	str	r3, [r7, #28]
+    stream.bytes_written = 0;
+ 8024914:	2300      	movs	r3, #0
+ 8024916:	623b      	str	r3, [r7, #32]
+#ifndef PB_NO_ERRMSG
+    stream.errmsg = NULL;
+ 8024918:	2300      	movs	r3, #0
+ 802491a:	627b      	str	r3, [r7, #36]	@ 0x24
+#endif
+    return stream;
+ 802491c:	68fb      	ldr	r3, [r7, #12]
+ 802491e:	461d      	mov	r5, r3
+ 8024920:	f107 0414 	add.w	r4, r7, #20
+ 8024924:	cc0f      	ldmia	r4!, {r0, r1, r2, r3}
+ 8024926:	c50f      	stmia	r5!, {r0, r1, r2, r3}
+ 8024928:	6823      	ldr	r3, [r4, #0]
+ 802492a:	602b      	str	r3, [r5, #0]
+}
+ 802492c:	68f8      	ldr	r0, [r7, #12]
+ 802492e:	372c      	adds	r7, #44	@ 0x2c
+ 8024930:	46bd      	mov	sp, r7
+ 8024932:	bcb0      	pop	{r4, r5, r7}
+ 8024934:	4770      	bx	lr
+ 8024936:	bf00      	nop
+ 8024938:	080248cd 	.word	0x080248cd
+
+0802493c <pb_write>:
+
+bool checkreturn pb_write(pb_ostream_t *stream, const pb_byte_t *buf, size_t count)
+{
+ 802493c:	b580      	push	{r7, lr}
+ 802493e:	b084      	sub	sp, #16
+ 8024940:	af00      	add	r7, sp, #0
+ 8024942:	60f8      	str	r0, [r7, #12]
+ 8024944:	60b9      	str	r1, [r7, #8]
+ 8024946:	607a      	str	r2, [r7, #4]
+    if (count > 0 && stream->callback != NULL)
+ 8024948:	687b      	ldr	r3, [r7, #4]
+ 802494a:	2b00      	cmp	r3, #0
+ 802494c:	d037      	beq.n	80249be <pb_write+0x82>
+ 802494e:	68fb      	ldr	r3, [r7, #12]
+ 8024950:	681b      	ldr	r3, [r3, #0]
+ 8024952:	2b00      	cmp	r3, #0
+ 8024954:	d033      	beq.n	80249be <pb_write+0x82>
+    {
+        if (stream->bytes_written + count < stream->bytes_written ||
+ 8024956:	68fb      	ldr	r3, [r7, #12]
+ 8024958:	68da      	ldr	r2, [r3, #12]
+ 802495a:	687b      	ldr	r3, [r7, #4]
+ 802495c:	441a      	add	r2, r3
+ 802495e:	68fb      	ldr	r3, [r7, #12]
+ 8024960:	68db      	ldr	r3, [r3, #12]
+ 8024962:	429a      	cmp	r2, r3
+ 8024964:	d307      	bcc.n	8024976 <pb_write+0x3a>
+            stream->bytes_written + count > stream->max_size)
+ 8024966:	68fb      	ldr	r3, [r7, #12]
+ 8024968:	68da      	ldr	r2, [r3, #12]
+ 802496a:	687b      	ldr	r3, [r7, #4]
+ 802496c:	441a      	add	r2, r3
+ 802496e:	68fb      	ldr	r3, [r7, #12]
+ 8024970:	689b      	ldr	r3, [r3, #8]
+        if (stream->bytes_written + count < stream->bytes_written ||
+ 8024972:	429a      	cmp	r2, r3
+ 8024974:	d90b      	bls.n	802498e <pb_write+0x52>
+        {
+            PB_RETURN_ERROR(stream, "stream full");
+ 8024976:	68fb      	ldr	r3, [r7, #12]
+ 8024978:	691b      	ldr	r3, [r3, #16]
+ 802497a:	2b00      	cmp	r3, #0
+ 802497c:	d002      	beq.n	8024984 <pb_write+0x48>
+ 802497e:	68fb      	ldr	r3, [r7, #12]
+ 8024980:	691b      	ldr	r3, [r3, #16]
+ 8024982:	e000      	b.n	8024986 <pb_write+0x4a>
+ 8024984:	4b13      	ldr	r3, [pc, #76]	@ (80249d4 <pb_write+0x98>)
+ 8024986:	68fa      	ldr	r2, [r7, #12]
+ 8024988:	6113      	str	r3, [r2, #16]
+ 802498a:	2300      	movs	r3, #0
+ 802498c:	e01e      	b.n	80249cc <pb_write+0x90>
+
+#ifdef PB_BUFFER_ONLY
+        if (!buf_write(stream, buf, count))
+            PB_RETURN_ERROR(stream, "io error");
+#else        
+        if (!stream->callback(stream, buf, count))
+ 802498e:	68fb      	ldr	r3, [r7, #12]
+ 8024990:	681b      	ldr	r3, [r3, #0]
+ 8024992:	687a      	ldr	r2, [r7, #4]
+ 8024994:	68b9      	ldr	r1, [r7, #8]
+ 8024996:	68f8      	ldr	r0, [r7, #12]
+ 8024998:	4798      	blx	r3
+ 802499a:	4603      	mov	r3, r0
+ 802499c:	f083 0301 	eor.w	r3, r3, #1
+ 80249a0:	b2db      	uxtb	r3, r3
+ 80249a2:	2b00      	cmp	r3, #0
+ 80249a4:	d00b      	beq.n	80249be <pb_write+0x82>
+            PB_RETURN_ERROR(stream, "io error");
+ 80249a6:	68fb      	ldr	r3, [r7, #12]
+ 80249a8:	691b      	ldr	r3, [r3, #16]
+ 80249aa:	2b00      	cmp	r3, #0
+ 80249ac:	d002      	beq.n	80249b4 <pb_write+0x78>
+ 80249ae:	68fb      	ldr	r3, [r7, #12]
+ 80249b0:	691b      	ldr	r3, [r3, #16]
+ 80249b2:	e000      	b.n	80249b6 <pb_write+0x7a>
+ 80249b4:	4b08      	ldr	r3, [pc, #32]	@ (80249d8 <pb_write+0x9c>)
+ 80249b6:	68fa      	ldr	r2, [r7, #12]
+ 80249b8:	6113      	str	r3, [r2, #16]
+ 80249ba:	2300      	movs	r3, #0
+ 80249bc:	e006      	b.n	80249cc <pb_write+0x90>
+#endif
+    }
+    
+    stream->bytes_written += count;
+ 80249be:	68fb      	ldr	r3, [r7, #12]
+ 80249c0:	68da      	ldr	r2, [r3, #12]
+ 80249c2:	687b      	ldr	r3, [r7, #4]
+ 80249c4:	441a      	add	r2, r3
+ 80249c6:	68fb      	ldr	r3, [r7, #12]
+ 80249c8:	60da      	str	r2, [r3, #12]
+    return true;
+ 80249ca:	2301      	movs	r3, #1
+}
+ 80249cc:	4618      	mov	r0, r3
+ 80249ce:	3710      	adds	r7, #16
+ 80249d0:	46bd      	mov	sp, r7
+ 80249d2:	bd80      	pop	{r7, pc}
+ 80249d4:	080411cc 	.word	0x080411cc
+ 80249d8:	080411d8 	.word	0x080411d8
+
+080249dc <safe_read_bool>:
+/* Read a bool value without causing undefined behavior even if the value
+ * is invalid. See issue #434 and
+ * https://stackoverflow.com/questions/27661768/weird-results-for-conditional
+ */
+static bool safe_read_bool(const void *pSize)
+{
+ 80249dc:	b480      	push	{r7}
+ 80249de:	b085      	sub	sp, #20
+ 80249e0:	af00      	add	r7, sp, #0
+ 80249e2:	6078      	str	r0, [r7, #4]
+    const char *p = (const char *)pSize;
+ 80249e4:	687b      	ldr	r3, [r7, #4]
+ 80249e6:	60bb      	str	r3, [r7, #8]
+    size_t i;
+    for (i = 0; i < sizeof(bool); i++)
+ 80249e8:	2300      	movs	r3, #0
+ 80249ea:	60fb      	str	r3, [r7, #12]
+ 80249ec:	e00a      	b.n	8024a04 <safe_read_bool+0x28>
+    {
+        if (p[i] != 0)
+ 80249ee:	68ba      	ldr	r2, [r7, #8]
+ 80249f0:	68fb      	ldr	r3, [r7, #12]
+ 80249f2:	4413      	add	r3, r2
+ 80249f4:	781b      	ldrb	r3, [r3, #0]
+ 80249f6:	2b00      	cmp	r3, #0
+ 80249f8:	d001      	beq.n	80249fe <safe_read_bool+0x22>
+            return true;
+ 80249fa:	2301      	movs	r3, #1
+ 80249fc:	e006      	b.n	8024a0c <safe_read_bool+0x30>
+    for (i = 0; i < sizeof(bool); i++)
+ 80249fe:	68fb      	ldr	r3, [r7, #12]
+ 8024a00:	3301      	adds	r3, #1
+ 8024a02:	60fb      	str	r3, [r7, #12]
+ 8024a04:	68fb      	ldr	r3, [r7, #12]
+ 8024a06:	2b00      	cmp	r3, #0
+ 8024a08:	d0f1      	beq.n	80249ee <safe_read_bool+0x12>
+    }
+    return false;
+ 8024a0a:	2300      	movs	r3, #0
+}
+ 8024a0c:	4618      	mov	r0, r3
+ 8024a0e:	3714      	adds	r7, #20
+ 8024a10:	46bd      	mov	sp, r7
+ 8024a12:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8024a16:	4770      	bx	lr
+
+08024a18 <encode_array>:
+
+/* Encode a static array. Handles the size calculations and possible packing. */
+static bool checkreturn encode_array(pb_ostream_t *stream, pb_field_iter_t *field)
+{
+ 8024a18:	b5b0      	push	{r4, r5, r7, lr}
+ 8024a1a:	b08c      	sub	sp, #48	@ 0x30
+ 8024a1c:	af00      	add	r7, sp, #0
+ 8024a1e:	6078      	str	r0, [r7, #4]
+ 8024a20:	6039      	str	r1, [r7, #0]
+    pb_size_t count;
+#ifndef PB_ENCODE_ARRAYS_UNPACKED
+    size_t size;
+#endif
+
+    count = *(pb_size_t*)field->pSize;
+ 8024a22:	683b      	ldr	r3, [r7, #0]
+ 8024a24:	6a1b      	ldr	r3, [r3, #32]
+ 8024a26:	881b      	ldrh	r3, [r3, #0]
+ 8024a28:	84bb      	strh	r3, [r7, #36]	@ 0x24
+
+    if (count == 0)
+ 8024a2a:	8cbb      	ldrh	r3, [r7, #36]	@ 0x24
+ 8024a2c:	2b00      	cmp	r3, #0
+ 8024a2e:	d101      	bne.n	8024a34 <encode_array+0x1c>
+        return true;
+ 8024a30:	2301      	movs	r3, #1
+ 8024a32:	e13d      	b.n	8024cb0 <encode_array+0x298>
+
+    if (PB_ATYPE(field->type) != PB_ATYPE_POINTER && count > field->array_size)
+ 8024a34:	683b      	ldr	r3, [r7, #0]
+ 8024a36:	7d9b      	ldrb	r3, [r3, #22]
+ 8024a38:	f003 03c0 	and.w	r3, r3, #192	@ 0xc0
+ 8024a3c:	2b80      	cmp	r3, #128	@ 0x80
+ 8024a3e:	d010      	beq.n	8024a62 <encode_array+0x4a>
+ 8024a40:	683b      	ldr	r3, [r7, #0]
+ 8024a42:	8a9b      	ldrh	r3, [r3, #20]
+ 8024a44:	8cba      	ldrh	r2, [r7, #36]	@ 0x24
+ 8024a46:	429a      	cmp	r2, r3
+ 8024a48:	d90b      	bls.n	8024a62 <encode_array+0x4a>
+        PB_RETURN_ERROR(stream, "array max size exceeded");
+ 8024a4a:	687b      	ldr	r3, [r7, #4]
+ 8024a4c:	691b      	ldr	r3, [r3, #16]
+ 8024a4e:	2b00      	cmp	r3, #0
+ 8024a50:	d002      	beq.n	8024a58 <encode_array+0x40>
+ 8024a52:	687b      	ldr	r3, [r7, #4]
+ 8024a54:	691b      	ldr	r3, [r3, #16]
+ 8024a56:	e000      	b.n	8024a5a <encode_array+0x42>
+ 8024a58:	4b97      	ldr	r3, [pc, #604]	@ (8024cb8 <encode_array+0x2a0>)
+ 8024a5a:	687a      	ldr	r2, [r7, #4]
+ 8024a5c:	6113      	str	r3, [r2, #16]
+ 8024a5e:	2300      	movs	r3, #0
+ 8024a60:	e126      	b.n	8024cb0 <encode_array+0x298>
+    
+#ifndef PB_ENCODE_ARRAYS_UNPACKED
+    /* We always pack arrays if the datatype allows it. */
+    if (PB_LTYPE(field->type) <= PB_LTYPE_LAST_PACKABLE)
+ 8024a62:	683b      	ldr	r3, [r7, #0]
+ 8024a64:	7d9b      	ldrb	r3, [r3, #22]
+ 8024a66:	f003 030f 	and.w	r3, r3, #15
+ 8024a6a:	2b05      	cmp	r3, #5
+ 8024a6c:	f200 80b3 	bhi.w	8024bd6 <encode_array+0x1be>
+    {
+        if (!pb_encode_tag(stream, PB_WT_STRING, field->tag))
+ 8024a70:	683b      	ldr	r3, [r7, #0]
+ 8024a72:	8a1b      	ldrh	r3, [r3, #16]
+ 8024a74:	461a      	mov	r2, r3
+ 8024a76:	2102      	movs	r1, #2
+ 8024a78:	6878      	ldr	r0, [r7, #4]
+ 8024a7a:	f000 fcdd 	bl	8025438 <pb_encode_tag>
+ 8024a7e:	4603      	mov	r3, r0
+ 8024a80:	f083 0301 	eor.w	r3, r3, #1
+ 8024a84:	b2db      	uxtb	r3, r3
+ 8024a86:	2b00      	cmp	r3, #0
+ 8024a88:	d001      	beq.n	8024a8e <encode_array+0x76>
+            return false;
+ 8024a8a:	2300      	movs	r3, #0
+ 8024a8c:	e110      	b.n	8024cb0 <encode_array+0x298>
+        
+        /* Determine the total size of packed array. */
+        if (PB_LTYPE(field->type) == PB_LTYPE_FIXED32)
+ 8024a8e:	683b      	ldr	r3, [r7, #0]
+ 8024a90:	7d9b      	ldrb	r3, [r3, #22]
+ 8024a92:	f003 030f 	and.w	r3, r3, #15
+ 8024a96:	2b04      	cmp	r3, #4
+ 8024a98:	d103      	bne.n	8024aa2 <encode_array+0x8a>
+        {
+            size = 4 * (size_t)count;
+ 8024a9a:	8cbb      	ldrh	r3, [r7, #36]	@ 0x24
+ 8024a9c:	009b      	lsls	r3, r3, #2
+ 8024a9e:	62bb      	str	r3, [r7, #40]	@ 0x28
+ 8024aa0:	e047      	b.n	8024b32 <encode_array+0x11a>
+        }
+        else if (PB_LTYPE(field->type) == PB_LTYPE_FIXED64)
+ 8024aa2:	683b      	ldr	r3, [r7, #0]
+ 8024aa4:	7d9b      	ldrb	r3, [r3, #22]
+ 8024aa6:	f003 030f 	and.w	r3, r3, #15
+ 8024aaa:	2b05      	cmp	r3, #5
+ 8024aac:	d103      	bne.n	8024ab6 <encode_array+0x9e>
+        {
+            size = 8 * (size_t)count;
+ 8024aae:	8cbb      	ldrh	r3, [r7, #36]	@ 0x24
+ 8024ab0:	00db      	lsls	r3, r3, #3
+ 8024ab2:	62bb      	str	r3, [r7, #40]	@ 0x28
+ 8024ab4:	e03d      	b.n	8024b32 <encode_array+0x11a>
+        }
+        else
+        { 
+            pb_ostream_t sizestream = PB_OSTREAM_SIZING;
+ 8024ab6:	f107 0308 	add.w	r3, r7, #8
+ 8024aba:	2200      	movs	r2, #0
+ 8024abc:	601a      	str	r2, [r3, #0]
+ 8024abe:	605a      	str	r2, [r3, #4]
+ 8024ac0:	609a      	str	r2, [r3, #8]
+ 8024ac2:	60da      	str	r2, [r3, #12]
+ 8024ac4:	611a      	str	r2, [r3, #16]
+            void *pData_orig = field->pData;
+ 8024ac6:	683b      	ldr	r3, [r7, #0]
+ 8024ac8:	69db      	ldr	r3, [r3, #28]
+ 8024aca:	61fb      	str	r3, [r7, #28]
+            for (i = 0; i < count; i++)
+ 8024acc:	2300      	movs	r3, #0
+ 8024ace:	85fb      	strh	r3, [r7, #46]	@ 0x2e
+ 8024ad0:	e026      	b.n	8024b20 <encode_array+0x108>
+            {
+                if (!pb_enc_varint(&sizestream, field))
+ 8024ad2:	f107 0308 	add.w	r3, r7, #8
+ 8024ad6:	6839      	ldr	r1, [r7, #0]
+ 8024ad8:	4618      	mov	r0, r3
+ 8024ada:	f000 fdef 	bl	80256bc <pb_enc_varint>
+ 8024ade:	4603      	mov	r3, r0
+ 8024ae0:	f083 0301 	eor.w	r3, r3, #1
+ 8024ae4:	b2db      	uxtb	r3, r3
+ 8024ae6:	2b00      	cmp	r3, #0
+ 8024ae8:	d010      	beq.n	8024b0c <encode_array+0xf4>
+                    PB_RETURN_ERROR(stream, PB_GET_ERROR(&sizestream));
+ 8024aea:	687b      	ldr	r3, [r7, #4]
+ 8024aec:	691b      	ldr	r3, [r3, #16]
+ 8024aee:	2b00      	cmp	r3, #0
+ 8024af0:	d002      	beq.n	8024af8 <encode_array+0xe0>
+ 8024af2:	687b      	ldr	r3, [r7, #4]
+ 8024af4:	691b      	ldr	r3, [r3, #16]
+ 8024af6:	e005      	b.n	8024b04 <encode_array+0xec>
+ 8024af8:	69bb      	ldr	r3, [r7, #24]
+ 8024afa:	2b00      	cmp	r3, #0
+ 8024afc:	d001      	beq.n	8024b02 <encode_array+0xea>
+ 8024afe:	69bb      	ldr	r3, [r7, #24]
+ 8024b00:	e000      	b.n	8024b04 <encode_array+0xec>
+ 8024b02:	4b6e      	ldr	r3, [pc, #440]	@ (8024cbc <encode_array+0x2a4>)
+ 8024b04:	687a      	ldr	r2, [r7, #4]
+ 8024b06:	6113      	str	r3, [r2, #16]
+ 8024b08:	2300      	movs	r3, #0
+ 8024b0a:	e0d1      	b.n	8024cb0 <encode_array+0x298>
+                field->pData = (char*)field->pData + field->data_size;
+ 8024b0c:	683b      	ldr	r3, [r7, #0]
+ 8024b0e:	69db      	ldr	r3, [r3, #28]
+ 8024b10:	683a      	ldr	r2, [r7, #0]
+ 8024b12:	8a52      	ldrh	r2, [r2, #18]
+ 8024b14:	441a      	add	r2, r3
+ 8024b16:	683b      	ldr	r3, [r7, #0]
+ 8024b18:	61da      	str	r2, [r3, #28]
+            for (i = 0; i < count; i++)
+ 8024b1a:	8dfb      	ldrh	r3, [r7, #46]	@ 0x2e
+ 8024b1c:	3301      	adds	r3, #1
+ 8024b1e:	85fb      	strh	r3, [r7, #46]	@ 0x2e
+ 8024b20:	8dfa      	ldrh	r2, [r7, #46]	@ 0x2e
+ 8024b22:	8cbb      	ldrh	r3, [r7, #36]	@ 0x24
+ 8024b24:	429a      	cmp	r2, r3
+ 8024b26:	d3d4      	bcc.n	8024ad2 <encode_array+0xba>
+            }
+            field->pData = pData_orig;
+ 8024b28:	683b      	ldr	r3, [r7, #0]
+ 8024b2a:	69fa      	ldr	r2, [r7, #28]
+ 8024b2c:	61da      	str	r2, [r3, #28]
+            size = sizestream.bytes_written;
+ 8024b2e:	697b      	ldr	r3, [r7, #20]
+ 8024b30:	62bb      	str	r3, [r7, #40]	@ 0x28
+        }
+        
+        if (!pb_encode_varint(stream, (pb_uint64_t)size))
+ 8024b32:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 8024b34:	2200      	movs	r2, #0
+ 8024b36:	461c      	mov	r4, r3
+ 8024b38:	4615      	mov	r5, r2
+ 8024b3a:	4622      	mov	r2, r4
+ 8024b3c:	462b      	mov	r3, r5
+ 8024b3e:	6878      	ldr	r0, [r7, #4]
+ 8024b40:	f000 fbf7 	bl	8025332 <pb_encode_varint>
+ 8024b44:	4603      	mov	r3, r0
+ 8024b46:	f083 0301 	eor.w	r3, r3, #1
+ 8024b4a:	b2db      	uxtb	r3, r3
+ 8024b4c:	2b00      	cmp	r3, #0
+ 8024b4e:	d001      	beq.n	8024b54 <encode_array+0x13c>
+            return false;
+ 8024b50:	2300      	movs	r3, #0
+ 8024b52:	e0ad      	b.n	8024cb0 <encode_array+0x298>
+        
+        if (stream->callback == NULL)
+ 8024b54:	687b      	ldr	r3, [r7, #4]
+ 8024b56:	681b      	ldr	r3, [r3, #0]
+ 8024b58:	2b00      	cmp	r3, #0
+ 8024b5a:	d106      	bne.n	8024b6a <encode_array+0x152>
+            return pb_write(stream, NULL, size); /* Just sizing.. */
+ 8024b5c:	6aba      	ldr	r2, [r7, #40]	@ 0x28
+ 8024b5e:	2100      	movs	r1, #0
+ 8024b60:	6878      	ldr	r0, [r7, #4]
+ 8024b62:	f7ff feeb 	bl	802493c <pb_write>
+ 8024b66:	4603      	mov	r3, r0
+ 8024b68:	e0a2      	b.n	8024cb0 <encode_array+0x298>
+        
+        /* Write the data */
+        for (i = 0; i < count; i++)
+ 8024b6a:	2300      	movs	r3, #0
+ 8024b6c:	85fb      	strh	r3, [r7, #46]	@ 0x2e
+ 8024b6e:	e02d      	b.n	8024bcc <encode_array+0x1b4>
+        {
+            if (PB_LTYPE(field->type) == PB_LTYPE_FIXED32 || PB_LTYPE(field->type) == PB_LTYPE_FIXED64)
+ 8024b70:	683b      	ldr	r3, [r7, #0]
+ 8024b72:	7d9b      	ldrb	r3, [r3, #22]
+ 8024b74:	f003 030f 	and.w	r3, r3, #15
+ 8024b78:	2b04      	cmp	r3, #4
+ 8024b7a:	d005      	beq.n	8024b88 <encode_array+0x170>
+ 8024b7c:	683b      	ldr	r3, [r7, #0]
+ 8024b7e:	7d9b      	ldrb	r3, [r3, #22]
+ 8024b80:	f003 030f 	and.w	r3, r3, #15
+ 8024b84:	2b05      	cmp	r3, #5
+ 8024b86:	d10b      	bne.n	8024ba0 <encode_array+0x188>
+            {
+                if (!pb_enc_fixed(stream, field))
+ 8024b88:	6839      	ldr	r1, [r7, #0]
+ 8024b8a:	6878      	ldr	r0, [r7, #4]
+ 8024b8c:	f000 fe58 	bl	8025840 <pb_enc_fixed>
+ 8024b90:	4603      	mov	r3, r0
+ 8024b92:	f083 0301 	eor.w	r3, r3, #1
+ 8024b96:	b2db      	uxtb	r3, r3
+ 8024b98:	2b00      	cmp	r3, #0
+ 8024b9a:	d00d      	beq.n	8024bb8 <encode_array+0x1a0>
+                    return false;
+ 8024b9c:	2300      	movs	r3, #0
+ 8024b9e:	e087      	b.n	8024cb0 <encode_array+0x298>
+            }
+            else
+            {
+                if (!pb_enc_varint(stream, field))
+ 8024ba0:	6839      	ldr	r1, [r7, #0]
+ 8024ba2:	6878      	ldr	r0, [r7, #4]
+ 8024ba4:	f000 fd8a 	bl	80256bc <pb_enc_varint>
+ 8024ba8:	4603      	mov	r3, r0
+ 8024baa:	f083 0301 	eor.w	r3, r3, #1
+ 8024bae:	b2db      	uxtb	r3, r3
+ 8024bb0:	2b00      	cmp	r3, #0
+ 8024bb2:	d001      	beq.n	8024bb8 <encode_array+0x1a0>
+                    return false;
+ 8024bb4:	2300      	movs	r3, #0
+ 8024bb6:	e07b      	b.n	8024cb0 <encode_array+0x298>
+            }
+
+            field->pData = (char*)field->pData + field->data_size;
+ 8024bb8:	683b      	ldr	r3, [r7, #0]
+ 8024bba:	69db      	ldr	r3, [r3, #28]
+ 8024bbc:	683a      	ldr	r2, [r7, #0]
+ 8024bbe:	8a52      	ldrh	r2, [r2, #18]
+ 8024bc0:	441a      	add	r2, r3
+ 8024bc2:	683b      	ldr	r3, [r7, #0]
+ 8024bc4:	61da      	str	r2, [r3, #28]
+        for (i = 0; i < count; i++)
+ 8024bc6:	8dfb      	ldrh	r3, [r7, #46]	@ 0x2e
+ 8024bc8:	3301      	adds	r3, #1
+ 8024bca:	85fb      	strh	r3, [r7, #46]	@ 0x2e
+ 8024bcc:	8dfa      	ldrh	r2, [r7, #46]	@ 0x2e
+ 8024bce:	8cbb      	ldrh	r3, [r7, #36]	@ 0x24
+ 8024bd0:	429a      	cmp	r2, r3
+ 8024bd2:	d3cd      	bcc.n	8024b70 <encode_array+0x158>
+ 8024bd4:	e06b      	b.n	8024cae <encode_array+0x296>
+        }
+    }
+    else /* Unpacked fields */
+#endif
+    {
+        for (i = 0; i < count; i++)
+ 8024bd6:	2300      	movs	r3, #0
+ 8024bd8:	85fb      	strh	r3, [r7, #46]	@ 0x2e
+ 8024bda:	e064      	b.n	8024ca6 <encode_array+0x28e>
+        {
+            /* Normally the data is stored directly in the array entries, but
+             * for pointer-type string and bytes fields, the array entries are
+             * actually pointers themselves also. So we have to dereference once
+             * more to get to the actual data. */
+            if (PB_ATYPE(field->type) == PB_ATYPE_POINTER &&
+ 8024bdc:	683b      	ldr	r3, [r7, #0]
+ 8024bde:	7d9b      	ldrb	r3, [r3, #22]
+ 8024be0:	f003 03c0 	and.w	r3, r3, #192	@ 0xc0
+ 8024be4:	2b80      	cmp	r3, #128	@ 0x80
+ 8024be6:	d147      	bne.n	8024c78 <encode_array+0x260>
+                (PB_LTYPE(field->type) == PB_LTYPE_STRING ||
+ 8024be8:	683b      	ldr	r3, [r7, #0]
+ 8024bea:	7d9b      	ldrb	r3, [r3, #22]
+ 8024bec:	f003 030f 	and.w	r3, r3, #15
+            if (PB_ATYPE(field->type) == PB_ATYPE_POINTER &&
+ 8024bf0:	2b07      	cmp	r3, #7
+ 8024bf2:	d005      	beq.n	8024c00 <encode_array+0x1e8>
+                 PB_LTYPE(field->type) == PB_LTYPE_BYTES))
+ 8024bf4:	683b      	ldr	r3, [r7, #0]
+ 8024bf6:	7d9b      	ldrb	r3, [r3, #22]
+ 8024bf8:	f003 030f 	and.w	r3, r3, #15
+                (PB_LTYPE(field->type) == PB_LTYPE_STRING ||
+ 8024bfc:	2b06      	cmp	r3, #6
+ 8024bfe:	d13b      	bne.n	8024c78 <encode_array+0x260>
+            {
+                bool status;
+                void *pData_orig = field->pData;
+ 8024c00:	683b      	ldr	r3, [r7, #0]
+ 8024c02:	69db      	ldr	r3, [r3, #28]
+ 8024c04:	623b      	str	r3, [r7, #32]
+                field->pData = *(void* const*)field->pData;
+ 8024c06:	683b      	ldr	r3, [r7, #0]
+ 8024c08:	69db      	ldr	r3, [r3, #28]
+ 8024c0a:	681a      	ldr	r2, [r3, #0]
+ 8024c0c:	683b      	ldr	r3, [r7, #0]
+ 8024c0e:	61da      	str	r2, [r3, #28]
+
+                if (!field->pData)
+ 8024c10:	683b      	ldr	r3, [r7, #0]
+ 8024c12:	69db      	ldr	r3, [r3, #28]
+ 8024c14:	2b00      	cmp	r3, #0
+ 8024c16:	d11c      	bne.n	8024c52 <encode_array+0x23a>
+                {
+                    /* Null pointer in array is treated as empty string / bytes */
+                    status = pb_encode_tag_for_field(stream, field) &&
+ 8024c18:	6839      	ldr	r1, [r7, #0]
+ 8024c1a:	6878      	ldr	r0, [r7, #4]
+ 8024c1c:	f000 fc36 	bl	802548c <pb_encode_tag_for_field>
+ 8024c20:	4603      	mov	r3, r0
+ 8024c22:	2b00      	cmp	r3, #0
+ 8024c24:	d00b      	beq.n	8024c3e <encode_array+0x226>
+                             pb_encode_varint(stream, 0);
+ 8024c26:	f04f 0200 	mov.w	r2, #0
+ 8024c2a:	f04f 0300 	mov.w	r3, #0
+ 8024c2e:	6878      	ldr	r0, [r7, #4]
+ 8024c30:	f000 fb7f 	bl	8025332 <pb_encode_varint>
+ 8024c34:	4603      	mov	r3, r0
+                    status = pb_encode_tag_for_field(stream, field) &&
+ 8024c36:	2b00      	cmp	r3, #0
+ 8024c38:	d001      	beq.n	8024c3e <encode_array+0x226>
+ 8024c3a:	2301      	movs	r3, #1
+ 8024c3c:	e000      	b.n	8024c40 <encode_array+0x228>
+ 8024c3e:	2300      	movs	r3, #0
+ 8024c40:	f887 3027 	strb.w	r3, [r7, #39]	@ 0x27
+ 8024c44:	f897 3027 	ldrb.w	r3, [r7, #39]	@ 0x27
+ 8024c48:	f003 0301 	and.w	r3, r3, #1
+ 8024c4c:	f887 3027 	strb.w	r3, [r7, #39]	@ 0x27
+ 8024c50:	e006      	b.n	8024c60 <encode_array+0x248>
+                }
+                else
+                {
+                    status = encode_basic_field(stream, field);
+ 8024c52:	6839      	ldr	r1, [r7, #0]
+ 8024c54:	6878      	ldr	r0, [r7, #4]
+ 8024c56:	f000 f951 	bl	8024efc <encode_basic_field>
+ 8024c5a:	4603      	mov	r3, r0
+ 8024c5c:	f887 3027 	strb.w	r3, [r7, #39]	@ 0x27
+                }
+
+                field->pData = pData_orig;
+ 8024c60:	683b      	ldr	r3, [r7, #0]
+ 8024c62:	6a3a      	ldr	r2, [r7, #32]
+ 8024c64:	61da      	str	r2, [r3, #28]
+
+                if (!status)
+ 8024c66:	f897 3027 	ldrb.w	r3, [r7, #39]	@ 0x27
+ 8024c6a:	f083 0301 	eor.w	r3, r3, #1
+ 8024c6e:	b2db      	uxtb	r3, r3
+ 8024c70:	2b00      	cmp	r3, #0
+ 8024c72:	d00d      	beq.n	8024c90 <encode_array+0x278>
+                    return false;
+ 8024c74:	2300      	movs	r3, #0
+ 8024c76:	e01b      	b.n	8024cb0 <encode_array+0x298>
+            }
+            else
+            {
+                if (!encode_basic_field(stream, field))
+ 8024c78:	6839      	ldr	r1, [r7, #0]
+ 8024c7a:	6878      	ldr	r0, [r7, #4]
+ 8024c7c:	f000 f93e 	bl	8024efc <encode_basic_field>
+ 8024c80:	4603      	mov	r3, r0
+ 8024c82:	f083 0301 	eor.w	r3, r3, #1
+ 8024c86:	b2db      	uxtb	r3, r3
+ 8024c88:	2b00      	cmp	r3, #0
+ 8024c8a:	d002      	beq.n	8024c92 <encode_array+0x27a>
+                    return false;
+ 8024c8c:	2300      	movs	r3, #0
+ 8024c8e:	e00f      	b.n	8024cb0 <encode_array+0x298>
+            {
+ 8024c90:	bf00      	nop
+            }
+            field->pData = (char*)field->pData + field->data_size;
+ 8024c92:	683b      	ldr	r3, [r7, #0]
+ 8024c94:	69db      	ldr	r3, [r3, #28]
+ 8024c96:	683a      	ldr	r2, [r7, #0]
+ 8024c98:	8a52      	ldrh	r2, [r2, #18]
+ 8024c9a:	441a      	add	r2, r3
+ 8024c9c:	683b      	ldr	r3, [r7, #0]
+ 8024c9e:	61da      	str	r2, [r3, #28]
+        for (i = 0; i < count; i++)
+ 8024ca0:	8dfb      	ldrh	r3, [r7, #46]	@ 0x2e
+ 8024ca2:	3301      	adds	r3, #1
+ 8024ca4:	85fb      	strh	r3, [r7, #46]	@ 0x2e
+ 8024ca6:	8dfa      	ldrh	r2, [r7, #46]	@ 0x2e
+ 8024ca8:	8cbb      	ldrh	r3, [r7, #36]	@ 0x24
+ 8024caa:	429a      	cmp	r2, r3
+ 8024cac:	d396      	bcc.n	8024bdc <encode_array+0x1c4>
+        }
+    }
+    
+    return true;
+ 8024cae:	2301      	movs	r3, #1
+}
+ 8024cb0:	4618      	mov	r0, r3
+ 8024cb2:	3730      	adds	r7, #48	@ 0x30
+ 8024cb4:	46bd      	mov	sp, r7
+ 8024cb6:	bdb0      	pop	{r4, r5, r7, pc}
+ 8024cb8:	080411e4 	.word	0x080411e4
+ 8024cbc:	080411fc 	.word	0x080411fc
+
+08024cc0 <pb_check_proto3_default_value>:
+
+/* In proto3, all fields are optional and are only encoded if their value is "non-zero".
+ * This function implements the check for the zero value. */
+static bool checkreturn pb_check_proto3_default_value(const pb_field_iter_t *field)
+{
+ 8024cc0:	b580      	push	{r7, lr}
+ 8024cc2:	b092      	sub	sp, #72	@ 0x48
+ 8024cc4:	af00      	add	r7, sp, #0
+ 8024cc6:	6078      	str	r0, [r7, #4]
+    pb_type_t type = field->type;
+ 8024cc8:	687b      	ldr	r3, [r7, #4]
+ 8024cca:	7d9b      	ldrb	r3, [r3, #22]
+ 8024ccc:	f887 3045 	strb.w	r3, [r7, #69]	@ 0x45
+
+    if (PB_ATYPE(type) == PB_ATYPE_STATIC)
+ 8024cd0:	f897 3045 	ldrb.w	r3, [r7, #69]	@ 0x45
+ 8024cd4:	f003 03c0 	and.w	r3, r3, #192	@ 0xc0
+ 8024cd8:	2b00      	cmp	r3, #0
+ 8024cda:	f040 80c9 	bne.w	8024e70 <pb_check_proto3_default_value+0x1b0>
+    {
+        if (PB_HTYPE(type) == PB_HTYPE_REQUIRED)
+ 8024cde:	f897 3045 	ldrb.w	r3, [r7, #69]	@ 0x45
+ 8024ce2:	f003 0330 	and.w	r3, r3, #48	@ 0x30
+ 8024ce6:	2b00      	cmp	r3, #0
+ 8024ce8:	d101      	bne.n	8024cee <pb_check_proto3_default_value+0x2e>
+        {
+            /* Required proto2 fields inside proto3 submessage, pretty rare case */
+            return false;
+ 8024cea:	2300      	movs	r3, #0
+ 8024cec:	e100      	b.n	8024ef0 <pb_check_proto3_default_value+0x230>
+        }
+        else if (PB_HTYPE(type) == PB_HTYPE_REPEATED)
+ 8024cee:	f897 3045 	ldrb.w	r3, [r7, #69]	@ 0x45
+ 8024cf2:	f003 0330 	and.w	r3, r3, #48	@ 0x30
+ 8024cf6:	2b20      	cmp	r3, #32
+ 8024cf8:	d108      	bne.n	8024d0c <pb_check_proto3_default_value+0x4c>
+        {
+            /* Repeated fields inside proto3 submessage: present if count != 0 */
+            return *(const pb_size_t*)field->pSize == 0;
+ 8024cfa:	687b      	ldr	r3, [r7, #4]
+ 8024cfc:	6a1b      	ldr	r3, [r3, #32]
+ 8024cfe:	881b      	ldrh	r3, [r3, #0]
+ 8024d00:	2b00      	cmp	r3, #0
+ 8024d02:	bf0c      	ite	eq
+ 8024d04:	2301      	moveq	r3, #1
+ 8024d06:	2300      	movne	r3, #0
+ 8024d08:	b2db      	uxtb	r3, r3
+ 8024d0a:	e0f1      	b.n	8024ef0 <pb_check_proto3_default_value+0x230>
+        }
+        else if (PB_HTYPE(type) == PB_HTYPE_ONEOF)
+ 8024d0c:	f897 3045 	ldrb.w	r3, [r7, #69]	@ 0x45
+ 8024d10:	f003 0330 	and.w	r3, r3, #48	@ 0x30
+ 8024d14:	2b30      	cmp	r3, #48	@ 0x30
+ 8024d16:	d108      	bne.n	8024d2a <pb_check_proto3_default_value+0x6a>
+        {
+            /* Oneof fields */
+            return *(const pb_size_t*)field->pSize == 0;
+ 8024d18:	687b      	ldr	r3, [r7, #4]
+ 8024d1a:	6a1b      	ldr	r3, [r3, #32]
+ 8024d1c:	881b      	ldrh	r3, [r3, #0]
+ 8024d1e:	2b00      	cmp	r3, #0
+ 8024d20:	bf0c      	ite	eq
+ 8024d22:	2301      	moveq	r3, #1
+ 8024d24:	2300      	movne	r3, #0
+ 8024d26:	b2db      	uxtb	r3, r3
+ 8024d28:	e0e2      	b.n	8024ef0 <pb_check_proto3_default_value+0x230>
+        }
+        else if (PB_HTYPE(type) == PB_HTYPE_OPTIONAL && field->pSize != NULL)
+ 8024d2a:	f897 3045 	ldrb.w	r3, [r7, #69]	@ 0x45
+ 8024d2e:	f003 0330 	and.w	r3, r3, #48	@ 0x30
+ 8024d32:	2b10      	cmp	r3, #16
+ 8024d34:	d115      	bne.n	8024d62 <pb_check_proto3_default_value+0xa2>
+ 8024d36:	687b      	ldr	r3, [r7, #4]
+ 8024d38:	6a1b      	ldr	r3, [r3, #32]
+ 8024d3a:	2b00      	cmp	r3, #0
+ 8024d3c:	d011      	beq.n	8024d62 <pb_check_proto3_default_value+0xa2>
+        {
+            /* Proto2 optional fields inside proto3 message, or proto3
+             * submessage fields. */
+            return safe_read_bool(field->pSize) == false;
+ 8024d3e:	687b      	ldr	r3, [r7, #4]
+ 8024d40:	6a1b      	ldr	r3, [r3, #32]
+ 8024d42:	4618      	mov	r0, r3
+ 8024d44:	f7ff fe4a 	bl	80249dc <safe_read_bool>
+ 8024d48:	4603      	mov	r3, r0
+ 8024d4a:	2b00      	cmp	r3, #0
+ 8024d4c:	bf14      	ite	ne
+ 8024d4e:	2301      	movne	r3, #1
+ 8024d50:	2300      	moveq	r3, #0
+ 8024d52:	b2db      	uxtb	r3, r3
+ 8024d54:	f083 0301 	eor.w	r3, r3, #1
+ 8024d58:	b2db      	uxtb	r3, r3
+ 8024d5a:	f003 0301 	and.w	r3, r3, #1
+ 8024d5e:	b2db      	uxtb	r3, r3
+ 8024d60:	e0c6      	b.n	8024ef0 <pb_check_proto3_default_value+0x230>
+        }
+        else if (field->descriptor->default_value)
+ 8024d62:	687b      	ldr	r3, [r7, #4]
+ 8024d64:	681b      	ldr	r3, [r3, #0]
+ 8024d66:	689b      	ldr	r3, [r3, #8]
+ 8024d68:	2b00      	cmp	r3, #0
+ 8024d6a:	d001      	beq.n	8024d70 <pb_check_proto3_default_value+0xb0>
+            /* Proto3 messages do not have default values, but proto2 messages
+             * can contain optional fields without has_fields (generator option 'proto3').
+             * In this case they must always be encoded, to make sure that the
+             * non-zero default value is overwritten.
+             */
+            return false;
+ 8024d6c:	2300      	movs	r3, #0
+ 8024d6e:	e0bf      	b.n	8024ef0 <pb_check_proto3_default_value+0x230>
+        }
+
+        /* Rest is proto3 singular fields */
+        if (PB_LTYPE(type) <= PB_LTYPE_LAST_PACKABLE)
+ 8024d70:	f897 3045 	ldrb.w	r3, [r7, #69]	@ 0x45
+ 8024d74:	f003 030f 	and.w	r3, r3, #15
+ 8024d78:	2b05      	cmp	r3, #5
+ 8024d7a:	d81c      	bhi.n	8024db6 <pb_check_proto3_default_value+0xf6>
+        {
+            /* Simple integer / float fields */
+            pb_size_t i;
+            const char *p = (const char*)field->pData;
+ 8024d7c:	687b      	ldr	r3, [r7, #4]
+ 8024d7e:	69db      	ldr	r3, [r3, #28]
+ 8024d80:	637b      	str	r3, [r7, #52]	@ 0x34
+            for (i = 0; i < field->data_size; i++)
+ 8024d82:	2300      	movs	r3, #0
+ 8024d84:	f8a7 3046 	strh.w	r3, [r7, #70]	@ 0x46
+ 8024d88:	e00d      	b.n	8024da6 <pb_check_proto3_default_value+0xe6>
+            {
+                if (p[i] != 0)
+ 8024d8a:	f8b7 3046 	ldrh.w	r3, [r7, #70]	@ 0x46
+ 8024d8e:	6b7a      	ldr	r2, [r7, #52]	@ 0x34
+ 8024d90:	4413      	add	r3, r2
+ 8024d92:	781b      	ldrb	r3, [r3, #0]
+ 8024d94:	2b00      	cmp	r3, #0
+ 8024d96:	d001      	beq.n	8024d9c <pb_check_proto3_default_value+0xdc>
+                {
+                    return false;
+ 8024d98:	2300      	movs	r3, #0
+ 8024d9a:	e0a9      	b.n	8024ef0 <pb_check_proto3_default_value+0x230>
+            for (i = 0; i < field->data_size; i++)
+ 8024d9c:	f8b7 3046 	ldrh.w	r3, [r7, #70]	@ 0x46
+ 8024da0:	3301      	adds	r3, #1
+ 8024da2:	f8a7 3046 	strh.w	r3, [r7, #70]	@ 0x46
+ 8024da6:	687b      	ldr	r3, [r7, #4]
+ 8024da8:	8a5b      	ldrh	r3, [r3, #18]
+ 8024daa:	f8b7 2046 	ldrh.w	r2, [r7, #70]	@ 0x46
+ 8024dae:	429a      	cmp	r2, r3
+ 8024db0:	d3eb      	bcc.n	8024d8a <pb_check_proto3_default_value+0xca>
+                }
+            }
+
+            return true;
+ 8024db2:	2301      	movs	r3, #1
+ 8024db4:	e09c      	b.n	8024ef0 <pb_check_proto3_default_value+0x230>
+        }
+        else if (PB_LTYPE(type) == PB_LTYPE_BYTES)
+ 8024db6:	f897 3045 	ldrb.w	r3, [r7, #69]	@ 0x45
+ 8024dba:	f003 030f 	and.w	r3, r3, #15
+ 8024dbe:	2b06      	cmp	r3, #6
+ 8024dc0:	d10a      	bne.n	8024dd8 <pb_check_proto3_default_value+0x118>
+        {
+            const pb_bytes_array_t *bytes = (const pb_bytes_array_t*)field->pData;
+ 8024dc2:	687b      	ldr	r3, [r7, #4]
+ 8024dc4:	69db      	ldr	r3, [r3, #28]
+ 8024dc6:	63bb      	str	r3, [r7, #56]	@ 0x38
+            return bytes->size == 0;
+ 8024dc8:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 8024dca:	881b      	ldrh	r3, [r3, #0]
+ 8024dcc:	2b00      	cmp	r3, #0
+ 8024dce:	bf0c      	ite	eq
+ 8024dd0:	2301      	moveq	r3, #1
+ 8024dd2:	2300      	movne	r3, #0
+ 8024dd4:	b2db      	uxtb	r3, r3
+ 8024dd6:	e08b      	b.n	8024ef0 <pb_check_proto3_default_value+0x230>
+        }
+        else if (PB_LTYPE(type) == PB_LTYPE_STRING)
+ 8024dd8:	f897 3045 	ldrb.w	r3, [r7, #69]	@ 0x45
+ 8024ddc:	f003 030f 	and.w	r3, r3, #15
+ 8024de0:	2b07      	cmp	r3, #7
+ 8024de2:	d108      	bne.n	8024df6 <pb_check_proto3_default_value+0x136>
+        {
+            return *(const char*)field->pData == '\0';
+ 8024de4:	687b      	ldr	r3, [r7, #4]
+ 8024de6:	69db      	ldr	r3, [r3, #28]
+ 8024de8:	781b      	ldrb	r3, [r3, #0]
+ 8024dea:	2b00      	cmp	r3, #0
+ 8024dec:	bf0c      	ite	eq
+ 8024dee:	2301      	moveq	r3, #1
+ 8024df0:	2300      	movne	r3, #0
+ 8024df2:	b2db      	uxtb	r3, r3
+ 8024df4:	e07c      	b.n	8024ef0 <pb_check_proto3_default_value+0x230>
+        }
+        else if (PB_LTYPE(type) == PB_LTYPE_FIXED_LENGTH_BYTES)
+ 8024df6:	f897 3045 	ldrb.w	r3, [r7, #69]	@ 0x45
+ 8024dfa:	f003 030f 	and.w	r3, r3, #15
+ 8024dfe:	2b0b      	cmp	r3, #11
+ 8024e00:	d107      	bne.n	8024e12 <pb_check_proto3_default_value+0x152>
+        {
+            /* Fixed length bytes is only empty if its length is fixed
+             * as 0. Which would be pretty strange, but we can check
+             * it anyway. */
+            return field->data_size == 0;
+ 8024e02:	687b      	ldr	r3, [r7, #4]
+ 8024e04:	8a5b      	ldrh	r3, [r3, #18]
+ 8024e06:	2b00      	cmp	r3, #0
+ 8024e08:	bf0c      	ite	eq
+ 8024e0a:	2301      	moveq	r3, #1
+ 8024e0c:	2300      	movne	r3, #0
+ 8024e0e:	b2db      	uxtb	r3, r3
+ 8024e10:	e06e      	b.n	8024ef0 <pb_check_proto3_default_value+0x230>
+        }
+        else if (PB_LTYPE_IS_SUBMSG(type))
+ 8024e12:	f897 3045 	ldrb.w	r3, [r7, #69]	@ 0x45
+ 8024e16:	f003 030f 	and.w	r3, r3, #15
+ 8024e1a:	2b08      	cmp	r3, #8
+ 8024e1c:	d005      	beq.n	8024e2a <pb_check_proto3_default_value+0x16a>
+ 8024e1e:	f897 3045 	ldrb.w	r3, [r7, #69]	@ 0x45
+ 8024e22:	f003 030f 	and.w	r3, r3, #15
+ 8024e26:	2b09      	cmp	r3, #9
+ 8024e28:	d161      	bne.n	8024eee <pb_check_proto3_default_value+0x22e>
+             * because the C struct may contain padding bytes that must
+             * be skipped. Note that usually proto3 submessages have
+             * a separate has_field that is checked earlier in this if.
+             */
+            pb_field_iter_t iter;
+            if (pb_field_iter_begin(&iter, field->submsg_desc, field->pData))
+ 8024e2a:	687b      	ldr	r3, [r7, #4]
+ 8024e2c:	6a59      	ldr	r1, [r3, #36]	@ 0x24
+ 8024e2e:	687b      	ldr	r3, [r7, #4]
+ 8024e30:	69da      	ldr	r2, [r3, #28]
+ 8024e32:	f107 030c 	add.w	r3, r7, #12
+ 8024e36:	4618      	mov	r0, r3
+ 8024e38:	f7fd fe36 	bl	8022aa8 <pb_field_iter_begin>
+ 8024e3c:	4603      	mov	r3, r0
+ 8024e3e:	2b00      	cmp	r3, #0
+ 8024e40:	d014      	beq.n	8024e6c <pb_check_proto3_default_value+0x1ac>
+            {
+                do
+                {
+                    if (!pb_check_proto3_default_value(&iter))
+ 8024e42:	f107 030c 	add.w	r3, r7, #12
+ 8024e46:	4618      	mov	r0, r3
+ 8024e48:	f7ff ff3a 	bl	8024cc0 <pb_check_proto3_default_value>
+ 8024e4c:	4603      	mov	r3, r0
+ 8024e4e:	f083 0301 	eor.w	r3, r3, #1
+ 8024e52:	b2db      	uxtb	r3, r3
+ 8024e54:	2b00      	cmp	r3, #0
+ 8024e56:	d001      	beq.n	8024e5c <pb_check_proto3_default_value+0x19c>
+                    {
+                        return false;
+ 8024e58:	2300      	movs	r3, #0
+ 8024e5a:	e049      	b.n	8024ef0 <pb_check_proto3_default_value+0x230>
+                    }
+                } while (pb_field_iter_next(&iter));
+ 8024e5c:	f107 030c 	add.w	r3, r7, #12
+ 8024e60:	4618      	mov	r0, r3
+ 8024e62:	f7fd fe6a 	bl	8022b3a <pb_field_iter_next>
+ 8024e66:	4603      	mov	r3, r0
+ 8024e68:	2b00      	cmp	r3, #0
+ 8024e6a:	d1ea      	bne.n	8024e42 <pb_check_proto3_default_value+0x182>
+            }
+            return true;
+ 8024e6c:	2301      	movs	r3, #1
+ 8024e6e:	e03f      	b.n	8024ef0 <pb_check_proto3_default_value+0x230>
+        }
+    }
+    else if (PB_ATYPE(type) == PB_ATYPE_POINTER)
+ 8024e70:	f897 3045 	ldrb.w	r3, [r7, #69]	@ 0x45
+ 8024e74:	f003 03c0 	and.w	r3, r3, #192	@ 0xc0
+ 8024e78:	2b80      	cmp	r3, #128	@ 0x80
+ 8024e7a:	d107      	bne.n	8024e8c <pb_check_proto3_default_value+0x1cc>
+    {
+        return field->pData == NULL;
+ 8024e7c:	687b      	ldr	r3, [r7, #4]
+ 8024e7e:	69db      	ldr	r3, [r3, #28]
+ 8024e80:	2b00      	cmp	r3, #0
+ 8024e82:	bf0c      	ite	eq
+ 8024e84:	2301      	moveq	r3, #1
+ 8024e86:	2300      	movne	r3, #0
+ 8024e88:	b2db      	uxtb	r3, r3
+ 8024e8a:	e031      	b.n	8024ef0 <pb_check_proto3_default_value+0x230>
+    }
+    else if (PB_ATYPE(type) == PB_ATYPE_CALLBACK)
+ 8024e8c:	f897 3045 	ldrb.w	r3, [r7, #69]	@ 0x45
+ 8024e90:	f003 03c0 	and.w	r3, r3, #192	@ 0xc0
+ 8024e94:	2b40      	cmp	r3, #64	@ 0x40
+ 8024e96:	d12a      	bne.n	8024eee <pb_check_proto3_default_value+0x22e>
+    {
+        if (PB_LTYPE(type) == PB_LTYPE_EXTENSION)
+ 8024e98:	f897 3045 	ldrb.w	r3, [r7, #69]	@ 0x45
+ 8024e9c:	f003 030f 	and.w	r3, r3, #15
+ 8024ea0:	2b0a      	cmp	r3, #10
+ 8024ea2:	d10a      	bne.n	8024eba <pb_check_proto3_default_value+0x1fa>
+        {
+            const pb_extension_t *extension = *(const pb_extension_t* const *)field->pData;
+ 8024ea4:	687b      	ldr	r3, [r7, #4]
+ 8024ea6:	69db      	ldr	r3, [r3, #28]
+ 8024ea8:	681b      	ldr	r3, [r3, #0]
+ 8024eaa:	63fb      	str	r3, [r7, #60]	@ 0x3c
+            return extension == NULL;
+ 8024eac:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
+ 8024eae:	2b00      	cmp	r3, #0
+ 8024eb0:	bf0c      	ite	eq
+ 8024eb2:	2301      	moveq	r3, #1
+ 8024eb4:	2300      	movne	r3, #0
+ 8024eb6:	b2db      	uxtb	r3, r3
+ 8024eb8:	e01a      	b.n	8024ef0 <pb_check_proto3_default_value+0x230>
+        }
+        else if (field->descriptor->field_callback == pb_default_field_callback)
+ 8024eba:	687b      	ldr	r3, [r7, #4]
+ 8024ebc:	681b      	ldr	r3, [r3, #0]
+ 8024ebe:	68db      	ldr	r3, [r3, #12]
+ 8024ec0:	4a0d      	ldr	r2, [pc, #52]	@ (8024ef8 <pb_check_proto3_default_value+0x238>)
+ 8024ec2:	4293      	cmp	r3, r2
+ 8024ec4:	d10a      	bne.n	8024edc <pb_check_proto3_default_value+0x21c>
+        {
+            pb_callback_t *pCallback = (pb_callback_t*)field->pData;
+ 8024ec6:	687b      	ldr	r3, [r7, #4]
+ 8024ec8:	69db      	ldr	r3, [r3, #28]
+ 8024eca:	643b      	str	r3, [r7, #64]	@ 0x40
+            return pCallback->funcs.encode == NULL;
+ 8024ecc:	6c3b      	ldr	r3, [r7, #64]	@ 0x40
+ 8024ece:	681b      	ldr	r3, [r3, #0]
+ 8024ed0:	2b00      	cmp	r3, #0
+ 8024ed2:	bf0c      	ite	eq
+ 8024ed4:	2301      	moveq	r3, #1
+ 8024ed6:	2300      	movne	r3, #0
+ 8024ed8:	b2db      	uxtb	r3, r3
+ 8024eda:	e009      	b.n	8024ef0 <pb_check_proto3_default_value+0x230>
+        }
+        else
+        {
+            return field->descriptor->field_callback == NULL;
+ 8024edc:	687b      	ldr	r3, [r7, #4]
+ 8024ede:	681b      	ldr	r3, [r3, #0]
+ 8024ee0:	68db      	ldr	r3, [r3, #12]
+ 8024ee2:	2b00      	cmp	r3, #0
+ 8024ee4:	bf0c      	ite	eq
+ 8024ee6:	2301      	moveq	r3, #1
+ 8024ee8:	2300      	movne	r3, #0
+ 8024eea:	b2db      	uxtb	r3, r3
+ 8024eec:	e000      	b.n	8024ef0 <pb_check_proto3_default_value+0x230>
+        }
+    }
+
+    return false; /* Not typically reached, safe default for weird special cases. */
+ 8024eee:	2300      	movs	r3, #0
+}
+ 8024ef0:	4618      	mov	r0, r3
+ 8024ef2:	3748      	adds	r7, #72	@ 0x48
+ 8024ef4:	46bd      	mov	sp, r7
+ 8024ef6:	bd80      	pop	{r7, pc}
+ 8024ef8:	08022cdd 	.word	0x08022cdd
+
+08024efc <encode_basic_field>:
+
+/* Encode a field with static or pointer allocation, i.e. one whose data
+ * is available to the encoder directly. */
+static bool checkreturn encode_basic_field(pb_ostream_t *stream, const pb_field_iter_t *field)
+{
+ 8024efc:	b580      	push	{r7, lr}
+ 8024efe:	b082      	sub	sp, #8
+ 8024f00:	af00      	add	r7, sp, #0
+ 8024f02:	6078      	str	r0, [r7, #4]
+ 8024f04:	6039      	str	r1, [r7, #0]
+    if (!field->pData)
+ 8024f06:	683b      	ldr	r3, [r7, #0]
+ 8024f08:	69db      	ldr	r3, [r3, #28]
+ 8024f0a:	2b00      	cmp	r3, #0
+ 8024f0c:	d101      	bne.n	8024f12 <encode_basic_field+0x16>
+    {
+        /* Missing pointer field */
+        return true;
+ 8024f0e:	2301      	movs	r3, #1
+ 8024f10:	e061      	b.n	8024fd6 <encode_basic_field+0xda>
+    }
+
+    if (!pb_encode_tag_for_field(stream, field))
+ 8024f12:	6839      	ldr	r1, [r7, #0]
+ 8024f14:	6878      	ldr	r0, [r7, #4]
+ 8024f16:	f000 fab9 	bl	802548c <pb_encode_tag_for_field>
+ 8024f1a:	4603      	mov	r3, r0
+ 8024f1c:	f083 0301 	eor.w	r3, r3, #1
+ 8024f20:	b2db      	uxtb	r3, r3
+ 8024f22:	2b00      	cmp	r3, #0
+ 8024f24:	d001      	beq.n	8024f2a <encode_basic_field+0x2e>
+        return false;
+ 8024f26:	2300      	movs	r3, #0
+ 8024f28:	e055      	b.n	8024fd6 <encode_basic_field+0xda>
+
+    switch (PB_LTYPE(field->type))
+ 8024f2a:	683b      	ldr	r3, [r7, #0]
+ 8024f2c:	7d9b      	ldrb	r3, [r3, #22]
+ 8024f2e:	f003 030f 	and.w	r3, r3, #15
+ 8024f32:	2b0b      	cmp	r3, #11
+ 8024f34:	d844      	bhi.n	8024fc0 <encode_basic_field+0xc4>
+ 8024f36:	a201      	add	r2, pc, #4	@ (adr r2, 8024f3c <encode_basic_field+0x40>)
+ 8024f38:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 8024f3c:	08024f6d 	.word	0x08024f6d
+ 8024f40:	08024f79 	.word	0x08024f79
+ 8024f44:	08024f79 	.word	0x08024f79
+ 8024f48:	08024f79 	.word	0x08024f79
+ 8024f4c:	08024f85 	.word	0x08024f85
+ 8024f50:	08024f85 	.word	0x08024f85
+ 8024f54:	08024f91 	.word	0x08024f91
+ 8024f58:	08024f9d 	.word	0x08024f9d
+ 8024f5c:	08024fa9 	.word	0x08024fa9
+ 8024f60:	08024fa9 	.word	0x08024fa9
+ 8024f64:	08024fc1 	.word	0x08024fc1
+ 8024f68:	08024fb5 	.word	0x08024fb5
+    {
+        case PB_LTYPE_BOOL:
+            return pb_enc_bool(stream, field);
+ 8024f6c:	6839      	ldr	r1, [r7, #0]
+ 8024f6e:	6878      	ldr	r0, [r7, #4]
+ 8024f70:	f000 fb8a 	bl	8025688 <pb_enc_bool>
+ 8024f74:	4603      	mov	r3, r0
+ 8024f76:	e02e      	b.n	8024fd6 <encode_basic_field+0xda>
+
+        case PB_LTYPE_VARINT:
+        case PB_LTYPE_UVARINT:
+        case PB_LTYPE_SVARINT:
+            return pb_enc_varint(stream, field);
+ 8024f78:	6839      	ldr	r1, [r7, #0]
+ 8024f7a:	6878      	ldr	r0, [r7, #4]
+ 8024f7c:	f000 fb9e 	bl	80256bc <pb_enc_varint>
+ 8024f80:	4603      	mov	r3, r0
+ 8024f82:	e028      	b.n	8024fd6 <encode_basic_field+0xda>
+
+        case PB_LTYPE_FIXED32:
+        case PB_LTYPE_FIXED64:
+            return pb_enc_fixed(stream, field);
+ 8024f84:	6839      	ldr	r1, [r7, #0]
+ 8024f86:	6878      	ldr	r0, [r7, #4]
+ 8024f88:	f000 fc5a 	bl	8025840 <pb_enc_fixed>
+ 8024f8c:	4603      	mov	r3, r0
+ 8024f8e:	e022      	b.n	8024fd6 <encode_basic_field+0xda>
+
+        case PB_LTYPE_BYTES:
+            return pb_enc_bytes(stream, field);
+ 8024f90:	6839      	ldr	r1, [r7, #0]
+ 8024f92:	6878      	ldr	r0, [r7, #4]
+ 8024f94:	f000 fc82 	bl	802589c <pb_enc_bytes>
+ 8024f98:	4603      	mov	r3, r0
+ 8024f9a:	e01c      	b.n	8024fd6 <encode_basic_field+0xda>
+
+        case PB_LTYPE_STRING:
+            return pb_enc_string(stream, field);
+ 8024f9c:	6839      	ldr	r1, [r7, #0]
+ 8024f9e:	6878      	ldr	r0, [r7, #4]
+ 8024fa0:	f000 fcba 	bl	8025918 <pb_enc_string>
+ 8024fa4:	4603      	mov	r3, r0
+ 8024fa6:	e016      	b.n	8024fd6 <encode_basic_field+0xda>
+
+        case PB_LTYPE_SUBMESSAGE:
+        case PB_LTYPE_SUBMSG_W_CB:
+            return pb_enc_submessage(stream, field);
+ 8024fa8:	6839      	ldr	r1, [r7, #0]
+ 8024faa:	6878      	ldr	r0, [r7, #4]
+ 8024fac:	f000 fd12 	bl	80259d4 <pb_enc_submessage>
+ 8024fb0:	4603      	mov	r3, r0
+ 8024fb2:	e010      	b.n	8024fd6 <encode_basic_field+0xda>
+
+        case PB_LTYPE_FIXED_LENGTH_BYTES:
+            return pb_enc_fixed_length_bytes(stream, field);
+ 8024fb4:	6839      	ldr	r1, [r7, #0]
+ 8024fb6:	6878      	ldr	r0, [r7, #4]
+ 8024fb8:	f000 fd52 	bl	8025a60 <pb_enc_fixed_length_bytes>
+ 8024fbc:	4603      	mov	r3, r0
+ 8024fbe:	e00a      	b.n	8024fd6 <encode_basic_field+0xda>
+
+        default:
+            PB_RETURN_ERROR(stream, "invalid field type");
+ 8024fc0:	687b      	ldr	r3, [r7, #4]
+ 8024fc2:	691b      	ldr	r3, [r3, #16]
+ 8024fc4:	2b00      	cmp	r3, #0
+ 8024fc6:	d002      	beq.n	8024fce <encode_basic_field+0xd2>
+ 8024fc8:	687b      	ldr	r3, [r7, #4]
+ 8024fca:	691b      	ldr	r3, [r3, #16]
+ 8024fcc:	e000      	b.n	8024fd0 <encode_basic_field+0xd4>
+ 8024fce:	4b04      	ldr	r3, [pc, #16]	@ (8024fe0 <encode_basic_field+0xe4>)
+ 8024fd0:	687a      	ldr	r2, [r7, #4]
+ 8024fd2:	6113      	str	r3, [r2, #16]
+ 8024fd4:	2300      	movs	r3, #0
+    }
+}
+ 8024fd6:	4618      	mov	r0, r3
+ 8024fd8:	3708      	adds	r7, #8
+ 8024fda:	46bd      	mov	sp, r7
+ 8024fdc:	bd80      	pop	{r7, pc}
+ 8024fde:	bf00      	nop
+ 8024fe0:	08041204 	.word	0x08041204
+
+08024fe4 <encode_callback_field>:
+
+/* Encode a field with callback semantics. This means that a user function is
+ * called to provide and encode the actual data. */
+static bool checkreturn encode_callback_field(pb_ostream_t *stream, const pb_field_iter_t *field)
+{
+ 8024fe4:	b580      	push	{r7, lr}
+ 8024fe6:	b082      	sub	sp, #8
+ 8024fe8:	af00      	add	r7, sp, #0
+ 8024fea:	6078      	str	r0, [r7, #4]
+ 8024fec:	6039      	str	r1, [r7, #0]
+    if (field->descriptor->field_callback != NULL)
+ 8024fee:	683b      	ldr	r3, [r7, #0]
+ 8024ff0:	681b      	ldr	r3, [r3, #0]
+ 8024ff2:	68db      	ldr	r3, [r3, #12]
+ 8024ff4:	2b00      	cmp	r3, #0
+ 8024ff6:	d018      	beq.n	802502a <encode_callback_field+0x46>
+    {
+        if (!field->descriptor->field_callback(NULL, stream, field))
+ 8024ff8:	683b      	ldr	r3, [r7, #0]
+ 8024ffa:	681b      	ldr	r3, [r3, #0]
+ 8024ffc:	68db      	ldr	r3, [r3, #12]
+ 8024ffe:	683a      	ldr	r2, [r7, #0]
+ 8025000:	6879      	ldr	r1, [r7, #4]
+ 8025002:	2000      	movs	r0, #0
+ 8025004:	4798      	blx	r3
+ 8025006:	4603      	mov	r3, r0
+ 8025008:	f083 0301 	eor.w	r3, r3, #1
+ 802500c:	b2db      	uxtb	r3, r3
+ 802500e:	2b00      	cmp	r3, #0
+ 8025010:	d00b      	beq.n	802502a <encode_callback_field+0x46>
+            PB_RETURN_ERROR(stream, "callback error");
+ 8025012:	687b      	ldr	r3, [r7, #4]
+ 8025014:	691b      	ldr	r3, [r3, #16]
+ 8025016:	2b00      	cmp	r3, #0
+ 8025018:	d002      	beq.n	8025020 <encode_callback_field+0x3c>
+ 802501a:	687b      	ldr	r3, [r7, #4]
+ 802501c:	691b      	ldr	r3, [r3, #16]
+ 802501e:	e000      	b.n	8025022 <encode_callback_field+0x3e>
+ 8025020:	4b04      	ldr	r3, [pc, #16]	@ (8025034 <encode_callback_field+0x50>)
+ 8025022:	687a      	ldr	r2, [r7, #4]
+ 8025024:	6113      	str	r3, [r2, #16]
+ 8025026:	2300      	movs	r3, #0
+ 8025028:	e000      	b.n	802502c <encode_callback_field+0x48>
+    }
+    return true;
+ 802502a:	2301      	movs	r3, #1
+}
+ 802502c:	4618      	mov	r0, r3
+ 802502e:	3708      	adds	r7, #8
+ 8025030:	46bd      	mov	sp, r7
+ 8025032:	bd80      	pop	{r7, pc}
+ 8025034:	08041218 	.word	0x08041218
+
+08025038 <encode_field>:
+
+/* Encode a single field of any callback, pointer or static type. */
+static bool checkreturn encode_field(pb_ostream_t *stream, pb_field_iter_t *field)
+{
+ 8025038:	b580      	push	{r7, lr}
+ 802503a:	b082      	sub	sp, #8
+ 802503c:	af00      	add	r7, sp, #0
+ 802503e:	6078      	str	r0, [r7, #4]
+ 8025040:	6039      	str	r1, [r7, #0]
+    /* Check field presence */
+    if (PB_HTYPE(field->type) == PB_HTYPE_ONEOF)
+ 8025042:	683b      	ldr	r3, [r7, #0]
+ 8025044:	7d9b      	ldrb	r3, [r3, #22]
+ 8025046:	f003 0330 	and.w	r3, r3, #48	@ 0x30
+ 802504a:	2b30      	cmp	r3, #48	@ 0x30
+ 802504c:	d108      	bne.n	8025060 <encode_field+0x28>
+    {
+        if (*(const pb_size_t*)field->pSize != field->tag)
+ 802504e:	683b      	ldr	r3, [r7, #0]
+ 8025050:	6a1b      	ldr	r3, [r3, #32]
+ 8025052:	881a      	ldrh	r2, [r3, #0]
+ 8025054:	683b      	ldr	r3, [r7, #0]
+ 8025056:	8a1b      	ldrh	r3, [r3, #16]
+ 8025058:	429a      	cmp	r2, r3
+ 802505a:	d026      	beq.n	80250aa <encode_field+0x72>
+        {
+            /* Different type oneof field */
+            return true;
+ 802505c:	2301      	movs	r3, #1
+ 802505e:	e059      	b.n	8025114 <encode_field+0xdc>
+        }
+    }
+    else if (PB_HTYPE(field->type) == PB_HTYPE_OPTIONAL)
+ 8025060:	683b      	ldr	r3, [r7, #0]
+ 8025062:	7d9b      	ldrb	r3, [r3, #22]
+ 8025064:	f003 0330 	and.w	r3, r3, #48	@ 0x30
+ 8025068:	2b10      	cmp	r3, #16
+ 802506a:	d11e      	bne.n	80250aa <encode_field+0x72>
+    {
+        if (field->pSize)
+ 802506c:	683b      	ldr	r3, [r7, #0]
+ 802506e:	6a1b      	ldr	r3, [r3, #32]
+ 8025070:	2b00      	cmp	r3, #0
+ 8025072:	d00c      	beq.n	802508e <encode_field+0x56>
+        {
+            if (safe_read_bool(field->pSize) == false)
+ 8025074:	683b      	ldr	r3, [r7, #0]
+ 8025076:	6a1b      	ldr	r3, [r3, #32]
+ 8025078:	4618      	mov	r0, r3
+ 802507a:	f7ff fcaf 	bl	80249dc <safe_read_bool>
+ 802507e:	4603      	mov	r3, r0
+ 8025080:	f083 0301 	eor.w	r3, r3, #1
+ 8025084:	b2db      	uxtb	r3, r3
+ 8025086:	2b00      	cmp	r3, #0
+ 8025088:	d00f      	beq.n	80250aa <encode_field+0x72>
+            {
+                /* Missing optional field */
+                return true;
+ 802508a:	2301      	movs	r3, #1
+ 802508c:	e042      	b.n	8025114 <encode_field+0xdc>
+            }
+        }
+        else if (PB_ATYPE(field->type) == PB_ATYPE_STATIC)
+ 802508e:	683b      	ldr	r3, [r7, #0]
+ 8025090:	7d9b      	ldrb	r3, [r3, #22]
+ 8025092:	f003 03c0 	and.w	r3, r3, #192	@ 0xc0
+ 8025096:	2b00      	cmp	r3, #0
+ 8025098:	d107      	bne.n	80250aa <encode_field+0x72>
+        {
+            /* Proto3 singular field */
+            if (pb_check_proto3_default_value(field))
+ 802509a:	6838      	ldr	r0, [r7, #0]
+ 802509c:	f7ff fe10 	bl	8024cc0 <pb_check_proto3_default_value>
+ 80250a0:	4603      	mov	r3, r0
+ 80250a2:	2b00      	cmp	r3, #0
+ 80250a4:	d001      	beq.n	80250aa <encode_field+0x72>
+                return true;
+ 80250a6:	2301      	movs	r3, #1
+ 80250a8:	e034      	b.n	8025114 <encode_field+0xdc>
+        }
+    }
+
+    if (!field->pData)
+ 80250aa:	683b      	ldr	r3, [r7, #0]
+ 80250ac:	69db      	ldr	r3, [r3, #28]
+ 80250ae:	2b00      	cmp	r3, #0
+ 80250b0:	d113      	bne.n	80250da <encode_field+0xa2>
+    {
+        if (PB_HTYPE(field->type) == PB_HTYPE_REQUIRED)
+ 80250b2:	683b      	ldr	r3, [r7, #0]
+ 80250b4:	7d9b      	ldrb	r3, [r3, #22]
+ 80250b6:	f003 0330 	and.w	r3, r3, #48	@ 0x30
+ 80250ba:	2b00      	cmp	r3, #0
+ 80250bc:	d10b      	bne.n	80250d6 <encode_field+0x9e>
+            PB_RETURN_ERROR(stream, "missing required field");
+ 80250be:	687b      	ldr	r3, [r7, #4]
+ 80250c0:	691b      	ldr	r3, [r3, #16]
+ 80250c2:	2b00      	cmp	r3, #0
+ 80250c4:	d002      	beq.n	80250cc <encode_field+0x94>
+ 80250c6:	687b      	ldr	r3, [r7, #4]
+ 80250c8:	691b      	ldr	r3, [r3, #16]
+ 80250ca:	e000      	b.n	80250ce <encode_field+0x96>
+ 80250cc:	4b13      	ldr	r3, [pc, #76]	@ (802511c <encode_field+0xe4>)
+ 80250ce:	687a      	ldr	r2, [r7, #4]
+ 80250d0:	6113      	str	r3, [r2, #16]
+ 80250d2:	2300      	movs	r3, #0
+ 80250d4:	e01e      	b.n	8025114 <encode_field+0xdc>
+
+        /* Pointer field set to NULL */
+        return true;
+ 80250d6:	2301      	movs	r3, #1
+ 80250d8:	e01c      	b.n	8025114 <encode_field+0xdc>
+    }
+
+    /* Then encode field contents */
+    if (PB_ATYPE(field->type) == PB_ATYPE_CALLBACK)
+ 80250da:	683b      	ldr	r3, [r7, #0]
+ 80250dc:	7d9b      	ldrb	r3, [r3, #22]
+ 80250de:	f003 03c0 	and.w	r3, r3, #192	@ 0xc0
+ 80250e2:	2b40      	cmp	r3, #64	@ 0x40
+ 80250e4:	d105      	bne.n	80250f2 <encode_field+0xba>
+    {
+        return encode_callback_field(stream, field);
+ 80250e6:	6839      	ldr	r1, [r7, #0]
+ 80250e8:	6878      	ldr	r0, [r7, #4]
+ 80250ea:	f7ff ff7b 	bl	8024fe4 <encode_callback_field>
+ 80250ee:	4603      	mov	r3, r0
+ 80250f0:	e010      	b.n	8025114 <encode_field+0xdc>
+    }
+    else if (PB_HTYPE(field->type) == PB_HTYPE_REPEATED)
+ 80250f2:	683b      	ldr	r3, [r7, #0]
+ 80250f4:	7d9b      	ldrb	r3, [r3, #22]
+ 80250f6:	f003 0330 	and.w	r3, r3, #48	@ 0x30
+ 80250fa:	2b20      	cmp	r3, #32
+ 80250fc:	d105      	bne.n	802510a <encode_field+0xd2>
+    {
+        return encode_array(stream, field);
+ 80250fe:	6839      	ldr	r1, [r7, #0]
+ 8025100:	6878      	ldr	r0, [r7, #4]
+ 8025102:	f7ff fc89 	bl	8024a18 <encode_array>
+ 8025106:	4603      	mov	r3, r0
+ 8025108:	e004      	b.n	8025114 <encode_field+0xdc>
+    }
+    else
+    {
+        return encode_basic_field(stream, field);
+ 802510a:	6839      	ldr	r1, [r7, #0]
+ 802510c:	6878      	ldr	r0, [r7, #4]
+ 802510e:	f7ff fef5 	bl	8024efc <encode_basic_field>
+ 8025112:	4603      	mov	r3, r0
+    }
+}
+ 8025114:	4618      	mov	r0, r3
+ 8025116:	3708      	adds	r7, #8
+ 8025118:	46bd      	mov	sp, r7
+ 802511a:	bd80      	pop	{r7, pc}
+ 802511c:	08041228 	.word	0x08041228
+
+08025120 <default_extension_encoder>:
+
+/* Default handler for extension fields. Expects to have a pb_msgdesc_t
+ * pointer in the extension->type->arg field, pointing to a message with
+ * only one field in it.  */
+static bool checkreturn default_extension_encoder(pb_ostream_t *stream, const pb_extension_t *extension)
+{
+ 8025120:	b580      	push	{r7, lr}
+ 8025122:	b08c      	sub	sp, #48	@ 0x30
+ 8025124:	af00      	add	r7, sp, #0
+ 8025126:	6078      	str	r0, [r7, #4]
+ 8025128:	6039      	str	r1, [r7, #0]
+    pb_field_iter_t iter;
+
+    if (!pb_field_iter_begin_extension_const(&iter, extension))
+ 802512a:	f107 0308 	add.w	r3, r7, #8
+ 802512e:	6839      	ldr	r1, [r7, #0]
+ 8025130:	4618      	mov	r0, r3
+ 8025132:	f7fd fdc1 	bl	8022cb8 <pb_field_iter_begin_extension_const>
+ 8025136:	4603      	mov	r3, r0
+ 8025138:	f083 0301 	eor.w	r3, r3, #1
+ 802513c:	b2db      	uxtb	r3, r3
+ 802513e:	2b00      	cmp	r3, #0
+ 8025140:	d00b      	beq.n	802515a <default_extension_encoder+0x3a>
+        PB_RETURN_ERROR(stream, "invalid extension");
+ 8025142:	687b      	ldr	r3, [r7, #4]
+ 8025144:	691b      	ldr	r3, [r3, #16]
+ 8025146:	2b00      	cmp	r3, #0
+ 8025148:	d002      	beq.n	8025150 <default_extension_encoder+0x30>
+ 802514a:	687b      	ldr	r3, [r7, #4]
+ 802514c:	691b      	ldr	r3, [r3, #16]
+ 802514e:	e000      	b.n	8025152 <default_extension_encoder+0x32>
+ 8025150:	4b07      	ldr	r3, [pc, #28]	@ (8025170 <default_extension_encoder+0x50>)
+ 8025152:	687a      	ldr	r2, [r7, #4]
+ 8025154:	6113      	str	r3, [r2, #16]
+ 8025156:	2300      	movs	r3, #0
+ 8025158:	e006      	b.n	8025168 <default_extension_encoder+0x48>
+
+    return encode_field(stream, &iter);
+ 802515a:	f107 0308 	add.w	r3, r7, #8
+ 802515e:	4619      	mov	r1, r3
+ 8025160:	6878      	ldr	r0, [r7, #4]
+ 8025162:	f7ff ff69 	bl	8025038 <encode_field>
+ 8025166:	4603      	mov	r3, r0
+}
+ 8025168:	4618      	mov	r0, r3
+ 802516a:	3730      	adds	r7, #48	@ 0x30
+ 802516c:	46bd      	mov	sp, r7
+ 802516e:	bd80      	pop	{r7, pc}
+ 8025170:	08041240 	.word	0x08041240
+
+08025174 <encode_extension_field>:
+
+
+/* Walk through all the registered extensions and give them a chance
+ * to encode themselves. */
+static bool checkreturn encode_extension_field(pb_ostream_t *stream, const pb_field_iter_t *field)
+{
+ 8025174:	b580      	push	{r7, lr}
+ 8025176:	b084      	sub	sp, #16
+ 8025178:	af00      	add	r7, sp, #0
+ 802517a:	6078      	str	r0, [r7, #4]
+ 802517c:	6039      	str	r1, [r7, #0]
+    const pb_extension_t *extension = *(const pb_extension_t* const *)field->pData;
+ 802517e:	683b      	ldr	r3, [r7, #0]
+ 8025180:	69db      	ldr	r3, [r3, #28]
+ 8025182:	681b      	ldr	r3, [r3, #0]
+ 8025184:	60fb      	str	r3, [r7, #12]
+
+    while (extension)
+ 8025186:	e01e      	b.n	80251c6 <encode_extension_field+0x52>
+    {
+        bool status;
+        if (extension->type->encode)
+ 8025188:	68fb      	ldr	r3, [r7, #12]
+ 802518a:	681b      	ldr	r3, [r3, #0]
+ 802518c:	685b      	ldr	r3, [r3, #4]
+ 802518e:	2b00      	cmp	r3, #0
+ 8025190:	d008      	beq.n	80251a4 <encode_extension_field+0x30>
+            status = extension->type->encode(stream, extension);
+ 8025192:	68fb      	ldr	r3, [r7, #12]
+ 8025194:	681b      	ldr	r3, [r3, #0]
+ 8025196:	685b      	ldr	r3, [r3, #4]
+ 8025198:	68f9      	ldr	r1, [r7, #12]
+ 802519a:	6878      	ldr	r0, [r7, #4]
+ 802519c:	4798      	blx	r3
+ 802519e:	4603      	mov	r3, r0
+ 80251a0:	72fb      	strb	r3, [r7, #11]
+ 80251a2:	e005      	b.n	80251b0 <encode_extension_field+0x3c>
+        else
+            status = default_extension_encoder(stream, extension);
+ 80251a4:	68f9      	ldr	r1, [r7, #12]
+ 80251a6:	6878      	ldr	r0, [r7, #4]
+ 80251a8:	f7ff ffba 	bl	8025120 <default_extension_encoder>
+ 80251ac:	4603      	mov	r3, r0
+ 80251ae:	72fb      	strb	r3, [r7, #11]
+
+        if (!status)
+ 80251b0:	7afb      	ldrb	r3, [r7, #11]
+ 80251b2:	f083 0301 	eor.w	r3, r3, #1
+ 80251b6:	b2db      	uxtb	r3, r3
+ 80251b8:	2b00      	cmp	r3, #0
+ 80251ba:	d001      	beq.n	80251c0 <encode_extension_field+0x4c>
+            return false;
+ 80251bc:	2300      	movs	r3, #0
+ 80251be:	e006      	b.n	80251ce <encode_extension_field+0x5a>
+        
+        extension = extension->next;
+ 80251c0:	68fb      	ldr	r3, [r7, #12]
+ 80251c2:	689b      	ldr	r3, [r3, #8]
+ 80251c4:	60fb      	str	r3, [r7, #12]
+    while (extension)
+ 80251c6:	68fb      	ldr	r3, [r7, #12]
+ 80251c8:	2b00      	cmp	r3, #0
+ 80251ca:	d1dd      	bne.n	8025188 <encode_extension_field+0x14>
+    }
+    
+    return true;
+ 80251cc:	2301      	movs	r3, #1
+}
+ 80251ce:	4618      	mov	r0, r3
+ 80251d0:	3710      	adds	r7, #16
+ 80251d2:	46bd      	mov	sp, r7
+ 80251d4:	bd80      	pop	{r7, pc}
+
+080251d6 <pb_encode>:
+/*********************
+ * Encode all fields *
+ *********************/
+
+bool checkreturn pb_encode(pb_ostream_t *stream, const pb_msgdesc_t *fields, const void *src_struct)
+{
+ 80251d6:	b580      	push	{r7, lr}
+ 80251d8:	b08e      	sub	sp, #56	@ 0x38
+ 80251da:	af00      	add	r7, sp, #0
+ 80251dc:	60f8      	str	r0, [r7, #12]
+ 80251de:	60b9      	str	r1, [r7, #8]
+ 80251e0:	607a      	str	r2, [r7, #4]
+    pb_field_iter_t iter;
+    if (!pb_field_iter_begin_const(&iter, fields, src_struct))
+ 80251e2:	f107 0310 	add.w	r3, r7, #16
+ 80251e6:	687a      	ldr	r2, [r7, #4]
+ 80251e8:	68b9      	ldr	r1, [r7, #8]
+ 80251ea:	4618      	mov	r0, r3
+ 80251ec:	f7fd fd50 	bl	8022c90 <pb_field_iter_begin_const>
+ 80251f0:	4603      	mov	r3, r0
+ 80251f2:	f083 0301 	eor.w	r3, r3, #1
+ 80251f6:	b2db      	uxtb	r3, r3
+ 80251f8:	2b00      	cmp	r3, #0
+ 80251fa:	d001      	beq.n	8025200 <pb_encode+0x2a>
+        return true; /* Empty message type */
+ 80251fc:	2301      	movs	r3, #1
+ 80251fe:	e02a      	b.n	8025256 <pb_encode+0x80>
+    
+    do {
+        if (PB_LTYPE(iter.type) == PB_LTYPE_EXTENSION)
+ 8025200:	f897 3026 	ldrb.w	r3, [r7, #38]	@ 0x26
+ 8025204:	f003 030f 	and.w	r3, r3, #15
+ 8025208:	2b0a      	cmp	r3, #10
+ 802520a:	d10d      	bne.n	8025228 <pb_encode+0x52>
+        {
+            /* Special case for the extension field placeholder */
+            if (!encode_extension_field(stream, &iter))
+ 802520c:	f107 0310 	add.w	r3, r7, #16
+ 8025210:	4619      	mov	r1, r3
+ 8025212:	68f8      	ldr	r0, [r7, #12]
+ 8025214:	f7ff ffae 	bl	8025174 <encode_extension_field>
+ 8025218:	4603      	mov	r3, r0
+ 802521a:	f083 0301 	eor.w	r3, r3, #1
+ 802521e:	b2db      	uxtb	r3, r3
+ 8025220:	2b00      	cmp	r3, #0
+ 8025222:	d00f      	beq.n	8025244 <pb_encode+0x6e>
+                return false;
+ 8025224:	2300      	movs	r3, #0
+ 8025226:	e016      	b.n	8025256 <pb_encode+0x80>
+        }
+        else
+        {
+            /* Regular field */
+            if (!encode_field(stream, &iter))
+ 8025228:	f107 0310 	add.w	r3, r7, #16
+ 802522c:	4619      	mov	r1, r3
+ 802522e:	68f8      	ldr	r0, [r7, #12]
+ 8025230:	f7ff ff02 	bl	8025038 <encode_field>
+ 8025234:	4603      	mov	r3, r0
+ 8025236:	f083 0301 	eor.w	r3, r3, #1
+ 802523a:	b2db      	uxtb	r3, r3
+ 802523c:	2b00      	cmp	r3, #0
+ 802523e:	d001      	beq.n	8025244 <pb_encode+0x6e>
+                return false;
+ 8025240:	2300      	movs	r3, #0
+ 8025242:	e008      	b.n	8025256 <pb_encode+0x80>
+        }
+    } while (pb_field_iter_next(&iter));
+ 8025244:	f107 0310 	add.w	r3, r7, #16
+ 8025248:	4618      	mov	r0, r3
+ 802524a:	f7fd fc76 	bl	8022b3a <pb_field_iter_next>
+ 802524e:	4603      	mov	r3, r0
+ 8025250:	2b00      	cmp	r3, #0
+ 8025252:	d1d5      	bne.n	8025200 <pb_encode+0x2a>
+    
+    return true;
+ 8025254:	2301      	movs	r3, #1
+}
+ 8025256:	4618      	mov	r0, r3
+ 8025258:	3738      	adds	r7, #56	@ 0x38
+ 802525a:	46bd      	mov	sp, r7
+ 802525c:	bd80      	pop	{r7, pc}
+
+0802525e <pb_encode_varint_32>:
+ * Helper functions *
+ ********************/
+
+/* This function avoids 64-bit shifts as they are quite slow on many platforms. */
+static bool checkreturn pb_encode_varint_32(pb_ostream_t *stream, uint32_t low, uint32_t high)
+{
+ 802525e:	b580      	push	{r7, lr}
+ 8025260:	b088      	sub	sp, #32
+ 8025262:	af00      	add	r7, sp, #0
+ 8025264:	60f8      	str	r0, [r7, #12]
+ 8025266:	60b9      	str	r1, [r7, #8]
+ 8025268:	607a      	str	r2, [r7, #4]
+    size_t i = 0;
+ 802526a:	2300      	movs	r3, #0
+ 802526c:	61fb      	str	r3, [r7, #28]
+    pb_byte_t buffer[10];
+    pb_byte_t byte = (pb_byte_t)(low & 0x7F);
+ 802526e:	68bb      	ldr	r3, [r7, #8]
+ 8025270:	b2db      	uxtb	r3, r3
+ 8025272:	f003 037f 	and.w	r3, r3, #127	@ 0x7f
+ 8025276:	76fb      	strb	r3, [r7, #27]
+    low >>= 7;
+ 8025278:	68bb      	ldr	r3, [r7, #8]
+ 802527a:	09db      	lsrs	r3, r3, #7
+ 802527c:	60bb      	str	r3, [r7, #8]
+
+    while (i < 4 && (low != 0 || high != 0))
+ 802527e:	e013      	b.n	80252a8 <pb_encode_varint_32+0x4a>
+    {
+        byte |= 0x80;
+ 8025280:	7efb      	ldrb	r3, [r7, #27]
+ 8025282:	f063 037f 	orn	r3, r3, #127	@ 0x7f
+ 8025286:	76fb      	strb	r3, [r7, #27]
+        buffer[i++] = byte;
+ 8025288:	69fb      	ldr	r3, [r7, #28]
+ 802528a:	1c5a      	adds	r2, r3, #1
+ 802528c:	61fa      	str	r2, [r7, #28]
+ 802528e:	3320      	adds	r3, #32
+ 8025290:	443b      	add	r3, r7
+ 8025292:	7efa      	ldrb	r2, [r7, #27]
+ 8025294:	f803 2c10 	strb.w	r2, [r3, #-16]
+        byte = (pb_byte_t)(low & 0x7F);
+ 8025298:	68bb      	ldr	r3, [r7, #8]
+ 802529a:	b2db      	uxtb	r3, r3
+ 802529c:	f003 037f 	and.w	r3, r3, #127	@ 0x7f
+ 80252a0:	76fb      	strb	r3, [r7, #27]
+        low >>= 7;
+ 80252a2:	68bb      	ldr	r3, [r7, #8]
+ 80252a4:	09db      	lsrs	r3, r3, #7
+ 80252a6:	60bb      	str	r3, [r7, #8]
+    while (i < 4 && (low != 0 || high != 0))
+ 80252a8:	69fb      	ldr	r3, [r7, #28]
+ 80252aa:	2b03      	cmp	r3, #3
+ 80252ac:	d805      	bhi.n	80252ba <pb_encode_varint_32+0x5c>
+ 80252ae:	68bb      	ldr	r3, [r7, #8]
+ 80252b0:	2b00      	cmp	r3, #0
+ 80252b2:	d1e5      	bne.n	8025280 <pb_encode_varint_32+0x22>
+ 80252b4:	687b      	ldr	r3, [r7, #4]
+ 80252b6:	2b00      	cmp	r3, #0
+ 80252b8:	d1e2      	bne.n	8025280 <pb_encode_varint_32+0x22>
+    }
+
+    if (high)
+ 80252ba:	687b      	ldr	r3, [r7, #4]
+ 80252bc:	2b00      	cmp	r3, #0
+ 80252be:	d024      	beq.n	802530a <pb_encode_varint_32+0xac>
+    {
+        byte = (pb_byte_t)(byte | ((high & 0x07) << 4));
+ 80252c0:	687b      	ldr	r3, [r7, #4]
+ 80252c2:	b2db      	uxtb	r3, r3
+ 80252c4:	011b      	lsls	r3, r3, #4
+ 80252c6:	b2db      	uxtb	r3, r3
+ 80252c8:	f003 0370 	and.w	r3, r3, #112	@ 0x70
+ 80252cc:	b2da      	uxtb	r2, r3
+ 80252ce:	7efb      	ldrb	r3, [r7, #27]
+ 80252d0:	4313      	orrs	r3, r2
+ 80252d2:	76fb      	strb	r3, [r7, #27]
+        high >>= 3;
+ 80252d4:	687b      	ldr	r3, [r7, #4]
+ 80252d6:	08db      	lsrs	r3, r3, #3
+ 80252d8:	607b      	str	r3, [r7, #4]
+
+        while (high)
+ 80252da:	e013      	b.n	8025304 <pb_encode_varint_32+0xa6>
+        {
+            byte |= 0x80;
+ 80252dc:	7efb      	ldrb	r3, [r7, #27]
+ 80252de:	f063 037f 	orn	r3, r3, #127	@ 0x7f
+ 80252e2:	76fb      	strb	r3, [r7, #27]
+            buffer[i++] = byte;
+ 80252e4:	69fb      	ldr	r3, [r7, #28]
+ 80252e6:	1c5a      	adds	r2, r3, #1
+ 80252e8:	61fa      	str	r2, [r7, #28]
+ 80252ea:	3320      	adds	r3, #32
+ 80252ec:	443b      	add	r3, r7
+ 80252ee:	7efa      	ldrb	r2, [r7, #27]
+ 80252f0:	f803 2c10 	strb.w	r2, [r3, #-16]
+            byte = (pb_byte_t)(high & 0x7F);
+ 80252f4:	687b      	ldr	r3, [r7, #4]
+ 80252f6:	b2db      	uxtb	r3, r3
+ 80252f8:	f003 037f 	and.w	r3, r3, #127	@ 0x7f
+ 80252fc:	76fb      	strb	r3, [r7, #27]
+            high >>= 7;
+ 80252fe:	687b      	ldr	r3, [r7, #4]
+ 8025300:	09db      	lsrs	r3, r3, #7
+ 8025302:	607b      	str	r3, [r7, #4]
+        while (high)
+ 8025304:	687b      	ldr	r3, [r7, #4]
+ 8025306:	2b00      	cmp	r3, #0
+ 8025308:	d1e8      	bne.n	80252dc <pb_encode_varint_32+0x7e>
+        }
+    }
+
+    buffer[i++] = byte;
+ 802530a:	69fb      	ldr	r3, [r7, #28]
+ 802530c:	1c5a      	adds	r2, r3, #1
+ 802530e:	61fa      	str	r2, [r7, #28]
+ 8025310:	3320      	adds	r3, #32
+ 8025312:	443b      	add	r3, r7
+ 8025314:	7efa      	ldrb	r2, [r7, #27]
+ 8025316:	f803 2c10 	strb.w	r2, [r3, #-16]
+
+    return pb_write(stream, buffer, i);
+ 802531a:	f107 0310 	add.w	r3, r7, #16
+ 802531e:	69fa      	ldr	r2, [r7, #28]
+ 8025320:	4619      	mov	r1, r3
+ 8025322:	68f8      	ldr	r0, [r7, #12]
+ 8025324:	f7ff fb0a 	bl	802493c <pb_write>
+ 8025328:	4603      	mov	r3, r0
+}
+ 802532a:	4618      	mov	r0, r3
+ 802532c:	3720      	adds	r7, #32
+ 802532e:	46bd      	mov	sp, r7
+ 8025330:	bd80      	pop	{r7, pc}
+
+08025332 <pb_encode_varint>:
+
+bool checkreturn pb_encode_varint(pb_ostream_t *stream, pb_uint64_t value)
+{
+ 8025332:	b590      	push	{r4, r7, lr}
+ 8025334:	b087      	sub	sp, #28
+ 8025336:	af00      	add	r7, sp, #0
+ 8025338:	60f8      	str	r0, [r7, #12]
+ 802533a:	e9c7 2300 	strd	r2, r3, [r7]
+    if (value <= 0x7F)
+ 802533e:	e9d7 2300 	ldrd	r2, r3, [r7]
+ 8025342:	2a80      	cmp	r2, #128	@ 0x80
+ 8025344:	f173 0300 	sbcs.w	r3, r3, #0
+ 8025348:	d20a      	bcs.n	8025360 <pb_encode_varint+0x2e>
+    {
+        /* Fast path: single byte */
+        pb_byte_t byte = (pb_byte_t)value;
+ 802534a:	783b      	ldrb	r3, [r7, #0]
+ 802534c:	75fb      	strb	r3, [r7, #23]
+        return pb_write(stream, &byte, 1);
+ 802534e:	f107 0317 	add.w	r3, r7, #23
+ 8025352:	2201      	movs	r2, #1
+ 8025354:	4619      	mov	r1, r3
+ 8025356:	68f8      	ldr	r0, [r7, #12]
+ 8025358:	f7ff faf0 	bl	802493c <pb_write>
+ 802535c:	4603      	mov	r3, r0
+ 802535e:	e00f      	b.n	8025380 <pb_encode_varint+0x4e>
+    else
+    {
+#ifdef PB_WITHOUT_64BIT
+        return pb_encode_varint_32(stream, value, 0);
+#else
+        return pb_encode_varint_32(stream, (uint32_t)value, (uint32_t)(value >> 32));
+ 8025360:	683c      	ldr	r4, [r7, #0]
+ 8025362:	e9d7 0100 	ldrd	r0, r1, [r7]
+ 8025366:	f04f 0200 	mov.w	r2, #0
+ 802536a:	f04f 0300 	mov.w	r3, #0
+ 802536e:	000a      	movs	r2, r1
+ 8025370:	2300      	movs	r3, #0
+ 8025372:	4613      	mov	r3, r2
+ 8025374:	461a      	mov	r2, r3
+ 8025376:	4621      	mov	r1, r4
+ 8025378:	68f8      	ldr	r0, [r7, #12]
+ 802537a:	f7ff ff70 	bl	802525e <pb_encode_varint_32>
+ 802537e:	4603      	mov	r3, r0
+#endif
+    }
+}
+ 8025380:	4618      	mov	r0, r3
+ 8025382:	371c      	adds	r7, #28
+ 8025384:	46bd      	mov	sp, r7
+ 8025386:	bd90      	pop	{r4, r7, pc}
+
+08025388 <pb_encode_svarint>:
+
+bool checkreturn pb_encode_svarint(pb_ostream_t *stream, pb_int64_t value)
+{
+ 8025388:	e92d 4fb0 	stmdb	sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
+ 802538c:	b08a      	sub	sp, #40	@ 0x28
+ 802538e:	af00      	add	r7, sp, #0
+ 8025390:	6178      	str	r0, [r7, #20]
+ 8025392:	e9c7 2302 	strd	r2, r3, [r7, #8]
+    pb_uint64_t zigzagged;
+    pb_uint64_t mask = ((pb_uint64_t)-1) >> 1; /* Satisfy clang -fsanitize=integer */
+ 8025396:	f04f 32ff 	mov.w	r2, #4294967295
+ 802539a:	f06f 4300 	mvn.w	r3, #2147483648	@ 0x80000000
+ 802539e:	e9c7 2306 	strd	r2, r3, [r7, #24]
+    if (value < 0)
+ 80253a2:	e9d7 2302 	ldrd	r2, r3, [r7, #8]
+ 80253a6:	2b00      	cmp	r3, #0
+ 80253a8:	da15      	bge.n	80253d6 <pb_encode_svarint+0x4e>
+        zigzagged = ~(((pb_uint64_t)value & mask) << 1);
+ 80253aa:	e9d7 0102 	ldrd	r0, r1, [r7, #8]
+ 80253ae:	e9d7 2306 	ldrd	r2, r3, [r7, #24]
+ 80253b2:	ea00 0402 	and.w	r4, r0, r2
+ 80253b6:	ea01 0503 	and.w	r5, r1, r3
+ 80253ba:	1923      	adds	r3, r4, r4
+ 80253bc:	603b      	str	r3, [r7, #0]
+ 80253be:	eb45 0305 	adc.w	r3, r5, r5
+ 80253c2:	607b      	str	r3, [r7, #4]
+ 80253c4:	e9d7 2300 	ldrd	r2, r3, [r7]
+ 80253c8:	ea6f 0a02 	mvn.w	sl, r2
+ 80253cc:	ea6f 0b03 	mvn.w	fp, r3
+ 80253d0:	e9c7 ab08 	strd	sl, fp, [r7, #32]
+ 80253d4:	e007      	b.n	80253e6 <pb_encode_svarint+0x5e>
+    else
+        zigzagged = (pb_uint64_t)value << 1;
+ 80253d6:	e9d7 2302 	ldrd	r2, r3, [r7, #8]
+ 80253da:	eb12 0802 	adds.w	r8, r2, r2
+ 80253de:	eb43 0903 	adc.w	r9, r3, r3
+ 80253e2:	e9c7 8908 	strd	r8, r9, [r7, #32]
+    
+    return pb_encode_varint(stream, zigzagged);
+ 80253e6:	e9d7 2308 	ldrd	r2, r3, [r7, #32]
+ 80253ea:	6978      	ldr	r0, [r7, #20]
+ 80253ec:	f7ff ffa1 	bl	8025332 <pb_encode_varint>
+ 80253f0:	4603      	mov	r3, r0
+}
+ 80253f2:	4618      	mov	r0, r3
+ 80253f4:	3728      	adds	r7, #40	@ 0x28
+ 80253f6:	46bd      	mov	sp, r7
+ 80253f8:	e8bd 8fb0 	ldmia.w	sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
+
+080253fc <pb_encode_fixed32>:
+
+bool checkreturn pb_encode_fixed32(pb_ostream_t *stream, const void *value)
+{
+ 80253fc:	b580      	push	{r7, lr}
+ 80253fe:	b082      	sub	sp, #8
+ 8025400:	af00      	add	r7, sp, #0
+ 8025402:	6078      	str	r0, [r7, #4]
+ 8025404:	6039      	str	r1, [r7, #0]
+#if defined(PB_LITTLE_ENDIAN_8BIT) && PB_LITTLE_ENDIAN_8BIT == 1
+    /* Fast path if we know that we're on little endian */
+    return pb_write(stream, (const pb_byte_t*)value, 4);
+ 8025406:	2204      	movs	r2, #4
+ 8025408:	6839      	ldr	r1, [r7, #0]
+ 802540a:	6878      	ldr	r0, [r7, #4]
+ 802540c:	f7ff fa96 	bl	802493c <pb_write>
+ 8025410:	4603      	mov	r3, r0
+    bytes[1] = (pb_byte_t)((val >> 8) & 0xFF);
+    bytes[2] = (pb_byte_t)((val >> 16) & 0xFF);
+    bytes[3] = (pb_byte_t)((val >> 24) & 0xFF);
+    return pb_write(stream, bytes, 4);
+#endif
+}
+ 8025412:	4618      	mov	r0, r3
+ 8025414:	3708      	adds	r7, #8
+ 8025416:	46bd      	mov	sp, r7
+ 8025418:	bd80      	pop	{r7, pc}
+
+0802541a <pb_encode_fixed64>:
+
+#ifndef PB_WITHOUT_64BIT
+bool checkreturn pb_encode_fixed64(pb_ostream_t *stream, const void *value)
+{
+ 802541a:	b580      	push	{r7, lr}
+ 802541c:	b082      	sub	sp, #8
+ 802541e:	af00      	add	r7, sp, #0
+ 8025420:	6078      	str	r0, [r7, #4]
+ 8025422:	6039      	str	r1, [r7, #0]
+#if defined(PB_LITTLE_ENDIAN_8BIT) && PB_LITTLE_ENDIAN_8BIT == 1
+    /* Fast path if we know that we're on little endian */
+    return pb_write(stream, (const pb_byte_t*)value, 8);
+ 8025424:	2208      	movs	r2, #8
+ 8025426:	6839      	ldr	r1, [r7, #0]
+ 8025428:	6878      	ldr	r0, [r7, #4]
+ 802542a:	f7ff fa87 	bl	802493c <pb_write>
+ 802542e:	4603      	mov	r3, r0
+    bytes[5] = (pb_byte_t)((val >> 40) & 0xFF);
+    bytes[6] = (pb_byte_t)((val >> 48) & 0xFF);
+    bytes[7] = (pb_byte_t)((val >> 56) & 0xFF);
+    return pb_write(stream, bytes, 8);
+#endif
+}
+ 8025430:	4618      	mov	r0, r3
+ 8025432:	3708      	adds	r7, #8
+ 8025434:	46bd      	mov	sp, r7
+ 8025436:	bd80      	pop	{r7, pc}
+
+08025438 <pb_encode_tag>:
+#endif
+
+bool checkreturn pb_encode_tag(pb_ostream_t *stream, pb_wire_type_t wiretype, uint32_t field_number)
+{
+ 8025438:	e92d 4fb0 	stmdb	sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
+ 802543c:	b088      	sub	sp, #32
+ 802543e:	af00      	add	r7, sp, #0
+ 8025440:	6178      	str	r0, [r7, #20]
+ 8025442:	460b      	mov	r3, r1
+ 8025444:	60fa      	str	r2, [r7, #12]
+ 8025446:	74fb      	strb	r3, [r7, #19]
+    pb_uint64_t tag = ((pb_uint64_t)field_number << 3) | wiretype;
+ 8025448:	68fb      	ldr	r3, [r7, #12]
+ 802544a:	2200      	movs	r2, #0
+ 802544c:	469a      	mov	sl, r3
+ 802544e:	4693      	mov	fp, r2
+ 8025450:	ea4f 755a 	mov.w	r5, sl, lsr #29
+ 8025454:	ea4f 04ca 	mov.w	r4, sl, lsl #3
+ 8025458:	7cfb      	ldrb	r3, [r7, #19]
+ 802545a:	2200      	movs	r2, #0
+ 802545c:	4698      	mov	r8, r3
+ 802545e:	4691      	mov	r9, r2
+ 8025460:	ea44 0308 	orr.w	r3, r4, r8
+ 8025464:	603b      	str	r3, [r7, #0]
+ 8025466:	ea45 0309 	orr.w	r3, r5, r9
+ 802546a:	607b      	str	r3, [r7, #4]
+ 802546c:	e9d7 3400 	ldrd	r3, r4, [r7]
+ 8025470:	e9c7 3406 	strd	r3, r4, [r7, #24]
+    return pb_encode_varint(stream, tag);
+ 8025474:	e9d7 2306 	ldrd	r2, r3, [r7, #24]
+ 8025478:	6978      	ldr	r0, [r7, #20]
+ 802547a:	f7ff ff5a 	bl	8025332 <pb_encode_varint>
+ 802547e:	4603      	mov	r3, r0
+}
+ 8025480:	4618      	mov	r0, r3
+ 8025482:	3720      	adds	r7, #32
+ 8025484:	46bd      	mov	sp, r7
+ 8025486:	e8bd 8fb0 	ldmia.w	sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
+	...
+
+0802548c <pb_encode_tag_for_field>:
+
+bool pb_encode_tag_for_field ( pb_ostream_t* stream, const pb_field_iter_t* field )
+{
+ 802548c:	b580      	push	{r7, lr}
+ 802548e:	b084      	sub	sp, #16
+ 8025490:	af00      	add	r7, sp, #0
+ 8025492:	6078      	str	r0, [r7, #4]
+ 8025494:	6039      	str	r1, [r7, #0]
+    pb_wire_type_t wiretype;
+    switch (PB_LTYPE(field->type))
+ 8025496:	683b      	ldr	r3, [r7, #0]
+ 8025498:	7d9b      	ldrb	r3, [r3, #22]
+ 802549a:	f003 030f 	and.w	r3, r3, #15
+ 802549e:	2b0b      	cmp	r3, #11
+ 80254a0:	d826      	bhi.n	80254f0 <pb_encode_tag_for_field+0x64>
+ 80254a2:	a201      	add	r2, pc, #4	@ (adr r2, 80254a8 <pb_encode_tag_for_field+0x1c>)
+ 80254a4:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 80254a8:	080254d9 	.word	0x080254d9
+ 80254ac:	080254d9 	.word	0x080254d9
+ 80254b0:	080254d9 	.word	0x080254d9
+ 80254b4:	080254d9 	.word	0x080254d9
+ 80254b8:	080254df 	.word	0x080254df
+ 80254bc:	080254e5 	.word	0x080254e5
+ 80254c0:	080254eb 	.word	0x080254eb
+ 80254c4:	080254eb 	.word	0x080254eb
+ 80254c8:	080254eb 	.word	0x080254eb
+ 80254cc:	080254eb 	.word	0x080254eb
+ 80254d0:	080254f1 	.word	0x080254f1
+ 80254d4:	080254eb 	.word	0x080254eb
+    {
+        case PB_LTYPE_BOOL:
+        case PB_LTYPE_VARINT:
+        case PB_LTYPE_UVARINT:
+        case PB_LTYPE_SVARINT:
+            wiretype = PB_WT_VARINT;
+ 80254d8:	2300      	movs	r3, #0
+ 80254da:	73fb      	strb	r3, [r7, #15]
+            break;
+ 80254dc:	e014      	b.n	8025508 <pb_encode_tag_for_field+0x7c>
+        
+        case PB_LTYPE_FIXED32:
+            wiretype = PB_WT_32BIT;
+ 80254de:	2305      	movs	r3, #5
+ 80254e0:	73fb      	strb	r3, [r7, #15]
+            break;
+ 80254e2:	e011      	b.n	8025508 <pb_encode_tag_for_field+0x7c>
+        
+        case PB_LTYPE_FIXED64:
+            wiretype = PB_WT_64BIT;
+ 80254e4:	2301      	movs	r3, #1
+ 80254e6:	73fb      	strb	r3, [r7, #15]
+            break;
+ 80254e8:	e00e      	b.n	8025508 <pb_encode_tag_for_field+0x7c>
+        case PB_LTYPE_BYTES:
+        case PB_LTYPE_STRING:
+        case PB_LTYPE_SUBMESSAGE:
+        case PB_LTYPE_SUBMSG_W_CB:
+        case PB_LTYPE_FIXED_LENGTH_BYTES:
+            wiretype = PB_WT_STRING;
+ 80254ea:	2302      	movs	r3, #2
+ 80254ec:	73fb      	strb	r3, [r7, #15]
+            break;
+ 80254ee:	e00b      	b.n	8025508 <pb_encode_tag_for_field+0x7c>
+        
+        default:
+            PB_RETURN_ERROR(stream, "invalid field type");
+ 80254f0:	687b      	ldr	r3, [r7, #4]
+ 80254f2:	691b      	ldr	r3, [r3, #16]
+ 80254f4:	2b00      	cmp	r3, #0
+ 80254f6:	d002      	beq.n	80254fe <pb_encode_tag_for_field+0x72>
+ 80254f8:	687b      	ldr	r3, [r7, #4]
+ 80254fa:	691b      	ldr	r3, [r3, #16]
+ 80254fc:	e000      	b.n	8025500 <pb_encode_tag_for_field+0x74>
+ 80254fe:	4b09      	ldr	r3, [pc, #36]	@ (8025524 <pb_encode_tag_for_field+0x98>)
+ 8025500:	687a      	ldr	r2, [r7, #4]
+ 8025502:	6113      	str	r3, [r2, #16]
+ 8025504:	2300      	movs	r3, #0
+ 8025506:	e008      	b.n	802551a <pb_encode_tag_for_field+0x8e>
+    }
+    
+    return pb_encode_tag(stream, wiretype, field->tag);
+ 8025508:	683b      	ldr	r3, [r7, #0]
+ 802550a:	8a1b      	ldrh	r3, [r3, #16]
+ 802550c:	461a      	mov	r2, r3
+ 802550e:	7bfb      	ldrb	r3, [r7, #15]
+ 8025510:	4619      	mov	r1, r3
+ 8025512:	6878      	ldr	r0, [r7, #4]
+ 8025514:	f7ff ff90 	bl	8025438 <pb_encode_tag>
+ 8025518:	4603      	mov	r3, r0
+}
+ 802551a:	4618      	mov	r0, r3
+ 802551c:	3710      	adds	r7, #16
+ 802551e:	46bd      	mov	sp, r7
+ 8025520:	bd80      	pop	{r7, pc}
+ 8025522:	bf00      	nop
+ 8025524:	08041204 	.word	0x08041204
+
+08025528 <pb_encode_string>:
+
+bool checkreturn pb_encode_string(pb_ostream_t *stream, const pb_byte_t *buffer, size_t size)
+{
+ 8025528:	b5b0      	push	{r4, r5, r7, lr}
+ 802552a:	b084      	sub	sp, #16
+ 802552c:	af00      	add	r7, sp, #0
+ 802552e:	60f8      	str	r0, [r7, #12]
+ 8025530:	60b9      	str	r1, [r7, #8]
+ 8025532:	607a      	str	r2, [r7, #4]
+    if (!pb_encode_varint(stream, (pb_uint64_t)size))
+ 8025534:	687b      	ldr	r3, [r7, #4]
+ 8025536:	2200      	movs	r2, #0
+ 8025538:	461c      	mov	r4, r3
+ 802553a:	4615      	mov	r5, r2
+ 802553c:	4622      	mov	r2, r4
+ 802553e:	462b      	mov	r3, r5
+ 8025540:	68f8      	ldr	r0, [r7, #12]
+ 8025542:	f7ff fef6 	bl	8025332 <pb_encode_varint>
+ 8025546:	4603      	mov	r3, r0
+ 8025548:	f083 0301 	eor.w	r3, r3, #1
+ 802554c:	b2db      	uxtb	r3, r3
+ 802554e:	2b00      	cmp	r3, #0
+ 8025550:	d001      	beq.n	8025556 <pb_encode_string+0x2e>
+        return false;
+ 8025552:	2300      	movs	r3, #0
+ 8025554:	e005      	b.n	8025562 <pb_encode_string+0x3a>
+    
+    return pb_write(stream, buffer, size);
+ 8025556:	687a      	ldr	r2, [r7, #4]
+ 8025558:	68b9      	ldr	r1, [r7, #8]
+ 802555a:	68f8      	ldr	r0, [r7, #12]
+ 802555c:	f7ff f9ee 	bl	802493c <pb_write>
+ 8025560:	4603      	mov	r3, r0
+}
+ 8025562:	4618      	mov	r0, r3
+ 8025564:	3710      	adds	r7, #16
+ 8025566:	46bd      	mov	sp, r7
+ 8025568:	bdb0      	pop	{r4, r5, r7, pc}
+	...
+
+0802556c <pb_encode_submessage>:
+
+bool checkreturn pb_encode_submessage(pb_ostream_t *stream, const pb_msgdesc_t *fields, const void *src_struct)
+{
+ 802556c:	b5b0      	push	{r4, r5, r7, lr}
+ 802556e:	b08c      	sub	sp, #48	@ 0x30
+ 8025570:	af00      	add	r7, sp, #0
+ 8025572:	60f8      	str	r0, [r7, #12]
+ 8025574:	60b9      	str	r1, [r7, #8]
+ 8025576:	607a      	str	r2, [r7, #4]
+    /* First calculate the message size using a non-writing substream. */
+    pb_ostream_t substream = PB_OSTREAM_SIZING;
+ 8025578:	f107 0314 	add.w	r3, r7, #20
+ 802557c:	2200      	movs	r2, #0
+ 802557e:	601a      	str	r2, [r3, #0]
+ 8025580:	605a      	str	r2, [r3, #4]
+ 8025582:	609a      	str	r2, [r3, #8]
+ 8025584:	60da      	str	r2, [r3, #12]
+ 8025586:	611a      	str	r2, [r3, #16]
+    size_t size;
+    bool status;
+    
+    if (!pb_encode(&substream, fields, src_struct))
+ 8025588:	f107 0314 	add.w	r3, r7, #20
+ 802558c:	687a      	ldr	r2, [r7, #4]
+ 802558e:	68b9      	ldr	r1, [r7, #8]
+ 8025590:	4618      	mov	r0, r3
+ 8025592:	f7ff fe20 	bl	80251d6 <pb_encode>
+ 8025596:	4603      	mov	r3, r0
+ 8025598:	f083 0301 	eor.w	r3, r3, #1
+ 802559c:	b2db      	uxtb	r3, r3
+ 802559e:	2b00      	cmp	r3, #0
+ 80255a0:	d004      	beq.n	80255ac <pb_encode_submessage+0x40>
+    {
+#ifndef PB_NO_ERRMSG
+        stream->errmsg = substream.errmsg;
+ 80255a2:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
+ 80255a4:	68fb      	ldr	r3, [r7, #12]
+ 80255a6:	611a      	str	r2, [r3, #16]
+#endif
+        return false;
+ 80255a8:	2300      	movs	r3, #0
+ 80255aa:	e065      	b.n	8025678 <pb_encode_submessage+0x10c>
+    }
+    
+    size = substream.bytes_written;
+ 80255ac:	6a3b      	ldr	r3, [r7, #32]
+ 80255ae:	62fb      	str	r3, [r7, #44]	@ 0x2c
+    
+    if (!pb_encode_varint(stream, (pb_uint64_t)size))
+ 80255b0:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
+ 80255b2:	2200      	movs	r2, #0
+ 80255b4:	461c      	mov	r4, r3
+ 80255b6:	4615      	mov	r5, r2
+ 80255b8:	4622      	mov	r2, r4
+ 80255ba:	462b      	mov	r3, r5
+ 80255bc:	68f8      	ldr	r0, [r7, #12]
+ 80255be:	f7ff feb8 	bl	8025332 <pb_encode_varint>
+ 80255c2:	4603      	mov	r3, r0
+ 80255c4:	f083 0301 	eor.w	r3, r3, #1
+ 80255c8:	b2db      	uxtb	r3, r3
+ 80255ca:	2b00      	cmp	r3, #0
+ 80255cc:	d001      	beq.n	80255d2 <pb_encode_submessage+0x66>
+        return false;
+ 80255ce:	2300      	movs	r3, #0
+ 80255d0:	e052      	b.n	8025678 <pb_encode_submessage+0x10c>
+    
+    if (stream->callback == NULL)
+ 80255d2:	68fb      	ldr	r3, [r7, #12]
+ 80255d4:	681b      	ldr	r3, [r3, #0]
+ 80255d6:	2b00      	cmp	r3, #0
+ 80255d8:	d106      	bne.n	80255e8 <pb_encode_submessage+0x7c>
+        return pb_write(stream, NULL, size); /* Just sizing */
+ 80255da:	6afa      	ldr	r2, [r7, #44]	@ 0x2c
+ 80255dc:	2100      	movs	r1, #0
+ 80255de:	68f8      	ldr	r0, [r7, #12]
+ 80255e0:	f7ff f9ac 	bl	802493c <pb_write>
+ 80255e4:	4603      	mov	r3, r0
+ 80255e6:	e047      	b.n	8025678 <pb_encode_submessage+0x10c>
+    
+    if (stream->bytes_written + size > stream->max_size)
+ 80255e8:	68fb      	ldr	r3, [r7, #12]
+ 80255ea:	68da      	ldr	r2, [r3, #12]
+ 80255ec:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
+ 80255ee:	441a      	add	r2, r3
+ 80255f0:	68fb      	ldr	r3, [r7, #12]
+ 80255f2:	689b      	ldr	r3, [r3, #8]
+ 80255f4:	429a      	cmp	r2, r3
+ 80255f6:	d90b      	bls.n	8025610 <pb_encode_submessage+0xa4>
+        PB_RETURN_ERROR(stream, "stream full");
+ 80255f8:	68fb      	ldr	r3, [r7, #12]
+ 80255fa:	691b      	ldr	r3, [r3, #16]
+ 80255fc:	2b00      	cmp	r3, #0
+ 80255fe:	d002      	beq.n	8025606 <pb_encode_submessage+0x9a>
+ 8025600:	68fb      	ldr	r3, [r7, #12]
+ 8025602:	691b      	ldr	r3, [r3, #16]
+ 8025604:	e000      	b.n	8025608 <pb_encode_submessage+0x9c>
+ 8025606:	4b1e      	ldr	r3, [pc, #120]	@ (8025680 <pb_encode_submessage+0x114>)
+ 8025608:	68fa      	ldr	r2, [r7, #12]
+ 802560a:	6113      	str	r3, [r2, #16]
+ 802560c:	2300      	movs	r3, #0
+ 802560e:	e033      	b.n	8025678 <pb_encode_submessage+0x10c>
+        
+    /* Use a substream to verify that a callback doesn't write more than
+     * what it did the first time. */
+    substream.callback = stream->callback;
+ 8025610:	68fb      	ldr	r3, [r7, #12]
+ 8025612:	681b      	ldr	r3, [r3, #0]
+ 8025614:	617b      	str	r3, [r7, #20]
+    substream.state = stream->state;
+ 8025616:	68fb      	ldr	r3, [r7, #12]
+ 8025618:	685b      	ldr	r3, [r3, #4]
+ 802561a:	61bb      	str	r3, [r7, #24]
+    substream.max_size = size;
+ 802561c:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
+ 802561e:	61fb      	str	r3, [r7, #28]
+    substream.bytes_written = 0;
+ 8025620:	2300      	movs	r3, #0
+ 8025622:	623b      	str	r3, [r7, #32]
+#ifndef PB_NO_ERRMSG
+    substream.errmsg = NULL;
+ 8025624:	2300      	movs	r3, #0
+ 8025626:	627b      	str	r3, [r7, #36]	@ 0x24
+#endif
+    
+    status = pb_encode(&substream, fields, src_struct);
+ 8025628:	f107 0314 	add.w	r3, r7, #20
+ 802562c:	687a      	ldr	r2, [r7, #4]
+ 802562e:	68b9      	ldr	r1, [r7, #8]
+ 8025630:	4618      	mov	r0, r3
+ 8025632:	f7ff fdd0 	bl	80251d6 <pb_encode>
+ 8025636:	4603      	mov	r3, r0
+ 8025638:	f887 302b 	strb.w	r3, [r7, #43]	@ 0x2b
+    
+    stream->bytes_written += substream.bytes_written;
+ 802563c:	68fb      	ldr	r3, [r7, #12]
+ 802563e:	68da      	ldr	r2, [r3, #12]
+ 8025640:	6a3b      	ldr	r3, [r7, #32]
+ 8025642:	441a      	add	r2, r3
+ 8025644:	68fb      	ldr	r3, [r7, #12]
+ 8025646:	60da      	str	r2, [r3, #12]
+    stream->state = substream.state;
+ 8025648:	69ba      	ldr	r2, [r7, #24]
+ 802564a:	68fb      	ldr	r3, [r7, #12]
+ 802564c:	605a      	str	r2, [r3, #4]
+#ifndef PB_NO_ERRMSG
+    stream->errmsg = substream.errmsg;
+ 802564e:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
+ 8025650:	68fb      	ldr	r3, [r7, #12]
+ 8025652:	611a      	str	r2, [r3, #16]
+#endif
+    
+    if (substream.bytes_written != size)
+ 8025654:	6a3b      	ldr	r3, [r7, #32]
+ 8025656:	6afa      	ldr	r2, [r7, #44]	@ 0x2c
+ 8025658:	429a      	cmp	r2, r3
+ 802565a:	d00b      	beq.n	8025674 <pb_encode_submessage+0x108>
+        PB_RETURN_ERROR(stream, "submsg size changed");
+ 802565c:	68fb      	ldr	r3, [r7, #12]
+ 802565e:	691b      	ldr	r3, [r3, #16]
+ 8025660:	2b00      	cmp	r3, #0
+ 8025662:	d002      	beq.n	802566a <pb_encode_submessage+0xfe>
+ 8025664:	68fb      	ldr	r3, [r7, #12]
+ 8025666:	691b      	ldr	r3, [r3, #16]
+ 8025668:	e000      	b.n	802566c <pb_encode_submessage+0x100>
+ 802566a:	4b06      	ldr	r3, [pc, #24]	@ (8025684 <pb_encode_submessage+0x118>)
+ 802566c:	68fa      	ldr	r2, [r7, #12]
+ 802566e:	6113      	str	r3, [r2, #16]
+ 8025670:	2300      	movs	r3, #0
+ 8025672:	e001      	b.n	8025678 <pb_encode_submessage+0x10c>
+    
+    return status;
+ 8025674:	f897 302b 	ldrb.w	r3, [r7, #43]	@ 0x2b
+}
+ 8025678:	4618      	mov	r0, r3
+ 802567a:	3730      	adds	r7, #48	@ 0x30
+ 802567c:	46bd      	mov	sp, r7
+ 802567e:	bdb0      	pop	{r4, r5, r7, pc}
+ 8025680:	080411cc 	.word	0x080411cc
+ 8025684:	08041254 	.word	0x08041254
+
+08025688 <pb_enc_bool>:
+
+/* Field encoders */
+
+static bool checkreturn pb_enc_bool(pb_ostream_t *stream, const pb_field_iter_t *field)
+{
+ 8025688:	b5b0      	push	{r4, r5, r7, lr}
+ 802568a:	b084      	sub	sp, #16
+ 802568c:	af00      	add	r7, sp, #0
+ 802568e:	6078      	str	r0, [r7, #4]
+ 8025690:	6039      	str	r1, [r7, #0]
+    uint32_t value = safe_read_bool(field->pData) ? 1 : 0;
+ 8025692:	683b      	ldr	r3, [r7, #0]
+ 8025694:	69db      	ldr	r3, [r3, #28]
+ 8025696:	4618      	mov	r0, r3
+ 8025698:	f7ff f9a0 	bl	80249dc <safe_read_bool>
+ 802569c:	4603      	mov	r3, r0
+ 802569e:	60fb      	str	r3, [r7, #12]
+    PB_UNUSED(field);
+    return pb_encode_varint(stream, value);
+ 80256a0:	68fb      	ldr	r3, [r7, #12]
+ 80256a2:	2200      	movs	r2, #0
+ 80256a4:	461c      	mov	r4, r3
+ 80256a6:	4615      	mov	r5, r2
+ 80256a8:	4622      	mov	r2, r4
+ 80256aa:	462b      	mov	r3, r5
+ 80256ac:	6878      	ldr	r0, [r7, #4]
+ 80256ae:	f7ff fe40 	bl	8025332 <pb_encode_varint>
+ 80256b2:	4603      	mov	r3, r0
+}
+ 80256b4:	4618      	mov	r0, r3
+ 80256b6:	3710      	adds	r7, #16
+ 80256b8:	46bd      	mov	sp, r7
+ 80256ba:	bdb0      	pop	{r4, r5, r7, pc}
+
+080256bc <pb_enc_varint>:
+
+static bool checkreturn pb_enc_varint(pb_ostream_t *stream, const pb_field_iter_t *field)
+{
+ 80256bc:	e92d 4fb0 	stmdb	sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
+ 80256c0:	b08c      	sub	sp, #48	@ 0x30
+ 80256c2:	af00      	add	r7, sp, #0
+ 80256c4:	61f8      	str	r0, [r7, #28]
+ 80256c6:	61b9      	str	r1, [r7, #24]
+    if (PB_LTYPE(field->type) == PB_LTYPE_UVARINT)
+ 80256c8:	69bb      	ldr	r3, [r7, #24]
+ 80256ca:	7d9b      	ldrb	r3, [r3, #22]
+ 80256cc:	f003 030f 	and.w	r3, r3, #15
+ 80256d0:	2b02      	cmp	r3, #2
+ 80256d2:	d152      	bne.n	802577a <pb_enc_varint+0xbe>
+    {
+        /* Perform unsigned integer extension */
+        pb_uint64_t value = 0;
+ 80256d4:	f04f 0200 	mov.w	r2, #0
+ 80256d8:	f04f 0300 	mov.w	r3, #0
+ 80256dc:	e9c7 230a 	strd	r2, r3, [r7, #40]	@ 0x28
+
+        if (field->data_size == sizeof(uint_least8_t))
+ 80256e0:	69bb      	ldr	r3, [r7, #24]
+ 80256e2:	8a5b      	ldrh	r3, [r3, #18]
+ 80256e4:	2b01      	cmp	r3, #1
+ 80256e6:	d10b      	bne.n	8025700 <pb_enc_varint+0x44>
+            value = *(const uint_least8_t*)field->pData;
+ 80256e8:	69bb      	ldr	r3, [r7, #24]
+ 80256ea:	69db      	ldr	r3, [r3, #28]
+ 80256ec:	781b      	ldrb	r3, [r3, #0]
+ 80256ee:	b2db      	uxtb	r3, r3
+ 80256f0:	2200      	movs	r2, #0
+ 80256f2:	613b      	str	r3, [r7, #16]
+ 80256f4:	617a      	str	r2, [r7, #20]
+ 80256f6:	e9d7 3404 	ldrd	r3, r4, [r7, #16]
+ 80256fa:	e9c7 340a 	strd	r3, r4, [r7, #40]	@ 0x28
+ 80256fe:	e035      	b.n	802576c <pb_enc_varint+0xb0>
+        else if (field->data_size == sizeof(uint_least16_t))
+ 8025700:	69bb      	ldr	r3, [r7, #24]
+ 8025702:	8a5b      	ldrh	r3, [r3, #18]
+ 8025704:	2b02      	cmp	r3, #2
+ 8025706:	d10b      	bne.n	8025720 <pb_enc_varint+0x64>
+            value = *(const uint_least16_t*)field->pData;
+ 8025708:	69bb      	ldr	r3, [r7, #24]
+ 802570a:	69db      	ldr	r3, [r3, #28]
+ 802570c:	881b      	ldrh	r3, [r3, #0]
+ 802570e:	b29b      	uxth	r3, r3
+ 8025710:	2200      	movs	r2, #0
+ 8025712:	60bb      	str	r3, [r7, #8]
+ 8025714:	60fa      	str	r2, [r7, #12]
+ 8025716:	e9d7 3402 	ldrd	r3, r4, [r7, #8]
+ 802571a:	e9c7 340a 	strd	r3, r4, [r7, #40]	@ 0x28
+ 802571e:	e025      	b.n	802576c <pb_enc_varint+0xb0>
+        else if (field->data_size == sizeof(uint32_t))
+ 8025720:	69bb      	ldr	r3, [r7, #24]
+ 8025722:	8a5b      	ldrh	r3, [r3, #18]
+ 8025724:	2b04      	cmp	r3, #4
+ 8025726:	d10a      	bne.n	802573e <pb_enc_varint+0x82>
+            value = *(const uint32_t*)field->pData;
+ 8025728:	69bb      	ldr	r3, [r7, #24]
+ 802572a:	69db      	ldr	r3, [r3, #28]
+ 802572c:	681b      	ldr	r3, [r3, #0]
+ 802572e:	2200      	movs	r2, #0
+ 8025730:	603b      	str	r3, [r7, #0]
+ 8025732:	607a      	str	r2, [r7, #4]
+ 8025734:	e9d7 3400 	ldrd	r3, r4, [r7]
+ 8025738:	e9c7 340a 	strd	r3, r4, [r7, #40]	@ 0x28
+ 802573c:	e016      	b.n	802576c <pb_enc_varint+0xb0>
+        else if (field->data_size == sizeof(pb_uint64_t))
+ 802573e:	69bb      	ldr	r3, [r7, #24]
+ 8025740:	8a5b      	ldrh	r3, [r3, #18]
+ 8025742:	2b08      	cmp	r3, #8
+ 8025744:	d106      	bne.n	8025754 <pb_enc_varint+0x98>
+            value = *(const pb_uint64_t*)field->pData;
+ 8025746:	69bb      	ldr	r3, [r7, #24]
+ 8025748:	69db      	ldr	r3, [r3, #28]
+ 802574a:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802574e:	e9c7 230a 	strd	r2, r3, [r7, #40]	@ 0x28
+ 8025752:	e00b      	b.n	802576c <pb_enc_varint+0xb0>
+        else
+            PB_RETURN_ERROR(stream, "invalid data_size");
+ 8025754:	69fb      	ldr	r3, [r7, #28]
+ 8025756:	691b      	ldr	r3, [r3, #16]
+ 8025758:	2b00      	cmp	r3, #0
+ 802575a:	d002      	beq.n	8025762 <pb_enc_varint+0xa6>
+ 802575c:	69fb      	ldr	r3, [r7, #28]
+ 802575e:	691b      	ldr	r3, [r3, #16]
+ 8025760:	e000      	b.n	8025764 <pb_enc_varint+0xa8>
+ 8025762:	4b36      	ldr	r3, [pc, #216]	@ (802583c <pb_enc_varint+0x180>)
+ 8025764:	69fa      	ldr	r2, [r7, #28]
+ 8025766:	6113      	str	r3, [r2, #16]
+ 8025768:	2300      	movs	r3, #0
+ 802576a:	e061      	b.n	8025830 <pb_enc_varint+0x174>
+
+        return pb_encode_varint(stream, value);
+ 802576c:	e9d7 230a 	ldrd	r2, r3, [r7, #40]	@ 0x28
+ 8025770:	69f8      	ldr	r0, [r7, #28]
+ 8025772:	f7ff fdde 	bl	8025332 <pb_encode_varint>
+ 8025776:	4603      	mov	r3, r0
+ 8025778:	e05a      	b.n	8025830 <pb_enc_varint+0x174>
+    }
+    else
+    {
+        /* Perform signed integer extension */
+        pb_int64_t value = 0;
+ 802577a:	f04f 0200 	mov.w	r2, #0
+ 802577e:	f04f 0300 	mov.w	r3, #0
+ 8025782:	e9c7 2308 	strd	r2, r3, [r7, #32]
+
+        if (field->data_size == sizeof(int_least8_t))
+ 8025786:	69bb      	ldr	r3, [r7, #24]
+ 8025788:	8a5b      	ldrh	r3, [r3, #18]
+ 802578a:	2b01      	cmp	r3, #1
+ 802578c:	d10a      	bne.n	80257a4 <pb_enc_varint+0xe8>
+            value = *(const int_least8_t*)field->pData;
+ 802578e:	69bb      	ldr	r3, [r7, #24]
+ 8025790:	69db      	ldr	r3, [r3, #28]
+ 8025792:	f993 3000 	ldrsb.w	r3, [r3]
+ 8025796:	b25b      	sxtb	r3, r3
+ 8025798:	17da      	asrs	r2, r3, #31
+ 802579a:	469a      	mov	sl, r3
+ 802579c:	4693      	mov	fp, r2
+ 802579e:	e9c7 ab08 	strd	sl, fp, [r7, #32]
+ 80257a2:	e032      	b.n	802580a <pb_enc_varint+0x14e>
+        else if (field->data_size == sizeof(int_least16_t))
+ 80257a4:	69bb      	ldr	r3, [r7, #24]
+ 80257a6:	8a5b      	ldrh	r3, [r3, #18]
+ 80257a8:	2b02      	cmp	r3, #2
+ 80257aa:	d10a      	bne.n	80257c2 <pb_enc_varint+0x106>
+            value = *(const int_least16_t*)field->pData;
+ 80257ac:	69bb      	ldr	r3, [r7, #24]
+ 80257ae:	69db      	ldr	r3, [r3, #28]
+ 80257b0:	f9b3 3000 	ldrsh.w	r3, [r3]
+ 80257b4:	b21b      	sxth	r3, r3
+ 80257b6:	17da      	asrs	r2, r3, #31
+ 80257b8:	4698      	mov	r8, r3
+ 80257ba:	4691      	mov	r9, r2
+ 80257bc:	e9c7 8908 	strd	r8, r9, [r7, #32]
+ 80257c0:	e023      	b.n	802580a <pb_enc_varint+0x14e>
+        else if (field->data_size == sizeof(int32_t))
+ 80257c2:	69bb      	ldr	r3, [r7, #24]
+ 80257c4:	8a5b      	ldrh	r3, [r3, #18]
+ 80257c6:	2b04      	cmp	r3, #4
+ 80257c8:	d108      	bne.n	80257dc <pb_enc_varint+0x120>
+            value = *(const int32_t*)field->pData;
+ 80257ca:	69bb      	ldr	r3, [r7, #24]
+ 80257cc:	69db      	ldr	r3, [r3, #28]
+ 80257ce:	681b      	ldr	r3, [r3, #0]
+ 80257d0:	17da      	asrs	r2, r3, #31
+ 80257d2:	461c      	mov	r4, r3
+ 80257d4:	4615      	mov	r5, r2
+ 80257d6:	e9c7 4508 	strd	r4, r5, [r7, #32]
+ 80257da:	e016      	b.n	802580a <pb_enc_varint+0x14e>
+        else if (field->data_size == sizeof(pb_int64_t))
+ 80257dc:	69bb      	ldr	r3, [r7, #24]
+ 80257de:	8a5b      	ldrh	r3, [r3, #18]
+ 80257e0:	2b08      	cmp	r3, #8
+ 80257e2:	d106      	bne.n	80257f2 <pb_enc_varint+0x136>
+            value = *(const pb_int64_t*)field->pData;
+ 80257e4:	69bb      	ldr	r3, [r7, #24]
+ 80257e6:	69db      	ldr	r3, [r3, #28]
+ 80257e8:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 80257ec:	e9c7 2308 	strd	r2, r3, [r7, #32]
+ 80257f0:	e00b      	b.n	802580a <pb_enc_varint+0x14e>
+        else
+            PB_RETURN_ERROR(stream, "invalid data_size");
+ 80257f2:	69fb      	ldr	r3, [r7, #28]
+ 80257f4:	691b      	ldr	r3, [r3, #16]
+ 80257f6:	2b00      	cmp	r3, #0
+ 80257f8:	d002      	beq.n	8025800 <pb_enc_varint+0x144>
+ 80257fa:	69fb      	ldr	r3, [r7, #28]
+ 80257fc:	691b      	ldr	r3, [r3, #16]
+ 80257fe:	e000      	b.n	8025802 <pb_enc_varint+0x146>
+ 8025800:	4b0e      	ldr	r3, [pc, #56]	@ (802583c <pb_enc_varint+0x180>)
+ 8025802:	69fa      	ldr	r2, [r7, #28]
+ 8025804:	6113      	str	r3, [r2, #16]
+ 8025806:	2300      	movs	r3, #0
+ 8025808:	e012      	b.n	8025830 <pb_enc_varint+0x174>
+
+        if (PB_LTYPE(field->type) == PB_LTYPE_SVARINT)
+ 802580a:	69bb      	ldr	r3, [r7, #24]
+ 802580c:	7d9b      	ldrb	r3, [r3, #22]
+ 802580e:	f003 030f 	and.w	r3, r3, #15
+ 8025812:	2b03      	cmp	r3, #3
+ 8025814:	d106      	bne.n	8025824 <pb_enc_varint+0x168>
+            return pb_encode_svarint(stream, value);
+ 8025816:	e9d7 2308 	ldrd	r2, r3, [r7, #32]
+ 802581a:	69f8      	ldr	r0, [r7, #28]
+ 802581c:	f7ff fdb4 	bl	8025388 <pb_encode_svarint>
+ 8025820:	4603      	mov	r3, r0
+ 8025822:	e005      	b.n	8025830 <pb_enc_varint+0x174>
+#ifdef PB_WITHOUT_64BIT
+        else if (value < 0)
+            return pb_encode_varint_32(stream, (uint32_t)value, (uint32_t)-1);
+#endif
+        else
+            return pb_encode_varint(stream, (pb_uint64_t)value);
+ 8025824:	e9d7 2308 	ldrd	r2, r3, [r7, #32]
+ 8025828:	69f8      	ldr	r0, [r7, #28]
+ 802582a:	f7ff fd82 	bl	8025332 <pb_encode_varint>
+ 802582e:	4603      	mov	r3, r0
+
+    }
+}
+ 8025830:	4618      	mov	r0, r3
+ 8025832:	3730      	adds	r7, #48	@ 0x30
+ 8025834:	46bd      	mov	sp, r7
+ 8025836:	e8bd 8fb0 	ldmia.w	sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
+ 802583a:	bf00      	nop
+ 802583c:	08041268 	.word	0x08041268
+
+08025840 <pb_enc_fixed>:
+
+static bool checkreturn pb_enc_fixed(pb_ostream_t *stream, const pb_field_iter_t *field)
+{
+ 8025840:	b580      	push	{r7, lr}
+ 8025842:	b082      	sub	sp, #8
+ 8025844:	af00      	add	r7, sp, #0
+ 8025846:	6078      	str	r0, [r7, #4]
+ 8025848:	6039      	str	r1, [r7, #0]
+    {
+        return pb_encode_float_as_double(stream, *(float*)field->pData);
+    }
+#endif
+
+    if (field->data_size == sizeof(uint32_t))
+ 802584a:	683b      	ldr	r3, [r7, #0]
+ 802584c:	8a5b      	ldrh	r3, [r3, #18]
+ 802584e:	2b04      	cmp	r3, #4
+ 8025850:	d107      	bne.n	8025862 <pb_enc_fixed+0x22>
+    {
+        return pb_encode_fixed32(stream, field->pData);
+ 8025852:	683b      	ldr	r3, [r7, #0]
+ 8025854:	69db      	ldr	r3, [r3, #28]
+ 8025856:	4619      	mov	r1, r3
+ 8025858:	6878      	ldr	r0, [r7, #4]
+ 802585a:	f7ff fdcf 	bl	80253fc <pb_encode_fixed32>
+ 802585e:	4603      	mov	r3, r0
+ 8025860:	e016      	b.n	8025890 <pb_enc_fixed+0x50>
+    }
+#ifndef PB_WITHOUT_64BIT
+    else if (field->data_size == sizeof(uint64_t))
+ 8025862:	683b      	ldr	r3, [r7, #0]
+ 8025864:	8a5b      	ldrh	r3, [r3, #18]
+ 8025866:	2b08      	cmp	r3, #8
+ 8025868:	d107      	bne.n	802587a <pb_enc_fixed+0x3a>
+    {
+        return pb_encode_fixed64(stream, field->pData);
+ 802586a:	683b      	ldr	r3, [r7, #0]
+ 802586c:	69db      	ldr	r3, [r3, #28]
+ 802586e:	4619      	mov	r1, r3
+ 8025870:	6878      	ldr	r0, [r7, #4]
+ 8025872:	f7ff fdd2 	bl	802541a <pb_encode_fixed64>
+ 8025876:	4603      	mov	r3, r0
+ 8025878:	e00a      	b.n	8025890 <pb_enc_fixed+0x50>
+    }
+#endif
+    else
+    {
+        PB_RETURN_ERROR(stream, "invalid data_size");
+ 802587a:	687b      	ldr	r3, [r7, #4]
+ 802587c:	691b      	ldr	r3, [r3, #16]
+ 802587e:	2b00      	cmp	r3, #0
+ 8025880:	d002      	beq.n	8025888 <pb_enc_fixed+0x48>
+ 8025882:	687b      	ldr	r3, [r7, #4]
+ 8025884:	691b      	ldr	r3, [r3, #16]
+ 8025886:	e000      	b.n	802588a <pb_enc_fixed+0x4a>
+ 8025888:	4b03      	ldr	r3, [pc, #12]	@ (8025898 <pb_enc_fixed+0x58>)
+ 802588a:	687a      	ldr	r2, [r7, #4]
+ 802588c:	6113      	str	r3, [r2, #16]
+ 802588e:	2300      	movs	r3, #0
+    }
+}
+ 8025890:	4618      	mov	r0, r3
+ 8025892:	3708      	adds	r7, #8
+ 8025894:	46bd      	mov	sp, r7
+ 8025896:	bd80      	pop	{r7, pc}
+ 8025898:	08041268 	.word	0x08041268
+
+0802589c <pb_enc_bytes>:
+
+static bool checkreturn pb_enc_bytes(pb_ostream_t *stream, const pb_field_iter_t *field)
+{
+ 802589c:	b580      	push	{r7, lr}
+ 802589e:	b084      	sub	sp, #16
+ 80258a0:	af00      	add	r7, sp, #0
+ 80258a2:	6078      	str	r0, [r7, #4]
+ 80258a4:	6039      	str	r1, [r7, #0]
+    const pb_bytes_array_t *bytes = NULL;
+ 80258a6:	2300      	movs	r3, #0
+ 80258a8:	60fb      	str	r3, [r7, #12]
+
+    bytes = (const pb_bytes_array_t*)field->pData;
+ 80258aa:	683b      	ldr	r3, [r7, #0]
+ 80258ac:	69db      	ldr	r3, [r3, #28]
+ 80258ae:	60fb      	str	r3, [r7, #12]
+    
+    if (bytes == NULL)
+ 80258b0:	68fb      	ldr	r3, [r7, #12]
+ 80258b2:	2b00      	cmp	r3, #0
+ 80258b4:	d106      	bne.n	80258c4 <pb_enc_bytes+0x28>
+    {
+        /* Treat null pointer as an empty bytes field */
+        return pb_encode_string(stream, NULL, 0);
+ 80258b6:	2200      	movs	r2, #0
+ 80258b8:	2100      	movs	r1, #0
+ 80258ba:	6878      	ldr	r0, [r7, #4]
+ 80258bc:	f7ff fe34 	bl	8025528 <pb_encode_string>
+ 80258c0:	4603      	mov	r3, r0
+ 80258c2:	e022      	b.n	802590a <pb_enc_bytes+0x6e>
+    }
+    
+    if (PB_ATYPE(field->type) == PB_ATYPE_STATIC &&
+ 80258c4:	683b      	ldr	r3, [r7, #0]
+ 80258c6:	7d9b      	ldrb	r3, [r3, #22]
+ 80258c8:	f003 03c0 	and.w	r3, r3, #192	@ 0xc0
+ 80258cc:	2b00      	cmp	r3, #0
+ 80258ce:	d113      	bne.n	80258f8 <pb_enc_bytes+0x5c>
+        bytes->size > field->data_size - offsetof(pb_bytes_array_t, bytes))
+ 80258d0:	68fb      	ldr	r3, [r7, #12]
+ 80258d2:	881b      	ldrh	r3, [r3, #0]
+ 80258d4:	461a      	mov	r2, r3
+ 80258d6:	683b      	ldr	r3, [r7, #0]
+ 80258d8:	8a5b      	ldrh	r3, [r3, #18]
+ 80258da:	3b02      	subs	r3, #2
+    if (PB_ATYPE(field->type) == PB_ATYPE_STATIC &&
+ 80258dc:	429a      	cmp	r2, r3
+ 80258de:	d90b      	bls.n	80258f8 <pb_enc_bytes+0x5c>
+    {
+        PB_RETURN_ERROR(stream, "bytes size exceeded");
+ 80258e0:	687b      	ldr	r3, [r7, #4]
+ 80258e2:	691b      	ldr	r3, [r3, #16]
+ 80258e4:	2b00      	cmp	r3, #0
+ 80258e6:	d002      	beq.n	80258ee <pb_enc_bytes+0x52>
+ 80258e8:	687b      	ldr	r3, [r7, #4]
+ 80258ea:	691b      	ldr	r3, [r3, #16]
+ 80258ec:	e000      	b.n	80258f0 <pb_enc_bytes+0x54>
+ 80258ee:	4b09      	ldr	r3, [pc, #36]	@ (8025914 <pb_enc_bytes+0x78>)
+ 80258f0:	687a      	ldr	r2, [r7, #4]
+ 80258f2:	6113      	str	r3, [r2, #16]
+ 80258f4:	2300      	movs	r3, #0
+ 80258f6:	e008      	b.n	802590a <pb_enc_bytes+0x6e>
+    }
+    
+    return pb_encode_string(stream, bytes->bytes, (size_t)bytes->size);
+ 80258f8:	68fb      	ldr	r3, [r7, #12]
+ 80258fa:	1c99      	adds	r1, r3, #2
+ 80258fc:	68fb      	ldr	r3, [r7, #12]
+ 80258fe:	881b      	ldrh	r3, [r3, #0]
+ 8025900:	461a      	mov	r2, r3
+ 8025902:	6878      	ldr	r0, [r7, #4]
+ 8025904:	f7ff fe10 	bl	8025528 <pb_encode_string>
+ 8025908:	4603      	mov	r3, r0
+}
+ 802590a:	4618      	mov	r0, r3
+ 802590c:	3710      	adds	r7, #16
+ 802590e:	46bd      	mov	sp, r7
+ 8025910:	bd80      	pop	{r7, pc}
+ 8025912:	bf00      	nop
+ 8025914:	0804127c 	.word	0x0804127c
+
+08025918 <pb_enc_string>:
+
+static bool checkreturn pb_enc_string(pb_ostream_t *stream, const pb_field_iter_t *field)
+{
+ 8025918:	b580      	push	{r7, lr}
+ 802591a:	b086      	sub	sp, #24
+ 802591c:	af00      	add	r7, sp, #0
+ 802591e:	6078      	str	r0, [r7, #4]
+ 8025920:	6039      	str	r1, [r7, #0]
+    size_t size = 0;
+ 8025922:	2300      	movs	r3, #0
+ 8025924:	617b      	str	r3, [r7, #20]
+    size_t max_size = (size_t)field->data_size;
+ 8025926:	683b      	ldr	r3, [r7, #0]
+ 8025928:	8a5b      	ldrh	r3, [r3, #18]
+ 802592a:	613b      	str	r3, [r7, #16]
+    const char *str = (const char*)field->pData;
+ 802592c:	683b      	ldr	r3, [r7, #0]
+ 802592e:	69db      	ldr	r3, [r3, #28]
+ 8025930:	60bb      	str	r3, [r7, #8]
+    
+    if (PB_ATYPE(field->type) == PB_ATYPE_POINTER)
+ 8025932:	683b      	ldr	r3, [r7, #0]
+ 8025934:	7d9b      	ldrb	r3, [r3, #22]
+ 8025936:	f003 03c0 	and.w	r3, r3, #192	@ 0xc0
+ 802593a:	2b80      	cmp	r3, #128	@ 0x80
+ 802593c:	d103      	bne.n	8025946 <pb_enc_string+0x2e>
+    {
+        max_size = (size_t)-1;
+ 802593e:	f04f 33ff 	mov.w	r3, #4294967295
+ 8025942:	613b      	str	r3, [r7, #16]
+ 8025944:	e011      	b.n	802596a <pb_enc_string+0x52>
+        /* pb_dec_string() assumes string fields end with a null
+         * terminator when the type isn't PB_ATYPE_POINTER, so we
+         * shouldn't allow more than max-1 bytes to be written to
+         * allow space for the null terminator.
+         */
+        if (max_size == 0)
+ 8025946:	693b      	ldr	r3, [r7, #16]
+ 8025948:	2b00      	cmp	r3, #0
+ 802594a:	d10b      	bne.n	8025964 <pb_enc_string+0x4c>
+            PB_RETURN_ERROR(stream, "zero-length string");
+ 802594c:	687b      	ldr	r3, [r7, #4]
+ 802594e:	691b      	ldr	r3, [r3, #16]
+ 8025950:	2b00      	cmp	r3, #0
+ 8025952:	d002      	beq.n	802595a <pb_enc_string+0x42>
+ 8025954:	687b      	ldr	r3, [r7, #4]
+ 8025956:	691b      	ldr	r3, [r3, #16]
+ 8025958:	e000      	b.n	802595c <pb_enc_string+0x44>
+ 802595a:	4b1c      	ldr	r3, [pc, #112]	@ (80259cc <pb_enc_string+0xb4>)
+ 802595c:	687a      	ldr	r2, [r7, #4]
+ 802595e:	6113      	str	r3, [r2, #16]
+ 8025960:	2300      	movs	r3, #0
+ 8025962:	e02f      	b.n	80259c4 <pb_enc_string+0xac>
+
+        max_size -= 1;
+ 8025964:	693b      	ldr	r3, [r7, #16]
+ 8025966:	3b01      	subs	r3, #1
+ 8025968:	613b      	str	r3, [r7, #16]
+    }
+
+
+    if (str == NULL)
+ 802596a:	68bb      	ldr	r3, [r7, #8]
+ 802596c:	2b00      	cmp	r3, #0
+ 802596e:	d102      	bne.n	8025976 <pb_enc_string+0x5e>
+    {
+        size = 0; /* Treat null pointer as an empty string */
+ 8025970:	2300      	movs	r3, #0
+ 8025972:	617b      	str	r3, [r7, #20]
+ 8025974:	e020      	b.n	80259b8 <pb_enc_string+0xa0>
+    }
+    else
+    {
+        const char *p = str;
+ 8025976:	68bb      	ldr	r3, [r7, #8]
+ 8025978:	60fb      	str	r3, [r7, #12]
+
+        /* strnlen() is not always available, so just use a loop */
+        while (size < max_size && *p != '\0')
+ 802597a:	e005      	b.n	8025988 <pb_enc_string+0x70>
+        {
+            size++;
+ 802597c:	697b      	ldr	r3, [r7, #20]
+ 802597e:	3301      	adds	r3, #1
+ 8025980:	617b      	str	r3, [r7, #20]
+            p++;
+ 8025982:	68fb      	ldr	r3, [r7, #12]
+ 8025984:	3301      	adds	r3, #1
+ 8025986:	60fb      	str	r3, [r7, #12]
+        while (size < max_size && *p != '\0')
+ 8025988:	697a      	ldr	r2, [r7, #20]
+ 802598a:	693b      	ldr	r3, [r7, #16]
+ 802598c:	429a      	cmp	r2, r3
+ 802598e:	d203      	bcs.n	8025998 <pb_enc_string+0x80>
+ 8025990:	68fb      	ldr	r3, [r7, #12]
+ 8025992:	781b      	ldrb	r3, [r3, #0]
+ 8025994:	2b00      	cmp	r3, #0
+ 8025996:	d1f1      	bne.n	802597c <pb_enc_string+0x64>
+        }
+
+        if (*p != '\0')
+ 8025998:	68fb      	ldr	r3, [r7, #12]
+ 802599a:	781b      	ldrb	r3, [r3, #0]
+ 802599c:	2b00      	cmp	r3, #0
+ 802599e:	d00b      	beq.n	80259b8 <pb_enc_string+0xa0>
+        {
+            PB_RETURN_ERROR(stream, "unterminated string");
+ 80259a0:	687b      	ldr	r3, [r7, #4]
+ 80259a2:	691b      	ldr	r3, [r3, #16]
+ 80259a4:	2b00      	cmp	r3, #0
+ 80259a6:	d002      	beq.n	80259ae <pb_enc_string+0x96>
+ 80259a8:	687b      	ldr	r3, [r7, #4]
+ 80259aa:	691b      	ldr	r3, [r3, #16]
+ 80259ac:	e000      	b.n	80259b0 <pb_enc_string+0x98>
+ 80259ae:	4b08      	ldr	r3, [pc, #32]	@ (80259d0 <pb_enc_string+0xb8>)
+ 80259b0:	687a      	ldr	r2, [r7, #4]
+ 80259b2:	6113      	str	r3, [r2, #16]
+ 80259b4:	2300      	movs	r3, #0
+ 80259b6:	e005      	b.n	80259c4 <pb_enc_string+0xac>
+#ifdef PB_VALIDATE_UTF8
+    if (!pb_validate_utf8(str))
+        PB_RETURN_ERROR(stream, "invalid utf8");
+#endif
+
+    return pb_encode_string(stream, (const pb_byte_t*)str, size);
+ 80259b8:	697a      	ldr	r2, [r7, #20]
+ 80259ba:	68b9      	ldr	r1, [r7, #8]
+ 80259bc:	6878      	ldr	r0, [r7, #4]
+ 80259be:	f7ff fdb3 	bl	8025528 <pb_encode_string>
+ 80259c2:	4603      	mov	r3, r0
+}
+ 80259c4:	4618      	mov	r0, r3
+ 80259c6:	3718      	adds	r7, #24
+ 80259c8:	46bd      	mov	sp, r7
+ 80259ca:	bd80      	pop	{r7, pc}
+ 80259cc:	08041290 	.word	0x08041290
+ 80259d0:	080412a4 	.word	0x080412a4
+
+080259d4 <pb_enc_submessage>:
+
+static bool checkreturn pb_enc_submessage(pb_ostream_t *stream, const pb_field_iter_t *field)
+{
+ 80259d4:	b580      	push	{r7, lr}
+ 80259d6:	b084      	sub	sp, #16
+ 80259d8:	af00      	add	r7, sp, #0
+ 80259da:	6078      	str	r0, [r7, #4]
+ 80259dc:	6039      	str	r1, [r7, #0]
+    if (field->submsg_desc == NULL)
+ 80259de:	683b      	ldr	r3, [r7, #0]
+ 80259e0:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 80259e2:	2b00      	cmp	r3, #0
+ 80259e4:	d10b      	bne.n	80259fe <pb_enc_submessage+0x2a>
+        PB_RETURN_ERROR(stream, "invalid field descriptor");
+ 80259e6:	687b      	ldr	r3, [r7, #4]
+ 80259e8:	691b      	ldr	r3, [r3, #16]
+ 80259ea:	2b00      	cmp	r3, #0
+ 80259ec:	d002      	beq.n	80259f4 <pb_enc_submessage+0x20>
+ 80259ee:	687b      	ldr	r3, [r7, #4]
+ 80259f0:	691b      	ldr	r3, [r3, #16]
+ 80259f2:	e000      	b.n	80259f6 <pb_enc_submessage+0x22>
+ 80259f4:	4b19      	ldr	r3, [pc, #100]	@ (8025a5c <pb_enc_submessage+0x88>)
+ 80259f6:	687a      	ldr	r2, [r7, #4]
+ 80259f8:	6113      	str	r3, [r2, #16]
+ 80259fa:	2300      	movs	r3, #0
+ 80259fc:	e029      	b.n	8025a52 <pb_enc_submessage+0x7e>
+
+    if (PB_LTYPE(field->type) == PB_LTYPE_SUBMSG_W_CB && field->pSize != NULL)
+ 80259fe:	683b      	ldr	r3, [r7, #0]
+ 8025a00:	7d9b      	ldrb	r3, [r3, #22]
+ 8025a02:	f003 030f 	and.w	r3, r3, #15
+ 8025a06:	2b09      	cmp	r3, #9
+ 8025a08:	d11a      	bne.n	8025a40 <pb_enc_submessage+0x6c>
+ 8025a0a:	683b      	ldr	r3, [r7, #0]
+ 8025a0c:	6a1b      	ldr	r3, [r3, #32]
+ 8025a0e:	2b00      	cmp	r3, #0
+ 8025a10:	d016      	beq.n	8025a40 <pb_enc_submessage+0x6c>
+    {
+        /* Message callback is stored right before pSize. */
+        pb_callback_t *callback = (pb_callback_t*)field->pSize - 1;
+ 8025a12:	683b      	ldr	r3, [r7, #0]
+ 8025a14:	6a1b      	ldr	r3, [r3, #32]
+ 8025a16:	3b08      	subs	r3, #8
+ 8025a18:	60fb      	str	r3, [r7, #12]
+        if (callback->funcs.encode)
+ 8025a1a:	68fb      	ldr	r3, [r7, #12]
+ 8025a1c:	681b      	ldr	r3, [r3, #0]
+ 8025a1e:	2b00      	cmp	r3, #0
+ 8025a20:	d00e      	beq.n	8025a40 <pb_enc_submessage+0x6c>
+        {
+            if (!callback->funcs.encode(stream, field, &callback->arg))
+ 8025a22:	68fb      	ldr	r3, [r7, #12]
+ 8025a24:	681b      	ldr	r3, [r3, #0]
+ 8025a26:	68fa      	ldr	r2, [r7, #12]
+ 8025a28:	3204      	adds	r2, #4
+ 8025a2a:	6839      	ldr	r1, [r7, #0]
+ 8025a2c:	6878      	ldr	r0, [r7, #4]
+ 8025a2e:	4798      	blx	r3
+ 8025a30:	4603      	mov	r3, r0
+ 8025a32:	f083 0301 	eor.w	r3, r3, #1
+ 8025a36:	b2db      	uxtb	r3, r3
+ 8025a38:	2b00      	cmp	r3, #0
+ 8025a3a:	d001      	beq.n	8025a40 <pb_enc_submessage+0x6c>
+                return false;
+ 8025a3c:	2300      	movs	r3, #0
+ 8025a3e:	e008      	b.n	8025a52 <pb_enc_submessage+0x7e>
+        }
+    }
+    
+    return pb_encode_submessage(stream, field->submsg_desc, field->pData);
+ 8025a40:	683b      	ldr	r3, [r7, #0]
+ 8025a42:	6a59      	ldr	r1, [r3, #36]	@ 0x24
+ 8025a44:	683b      	ldr	r3, [r7, #0]
+ 8025a46:	69db      	ldr	r3, [r3, #28]
+ 8025a48:	461a      	mov	r2, r3
+ 8025a4a:	6878      	ldr	r0, [r7, #4]
+ 8025a4c:	f7ff fd8e 	bl	802556c <pb_encode_submessage>
+ 8025a50:	4603      	mov	r3, r0
+}
+ 8025a52:	4618      	mov	r0, r3
+ 8025a54:	3710      	adds	r7, #16
+ 8025a56:	46bd      	mov	sp, r7
+ 8025a58:	bd80      	pop	{r7, pc}
+ 8025a5a:	bf00      	nop
+ 8025a5c:	080412b8 	.word	0x080412b8
+
+08025a60 <pb_enc_fixed_length_bytes>:
+
+static bool checkreturn pb_enc_fixed_length_bytes(pb_ostream_t *stream, const pb_field_iter_t *field)
+{
+ 8025a60:	b580      	push	{r7, lr}
+ 8025a62:	b082      	sub	sp, #8
+ 8025a64:	af00      	add	r7, sp, #0
+ 8025a66:	6078      	str	r0, [r7, #4]
+ 8025a68:	6039      	str	r1, [r7, #0]
+    return pb_encode_string(stream, (const pb_byte_t*)field->pData, (size_t)field->data_size);
+ 8025a6a:	683b      	ldr	r3, [r7, #0]
+ 8025a6c:	69d9      	ldr	r1, [r3, #28]
+ 8025a6e:	683b      	ldr	r3, [r7, #0]
+ 8025a70:	8a5b      	ldrh	r3, [r3, #18]
+ 8025a72:	461a      	mov	r2, r3
+ 8025a74:	6878      	ldr	r0, [r7, #4]
+ 8025a76:	f7ff fd57 	bl	8025528 <pb_encode_string>
+ 8025a7a:	4603      	mov	r3, r0
+}
+ 8025a7c:	4618      	mov	r0, r3
+ 8025a7e:	3708      	adds	r7, #8
+ 8025a80:	46bd      	mov	sp, r7
+ 8025a82:	bd80      	pop	{r7, pc}
+
+08025a84 <DLT_RB_Receive_GetNextMessageAddress>:
+ * Static functions implementation
+ ********************************************************************************************
+ */
+
+static RB_Status DLT_RB_Receive_GetNextMessageAddress(BluRingBufferReceive_t *Buf, uint8_t **WriteAddress)
+{
+ 8025a84:	b480      	push	{r7}
+ 8025a86:	b085      	sub	sp, #20
+ 8025a88:	af00      	add	r7, sp, #0
+ 8025a8a:	6078      	str	r0, [r7, #4]
+ 8025a8c:	6039      	str	r1, [r7, #0]
+	/* TODO: The implementation isn't optimal...*/
+	static uint8_t DefaultBlindBuffer[DLT_REC_SINGLE_MESSAGE_MAX_SIZE];
+
+	/*Mark previous message as ready to read*/
+	Buf->ReadyToRead[Buf->Head] = true;
+ 8025a8e:	687b      	ldr	r3, [r7, #4]
+ 8025a90:	881b      	ldrh	r3, [r3, #0]
+ 8025a92:	461a      	mov	r2, r3
+ 8025a94:	687b      	ldr	r3, [r7, #4]
+ 8025a96:	4413      	add	r3, r2
+ 8025a98:	2201      	movs	r2, #1
+ 8025a9a:	719a      	strb	r2, [r3, #6]
+
+	// Compute new Head pointer value of a ring buffer
+	uint16_t HeadTmp = (Buf->Head + 1) % DLT_RECEIVE_RING_BUFFER_SIZE;
+ 8025a9c:	687b      	ldr	r3, [r7, #4]
+ 8025a9e:	881b      	ldrh	r3, [r3, #0]
+ 8025aa0:	3301      	adds	r3, #1
+ 8025aa2:	2b00      	cmp	r3, #0
+ 8025aa4:	f003 0301 	and.w	r3, r3, #1
+ 8025aa8:	bfb8      	it	lt
+ 8025aaa:	425b      	neglt	r3, r3
+ 8025aac:	81fb      	strh	r3, [r7, #14]
+
+	// Check if there is one free space ahead the Head buffer
+	if(HeadTmp == Buf->Tail)
+ 8025aae:	687b      	ldr	r3, [r7, #4]
+ 8025ab0:	885b      	ldrh	r3, [r3, #2]
+ 8025ab2:	89fa      	ldrh	r2, [r7, #14]
+ 8025ab4:	429a      	cmp	r2, r3
+ 8025ab6:	d104      	bne.n	8025ac2 <DLT_RB_Receive_GetNextMessageAddress+0x3e>
+	{
+		/*Even if buffer is full data must be received somewhere to don't crush application/ dma*/
+		*WriteAddress = DefaultBlindBuffer;
+ 8025ab8:	683b      	ldr	r3, [r7, #0]
+ 8025aba:	4a10      	ldr	r2, [pc, #64]	@ (8025afc <DLT_RB_Receive_GetNextMessageAddress+0x78>)
+ 8025abc:	601a      	str	r2, [r3, #0]
+		// There is no space in the buffer - return an error
+		return RB_ERROR;
+ 8025abe:	2301      	movs	r3, #1
+ 8025ac0:	e015      	b.n	8025aee <DLT_RB_Receive_GetNextMessageAddress+0x6a>
+	}
+
+	Buf->ReadyToRead[HeadTmp] = false;
+ 8025ac2:	89fb      	ldrh	r3, [r7, #14]
+ 8025ac4:	687a      	ldr	r2, [r7, #4]
+ 8025ac6:	4413      	add	r3, r2
+ 8025ac8:	2200      	movs	r2, #0
+ 8025aca:	719a      	strb	r2, [r3, #6]
+	Buf->MessageSize[HeadTmp] = DLT_RECEIVE_RING_BUFFER_SIZE;
+ 8025acc:	89fb      	ldrh	r3, [r7, #14]
+ 8025ace:	687a      	ldr	r2, [r7, #4]
+ 8025ad0:	4413      	add	r3, r2
+ 8025ad2:	2202      	movs	r2, #2
+ 8025ad4:	711a      	strb	r2, [r3, #4]
+	Buf->Head = HeadTmp;
+ 8025ad6:	687b      	ldr	r3, [r7, #4]
+ 8025ad8:	89fa      	ldrh	r2, [r7, #14]
+ 8025ada:	801a      	strh	r2, [r3, #0]
+
+	*WriteAddress = &BluMainReceiveMessagesTab[HeadTmp][0];
+ 8025adc:	89fa      	ldrh	r2, [r7, #14]
+ 8025ade:	4613      	mov	r3, r2
+ 8025ae0:	021b      	lsls	r3, r3, #8
+ 8025ae2:	1a9b      	subs	r3, r3, r2
+ 8025ae4:	4a06      	ldr	r2, [pc, #24]	@ (8025b00 <DLT_RB_Receive_GetNextMessageAddress+0x7c>)
+ 8025ae6:	441a      	add	r2, r3
+ 8025ae8:	683b      	ldr	r3, [r7, #0]
+ 8025aea:	601a      	str	r2, [r3, #0]
+
+	// Everything is ok - return OK status
+	return RB_OK;
+ 8025aec:	2300      	movs	r3, #0
+}
+ 8025aee:	4618      	mov	r0, r3
+ 8025af0:	3714      	adds	r7, #20
+ 8025af2:	46bd      	mov	sp, r7
+ 8025af4:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8025af8:	4770      	bx	lr
+ 8025afa:	bf00      	nop
+ 8025afc:	2400a268 	.word	0x2400a268
+ 8025b00:	2400a068 	.word	0x2400a068
+
+08025b04 <DLT_RB_Receive_Read>:
+
+static RB_Status DLT_RB_Receive_Read(BluRingBufferReceive_t *Buf, uint8_t *MessageSize, uint8_t **MessagePointer)
+{
+ 8025b04:	b480      	push	{r7}
+ 8025b06:	b085      	sub	sp, #20
+ 8025b08:	af00      	add	r7, sp, #0
+ 8025b0a:	60f8      	str	r0, [r7, #12]
+ 8025b0c:	60b9      	str	r1, [r7, #8]
+ 8025b0e:	607a      	str	r2, [r7, #4]
+	if(Buf->ReadyToRead[Buf->Tail] == false)
+ 8025b10:	68fb      	ldr	r3, [r7, #12]
+ 8025b12:	885b      	ldrh	r3, [r3, #2]
+ 8025b14:	461a      	mov	r2, r3
+ 8025b16:	68fb      	ldr	r3, [r7, #12]
+ 8025b18:	4413      	add	r3, r2
+ 8025b1a:	799b      	ldrb	r3, [r3, #6]
+ 8025b1c:	f083 0301 	eor.w	r3, r3, #1
+ 8025b20:	b2db      	uxtb	r3, r3
+ 8025b22:	2b00      	cmp	r3, #0
+ 8025b24:	d001      	beq.n	8025b2a <DLT_RB_Receive_Read+0x26>
+	{
+		/*Any message in ring buffer isn't ready to read*/
+		return RB_ERROR;
+ 8025b26:	2301      	movs	r3, #1
+ 8025b28:	e02c      	b.n	8025b84 <DLT_RB_Receive_Read+0x80>
+	}
+	/*Mark again as not ready to read*/
+	Buf->ReadyToRead[Buf->Tail] = false;
+ 8025b2a:	68fb      	ldr	r3, [r7, #12]
+ 8025b2c:	885b      	ldrh	r3, [r3, #2]
+ 8025b2e:	461a      	mov	r2, r3
+ 8025b30:	68fb      	ldr	r3, [r7, #12]
+ 8025b32:	4413      	add	r3, r2
+ 8025b34:	2200      	movs	r2, #0
+ 8025b36:	719a      	strb	r2, [r3, #6]
+
+	// Check if Tail hit Head
+	if(Buf->Head == Buf->Tail)
+ 8025b38:	68fb      	ldr	r3, [r7, #12]
+ 8025b3a:	881a      	ldrh	r2, [r3, #0]
+ 8025b3c:	68fb      	ldr	r3, [r7, #12]
+ 8025b3e:	885b      	ldrh	r3, [r3, #2]
+ 8025b40:	429a      	cmp	r2, r3
+ 8025b42:	d101      	bne.n	8025b48 <DLT_RB_Receive_Read+0x44>
+	{
+		// If yes - there is nothing to read
+		return RB_ERROR;
+ 8025b44:	2301      	movs	r3, #1
+ 8025b46:	e01d      	b.n	8025b84 <DLT_RB_Receive_Read+0x80>
+	}
+
+	// Write current value from buffer to pointer from argument
+	*MessageSize = Buf->MessageSize[Buf->Tail];
+ 8025b48:	68fb      	ldr	r3, [r7, #12]
+ 8025b4a:	885b      	ldrh	r3, [r3, #2]
+ 8025b4c:	461a      	mov	r2, r3
+ 8025b4e:	68fb      	ldr	r3, [r7, #12]
+ 8025b50:	4413      	add	r3, r2
+ 8025b52:	791a      	ldrb	r2, [r3, #4]
+ 8025b54:	68bb      	ldr	r3, [r7, #8]
+ 8025b56:	701a      	strb	r2, [r3, #0]
+	*MessagePointer = &BluMainReceiveMessagesTab[Buf->Tail][0];
+ 8025b58:	68fb      	ldr	r3, [r7, #12]
+ 8025b5a:	885b      	ldrh	r3, [r3, #2]
+ 8025b5c:	461a      	mov	r2, r3
+ 8025b5e:	4613      	mov	r3, r2
+ 8025b60:	021b      	lsls	r3, r3, #8
+ 8025b62:	1a9b      	subs	r3, r3, r2
+ 8025b64:	4a0a      	ldr	r2, [pc, #40]	@ (8025b90 <DLT_RB_Receive_Read+0x8c>)
+ 8025b66:	441a      	add	r2, r3
+ 8025b68:	687b      	ldr	r3, [r7, #4]
+ 8025b6a:	601a      	str	r2, [r3, #0]
+
+	// Calculate new Tail pointer
+	Buf->Tail = (Buf->Tail + 1) % DLT_RECEIVE_RING_BUFFER_SIZE;
+ 8025b6c:	68fb      	ldr	r3, [r7, #12]
+ 8025b6e:	885b      	ldrh	r3, [r3, #2]
+ 8025b70:	3301      	adds	r3, #1
+ 8025b72:	2b00      	cmp	r3, #0
+ 8025b74:	f003 0301 	and.w	r3, r3, #1
+ 8025b78:	bfb8      	it	lt
+ 8025b7a:	425b      	neglt	r3, r3
+ 8025b7c:	b29a      	uxth	r2, r3
+ 8025b7e:	68fb      	ldr	r3, [r7, #12]
+ 8025b80:	805a      	strh	r2, [r3, #2]
+
+	// Everything is ok - return OK status
+	return RB_OK;
+ 8025b82:	2300      	movs	r3, #0
+}
+ 8025b84:	4618      	mov	r0, r3
+ 8025b86:	3714      	adds	r7, #20
+ 8025b88:	46bd      	mov	sp, r7
+ 8025b8a:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8025b8e:	4770      	bx	lr
+ 8025b90:	2400a068 	.word	0x2400a068
+
+08025b94 <DLT_RB_TransmitRead>:
+
+static RB_Status DLT_RB_TransmitRead(DltRingBufferTransmit_t *Buf, uint8_t *MessageSize, uint8_t **MessagePointer)
+{
+ 8025b94:	b480      	push	{r7}
+ 8025b96:	b085      	sub	sp, #20
+ 8025b98:	af00      	add	r7, sp, #0
+ 8025b9a:	60f8      	str	r0, [r7, #12]
+ 8025b9c:	60b9      	str	r1, [r7, #8]
+ 8025b9e:	607a      	str	r2, [r7, #4]
+	// Check if Tail hit Head
+	if(Buf->Head == Buf->Tail)
+ 8025ba0:	68fb      	ldr	r3, [r7, #12]
+ 8025ba2:	881a      	ldrh	r2, [r3, #0]
+ 8025ba4:	68fb      	ldr	r3, [r7, #12]
+ 8025ba6:	885b      	ldrh	r3, [r3, #2]
+ 8025ba8:	429a      	cmp	r2, r3
+ 8025baa:	d101      	bne.n	8025bb0 <DLT_RB_TransmitRead+0x1c>
+	{
+		// If yes - there is nothing to read
+		return RB_ERROR;
+ 8025bac:	2301      	movs	r3, #1
+ 8025bae:	e02d      	b.n	8025c0c <DLT_RB_TransmitRead+0x78>
+	}
+	else if(true == Buf->readyToTransmit[Buf->Tail])
+ 8025bb0:	68fb      	ldr	r3, [r7, #12]
+ 8025bb2:	885b      	ldrh	r3, [r3, #2]
+ 8025bb4:	461a      	mov	r2, r3
+ 8025bb6:	68fb      	ldr	r3, [r7, #12]
+ 8025bb8:	4413      	add	r3, r2
+ 8025bba:	791b      	ldrb	r3, [r3, #4]
+ 8025bbc:	2b00      	cmp	r3, #0
+ 8025bbe:	d024      	beq.n	8025c0a <DLT_RB_TransmitRead+0x76>
+	{
+		// Write current value from buffer to pointer from argument
+		*MessageSize = Buf->dataSize[Buf->Tail];
+ 8025bc0:	68fb      	ldr	r3, [r7, #12]
+ 8025bc2:	885b      	ldrh	r3, [r3, #2]
+ 8025bc4:	461a      	mov	r2, r3
+ 8025bc6:	68fb      	ldr	r3, [r7, #12]
+ 8025bc8:	4413      	add	r3, r2
+ 8025bca:	7cda      	ldrb	r2, [r3, #19]
+ 8025bcc:	68bb      	ldr	r3, [r7, #8]
+ 8025bce:	701a      	strb	r2, [r3, #0]
+		*MessagePointer = &DltTrsmtMessagesTab[Buf->Tail][0];
+ 8025bd0:	68fb      	ldr	r3, [r7, #12]
+ 8025bd2:	885b      	ldrh	r3, [r3, #2]
+ 8025bd4:	461a      	mov	r2, r3
+ 8025bd6:	4613      	mov	r3, r2
+ 8025bd8:	021b      	lsls	r3, r3, #8
+ 8025bda:	1a9b      	subs	r3, r3, r2
+ 8025bdc:	4a0e      	ldr	r2, [pc, #56]	@ (8025c18 <DLT_RB_TransmitRead+0x84>)
+ 8025bde:	441a      	add	r2, r3
+ 8025be0:	687b      	ldr	r3, [r7, #4]
+ 8025be2:	601a      	str	r2, [r3, #0]
+
+		// Calculate new Tail pointer
+		Buf->Tail = (Buf->Tail + 1) % DLT_TRANSMIT_RING_BUFFER_SIZE;
+ 8025be4:	68fb      	ldr	r3, [r7, #12]
+ 8025be6:	885b      	ldrh	r3, [r3, #2]
+ 8025be8:	1c5a      	adds	r2, r3, #1
+ 8025bea:	4b0c      	ldr	r3, [pc, #48]	@ (8025c1c <DLT_RB_TransmitRead+0x88>)
+ 8025bec:	fb83 1302 	smull	r1, r3, r3, r2
+ 8025bf0:	4413      	add	r3, r2
+ 8025bf2:	10d9      	asrs	r1, r3, #3
+ 8025bf4:	17d3      	asrs	r3, r2, #31
+ 8025bf6:	1ac9      	subs	r1, r1, r3
+ 8025bf8:	460b      	mov	r3, r1
+ 8025bfa:	011b      	lsls	r3, r3, #4
+ 8025bfc:	1a5b      	subs	r3, r3, r1
+ 8025bfe:	1ad1      	subs	r1, r2, r3
+ 8025c00:	b28a      	uxth	r2, r1
+ 8025c02:	68fb      	ldr	r3, [r7, #12]
+ 8025c04:	805a      	strh	r2, [r3, #2]
+		// Everything is ok - return OK status
+		return RB_OK;
+ 8025c06:	2300      	movs	r3, #0
+ 8025c08:	e000      	b.n	8025c0c <DLT_RB_TransmitRead+0x78>
+	}
+	else
+	{
+		/* Message still not ready to transmit */
+		return RB_ERROR;
+ 8025c0a:	2301      	movs	r3, #1
+	}
+
+}
+ 8025c0c:	4618      	mov	r0, r3
+ 8025c0e:	3714      	adds	r7, #20
+ 8025c10:	46bd      	mov	sp, r7
+ 8025c12:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8025c16:	4770      	bx	lr
+ 8025c18:	2400916c 	.word	0x2400916c
+ 8025c1c:	88888889 	.word	0x88888889
+
+08025c20 <DLT_RB_GetNextWriteIndex>:
+
+static RB_Status DLT_RB_GetNextWriteIndex(DltRingBufferTransmit_t *Buf,uint16_t *writeIndex)
+{
+ 8025c20:	b480      	push	{r7}
+ 8025c22:	b085      	sub	sp, #20
+ 8025c24:	af00      	add	r7, sp, #0
+ 8025c26:	6078      	str	r0, [r7, #4]
+ 8025c28:	6039      	str	r1, [r7, #0]
+DLTuc_OS_CRITICAL_START();
+	// Calculate new Head pointer value
+	uint8_t HeadTmp = (Buf->Head + 1) % DLT_TRANSMIT_RING_BUFFER_SIZE;
+ 8025c2a:	687b      	ldr	r3, [r7, #4]
+ 8025c2c:	881b      	ldrh	r3, [r3, #0]
+ 8025c2e:	1c5a      	adds	r2, r3, #1
+ 8025c30:	4b15      	ldr	r3, [pc, #84]	@ (8025c88 <DLT_RB_GetNextWriteIndex+0x68>)
+ 8025c32:	fb83 1302 	smull	r1, r3, r3, r2
+ 8025c36:	4413      	add	r3, r2
+ 8025c38:	10d9      	asrs	r1, r3, #3
+ 8025c3a:	17d3      	asrs	r3, r2, #31
+ 8025c3c:	1ac9      	subs	r1, r1, r3
+ 8025c3e:	460b      	mov	r3, r1
+ 8025c40:	011b      	lsls	r3, r3, #4
+ 8025c42:	1a5b      	subs	r3, r3, r1
+ 8025c44:	1ad1      	subs	r1, r2, r3
+ 8025c46:	460b      	mov	r3, r1
+ 8025c48:	73fb      	strb	r3, [r7, #15]
+
+	// Check if there is one free space ahead the Head buffer
+	if(HeadTmp == Buf->Tail)
+ 8025c4a:	7bfb      	ldrb	r3, [r7, #15]
+ 8025c4c:	b29a      	uxth	r2, r3
+ 8025c4e:	687b      	ldr	r3, [r7, #4]
+ 8025c50:	885b      	ldrh	r3, [r3, #2]
+ 8025c52:	429a      	cmp	r2, r3
+ 8025c54:	d101      	bne.n	8025c5a <DLT_RB_GetNextWriteIndex+0x3a>
+	{
+		DLTuc_OS_CRITICAL_END();
+		// There is no space in the buffer - return an error
+		return RB_ERROR;
+ 8025c56:	2301      	movs	r3, #1
+ 8025c58:	e00f      	b.n	8025c7a <DLT_RB_GetNextWriteIndex+0x5a>
+	}
+	Buf->Head = HeadTmp;
+ 8025c5a:	7bfb      	ldrb	r3, [r7, #15]
+ 8025c5c:	b29a      	uxth	r2, r3
+ 8025c5e:	687b      	ldr	r3, [r7, #4]
+ 8025c60:	801a      	strh	r2, [r3, #0]
+	Buf->readyToTransmit[Buf->Head] = false;
+ 8025c62:	687b      	ldr	r3, [r7, #4]
+ 8025c64:	881b      	ldrh	r3, [r3, #0]
+ 8025c66:	461a      	mov	r2, r3
+ 8025c68:	687b      	ldr	r3, [r7, #4]
+ 8025c6a:	4413      	add	r3, r2
+ 8025c6c:	2200      	movs	r2, #0
+ 8025c6e:	711a      	strb	r2, [r3, #4]
+	*writeIndex = Buf->Head;
+ 8025c70:	687b      	ldr	r3, [r7, #4]
+ 8025c72:	881a      	ldrh	r2, [r3, #0]
+ 8025c74:	683b      	ldr	r3, [r7, #0]
+ 8025c76:	801a      	strh	r2, [r3, #0]
+	DLTuc_OS_CRITICAL_END();
+
+	return RB_OK;
+ 8025c78:	2300      	movs	r3, #0
+}
+ 8025c7a:	4618      	mov	r0, r3
+ 8025c7c:	3714      	adds	r7, #20
+ 8025c7e:	46bd      	mov	sp, r7
+ 8025c80:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8025c84:	4770      	bx	lr
+ 8025c86:	bf00      	nop
+ 8025c88:	88888889 	.word	0x88888889
+
+08025c8c <PrepareDltHeader>:
+
+static void PrepareDltHeader(uint8_t Level, uint32_t AppId, uint32_t ContextId, uint16_t size,uint8_t *headerAddrStart)
+{
+ 8025c8c:	b580      	push	{r7, lr}
+ 8025c8e:	b086      	sub	sp, #24
+ 8025c90:	af00      	add	r7, sp, #0
+ 8025c92:	60b9      	str	r1, [r7, #8]
+ 8025c94:	607a      	str	r2, [r7, #4]
+ 8025c96:	461a      	mov	r2, r3
+ 8025c98:	4603      	mov	r3, r0
+ 8025c9a:	73fb      	strb	r3, [r7, #15]
+ 8025c9c:	4613      	mov	r3, r2
+ 8025c9e:	81bb      	strh	r3, [r7, #12]
+	uint32_t ActualTime = 0;
+ 8025ca0:	2300      	movs	r3, #0
+ 8025ca2:	617b      	str	r3, [r7, #20]
+
+	if(GetSystemTimeMs != NULL)
+ 8025ca4:	4b5b      	ldr	r3, [pc, #364]	@ (8025e14 <PrepareDltHeader+0x188>)
+ 8025ca6:	681b      	ldr	r3, [r3, #0]
+ 8025ca8:	2b00      	cmp	r3, #0
+ 8025caa:	d008      	beq.n	8025cbe <PrepareDltHeader+0x32>
+	{
+		ActualTime = GetSystemTimeMs() * 10U; 
+ 8025cac:	4b59      	ldr	r3, [pc, #356]	@ (8025e14 <PrepareDltHeader+0x188>)
+ 8025cae:	681b      	ldr	r3, [r3, #0]
+ 8025cb0:	4798      	blx	r3
+ 8025cb2:	4602      	mov	r2, r0
+ 8025cb4:	4613      	mov	r3, r2
+ 8025cb6:	009b      	lsls	r3, r3, #2
+ 8025cb8:	4413      	add	r3, r2
+ 8025cba:	005b      	lsls	r3, r3, #1
+ 8025cbc:	617b      	str	r3, [r7, #20]
+				/*Multiply by 10 to get value in MS also in DLTViewer
+				*Reson: Resolution in DLT Viewer is equal: 10^-4
+				*/
+	}
+
+	if(size > ((UINT8_MAX -1) - DLT_ACT_HEADER_SIZE) )
+ 8025cbe:	89bb      	ldrh	r3, [r7, #12]
+ 8025cc0:	2bde      	cmp	r3, #222	@ 0xde
+ 8025cc2:	d902      	bls.n	8025cca <PrepareDltHeader+0x3e>
+		/*Error to handle, or please develop this function to handle input size > UINT8_MAX */
+		// while(1)
+		// {
+		// 	/*For development phase: lock the app*/
+		// }
+		size = size - DLT_ACT_HEADER_SIZE -1;
+ 8025cc4:	89bb      	ldrh	r3, [r7, #12]
+ 8025cc6:	3b21      	subs	r3, #33	@ 0x21
+ 8025cc8:	81bb      	strh	r3, [r7, #12]
+	}
+
+
+	/*START HEADER*/
+	headerAddrStart[0] =  0x44; /*'D'*/
+ 8025cca:	6a3b      	ldr	r3, [r7, #32]
+ 8025ccc:	2244      	movs	r2, #68	@ 0x44
+ 8025cce:	701a      	strb	r2, [r3, #0]
+	headerAddrStart[1] =  0x4c; /*'L'*/
+ 8025cd0:	6a3b      	ldr	r3, [r7, #32]
+ 8025cd2:	3301      	adds	r3, #1
+ 8025cd4:	224c      	movs	r2, #76	@ 0x4c
+ 8025cd6:	701a      	strb	r2, [r3, #0]
+	headerAddrStart[2] =  0x53; /*'S'*/
+ 8025cd8:	6a3b      	ldr	r3, [r7, #32]
+ 8025cda:	3302      	adds	r3, #2
+ 8025cdc:	2253      	movs	r2, #83	@ 0x53
+ 8025cde:	701a      	strb	r2, [r3, #0]
+	headerAddrStart[3] =  0x01; /*'0x01'*/
+ 8025ce0:	6a3b      	ldr	r3, [r7, #32]
+ 8025ce2:	3303      	adds	r3, #3
+ 8025ce4:	2201      	movs	r2, #1
+ 8025ce6:	701a      	strb	r2, [r3, #0]
+
+
+	headerAddrStart[4] =  0x35; /*'Dlt base header config
+ 8025ce8:	6a3b      	ldr	r3, [r7, #32]
+ 8025cea:	3304      	adds	r3, #4
+ 8025cec:	2235      	movs	r2, #53	@ 0x35
+ 8025cee:	701a      	strb	r2, [r3, #0]
+	* With Seesion ID - false
+	* With time stamp - true
+	* version number -random
+	'*/
+
+	headerAddrStart[5] =  ActDltMessageCounter++; /*'Message counter value '*/
+ 8025cf0:	4b49      	ldr	r3, [pc, #292]	@ (8025e18 <PrepareDltHeader+0x18c>)
+ 8025cf2:	781b      	ldrb	r3, [r3, #0]
+ 8025cf4:	1c5a      	adds	r2, r3, #1
+ 8025cf6:	b2d1      	uxtb	r1, r2
+ 8025cf8:	4a47      	ldr	r2, [pc, #284]	@ (8025e18 <PrepareDltHeader+0x18c>)
+ 8025cfa:	7011      	strb	r1, [r2, #0]
+ 8025cfc:	6a3a      	ldr	r2, [r7, #32]
+ 8025cfe:	3205      	adds	r2, #5
+ 8025d00:	7013      	strb	r3, [r2, #0]
+
+	/*TODO: - it must be fixed!!!! - Length*/
+	headerAddrStart[6] =  0x00; /*Message length general*/
+ 8025d02:	6a3b      	ldr	r3, [r7, #32]
+ 8025d04:	3306      	adds	r3, #6
+ 8025d06:	2200      	movs	r2, #0
+ 8025d08:	701a      	strb	r2, [r3, #0]
+//	headerAddrStart[7] =  0x37; /*'Message length general '*/
+	headerAddrStart[7]=28+size; /*General size */
+ 8025d0a:	89bb      	ldrh	r3, [r7, #12]
+ 8025d0c:	b2da      	uxtb	r2, r3
+ 8025d0e:	6a3b      	ldr	r3, [r7, #32]
+ 8025d10:	3307      	adds	r3, #7
+ 8025d12:	321c      	adds	r2, #28
+ 8025d14:	b2d2      	uxtb	r2, r2
+ 8025d16:	701a      	strb	r2, [r3, #0]
+
+
+	uint32_t TempEcuId = DLT_LOG_ECUID_VALUE;
+ 8025d18:	2375      	movs	r3, #117	@ 0x75
+ 8025d1a:	061a      	lsls	r2, r3, #24
+ 8025d1c:	2343      	movs	r3, #67	@ 0x43
+ 8025d1e:	041b      	lsls	r3, r3, #16
+ 8025d20:	431a      	orrs	r2, r3
+ 8025d22:	2349      	movs	r3, #73	@ 0x49
+ 8025d24:	021b      	lsls	r3, r3, #8
+ 8025d26:	4313      	orrs	r3, r2
+ 8025d28:	2244      	movs	r2, #68	@ 0x44
+ 8025d2a:	4313      	orrs	r3, r2
+ 8025d2c:	613b      	str	r3, [r7, #16]
+	/*ECU ID*/
+	headerAddrStart[8]= ((uint8_t*)&TempEcuId)[3];
+ 8025d2e:	6a3b      	ldr	r3, [r7, #32]
+ 8025d30:	3308      	adds	r3, #8
+ 8025d32:	7cfa      	ldrb	r2, [r7, #19]
+ 8025d34:	701a      	strb	r2, [r3, #0]
+	headerAddrStart[9]= ((uint8_t*)&TempEcuId)[2];
+ 8025d36:	6a3b      	ldr	r3, [r7, #32]
+ 8025d38:	3309      	adds	r3, #9
+ 8025d3a:	7cba      	ldrb	r2, [r7, #18]
+ 8025d3c:	701a      	strb	r2, [r3, #0]
+	headerAddrStart[10]= ((uint8_t*)&TempEcuId)[1];
+ 8025d3e:	6a3b      	ldr	r3, [r7, #32]
+ 8025d40:	330a      	adds	r3, #10
+ 8025d42:	7c7a      	ldrb	r2, [r7, #17]
+ 8025d44:	701a      	strb	r2, [r3, #0]
+	headerAddrStart[11]= ((uint8_t*)&TempEcuId)[0];
+ 8025d46:	f107 0210 	add.w	r2, r7, #16
+ 8025d4a:	6a3b      	ldr	r3, [r7, #32]
+ 8025d4c:	330b      	adds	r3, #11
+ 8025d4e:	7812      	ldrb	r2, [r2, #0]
+ 8025d50:	701a      	strb	r2, [r3, #0]
+
+	/*Time stamp*/
+	headerAddrStart[12]= ((uint8_t*)&ActualTime)[3];
+ 8025d52:	6a3b      	ldr	r3, [r7, #32]
+ 8025d54:	330c      	adds	r3, #12
+ 8025d56:	7dfa      	ldrb	r2, [r7, #23]
+ 8025d58:	701a      	strb	r2, [r3, #0]
+	headerAddrStart[13]= ((uint8_t*)&ActualTime)[2];
+ 8025d5a:	6a3b      	ldr	r3, [r7, #32]
+ 8025d5c:	330d      	adds	r3, #13
+ 8025d5e:	7dba      	ldrb	r2, [r7, #22]
+ 8025d60:	701a      	strb	r2, [r3, #0]
+	headerAddrStart[14]= ((uint8_t*)&ActualTime)[1];
+ 8025d62:	6a3b      	ldr	r3, [r7, #32]
+ 8025d64:	330e      	adds	r3, #14
+ 8025d66:	7d7a      	ldrb	r2, [r7, #21]
+ 8025d68:	701a      	strb	r2, [r3, #0]
+	headerAddrStart[15]= ((uint8_t*)&ActualTime)[0];
+ 8025d6a:	f107 0214 	add.w	r2, r7, #20
+ 8025d6e:	6a3b      	ldr	r3, [r7, #32]
+ 8025d70:	330f      	adds	r3, #15
+ 8025d72:	7812      	ldrb	r2, [r2, #0]
+ 8025d74:	701a      	strb	r2, [r3, #0]
+
+	/*Extended header --verbose | type serial*/
+//	headerAddrStart[16]= 0x41; /**/
+	headerAddrStart[16]= (Level << 4) | 1;
+ 8025d76:	7bfb      	ldrb	r3, [r7, #15]
+ 8025d78:	011b      	lsls	r3, r3, #4
+ 8025d7a:	b25b      	sxtb	r3, r3
+ 8025d7c:	f043 0301 	orr.w	r3, r3, #1
+ 8025d80:	b25a      	sxtb	r2, r3
+ 8025d82:	6a3b      	ldr	r3, [r7, #32]
+ 8025d84:	3310      	adds	r3, #16
+ 8025d86:	b2d2      	uxtb	r2, r2
+ 8025d88:	701a      	strb	r2, [r3, #0]
+
+	/*Number of arguments*/
+	headerAddrStart[17]= 0x01; /**/
+ 8025d8a:	6a3b      	ldr	r3, [r7, #32]
+ 8025d8c:	3311      	adds	r3, #17
+ 8025d8e:	2201      	movs	r2, #1
+ 8025d90:	701a      	strb	r2, [r3, #0]
+
+	/*App id */
+	headerAddrStart[18]= ((uint8_t*)&AppId)[3];
+ 8025d92:	6a3b      	ldr	r3, [r7, #32]
+ 8025d94:	3312      	adds	r3, #18
+ 8025d96:	7afa      	ldrb	r2, [r7, #11]
+ 8025d98:	701a      	strb	r2, [r3, #0]
+	headerAddrStart[19]= ((uint8_t*)&AppId)[2];
+ 8025d9a:	6a3b      	ldr	r3, [r7, #32]
+ 8025d9c:	3313      	adds	r3, #19
+ 8025d9e:	7aba      	ldrb	r2, [r7, #10]
+ 8025da0:	701a      	strb	r2, [r3, #0]
+	headerAddrStart[20]= ((uint8_t*)&AppId)[1];
+ 8025da2:	6a3b      	ldr	r3, [r7, #32]
+ 8025da4:	3314      	adds	r3, #20
+ 8025da6:	7a7a      	ldrb	r2, [r7, #9]
+ 8025da8:	701a      	strb	r2, [r3, #0]
+	headerAddrStart[21]= ((uint8_t*)&AppId)[0];
+ 8025daa:	f107 0208 	add.w	r2, r7, #8
+ 8025dae:	6a3b      	ldr	r3, [r7, #32]
+ 8025db0:	3315      	adds	r3, #21
+ 8025db2:	7812      	ldrb	r2, [r2, #0]
+ 8025db4:	701a      	strb	r2, [r3, #0]
+
+	/*Contex ID  (4 bytes*/
+	headerAddrStart[22]= ((uint8_t*)&ContextId)[3];
+ 8025db6:	6a3b      	ldr	r3, [r7, #32]
+ 8025db8:	3316      	adds	r3, #22
+ 8025dba:	79fa      	ldrb	r2, [r7, #7]
+ 8025dbc:	701a      	strb	r2, [r3, #0]
+	headerAddrStart[23]= ((uint8_t*)&ContextId)[2];
+ 8025dbe:	6a3b      	ldr	r3, [r7, #32]
+ 8025dc0:	3317      	adds	r3, #23
+ 8025dc2:	79ba      	ldrb	r2, [r7, #6]
+ 8025dc4:	701a      	strb	r2, [r3, #0]
+	headerAddrStart[24]= ((uint8_t*)&ContextId)[1];
+ 8025dc6:	6a3b      	ldr	r3, [r7, #32]
+ 8025dc8:	3318      	adds	r3, #24
+ 8025dca:	797a      	ldrb	r2, [r7, #5]
+ 8025dcc:	701a      	strb	r2, [r3, #0]
+	headerAddrStart[25]= ((uint8_t*)&ContextId)[0];
+ 8025dce:	1d3a      	adds	r2, r7, #4
+ 8025dd0:	6a3b      	ldr	r3, [r7, #32]
+ 8025dd2:	3319      	adds	r3, #25
+ 8025dd4:	7812      	ldrb	r2, [r2, #0]
+ 8025dd6:	701a      	strb	r2, [r3, #0]
+
+	/*Type info*/
+	headerAddrStart[26]= 0x01; /**/
+ 8025dd8:	6a3b      	ldr	r3, [r7, #32]
+ 8025dda:	331a      	adds	r3, #26
+ 8025ddc:	2201      	movs	r2, #1
+ 8025dde:	701a      	strb	r2, [r3, #0]
+	headerAddrStart[27]= 0x82; /**/
+ 8025de0:	6a3b      	ldr	r3, [r7, #32]
+ 8025de2:	331b      	adds	r3, #27
+ 8025de4:	2282      	movs	r2, #130	@ 0x82
+ 8025de6:	701a      	strb	r2, [r3, #0]
+	headerAddrStart[28]= 0x00; /**/
+ 8025de8:	6a3b      	ldr	r3, [r7, #32]
+ 8025dea:	331c      	adds	r3, #28
+ 8025dec:	2200      	movs	r2, #0
+ 8025dee:	701a      	strb	r2, [r3, #0]
+	headerAddrStart[29]= 0x00; /**/
+ 8025df0:	6a3b      	ldr	r3, [r7, #32]
+ 8025df2:	331d      	adds	r3, #29
+ 8025df4:	2200      	movs	r2, #0
+ 8025df6:	701a      	strb	r2, [r3, #0]
+
+	/*Argument 1*/
+	headerAddrStart[30]= size; 
+ 8025df8:	6a3b      	ldr	r3, [r7, #32]
+ 8025dfa:	331e      	adds	r3, #30
+ 8025dfc:	89ba      	ldrh	r2, [r7, #12]
+ 8025dfe:	b2d2      	uxtb	r2, r2
+ 8025e00:	701a      	strb	r2, [r3, #0]
+	/* Size of the load in simplified form, please verify in documentation of DLT protcool documentation */
+	headerAddrStart[31]= 0x00; /**/
+ 8025e02:	6a3b      	ldr	r3, [r7, #32]
+ 8025e04:	331f      	adds	r3, #31
+ 8025e06:	2200      	movs	r2, #0
+ 8025e08:	701a      	strb	r2, [r3, #0]
+}
+ 8025e0a:	bf00      	nop
+ 8025e0c:	3718      	adds	r7, #24
+ 8025e0e:	46bd      	mov	sp, r7
+ 8025e10:	bd80      	pop	{r7, pc}
+ 8025e12:	bf00      	nop
+ 8025e14:	24009120 	.word	0x24009120
+ 8025e18:	24009169 	.word	0x24009169
+
+08025e1c <DLTuc_RawDataReceiveDone>:
+ * Descriptions are added in header file
+ *****************************************************************************************************
+ */
+
+void DLTuc_RawDataReceiveDone(uint16_t Size)
+{
+ 8025e1c:	b590      	push	{r4, r7, lr}
+ 8025e1e:	b08d      	sub	sp, #52	@ 0x34
+ 8025e20:	af02      	add	r7, sp, #8
+ 8025e22:	4603      	mov	r3, r0
+ 8025e24:	80fb      	strh	r3, [r7, #6]
+	static uint8_t *MessageReceiveBufferAddress = NULL;
+	uint8_t *MessageToRead_p = NULL;
+ 8025e26:	2300      	movs	r3, #0
+ 8025e28:	60fb      	str	r3, [r7, #12]
+	uint8_t MessageToReadSize= 0U;
+ 8025e2a:	2300      	movs	r3, #0
+ 8025e2c:	72fb      	strb	r3, [r7, #11]
+
+	DLT_RB_Receive_GetNextMessageAddress(&BleMainReceiveRingBuffer,&MessageReceiveBufferAddress);
+ 8025e2e:	499d      	ldr	r1, [pc, #628]	@ (80260a4 <DLTuc_RawDataReceiveDone+0x288>)
+ 8025e30:	489d      	ldr	r0, [pc, #628]	@ (80260a8 <DLTuc_RawDataReceiveDone+0x28c>)
+ 8025e32:	f7ff fe27 	bl	8025a84 <DLT_RB_Receive_GetNextMessageAddress>
+	if(ExtSerialRecDataFunctionCb != NULL){
+ 8025e36:	4b9d      	ldr	r3, [pc, #628]	@ (80260ac <DLTuc_RawDataReceiveDone+0x290>)
+ 8025e38:	681b      	ldr	r3, [r3, #0]
+ 8025e3a:	2b00      	cmp	r3, #0
+ 8025e3c:	d006      	beq.n	8025e4c <DLTuc_RawDataReceiveDone+0x30>
+		ExtSerialRecDataFunctionCb(MessageReceiveBufferAddress,DLT_REC_SINGLE_MESSAGE_MAX_SIZE);
+ 8025e3e:	4b9b      	ldr	r3, [pc, #620]	@ (80260ac <DLTuc_RawDataReceiveDone+0x290>)
+ 8025e40:	681b      	ldr	r3, [r3, #0]
+ 8025e42:	4a98      	ldr	r2, [pc, #608]	@ (80260a4 <DLTuc_RawDataReceiveDone+0x288>)
+ 8025e44:	6812      	ldr	r2, [r2, #0]
+ 8025e46:	21ff      	movs	r1, #255	@ 0xff
+ 8025e48:	4610      	mov	r0, r2
+ 8025e4a:	4798      	blx	r3
+	/*
+	* The receive buffer isn't handled fully correctly, it require deeper investigation.
+	* However, it is possible to receive the Injection messages, and base commands if are transmitted with breakes..
+	* Received DTL messages are divided by the "IDLE" irq for now.., not by the size and etc...
+	*/
+	if(DLT_RB_Receive_Read(&BleMainReceiveRingBuffer, &MessageToReadSize,&MessageToRead_p) == RB_OK)
+ 8025e4c:	f107 020c 	add.w	r2, r7, #12
+ 8025e50:	f107 030b 	add.w	r3, r7, #11
+ 8025e54:	4619      	mov	r1, r3
+ 8025e56:	4894      	ldr	r0, [pc, #592]	@ (80260a8 <DLTuc_RawDataReceiveDone+0x28c>)
+ 8025e58:	f7ff fe54 	bl	8025b04 <DLT_RB_Receive_Read>
+ 8025e5c:	4603      	mov	r3, r0
+ 8025e5e:	2b00      	cmp	r3, #0
+ 8025e60:	f040 811c 	bne.w	802609c <DLTuc_RawDataReceiveDone+0x280>
+	{
+		if(MessageToRead_p[4] == 53) /**/
+ 8025e64:	68fb      	ldr	r3, [r7, #12]
+ 8025e66:	3304      	adds	r3, #4
+ 8025e68:	781b      	ldrb	r3, [r3, #0]
+ 8025e6a:	2b35      	cmp	r3, #53	@ 0x35
+ 8025e6c:	f040 8116 	bne.w	802609c <DLTuc_RawDataReceiveDone+0x280>
+			[18-21] - AppId
+			[22-25] - ContexId
+			[26-29] - ServiceId
+			[30-33] - Size*/
+
+			uint32_t AppId =         MessageToRead_p[21] << 24 |MessageToRead_p[20] << 16 | MessageToRead_p[19] << 8 | MessageToRead_p[18] << 0;
+ 8025e70:	68fb      	ldr	r3, [r7, #12]
+ 8025e72:	3315      	adds	r3, #21
+ 8025e74:	781b      	ldrb	r3, [r3, #0]
+ 8025e76:	061a      	lsls	r2, r3, #24
+ 8025e78:	68fb      	ldr	r3, [r7, #12]
+ 8025e7a:	3314      	adds	r3, #20
+ 8025e7c:	781b      	ldrb	r3, [r3, #0]
+ 8025e7e:	041b      	lsls	r3, r3, #16
+ 8025e80:	431a      	orrs	r2, r3
+ 8025e82:	68fb      	ldr	r3, [r7, #12]
+ 8025e84:	3313      	adds	r3, #19
+ 8025e86:	781b      	ldrb	r3, [r3, #0]
+ 8025e88:	021b      	lsls	r3, r3, #8
+ 8025e8a:	4313      	orrs	r3, r2
+ 8025e8c:	68fa      	ldr	r2, [r7, #12]
+ 8025e8e:	3212      	adds	r2, #18
+ 8025e90:	7812      	ldrb	r2, [r2, #0]
+ 8025e92:	4313      	orrs	r3, r2
+ 8025e94:	627b      	str	r3, [r7, #36]	@ 0x24
+			uint32_t RecContexId =   MessageToRead_p[25] << 24 |MessageToRead_p[24] << 16 | MessageToRead_p[23] << 8 | MessageToRead_p[22] << 0;
+ 8025e96:	68fb      	ldr	r3, [r7, #12]
+ 8025e98:	3319      	adds	r3, #25
+ 8025e9a:	781b      	ldrb	r3, [r3, #0]
+ 8025e9c:	061a      	lsls	r2, r3, #24
+ 8025e9e:	68fb      	ldr	r3, [r7, #12]
+ 8025ea0:	3318      	adds	r3, #24
+ 8025ea2:	781b      	ldrb	r3, [r3, #0]
+ 8025ea4:	041b      	lsls	r3, r3, #16
+ 8025ea6:	431a      	orrs	r2, r3
+ 8025ea8:	68fb      	ldr	r3, [r7, #12]
+ 8025eaa:	3317      	adds	r3, #23
+ 8025eac:	781b      	ldrb	r3, [r3, #0]
+ 8025eae:	021b      	lsls	r3, r3, #8
+ 8025eb0:	4313      	orrs	r3, r2
+ 8025eb2:	68fa      	ldr	r2, [r7, #12]
+ 8025eb4:	3216      	adds	r2, #22
+ 8025eb6:	7812      	ldrb	r2, [r2, #0]
+ 8025eb8:	4313      	orrs	r3, r2
+ 8025eba:	623b      	str	r3, [r7, #32]
+			uint32_t RecServiceId =  MessageToRead_p[29] << 24 |MessageToRead_p[28] << 16 | MessageToRead_p[27] << 8 | MessageToRead_p[26] << 0;
+ 8025ebc:	68fb      	ldr	r3, [r7, #12]
+ 8025ebe:	331d      	adds	r3, #29
+ 8025ec0:	781b      	ldrb	r3, [r3, #0]
+ 8025ec2:	061a      	lsls	r2, r3, #24
+ 8025ec4:	68fb      	ldr	r3, [r7, #12]
+ 8025ec6:	331c      	adds	r3, #28
+ 8025ec8:	781b      	ldrb	r3, [r3, #0]
+ 8025eca:	041b      	lsls	r3, r3, #16
+ 8025ecc:	431a      	orrs	r2, r3
+ 8025ece:	68fb      	ldr	r3, [r7, #12]
+ 8025ed0:	331b      	adds	r3, #27
+ 8025ed2:	781b      	ldrb	r3, [r3, #0]
+ 8025ed4:	021b      	lsls	r3, r3, #8
+ 8025ed6:	4313      	orrs	r3, r2
+ 8025ed8:	68fa      	ldr	r2, [r7, #12]
+ 8025eda:	321a      	adds	r2, #26
+ 8025edc:	7812      	ldrb	r2, [r2, #0]
+ 8025ede:	4313      	orrs	r3, r2
+ 8025ee0:	61fb      	str	r3, [r7, #28]
+
+			if(RecServiceId >= DLT_SERVICE_ID_CALLSW_CINJECTION)
+ 8025ee2:	69fb      	ldr	r3, [r7, #28]
+ 8025ee4:	f640 72fe 	movw	r2, #4094	@ 0xffe
+ 8025ee8:	4293      	cmp	r3, r2
+ 8025eea:	d925      	bls.n	8025f38 <DLTuc_RawDataReceiveDone+0x11c>
+			{
+				if(NULL != ExtInfoInjectionDataRcvdCb)
+ 8025eec:	4b70      	ldr	r3, [pc, #448]	@ (80260b0 <DLTuc_RawDataReceiveDone+0x294>)
+ 8025eee:	681b      	ldr	r3, [r3, #0]
+ 8025ef0:	2b00      	cmp	r3, #0
+ 8025ef2:	f000 80d3 	beq.w	802609c <DLTuc_RawDataReceiveDone+0x280>
+				{
+					/*MSB LSB, wtf..?, it is somehow mixed? */
+					uint32_t DltDatSize =  MessageToRead_p[33] << 24 | MessageToRead_p[32] << 16 | MessageToRead_p[31] << 8 | MessageToRead_p[30] << 0;
+ 8025ef6:	68fb      	ldr	r3, [r7, #12]
+ 8025ef8:	3321      	adds	r3, #33	@ 0x21
+ 8025efa:	781b      	ldrb	r3, [r3, #0]
+ 8025efc:	061a      	lsls	r2, r3, #24
+ 8025efe:	68fb      	ldr	r3, [r7, #12]
+ 8025f00:	3320      	adds	r3, #32
+ 8025f02:	781b      	ldrb	r3, [r3, #0]
+ 8025f04:	041b      	lsls	r3, r3, #16
+ 8025f06:	431a      	orrs	r2, r3
+ 8025f08:	68fb      	ldr	r3, [r7, #12]
+ 8025f0a:	331f      	adds	r3, #31
+ 8025f0c:	781b      	ldrb	r3, [r3, #0]
+ 8025f0e:	021b      	lsls	r3, r3, #8
+ 8025f10:	4313      	orrs	r3, r2
+ 8025f12:	68fa      	ldr	r2, [r7, #12]
+ 8025f14:	321e      	adds	r2, #30
+ 8025f16:	7812      	ldrb	r2, [r2, #0]
+ 8025f18:	4313      	orrs	r3, r2
+ 8025f1a:	613b      	str	r3, [r7, #16]
+
+					ExtInfoInjectionDataRcvdCb(AppId,RecContexId,RecServiceId,&MessageToRead_p[34],(uint16_t)DltDatSize);
+ 8025f1c:	4b64      	ldr	r3, [pc, #400]	@ (80260b0 <DLTuc_RawDataReceiveDone+0x294>)
+ 8025f1e:	681c      	ldr	r4, [r3, #0]
+ 8025f20:	68fb      	ldr	r3, [r7, #12]
+ 8025f22:	f103 0222 	add.w	r2, r3, #34	@ 0x22
+ 8025f26:	693b      	ldr	r3, [r7, #16]
+ 8025f28:	b29b      	uxth	r3, r3
+ 8025f2a:	9300      	str	r3, [sp, #0]
+ 8025f2c:	4613      	mov	r3, r2
+ 8025f2e:	69fa      	ldr	r2, [r7, #28]
+ 8025f30:	6a39      	ldr	r1, [r7, #32]
+ 8025f32:	6a78      	ldr	r0, [r7, #36]	@ 0x24
+ 8025f34:	47a0      	blx	r4
+			{
+				LOG("Default log level: %d", DLT_LOG_ENABLE_LEVEL);
+			}
+		}
+	}
+}
+ 8025f36:	e0b1      	b.n	802609c <DLTuc_RawDataReceiveDone+0x280>
+			else if(RecServiceId == DLT_SERVICE_ID_SET_LOG_LEVEL)
+ 8025f38:	69fb      	ldr	r3, [r7, #28]
+ 8025f3a:	2b01      	cmp	r3, #1
+ 8025f3c:	d124      	bne.n	8025f88 <DLTuc_RawDataReceiveDone+0x16c>
+				uint32_t NewLogLevel =  MessageToRead_p[30];
+ 8025f3e:	68fb      	ldr	r3, [r7, #12]
+ 8025f40:	331e      	adds	r3, #30
+ 8025f42:	781b      	ldrb	r3, [r3, #0]
+ 8025f44:	617b      	str	r3, [r7, #20]
+				LOG("Set new log level request: %d How you triggered it?? , not supported", NewLogLevel);
+ 8025f46:	4b5b      	ldr	r3, [pc, #364]	@ (80260b4 <DLTuc_RawDataReceiveDone+0x298>)
+ 8025f48:	781b      	ldrb	r3, [r3, #0]
+ 8025f4a:	2b03      	cmp	r3, #3
+ 8025f4c:	f240 80a6 	bls.w	802609c <DLTuc_RawDataReceiveDone+0x280>
+ 8025f50:	2330      	movs	r3, #48	@ 0x30
+ 8025f52:	061a      	lsls	r2, r3, #24
+ 8025f54:	2330      	movs	r3, #48	@ 0x30
+ 8025f56:	041b      	lsls	r3, r3, #16
+ 8025f58:	431a      	orrs	r2, r3
+ 8025f5a:	2330      	movs	r3, #48	@ 0x30
+ 8025f5c:	021b      	lsls	r3, r3, #8
+ 8025f5e:	4313      	orrs	r3, r2
+ 8025f60:	2230      	movs	r2, #48	@ 0x30
+ 8025f62:	ea43 0102 	orr.w	r1, r3, r2
+ 8025f66:	2344      	movs	r3, #68	@ 0x44
+ 8025f68:	061a      	lsls	r2, r3, #24
+ 8025f6a:	2346      	movs	r3, #70	@ 0x46
+ 8025f6c:	041b      	lsls	r3, r3, #16
+ 8025f6e:	431a      	orrs	r2, r3
+ 8025f70:	234c      	movs	r3, #76	@ 0x4c
+ 8025f72:	021b      	lsls	r3, r3, #8
+ 8025f74:	4313      	orrs	r3, r2
+ 8025f76:	2254      	movs	r2, #84	@ 0x54
+ 8025f78:	431a      	orrs	r2, r3
+ 8025f7a:	697b      	ldr	r3, [r7, #20]
+ 8025f7c:	9300      	str	r3, [sp, #0]
+ 8025f7e:	4b4e      	ldr	r3, [pc, #312]	@ (80260b8 <DLTuc_RawDataReceiveDone+0x29c>)
+ 8025f80:	2004      	movs	r0, #4
+ 8025f82:	f000 f957 	bl	8026234 <DLTuc_LogOutVarArgs>
+}
+ 8025f86:	e089      	b.n	802609c <DLTuc_RawDataReceiveDone+0x280>
+			else if(RecServiceId == DLT_SERVICE_ID_SET_DEFAULT_LOG_LEVEL)
+ 8025f88:	69fb      	ldr	r3, [r7, #28]
+ 8025f8a:	2b11      	cmp	r3, #17
+ 8025f8c:	d140      	bne.n	8026010 <DLTuc_RawDataReceiveDone+0x1f4>
+				uint32_t NewLogLevel =  MessageToRead_p[30];
+ 8025f8e:	68fb      	ldr	r3, [r7, #12]
+ 8025f90:	331e      	adds	r3, #30
+ 8025f92:	781b      	ldrb	r3, [r3, #0]
+ 8025f94:	61bb      	str	r3, [r7, #24]
+				LOG("Set default log level request: %d", NewLogLevel);
+ 8025f96:	4b47      	ldr	r3, [pc, #284]	@ (80260b4 <DLTuc_RawDataReceiveDone+0x298>)
+ 8025f98:	781b      	ldrb	r3, [r3, #0]
+ 8025f9a:	2b03      	cmp	r3, #3
+ 8025f9c:	d91a      	bls.n	8025fd4 <DLTuc_RawDataReceiveDone+0x1b8>
+ 8025f9e:	2330      	movs	r3, #48	@ 0x30
+ 8025fa0:	061a      	lsls	r2, r3, #24
+ 8025fa2:	2330      	movs	r3, #48	@ 0x30
+ 8025fa4:	041b      	lsls	r3, r3, #16
+ 8025fa6:	431a      	orrs	r2, r3
+ 8025fa8:	2330      	movs	r3, #48	@ 0x30
+ 8025faa:	021b      	lsls	r3, r3, #8
+ 8025fac:	4313      	orrs	r3, r2
+ 8025fae:	2230      	movs	r2, #48	@ 0x30
+ 8025fb0:	ea43 0102 	orr.w	r1, r3, r2
+ 8025fb4:	2344      	movs	r3, #68	@ 0x44
+ 8025fb6:	061a      	lsls	r2, r3, #24
+ 8025fb8:	2346      	movs	r3, #70	@ 0x46
+ 8025fba:	041b      	lsls	r3, r3, #16
+ 8025fbc:	431a      	orrs	r2, r3
+ 8025fbe:	234c      	movs	r3, #76	@ 0x4c
+ 8025fc0:	021b      	lsls	r3, r3, #8
+ 8025fc2:	4313      	orrs	r3, r2
+ 8025fc4:	2254      	movs	r2, #84	@ 0x54
+ 8025fc6:	431a      	orrs	r2, r3
+ 8025fc8:	69bb      	ldr	r3, [r7, #24]
+ 8025fca:	9300      	str	r3, [sp, #0]
+ 8025fcc:	4b3b      	ldr	r3, [pc, #236]	@ (80260bc <DLTuc_RawDataReceiveDone+0x2a0>)
+ 8025fce:	2004      	movs	r0, #4
+ 8025fd0:	f000 f930 	bl	8026234 <DLTuc_LogOutVarArgs>
+				LOG("Not supported yet, I'm too lazy :)");
+ 8025fd4:	4b37      	ldr	r3, [pc, #220]	@ (80260b4 <DLTuc_RawDataReceiveDone+0x298>)
+ 8025fd6:	781b      	ldrb	r3, [r3, #0]
+ 8025fd8:	2b03      	cmp	r3, #3
+ 8025fda:	d95f      	bls.n	802609c <DLTuc_RawDataReceiveDone+0x280>
+ 8025fdc:	2330      	movs	r3, #48	@ 0x30
+ 8025fde:	061a      	lsls	r2, r3, #24
+ 8025fe0:	2330      	movs	r3, #48	@ 0x30
+ 8025fe2:	041b      	lsls	r3, r3, #16
+ 8025fe4:	431a      	orrs	r2, r3
+ 8025fe6:	2330      	movs	r3, #48	@ 0x30
+ 8025fe8:	021b      	lsls	r3, r3, #8
+ 8025fea:	4313      	orrs	r3, r2
+ 8025fec:	2230      	movs	r2, #48	@ 0x30
+ 8025fee:	ea43 0102 	orr.w	r1, r3, r2
+ 8025ff2:	2344      	movs	r3, #68	@ 0x44
+ 8025ff4:	061a      	lsls	r2, r3, #24
+ 8025ff6:	2346      	movs	r3, #70	@ 0x46
+ 8025ff8:	041b      	lsls	r3, r3, #16
+ 8025ffa:	431a      	orrs	r2, r3
+ 8025ffc:	234c      	movs	r3, #76	@ 0x4c
+ 8025ffe:	021b      	lsls	r3, r3, #8
+ 8026000:	4313      	orrs	r3, r2
+ 8026002:	2254      	movs	r2, #84	@ 0x54
+ 8026004:	431a      	orrs	r2, r3
+ 8026006:	4b2e      	ldr	r3, [pc, #184]	@ (80260c0 <DLTuc_RawDataReceiveDone+0x2a4>)
+ 8026008:	2004      	movs	r0, #4
+ 802600a:	f000 f913 	bl	8026234 <DLTuc_LogOutVarArgs>
+}
+ 802600e:	e045      	b.n	802609c <DLTuc_RawDataReceiveDone+0x280>
+			else if(DLT_SERVICE_ID_GET_SOFTWARE_VERSION == RecServiceId)
+ 8026010:	69fb      	ldr	r3, [r7, #28]
+ 8026012:	2b13      	cmp	r3, #19
+ 8026014:	d11f      	bne.n	8026056 <DLTuc_RawDataReceiveDone+0x23a>
+				LOG("ECU_SW_VERSION: %d", DLT_ECU_SW_VER);
+ 8026016:	4b27      	ldr	r3, [pc, #156]	@ (80260b4 <DLTuc_RawDataReceiveDone+0x298>)
+ 8026018:	781b      	ldrb	r3, [r3, #0]
+ 802601a:	2b03      	cmp	r3, #3
+ 802601c:	d93e      	bls.n	802609c <DLTuc_RawDataReceiveDone+0x280>
+ 802601e:	2330      	movs	r3, #48	@ 0x30
+ 8026020:	061a      	lsls	r2, r3, #24
+ 8026022:	2330      	movs	r3, #48	@ 0x30
+ 8026024:	041b      	lsls	r3, r3, #16
+ 8026026:	431a      	orrs	r2, r3
+ 8026028:	2330      	movs	r3, #48	@ 0x30
+ 802602a:	021b      	lsls	r3, r3, #8
+ 802602c:	4313      	orrs	r3, r2
+ 802602e:	2230      	movs	r2, #48	@ 0x30
+ 8026030:	ea43 0102 	orr.w	r1, r3, r2
+ 8026034:	2344      	movs	r3, #68	@ 0x44
+ 8026036:	061a      	lsls	r2, r3, #24
+ 8026038:	2346      	movs	r3, #70	@ 0x46
+ 802603a:	041b      	lsls	r3, r3, #16
+ 802603c:	431a      	orrs	r2, r3
+ 802603e:	234c      	movs	r3, #76	@ 0x4c
+ 8026040:	021b      	lsls	r3, r3, #8
+ 8026042:	4313      	orrs	r3, r2
+ 8026044:	2254      	movs	r2, #84	@ 0x54
+ 8026046:	431a      	orrs	r2, r3
+ 8026048:	2301      	movs	r3, #1
+ 802604a:	9300      	str	r3, [sp, #0]
+ 802604c:	4b1d      	ldr	r3, [pc, #116]	@ (80260c4 <DLTuc_RawDataReceiveDone+0x2a8>)
+ 802604e:	2004      	movs	r0, #4
+ 8026050:	f000 f8f0 	bl	8026234 <DLTuc_LogOutVarArgs>
+}
+ 8026054:	e022      	b.n	802609c <DLTuc_RawDataReceiveDone+0x280>
+			else if(DLT_SERVICE_ID_GET_DEFAULT_LOG_LEVEL == RecServiceId)
+ 8026056:	69fb      	ldr	r3, [r7, #28]
+ 8026058:	2b04      	cmp	r3, #4
+ 802605a:	d11f      	bne.n	802609c <DLTuc_RawDataReceiveDone+0x280>
+				LOG("Default log level: %d", DLT_LOG_ENABLE_LEVEL);
+ 802605c:	4b15      	ldr	r3, [pc, #84]	@ (80260b4 <DLTuc_RawDataReceiveDone+0x298>)
+ 802605e:	781b      	ldrb	r3, [r3, #0]
+ 8026060:	2b03      	cmp	r3, #3
+ 8026062:	d91b      	bls.n	802609c <DLTuc_RawDataReceiveDone+0x280>
+ 8026064:	2330      	movs	r3, #48	@ 0x30
+ 8026066:	061a      	lsls	r2, r3, #24
+ 8026068:	2330      	movs	r3, #48	@ 0x30
+ 802606a:	041b      	lsls	r3, r3, #16
+ 802606c:	431a      	orrs	r2, r3
+ 802606e:	2330      	movs	r3, #48	@ 0x30
+ 8026070:	021b      	lsls	r3, r3, #8
+ 8026072:	4313      	orrs	r3, r2
+ 8026074:	2230      	movs	r2, #48	@ 0x30
+ 8026076:	ea43 0102 	orr.w	r1, r3, r2
+ 802607a:	2344      	movs	r3, #68	@ 0x44
+ 802607c:	061a      	lsls	r2, r3, #24
+ 802607e:	2346      	movs	r3, #70	@ 0x46
+ 8026080:	041b      	lsls	r3, r3, #16
+ 8026082:	431a      	orrs	r2, r3
+ 8026084:	234c      	movs	r3, #76	@ 0x4c
+ 8026086:	021b      	lsls	r3, r3, #8
+ 8026088:	4313      	orrs	r3, r2
+ 802608a:	2254      	movs	r2, #84	@ 0x54
+ 802608c:	431a      	orrs	r2, r3
+ 802608e:	4b09      	ldr	r3, [pc, #36]	@ (80260b4 <DLTuc_RawDataReceiveDone+0x298>)
+ 8026090:	781b      	ldrb	r3, [r3, #0]
+ 8026092:	9300      	str	r3, [sp, #0]
+ 8026094:	4b0c      	ldr	r3, [pc, #48]	@ (80260c8 <DLTuc_RawDataReceiveDone+0x2ac>)
+ 8026096:	2004      	movs	r0, #4
+ 8026098:	f000 f8cc 	bl	8026234 <DLTuc_LogOutVarArgs>
+}
+ 802609c:	bf00      	nop
+ 802609e:	372c      	adds	r7, #44	@ 0x2c
+ 80260a0:	46bd      	mov	sp, r7
+ 80260a2:	bd90      	pop	{r4, r7, pc}
+ 80260a4:	2400a368 	.word	0x2400a368
+ 80260a8:	2400a060 	.word	0x2400a060
+ 80260ac:	24009118 	.word	0x24009118
+ 80260b0:	2400911c 	.word	0x2400911c
+ 80260b4:	24009110 	.word	0x24009110
+ 80260b8:	080412d4 	.word	0x080412d4
+ 80260bc:	0804131c 	.word	0x0804131c
+ 80260c0:	08041340 	.word	0x08041340
+ 80260c4:	08041364 	.word	0x08041364
+ 80260c8:	08041378 	.word	0x08041378
+
+080260cc <DLTuc_RegisterInjectionDataReceivedCb>:
+
+void DLTuc_RegisterInjectionDataReceivedCb(
+	void InjectionDataRcvd(uint32_t AppId, uint32_t ConId,uint32_t ServId,uint8_t *Data, uint16_t Size))
+{
+ 80260cc:	b480      	push	{r7}
+ 80260ce:	b083      	sub	sp, #12
+ 80260d0:	af00      	add	r7, sp, #0
+ 80260d2:	6078      	str	r0, [r7, #4]
+	ExtInfoInjectionDataRcvdCb = InjectionDataRcvd;
+ 80260d4:	4a04      	ldr	r2, [pc, #16]	@ (80260e8 <DLTuc_RegisterInjectionDataReceivedCb+0x1c>)
+ 80260d6:	687b      	ldr	r3, [r7, #4]
+ 80260d8:	6013      	str	r3, [r2, #0]
+}
+ 80260da:	bf00      	nop
+ 80260dc:	370c      	adds	r7, #12
+ 80260de:	46bd      	mov	sp, r7
+ 80260e0:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80260e4:	4770      	bx	lr
+ 80260e6:	bf00      	nop
+ 80260e8:	2400911c 	.word	0x2400911c
+
+080260ec <DLTuc_RegisterReceiveSerialDataFunction>:
+
+void DLTuc_RegisterReceiveSerialDataFunction(void LLSerialRecDataFunctionC(uint8_t *DltLogData, uint16_t Size))
+{
+ 80260ec:	b580      	push	{r7, lr}
+ 80260ee:	b082      	sub	sp, #8
+ 80260f0:	af00      	add	r7, sp, #0
+ 80260f2:	6078      	str	r0, [r7, #4]
+	ExtSerialRecDataFunctionCb = LLSerialRecDataFunctionC;
+ 80260f4:	4a07      	ldr	r2, [pc, #28]	@ (8026114 <DLTuc_RegisterReceiveSerialDataFunction+0x28>)
+ 80260f6:	687b      	ldr	r3, [r7, #4]
+ 80260f8:	6013      	str	r3, [r2, #0]
+
+	if(ExtSerialRecDataFunctionCb != NULL)
+ 80260fa:	4b06      	ldr	r3, [pc, #24]	@ (8026114 <DLTuc_RegisterReceiveSerialDataFunction+0x28>)
+ 80260fc:	681b      	ldr	r3, [r3, #0]
+ 80260fe:	2b00      	cmp	r3, #0
+ 8026100:	d004      	beq.n	802610c <DLTuc_RegisterReceiveSerialDataFunction+0x20>
+	{
+		ExtSerialRecDataFunctionCb(&BluMainReceiveMessagesTab[0][0],DLT_REC_SINGLE_MESSAGE_MAX_SIZE);
+ 8026102:	4b04      	ldr	r3, [pc, #16]	@ (8026114 <DLTuc_RegisterReceiveSerialDataFunction+0x28>)
+ 8026104:	681b      	ldr	r3, [r3, #0]
+ 8026106:	21ff      	movs	r1, #255	@ 0xff
+ 8026108:	4803      	ldr	r0, [pc, #12]	@ (8026118 <DLTuc_RegisterReceiveSerialDataFunction+0x2c>)
+ 802610a:	4798      	blx	r3
+	}
+}
+ 802610c:	bf00      	nop
+ 802610e:	3708      	adds	r7, #8
+ 8026110:	46bd      	mov	sp, r7
+ 8026112:	bd80      	pop	{r7, pc}
+ 8026114:	24009118 	.word	0x24009118
+ 8026118:	2400a068 	.word	0x2400a068
+
+0802611c <DLTuc_RegisterTransmitSerialDataFunction>:
+
+void DLTuc_RegisterTransmitSerialDataFunction(void LLSerialTrDataFunctionC(uint8_t *DltLogData, uint8_t Size))
+{
+ 802611c:	b580      	push	{r7, lr}
+ 802611e:	b086      	sub	sp, #24
+ 8026120:	af02      	add	r7, sp, #8
+ 8026122:	6078      	str	r0, [r7, #4]
+	ExtSerialTrDataFunctionCb = LLSerialTrDataFunctionC;
+ 8026124:	4a11      	ldr	r2, [pc, #68]	@ (802616c <DLTuc_RegisterTransmitSerialDataFunction+0x50>)
+ 8026126:	687b      	ldr	r3, [r7, #4]
+ 8026128:	6013      	str	r3, [r2, #0]
+
+	/*Preapre LOG DROP Info Log*/
+	/* 0x444C5443 - In Ascii code it is: DLTC. It is more convience to put magic numbers here :) */
+	PrepareDltHeader(DL_ERROR,0x444C5443, 0x444C5443,sizeof(DltLogDroppedInfo),DltLogDroppedInfoBuffer);
+ 802612a:	4b11      	ldr	r3, [pc, #68]	@ (8026170 <DLTuc_RegisterTransmitSerialDataFunction+0x54>)
+ 802612c:	9300      	str	r3, [sp, #0]
+ 802612e:	230f      	movs	r3, #15
+ 8026130:	4a10      	ldr	r2, [pc, #64]	@ (8026174 <DLTuc_RegisterTransmitSerialDataFunction+0x58>)
+ 8026132:	4910      	ldr	r1, [pc, #64]	@ (8026174 <DLTuc_RegisterTransmitSerialDataFunction+0x58>)
+ 8026134:	2002      	movs	r0, #2
+ 8026136:	f7ff fda9 	bl	8025c8c <PrepareDltHeader>
+	for(int i=0; i<sizeof(DltLogDroppedInfo); i++)
+ 802613a:	2300      	movs	r3, #0
+ 802613c:	60fb      	str	r3, [r7, #12]
+ 802613e:	e00a      	b.n	8026156 <DLTuc_RegisterTransmitSerialDataFunction+0x3a>
+	{
+		DltLogDroppedInfoBuffer[i+DLT_ACT_HEADER_SIZE] = DltLogDroppedInfo[i];
+ 8026140:	68fb      	ldr	r3, [r7, #12]
+ 8026142:	3320      	adds	r3, #32
+ 8026144:	490c      	ldr	r1, [pc, #48]	@ (8026178 <DLTuc_RegisterTransmitSerialDataFunction+0x5c>)
+ 8026146:	68fa      	ldr	r2, [r7, #12]
+ 8026148:	440a      	add	r2, r1
+ 802614a:	7811      	ldrb	r1, [r2, #0]
+ 802614c:	4a08      	ldr	r2, [pc, #32]	@ (8026170 <DLTuc_RegisterTransmitSerialDataFunction+0x54>)
+ 802614e:	54d1      	strb	r1, [r2, r3]
+	for(int i=0; i<sizeof(DltLogDroppedInfo); i++)
+ 8026150:	68fb      	ldr	r3, [r7, #12]
+ 8026152:	3301      	adds	r3, #1
+ 8026154:	60fb      	str	r3, [r7, #12]
+ 8026156:	68fb      	ldr	r3, [r7, #12]
+ 8026158:	2b0e      	cmp	r3, #14
+ 802615a:	d9f1      	bls.n	8026140 <DLTuc_RegisterTransmitSerialDataFunction+0x24>
+	}
+
+	DLtLogDroppedSize = DLT_ACT_HEADER_SIZE + sizeof(DltLogDroppedInfo);
+ 802615c:	4b07      	ldr	r3, [pc, #28]	@ (802617c <DLTuc_RegisterTransmitSerialDataFunction+0x60>)
+ 802615e:	222f      	movs	r2, #47	@ 0x2f
+ 8026160:	701a      	strb	r2, [r3, #0]
+}
+ 8026162:	bf00      	nop
+ 8026164:	3710      	adds	r7, #16
+ 8026166:	46bd      	mov	sp, r7
+ 8026168:	bd80      	pop	{r7, pc}
+ 802616a:	bf00      	nop
+ 802616c:	24009114 	.word	0x24009114
+ 8026170:	2400912c 	.word	0x2400912c
+ 8026174:	444c5443 	.word	0x444c5443
+ 8026178:	24000004 	.word	0x24000004
+ 802617c:	24009168 	.word	0x24009168
+
+08026180 <DLTuc_MessageTransmitDone>:
+
+void DLTuc_MessageTransmitDone(void)
+{
+ 8026180:	b580      	push	{r7, lr}
+ 8026182:	b084      	sub	sp, #16
+ 8026184:	af00      	add	r7, sp, #0
+	uint8_t TmpMessageSize=0;
+ 8026186:	2300      	movs	r3, #0
+ 8026188:	72fb      	strb	r3, [r7, #11]
+	uint8_t *TmpMessagePointer = NULL;
+ 802618a:	2300      	movs	r3, #0
+ 802618c:	607b      	str	r3, [r7, #4]
+	uint32_t ActualSysTime = 0u;
+ 802618e:	2300      	movs	r3, #0
+ 8026190:	60fb      	str	r3, [r7, #12]
+
+	if(GetSystemTimeMs != NULL)
+ 8026192:	4b20      	ldr	r3, [pc, #128]	@ (8026214 <DLTuc_MessageTransmitDone+0x94>)
+ 8026194:	681b      	ldr	r3, [r3, #0]
+ 8026196:	2b00      	cmp	r3, #0
+ 8026198:	d003      	beq.n	80261a2 <DLTuc_MessageTransmitDone+0x22>
+	{
+		ActualSysTime = GetSystemTimeMs();
+ 802619a:	4b1e      	ldr	r3, [pc, #120]	@ (8026214 <DLTuc_MessageTransmitDone+0x94>)
+ 802619c:	681b      	ldr	r3, [r3, #0]
+ 802619e:	4798      	blx	r3
+ 80261a0:	60f8      	str	r0, [r7, #12]
+	}
+
+	if(LogDroppedFlag == true && (ActualSysTime - PrevLogDropSendTime > DLT_MINIMUM_LOG_DROP_PERIOD) )
+ 80261a2:	4b1d      	ldr	r3, [pc, #116]	@ (8026218 <DLTuc_MessageTransmitDone+0x98>)
+ 80261a4:	781b      	ldrb	r3, [r3, #0]
+ 80261a6:	2b00      	cmp	r3, #0
+ 80261a8:	d017      	beq.n	80261da <DLTuc_MessageTransmitDone+0x5a>
+ 80261aa:	4b1c      	ldr	r3, [pc, #112]	@ (802621c <DLTuc_MessageTransmitDone+0x9c>)
+ 80261ac:	681b      	ldr	r3, [r3, #0]
+ 80261ae:	68fa      	ldr	r2, [r7, #12]
+ 80261b0:	1ad3      	subs	r3, r2, r3
+ 80261b2:	2bc8      	cmp	r3, #200	@ 0xc8
+ 80261b4:	d911      	bls.n	80261da <DLTuc_MessageTransmitDone+0x5a>
+	{
+		/* If DLTuc will always send the DROP Message info,
+		* then will not read any message from RB..*/
+		PrevLogDropSendTime = ActualSysTime;
+ 80261b6:	4a19      	ldr	r2, [pc, #100]	@ (802621c <DLTuc_MessageTransmitDone+0x9c>)
+ 80261b8:	68fb      	ldr	r3, [r7, #12]
+ 80261ba:	6013      	str	r3, [r2, #0]
+		LogDroppedFlag = false;
+ 80261bc:	4b16      	ldr	r3, [pc, #88]	@ (8026218 <DLTuc_MessageTransmitDone+0x98>)
+ 80261be:	2200      	movs	r2, #0
+ 80261c0:	701a      	strb	r2, [r3, #0]
+
+		if(ExtSerialTrDataFunctionCb != NULL)
+ 80261c2:	4b17      	ldr	r3, [pc, #92]	@ (8026220 <DLTuc_MessageTransmitDone+0xa0>)
+ 80261c4:	681b      	ldr	r3, [r3, #0]
+ 80261c6:	2b00      	cmp	r3, #0
+ 80261c8:	d020      	beq.n	802620c <DLTuc_MessageTransmitDone+0x8c>
+		{
+			ExtSerialTrDataFunctionCb(DltLogDroppedInfoBuffer, DLtLogDroppedSize);
+ 80261ca:	4b15      	ldr	r3, [pc, #84]	@ (8026220 <DLTuc_MessageTransmitDone+0xa0>)
+ 80261cc:	681b      	ldr	r3, [r3, #0]
+ 80261ce:	4a15      	ldr	r2, [pc, #84]	@ (8026224 <DLTuc_MessageTransmitDone+0xa4>)
+ 80261d0:	7812      	ldrb	r2, [r2, #0]
+ 80261d2:	4611      	mov	r1, r2
+ 80261d4:	4814      	ldr	r0, [pc, #80]	@ (8026228 <DLTuc_MessageTransmitDone+0xa8>)
+ 80261d6:	4798      	blx	r3
+ 80261d8:	e019      	b.n	802620e <DLTuc_MessageTransmitDone+0x8e>
+		}
+		return;
+	}
+
+	DLTuc_OS_CRITICAL_START();
+	if(DLT_RB_TransmitRead(&DltTrsmtRingBuffer,&TmpMessageSize,&TmpMessagePointer) == RB_OK)
+ 80261da:	1d3a      	adds	r2, r7, #4
+ 80261dc:	f107 030b 	add.w	r3, r7, #11
+ 80261e0:	4619      	mov	r1, r3
+ 80261e2:	4812      	ldr	r0, [pc, #72]	@ (802622c <DLTuc_MessageTransmitDone+0xac>)
+ 80261e4:	f7ff fcd6 	bl	8025b94 <DLT_RB_TransmitRead>
+ 80261e8:	4603      	mov	r3, r0
+ 80261ea:	2b00      	cmp	r3, #0
+ 80261ec:	d10a      	bne.n	8026204 <DLTuc_MessageTransmitDone+0x84>
+	{
+		if(ExtSerialTrDataFunctionCb != NULL)
+ 80261ee:	4b0c      	ldr	r3, [pc, #48]	@ (8026220 <DLTuc_MessageTransmitDone+0xa0>)
+ 80261f0:	681b      	ldr	r3, [r3, #0]
+ 80261f2:	2b00      	cmp	r3, #0
+ 80261f4:	d00b      	beq.n	802620e <DLTuc_MessageTransmitDone+0x8e>
+		{
+			DLTuc_OS_CRITICAL_END();
+			ExtSerialTrDataFunctionCb(TmpMessagePointer, TmpMessageSize);
+ 80261f6:	4b0a      	ldr	r3, [pc, #40]	@ (8026220 <DLTuc_MessageTransmitDone+0xa0>)
+ 80261f8:	681b      	ldr	r3, [r3, #0]
+ 80261fa:	687a      	ldr	r2, [r7, #4]
+ 80261fc:	7af9      	ldrb	r1, [r7, #11]
+ 80261fe:	4610      	mov	r0, r2
+ 8026200:	4798      	blx	r3
+ 8026202:	e004      	b.n	802620e <DLTuc_MessageTransmitDone+0x8e>
+		}
+	}
+	else
+	{
+		TransmitReadyStateFlag = true;
+ 8026204:	4b0a      	ldr	r3, [pc, #40]	@ (8026230 <DLTuc_MessageTransmitDone+0xb0>)
+ 8026206:	2201      	movs	r2, #1
+ 8026208:	701a      	strb	r2, [r3, #0]
+ 802620a:	e000      	b.n	802620e <DLTuc_MessageTransmitDone+0x8e>
+		return;
+ 802620c:	bf00      	nop
+	}
+	DLTuc_OS_CRITICAL_END();
+}
+ 802620e:	3710      	adds	r7, #16
+ 8026210:	46bd      	mov	sp, r7
+ 8026212:	bd80      	pop	{r7, pc}
+ 8026214:	24009120 	.word	0x24009120
+ 8026218:	24009124 	.word	0x24009124
+ 802621c:	24009128 	.word	0x24009128
+ 8026220:	24009114 	.word	0x24009114
+ 8026224:	24009168 	.word	0x24009168
+ 8026228:	2400912c 	.word	0x2400912c
+ 802622c:	24000014 	.word	0x24000014
+ 8026230:	24000036 	.word	0x24000036
+
+08026234 <DLTuc_LogOutVarArgs>:
+
+void DLTuc_LogOutVarArgs(DltLogLevel_t Level, uint32_t AppId, uint32_t ContextId, uint8_t *Payload, ...)
+{
+ 8026234:	b408      	push	{r3}
+ 8026236:	b580      	push	{r7, lr}
+ 8026238:	b08b      	sub	sp, #44	@ 0x2c
+ 802623a:	af02      	add	r7, sp, #8
+ 802623c:	4603      	mov	r3, r0
+ 802623e:	60b9      	str	r1, [r7, #8]
+ 8026240:	607a      	str	r2, [r7, #4]
+ 8026242:	73fb      	strb	r3, [r7, #15]
+	uint16_t Size;                        /*  */
+	uint8_t TmpMessageSize=0U;            /*  */
+ 8026244:	2300      	movs	r3, #0
+ 8026246:	777b      	strb	r3, [r7, #29]
+	uint8_t *TmpMessagePointer = NULL;    /*  */
+ 8026248:	2300      	movs	r3, #0
+ 802624a:	61bb      	str	r3, [r7, #24]
+	uint16_t writeIndex = 0U;             /*  */
+ 802624c:	2300      	movs	r3, #0
+ 802624e:	82fb      	strh	r3, [r7, #22]
+
+	if(DLT_RB_GetNextWriteIndex(&DltTrsmtRingBuffer,&writeIndex) != RB_OK)
+ 8026250:	f107 0316 	add.w	r3, r7, #22
+ 8026254:	4619      	mov	r1, r3
+ 8026256:	4840      	ldr	r0, [pc, #256]	@ (8026358 <DLTuc_LogOutVarArgs+0x124>)
+ 8026258:	f7ff fce2 	bl	8025c20 <DLT_RB_GetNextWriteIndex>
+ 802625c:	4603      	mov	r3, r0
+ 802625e:	2b00      	cmp	r3, #0
+ 8026260:	d003      	beq.n	802626a <DLTuc_LogOutVarArgs+0x36>
+	{
+		DLTuc_OS_CRITICAL_START();
+		LogDroppedFlag = true;
+ 8026262:	4b3e      	ldr	r3, [pc, #248]	@ (802635c <DLTuc_LogOutVarArgs+0x128>)
+ 8026264:	2201      	movs	r2, #1
+ 8026266:	701a      	strb	r2, [r3, #0]
+ 8026268:	e04f      	b.n	802630a <DLTuc_LogOutVarArgs+0xd6>
+	}
+	else
+	{
+		/* Put the DLT message data directly in ring buffer*/
+		va_list ap;                           /*  */
+		va_start(ap, Payload);
+ 802626a:	f107 0330 	add.w	r3, r7, #48	@ 0x30
+ 802626e:	613b      	str	r3, [r7, #16]
+		Size = vsprintf((char *)&(DltTrsmtMessagesTab[writeIndex][DLT_ACT_HEADER_SIZE]), (char *)Payload,ap);
+ 8026270:	8afb      	ldrh	r3, [r7, #22]
+ 8026272:	461a      	mov	r2, r3
+ 8026274:	4613      	mov	r3, r2
+ 8026276:	021b      	lsls	r3, r3, #8
+ 8026278:	1a9b      	subs	r3, r3, r2
+ 802627a:	3320      	adds	r3, #32
+ 802627c:	4a38      	ldr	r2, [pc, #224]	@ (8026360 <DLTuc_LogOutVarArgs+0x12c>)
+ 802627e:	4413      	add	r3, r2
+ 8026280:	693a      	ldr	r2, [r7, #16]
+ 8026282:	6af9      	ldr	r1, [r7, #44]	@ 0x2c
+ 8026284:	4618      	mov	r0, r3
+ 8026286:	f01a f825 	bl	80402d4 <vsiprintf>
+ 802628a:	4603      	mov	r3, r0
+ 802628c:	83fb      	strh	r3, [r7, #30]
+		va_end(ap);
+
+		Size += DLT_ACT_HEADER_SIZE;
+ 802628e:	8bfb      	ldrh	r3, [r7, #30]
+ 8026290:	3320      	adds	r3, #32
+ 8026292:	83fb      	strh	r3, [r7, #30]
+		/*Add additional zeros on the end of message - thanks to that it work stable */
+		Size++;
+ 8026294:	8bfb      	ldrh	r3, [r7, #30]
+ 8026296:	3301      	adds	r3, #1
+ 8026298:	83fb      	strh	r3, [r7, #30]
+		DltTrsmtMessagesTab[writeIndex][Size] = 0U;
+ 802629a:	8afb      	ldrh	r3, [r7, #22]
+ 802629c:	4618      	mov	r0, r3
+ 802629e:	8bfa      	ldrh	r2, [r7, #30]
+ 80262a0:	492f      	ldr	r1, [pc, #188]	@ (8026360 <DLTuc_LogOutVarArgs+0x12c>)
+ 80262a2:	4603      	mov	r3, r0
+ 80262a4:	021b      	lsls	r3, r3, #8
+ 80262a6:	1a1b      	subs	r3, r3, r0
+ 80262a8:	440b      	add	r3, r1
+ 80262aa:	4413      	add	r3, r2
+ 80262ac:	2200      	movs	r2, #0
+ 80262ae:	701a      	strb	r2, [r3, #0]
+		Size++;
+ 80262b0:	8bfb      	ldrh	r3, [r7, #30]
+ 80262b2:	3301      	adds	r3, #1
+ 80262b4:	83fb      	strh	r3, [r7, #30]
+		DltTrsmtMessagesTab[writeIndex][Size] = 0U;
+ 80262b6:	8afb      	ldrh	r3, [r7, #22]
+ 80262b8:	4618      	mov	r0, r3
+ 80262ba:	8bfa      	ldrh	r2, [r7, #30]
+ 80262bc:	4928      	ldr	r1, [pc, #160]	@ (8026360 <DLTuc_LogOutVarArgs+0x12c>)
+ 80262be:	4603      	mov	r3, r0
+ 80262c0:	021b      	lsls	r3, r3, #8
+ 80262c2:	1a1b      	subs	r3, r3, r0
+ 80262c4:	440b      	add	r3, r1
+ 80262c6:	4413      	add	r3, r2
+ 80262c8:	2200      	movs	r2, #0
+ 80262ca:	701a      	strb	r2, [r3, #0]
+
+		PrepareDltHeader(Level,AppId,ContextId,Size,&(DltTrsmtMessagesTab[writeIndex][0]));
+ 80262cc:	8afb      	ldrh	r3, [r7, #22]
+ 80262ce:	461a      	mov	r2, r3
+ 80262d0:	4613      	mov	r3, r2
+ 80262d2:	021b      	lsls	r3, r3, #8
+ 80262d4:	1a9b      	subs	r3, r3, r2
+ 80262d6:	4a22      	ldr	r2, [pc, #136]	@ (8026360 <DLTuc_LogOutVarArgs+0x12c>)
+ 80262d8:	4413      	add	r3, r2
+ 80262da:	8bfa      	ldrh	r2, [r7, #30]
+ 80262dc:	7bf8      	ldrb	r0, [r7, #15]
+ 80262de:	9300      	str	r3, [sp, #0]
+ 80262e0:	4613      	mov	r3, r2
+ 80262e2:	687a      	ldr	r2, [r7, #4]
+ 80262e4:	68b9      	ldr	r1, [r7, #8]
+ 80262e6:	f7ff fcd1 	bl	8025c8c <PrepareDltHeader>
+
+		Size = Size + DLT_ACT_HEADER_SIZE;
+ 80262ea:	8bfb      	ldrh	r3, [r7, #30]
+ 80262ec:	3320      	adds	r3, #32
+ 80262ee:	83fb      	strh	r3, [r7, #30]
+		DltTrsmtRingBuffer.dataSize[writeIndex] = Size;
+ 80262f0:	8afb      	ldrh	r3, [r7, #22]
+ 80262f2:	4619      	mov	r1, r3
+ 80262f4:	8bfb      	ldrh	r3, [r7, #30]
+ 80262f6:	b2da      	uxtb	r2, r3
+ 80262f8:	4b17      	ldr	r3, [pc, #92]	@ (8026358 <DLTuc_LogOutVarArgs+0x124>)
+ 80262fa:	440b      	add	r3, r1
+ 80262fc:	74da      	strb	r2, [r3, #19]
+
+		DLTuc_OS_CRITICAL_START();
+		DltTrsmtRingBuffer.readyToTransmit[writeIndex] = true;
+ 80262fe:	8afb      	ldrh	r3, [r7, #22]
+ 8026300:	461a      	mov	r2, r3
+ 8026302:	4b15      	ldr	r3, [pc, #84]	@ (8026358 <DLTuc_LogOutVarArgs+0x124>)
+ 8026304:	4413      	add	r3, r2
+ 8026306:	2201      	movs	r2, #1
+ 8026308:	711a      	strb	r2, [r3, #4]
+		DLTuc_OS_CRITICAL_END();
+	}
+
+	DLTuc_OS_CRITICAL_START();
+	if(TransmitReadyStateFlag == true)
+ 802630a:	4b16      	ldr	r3, [pc, #88]	@ (8026364 <DLTuc_LogOutVarArgs+0x130>)
+ 802630c:	781b      	ldrb	r3, [r3, #0]
+ 802630e:	b2db      	uxtb	r3, r3
+ 8026310:	2b01      	cmp	r3, #1
+ 8026312:	d11a      	bne.n	802634a <DLTuc_LogOutVarArgs+0x116>
+	{
+		if(DLT_RB_TransmitRead(&DltTrsmtRingBuffer,&TmpMessageSize,&TmpMessagePointer) == RB_OK)
+ 8026314:	f107 0218 	add.w	r2, r7, #24
+ 8026318:	f107 031d 	add.w	r3, r7, #29
+ 802631c:	4619      	mov	r1, r3
+ 802631e:	480e      	ldr	r0, [pc, #56]	@ (8026358 <DLTuc_LogOutVarArgs+0x124>)
+ 8026320:	f7ff fc38 	bl	8025b94 <DLT_RB_TransmitRead>
+ 8026324:	4603      	mov	r3, r0
+ 8026326:	2b00      	cmp	r3, #0
+ 8026328:	d10f      	bne.n	802634a <DLTuc_LogOutVarArgs+0x116>
+		{
+			if(TmpMessageSize != 0U)
+ 802632a:	7f7b      	ldrb	r3, [r7, #29]
+ 802632c:	2b00      	cmp	r3, #0
+ 802632e:	d00c      	beq.n	802634a <DLTuc_LogOutVarArgs+0x116>
+			{
+				TransmitReadyStateFlag = false;
+ 8026330:	4b0c      	ldr	r3, [pc, #48]	@ (8026364 <DLTuc_LogOutVarArgs+0x130>)
+ 8026332:	2200      	movs	r2, #0
+ 8026334:	701a      	strb	r2, [r3, #0]
+							/*Log transmission must be started in this contex...*/
+							/***********************************************/
+							/* It may be a bug in implementation - it must be investigated.. */
+							/* It's important to be aware of this fact!!*/
+							/***********************************************/
+				if(ExtSerialTrDataFunctionCb != NULL)
+ 8026336:	4b0c      	ldr	r3, [pc, #48]	@ (8026368 <DLTuc_LogOutVarArgs+0x134>)
+ 8026338:	681b      	ldr	r3, [r3, #0]
+ 802633a:	2b00      	cmp	r3, #0
+ 802633c:	d005      	beq.n	802634a <DLTuc_LogOutVarArgs+0x116>
+				{
+					ExtSerialTrDataFunctionCb(TmpMessagePointer, TmpMessageSize);
+ 802633e:	4b0a      	ldr	r3, [pc, #40]	@ (8026368 <DLTuc_LogOutVarArgs+0x134>)
+ 8026340:	681b      	ldr	r3, [r3, #0]
+ 8026342:	69ba      	ldr	r2, [r7, #24]
+ 8026344:	7f79      	ldrb	r1, [r7, #29]
+ 8026346:	4610      	mov	r0, r2
+ 8026348:	4798      	blx	r3
+				}
+			}
+		}
+	}
+	DLTuc_OS_CRITICAL_END();
+}
+ 802634a:	bf00      	nop
+ 802634c:	3724      	adds	r7, #36	@ 0x24
+ 802634e:	46bd      	mov	sp, r7
+ 8026350:	e8bd 4080 	ldmia.w	sp!, {r7, lr}
+ 8026354:	b001      	add	sp, #4
+ 8026356:	4770      	bx	lr
+ 8026358:	24000014 	.word	0x24000014
+ 802635c:	24009124 	.word	0x24009124
+ 8026360:	2400916c 	.word	0x2400916c
+ 8026364:	24000036 	.word	0x24000036
+ 8026368:	24009114 	.word	0x24009114
+
+0802636c <DLTuc_RegisterGetTimeStampMsCallback>:
+
+void DLTuc_RegisterGetTimeStampMsCallback(uint32_t GetSysTime(void))
+{
+ 802636c:	b480      	push	{r7}
+ 802636e:	b083      	sub	sp, #12
+ 8026370:	af00      	add	r7, sp, #0
+ 8026372:	6078      	str	r0, [r7, #4]
+	GetSystemTimeMs = GetSysTime;
+ 8026374:	4a04      	ldr	r2, [pc, #16]	@ (8026388 <DLTuc_RegisterGetTimeStampMsCallback+0x1c>)
+ 8026376:	687b      	ldr	r3, [r7, #4]
+ 8026378:	6013      	str	r3, [r2, #0]
+}
+ 802637a:	bf00      	nop
+ 802637c:	370c      	adds	r7, #12
+ 802637e:	46bd      	mov	sp, r7
+ 8026380:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8026384:	4770      	bx	lr
+ 8026386:	bf00      	nop
+ 8026388:	24009120 	.word	0x24009120
+
+0802638c <blast_control_intialize>:
+int BlastMachineEncodeHandle();
+bool encode_to_arrays(remote_code_t code1, remote_code_t code2,
+                     uint8_t array1[ARRAY_LENGTH], uint8_t array2[ARRAY_LENGTH]);
+
+void blast_control_intialize(struct UARTHandler *Handler)
+{
+ 802638c:	b480      	push	{r7}
+ 802638e:	b083      	sub	sp, #12
+ 8026390:	af00      	add	r7, sp, #0
+ 8026392:	6078      	str	r0, [r7, #4]
+	blastControl = Handler;
+ 8026394:	4a04      	ldr	r2, [pc, #16]	@ (80263a8 <blast_control_intialize+0x1c>)
+ 8026396:	687b      	ldr	r3, [r7, #4]
+ 8026398:	6013      	str	r3, [r2, #0]
+}
+ 802639a:	bf00      	nop
+ 802639c:	370c      	adds	r7, #12
+ 802639e:	46bd      	mov	sp, r7
+ 80263a0:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80263a4:	4770      	bx	lr
+ 80263a6:	bf00      	nop
+ 80263a8:	2400a36c 	.word	0x2400a36c
+
+080263ac <Blast_Machine_Control_Fun>:
+
+uint32_t blastMachineRemoteEncoder_1 = 0;
+uint32_t blastMachineRemoteEncoder_2 = 0;
+int blast_flag=1;
+void Blast_Machine_Control_Fun()
+{
+ 80263ac:	b580      	push	{r7, lr}
+ 80263ae:	af00      	add	r7, sp, #0
+	BlastMachineEncodeHandle();  //遥控器编码处理函数
+ 80263b0:	f000 f828 	bl	8026404 <BlastMachineEncodeHandle>
+
+	//只要有报错码就关喷砂机，没有的错的话再根据按键开喷砂机
+	if(((IV.SystemError!=0)&&(IV.SystemError!=2))||(IV.Left_Motor_Err!=0)||(IV.Right_Motor_Err!=0)||(IV.Swing_Motor_Err!=0))
+ 80263b4:	4b11      	ldr	r3, [pc, #68]	@ (80263fc <Blast_Machine_Control_Fun+0x50>)
+ 80263b6:	695b      	ldr	r3, [r3, #20]
+ 80263b8:	2b00      	cmp	r3, #0
+ 80263ba:	d003      	beq.n	80263c4 <Blast_Machine_Control_Fun+0x18>
+ 80263bc:	4b0f      	ldr	r3, [pc, #60]	@ (80263fc <Blast_Machine_Control_Fun+0x50>)
+ 80263be:	695b      	ldr	r3, [r3, #20]
+ 80263c0:	2b02      	cmp	r3, #2
+ 80263c2:	d10b      	bne.n	80263dc <Blast_Machine_Control_Fun+0x30>
+ 80263c4:	4b0d      	ldr	r3, [pc, #52]	@ (80263fc <Blast_Machine_Control_Fun+0x50>)
+ 80263c6:	699b      	ldr	r3, [r3, #24]
+ 80263c8:	2b00      	cmp	r3, #0
+ 80263ca:	d107      	bne.n	80263dc <Blast_Machine_Control_Fun+0x30>
+ 80263cc:	4b0b      	ldr	r3, [pc, #44]	@ (80263fc <Blast_Machine_Control_Fun+0x50>)
+ 80263ce:	69db      	ldr	r3, [r3, #28]
+ 80263d0:	2b00      	cmp	r3, #0
+ 80263d2:	d103      	bne.n	80263dc <Blast_Machine_Control_Fun+0x30>
+ 80263d4:	4b09      	ldr	r3, [pc, #36]	@ (80263fc <Blast_Machine_Control_Fun+0x50>)
+ 80263d6:	6a1b      	ldr	r3, [r3, #32]
+ 80263d8:	2b00      	cmp	r3, #0
+ 80263da:	d002      	beq.n	80263e2 <Blast_Machine_Control_Fun+0x36>
+	{
+		Blast_Machine_Close_Fun();
+ 80263dc:	f000 f8f0 	bl	80265c0 <Blast_Machine_Close_Fun>
+	else
+	{
+		Blast_Machine_Close_Fun();
+		//Blast_Machine_Open_Fun();
+	}
+}
+ 80263e0:	e00a      	b.n	80263f8 <Blast_Machine_Control_Fun+0x4c>
+	else if(P_MK32->CH6_SC==-1000)
+ 80263e2:	4b07      	ldr	r3, [pc, #28]	@ (8026400 <Blast_Machine_Control_Fun+0x54>)
+ 80263e4:	681b      	ldr	r3, [r3, #0]
+ 80263e6:	69db      	ldr	r3, [r3, #28]
+ 80263e8:	f513 7f7a 	cmn.w	r3, #1000	@ 0x3e8
+ 80263ec:	d102      	bne.n	80263f4 <Blast_Machine_Control_Fun+0x48>
+		Blast_Machine_Open_Fun();
+ 80263ee:	f000 f83f 	bl	8026470 <Blast_Machine_Open_Fun>
+}
+ 80263f2:	e001      	b.n	80263f8 <Blast_Machine_Control_Fun+0x4c>
+		Blast_Machine_Close_Fun();
+ 80263f4:	f000 f8e4 	bl	80265c0 <Blast_Machine_Close_Fun>
+}
+ 80263f8:	bf00      	nop
+ 80263fa:	bd80      	pop	{r7, pc}
+ 80263fc:	240005e0 	.word	0x240005e0
+ 8026400:	2400a3f8 	.word	0x2400a3f8
+
+08026404 <BlastMachineEncodeHandle>:
+uint8_t blastMachineRemoteEncoderCommand[ARRAY_LENGTH] = {0};
+uint8_t blastMachineRemoteEncoderCommand2[ARRAY_LENGTH] = {0};
+int BlastMachineEncodeHandle()
+{
+ 8026404:	b580      	push	{r7, lr}
+ 8026406:	b082      	sub	sp, #8
+ 8026408:	af00      	add	r7, sp, #0
+	if(P_MK32->CH6_SC!=-1000)
+ 802640a:	4b13      	ldr	r3, [pc, #76]	@ (8026458 <BlastMachineEncodeHandle+0x54>)
+ 802640c:	681b      	ldr	r3, [r3, #0]
+ 802640e:	69db      	ldr	r3, [r3, #28]
+ 8026410:	f513 7f7a 	cmn.w	r3, #1000	@ 0x3e8
+ 8026414:	d009      	beq.n	802642a <BlastMachineEncodeHandle+0x26>
+	{
+		blastMachineRemoteEncoder_1 = CV.PV.Robot_SandBalst_Encode_One;
+ 8026416:	4b11      	ldr	r3, [pc, #68]	@ (802645c <BlastMachineEncodeHandle+0x58>)
+ 8026418:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 802641a:	461a      	mov	r2, r3
+ 802641c:	4b10      	ldr	r3, [pc, #64]	@ (8026460 <BlastMachineEncodeHandle+0x5c>)
+ 802641e:	601a      	str	r2, [r3, #0]
+		blastMachineRemoteEncoder_2 = CV.PV.Robot_SandBalst_Encode_Two;
+ 8026420:	4b0e      	ldr	r3, [pc, #56]	@ (802645c <BlastMachineEncodeHandle+0x58>)
+ 8026422:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
+ 8026424:	461a      	mov	r2, r3
+ 8026426:	4b0f      	ldr	r3, [pc, #60]	@ (8026464 <BlastMachineEncodeHandle+0x60>)
+ 8026428:	601a      	str	r2, [r3, #0]
+	//	blastMachineRemoteEncoder_1 = 20212111;
+	//	blastMachineRemoteEncoder_2 = 20212222;
+	}
+
+    // 调用核心函数并检查返回值
+    bool encode_success = encode_to_arrays(blastMachineRemoteEncoder_1, blastMachineRemoteEncoder_2,
+ 802642a:	4b0d      	ldr	r3, [pc, #52]	@ (8026460 <BlastMachineEncodeHandle+0x5c>)
+ 802642c:	6818      	ldr	r0, [r3, #0]
+ 802642e:	4b0d      	ldr	r3, [pc, #52]	@ (8026464 <BlastMachineEncodeHandle+0x60>)
+ 8026430:	6819      	ldr	r1, [r3, #0]
+ 8026432:	4b0d      	ldr	r3, [pc, #52]	@ (8026468 <BlastMachineEncodeHandle+0x64>)
+ 8026434:	4a0d      	ldr	r2, [pc, #52]	@ (802646c <BlastMachineEncodeHandle+0x68>)
+ 8026436:	f000 fb25 	bl	8026a84 <encode_to_arrays>
+ 802643a:	4603      	mov	r3, r0
+ 802643c:	71fb      	strb	r3, [r7, #7]
+    									blastMachineRemoteEncoderCommand, blastMachineRemoteEncoderCommand2);
+    if (!encode_success) {
+ 802643e:	79fb      	ldrb	r3, [r7, #7]
+ 8026440:	f083 0301 	eor.w	r3, r3, #1
+ 8026444:	b2db      	uxtb	r3, r3
+ 8026446:	2b00      	cmp	r3, #0
+ 8026448:	d001      	beq.n	802644e <BlastMachineEncodeHandle+0x4a>
+        return 0;
+ 802644a:	2300      	movs	r3, #0
+ 802644c:	e7ff      	b.n	802644e <BlastMachineEncodeHandle+0x4a>
+    }
+}
+ 802644e:	4618      	mov	r0, r3
+ 8026450:	3708      	adds	r7, #8
+ 8026452:	46bd      	mov	sp, r7
+ 8026454:	bd80      	pop	{r7, pc}
+ 8026456:	bf00      	nop
+ 8026458:	2400a3f8 	.word	0x2400a3f8
+ 802645c:	240002a0 	.word	0x240002a0
+ 8026460:	2400a370 	.word	0x2400a370
+ 8026464:	2400a374 	.word	0x2400a374
+ 8026468:	2400a380 	.word	0x2400a380
+ 802646c:	2400a378 	.word	0x2400a378
+
+08026470 <Blast_Machine_Open_Fun>:
+uint32_t control_close_commend_counts = 0;
+int blast_times=5;  //每次执行发送5次
+uint32_t testcounts = 0;
+
+void Blast_Machine_Open_Fun()
+{
+ 8026470:	b580      	push	{r7, lr}
+ 8026472:	af00      	add	r7, sp, #0
+//	if(blast_flag==0)
+//	{
+	control_open_commend_counts++;
+ 8026474:	4b4c      	ldr	r3, [pc, #304]	@ (80265a8 <Blast_Machine_Open_Fun+0x138>)
+ 8026476:	681b      	ldr	r3, [r3, #0]
+ 8026478:	3301      	adds	r3, #1
+ 802647a:	4a4b      	ldr	r2, [pc, #300]	@ (80265a8 <Blast_Machine_Open_Fun+0x138>)
+ 802647c:	6013      	str	r3, [r2, #0]
+	//1. 先发送遥控器编码指令  2.发送开启指令
+	switch(control_open_commend_counts)
+ 802647e:	4b4a      	ldr	r3, [pc, #296]	@ (80265a8 <Blast_Machine_Open_Fun+0x138>)
+ 8026480:	681b      	ldr	r3, [r3, #0]
+ 8026482:	f5b3 7f96 	cmp.w	r3, #300	@ 0x12c
+ 8026486:	f000 8086 	beq.w	8026596 <Blast_Machine_Open_Fun+0x126>
+ 802648a:	f5b3 7f96 	cmp.w	r3, #300	@ 0x12c
+ 802648e:	f200 8089 	bhi.w	80265a4 <Blast_Machine_Open_Fun+0x134>
+ 8026492:	2bf0      	cmp	r3, #240	@ 0xf0
+ 8026494:	d062      	beq.n	802655c <Blast_Machine_Open_Fun+0xec>
+ 8026496:	2bf0      	cmp	r3, #240	@ 0xf0
+ 8026498:	f200 8084 	bhi.w	80265a4 <Blast_Machine_Open_Fun+0x134>
+ 802649c:	2bb4      	cmp	r3, #180	@ 0xb4
+ 802649e:	d040      	beq.n	8026522 <Blast_Machine_Open_Fun+0xb2>
+ 80264a0:	2bb4      	cmp	r3, #180	@ 0xb4
+ 80264a2:	d87f      	bhi.n	80265a4 <Blast_Machine_Open_Fun+0x134>
+ 80264a4:	2b3c      	cmp	r3, #60	@ 0x3c
+ 80264a6:	d002      	beq.n	80264ae <Blast_Machine_Open_Fun+0x3e>
+ 80264a8:	2b78      	cmp	r3, #120	@ 0x78
+ 80264aa:	d01d      	beq.n	80264e8 <Blast_Machine_Open_Fun+0x78>
+//					blast_times=5;
+//				}
+			break;
+	}
+//	}
+}
+ 80264ac:	e07a      	b.n	80265a4 <Blast_Machine_Open_Fun+0x134>
+			testcounts = 1;
+ 80264ae:	4b3f      	ldr	r3, [pc, #252]	@ (80265ac <Blast_Machine_Open_Fun+0x13c>)
+ 80264b0:	2201      	movs	r2, #1
+ 80264b2:	601a      	str	r2, [r3, #0]
+			memcpy(&blastControl->Tx_Buf, &blastMachineRemoteEncoderCommand, 8);
+ 80264b4:	4b3e      	ldr	r3, [pc, #248]	@ (80265b0 <Blast_Machine_Open_Fun+0x140>)
+ 80264b6:	681b      	ldr	r3, [r3, #0]
+ 80264b8:	f603 0321 	addw	r3, r3, #2081	@ 0x821
+ 80264bc:	493d      	ldr	r1, [pc, #244]	@ (80265b4 <Blast_Machine_Open_Fun+0x144>)
+ 80264be:	461a      	mov	r2, r3
+ 80264c0:	460b      	mov	r3, r1
+ 80264c2:	cb03      	ldmia	r3!, {r0, r1}
+ 80264c4:	6010      	str	r0, [r2, #0]
+ 80264c6:	6051      	str	r1, [r2, #4]
+			blastControl->TxCount = 8;
+ 80264c8:	4b39      	ldr	r3, [pc, #228]	@ (80265b0 <Blast_Machine_Open_Fun+0x140>)
+ 80264ca:	681b      	ldr	r3, [r3, #0]
+ 80264cc:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 80264d0:	2208      	movs	r2, #8
+ 80264d2:	845a      	strh	r2, [r3, #34]	@ 0x22
+			blastControl->UART_Tx(blastControl);
+ 80264d4:	4b36      	ldr	r3, [pc, #216]	@ (80265b0 <Blast_Machine_Open_Fun+0x140>)
+ 80264d6:	681b      	ldr	r3, [r3, #0]
+ 80264d8:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 80264dc:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 80264de:	4a34      	ldr	r2, [pc, #208]	@ (80265b0 <Blast_Machine_Open_Fun+0x140>)
+ 80264e0:	6812      	ldr	r2, [r2, #0]
+ 80264e2:	4610      	mov	r0, r2
+ 80264e4:	4798      	blx	r3
+			break;
+ 80264e6:	e05d      	b.n	80265a4 <Blast_Machine_Open_Fun+0x134>
+			testcounts = 2;
+ 80264e8:	4b30      	ldr	r3, [pc, #192]	@ (80265ac <Blast_Machine_Open_Fun+0x13c>)
+ 80264ea:	2202      	movs	r2, #2
+ 80264ec:	601a      	str	r2, [r3, #0]
+			memcpy(&blastControl->Tx_Buf, &blastMachineOpenCommand, 8);
+ 80264ee:	4b30      	ldr	r3, [pc, #192]	@ (80265b0 <Blast_Machine_Open_Fun+0x140>)
+ 80264f0:	681b      	ldr	r3, [r3, #0]
+ 80264f2:	f603 0321 	addw	r3, r3, #2081	@ 0x821
+ 80264f6:	4930      	ldr	r1, [pc, #192]	@ (80265b8 <Blast_Machine_Open_Fun+0x148>)
+ 80264f8:	461a      	mov	r2, r3
+ 80264fa:	460b      	mov	r3, r1
+ 80264fc:	cb03      	ldmia	r3!, {r0, r1}
+ 80264fe:	6010      	str	r0, [r2, #0]
+ 8026500:	6051      	str	r1, [r2, #4]
+			blastControl->TxCount = 8;
+ 8026502:	4b2b      	ldr	r3, [pc, #172]	@ (80265b0 <Blast_Machine_Open_Fun+0x140>)
+ 8026504:	681b      	ldr	r3, [r3, #0]
+ 8026506:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 802650a:	2208      	movs	r2, #8
+ 802650c:	845a      	strh	r2, [r3, #34]	@ 0x22
+			blastControl->UART_Tx(blastControl);
+ 802650e:	4b28      	ldr	r3, [pc, #160]	@ (80265b0 <Blast_Machine_Open_Fun+0x140>)
+ 8026510:	681b      	ldr	r3, [r3, #0]
+ 8026512:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8026516:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 8026518:	4a25      	ldr	r2, [pc, #148]	@ (80265b0 <Blast_Machine_Open_Fun+0x140>)
+ 802651a:	6812      	ldr	r2, [r2, #0]
+ 802651c:	4610      	mov	r0, r2
+ 802651e:	4798      	blx	r3
+			break;
+ 8026520:	e040      	b.n	80265a4 <Blast_Machine_Open_Fun+0x134>
+			testcounts = 3;
+ 8026522:	4b22      	ldr	r3, [pc, #136]	@ (80265ac <Blast_Machine_Open_Fun+0x13c>)
+ 8026524:	2203      	movs	r2, #3
+ 8026526:	601a      	str	r2, [r3, #0]
+			memcpy(&blastControl->Tx_Buf, &blastMachineRemoteEncoderCommand2, 8);
+ 8026528:	4b21      	ldr	r3, [pc, #132]	@ (80265b0 <Blast_Machine_Open_Fun+0x140>)
+ 802652a:	681b      	ldr	r3, [r3, #0]
+ 802652c:	f603 0321 	addw	r3, r3, #2081	@ 0x821
+ 8026530:	4922      	ldr	r1, [pc, #136]	@ (80265bc <Blast_Machine_Open_Fun+0x14c>)
+ 8026532:	461a      	mov	r2, r3
+ 8026534:	460b      	mov	r3, r1
+ 8026536:	cb03      	ldmia	r3!, {r0, r1}
+ 8026538:	6010      	str	r0, [r2, #0]
+ 802653a:	6051      	str	r1, [r2, #4]
+			blastControl->TxCount = 8;
+ 802653c:	4b1c      	ldr	r3, [pc, #112]	@ (80265b0 <Blast_Machine_Open_Fun+0x140>)
+ 802653e:	681b      	ldr	r3, [r3, #0]
+ 8026540:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8026544:	2208      	movs	r2, #8
+ 8026546:	845a      	strh	r2, [r3, #34]	@ 0x22
+			blastControl->UART_Tx(blastControl);
+ 8026548:	4b19      	ldr	r3, [pc, #100]	@ (80265b0 <Blast_Machine_Open_Fun+0x140>)
+ 802654a:	681b      	ldr	r3, [r3, #0]
+ 802654c:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8026550:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 8026552:	4a17      	ldr	r2, [pc, #92]	@ (80265b0 <Blast_Machine_Open_Fun+0x140>)
+ 8026554:	6812      	ldr	r2, [r2, #0]
+ 8026556:	4610      	mov	r0, r2
+ 8026558:	4798      	blx	r3
+			break;
+ 802655a:	e023      	b.n	80265a4 <Blast_Machine_Open_Fun+0x134>
+			testcounts = 4;
+ 802655c:	4b13      	ldr	r3, [pc, #76]	@ (80265ac <Blast_Machine_Open_Fun+0x13c>)
+ 802655e:	2204      	movs	r2, #4
+ 8026560:	601a      	str	r2, [r3, #0]
+			memcpy(&blastControl->Tx_Buf, &blastMachineOpenCommand, 8);
+ 8026562:	4b13      	ldr	r3, [pc, #76]	@ (80265b0 <Blast_Machine_Open_Fun+0x140>)
+ 8026564:	681b      	ldr	r3, [r3, #0]
+ 8026566:	f603 0321 	addw	r3, r3, #2081	@ 0x821
+ 802656a:	4913      	ldr	r1, [pc, #76]	@ (80265b8 <Blast_Machine_Open_Fun+0x148>)
+ 802656c:	461a      	mov	r2, r3
+ 802656e:	460b      	mov	r3, r1
+ 8026570:	cb03      	ldmia	r3!, {r0, r1}
+ 8026572:	6010      	str	r0, [r2, #0]
+ 8026574:	6051      	str	r1, [r2, #4]
+			blastControl->TxCount = 8;
+ 8026576:	4b0e      	ldr	r3, [pc, #56]	@ (80265b0 <Blast_Machine_Open_Fun+0x140>)
+ 8026578:	681b      	ldr	r3, [r3, #0]
+ 802657a:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 802657e:	2208      	movs	r2, #8
+ 8026580:	845a      	strh	r2, [r3, #34]	@ 0x22
+			blastControl->UART_Tx(blastControl);
+ 8026582:	4b0b      	ldr	r3, [pc, #44]	@ (80265b0 <Blast_Machine_Open_Fun+0x140>)
+ 8026584:	681b      	ldr	r3, [r3, #0]
+ 8026586:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 802658a:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 802658c:	4a08      	ldr	r2, [pc, #32]	@ (80265b0 <Blast_Machine_Open_Fun+0x140>)
+ 802658e:	6812      	ldr	r2, [r2, #0]
+ 8026590:	4610      	mov	r0, r2
+ 8026592:	4798      	blx	r3
+			break;
+ 8026594:	e006      	b.n	80265a4 <Blast_Machine_Open_Fun+0x134>
+			testcounts = 5;
+ 8026596:	4b05      	ldr	r3, [pc, #20]	@ (80265ac <Blast_Machine_Open_Fun+0x13c>)
+ 8026598:	2205      	movs	r2, #5
+ 802659a:	601a      	str	r2, [r3, #0]
+			control_open_commend_counts=0;
+ 802659c:	4b02      	ldr	r3, [pc, #8]	@ (80265a8 <Blast_Machine_Open_Fun+0x138>)
+ 802659e:	2200      	movs	r2, #0
+ 80265a0:	601a      	str	r2, [r3, #0]
+			break;
+ 80265a2:	bf00      	nop
+}
+ 80265a4:	bf00      	nop
+ 80265a6:	bd80      	pop	{r7, pc}
+ 80265a8:	2400a388 	.word	0x2400a388
+ 80265ac:	2400a390 	.word	0x2400a390
+ 80265b0:	2400a36c 	.word	0x2400a36c
+ 80265b4:	2400a378 	.word	0x2400a378
+ 80265b8:	24000038 	.word	0x24000038
+ 80265bc:	2400a380 	.word	0x2400a380
+
+080265c0 <Blast_Machine_Close_Fun>:
+
+void Blast_Machine_Close_Fun()
+{
+ 80265c0:	b580      	push	{r7, lr}
+ 80265c2:	af00      	add	r7, sp, #0
+//	if(blast_flag==1)
+//	{
+	control_close_commend_counts++;
+ 80265c4:	4b4c      	ldr	r3, [pc, #304]	@ (80266f8 <Blast_Machine_Close_Fun+0x138>)
+ 80265c6:	681b      	ldr	r3, [r3, #0]
+ 80265c8:	3301      	adds	r3, #1
+ 80265ca:	4a4b      	ldr	r2, [pc, #300]	@ (80266f8 <Blast_Machine_Close_Fun+0x138>)
+ 80265cc:	6013      	str	r3, [r2, #0]
+		//1. 先发送遥控器编码指令   2.发送关闭指令
+	switch(control_close_commend_counts)
+ 80265ce:	4b4a      	ldr	r3, [pc, #296]	@ (80266f8 <Blast_Machine_Close_Fun+0x138>)
+ 80265d0:	681b      	ldr	r3, [r3, #0]
+ 80265d2:	f5b3 7f96 	cmp.w	r3, #300	@ 0x12c
+ 80265d6:	f000 8086 	beq.w	80266e6 <Blast_Machine_Close_Fun+0x126>
+ 80265da:	f5b3 7f96 	cmp.w	r3, #300	@ 0x12c
+ 80265de:	f200 8089 	bhi.w	80266f4 <Blast_Machine_Close_Fun+0x134>
+ 80265e2:	2bf0      	cmp	r3, #240	@ 0xf0
+ 80265e4:	d062      	beq.n	80266ac <Blast_Machine_Close_Fun+0xec>
+ 80265e6:	2bf0      	cmp	r3, #240	@ 0xf0
+ 80265e8:	f200 8084 	bhi.w	80266f4 <Blast_Machine_Close_Fun+0x134>
+ 80265ec:	2bb4      	cmp	r3, #180	@ 0xb4
+ 80265ee:	d040      	beq.n	8026672 <Blast_Machine_Close_Fun+0xb2>
+ 80265f0:	2bb4      	cmp	r3, #180	@ 0xb4
+ 80265f2:	d87f      	bhi.n	80266f4 <Blast_Machine_Close_Fun+0x134>
+ 80265f4:	2b3c      	cmp	r3, #60	@ 0x3c
+ 80265f6:	d002      	beq.n	80265fe <Blast_Machine_Close_Fun+0x3e>
+ 80265f8:	2b78      	cmp	r3, #120	@ 0x78
+ 80265fa:	d01d      	beq.n	8026638 <Blast_Machine_Close_Fun+0x78>
+//					blast_times=5;
+//				}
+			break;
+	}
+//	}
+}
+ 80265fc:	e07a      	b.n	80266f4 <Blast_Machine_Close_Fun+0x134>
+			testcounts=6;
+ 80265fe:	4b3f      	ldr	r3, [pc, #252]	@ (80266fc <Blast_Machine_Close_Fun+0x13c>)
+ 8026600:	2206      	movs	r2, #6
+ 8026602:	601a      	str	r2, [r3, #0]
+			memcpy(&blastControl->Tx_Buf, &blastMachineRemoteEncoderCommand, 8);
+ 8026604:	4b3e      	ldr	r3, [pc, #248]	@ (8026700 <Blast_Machine_Close_Fun+0x140>)
+ 8026606:	681b      	ldr	r3, [r3, #0]
+ 8026608:	f603 0321 	addw	r3, r3, #2081	@ 0x821
+ 802660c:	493d      	ldr	r1, [pc, #244]	@ (8026704 <Blast_Machine_Close_Fun+0x144>)
+ 802660e:	461a      	mov	r2, r3
+ 8026610:	460b      	mov	r3, r1
+ 8026612:	cb03      	ldmia	r3!, {r0, r1}
+ 8026614:	6010      	str	r0, [r2, #0]
+ 8026616:	6051      	str	r1, [r2, #4]
+			blastControl->TxCount = 8;
+ 8026618:	4b39      	ldr	r3, [pc, #228]	@ (8026700 <Blast_Machine_Close_Fun+0x140>)
+ 802661a:	681b      	ldr	r3, [r3, #0]
+ 802661c:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8026620:	2208      	movs	r2, #8
+ 8026622:	845a      	strh	r2, [r3, #34]	@ 0x22
+			blastControl->UART_Tx(blastControl);
+ 8026624:	4b36      	ldr	r3, [pc, #216]	@ (8026700 <Blast_Machine_Close_Fun+0x140>)
+ 8026626:	681b      	ldr	r3, [r3, #0]
+ 8026628:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 802662c:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 802662e:	4a34      	ldr	r2, [pc, #208]	@ (8026700 <Blast_Machine_Close_Fun+0x140>)
+ 8026630:	6812      	ldr	r2, [r2, #0]
+ 8026632:	4610      	mov	r0, r2
+ 8026634:	4798      	blx	r3
+			break;
+ 8026636:	e05d      	b.n	80266f4 <Blast_Machine_Close_Fun+0x134>
+			testcounts=7;
+ 8026638:	4b30      	ldr	r3, [pc, #192]	@ (80266fc <Blast_Machine_Close_Fun+0x13c>)
+ 802663a:	2207      	movs	r2, #7
+ 802663c:	601a      	str	r2, [r3, #0]
+			memcpy(&blastControl->Tx_Buf, &blastMachineCloseCommand, 8);
+ 802663e:	4b30      	ldr	r3, [pc, #192]	@ (8026700 <Blast_Machine_Close_Fun+0x140>)
+ 8026640:	681b      	ldr	r3, [r3, #0]
+ 8026642:	f603 0321 	addw	r3, r3, #2081	@ 0x821
+ 8026646:	4930      	ldr	r1, [pc, #192]	@ (8026708 <Blast_Machine_Close_Fun+0x148>)
+ 8026648:	461a      	mov	r2, r3
+ 802664a:	460b      	mov	r3, r1
+ 802664c:	cb03      	ldmia	r3!, {r0, r1}
+ 802664e:	6010      	str	r0, [r2, #0]
+ 8026650:	6051      	str	r1, [r2, #4]
+			blastControl->TxCount = 8;
+ 8026652:	4b2b      	ldr	r3, [pc, #172]	@ (8026700 <Blast_Machine_Close_Fun+0x140>)
+ 8026654:	681b      	ldr	r3, [r3, #0]
+ 8026656:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 802665a:	2208      	movs	r2, #8
+ 802665c:	845a      	strh	r2, [r3, #34]	@ 0x22
+			blastControl->UART_Tx(blastControl);
+ 802665e:	4b28      	ldr	r3, [pc, #160]	@ (8026700 <Blast_Machine_Close_Fun+0x140>)
+ 8026660:	681b      	ldr	r3, [r3, #0]
+ 8026662:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8026666:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 8026668:	4a25      	ldr	r2, [pc, #148]	@ (8026700 <Blast_Machine_Close_Fun+0x140>)
+ 802666a:	6812      	ldr	r2, [r2, #0]
+ 802666c:	4610      	mov	r0, r2
+ 802666e:	4798      	blx	r3
+			break;
+ 8026670:	e040      	b.n	80266f4 <Blast_Machine_Close_Fun+0x134>
+			testcounts=8;
+ 8026672:	4b22      	ldr	r3, [pc, #136]	@ (80266fc <Blast_Machine_Close_Fun+0x13c>)
+ 8026674:	2208      	movs	r2, #8
+ 8026676:	601a      	str	r2, [r3, #0]
+			memcpy(&blastControl->Tx_Buf, &blastMachineRemoteEncoderCommand2, 8);
+ 8026678:	4b21      	ldr	r3, [pc, #132]	@ (8026700 <Blast_Machine_Close_Fun+0x140>)
+ 802667a:	681b      	ldr	r3, [r3, #0]
+ 802667c:	f603 0321 	addw	r3, r3, #2081	@ 0x821
+ 8026680:	4922      	ldr	r1, [pc, #136]	@ (802670c <Blast_Machine_Close_Fun+0x14c>)
+ 8026682:	461a      	mov	r2, r3
+ 8026684:	460b      	mov	r3, r1
+ 8026686:	cb03      	ldmia	r3!, {r0, r1}
+ 8026688:	6010      	str	r0, [r2, #0]
+ 802668a:	6051      	str	r1, [r2, #4]
+			blastControl->TxCount = 8;
+ 802668c:	4b1c      	ldr	r3, [pc, #112]	@ (8026700 <Blast_Machine_Close_Fun+0x140>)
+ 802668e:	681b      	ldr	r3, [r3, #0]
+ 8026690:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8026694:	2208      	movs	r2, #8
+ 8026696:	845a      	strh	r2, [r3, #34]	@ 0x22
+			blastControl->UART_Tx(blastControl);
+ 8026698:	4b19      	ldr	r3, [pc, #100]	@ (8026700 <Blast_Machine_Close_Fun+0x140>)
+ 802669a:	681b      	ldr	r3, [r3, #0]
+ 802669c:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 80266a0:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 80266a2:	4a17      	ldr	r2, [pc, #92]	@ (8026700 <Blast_Machine_Close_Fun+0x140>)
+ 80266a4:	6812      	ldr	r2, [r2, #0]
+ 80266a6:	4610      	mov	r0, r2
+ 80266a8:	4798      	blx	r3
+			break;
+ 80266aa:	e023      	b.n	80266f4 <Blast_Machine_Close_Fun+0x134>
+			testcounts=9;
+ 80266ac:	4b13      	ldr	r3, [pc, #76]	@ (80266fc <Blast_Machine_Close_Fun+0x13c>)
+ 80266ae:	2209      	movs	r2, #9
+ 80266b0:	601a      	str	r2, [r3, #0]
+			memcpy(&blastControl->Tx_Buf, &blastMachineCloseCommand, 8);
+ 80266b2:	4b13      	ldr	r3, [pc, #76]	@ (8026700 <Blast_Machine_Close_Fun+0x140>)
+ 80266b4:	681b      	ldr	r3, [r3, #0]
+ 80266b6:	f603 0321 	addw	r3, r3, #2081	@ 0x821
+ 80266ba:	4913      	ldr	r1, [pc, #76]	@ (8026708 <Blast_Machine_Close_Fun+0x148>)
+ 80266bc:	461a      	mov	r2, r3
+ 80266be:	460b      	mov	r3, r1
+ 80266c0:	cb03      	ldmia	r3!, {r0, r1}
+ 80266c2:	6010      	str	r0, [r2, #0]
+ 80266c4:	6051      	str	r1, [r2, #4]
+			blastControl->TxCount = 8;
+ 80266c6:	4b0e      	ldr	r3, [pc, #56]	@ (8026700 <Blast_Machine_Close_Fun+0x140>)
+ 80266c8:	681b      	ldr	r3, [r3, #0]
+ 80266ca:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 80266ce:	2208      	movs	r2, #8
+ 80266d0:	845a      	strh	r2, [r3, #34]	@ 0x22
+			blastControl->UART_Tx(blastControl);
+ 80266d2:	4b0b      	ldr	r3, [pc, #44]	@ (8026700 <Blast_Machine_Close_Fun+0x140>)
+ 80266d4:	681b      	ldr	r3, [r3, #0]
+ 80266d6:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 80266da:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 80266dc:	4a08      	ldr	r2, [pc, #32]	@ (8026700 <Blast_Machine_Close_Fun+0x140>)
+ 80266de:	6812      	ldr	r2, [r2, #0]
+ 80266e0:	4610      	mov	r0, r2
+ 80266e2:	4798      	blx	r3
+			break;
+ 80266e4:	e006      	b.n	80266f4 <Blast_Machine_Close_Fun+0x134>
+			testcounts=10;
+ 80266e6:	4b05      	ldr	r3, [pc, #20]	@ (80266fc <Blast_Machine_Close_Fun+0x13c>)
+ 80266e8:	220a      	movs	r2, #10
+ 80266ea:	601a      	str	r2, [r3, #0]
+			control_close_commend_counts=0;
+ 80266ec:	4b02      	ldr	r3, [pc, #8]	@ (80266f8 <Blast_Machine_Close_Fun+0x138>)
+ 80266ee:	2200      	movs	r2, #0
+ 80266f0:	601a      	str	r2, [r3, #0]
+			break;
+ 80266f2:	bf00      	nop
+}
+ 80266f4:	bf00      	nop
+ 80266f6:	bd80      	pop	{r7, pc}
+ 80266f8:	2400a38c 	.word	0x2400a38c
+ 80266fc:	2400a390 	.word	0x2400a390
+ 8026700:	2400a36c 	.word	0x2400a36c
+ 8026704:	2400a378 	.word	0x2400a378
+ 8026708:	24000040 	.word	0x24000040
+ 802670c:	2400a380 	.word	0x2400a380
+
+08026710 <code_to_str>:
+ * @brief 将uint32_t编码转换为字符串（确保仅含0/1/2）
+ * @param code 输入的uint32_t编码（无符号）
+ * @param str_buf 输出字符串缓冲区（至少CODE_STR_LEN大小）
+ * @return 合法返回true，否则false
+ */
+static bool code_to_str(remote_code_t code, char *str_buf) {
+ 8026710:	b580      	push	{r7, lr}
+ 8026712:	b084      	sub	sp, #16
+ 8026714:	af00      	add	r7, sp, #0
+ 8026716:	6078      	str	r0, [r7, #4]
+ 8026718:	6039      	str	r1, [r7, #0]
+    if (str_buf == NULL) {
+ 802671a:	683b      	ldr	r3, [r7, #0]
+ 802671c:	2b00      	cmp	r3, #0
+ 802671e:	d101      	bne.n	8026724 <code_to_str+0x14>
+        return false;
+ 8026720:	2300      	movs	r3, #0
+ 8026722:	e02f      	b.n	8026784 <code_to_str+0x74>
+    }
+
+    // 转换为无符号整数字符串（使用PRIu32宏确保跨平台兼容性）
+    int ret = snprintf(str_buf, CODE_STR_LEN, "%" PRIu32, code);
+ 8026724:	687b      	ldr	r3, [r7, #4]
+ 8026726:	4a19      	ldr	r2, [pc, #100]	@ (802678c <code_to_str+0x7c>)
+ 8026728:	210b      	movs	r1, #11
+ 802672a:	6838      	ldr	r0, [r7, #0]
+ 802672c:	f019 fd88 	bl	8040240 <sniprintf>
+ 8026730:	60b8      	str	r0, [r7, #8]
+    if (ret < 0 || (size_t)ret >= CODE_STR_LEN) {
+ 8026732:	68bb      	ldr	r3, [r7, #8]
+ 8026734:	2b00      	cmp	r3, #0
+ 8026736:	db02      	blt.n	802673e <code_to_str+0x2e>
+ 8026738:	68bb      	ldr	r3, [r7, #8]
+ 802673a:	2b0a      	cmp	r3, #10
+ 802673c:	d901      	bls.n	8026742 <code_to_str+0x32>
+        return false;  // 转换失败或缓冲区不足
+ 802673e:	2300      	movs	r3, #0
+ 8026740:	e020      	b.n	8026784 <code_to_str+0x74>
+    }
+
+    // 检查字符串是否仅包含0/1/2
+    for (size_t i = 0; str_buf[i] != '\0'; i++) {
+ 8026742:	2300      	movs	r3, #0
+ 8026744:	60fb      	str	r3, [r7, #12]
+ 8026746:	e016      	b.n	8026776 <code_to_str+0x66>
+        if (str_buf[i] != '0' && str_buf[i] != '1' && str_buf[i] != '2') {
+ 8026748:	683a      	ldr	r2, [r7, #0]
+ 802674a:	68fb      	ldr	r3, [r7, #12]
+ 802674c:	4413      	add	r3, r2
+ 802674e:	781b      	ldrb	r3, [r3, #0]
+ 8026750:	2b30      	cmp	r3, #48	@ 0x30
+ 8026752:	d00d      	beq.n	8026770 <code_to_str+0x60>
+ 8026754:	683a      	ldr	r2, [r7, #0]
+ 8026756:	68fb      	ldr	r3, [r7, #12]
+ 8026758:	4413      	add	r3, r2
+ 802675a:	781b      	ldrb	r3, [r3, #0]
+ 802675c:	2b31      	cmp	r3, #49	@ 0x31
+ 802675e:	d007      	beq.n	8026770 <code_to_str+0x60>
+ 8026760:	683a      	ldr	r2, [r7, #0]
+ 8026762:	68fb      	ldr	r3, [r7, #12]
+ 8026764:	4413      	add	r3, r2
+ 8026766:	781b      	ldrb	r3, [r3, #0]
+ 8026768:	2b32      	cmp	r3, #50	@ 0x32
+ 802676a:	d001      	beq.n	8026770 <code_to_str+0x60>
+            return false;
+ 802676c:	2300      	movs	r3, #0
+ 802676e:	e009      	b.n	8026784 <code_to_str+0x74>
+    for (size_t i = 0; str_buf[i] != '\0'; i++) {
+ 8026770:	68fb      	ldr	r3, [r7, #12]
+ 8026772:	3301      	adds	r3, #1
+ 8026774:	60fb      	str	r3, [r7, #12]
+ 8026776:	683a      	ldr	r2, [r7, #0]
+ 8026778:	68fb      	ldr	r3, [r7, #12]
+ 802677a:	4413      	add	r3, r2
+ 802677c:	781b      	ldrb	r3, [r3, #0]
+ 802677e:	2b00      	cmp	r3, #0
+ 8026780:	d1e2      	bne.n	8026748 <code_to_str+0x38>
+        }
+    }
+
+    return true;
+ 8026782:	2301      	movs	r3, #1
+}
+ 8026784:	4618      	mov	r0, r3
+ 8026786:	3710      	adds	r7, #16
+ 8026788:	46bd      	mov	sp, r7
+ 802678a:	bd80      	pop	{r7, pc}
+ 802678c:	08041390 	.word	0x08041390
+
+08026790 <str_to_bin>:
+ * @brief 将原始编码字符串转换为二进制字符串（2→10、0→00、1→01）
+ * @param input 原始编码字符串（必须合法）
+ * @param bin_buf 输出二进制缓冲区（需至少BIN_BUF_LEN大小）
+ * @return 成功返回true，缓冲区溢出返回false
+ */
+static bool str_to_bin(const char *input, char *bin_buf) {
+ 8026790:	b480      	push	{r7}
+ 8026792:	b085      	sub	sp, #20
+ 8026794:	af00      	add	r7, sp, #0
+ 8026796:	6078      	str	r0, [r7, #4]
+ 8026798:	6039      	str	r1, [r7, #0]
+    if (input == NULL || bin_buf == NULL) {
+ 802679a:	687b      	ldr	r3, [r7, #4]
+ 802679c:	2b00      	cmp	r3, #0
+ 802679e:	d002      	beq.n	80267a6 <str_to_bin+0x16>
+ 80267a0:	683b      	ldr	r3, [r7, #0]
+ 80267a2:	2b00      	cmp	r3, #0
+ 80267a4:	d101      	bne.n	80267aa <str_to_bin+0x1a>
+        return false;
+ 80267a6:	2300      	movs	r3, #0
+ 80267a8:	e055      	b.n	8026856 <str_to_bin+0xc6>
+    }
+
+    size_t bin_idx = 0;
+ 80267aa:	2300      	movs	r3, #0
+ 80267ac:	60fb      	str	r3, [r7, #12]
+    for (size_t i = 0; input[i] != '\0'; i++) {
+ 80267ae:	2300      	movs	r3, #0
+ 80267b0:	60bb      	str	r3, [r7, #8]
+ 80267b2:	e044      	b.n	802683e <str_to_bin+0xae>
+        if (bin_idx + 2 >= BIN_BUF_LEN) {
+ 80267b4:	68fb      	ldr	r3, [r7, #12]
+ 80267b6:	3302      	adds	r3, #2
+ 80267b8:	2b27      	cmp	r3, #39	@ 0x27
+ 80267ba:	d901      	bls.n	80267c0 <str_to_bin+0x30>
+            return false;  // 缓冲区溢出
+ 80267bc:	2300      	movs	r3, #0
+ 80267be:	e04a      	b.n	8026856 <str_to_bin+0xc6>
+        }
+
+        switch (input[i]) {
+ 80267c0:	687a      	ldr	r2, [r7, #4]
+ 80267c2:	68bb      	ldr	r3, [r7, #8]
+ 80267c4:	4413      	add	r3, r2
+ 80267c6:	781b      	ldrb	r3, [r3, #0]
+ 80267c8:	2b32      	cmp	r3, #50	@ 0x32
+ 80267ca:	d006      	beq.n	80267da <str_to_bin+0x4a>
+ 80267cc:	2b32      	cmp	r3, #50	@ 0x32
+ 80267ce:	dc31      	bgt.n	8026834 <str_to_bin+0xa4>
+ 80267d0:	2b30      	cmp	r3, #48	@ 0x30
+ 80267d2:	d011      	beq.n	80267f8 <str_to_bin+0x68>
+ 80267d4:	2b31      	cmp	r3, #49	@ 0x31
+ 80267d6:	d01e      	beq.n	8026816 <str_to_bin+0x86>
+ 80267d8:	e02c      	b.n	8026834 <str_to_bin+0xa4>
+            case '2':
+                bin_buf[bin_idx++] = '1';
+ 80267da:	68fb      	ldr	r3, [r7, #12]
+ 80267dc:	1c5a      	adds	r2, r3, #1
+ 80267de:	60fa      	str	r2, [r7, #12]
+ 80267e0:	683a      	ldr	r2, [r7, #0]
+ 80267e2:	4413      	add	r3, r2
+ 80267e4:	2231      	movs	r2, #49	@ 0x31
+ 80267e6:	701a      	strb	r2, [r3, #0]
+                bin_buf[bin_idx++] = '0';
+ 80267e8:	68fb      	ldr	r3, [r7, #12]
+ 80267ea:	1c5a      	adds	r2, r3, #1
+ 80267ec:	60fa      	str	r2, [r7, #12]
+ 80267ee:	683a      	ldr	r2, [r7, #0]
+ 80267f0:	4413      	add	r3, r2
+ 80267f2:	2230      	movs	r2, #48	@ 0x30
+ 80267f4:	701a      	strb	r2, [r3, #0]
+                break;
+ 80267f6:	e01f      	b.n	8026838 <str_to_bin+0xa8>
+            case '0':
+                bin_buf[bin_idx++] = '0';
+ 80267f8:	68fb      	ldr	r3, [r7, #12]
+ 80267fa:	1c5a      	adds	r2, r3, #1
+ 80267fc:	60fa      	str	r2, [r7, #12]
+ 80267fe:	683a      	ldr	r2, [r7, #0]
+ 8026800:	4413      	add	r3, r2
+ 8026802:	2230      	movs	r2, #48	@ 0x30
+ 8026804:	701a      	strb	r2, [r3, #0]
+                bin_buf[bin_idx++] = '0';
+ 8026806:	68fb      	ldr	r3, [r7, #12]
+ 8026808:	1c5a      	adds	r2, r3, #1
+ 802680a:	60fa      	str	r2, [r7, #12]
+ 802680c:	683a      	ldr	r2, [r7, #0]
+ 802680e:	4413      	add	r3, r2
+ 8026810:	2230      	movs	r2, #48	@ 0x30
+ 8026812:	701a      	strb	r2, [r3, #0]
+                break;
+ 8026814:	e010      	b.n	8026838 <str_to_bin+0xa8>
+            case '1':
+                bin_buf[bin_idx++] = '0';
+ 8026816:	68fb      	ldr	r3, [r7, #12]
+ 8026818:	1c5a      	adds	r2, r3, #1
+ 802681a:	60fa      	str	r2, [r7, #12]
+ 802681c:	683a      	ldr	r2, [r7, #0]
+ 802681e:	4413      	add	r3, r2
+ 8026820:	2230      	movs	r2, #48	@ 0x30
+ 8026822:	701a      	strb	r2, [r3, #0]
+                bin_buf[bin_idx++] = '1';
+ 8026824:	68fb      	ldr	r3, [r7, #12]
+ 8026826:	1c5a      	adds	r2, r3, #1
+ 8026828:	60fa      	str	r2, [r7, #12]
+ 802682a:	683a      	ldr	r2, [r7, #0]
+ 802682c:	4413      	add	r3, r2
+ 802682e:	2231      	movs	r2, #49	@ 0x31
+ 8026830:	701a      	strb	r2, [r3, #0]
+                break;
+ 8026832:	e001      	b.n	8026838 <str_to_bin+0xa8>
+            default:
+                return false;  // 应被code_to_str提前过滤
+ 8026834:	2300      	movs	r3, #0
+ 8026836:	e00e      	b.n	8026856 <str_to_bin+0xc6>
+    for (size_t i = 0; input[i] != '\0'; i++) {
+ 8026838:	68bb      	ldr	r3, [r7, #8]
+ 802683a:	3301      	adds	r3, #1
+ 802683c:	60bb      	str	r3, [r7, #8]
+ 802683e:	687a      	ldr	r2, [r7, #4]
+ 8026840:	68bb      	ldr	r3, [r7, #8]
+ 8026842:	4413      	add	r3, r2
+ 8026844:	781b      	ldrb	r3, [r3, #0]
+ 8026846:	2b00      	cmp	r3, #0
+ 8026848:	d1b4      	bne.n	80267b4 <str_to_bin+0x24>
+        }
+    }
+    bin_buf[bin_idx] = '\0';
+ 802684a:	683a      	ldr	r2, [r7, #0]
+ 802684c:	68fb      	ldr	r3, [r7, #12]
+ 802684e:	4413      	add	r3, r2
+ 8026850:	2200      	movs	r2, #0
+ 8026852:	701a      	strb	r2, [r3, #0]
+    return true;
+ 8026854:	2301      	movs	r3, #1
+}
+ 8026856:	4618      	mov	r0, r3
+ 8026858:	3714      	adds	r7, #20
+ 802685a:	46bd      	mov	sp, r7
+ 802685c:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8026860:	4770      	bx	lr
+
+08026862 <bin_to_hex>:
+ * @brief 将二进制字符串转换为16进制字符串
+ * @param bin 二进制字符串
+ * @param hex_buf 输出16进制缓冲区（需至少HEX_BUF_LEN大小）
+ * @return 成功返回true，失败返回false
+ */
+static bool bin_to_hex(const char *bin, char *hex_buf) {
+ 8026862:	b580      	push	{r7, lr}
+ 8026864:	b08e      	sub	sp, #56	@ 0x38
+ 8026866:	af00      	add	r7, sp, #0
+ 8026868:	6078      	str	r0, [r7, #4]
+ 802686a:	6039      	str	r1, [r7, #0]
+    if (bin == NULL || hex_buf == NULL) {
+ 802686c:	687b      	ldr	r3, [r7, #4]
+ 802686e:	2b00      	cmp	r3, #0
+ 8026870:	d002      	beq.n	8026878 <bin_to_hex+0x16>
+ 8026872:	683b      	ldr	r3, [r7, #0]
+ 8026874:	2b00      	cmp	r3, #0
+ 8026876:	d101      	bne.n	802687c <bin_to_hex+0x1a>
+        return false;
+ 8026878:	2300      	movs	r3, #0
+ 802687a:	e0b4      	b.n	80269e6 <bin_to_hex+0x184>
+    }
+
+    const size_t bin_len = strlen(bin);
+ 802687c:	6878      	ldr	r0, [r7, #4]
+ 802687e:	f7f9 fd39 	bl	80202f4 <strlen>
+ 8026882:	61f8      	str	r0, [r7, #28]
+    const uint32_t pad = (HEX_GROUP_LEN - (bin_len % HEX_GROUP_LEN)) % HEX_GROUP_LEN;
+ 8026884:	69fb      	ldr	r3, [r7, #28]
+ 8026886:	425b      	negs	r3, r3
+ 8026888:	f003 0303 	and.w	r3, r3, #3
+ 802688c:	61bb      	str	r3, [r7, #24]
+    size_t hex_idx = 0;
+ 802688e:	2300      	movs	r3, #0
+ 8026890:	637b      	str	r3, [r7, #52]	@ 0x34
+    char temp[HEX_GROUP_LEN + 1] = {0};
+ 8026892:	2300      	movs	r3, #0
+ 8026894:	60fb      	str	r3, [r7, #12]
+ 8026896:	2300      	movs	r3, #0
+ 8026898:	743b      	strb	r3, [r7, #16]
+
+    if (pad > 0) {
+ 802689a:	69bb      	ldr	r3, [r7, #24]
+ 802689c:	2b00      	cmp	r3, #0
+ 802689e:	d03d      	beq.n	802691c <bin_to_hex+0xba>
+        if (hex_idx >= HEX_BUF_LEN) {
+ 80268a0:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
+ 80268a2:	2b13      	cmp	r3, #19
+ 80268a4:	d901      	bls.n	80268aa <bin_to_hex+0x48>
+            return false;
+ 80268a6:	2300      	movs	r3, #0
+ 80268a8:	e09d      	b.n	80269e6 <bin_to_hex+0x184>
+        }
+        memset(temp, '0', pad);
+ 80268aa:	f107 030c 	add.w	r3, r7, #12
+ 80268ae:	69ba      	ldr	r2, [r7, #24]
+ 80268b0:	2130      	movs	r1, #48	@ 0x30
+ 80268b2:	4618      	mov	r0, r3
+ 80268b4:	f019 fd18 	bl	80402e8 <memset>
+        strncpy(temp + pad, bin, HEX_GROUP_LEN - pad);
+ 80268b8:	f107 020c 	add.w	r2, r7, #12
+ 80268bc:	69bb      	ldr	r3, [r7, #24]
+ 80268be:	18d0      	adds	r0, r2, r3
+ 80268c0:	69bb      	ldr	r3, [r7, #24]
+ 80268c2:	f1c3 0304 	rsb	r3, r3, #4
+ 80268c6:	461a      	mov	r2, r3
+ 80268c8:	6879      	ldr	r1, [r7, #4]
+ 80268ca:	f019 fd28 	bl	804031e <strncpy>
+
+        uint32_t val = 0;
+ 80268ce:	2300      	movs	r3, #0
+ 80268d0:	633b      	str	r3, [r7, #48]	@ 0x30
+        for (size_t i = 0; i < HEX_GROUP_LEN; i++) {
+ 80268d2:	2300      	movs	r3, #0
+ 80268d4:	62fb      	str	r3, [r7, #44]	@ 0x2c
+ 80268d6:	e00c      	b.n	80268f2 <bin_to_hex+0x90>
+            val = (val << 1) | (temp[i] - '0');
+ 80268d8:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
+ 80268da:	005b      	lsls	r3, r3, #1
+ 80268dc:	f107 010c 	add.w	r1, r7, #12
+ 80268e0:	6afa      	ldr	r2, [r7, #44]	@ 0x2c
+ 80268e2:	440a      	add	r2, r1
+ 80268e4:	7812      	ldrb	r2, [r2, #0]
+ 80268e6:	3a30      	subs	r2, #48	@ 0x30
+ 80268e8:	4313      	orrs	r3, r2
+ 80268ea:	633b      	str	r3, [r7, #48]	@ 0x30
+        for (size_t i = 0; i < HEX_GROUP_LEN; i++) {
+ 80268ec:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
+ 80268ee:	3301      	adds	r3, #1
+ 80268f0:	62fb      	str	r3, [r7, #44]	@ 0x2c
+ 80268f2:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
+ 80268f4:	2b03      	cmp	r3, #3
+ 80268f6:	d9ef      	bls.n	80268d8 <bin_to_hex+0x76>
+        }
+        hex_buf[hex_idx++] = (val < 10) ? ('0' + val) : ('A' + (val - 10));
+ 80268f8:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
+ 80268fa:	2b09      	cmp	r3, #9
+ 80268fc:	d804      	bhi.n	8026908 <bin_to_hex+0xa6>
+ 80268fe:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
+ 8026900:	b2db      	uxtb	r3, r3
+ 8026902:	3330      	adds	r3, #48	@ 0x30
+ 8026904:	b2da      	uxtb	r2, r3
+ 8026906:	e003      	b.n	8026910 <bin_to_hex+0xae>
+ 8026908:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
+ 802690a:	b2db      	uxtb	r3, r3
+ 802690c:	3337      	adds	r3, #55	@ 0x37
+ 802690e:	b2da      	uxtb	r2, r3
+ 8026910:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
+ 8026912:	1c59      	adds	r1, r3, #1
+ 8026914:	6379      	str	r1, [r7, #52]	@ 0x34
+ 8026916:	6839      	ldr	r1, [r7, #0]
+ 8026918:	440b      	add	r3, r1
+ 802691a:	701a      	strb	r2, [r3, #0]
+    }
+
+    for (size_t i = pad; i < bin_len; i += HEX_GROUP_LEN) {
+ 802691c:	69bb      	ldr	r3, [r7, #24]
+ 802691e:	62bb      	str	r3, [r7, #40]	@ 0x28
+ 8026920:	e057      	b.n	80269d2 <bin_to_hex+0x170>
+        if (hex_idx >= HEX_BUF_LEN) {
+ 8026922:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
+ 8026924:	2b13      	cmp	r3, #19
+ 8026926:	d901      	bls.n	802692c <bin_to_hex+0xca>
+            return false;
+ 8026928:	2300      	movs	r3, #0
+ 802692a:	e05c      	b.n	80269e6 <bin_to_hex+0x184>
+        }
+        const size_t copy_len = (i + HEX_GROUP_LEN <= bin_len) ? HEX_GROUP_LEN : (bin_len - i);
+ 802692c:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 802692e:	3304      	adds	r3, #4
+ 8026930:	69fa      	ldr	r2, [r7, #28]
+ 8026932:	429a      	cmp	r2, r3
+ 8026934:	d203      	bcs.n	802693e <bin_to_hex+0xdc>
+ 8026936:	69fa      	ldr	r2, [r7, #28]
+ 8026938:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 802693a:	1ad3      	subs	r3, r2, r3
+ 802693c:	e000      	b.n	8026940 <bin_to_hex+0xde>
+ 802693e:	2304      	movs	r3, #4
+ 8026940:	617b      	str	r3, [r7, #20]
+        memset(temp, 0, HEX_GROUP_LEN + 1);
+ 8026942:	f107 030c 	add.w	r3, r7, #12
+ 8026946:	2205      	movs	r2, #5
+ 8026948:	2100      	movs	r1, #0
+ 802694a:	4618      	mov	r0, r3
+ 802694c:	f019 fccc 	bl	80402e8 <memset>
+        strncpy(temp, bin + i, copy_len);
+ 8026950:	687a      	ldr	r2, [r7, #4]
+ 8026952:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 8026954:	18d1      	adds	r1, r2, r3
+ 8026956:	f107 030c 	add.w	r3, r7, #12
+ 802695a:	697a      	ldr	r2, [r7, #20]
+ 802695c:	4618      	mov	r0, r3
+ 802695e:	f019 fcde 	bl	804031e <strncpy>
+        if (copy_len < HEX_GROUP_LEN) {
+ 8026962:	697b      	ldr	r3, [r7, #20]
+ 8026964:	2b03      	cmp	r3, #3
+ 8026966:	d80a      	bhi.n	802697e <bin_to_hex+0x11c>
+            memset(temp + copy_len, '0', HEX_GROUP_LEN - copy_len);
+ 8026968:	f107 020c 	add.w	r2, r7, #12
+ 802696c:	697b      	ldr	r3, [r7, #20]
+ 802696e:	18d0      	adds	r0, r2, r3
+ 8026970:	697b      	ldr	r3, [r7, #20]
+ 8026972:	f1c3 0304 	rsb	r3, r3, #4
+ 8026976:	461a      	mov	r2, r3
+ 8026978:	2130      	movs	r1, #48	@ 0x30
+ 802697a:	f019 fcb5 	bl	80402e8 <memset>
+        }
+
+        uint32_t val = 0;
+ 802697e:	2300      	movs	r3, #0
+ 8026980:	627b      	str	r3, [r7, #36]	@ 0x24
+        for (size_t j = 0; j < HEX_GROUP_LEN; j++) {
+ 8026982:	2300      	movs	r3, #0
+ 8026984:	623b      	str	r3, [r7, #32]
+ 8026986:	e00c      	b.n	80269a2 <bin_to_hex+0x140>
+            val = (val << 1) | (temp[j] - '0');
+ 8026988:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 802698a:	005b      	lsls	r3, r3, #1
+ 802698c:	f107 010c 	add.w	r1, r7, #12
+ 8026990:	6a3a      	ldr	r2, [r7, #32]
+ 8026992:	440a      	add	r2, r1
+ 8026994:	7812      	ldrb	r2, [r2, #0]
+ 8026996:	3a30      	subs	r2, #48	@ 0x30
+ 8026998:	4313      	orrs	r3, r2
+ 802699a:	627b      	str	r3, [r7, #36]	@ 0x24
+        for (size_t j = 0; j < HEX_GROUP_LEN; j++) {
+ 802699c:	6a3b      	ldr	r3, [r7, #32]
+ 802699e:	3301      	adds	r3, #1
+ 80269a0:	623b      	str	r3, [r7, #32]
+ 80269a2:	6a3b      	ldr	r3, [r7, #32]
+ 80269a4:	2b03      	cmp	r3, #3
+ 80269a6:	d9ef      	bls.n	8026988 <bin_to_hex+0x126>
+        }
+        hex_buf[hex_idx++] = (val < 10) ? ('0' + val) : ('A' + (val - 10));
+ 80269a8:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 80269aa:	2b09      	cmp	r3, #9
+ 80269ac:	d804      	bhi.n	80269b8 <bin_to_hex+0x156>
+ 80269ae:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 80269b0:	b2db      	uxtb	r3, r3
+ 80269b2:	3330      	adds	r3, #48	@ 0x30
+ 80269b4:	b2da      	uxtb	r2, r3
+ 80269b6:	e003      	b.n	80269c0 <bin_to_hex+0x15e>
+ 80269b8:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 80269ba:	b2db      	uxtb	r3, r3
+ 80269bc:	3337      	adds	r3, #55	@ 0x37
+ 80269be:	b2da      	uxtb	r2, r3
+ 80269c0:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
+ 80269c2:	1c59      	adds	r1, r3, #1
+ 80269c4:	6379      	str	r1, [r7, #52]	@ 0x34
+ 80269c6:	6839      	ldr	r1, [r7, #0]
+ 80269c8:	440b      	add	r3, r1
+ 80269ca:	701a      	strb	r2, [r3, #0]
+    for (size_t i = pad; i < bin_len; i += HEX_GROUP_LEN) {
+ 80269cc:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 80269ce:	3304      	adds	r3, #4
+ 80269d0:	62bb      	str	r3, [r7, #40]	@ 0x28
+ 80269d2:	6aba      	ldr	r2, [r7, #40]	@ 0x28
+ 80269d4:	69fb      	ldr	r3, [r7, #28]
+ 80269d6:	429a      	cmp	r2, r3
+ 80269d8:	d3a3      	bcc.n	8026922 <bin_to_hex+0xc0>
+    }
+    hex_buf[hex_idx] = '\0';
+ 80269da:	683a      	ldr	r2, [r7, #0]
+ 80269dc:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
+ 80269de:	4413      	add	r3, r2
+ 80269e0:	2200      	movs	r2, #0
+ 80269e2:	701a      	strb	r2, [r3, #0]
+    return true;
+ 80269e4:	2301      	movs	r3, #1
+}
+ 80269e6:	4618      	mov	r0, r3
+ 80269e8:	3738      	adds	r7, #56	@ 0x38
+ 80269ea:	46bd      	mov	sp, r7
+ 80269ec:	bd80      	pop	{r7, pc}
+
+080269ee <hex_to_bytes>:
+ * @param hex 16进制字符串（至少4位，不足补前导0）
+ * @param byte1 输出第一个字节（高8位）
+ * @param byte2 输出第二个字节（低8位）
+ * @return 成功返回true，失败返回false
+ */
+static bool hex_to_bytes(const char *hex, uint8_t *byte1, uint8_t *byte2) {
+ 80269ee:	b580      	push	{r7, lr}
+ 80269f0:	b088      	sub	sp, #32
+ 80269f2:	af00      	add	r7, sp, #0
+ 80269f4:	60f8      	str	r0, [r7, #12]
+ 80269f6:	60b9      	str	r1, [r7, #8]
+ 80269f8:	607a      	str	r2, [r7, #4]
+    if (hex == NULL || byte1 == NULL || byte2 == NULL) {
+ 80269fa:	68fb      	ldr	r3, [r7, #12]
+ 80269fc:	2b00      	cmp	r3, #0
+ 80269fe:	d005      	beq.n	8026a0c <hex_to_bytes+0x1e>
+ 8026a00:	68bb      	ldr	r3, [r7, #8]
+ 8026a02:	2b00      	cmp	r3, #0
+ 8026a04:	d002      	beq.n	8026a0c <hex_to_bytes+0x1e>
+ 8026a06:	687b      	ldr	r3, [r7, #4]
+ 8026a08:	2b00      	cmp	r3, #0
+ 8026a0a:	d101      	bne.n	8026a10 <hex_to_bytes+0x22>
+        return false;
+ 8026a0c:	2300      	movs	r3, #0
+ 8026a0e:	e034      	b.n	8026a7a <hex_to_bytes+0x8c>
+    }
+
+    char hex_str[5] = {0};
+ 8026a10:	2300      	movs	r3, #0
+ 8026a12:	613b      	str	r3, [r7, #16]
+ 8026a14:	2300      	movs	r3, #0
+ 8026a16:	753b      	strb	r3, [r7, #20]
+    const size_t hex_len = strlen(hex);
+ 8026a18:	68f8      	ldr	r0, [r7, #12]
+ 8026a1a:	f7f9 fc6b 	bl	80202f4 <strlen>
+ 8026a1e:	61f8      	str	r0, [r7, #28]
+
+    if (hex_len < 4) {
+ 8026a20:	69fb      	ldr	r3, [r7, #28]
+ 8026a22:	2b03      	cmp	r3, #3
+ 8026a24:	d810      	bhi.n	8026a48 <hex_to_bytes+0x5a>
+        memset(hex_str, '0', 4 - hex_len);
+ 8026a26:	69fb      	ldr	r3, [r7, #28]
+ 8026a28:	f1c3 0204 	rsb	r2, r3, #4
+ 8026a2c:	f107 0310 	add.w	r3, r7, #16
+ 8026a30:	2130      	movs	r1, #48	@ 0x30
+ 8026a32:	4618      	mov	r0, r3
+ 8026a34:	f019 fc58 	bl	80402e8 <memset>
+        strncat(hex_str, hex, hex_len);
+ 8026a38:	f107 0310 	add.w	r3, r7, #16
+ 8026a3c:	69fa      	ldr	r2, [r7, #28]
+ 8026a3e:	68f9      	ldr	r1, [r7, #12]
+ 8026a40:	4618      	mov	r0, r3
+ 8026a42:	f019 fc59 	bl	80402f8 <strncat>
+ 8026a46:	e006      	b.n	8026a56 <hex_to_bytes+0x68>
+    } else {
+        strncpy(hex_str, hex, 4);
+ 8026a48:	f107 0310 	add.w	r3, r7, #16
+ 8026a4c:	2204      	movs	r2, #4
+ 8026a4e:	68f9      	ldr	r1, [r7, #12]
+ 8026a50:	4618      	mov	r0, r3
+ 8026a52:	f019 fc64 	bl	804031e <strncpy>
+    }
+
+    const unsigned long val = strtoul(hex_str, NULL, 16);
+ 8026a56:	f107 0310 	add.w	r3, r7, #16
+ 8026a5a:	2210      	movs	r2, #16
+ 8026a5c:	2100      	movs	r1, #0
+ 8026a5e:	4618      	mov	r0, r3
+ 8026a60:	f019 fbe4 	bl	804022c <strtoul>
+ 8026a64:	61b8      	str	r0, [r7, #24]
+    *byte1 = (uint8_t)(val >> 8);
+ 8026a66:	69bb      	ldr	r3, [r7, #24]
+ 8026a68:	0a1b      	lsrs	r3, r3, #8
+ 8026a6a:	b2da      	uxtb	r2, r3
+ 8026a6c:	68bb      	ldr	r3, [r7, #8]
+ 8026a6e:	701a      	strb	r2, [r3, #0]
+    *byte2 = (uint8_t)(val & 0xFF);
+ 8026a70:	69bb      	ldr	r3, [r7, #24]
+ 8026a72:	b2da      	uxtb	r2, r3
+ 8026a74:	687b      	ldr	r3, [r7, #4]
+ 8026a76:	701a      	strb	r2, [r3, #0]
+    return true;
+ 8026a78:	2301      	movs	r3, #1
+}
+ 8026a7a:	4618      	mov	r0, r3
+ 8026a7c:	3720      	adds	r7, #32
+ 8026a7e:	46bd      	mov	sp, r7
+ 8026a80:	bd80      	pop	{r7, pc}
+	...
+
+08026a84 <encode_to_arrays>:
+ * @param array1 第一个目标数组（需提前分配ARRAY_LENGTH大小）
+ * @param array2 第二个目标数组（需提前分配ARRAY_LENGTH大小）
+ * @return 成功返回true，任何步骤失败返回false
+ */
+bool encode_to_arrays(remote_code_t code1, remote_code_t code2,
+                     uint8_t array1[ARRAY_LENGTH], uint8_t array2[ARRAY_LENGTH]) {
+ 8026a84:	b580      	push	{r7, lr}
+ 8026a86:	b0ac      	sub	sp, #176	@ 0xb0
+ 8026a88:	af00      	add	r7, sp, #0
+ 8026a8a:	60f8      	str	r0, [r7, #12]
+ 8026a8c:	60b9      	str	r1, [r7, #8]
+ 8026a8e:	607a      	str	r2, [r7, #4]
+ 8026a90:	603b      	str	r3, [r7, #0]
+    // 检查数组指针合法性
+    if (array1 == NULL || array2 == NULL) {
+ 8026a92:	687b      	ldr	r3, [r7, #4]
+ 8026a94:	2b00      	cmp	r3, #0
+ 8026a96:	d002      	beq.n	8026a9e <encode_to_arrays+0x1a>
+ 8026a98:	683b      	ldr	r3, [r7, #0]
+ 8026a9a:	2b00      	cmp	r3, #0
+ 8026a9c:	d101      	bne.n	8026aa2 <encode_to_arrays+0x1e>
+        return false;
+ 8026a9e:	2300      	movs	r3, #0
+ 8026aa0:	e0fd      	b.n	8026c9e <encode_to_arrays+0x21a>
+    }
+
+    // 初始化数组固定部分
+    memcpy(array1, FIXED_ARRAY, FIXED_PART_LEN);
+ 8026aa2:	687b      	ldr	r3, [r7, #4]
+ 8026aa4:	4a80      	ldr	r2, [pc, #512]	@ (8026ca8 <encode_to_arrays+0x224>)
+ 8026aa6:	6810      	ldr	r0, [r2, #0]
+ 8026aa8:	6018      	str	r0, [r3, #0]
+    memcpy(array2, FIXED_ARRAY, FIXED_PART_LEN);
+ 8026aaa:	683b      	ldr	r3, [r7, #0]
+ 8026aac:	4a7e      	ldr	r2, [pc, #504]	@ (8026ca8 <encode_to_arrays+0x224>)
+ 8026aae:	6810      	ldr	r0, [r2, #0]
+ 8026ab0:	6018      	str	r0, [r3, #0]
+    array1[6] = array1[7] = 0x00;
+ 8026ab2:	687b      	ldr	r3, [r7, #4]
+ 8026ab4:	3307      	adds	r3, #7
+ 8026ab6:	2200      	movs	r2, #0
+ 8026ab8:	701a      	strb	r2, [r3, #0]
+ 8026aba:	687a      	ldr	r2, [r7, #4]
+ 8026abc:	3206      	adds	r2, #6
+ 8026abe:	781b      	ldrb	r3, [r3, #0]
+ 8026ac0:	7013      	strb	r3, [r2, #0]
+    array2[6] = array2[7] = 0x00;
+ 8026ac2:	683b      	ldr	r3, [r7, #0]
+ 8026ac4:	3307      	adds	r3, #7
+ 8026ac6:	2200      	movs	r2, #0
+ 8026ac8:	701a      	strb	r2, [r3, #0]
+ 8026aca:	683a      	ldr	r2, [r7, #0]
+ 8026acc:	3206      	adds	r2, #6
+ 8026ace:	781b      	ldrb	r3, [r3, #0]
+ 8026ad0:	7013      	strb	r3, [r2, #0]
+
+    // 处理第一个编码（uint32_t → 字符串 → 二进制 → 十六进制 → 字节）
+    char code1_str[CODE_STR_LEN] = {0};
+ 8026ad2:	2300      	movs	r3, #0
+ 8026ad4:	f8c7 309c 	str.w	r3, [r7, #156]	@ 0x9c
+ 8026ad8:	f107 03a0 	add.w	r3, r7, #160	@ 0xa0
+ 8026adc:	2200      	movs	r2, #0
+ 8026ade:	601a      	str	r2, [r3, #0]
+ 8026ae0:	f8c3 2003 	str.w	r2, [r3, #3]
+    bool code1_str_ok = code_to_str(code1, code1_str);
+ 8026ae4:	f107 039c 	add.w	r3, r7, #156	@ 0x9c
+ 8026ae8:	4619      	mov	r1, r3
+ 8026aea:	68f8      	ldr	r0, [r7, #12]
+ 8026aec:	f7ff fe10 	bl	8026710 <code_to_str>
+ 8026af0:	4603      	mov	r3, r0
+ 8026af2:	f887 30af 	strb.w	r3, [r7, #175]	@ 0xaf
+
+    char bin1[BIN_BUF_LEN] = {0};
+ 8026af6:	2300      	movs	r3, #0
+ 8026af8:	677b      	str	r3, [r7, #116]	@ 0x74
+ 8026afa:	f107 0378 	add.w	r3, r7, #120	@ 0x78
+ 8026afe:	2224      	movs	r2, #36	@ 0x24
+ 8026b00:	2100      	movs	r1, #0
+ 8026b02:	4618      	mov	r0, r3
+ 8026b04:	f019 fbf0 	bl	80402e8 <memset>
+    bool bin1_ok = code1_str_ok ? str_to_bin(code1_str, bin1) : false;
+ 8026b08:	f897 30af 	ldrb.w	r3, [r7, #175]	@ 0xaf
+ 8026b0c:	2b00      	cmp	r3, #0
+ 8026b0e:	d00c      	beq.n	8026b2a <encode_to_arrays+0xa6>
+ 8026b10:	f107 0274 	add.w	r2, r7, #116	@ 0x74
+ 8026b14:	f107 039c 	add.w	r3, r7, #156	@ 0x9c
+ 8026b18:	4611      	mov	r1, r2
+ 8026b1a:	4618      	mov	r0, r3
+ 8026b1c:	f7ff fe38 	bl	8026790 <str_to_bin>
+ 8026b20:	4603      	mov	r3, r0
+ 8026b22:	2b00      	cmp	r3, #0
+ 8026b24:	d001      	beq.n	8026b2a <encode_to_arrays+0xa6>
+ 8026b26:	2301      	movs	r3, #1
+ 8026b28:	e000      	b.n	8026b2c <encode_to_arrays+0xa8>
+ 8026b2a:	2300      	movs	r3, #0
+ 8026b2c:	f887 30ae 	strb.w	r3, [r7, #174]	@ 0xae
+
+    char hex1[HEX_BUF_LEN] = {0};
+ 8026b30:	2300      	movs	r3, #0
+ 8026b32:	663b      	str	r3, [r7, #96]	@ 0x60
+ 8026b34:	f107 0364 	add.w	r3, r7, #100	@ 0x64
+ 8026b38:	2200      	movs	r2, #0
+ 8026b3a:	601a      	str	r2, [r3, #0]
+ 8026b3c:	605a      	str	r2, [r3, #4]
+ 8026b3e:	609a      	str	r2, [r3, #8]
+ 8026b40:	60da      	str	r2, [r3, #12]
+    bool hex1_ok = bin1_ok ? bin_to_hex(bin1, hex1) : false;
+ 8026b42:	f897 30ae 	ldrb.w	r3, [r7, #174]	@ 0xae
+ 8026b46:	2b00      	cmp	r3, #0
+ 8026b48:	d00c      	beq.n	8026b64 <encode_to_arrays+0xe0>
+ 8026b4a:	f107 0260 	add.w	r2, r7, #96	@ 0x60
+ 8026b4e:	f107 0374 	add.w	r3, r7, #116	@ 0x74
+ 8026b52:	4611      	mov	r1, r2
+ 8026b54:	4618      	mov	r0, r3
+ 8026b56:	f7ff fe84 	bl	8026862 <bin_to_hex>
+ 8026b5a:	4603      	mov	r3, r0
+ 8026b5c:	2b00      	cmp	r3, #0
+ 8026b5e:	d001      	beq.n	8026b64 <encode_to_arrays+0xe0>
+ 8026b60:	2301      	movs	r3, #1
+ 8026b62:	e000      	b.n	8026b66 <encode_to_arrays+0xe2>
+ 8026b64:	2300      	movs	r3, #0
+ 8026b66:	f887 30ad 	strb.w	r3, [r7, #173]	@ 0xad
+
+    uint8_t b1_1, b1_2;
+    bool bytes1_ok = hex1_ok ? hex_to_bytes(hex1, &b1_1, &b1_2) : false;
+ 8026b6a:	f897 30ad 	ldrb.w	r3, [r7, #173]	@ 0xad
+ 8026b6e:	2b00      	cmp	r3, #0
+ 8026b70:	d00d      	beq.n	8026b8e <encode_to_arrays+0x10a>
+ 8026b72:	f107 025e 	add.w	r2, r7, #94	@ 0x5e
+ 8026b76:	f107 015f 	add.w	r1, r7, #95	@ 0x5f
+ 8026b7a:	f107 0360 	add.w	r3, r7, #96	@ 0x60
+ 8026b7e:	4618      	mov	r0, r3
+ 8026b80:	f7ff ff35 	bl	80269ee <hex_to_bytes>
+ 8026b84:	4603      	mov	r3, r0
+ 8026b86:	2b00      	cmp	r3, #0
+ 8026b88:	d001      	beq.n	8026b8e <encode_to_arrays+0x10a>
+ 8026b8a:	2301      	movs	r3, #1
+ 8026b8c:	e000      	b.n	8026b90 <encode_to_arrays+0x10c>
+ 8026b8e:	2300      	movs	r3, #0
+ 8026b90:	f887 30ac 	strb.w	r3, [r7, #172]	@ 0xac
+
+    if (!bytes1_ok) {
+ 8026b94:	f897 30ac 	ldrb.w	r3, [r7, #172]	@ 0xac
+ 8026b98:	f083 0301 	eor.w	r3, r3, #1
+ 8026b9c:	b2db      	uxtb	r3, r3
+ 8026b9e:	2b00      	cmp	r3, #0
+ 8026ba0:	d001      	beq.n	8026ba6 <encode_to_arrays+0x122>
+        return false;
+ 8026ba2:	2300      	movs	r3, #0
+ 8026ba4:	e07b      	b.n	8026c9e <encode_to_arrays+0x21a>
+    }
+    array1[4] = b1_1;
+ 8026ba6:	687b      	ldr	r3, [r7, #4]
+ 8026ba8:	3304      	adds	r3, #4
+ 8026baa:	f897 205f 	ldrb.w	r2, [r7, #95]	@ 0x5f
+ 8026bae:	701a      	strb	r2, [r3, #0]
+    array1[5] = b1_2;
+ 8026bb0:	687b      	ldr	r3, [r7, #4]
+ 8026bb2:	3305      	adds	r3, #5
+ 8026bb4:	f897 205e 	ldrb.w	r2, [r7, #94]	@ 0x5e
+ 8026bb8:	701a      	strb	r2, [r3, #0]
+
+    // 处理第二个编码（同上）
+    char code2_str[CODE_STR_LEN] = {0};
+ 8026bba:	2300      	movs	r3, #0
+ 8026bbc:	653b      	str	r3, [r7, #80]	@ 0x50
+ 8026bbe:	f107 0354 	add.w	r3, r7, #84	@ 0x54
+ 8026bc2:	2200      	movs	r2, #0
+ 8026bc4:	601a      	str	r2, [r3, #0]
+ 8026bc6:	f8c3 2003 	str.w	r2, [r3, #3]
+    bool code2_str_ok = code_to_str(code2, code2_str);
+ 8026bca:	f107 0350 	add.w	r3, r7, #80	@ 0x50
+ 8026bce:	4619      	mov	r1, r3
+ 8026bd0:	68b8      	ldr	r0, [r7, #8]
+ 8026bd2:	f7ff fd9d 	bl	8026710 <code_to_str>
+ 8026bd6:	4603      	mov	r3, r0
+ 8026bd8:	f887 30ab 	strb.w	r3, [r7, #171]	@ 0xab
+
+    char bin2[BIN_BUF_LEN] = {0};
+ 8026bdc:	2300      	movs	r3, #0
+ 8026bde:	62bb      	str	r3, [r7, #40]	@ 0x28
+ 8026be0:	f107 032c 	add.w	r3, r7, #44	@ 0x2c
+ 8026be4:	2224      	movs	r2, #36	@ 0x24
+ 8026be6:	2100      	movs	r1, #0
+ 8026be8:	4618      	mov	r0, r3
+ 8026bea:	f019 fb7d 	bl	80402e8 <memset>
+    bool bin2_ok = code2_str_ok ? str_to_bin(code2_str, bin2) : false;
+ 8026bee:	f897 30ab 	ldrb.w	r3, [r7, #171]	@ 0xab
+ 8026bf2:	2b00      	cmp	r3, #0
+ 8026bf4:	d00c      	beq.n	8026c10 <encode_to_arrays+0x18c>
+ 8026bf6:	f107 0228 	add.w	r2, r7, #40	@ 0x28
+ 8026bfa:	f107 0350 	add.w	r3, r7, #80	@ 0x50
+ 8026bfe:	4611      	mov	r1, r2
+ 8026c00:	4618      	mov	r0, r3
+ 8026c02:	f7ff fdc5 	bl	8026790 <str_to_bin>
+ 8026c06:	4603      	mov	r3, r0
+ 8026c08:	2b00      	cmp	r3, #0
+ 8026c0a:	d001      	beq.n	8026c10 <encode_to_arrays+0x18c>
+ 8026c0c:	2301      	movs	r3, #1
+ 8026c0e:	e000      	b.n	8026c12 <encode_to_arrays+0x18e>
+ 8026c10:	2300      	movs	r3, #0
+ 8026c12:	f887 30aa 	strb.w	r3, [r7, #170]	@ 0xaa
+
+    char hex2[HEX_BUF_LEN] = {0};
+ 8026c16:	2300      	movs	r3, #0
+ 8026c18:	617b      	str	r3, [r7, #20]
+ 8026c1a:	f107 0318 	add.w	r3, r7, #24
+ 8026c1e:	2200      	movs	r2, #0
+ 8026c20:	601a      	str	r2, [r3, #0]
+ 8026c22:	605a      	str	r2, [r3, #4]
+ 8026c24:	609a      	str	r2, [r3, #8]
+ 8026c26:	60da      	str	r2, [r3, #12]
+    bool hex2_ok = bin2_ok ? bin_to_hex(bin2, hex2) : false;
+ 8026c28:	f897 30aa 	ldrb.w	r3, [r7, #170]	@ 0xaa
+ 8026c2c:	2b00      	cmp	r3, #0
+ 8026c2e:	d00c      	beq.n	8026c4a <encode_to_arrays+0x1c6>
+ 8026c30:	f107 0214 	add.w	r2, r7, #20
+ 8026c34:	f107 0328 	add.w	r3, r7, #40	@ 0x28
+ 8026c38:	4611      	mov	r1, r2
+ 8026c3a:	4618      	mov	r0, r3
+ 8026c3c:	f7ff fe11 	bl	8026862 <bin_to_hex>
+ 8026c40:	4603      	mov	r3, r0
+ 8026c42:	2b00      	cmp	r3, #0
+ 8026c44:	d001      	beq.n	8026c4a <encode_to_arrays+0x1c6>
+ 8026c46:	2301      	movs	r3, #1
+ 8026c48:	e000      	b.n	8026c4c <encode_to_arrays+0x1c8>
+ 8026c4a:	2300      	movs	r3, #0
+ 8026c4c:	f887 30a9 	strb.w	r3, [r7, #169]	@ 0xa9
+
+    uint8_t b2_1, b2_2;
+    bool bytes2_ok = hex2_ok ? hex_to_bytes(hex2, &b2_1, &b2_2) : false;
+ 8026c50:	f897 30a9 	ldrb.w	r3, [r7, #169]	@ 0xa9
+ 8026c54:	2b00      	cmp	r3, #0
+ 8026c56:	d00d      	beq.n	8026c74 <encode_to_arrays+0x1f0>
+ 8026c58:	f107 0212 	add.w	r2, r7, #18
+ 8026c5c:	f107 0113 	add.w	r1, r7, #19
+ 8026c60:	f107 0314 	add.w	r3, r7, #20
+ 8026c64:	4618      	mov	r0, r3
+ 8026c66:	f7ff fec2 	bl	80269ee <hex_to_bytes>
+ 8026c6a:	4603      	mov	r3, r0
+ 8026c6c:	2b00      	cmp	r3, #0
+ 8026c6e:	d001      	beq.n	8026c74 <encode_to_arrays+0x1f0>
+ 8026c70:	2301      	movs	r3, #1
+ 8026c72:	e000      	b.n	8026c76 <encode_to_arrays+0x1f2>
+ 8026c74:	2300      	movs	r3, #0
+ 8026c76:	f887 30a8 	strb.w	r3, [r7, #168]	@ 0xa8
+
+    if (!bytes2_ok) {
+ 8026c7a:	f897 30a8 	ldrb.w	r3, [r7, #168]	@ 0xa8
+ 8026c7e:	f083 0301 	eor.w	r3, r3, #1
+ 8026c82:	b2db      	uxtb	r3, r3
+ 8026c84:	2b00      	cmp	r3, #0
+ 8026c86:	d001      	beq.n	8026c8c <encode_to_arrays+0x208>
+        return false;
+ 8026c88:	2300      	movs	r3, #0
+ 8026c8a:	e008      	b.n	8026c9e <encode_to_arrays+0x21a>
+    }
+    array2[4] = b2_1;
+ 8026c8c:	683b      	ldr	r3, [r7, #0]
+ 8026c8e:	3304      	adds	r3, #4
+ 8026c90:	7cfa      	ldrb	r2, [r7, #19]
+ 8026c92:	701a      	strb	r2, [r3, #0]
+    array2[5] = b2_2;
+ 8026c94:	683b      	ldr	r3, [r7, #0]
+ 8026c96:	3305      	adds	r3, #5
+ 8026c98:	7cba      	ldrb	r2, [r7, #18]
+ 8026c9a:	701a      	strb	r2, [r3, #0]
+
+    return true;
+ 8026c9c:	2301      	movs	r3, #1
+}
+ 8026c9e:	4618      	mov	r0, r3
+ 8026ca0:	37b0      	adds	r7, #176	@ 0xb0
+ 8026ca2:	46bd      	mov	sp, r7
+ 8026ca4:	bd80      	pop	{r7, pc}
+ 8026ca6:	bf00      	nop
+ 8026ca8:	08041c20 	.word	0x08041c20
+
+08026cac <CMCU_sensor_intialize>:
+uint8_t crc_checkl = 0;
+
+
+
+void CMCU_sensor_intialize(struct UARTHandler *Handler)
+{
+ 8026cac:	b590      	push	{r4, r7, lr}
+ 8026cae:	b083      	sub	sp, #12
+ 8026cb0:	af00      	add	r7, sp, #0
+ 8026cb2:	6078      	str	r0, [r7, #4]
+	cmcu_sensor = Handler;
+ 8026cb4:	4a26      	ldr	r2, [pc, #152]	@ (8026d50 <CMCU_sensor_intialize+0xa4>)
+ 8026cb6:	687b      	ldr	r3, [r7, #4]
+ 8026cb8:	6013      	str	r3, [r2, #0]
+	cmcu_sensor->UART_Decode=decode_cmcu_sensor;
+ 8026cba:	4b25      	ldr	r3, [pc, #148]	@ (8026d50 <CMCU_sensor_intialize+0xa4>)
+ 8026cbc:	681b      	ldr	r3, [r3, #0]
+ 8026cbe:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8026cc2:	461a      	mov	r2, r3
+ 8026cc4:	4b23      	ldr	r3, [pc, #140]	@ (8026d54 <CMCU_sensor_intialize+0xa8>)
+ 8026cc6:	6313      	str	r3, [r2, #48]	@ 0x30
+	cmcu_sensor->Wait_time = 6; //等待10ms 最低不要低于4；
+ 8026cc8:	4b21      	ldr	r3, [pc, #132]	@ (8026d50 <CMCU_sensor_intialize+0xa4>)
+ 8026cca:	681b      	ldr	r3, [r3, #0]
+ 8026ccc:	2206      	movs	r2, #6
+ 8026cce:	609a      	str	r2, [r3, #8]
+	cmcu_sensor_dispacherController=Handler->dispacherController;
+ 8026cd0:	687b      	ldr	r3, [r7, #4]
+ 8026cd2:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8026cd6:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 8026cd8:	4a1f      	ldr	r2, [pc, #124]	@ (8026d58 <CMCU_sensor_intialize+0xac>)
+ 8026cda:	6013      	str	r3, [r2, #0]
+	cmcu_sensor_dispacherController->Dispacher_Enable=1;
+ 8026cdc:	4b1e      	ldr	r3, [pc, #120]	@ (8026d58 <CMCU_sensor_intialize+0xac>)
+ 8026cde:	681b      	ldr	r3, [r3, #0]
+ 8026ce0:	2201      	movs	r2, #1
+ 8026ce2:	81da      	strh	r2, [r3, #14]
+	//不周期性发送
+	cmcu_sensor_dispacherController->DispacherCallTime = 100;
+ 8026ce4:	4b1c      	ldr	r3, [pc, #112]	@ (8026d58 <CMCU_sensor_intialize+0xac>)
+ 8026ce6:	681b      	ldr	r3, [r3, #0]
+ 8026ce8:	2264      	movs	r2, #100	@ 0x64
+ 8026cea:	815a      	strh	r2, [r3, #10]
+	LOG("cmcu_sensor_intialize");
+ 8026cec:	4b1b      	ldr	r3, [pc, #108]	@ (8026d5c <CMCU_sensor_intialize+0xb0>)
+ 8026cee:	781b      	ldrb	r3, [r3, #0]
+ 8026cf0:	2b03      	cmp	r3, #3
+ 8026cf2:	d918      	bls.n	8026d26 <CMCU_sensor_intialize+0x7a>
+ 8026cf4:	2330      	movs	r3, #48	@ 0x30
+ 8026cf6:	061a      	lsls	r2, r3, #24
+ 8026cf8:	2330      	movs	r3, #48	@ 0x30
+ 8026cfa:	041b      	lsls	r3, r3, #16
+ 8026cfc:	431a      	orrs	r2, r3
+ 8026cfe:	2330      	movs	r3, #48	@ 0x30
+ 8026d00:	021b      	lsls	r3, r3, #8
+ 8026d02:	4313      	orrs	r3, r2
+ 8026d04:	2230      	movs	r2, #48	@ 0x30
+ 8026d06:	ea43 0102 	orr.w	r1, r3, r2
+ 8026d0a:	2344      	movs	r3, #68	@ 0x44
+ 8026d0c:	061a      	lsls	r2, r3, #24
+ 8026d0e:	2346      	movs	r3, #70	@ 0x46
+ 8026d10:	041b      	lsls	r3, r3, #16
+ 8026d12:	431a      	orrs	r2, r3
+ 8026d14:	234c      	movs	r3, #76	@ 0x4c
+ 8026d16:	021b      	lsls	r3, r3, #8
+ 8026d18:	4313      	orrs	r3, r2
+ 8026d1a:	2254      	movs	r2, #84	@ 0x54
+ 8026d1c:	431a      	orrs	r2, r3
+ 8026d1e:	4b10      	ldr	r3, [pc, #64]	@ (8026d60 <CMCU_sensor_intialize+0xb4>)
+ 8026d20:	2004      	movs	r0, #4
+ 8026d22:	f7ff fa87 	bl	8026234 <DLTuc_LogOutVarArgs>
+
+		//log_info("angle_encoder_intialize");
+	cmcu_sensor_dispacherController->Add_Dispatcher_List(cmcu_sensor_dispacherController,GF_CMCU_Inquiry);
+ 8026d26:	4b0c      	ldr	r3, [pc, #48]	@ (8026d58 <CMCU_sensor_intialize+0xac>)
+ 8026d28:	681b      	ldr	r3, [r3, #0]
+ 8026d2a:	691b      	ldr	r3, [r3, #16]
+ 8026d2c:	4a0a      	ldr	r2, [pc, #40]	@ (8026d58 <CMCU_sensor_intialize+0xac>)
+ 8026d2e:	6812      	ldr	r2, [r2, #0]
+ 8026d30:	490c      	ldr	r1, [pc, #48]	@ (8026d64 <CMCU_sensor_intialize+0xb8>)
+ 8026d32:	4610      	mov	r0, r2
+ 8026d34:	4798      	blx	r3
+	HardWareErrorController->Add_PCOMHardWare(HardWareErrorController,"ComError_Force_Sensor",0,ComError_Force_Sensor);
+ 8026d36:	4b0c      	ldr	r3, [pc, #48]	@ (8026d68 <CMCU_sensor_intialize+0xbc>)
+ 8026d38:	681b      	ldr	r3, [r3, #0]
+ 8026d3a:	68dc      	ldr	r4, [r3, #12]
+ 8026d3c:	4b0a      	ldr	r3, [pc, #40]	@ (8026d68 <CMCU_sensor_intialize+0xbc>)
+ 8026d3e:	6818      	ldr	r0, [r3, #0]
+ 8026d40:	2307      	movs	r3, #7
+ 8026d42:	2200      	movs	r2, #0
+ 8026d44:	4909      	ldr	r1, [pc, #36]	@ (8026d6c <CMCU_sensor_intialize+0xc0>)
+ 8026d46:	47a0      	blx	r4
+
+}
+ 8026d48:	bf00      	nop
+ 8026d4a:	370c      	adds	r7, #12
+ 8026d4c:	46bd      	mov	sp, r7
+ 8026d4e:	bd90      	pop	{r4, r7, pc}
+ 8026d50:	2400a394 	.word	0x2400a394
+ 8026d54:	08026db5 	.word	0x08026db5
+ 8026d58:	2400a39c 	.word	0x2400a39c
+ 8026d5c:	24009110 	.word	0x24009110
+ 8026d60:	08041394 	.word	0x08041394
+ 8026d64:	08026d71 	.word	0x08026d71
+ 8026d68:	24000618 	.word	0x24000618
+ 8026d6c:	080413ac 	.word	0x080413ac
+
+08026d70 <GF_CMCU_Inquiry>:
+
+uint8_t Inquiry_Order_CMCU[8]={0X01, 0X03, 0X00, 0X00, 0X00, 0X02, 0XC4, 0X0B};
+void GF_CMCU_Inquiry()
+{
+ 8026d70:	b580      	push	{r7, lr}
+ 8026d72:	af00      	add	r7, sp, #0
+	memcpy(&cmcu_sensor->Tx_Buf, &Inquiry_Order_CMCU, 8);
+ 8026d74:	4b0d      	ldr	r3, [pc, #52]	@ (8026dac <GF_CMCU_Inquiry+0x3c>)
+ 8026d76:	681b      	ldr	r3, [r3, #0]
+ 8026d78:	f603 0321 	addw	r3, r3, #2081	@ 0x821
+ 8026d7c:	490c      	ldr	r1, [pc, #48]	@ (8026db0 <GF_CMCU_Inquiry+0x40>)
+ 8026d7e:	461a      	mov	r2, r3
+ 8026d80:	460b      	mov	r3, r1
+ 8026d82:	cb03      	ldmia	r3!, {r0, r1}
+ 8026d84:	6010      	str	r0, [r2, #0]
+ 8026d86:	6051      	str	r1, [r2, #4]
+	cmcu_sensor->TxCount = 8;
+ 8026d88:	4b08      	ldr	r3, [pc, #32]	@ (8026dac <GF_CMCU_Inquiry+0x3c>)
+ 8026d8a:	681b      	ldr	r3, [r3, #0]
+ 8026d8c:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8026d90:	2208      	movs	r2, #8
+ 8026d92:	845a      	strh	r2, [r3, #34]	@ 0x22
+	cmcu_sensor->UART_Tx(cmcu_sensor);
+ 8026d94:	4b05      	ldr	r3, [pc, #20]	@ (8026dac <GF_CMCU_Inquiry+0x3c>)
+ 8026d96:	681b      	ldr	r3, [r3, #0]
+ 8026d98:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8026d9c:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 8026d9e:	4a03      	ldr	r2, [pc, #12]	@ (8026dac <GF_CMCU_Inquiry+0x3c>)
+ 8026da0:	6812      	ldr	r2, [r2, #0]
+ 8026da2:	4610      	mov	r0, r2
+ 8026da4:	4798      	blx	r3
+}
+ 8026da6:	bf00      	nop
+ 8026da8:	bd80      	pop	{r7, pc}
+ 8026daa:	bf00      	nop
+ 8026dac:	2400a394 	.word	0x2400a394
+ 8026db0:	24000048 	.word	0x24000048
+
+08026db4 <decode_cmcu_sensor>:
+
+void decode_cmcu_sensor(uint8_t *buffer, uint16_t length)
+{
+ 8026db4:	b580      	push	{r7, lr}
+ 8026db6:	b082      	sub	sp, #8
+ 8026db8:	af00      	add	r7, sp, #0
+ 8026dba:	6078      	str	r0, [r7, #4]
+ 8026dbc:	460b      	mov	r3, r1
+ 8026dbe:	807b      	strh	r3, [r7, #2]
+	if(buffer[0] == 0X01 && buffer[1] == 0X03 && buffer[2] == 0X04)
+ 8026dc0:	687b      	ldr	r3, [r7, #4]
+ 8026dc2:	781b      	ldrb	r3, [r3, #0]
+ 8026dc4:	2b01      	cmp	r3, #1
+ 8026dc6:	d14f      	bne.n	8026e68 <decode_cmcu_sensor+0xb4>
+ 8026dc8:	687b      	ldr	r3, [r7, #4]
+ 8026dca:	3301      	adds	r3, #1
+ 8026dcc:	781b      	ldrb	r3, [r3, #0]
+ 8026dce:	2b03      	cmp	r3, #3
+ 8026dd0:	d14a      	bne.n	8026e68 <decode_cmcu_sensor+0xb4>
+ 8026dd2:	687b      	ldr	r3, [r7, #4]
+ 8026dd4:	3302      	adds	r3, #2
+ 8026dd6:	781b      	ldrb	r3, [r3, #0]
+ 8026dd8:	2b04      	cmp	r3, #4
+ 8026dda:	d145      	bne.n	8026e68 <decode_cmcu_sensor+0xb4>
+	{
+		Pressure_value = ((buffer[5] << 24) | (buffer[6] << 16)) | ((buffer[3] << 8) | buffer[4]);
+ 8026ddc:	687b      	ldr	r3, [r7, #4]
+ 8026dde:	3305      	adds	r3, #5
+ 8026de0:	781b      	ldrb	r3, [r3, #0]
+ 8026de2:	061a      	lsls	r2, r3, #24
+ 8026de4:	687b      	ldr	r3, [r7, #4]
+ 8026de6:	3306      	adds	r3, #6
+ 8026de8:	781b      	ldrb	r3, [r3, #0]
+ 8026dea:	041b      	lsls	r3, r3, #16
+ 8026dec:	431a      	orrs	r2, r3
+ 8026dee:	687b      	ldr	r3, [r7, #4]
+ 8026df0:	3303      	adds	r3, #3
+ 8026df2:	781b      	ldrb	r3, [r3, #0]
+ 8026df4:	021b      	lsls	r3, r3, #8
+ 8026df6:	6879      	ldr	r1, [r7, #4]
+ 8026df8:	3104      	adds	r1, #4
+ 8026dfa:	7809      	ldrb	r1, [r1, #0]
+ 8026dfc:	430b      	orrs	r3, r1
+ 8026dfe:	4313      	orrs	r3, r2
+ 8026e00:	4a1b      	ldr	r2, [pc, #108]	@ (8026e70 <decode_cmcu_sensor+0xbc>)
+ 8026e02:	6013      	str	r3, [r2, #0]
+		crc_checkH = buffer[8];
+ 8026e04:	687b      	ldr	r3, [r7, #4]
+ 8026e06:	7a1a      	ldrb	r2, [r3, #8]
+ 8026e08:	4b1a      	ldr	r3, [pc, #104]	@ (8026e74 <decode_cmcu_sensor+0xc0>)
+ 8026e0a:	701a      	strb	r2, [r3, #0]
+		crc_checkL = buffer[7];
+ 8026e0c:	687b      	ldr	r3, [r7, #4]
+ 8026e0e:	79da      	ldrb	r2, [r3, #7]
+ 8026e10:	4b19      	ldr	r3, [pc, #100]	@ (8026e78 <decode_cmcu_sensor+0xc4>)
+ 8026e12:	701a      	strb	r2, [r3, #0]
+		Crc_check = MB_CRC16(buffer,7);
+ 8026e14:	2107      	movs	r1, #7
+ 8026e16:	6878      	ldr	r0, [r7, #4]
+ 8026e18:	f7fa fadc 	bl	80213d4 <MB_CRC16>
+ 8026e1c:	4603      	mov	r3, r0
+ 8026e1e:	461a      	mov	r2, r3
+ 8026e20:	4b16      	ldr	r3, [pc, #88]	@ (8026e7c <decode_cmcu_sensor+0xc8>)
+ 8026e22:	801a      	strh	r2, [r3, #0]
+		crc_checkh = Crc_check >> 8;
+ 8026e24:	4b15      	ldr	r3, [pc, #84]	@ (8026e7c <decode_cmcu_sensor+0xc8>)
+ 8026e26:	881b      	ldrh	r3, [r3, #0]
+ 8026e28:	0a1b      	lsrs	r3, r3, #8
+ 8026e2a:	b29b      	uxth	r3, r3
+ 8026e2c:	b2da      	uxtb	r2, r3
+ 8026e2e:	4b14      	ldr	r3, [pc, #80]	@ (8026e80 <decode_cmcu_sensor+0xcc>)
+ 8026e30:	701a      	strb	r2, [r3, #0]
+		crc_checkl = Crc_check;
+ 8026e32:	4b12      	ldr	r3, [pc, #72]	@ (8026e7c <decode_cmcu_sensor+0xc8>)
+ 8026e34:	881b      	ldrh	r3, [r3, #0]
+ 8026e36:	b2da      	uxtb	r2, r3
+ 8026e38:	4b12      	ldr	r3, [pc, #72]	@ (8026e84 <decode_cmcu_sensor+0xd0>)
+ 8026e3a:	701a      	strb	r2, [r3, #0]
+		if((crc_checkH == crc_checkh) && (crc_checkL == crc_checkl))
+ 8026e3c:	4b0d      	ldr	r3, [pc, #52]	@ (8026e74 <decode_cmcu_sensor+0xc0>)
+ 8026e3e:	781a      	ldrb	r2, [r3, #0]
+ 8026e40:	4b0f      	ldr	r3, [pc, #60]	@ (8026e80 <decode_cmcu_sensor+0xcc>)
+ 8026e42:	781b      	ldrb	r3, [r3, #0]
+ 8026e44:	429a      	cmp	r2, r3
+ 8026e46:	d10f      	bne.n	8026e68 <decode_cmcu_sensor+0xb4>
+ 8026e48:	4b0b      	ldr	r3, [pc, #44]	@ (8026e78 <decode_cmcu_sensor+0xc4>)
+ 8026e4a:	781a      	ldrb	r2, [r3, #0]
+ 8026e4c:	4b0d      	ldr	r3, [pc, #52]	@ (8026e84 <decode_cmcu_sensor+0xd0>)
+ 8026e4e:	781b      	ldrb	r3, [r3, #0]
+ 8026e50:	429a      	cmp	r2, r3
+ 8026e52:	d109      	bne.n	8026e68 <decode_cmcu_sensor+0xb4>
+		{
+			CMCU_Command_Comp();
+ 8026e54:	f000 f81c 	bl	8026e90 <CMCU_Command_Comp>
+			HardWareErrorController->Set_PCOMHardWare(HardWareErrorController,"ComError_Force_Sensor",1);
+ 8026e58:	4b0b      	ldr	r3, [pc, #44]	@ (8026e88 <decode_cmcu_sensor+0xd4>)
+ 8026e5a:	681b      	ldr	r3, [r3, #0]
+ 8026e5c:	695b      	ldr	r3, [r3, #20]
+ 8026e5e:	4a0a      	ldr	r2, [pc, #40]	@ (8026e88 <decode_cmcu_sensor+0xd4>)
+ 8026e60:	6810      	ldr	r0, [r2, #0]
+ 8026e62:	2201      	movs	r2, #1
+ 8026e64:	4909      	ldr	r1, [pc, #36]	@ (8026e8c <decode_cmcu_sensor+0xd8>)
+ 8026e66:	4798      	blx	r3
+		}
+
+	}
+}
+ 8026e68:	bf00      	nop
+ 8026e6a:	3708      	adds	r7, #8
+ 8026e6c:	46bd      	mov	sp, r7
+ 8026e6e:	bd80      	pop	{r7, pc}
+ 8026e70:	2400a3a0 	.word	0x2400a3a0
+ 8026e74:	2400a3a6 	.word	0x2400a3a6
+ 8026e78:	2400a3a7 	.word	0x2400a3a7
+ 8026e7c:	2400a3a4 	.word	0x2400a3a4
+ 8026e80:	2400a3a8 	.word	0x2400a3a8
+ 8026e84:	2400a3a9 	.word	0x2400a3a9
+ 8026e88:	24000618 	.word	0x24000618
+ 8026e8c:	080413ac 	.word	0x080413ac
+
+08026e90 <CMCU_Command_Comp>:
+
+void CMCU_Command_Comp()
+{
+ 8026e90:	b480      	push	{r7}
+ 8026e92:	af00      	add	r7, sp, #0
+	switch(Pressure_value & 0X80000000)
+ 8026e94:	4b0d      	ldr	r3, [pc, #52]	@ (8026ecc <CMCU_Command_Comp+0x3c>)
+ 8026e96:	681b      	ldr	r3, [r3, #0]
+ 8026e98:	f003 4300 	and.w	r3, r3, #2147483648	@ 0x80000000
+ 8026e9c:	2b00      	cmp	r3, #0
+ 8026e9e:	d003      	beq.n	8026ea8 <CMCU_Command_Comp+0x18>
+ 8026ea0:	f1b3 4f00 	cmp.w	r3, #2147483648	@ 0x80000000
+ 8026ea4:	d006      	beq.n	8026eb4 <CMCU_Command_Comp+0x24>
+			break;
+		case 0X80000000:
+			CMCU->CMCU_Measuring_value = Pressure_value - 0XFFFFFFFF - 1;
+			break;
+	}
+}
+ 8026ea6:	e00b      	b.n	8026ec0 <CMCU_Command_Comp+0x30>
+			CMCU->CMCU_Measuring_value = Pressure_value;
+ 8026ea8:	4b09      	ldr	r3, [pc, #36]	@ (8026ed0 <CMCU_Command_Comp+0x40>)
+ 8026eaa:	681b      	ldr	r3, [r3, #0]
+ 8026eac:	4a07      	ldr	r2, [pc, #28]	@ (8026ecc <CMCU_Command_Comp+0x3c>)
+ 8026eae:	6812      	ldr	r2, [r2, #0]
+ 8026eb0:	601a      	str	r2, [r3, #0]
+			break;
+ 8026eb2:	e005      	b.n	8026ec0 <CMCU_Command_Comp+0x30>
+			CMCU->CMCU_Measuring_value = Pressure_value - 0XFFFFFFFF - 1;
+ 8026eb4:	4b06      	ldr	r3, [pc, #24]	@ (8026ed0 <CMCU_Command_Comp+0x40>)
+ 8026eb6:	681b      	ldr	r3, [r3, #0]
+ 8026eb8:	4a04      	ldr	r2, [pc, #16]	@ (8026ecc <CMCU_Command_Comp+0x3c>)
+ 8026eba:	6812      	ldr	r2, [r2, #0]
+ 8026ebc:	601a      	str	r2, [r3, #0]
+			break;
+ 8026ebe:	bf00      	nop
+}
+ 8026ec0:	bf00      	nop
+ 8026ec2:	46bd      	mov	sp, r7
+ 8026ec4:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8026ec8:	4770      	bx	lr
+ 8026eca:	bf00      	nop
+ 8026ecc:	2400a3a0 	.word	0x2400a3a0
+ 8026ed0:	2400a398 	.word	0x2400a398
+
+08026ed4 <GF_MSP_Gyro_MFOG40_Init>:
+void  GF_Gyro_Unscramble_Callback();
+void Gyro_Command_Comp();
+
+
+uint8_t GF_MSP_Gyro_MFOG40_Init(UART_HandleTypeDef* huart,MFOG40_Gyro_struct_define* _gyro_mfog40)
+{
+ 8026ed4:	b590      	push	{r4, r7, lr}
+ 8026ed6:	b083      	sub	sp, #12
+ 8026ed8:	af00      	add	r7, sp, #0
+ 8026eda:	6078      	str	r0, [r7, #4]
+ 8026edc:	6039      	str	r1, [r7, #0]
+	Huart_Gyro_MFOG40 = huart;
+ 8026ede:	4a0f      	ldr	r2, [pc, #60]	@ (8026f1c <GF_MSP_Gyro_MFOG40_Init+0x48>)
+ 8026ee0:	687b      	ldr	r3, [r7, #4]
+ 8026ee2:	6013      	str	r3, [r2, #0]
+	GF_BSP_Interrupt_Add_CallBack(DF_BSP_InterCall_RS485_2_RxCpltCallback, GF_Gyro_Unscramble_Callback);
+ 8026ee4:	490e      	ldr	r1, [pc, #56]	@ (8026f20 <GF_MSP_Gyro_MFOG40_Init+0x4c>)
+ 8026ee6:	2003      	movs	r0, #3
+ 8026ee8:	f7fa fa02 	bl	80212f0 <GF_BSP_Interrupt_Add_CallBack>
+	HAL_UART_Receive_IT(Huart_Gyro_MFOG40,Gyro_stas,1);
+ 8026eec:	4b0b      	ldr	r3, [pc, #44]	@ (8026f1c <GF_MSP_Gyro_MFOG40_Init+0x48>)
+ 8026eee:	681b      	ldr	r3, [r3, #0]
+ 8026ef0:	2201      	movs	r2, #1
+ 8026ef2:	490c      	ldr	r1, [pc, #48]	@ (8026f24 <GF_MSP_Gyro_MFOG40_Init+0x50>)
+ 8026ef4:	4618      	mov	r0, r3
+ 8026ef6:	f016 fb89 	bl	803d60c <HAL_UART_Receive_IT>
+	Gyro_mfog40 = _gyro_mfog40;
+ 8026efa:	4a0b      	ldr	r2, [pc, #44]	@ (8026f28 <GF_MSP_Gyro_MFOG40_Init+0x54>)
+ 8026efc:	683b      	ldr	r3, [r7, #0]
+ 8026efe:	6013      	str	r3, [r2, #0]
+	HardWareErrorController->Add_PCOMHardWare(HardWareErrorController,"Mfog40",0,ComError_Mfog40);
+ 8026f00:	4b0a      	ldr	r3, [pc, #40]	@ (8026f2c <GF_MSP_Gyro_MFOG40_Init+0x58>)
+ 8026f02:	681b      	ldr	r3, [r3, #0]
+ 8026f04:	68dc      	ldr	r4, [r3, #12]
+ 8026f06:	4b09      	ldr	r3, [pc, #36]	@ (8026f2c <GF_MSP_Gyro_MFOG40_Init+0x58>)
+ 8026f08:	6818      	ldr	r0, [r3, #0]
+ 8026f0a:	2308      	movs	r3, #8
+ 8026f0c:	2200      	movs	r2, #0
+ 8026f0e:	4908      	ldr	r1, [pc, #32]	@ (8026f30 <GF_MSP_Gyro_MFOG40_Init+0x5c>)
+ 8026f10:	47a0      	blx	r4
+	return 1;
+ 8026f12:	2301      	movs	r3, #1
+}
+ 8026f14:	4618      	mov	r0, r3
+ 8026f16:	370c      	adds	r7, #12
+ 8026f18:	46bd      	mov	sp, r7
+ 8026f1a:	bd90      	pop	{r4, r7, pc}
+ 8026f1c:	2400a3b4 	.word	0x2400a3b4
+ 8026f20:	08026f35 	.word	0x08026f35
+ 8026f24:	2400a3b8 	.word	0x2400a3b8
+ 8026f28:	2400a3b0 	.word	0x2400a3b0
+ 8026f2c:	24000618 	.word	0x24000618
+ 8026f30:	080413c4 	.word	0x080413c4
+
+08026f34 <GF_Gyro_Unscramble_Callback>:
+
+void  GF_Gyro_Unscramble_Callback()
+{
+ 8026f34:	b580      	push	{r7, lr}
+ 8026f36:	af00      	add	r7, sp, #0
+
+//	HAL_UART_Receive_IT(Huart_Gyro_MFOG40,Gyro_stas1,4);
+	switch(Gyro_Falg)
+ 8026f38:	4b8d      	ldr	r3, [pc, #564]	@ (8027170 <GF_Gyro_Unscramble_Callback+0x23c>)
+ 8026f3a:	781b      	ldrb	r3, [r3, #0]
+ 8026f3c:	3b01      	subs	r3, #1
+ 8026f3e:	2b0d      	cmp	r3, #13
+ 8026f40:	f200 8114 	bhi.w	802716c <GF_Gyro_Unscramble_Callback+0x238>
+ 8026f44:	a201      	add	r2, pc, #4	@ (adr r2, 8026f4c <GF_Gyro_Unscramble_Callback+0x18>)
+ 8026f46:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 8026f4a:	bf00      	nop
+ 8026f4c:	08026f85 	.word	0x08026f85
+ 8026f50:	08026fb9 	.word	0x08026fb9
+ 8026f54:	08026fed 	.word	0x08026fed
+ 8026f58:	08027003 	.word	0x08027003
+ 8026f5c:	08027019 	.word	0x08027019
+ 8026f60:	0802702f 	.word	0x0802702f
+ 8026f64:	08027045 	.word	0x08027045
+ 8026f68:	0802705b 	.word	0x0802705b
+ 8026f6c:	08027071 	.word	0x08027071
+ 8026f70:	08027087 	.word	0x08027087
+ 8026f74:	0802709d 	.word	0x0802709d
+ 8026f78:	080270b3 	.word	0x080270b3
+ 8026f7c:	080270c9 	.word	0x080270c9
+ 8026f80:	080270df 	.word	0x080270df
+	{
+		case 1:
+			if(Gyro_stas[0] == 0x80)
+ 8026f84:	4b7b      	ldr	r3, [pc, #492]	@ (8027174 <GF_Gyro_Unscramble_Callback+0x240>)
+ 8026f86:	781b      	ldrb	r3, [r3, #0]
+ 8026f88:	2b80      	cmp	r3, #128	@ 0x80
+ 8026f8a:	d10a      	bne.n	8026fa2 <GF_Gyro_Unscramble_Callback+0x6e>
+			{
+				HAL_UART_Receive_IT(Huart_Gyro_MFOG40,Gyro_stas,1);
+ 8026f8c:	4b7a      	ldr	r3, [pc, #488]	@ (8027178 <GF_Gyro_Unscramble_Callback+0x244>)
+ 8026f8e:	681b      	ldr	r3, [r3, #0]
+ 8026f90:	2201      	movs	r2, #1
+ 8026f92:	4978      	ldr	r1, [pc, #480]	@ (8027174 <GF_Gyro_Unscramble_Callback+0x240>)
+ 8026f94:	4618      	mov	r0, r3
+ 8026f96:	f016 fb39 	bl	803d60c <HAL_UART_Receive_IT>
+				Gyro_Falg = 2;
+ 8026f9a:	4b75      	ldr	r3, [pc, #468]	@ (8027170 <GF_Gyro_Unscramble_Callback+0x23c>)
+ 8026f9c:	2202      	movs	r2, #2
+ 8026f9e:	701a      	strb	r2, [r3, #0]
+			}
+			else {
+				HAL_UART_Receive_IT(Huart_Gyro_MFOG40,Gyro_stas,1);
+				Gyro_Falg = 1;
+			}
+		break;
+ 8026fa0:	e0e4      	b.n	802716c <GF_Gyro_Unscramble_Callback+0x238>
+				HAL_UART_Receive_IT(Huart_Gyro_MFOG40,Gyro_stas,1);
+ 8026fa2:	4b75      	ldr	r3, [pc, #468]	@ (8027178 <GF_Gyro_Unscramble_Callback+0x244>)
+ 8026fa4:	681b      	ldr	r3, [r3, #0]
+ 8026fa6:	2201      	movs	r2, #1
+ 8026fa8:	4972      	ldr	r1, [pc, #456]	@ (8027174 <GF_Gyro_Unscramble_Callback+0x240>)
+ 8026faa:	4618      	mov	r0, r3
+ 8026fac:	f016 fb2e 	bl	803d60c <HAL_UART_Receive_IT>
+				Gyro_Falg = 1;
+ 8026fb0:	4b6f      	ldr	r3, [pc, #444]	@ (8027170 <GF_Gyro_Unscramble_Callback+0x23c>)
+ 8026fb2:	2201      	movs	r2, #1
+ 8026fb4:	701a      	strb	r2, [r3, #0]
+		break;
+ 8026fb6:	e0d9      	b.n	802716c <GF_Gyro_Unscramble_Callback+0x238>
+		case 2:
+			if(Gyro_stas[0] == 0x80)
+ 8026fb8:	4b6e      	ldr	r3, [pc, #440]	@ (8027174 <GF_Gyro_Unscramble_Callback+0x240>)
+ 8026fba:	781b      	ldrb	r3, [r3, #0]
+ 8026fbc:	2b80      	cmp	r3, #128	@ 0x80
+ 8026fbe:	d10a      	bne.n	8026fd6 <GF_Gyro_Unscramble_Callback+0xa2>
+			{
+				HAL_UART_Receive_IT(Huart_Gyro_MFOG40,Gyro_Vale_AngularVel0,1);
+ 8026fc0:	4b6d      	ldr	r3, [pc, #436]	@ (8027178 <GF_Gyro_Unscramble_Callback+0x244>)
+ 8026fc2:	681b      	ldr	r3, [r3, #0]
+ 8026fc4:	2201      	movs	r2, #1
+ 8026fc6:	496d      	ldr	r1, [pc, #436]	@ (802717c <GF_Gyro_Unscramble_Callback+0x248>)
+ 8026fc8:	4618      	mov	r0, r3
+ 8026fca:	f016 fb1f 	bl	803d60c <HAL_UART_Receive_IT>
+				Gyro_Falg = 3;
+ 8026fce:	4b68      	ldr	r3, [pc, #416]	@ (8027170 <GF_Gyro_Unscramble_Callback+0x23c>)
+ 8026fd0:	2203      	movs	r2, #3
+ 8026fd2:	701a      	strb	r2, [r3, #0]
+			else
+			{
+				HAL_UART_Receive_IT(Huart_Gyro_MFOG40,Gyro_stas,1);
+				Gyro_Falg = 1;
+			}
+		break;
+ 8026fd4:	e0ca      	b.n	802716c <GF_Gyro_Unscramble_Callback+0x238>
+				HAL_UART_Receive_IT(Huart_Gyro_MFOG40,Gyro_stas,1);
+ 8026fd6:	4b68      	ldr	r3, [pc, #416]	@ (8027178 <GF_Gyro_Unscramble_Callback+0x244>)
+ 8026fd8:	681b      	ldr	r3, [r3, #0]
+ 8026fda:	2201      	movs	r2, #1
+ 8026fdc:	4965      	ldr	r1, [pc, #404]	@ (8027174 <GF_Gyro_Unscramble_Callback+0x240>)
+ 8026fde:	4618      	mov	r0, r3
+ 8026fe0:	f016 fb14 	bl	803d60c <HAL_UART_Receive_IT>
+				Gyro_Falg = 1;
+ 8026fe4:	4b62      	ldr	r3, [pc, #392]	@ (8027170 <GF_Gyro_Unscramble_Callback+0x23c>)
+ 8026fe6:	2201      	movs	r2, #1
+ 8026fe8:	701a      	strb	r2, [r3, #0]
+		break;
+ 8026fea:	e0bf      	b.n	802716c <GF_Gyro_Unscramble_Callback+0x238>
+		case 3:
+			HAL_UART_Receive_IT(Huart_Gyro_MFOG40,Gyro_Vale_AngularVel1,1);
+ 8026fec:	4b62      	ldr	r3, [pc, #392]	@ (8027178 <GF_Gyro_Unscramble_Callback+0x244>)
+ 8026fee:	681b      	ldr	r3, [r3, #0]
+ 8026ff0:	2201      	movs	r2, #1
+ 8026ff2:	4963      	ldr	r1, [pc, #396]	@ (8027180 <GF_Gyro_Unscramble_Callback+0x24c>)
+ 8026ff4:	4618      	mov	r0, r3
+ 8026ff6:	f016 fb09 	bl	803d60c <HAL_UART_Receive_IT>
+			Gyro_Falg = 4;
+ 8026ffa:	4b5d      	ldr	r3, [pc, #372]	@ (8027170 <GF_Gyro_Unscramble_Callback+0x23c>)
+ 8026ffc:	2204      	movs	r2, #4
+ 8026ffe:	701a      	strb	r2, [r3, #0]
+			break;
+ 8027000:	e0b4      	b.n	802716c <GF_Gyro_Unscramble_Callback+0x238>
+		case 4:
+			HAL_UART_Receive_IT(Huart_Gyro_MFOG40,Gyro_Vale_AngularVel2,1);
+ 8027002:	4b5d      	ldr	r3, [pc, #372]	@ (8027178 <GF_Gyro_Unscramble_Callback+0x244>)
+ 8027004:	681b      	ldr	r3, [r3, #0]
+ 8027006:	2201      	movs	r2, #1
+ 8027008:	495e      	ldr	r1, [pc, #376]	@ (8027184 <GF_Gyro_Unscramble_Callback+0x250>)
+ 802700a:	4618      	mov	r0, r3
+ 802700c:	f016 fafe 	bl	803d60c <HAL_UART_Receive_IT>
+			Gyro_Falg = 5;
+ 8027010:	4b57      	ldr	r3, [pc, #348]	@ (8027170 <GF_Gyro_Unscramble_Callback+0x23c>)
+ 8027012:	2205      	movs	r2, #5
+ 8027014:	701a      	strb	r2, [r3, #0]
+			break;
+ 8027016:	e0a9      	b.n	802716c <GF_Gyro_Unscramble_Callback+0x238>
+		case 5:
+			HAL_UART_Receive_IT(Huart_Gyro_MFOG40,Gyro_Vale_AngularVel3,1);
+ 8027018:	4b57      	ldr	r3, [pc, #348]	@ (8027178 <GF_Gyro_Unscramble_Callback+0x244>)
+ 802701a:	681b      	ldr	r3, [r3, #0]
+ 802701c:	2201      	movs	r2, #1
+ 802701e:	495a      	ldr	r1, [pc, #360]	@ (8027188 <GF_Gyro_Unscramble_Callback+0x254>)
+ 8027020:	4618      	mov	r0, r3
+ 8027022:	f016 faf3 	bl	803d60c <HAL_UART_Receive_IT>
+			Gyro_Falg = 6;
+ 8027026:	4b52      	ldr	r3, [pc, #328]	@ (8027170 <GF_Gyro_Unscramble_Callback+0x23c>)
+ 8027028:	2206      	movs	r2, #6
+ 802702a:	701a      	strb	r2, [r3, #0]
+			break;
+ 802702c:	e09e      	b.n	802716c <GF_Gyro_Unscramble_Callback+0x238>
+		case 6:
+			HAL_UART_Receive_IT(Huart_Gyro_MFOG40,Gyro_Vale_Angular0,1);
+ 802702e:	4b52      	ldr	r3, [pc, #328]	@ (8027178 <GF_Gyro_Unscramble_Callback+0x244>)
+ 8027030:	681b      	ldr	r3, [r3, #0]
+ 8027032:	2201      	movs	r2, #1
+ 8027034:	4955      	ldr	r1, [pc, #340]	@ (802718c <GF_Gyro_Unscramble_Callback+0x258>)
+ 8027036:	4618      	mov	r0, r3
+ 8027038:	f016 fae8 	bl	803d60c <HAL_UART_Receive_IT>
+			Gyro_Falg = 7;
+ 802703c:	4b4c      	ldr	r3, [pc, #304]	@ (8027170 <GF_Gyro_Unscramble_Callback+0x23c>)
+ 802703e:	2207      	movs	r2, #7
+ 8027040:	701a      	strb	r2, [r3, #0]
+			break;
+ 8027042:	e093      	b.n	802716c <GF_Gyro_Unscramble_Callback+0x238>
+		case 7:
+			HAL_UART_Receive_IT(Huart_Gyro_MFOG40,Gyro_Vale_Angular1,1);
+ 8027044:	4b4c      	ldr	r3, [pc, #304]	@ (8027178 <GF_Gyro_Unscramble_Callback+0x244>)
+ 8027046:	681b      	ldr	r3, [r3, #0]
+ 8027048:	2201      	movs	r2, #1
+ 802704a:	4951      	ldr	r1, [pc, #324]	@ (8027190 <GF_Gyro_Unscramble_Callback+0x25c>)
+ 802704c:	4618      	mov	r0, r3
+ 802704e:	f016 fadd 	bl	803d60c <HAL_UART_Receive_IT>
+			Gyro_Falg = 8;
+ 8027052:	4b47      	ldr	r3, [pc, #284]	@ (8027170 <GF_Gyro_Unscramble_Callback+0x23c>)
+ 8027054:	2208      	movs	r2, #8
+ 8027056:	701a      	strb	r2, [r3, #0]
+			break;
+ 8027058:	e088      	b.n	802716c <GF_Gyro_Unscramble_Callback+0x238>
+		case 8:
+			HAL_UART_Receive_IT(Huart_Gyro_MFOG40,Gyro_Vale_Angular2,1);
+ 802705a:	4b47      	ldr	r3, [pc, #284]	@ (8027178 <GF_Gyro_Unscramble_Callback+0x244>)
+ 802705c:	681b      	ldr	r3, [r3, #0]
+ 802705e:	2201      	movs	r2, #1
+ 8027060:	494c      	ldr	r1, [pc, #304]	@ (8027194 <GF_Gyro_Unscramble_Callback+0x260>)
+ 8027062:	4618      	mov	r0, r3
+ 8027064:	f016 fad2 	bl	803d60c <HAL_UART_Receive_IT>
+			Gyro_Falg = 9;
+ 8027068:	4b41      	ldr	r3, [pc, #260]	@ (8027170 <GF_Gyro_Unscramble_Callback+0x23c>)
+ 802706a:	2209      	movs	r2, #9
+ 802706c:	701a      	strb	r2, [r3, #0]
+			break;
+ 802706e:	e07d      	b.n	802716c <GF_Gyro_Unscramble_Callback+0x238>
+		case 9:
+			HAL_UART_Receive_IT(Huart_Gyro_MFOG40,Gyro_Vale_Angular3,1);
+ 8027070:	4b41      	ldr	r3, [pc, #260]	@ (8027178 <GF_Gyro_Unscramble_Callback+0x244>)
+ 8027072:	681b      	ldr	r3, [r3, #0]
+ 8027074:	2201      	movs	r2, #1
+ 8027076:	4948      	ldr	r1, [pc, #288]	@ (8027198 <GF_Gyro_Unscramble_Callback+0x264>)
+ 8027078:	4618      	mov	r0, r3
+ 802707a:	f016 fac7 	bl	803d60c <HAL_UART_Receive_IT>
+			Gyro_Falg = 10;
+ 802707e:	4b3c      	ldr	r3, [pc, #240]	@ (8027170 <GF_Gyro_Unscramble_Callback+0x23c>)
+ 8027080:	220a      	movs	r2, #10
+ 8027082:	701a      	strb	r2, [r3, #0]
+			break;
+ 8027084:	e072      	b.n	802716c <GF_Gyro_Unscramble_Callback+0x238>
+		case 10:
+			HAL_UART_Receive_IT(Huart_Gyro_MFOG40,Gyro_Vale_Temper0,1);
+ 8027086:	4b3c      	ldr	r3, [pc, #240]	@ (8027178 <GF_Gyro_Unscramble_Callback+0x244>)
+ 8027088:	681b      	ldr	r3, [r3, #0]
+ 802708a:	2201      	movs	r2, #1
+ 802708c:	4943      	ldr	r1, [pc, #268]	@ (802719c <GF_Gyro_Unscramble_Callback+0x268>)
+ 802708e:	4618      	mov	r0, r3
+ 8027090:	f016 fabc 	bl	803d60c <HAL_UART_Receive_IT>
+			Gyro_Falg = 11;
+ 8027094:	4b36      	ldr	r3, [pc, #216]	@ (8027170 <GF_Gyro_Unscramble_Callback+0x23c>)
+ 8027096:	220b      	movs	r2, #11
+ 8027098:	701a      	strb	r2, [r3, #0]
+			break;
+ 802709a:	e067      	b.n	802716c <GF_Gyro_Unscramble_Callback+0x238>
+		case 11:
+			HAL_UART_Receive_IT(Huart_Gyro_MFOG40,Gyro_Vale_Temper1,1);
+ 802709c:	4b36      	ldr	r3, [pc, #216]	@ (8027178 <GF_Gyro_Unscramble_Callback+0x244>)
+ 802709e:	681b      	ldr	r3, [r3, #0]
+ 80270a0:	2201      	movs	r2, #1
+ 80270a2:	493f      	ldr	r1, [pc, #252]	@ (80271a0 <GF_Gyro_Unscramble_Callback+0x26c>)
+ 80270a4:	4618      	mov	r0, r3
+ 80270a6:	f016 fab1 	bl	803d60c <HAL_UART_Receive_IT>
+			Gyro_Falg = 12;
+ 80270aa:	4b31      	ldr	r3, [pc, #196]	@ (8027170 <GF_Gyro_Unscramble_Callback+0x23c>)
+ 80270ac:	220c      	movs	r2, #12
+ 80270ae:	701a      	strb	r2, [r3, #0]
+			break;
+ 80270b0:	e05c      	b.n	802716c <GF_Gyro_Unscramble_Callback+0x238>
+		case 12:
+			HAL_UART_Receive_IT(Huart_Gyro_MFOG40,Gyro_Vale_Check0,1);
+ 80270b2:	4b31      	ldr	r3, [pc, #196]	@ (8027178 <GF_Gyro_Unscramble_Callback+0x244>)
+ 80270b4:	681b      	ldr	r3, [r3, #0]
+ 80270b6:	2201      	movs	r2, #1
+ 80270b8:	493a      	ldr	r1, [pc, #232]	@ (80271a4 <GF_Gyro_Unscramble_Callback+0x270>)
+ 80270ba:	4618      	mov	r0, r3
+ 80270bc:	f016 faa6 	bl	803d60c <HAL_UART_Receive_IT>
+			Gyro_Falg = 13;
+ 80270c0:	4b2b      	ldr	r3, [pc, #172]	@ (8027170 <GF_Gyro_Unscramble_Callback+0x23c>)
+ 80270c2:	220d      	movs	r2, #13
+ 80270c4:	701a      	strb	r2, [r3, #0]
+			break;
+ 80270c6:	e051      	b.n	802716c <GF_Gyro_Unscramble_Callback+0x238>
+		case 13:
+			HAL_UART_Receive_IT(Huart_Gyro_MFOG40,Gyro_Vale_Check1,1);
+ 80270c8:	4b2b      	ldr	r3, [pc, #172]	@ (8027178 <GF_Gyro_Unscramble_Callback+0x244>)
+ 80270ca:	681b      	ldr	r3, [r3, #0]
+ 80270cc:	2201      	movs	r2, #1
+ 80270ce:	4936      	ldr	r1, [pc, #216]	@ (80271a8 <GF_Gyro_Unscramble_Callback+0x274>)
+ 80270d0:	4618      	mov	r0, r3
+ 80270d2:	f016 fa9b 	bl	803d60c <HAL_UART_Receive_IT>
+			Gyro_Falg = 14;
+ 80270d6:	4b26      	ldr	r3, [pc, #152]	@ (8027170 <GF_Gyro_Unscramble_Callback+0x23c>)
+ 80270d8:	220e      	movs	r2, #14
+ 80270da:	701a      	strb	r2, [r3, #0]
+			break;
+ 80270dc:	e046      	b.n	802716c <GF_Gyro_Unscramble_Callback+0x238>
+		case 14:
+			HardWareErrorController->Set_PCOMHardWare(HardWareErrorController,"Mfog40",1);
+ 80270de:	4b33      	ldr	r3, [pc, #204]	@ (80271ac <GF_Gyro_Unscramble_Callback+0x278>)
+ 80270e0:	681b      	ldr	r3, [r3, #0]
+ 80270e2:	695b      	ldr	r3, [r3, #20]
+ 80270e4:	4a31      	ldr	r2, [pc, #196]	@ (80271ac <GF_Gyro_Unscramble_Callback+0x278>)
+ 80270e6:	6810      	ldr	r0, [r2, #0]
+ 80270e8:	2201      	movs	r2, #1
+ 80270ea:	4931      	ldr	r1, [pc, #196]	@ (80271b0 <GF_Gyro_Unscramble_Callback+0x27c>)
+ 80270ec:	4798      	blx	r3
+			Cheak = Gyro_Vale_AngularVel0[0] + Gyro_Vale_AngularVel1[0] + Gyro_Vale_AngularVel2[0] + Gyro_Vale_AngularVel3[0]
+ 80270ee:	4b23      	ldr	r3, [pc, #140]	@ (802717c <GF_Gyro_Unscramble_Callback+0x248>)
+ 80270f0:	781a      	ldrb	r2, [r3, #0]
+ 80270f2:	4b23      	ldr	r3, [pc, #140]	@ (8027180 <GF_Gyro_Unscramble_Callback+0x24c>)
+ 80270f4:	781b      	ldrb	r3, [r3, #0]
+ 80270f6:	4413      	add	r3, r2
+ 80270f8:	b2da      	uxtb	r2, r3
+ 80270fa:	4b22      	ldr	r3, [pc, #136]	@ (8027184 <GF_Gyro_Unscramble_Callback+0x250>)
+ 80270fc:	781b      	ldrb	r3, [r3, #0]
+ 80270fe:	4413      	add	r3, r2
+ 8027100:	b2da      	uxtb	r2, r3
+ 8027102:	4b21      	ldr	r3, [pc, #132]	@ (8027188 <GF_Gyro_Unscramble_Callback+0x254>)
+ 8027104:	781b      	ldrb	r3, [r3, #0]
+ 8027106:	4413      	add	r3, r2
+ 8027108:	b2da      	uxtb	r2, r3
+					+ Gyro_Vale_Angular0[0] + Gyro_Vale_Angular1[0] + Gyro_Vale_Angular2[0] + Gyro_Vale_Angular3[0] + Gyro_Vale_Temper0[0]
+ 802710a:	4b20      	ldr	r3, [pc, #128]	@ (802718c <GF_Gyro_Unscramble_Callback+0x258>)
+ 802710c:	781b      	ldrb	r3, [r3, #0]
+ 802710e:	4413      	add	r3, r2
+ 8027110:	b2da      	uxtb	r2, r3
+ 8027112:	4b1f      	ldr	r3, [pc, #124]	@ (8027190 <GF_Gyro_Unscramble_Callback+0x25c>)
+ 8027114:	781b      	ldrb	r3, [r3, #0]
+ 8027116:	4413      	add	r3, r2
+ 8027118:	b2da      	uxtb	r2, r3
+ 802711a:	4b1e      	ldr	r3, [pc, #120]	@ (8027194 <GF_Gyro_Unscramble_Callback+0x260>)
+ 802711c:	781b      	ldrb	r3, [r3, #0]
+ 802711e:	4413      	add	r3, r2
+ 8027120:	b2da      	uxtb	r2, r3
+ 8027122:	4b1d      	ldr	r3, [pc, #116]	@ (8027198 <GF_Gyro_Unscramble_Callback+0x264>)
+ 8027124:	781b      	ldrb	r3, [r3, #0]
+ 8027126:	4413      	add	r3, r2
+ 8027128:	b2da      	uxtb	r2, r3
+ 802712a:	4b1c      	ldr	r3, [pc, #112]	@ (802719c <GF_Gyro_Unscramble_Callback+0x268>)
+ 802712c:	781b      	ldrb	r3, [r3, #0]
+ 802712e:	4413      	add	r3, r2
+ 8027130:	b2da      	uxtb	r2, r3
+					+ Gyro_Vale_Temper1[0];
+ 8027132:	4b1b      	ldr	r3, [pc, #108]	@ (80271a0 <GF_Gyro_Unscramble_Callback+0x26c>)
+ 8027134:	781b      	ldrb	r3, [r3, #0]
+ 8027136:	4413      	add	r3, r2
+ 8027138:	b2da      	uxtb	r2, r3
+			Cheak = Gyro_Vale_AngularVel0[0] + Gyro_Vale_AngularVel1[0] + Gyro_Vale_AngularVel2[0] + Gyro_Vale_AngularVel3[0]
+ 802713a:	4b1e      	ldr	r3, [pc, #120]	@ (80271b4 <GF_Gyro_Unscramble_Callback+0x280>)
+ 802713c:	701a      	strb	r2, [r3, #0]
+			if(Cheak == Gyro_Vale_Check1[0])
+ 802713e:	4b1a      	ldr	r3, [pc, #104]	@ (80271a8 <GF_Gyro_Unscramble_Callback+0x274>)
+ 8027140:	781a      	ldrb	r2, [r3, #0]
+ 8027142:	4b1c      	ldr	r3, [pc, #112]	@ (80271b4 <GF_Gyro_Unscramble_Callback+0x280>)
+ 8027144:	781b      	ldrb	r3, [r3, #0]
+ 8027146:	429a      	cmp	r2, r3
+ 8027148:	d105      	bne.n	8027156 <GF_Gyro_Unscramble_Callback+0x222>
+			{
+				Gyro_Command_Comp();
+ 802714a:	f000 f835 	bl	80271b8 <Gyro_Command_Comp>
+				Gyro_Falg = 1;
+ 802714e:	4b08      	ldr	r3, [pc, #32]	@ (8027170 <GF_Gyro_Unscramble_Callback+0x23c>)
+ 8027150:	2201      	movs	r2, #1
+ 8027152:	701a      	strb	r2, [r3, #0]
+ 8027154:	e002      	b.n	802715c <GF_Gyro_Unscramble_Callback+0x228>
+			}
+			else
+			{
+				Gyro_Falg = 1;
+ 8027156:	4b06      	ldr	r3, [pc, #24]	@ (8027170 <GF_Gyro_Unscramble_Callback+0x23c>)
+ 8027158:	2201      	movs	r2, #1
+ 802715a:	701a      	strb	r2, [r3, #0]
+			}
+			HAL_UART_Receive_IT(Huart_Gyro_MFOG40,Gyro_stas,1);
+ 802715c:	4b06      	ldr	r3, [pc, #24]	@ (8027178 <GF_Gyro_Unscramble_Callback+0x244>)
+ 802715e:	681b      	ldr	r3, [r3, #0]
+ 8027160:	2201      	movs	r2, #1
+ 8027162:	4904      	ldr	r1, [pc, #16]	@ (8027174 <GF_Gyro_Unscramble_Callback+0x240>)
+ 8027164:	4618      	mov	r0, r3
+ 8027166:	f016 fa51 	bl	803d60c <HAL_UART_Receive_IT>
+			break;
+ 802716a:	bf00      	nop
+	}
+}
+ 802716c:	bf00      	nop
+ 802716e:	bd80      	pop	{r7, pc}
+ 8027170:	24000050 	.word	0x24000050
+ 8027174:	2400a3b8 	.word	0x2400a3b8
+ 8027178:	2400a3b4 	.word	0x2400a3b4
+ 802717c:	2400a3bc 	.word	0x2400a3bc
+ 8027180:	2400a3c0 	.word	0x2400a3c0
+ 8027184:	2400a3c4 	.word	0x2400a3c4
+ 8027188:	2400a3c8 	.word	0x2400a3c8
+ 802718c:	2400a3cc 	.word	0x2400a3cc
+ 8027190:	2400a3d0 	.word	0x2400a3d0
+ 8027194:	2400a3d4 	.word	0x2400a3d4
+ 8027198:	2400a3d8 	.word	0x2400a3d8
+ 802719c:	2400a3dc 	.word	0x2400a3dc
+ 80271a0:	2400a3e0 	.word	0x2400a3e0
+ 80271a4:	2400a3e4 	.word	0x2400a3e4
+ 80271a8:	2400a3e8 	.word	0x2400a3e8
+ 80271ac:	24000618 	.word	0x24000618
+ 80271b0:	080413c4 	.word	0x080413c4
+ 80271b4:	2400a3e9 	.word	0x2400a3e9
+
+080271b8 <Gyro_Command_Comp>:
+
+double Angle_Pi_Pi=0;
+void Gyro_Command_Comp()
+{
+ 80271b8:	b480      	push	{r7}
+ 80271ba:	b085      	sub	sp, #20
+ 80271bc:	af00      	add	r7, sp, #0
+    int result = (Gyro_Vale_Angular0[0] << 21) + (Gyro_Vale_Angular1[0] << 14) + (Gyro_Vale_Angular2[0] << 7) + Gyro_Vale_Angular3[0];
+ 80271be:	4b52      	ldr	r3, [pc, #328]	@ (8027308 <Gyro_Command_Comp+0x150>)
+ 80271c0:	781b      	ldrb	r3, [r3, #0]
+ 80271c2:	055a      	lsls	r2, r3, #21
+ 80271c4:	4b51      	ldr	r3, [pc, #324]	@ (802730c <Gyro_Command_Comp+0x154>)
+ 80271c6:	781b      	ldrb	r3, [r3, #0]
+ 80271c8:	039b      	lsls	r3, r3, #14
+ 80271ca:	441a      	add	r2, r3
+ 80271cc:	4b50      	ldr	r3, [pc, #320]	@ (8027310 <Gyro_Command_Comp+0x158>)
+ 80271ce:	781b      	ldrb	r3, [r3, #0]
+ 80271d0:	01db      	lsls	r3, r3, #7
+ 80271d2:	4413      	add	r3, r2
+ 80271d4:	4a4f      	ldr	r2, [pc, #316]	@ (8027314 <Gyro_Command_Comp+0x15c>)
+ 80271d6:	7812      	ldrb	r2, [r2, #0]
+ 80271d8:	4413      	add	r3, r2
+ 80271da:	60fb      	str	r3, [r7, #12]
+    double_t result_double = 0;
+ 80271dc:	f04f 0200 	mov.w	r2, #0
+ 80271e0:	f04f 0300 	mov.w	r3, #0
+ 80271e4:	e9c7 2300 	strd	r2, r3, [r7]
+
+	switch(result & 0x8000000)
+ 80271e8:	68fb      	ldr	r3, [r7, #12]
+ 80271ea:	f003 6300 	and.w	r3, r3, #134217728	@ 0x8000000
+ 80271ee:	2b00      	cmp	r3, #0
+ 80271f0:	d003      	beq.n	80271fa <Gyro_Command_Comp+0x42>
+ 80271f2:	f1b3 6f00 	cmp.w	r3, #134217728	@ 0x8000000
+ 80271f6:	d012      	beq.n	802721e <Gyro_Command_Comp+0x66>
+ 80271f8:	e027      	b.n	802724a <Gyro_Command_Comp+0x92>
+	    {
+	        case 0:
+	        	result_double = (double)result / 28100;
+ 80271fa:	68fb      	ldr	r3, [r7, #12]
+ 80271fc:	ee07 3a90 	vmov	s15, r3
+ 8027200:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 8027204:	ed9f 5b38 	vldr	d5, [pc, #224]	@ 80272e8 <Gyro_Command_Comp+0x130>
+ 8027208:	ee86 7b05 	vdiv.f64	d7, d6, d5
+ 802720c:	ed87 7b00 	vstr	d7, [r7]
+	        	Gyro_mfog40->gyro_angular = result_double;
+ 8027210:	4b41      	ldr	r3, [pc, #260]	@ (8027318 <Gyro_Command_Comp+0x160>)
+ 8027212:	6819      	ldr	r1, [r3, #0]
+ 8027214:	e9d7 2300 	ldrd	r2, r3, [r7]
+ 8027218:	e9c1 2302 	strd	r2, r3, [r1, #8]
+	        break;
+ 802721c:	e015      	b.n	802724a <Gyro_Command_Comp+0x92>
+	        case 0x8000000:
+	        	result = result - 0xFFFFFFF - 1;
+ 802721e:	68fb      	ldr	r3, [r7, #12]
+ 8027220:	f103 4370 	add.w	r3, r3, #4026531840	@ 0xf0000000
+ 8027224:	60fb      	str	r3, [r7, #12]
+	            result_double = (double)result / 28100;
+ 8027226:	68fb      	ldr	r3, [r7, #12]
+ 8027228:	ee07 3a90 	vmov	s15, r3
+ 802722c:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 8027230:	ed9f 5b2d 	vldr	d5, [pc, #180]	@ 80272e8 <Gyro_Command_Comp+0x130>
+ 8027234:	ee86 7b05 	vdiv.f64	d7, d6, d5
+ 8027238:	ed87 7b00 	vstr	d7, [r7]
+	            Gyro_mfog40->gyro_angular = result_double;
+ 802723c:	4b36      	ldr	r3, [pc, #216]	@ (8027318 <Gyro_Command_Comp+0x160>)
+ 802723e:	6819      	ldr	r1, [r3, #0]
+ 8027240:	e9d7 2300 	ldrd	r2, r3, [r7]
+ 8027244:	e9c1 2302 	strd	r2, r3, [r1, #8]
+	        break;
+ 8027248:	bf00      	nop
+	    }
+	Angle_Pi_Pi=Gyro_mfog40->gyro_angular- 360.0 * ((int)(Gyro_mfog40->gyro_angular/360.0));
+ 802724a:	4b33      	ldr	r3, [pc, #204]	@ (8027318 <Gyro_Command_Comp+0x160>)
+ 802724c:	681b      	ldr	r3, [r3, #0]
+ 802724e:	ed93 6b02 	vldr	d6, [r3, #8]
+ 8027252:	4b31      	ldr	r3, [pc, #196]	@ (8027318 <Gyro_Command_Comp+0x160>)
+ 8027254:	681b      	ldr	r3, [r3, #0]
+ 8027256:	ed93 5b02 	vldr	d5, [r3, #8]
+ 802725a:	ed9f 4b25 	vldr	d4, [pc, #148]	@ 80272f0 <Gyro_Command_Comp+0x138>
+ 802725e:	ee85 7b04 	vdiv.f64	d7, d5, d4
+ 8027262:	eefd 7bc7 	vcvt.s32.f64	s15, d7
+ 8027266:	eeb8 7be7 	vcvt.f64.s32	d7, s15
+ 802726a:	ed9f 5b21 	vldr	d5, [pc, #132]	@ 80272f0 <Gyro_Command_Comp+0x138>
+ 802726e:	ee27 7b05 	vmul.f64	d7, d7, d5
+ 8027272:	ee36 7b47 	vsub.f64	d7, d6, d7
+ 8027276:	4b29      	ldr	r3, [pc, #164]	@ (802731c <Gyro_Command_Comp+0x164>)
+ 8027278:	ed83 7b00 	vstr	d7, [r3]
+//	Gyro_mfog40->gyro_angular=Gyro_mfog40->gyro_angular- 360.0 * ((int)(Gyro_mfog40->gyro_angular/360.0));
+//	Angle_Pi_Pi=Gyro_mfog40->gyro_angular;
+	if(Angle_Pi_Pi>180)
+ 802727c:	4b27      	ldr	r3, [pc, #156]	@ (802731c <Gyro_Command_Comp+0x164>)
+ 802727e:	ed93 7b00 	vldr	d7, [r3]
+ 8027282:	ed9f 6b1d 	vldr	d6, [pc, #116]	@ 80272f8 <Gyro_Command_Comp+0x140>
+ 8027286:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 802728a:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802728e:	dd0a      	ble.n	80272a6 <Gyro_Command_Comp+0xee>
+	{
+		Angle_Pi_Pi=Angle_Pi_Pi-360;
+ 8027290:	4b22      	ldr	r3, [pc, #136]	@ (802731c <Gyro_Command_Comp+0x164>)
+ 8027292:	ed93 7b00 	vldr	d7, [r3]
+ 8027296:	ed9f 6b16 	vldr	d6, [pc, #88]	@ 80272f0 <Gyro_Command_Comp+0x138>
+ 802729a:	ee37 7b46 	vsub.f64	d7, d7, d6
+ 802729e:	4b1f      	ldr	r3, [pc, #124]	@ (802731c <Gyro_Command_Comp+0x164>)
+ 80272a0:	ed83 7b00 	vstr	d7, [r3]
+ 80272a4:	e013      	b.n	80272ce <Gyro_Command_Comp+0x116>
+	}
+	else if(Angle_Pi_Pi<-180)
+ 80272a6:	4b1d      	ldr	r3, [pc, #116]	@ (802731c <Gyro_Command_Comp+0x164>)
+ 80272a8:	ed93 7b00 	vldr	d7, [r3]
+ 80272ac:	ed9f 6b14 	vldr	d6, [pc, #80]	@ 8027300 <Gyro_Command_Comp+0x148>
+ 80272b0:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 80272b4:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 80272b8:	d509      	bpl.n	80272ce <Gyro_Command_Comp+0x116>
+	{
+		Angle_Pi_Pi=Angle_Pi_Pi+360;
+ 80272ba:	4b18      	ldr	r3, [pc, #96]	@ (802731c <Gyro_Command_Comp+0x164>)
+ 80272bc:	ed93 7b00 	vldr	d7, [r3]
+ 80272c0:	ed9f 6b0b 	vldr	d6, [pc, #44]	@ 80272f0 <Gyro_Command_Comp+0x138>
+ 80272c4:	ee37 7b06 	vadd.f64	d7, d7, d6
+ 80272c8:	4b14      	ldr	r3, [pc, #80]	@ (802731c <Gyro_Command_Comp+0x164>)
+ 80272ca:	ed83 7b00 	vstr	d7, [r3]
+	}
+	Gyro_mfog40->gyro_angular=Angle_Pi_Pi;
+ 80272ce:	4b12      	ldr	r3, [pc, #72]	@ (8027318 <Gyro_Command_Comp+0x160>)
+ 80272d0:	6819      	ldr	r1, [r3, #0]
+ 80272d2:	4b12      	ldr	r3, [pc, #72]	@ (802731c <Gyro_Command_Comp+0x164>)
+ 80272d4:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 80272d8:	e9c1 2302 	strd	r2, r3, [r1, #8]
+}
+ 80272dc:	bf00      	nop
+ 80272de:	3714      	adds	r7, #20
+ 80272e0:	46bd      	mov	sp, r7
+ 80272e2:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80272e6:	4770      	bx	lr
+ 80272e8:	00000000 	.word	0x00000000
+ 80272ec:	40db7100 	.word	0x40db7100
+ 80272f0:	00000000 	.word	0x00000000
+ 80272f4:	40768000 	.word	0x40768000
+ 80272f8:	00000000 	.word	0x00000000
+ 80272fc:	40668000 	.word	0x40668000
+ 8027300:	00000000 	.word	0x00000000
+ 8027304:	c0668000 	.word	0xc0668000
+ 8027308:	2400a3cc 	.word	0x2400a3cc
+ 802730c:	2400a3d0 	.word	0x2400a3d0
+ 8027310:	2400a3d4 	.word	0x2400a3d4
+ 8027314:	2400a3d8 	.word	0x2400a3d8
+ 8027318:	2400a3b0 	.word	0x2400a3b0
+ 802731c:	2400a3f0 	.word	0x2400a3f0
+
+08027320 <decode_MK32Data>:
+
+
+
+struct UARTHandler *MK32_Sbus_Controller;
+void decode_MK32Data(uint8_t *buffer, uint16_t length)
+{
+ 8027320:	b580      	push	{r7, lr}
+ 8027322:	b082      	sub	sp, #8
+ 8027324:	af00      	add	r7, sp, #0
+ 8027326:	6078      	str	r0, [r7, #4]
+ 8027328:	460b      	mov	r3, r1
+ 802732a:	807b      	strh	r3, [r7, #2]
+	if(length!=25)
+ 802732c:	887b      	ldrh	r3, [r7, #2]
+ 802732e:	2b19      	cmp	r3, #25
+ 8027330:	d119      	bne.n	8027366 <decode_MK32Data+0x46>
+	{
+		return;
+	}
+	if(buffer[0]==0X0f&&buffer[24]==0X00)
+ 8027332:	687b      	ldr	r3, [r7, #4]
+ 8027334:	781b      	ldrb	r3, [r3, #0]
+ 8027336:	2b0f      	cmp	r3, #15
+ 8027338:	d10c      	bne.n	8027354 <decode_MK32Data+0x34>
+ 802733a:	687b      	ldr	r3, [r7, #4]
+ 802733c:	3318      	adds	r3, #24
+ 802733e:	781b      	ldrb	r3, [r3, #0]
+ 8027340:	2b00      	cmp	r3, #0
+ 8027342:	d107      	bne.n	8027354 <decode_MK32Data+0x34>
+	{
+		Sbus_Data_Count(&buffer[1], (int32_t*) (P_MK32));
+ 8027344:	687b      	ldr	r3, [r7, #4]
+ 8027346:	3301      	adds	r3, #1
+ 8027348:	4a09      	ldr	r2, [pc, #36]	@ (8027370 <decode_MK32Data+0x50>)
+ 802734a:	6812      	ldr	r2, [r2, #0]
+ 802734c:	4611      	mov	r1, r2
+ 802734e:	4618      	mov	r0, r3
+ 8027350:	f000 f816 	bl	8027380 <Sbus_Data_Count>
+	}
+
+	HardWareErrorController->Set_PCOMHardWare(HardWareErrorController,"mk32_sbus",1);
+ 8027354:	4b07      	ldr	r3, [pc, #28]	@ (8027374 <decode_MK32Data+0x54>)
+ 8027356:	681b      	ldr	r3, [r3, #0]
+ 8027358:	695b      	ldr	r3, [r3, #20]
+ 802735a:	4a06      	ldr	r2, [pc, #24]	@ (8027374 <decode_MK32Data+0x54>)
+ 802735c:	6810      	ldr	r0, [r2, #0]
+ 802735e:	2201      	movs	r2, #1
+ 8027360:	4905      	ldr	r1, [pc, #20]	@ (8027378 <decode_MK32Data+0x58>)
+ 8027362:	4798      	blx	r3
+ 8027364:	e000      	b.n	8027368 <decode_MK32Data+0x48>
+		return;
+ 8027366:	bf00      	nop
+
+}
+ 8027368:	3708      	adds	r7, #8
+ 802736a:	46bd      	mov	sp, r7
+ 802736c:	bd80      	pop	{r7, pc}
+ 802736e:	bf00      	nop
+ 8027370:	2400a3f8 	.word	0x2400a3f8
+ 8027374:	24000618 	.word	0x24000618
+ 8027378:	080413cc 	.word	0x080413cc
+ 802737c:	00000000 	.word	0x00000000
+
+08027380 <Sbus_Data_Count>:
+
+void Sbus_Data_Count(uint8_t *buf, int32_t *But_Value)
+{
+ 8027380:	b480      	push	{r7}
+ 8027382:	b08d      	sub	sp, #52	@ 0x34
+ 8027384:	af00      	add	r7, sp, #0
+ 8027386:	6078      	str	r0, [r7, #4]
+ 8027388:	6039      	str	r1, [r7, #0]
+
+	int16_t CH[16];
+	int Start_byte = -1;
+ 802738a:	f04f 33ff 	mov.w	r3, #4294967295
+ 802738e:	62bb      	str	r3, [r7, #40]	@ 0x28
+
+	CH[0] = ((buf[Start_byte + 1] | buf[Start_byte + 2] << 8) & 0x07FF);
+ 8027390:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 8027392:	3301      	adds	r3, #1
+ 8027394:	687a      	ldr	r2, [r7, #4]
+ 8027396:	4413      	add	r3, r2
+ 8027398:	781b      	ldrb	r3, [r3, #0]
+ 802739a:	b21a      	sxth	r2, r3
+ 802739c:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 802739e:	3302      	adds	r3, #2
+ 80273a0:	6879      	ldr	r1, [r7, #4]
+ 80273a2:	440b      	add	r3, r1
+ 80273a4:	781b      	ldrb	r3, [r3, #0]
+ 80273a6:	021b      	lsls	r3, r3, #8
+ 80273a8:	b21b      	sxth	r3, r3
+ 80273aa:	4313      	orrs	r3, r2
+ 80273ac:	b21b      	sxth	r3, r3
+ 80273ae:	f3c3 030a 	ubfx	r3, r3, #0, #11
+ 80273b2:	b21b      	sxth	r3, r3
+ 80273b4:	813b      	strh	r3, [r7, #8]
+	CH[1] = ((buf[Start_byte + 2] >> 3 | buf[Start_byte + 3] << 5) & 0x07FF);
+ 80273b6:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 80273b8:	3302      	adds	r3, #2
+ 80273ba:	687a      	ldr	r2, [r7, #4]
+ 80273bc:	4413      	add	r3, r2
+ 80273be:	781b      	ldrb	r3, [r3, #0]
+ 80273c0:	08db      	lsrs	r3, r3, #3
+ 80273c2:	b2db      	uxtb	r3, r3
+ 80273c4:	b21a      	sxth	r2, r3
+ 80273c6:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 80273c8:	3303      	adds	r3, #3
+ 80273ca:	6879      	ldr	r1, [r7, #4]
+ 80273cc:	440b      	add	r3, r1
+ 80273ce:	781b      	ldrb	r3, [r3, #0]
+ 80273d0:	015b      	lsls	r3, r3, #5
+ 80273d2:	b21b      	sxth	r3, r3
+ 80273d4:	4313      	orrs	r3, r2
+ 80273d6:	b21b      	sxth	r3, r3
+ 80273d8:	f3c3 030a 	ubfx	r3, r3, #0, #11
+ 80273dc:	b21b      	sxth	r3, r3
+ 80273de:	817b      	strh	r3, [r7, #10]
+	CH[2] = ((buf[Start_byte + 3] >> 6 | buf[Start_byte + 4] << 2
+ 80273e0:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 80273e2:	3303      	adds	r3, #3
+ 80273e4:	687a      	ldr	r2, [r7, #4]
+ 80273e6:	4413      	add	r3, r2
+ 80273e8:	781b      	ldrb	r3, [r3, #0]
+ 80273ea:	099b      	lsrs	r3, r3, #6
+ 80273ec:	b2db      	uxtb	r3, r3
+ 80273ee:	b21a      	sxth	r2, r3
+ 80273f0:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 80273f2:	3304      	adds	r3, #4
+ 80273f4:	6879      	ldr	r1, [r7, #4]
+ 80273f6:	440b      	add	r3, r1
+ 80273f8:	781b      	ldrb	r3, [r3, #0]
+ 80273fa:	009b      	lsls	r3, r3, #2
+ 80273fc:	b21b      	sxth	r3, r3
+ 80273fe:	4313      	orrs	r3, r2
+ 8027400:	b21a      	sxth	r2, r3
+			| buf[Start_byte + 5] << 10) & 0x07FF);
+ 8027402:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 8027404:	3305      	adds	r3, #5
+ 8027406:	6879      	ldr	r1, [r7, #4]
+ 8027408:	440b      	add	r3, r1
+ 802740a:	781b      	ldrb	r3, [r3, #0]
+ 802740c:	029b      	lsls	r3, r3, #10
+ 802740e:	b21b      	sxth	r3, r3
+ 8027410:	4313      	orrs	r3, r2
+ 8027412:	b21b      	sxth	r3, r3
+ 8027414:	f3c3 030a 	ubfx	r3, r3, #0, #11
+ 8027418:	b21b      	sxth	r3, r3
+	CH[2] = ((buf[Start_byte + 3] >> 6 | buf[Start_byte + 4] << 2
+ 802741a:	81bb      	strh	r3, [r7, #12]
+	CH[3] = ((buf[Start_byte + 5] >> 1 | buf[Start_byte + 6] << 7) & 0x07FF);
+ 802741c:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 802741e:	3305      	adds	r3, #5
+ 8027420:	687a      	ldr	r2, [r7, #4]
+ 8027422:	4413      	add	r3, r2
+ 8027424:	781b      	ldrb	r3, [r3, #0]
+ 8027426:	085b      	lsrs	r3, r3, #1
+ 8027428:	b2db      	uxtb	r3, r3
+ 802742a:	b21a      	sxth	r2, r3
+ 802742c:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 802742e:	3306      	adds	r3, #6
+ 8027430:	6879      	ldr	r1, [r7, #4]
+ 8027432:	440b      	add	r3, r1
+ 8027434:	781b      	ldrb	r3, [r3, #0]
+ 8027436:	01db      	lsls	r3, r3, #7
+ 8027438:	b21b      	sxth	r3, r3
+ 802743a:	4313      	orrs	r3, r2
+ 802743c:	b21b      	sxth	r3, r3
+ 802743e:	f3c3 030a 	ubfx	r3, r3, #0, #11
+ 8027442:	b21b      	sxth	r3, r3
+ 8027444:	81fb      	strh	r3, [r7, #14]
+	CH[4] = ((buf[Start_byte + 6] >> 4 | buf[Start_byte + 7] << 4) & 0x07FF);
+ 8027446:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 8027448:	3306      	adds	r3, #6
+ 802744a:	687a      	ldr	r2, [r7, #4]
+ 802744c:	4413      	add	r3, r2
+ 802744e:	781b      	ldrb	r3, [r3, #0]
+ 8027450:	091b      	lsrs	r3, r3, #4
+ 8027452:	b2db      	uxtb	r3, r3
+ 8027454:	b21a      	sxth	r2, r3
+ 8027456:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 8027458:	3307      	adds	r3, #7
+ 802745a:	6879      	ldr	r1, [r7, #4]
+ 802745c:	440b      	add	r3, r1
+ 802745e:	781b      	ldrb	r3, [r3, #0]
+ 8027460:	011b      	lsls	r3, r3, #4
+ 8027462:	b21b      	sxth	r3, r3
+ 8027464:	4313      	orrs	r3, r2
+ 8027466:	b21b      	sxth	r3, r3
+ 8027468:	f3c3 030a 	ubfx	r3, r3, #0, #11
+ 802746c:	b21b      	sxth	r3, r3
+ 802746e:	823b      	strh	r3, [r7, #16]
+	CH[5] = ((buf[Start_byte + 7] >> 7 | buf[Start_byte + 8] << 1
+ 8027470:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 8027472:	3307      	adds	r3, #7
+ 8027474:	687a      	ldr	r2, [r7, #4]
+ 8027476:	4413      	add	r3, r2
+ 8027478:	781b      	ldrb	r3, [r3, #0]
+ 802747a:	09db      	lsrs	r3, r3, #7
+ 802747c:	b2db      	uxtb	r3, r3
+ 802747e:	b21a      	sxth	r2, r3
+ 8027480:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 8027482:	3308      	adds	r3, #8
+ 8027484:	6879      	ldr	r1, [r7, #4]
+ 8027486:	440b      	add	r3, r1
+ 8027488:	781b      	ldrb	r3, [r3, #0]
+ 802748a:	005b      	lsls	r3, r3, #1
+ 802748c:	b21b      	sxth	r3, r3
+ 802748e:	4313      	orrs	r3, r2
+ 8027490:	b21a      	sxth	r2, r3
+			| buf[Start_byte + 9] << 9) & 0x07FF);
+ 8027492:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 8027494:	3309      	adds	r3, #9
+ 8027496:	6879      	ldr	r1, [r7, #4]
+ 8027498:	440b      	add	r3, r1
+ 802749a:	781b      	ldrb	r3, [r3, #0]
+ 802749c:	025b      	lsls	r3, r3, #9
+ 802749e:	b21b      	sxth	r3, r3
+ 80274a0:	4313      	orrs	r3, r2
+ 80274a2:	b21b      	sxth	r3, r3
+ 80274a4:	f3c3 030a 	ubfx	r3, r3, #0, #11
+ 80274a8:	b21b      	sxth	r3, r3
+	CH[5] = ((buf[Start_byte + 7] >> 7 | buf[Start_byte + 8] << 1
+ 80274aa:	827b      	strh	r3, [r7, #18]
+	CH[6] = ((buf[Start_byte + 9] >> 2 | buf[Start_byte + 10] << 6) & 0x07FF);
+ 80274ac:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 80274ae:	3309      	adds	r3, #9
+ 80274b0:	687a      	ldr	r2, [r7, #4]
+ 80274b2:	4413      	add	r3, r2
+ 80274b4:	781b      	ldrb	r3, [r3, #0]
+ 80274b6:	089b      	lsrs	r3, r3, #2
+ 80274b8:	b2db      	uxtb	r3, r3
+ 80274ba:	b21a      	sxth	r2, r3
+ 80274bc:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 80274be:	330a      	adds	r3, #10
+ 80274c0:	6879      	ldr	r1, [r7, #4]
+ 80274c2:	440b      	add	r3, r1
+ 80274c4:	781b      	ldrb	r3, [r3, #0]
+ 80274c6:	019b      	lsls	r3, r3, #6
+ 80274c8:	b21b      	sxth	r3, r3
+ 80274ca:	4313      	orrs	r3, r2
+ 80274cc:	b21b      	sxth	r3, r3
+ 80274ce:	f3c3 030a 	ubfx	r3, r3, #0, #11
+ 80274d2:	b21b      	sxth	r3, r3
+ 80274d4:	82bb      	strh	r3, [r7, #20]
+	CH[7] = ((buf[Start_byte + 10] >> 5 | buf[Start_byte + 11] << 3) & 0x07FF);
+ 80274d6:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 80274d8:	330a      	adds	r3, #10
+ 80274da:	687a      	ldr	r2, [r7, #4]
+ 80274dc:	4413      	add	r3, r2
+ 80274de:	781b      	ldrb	r3, [r3, #0]
+ 80274e0:	095b      	lsrs	r3, r3, #5
+ 80274e2:	b2db      	uxtb	r3, r3
+ 80274e4:	b21a      	sxth	r2, r3
+ 80274e6:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 80274e8:	330b      	adds	r3, #11
+ 80274ea:	6879      	ldr	r1, [r7, #4]
+ 80274ec:	440b      	add	r3, r1
+ 80274ee:	781b      	ldrb	r3, [r3, #0]
+ 80274f0:	00db      	lsls	r3, r3, #3
+ 80274f2:	b21b      	sxth	r3, r3
+ 80274f4:	4313      	orrs	r3, r2
+ 80274f6:	b21b      	sxth	r3, r3
+ 80274f8:	f3c3 030a 	ubfx	r3, r3, #0, #11
+ 80274fc:	b21b      	sxth	r3, r3
+ 80274fe:	82fb      	strh	r3, [r7, #22]
+	CH[8] = ((buf[Start_byte + 12] | buf[Start_byte + 13] << 8) & 0x07FF);
+ 8027500:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 8027502:	330c      	adds	r3, #12
+ 8027504:	687a      	ldr	r2, [r7, #4]
+ 8027506:	4413      	add	r3, r2
+ 8027508:	781b      	ldrb	r3, [r3, #0]
+ 802750a:	b21a      	sxth	r2, r3
+ 802750c:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 802750e:	330d      	adds	r3, #13
+ 8027510:	6879      	ldr	r1, [r7, #4]
+ 8027512:	440b      	add	r3, r1
+ 8027514:	781b      	ldrb	r3, [r3, #0]
+ 8027516:	021b      	lsls	r3, r3, #8
+ 8027518:	b21b      	sxth	r3, r3
+ 802751a:	4313      	orrs	r3, r2
+ 802751c:	b21b      	sxth	r3, r3
+ 802751e:	f3c3 030a 	ubfx	r3, r3, #0, #11
+ 8027522:	b21b      	sxth	r3, r3
+ 8027524:	833b      	strh	r3, [r7, #24]
+	CH[9] = ((buf[Start_byte + 13] >> 3 | buf[Start_byte + 14] << 5) & 0x07FF);
+ 8027526:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 8027528:	330d      	adds	r3, #13
+ 802752a:	687a      	ldr	r2, [r7, #4]
+ 802752c:	4413      	add	r3, r2
+ 802752e:	781b      	ldrb	r3, [r3, #0]
+ 8027530:	08db      	lsrs	r3, r3, #3
+ 8027532:	b2db      	uxtb	r3, r3
+ 8027534:	b21a      	sxth	r2, r3
+ 8027536:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 8027538:	330e      	adds	r3, #14
+ 802753a:	6879      	ldr	r1, [r7, #4]
+ 802753c:	440b      	add	r3, r1
+ 802753e:	781b      	ldrb	r3, [r3, #0]
+ 8027540:	015b      	lsls	r3, r3, #5
+ 8027542:	b21b      	sxth	r3, r3
+ 8027544:	4313      	orrs	r3, r2
+ 8027546:	b21b      	sxth	r3, r3
+ 8027548:	f3c3 030a 	ubfx	r3, r3, #0, #11
+ 802754c:	b21b      	sxth	r3, r3
+ 802754e:	837b      	strh	r3, [r7, #26]
+	CH[10] = ((buf[Start_byte + 14] >> 6 | buf[Start_byte + 15] << 2
+ 8027550:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 8027552:	330e      	adds	r3, #14
+ 8027554:	687a      	ldr	r2, [r7, #4]
+ 8027556:	4413      	add	r3, r2
+ 8027558:	781b      	ldrb	r3, [r3, #0]
+ 802755a:	099b      	lsrs	r3, r3, #6
+ 802755c:	b2db      	uxtb	r3, r3
+ 802755e:	b21a      	sxth	r2, r3
+ 8027560:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 8027562:	330f      	adds	r3, #15
+ 8027564:	6879      	ldr	r1, [r7, #4]
+ 8027566:	440b      	add	r3, r1
+ 8027568:	781b      	ldrb	r3, [r3, #0]
+ 802756a:	009b      	lsls	r3, r3, #2
+ 802756c:	b21b      	sxth	r3, r3
+ 802756e:	4313      	orrs	r3, r2
+ 8027570:	b21a      	sxth	r2, r3
+			| buf[Start_byte + 16] << 10) & 0x07FF);
+ 8027572:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 8027574:	3310      	adds	r3, #16
+ 8027576:	6879      	ldr	r1, [r7, #4]
+ 8027578:	440b      	add	r3, r1
+ 802757a:	781b      	ldrb	r3, [r3, #0]
+ 802757c:	029b      	lsls	r3, r3, #10
+ 802757e:	b21b      	sxth	r3, r3
+ 8027580:	4313      	orrs	r3, r2
+ 8027582:	b21b      	sxth	r3, r3
+ 8027584:	f3c3 030a 	ubfx	r3, r3, #0, #11
+ 8027588:	b21b      	sxth	r3, r3
+	CH[10] = ((buf[Start_byte + 14] >> 6 | buf[Start_byte + 15] << 2
+ 802758a:	83bb      	strh	r3, [r7, #28]
+	CH[11] = ((buf[Start_byte + 16] >> 1 | buf[Start_byte + 17] << 7) & 0x07FF);
+ 802758c:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 802758e:	3310      	adds	r3, #16
+ 8027590:	687a      	ldr	r2, [r7, #4]
+ 8027592:	4413      	add	r3, r2
+ 8027594:	781b      	ldrb	r3, [r3, #0]
+ 8027596:	085b      	lsrs	r3, r3, #1
+ 8027598:	b2db      	uxtb	r3, r3
+ 802759a:	b21a      	sxth	r2, r3
+ 802759c:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 802759e:	3311      	adds	r3, #17
+ 80275a0:	6879      	ldr	r1, [r7, #4]
+ 80275a2:	440b      	add	r3, r1
+ 80275a4:	781b      	ldrb	r3, [r3, #0]
+ 80275a6:	01db      	lsls	r3, r3, #7
+ 80275a8:	b21b      	sxth	r3, r3
+ 80275aa:	4313      	orrs	r3, r2
+ 80275ac:	b21b      	sxth	r3, r3
+ 80275ae:	f3c3 030a 	ubfx	r3, r3, #0, #11
+ 80275b2:	b21b      	sxth	r3, r3
+ 80275b4:	83fb      	strh	r3, [r7, #30]
+	CH[12] = ((buf[Start_byte + 17] >> 4 | buf[Start_byte + 18] << 4) & 0x07FF);
+ 80275b6:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 80275b8:	3311      	adds	r3, #17
+ 80275ba:	687a      	ldr	r2, [r7, #4]
+ 80275bc:	4413      	add	r3, r2
+ 80275be:	781b      	ldrb	r3, [r3, #0]
+ 80275c0:	091b      	lsrs	r3, r3, #4
+ 80275c2:	b2db      	uxtb	r3, r3
+ 80275c4:	b21a      	sxth	r2, r3
+ 80275c6:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 80275c8:	3312      	adds	r3, #18
+ 80275ca:	6879      	ldr	r1, [r7, #4]
+ 80275cc:	440b      	add	r3, r1
+ 80275ce:	781b      	ldrb	r3, [r3, #0]
+ 80275d0:	011b      	lsls	r3, r3, #4
+ 80275d2:	b21b      	sxth	r3, r3
+ 80275d4:	4313      	orrs	r3, r2
+ 80275d6:	b21b      	sxth	r3, r3
+ 80275d8:	f3c3 030a 	ubfx	r3, r3, #0, #11
+ 80275dc:	b21b      	sxth	r3, r3
+ 80275de:	843b      	strh	r3, [r7, #32]
+	CH[13] = ((buf[Start_byte + 18] >> 7 | buf[Start_byte + 19] << 1
+ 80275e0:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 80275e2:	3312      	adds	r3, #18
+ 80275e4:	687a      	ldr	r2, [r7, #4]
+ 80275e6:	4413      	add	r3, r2
+ 80275e8:	781b      	ldrb	r3, [r3, #0]
+ 80275ea:	09db      	lsrs	r3, r3, #7
+ 80275ec:	b2db      	uxtb	r3, r3
+ 80275ee:	b21a      	sxth	r2, r3
+ 80275f0:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 80275f2:	3313      	adds	r3, #19
+ 80275f4:	6879      	ldr	r1, [r7, #4]
+ 80275f6:	440b      	add	r3, r1
+ 80275f8:	781b      	ldrb	r3, [r3, #0]
+ 80275fa:	005b      	lsls	r3, r3, #1
+ 80275fc:	b21b      	sxth	r3, r3
+ 80275fe:	4313      	orrs	r3, r2
+ 8027600:	b21a      	sxth	r2, r3
+			| buf[Start_byte + 20] << 9) & 0x07FF);
+ 8027602:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 8027604:	3314      	adds	r3, #20
+ 8027606:	6879      	ldr	r1, [r7, #4]
+ 8027608:	440b      	add	r3, r1
+ 802760a:	781b      	ldrb	r3, [r3, #0]
+ 802760c:	025b      	lsls	r3, r3, #9
+ 802760e:	b21b      	sxth	r3, r3
+ 8027610:	4313      	orrs	r3, r2
+ 8027612:	b21b      	sxth	r3, r3
+ 8027614:	f3c3 030a 	ubfx	r3, r3, #0, #11
+ 8027618:	b21b      	sxth	r3, r3
+	CH[13] = ((buf[Start_byte + 18] >> 7 | buf[Start_byte + 19] << 1
+ 802761a:	847b      	strh	r3, [r7, #34]	@ 0x22
+	CH[14] = ((buf[Start_byte + 20] >> 2 | buf[Start_byte + 21] << 6) & 0x07FF);
+ 802761c:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 802761e:	3314      	adds	r3, #20
+ 8027620:	687a      	ldr	r2, [r7, #4]
+ 8027622:	4413      	add	r3, r2
+ 8027624:	781b      	ldrb	r3, [r3, #0]
+ 8027626:	089b      	lsrs	r3, r3, #2
+ 8027628:	b2db      	uxtb	r3, r3
+ 802762a:	b21a      	sxth	r2, r3
+ 802762c:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 802762e:	3315      	adds	r3, #21
+ 8027630:	6879      	ldr	r1, [r7, #4]
+ 8027632:	440b      	add	r3, r1
+ 8027634:	781b      	ldrb	r3, [r3, #0]
+ 8027636:	019b      	lsls	r3, r3, #6
+ 8027638:	b21b      	sxth	r3, r3
+ 802763a:	4313      	orrs	r3, r2
+ 802763c:	b21b      	sxth	r3, r3
+ 802763e:	f3c3 030a 	ubfx	r3, r3, #0, #11
+ 8027642:	b21b      	sxth	r3, r3
+ 8027644:	84bb      	strh	r3, [r7, #36]	@ 0x24
+	CH[15] = ((buf[Start_byte + 21] >> 5 | buf[Start_byte + 22] << 3) & 0x07FF);
+ 8027646:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 8027648:	3315      	adds	r3, #21
+ 802764a:	687a      	ldr	r2, [r7, #4]
+ 802764c:	4413      	add	r3, r2
+ 802764e:	781b      	ldrb	r3, [r3, #0]
+ 8027650:	095b      	lsrs	r3, r3, #5
+ 8027652:	b2db      	uxtb	r3, r3
+ 8027654:	b21a      	sxth	r2, r3
+ 8027656:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 8027658:	3316      	adds	r3, #22
+ 802765a:	6879      	ldr	r1, [r7, #4]
+ 802765c:	440b      	add	r3, r1
+ 802765e:	781b      	ldrb	r3, [r3, #0]
+ 8027660:	00db      	lsls	r3, r3, #3
+ 8027662:	b21b      	sxth	r3, r3
+ 8027664:	4313      	orrs	r3, r2
+ 8027666:	b21b      	sxth	r3, r3
+ 8027668:	f3c3 030a 	ubfx	r3, r3, #0, #11
+ 802766c:	b21b      	sxth	r3, r3
+ 802766e:	84fb      	strh	r3, [r7, #38]	@ 0x26
+
+	//按键数值：1050为中间值，272-1712
+	for (int i = 0; i < 16; i++)
+ 8027670:	2300      	movs	r3, #0
+ 8027672:	62fb      	str	r3, [r7, #44]	@ 0x2c
+ 8027674:	e01c      	b.n	80276b0 <Sbus_Data_Count+0x330>
+	{
+		//But_Value[i+1]=  (int32_t)(((CH[i]-272)*0.625+1050-1500)*2.22222);
+
+		But_Value[i + 1] = (int32_t) ((CH[i] - 992) * 1.388889);
+ 8027676:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
+ 8027678:	005b      	lsls	r3, r3, #1
+ 802767a:	3330      	adds	r3, #48	@ 0x30
+ 802767c:	443b      	add	r3, r7
+ 802767e:	f933 3c28 	ldrsh.w	r3, [r3, #-40]
+ 8027682:	f5a3 7378 	sub.w	r3, r3, #992	@ 0x3e0
+ 8027686:	ee07 3a90 	vmov	s15, r3
+ 802768a:	eeb8 7be7 	vcvt.f64.s32	d7, s15
+ 802768e:	ed9f 6b16 	vldr	d6, [pc, #88]	@ 80276e8 <Sbus_Data_Count+0x368>
+ 8027692:	ee27 7b06 	vmul.f64	d7, d7, d6
+ 8027696:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
+ 8027698:	3301      	adds	r3, #1
+ 802769a:	009b      	lsls	r3, r3, #2
+ 802769c:	683a      	ldr	r2, [r7, #0]
+ 802769e:	4413      	add	r3, r2
+ 80276a0:	eefd 7bc7 	vcvt.s32.f64	s15, d7
+ 80276a4:	ee17 2a90 	vmov	r2, s15
+ 80276a8:	601a      	str	r2, [r3, #0]
+	for (int i = 0; i < 16; i++)
+ 80276aa:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
+ 80276ac:	3301      	adds	r3, #1
+ 80276ae:	62fb      	str	r3, [r7, #44]	@ 0x2c
+ 80276b0:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
+ 80276b2:	2b0f      	cmp	r3, #15
+ 80276b4:	dddf      	ble.n	8027676 <Sbus_Data_Count+0x2f6>
+	}
+
+	//遥控器地面站在线状态
+	if (buf[22] == 0)
+ 80276b6:	687b      	ldr	r3, [r7, #4]
+ 80276b8:	3316      	adds	r3, #22
+ 80276ba:	781b      	ldrb	r3, [r3, #0]
+ 80276bc:	2b00      	cmp	r3, #0
+ 80276be:	d104      	bne.n	80276ca <Sbus_Data_Count+0x34a>
+		But_Value[17] = 1;
+ 80276c0:	683b      	ldr	r3, [r7, #0]
+ 80276c2:	3344      	adds	r3, #68	@ 0x44
+ 80276c4:	2201      	movs	r2, #1
+ 80276c6:	601a      	str	r2, [r3, #0]
+ 80276c8:	e003      	b.n	80276d2 <Sbus_Data_Count+0x352>
+	else
+		But_Value[17] = 0;
+ 80276ca:	683b      	ldr	r3, [r7, #0]
+ 80276cc:	3344      	adds	r3, #68	@ 0x44
+ 80276ce:	2200      	movs	r2, #0
+ 80276d0:	601a      	str	r2, [r3, #0]
+
+	But_Value[0]++;
+ 80276d2:	683b      	ldr	r3, [r7, #0]
+ 80276d4:	681b      	ldr	r3, [r3, #0]
+ 80276d6:	1c5a      	adds	r2, r3, #1
+ 80276d8:	683b      	ldr	r3, [r7, #0]
+ 80276da:	601a      	str	r2, [r3, #0]
+}
+ 80276dc:	bf00      	nop
+ 80276de:	3734      	adds	r7, #52	@ 0x34
+ 80276e0:	46bd      	mov	sp, r7
+ 80276e2:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80276e6:	4770      	bx	lr
+ 80276e8:	ac0c62e5 	.word	0xac0c62e5
+ 80276ec:	3ff638e3 	.word	0x3ff638e3
+
+080276f0 <MK32_Sbus_UART_Handler_intialize>:
+
+
+void MK32_Sbus_UART_Handler_intialize(struct UARTHandler* Handler)
+{
+ 80276f0:	b590      	push	{r4, r7, lr}
+ 80276f2:	b083      	sub	sp, #12
+ 80276f4:	af00      	add	r7, sp, #0
+ 80276f6:	6078      	str	r0, [r7, #4]
+	MK32_Sbus_Controller = Handler;
+ 80276f8:	4a1f      	ldr	r2, [pc, #124]	@ (8027778 <MK32_Sbus_UART_Handler_intialize+0x88>)
+ 80276fa:	687b      	ldr	r3, [r7, #4]
+ 80276fc:	6013      	str	r3, [r2, #0]
+	MK32_Sbus_Controller->UART_Decode = decode_MK32Data;
+ 80276fe:	4b1e      	ldr	r3, [pc, #120]	@ (8027778 <MK32_Sbus_UART_Handler_intialize+0x88>)
+ 8027700:	681b      	ldr	r3, [r3, #0]
+ 8027702:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8027706:	461a      	mov	r2, r3
+ 8027708:	4b1c      	ldr	r3, [pc, #112]	@ (802777c <MK32_Sbus_UART_Handler_intialize+0x8c>)
+ 802770a:	6313      	str	r3, [r2, #48]	@ 0x30
+	MK32_Sbus_Controller->Wait_time=4;
+ 802770c:	4b1a      	ldr	r3, [pc, #104]	@ (8027778 <MK32_Sbus_UART_Handler_intialize+0x88>)
+ 802770e:	681b      	ldr	r3, [r3, #0]
+ 8027710:	2204      	movs	r2, #4
+ 8027712:	609a      	str	r2, [r3, #8]
+	MK32_Sbus_Controller->dispacherController->Dispacher_Enable=0;//不周期性发送
+ 8027714:	4b18      	ldr	r3, [pc, #96]	@ (8027778 <MK32_Sbus_UART_Handler_intialize+0x88>)
+ 8027716:	681b      	ldr	r3, [r3, #0]
+ 8027718:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 802771c:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 802771e:	2200      	movs	r2, #0
+ 8027720:	81da      	strh	r2, [r3, #14]
+	HardWareErrorController->Add_PCOMHardWare(HardWareErrorController,"mk32_sbus",0,ComError_Mk32_SBus);
+ 8027722:	4b17      	ldr	r3, [pc, #92]	@ (8027780 <MK32_Sbus_UART_Handler_intialize+0x90>)
+ 8027724:	681b      	ldr	r3, [r3, #0]
+ 8027726:	68dc      	ldr	r4, [r3, #12]
+ 8027728:	4b15      	ldr	r3, [pc, #84]	@ (8027780 <MK32_Sbus_UART_Handler_intialize+0x90>)
+ 802772a:	6818      	ldr	r0, [r3, #0]
+ 802772c:	2300      	movs	r3, #0
+ 802772e:	2200      	movs	r2, #0
+ 8027730:	4914      	ldr	r1, [pc, #80]	@ (8027784 <MK32_Sbus_UART_Handler_intialize+0x94>)
+ 8027732:	47a0      	blx	r4
+  	LOG("MK32_Sbus_intialize");
+ 8027734:	4b14      	ldr	r3, [pc, #80]	@ (8027788 <MK32_Sbus_UART_Handler_intialize+0x98>)
+ 8027736:	781b      	ldrb	r3, [r3, #0]
+ 8027738:	2b03      	cmp	r3, #3
+ 802773a:	d918      	bls.n	802776e <MK32_Sbus_UART_Handler_intialize+0x7e>
+ 802773c:	2330      	movs	r3, #48	@ 0x30
+ 802773e:	061a      	lsls	r2, r3, #24
+ 8027740:	2330      	movs	r3, #48	@ 0x30
+ 8027742:	041b      	lsls	r3, r3, #16
+ 8027744:	431a      	orrs	r2, r3
+ 8027746:	2330      	movs	r3, #48	@ 0x30
+ 8027748:	021b      	lsls	r3, r3, #8
+ 802774a:	4313      	orrs	r3, r2
+ 802774c:	2230      	movs	r2, #48	@ 0x30
+ 802774e:	ea43 0102 	orr.w	r1, r3, r2
+ 8027752:	2344      	movs	r3, #68	@ 0x44
+ 8027754:	061a      	lsls	r2, r3, #24
+ 8027756:	2346      	movs	r3, #70	@ 0x46
+ 8027758:	041b      	lsls	r3, r3, #16
+ 802775a:	431a      	orrs	r2, r3
+ 802775c:	234c      	movs	r3, #76	@ 0x4c
+ 802775e:	021b      	lsls	r3, r3, #8
+ 8027760:	4313      	orrs	r3, r2
+ 8027762:	2254      	movs	r2, #84	@ 0x54
+ 8027764:	431a      	orrs	r2, r3
+ 8027766:	4b09      	ldr	r3, [pc, #36]	@ (802778c <MK32_Sbus_UART_Handler_intialize+0x9c>)
+ 8027768:	2004      	movs	r0, #4
+ 802776a:	f7fe fd63 	bl	8026234 <DLTuc_LogOutVarArgs>
+}
+ 802776e:	bf00      	nop
+ 8027770:	370c      	adds	r7, #12
+ 8027772:	46bd      	mov	sp, r7
+ 8027774:	bd90      	pop	{r4, r7, pc}
+ 8027776:	bf00      	nop
+ 8027778:	2400a3fc 	.word	0x2400a3fc
+ 802777c:	08027321 	.word	0x08027321
+ 8027780:	24000618 	.word	0x24000618
+ 8027784:	080413cc 	.word	0x080413cc
+ 8027788:	24009110 	.word	0x24009110
+ 802778c:	080413d8 	.word	0x080413d8
+
+08027790 <Speedl_PID>:
+double PID_KD = 12;
+//double Sys_T=0.01;//System time
+double k_1_error = 0;
+void Speedl_PID(double CurrentValue, double TargetValue, double Sys_T,
+        double *Gain_speed)
+{
+ 8027790:	b480      	push	{r7}
+ 8027792:	b08f      	sub	sp, #60	@ 0x3c
+ 8027794:	af00      	add	r7, sp, #0
+ 8027796:	ed87 0b06 	vstr	d0, [r7, #24]
+ 802779a:	ed87 1b04 	vstr	d1, [r7, #16]
+ 802779e:	ed87 2b02 	vstr	d2, [r7, #8]
+ 80277a2:	6078      	str	r0, [r7, #4]
+	double Error;
+	double P_Error;
+	double D_Error;
+	Error = TargetValue - CurrentValue;
+ 80277a4:	ed97 6b04 	vldr	d6, [r7, #16]
+ 80277a8:	ed97 7b06 	vldr	d7, [r7, #24]
+ 80277ac:	ee36 7b47 	vsub.f64	d7, d6, d7
+ 80277b0:	ed87 7b0c 	vstr	d7, [r7, #48]	@ 0x30
+	if (Error >= 180)
+ 80277b4:	ed97 7b0c 	vldr	d7, [r7, #48]	@ 0x30
+ 80277b8:	ed9f 6b27 	vldr	d6, [pc, #156]	@ 8027858 <Speedl_PID+0xc8>
+ 80277bc:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 80277c0:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 80277c4:	db08      	blt.n	80277d8 <Speedl_PID+0x48>
+	{
+		Error = Error - 360;
+ 80277c6:	ed97 7b0c 	vldr	d7, [r7, #48]	@ 0x30
+ 80277ca:	ed9f 6b25 	vldr	d6, [pc, #148]	@ 8027860 <Speedl_PID+0xd0>
+ 80277ce:	ee37 7b46 	vsub.f64	d7, d7, d6
+ 80277d2:	ed87 7b0c 	vstr	d7, [r7, #48]	@ 0x30
+ 80277d6:	e010      	b.n	80277fa <Speedl_PID+0x6a>
+	}
+	else if (Error <= -180)
+ 80277d8:	ed97 7b0c 	vldr	d7, [r7, #48]	@ 0x30
+ 80277dc:	ed9f 6b22 	vldr	d6, [pc, #136]	@ 8027868 <Speedl_PID+0xd8>
+ 80277e0:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 80277e4:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 80277e8:	d807      	bhi.n	80277fa <Speedl_PID+0x6a>
+	{
+		Error = Error + 360;
+ 80277ea:	ed97 7b0c 	vldr	d7, [r7, #48]	@ 0x30
+ 80277ee:	ed9f 6b1c 	vldr	d6, [pc, #112]	@ 8027860 <Speedl_PID+0xd0>
+ 80277f2:	ee37 7b06 	vadd.f64	d7, d7, d6
+ 80277f6:	ed87 7b0c 	vstr	d7, [r7, #48]	@ 0x30
+	}
+	P_Error = Error;
+ 80277fa:	e9d7 230c 	ldrd	r2, r3, [r7, #48]	@ 0x30
+ 80277fe:	e9c7 230a 	strd	r2, r3, [r7, #40]	@ 0x28
+	D_Error = Error - k_1_error;
+ 8027802:	4b1b      	ldr	r3, [pc, #108]	@ (8027870 <Speedl_PID+0xe0>)
+ 8027804:	ed93 7b00 	vldr	d7, [r3]
+ 8027808:	ed97 6b0c 	vldr	d6, [r7, #48]	@ 0x30
+ 802780c:	ee36 7b47 	vsub.f64	d7, d6, d7
+ 8027810:	ed87 7b08 	vstr	d7, [r7, #32]
+	k_1_error = Error;
+ 8027814:	4916      	ldr	r1, [pc, #88]	@ (8027870 <Speedl_PID+0xe0>)
+ 8027816:	e9d7 230c 	ldrd	r2, r3, [r7, #48]	@ 0x30
+ 802781a:	e9c1 2300 	strd	r2, r3, [r1]
+	Gain_speed[0] = PID_KP * P_Error + PID_KD * D_Error / Sys_T;
+ 802781e:	4b15      	ldr	r3, [pc, #84]	@ (8027874 <Speedl_PID+0xe4>)
+ 8027820:	ed93 6b00 	vldr	d6, [r3]
+ 8027824:	ed97 7b0a 	vldr	d7, [r7, #40]	@ 0x28
+ 8027828:	ee26 6b07 	vmul.f64	d6, d6, d7
+ 802782c:	4b12      	ldr	r3, [pc, #72]	@ (8027878 <Speedl_PID+0xe8>)
+ 802782e:	ed93 5b00 	vldr	d5, [r3]
+ 8027832:	ed97 7b08 	vldr	d7, [r7, #32]
+ 8027836:	ee25 4b07 	vmul.f64	d4, d5, d7
+ 802783a:	ed97 5b02 	vldr	d5, [r7, #8]
+ 802783e:	ee84 7b05 	vdiv.f64	d7, d4, d5
+ 8027842:	ee36 7b07 	vadd.f64	d7, d6, d7
+ 8027846:	687b      	ldr	r3, [r7, #4]
+ 8027848:	ed83 7b00 	vstr	d7, [r3]
+}
+ 802784c:	bf00      	nop
+ 802784e:	373c      	adds	r7, #60	@ 0x3c
+ 8027850:	46bd      	mov	sp, r7
+ 8027852:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8027856:	4770      	bx	lr
+ 8027858:	00000000 	.word	0x00000000
+ 802785c:	40668000 	.word	0x40668000
+ 8027860:	00000000 	.word	0x00000000
+ 8027864:	40768000 	.word	0x40768000
+ 8027868:	00000000 	.word	0x00000000
+ 802786c:	c0668000 	.word	0xc0668000
+ 8027870:	2400a408 	.word	0x2400a408
+ 8027874:	24000058 	.word	0x24000058
+ 8027878:	24000060 	.word	0x24000060
+
+0802787c <GF_MSP_PID_Now_Der_adj_Com_Horizon>:
+
+}
+
+
+void GF_MSP_PID_Now_Der_adj_Com_Horizon(double Current_Angle, double Desire_Angle_Input,     double Auto_Speed, double Auto_Speed_Max, double System_time,  double *W_Speed_1)
+{
+ 802787c:	b580      	push	{r7, lr}
+ 802787e:	b0a2      	sub	sp, #136	@ 0x88
+ 8027880:	af00      	add	r7, sp, #0
+ 8027882:	ed87 0b0a 	vstr	d0, [r7, #40]	@ 0x28
+ 8027886:	ed87 1b08 	vstr	d1, [r7, #32]
+ 802788a:	ed87 2b06 	vstr	d2, [r7, #24]
+ 802788e:	ed87 3b04 	vstr	d3, [r7, #16]
+ 8027892:	ed87 4b02 	vstr	d4, [r7, #8]
+ 8027896:	6078      	str	r0, [r7, #4]
+
+	Desire_Angle = Desire_Angle_Input;
+ 8027898:	49d8      	ldr	r1, [pc, #864]	@ (8027bfc <GF_MSP_PID_Now_Der_adj_Com_Horizon+0x380>)
+ 802789a:	e9d7 2308 	ldrd	r2, r3, [r7, #32]
+ 802789e:	e9c1 2300 	strd	r2, r3, [r1]
+	//水平 前进抬车头
+	double Detal_Angle = fabs(Current_Angle - Desire_Angle);
+ 80278a2:	4bd6      	ldr	r3, [pc, #856]	@ (8027bfc <GF_MSP_PID_Now_Der_adj_Com_Horizon+0x380>)
+ 80278a4:	ed93 7b00 	vldr	d7, [r3]
+ 80278a8:	ed97 6b0a 	vldr	d6, [r7, #40]	@ 0x28
+ 80278ac:	ee36 7b47 	vsub.f64	d7, d6, d7
+ 80278b0:	eeb0 7bc7 	vabs.f64	d7, d7
+ 80278b4:	ed87 7b18 	vstr	d7, [r7, #96]	@ 0x60
+	double Incre_Speed[1];
+	Speedl_PID(Current_Angle, Desire_Angle, System_time, Incre_Speed);
+ 80278b8:	4bd0      	ldr	r3, [pc, #832]	@ (8027bfc <GF_MSP_PID_Now_Der_adj_Com_Horizon+0x380>)
+ 80278ba:	ed93 7b00 	vldr	d7, [r3]
+ 80278be:	f107 0330 	add.w	r3, r7, #48	@ 0x30
+ 80278c2:	4618      	mov	r0, r3
+ 80278c4:	ed97 2b02 	vldr	d2, [r7, #8]
+ 80278c8:	eeb0 1b47 	vmov.f64	d1, d7
+ 80278cc:	ed97 0b0a 	vldr	d0, [r7, #40]	@ 0x28
+ 80278d0:	f7ff ff5e 	bl	8027790 <Speedl_PID>
+	Incre_Speed[0] = 8 * Incre_Speed[0];
+ 80278d4:	ed97 7b0c 	vldr	d7, [r7, #48]	@ 0x30
+ 80278d8:	eeb2 6b00 	vmov.f64	d6, #32	@ 0x41000000  8.0
+ 80278dc:	ee27 7b06 	vmul.f64	d7, d7, d6
+ 80278e0:	ed87 7b0c 	vstr	d7, [r7, #48]	@ 0x30
+	double deltaAngle1 = 2;
+ 80278e4:	f04f 0200 	mov.w	r2, #0
+ 80278e8:	f04f 4380 	mov.w	r3, #1073741824	@ 0x40000000
+ 80278ec:	e9c7 2316 	strd	r2, r3, [r7, #88]	@ 0x58
+	double deltaAngle2 = 5;
+ 80278f0:	f04f 0200 	mov.w	r2, #0
+ 80278f4:	4bc2      	ldr	r3, [pc, #776]	@ (8027c00 <GF_MSP_PID_Now_Der_adj_Com_Horizon+0x384>)
+ 80278f6:	e9c7 2314 	strd	r2, r3, [r7, #80]	@ 0x50
+	double deltaAngle3 = 10;
+ 80278fa:	f04f 0200 	mov.w	r2, #0
+ 80278fe:	4bc1      	ldr	r3, [pc, #772]	@ (8027c04 <GF_MSP_PID_Now_Der_adj_Com_Horizon+0x388>)
+ 8027900:	e9c7 2312 	strd	r2, r3, [r7, #72]	@ 0x48
+	//double deltaAngle4=25;
+	double LeftSpeed_Con_1;
+	double RightSpeed_Con_1;
+	double LeftSpeed_Con_2;
+	double RightSpeed_Con_2;
+	if (Detal_Angle <= deltaAngle1)
+ 8027904:	ed97 6b18 	vldr	d6, [r7, #96]	@ 0x60
+ 8027908:	ed97 7b16 	vldr	d7, [r7, #88]	@ 0x58
+ 802790c:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 8027910:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 8027914:	d834      	bhi.n	8027980 <GF_MSP_PID_Now_Der_adj_Com_Horizon+0x104>
+	{
+		LeftSpeed_Con_1 = (Auto_Speed + Kp1 * Incre_Speed[0]);
+ 8027916:	ed97 6b0c 	vldr	d6, [r7, #48]	@ 0x30
+ 802791a:	4bbb      	ldr	r3, [pc, #748]	@ (8027c08 <GF_MSP_PID_Now_Der_adj_Com_Horizon+0x38c>)
+ 802791c:	ed93 7b00 	vldr	d7, [r3]
+ 8027920:	ee26 7b07 	vmul.f64	d7, d6, d7
+ 8027924:	ed97 6b06 	vldr	d6, [r7, #24]
+ 8027928:	ee36 7b07 	vadd.f64	d7, d6, d7
+ 802792c:	ed87 7b20 	vstr	d7, [r7, #128]	@ 0x80
+		RightSpeed_Con_1 = (Auto_Speed - Kp1 * Incre_Speed[0]);
+ 8027930:	ed97 6b0c 	vldr	d6, [r7, #48]	@ 0x30
+ 8027934:	4bb4      	ldr	r3, [pc, #720]	@ (8027c08 <GF_MSP_PID_Now_Der_adj_Com_Horizon+0x38c>)
+ 8027936:	ed93 7b00 	vldr	d7, [r3]
+ 802793a:	ee26 7b07 	vmul.f64	d7, d6, d7
+ 802793e:	ed97 6b06 	vldr	d6, [r7, #24]
+ 8027942:	ee36 7b47 	vsub.f64	d7, d6, d7
+ 8027946:	ed87 7b1e 	vstr	d7, [r7, #120]	@ 0x78
+		LeftSpeed_Con_2 = Auto_Speed + Kp1 * Incre_Speed[0];
+ 802794a:	ed97 6b0c 	vldr	d6, [r7, #48]	@ 0x30
+ 802794e:	4bae      	ldr	r3, [pc, #696]	@ (8027c08 <GF_MSP_PID_Now_Der_adj_Com_Horizon+0x38c>)
+ 8027950:	ed93 7b00 	vldr	d7, [r3]
+ 8027954:	ee26 7b07 	vmul.f64	d7, d6, d7
+ 8027958:	ed97 6b06 	vldr	d6, [r7, #24]
+ 802795c:	ee36 7b07 	vadd.f64	d7, d6, d7
+ 8027960:	ed87 7b1c 	vstr	d7, [r7, #112]	@ 0x70
+		RightSpeed_Con_2 = Auto_Speed - Kp1 * Incre_Speed[0];
+ 8027964:	ed97 6b0c 	vldr	d6, [r7, #48]	@ 0x30
+ 8027968:	4ba7      	ldr	r3, [pc, #668]	@ (8027c08 <GF_MSP_PID_Now_Der_adj_Com_Horizon+0x38c>)
+ 802796a:	ed93 7b00 	vldr	d7, [r3]
+ 802796e:	ee26 7b07 	vmul.f64	d7, d6, d7
+ 8027972:	ed97 6b06 	vldr	d6, [r7, #24]
+ 8027976:	ee36 7b47 	vsub.f64	d7, d6, d7
+ 802797a:	ed87 7b1a 	vstr	d7, [r7, #104]	@ 0x68
+ 802797e:	e0c1      	b.n	8027b04 <GF_MSP_PID_Now_Der_adj_Com_Horizon+0x288>
+//小角度时，两前轮调整
+	}
+	else if (Detal_Angle > deltaAngle1 && Detal_Angle <= deltaAngle2)
+ 8027980:	ed97 6b18 	vldr	d6, [r7, #96]	@ 0x60
+ 8027984:	ed97 7b16 	vldr	d7, [r7, #88]	@ 0x58
+ 8027988:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802798c:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 8027990:	dd3d      	ble.n	8027a0e <GF_MSP_PID_Now_Der_adj_Com_Horizon+0x192>
+ 8027992:	ed97 6b18 	vldr	d6, [r7, #96]	@ 0x60
+ 8027996:	ed97 7b14 	vldr	d7, [r7, #80]	@ 0x50
+ 802799a:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802799e:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 80279a2:	d834      	bhi.n	8027a0e <GF_MSP_PID_Now_Der_adj_Com_Horizon+0x192>
+	{
+		LeftSpeed_Con_1 = (Auto_Speed + Kp2 * Incre_Speed[0]);
+ 80279a4:	ed97 6b0c 	vldr	d6, [r7, #48]	@ 0x30
+ 80279a8:	4b98      	ldr	r3, [pc, #608]	@ (8027c0c <GF_MSP_PID_Now_Der_adj_Com_Horizon+0x390>)
+ 80279aa:	ed93 7b00 	vldr	d7, [r3]
+ 80279ae:	ee26 7b07 	vmul.f64	d7, d6, d7
+ 80279b2:	ed97 6b06 	vldr	d6, [r7, #24]
+ 80279b6:	ee36 7b07 	vadd.f64	d7, d6, d7
+ 80279ba:	ed87 7b20 	vstr	d7, [r7, #128]	@ 0x80
+		RightSpeed_Con_1 = (Auto_Speed - Kp2 * Incre_Speed[0]);
+ 80279be:	ed97 6b0c 	vldr	d6, [r7, #48]	@ 0x30
+ 80279c2:	4b92      	ldr	r3, [pc, #584]	@ (8027c0c <GF_MSP_PID_Now_Der_adj_Com_Horizon+0x390>)
+ 80279c4:	ed93 7b00 	vldr	d7, [r3]
+ 80279c8:	ee26 7b07 	vmul.f64	d7, d6, d7
+ 80279cc:	ed97 6b06 	vldr	d6, [r7, #24]
+ 80279d0:	ee36 7b47 	vsub.f64	d7, d6, d7
+ 80279d4:	ed87 7b1e 	vstr	d7, [r7, #120]	@ 0x78
+		LeftSpeed_Con_2 = Auto_Speed + Kp2 * Incre_Speed[0];
+ 80279d8:	ed97 6b0c 	vldr	d6, [r7, #48]	@ 0x30
+ 80279dc:	4b8b      	ldr	r3, [pc, #556]	@ (8027c0c <GF_MSP_PID_Now_Der_adj_Com_Horizon+0x390>)
+ 80279de:	ed93 7b00 	vldr	d7, [r3]
+ 80279e2:	ee26 7b07 	vmul.f64	d7, d6, d7
+ 80279e6:	ed97 6b06 	vldr	d6, [r7, #24]
+ 80279ea:	ee36 7b07 	vadd.f64	d7, d6, d7
+ 80279ee:	ed87 7b1c 	vstr	d7, [r7, #112]	@ 0x70
+		RightSpeed_Con_2 = Auto_Speed - Kp2 * Incre_Speed[0];
+ 80279f2:	ed97 6b0c 	vldr	d6, [r7, #48]	@ 0x30
+ 80279f6:	4b85      	ldr	r3, [pc, #532]	@ (8027c0c <GF_MSP_PID_Now_Der_adj_Com_Horizon+0x390>)
+ 80279f8:	ed93 7b00 	vldr	d7, [r3]
+ 80279fc:	ee26 7b07 	vmul.f64	d7, d6, d7
+ 8027a00:	ed97 6b06 	vldr	d6, [r7, #24]
+ 8027a04:	ee36 7b47 	vsub.f64	d7, d6, d7
+ 8027a08:	ed87 7b1a 	vstr	d7, [r7, #104]	@ 0x68
+ 8027a0c:	e07a      	b.n	8027b04 <GF_MSP_PID_Now_Der_adj_Com_Horizon+0x288>
+//中小角度时，两前轮差速，两后轮跟踪调整
+	}
+	else if (Detal_Angle > deltaAngle2 && Detal_Angle <= deltaAngle3)
+ 8027a0e:	ed97 6b18 	vldr	d6, [r7, #96]	@ 0x60
+ 8027a12:	ed97 7b14 	vldr	d7, [r7, #80]	@ 0x50
+ 8027a16:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 8027a1a:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 8027a1e:	dd3d      	ble.n	8027a9c <GF_MSP_PID_Now_Der_adj_Com_Horizon+0x220>
+ 8027a20:	ed97 6b18 	vldr	d6, [r7, #96]	@ 0x60
+ 8027a24:	ed97 7b12 	vldr	d7, [r7, #72]	@ 0x48
+ 8027a28:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 8027a2c:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 8027a30:	d834      	bhi.n	8027a9c <GF_MSP_PID_Now_Der_adj_Com_Horizon+0x220>
+	{
+		LeftSpeed_Con_1 = (Auto_Speed + Kp3 * Incre_Speed[0]);
+ 8027a32:	ed97 6b0c 	vldr	d6, [r7, #48]	@ 0x30
+ 8027a36:	4b76      	ldr	r3, [pc, #472]	@ (8027c10 <GF_MSP_PID_Now_Der_adj_Com_Horizon+0x394>)
+ 8027a38:	ed93 7b00 	vldr	d7, [r3]
+ 8027a3c:	ee26 7b07 	vmul.f64	d7, d6, d7
+ 8027a40:	ed97 6b06 	vldr	d6, [r7, #24]
+ 8027a44:	ee36 7b07 	vadd.f64	d7, d6, d7
+ 8027a48:	ed87 7b20 	vstr	d7, [r7, #128]	@ 0x80
+		RightSpeed_Con_1 = (Auto_Speed - Kp3 * Incre_Speed[0]);
+ 8027a4c:	ed97 6b0c 	vldr	d6, [r7, #48]	@ 0x30
+ 8027a50:	4b6f      	ldr	r3, [pc, #444]	@ (8027c10 <GF_MSP_PID_Now_Der_adj_Com_Horizon+0x394>)
+ 8027a52:	ed93 7b00 	vldr	d7, [r3]
+ 8027a56:	ee26 7b07 	vmul.f64	d7, d6, d7
+ 8027a5a:	ed97 6b06 	vldr	d6, [r7, #24]
+ 8027a5e:	ee36 7b47 	vsub.f64	d7, d6, d7
+ 8027a62:	ed87 7b1e 	vstr	d7, [r7, #120]	@ 0x78
+		LeftSpeed_Con_2 = Auto_Speed + Kp3 * Incre_Speed[0];
+ 8027a66:	ed97 6b0c 	vldr	d6, [r7, #48]	@ 0x30
+ 8027a6a:	4b69      	ldr	r3, [pc, #420]	@ (8027c10 <GF_MSP_PID_Now_Der_adj_Com_Horizon+0x394>)
+ 8027a6c:	ed93 7b00 	vldr	d7, [r3]
+ 8027a70:	ee26 7b07 	vmul.f64	d7, d6, d7
+ 8027a74:	ed97 6b06 	vldr	d6, [r7, #24]
+ 8027a78:	ee36 7b07 	vadd.f64	d7, d6, d7
+ 8027a7c:	ed87 7b1c 	vstr	d7, [r7, #112]	@ 0x70
+		RightSpeed_Con_2 = Auto_Speed - Kp3 * Incre_Speed[0];
+ 8027a80:	ed97 6b0c 	vldr	d6, [r7, #48]	@ 0x30
+ 8027a84:	4b62      	ldr	r3, [pc, #392]	@ (8027c10 <GF_MSP_PID_Now_Der_adj_Com_Horizon+0x394>)
+ 8027a86:	ed93 7b00 	vldr	d7, [r3]
+ 8027a8a:	ee26 7b07 	vmul.f64	d7, d6, d7
+ 8027a8e:	ed97 6b06 	vldr	d6, [r7, #24]
+ 8027a92:	ee36 7b47 	vsub.f64	d7, d6, d7
+ 8027a96:	ed87 7b1a 	vstr	d7, [r7, #104]	@ 0x68
+ 8027a9a:	e033      	b.n	8027b04 <GF_MSP_PID_Now_Der_adj_Com_Horizon+0x288>
+	}
+	else
+	{
+		LeftSpeed_Con_1 = (Auto_Speed + Kp4 * Incre_Speed[0]);
+ 8027a9c:	ed97 6b0c 	vldr	d6, [r7, #48]	@ 0x30
+ 8027aa0:	4b5c      	ldr	r3, [pc, #368]	@ (8027c14 <GF_MSP_PID_Now_Der_adj_Com_Horizon+0x398>)
+ 8027aa2:	ed93 7b00 	vldr	d7, [r3]
+ 8027aa6:	ee26 7b07 	vmul.f64	d7, d6, d7
+ 8027aaa:	ed97 6b06 	vldr	d6, [r7, #24]
+ 8027aae:	ee36 7b07 	vadd.f64	d7, d6, d7
+ 8027ab2:	ed87 7b20 	vstr	d7, [r7, #128]	@ 0x80
+		RightSpeed_Con_1 = (Auto_Speed - Kp4 * Incre_Speed[0]);
+ 8027ab6:	ed97 6b0c 	vldr	d6, [r7, #48]	@ 0x30
+ 8027aba:	4b56      	ldr	r3, [pc, #344]	@ (8027c14 <GF_MSP_PID_Now_Der_adj_Com_Horizon+0x398>)
+ 8027abc:	ed93 7b00 	vldr	d7, [r3]
+ 8027ac0:	ee26 7b07 	vmul.f64	d7, d6, d7
+ 8027ac4:	ed97 6b06 	vldr	d6, [r7, #24]
+ 8027ac8:	ee36 7b47 	vsub.f64	d7, d6, d7
+ 8027acc:	ed87 7b1e 	vstr	d7, [r7, #120]	@ 0x78
+		LeftSpeed_Con_2 = Auto_Speed + Kp4 * Incre_Speed[0];
+ 8027ad0:	ed97 6b0c 	vldr	d6, [r7, #48]	@ 0x30
+ 8027ad4:	4b4f      	ldr	r3, [pc, #316]	@ (8027c14 <GF_MSP_PID_Now_Der_adj_Com_Horizon+0x398>)
+ 8027ad6:	ed93 7b00 	vldr	d7, [r3]
+ 8027ada:	ee26 7b07 	vmul.f64	d7, d6, d7
+ 8027ade:	ed97 6b06 	vldr	d6, [r7, #24]
+ 8027ae2:	ee36 7b07 	vadd.f64	d7, d6, d7
+ 8027ae6:	ed87 7b1c 	vstr	d7, [r7, #112]	@ 0x70
+		RightSpeed_Con_2 = Auto_Speed - Kp4 * Incre_Speed[0];
+ 8027aea:	ed97 6b0c 	vldr	d6, [r7, #48]	@ 0x30
+ 8027aee:	4b49      	ldr	r3, [pc, #292]	@ (8027c14 <GF_MSP_PID_Now_Der_adj_Com_Horizon+0x398>)
+ 8027af0:	ed93 7b00 	vldr	d7, [r3]
+ 8027af4:	ee26 7b07 	vmul.f64	d7, d6, d7
+ 8027af8:	ed97 6b06 	vldr	d6, [r7, #24]
+ 8027afc:	ee36 7b47 	vsub.f64	d7, d6, d7
+ 8027b00:	ed87 7b1a 	vstr	d7, [r7, #104]	@ 0x68
+	}
+
+	double Jud_value = fabs(LeftSpeed_Con_1) - fabs(RightSpeed_Con_1);
+ 8027b04:	ed97 7b20 	vldr	d7, [r7, #128]	@ 0x80
+ 8027b08:	eeb0 6bc7 	vabs.f64	d6, d7
+ 8027b0c:	ed97 7b1e 	vldr	d7, [r7, #120]	@ 0x78
+ 8027b10:	eeb0 7bc7 	vabs.f64	d7, d7
+ 8027b14:	ee36 7b47 	vsub.f64	d7, d6, d7
+ 8027b18:	ed87 7b10 	vstr	d7, [r7, #64]	@ 0x40
+	double factor = 0;
+ 8027b1c:	f04f 0200 	mov.w	r2, #0
+ 8027b20:	f04f 0300 	mov.w	r3, #0
+ 8027b24:	e9c7 230e 	strd	r2, r3, [r7, #56]	@ 0x38
+	if (Jud_value >= 0)
+ 8027b28:	ed97 7b10 	vldr	d7, [r7, #64]	@ 0x40
+ 8027b2c:	eeb5 7bc0 	vcmpe.f64	d7, #0.0
+ 8027b30:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 8027b34:	db70      	blt.n	8027c18 <GF_MSP_PID_Now_Der_adj_Com_Horizon+0x39c>
+	{
+		if (LeftSpeed_Con_1 > Auto_Speed_Max)
+ 8027b36:	ed97 6b20 	vldr	d6, [r7, #128]	@ 0x80
+ 8027b3a:	ed97 7b04 	vldr	d7, [r7, #16]
+ 8027b3e:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 8027b42:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 8027b46:	dd24      	ble.n	8027b92 <GF_MSP_PID_Now_Der_adj_Com_Horizon+0x316>
+		{
+			factor = Auto_Speed_Max / LeftSpeed_Con_1;
+ 8027b48:	ed97 5b04 	vldr	d5, [r7, #16]
+ 8027b4c:	ed97 6b20 	vldr	d6, [r7, #128]	@ 0x80
+ 8027b50:	ee85 7b06 	vdiv.f64	d7, d5, d6
+ 8027b54:	ed87 7b0e 	vstr	d7, [r7, #56]	@ 0x38
+			LeftSpeed_Con_1 = Auto_Speed_Max;
+ 8027b58:	e9d7 2304 	ldrd	r2, r3, [r7, #16]
+ 8027b5c:	e9c7 2320 	strd	r2, r3, [r7, #128]	@ 0x80
+			LeftSpeed_Con_2 = LeftSpeed_Con_2 * factor;
+ 8027b60:	ed97 6b1c 	vldr	d6, [r7, #112]	@ 0x70
+ 8027b64:	ed97 7b0e 	vldr	d7, [r7, #56]	@ 0x38
+ 8027b68:	ee26 7b07 	vmul.f64	d7, d6, d7
+ 8027b6c:	ed87 7b1c 	vstr	d7, [r7, #112]	@ 0x70
+			RightSpeed_Con_1 = RightSpeed_Con_1 * factor;
+ 8027b70:	ed97 6b1e 	vldr	d6, [r7, #120]	@ 0x78
+ 8027b74:	ed97 7b0e 	vldr	d7, [r7, #56]	@ 0x38
+ 8027b78:	ee26 7b07 	vmul.f64	d7, d6, d7
+ 8027b7c:	ed87 7b1e 	vstr	d7, [r7, #120]	@ 0x78
+			RightSpeed_Con_2 = RightSpeed_Con_2 * factor;
+ 8027b80:	ed97 6b1a 	vldr	d6, [r7, #104]	@ 0x68
+ 8027b84:	ed97 7b0e 	vldr	d7, [r7, #56]	@ 0x38
+ 8027b88:	ee26 7b07 	vmul.f64	d7, d6, d7
+ 8027b8c:	ed87 7b1a 	vstr	d7, [r7, #104]	@ 0x68
+ 8027b90:	e0a3      	b.n	8027cda <GF_MSP_PID_Now_Der_adj_Com_Horizon+0x45e>
+		}
+		else if (LeftSpeed_Con_1 < -Auto_Speed_Max)
+ 8027b92:	ed97 7b04 	vldr	d7, [r7, #16]
+ 8027b96:	eeb1 7b47 	vneg.f64	d7, d7
+ 8027b9a:	ed97 6b20 	vldr	d6, [r7, #128]	@ 0x80
+ 8027b9e:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 8027ba2:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 8027ba6:	f140 8098 	bpl.w	8027cda <GF_MSP_PID_Now_Der_adj_Com_Horizon+0x45e>
+		{
+			factor = -Auto_Speed_Max / LeftSpeed_Con_1;
+ 8027baa:	ed97 7b04 	vldr	d7, [r7, #16]
+ 8027bae:	eeb1 5b47 	vneg.f64	d5, d7
+ 8027bb2:	ed97 6b20 	vldr	d6, [r7, #128]	@ 0x80
+ 8027bb6:	ee85 7b06 	vdiv.f64	d7, d5, d6
+ 8027bba:	ed87 7b0e 	vstr	d7, [r7, #56]	@ 0x38
+			LeftSpeed_Con_1 = -Auto_Speed_Max;
+ 8027bbe:	ed97 7b04 	vldr	d7, [r7, #16]
+ 8027bc2:	eeb1 7b47 	vneg.f64	d7, d7
+ 8027bc6:	ed87 7b20 	vstr	d7, [r7, #128]	@ 0x80
+			LeftSpeed_Con_2 = LeftSpeed_Con_2 * factor;
+ 8027bca:	ed97 6b1c 	vldr	d6, [r7, #112]	@ 0x70
+ 8027bce:	ed97 7b0e 	vldr	d7, [r7, #56]	@ 0x38
+ 8027bd2:	ee26 7b07 	vmul.f64	d7, d6, d7
+ 8027bd6:	ed87 7b1c 	vstr	d7, [r7, #112]	@ 0x70
+			RightSpeed_Con_1 = RightSpeed_Con_1 * factor;
+ 8027bda:	ed97 6b1e 	vldr	d6, [r7, #120]	@ 0x78
+ 8027bde:	ed97 7b0e 	vldr	d7, [r7, #56]	@ 0x38
+ 8027be2:	ee26 7b07 	vmul.f64	d7, d6, d7
+ 8027be6:	ed87 7b1e 	vstr	d7, [r7, #120]	@ 0x78
+			RightSpeed_Con_2 = RightSpeed_Con_2 * factor;
+ 8027bea:	ed97 6b1a 	vldr	d6, [r7, #104]	@ 0x68
+ 8027bee:	ed97 7b0e 	vldr	d7, [r7, #56]	@ 0x38
+ 8027bf2:	ee26 7b07 	vmul.f64	d7, d6, d7
+ 8027bf6:	ed87 7b1a 	vstr	d7, [r7, #104]	@ 0x68
+ 8027bfa:	e06e      	b.n	8027cda <GF_MSP_PID_Now_Der_adj_Com_Horizon+0x45e>
+ 8027bfc:	2400a400 	.word	0x2400a400
+ 8027c00:	40140000 	.word	0x40140000
+ 8027c04:	40240000 	.word	0x40240000
+ 8027c08:	24000068 	.word	0x24000068
+ 8027c0c:	24000070 	.word	0x24000070
+ 8027c10:	24000078 	.word	0x24000078
+ 8027c14:	24000080 	.word	0x24000080
+		}
+	}
+	else
+	{
+		if (RightSpeed_Con_1 > Auto_Speed_Max)
+ 8027c18:	ed97 6b1e 	vldr	d6, [r7, #120]	@ 0x78
+ 8027c1c:	ed97 7b04 	vldr	d7, [r7, #16]
+ 8027c20:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 8027c24:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 8027c28:	dd24      	ble.n	8027c74 <GF_MSP_PID_Now_Der_adj_Com_Horizon+0x3f8>
+		{
+			factor = Auto_Speed_Max / RightSpeed_Con_1;
+ 8027c2a:	ed97 5b04 	vldr	d5, [r7, #16]
+ 8027c2e:	ed97 6b1e 	vldr	d6, [r7, #120]	@ 0x78
+ 8027c32:	ee85 7b06 	vdiv.f64	d7, d5, d6
+ 8027c36:	ed87 7b0e 	vstr	d7, [r7, #56]	@ 0x38
+			RightSpeed_Con_1 = Auto_Speed_Max;
+ 8027c3a:	e9d7 2304 	ldrd	r2, r3, [r7, #16]
+ 8027c3e:	e9c7 231e 	strd	r2, r3, [r7, #120]	@ 0x78
+			RightSpeed_Con_2 = RightSpeed_Con_2 * factor;
+ 8027c42:	ed97 6b1a 	vldr	d6, [r7, #104]	@ 0x68
+ 8027c46:	ed97 7b0e 	vldr	d7, [r7, #56]	@ 0x38
+ 8027c4a:	ee26 7b07 	vmul.f64	d7, d6, d7
+ 8027c4e:	ed87 7b1a 	vstr	d7, [r7, #104]	@ 0x68
+
+			LeftSpeed_Con_1 = LeftSpeed_Con_1 * factor;
+ 8027c52:	ed97 6b20 	vldr	d6, [r7, #128]	@ 0x80
+ 8027c56:	ed97 7b0e 	vldr	d7, [r7, #56]	@ 0x38
+ 8027c5a:	ee26 7b07 	vmul.f64	d7, d6, d7
+ 8027c5e:	ed87 7b20 	vstr	d7, [r7, #128]	@ 0x80
+			LeftSpeed_Con_2 = LeftSpeed_Con_2 * factor;
+ 8027c62:	ed97 6b1c 	vldr	d6, [r7, #112]	@ 0x70
+ 8027c66:	ed97 7b0e 	vldr	d7, [r7, #56]	@ 0x38
+ 8027c6a:	ee26 7b07 	vmul.f64	d7, d6, d7
+ 8027c6e:	ed87 7b1c 	vstr	d7, [r7, #112]	@ 0x70
+ 8027c72:	e032      	b.n	8027cda <GF_MSP_PID_Now_Der_adj_Com_Horizon+0x45e>
+		}
+		else if (LeftSpeed_Con_2 < -Auto_Speed_Max)
+ 8027c74:	ed97 7b04 	vldr	d7, [r7, #16]
+ 8027c78:	eeb1 7b47 	vneg.f64	d7, d7
+ 8027c7c:	ed97 6b1c 	vldr	d6, [r7, #112]	@ 0x70
+ 8027c80:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 8027c84:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 8027c88:	d527      	bpl.n	8027cda <GF_MSP_PID_Now_Der_adj_Com_Horizon+0x45e>
+		{
+			factor = -Auto_Speed_Max / RightSpeed_Con_1;
+ 8027c8a:	ed97 7b04 	vldr	d7, [r7, #16]
+ 8027c8e:	eeb1 5b47 	vneg.f64	d5, d7
+ 8027c92:	ed97 6b1e 	vldr	d6, [r7, #120]	@ 0x78
+ 8027c96:	ee85 7b06 	vdiv.f64	d7, d5, d6
+ 8027c9a:	ed87 7b0e 	vstr	d7, [r7, #56]	@ 0x38
+			RightSpeed_Con_1 = -Auto_Speed_Max;
+ 8027c9e:	ed97 7b04 	vldr	d7, [r7, #16]
+ 8027ca2:	eeb1 7b47 	vneg.f64	d7, d7
+ 8027ca6:	ed87 7b1e 	vstr	d7, [r7, #120]	@ 0x78
+			RightSpeed_Con_2 = RightSpeed_Con_2 * factor;
+ 8027caa:	ed97 6b1a 	vldr	d6, [r7, #104]	@ 0x68
+ 8027cae:	ed97 7b0e 	vldr	d7, [r7, #56]	@ 0x38
+ 8027cb2:	ee26 7b07 	vmul.f64	d7, d6, d7
+ 8027cb6:	ed87 7b1a 	vstr	d7, [r7, #104]	@ 0x68
+
+			LeftSpeed_Con_1 = LeftSpeed_Con_1 * factor;
+ 8027cba:	ed97 6b20 	vldr	d6, [r7, #128]	@ 0x80
+ 8027cbe:	ed97 7b0e 	vldr	d7, [r7, #56]	@ 0x38
+ 8027cc2:	ee26 7b07 	vmul.f64	d7, d6, d7
+ 8027cc6:	ed87 7b20 	vstr	d7, [r7, #128]	@ 0x80
+			LeftSpeed_Con_2 = LeftSpeed_Con_2 * factor;
+ 8027cca:	ed97 6b1c 	vldr	d6, [r7, #112]	@ 0x70
+ 8027cce:	ed97 7b0e 	vldr	d7, [r7, #56]	@ 0x38
+ 8027cd2:	ee26 7b07 	vmul.f64	d7, d6, d7
+ 8027cd6:	ed87 7b1c 	vstr	d7, [r7, #112]	@ 0x70
+		}
+	}
+
+	W_Speed_1[0] = LeftSpeed_Con_1;
+ 8027cda:	6879      	ldr	r1, [r7, #4]
+ 8027cdc:	e9d7 2320 	ldrd	r2, r3, [r7, #128]	@ 0x80
+ 8027ce0:	e9c1 2300 	strd	r2, r3, [r1]
+	W_Speed_1[1] = RightSpeed_Con_1;
+ 8027ce4:	687b      	ldr	r3, [r7, #4]
+ 8027ce6:	f103 0108 	add.w	r1, r3, #8
+ 8027cea:	e9d7 231e 	ldrd	r2, r3, [r7, #120]	@ 0x78
+ 8027cee:	e9c1 2300 	strd	r2, r3, [r1]
+	W_Speed_1[2] = LeftSpeed_Con_2;
+ 8027cf2:	687b      	ldr	r3, [r7, #4]
+ 8027cf4:	f103 0110 	add.w	r1, r3, #16
+ 8027cf8:	e9d7 231c 	ldrd	r2, r3, [r7, #112]	@ 0x70
+ 8027cfc:	e9c1 2300 	strd	r2, r3, [r1]
+	W_Speed_1[3] = RightSpeed_Con_2;
+ 8027d00:	687b      	ldr	r3, [r7, #4]
+ 8027d02:	f103 0118 	add.w	r1, r3, #24
+ 8027d06:	e9d7 231a 	ldrd	r2, r3, [r7, #104]	@ 0x68
+ 8027d0a:	e9c1 2300 	strd	r2, r3, [r1]
+
+}
+ 8027d0e:	bf00      	nop
+ 8027d10:	3788      	adds	r7, #136	@ 0x88
+ 8027d12:	46bd      	mov	sp, r7
+ 8027d14:	bd80      	pop	{r7, pc}
+ 8027d16:	bf00      	nop
+
+08027d18 <TL720D_intialize>:
+
+void decode_TL720D(uint8_t *buffer, uint16_t length);
+int16_t getDeci(uint8_t *data);
+
+void TL720D_intialize(struct UARTHandler *Handler)
+{
+ 8027d18:	b590      	push	{r4, r7, lr}
+ 8027d1a:	b087      	sub	sp, #28
+ 8027d1c:	af04      	add	r7, sp, #16
+ 8027d1e:	6078      	str	r0, [r7, #4]
+
+	//TL720D_UART_Handler->UART_Decode = NULL;
+	TL720D_UART_Handler = Handler;
+ 8027d20:	4a22      	ldr	r2, [pc, #136]	@ (8027dac <TL720D_intialize+0x94>)
+ 8027d22:	687b      	ldr	r3, [r7, #4]
+ 8027d24:	6013      	str	r3, [r2, #0]
+	TL720D_UART_Handler->Wait_time=6;
+ 8027d26:	4b21      	ldr	r3, [pc, #132]	@ (8027dac <TL720D_intialize+0x94>)
+ 8027d28:	681b      	ldr	r3, [r3, #0]
+ 8027d2a:	2206      	movs	r2, #6
+ 8027d2c:	609a      	str	r2, [r3, #8]
+	TL720D_UART_Handler->dispacherController->Dispacher_Enable=0;//不周期性发送
+ 8027d2e:	4b1f      	ldr	r3, [pc, #124]	@ (8027dac <TL720D_intialize+0x94>)
+ 8027d30:	681b      	ldr	r3, [r3, #0]
+ 8027d32:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8027d36:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 8027d38:	2200      	movs	r2, #0
+ 8027d3a:	81da      	strh	r2, [r3, #14]
+	TL720D_UART_Handler->UART_Decode = decode_TL720D;
+ 8027d3c:	4b1b      	ldr	r3, [pc, #108]	@ (8027dac <TL720D_intialize+0x94>)
+ 8027d3e:	681b      	ldr	r3, [r3, #0]
+ 8027d40:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8027d44:	461a      	mov	r2, r3
+ 8027d46:	4b1a      	ldr	r3, [pc, #104]	@ (8027db0 <TL720D_intialize+0x98>)
+ 8027d48:	6313      	str	r3, [r2, #48]	@ 0x30
+	HardWareErrorController->Add_PCOMHardWare(HardWareErrorController,"TL720D",0,ComError_TL720D);
+ 8027d4a:	4b1a      	ldr	r3, [pc, #104]	@ (8027db4 <TL720D_intialize+0x9c>)
+ 8027d4c:	681b      	ldr	r3, [r3, #0]
+ 8027d4e:	68dc      	ldr	r4, [r3, #12]
+ 8027d50:	4b18      	ldr	r3, [pc, #96]	@ (8027db4 <TL720D_intialize+0x9c>)
+ 8027d52:	6818      	ldr	r0, [r3, #0]
+ 8027d54:	2303      	movs	r3, #3
+ 8027d56:	2200      	movs	r2, #0
+ 8027d58:	4917      	ldr	r1, [pc, #92]	@ (8027db8 <TL720D_intialize+0xa0>)
+ 8027d5a:	47a0      	blx	r4
+	//log_info("TL720D_intialize");
+	LOGFF(DL_ERROR,"TL720D_intialize");
+ 8027d5c:	4b17      	ldr	r3, [pc, #92]	@ (8027dbc <TL720D_intialize+0xa4>)
+ 8027d5e:	781b      	ldrb	r3, [r3, #0]
+ 8027d60:	2b01      	cmp	r3, #1
+ 8027d62:	d91e      	bls.n	8027da2 <TL720D_intialize+0x8a>
+ 8027d64:	2330      	movs	r3, #48	@ 0x30
+ 8027d66:	061a      	lsls	r2, r3, #24
+ 8027d68:	2330      	movs	r3, #48	@ 0x30
+ 8027d6a:	041b      	lsls	r3, r3, #16
+ 8027d6c:	431a      	orrs	r2, r3
+ 8027d6e:	2330      	movs	r3, #48	@ 0x30
+ 8027d70:	021b      	lsls	r3, r3, #8
+ 8027d72:	4313      	orrs	r3, r2
+ 8027d74:	2230      	movs	r2, #48	@ 0x30
+ 8027d76:	ea43 0102 	orr.w	r1, r3, r2
+ 8027d7a:	2344      	movs	r3, #68	@ 0x44
+ 8027d7c:	061a      	lsls	r2, r3, #24
+ 8027d7e:	2346      	movs	r3, #70	@ 0x46
+ 8027d80:	041b      	lsls	r3, r3, #16
+ 8027d82:	431a      	orrs	r2, r3
+ 8027d84:	234c      	movs	r3, #76	@ 0x4c
+ 8027d86:	021b      	lsls	r3, r3, #8
+ 8027d88:	4313      	orrs	r3, r2
+ 8027d8a:	2254      	movs	r2, #84	@ 0x54
+ 8027d8c:	431a      	orrs	r2, r3
+ 8027d8e:	4b0c      	ldr	r3, [pc, #48]	@ (8027dc0 <TL720D_intialize+0xa8>)
+ 8027d90:	9302      	str	r3, [sp, #8]
+ 8027d92:	2322      	movs	r3, #34	@ 0x22
+ 8027d94:	9301      	str	r3, [sp, #4]
+ 8027d96:	4b0b      	ldr	r3, [pc, #44]	@ (8027dc4 <TL720D_intialize+0xac>)
+ 8027d98:	9300      	str	r3, [sp, #0]
+ 8027d9a:	4b0b      	ldr	r3, [pc, #44]	@ (8027dc8 <TL720D_intialize+0xb0>)
+ 8027d9c:	2002      	movs	r0, #2
+ 8027d9e:	f7fe fa49 	bl	8026234 <DLTuc_LogOutVarArgs>
+}
+ 8027da2:	bf00      	nop
+ 8027da4:	370c      	adds	r7, #12
+ 8027da6:	46bd      	mov	sp, r7
+ 8027da8:	bd90      	pop	{r4, r7, pc}
+ 8027daa:	bf00      	nop
+ 8027dac:	2400a414 	.word	0x2400a414
+ 8027db0:	08027dcd 	.word	0x08027dcd
+ 8027db4:	24000618 	.word	0x24000618
+ 8027db8:	080413ec 	.word	0x080413ec
+ 8027dbc:	24009110 	.word	0x24009110
+ 8027dc0:	08041c24 	.word	0x08041c24
+ 8027dc4:	08041424 	.word	0x08041424
+ 8027dc8:	080413f4 	.word	0x080413f4
+
+08027dcc <decode_TL720D>:
+void decode_TL720D(uint8_t *buffer, uint16_t length)
+{
+ 8027dcc:	b580      	push	{r7, lr}
+ 8027dce:	b086      	sub	sp, #24
+ 8027dd0:	af04      	add	r7, sp, #16
+ 8027dd2:	6078      	str	r0, [r7, #4]
+ 8027dd4:	460b      	mov	r3, r1
+ 8027dd6:	807b      	strh	r3, [r7, #2]
+
+	if (buffer[0] == 0x68 && buffer[1] == 0x1F && buffer[2] == 0x00
+ 8027dd8:	687b      	ldr	r3, [r7, #4]
+ 8027dda:	781b      	ldrb	r3, [r3, #0]
+ 8027ddc:	2b68      	cmp	r3, #104	@ 0x68
+ 8027dde:	f040 8098 	bne.w	8027f12 <decode_TL720D+0x146>
+ 8027de2:	687b      	ldr	r3, [r7, #4]
+ 8027de4:	3301      	adds	r3, #1
+ 8027de6:	781b      	ldrb	r3, [r3, #0]
+ 8027de8:	2b1f      	cmp	r3, #31
+ 8027dea:	f040 8092 	bne.w	8027f12 <decode_TL720D+0x146>
+ 8027dee:	687b      	ldr	r3, [r7, #4]
+ 8027df0:	3302      	adds	r3, #2
+ 8027df2:	781b      	ldrb	r3, [r3, #0]
+ 8027df4:	2b00      	cmp	r3, #0
+ 8027df6:	f040 808c 	bne.w	8027f12 <decode_TL720D+0x146>
+			&& buffer[3] == 0x84)
+ 8027dfa:	687b      	ldr	r3, [r7, #4]
+ 8027dfc:	3303      	adds	r3, #3
+ 8027dfe:	781b      	ldrb	r3, [r3, #0]
+ 8027e00:	2b84      	cmp	r3, #132	@ 0x84
+ 8027e02:	f040 8086 	bne.w	8027f12 <decode_TL720D+0x146>
+	{
+		//SP_MSP_RF_TL720D_Parameters_In.
+		SP_MSP_RF_TL720D_Parameters_In->RF_Angle_Roll = getDeci(&buffer[4]);
+ 8027e06:	687b      	ldr	r3, [r7, #4]
+ 8027e08:	3304      	adds	r3, #4
+ 8027e0a:	4618      	mov	r0, r3
+ 8027e0c:	f000 f8ba 	bl	8027f84 <getDeci>
+ 8027e10:	4603      	mov	r3, r0
+ 8027e12:	461a      	mov	r2, r3
+ 8027e14:	4b52      	ldr	r3, [pc, #328]	@ (8027f60 <decode_TL720D+0x194>)
+ 8027e16:	681b      	ldr	r3, [r3, #0]
+ 8027e18:	601a      	str	r2, [r3, #0]
+		SP_MSP_RF_TL720D_Parameters_In->RF_Angle_Pitch = getDeci(&buffer[7]);
+ 8027e1a:	687b      	ldr	r3, [r7, #4]
+ 8027e1c:	3307      	adds	r3, #7
+ 8027e1e:	4618      	mov	r0, r3
+ 8027e20:	f000 f8b0 	bl	8027f84 <getDeci>
+ 8027e24:	4603      	mov	r3, r0
+ 8027e26:	461a      	mov	r2, r3
+ 8027e28:	4b4d      	ldr	r3, [pc, #308]	@ (8027f60 <decode_TL720D+0x194>)
+ 8027e2a:	681b      	ldr	r3, [r3, #0]
+ 8027e2c:	605a      	str	r2, [r3, #4]
+		SP_MSP_RF_TL720D_Parameters_In->RF_Angle_Yaw = getDeci(&buffer[10]);
+ 8027e2e:	687b      	ldr	r3, [r7, #4]
+ 8027e30:	330a      	adds	r3, #10
+ 8027e32:	4618      	mov	r0, r3
+ 8027e34:	f000 f8a6 	bl	8027f84 <getDeci>
+ 8027e38:	4603      	mov	r3, r0
+ 8027e3a:	461a      	mov	r2, r3
+ 8027e3c:	4b48      	ldr	r3, [pc, #288]	@ (8027f60 <decode_TL720D+0x194>)
+ 8027e3e:	681b      	ldr	r3, [r3, #0]
+ 8027e40:	609a      	str	r2, [r3, #8]
+		SP_MSP_RF_TL720D_Parameters_In->RF_Acc_X = getDeci(&buffer[13]);
+ 8027e42:	687b      	ldr	r3, [r7, #4]
+ 8027e44:	330d      	adds	r3, #13
+ 8027e46:	4618      	mov	r0, r3
+ 8027e48:	f000 f89c 	bl	8027f84 <getDeci>
+ 8027e4c:	4603      	mov	r3, r0
+ 8027e4e:	461a      	mov	r2, r3
+ 8027e50:	4b43      	ldr	r3, [pc, #268]	@ (8027f60 <decode_TL720D+0x194>)
+ 8027e52:	681b      	ldr	r3, [r3, #0]
+ 8027e54:	60da      	str	r2, [r3, #12]
+		SP_MSP_RF_TL720D_Parameters_In->RF_Acc_Y = getDeci(&buffer[16]);
+ 8027e56:	687b      	ldr	r3, [r7, #4]
+ 8027e58:	3310      	adds	r3, #16
+ 8027e5a:	4618      	mov	r0, r3
+ 8027e5c:	f000 f892 	bl	8027f84 <getDeci>
+ 8027e60:	4603      	mov	r3, r0
+ 8027e62:	461a      	mov	r2, r3
+ 8027e64:	4b3e      	ldr	r3, [pc, #248]	@ (8027f60 <decode_TL720D+0x194>)
+ 8027e66:	681b      	ldr	r3, [r3, #0]
+ 8027e68:	611a      	str	r2, [r3, #16]
+		SP_MSP_RF_TL720D_Parameters_In->RF_Acc_Z = getDeci(&buffer[19]);
+ 8027e6a:	687b      	ldr	r3, [r7, #4]
+ 8027e6c:	3313      	adds	r3, #19
+ 8027e6e:	4618      	mov	r0, r3
+ 8027e70:	f000 f888 	bl	8027f84 <getDeci>
+ 8027e74:	4603      	mov	r3, r0
+ 8027e76:	461a      	mov	r2, r3
+ 8027e78:	4b39      	ldr	r3, [pc, #228]	@ (8027f60 <decode_TL720D+0x194>)
+ 8027e7a:	681b      	ldr	r3, [r3, #0]
+ 8027e7c:	615a      	str	r2, [r3, #20]
+		SP_MSP_RF_TL720D_Parameters_In->RF_Gro_X = getDeci(&buffer[22]);
+ 8027e7e:	687b      	ldr	r3, [r7, #4]
+ 8027e80:	3316      	adds	r3, #22
+ 8027e82:	4618      	mov	r0, r3
+ 8027e84:	f000 f87e 	bl	8027f84 <getDeci>
+ 8027e88:	4603      	mov	r3, r0
+ 8027e8a:	461a      	mov	r2, r3
+ 8027e8c:	4b34      	ldr	r3, [pc, #208]	@ (8027f60 <decode_TL720D+0x194>)
+ 8027e8e:	681b      	ldr	r3, [r3, #0]
+ 8027e90:	619a      	str	r2, [r3, #24]
+		SP_MSP_RF_TL720D_Parameters_In->RF_Gro_Y = getDeci(&buffer[25]);
+ 8027e92:	687b      	ldr	r3, [r7, #4]
+ 8027e94:	3319      	adds	r3, #25
+ 8027e96:	4618      	mov	r0, r3
+ 8027e98:	f000 f874 	bl	8027f84 <getDeci>
+ 8027e9c:	4603      	mov	r3, r0
+ 8027e9e:	461a      	mov	r2, r3
+ 8027ea0:	4b2f      	ldr	r3, [pc, #188]	@ (8027f60 <decode_TL720D+0x194>)
+ 8027ea2:	681b      	ldr	r3, [r3, #0]
+ 8027ea4:	61da      	str	r2, [r3, #28]
+		SP_MSP_RF_TL720D_Parameters_In->RF_Gro_Z = getDeci(&buffer[28]);
+ 8027ea6:	687b      	ldr	r3, [r7, #4]
+ 8027ea8:	331c      	adds	r3, #28
+ 8027eaa:	4618      	mov	r0, r3
+ 8027eac:	f000 f86a 	bl	8027f84 <getDeci>
+ 8027eb0:	4603      	mov	r3, r0
+ 8027eb2:	461a      	mov	r2, r3
+ 8027eb4:	4b2a      	ldr	r3, [pc, #168]	@ (8027f60 <decode_TL720D+0x194>)
+ 8027eb6:	681b      	ldr	r3, [r3, #0]
+ 8027eb8:	621a      	str	r2, [r3, #32]
+		LOG("TL720D decoding  succeeded");
+ 8027eba:	4b2a      	ldr	r3, [pc, #168]	@ (8027f64 <decode_TL720D+0x198>)
+ 8027ebc:	781b      	ldrb	r3, [r3, #0]
+ 8027ebe:	2b03      	cmp	r3, #3
+ 8027ec0:	d918      	bls.n	8027ef4 <decode_TL720D+0x128>
+ 8027ec2:	2330      	movs	r3, #48	@ 0x30
+ 8027ec4:	061a      	lsls	r2, r3, #24
+ 8027ec6:	2330      	movs	r3, #48	@ 0x30
+ 8027ec8:	041b      	lsls	r3, r3, #16
+ 8027eca:	431a      	orrs	r2, r3
+ 8027ecc:	2330      	movs	r3, #48	@ 0x30
+ 8027ece:	021b      	lsls	r3, r3, #8
+ 8027ed0:	4313      	orrs	r3, r2
+ 8027ed2:	2230      	movs	r2, #48	@ 0x30
+ 8027ed4:	ea43 0102 	orr.w	r1, r3, r2
+ 8027ed8:	2344      	movs	r3, #68	@ 0x44
+ 8027eda:	061a      	lsls	r2, r3, #24
+ 8027edc:	2346      	movs	r3, #70	@ 0x46
+ 8027ede:	041b      	lsls	r3, r3, #16
+ 8027ee0:	431a      	orrs	r2, r3
+ 8027ee2:	234c      	movs	r3, #76	@ 0x4c
+ 8027ee4:	021b      	lsls	r3, r3, #8
+ 8027ee6:	4313      	orrs	r3, r2
+ 8027ee8:	2254      	movs	r2, #84	@ 0x54
+ 8027eea:	431a      	orrs	r2, r3
+ 8027eec:	4b1e      	ldr	r3, [pc, #120]	@ (8027f68 <decode_TL720D+0x19c>)
+ 8027eee:	2004      	movs	r0, #4
+ 8027ef0:	f7fe f9a0 	bl	8026234 <DLTuc_LogOutVarArgs>
+
+		*RobotAngle=SP_MSP_RF_TL720D_Parameters_In->RF_Angle_Roll;
+ 8027ef4:	4b1a      	ldr	r3, [pc, #104]	@ (8027f60 <decode_TL720D+0x194>)
+ 8027ef6:	681a      	ldr	r2, [r3, #0]
+ 8027ef8:	4b1c      	ldr	r3, [pc, #112]	@ (8027f6c <decode_TL720D+0x1a0>)
+ 8027efa:	681b      	ldr	r3, [r3, #0]
+ 8027efc:	6812      	ldr	r2, [r2, #0]
+ 8027efe:	601a      	str	r2, [r3, #0]
+		//Is_TL720_Updating_Flag=true;
+		 HardWareErrorController->Set_PCOMHardWare(HardWareErrorController,"TL720D",1);
+ 8027f00:	4b1b      	ldr	r3, [pc, #108]	@ (8027f70 <decode_TL720D+0x1a4>)
+ 8027f02:	681b      	ldr	r3, [r3, #0]
+ 8027f04:	695b      	ldr	r3, [r3, #20]
+ 8027f06:	4a1a      	ldr	r2, [pc, #104]	@ (8027f70 <decode_TL720D+0x1a4>)
+ 8027f08:	6810      	ldr	r0, [r2, #0]
+ 8027f0a:	2201      	movs	r2, #1
+ 8027f0c:	4919      	ldr	r1, [pc, #100]	@ (8027f74 <decode_TL720D+0x1a8>)
+ 8027f0e:	4798      	blx	r3
+		//log_error("TL720D decoding failed");
+		LOGFF(DL_ERROR,"TL720D decoding failed");
+
+	}
+
+}
+ 8027f10:	e022      	b.n	8027f58 <decode_TL720D+0x18c>
+		LOGFF(DL_ERROR,"TL720D decoding failed");
+ 8027f12:	4b14      	ldr	r3, [pc, #80]	@ (8027f64 <decode_TL720D+0x198>)
+ 8027f14:	781b      	ldrb	r3, [r3, #0]
+ 8027f16:	2b01      	cmp	r3, #1
+ 8027f18:	d91e      	bls.n	8027f58 <decode_TL720D+0x18c>
+ 8027f1a:	2330      	movs	r3, #48	@ 0x30
+ 8027f1c:	061a      	lsls	r2, r3, #24
+ 8027f1e:	2330      	movs	r3, #48	@ 0x30
+ 8027f20:	041b      	lsls	r3, r3, #16
+ 8027f22:	431a      	orrs	r2, r3
+ 8027f24:	2330      	movs	r3, #48	@ 0x30
+ 8027f26:	021b      	lsls	r3, r3, #8
+ 8027f28:	4313      	orrs	r3, r2
+ 8027f2a:	2230      	movs	r2, #48	@ 0x30
+ 8027f2c:	ea43 0102 	orr.w	r1, r3, r2
+ 8027f30:	2344      	movs	r3, #68	@ 0x44
+ 8027f32:	061a      	lsls	r2, r3, #24
+ 8027f34:	2346      	movs	r3, #70	@ 0x46
+ 8027f36:	041b      	lsls	r3, r3, #16
+ 8027f38:	431a      	orrs	r2, r3
+ 8027f3a:	234c      	movs	r3, #76	@ 0x4c
+ 8027f3c:	021b      	lsls	r3, r3, #8
+ 8027f3e:	4313      	orrs	r3, r2
+ 8027f40:	2254      	movs	r2, #84	@ 0x54
+ 8027f42:	431a      	orrs	r2, r3
+ 8027f44:	4b0c      	ldr	r3, [pc, #48]	@ (8027f78 <decode_TL720D+0x1ac>)
+ 8027f46:	9302      	str	r3, [sp, #8]
+ 8027f48:	233c      	movs	r3, #60	@ 0x3c
+ 8027f4a:	9301      	str	r3, [sp, #4]
+ 8027f4c:	4b0b      	ldr	r3, [pc, #44]	@ (8027f7c <decode_TL720D+0x1b0>)
+ 8027f4e:	9300      	str	r3, [sp, #0]
+ 8027f50:	4b0b      	ldr	r3, [pc, #44]	@ (8027f80 <decode_TL720D+0x1b4>)
+ 8027f52:	2002      	movs	r0, #2
+ 8027f54:	f7fe f96e 	bl	8026234 <DLTuc_LogOutVarArgs>
+}
+ 8027f58:	bf00      	nop
+ 8027f5a:	3708      	adds	r7, #8
+ 8027f5c:	46bd      	mov	sp, r7
+ 8027f5e:	bd80      	pop	{r7, pc}
+ 8027f60:	2400a418 	.word	0x2400a418
+ 8027f64:	24009110 	.word	0x24009110
+ 8027f68:	08041448 	.word	0x08041448
+ 8027f6c:	2400a410 	.word	0x2400a410
+ 8027f70:	24000618 	.word	0x24000618
+ 8027f74:	080413ec 	.word	0x080413ec
+ 8027f78:	08041c38 	.word	0x08041c38
+ 8027f7c:	08041424 	.word	0x08041424
+ 8027f80:	08041464 	.word	0x08041464
+
+08027f84 <getDeci>:
+int16_t getDeci(uint8_t *data)
+{
+ 8027f84:	b480      	push	{r7}
+ 8027f86:	b085      	sub	sp, #20
+ 8027f88:	af00      	add	r7, sp, #0
+ 8027f8a:	6078      	str	r0, [r7, #4]
+	char isNegative = 0;
+ 8027f8c:	2300      	movs	r3, #0
+ 8027f8e:	73fb      	strb	r3, [r7, #15]
+
+	if (*data >> 4)
+ 8027f90:	687b      	ldr	r3, [r7, #4]
+ 8027f92:	781b      	ldrb	r3, [r3, #0]
+ 8027f94:	091b      	lsrs	r3, r3, #4
+ 8027f96:	b2db      	uxtb	r3, r3
+ 8027f98:	2b00      	cmp	r3, #0
+ 8027f9a:	d002      	beq.n	8027fa2 <getDeci+0x1e>
+	{
+		isNegative = 1;
+ 8027f9c:	2301      	movs	r3, #1
+ 8027f9e:	73fb      	strb	r3, [r7, #15]
+ 8027fa0:	e001      	b.n	8027fa6 <getDeci+0x22>
+	} else
+	{
+		isNegative = 0;
+ 8027fa2:	2300      	movs	r3, #0
+ 8027fa4:	73fb      	strb	r3, [r7, #15]
+	}
+
+	int16_t data_value = 0;
+ 8027fa6:	2300      	movs	r3, #0
+ 8027fa8:	81bb      	strh	r3, [r7, #12]
+	data_value = ((*data) & 0x0f) * 10000;
+ 8027faa:	687b      	ldr	r3, [r7, #4]
+ 8027fac:	781b      	ldrb	r3, [r3, #0]
+ 8027fae:	f003 030f 	and.w	r3, r3, #15
+ 8027fb2:	b29b      	uxth	r3, r3
+ 8027fb4:	461a      	mov	r2, r3
+ 8027fb6:	0152      	lsls	r2, r2, #5
+ 8027fb8:	1ad2      	subs	r2, r2, r3
+ 8027fba:	0092      	lsls	r2, r2, #2
+ 8027fbc:	4413      	add	r3, r2
+ 8027fbe:	461a      	mov	r2, r3
+ 8027fc0:	0091      	lsls	r1, r2, #2
+ 8027fc2:	461a      	mov	r2, r3
+ 8027fc4:	460b      	mov	r3, r1
+ 8027fc6:	4413      	add	r3, r2
+ 8027fc8:	011b      	lsls	r3, r3, #4
+ 8027fca:	b29b      	uxth	r3, r3
+ 8027fcc:	81bb      	strh	r3, [r7, #12]
+	data++;
+ 8027fce:	687b      	ldr	r3, [r7, #4]
+ 8027fd0:	3301      	adds	r3, #1
+ 8027fd2:	607b      	str	r3, [r7, #4]
+	data_value += (*data >> 4) * 1000;
+ 8027fd4:	687b      	ldr	r3, [r7, #4]
+ 8027fd6:	781b      	ldrb	r3, [r3, #0]
+ 8027fd8:	091b      	lsrs	r3, r3, #4
+ 8027fda:	b2db      	uxtb	r3, r3
+ 8027fdc:	461a      	mov	r2, r3
+ 8027fde:	0152      	lsls	r2, r2, #5
+ 8027fe0:	1ad2      	subs	r2, r2, r3
+ 8027fe2:	0092      	lsls	r2, r2, #2
+ 8027fe4:	4413      	add	r3, r2
+ 8027fe6:	00db      	lsls	r3, r3, #3
+ 8027fe8:	b29a      	uxth	r2, r3
+ 8027fea:	89bb      	ldrh	r3, [r7, #12]
+ 8027fec:	4413      	add	r3, r2
+ 8027fee:	b29b      	uxth	r3, r3
+ 8027ff0:	81bb      	strh	r3, [r7, #12]
+	data_value += ((*data) & 0x0f) * 100;
+ 8027ff2:	687b      	ldr	r3, [r7, #4]
+ 8027ff4:	781b      	ldrb	r3, [r3, #0]
+ 8027ff6:	f003 030f 	and.w	r3, r3, #15
+ 8027ffa:	b29b      	uxth	r3, r3
+ 8027ffc:	461a      	mov	r2, r3
+ 8027ffe:	0092      	lsls	r2, r2, #2
+ 8028000:	4413      	add	r3, r2
+ 8028002:	461a      	mov	r2, r3
+ 8028004:	0091      	lsls	r1, r2, #2
+ 8028006:	461a      	mov	r2, r3
+ 8028008:	460b      	mov	r3, r1
+ 802800a:	4413      	add	r3, r2
+ 802800c:	009b      	lsls	r3, r3, #2
+ 802800e:	b29a      	uxth	r2, r3
+ 8028010:	89bb      	ldrh	r3, [r7, #12]
+ 8028012:	4413      	add	r3, r2
+ 8028014:	b29b      	uxth	r3, r3
+ 8028016:	81bb      	strh	r3, [r7, #12]
+	data++;
+ 8028018:	687b      	ldr	r3, [r7, #4]
+ 802801a:	3301      	adds	r3, #1
+ 802801c:	607b      	str	r3, [r7, #4]
+
+	int16_t xiaoshu = 0;
+ 802801e:	2300      	movs	r3, #0
+ 8028020:	817b      	strh	r3, [r7, #10]
+	xiaoshu = (*data >> 4) * 10;
+ 8028022:	687b      	ldr	r3, [r7, #4]
+ 8028024:	781b      	ldrb	r3, [r3, #0]
+ 8028026:	091b      	lsrs	r3, r3, #4
+ 8028028:	b2db      	uxtb	r3, r3
+ 802802a:	461a      	mov	r2, r3
+ 802802c:	0092      	lsls	r2, r2, #2
+ 802802e:	4413      	add	r3, r2
+ 8028030:	005b      	lsls	r3, r3, #1
+ 8028032:	b29b      	uxth	r3, r3
+ 8028034:	817b      	strh	r3, [r7, #10]
+	xiaoshu += (*data) & 0x0f;
+ 8028036:	687b      	ldr	r3, [r7, #4]
+ 8028038:	781b      	ldrb	r3, [r3, #0]
+ 802803a:	f003 030f 	and.w	r3, r3, #15
+ 802803e:	b29a      	uxth	r2, r3
+ 8028040:	897b      	ldrh	r3, [r7, #10]
+ 8028042:	4413      	add	r3, r2
+ 8028044:	b29b      	uxth	r3, r3
+ 8028046:	817b      	strh	r3, [r7, #10]
+	if (isNegative)
+ 8028048:	7bfb      	ldrb	r3, [r7, #15]
+ 802804a:	2b00      	cmp	r3, #0
+ 802804c:	d007      	beq.n	802805e <getDeci+0xda>
+	{
+		return -(data_value + xiaoshu);
+ 802804e:	89ba      	ldrh	r2, [r7, #12]
+ 8028050:	897b      	ldrh	r3, [r7, #10]
+ 8028052:	4413      	add	r3, r2
+ 8028054:	b29b      	uxth	r3, r3
+ 8028056:	425b      	negs	r3, r3
+ 8028058:	b29b      	uxth	r3, r3
+ 802805a:	b21b      	sxth	r3, r3
+ 802805c:	e004      	b.n	8028068 <getDeci+0xe4>
+	} else
+	{
+		return (data_value + xiaoshu);
+ 802805e:	89ba      	ldrh	r2, [r7, #12]
+ 8028060:	897b      	ldrh	r3, [r7, #10]
+ 8028062:	4413      	add	r3, r2
+ 8028064:	b29b      	uxth	r3, r3
+ 8028066:	b21b      	sxth	r3, r3
+	}
+
+}
+ 8028068:	4618      	mov	r0, r3
+ 802806a:	3714      	adds	r7, #20
+ 802806c:	46bd      	mov	sp, r7
+ 802806e:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8028072:	4770      	bx	lr
+
+08028074 <ActivateMotor>:
+#include "BHBF_ROBOT.h"
+#include "bsp_FDCAN.h"
+
+void ActivateMotor(int32_t MotorID, FDCANHandler *ZQ_Motor_Controller,
+        int32_t WaitTime)
+{
+ 8028074:	b590      	push	{r4, r7, lr}
+ 8028076:	b087      	sub	sp, #28
+ 8028078:	af02      	add	r7, sp, #8
+ 802807a:	60f8      	str	r0, [r7, #12]
+ 802807c:	60b9      	str	r1, [r7, #8]
+ 802807e:	607a      	str	r2, [r7, #4]
+	ZQ_Motor_Controller->Tx_Buf[0] = 0x10;
+ 8028080:	68bb      	ldr	r3, [r7, #8]
+ 8028082:	2210      	movs	r2, #16
+ 8028084:	f883 20a8 	strb.w	r2, [r3, #168]	@ 0xa8
+	ZQ_Motor_Controller->Tx_Buf[1] = 0x10;
+ 8028088:	68bb      	ldr	r3, [r7, #8]
+ 802808a:	2210      	movs	r2, #16
+ 802808c:	f883 20a9 	strb.w	r2, [r3, #169]	@ 0xa9
+	ZQ_Motor_Controller->AddCANSendList(ZQ_Motor_Controller, MotorID, 2,
+ 8028090:	68bb      	ldr	r3, [r7, #8]
+ 8028092:	699c      	ldr	r4, [r3, #24]
+ 8028094:	68f9      	ldr	r1, [r7, #12]
+	        ZQ_Motor_Controller->Tx_Buf, WaitTime, NULL); //wait for 5 seconds to send
+ 8028096:	68bb      	ldr	r3, [r7, #8]
+ 8028098:	f103 02a8 	add.w	r2, r3, #168	@ 0xa8
+	ZQ_Motor_Controller->AddCANSendList(ZQ_Motor_Controller, MotorID, 2,
+ 802809c:	687b      	ldr	r3, [r7, #4]
+ 802809e:	2000      	movs	r0, #0
+ 80280a0:	9001      	str	r0, [sp, #4]
+ 80280a2:	9300      	str	r3, [sp, #0]
+ 80280a4:	4613      	mov	r3, r2
+ 80280a6:	2202      	movs	r2, #2
+ 80280a8:	68b8      	ldr	r0, [r7, #8]
+ 80280aa:	47a0      	blx	r4
+
+	//CANSendMessageSDO_ADD_To_SendList(MotorID, 0x23, 0x6083, 0x00, AccTime,ZQ_Motor_Controller,WaitTime);
+}
+ 80280ac:	bf00      	nop
+ 80280ae:	3714      	adds	r7, #20
+ 80280b0:	46bd      	mov	sp, r7
+ 80280b2:	bd90      	pop	{r4, r7, pc}
+
+080280b4 <Enable_NMT>:
+void Enable_NMT(int32_t MotorID, FDCANHandler *ZQ_Motor_Controller, int32_t Node_Number,  int32_t WaitTime)
+{
+ 80280b4:	b590      	push	{r4, r7, lr}
+ 80280b6:	b087      	sub	sp, #28
+ 80280b8:	af02      	add	r7, sp, #8
+ 80280ba:	60f8      	str	r0, [r7, #12]
+ 80280bc:	60b9      	str	r1, [r7, #8]
+ 80280be:	607a      	str	r2, [r7, #4]
+ 80280c0:	603b      	str	r3, [r7, #0]
+	ZQ_Motor_Controller->Tx_Buf[0] = 0x01;
+ 80280c2:	68bb      	ldr	r3, [r7, #8]
+ 80280c4:	2201      	movs	r2, #1
+ 80280c6:	f883 20a8 	strb.w	r2, [r3, #168]	@ 0xa8
+	ZQ_Motor_Controller->Tx_Buf[1] = Node_Number;
+ 80280ca:	687b      	ldr	r3, [r7, #4]
+ 80280cc:	b2da      	uxtb	r2, r3
+ 80280ce:	68bb      	ldr	r3, [r7, #8]
+ 80280d0:	f883 20a9 	strb.w	r2, [r3, #169]	@ 0xa9
+	ZQ_Motor_Controller->AddCANSendList(ZQ_Motor_Controller, MotorID, 2, ZQ_Motor_Controller->Tx_Buf, WaitTime, NULL); //wait for 5 seconds to send
+ 80280d4:	68bb      	ldr	r3, [r7, #8]
+ 80280d6:	699c      	ldr	r4, [r3, #24]
+ 80280d8:	68f9      	ldr	r1, [r7, #12]
+ 80280da:	68bb      	ldr	r3, [r7, #8]
+ 80280dc:	f103 02a8 	add.w	r2, r3, #168	@ 0xa8
+ 80280e0:	683b      	ldr	r3, [r7, #0]
+ 80280e2:	2000      	movs	r0, #0
+ 80280e4:	9001      	str	r0, [sp, #4]
+ 80280e6:	9300      	str	r3, [sp, #0]
+ 80280e8:	4613      	mov	r3, r2
+ 80280ea:	2202      	movs	r2, #2
+ 80280ec:	68b8      	ldr	r0, [r7, #8]
+ 80280ee:	47a0      	blx	r4
+}
+ 80280f0:	bf00      	nop
+ 80280f2:	3714      	adds	r7, #20
+ 80280f4:	46bd      	mov	sp, r7
+ 80280f6:	bd90      	pop	{r4, r7, pc}
+
+080280f8 <Configure_Asynchronous_Mode>:
+
+void Configure_Asynchronous_Mode(int32_t MotorID, FDCANHandler *ZQ_Motor_Controller, int32_t Node_Number,  int32_t WaitTime)
+{
+ 80280f8:	b590      	push	{r4, r7, lr}
+ 80280fa:	b087      	sub	sp, #28
+ 80280fc:	af02      	add	r7, sp, #8
+ 80280fe:	60f8      	str	r0, [r7, #12]
+ 8028100:	60b9      	str	r1, [r7, #8]
+ 8028102:	607a      	str	r2, [r7, #4]
+ 8028104:	603b      	str	r3, [r7, #0]
+	ZQ_Motor_Controller->Tx_Buf[0] = 0x23;
+ 8028106:	68bb      	ldr	r3, [r7, #8]
+ 8028108:	2223      	movs	r2, #35	@ 0x23
+ 802810a:	f883 20a8 	strb.w	r2, [r3, #168]	@ 0xa8
+	ZQ_Motor_Controller->Tx_Buf[1] = 0x16;
+ 802810e:	68bb      	ldr	r3, [r7, #8]
+ 8028110:	2216      	movs	r2, #22
+ 8028112:	f883 20a9 	strb.w	r2, [r3, #169]	@ 0xa9
+	ZQ_Motor_Controller->Tx_Buf[2] = 0x10;
+ 8028116:	68bb      	ldr	r3, [r7, #8]
+ 8028118:	2210      	movs	r2, #16
+ 802811a:	f883 20aa 	strb.w	r2, [r3, #170]	@ 0xaa
+	ZQ_Motor_Controller->Tx_Buf[3] = 0x01;
+ 802811e:	68bb      	ldr	r3, [r7, #8]
+ 8028120:	2201      	movs	r2, #1
+ 8028122:	f883 20ab 	strb.w	r2, [r3, #171]	@ 0xab
+	ZQ_Motor_Controller->Tx_Buf[4] = 0x64;
+ 8028126:	68bb      	ldr	r3, [r7, #8]
+ 8028128:	2264      	movs	r2, #100	@ 0x64
+ 802812a:	f883 20ac 	strb.w	r2, [r3, #172]	@ 0xac
+	ZQ_Motor_Controller->Tx_Buf[5] = 0x00;
+ 802812e:	68bb      	ldr	r3, [r7, #8]
+ 8028130:	2200      	movs	r2, #0
+ 8028132:	f883 20ad 	strb.w	r2, [r3, #173]	@ 0xad
+	ZQ_Motor_Controller->Tx_Buf[6] = Node_Number;
+ 8028136:	687b      	ldr	r3, [r7, #4]
+ 8028138:	b2da      	uxtb	r2, r3
+ 802813a:	68bb      	ldr	r3, [r7, #8]
+ 802813c:	f883 20ae 	strb.w	r2, [r3, #174]	@ 0xae
+	ZQ_Motor_Controller->Tx_Buf[7] = 0x00;
+ 8028140:	68bb      	ldr	r3, [r7, #8]
+ 8028142:	2200      	movs	r2, #0
+ 8028144:	f883 20af 	strb.w	r2, [r3, #175]	@ 0xaf
+	ZQ_Motor_Controller->AddCANSendList(ZQ_Motor_Controller, 0x600 + MotorID, 8, ZQ_Motor_Controller->Tx_Buf, WaitTime, NULL);
+ 8028148:	68bb      	ldr	r3, [r7, #8]
+ 802814a:	699c      	ldr	r4, [r3, #24]
+ 802814c:	68fb      	ldr	r3, [r7, #12]
+ 802814e:	f503 63c0 	add.w	r3, r3, #1536	@ 0x600
+ 8028152:	4618      	mov	r0, r3
+ 8028154:	68bb      	ldr	r3, [r7, #8]
+ 8028156:	f103 02a8 	add.w	r2, r3, #168	@ 0xa8
+ 802815a:	683b      	ldr	r3, [r7, #0]
+ 802815c:	2100      	movs	r1, #0
+ 802815e:	9101      	str	r1, [sp, #4]
+ 8028160:	9300      	str	r3, [sp, #0]
+ 8028162:	4613      	mov	r3, r2
+ 8028164:	2208      	movs	r2, #8
+ 8028166:	4601      	mov	r1, r0
+ 8028168:	68b8      	ldr	r0, [r7, #8]
+ 802816a:	47a0      	blx	r4
+}
+ 802816c:	bf00      	nop
+ 802816e:	3714      	adds	r7, #20
+ 8028170:	46bd      	mov	sp, r7
+ 8028172:	bd90      	pop	{r4, r7, pc}
+
+08028174 <Consumer_Or_microcontroller_Heartbeat>:
+
+void Consumer_Or_microcontroller_Heartbeat(int32_t MotorID, FDCANHandler *ZQ_Motor_Controller,   int32_t WaitTime)
+{
+ 8028174:	b590      	push	{r4, r7, lr}
+ 8028176:	b087      	sub	sp, #28
+ 8028178:	af02      	add	r7, sp, #8
+ 802817a:	60f8      	str	r0, [r7, #12]
+ 802817c:	60b9      	str	r1, [r7, #8]
+ 802817e:	607a      	str	r2, [r7, #4]
+	ZQ_Motor_Controller->Tx_Buf[0] = 0x05;
+ 8028180:	68bb      	ldr	r3, [r7, #8]
+ 8028182:	2205      	movs	r2, #5
+ 8028184:	f883 20a8 	strb.w	r2, [r3, #168]	@ 0xa8
+	ZQ_Motor_Controller->AddCANSendList(ZQ_Motor_Controller, MotorID, 1, ZQ_Motor_Controller->Tx_Buf, WaitTime, NULL); //wait for 5 seconds to send
+ 8028188:	68bb      	ldr	r3, [r7, #8]
+ 802818a:	699c      	ldr	r4, [r3, #24]
+ 802818c:	68f9      	ldr	r1, [r7, #12]
+ 802818e:	68bb      	ldr	r3, [r7, #8]
+ 8028190:	f103 02a8 	add.w	r2, r3, #168	@ 0xa8
+ 8028194:	687b      	ldr	r3, [r7, #4]
+ 8028196:	2000      	movs	r0, #0
+ 8028198:	9001      	str	r0, [sp, #4]
+ 802819a:	9300      	str	r3, [sp, #0]
+ 802819c:	4613      	mov	r3, r2
+ 802819e:	2201      	movs	r2, #1
+ 80281a0:	68b8      	ldr	r0, [r7, #8]
+ 80281a2:	47a0      	blx	r4
+}
+ 80281a4:	bf00      	nop
+ 80281a6:	3714      	adds	r7, #20
+ 80281a8:	46bd      	mov	sp, r7
+ 80281aa:	bd90      	pop	{r4, r7, pc}
+
+080281ac <CANSendMessageSDO_ADD_To_SendList>:
+
+
+void CANSendMessageSDO_ADD_To_SendList(int32_t MotorID, uint8_t Function,
+        uint16_t ControlWord, uint8_t subWord, int32_t ControlWordValue,
+        FDCANHandler *ZQ_Motor_Controller, int32_t WaitTime)
+{
+ 80281ac:	b590      	push	{r4, r7, lr}
+ 80281ae:	b085      	sub	sp, #20
+ 80281b0:	af02      	add	r7, sp, #8
+ 80281b2:	6078      	str	r0, [r7, #4]
+ 80281b4:	4608      	mov	r0, r1
+ 80281b6:	4611      	mov	r1, r2
+ 80281b8:	461a      	mov	r2, r3
+ 80281ba:	4603      	mov	r3, r0
+ 80281bc:	70fb      	strb	r3, [r7, #3]
+ 80281be:	460b      	mov	r3, r1
+ 80281c0:	803b      	strh	r3, [r7, #0]
+ 80281c2:	4613      	mov	r3, r2
+ 80281c4:	70bb      	strb	r3, [r7, #2]
+	//copy the corresponsiding data to the send Array
+	ZQ_Motor_Controller->Tx_Buf[0] = Function;
+ 80281c6:	69fb      	ldr	r3, [r7, #28]
+ 80281c8:	78fa      	ldrb	r2, [r7, #3]
+ 80281ca:	f883 20a8 	strb.w	r2, [r3, #168]	@ 0xa8
+	memcpy(&ZQ_Motor_Controller->Tx_Buf[1], &ControlWord, 2);
+ 80281ce:	69fb      	ldr	r3, [r7, #28]
+ 80281d0:	33a9      	adds	r3, #169	@ 0xa9
+ 80281d2:	883a      	ldrh	r2, [r7, #0]
+ 80281d4:	801a      	strh	r2, [r3, #0]
+	ZQ_Motor_Controller->Tx_Buf[3] = subWord;
+ 80281d6:	69fb      	ldr	r3, [r7, #28]
+ 80281d8:	78ba      	ldrb	r2, [r7, #2]
+ 80281da:	f883 20ab 	strb.w	r2, [r3, #171]	@ 0xab
+	memcpy(&ZQ_Motor_Controller->Tx_Buf[4], &ControlWordValue, 4);
+ 80281de:	69fb      	ldr	r3, [r7, #28]
+ 80281e0:	33ac      	adds	r3, #172	@ 0xac
+ 80281e2:	69ba      	ldr	r2, [r7, #24]
+ 80281e4:	601a      	str	r2, [r3, #0]
+	//send 8 bytes data
+
+	ZQ_Motor_Controller->AddCANSendList(ZQ_Motor_Controller, 0x600 + MotorID, 8,
+ 80281e6:	69fb      	ldr	r3, [r7, #28]
+ 80281e8:	699c      	ldr	r4, [r3, #24]
+ 80281ea:	687b      	ldr	r3, [r7, #4]
+ 80281ec:	f503 63c0 	add.w	r3, r3, #1536	@ 0x600
+ 80281f0:	4618      	mov	r0, r3
+	        ZQ_Motor_Controller->Tx_Buf, WaitTime, NULL);
+ 80281f2:	69fb      	ldr	r3, [r7, #28]
+ 80281f4:	f103 02a8 	add.w	r2, r3, #168	@ 0xa8
+	ZQ_Motor_Controller->AddCANSendList(ZQ_Motor_Controller, 0x600 + MotorID, 8,
+ 80281f8:	6a3b      	ldr	r3, [r7, #32]
+ 80281fa:	2100      	movs	r1, #0
+ 80281fc:	9101      	str	r1, [sp, #4]
+ 80281fe:	9300      	str	r3, [sp, #0]
+ 8028200:	4613      	mov	r3, r2
+ 8028202:	2208      	movs	r2, #8
+ 8028204:	4601      	mov	r1, r0
+ 8028206:	69f8      	ldr	r0, [r7, #28]
+ 8028208:	47a0      	blx	r4
+}
+ 802820a:	bf00      	nop
+ 802820c:	370c      	adds	r7, #12
+ 802820e:	46bd      	mov	sp, r7
+ 8028210:	bd90      	pop	{r4, r7, pc}
+
+08028212 <Postion_Velcocity_Run_SetParameter>:
+
+//位置速度模式
+void Postion_Velcocity_Run_SetParameter(int32_t MotorID, int32_t TargetPosition,
+        int32_t TargetSpeed, int32_t AccTime, int32_t DecTime,
+        FDCANHandler *ZQ_Motor_Controller, int32_t WaitTime)
+{
+ 8028212:	b580      	push	{r7, lr}
+ 8028214:	b088      	sub	sp, #32
+ 8028216:	af04      	add	r7, sp, #16
+ 8028218:	60f8      	str	r0, [r7, #12]
+ 802821a:	60b9      	str	r1, [r7, #8]
+ 802821c:	607a      	str	r2, [r7, #4]
+ 802821e:	603b      	str	r3, [r7, #0]
+	CANSendMessageSDO_ADD_To_SendList(MotorID, 0x2f, 0x6060, 0x00, 1,
+ 8028220:	6a3b      	ldr	r3, [r7, #32]
+ 8028222:	9302      	str	r3, [sp, #8]
+ 8028224:	69fb      	ldr	r3, [r7, #28]
+ 8028226:	9301      	str	r3, [sp, #4]
+ 8028228:	2301      	movs	r3, #1
+ 802822a:	9300      	str	r3, [sp, #0]
+ 802822c:	2300      	movs	r3, #0
+ 802822e:	f246 0260 	movw	r2, #24672	@ 0x6060
+ 8028232:	212f      	movs	r1, #47	@ 0x2f
+ 8028234:	68f8      	ldr	r0, [r7, #12]
+ 8028236:	f7ff ffb9 	bl	80281ac <CANSendMessageSDO_ADD_To_SendList>
+	        ZQ_Motor_Controller, WaitTime); // 1：设置操作模式，向索引0x6060:00写入0x01
+	if (TargetSpeed >= 3500) //the highest is 3500
+ 802823a:	687b      	ldr	r3, [r7, #4]
+ 802823c:	f640 52ab 	movw	r2, #3499	@ 0xdab
+ 8028240:	4293      	cmp	r3, r2
+ 8028242:	dd02      	ble.n	802824a <Postion_Velcocity_Run_SetParameter+0x38>
+	{
+		TargetSpeed = 3500;
+ 8028244:	f640 53ac 	movw	r3, #3500	@ 0xdac
+ 8028248:	607b      	str	r3, [r7, #4]
+	}
+	if (TargetSpeed < 0)
+ 802824a:	687b      	ldr	r3, [r7, #4]
+ 802824c:	2b00      	cmp	r3, #0
+ 802824e:	da01      	bge.n	8028254 <Postion_Velcocity_Run_SetParameter+0x42>
+	{
+		TargetSpeed = 0;
+ 8028250:	2300      	movs	r3, #0
+ 8028252:	607b      	str	r3, [r7, #4]
+	}
+	CANSendMessageSDO_ADD_To_SendList(MotorID, 0x23, 0x6083, 0x00, AccTime,
+ 8028254:	6a3b      	ldr	r3, [r7, #32]
+ 8028256:	9302      	str	r3, [sp, #8]
+ 8028258:	69fb      	ldr	r3, [r7, #28]
+ 802825a:	9301      	str	r3, [sp, #4]
+ 802825c:	683b      	ldr	r3, [r7, #0]
+ 802825e:	9300      	str	r3, [sp, #0]
+ 8028260:	2300      	movs	r3, #0
+ 8028262:	f246 0283 	movw	r2, #24707	@ 0x6083
+ 8028266:	2123      	movs	r1, #35	@ 0x23
+ 8028268:	68f8      	ldr	r0, [r7, #12]
+ 802826a:	f7ff ff9f 	bl	80281ac <CANSendMessageSDO_ADD_To_SendList>
+	        ZQ_Motor_Controller, WaitTime); //2：设置加速时间，向索引0x6083:00写入4字节数值
+	// Thread.Sleep(2);
+	CANSendMessageSDO_ADD_To_SendList(MotorID, 0x23, 0x6084, 0x00, DecTime,
+ 802826e:	6a3b      	ldr	r3, [r7, #32]
+ 8028270:	9302      	str	r3, [sp, #8]
+ 8028272:	69fb      	ldr	r3, [r7, #28]
+ 8028274:	9301      	str	r3, [sp, #4]
+ 8028276:	69bb      	ldr	r3, [r7, #24]
+ 8028278:	9300      	str	r3, [sp, #0]
+ 802827a:	2300      	movs	r3, #0
+ 802827c:	f246 0284 	movw	r2, #24708	@ 0x6084
+ 8028280:	2123      	movs	r1, #35	@ 0x23
+ 8028282:	68f8      	ldr	r0, [r7, #12]
+ 8028284:	f7ff ff92 	bl	80281ac <CANSendMessageSDO_ADD_To_SendList>
+	        ZQ_Motor_Controller, WaitTime);  //3：设置减速时间，向索引0x6084:00写入4字节数值
+	//Thread.Sleep(2);
+	CANSendMessageSDO_ADD_To_SendList(MotorID, 0x23, 0x607A, 0x00,
+ 8028288:	6a3b      	ldr	r3, [r7, #32]
+ 802828a:	9302      	str	r3, [sp, #8]
+ 802828c:	69fb      	ldr	r3, [r7, #28]
+ 802828e:	9301      	str	r3, [sp, #4]
+ 8028290:	68bb      	ldr	r3, [r7, #8]
+ 8028292:	9300      	str	r3, [sp, #0]
+ 8028294:	2300      	movs	r3, #0
+ 8028296:	f246 027a 	movw	r2, #24698	@ 0x607a
+ 802829a:	2123      	movs	r1, #35	@ 0x23
+ 802829c:	68f8      	ldr	r0, [r7, #12]
+ 802829e:	f7ff ff85 	bl	80281ac <CANSendMessageSDO_ADD_To_SendList>
+	// Thread.Sleep(2);
+
+	//23：写4字节数据；
+	//816000:索引号为0x6081,子索引号为0x00；
+	//E80300 00:设置运行速度为1000（单位0.1rpm）
+	CANSendMessageSDO_ADD_To_SendList(MotorID, 0x23, 0x6081, 0x00,
+ 80282a2:	687a      	ldr	r2, [r7, #4]
+ 80282a4:	4613      	mov	r3, r2
+ 80282a6:	009b      	lsls	r3, r3, #2
+ 80282a8:	4413      	add	r3, r2
+ 80282aa:	005b      	lsls	r3, r3, #1
+ 80282ac:	461a      	mov	r2, r3
+ 80282ae:	6a3b      	ldr	r3, [r7, #32]
+ 80282b0:	9302      	str	r3, [sp, #8]
+ 80282b2:	69fb      	ldr	r3, [r7, #28]
+ 80282b4:	9301      	str	r3, [sp, #4]
+ 80282b6:	9200      	str	r2, [sp, #0]
+ 80282b8:	2300      	movs	r3, #0
+ 80282ba:	f246 0281 	movw	r2, #24705	@ 0x6081
+ 80282be:	2123      	movs	r1, #35	@ 0x23
+ 80282c0:	68f8      	ldr	r0, [r7, #12]
+ 80282c2:	f7ff ff73 	bl	80281ac <CANSendMessageSDO_ADD_To_SendList>
+	        TargetSpeed * 10, ZQ_Motor_Controller, WaitTime); //5：设置运行速度，向索引	0x6081:00写入4字节数值
+
+	CANSendMessageSDO_ADD_To_SendList(MotorID, 0x2b, 0x6040, 0x00, 0x80,
+ 80282c6:	6a3b      	ldr	r3, [r7, #32]
+ 80282c8:	9302      	str	r3, [sp, #8]
+ 80282ca:	69fb      	ldr	r3, [r7, #28]
+ 80282cc:	9301      	str	r3, [sp, #4]
+ 80282ce:	2380      	movs	r3, #128	@ 0x80
+ 80282d0:	9300      	str	r3, [sp, #0]
+ 80282d2:	2300      	movs	r3, #0
+ 80282d4:	f246 0240 	movw	r2, #24640	@ 0x6040
+ 80282d8:	212b      	movs	r1, #43	@ 0x2b
+ 80282da:	68f8      	ldr	r0, [r7, #12]
+ 80282dc:	f7ff ff66 	bl	80281ac <CANSendMessageSDO_ADD_To_SendList>
+	        ZQ_Motor_Controller, WaitTime);  ///6:清除异常，向控制字0x6040:00写入0x80
+
+	CANSendMessageSDO_ADD_To_SendList(MotorID, 0x2b, 0x6040, 0x00, 0x06,
+ 80282e0:	6a3b      	ldr	r3, [r7, #32]
+ 80282e2:	9302      	str	r3, [sp, #8]
+ 80282e4:	69fb      	ldr	r3, [r7, #28]
+ 80282e6:	9301      	str	r3, [sp, #4]
+ 80282e8:	2306      	movs	r3, #6
+ 80282ea:	9300      	str	r3, [sp, #0]
+ 80282ec:	2300      	movs	r3, #0
+ 80282ee:	f246 0240 	movw	r2, #24640	@ 0x6040
+ 80282f2:	212b      	movs	r1, #43	@ 0x2b
+ 80282f4:	68f8      	ldr	r0, [r7, #12]
+ 80282f6:	f7ff ff59 	bl	80281ac <CANSendMessageSDO_ADD_To_SendList>
+	        ZQ_Motor_Controller, WaitTime);  //7：伺服准备，向控制字	0x6040:00写入0x06
+
+	CANSendMessageSDO_ADD_To_SendList(MotorID, 0x2b, 0x6040, 0x00, 0x07,
+ 80282fa:	6a3b      	ldr	r3, [r7, #32]
+ 80282fc:	9302      	str	r3, [sp, #8]
+ 80282fe:	69fb      	ldr	r3, [r7, #28]
+ 8028300:	9301      	str	r3, [sp, #4]
+ 8028302:	2307      	movs	r3, #7
+ 8028304:	9300      	str	r3, [sp, #0]
+ 8028306:	2300      	movs	r3, #0
+ 8028308:	f246 0240 	movw	r2, #24640	@ 0x6040
+ 802830c:	212b      	movs	r1, #43	@ 0x2b
+ 802830e:	68f8      	ldr	r0, [r7, #12]
+ 8028310:	f7ff ff4c 	bl	80281ac <CANSendMessageSDO_ADD_To_SendList>
+	        ZQ_Motor_Controller, WaitTime);  //8：伺服等待使能，向控制字0x6040:00写入0x07
+
+	CANSendMessageSDO_ADD_To_SendList(MotorID, 0x2b, 0x6040, 0x00, 0x2f,
+ 8028314:	6a3b      	ldr	r3, [r7, #32]
+ 8028316:	9302      	str	r3, [sp, #8]
+ 8028318:	69fb      	ldr	r3, [r7, #28]
+ 802831a:	9301      	str	r3, [sp, #4]
+ 802831c:	232f      	movs	r3, #47	@ 0x2f
+ 802831e:	9300      	str	r3, [sp, #0]
+ 8028320:	2300      	movs	r3, #0
+ 8028322:	f246 0240 	movw	r2, #24640	@ 0x6040
+ 8028326:	212b      	movs	r1, #43	@ 0x2b
+ 8028328:	68f8      	ldr	r0, [r7, #12]
+ 802832a:	f7ff ff3f 	bl	80281ac <CANSendMessageSDO_ADD_To_SendList>
+	        ZQ_Motor_Controller, WaitTime);  //9：伺服使能，向控制字0x6040:00写入0x0F
+
+	CANSendMessageSDO_ADD_To_SendList(MotorID, 0x2b, 0x6040, 0x00, 0x3f,
+ 802832e:	6a3b      	ldr	r3, [r7, #32]
+ 8028330:	9302      	str	r3, [sp, #8]
+ 8028332:	69fb      	ldr	r3, [r7, #28]
+ 8028334:	9301      	str	r3, [sp, #4]
+ 8028336:	233f      	movs	r3, #63	@ 0x3f
+ 8028338:	9300      	str	r3, [sp, #0]
+ 802833a:	2300      	movs	r3, #0
+ 802833c:	f246 0240 	movw	r2, #24640	@ 0x6040
+ 8028340:	212b      	movs	r1, #43	@ 0x2b
+ 8028342:	68f8      	ldr	r0, [r7, #12]
+ 8028344:	f7ff ff32 	bl	80281ac <CANSendMessageSDO_ADD_To_SendList>
+	        ZQ_Motor_Controller, WaitTime); //10：伺服启动,向控制字	0x6040:00写入0x1F  ///：
+}
+ 8028348:	bf00      	nop
+ 802834a:	3710      	adds	r7, #16
+ 802834c:	46bd      	mov	sp, r7
+ 802834e:	bd80      	pop	{r7, pc}
+
+08028350 <SpeedModeSetup>:
+//	CANSendMessageSDO_ADD_To_SendList(MotorID, 0x2f, 0x6040, 0x00, 0x1F,ZQ_Motor_Controller,WaitTime);  //7：启动原点定位,向控制字0x6040:00写入0x1F
+//}
+
+void SpeedModeSetup(int32_t MotorID, FDCANHandler *ZQ_Motor_Controller,
+        int32_t WaitTime, int32_t Acc, int32_t Dec, int32_t TargetVelocity) //设定速度模式，并更改相关速度
+{
+ 8028350:	b580      	push	{r7, lr}
+ 8028352:	b088      	sub	sp, #32
+ 8028354:	af04      	add	r7, sp, #16
+ 8028356:	60f8      	str	r0, [r7, #12]
+ 8028358:	60b9      	str	r1, [r7, #8]
+ 802835a:	607a      	str	r2, [r7, #4]
+ 802835c:	603b      	str	r3, [r7, #0]
+	CANSendMessageSDO_ADD_To_SendList(MotorID, 0x2b, 0x6040, 0x00, 0x02,
+ 802835e:	2364      	movs	r3, #100	@ 0x64
+ 8028360:	9302      	str	r3, [sp, #8]
+ 8028362:	68bb      	ldr	r3, [r7, #8]
+ 8028364:	9301      	str	r3, [sp, #4]
+ 8028366:	2302      	movs	r3, #2
+ 8028368:	9300      	str	r3, [sp, #0]
+ 802836a:	2300      	movs	r3, #0
+ 802836c:	f246 0240 	movw	r2, #24640	@ 0x6040
+ 8028370:	212b      	movs	r1, #43	@ 0x2b
+ 8028372:	68f8      	ldr	r0, [r7, #12]
+ 8028374:	f7ff ff1a 	bl	80281ac <CANSendMessageSDO_ADD_To_SendList>
+	        ZQ_Motor_Controller, 100);
+	//设置操作模式，向索引0x6060：00写入0x03
+	CANSendMessageSDO_ADD_To_SendList(MotorID, 0x2f, 0x6060, 0x00, 0x3,
+ 8028378:	687b      	ldr	r3, [r7, #4]
+ 802837a:	9302      	str	r3, [sp, #8]
+ 802837c:	68bb      	ldr	r3, [r7, #8]
+ 802837e:	9301      	str	r3, [sp, #4]
+ 8028380:	2303      	movs	r3, #3
+ 8028382:	9300      	str	r3, [sp, #0]
+ 8028384:	2300      	movs	r3, #0
+ 8028386:	f246 0260 	movw	r2, #24672	@ 0x6060
+ 802838a:	212f      	movs	r1, #47	@ 0x2f
+ 802838c:	68f8      	ldr	r0, [r7, #12]
+ 802838e:	f7ff ff0d 	bl	80281ac <CANSendMessageSDO_ADD_To_SendList>
+	        ZQ_Motor_Controller, WaitTime);
+	//2:清除异常， 向控制字	0x6040:00 写入 0x80
+	CANSendMessageSDO_ADD_To_SendList(MotorID, 0x2b, 0x6040, 0x00, 0x80,
+ 8028392:	687b      	ldr	r3, [r7, #4]
+ 8028394:	9302      	str	r3, [sp, #8]
+ 8028396:	68bb      	ldr	r3, [r7, #8]
+ 8028398:	9301      	str	r3, [sp, #4]
+ 802839a:	2380      	movs	r3, #128	@ 0x80
+ 802839c:	9300      	str	r3, [sp, #0]
+ 802839e:	2300      	movs	r3, #0
+ 80283a0:	f246 0240 	movw	r2, #24640	@ 0x6040
+ 80283a4:	212b      	movs	r1, #43	@ 0x2b
+ 80283a6:	68f8      	ldr	r0, [r7, #12]
+ 80283a8:	f7ff ff00 	bl	80281ac <CANSendMessageSDO_ADD_To_SendList>
+	        ZQ_Motor_Controller, WaitTime);
+	//3： 伺服准备, 向控制字	0x6040:00 写入 0x06
+	CANSendMessageSDO_ADD_To_SendList(MotorID, 0x2b, 0x6040, 0x00, 0x06,
+ 80283ac:	687b      	ldr	r3, [r7, #4]
+ 80283ae:	9302      	str	r3, [sp, #8]
+ 80283b0:	68bb      	ldr	r3, [r7, #8]
+ 80283b2:	9301      	str	r3, [sp, #4]
+ 80283b4:	2306      	movs	r3, #6
+ 80283b6:	9300      	str	r3, [sp, #0]
+ 80283b8:	2300      	movs	r3, #0
+ 80283ba:	f246 0240 	movw	r2, #24640	@ 0x6040
+ 80283be:	212b      	movs	r1, #43	@ 0x2b
+ 80283c0:	68f8      	ldr	r0, [r7, #12]
+ 80283c2:	f7ff fef3 	bl	80281ac <CANSendMessageSDO_ADD_To_SendList>
+	        ZQ_Motor_Controller, WaitTime);
+	//4： 伺服等待使能, 向控制字 0x6040:00 写入 0x07
+	CANSendMessageSDO_ADD_To_SendList(MotorID, 0x2b, 0x6040, 0x00, 0x07,
+ 80283c6:	687b      	ldr	r3, [r7, #4]
+ 80283c8:	9302      	str	r3, [sp, #8]
+ 80283ca:	68bb      	ldr	r3, [r7, #8]
+ 80283cc:	9301      	str	r3, [sp, #4]
+ 80283ce:	2307      	movs	r3, #7
+ 80283d0:	9300      	str	r3, [sp, #0]
+ 80283d2:	2300      	movs	r3, #0
+ 80283d4:	f246 0240 	movw	r2, #24640	@ 0x6040
+ 80283d8:	212b      	movs	r1, #43	@ 0x2b
+ 80283da:	68f8      	ldr	r0, [r7, #12]
+ 80283dc:	f7ff fee6 	bl	80281ac <CANSendMessageSDO_ADD_To_SendList>
+	        ZQ_Motor_Controller, WaitTime);
+	//5： 伺服使能,向控制字0x6040:00 写入 0x0F
+	CANSendMessageSDO_ADD_To_SendList(MotorID, 0x2b, 0x6040, 0x00, 0x0f,
+ 80283e0:	687b      	ldr	r3, [r7, #4]
+ 80283e2:	9302      	str	r3, [sp, #8]
+ 80283e4:	68bb      	ldr	r3, [r7, #8]
+ 80283e6:	9301      	str	r3, [sp, #4]
+ 80283e8:	230f      	movs	r3, #15
+ 80283ea:	9300      	str	r3, [sp, #0]
+ 80283ec:	2300      	movs	r3, #0
+ 80283ee:	f246 0240 	movw	r2, #24640	@ 0x6040
+ 80283f2:	212b      	movs	r1, #43	@ 0x2b
+ 80283f4:	68f8      	ldr	r0, [r7, #12]
+ 80283f6:	f7ff fed9 	bl	80281ac <CANSendMessageSDO_ADD_To_SendList>
+	        ZQ_Motor_Controller, WaitTime);
+	//6:设置加速时间， 向索引	0x201C:00写入4字节数值 //不关心加速时间的模式下， 加减速时间建议设置为 1500（ms） 以上
+	CANSendMessageSDO_ADD_To_SendList(MotorID, 0x23, 0x201c, 0x00, Acc,
+ 80283fa:	687b      	ldr	r3, [r7, #4]
+ 80283fc:	9302      	str	r3, [sp, #8]
+ 80283fe:	68bb      	ldr	r3, [r7, #8]
+ 8028400:	9301      	str	r3, [sp, #4]
+ 8028402:	683b      	ldr	r3, [r7, #0]
+ 8028404:	9300      	str	r3, [sp, #0]
+ 8028406:	2300      	movs	r3, #0
+ 8028408:	f242 021c 	movw	r2, #8220	@ 0x201c
+ 802840c:	2123      	movs	r1, #35	@ 0x23
+ 802840e:	68f8      	ldr	r0, [r7, #12]
+ 8028410:	f7ff fecc 	bl	80281ac <CANSendMessageSDO_ADD_To_SendList>
+	        ZQ_Motor_Controller, WaitTime);
+	//7： 设置减速时间， 向索引0x201D:00写入4字节数据
+	CANSendMessageSDO_ADD_To_SendList(MotorID, 0x23, 0x201d, 0x00, Dec,
+ 8028414:	687b      	ldr	r3, [r7, #4]
+ 8028416:	9302      	str	r3, [sp, #8]
+ 8028418:	68bb      	ldr	r3, [r7, #8]
+ 802841a:	9301      	str	r3, [sp, #4]
+ 802841c:	69bb      	ldr	r3, [r7, #24]
+ 802841e:	9300      	str	r3, [sp, #0]
+ 8028420:	2300      	movs	r3, #0
+ 8028422:	f242 021d 	movw	r2, #8221	@ 0x201d
+ 8028426:	2123      	movs	r1, #35	@ 0x23
+ 8028428:	68f8      	ldr	r0, [r7, #12]
+ 802842a:	f7ff febf 	bl	80281ac <CANSendMessageSDO_ADD_To_SendList>
+	        ZQ_Motor_Controller, WaitTime);
+	//8： 设定目标速度值， 向索引 0x60FF:00 写入 4 字节数值（有符号）
+	CANSendMessageSDO_ADD_To_SendList(MotorID, 0x23, 0x60ff, 0x00,
+ 802842e:	687b      	ldr	r3, [r7, #4]
+ 8028430:	9302      	str	r3, [sp, #8]
+ 8028432:	68bb      	ldr	r3, [r7, #8]
+ 8028434:	9301      	str	r3, [sp, #4]
+ 8028436:	69fb      	ldr	r3, [r7, #28]
+ 8028438:	9300      	str	r3, [sp, #0]
+ 802843a:	2300      	movs	r3, #0
+ 802843c:	f246 02ff 	movw	r2, #24831	@ 0x60ff
+ 8028440:	2123      	movs	r1, #35	@ 0x23
+ 8028442:	68f8      	ldr	r0, [r7, #12]
+ 8028444:	f7ff feb2 	bl	80281ac <CANSendMessageSDO_ADD_To_SendList>
+
+	//修改步骤8 可以实现速度的改变
+	// 23:写 4 字节数据；FF 60 00:索引号为 0x60FF，
+	// 子索引号为 0x00;E8 03 00 00：
+	// 设置目标速度 1000（单位 0.1rpm）
+}
+ 8028448:	bf00      	nop
+ 802844a:	3710      	adds	r7, #16
+ 802844c:	46bd      	mov	sp, r7
+ 802844e:	bd80      	pop	{r7, pc}
+
+08028450 <TT_SpeedMode_Set_TargetSpeed>:
+void TT_SpeedMode_Set_TargetSpeed(uint32_t MotorID,
+        FDCANHandler *ZQ_Motor_Controller, int32_t WaitTime,
+        int32_t TargetSpeed)
+{
+ 8028450:	b580      	push	{r7, lr}
+ 8028452:	b088      	sub	sp, #32
+ 8028454:	af04      	add	r7, sp, #16
+ 8028456:	60f8      	str	r0, [r7, #12]
+ 8028458:	60b9      	str	r1, [r7, #8]
+ 802845a:	607a      	str	r2, [r7, #4]
+ 802845c:	603b      	str	r3, [r7, #0]
+	CANSendMessageSDO_ADD_To_SendList(MotorID, 0x23, 0x60ff, 0x00, TargetSpeed,
+ 802845e:	68f8      	ldr	r0, [r7, #12]
+ 8028460:	687b      	ldr	r3, [r7, #4]
+ 8028462:	9302      	str	r3, [sp, #8]
+ 8028464:	68bb      	ldr	r3, [r7, #8]
+ 8028466:	9301      	str	r3, [sp, #4]
+ 8028468:	683b      	ldr	r3, [r7, #0]
+ 802846a:	9300      	str	r3, [sp, #0]
+ 802846c:	2300      	movs	r3, #0
+ 802846e:	f246 02ff 	movw	r2, #24831	@ 0x60ff
+ 8028472:	2123      	movs	r1, #35	@ 0x23
+ 8028474:	f7ff fe9a 	bl	80281ac <CANSendMessageSDO_ADD_To_SendList>
+	        ZQ_Motor_Controller, WaitTime);
+}
+ 8028478:	bf00      	nop
+ 802847a:	3710      	adds	r7, #16
+ 802847c:	46bd      	mov	sp, r7
+ 802847e:	bd80      	pop	{r7, pc}
+
+08028480 <TT_Request_Position>:
+
+}
+
+void TT_Request_Position(uint32_t Motor_ID_1, FDCANHandler *ZQ_Motor_Controller,
+        int32_t WaitTime)     // Home  设置当前位置为零点
+{
+ 8028480:	b580      	push	{r7, lr}
+ 8028482:	b088      	sub	sp, #32
+ 8028484:	af04      	add	r7, sp, #16
+ 8028486:	60f8      	str	r0, [r7, #12]
+ 8028488:	60b9      	str	r1, [r7, #8]
+ 802848a:	607a      	str	r2, [r7, #4]
+	CANSendMessageSDO_ADD_To_SendList(Motor_ID_1, 0x40, 0x6064, 0x00, 0x00,
+ 802848c:	68f8      	ldr	r0, [r7, #12]
+ 802848e:	687b      	ldr	r3, [r7, #4]
+ 8028490:	9302      	str	r3, [sp, #8]
+ 8028492:	68bb      	ldr	r3, [r7, #8]
+ 8028494:	9301      	str	r3, [sp, #4]
+ 8028496:	2300      	movs	r3, #0
+ 8028498:	9300      	str	r3, [sp, #0]
+ 802849a:	2300      	movs	r3, #0
+ 802849c:	f246 0264 	movw	r2, #24676	@ 0x6064
+ 80284a0:	2140      	movs	r1, #64	@ 0x40
+ 80284a2:	f7ff fe83 	bl	80281ac <CANSendMessageSDO_ADD_To_SendList>
+	        ZQ_Motor_Controller, WaitTime); //用户实际速度反馈(0.1rpm)
+}
+ 80284a6:	bf00      	nop
+ 80284a8:	3710      	adds	r7, #16
+ 80284aa:	46bd      	mov	sp, r7
+ 80284ac:	bd80      	pop	{r7, pc}
+
+080284ae <Position_Immediately_Setting>:
+
+
+void Position_Immediately_Setting(uint8_t MotorID, FDCANHandler *ZQ_Motor_Controller,int32_t Deri_Position,int32_t Deri_Speed, int32_t WaitTime)  // Home  设置当前位置为零点
+{
+ 80284ae:	b580      	push	{r7, lr}
+ 80284b0:	b088      	sub	sp, #32
+ 80284b2:	af04      	add	r7, sp, #16
+ 80284b4:	60b9      	str	r1, [r7, #8]
+ 80284b6:	607a      	str	r2, [r7, #4]
+ 80284b8:	603b      	str	r3, [r7, #0]
+ 80284ba:	4603      	mov	r3, r0
+ 80284bc:	73fb      	strb	r3, [r7, #15]
+	CANSendMessageSDO_ADD_To_SendList(MotorID, 0x23, 0x607A, 0x00, Deri_Position, ZQ_Motor_Controller, WaitTime); //设置位置
+ 80284be:	7bf8      	ldrb	r0, [r7, #15]
+ 80284c0:	69bb      	ldr	r3, [r7, #24]
+ 80284c2:	9302      	str	r3, [sp, #8]
+ 80284c4:	68bb      	ldr	r3, [r7, #8]
+ 80284c6:	9301      	str	r3, [sp, #4]
+ 80284c8:	687b      	ldr	r3, [r7, #4]
+ 80284ca:	9300      	str	r3, [sp, #0]
+ 80284cc:	2300      	movs	r3, #0
+ 80284ce:	f246 027a 	movw	r2, #24698	@ 0x607a
+ 80284d2:	2123      	movs	r1, #35	@ 0x23
+ 80284d4:	f7ff fe6a 	bl	80281ac <CANSendMessageSDO_ADD_To_SendList>
+	CANSendMessageSDO_ADD_To_SendList(MotorID, 0x23, 0x6081, 0x00, Deri_Speed,    ZQ_Motor_Controller, WaitTime); //设置速度
+ 80284d8:	7bf8      	ldrb	r0, [r7, #15]
+ 80284da:	69bb      	ldr	r3, [r7, #24]
+ 80284dc:	9302      	str	r3, [sp, #8]
+ 80284de:	68bb      	ldr	r3, [r7, #8]
+ 80284e0:	9301      	str	r3, [sp, #4]
+ 80284e2:	683b      	ldr	r3, [r7, #0]
+ 80284e4:	9300      	str	r3, [sp, #0]
+ 80284e6:	2300      	movs	r3, #0
+ 80284e8:	f246 0281 	movw	r2, #24705	@ 0x6081
+ 80284ec:	2123      	movs	r1, #35	@ 0x23
+ 80284ee:	f7ff fe5d 	bl	80281ac <CANSendMessageSDO_ADD_To_SendList>
+	CANSendMessageSDO_ADD_To_SendList(MotorID, 0x2B, 0x6040, 0x00, 0x2f,          ZQ_Motor_Controller, WaitTime);
+ 80284f2:	7bf8      	ldrb	r0, [r7, #15]
+ 80284f4:	69bb      	ldr	r3, [r7, #24]
+ 80284f6:	9302      	str	r3, [sp, #8]
+ 80284f8:	68bb      	ldr	r3, [r7, #8]
+ 80284fa:	9301      	str	r3, [sp, #4]
+ 80284fc:	232f      	movs	r3, #47	@ 0x2f
+ 80284fe:	9300      	str	r3, [sp, #0]
+ 8028500:	2300      	movs	r3, #0
+ 8028502:	f246 0240 	movw	r2, #24640	@ 0x6040
+ 8028506:	212b      	movs	r1, #43	@ 0x2b
+ 8028508:	f7ff fe50 	bl	80281ac <CANSendMessageSDO_ADD_To_SendList>
+	CANSendMessageSDO_ADD_To_SendList(MotorID, 0x2B, 0x6040, 0x00, 0x3f,          ZQ_Motor_Controller, WaitTime);
+ 802850c:	7bf8      	ldrb	r0, [r7, #15]
+ 802850e:	69bb      	ldr	r3, [r7, #24]
+ 8028510:	9302      	str	r3, [sp, #8]
+ 8028512:	68bb      	ldr	r3, [r7, #8]
+ 8028514:	9301      	str	r3, [sp, #4]
+ 8028516:	233f      	movs	r3, #63	@ 0x3f
+ 8028518:	9300      	str	r3, [sp, #0]
+ 802851a:	2300      	movs	r3, #0
+ 802851c:	f246 0240 	movw	r2, #24640	@ 0x6040
+ 8028520:	212b      	movs	r1, #43	@ 0x2b
+ 8028522:	f7ff fe43 	bl	80281ac <CANSendMessageSDO_ADD_To_SendList>
+}
+ 8028526:	bf00      	nop
+ 8028528:	3710      	adds	r7, #16
+ 802852a:	46bd      	mov	sp, r7
+ 802852c:	bd80      	pop	{r7, pc}
+
+0802852e <Position_Lag_Setting>:
+
+void Position_Lag_Setting(uint8_t MotorID, FDCANHandler *ZQ_Motor_Controller,int32_t Deri_Position,int32_t Deri_Speed, int32_t WaitTime)  // Home  设置当前位置为零点
+{
+ 802852e:	b580      	push	{r7, lr}
+ 8028530:	b088      	sub	sp, #32
+ 8028532:	af04      	add	r7, sp, #16
+ 8028534:	60b9      	str	r1, [r7, #8]
+ 8028536:	607a      	str	r2, [r7, #4]
+ 8028538:	603b      	str	r3, [r7, #0]
+ 802853a:	4603      	mov	r3, r0
+ 802853c:	73fb      	strb	r3, [r7, #15]
+	CANSendMessageSDO_ADD_To_SendList(MotorID, 0x23, 0x607A, 0x00, Deri_Position, ZQ_Motor_Controller, WaitTime); //设置位置
+ 802853e:	7bf8      	ldrb	r0, [r7, #15]
+ 8028540:	69bb      	ldr	r3, [r7, #24]
+ 8028542:	9302      	str	r3, [sp, #8]
+ 8028544:	68bb      	ldr	r3, [r7, #8]
+ 8028546:	9301      	str	r3, [sp, #4]
+ 8028548:	687b      	ldr	r3, [r7, #4]
+ 802854a:	9300      	str	r3, [sp, #0]
+ 802854c:	2300      	movs	r3, #0
+ 802854e:	f246 027a 	movw	r2, #24698	@ 0x607a
+ 8028552:	2123      	movs	r1, #35	@ 0x23
+ 8028554:	f7ff fe2a 	bl	80281ac <CANSendMessageSDO_ADD_To_SendList>
+	CANSendMessageSDO_ADD_To_SendList(MotorID, 0x23, 0x6081, 0x00, Deri_Speed,    ZQ_Motor_Controller, WaitTime); //设置速度
+ 8028558:	7bf8      	ldrb	r0, [r7, #15]
+ 802855a:	69bb      	ldr	r3, [r7, #24]
+ 802855c:	9302      	str	r3, [sp, #8]
+ 802855e:	68bb      	ldr	r3, [r7, #8]
+ 8028560:	9301      	str	r3, [sp, #4]
+ 8028562:	683b      	ldr	r3, [r7, #0]
+ 8028564:	9300      	str	r3, [sp, #0]
+ 8028566:	2300      	movs	r3, #0
+ 8028568:	f246 0281 	movw	r2, #24705	@ 0x6081
+ 802856c:	2123      	movs	r1, #35	@ 0x23
+ 802856e:	f7ff fe1d 	bl	80281ac <CANSendMessageSDO_ADD_To_SendList>
+	CANSendMessageSDO_ADD_To_SendList(MotorID, 0x2B, 0x6040, 0x00, 0x0f,          ZQ_Motor_Controller, WaitTime);
+ 8028572:	7bf8      	ldrb	r0, [r7, #15]
+ 8028574:	69bb      	ldr	r3, [r7, #24]
+ 8028576:	9302      	str	r3, [sp, #8]
+ 8028578:	68bb      	ldr	r3, [r7, #8]
+ 802857a:	9301      	str	r3, [sp, #4]
+ 802857c:	230f      	movs	r3, #15
+ 802857e:	9300      	str	r3, [sp, #0]
+ 8028580:	2300      	movs	r3, #0
+ 8028582:	f246 0240 	movw	r2, #24640	@ 0x6040
+ 8028586:	212b      	movs	r1, #43	@ 0x2b
+ 8028588:	f7ff fe10 	bl	80281ac <CANSendMessageSDO_ADD_To_SendList>
+	CANSendMessageSDO_ADD_To_SendList(MotorID, 0x2B, 0x6040, 0x00, 0x1f,          ZQ_Motor_Controller, WaitTime);
+ 802858c:	7bf8      	ldrb	r0, [r7, #15]
+ 802858e:	69bb      	ldr	r3, [r7, #24]
+ 8028590:	9302      	str	r3, [sp, #8]
+ 8028592:	68bb      	ldr	r3, [r7, #8]
+ 8028594:	9301      	str	r3, [sp, #4]
+ 8028596:	231f      	movs	r3, #31
+ 8028598:	9300      	str	r3, [sp, #0]
+ 802859a:	2300      	movs	r3, #0
+ 802859c:	f246 0240 	movw	r2, #24640	@ 0x6040
+ 80285a0:	212b      	movs	r1, #43	@ 0x2b
+ 80285a2:	f7ff fe03 	bl	80281ac <CANSendMessageSDO_ADD_To_SendList>
+}
+ 80285a6:	bf00      	nop
+ 80285a8:	3710      	adds	r7, #16
+ 80285aa:	46bd      	mov	sp, r7
+ 80285ac:	bd80      	pop	{r7, pc}
+
+080285ae <TT_Request_Velocity>:
+
+
+
+void TT_Request_Velocity(uint32_t Motor_ID_1, FDCANHandler *ZQ_Motor_Controller,
+        int32_t WaitTime)
+{
+ 80285ae:	b580      	push	{r7, lr}
+ 80285b0:	b088      	sub	sp, #32
+ 80285b2:	af04      	add	r7, sp, #16
+ 80285b4:	60f8      	str	r0, [r7, #12]
+ 80285b6:	60b9      	str	r1, [r7, #8]
+ 80285b8:	607a      	str	r2, [r7, #4]
+	CANSendMessageSDO_ADD_To_SendList(Motor_ID_1, 0x40, 0x606c, 0x00, 0x00,
+ 80285ba:	68f8      	ldr	r0, [r7, #12]
+ 80285bc:	687b      	ldr	r3, [r7, #4]
+ 80285be:	9302      	str	r3, [sp, #8]
+ 80285c0:	68bb      	ldr	r3, [r7, #8]
+ 80285c2:	9301      	str	r3, [sp, #4]
+ 80285c4:	2300      	movs	r3, #0
+ 80285c6:	9300      	str	r3, [sp, #0]
+ 80285c8:	2300      	movs	r3, #0
+ 80285ca:	f246 026c 	movw	r2, #24684	@ 0x606c
+ 80285ce:	2140      	movs	r1, #64	@ 0x40
+ 80285d0:	f7ff fdec 	bl	80281ac <CANSendMessageSDO_ADD_To_SendList>
+	        ZQ_Motor_Controller, WaitTime); //用户实际速度反馈(0.1rpm)
+
+}
+ 80285d4:	bf00      	nop
+ 80285d6:	3710      	adds	r7, #16
+ 80285d8:	46bd      	mov	sp, r7
+ 80285da:	bd80      	pop	{r7, pc}
+
+080285dc <TT_Request_Fault>:
+//
+//
+void TT_Request_Fault(uint32_t Motor_ID_1, FDCANHandler *ZQ_Motor_Controller,
+        int32_t WaitTime)
+{
+ 80285dc:	b580      	push	{r7, lr}
+ 80285de:	b088      	sub	sp, #32
+ 80285e0:	af04      	add	r7, sp, #16
+ 80285e2:	60f8      	str	r0, [r7, #12]
+ 80285e4:	60b9      	str	r1, [r7, #8]
+ 80285e6:	607a      	str	r2, [r7, #4]
+	CANSendMessageSDO_ADD_To_SendList(Motor_ID_1, 0x40, 0x300A, 0x00, 0x00,
+ 80285e8:	68f8      	ldr	r0, [r7, #12]
+ 80285ea:	687b      	ldr	r3, [r7, #4]
+ 80285ec:	9302      	str	r3, [sp, #8]
+ 80285ee:	68bb      	ldr	r3, [r7, #8]
+ 80285f0:	9301      	str	r3, [sp, #4]
+ 80285f2:	2300      	movs	r3, #0
+ 80285f4:	9300      	str	r3, [sp, #0]
+ 80285f6:	2300      	movs	r3, #0
+ 80285f8:	f243 020a 	movw	r2, #12298	@ 0x300a
+ 80285fc:	2140      	movs	r1, #64	@ 0x40
+ 80285fe:	f7ff fdd5 	bl	80281ac <CANSendMessageSDO_ADD_To_SendList>
+	        ZQ_Motor_Controller, WaitTime);
+
+}
+ 8028602:	bf00      	nop
+ 8028604:	3710      	adds	r7, #16
+ 8028606:	46bd      	mov	sp, r7
+ 8028608:	bd80      	pop	{r7, pc}
+
+0802860a <TT_Request_Current>:
+
+void TT_Request_Current(uint32_t Motor_ID_1, FDCANHandler *ZQ_Motor_Controller,
+        int32_t WaitTime)
+{
+ 802860a:	b580      	push	{r7, lr}
+ 802860c:	b088      	sub	sp, #32
+ 802860e:	af04      	add	r7, sp, #16
+ 8028610:	60f8      	str	r0, [r7, #12]
+ 8028612:	60b9      	str	r1, [r7, #8]
+ 8028614:	607a      	str	r2, [r7, #4]
+	CANSendMessageSDO_ADD_To_SendList(Motor_ID_1, 0x40, 0x6078, 0x00, 0x00,
+ 8028616:	68f8      	ldr	r0, [r7, #12]
+ 8028618:	687b      	ldr	r3, [r7, #4]
+ 802861a:	9302      	str	r3, [sp, #8]
+ 802861c:	68bb      	ldr	r3, [r7, #8]
+ 802861e:	9301      	str	r3, [sp, #4]
+ 8028620:	2300      	movs	r3, #0
+ 8028622:	9300      	str	r3, [sp, #0]
+ 8028624:	2300      	movs	r3, #0
+ 8028626:	f246 0278 	movw	r2, #24696	@ 0x6078
+ 802862a:	2140      	movs	r1, #64	@ 0x40
+ 802862c:	f7ff fdbe 	bl	80281ac <CANSendMessageSDO_ADD_To_SendList>
+	        ZQ_Motor_Controller, WaitTime);
+}
+ 8028630:	bf00      	nop
+ 8028632:	3710      	adds	r7, #16
+ 8028634:	46bd      	mov	sp, r7
+ 8028636:	bd80      	pop	{r7, pc}
+
+08028638 <TT_Analytic_Fun>:
+
+void TT_Analytic_Fun(int32_t ID_A_T_A, char *buffer)
+{
+ 8028638:	b480      	push	{r7}
+ 802863a:	b089      	sub	sp, #36	@ 0x24
+ 802863c:	af00      	add	r7, sp, #0
+ 802863e:	6078      	str	r0, [r7, #4]
+ 8028640:	6039      	str	r1, [r7, #0]
+
+	int Function_code = (int) ((int16_t) (buffer[1] | buffer[2] << 8));
+ 8028642:	683b      	ldr	r3, [r7, #0]
+ 8028644:	3301      	adds	r3, #1
+ 8028646:	781b      	ldrb	r3, [r3, #0]
+ 8028648:	b21a      	sxth	r2, r3
+ 802864a:	683b      	ldr	r3, [r7, #0]
+ 802864c:	3302      	adds	r3, #2
+ 802864e:	781b      	ldrb	r3, [r3, #0]
+ 8028650:	021b      	lsls	r3, r3, #8
+ 8028652:	b21b      	sxth	r3, r3
+ 8028654:	4313      	orrs	r3, r2
+ 8028656:	b21b      	sxth	r3, r3
+ 8028658:	61fb      	str	r3, [r7, #28]
+	switch (Function_code)
+ 802865a:	69fb      	ldr	r3, [r7, #28]
+ 802865c:	f246 02ff 	movw	r2, #24831	@ 0x60ff
+ 8028660:	4293      	cmp	r3, r2
+ 8028662:	f000 80ee 	beq.w	8028842 <TT_Analytic_Fun+0x20a>
+ 8028666:	69fb      	ldr	r3, [r7, #28]
+ 8028668:	f5b3 4fc2 	cmp.w	r3, #24832	@ 0x6100
+ 802866c:	f280 8205 	bge.w	8028a7a <TT_Analytic_Fun+0x442>
+ 8028670:	69fb      	ldr	r3, [r7, #28]
+ 8028672:	f246 0284 	movw	r2, #24708	@ 0x6084
+ 8028676:	4293      	cmp	r3, r2
+ 8028678:	f300 81ff 	bgt.w	8028a7a <TT_Analytic_Fun+0x442>
+ 802867c:	69fb      	ldr	r3, [r7, #28]
+ 802867e:	f246 0240 	movw	r2, #24640	@ 0x6040
+ 8028682:	4293      	cmp	r3, r2
+ 8028684:	da18      	bge.n	80286b8 <TT_Analytic_Fun+0x80>
+ 8028686:	69fb      	ldr	r3, [r7, #28]
+ 8028688:	f243 020a 	movw	r2, #12298	@ 0x300a
+ 802868c:	4293      	cmp	r3, r2
+ 802868e:	f000 81d0 	beq.w	8028a32 <TT_Analytic_Fun+0x3fa>
+ 8028692:	69fb      	ldr	r3, [r7, #28]
+ 8028694:	f243 020a 	movw	r2, #12298	@ 0x300a
+ 8028698:	4293      	cmp	r3, r2
+ 802869a:	f300 81ee 	bgt.w	8028a7a <TT_Analytic_Fun+0x442>
+ 802869e:	69fb      	ldr	r3, [r7, #28]
+ 80286a0:	f242 021c 	movw	r2, #8220	@ 0x201c
+ 80286a4:	4293      	cmp	r3, r2
+ 80286a6:	f000 80c5 	beq.w	8028834 <TT_Analytic_Fun+0x1fc>
+ 80286aa:	69fb      	ldr	r3, [r7, #28]
+ 80286ac:	f242 021d 	movw	r2, #8221	@ 0x201d
+ 80286b0:	4293      	cmp	r3, r2
+ 80286b2:	f000 80cd 	beq.w	8028850 <TT_Analytic_Fun+0x218>
+ 80286b6:	e1e0      	b.n	8028a7a <TT_Analytic_Fun+0x442>
+ 80286b8:	69fa      	ldr	r2, [r7, #28]
+ 80286ba:	4b9c      	ldr	r3, [pc, #624]	@ (802892c <TT_Analytic_Fun+0x2f4>)
+ 80286bc:	4413      	add	r3, r2
+ 80286be:	2b44      	cmp	r3, #68	@ 0x44
+ 80286c0:	f200 81db 	bhi.w	8028a7a <TT_Analytic_Fun+0x442>
+ 80286c4:	a201      	add	r2, pc, #4	@ (adr r2, 80286cc <TT_Analytic_Fun+0x94>)
+ 80286c6:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 80286ca:	bf00      	nop
+ 80286cc:	08028827 	.word	0x08028827
+ 80286d0:	08028a7b 	.word	0x08028a7b
+ 80286d4:	08028a7b 	.word	0x08028a7b
+ 80286d8:	08028a7b 	.word	0x08028a7b
+ 80286dc:	08028a7b 	.word	0x08028a7b
+ 80286e0:	08028a7b 	.word	0x08028a7b
+ 80286e4:	08028a7b 	.word	0x08028a7b
+ 80286e8:	08028a7b 	.word	0x08028a7b
+ 80286ec:	08028a7b 	.word	0x08028a7b
+ 80286f0:	08028a7b 	.word	0x08028a7b
+ 80286f4:	08028a7b 	.word	0x08028a7b
+ 80286f8:	08028a7b 	.word	0x08028a7b
+ 80286fc:	08028a7b 	.word	0x08028a7b
+ 8028700:	08028a7b 	.word	0x08028a7b
+ 8028704:	08028a7b 	.word	0x08028a7b
+ 8028708:	08028a7b 	.word	0x08028a7b
+ 802870c:	08028a7b 	.word	0x08028a7b
+ 8028710:	08028a7b 	.word	0x08028a7b
+ 8028714:	08028a7b 	.word	0x08028a7b
+ 8028718:	08028a7b 	.word	0x08028a7b
+ 802871c:	08028a7b 	.word	0x08028a7b
+ 8028720:	08028a7b 	.word	0x08028a7b
+ 8028724:	08028a7b 	.word	0x08028a7b
+ 8028728:	08028a7b 	.word	0x08028a7b
+ 802872c:	08028a7b 	.word	0x08028a7b
+ 8028730:	08028a7b 	.word	0x08028a7b
+ 8028734:	08028a7b 	.word	0x08028a7b
+ 8028738:	08028a7b 	.word	0x08028a7b
+ 802873c:	08028a7b 	.word	0x08028a7b
+ 8028740:	08028a7b 	.word	0x08028a7b
+ 8028744:	08028a7b 	.word	0x08028a7b
+ 8028748:	08028a7b 	.word	0x08028a7b
+ 802874c:	080287e1 	.word	0x080287e1
+ 8028750:	08028a7b 	.word	0x08028a7b
+ 8028754:	08028a7b 	.word	0x08028a7b
+ 8028758:	08028a7b 	.word	0x08028a7b
+ 802875c:	0802885f 	.word	0x0802885f
+ 8028760:	08028a7b 	.word	0x08028a7b
+ 8028764:	08028a7b 	.word	0x08028a7b
+ 8028768:	08028a7b 	.word	0x08028a7b
+ 802876c:	08028a7b 	.word	0x08028a7b
+ 8028770:	08028a7b 	.word	0x08028a7b
+ 8028774:	08028a7b 	.word	0x08028a7b
+ 8028778:	08028a7b 	.word	0x08028a7b
+ 802877c:	080289cb 	.word	0x080289cb
+ 8028780:	08028a7b 	.word	0x08028a7b
+ 8028784:	08028a7b 	.word	0x08028a7b
+ 8028788:	08028a7b 	.word	0x08028a7b
+ 802878c:	08028a7b 	.word	0x08028a7b
+ 8028790:	08028a7b 	.word	0x08028a7b
+ 8028794:	08028a7b 	.word	0x08028a7b
+ 8028798:	08028a7b 	.word	0x08028a7b
+ 802879c:	08028a7b 	.word	0x08028a7b
+ 80287a0:	08028a7b 	.word	0x08028a7b
+ 80287a4:	08028a7b 	.word	0x08028a7b
+ 80287a8:	08028a7b 	.word	0x08028a7b
+ 80287ac:	080289ff 	.word	0x080289ff
+ 80287b0:	08028a7b 	.word	0x08028a7b
+ 80287b4:	0802880b 	.word	0x0802880b
+ 80287b8:	08028a7b 	.word	0x08028a7b
+ 80287bc:	08028a7b 	.word	0x08028a7b
+ 80287c0:	08028a7b 	.word	0x08028a7b
+ 80287c4:	08028a7b 	.word	0x08028a7b
+ 80287c8:	08028a7b 	.word	0x08028a7b
+ 80287cc:	08028a7b 	.word	0x08028a7b
+ 80287d0:	08028819 	.word	0x08028819
+ 80287d4:	08028a7b 	.word	0x08028a7b
+ 80287d8:	080287ef 	.word	0x080287ef
+ 80287dc:	080287fd 	.word	0x080287fd
+	{
+
+		case 24672:
+			TT_Motor[ID_A_T_A]->Cont_Posi_Suc = 1;
+ 80287e0:	4a53      	ldr	r2, [pc, #332]	@ (8028930 <TT_Analytic_Fun+0x2f8>)
+ 80287e2:	687b      	ldr	r3, [r7, #4]
+ 80287e4:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
+ 80287e8:	2201      	movs	r2, #1
+ 80287ea:	61da      	str	r2, [r3, #28]
+			break;
+ 80287ec:	e15f      	b.n	8028aae <TT_Analytic_Fun+0x476>
+		case 24707:
+			TT_Motor[ID_A_T_A]->Acc_Suc = 1;
+ 80287ee:	4a50      	ldr	r2, [pc, #320]	@ (8028930 <TT_Analytic_Fun+0x2f8>)
+ 80287f0:	687b      	ldr	r3, [r7, #4]
+ 80287f2:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
+ 80287f6:	2201      	movs	r2, #1
+ 80287f8:	621a      	str	r2, [r3, #32]
+			break;
+ 80287fa:	e158      	b.n	8028aae <TT_Analytic_Fun+0x476>
+		case 24708:
+			TT_Motor[ID_A_T_A]->Dec_Suc = 1;
+ 80287fc:	4a4c      	ldr	r2, [pc, #304]	@ (8028930 <TT_Analytic_Fun+0x2f8>)
+ 80287fe:	687b      	ldr	r3, [r7, #4]
+ 8028800:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
+ 8028804:	2201      	movs	r2, #1
+ 8028806:	625a      	str	r2, [r3, #36]	@ 0x24
+			break;
+ 8028808:	e151      	b.n	8028aae <TT_Analytic_Fun+0x476>
+		case 24698:
+			TT_Motor[ID_A_T_A]->Target_Posi_Suc = 1;
+ 802880a:	4a49      	ldr	r2, [pc, #292]	@ (8028930 <TT_Analytic_Fun+0x2f8>)
+ 802880c:	687b      	ldr	r3, [r7, #4]
+ 802880e:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
+ 8028812:	2201      	movs	r2, #1
+ 8028814:	629a      	str	r2, [r3, #40]	@ 0x28
+			break;
+ 8028816:	e14a      	b.n	8028aae <TT_Analytic_Fun+0x476>
+		case 24705:
+			TT_Motor[ID_A_T_A]->Run_Speed_Suc = 1;
+ 8028818:	4a45      	ldr	r2, [pc, #276]	@ (8028930 <TT_Analytic_Fun+0x2f8>)
+ 802881a:	687b      	ldr	r3, [r7, #4]
+ 802881c:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
+ 8028820:	2201      	movs	r2, #1
+ 8028822:	62da      	str	r2, [r3, #44]	@ 0x2c
+			break;
+ 8028824:	e143      	b.n	8028aae <TT_Analytic_Fun+0x476>
+		case 24640:
+			TT_Motor[ID_A_T_A]->Clear_Suc = 1;
+ 8028826:	4a42      	ldr	r2, [pc, #264]	@ (8028930 <TT_Analytic_Fun+0x2f8>)
+ 8028828:	687b      	ldr	r3, [r7, #4]
+ 802882a:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
+ 802882e:	2201      	movs	r2, #1
+ 8028830:	631a      	str	r2, [r3, #48]	@ 0x30
+			break;
+ 8028832:	e13c      	b.n	8028aae <TT_Analytic_Fun+0x476>
+		case 8220:
+			TT_Motor[ID_A_T_A]->Acc_Suc_Speed = 1;
+ 8028834:	4a3e      	ldr	r2, [pc, #248]	@ (8028930 <TT_Analytic_Fun+0x2f8>)
+ 8028836:	687b      	ldr	r3, [r7, #4]
+ 8028838:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
+ 802883c:	2201      	movs	r2, #1
+ 802883e:	639a      	str	r2, [r3, #56]	@ 0x38
+			break;
+ 8028840:	e135      	b.n	8028aae <TT_Analytic_Fun+0x476>
+		case 24831:
+			TT_Motor[ID_A_T_A]->Suc_Speed_S = 1;
+ 8028842:	4a3b      	ldr	r2, [pc, #236]	@ (8028930 <TT_Analytic_Fun+0x2f8>)
+ 8028844:	687b      	ldr	r3, [r7, #4]
+ 8028846:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
+ 802884a:	2201      	movs	r2, #1
+ 802884c:	641a      	str	r2, [r3, #64]	@ 0x40
+			break;
+ 802884e:	e12e      	b.n	8028aae <TT_Analytic_Fun+0x476>
+		case 8221:
+			TT_Motor[ID_A_T_A]->Dec_Suc_Speed = 1;
+ 8028850:	4a37      	ldr	r2, [pc, #220]	@ (8028930 <TT_Analytic_Fun+0x2f8>)
+ 8028852:	687b      	ldr	r3, [r7, #4]
+ 8028854:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
+ 8028858:	2201      	movs	r2, #1
+ 802885a:	63da      	str	r2, [r3, #60]	@ 0x3c
+			break;
+ 802885c:	e127      	b.n	8028aae <TT_Analytic_Fun+0x476>
+		case 24676:
+		{
+			TT_Motor[ID_A_T_A]->Real_Position = (int) (buffer[4]
+ 802885e:	683b      	ldr	r3, [r7, #0]
+ 8028860:	3304      	adds	r3, #4
+ 8028862:	781b      	ldrb	r3, [r3, #0]
+ 8028864:	461a      	mov	r2, r3
+			        | (buffer[5]) << 8 | (buffer[6]) << 16 | (buffer[7] << 24));
+ 8028866:	683b      	ldr	r3, [r7, #0]
+ 8028868:	3305      	adds	r3, #5
+ 802886a:	781b      	ldrb	r3, [r3, #0]
+ 802886c:	021b      	lsls	r3, r3, #8
+ 802886e:	431a      	orrs	r2, r3
+ 8028870:	683b      	ldr	r3, [r7, #0]
+ 8028872:	3306      	adds	r3, #6
+ 8028874:	781b      	ldrb	r3, [r3, #0]
+ 8028876:	041b      	lsls	r3, r3, #16
+ 8028878:	ea42 0103 	orr.w	r1, r2, r3
+ 802887c:	683b      	ldr	r3, [r7, #0]
+ 802887e:	3307      	adds	r3, #7
+ 8028880:	781b      	ldrb	r3, [r3, #0]
+ 8028882:	061a      	lsls	r2, r3, #24
+			TT_Motor[ID_A_T_A]->Real_Position = (int) (buffer[4]
+ 8028884:	482a      	ldr	r0, [pc, #168]	@ (8028930 <TT_Analytic_Fun+0x2f8>)
+ 8028886:	687b      	ldr	r3, [r7, #4]
+ 8028888:	f850 3023 	ldr.w	r3, [r0, r3, lsl #2]
+ 802888c:	430a      	orrs	r2, r1
+ 802888e:	635a      	str	r2, [r3, #52]	@ 0x34
+			if (TT_Motor[ID_A_T_A]->Start_Measuring == 1)
+ 8028890:	4a27      	ldr	r2, [pc, #156]	@ (8028930 <TT_Analytic_Fun+0x2f8>)
+ 8028892:	687b      	ldr	r3, [r7, #4]
+ 8028894:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
+ 8028898:	6e9b      	ldr	r3, [r3, #104]	@ 0x68
+ 802889a:	2b01      	cmp	r3, #1
+ 802889c:	d120      	bne.n	80288e0 <TT_Analytic_Fun+0x2a8>
+			{
+				TT_Motor[ID_A_T_A]->Start_Measuring =0;
+ 802889e:	4a24      	ldr	r2, [pc, #144]	@ (8028930 <TT_Analytic_Fun+0x2f8>)
+ 80288a0:	687b      	ldr	r3, [r7, #4]
+ 80288a2:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
+ 80288a6:	2200      	movs	r2, #0
+ 80288a8:	669a      	str	r2, [r3, #104]	@ 0x68
+				TT_Motor[ID_A_T_A]->Number_Of_Rounds=0;
+ 80288aa:	4a21      	ldr	r2, [pc, #132]	@ (8028930 <TT_Analytic_Fun+0x2f8>)
+ 80288ac:	687b      	ldr	r3, [r7, #4]
+ 80288ae:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
+ 80288b2:	2200      	movs	r2, #0
+ 80288b4:	651a      	str	r2, [r3, #80]	@ 0x50
+
+				TT_Motor[ID_A_T_A]->Start_Measuring_Position=TT_Motor[ID_A_T_A]->Real_Position;
+ 80288b6:	4a1e      	ldr	r2, [pc, #120]	@ (8028930 <TT_Analytic_Fun+0x2f8>)
+ 80288b8:	687b      	ldr	r3, [r7, #4]
+ 80288ba:	f852 2023 	ldr.w	r2, [r2, r3, lsl #2]
+ 80288be:	491c      	ldr	r1, [pc, #112]	@ (8028930 <TT_Analytic_Fun+0x2f8>)
+ 80288c0:	687b      	ldr	r3, [r7, #4]
+ 80288c2:	f851 3023 	ldr.w	r3, [r1, r3, lsl #2]
+ 80288c6:	6b52      	ldr	r2, [r2, #52]	@ 0x34
+ 80288c8:	655a      	str	r2, [r3, #84]	@ 0x54
+				TT_Motor[ID_A_T_A]->Last_Real_Position=TT_Motor[ID_A_T_A]->Real_Position;
+ 80288ca:	4a19      	ldr	r2, [pc, #100]	@ (8028930 <TT_Analytic_Fun+0x2f8>)
+ 80288cc:	687b      	ldr	r3, [r7, #4]
+ 80288ce:	f852 2023 	ldr.w	r2, [r2, r3, lsl #2]
+ 80288d2:	4917      	ldr	r1, [pc, #92]	@ (8028930 <TT_Analytic_Fun+0x2f8>)
+ 80288d4:	687b      	ldr	r3, [r7, #4]
+ 80288d6:	f851 3023 	ldr.w	r3, [r1, r3, lsl #2]
+ 80288da:	6b52      	ldr	r2, [r2, #52]	@ 0x34
+ 80288dc:	659a      	str	r2, [r3, #88]	@ 0x58
+ 80288de:	e034      	b.n	802894a <TT_Analytic_Fun+0x312>
+			}
+			else
+			{
+				if (abs(
+				        TT_Motor[ID_A_T_A]->Real_Position
+ 80288e0:	4a13      	ldr	r2, [pc, #76]	@ (8028930 <TT_Analytic_Fun+0x2f8>)
+ 80288e2:	687b      	ldr	r3, [r7, #4]
+ 80288e4:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
+ 80288e8:	6b5a      	ldr	r2, [r3, #52]	@ 0x34
+				                - TT_Motor[ID_A_T_A]->Last_Real_Position)
+ 80288ea:	4911      	ldr	r1, [pc, #68]	@ (8028930 <TT_Analytic_Fun+0x2f8>)
+ 80288ec:	687b      	ldr	r3, [r7, #4]
+ 80288ee:	f851 3023 	ldr.w	r3, [r1, r3, lsl #2]
+ 80288f2:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
+ 80288f4:	1ad3      	subs	r3, r2, r3
+				if (abs(
+ 80288f6:	2b00      	cmp	r3, #0
+ 80288f8:	bfb8      	it	lt
+ 80288fa:	425b      	neglt	r3, r3
+ 80288fc:	f247 522f 	movw	r2, #29999	@ 0x752f
+ 8028900:	4293      	cmp	r3, r2
+ 8028902:	dd22      	ble.n	802894a <TT_Analytic_Fun+0x312>
+				        >= 30000)
+				{
+					if (TT_Motor[ID_A_T_A]->Real_Position > 0)
+ 8028904:	4a0a      	ldr	r2, [pc, #40]	@ (8028930 <TT_Analytic_Fun+0x2f8>)
+ 8028906:	687b      	ldr	r3, [r7, #4]
+ 8028908:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
+ 802890c:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
+ 802890e:	2b00      	cmp	r3, #0
+ 8028910:	dd10      	ble.n	8028934 <TT_Analytic_Fun+0x2fc>
+					{
+						TT_Motor[ID_A_T_A]->Number_Of_Rounds -= 1;
+ 8028912:	4a07      	ldr	r2, [pc, #28]	@ (8028930 <TT_Analytic_Fun+0x2f8>)
+ 8028914:	687b      	ldr	r3, [r7, #4]
+ 8028916:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
+ 802891a:	6d1a      	ldr	r2, [r3, #80]	@ 0x50
+ 802891c:	4904      	ldr	r1, [pc, #16]	@ (8028930 <TT_Analytic_Fun+0x2f8>)
+ 802891e:	687b      	ldr	r3, [r7, #4]
+ 8028920:	f851 3023 	ldr.w	r3, [r1, r3, lsl #2]
+ 8028924:	3a01      	subs	r2, #1
+ 8028926:	651a      	str	r2, [r3, #80]	@ 0x50
+ 8028928:	e00f      	b.n	802894a <TT_Analytic_Fun+0x312>
+ 802892a:	bf00      	nop
+ 802892c:	ffff9fc0 	.word	0xffff9fc0
+ 8028930:	24000290 	.word	0x24000290
+					}
+					else
+					{
+						TT_Motor[ID_A_T_A]->Number_Of_Rounds += 1;
+ 8028934:	4a68      	ldr	r2, [pc, #416]	@ (8028ad8 <TT_Analytic_Fun+0x4a0>)
+ 8028936:	687b      	ldr	r3, [r7, #4]
+ 8028938:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
+ 802893c:	6d1a      	ldr	r2, [r3, #80]	@ 0x50
+ 802893e:	4966      	ldr	r1, [pc, #408]	@ (8028ad8 <TT_Analytic_Fun+0x4a0>)
+ 8028940:	687b      	ldr	r3, [r7, #4]
+ 8028942:	f851 3023 	ldr.w	r3, [r1, r3, lsl #2]
+ 8028946:	3201      	adds	r2, #1
+ 8028948:	651a      	str	r2, [r3, #80]	@ 0x50
+					}
+				}
+			}
+
+			TT_Motor[ID_A_T_A]->Last_Real_Position =
+			        TT_Motor[ID_A_T_A]->Real_Position;
+ 802894a:	4a63      	ldr	r2, [pc, #396]	@ (8028ad8 <TT_Analytic_Fun+0x4a0>)
+ 802894c:	687b      	ldr	r3, [r7, #4]
+ 802894e:	f852 2023 	ldr.w	r2, [r2, r3, lsl #2]
+			TT_Motor[ID_A_T_A]->Last_Real_Position =
+ 8028952:	4961      	ldr	r1, [pc, #388]	@ (8028ad8 <TT_Analytic_Fun+0x4a0>)
+ 8028954:	687b      	ldr	r3, [r7, #4]
+ 8028956:	f851 3023 	ldr.w	r3, [r1, r3, lsl #2]
+			        TT_Motor[ID_A_T_A]->Real_Position;
+ 802895a:	6b52      	ldr	r2, [r2, #52]	@ 0x34
+			TT_Motor[ID_A_T_A]->Last_Real_Position =
+ 802895c:	659a      	str	r2, [r3, #88]	@ 0x58
+
+			double CircleLength = 3.14 * 280/1000 ; //pi*d //m
+ 802895e:	a358      	add	r3, pc, #352	@ (adr r3, 8028ac0 <TT_Analytic_Fun+0x488>)
+ 8028960:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 8028964:	e9c7 2304 	strd	r2, r3, [r7, #16]
+
+			double _tempDeltCounts = TT_Motor[ID_A_T_A]->Real_Position
+ 8028968:	4a5b      	ldr	r2, [pc, #364]	@ (8028ad8 <TT_Analytic_Fun+0x4a0>)
+ 802896a:	687b      	ldr	r3, [r7, #4]
+ 802896c:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
+ 8028970:	6b5a      	ldr	r2, [r3, #52]	@ 0x34
+			        - TT_Motor[ID_A_T_A]->Start_Measuring_Position;
+ 8028972:	4959      	ldr	r1, [pc, #356]	@ (8028ad8 <TT_Analytic_Fun+0x4a0>)
+ 8028974:	687b      	ldr	r3, [r7, #4]
+ 8028976:	f851 3023 	ldr.w	r3, [r1, r3, lsl #2]
+ 802897a:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
+ 802897c:	1ad3      	subs	r3, r2, r3
+			double _tempDeltCounts = TT_Motor[ID_A_T_A]->Real_Position
+ 802897e:	ee07 3a90 	vmov	s15, r3
+ 8028982:	eeb8 7be7 	vcvt.f64.s32	d7, s15
+ 8028986:	ed87 7b02 	vstr	d7, [r7, #8]
+			TT_Motor[ID_A_T_A]->Real_Disatnce = (_tempDeltCounts/ 32768/101
+ 802898a:	ed97 6b02 	vldr	d6, [r7, #8]
+ 802898e:	ed9f 5b4e 	vldr	d5, [pc, #312]	@ 8028ac8 <TT_Analytic_Fun+0x490>
+ 8028992:	ee86 7b05 	vdiv.f64	d7, d6, d5
+ 8028996:	ed9f 5b4e 	vldr	d5, [pc, #312]	@ 8028ad0 <TT_Analytic_Fun+0x498>
+ 802899a:	ee87 6b05 	vdiv.f64	d6, d7, d5
+			        + (double) TT_Motor[ID_A_T_A]->Number_Of_Rounds
+ 802899e:	4a4e      	ldr	r2, [pc, #312]	@ (8028ad8 <TT_Analytic_Fun+0x4a0>)
+ 80289a0:	687b      	ldr	r3, [r7, #4]
+ 80289a2:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
+ 80289a6:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
+ 80289a8:	ee07 3a90 	vmov	s15, r3
+ 80289ac:	eeb8 7be7 	vcvt.f64.s32	d7, s15
+ 80289b0:	ee36 6b07 	vadd.f64	d6, d6, d7
+			TT_Motor[ID_A_T_A]->Real_Disatnce = (_tempDeltCounts/ 32768/101
+ 80289b4:	4a48      	ldr	r2, [pc, #288]	@ (8028ad8 <TT_Analytic_Fun+0x4a0>)
+ 80289b6:	687b      	ldr	r3, [r7, #4]
+ 80289b8:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
+			                )
+			        * CircleLength;
+ 80289bc:	ed97 7b04 	vldr	d7, [r7, #16]
+ 80289c0:	ee26 7b07 	vmul.f64	d7, d6, d7
+			TT_Motor[ID_A_T_A]->Real_Disatnce = (_tempDeltCounts/ 32768/101
+ 80289c4:	ed83 7b18 	vstr	d7, [r3, #96]	@ 0x60
+
+		}
+
+			break;
+ 80289c8:	e071      	b.n	8028aae <TT_Analytic_Fun+0x476>
+		case 24684:
+			TT_Motor[ID_A_T_A]->Real_Velcity = (int) (buffer[4]
+ 80289ca:	683b      	ldr	r3, [r7, #0]
+ 80289cc:	3304      	adds	r3, #4
+ 80289ce:	781b      	ldrb	r3, [r3, #0]
+ 80289d0:	461a      	mov	r2, r3
+			        | (buffer[5]) << 8 | (buffer[6]) << 16 | (buffer[7] << 24));
+ 80289d2:	683b      	ldr	r3, [r7, #0]
+ 80289d4:	3305      	adds	r3, #5
+ 80289d6:	781b      	ldrb	r3, [r3, #0]
+ 80289d8:	021b      	lsls	r3, r3, #8
+ 80289da:	431a      	orrs	r2, r3
+ 80289dc:	683b      	ldr	r3, [r7, #0]
+ 80289de:	3306      	adds	r3, #6
+ 80289e0:	781b      	ldrb	r3, [r3, #0]
+ 80289e2:	041b      	lsls	r3, r3, #16
+ 80289e4:	ea42 0103 	orr.w	r1, r2, r3
+ 80289e8:	683b      	ldr	r3, [r7, #0]
+ 80289ea:	3307      	adds	r3, #7
+ 80289ec:	781b      	ldrb	r3, [r3, #0]
+ 80289ee:	061a      	lsls	r2, r3, #24
+			TT_Motor[ID_A_T_A]->Real_Velcity = (int) (buffer[4]
+ 80289f0:	4839      	ldr	r0, [pc, #228]	@ (8028ad8 <TT_Analytic_Fun+0x4a0>)
+ 80289f2:	687b      	ldr	r3, [r7, #4]
+ 80289f4:	f850 3023 	ldr.w	r3, [r0, r3, lsl #2]
+ 80289f8:	430a      	orrs	r2, r1
+ 80289fa:	60da      	str	r2, [r3, #12]
+			break;
+ 80289fc:	e057      	b.n	8028aae <TT_Analytic_Fun+0x476>
+
+		case 24696:
+			TT_Motor[ID_A_T_A]->Real_Current = (int) (buffer[4]
+ 80289fe:	683b      	ldr	r3, [r7, #0]
+ 8028a00:	3304      	adds	r3, #4
+ 8028a02:	781b      	ldrb	r3, [r3, #0]
+ 8028a04:	461a      	mov	r2, r3
+			        | (buffer[5]) << 8 | (buffer[6]) << 16 | (buffer[7] << 24)); //0.1A
+ 8028a06:	683b      	ldr	r3, [r7, #0]
+ 8028a08:	3305      	adds	r3, #5
+ 8028a0a:	781b      	ldrb	r3, [r3, #0]
+ 8028a0c:	021b      	lsls	r3, r3, #8
+ 8028a0e:	431a      	orrs	r2, r3
+ 8028a10:	683b      	ldr	r3, [r7, #0]
+ 8028a12:	3306      	adds	r3, #6
+ 8028a14:	781b      	ldrb	r3, [r3, #0]
+ 8028a16:	041b      	lsls	r3, r3, #16
+ 8028a18:	ea42 0103 	orr.w	r1, r2, r3
+ 8028a1c:	683b      	ldr	r3, [r7, #0]
+ 8028a1e:	3307      	adds	r3, #7
+ 8028a20:	781b      	ldrb	r3, [r3, #0]
+ 8028a22:	061a      	lsls	r2, r3, #24
+			TT_Motor[ID_A_T_A]->Real_Current = (int) (buffer[4]
+ 8028a24:	482c      	ldr	r0, [pc, #176]	@ (8028ad8 <TT_Analytic_Fun+0x4a0>)
+ 8028a26:	687b      	ldr	r3, [r7, #4]
+ 8028a28:	f850 3023 	ldr.w	r3, [r0, r3, lsl #2]
+ 8028a2c:	430a      	orrs	r2, r1
+ 8028a2e:	605a      	str	r2, [r3, #4]
+			break;
+ 8028a30:	e03d      	b.n	8028aae <TT_Analytic_Fun+0x476>
+		case 12298://0x3001
+			TT_Motor[ID_A_T_A]->TT_Motor_Fault = (int) (buffer[4]
+ 8028a32:	683b      	ldr	r3, [r7, #0]
+ 8028a34:	3304      	adds	r3, #4
+ 8028a36:	781b      	ldrb	r3, [r3, #0]
+ 8028a38:	461a      	mov	r2, r3
+			        | (buffer[5]) << 8 | (buffer[6]) << 16 | (buffer[7] << 24));
+ 8028a3a:	683b      	ldr	r3, [r7, #0]
+ 8028a3c:	3305      	adds	r3, #5
+ 8028a3e:	781b      	ldrb	r3, [r3, #0]
+ 8028a40:	021b      	lsls	r3, r3, #8
+ 8028a42:	431a      	orrs	r2, r3
+ 8028a44:	683b      	ldr	r3, [r7, #0]
+ 8028a46:	3306      	adds	r3, #6
+ 8028a48:	781b      	ldrb	r3, [r3, #0]
+ 8028a4a:	041b      	lsls	r3, r3, #16
+ 8028a4c:	ea42 0103 	orr.w	r1, r2, r3
+ 8028a50:	683b      	ldr	r3, [r7, #0]
+ 8028a52:	3307      	adds	r3, #7
+ 8028a54:	781b      	ldrb	r3, [r3, #0]
+ 8028a56:	061a      	lsls	r2, r3, #24
+			TT_Motor[ID_A_T_A]->TT_Motor_Fault = (int) (buffer[4]
+ 8028a58:	481f      	ldr	r0, [pc, #124]	@ (8028ad8 <TT_Analytic_Fun+0x4a0>)
+ 8028a5a:	687b      	ldr	r3, [r7, #4]
+ 8028a5c:	f850 3023 	ldr.w	r3, [r0, r3, lsl #2]
+ 8028a60:	430a      	orrs	r2, r1
+ 8028a62:	645a      	str	r2, [r3, #68]	@ 0x44
+
+			*Motor_ID_Errors[ID_A_T_A] = TT_Motor[ID_A_T_A]->TT_Motor_Fault;
+ 8028a64:	4a1c      	ldr	r2, [pc, #112]	@ (8028ad8 <TT_Analytic_Fun+0x4a0>)
+ 8028a66:	687b      	ldr	r3, [r7, #4]
+ 8028a68:	f852 2023 	ldr.w	r2, [r2, r3, lsl #2]
+ 8028a6c:	491b      	ldr	r1, [pc, #108]	@ (8028adc <TT_Analytic_Fun+0x4a4>)
+ 8028a6e:	687b      	ldr	r3, [r7, #4]
+ 8028a70:	f851 3023 	ldr.w	r3, [r1, r3, lsl #2]
+ 8028a74:	6c52      	ldr	r2, [r2, #68]	@ 0x44
+ 8028a76:	601a      	str	r2, [r3, #0]
+			break;
+ 8028a78:	e019      	b.n	8028aae <TT_Analytic_Fun+0x476>
+
+		default:
+			if ((buffer[0] == (0XAA)) | (buffer[1] == (0XBB)))
+ 8028a7a:	683b      	ldr	r3, [r7, #0]
+ 8028a7c:	781b      	ldrb	r3, [r3, #0]
+ 8028a7e:	2baa      	cmp	r3, #170	@ 0xaa
+ 8028a80:	bf0c      	ite	eq
+ 8028a82:	2301      	moveq	r3, #1
+ 8028a84:	2300      	movne	r3, #0
+ 8028a86:	b2da      	uxtb	r2, r3
+ 8028a88:	683b      	ldr	r3, [r7, #0]
+ 8028a8a:	3301      	adds	r3, #1
+ 8028a8c:	781b      	ldrb	r3, [r3, #0]
+ 8028a8e:	2bbb      	cmp	r3, #187	@ 0xbb
+ 8028a90:	bf0c      	ite	eq
+ 8028a92:	2301      	moveq	r3, #1
+ 8028a94:	2300      	movne	r3, #0
+ 8028a96:	b2db      	uxtb	r3, r3
+ 8028a98:	4313      	orrs	r3, r2
+ 8028a9a:	b2db      	uxtb	r3, r3
+ 8028a9c:	2b00      	cmp	r3, #0
+ 8028a9e:	d005      	beq.n	8028aac <TT_Analytic_Fun+0x474>
+			{
+				TT_Motor[ID_A_T_A]->Act_Suc = 1;
+ 8028aa0:	4a0d      	ldr	r2, [pc, #52]	@ (8028ad8 <TT_Analytic_Fun+0x4a0>)
+ 8028aa2:	687b      	ldr	r3, [r7, #4]
+ 8028aa4:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
+ 8028aa8:	2201      	movs	r2, #1
+ 8028aaa:	619a      	str	r2, [r3, #24]
+			}
+			break;
+ 8028aac:	bf00      	nop
+	}
+}
+ 8028aae:	bf00      	nop
+ 8028ab0:	3724      	adds	r7, #36	@ 0x24
+ 8028ab2:	46bd      	mov	sp, r7
+ 8028ab4:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8028ab8:	4770      	bx	lr
+ 8028aba:	bf00      	nop
+ 8028abc:	f3af 8000 	nop.w
+ 8028ac0:	09d49519 	.word	0x09d49519
+ 8028ac4:	3fec2268 	.word	0x3fec2268
+ 8028ac8:	00000000 	.word	0x00000000
+ 8028acc:	40e00000 	.word	0x40e00000
+ 8028ad0:	00000000 	.word	0x00000000
+ 8028ad4:	40594000 	.word	0x40594000
+ 8028ad8:	24000290 	.word	0x24000290
+ 8028adc:	2400026c 	.word	0x2400026c
+
+08028ae0 <WH_LTE_7S0_intialize>:
+void NormalState()
+{
+	HAL_GPIO_WritePin(S0_RESET_GPIO_Port, S0_RESET_Pin, GPIO_PIN_SET);
+}
+void WH_LTE_7S0_intialize(struct UARTHandler *Handler)
+{
+ 8028ae0:	b580      	push	{r7, lr}
+ 8028ae2:	b082      	sub	sp, #8
+ 8028ae4:	af00      	add	r7, sp, #0
+ 8028ae6:	6078      	str	r0, [r7, #4]
+	//NormalState();
+	HAL_GPIO_WritePin(S0_RESET_GPIO_Port, GPIO_PIN_10, GPIO_PIN_SET);
+ 8028ae8:	2201      	movs	r2, #1
+ 8028aea:	f44f 6180 	mov.w	r1, #1024	@ 0x400
+ 8028aee:	4824      	ldr	r0, [pc, #144]	@ (8028b80 <WH_LTE_7S0_intialize+0xa0>)
+ 8028af0:	f00e ff24 	bl	803793c <HAL_GPIO_WritePin>
+	wh_LTE_7S0_Handler = Handler;
+ 8028af4:	4a23      	ldr	r2, [pc, #140]	@ (8028b84 <WH_LTE_7S0_intialize+0xa4>)
+ 8028af6:	687b      	ldr	r3, [r7, #4]
+ 8028af8:	6013      	str	r3, [r2, #0]
+	wh_LTE_7S0_Handler->Wait_time = 40; //  最低不要低于4；
+ 8028afa:	4b22      	ldr	r3, [pc, #136]	@ (8028b84 <WH_LTE_7S0_intialize+0xa4>)
+ 8028afc:	681b      	ldr	r3, [r3, #0]
+ 8028afe:	2228      	movs	r2, #40	@ 0x28
+ 8028b00:	609a      	str	r2, [r3, #8]
+	wh_LTE_7S0_dispacher=Handler->dispacherController;
+ 8028b02:	687b      	ldr	r3, [r7, #4]
+ 8028b04:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8028b08:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 8028b0a:	4a1f      	ldr	r2, [pc, #124]	@ (8028b88 <WH_LTE_7S0_intialize+0xa8>)
+ 8028b0c:	6013      	str	r3, [r2, #0]
+	//不周期性发送
+	wh_LTE_7S0_dispacher->Dispacher_Enable=1;
+ 8028b0e:	4b1e      	ldr	r3, [pc, #120]	@ (8028b88 <WH_LTE_7S0_intialize+0xa8>)
+ 8028b10:	681b      	ldr	r3, [r3, #0]
+ 8028b12:	2201      	movs	r2, #1
+ 8028b14:	81da      	strh	r2, [r3, #14]
+	wh_LTE_7S0_dispacher->Add_Dispatcher_List(wh_LTE_7S0_dispacher,UpdateGV);
+ 8028b16:	4b1c      	ldr	r3, [pc, #112]	@ (8028b88 <WH_LTE_7S0_intialize+0xa8>)
+ 8028b18:	681b      	ldr	r3, [r3, #0]
+ 8028b1a:	691b      	ldr	r3, [r3, #16]
+ 8028b1c:	4a1a      	ldr	r2, [pc, #104]	@ (8028b88 <WH_LTE_7S0_intialize+0xa8>)
+ 8028b1e:	6812      	ldr	r2, [r2, #0]
+ 8028b20:	491a      	ldr	r1, [pc, #104]	@ (8028b8c <WH_LTE_7S0_intialize+0xac>)
+ 8028b22:	4610      	mov	r0, r2
+ 8028b24:	4798      	blx	r3
+	wh_LTE_7S0_dispacher->DispacherCallTime=1000;
+ 8028b26:	4b18      	ldr	r3, [pc, #96]	@ (8028b88 <WH_LTE_7S0_intialize+0xa8>)
+ 8028b28:	681b      	ldr	r3, [r3, #0]
+ 8028b2a:	f44f 727a 	mov.w	r2, #1000	@ 0x3e8
+ 8028b2e:	815a      	strh	r2, [r3, #10]
+
+
+	LOG("WH_LTE_7S0_intialize");
+ 8028b30:	4b17      	ldr	r3, [pc, #92]	@ (8028b90 <WH_LTE_7S0_intialize+0xb0>)
+ 8028b32:	781b      	ldrb	r3, [r3, #0]
+ 8028b34:	2b03      	cmp	r3, #3
+ 8028b36:	d918      	bls.n	8028b6a <WH_LTE_7S0_intialize+0x8a>
+ 8028b38:	2330      	movs	r3, #48	@ 0x30
+ 8028b3a:	061a      	lsls	r2, r3, #24
+ 8028b3c:	2330      	movs	r3, #48	@ 0x30
+ 8028b3e:	041b      	lsls	r3, r3, #16
+ 8028b40:	431a      	orrs	r2, r3
+ 8028b42:	2330      	movs	r3, #48	@ 0x30
+ 8028b44:	021b      	lsls	r3, r3, #8
+ 8028b46:	4313      	orrs	r3, r2
+ 8028b48:	2230      	movs	r2, #48	@ 0x30
+ 8028b4a:	ea43 0102 	orr.w	r1, r3, r2
+ 8028b4e:	2344      	movs	r3, #68	@ 0x44
+ 8028b50:	061a      	lsls	r2, r3, #24
+ 8028b52:	2346      	movs	r3, #70	@ 0x46
+ 8028b54:	041b      	lsls	r3, r3, #16
+ 8028b56:	431a      	orrs	r2, r3
+ 8028b58:	234c      	movs	r3, #76	@ 0x4c
+ 8028b5a:	021b      	lsls	r3, r3, #8
+ 8028b5c:	4313      	orrs	r3, r2
+ 8028b5e:	2254      	movs	r2, #84	@ 0x54
+ 8028b60:	431a      	orrs	r2, r3
+ 8028b62:	4b0c      	ldr	r3, [pc, #48]	@ (8028b94 <WH_LTE_7S0_intialize+0xb4>)
+ 8028b64:	2004      	movs	r0, #4
+ 8028b66:	f7fd fb65 	bl	8026234 <DLTuc_LogOutVarArgs>
+
+	 wh_LTE_7S0_Handler->UART_Decode = decode_received_data_from_computer; //indicate that there is no need to listen
+ 8028b6a:	4b06      	ldr	r3, [pc, #24]	@ (8028b84 <WH_LTE_7S0_intialize+0xa4>)
+ 8028b6c:	681b      	ldr	r3, [r3, #0]
+ 8028b6e:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8028b72:	461a      	mov	r2, r3
+ 8028b74:	4b08      	ldr	r3, [pc, #32]	@ (8028b98 <WH_LTE_7S0_intialize+0xb8>)
+ 8028b76:	6313      	str	r3, [r2, #48]	@ 0x30
+
+}
+ 8028b78:	bf00      	nop
+ 8028b7a:	3708      	adds	r7, #8
+ 8028b7c:	46bd      	mov	sp, r7
+ 8028b7e:	bd80      	pop	{r7, pc}
+ 8028b80:	58020800 	.word	0x58020800
+ 8028b84:	2400a41c 	.word	0x2400a41c
+ 8028b88:	2400a420 	.word	0x2400a420
+ 8028b8c:	08028b9d 	.word	0x08028b9d
+ 8028b90:	24009110 	.word	0x24009110
+ 8028b94:	08041498 	.word	0x08041498
+ 8028b98:	08028c51 	.word	0x08028c51
+
+08028b9c <UpdateGV>:
+	wh_LTE_7S0_Handler->TxCount = length;
+	wh_LTE_7S0_Handler->UART_Tx(wh_LTE_7S0_Handler);
+
+}
+void UpdateGV()
+{
+ 8028b9c:	b5b0      	push	{r4, r5, r7, lr}
+ 8028b9e:	f5ad 6d86 	sub.w	sp, sp, #1072	@ 0x430
+ 8028ba2:	af00      	add	r7, sp, #0
+
+	pb_ostream_t GV_o_stream =
+ 8028ba4:	f207 431c 	addw	r3, r7, #1052	@ 0x41c
+ 8028ba8:	2200      	movs	r2, #0
+ 8028baa:	601a      	str	r2, [r3, #0]
+ 8028bac:	605a      	str	r2, [r3, #4]
+ 8028bae:	609a      	str	r2, [r3, #8]
+ 8028bb0:	60da      	str	r2, [r3, #12]
+ 8028bb2:	611a      	str	r2, [r3, #16]
+	{ 0 };
+	char buf[1024];
+	GV_o_stream = pb_ostream_from_buffer(buf, sizeof(buf));
+ 8028bb4:	463b      	mov	r3, r7
+ 8028bb6:	f107 011c 	add.w	r1, r7, #28
+ 8028bba:	f44f 6280 	mov.w	r2, #1024	@ 0x400
+ 8028bbe:	4618      	mov	r0, r3
+ 8028bc0:	f7fb fe9c 	bl	80248fc <pb_ostream_from_buffer>
+ 8028bc4:	f507 6386 	add.w	r3, r7, #1072	@ 0x430
+ 8028bc8:	f5a3 6386 	sub.w	r3, r3, #1072	@ 0x430
+ 8028bcc:	f207 441c 	addw	r4, r7, #1052	@ 0x41c
+ 8028bd0:	461d      	mov	r5, r3
+ 8028bd2:	cd0f      	ldmia	r5!, {r0, r1, r2, r3}
+ 8028bd4:	c40f      	stmia	r4!, {r0, r1, r2, r3}
+ 8028bd6:	682b      	ldr	r3, [r5, #0]
+ 8028bd8:	6023      	str	r3, [r4, #0]
+	pb_encode(&GV_o_stream, GV_struct_define_fields, &GV);
+ 8028bda:	f207 431c 	addw	r3, r7, #1052	@ 0x41c
+ 8028bde:	4a19      	ldr	r2, [pc, #100]	@ (8028c44 <UpdateGV+0xa8>)
+ 8028be0:	4919      	ldr	r1, [pc, #100]	@ (8028c48 <UpdateGV+0xac>)
+ 8028be2:	4618      	mov	r0, r3
+ 8028be4:	f7fc faf7 	bl	80251d6 <pb_encode>
+
+
+	memcpy(&wh_LTE_7S0_Handler->Tx_Buf[2], buf, GV_o_stream.bytes_written);
+ 8028be8:	4b18      	ldr	r3, [pc, #96]	@ (8028c4c <UpdateGV+0xb0>)
+ 8028bea:	681b      	ldr	r3, [r3, #0]
+ 8028bec:	f603 0323 	addw	r3, r3, #2083	@ 0x823
+ 8028bf0:	f8d7 2428 	ldr.w	r2, [r7, #1064]	@ 0x428
+ 8028bf4:	f107 011c 	add.w	r1, r7, #28
+ 8028bf8:	4618      	mov	r0, r3
+ 8028bfa:	f017 fbdf 	bl	80403bc <memcpy>
+	wh_LTE_7S0_Handler->Tx_Buf[0]='1';
+ 8028bfe:	4b13      	ldr	r3, [pc, #76]	@ (8028c4c <UpdateGV+0xb0>)
+ 8028c00:	681b      	ldr	r3, [r3, #0]
+ 8028c02:	2231      	movs	r2, #49	@ 0x31
+ 8028c04:	f883 2821 	strb.w	r2, [r3, #2081]	@ 0x821
+	wh_LTE_7S0_Handler->Tx_Buf[1]=',';
+ 8028c08:	4b10      	ldr	r3, [pc, #64]	@ (8028c4c <UpdateGV+0xb0>)
+ 8028c0a:	681b      	ldr	r3, [r3, #0]
+ 8028c0c:	222c      	movs	r2, #44	@ 0x2c
+ 8028c0e:	f883 2822 	strb.w	r2, [r3, #2082]	@ 0x822
+
+	wh_LTE_7S0_Handler->TxCount = GV_o_stream.bytes_written+2;
+ 8028c12:	f8d7 3428 	ldr.w	r3, [r7, #1064]	@ 0x428
+ 8028c16:	b29a      	uxth	r2, r3
+ 8028c18:	4b0c      	ldr	r3, [pc, #48]	@ (8028c4c <UpdateGV+0xb0>)
+ 8028c1a:	681b      	ldr	r3, [r3, #0]
+ 8028c1c:	3202      	adds	r2, #2
+ 8028c1e:	b292      	uxth	r2, r2
+ 8028c20:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8028c24:	845a      	strh	r2, [r3, #34]	@ 0x22
+	wh_LTE_7S0_Handler->UART_Tx(wh_LTE_7S0_Handler);
+ 8028c26:	4b09      	ldr	r3, [pc, #36]	@ (8028c4c <UpdateGV+0xb0>)
+ 8028c28:	681b      	ldr	r3, [r3, #0]
+ 8028c2a:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8028c2e:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 8028c30:	4a06      	ldr	r2, [pc, #24]	@ (8028c4c <UpdateGV+0xb0>)
+ 8028c32:	6812      	ldr	r2, [r2, #0]
+ 8028c34:	4610      	mov	r0, r2
+ 8028c36:	4798      	blx	r3
+}
+ 8028c38:	bf00      	nop
+ 8028c3a:	f507 6786 	add.w	r7, r7, #1072	@ 0x430
+ 8028c3e:	46bd      	mov	sp, r7
+ 8028c40:	bdb0      	pop	{r4, r5, r7, pc}
+ 8028c42:	bf00      	nop
+ 8028c44:	24000340 	.word	0x24000340
+ 8028c48:	080416a4 	.word	0x080416a4
+ 8028c4c:	2400a41c 	.word	0x2400a41c
+
+08028c50 <decode_received_data_from_computer>:
+
+void decode_received_data_from_computer(uint8_t *buffer, uint16_t length)
+{
+ 8028c50:	b580      	push	{r7, lr}
+ 8028c52:	f5ad 6d81 	sub.w	sp, sp, #1032	@ 0x408
+ 8028c56:	af00      	add	r7, sp, #0
+ 8028c58:	f507 6381 	add.w	r3, r7, #1032	@ 0x408
+ 8028c5c:	f2a3 4304 	subw	r3, r3, #1028	@ 0x404
+ 8028c60:	6018      	str	r0, [r3, #0]
+ 8028c62:	460a      	mov	r2, r1
+ 8028c64:	f507 6381 	add.w	r3, r7, #1032	@ 0x408
+ 8028c68:	f2a3 4306 	subw	r3, r3, #1030	@ 0x406
+ 8028c6c:	801a      	strh	r2, [r3, #0]
+	char buf[1024];
+	memcpy(buf, buffer, length);
+ 8028c6e:	f507 6381 	add.w	r3, r7, #1032	@ 0x408
+ 8028c72:	f2a3 4306 	subw	r3, r3, #1030	@ 0x406
+ 8028c76:	881a      	ldrh	r2, [r3, #0]
+ 8028c78:	f507 6381 	add.w	r3, r7, #1032	@ 0x408
+ 8028c7c:	f2a3 4304 	subw	r3, r3, #1028	@ 0x404
+ 8028c80:	f107 0008 	add.w	r0, r7, #8
+ 8028c84:	6819      	ldr	r1, [r3, #0]
+ 8028c86:	f017 fb99 	bl	80403bc <memcpy>
+	if(buffer[0]=='2'&&buffer[1]==',')
+ 8028c8a:	f507 6381 	add.w	r3, r7, #1032	@ 0x408
+ 8028c8e:	f2a3 4304 	subw	r3, r3, #1028	@ 0x404
+ 8028c92:	681b      	ldr	r3, [r3, #0]
+ 8028c94:	781b      	ldrb	r3, [r3, #0]
+ 8028c96:	2b32      	cmp	r3, #50	@ 0x32
+ 8028c98:	d11a      	bne.n	8028cd0 <decode_received_data_from_computer+0x80>
+ 8028c9a:	f507 6381 	add.w	r3, r7, #1032	@ 0x408
+ 8028c9e:	f2a3 4304 	subw	r3, r3, #1028	@ 0x404
+ 8028ca2:	681b      	ldr	r3, [r3, #0]
+ 8028ca4:	3301      	adds	r3, #1
+ 8028ca6:	781b      	ldrb	r3, [r3, #0]
+ 8028ca8:	2b2c      	cmp	r3, #44	@ 0x2c
+ 8028caa:	d111      	bne.n	8028cd0 <decode_received_data_from_computer+0x80>
+	{
+		//Decode protobuf
+		//decode_command_from_computer(buffer+2,length-2);
+		decode_command_and_feedback(buffer+2,length-2,1,wh_LTE_7S0_Handler);
+ 8028cac:	f507 6381 	add.w	r3, r7, #1032	@ 0x408
+ 8028cb0:	f2a3 4304 	subw	r3, r3, #1028	@ 0x404
+ 8028cb4:	681b      	ldr	r3, [r3, #0]
+ 8028cb6:	1c98      	adds	r0, r3, #2
+ 8028cb8:	f507 6381 	add.w	r3, r7, #1032	@ 0x408
+ 8028cbc:	f2a3 4306 	subw	r3, r3, #1030	@ 0x406
+ 8028cc0:	881b      	ldrh	r3, [r3, #0]
+ 8028cc2:	3b02      	subs	r3, #2
+ 8028cc4:	b299      	uxth	r1, r3
+ 8028cc6:	4b0d      	ldr	r3, [pc, #52]	@ (8028cfc <decode_received_data_from_computer+0xac>)
+ 8028cc8:	681b      	ldr	r3, [r3, #0]
+ 8028cca:	2201      	movs	r2, #1
+ 8028ccc:	f7f9 fc4e 	bl	802256c <decode_command_and_feedback>
+
+	}
+	if(NeedToFeedBackToComputer==1)
+ 8028cd0:	4b0b      	ldr	r3, [pc, #44]	@ (8028d00 <decode_received_data_from_computer+0xb0>)
+ 8028cd2:	781b      	ldrb	r3, [r3, #0]
+ 8028cd4:	2b01      	cmp	r3, #1
+ 8028cd6:	d10c      	bne.n	8028cf2 <decode_received_data_from_computer+0xa2>
+	{
+		send_received_data_to_upper_computer(buffer, length);
+ 8028cd8:	f507 6381 	add.w	r3, r7, #1032	@ 0x408
+ 8028cdc:	f2a3 4306 	subw	r3, r3, #1030	@ 0x406
+ 8028ce0:	881a      	ldrh	r2, [r3, #0]
+ 8028ce2:	f507 6381 	add.w	r3, r7, #1032	@ 0x408
+ 8028ce6:	f2a3 4304 	subw	r3, r3, #1028	@ 0x404
+ 8028cea:	4611      	mov	r1, r2
+ 8028cec:	6818      	ldr	r0, [r3, #0]
+ 8028cee:	f7f9 fce7 	bl	80226c0 <send_received_data_to_upper_computer>
+	}
+
+}
+ 8028cf2:	bf00      	nop
+ 8028cf4:	f507 6781 	add.w	r7, r7, #1032	@ 0x408
+ 8028cf8:	46bd      	mov	sp, r7
+ 8028cfa:	bd80      	pop	{r7, pc}
+ 8028cfc:	2400a41c 	.word	0x2400a41c
+ 8028d00:	24000088 	.word	0x24000088
+
+08028d04 <MX_ADC2_Init>:
+
+ADC_HandleTypeDef hadc2;
+
+/* ADC2 init function */
+void MX_ADC2_Init(void)
+{
+ 8028d04:	b580      	push	{r7, lr}
+ 8028d06:	b088      	sub	sp, #32
+ 8028d08:	af00      	add	r7, sp, #0
+
+  /* USER CODE BEGIN ADC2_Init 0 */
+
+  /* USER CODE END ADC2_Init 0 */
+
+  ADC_ChannelConfTypeDef sConfig = {0};
+ 8028d0a:	1d3b      	adds	r3, r7, #4
+ 8028d0c:	2200      	movs	r2, #0
+ 8028d0e:	601a      	str	r2, [r3, #0]
+ 8028d10:	605a      	str	r2, [r3, #4]
+ 8028d12:	609a      	str	r2, [r3, #8]
+ 8028d14:	60da      	str	r2, [r3, #12]
+ 8028d16:	611a      	str	r2, [r3, #16]
+ 8028d18:	615a      	str	r2, [r3, #20]
+ 8028d1a:	619a      	str	r2, [r3, #24]
+
+  /* USER CODE END ADC2_Init 1 */
+
+  /** Common config
+  */
+  hadc2.Instance = ADC2;
+ 8028d1c:	4b29      	ldr	r3, [pc, #164]	@ (8028dc4 <MX_ADC2_Init+0xc0>)
+ 8028d1e:	4a2a      	ldr	r2, [pc, #168]	@ (8028dc8 <MX_ADC2_Init+0xc4>)
+ 8028d20:	601a      	str	r2, [r3, #0]
+  hadc2.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1;
+ 8028d22:	4b28      	ldr	r3, [pc, #160]	@ (8028dc4 <MX_ADC2_Init+0xc0>)
+ 8028d24:	2200      	movs	r2, #0
+ 8028d26:	605a      	str	r2, [r3, #4]
+  hadc2.Init.Resolution = ADC_RESOLUTION_16B;
+ 8028d28:	4b26      	ldr	r3, [pc, #152]	@ (8028dc4 <MX_ADC2_Init+0xc0>)
+ 8028d2a:	2200      	movs	r2, #0
+ 8028d2c:	609a      	str	r2, [r3, #8]
+  hadc2.Init.ScanConvMode = ADC_SCAN_DISABLE;
+ 8028d2e:	4b25      	ldr	r3, [pc, #148]	@ (8028dc4 <MX_ADC2_Init+0xc0>)
+ 8028d30:	2200      	movs	r2, #0
+ 8028d32:	60da      	str	r2, [r3, #12]
+  hadc2.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
+ 8028d34:	4b23      	ldr	r3, [pc, #140]	@ (8028dc4 <MX_ADC2_Init+0xc0>)
+ 8028d36:	2204      	movs	r2, #4
+ 8028d38:	611a      	str	r2, [r3, #16]
+  hadc2.Init.LowPowerAutoWait = DISABLE;
+ 8028d3a:	4b22      	ldr	r3, [pc, #136]	@ (8028dc4 <MX_ADC2_Init+0xc0>)
+ 8028d3c:	2200      	movs	r2, #0
+ 8028d3e:	751a      	strb	r2, [r3, #20]
+  hadc2.Init.ContinuousConvMode = ENABLE;
+ 8028d40:	4b20      	ldr	r3, [pc, #128]	@ (8028dc4 <MX_ADC2_Init+0xc0>)
+ 8028d42:	2201      	movs	r2, #1
+ 8028d44:	755a      	strb	r2, [r3, #21]
+  hadc2.Init.NbrOfConversion = 1;
+ 8028d46:	4b1f      	ldr	r3, [pc, #124]	@ (8028dc4 <MX_ADC2_Init+0xc0>)
+ 8028d48:	2201      	movs	r2, #1
+ 8028d4a:	619a      	str	r2, [r3, #24]
+  hadc2.Init.DiscontinuousConvMode = DISABLE;
+ 8028d4c:	4b1d      	ldr	r3, [pc, #116]	@ (8028dc4 <MX_ADC2_Init+0xc0>)
+ 8028d4e:	2200      	movs	r2, #0
+ 8028d50:	771a      	strb	r2, [r3, #28]
+  hadc2.Init.ExternalTrigConv = ADC_SOFTWARE_START;
+ 8028d52:	4b1c      	ldr	r3, [pc, #112]	@ (8028dc4 <MX_ADC2_Init+0xc0>)
+ 8028d54:	2200      	movs	r2, #0
+ 8028d56:	625a      	str	r2, [r3, #36]	@ 0x24
+  hadc2.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
+ 8028d58:	4b1a      	ldr	r3, [pc, #104]	@ (8028dc4 <MX_ADC2_Init+0xc0>)
+ 8028d5a:	2200      	movs	r2, #0
+ 8028d5c:	629a      	str	r2, [r3, #40]	@ 0x28
+  hadc2.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR;
+ 8028d5e:	4b19      	ldr	r3, [pc, #100]	@ (8028dc4 <MX_ADC2_Init+0xc0>)
+ 8028d60:	2200      	movs	r2, #0
+ 8028d62:	62da      	str	r2, [r3, #44]	@ 0x2c
+  hadc2.Init.Overrun = ADC_OVR_DATA_PRESERVED;
+ 8028d64:	4b17      	ldr	r3, [pc, #92]	@ (8028dc4 <MX_ADC2_Init+0xc0>)
+ 8028d66:	2200      	movs	r2, #0
+ 8028d68:	631a      	str	r2, [r3, #48]	@ 0x30
+  hadc2.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE;
+ 8028d6a:	4b16      	ldr	r3, [pc, #88]	@ (8028dc4 <MX_ADC2_Init+0xc0>)
+ 8028d6c:	2200      	movs	r2, #0
+ 8028d6e:	635a      	str	r2, [r3, #52]	@ 0x34
+  hadc2.Init.OversamplingMode = DISABLE;
+ 8028d70:	4b14      	ldr	r3, [pc, #80]	@ (8028dc4 <MX_ADC2_Init+0xc0>)
+ 8028d72:	2200      	movs	r2, #0
+ 8028d74:	f883 2038 	strb.w	r2, [r3, #56]	@ 0x38
+  if (HAL_ADC_Init(&hadc2) != HAL_OK)
+ 8028d78:	4812      	ldr	r0, [pc, #72]	@ (8028dc4 <MX_ADC2_Init+0xc0>)
+ 8028d7a:	f008 ffb5 	bl	8031ce8 <HAL_ADC_Init>
+ 8028d7e:	4603      	mov	r3, r0
+ 8028d80:	2b00      	cmp	r3, #0
+ 8028d82:	d001      	beq.n	8028d88 <MX_ADC2_Init+0x84>
+  {
+    Error_Handler();
+ 8028d84:	f006 fe80 	bl	802fa88 <Error_Handler>
+  }
+
+  /** Configure Regular Channel
+  */
+  sConfig.Channel = ADC_CHANNEL_5;
+ 8028d88:	4b10      	ldr	r3, [pc, #64]	@ (8028dcc <MX_ADC2_Init+0xc8>)
+ 8028d8a:	607b      	str	r3, [r7, #4]
+  sConfig.Rank = ADC_REGULAR_RANK_1;
+ 8028d8c:	2306      	movs	r3, #6
+ 8028d8e:	60bb      	str	r3, [r7, #8]
+  sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5;
+ 8028d90:	2300      	movs	r3, #0
+ 8028d92:	60fb      	str	r3, [r7, #12]
+  sConfig.SingleDiff = ADC_SINGLE_ENDED;
+ 8028d94:	f240 73ff 	movw	r3, #2047	@ 0x7ff
+ 8028d98:	613b      	str	r3, [r7, #16]
+  sConfig.OffsetNumber = ADC_OFFSET_NONE;
+ 8028d9a:	2304      	movs	r3, #4
+ 8028d9c:	617b      	str	r3, [r7, #20]
+  sConfig.Offset = 0;
+ 8028d9e:	2300      	movs	r3, #0
+ 8028da0:	61bb      	str	r3, [r7, #24]
+  sConfig.OffsetSignedSaturation = DISABLE;
+ 8028da2:	2300      	movs	r3, #0
+ 8028da4:	777b      	strb	r3, [r7, #29]
+  if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
+ 8028da6:	1d3b      	adds	r3, r7, #4
+ 8028da8:	4619      	mov	r1, r3
+ 8028daa:	4806      	ldr	r0, [pc, #24]	@ (8028dc4 <MX_ADC2_Init+0xc0>)
+ 8028dac:	f009 f93e 	bl	803202c <HAL_ADC_ConfigChannel>
+ 8028db0:	4603      	mov	r3, r0
+ 8028db2:	2b00      	cmp	r3, #0
+ 8028db4:	d001      	beq.n	8028dba <MX_ADC2_Init+0xb6>
+  {
+    Error_Handler();
+ 8028db6:	f006 fe67 	bl	802fa88 <Error_Handler>
+  }
+  /* USER CODE BEGIN ADC2_Init 2 */
+
+  /* USER CODE END ADC2_Init 2 */
+
+}
+ 8028dba:	bf00      	nop
+ 8028dbc:	3720      	adds	r7, #32
+ 8028dbe:	46bd      	mov	sp, r7
+ 8028dc0:	bd80      	pop	{r7, pc}
+ 8028dc2:	bf00      	nop
+ 8028dc4:	2400a424 	.word	0x2400a424
+ 8028dc8:	40022100 	.word	0x40022100
+ 8028dcc:	14f00020 	.word	0x14f00020
+
+08028dd0 <HAL_ADC_MspInit>:
+
+void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle)
+{
+ 8028dd0:	b580      	push	{r7, lr}
+ 8028dd2:	b0ba      	sub	sp, #232	@ 0xe8
+ 8028dd4:	af00      	add	r7, sp, #0
+ 8028dd6:	6078      	str	r0, [r7, #4]
+
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+ 8028dd8:	f107 03d4 	add.w	r3, r7, #212	@ 0xd4
+ 8028ddc:	2200      	movs	r2, #0
+ 8028dde:	601a      	str	r2, [r3, #0]
+ 8028de0:	605a      	str	r2, [r3, #4]
+ 8028de2:	609a      	str	r2, [r3, #8]
+ 8028de4:	60da      	str	r2, [r3, #12]
+ 8028de6:	611a      	str	r2, [r3, #16]
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+ 8028de8:	f107 0310 	add.w	r3, r7, #16
+ 8028dec:	22c0      	movs	r2, #192	@ 0xc0
+ 8028dee:	2100      	movs	r1, #0
+ 8028df0:	4618      	mov	r0, r3
+ 8028df2:	f017 fa79 	bl	80402e8 <memset>
+  if(adcHandle->Instance==ADC2)
+ 8028df6:	687b      	ldr	r3, [r7, #4]
+ 8028df8:	681b      	ldr	r3, [r3, #0]
+ 8028dfa:	4a2c      	ldr	r2, [pc, #176]	@ (8028eac <HAL_ADC_MspInit+0xdc>)
+ 8028dfc:	4293      	cmp	r3, r2
+ 8028dfe:	d150      	bne.n	8028ea2 <HAL_ADC_MspInit+0xd2>
+
+  /* USER CODE END ADC2_MspInit 0 */
+
+  /** Initializes the peripherals clock
+  */
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADC;
+ 8028e00:	f44f 2200 	mov.w	r2, #524288	@ 0x80000
+ 8028e04:	f04f 0300 	mov.w	r3, #0
+ 8028e08:	e9c7 2304 	strd	r2, r3, [r7, #16]
+    PeriphClkInitStruct.PLL2.PLL2M = 25;
+ 8028e0c:	2319      	movs	r3, #25
+ 8028e0e:	61bb      	str	r3, [r7, #24]
+    PeriphClkInitStruct.PLL2.PLL2N = 288;
+ 8028e10:	f44f 7390 	mov.w	r3, #288	@ 0x120
+ 8028e14:	61fb      	str	r3, [r7, #28]
+    PeriphClkInitStruct.PLL2.PLL2P = 4;
+ 8028e16:	2304      	movs	r3, #4
+ 8028e18:	623b      	str	r3, [r7, #32]
+    PeriphClkInitStruct.PLL2.PLL2Q = 1;
+ 8028e1a:	2301      	movs	r3, #1
+ 8028e1c:	627b      	str	r3, [r7, #36]	@ 0x24
+    PeriphClkInitStruct.PLL2.PLL2R = 2;
+ 8028e1e:	2302      	movs	r3, #2
+ 8028e20:	62bb      	str	r3, [r7, #40]	@ 0x28
+    PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_0;
+ 8028e22:	2300      	movs	r3, #0
+ 8028e24:	62fb      	str	r3, [r7, #44]	@ 0x2c
+    PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE;
+ 8028e26:	2300      	movs	r3, #0
+ 8028e28:	633b      	str	r3, [r7, #48]	@ 0x30
+    PeriphClkInitStruct.PLL2.PLL2FRACN = 0;
+ 8028e2a:	2300      	movs	r3, #0
+ 8028e2c:	637b      	str	r3, [r7, #52]	@ 0x34
+    PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_PLL2;
+ 8028e2e:	2300      	movs	r3, #0
+ 8028e30:	f8c7 30b4 	str.w	r3, [r7, #180]	@ 0xb4
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+ 8028e34:	f107 0310 	add.w	r3, r7, #16
+ 8028e38:	4618      	mov	r0, r3
+ 8028e3a:	f011 f923 	bl	803a084 <HAL_RCCEx_PeriphCLKConfig>
+ 8028e3e:	4603      	mov	r3, r0
+ 8028e40:	2b00      	cmp	r3, #0
+ 8028e42:	d001      	beq.n	8028e48 <HAL_ADC_MspInit+0x78>
+    {
+      Error_Handler();
+ 8028e44:	f006 fe20 	bl	802fa88 <Error_Handler>
+    }
+
+    /* ADC2 clock enable */
+    __HAL_RCC_ADC12_CLK_ENABLE();
+ 8028e48:	4b19      	ldr	r3, [pc, #100]	@ (8028eb0 <HAL_ADC_MspInit+0xe0>)
+ 8028e4a:	f8d3 30d8 	ldr.w	r3, [r3, #216]	@ 0xd8
+ 8028e4e:	4a18      	ldr	r2, [pc, #96]	@ (8028eb0 <HAL_ADC_MspInit+0xe0>)
+ 8028e50:	f043 0320 	orr.w	r3, r3, #32
+ 8028e54:	f8c2 30d8 	str.w	r3, [r2, #216]	@ 0xd8
+ 8028e58:	4b15      	ldr	r3, [pc, #84]	@ (8028eb0 <HAL_ADC_MspInit+0xe0>)
+ 8028e5a:	f8d3 30d8 	ldr.w	r3, [r3, #216]	@ 0xd8
+ 8028e5e:	f003 0320 	and.w	r3, r3, #32
+ 8028e62:	60fb      	str	r3, [r7, #12]
+ 8028e64:	68fb      	ldr	r3, [r7, #12]
+
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+ 8028e66:	4b12      	ldr	r3, [pc, #72]	@ (8028eb0 <HAL_ADC_MspInit+0xe0>)
+ 8028e68:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
+ 8028e6c:	4a10      	ldr	r2, [pc, #64]	@ (8028eb0 <HAL_ADC_MspInit+0xe0>)
+ 8028e6e:	f043 0302 	orr.w	r3, r3, #2
+ 8028e72:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
+ 8028e76:	4b0e      	ldr	r3, [pc, #56]	@ (8028eb0 <HAL_ADC_MspInit+0xe0>)
+ 8028e78:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
+ 8028e7c:	f003 0302 	and.w	r3, r3, #2
+ 8028e80:	60bb      	str	r3, [r7, #8]
+ 8028e82:	68bb      	ldr	r3, [r7, #8]
+    /**ADC2 GPIO Configuration
+    PB1     ------> ADC2_INP5
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_1;
+ 8028e84:	2302      	movs	r3, #2
+ 8028e86:	f8c7 30d4 	str.w	r3, [r7, #212]	@ 0xd4
+    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+ 8028e8a:	2303      	movs	r3, #3
+ 8028e8c:	f8c7 30d8 	str.w	r3, [r7, #216]	@ 0xd8
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 8028e90:	2300      	movs	r3, #0
+ 8028e92:	f8c7 30dc 	str.w	r3, [r7, #220]	@ 0xdc
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+ 8028e96:	f107 03d4 	add.w	r3, r7, #212	@ 0xd4
+ 8028e9a:	4619      	mov	r1, r3
+ 8028e9c:	4805      	ldr	r0, [pc, #20]	@ (8028eb4 <HAL_ADC_MspInit+0xe4>)
+ 8028e9e:	f00e fb9d 	bl	80375dc <HAL_GPIO_Init>
+
+  /* USER CODE BEGIN ADC2_MspInit 1 */
+
+  /* USER CODE END ADC2_MspInit 1 */
+  }
+}
+ 8028ea2:	bf00      	nop
+ 8028ea4:	37e8      	adds	r7, #232	@ 0xe8
+ 8028ea6:	46bd      	mov	sp, r7
+ 8028ea8:	bd80      	pop	{r7, pc}
+ 8028eaa:	bf00      	nop
+ 8028eac:	40022100 	.word	0x40022100
+ 8028eb0:	58024400 	.word	0x58024400
+ 8028eb4:	58020400 	.word	0x58020400
+
+08028eb8 <MX_DMA_Init>:
+
+/**
+  * Enable DMA controller clock
+  */
+void MX_DMA_Init(void)
+{
+ 8028eb8:	b580      	push	{r7, lr}
+ 8028eba:	b082      	sub	sp, #8
+ 8028ebc:	af00      	add	r7, sp, #0
+
+  /* DMA controller clock enable */
+  __HAL_RCC_DMA1_CLK_ENABLE();
+ 8028ebe:	4b25      	ldr	r3, [pc, #148]	@ (8028f54 <MX_DMA_Init+0x9c>)
+ 8028ec0:	f8d3 30d8 	ldr.w	r3, [r3, #216]	@ 0xd8
+ 8028ec4:	4a23      	ldr	r2, [pc, #140]	@ (8028f54 <MX_DMA_Init+0x9c>)
+ 8028ec6:	f043 0301 	orr.w	r3, r3, #1
+ 8028eca:	f8c2 30d8 	str.w	r3, [r2, #216]	@ 0xd8
+ 8028ece:	4b21      	ldr	r3, [pc, #132]	@ (8028f54 <MX_DMA_Init+0x9c>)
+ 8028ed0:	f8d3 30d8 	ldr.w	r3, [r3, #216]	@ 0xd8
+ 8028ed4:	f003 0301 	and.w	r3, r3, #1
+ 8028ed8:	607b      	str	r3, [r7, #4]
+ 8028eda:	687b      	ldr	r3, [r7, #4]
+
+  /* DMA interrupt init */
+  /* DMA1_Stream0_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 0, 0);
+ 8028edc:	2200      	movs	r2, #0
+ 8028ede:	2100      	movs	r1, #0
+ 8028ee0:	200b      	movs	r0, #11
+ 8028ee2:	f009 fde6 	bl	8032ab2 <HAL_NVIC_SetPriority>
+  HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn);
+ 8028ee6:	200b      	movs	r0, #11
+ 8028ee8:	f009 fdfd 	bl	8032ae6 <HAL_NVIC_EnableIRQ>
+  /* DMA1_Stream1_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Stream1_IRQn, 0, 0);
+ 8028eec:	2200      	movs	r2, #0
+ 8028eee:	2100      	movs	r1, #0
+ 8028ef0:	200c      	movs	r0, #12
+ 8028ef2:	f009 fdde 	bl	8032ab2 <HAL_NVIC_SetPriority>
+  HAL_NVIC_EnableIRQ(DMA1_Stream1_IRQn);
+ 8028ef6:	200c      	movs	r0, #12
+ 8028ef8:	f009 fdf5 	bl	8032ae6 <HAL_NVIC_EnableIRQ>
+  /* DMA1_Stream2_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Stream2_IRQn, 0, 0);
+ 8028efc:	2200      	movs	r2, #0
+ 8028efe:	2100      	movs	r1, #0
+ 8028f00:	200d      	movs	r0, #13
+ 8028f02:	f009 fdd6 	bl	8032ab2 <HAL_NVIC_SetPriority>
+  HAL_NVIC_EnableIRQ(DMA1_Stream2_IRQn);
+ 8028f06:	200d      	movs	r0, #13
+ 8028f08:	f009 fded 	bl	8032ae6 <HAL_NVIC_EnableIRQ>
+  /* DMA1_Stream3_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Stream3_IRQn, 0, 0);
+ 8028f0c:	2200      	movs	r2, #0
+ 8028f0e:	2100      	movs	r1, #0
+ 8028f10:	200e      	movs	r0, #14
+ 8028f12:	f009 fdce 	bl	8032ab2 <HAL_NVIC_SetPriority>
+  HAL_NVIC_EnableIRQ(DMA1_Stream3_IRQn);
+ 8028f16:	200e      	movs	r0, #14
+ 8028f18:	f009 fde5 	bl	8032ae6 <HAL_NVIC_EnableIRQ>
+  /* DMA1_Stream5_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Stream5_IRQn, 0, 0);
+ 8028f1c:	2200      	movs	r2, #0
+ 8028f1e:	2100      	movs	r1, #0
+ 8028f20:	2010      	movs	r0, #16
+ 8028f22:	f009 fdc6 	bl	8032ab2 <HAL_NVIC_SetPriority>
+  HAL_NVIC_EnableIRQ(DMA1_Stream5_IRQn);
+ 8028f26:	2010      	movs	r0, #16
+ 8028f28:	f009 fddd 	bl	8032ae6 <HAL_NVIC_EnableIRQ>
+  /* DMA1_Stream6_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Stream6_IRQn, 0, 0);
+ 8028f2c:	2200      	movs	r2, #0
+ 8028f2e:	2100      	movs	r1, #0
+ 8028f30:	2011      	movs	r0, #17
+ 8028f32:	f009 fdbe 	bl	8032ab2 <HAL_NVIC_SetPriority>
+  HAL_NVIC_EnableIRQ(DMA1_Stream6_IRQn);
+ 8028f36:	2011      	movs	r0, #17
+ 8028f38:	f009 fdd5 	bl	8032ae6 <HAL_NVIC_EnableIRQ>
+  /* DMA1_Stream7_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Stream7_IRQn, 0, 0);
+ 8028f3c:	2200      	movs	r2, #0
+ 8028f3e:	2100      	movs	r1, #0
+ 8028f40:	202f      	movs	r0, #47	@ 0x2f
+ 8028f42:	f009 fdb6 	bl	8032ab2 <HAL_NVIC_SetPriority>
+  HAL_NVIC_EnableIRQ(DMA1_Stream7_IRQn);
+ 8028f46:	202f      	movs	r0, #47	@ 0x2f
+ 8028f48:	f009 fdcd 	bl	8032ae6 <HAL_NVIC_EnableIRQ>
+
+}
+ 8028f4c:	bf00      	nop
+ 8028f4e:	3708      	adds	r7, #8
+ 8028f50:	46bd      	mov	sp, r7
+ 8028f52:	bd80      	pop	{r7, pc}
+ 8028f54:	58024400 	.word	0x58024400
+
+08028f58 <MX_ETH_Init>:
+
+ETH_HandleTypeDef heth;
+
+/* ETH init function */
+void MX_ETH_Init(void)
+{
+ 8028f58:	b580      	push	{r7, lr}
+ 8028f5a:	af00      	add	r7, sp, #0
+   static uint8_t MACAddr[6];
+
+  /* USER CODE BEGIN ETH_Init 1 */
+
+  /* USER CODE END ETH_Init 1 */
+  heth.Instance = ETH;
+ 8028f5c:	4b1e      	ldr	r3, [pc, #120]	@ (8028fd8 <MX_ETH_Init+0x80>)
+ 8028f5e:	4a1f      	ldr	r2, [pc, #124]	@ (8028fdc <MX_ETH_Init+0x84>)
+ 8028f60:	601a      	str	r2, [r3, #0]
+  MACAddr[0] = 0x00;
+ 8028f62:	4b1f      	ldr	r3, [pc, #124]	@ (8028fe0 <MX_ETH_Init+0x88>)
+ 8028f64:	2200      	movs	r2, #0
+ 8028f66:	701a      	strb	r2, [r3, #0]
+  MACAddr[1] = 0x80;
+ 8028f68:	4b1d      	ldr	r3, [pc, #116]	@ (8028fe0 <MX_ETH_Init+0x88>)
+ 8028f6a:	2280      	movs	r2, #128	@ 0x80
+ 8028f6c:	705a      	strb	r2, [r3, #1]
+  MACAddr[2] = 0xE1;
+ 8028f6e:	4b1c      	ldr	r3, [pc, #112]	@ (8028fe0 <MX_ETH_Init+0x88>)
+ 8028f70:	22e1      	movs	r2, #225	@ 0xe1
+ 8028f72:	709a      	strb	r2, [r3, #2]
+  MACAddr[3] = 0x00;
+ 8028f74:	4b1a      	ldr	r3, [pc, #104]	@ (8028fe0 <MX_ETH_Init+0x88>)
+ 8028f76:	2200      	movs	r2, #0
+ 8028f78:	70da      	strb	r2, [r3, #3]
+  MACAddr[4] = 0x00;
+ 8028f7a:	4b19      	ldr	r3, [pc, #100]	@ (8028fe0 <MX_ETH_Init+0x88>)
+ 8028f7c:	2200      	movs	r2, #0
+ 8028f7e:	711a      	strb	r2, [r3, #4]
+  MACAddr[5] = 0x00;
+ 8028f80:	4b17      	ldr	r3, [pc, #92]	@ (8028fe0 <MX_ETH_Init+0x88>)
+ 8028f82:	2200      	movs	r2, #0
+ 8028f84:	715a      	strb	r2, [r3, #5]
+  heth.Init.MACAddr = &MACAddr[0];
+ 8028f86:	4b14      	ldr	r3, [pc, #80]	@ (8028fd8 <MX_ETH_Init+0x80>)
+ 8028f88:	4a15      	ldr	r2, [pc, #84]	@ (8028fe0 <MX_ETH_Init+0x88>)
+ 8028f8a:	605a      	str	r2, [r3, #4]
+  heth.Init.MediaInterface = HAL_ETH_RMII_MODE;
+ 8028f8c:	4b12      	ldr	r3, [pc, #72]	@ (8028fd8 <MX_ETH_Init+0x80>)
+ 8028f8e:	2201      	movs	r2, #1
+ 8028f90:	721a      	strb	r2, [r3, #8]
+  heth.Init.TxDesc = DMATxDscrTab;
+ 8028f92:	4b11      	ldr	r3, [pc, #68]	@ (8028fd8 <MX_ETH_Init+0x80>)
+ 8028f94:	4a13      	ldr	r2, [pc, #76]	@ (8028fe4 <MX_ETH_Init+0x8c>)
+ 8028f96:	60da      	str	r2, [r3, #12]
+  heth.Init.RxDesc = DMARxDscrTab;
+ 8028f98:	4b0f      	ldr	r3, [pc, #60]	@ (8028fd8 <MX_ETH_Init+0x80>)
+ 8028f9a:	4a13      	ldr	r2, [pc, #76]	@ (8028fe8 <MX_ETH_Init+0x90>)
+ 8028f9c:	611a      	str	r2, [r3, #16]
+  heth.Init.RxBuffLen = 1528;
+ 8028f9e:	4b0e      	ldr	r3, [pc, #56]	@ (8028fd8 <MX_ETH_Init+0x80>)
+ 8028fa0:	f44f 62bf 	mov.w	r2, #1528	@ 0x5f8
+ 8028fa4:	615a      	str	r2, [r3, #20]
+
+  /* USER CODE BEGIN MACADDRESS */
+
+  /* USER CODE END MACADDRESS */
+
+  if (HAL_ETH_Init(&heth) != HAL_OK)
+ 8028fa6:	480c      	ldr	r0, [pc, #48]	@ (8028fd8 <MX_ETH_Init+0x80>)
+ 8028fa8:	f00c fc7a 	bl	80358a0 <HAL_ETH_Init>
+ 8028fac:	4603      	mov	r3, r0
+ 8028fae:	2b00      	cmp	r3, #0
+ 8028fb0:	d001      	beq.n	8028fb6 <MX_ETH_Init+0x5e>
+  {
+    Error_Handler();
+ 8028fb2:	f006 fd69 	bl	802fa88 <Error_Handler>
+  }
+
+  memset(&TxConfig, 0 , sizeof(ETH_TxPacketConfig));
+ 8028fb6:	2238      	movs	r2, #56	@ 0x38
+ 8028fb8:	2100      	movs	r1, #0
+ 8028fba:	480c      	ldr	r0, [pc, #48]	@ (8028fec <MX_ETH_Init+0x94>)
+ 8028fbc:	f017 f994 	bl	80402e8 <memset>
+  TxConfig.Attributes = ETH_TX_PACKETS_FEATURES_CSUM | ETH_TX_PACKETS_FEATURES_CRCPAD;
+ 8028fc0:	4b0a      	ldr	r3, [pc, #40]	@ (8028fec <MX_ETH_Init+0x94>)
+ 8028fc2:	2221      	movs	r2, #33	@ 0x21
+ 8028fc4:	601a      	str	r2, [r3, #0]
+  TxConfig.ChecksumCtrl = ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC;
+ 8028fc6:	4b09      	ldr	r3, [pc, #36]	@ (8028fec <MX_ETH_Init+0x94>)
+ 8028fc8:	f44f 3240 	mov.w	r2, #196608	@ 0x30000
+ 8028fcc:	615a      	str	r2, [r3, #20]
+  TxConfig.CRCPadCtrl = ETH_CRC_PAD_INSERT;
+ 8028fce:	4b07      	ldr	r3, [pc, #28]	@ (8028fec <MX_ETH_Init+0x94>)
+ 8028fd0:	2200      	movs	r2, #0
+ 8028fd2:	611a      	str	r2, [r3, #16]
+  /* USER CODE BEGIN ETH_Init 2 */
+
+  /* USER CODE END ETH_Init 2 */
+
+}
+ 8028fd4:	bf00      	nop
+ 8028fd6:	bd80      	pop	{r7, pc}
+ 8028fd8:	2400a4c0 	.word	0x2400a4c0
+ 8028fdc:	40028000 	.word	0x40028000
+ 8028fe0:	2400a570 	.word	0x2400a570
+ 8028fe4:	240001ec 	.word	0x240001ec
+ 8028fe8:	2400018c 	.word	0x2400018c
+ 8028fec:	2400a488 	.word	0x2400a488
+
+08028ff0 <HAL_ETH_MspInit>:
+
+void HAL_ETH_MspInit(ETH_HandleTypeDef* ethHandle)
+{
+ 8028ff0:	b580      	push	{r7, lr}
+ 8028ff2:	b08e      	sub	sp, #56	@ 0x38
+ 8028ff4:	af00      	add	r7, sp, #0
+ 8028ff6:	6078      	str	r0, [r7, #4]
+
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+ 8028ff8:	f107 0324 	add.w	r3, r7, #36	@ 0x24
+ 8028ffc:	2200      	movs	r2, #0
+ 8028ffe:	601a      	str	r2, [r3, #0]
+ 8029000:	605a      	str	r2, [r3, #4]
+ 8029002:	609a      	str	r2, [r3, #8]
+ 8029004:	60da      	str	r2, [r3, #12]
+ 8029006:	611a      	str	r2, [r3, #16]
+  if(ethHandle->Instance==ETH)
+ 8029008:	687b      	ldr	r3, [r7, #4]
+ 802900a:	681b      	ldr	r3, [r3, #0]
+ 802900c:	4a51      	ldr	r2, [pc, #324]	@ (8029154 <HAL_ETH_MspInit+0x164>)
+ 802900e:	4293      	cmp	r3, r2
+ 8029010:	f040 809b 	bne.w	802914a <HAL_ETH_MspInit+0x15a>
+  {
+  /* USER CODE BEGIN ETH_MspInit 0 */
+
+  /* USER CODE END ETH_MspInit 0 */
+    /* ETH clock enable */
+    __HAL_RCC_ETH1MAC_CLK_ENABLE();
+ 8029014:	4b50      	ldr	r3, [pc, #320]	@ (8029158 <HAL_ETH_MspInit+0x168>)
+ 8029016:	f8d3 30d8 	ldr.w	r3, [r3, #216]	@ 0xd8
+ 802901a:	4a4f      	ldr	r2, [pc, #316]	@ (8029158 <HAL_ETH_MspInit+0x168>)
+ 802901c:	f443 4300 	orr.w	r3, r3, #32768	@ 0x8000
+ 8029020:	f8c2 30d8 	str.w	r3, [r2, #216]	@ 0xd8
+ 8029024:	4b4c      	ldr	r3, [pc, #304]	@ (8029158 <HAL_ETH_MspInit+0x168>)
+ 8029026:	f8d3 30d8 	ldr.w	r3, [r3, #216]	@ 0xd8
+ 802902a:	f403 4300 	and.w	r3, r3, #32768	@ 0x8000
+ 802902e:	623b      	str	r3, [r7, #32]
+ 8029030:	6a3b      	ldr	r3, [r7, #32]
+    __HAL_RCC_ETH1TX_CLK_ENABLE();
+ 8029032:	4b49      	ldr	r3, [pc, #292]	@ (8029158 <HAL_ETH_MspInit+0x168>)
+ 8029034:	f8d3 30d8 	ldr.w	r3, [r3, #216]	@ 0xd8
+ 8029038:	4a47      	ldr	r2, [pc, #284]	@ (8029158 <HAL_ETH_MspInit+0x168>)
+ 802903a:	f443 3380 	orr.w	r3, r3, #65536	@ 0x10000
+ 802903e:	f8c2 30d8 	str.w	r3, [r2, #216]	@ 0xd8
+ 8029042:	4b45      	ldr	r3, [pc, #276]	@ (8029158 <HAL_ETH_MspInit+0x168>)
+ 8029044:	f8d3 30d8 	ldr.w	r3, [r3, #216]	@ 0xd8
+ 8029048:	f403 3380 	and.w	r3, r3, #65536	@ 0x10000
+ 802904c:	61fb      	str	r3, [r7, #28]
+ 802904e:	69fb      	ldr	r3, [r7, #28]
+    __HAL_RCC_ETH1RX_CLK_ENABLE();
+ 8029050:	4b41      	ldr	r3, [pc, #260]	@ (8029158 <HAL_ETH_MspInit+0x168>)
+ 8029052:	f8d3 30d8 	ldr.w	r3, [r3, #216]	@ 0xd8
+ 8029056:	4a40      	ldr	r2, [pc, #256]	@ (8029158 <HAL_ETH_MspInit+0x168>)
+ 8029058:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
+ 802905c:	f8c2 30d8 	str.w	r3, [r2, #216]	@ 0xd8
+ 8029060:	4b3d      	ldr	r3, [pc, #244]	@ (8029158 <HAL_ETH_MspInit+0x168>)
+ 8029062:	f8d3 30d8 	ldr.w	r3, [r3, #216]	@ 0xd8
+ 8029066:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
+ 802906a:	61bb      	str	r3, [r7, #24]
+ 802906c:	69bb      	ldr	r3, [r7, #24]
+
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+ 802906e:	4b3a      	ldr	r3, [pc, #232]	@ (8029158 <HAL_ETH_MspInit+0x168>)
+ 8029070:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
+ 8029074:	4a38      	ldr	r2, [pc, #224]	@ (8029158 <HAL_ETH_MspInit+0x168>)
+ 8029076:	f043 0304 	orr.w	r3, r3, #4
+ 802907a:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
+ 802907e:	4b36      	ldr	r3, [pc, #216]	@ (8029158 <HAL_ETH_MspInit+0x168>)
+ 8029080:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
+ 8029084:	f003 0304 	and.w	r3, r3, #4
+ 8029088:	617b      	str	r3, [r7, #20]
+ 802908a:	697b      	ldr	r3, [r7, #20]
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+ 802908c:	4b32      	ldr	r3, [pc, #200]	@ (8029158 <HAL_ETH_MspInit+0x168>)
+ 802908e:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
+ 8029092:	4a31      	ldr	r2, [pc, #196]	@ (8029158 <HAL_ETH_MspInit+0x168>)
+ 8029094:	f043 0301 	orr.w	r3, r3, #1
+ 8029098:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
+ 802909c:	4b2e      	ldr	r3, [pc, #184]	@ (8029158 <HAL_ETH_MspInit+0x168>)
+ 802909e:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
+ 80290a2:	f003 0301 	and.w	r3, r3, #1
+ 80290a6:	613b      	str	r3, [r7, #16]
+ 80290a8:	693b      	ldr	r3, [r7, #16]
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+ 80290aa:	4b2b      	ldr	r3, [pc, #172]	@ (8029158 <HAL_ETH_MspInit+0x168>)
+ 80290ac:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
+ 80290b0:	4a29      	ldr	r2, [pc, #164]	@ (8029158 <HAL_ETH_MspInit+0x168>)
+ 80290b2:	f043 0302 	orr.w	r3, r3, #2
+ 80290b6:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
+ 80290ba:	4b27      	ldr	r3, [pc, #156]	@ (8029158 <HAL_ETH_MspInit+0x168>)
+ 80290bc:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
+ 80290c0:	f003 0302 	and.w	r3, r3, #2
+ 80290c4:	60fb      	str	r3, [r7, #12]
+ 80290c6:	68fb      	ldr	r3, [r7, #12]
+    PC5     ------> ETH_RXD1
+    PB11     ------> ETH_TX_EN
+    PB12     ------> ETH_TXD0
+    PB13     ------> ETH_TXD1
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5;
+ 80290c8:	2332      	movs	r3, #50	@ 0x32
+ 80290ca:	627b      	str	r3, [r7, #36]	@ 0x24
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 80290cc:	2302      	movs	r3, #2
+ 80290ce:	62bb      	str	r3, [r7, #40]	@ 0x28
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 80290d0:	2300      	movs	r3, #0
+ 80290d2:	62fb      	str	r3, [r7, #44]	@ 0x2c
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ 80290d4:	2303      	movs	r3, #3
+ 80290d6:	633b      	str	r3, [r7, #48]	@ 0x30
+    GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
+ 80290d8:	230b      	movs	r3, #11
+ 80290da:	637b      	str	r3, [r7, #52]	@ 0x34
+    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+ 80290dc:	f107 0324 	add.w	r3, r7, #36	@ 0x24
+ 80290e0:	4619      	mov	r1, r3
+ 80290e2:	481e      	ldr	r0, [pc, #120]	@ (802915c <HAL_ETH_MspInit+0x16c>)
+ 80290e4:	f00e fa7a 	bl	80375dc <HAL_GPIO_Init>
+
+    GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_7;
+ 80290e8:	2386      	movs	r3, #134	@ 0x86
+ 80290ea:	627b      	str	r3, [r7, #36]	@ 0x24
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 80290ec:	2302      	movs	r3, #2
+ 80290ee:	62bb      	str	r3, [r7, #40]	@ 0x28
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 80290f0:	2300      	movs	r3, #0
+ 80290f2:	62fb      	str	r3, [r7, #44]	@ 0x2c
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ 80290f4:	2303      	movs	r3, #3
+ 80290f6:	633b      	str	r3, [r7, #48]	@ 0x30
+    GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
+ 80290f8:	230b      	movs	r3, #11
+ 80290fa:	637b      	str	r3, [r7, #52]	@ 0x34
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 80290fc:	f107 0324 	add.w	r3, r7, #36	@ 0x24
+ 8029100:	4619      	mov	r1, r3
+ 8029102:	4817      	ldr	r0, [pc, #92]	@ (8029160 <HAL_ETH_MspInit+0x170>)
+ 8029104:	f00e fa6a 	bl	80375dc <HAL_GPIO_Init>
+
+    GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13;
+ 8029108:	f44f 5360 	mov.w	r3, #14336	@ 0x3800
+ 802910c:	627b      	str	r3, [r7, #36]	@ 0x24
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 802910e:	2302      	movs	r3, #2
+ 8029110:	62bb      	str	r3, [r7, #40]	@ 0x28
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 8029112:	2300      	movs	r3, #0
+ 8029114:	62fb      	str	r3, [r7, #44]	@ 0x2c
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ 8029116:	2303      	movs	r3, #3
+ 8029118:	633b      	str	r3, [r7, #48]	@ 0x30
+    GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
+ 802911a:	230b      	movs	r3, #11
+ 802911c:	637b      	str	r3, [r7, #52]	@ 0x34
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+ 802911e:	f107 0324 	add.w	r3, r7, #36	@ 0x24
+ 8029122:	4619      	mov	r1, r3
+ 8029124:	480f      	ldr	r0, [pc, #60]	@ (8029164 <HAL_ETH_MspInit+0x174>)
+ 8029126:	f00e fa59 	bl	80375dc <HAL_GPIO_Init>
+
+    /* ETH interrupt Init */
+    HAL_NVIC_SetPriority(ETH_IRQn, 6, 0);
+ 802912a:	2200      	movs	r2, #0
+ 802912c:	2106      	movs	r1, #6
+ 802912e:	203d      	movs	r0, #61	@ 0x3d
+ 8029130:	f009 fcbf 	bl	8032ab2 <HAL_NVIC_SetPriority>
+    HAL_NVIC_EnableIRQ(ETH_IRQn);
+ 8029134:	203d      	movs	r0, #61	@ 0x3d
+ 8029136:	f009 fcd6 	bl	8032ae6 <HAL_NVIC_EnableIRQ>
+    HAL_NVIC_SetPriority(ETH_WKUP_IRQn, 0, 0);
+ 802913a:	2200      	movs	r2, #0
+ 802913c:	2100      	movs	r1, #0
+ 802913e:	203e      	movs	r0, #62	@ 0x3e
+ 8029140:	f009 fcb7 	bl	8032ab2 <HAL_NVIC_SetPriority>
+    HAL_NVIC_EnableIRQ(ETH_WKUP_IRQn);
+ 8029144:	203e      	movs	r0, #62	@ 0x3e
+ 8029146:	f009 fcce 	bl	8032ae6 <HAL_NVIC_EnableIRQ>
+  /* USER CODE BEGIN ETH_MspInit 1 */
+
+  /* USER CODE END ETH_MspInit 1 */
+  }
+}
+ 802914a:	bf00      	nop
+ 802914c:	3738      	adds	r7, #56	@ 0x38
+ 802914e:	46bd      	mov	sp, r7
+ 8029150:	bd80      	pop	{r7, pc}
+ 8029152:	bf00      	nop
+ 8029154:	40028000 	.word	0x40028000
+ 8029158:	58024400 	.word	0x58024400
+ 802915c:	58020800 	.word	0x58020800
+ 8029160:	58020000 	.word	0x58020000
+ 8029164:	58020400 	.word	0x58020400
+
+08029168 <MX_FDCAN1_Init>:
+FDCAN_HandleTypeDef hfdcan1;
+FDCAN_HandleTypeDef hfdcan2;
+
+/* FDCAN1 init function */
+void MX_FDCAN1_Init(void)
+{
+ 8029168:	b580      	push	{r7, lr}
+ 802916a:	af00      	add	r7, sp, #0
+  /* USER CODE END FDCAN1_Init 0 */
+
+  /* USER CODE BEGIN FDCAN1_Init 1 */
+
+  /* USER CODE END FDCAN1_Init 1 */
+  hfdcan1.Instance = FDCAN1;
+ 802916c:	4b2e      	ldr	r3, [pc, #184]	@ (8029228 <MX_FDCAN1_Init+0xc0>)
+ 802916e:	4a2f      	ldr	r2, [pc, #188]	@ (802922c <MX_FDCAN1_Init+0xc4>)
+ 8029170:	601a      	str	r2, [r3, #0]
+  hfdcan1.Init.FrameFormat = FDCAN_FRAME_CLASSIC;
+ 8029172:	4b2d      	ldr	r3, [pc, #180]	@ (8029228 <MX_FDCAN1_Init+0xc0>)
+ 8029174:	2200      	movs	r2, #0
+ 8029176:	609a      	str	r2, [r3, #8]
+  hfdcan1.Init.Mode = FDCAN_MODE_NORMAL;
+ 8029178:	4b2b      	ldr	r3, [pc, #172]	@ (8029228 <MX_FDCAN1_Init+0xc0>)
+ 802917a:	2200      	movs	r2, #0
+ 802917c:	60da      	str	r2, [r3, #12]
+  hfdcan1.Init.AutoRetransmission = DISABLE;
+ 802917e:	4b2a      	ldr	r3, [pc, #168]	@ (8029228 <MX_FDCAN1_Init+0xc0>)
+ 8029180:	2200      	movs	r2, #0
+ 8029182:	741a      	strb	r2, [r3, #16]
+  hfdcan1.Init.TransmitPause = DISABLE;
+ 8029184:	4b28      	ldr	r3, [pc, #160]	@ (8029228 <MX_FDCAN1_Init+0xc0>)
+ 8029186:	2200      	movs	r2, #0
+ 8029188:	745a      	strb	r2, [r3, #17]
+  hfdcan1.Init.ProtocolException = DISABLE;
+ 802918a:	4b27      	ldr	r3, [pc, #156]	@ (8029228 <MX_FDCAN1_Init+0xc0>)
+ 802918c:	2200      	movs	r2, #0
+ 802918e:	749a      	strb	r2, [r3, #18]
+  hfdcan1.Init.NominalPrescaler = 20;
+ 8029190:	4b25      	ldr	r3, [pc, #148]	@ (8029228 <MX_FDCAN1_Init+0xc0>)
+ 8029192:	2214      	movs	r2, #20
+ 8029194:	615a      	str	r2, [r3, #20]
+  hfdcan1.Init.NominalSyncJumpWidth = 1;
+ 8029196:	4b24      	ldr	r3, [pc, #144]	@ (8029228 <MX_FDCAN1_Init+0xc0>)
+ 8029198:	2201      	movs	r2, #1
+ 802919a:	619a      	str	r2, [r3, #24]
+  hfdcan1.Init.NominalTimeSeg1 = 5;
+ 802919c:	4b22      	ldr	r3, [pc, #136]	@ (8029228 <MX_FDCAN1_Init+0xc0>)
+ 802919e:	2205      	movs	r2, #5
+ 80291a0:	61da      	str	r2, [r3, #28]
+  hfdcan1.Init.NominalTimeSeg2 = 2;
+ 80291a2:	4b21      	ldr	r3, [pc, #132]	@ (8029228 <MX_FDCAN1_Init+0xc0>)
+ 80291a4:	2202      	movs	r2, #2
+ 80291a6:	621a      	str	r2, [r3, #32]
+  hfdcan1.Init.DataPrescaler = 1;
+ 80291a8:	4b1f      	ldr	r3, [pc, #124]	@ (8029228 <MX_FDCAN1_Init+0xc0>)
+ 80291aa:	2201      	movs	r2, #1
+ 80291ac:	625a      	str	r2, [r3, #36]	@ 0x24
+  hfdcan1.Init.DataSyncJumpWidth = 1;
+ 80291ae:	4b1e      	ldr	r3, [pc, #120]	@ (8029228 <MX_FDCAN1_Init+0xc0>)
+ 80291b0:	2201      	movs	r2, #1
+ 80291b2:	629a      	str	r2, [r3, #40]	@ 0x28
+  hfdcan1.Init.DataTimeSeg1 = 1;
+ 80291b4:	4b1c      	ldr	r3, [pc, #112]	@ (8029228 <MX_FDCAN1_Init+0xc0>)
+ 80291b6:	2201      	movs	r2, #1
+ 80291b8:	62da      	str	r2, [r3, #44]	@ 0x2c
+  hfdcan1.Init.DataTimeSeg2 = 1;
+ 80291ba:	4b1b      	ldr	r3, [pc, #108]	@ (8029228 <MX_FDCAN1_Init+0xc0>)
+ 80291bc:	2201      	movs	r2, #1
+ 80291be:	631a      	str	r2, [r3, #48]	@ 0x30
+  hfdcan1.Init.MessageRAMOffset = 0;
+ 80291c0:	4b19      	ldr	r3, [pc, #100]	@ (8029228 <MX_FDCAN1_Init+0xc0>)
+ 80291c2:	2200      	movs	r2, #0
+ 80291c4:	635a      	str	r2, [r3, #52]	@ 0x34
+  hfdcan1.Init.StdFiltersNbr = 0;
+ 80291c6:	4b18      	ldr	r3, [pc, #96]	@ (8029228 <MX_FDCAN1_Init+0xc0>)
+ 80291c8:	2200      	movs	r2, #0
+ 80291ca:	639a      	str	r2, [r3, #56]	@ 0x38
+  hfdcan1.Init.ExtFiltersNbr = 0;
+ 80291cc:	4b16      	ldr	r3, [pc, #88]	@ (8029228 <MX_FDCAN1_Init+0xc0>)
+ 80291ce:	2200      	movs	r2, #0
+ 80291d0:	63da      	str	r2, [r3, #60]	@ 0x3c
+  hfdcan1.Init.RxFifo0ElmtsNbr = 32;
+ 80291d2:	4b15      	ldr	r3, [pc, #84]	@ (8029228 <MX_FDCAN1_Init+0xc0>)
+ 80291d4:	2220      	movs	r2, #32
+ 80291d6:	641a      	str	r2, [r3, #64]	@ 0x40
+  hfdcan1.Init.RxFifo0ElmtSize = FDCAN_DATA_BYTES_8;
+ 80291d8:	4b13      	ldr	r3, [pc, #76]	@ (8029228 <MX_FDCAN1_Init+0xc0>)
+ 80291da:	2204      	movs	r2, #4
+ 80291dc:	645a      	str	r2, [r3, #68]	@ 0x44
+  hfdcan1.Init.RxFifo1ElmtsNbr = 0;
+ 80291de:	4b12      	ldr	r3, [pc, #72]	@ (8029228 <MX_FDCAN1_Init+0xc0>)
+ 80291e0:	2200      	movs	r2, #0
+ 80291e2:	649a      	str	r2, [r3, #72]	@ 0x48
+  hfdcan1.Init.RxFifo1ElmtSize = FDCAN_DATA_BYTES_8;
+ 80291e4:	4b10      	ldr	r3, [pc, #64]	@ (8029228 <MX_FDCAN1_Init+0xc0>)
+ 80291e6:	2204      	movs	r2, #4
+ 80291e8:	64da      	str	r2, [r3, #76]	@ 0x4c
+  hfdcan1.Init.RxBuffersNbr = 0;
+ 80291ea:	4b0f      	ldr	r3, [pc, #60]	@ (8029228 <MX_FDCAN1_Init+0xc0>)
+ 80291ec:	2200      	movs	r2, #0
+ 80291ee:	651a      	str	r2, [r3, #80]	@ 0x50
+  hfdcan1.Init.RxBufferSize = FDCAN_DATA_BYTES_8;
+ 80291f0:	4b0d      	ldr	r3, [pc, #52]	@ (8029228 <MX_FDCAN1_Init+0xc0>)
+ 80291f2:	2204      	movs	r2, #4
+ 80291f4:	655a      	str	r2, [r3, #84]	@ 0x54
+  hfdcan1.Init.TxEventsNbr = 0;
+ 80291f6:	4b0c      	ldr	r3, [pc, #48]	@ (8029228 <MX_FDCAN1_Init+0xc0>)
+ 80291f8:	2200      	movs	r2, #0
+ 80291fa:	659a      	str	r2, [r3, #88]	@ 0x58
+  hfdcan1.Init.TxBuffersNbr = 0;
+ 80291fc:	4b0a      	ldr	r3, [pc, #40]	@ (8029228 <MX_FDCAN1_Init+0xc0>)
+ 80291fe:	2200      	movs	r2, #0
+ 8029200:	65da      	str	r2, [r3, #92]	@ 0x5c
+  hfdcan1.Init.TxFifoQueueElmtsNbr = 32;
+ 8029202:	4b09      	ldr	r3, [pc, #36]	@ (8029228 <MX_FDCAN1_Init+0xc0>)
+ 8029204:	2220      	movs	r2, #32
+ 8029206:	661a      	str	r2, [r3, #96]	@ 0x60
+  hfdcan1.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION;
+ 8029208:	4b07      	ldr	r3, [pc, #28]	@ (8029228 <MX_FDCAN1_Init+0xc0>)
+ 802920a:	2200      	movs	r2, #0
+ 802920c:	665a      	str	r2, [r3, #100]	@ 0x64
+  hfdcan1.Init.TxElmtSize = FDCAN_DATA_BYTES_8;
+ 802920e:	4b06      	ldr	r3, [pc, #24]	@ (8029228 <MX_FDCAN1_Init+0xc0>)
+ 8029210:	2204      	movs	r2, #4
+ 8029212:	669a      	str	r2, [r3, #104]	@ 0x68
+  if (HAL_FDCAN_Init(&hfdcan1) != HAL_OK)
+ 8029214:	4804      	ldr	r0, [pc, #16]	@ (8029228 <MX_FDCAN1_Init+0xc0>)
+ 8029216:	f00d f8a7 	bl	8036368 <HAL_FDCAN_Init>
+ 802921a:	4603      	mov	r3, r0
+ 802921c:	2b00      	cmp	r3, #0
+ 802921e:	d001      	beq.n	8029224 <MX_FDCAN1_Init+0xbc>
+  {
+    Error_Handler();
+ 8029220:	f006 fc32 	bl	802fa88 <Error_Handler>
+  }
+  /* USER CODE BEGIN FDCAN1_Init 2 */
+
+  /* USER CODE END FDCAN1_Init 2 */
+
+}
+ 8029224:	bf00      	nop
+ 8029226:	bd80      	pop	{r7, pc}
+ 8029228:	2400a578 	.word	0x2400a578
+ 802922c:	4000a000 	.word	0x4000a000
+
+08029230 <MX_FDCAN2_Init>:
+/* FDCAN2 init function */
+void MX_FDCAN2_Init(void)
+{
+ 8029230:	b580      	push	{r7, lr}
+ 8029232:	af00      	add	r7, sp, #0
+  /* USER CODE END FDCAN2_Init 0 */
+
+  /* USER CODE BEGIN FDCAN2_Init 1 */
+
+  /* USER CODE END FDCAN2_Init 1 */
+  hfdcan2.Instance = FDCAN2;
+ 8029234:	4b2e      	ldr	r3, [pc, #184]	@ (80292f0 <MX_FDCAN2_Init+0xc0>)
+ 8029236:	4a2f      	ldr	r2, [pc, #188]	@ (80292f4 <MX_FDCAN2_Init+0xc4>)
+ 8029238:	601a      	str	r2, [r3, #0]
+  hfdcan2.Init.FrameFormat = FDCAN_FRAME_CLASSIC;
+ 802923a:	4b2d      	ldr	r3, [pc, #180]	@ (80292f0 <MX_FDCAN2_Init+0xc0>)
+ 802923c:	2200      	movs	r2, #0
+ 802923e:	609a      	str	r2, [r3, #8]
+  hfdcan2.Init.Mode = FDCAN_MODE_NORMAL;
+ 8029240:	4b2b      	ldr	r3, [pc, #172]	@ (80292f0 <MX_FDCAN2_Init+0xc0>)
+ 8029242:	2200      	movs	r2, #0
+ 8029244:	60da      	str	r2, [r3, #12]
+  hfdcan2.Init.AutoRetransmission = DISABLE;
+ 8029246:	4b2a      	ldr	r3, [pc, #168]	@ (80292f0 <MX_FDCAN2_Init+0xc0>)
+ 8029248:	2200      	movs	r2, #0
+ 802924a:	741a      	strb	r2, [r3, #16]
+  hfdcan2.Init.TransmitPause = DISABLE;
+ 802924c:	4b28      	ldr	r3, [pc, #160]	@ (80292f0 <MX_FDCAN2_Init+0xc0>)
+ 802924e:	2200      	movs	r2, #0
+ 8029250:	745a      	strb	r2, [r3, #17]
+  hfdcan2.Init.ProtocolException = DISABLE;
+ 8029252:	4b27      	ldr	r3, [pc, #156]	@ (80292f0 <MX_FDCAN2_Init+0xc0>)
+ 8029254:	2200      	movs	r2, #0
+ 8029256:	749a      	strb	r2, [r3, #18]
+  hfdcan2.Init.NominalPrescaler = 20;
+ 8029258:	4b25      	ldr	r3, [pc, #148]	@ (80292f0 <MX_FDCAN2_Init+0xc0>)
+ 802925a:	2214      	movs	r2, #20
+ 802925c:	615a      	str	r2, [r3, #20]
+  hfdcan2.Init.NominalSyncJumpWidth = 1;
+ 802925e:	4b24      	ldr	r3, [pc, #144]	@ (80292f0 <MX_FDCAN2_Init+0xc0>)
+ 8029260:	2201      	movs	r2, #1
+ 8029262:	619a      	str	r2, [r3, #24]
+  hfdcan2.Init.NominalTimeSeg1 = 5;
+ 8029264:	4b22      	ldr	r3, [pc, #136]	@ (80292f0 <MX_FDCAN2_Init+0xc0>)
+ 8029266:	2205      	movs	r2, #5
+ 8029268:	61da      	str	r2, [r3, #28]
+  hfdcan2.Init.NominalTimeSeg2 = 2;
+ 802926a:	4b21      	ldr	r3, [pc, #132]	@ (80292f0 <MX_FDCAN2_Init+0xc0>)
+ 802926c:	2202      	movs	r2, #2
+ 802926e:	621a      	str	r2, [r3, #32]
+  hfdcan2.Init.DataPrescaler = 1;
+ 8029270:	4b1f      	ldr	r3, [pc, #124]	@ (80292f0 <MX_FDCAN2_Init+0xc0>)
+ 8029272:	2201      	movs	r2, #1
+ 8029274:	625a      	str	r2, [r3, #36]	@ 0x24
+  hfdcan2.Init.DataSyncJumpWidth = 1;
+ 8029276:	4b1e      	ldr	r3, [pc, #120]	@ (80292f0 <MX_FDCAN2_Init+0xc0>)
+ 8029278:	2201      	movs	r2, #1
+ 802927a:	629a      	str	r2, [r3, #40]	@ 0x28
+  hfdcan2.Init.DataTimeSeg1 = 1;
+ 802927c:	4b1c      	ldr	r3, [pc, #112]	@ (80292f0 <MX_FDCAN2_Init+0xc0>)
+ 802927e:	2201      	movs	r2, #1
+ 8029280:	62da      	str	r2, [r3, #44]	@ 0x2c
+  hfdcan2.Init.DataTimeSeg2 = 1;
+ 8029282:	4b1b      	ldr	r3, [pc, #108]	@ (80292f0 <MX_FDCAN2_Init+0xc0>)
+ 8029284:	2201      	movs	r2, #1
+ 8029286:	631a      	str	r2, [r3, #48]	@ 0x30
+  hfdcan2.Init.MessageRAMOffset = 0;
+ 8029288:	4b19      	ldr	r3, [pc, #100]	@ (80292f0 <MX_FDCAN2_Init+0xc0>)
+ 802928a:	2200      	movs	r2, #0
+ 802928c:	635a      	str	r2, [r3, #52]	@ 0x34
+  hfdcan2.Init.StdFiltersNbr = 0;
+ 802928e:	4b18      	ldr	r3, [pc, #96]	@ (80292f0 <MX_FDCAN2_Init+0xc0>)
+ 8029290:	2200      	movs	r2, #0
+ 8029292:	639a      	str	r2, [r3, #56]	@ 0x38
+  hfdcan2.Init.ExtFiltersNbr = 0;
+ 8029294:	4b16      	ldr	r3, [pc, #88]	@ (80292f0 <MX_FDCAN2_Init+0xc0>)
+ 8029296:	2200      	movs	r2, #0
+ 8029298:	63da      	str	r2, [r3, #60]	@ 0x3c
+  hfdcan2.Init.RxFifo0ElmtsNbr = 32;
+ 802929a:	4b15      	ldr	r3, [pc, #84]	@ (80292f0 <MX_FDCAN2_Init+0xc0>)
+ 802929c:	2220      	movs	r2, #32
+ 802929e:	641a      	str	r2, [r3, #64]	@ 0x40
+  hfdcan2.Init.RxFifo0ElmtSize = FDCAN_DATA_BYTES_8;
+ 80292a0:	4b13      	ldr	r3, [pc, #76]	@ (80292f0 <MX_FDCAN2_Init+0xc0>)
+ 80292a2:	2204      	movs	r2, #4
+ 80292a4:	645a      	str	r2, [r3, #68]	@ 0x44
+  hfdcan2.Init.RxFifo1ElmtsNbr = 0;
+ 80292a6:	4b12      	ldr	r3, [pc, #72]	@ (80292f0 <MX_FDCAN2_Init+0xc0>)
+ 80292a8:	2200      	movs	r2, #0
+ 80292aa:	649a      	str	r2, [r3, #72]	@ 0x48
+  hfdcan2.Init.RxFifo1ElmtSize = FDCAN_DATA_BYTES_8;
+ 80292ac:	4b10      	ldr	r3, [pc, #64]	@ (80292f0 <MX_FDCAN2_Init+0xc0>)
+ 80292ae:	2204      	movs	r2, #4
+ 80292b0:	64da      	str	r2, [r3, #76]	@ 0x4c
+  hfdcan2.Init.RxBuffersNbr = 0;
+ 80292b2:	4b0f      	ldr	r3, [pc, #60]	@ (80292f0 <MX_FDCAN2_Init+0xc0>)
+ 80292b4:	2200      	movs	r2, #0
+ 80292b6:	651a      	str	r2, [r3, #80]	@ 0x50
+  hfdcan2.Init.RxBufferSize = FDCAN_DATA_BYTES_8;
+ 80292b8:	4b0d      	ldr	r3, [pc, #52]	@ (80292f0 <MX_FDCAN2_Init+0xc0>)
+ 80292ba:	2204      	movs	r2, #4
+ 80292bc:	655a      	str	r2, [r3, #84]	@ 0x54
+  hfdcan2.Init.TxEventsNbr = 0;
+ 80292be:	4b0c      	ldr	r3, [pc, #48]	@ (80292f0 <MX_FDCAN2_Init+0xc0>)
+ 80292c0:	2200      	movs	r2, #0
+ 80292c2:	659a      	str	r2, [r3, #88]	@ 0x58
+  hfdcan2.Init.TxBuffersNbr = 0;
+ 80292c4:	4b0a      	ldr	r3, [pc, #40]	@ (80292f0 <MX_FDCAN2_Init+0xc0>)
+ 80292c6:	2200      	movs	r2, #0
+ 80292c8:	65da      	str	r2, [r3, #92]	@ 0x5c
+  hfdcan2.Init.TxFifoQueueElmtsNbr = 32;
+ 80292ca:	4b09      	ldr	r3, [pc, #36]	@ (80292f0 <MX_FDCAN2_Init+0xc0>)
+ 80292cc:	2220      	movs	r2, #32
+ 80292ce:	661a      	str	r2, [r3, #96]	@ 0x60
+  hfdcan2.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION;
+ 80292d0:	4b07      	ldr	r3, [pc, #28]	@ (80292f0 <MX_FDCAN2_Init+0xc0>)
+ 80292d2:	2200      	movs	r2, #0
+ 80292d4:	665a      	str	r2, [r3, #100]	@ 0x64
+  hfdcan2.Init.TxElmtSize = FDCAN_DATA_BYTES_8;
+ 80292d6:	4b06      	ldr	r3, [pc, #24]	@ (80292f0 <MX_FDCAN2_Init+0xc0>)
+ 80292d8:	2204      	movs	r2, #4
+ 80292da:	669a      	str	r2, [r3, #104]	@ 0x68
+  if (HAL_FDCAN_Init(&hfdcan2) != HAL_OK)
+ 80292dc:	4804      	ldr	r0, [pc, #16]	@ (80292f0 <MX_FDCAN2_Init+0xc0>)
+ 80292de:	f00d f843 	bl	8036368 <HAL_FDCAN_Init>
+ 80292e2:	4603      	mov	r3, r0
+ 80292e4:	2b00      	cmp	r3, #0
+ 80292e6:	d001      	beq.n	80292ec <MX_FDCAN2_Init+0xbc>
+  {
+    Error_Handler();
+ 80292e8:	f006 fbce 	bl	802fa88 <Error_Handler>
+  }
+  /* USER CODE BEGIN FDCAN2_Init 2 */
+
+  /* USER CODE END FDCAN2_Init 2 */
+
+}
+ 80292ec:	bf00      	nop
+ 80292ee:	bd80      	pop	{r7, pc}
+ 80292f0:	2400a618 	.word	0x2400a618
+ 80292f4:	4000a400 	.word	0x4000a400
+
+080292f8 <HAL_FDCAN_MspInit>:
+
+static uint32_t HAL_RCC_FDCAN_CLK_ENABLED=0;
+
+void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef* fdcanHandle)
+{
+ 80292f8:	b580      	push	{r7, lr}
+ 80292fa:	b0bc      	sub	sp, #240	@ 0xf0
+ 80292fc:	af00      	add	r7, sp, #0
+ 80292fe:	6078      	str	r0, [r7, #4]
+
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+ 8029300:	f107 03dc 	add.w	r3, r7, #220	@ 0xdc
+ 8029304:	2200      	movs	r2, #0
+ 8029306:	601a      	str	r2, [r3, #0]
+ 8029308:	605a      	str	r2, [r3, #4]
+ 802930a:	609a      	str	r2, [r3, #8]
+ 802930c:	60da      	str	r2, [r3, #12]
+ 802930e:	611a      	str	r2, [r3, #16]
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+ 8029310:	f107 0318 	add.w	r3, r7, #24
+ 8029314:	22c0      	movs	r2, #192	@ 0xc0
+ 8029316:	2100      	movs	r1, #0
+ 8029318:	4618      	mov	r0, r3
+ 802931a:	f016 ffe5 	bl	80402e8 <memset>
+  if(fdcanHandle->Instance==FDCAN1)
+ 802931e:	687b      	ldr	r3, [r7, #4]
+ 8029320:	681b      	ldr	r3, [r3, #0]
+ 8029322:	4a5f      	ldr	r2, [pc, #380]	@ (80294a0 <HAL_FDCAN_MspInit+0x1a8>)
+ 8029324:	4293      	cmp	r3, r2
+ 8029326:	d159      	bne.n	80293dc <HAL_FDCAN_MspInit+0xe4>
+
+  /* USER CODE END FDCAN1_MspInit 0 */
+
+  /** Initializes the peripherals clock
+  */
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_FDCAN;
+ 8029328:	f44f 4200 	mov.w	r2, #32768	@ 0x8000
+ 802932c:	f04f 0300 	mov.w	r3, #0
+ 8029330:	e9c7 2306 	strd	r2, r3, [r7, #24]
+    PeriphClkInitStruct.FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL;
+ 8029334:	f04f 5380 	mov.w	r3, #268435456	@ 0x10000000
+ 8029338:	f8c7 3088 	str.w	r3, [r7, #136]	@ 0x88
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+ 802933c:	f107 0318 	add.w	r3, r7, #24
+ 8029340:	4618      	mov	r0, r3
+ 8029342:	f010 fe9f 	bl	803a084 <HAL_RCCEx_PeriphCLKConfig>
+ 8029346:	4603      	mov	r3, r0
+ 8029348:	2b00      	cmp	r3, #0
+ 802934a:	d001      	beq.n	8029350 <HAL_FDCAN_MspInit+0x58>
+    {
+      Error_Handler();
+ 802934c:	f006 fb9c 	bl	802fa88 <Error_Handler>
+    }
+
+    /* FDCAN1 clock enable */
+    HAL_RCC_FDCAN_CLK_ENABLED++;
+ 8029350:	4b54      	ldr	r3, [pc, #336]	@ (80294a4 <HAL_FDCAN_MspInit+0x1ac>)
+ 8029352:	681b      	ldr	r3, [r3, #0]
+ 8029354:	3301      	adds	r3, #1
+ 8029356:	4a53      	ldr	r2, [pc, #332]	@ (80294a4 <HAL_FDCAN_MspInit+0x1ac>)
+ 8029358:	6013      	str	r3, [r2, #0]
+    if(HAL_RCC_FDCAN_CLK_ENABLED==1){
+ 802935a:	4b52      	ldr	r3, [pc, #328]	@ (80294a4 <HAL_FDCAN_MspInit+0x1ac>)
+ 802935c:	681b      	ldr	r3, [r3, #0]
+ 802935e:	2b01      	cmp	r3, #1
+ 8029360:	d10e      	bne.n	8029380 <HAL_FDCAN_MspInit+0x88>
+      __HAL_RCC_FDCAN_CLK_ENABLE();
+ 8029362:	4b51      	ldr	r3, [pc, #324]	@ (80294a8 <HAL_FDCAN_MspInit+0x1b0>)
+ 8029364:	f8d3 30ec 	ldr.w	r3, [r3, #236]	@ 0xec
+ 8029368:	4a4f      	ldr	r2, [pc, #316]	@ (80294a8 <HAL_FDCAN_MspInit+0x1b0>)
+ 802936a:	f443 7380 	orr.w	r3, r3, #256	@ 0x100
+ 802936e:	f8c2 30ec 	str.w	r3, [r2, #236]	@ 0xec
+ 8029372:	4b4d      	ldr	r3, [pc, #308]	@ (80294a8 <HAL_FDCAN_MspInit+0x1b0>)
+ 8029374:	f8d3 30ec 	ldr.w	r3, [r3, #236]	@ 0xec
+ 8029378:	f403 7380 	and.w	r3, r3, #256	@ 0x100
+ 802937c:	617b      	str	r3, [r7, #20]
+ 802937e:	697b      	ldr	r3, [r7, #20]
+    }
+
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+ 8029380:	4b49      	ldr	r3, [pc, #292]	@ (80294a8 <HAL_FDCAN_MspInit+0x1b0>)
+ 8029382:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
+ 8029386:	4a48      	ldr	r2, [pc, #288]	@ (80294a8 <HAL_FDCAN_MspInit+0x1b0>)
+ 8029388:	f043 0302 	orr.w	r3, r3, #2
+ 802938c:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
+ 8029390:	4b45      	ldr	r3, [pc, #276]	@ (80294a8 <HAL_FDCAN_MspInit+0x1b0>)
+ 8029392:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
+ 8029396:	f003 0302 	and.w	r3, r3, #2
+ 802939a:	613b      	str	r3, [r7, #16]
+ 802939c:	693b      	ldr	r3, [r7, #16]
+    /**FDCAN1 GPIO Configuration
+    PB8     ------> FDCAN1_RX
+    PB9     ------> FDCAN1_TX
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9;
+ 802939e:	f44f 7340 	mov.w	r3, #768	@ 0x300
+ 80293a2:	f8c7 30dc 	str.w	r3, [r7, #220]	@ 0xdc
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 80293a6:	2302      	movs	r3, #2
+ 80293a8:	f8c7 30e0 	str.w	r3, [r7, #224]	@ 0xe0
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 80293ac:	2300      	movs	r3, #0
+ 80293ae:	f8c7 30e4 	str.w	r3, [r7, #228]	@ 0xe4
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 80293b2:	2300      	movs	r3, #0
+ 80293b4:	f8c7 30e8 	str.w	r3, [r7, #232]	@ 0xe8
+    GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN1;
+ 80293b8:	2309      	movs	r3, #9
+ 80293ba:	f8c7 30ec 	str.w	r3, [r7, #236]	@ 0xec
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+ 80293be:	f107 03dc 	add.w	r3, r7, #220	@ 0xdc
+ 80293c2:	4619      	mov	r1, r3
+ 80293c4:	4839      	ldr	r0, [pc, #228]	@ (80294ac <HAL_FDCAN_MspInit+0x1b4>)
+ 80293c6:	f00e f909 	bl	80375dc <HAL_GPIO_Init>
+
+    /* FDCAN1 interrupt Init */
+    HAL_NVIC_SetPriority(FDCAN1_IT0_IRQn, 0, 0);
+ 80293ca:	2200      	movs	r2, #0
+ 80293cc:	2100      	movs	r1, #0
+ 80293ce:	2013      	movs	r0, #19
+ 80293d0:	f009 fb6f 	bl	8032ab2 <HAL_NVIC_SetPriority>
+    HAL_NVIC_EnableIRQ(FDCAN1_IT0_IRQn);
+ 80293d4:	2013      	movs	r0, #19
+ 80293d6:	f009 fb86 	bl	8032ae6 <HAL_NVIC_EnableIRQ>
+    HAL_NVIC_EnableIRQ(FDCAN2_IT0_IRQn);
+  /* USER CODE BEGIN FDCAN2_MspInit 1 */
+
+  /* USER CODE END FDCAN2_MspInit 1 */
+  }
+}
+ 80293da:	e05c      	b.n	8029496 <HAL_FDCAN_MspInit+0x19e>
+  else if(fdcanHandle->Instance==FDCAN2)
+ 80293dc:	687b      	ldr	r3, [r7, #4]
+ 80293de:	681b      	ldr	r3, [r3, #0]
+ 80293e0:	4a33      	ldr	r2, [pc, #204]	@ (80294b0 <HAL_FDCAN_MspInit+0x1b8>)
+ 80293e2:	4293      	cmp	r3, r2
+ 80293e4:	d157      	bne.n	8029496 <HAL_FDCAN_MspInit+0x19e>
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_FDCAN;
+ 80293e6:	f44f 4200 	mov.w	r2, #32768	@ 0x8000
+ 80293ea:	f04f 0300 	mov.w	r3, #0
+ 80293ee:	e9c7 2306 	strd	r2, r3, [r7, #24]
+    PeriphClkInitStruct.FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL;
+ 80293f2:	f04f 5380 	mov.w	r3, #268435456	@ 0x10000000
+ 80293f6:	f8c7 3088 	str.w	r3, [r7, #136]	@ 0x88
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+ 80293fa:	f107 0318 	add.w	r3, r7, #24
+ 80293fe:	4618      	mov	r0, r3
+ 8029400:	f010 fe40 	bl	803a084 <HAL_RCCEx_PeriphCLKConfig>
+ 8029404:	4603      	mov	r3, r0
+ 8029406:	2b00      	cmp	r3, #0
+ 8029408:	d001      	beq.n	802940e <HAL_FDCAN_MspInit+0x116>
+      Error_Handler();
+ 802940a:	f006 fb3d 	bl	802fa88 <Error_Handler>
+    HAL_RCC_FDCAN_CLK_ENABLED++;
+ 802940e:	4b25      	ldr	r3, [pc, #148]	@ (80294a4 <HAL_FDCAN_MspInit+0x1ac>)
+ 8029410:	681b      	ldr	r3, [r3, #0]
+ 8029412:	3301      	adds	r3, #1
+ 8029414:	4a23      	ldr	r2, [pc, #140]	@ (80294a4 <HAL_FDCAN_MspInit+0x1ac>)
+ 8029416:	6013      	str	r3, [r2, #0]
+    if(HAL_RCC_FDCAN_CLK_ENABLED==1){
+ 8029418:	4b22      	ldr	r3, [pc, #136]	@ (80294a4 <HAL_FDCAN_MspInit+0x1ac>)
+ 802941a:	681b      	ldr	r3, [r3, #0]
+ 802941c:	2b01      	cmp	r3, #1
+ 802941e:	d10e      	bne.n	802943e <HAL_FDCAN_MspInit+0x146>
+      __HAL_RCC_FDCAN_CLK_ENABLE();
+ 8029420:	4b21      	ldr	r3, [pc, #132]	@ (80294a8 <HAL_FDCAN_MspInit+0x1b0>)
+ 8029422:	f8d3 30ec 	ldr.w	r3, [r3, #236]	@ 0xec
+ 8029426:	4a20      	ldr	r2, [pc, #128]	@ (80294a8 <HAL_FDCAN_MspInit+0x1b0>)
+ 8029428:	f443 7380 	orr.w	r3, r3, #256	@ 0x100
+ 802942c:	f8c2 30ec 	str.w	r3, [r2, #236]	@ 0xec
+ 8029430:	4b1d      	ldr	r3, [pc, #116]	@ (80294a8 <HAL_FDCAN_MspInit+0x1b0>)
+ 8029432:	f8d3 30ec 	ldr.w	r3, [r3, #236]	@ 0xec
+ 8029436:	f403 7380 	and.w	r3, r3, #256	@ 0x100
+ 802943a:	60fb      	str	r3, [r7, #12]
+ 802943c:	68fb      	ldr	r3, [r7, #12]
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+ 802943e:	4b1a      	ldr	r3, [pc, #104]	@ (80294a8 <HAL_FDCAN_MspInit+0x1b0>)
+ 8029440:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
+ 8029444:	4a18      	ldr	r2, [pc, #96]	@ (80294a8 <HAL_FDCAN_MspInit+0x1b0>)
+ 8029446:	f043 0302 	orr.w	r3, r3, #2
+ 802944a:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
+ 802944e:	4b16      	ldr	r3, [pc, #88]	@ (80294a8 <HAL_FDCAN_MspInit+0x1b0>)
+ 8029450:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
+ 8029454:	f003 0302 	and.w	r3, r3, #2
+ 8029458:	60bb      	str	r3, [r7, #8]
+ 802945a:	68bb      	ldr	r3, [r7, #8]
+    GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6;
+ 802945c:	2360      	movs	r3, #96	@ 0x60
+ 802945e:	f8c7 30dc 	str.w	r3, [r7, #220]	@ 0xdc
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 8029462:	2302      	movs	r3, #2
+ 8029464:	f8c7 30e0 	str.w	r3, [r7, #224]	@ 0xe0
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 8029468:	2300      	movs	r3, #0
+ 802946a:	f8c7 30e4 	str.w	r3, [r7, #228]	@ 0xe4
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 802946e:	2300      	movs	r3, #0
+ 8029470:	f8c7 30e8 	str.w	r3, [r7, #232]	@ 0xe8
+    GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN2;
+ 8029474:	2309      	movs	r3, #9
+ 8029476:	f8c7 30ec 	str.w	r3, [r7, #236]	@ 0xec
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+ 802947a:	f107 03dc 	add.w	r3, r7, #220	@ 0xdc
+ 802947e:	4619      	mov	r1, r3
+ 8029480:	480a      	ldr	r0, [pc, #40]	@ (80294ac <HAL_FDCAN_MspInit+0x1b4>)
+ 8029482:	f00e f8ab 	bl	80375dc <HAL_GPIO_Init>
+    HAL_NVIC_SetPriority(FDCAN2_IT0_IRQn, 0, 0);
+ 8029486:	2200      	movs	r2, #0
+ 8029488:	2100      	movs	r1, #0
+ 802948a:	2014      	movs	r0, #20
+ 802948c:	f009 fb11 	bl	8032ab2 <HAL_NVIC_SetPriority>
+    HAL_NVIC_EnableIRQ(FDCAN2_IT0_IRQn);
+ 8029490:	2014      	movs	r0, #20
+ 8029492:	f009 fb28 	bl	8032ae6 <HAL_NVIC_EnableIRQ>
+}
+ 8029496:	bf00      	nop
+ 8029498:	37f0      	adds	r7, #240	@ 0xf0
+ 802949a:	46bd      	mov	sp, r7
+ 802949c:	bd80      	pop	{r7, pc}
+ 802949e:	bf00      	nop
+ 80294a0:	4000a000 	.word	0x4000a000
+ 80294a4:	2400a6b8 	.word	0x2400a6b8
+ 80294a8:	58024400 	.word	0x58024400
+ 80294ac:	58020400 	.word	0x58020400
+ 80294b0:	4000a400 	.word	0x4000a400
+
+080294b4 <Fsm_Init>:
+{ Move_Horizontal_Task_Forwards, Move_Horizontal_Vertical_Task_Forwards_Do_Forwards },//水平前向运动
+{ Move_Horizontal_Task_Backwards, Move_Horizontal_Vertical_Task_Backwards_Do_Backward },//水平后退运动
+};
+
+void Fsm_Init()
+{
+ 80294b4:	b580      	push	{r7, lr}
+ 80294b6:	af00      	add	r7, sp, #0
+
+	GF_BSP_Interrupt_Add_CallBack(DF_BSP_InterCall_TIM8_2ms_PeriodElapsedCallback, GF_Dispatch);
+ 80294b8:	4902      	ldr	r1, [pc, #8]	@ (80294c4 <Fsm_Init+0x10>)
+ 80294ba:	200a      	movs	r0, #10
+ 80294bc:	f7f7 ff18 	bl	80212f0 <GF_BSP_Interrupt_Add_CallBack>
+}
+ 80294c0:	bf00      	nop
+ 80294c2:	bd80      	pop	{r7, pc}
+ 80294c4:	080294c9 	.word	0x080294c9
+
+080294c8 <GF_Dispatch>:
+double MF40G_Angle_Add_Deg=0;
+int MF40G_Angle_Add_Count=0;
+
+int stop_flag = 0;
+void GF_Dispatch()
+{
+ 80294c8:	b580      	push	{r7, lr}
+ 80294ca:	b088      	sub	sp, #32
+ 80294cc:	af00      	add	r7, sp, #0
+	if(P_MK32->CH7_SD != -1000)
+ 80294ce:	4bb6      	ldr	r3, [pc, #728]	@ (80297a8 <GF_Dispatch+0x2e0>)
+ 80294d0:	681b      	ldr	r3, [r3, #0]
+ 80294d2:	6a1b      	ldr	r3, [r3, #32]
+ 80294d4:	f513 7f7a 	cmn.w	r3, #1000	@ 0x3e8
+ 80294d8:	d001      	beq.n	80294de <GF_Dispatch+0x16>
+	{
+		Blast_Machine_Control_Fun();
+ 80294da:	f7fc ff67 	bl	80263ac <Blast_Machine_Control_Fun>
+	}
+
+	MF40G_Angle_Add_Count++;
+ 80294de:	4bb3      	ldr	r3, [pc, #716]	@ (80297ac <GF_Dispatch+0x2e4>)
+ 80294e0:	681b      	ldr	r3, [r3, #0]
+ 80294e2:	3301      	adds	r3, #1
+ 80294e4:	4ab1      	ldr	r2, [pc, #708]	@ (80297ac <GF_Dispatch+0x2e4>)
+ 80294e6:	6013      	str	r3, [r2, #0]
+	MF40G_Angle_Add_Deg=GV.MFOG40_Plane.gyro_angular-MF40G_Angle_Add_Count*MF40G_Angle_Add_Count_Fact;
+ 80294e8:	4bb1      	ldr	r3, [pc, #708]	@ (80297b0 <GF_Dispatch+0x2e8>)
+ 80294ea:	ed93 6b9e 	vldr	d6, [r3, #632]	@ 0x278
+ 80294ee:	4baf      	ldr	r3, [pc, #700]	@ (80297ac <GF_Dispatch+0x2e4>)
+ 80294f0:	681b      	ldr	r3, [r3, #0]
+ 80294f2:	ee07 3a90 	vmov	s15, r3
+ 80294f6:	eeb8 5be7 	vcvt.f64.s32	d5, s15
+ 80294fa:	4bae      	ldr	r3, [pc, #696]	@ (80297b4 <GF_Dispatch+0x2ec>)
+ 80294fc:	ed93 7b00 	vldr	d7, [r3]
+ 8029500:	ee25 7b07 	vmul.f64	d7, d5, d7
+ 8029504:	ee36 7b47 	vsub.f64	d7, d6, d7
+ 8029508:	4bab      	ldr	r3, [pc, #684]	@ (80297b8 <GF_Dispatch+0x2f0>)
+ 802950a:	ed83 7b00 	vstr	d7, [r3]
+	if(MF40G_Angle_Add_Deg>180)
+ 802950e:	4baa      	ldr	r3, [pc, #680]	@ (80297b8 <GF_Dispatch+0x2f0>)
+ 8029510:	ed93 7b00 	vldr	d7, [r3]
+ 8029514:	ed9f 6b9a 	vldr	d6, [pc, #616]	@ 8029780 <GF_Dispatch+0x2b8>
+ 8029518:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 802951c:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 8029520:	dd0a      	ble.n	8029538 <GF_Dispatch+0x70>
+	{
+		MF40G_Angle_Add_Deg=MF40G_Angle_Add_Deg-360;
+ 8029522:	4ba5      	ldr	r3, [pc, #660]	@ (80297b8 <GF_Dispatch+0x2f0>)
+ 8029524:	ed93 7b00 	vldr	d7, [r3]
+ 8029528:	ed9f 6b97 	vldr	d6, [pc, #604]	@ 8029788 <GF_Dispatch+0x2c0>
+ 802952c:	ee37 7b46 	vsub.f64	d7, d7, d6
+ 8029530:	4ba1      	ldr	r3, [pc, #644]	@ (80297b8 <GF_Dispatch+0x2f0>)
+ 8029532:	ed83 7b00 	vstr	d7, [r3]
+ 8029536:	e013      	b.n	8029560 <GF_Dispatch+0x98>
+	}
+	else if(MF40G_Angle_Add_Deg<-180)
+ 8029538:	4b9f      	ldr	r3, [pc, #636]	@ (80297b8 <GF_Dispatch+0x2f0>)
+ 802953a:	ed93 7b00 	vldr	d7, [r3]
+ 802953e:	ed9f 6b94 	vldr	d6, [pc, #592]	@ 8029790 <GF_Dispatch+0x2c8>
+ 8029542:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 8029546:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802954a:	d509      	bpl.n	8029560 <GF_Dispatch+0x98>
+	{
+		MF40G_Angle_Add_Deg=MF40G_Angle_Add_Deg+360;
+ 802954c:	4b9a      	ldr	r3, [pc, #616]	@ (80297b8 <GF_Dispatch+0x2f0>)
+ 802954e:	ed93 7b00 	vldr	d7, [r3]
+ 8029552:	ed9f 6b8d 	vldr	d6, [pc, #564]	@ 8029788 <GF_Dispatch+0x2c0>
+ 8029556:	ee37 7b06 	vadd.f64	d7, d7, d6
+ 802955a:	4b97      	ldr	r3, [pc, #604]	@ (80297b8 <GF_Dispatch+0x2f0>)
+ 802955c:	ed83 7b00 	vstr	d7, [r3]
+	}
+	//EmergencyStop_Hardware_Communication_Detection_1();
+	  EmergencyStop_Hardware_Communication_Detection();
+ 8029560:	f005 f818 	bl	802e594 <EmergencyStop_Hardware_Communication_Detection>
+//	if(GV.SystemErrorData.ErrorCode != 0 && GV.SystemErrorData.ErrorCode != 2)
+//	{
+//		Blast_Machine_Control_Fun();
+//	}
+
+	  switch (Robot_Main_Flag)
+ 8029564:	4b95      	ldr	r3, [pc, #596]	@ (80297bc <GF_Dispatch+0x2f4>)
+ 8029566:	681b      	ldr	r3, [r3, #0]
+ 8029568:	2b02      	cmp	r3, #2
+ 802956a:	f000 8131 	beq.w	80297d0 <GF_Dispatch+0x308>
+ 802956e:	2b02      	cmp	r3, #2
+ 8029570:	f300 8134 	bgt.w	80297dc <GF_Dispatch+0x314>
+ 8029574:	2b00      	cmp	r3, #0
+ 8029576:	d002      	beq.n	802957e <GF_Dispatch+0xb6>
+ 8029578:	2b01      	cmp	r3, #1
+ 802957a:	d07d      	beq.n	8029678 <GF_Dispatch+0x1b0>
+ 802957c:	e12e      	b.n	80297dc <GF_Dispatch+0x314>
+		  case Serial_Mode_Config://读取串口模式，推杆手动控制在其中，机器人运动则进入下一模式中；
+//			  Markkk = 0;
+//			  GV.SwingMotor.Position_immediately1_Lag2=AAAAA;
+//			  GV.SwingMotor.Tar_Position_count=BBBBB;
+//			  GV.SwingMotor.Tar_Position_Velcity_RPM=CCCCC;
+			  GV_Operation_Mode=(int)CV.PV.Robot_Operation_Mode;
+ 802957e:	4b90      	ldr	r3, [pc, #576]	@ (80297c0 <GF_Dispatch+0x2f8>)
+ 8029580:	685b      	ldr	r3, [r3, #4]
+ 8029582:	4a90      	ldr	r2, [pc, #576]	@ (80297c4 <GF_Dispatch+0x2fc>)
+ 8029584:	6013      	str	r3, [r2, #0]
+
+			  if(ctl_flag == 1)//自动喷砂结束关闭喷砂机
+ 8029586:	4b90      	ldr	r3, [pc, #576]	@ (80297c8 <GF_Dispatch+0x300>)
+ 8029588:	681b      	ldr	r3, [r3, #0]
+ 802958a:	2b01      	cmp	r3, #1
+ 802958c:	d104      	bne.n	8029598 <GF_Dispatch+0xd0>
+			  {
+				  Blast_Machine_Close_Fun();
+ 802958e:	f7fd f817 	bl	80265c0 <Blast_Machine_Close_Fun>
+				  ctl_flag = 0;
+ 8029592:	4b8d      	ldr	r3, [pc, #564]	@ (80297c8 <GF_Dispatch+0x300>)
+ 8029594:	2200      	movs	r2, #0
+ 8029596:	601a      	str	r2, [r3, #0]
+			  }
+
+//			  PushRod_Contronl();//推杆上下停止控制
+
+			  double y_value = P_MK32->CH2_LY_V; // 假设 Y 是纵向（前后）
+ 8029598:	4b83      	ldr	r3, [pc, #524]	@ (80297a8 <GF_Dispatch+0x2e0>)
+ 802959a:	681b      	ldr	r3, [r3, #0]
+ 802959c:	68db      	ldr	r3, [r3, #12]
+ 802959e:	ee07 3a90 	vmov	s15, r3
+ 80295a2:	eeb8 7be7 	vcvt.f64.s32	d7, s15
+ 80295a6:	ed87 7b06 	vstr	d7, [r7, #24]
+			  double x_value = P_MK32->CH3_LY_H; // 假设 X 是横向（左右）
+ 80295aa:	4b7f      	ldr	r3, [pc, #508]	@ (80297a8 <GF_Dispatch+0x2e0>)
+ 80295ac:	681b      	ldr	r3, [r3, #0]
+ 80295ae:	691b      	ldr	r3, [r3, #16]
+ 80295b0:	ee07 3a90 	vmov	s15, r3
+ 80295b4:	eeb8 7be7 	vcvt.f64.s32	d7, s15
+ 80295b8:	ed87 7b04 	vstr	d7, [r7, #16]
+
+			  double w_value = P_MK32->CH0_RY_H; // 假设 X 是横向（左右）
+ 80295bc:	4b7a      	ldr	r3, [pc, #488]	@ (80297a8 <GF_Dispatch+0x2e0>)
+ 80295be:	681b      	ldr	r3, [r3, #0]
+ 80295c0:	685b      	ldr	r3, [r3, #4]
+ 80295c2:	ee07 3a90 	vmov	s15, r3
+ 80295c6:	eeb8 7be7 	vcvt.f64.s32	d7, s15
+ 80295ca:	ed87 7b02 	vstr	d7, [r7, #8]
+			  double z_value = P_MK32->CH1_RY_V; // 假设 X 是横向（左右）
+ 80295ce:	4b76      	ldr	r3, [pc, #472]	@ (80297a8 <GF_Dispatch+0x2e0>)
+ 80295d0:	681b      	ldr	r3, [r3, #0]
+ 80295d2:	689b      	ldr	r3, [r3, #8]
+ 80295d4:	ee07 3a90 	vmov	s15, r3
+ 80295d8:	eeb8 7be7 	vcvt.f64.s32	d7, s15
+ 80295dc:	ed87 7b00 	vstr	d7, [r7]
+
+			  if((fabs(y_value)>=300)||(fabs(x_value)>=300)||(P_MK32->CH7_SD==-1000)||(P_MK32->CH4_SA!=0)
+ 80295e0:	ed97 7b06 	vldr	d7, [r7, #24]
+ 80295e4:	eeb0 7bc7 	vabs.f64	d7, d7
+ 80295e8:	ed9f 6b6b 	vldr	d6, [pc, #428]	@ 8029798 <GF_Dispatch+0x2d0>
+ 80295ec:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 80295f0:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 80295f4:	da30      	bge.n	8029658 <GF_Dispatch+0x190>
+ 80295f6:	ed97 7b04 	vldr	d7, [r7, #16]
+ 80295fa:	eeb0 7bc7 	vabs.f64	d7, d7
+ 80295fe:	ed9f 6b66 	vldr	d6, [pc, #408]	@ 8029798 <GF_Dispatch+0x2d0>
+ 8029602:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 8029606:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802960a:	da25      	bge.n	8029658 <GF_Dispatch+0x190>
+ 802960c:	4b66      	ldr	r3, [pc, #408]	@ (80297a8 <GF_Dispatch+0x2e0>)
+ 802960e:	681b      	ldr	r3, [r3, #0]
+ 8029610:	6a1b      	ldr	r3, [r3, #32]
+ 8029612:	f513 7f7a 	cmn.w	r3, #1000	@ 0x3e8
+ 8029616:	d01f      	beq.n	8029658 <GF_Dispatch+0x190>
+ 8029618:	4b63      	ldr	r3, [pc, #396]	@ (80297a8 <GF_Dispatch+0x2e0>)
+ 802961a:	681b      	ldr	r3, [r3, #0]
+ 802961c:	695b      	ldr	r3, [r3, #20]
+ 802961e:	2b00      	cmp	r3, #0
+ 8029620:	d11a      	bne.n	8029658 <GF_Dispatch+0x190>
+					  ||(fabs(w_value)>=300)||(fabs(z_value)>=300)||(P_MK32->CH5_SB!=0))
+ 8029622:	ed97 7b02 	vldr	d7, [r7, #8]
+ 8029626:	eeb0 7bc7 	vabs.f64	d7, d7
+ 802962a:	ed9f 6b5b 	vldr	d6, [pc, #364]	@ 8029798 <GF_Dispatch+0x2d0>
+ 802962e:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 8029632:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 8029636:	da0f      	bge.n	8029658 <GF_Dispatch+0x190>
+ 8029638:	ed97 7b00 	vldr	d7, [r7]
+ 802963c:	eeb0 7bc7 	vabs.f64	d7, d7
+ 8029640:	ed9f 6b55 	vldr	d6, [pc, #340]	@ 8029798 <GF_Dispatch+0x2d0>
+ 8029644:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 8029648:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802964c:	da04      	bge.n	8029658 <GF_Dispatch+0x190>
+ 802964e:	4b56      	ldr	r3, [pc, #344]	@ (80297a8 <GF_Dispatch+0x2e0>)
+ 8029650:	681b      	ldr	r3, [r3, #0]
+ 8029652:	699b      	ldr	r3, [r3, #24]
+ 8029654:	2b00      	cmp	r3, #0
+ 8029656:	d004      	beq.n	8029662 <GF_Dispatch+0x19a>
+			  {
+				  Robot_Main_Flag++;
+ 8029658:	4b58      	ldr	r3, [pc, #352]	@ (80297bc <GF_Dispatch+0x2f4>)
+ 802965a:	681b      	ldr	r3, [r3, #0]
+ 802965c:	3301      	adds	r3, #1
+ 802965e:	4a57      	ldr	r2, [pc, #348]	@ (80297bc <GF_Dispatch+0x2f4>)
+ 8029660:	6013      	str	r3, [r2, #0]
+			  }
+
+			  //计划将机器人运动参数计算，需要放在此处，但暂时还没做
+			  PV_Data_Reading();
+ 8029662:	f004 fe9d 	bl	802e3a0 <PV_Data_Reading>
+			  Move_Speed_Define();
+ 8029666:	f002 fbb5 	bl	802bdd4 <Move_Speed_Define>
+			  Horiz_Angle_Judge();
+ 802966a:	f001 ffed 	bl	802b648 <Horiz_Angle_Judge>
+			  Robot_Halt_Mode();
+ 802966e:	f000 f907 	bl	8029880 <Robot_Halt_Mode>
+			  Swing_Mode_Determination();
+ 8029672:	f005 fc3d 	bl	802eef0 <Swing_Mode_Determination>
+			  break;
+ 8029676:	e0b1      	b.n	80297dc <GF_Dispatch+0x314>
+		  case Action_Execute:
+			  switch (GV_Operation_Mode)
+ 8029678:	4b52      	ldr	r3, [pc, #328]	@ (80297c4 <GF_Dispatch+0x2fc>)
+ 802967a:	681b      	ldr	r3, [r3, #0]
+ 802967c:	2b07      	cmp	r3, #7
+ 802967e:	d875      	bhi.n	802976c <GF_Dispatch+0x2a4>
+ 8029680:	a201      	add	r2, pc, #4	@ (adr r2, 8029688 <GF_Dispatch+0x1c0>)
+ 8029682:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 8029686:	bf00      	nop
+ 8029688:	080296a9 	.word	0x080296a9
+ 802968c:	080296bd 	.word	0x080296bd
+ 8029690:	080296d1 	.word	0x080296d1
+ 8029694:	080296eb 	.word	0x080296eb
+ 8029698:	08029705 	.word	0x08029705
+ 802969c:	0802971f 	.word	0x0802971f
+ 80296a0:	08029739 	.word	0x08029739
+ 80296a4:	08029753 	.word	0x08029753
+			  {
+				 case Halt_Mode:
+					  Robot_Halt_Mode();
+ 80296a8:	f000 f8ea 	bl	8029880 <Robot_Halt_Mode>
+					  Robot_Angle_G_P_Deg=0;
+ 80296ac:	4947      	ldr	r1, [pc, #284]	@ (80297cc <GF_Dispatch+0x304>)
+ 80296ae:	f04f 0200 	mov.w	r2, #0
+ 80296b2:	f04f 0300 	mov.w	r3, #0
+ 80296b6:	e9c1 2300 	strd	r2, r3, [r1]
+					  break;
+ 80296ba:	e05d      	b.n	8029778 <GF_Dispatch+0x2b0>
+				  case Manual_Mode:
+					  Robot_Manual_Operation_Mode();//手动操作//已检查无问题
+ 80296bc:	f000 f8f0 	bl	80298a0 <Robot_Manual_Operation_Mode>
+					  Robot_Angle_G_P_Deg=0;
+ 80296c0:	4942      	ldr	r1, [pc, #264]	@ (80297cc <GF_Dispatch+0x304>)
+ 80296c2:	f04f 0200 	mov.w	r2, #0
+ 80296c6:	f04f 0300 	mov.w	r3, #0
+ 80296ca:	e9c1 2300 	strd	r2, r3, [r1]
+					  break;
+ 80296ce:	e053      	b.n	8029778 <GF_Dispatch+0x2b0>
+				  case Horizontal_Mode:
+					  Horizontal_Operatin_Main_Func();
+ 80296d0:	f000 fabe 	bl	8029c50 <Horizontal_Operatin_Main_Func>
+					  Robot_Angle_G_P_Deg=GV.TL720DParameters.RF_Angle_Roll;
+ 80296d4:	4b36      	ldr	r3, [pc, #216]	@ (80297b0 <GF_Dispatch+0x2e8>)
+ 80296d6:	f8d3 3218 	ldr.w	r3, [r3, #536]	@ 0x218
+ 80296da:	ee07 3a90 	vmov	s15, r3
+ 80296de:	eeb8 7be7 	vcvt.f64.s32	d7, s15
+ 80296e2:	4b3a      	ldr	r3, [pc, #232]	@ (80297cc <GF_Dispatch+0x304>)
+ 80296e4:	ed83 7b00 	vstr	d7, [r3]
+					  break;
+ 80296e8:	e046      	b.n	8029778 <GF_Dispatch+0x2b0>
+				  case Flat_Mode:
+					  Plane_Operatin_Main_Func();
+ 80296ea:	f000 ff2f 	bl	802a54c <Plane_Operatin_Main_Func>
+//					  Markkk = 333;
+					  Robot_Angle_G_P_Deg=MF40G_Angle_Add_Deg*100;
+ 80296ee:	4b32      	ldr	r3, [pc, #200]	@ (80297b8 <GF_Dispatch+0x2f0>)
+ 80296f0:	ed93 7b00 	vldr	d7, [r3]
+ 80296f4:	ed9f 6b2a 	vldr	d6, [pc, #168]	@ 80297a0 <GF_Dispatch+0x2d8>
+ 80296f8:	ee27 7b06 	vmul.f64	d7, d7, d6
+ 80296fc:	4b33      	ldr	r3, [pc, #204]	@ (80297cc <GF_Dispatch+0x304>)
+ 80296fe:	ed83 7b00 	vstr	d7, [r3]
+					  break;
+ 8029702:	e039      	b.n	8029778 <GF_Dispatch+0x2b0>
+				  case Vertical_Mode_Left:
+					  Vertical_Operatin_Main_Func_Left();
+ 8029704:	f000 fcf0 	bl	802a0e8 <Vertical_Operatin_Main_Func_Left>
+					  Robot_Angle_G_P_Deg=GV.TL720DParameters.RF_Angle_Roll;
+ 8029708:	4b29      	ldr	r3, [pc, #164]	@ (80297b0 <GF_Dispatch+0x2e8>)
+ 802970a:	f8d3 3218 	ldr.w	r3, [r3, #536]	@ 0x218
+ 802970e:	ee07 3a90 	vmov	s15, r3
+ 8029712:	eeb8 7be7 	vcvt.f64.s32	d7, s15
+ 8029716:	4b2d      	ldr	r3, [pc, #180]	@ (80297cc <GF_Dispatch+0x304>)
+ 8029718:	ed83 7b00 	vstr	d7, [r3]
+					  break;
+ 802971c:	e02c      	b.n	8029778 <GF_Dispatch+0x2b0>
+				  case Vertical_Mode_Right:
+					  Vertical_Operatin_Main_Func_Right();//今日检查
+ 802971e:	f000 fd6f 	bl	802a200 <Vertical_Operatin_Main_Func_Right>
+					  Robot_Angle_G_P_Deg=GV.TL720DParameters.RF_Angle_Roll;
+ 8029722:	4b23      	ldr	r3, [pc, #140]	@ (80297b0 <GF_Dispatch+0x2e8>)
+ 8029724:	f8d3 3218 	ldr.w	r3, [r3, #536]	@ 0x218
+ 8029728:	ee07 3a90 	vmov	s15, r3
+ 802972c:	eeb8 7be7 	vcvt.f64.s32	d7, s15
+ 8029730:	4b26      	ldr	r3, [pc, #152]	@ (80297cc <GF_Dispatch+0x304>)
+ 8029732:	ed83 7b00 	vstr	d7, [r3]
+					  break;
+ 8029736:	e01f      	b.n	8029778 <GF_Dispatch+0x2b0>
+				  case Regional_Horizontal_Automatic_Task:
+					  Regional_Horizontal_Automatic_Functionc();//待检查
+ 8029738:	f005 f81c 	bl	802e774 <Regional_Horizontal_Automatic_Functionc>
+					  Robot_Angle_G_P_Deg=GV.TL720DParameters.RF_Angle_Roll;
+ 802973c:	4b1c      	ldr	r3, [pc, #112]	@ (80297b0 <GF_Dispatch+0x2e8>)
+ 802973e:	f8d3 3218 	ldr.w	r3, [r3, #536]	@ 0x218
+ 8029742:	ee07 3a90 	vmov	s15, r3
+ 8029746:	eeb8 7be7 	vcvt.f64.s32	d7, s15
+ 802974a:	4b20      	ldr	r3, [pc, #128]	@ (80297cc <GF_Dispatch+0x304>)
+ 802974c:	ed83 7b00 	vstr	d7, [r3]
+					  break;
+ 8029750:	e012      	b.n	8029778 <GF_Dispatch+0x2b0>
+				  case Regional_Flat_Automatic_Task:
+					  Regional_Plane_Automatic_Functionc();
+ 8029752:	f005 f87d 	bl	802e850 <Regional_Plane_Automatic_Functionc>
+					  Robot_Angle_G_P_Deg=MF40G_Angle_Add_Deg*100;
+ 8029756:	4b18      	ldr	r3, [pc, #96]	@ (80297b8 <GF_Dispatch+0x2f0>)
+ 8029758:	ed93 7b00 	vldr	d7, [r3]
+ 802975c:	ed9f 6b10 	vldr	d6, [pc, #64]	@ 80297a0 <GF_Dispatch+0x2d8>
+ 8029760:	ee27 7b06 	vmul.f64	d7, d7, d6
+ 8029764:	4b19      	ldr	r3, [pc, #100]	@ (80297cc <GF_Dispatch+0x304>)
+ 8029766:	ed83 7b00 	vstr	d7, [r3]
+					  break;
+ 802976a:	e005      	b.n	8029778 <GF_Dispatch+0x2b0>
+				default:
+					Robot_Main_Flag=Serial_Mode_Config;
+ 802976c:	4b13      	ldr	r3, [pc, #76]	@ (80297bc <GF_Dispatch+0x2f4>)
+ 802976e:	2200      	movs	r2, #0
+ 8029770:	601a      	str	r2, [r3, #0]
+					Robot_Halt_Mode();
+ 8029772:	f000 f885 	bl	8029880 <Robot_Halt_Mode>
+					 break;
+ 8029776:	bf00      	nop
+			  }
+		  	  break;
+ 8029778:	e030      	b.n	80297dc <GF_Dispatch+0x314>
+ 802977a:	bf00      	nop
+ 802977c:	f3af 8000 	nop.w
+ 8029780:	00000000 	.word	0x00000000
+ 8029784:	40668000 	.word	0x40668000
+ 8029788:	00000000 	.word	0x00000000
+ 802978c:	40768000 	.word	0x40768000
+ 8029790:	00000000 	.word	0x00000000
+ 8029794:	c0668000 	.word	0xc0668000
+ 8029798:	00000000 	.word	0x00000000
+ 802979c:	4072c000 	.word	0x4072c000
+ 80297a0:	00000000 	.word	0x00000000
+ 80297a4:	40590000 	.word	0x40590000
+ 80297a8:	2400a3f8 	.word	0x2400a3f8
+ 80297ac:	2400a790 	.word	0x2400a790
+ 80297b0:	24000340 	.word	0x24000340
+ 80297b4:	240000f8 	.word	0x240000f8
+ 80297b8:	2400a788 	.word	0x2400a788
+ 80297bc:	2400a77c 	.word	0x2400a77c
+ 80297c0:	240002a0 	.word	0x240002a0
+ 80297c4:	2400a750 	.word	0x2400a750
+ 80297c8:	2400a770 	.word	0x2400a770
+ 80297cc:	2400a780 	.word	0x2400a780
+		  case Action_Shut_down:
+			  Robot_Halt_Mode();
+ 80297d0:	f000 f856 	bl	8029880 <Robot_Halt_Mode>
+			  Robot_Main_Flag=Serial_Mode_Config;
+ 80297d4:	4b0c      	ldr	r3, [pc, #48]	@ (8029808 <GF_Dispatch+0x340>)
+ 80297d6:	2200      	movs	r2, #0
+ 80297d8:	601a      	str	r2, [r3, #0]
+			  break;
+ 80297da:	bf00      	nop
+	  }
+//	IV_control();
+
+	if(MF40G_Angle_Add_Count%10==0)
+ 80297dc:	4b0b      	ldr	r3, [pc, #44]	@ (802980c <GF_Dispatch+0x344>)
+ 80297de:	6819      	ldr	r1, [r3, #0]
+ 80297e0:	4b0b      	ldr	r3, [pc, #44]	@ (8029810 <GF_Dispatch+0x348>)
+ 80297e2:	fb83 2301 	smull	r2, r3, r3, r1
+ 80297e6:	109a      	asrs	r2, r3, #2
+ 80297e8:	17cb      	asrs	r3, r1, #31
+ 80297ea:	1ad2      	subs	r2, r2, r3
+ 80297ec:	4613      	mov	r3, r2
+ 80297ee:	009b      	lsls	r3, r3, #2
+ 80297f0:	4413      	add	r3, r2
+ 80297f2:	005b      	lsls	r3, r3, #1
+ 80297f4:	1aca      	subs	r2, r1, r3
+ 80297f6:	2a00      	cmp	r2, #0
+ 80297f8:	d101      	bne.n	80297fe <GF_Dispatch+0x336>
+	{
+		IV_control_1();
+ 80297fa:	f004 fd39 	bl	802e270 <IV_control_1>
+	}
+}
+ 80297fe:	bf00      	nop
+ 8029800:	3720      	adds	r7, #32
+ 8029802:	46bd      	mov	sp, r7
+ 8029804:	bd80      	pop	{r7, pc}
+ 8029806:	bf00      	nop
+ 8029808:	2400a77c 	.word	0x2400a77c
+ 802980c:	2400a790 	.word	0x2400a790
+ 8029810:	66666667 	.word	0x66666667
+
+08029814 <action_perfrom>:
+
+
+
+void action_perfrom(transition_t transitions[], int length, int state)
+{
+ 8029814:	b580      	push	{r7, lr}
+ 8029816:	b084      	sub	sp, #16
+ 8029818:	af00      	add	r7, sp, #0
+ 802981a:	60f8      	str	r0, [r7, #12]
+ 802981c:	60b9      	str	r1, [r7, #8]
+ 802981e:	607a      	str	r2, [r7, #4]
+
+	for (index_counter = 0; index_counter < length; index_counter++)
+ 8029820:	4b16      	ldr	r3, [pc, #88]	@ (802987c <action_perfrom+0x68>)
+ 8029822:	2200      	movs	r2, #0
+ 8029824:	601a      	str	r2, [r3, #0]
+ 8029826:	e01d      	b.n	8029864 <action_perfrom+0x50>
+	{
+		if (transitions[index_counter].State == state)
+ 8029828:	4b14      	ldr	r3, [pc, #80]	@ (802987c <action_perfrom+0x68>)
+ 802982a:	681b      	ldr	r3, [r3, #0]
+ 802982c:	00db      	lsls	r3, r3, #3
+ 802982e:	68fa      	ldr	r2, [r7, #12]
+ 8029830:	4413      	add	r3, r2
+ 8029832:	681b      	ldr	r3, [r3, #0]
+ 8029834:	687a      	ldr	r2, [r7, #4]
+ 8029836:	429a      	cmp	r2, r3
+ 8029838:	d10f      	bne.n	802985a <action_perfrom+0x46>
+		{
+			if (transitions[index_counter].robotRun != NULL)
+ 802983a:	4b10      	ldr	r3, [pc, #64]	@ (802987c <action_perfrom+0x68>)
+ 802983c:	681b      	ldr	r3, [r3, #0]
+ 802983e:	00db      	lsls	r3, r3, #3
+ 8029840:	68fa      	ldr	r2, [r7, #12]
+ 8029842:	4413      	add	r3, r2
+ 8029844:	685b      	ldr	r3, [r3, #4]
+ 8029846:	2b00      	cmp	r3, #0
+ 8029848:	d012      	beq.n	8029870 <action_perfrom+0x5c>
+			{
+				transitions[index_counter].robotRun();
+ 802984a:	4b0c      	ldr	r3, [pc, #48]	@ (802987c <action_perfrom+0x68>)
+ 802984c:	681b      	ldr	r3, [r3, #0]
+ 802984e:	00db      	lsls	r3, r3, #3
+ 8029850:	68fa      	ldr	r2, [r7, #12]
+ 8029852:	4413      	add	r3, r2
+ 8029854:	685b      	ldr	r3, [r3, #4]
+ 8029856:	4798      	blx	r3
+			}
+
+			break;
+ 8029858:	e00a      	b.n	8029870 <action_perfrom+0x5c>
+	for (index_counter = 0; index_counter < length; index_counter++)
+ 802985a:	4b08      	ldr	r3, [pc, #32]	@ (802987c <action_perfrom+0x68>)
+ 802985c:	681b      	ldr	r3, [r3, #0]
+ 802985e:	3301      	adds	r3, #1
+ 8029860:	4a06      	ldr	r2, [pc, #24]	@ (802987c <action_perfrom+0x68>)
+ 8029862:	6013      	str	r3, [r2, #0]
+ 8029864:	4b05      	ldr	r3, [pc, #20]	@ (802987c <action_perfrom+0x68>)
+ 8029866:	681b      	ldr	r3, [r3, #0]
+ 8029868:	68ba      	ldr	r2, [r7, #8]
+ 802986a:	429a      	cmp	r2, r3
+ 802986c:	dcdc      	bgt.n	8029828 <action_perfrom+0x14>
+			//return;
+		}
+	}
+}
+ 802986e:	e000      	b.n	8029872 <action_perfrom+0x5e>
+			break;
+ 8029870:	bf00      	nop
+}
+ 8029872:	bf00      	nop
+ 8029874:	3710      	adds	r7, #16
+ 8029876:	46bd      	mov	sp, r7
+ 8029878:	bd80      	pop	{r7, pc}
+ 802987a:	bf00      	nop
+ 802987c:	2400a6bc 	.word	0x2400a6bc
+
+08029880 <Robot_Halt_Mode>:
+
+
+
+
+void Robot_Halt_Mode()
+{
+ 8029880:	b580      	push	{r7, lr}
+ 8029882:	af00      	add	r7, sp, #0
+	GV.LeftMotor.Target_Velcity  = 0;
+ 8029884:	4b05      	ldr	r3, [pc, #20]	@ (802989c <Robot_Halt_Mode+0x1c>)
+ 8029886:	2200      	movs	r2, #0
+ 8029888:	679a      	str	r2, [r3, #120]	@ 0x78
+	GV.RightMotor.Target_Velcity  = 0;
+ 802988a:	4b04      	ldr	r3, [pc, #16]	@ (802989c <Robot_Halt_Mode+0x1c>)
+ 802988c:	2200      	movs	r2, #0
+ 802988e:	f8c3 20f8 	str.w	r2, [r3, #248]	@ 0xf8
+	Move_Swing_Halt_Func_Do();
+ 8029892:	f003 fdcf 	bl	802d434 <Move_Swing_Halt_Func_Do>
+}
+ 8029896:	bf00      	nop
+ 8029898:	bd80      	pop	{r7, pc}
+ 802989a:	bf00      	nop
+ 802989c:	24000340 	.word	0x24000340
+
+080298a0 <Robot_Manual_Operation_Mode>:
+
+
+void Robot_Manual_Operation_Mode()
+{
+ 80298a0:	b580      	push	{r7, lr}
+ 80298a2:	af00      	add	r7, sp, #0
+//		PushRod_Contronl();//推杆上下停止控制
+		Robot_Manual_Operation_Function();
+ 80298a4:	f000 f89c 	bl	80299e0 <Robot_Manual_Operation_Function>
+		Robot_Main_Mode_Jude();
+ 80298a8:	f004 fdf2 	bl	802e490 <Robot_Main_Mode_Jude>
+		UltraStopReverse_Manually_Backward();
+ 80298ac:	f000 f866 	bl	802997c <UltraStopReverse_Manually_Backward>
+		PushRod_Contronl();
+ 80298b0:	f000 f86c 	bl	802998c <PushRod_Contronl>
+//		Pressure_Adaptive_Function_Uptata(200);
+//		PushRod_Contronl();//推杆上下停止控制
+}
+ 80298b4:	bf00      	nop
+ 80298b6:	bd80      	pop	{r7, pc}
+
+080298b8 <UltraStopReverse>:
+
+
+
+void UltraStopReverse(int Flag_Current)
+{
+ 80298b8:	b480      	push	{r7}
+ 80298ba:	b083      	sub	sp, #12
+ 80298bc:	af00      	add	r7, sp, #0
+ 80298be:	6078      	str	r0, [r7, #4]
+	static int UltraStop_Flag_1;
+	static int Flag_Last;
+	static int Stop_Flag;
+	if(P_MK32->CH10_LD1<=100)
+ 80298c0:	4b29      	ldr	r3, [pc, #164]	@ (8029968 <UltraStopReverse+0xb0>)
+ 80298c2:	681b      	ldr	r3, [r3, #0]
+ 80298c4:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 80298c6:	2b64      	cmp	r3, #100	@ 0x64
+ 80298c8:	dc02      	bgt.n	80298d0 <UltraStopReverse+0x18>
+	{
+		UltraStop_Flag_1=3;
+ 80298ca:	4b28      	ldr	r3, [pc, #160]	@ (802996c <UltraStopReverse+0xb4>)
+ 80298cc:	2203      	movs	r2, #3
+ 80298ce:	601a      	str	r2, [r3, #0]
+	}
+	else
+	{
+//		UltraStop_Flag_1=0;
+	}
+	switch(UltraStop_Flag_1)
+ 80298d0:	4b26      	ldr	r3, [pc, #152]	@ (802996c <UltraStopReverse+0xb4>)
+ 80298d2:	681b      	ldr	r3, [r3, #0]
+ 80298d4:	2b03      	cmp	r3, #3
+ 80298d6:	d036      	beq.n	8029946 <UltraStopReverse+0x8e>
+ 80298d8:	2b03      	cmp	r3, #3
+ 80298da:	dc3b      	bgt.n	8029954 <UltraStopReverse+0x9c>
+ 80298dc:	2b00      	cmp	r3, #0
+ 80298de:	d002      	beq.n	80298e6 <UltraStopReverse+0x2e>
+ 80298e0:	2b01      	cmp	r3, #1
+ 80298e2:	d020      	beq.n	8029926 <UltraStopReverse+0x6e>
+ 80298e4:	e036      	b.n	8029954 <UltraStopReverse+0x9c>
+	{
+		case 0:
+			if((GV.Robot_To_Wall_mm.KS206_1_Measuring_Distance>=250)||(GV.Robot_To_Wall_mm.KS206_2_Measuring_Distance>=250))
+ 80298e6:	4b22      	ldr	r3, [pc, #136]	@ (8029970 <UltraStopReverse+0xb8>)
+ 80298e8:	f8d3 3294 	ldr.w	r3, [r3, #660]	@ 0x294
+ 80298ec:	2bf9      	cmp	r3, #249	@ 0xf9
+ 80298ee:	dc04      	bgt.n	80298fa <UltraStopReverse+0x42>
+ 80298f0:	4b1f      	ldr	r3, [pc, #124]	@ (8029970 <UltraStopReverse+0xb8>)
+ 80298f2:	f8d3 3298 	ldr.w	r3, [r3, #664]	@ 0x298
+ 80298f6:	2bf9      	cmp	r3, #249	@ 0xf9
+ 80298f8:	dd05      	ble.n	8029906 <UltraStopReverse+0x4e>
+			{
+				Stop_Flag++;
+ 80298fa:	4b1e      	ldr	r3, [pc, #120]	@ (8029974 <UltraStopReverse+0xbc>)
+ 80298fc:	681b      	ldr	r3, [r3, #0]
+ 80298fe:	3301      	adds	r3, #1
+ 8029900:	4a1c      	ldr	r2, [pc, #112]	@ (8029974 <UltraStopReverse+0xbc>)
+ 8029902:	6013      	str	r3, [r2, #0]
+ 8029904:	e002      	b.n	802990c <UltraStopReverse+0x54>
+			}
+			else
+			{
+				Stop_Flag=0;
+ 8029906:	4b1b      	ldr	r3, [pc, #108]	@ (8029974 <UltraStopReverse+0xbc>)
+ 8029908:	2200      	movs	r2, #0
+ 802990a:	601a      	str	r2, [r3, #0]
+			}
+			if(Stop_Flag>10)
+ 802990c:	4b19      	ldr	r3, [pc, #100]	@ (8029974 <UltraStopReverse+0xbc>)
+ 802990e:	681b      	ldr	r3, [r3, #0]
+ 8029910:	2b0a      	cmp	r3, #10
+ 8029912:	dd1c      	ble.n	802994e <UltraStopReverse+0x96>
+			{
+				Stop_Flag=0;
+ 8029914:	4b17      	ldr	r3, [pc, #92]	@ (8029974 <UltraStopReverse+0xbc>)
+ 8029916:	2200      	movs	r2, #0
+ 8029918:	601a      	str	r2, [r3, #0]
+				UltraStop_Flag_1++;
+ 802991a:	4b14      	ldr	r3, [pc, #80]	@ (802996c <UltraStopReverse+0xb4>)
+ 802991c:	681b      	ldr	r3, [r3, #0]
+ 802991e:	3301      	adds	r3, #1
+ 8029920:	4a12      	ldr	r2, [pc, #72]	@ (802996c <UltraStopReverse+0xb4>)
+ 8029922:	6013      	str	r3, [r2, #0]
+			}
+			break;
+ 8029924:	e013      	b.n	802994e <UltraStopReverse+0x96>
+		case 1:
+			GV.LeftMotor.Target_Velcity  =0;
+ 8029926:	4b12      	ldr	r3, [pc, #72]	@ (8029970 <UltraStopReverse+0xb8>)
+ 8029928:	2200      	movs	r2, #0
+ 802992a:	679a      	str	r2, [r3, #120]	@ 0x78
+			GV.RightMotor.Target_Velcity =0;
+ 802992c:	4b10      	ldr	r3, [pc, #64]	@ (8029970 <UltraStopReverse+0xb8>)
+ 802992e:	2200      	movs	r2, #0
+ 8029930:	f8c3 20f8 	str.w	r2, [r3, #248]	@ 0xf8
+			if(Flag_Last!=Flag_Current)
+ 8029934:	4b10      	ldr	r3, [pc, #64]	@ (8029978 <UltraStopReverse+0xc0>)
+ 8029936:	681b      	ldr	r3, [r3, #0]
+ 8029938:	687a      	ldr	r2, [r7, #4]
+ 802993a:	429a      	cmp	r2, r3
+ 802993c:	d009      	beq.n	8029952 <UltraStopReverse+0x9a>
+			{
+				UltraStop_Flag_1=0;
+ 802993e:	4b0b      	ldr	r3, [pc, #44]	@ (802996c <UltraStopReverse+0xb4>)
+ 8029940:	2200      	movs	r2, #0
+ 8029942:	601a      	str	r2, [r3, #0]
+			}
+			break;
+ 8029944:	e005      	b.n	8029952 <UltraStopReverse+0x9a>
+		case 3:
+			UltraStop_Flag_1=0;
+ 8029946:	4b09      	ldr	r3, [pc, #36]	@ (802996c <UltraStopReverse+0xb4>)
+ 8029948:	2200      	movs	r2, #0
+ 802994a:	601a      	str	r2, [r3, #0]
+			break;
+ 802994c:	e002      	b.n	8029954 <UltraStopReverse+0x9c>
+			break;
+ 802994e:	bf00      	nop
+ 8029950:	e000      	b.n	8029954 <UltraStopReverse+0x9c>
+			break;
+ 8029952:	bf00      	nop
+	}
+	Flag_Last=Flag_Current;
+ 8029954:	4a08      	ldr	r2, [pc, #32]	@ (8029978 <UltraStopReverse+0xc0>)
+ 8029956:	687b      	ldr	r3, [r7, #4]
+ 8029958:	6013      	str	r3, [r2, #0]
+}
+ 802995a:	bf00      	nop
+ 802995c:	370c      	adds	r7, #12
+ 802995e:	46bd      	mov	sp, r7
+ 8029960:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8029964:	4770      	bx	lr
+ 8029966:	bf00      	nop
+ 8029968:	2400a3f8 	.word	0x2400a3f8
+ 802996c:	2400a880 	.word	0x2400a880
+ 8029970:	24000340 	.word	0x24000340
+ 8029974:	2400a884 	.word	0x2400a884
+ 8029978:	2400a888 	.word	0x2400a888
+
+0802997c <UltraStopReverse_Manually_Backward>:
+
+void UltraStopReverse_Manually_Backward()
+{
+ 802997c:	b480      	push	{r7}
+ 802997e:	af00      	add	r7, sp, #0
+//			{
+//				UltraStop_Flag=0;
+//			}
+//			break;
+//	}
+}
+ 8029980:	bf00      	nop
+ 8029982:	46bd      	mov	sp, r7
+ 8029984:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8029988:	4770      	bx	lr
+	...
+
+0802998c <PushRod_Contronl>:
+
+void PushRod_Contronl()
+{
+ 802998c:	b580      	push	{r7, lr}
+ 802998e:	af00      	add	r7, sp, #0
+	if (P_MK32->CH1_RY_V >= 300)
+ 8029990:	4b0f      	ldr	r3, [pc, #60]	@ (80299d0 <PushRod_Contronl+0x44>)
+ 8029992:	681b      	ldr	r3, [r3, #0]
+ 8029994:	689b      	ldr	r3, [r3, #8]
+ 8029996:	f5b3 7f96 	cmp.w	r3, #300	@ 0x12c
+ 802999a:	db03      	blt.n	80299a4 <PushRod_Contronl+0x18>
+	{
+		Current_PushRod_STATE = PushRod_UP;
+ 802999c:	4b0d      	ldr	r3, [pc, #52]	@ (80299d4 <PushRod_Contronl+0x48>)
+ 802999e:	2201      	movs	r2, #1
+ 80299a0:	701a      	strb	r2, [r3, #0]
+ 80299a2:	e00c      	b.n	80299be <PushRod_Contronl+0x32>
+	}
+	else if (P_MK32->CH1_RY_V <= -300)
+ 80299a4:	4b0a      	ldr	r3, [pc, #40]	@ (80299d0 <PushRod_Contronl+0x44>)
+ 80299a6:	681b      	ldr	r3, [r3, #0]
+ 80299a8:	689b      	ldr	r3, [r3, #8]
+ 80299aa:	f513 7f96 	cmn.w	r3, #300	@ 0x12c
+ 80299ae:	dc03      	bgt.n	80299b8 <PushRod_Contronl+0x2c>
+	{
+		Current_PushRod_STATE = PushRod_Down;
+ 80299b0:	4b08      	ldr	r3, [pc, #32]	@ (80299d4 <PushRod_Contronl+0x48>)
+ 80299b2:	2202      	movs	r2, #2
+ 80299b4:	701a      	strb	r2, [r3, #0]
+ 80299b6:	e002      	b.n	80299be <PushRod_Contronl+0x32>
+	}
+	else
+	{
+		Current_PushRod_STATE = PushRod_HALT;
+ 80299b8:	4b06      	ldr	r3, [pc, #24]	@ (80299d4 <PushRod_Contronl+0x48>)
+ 80299ba:	2200      	movs	r2, #0
+ 80299bc:	701a      	strb	r2, [r3, #0]
+	}
+	action_perfrom(Set_PushRod_States,
+ 80299be:	4b05      	ldr	r3, [pc, #20]	@ (80299d4 <PushRod_Contronl+0x48>)
+ 80299c0:	781b      	ldrb	r3, [r3, #0]
+ 80299c2:	461a      	mov	r2, r3
+ 80299c4:	2103      	movs	r1, #3
+ 80299c6:	4804      	ldr	r0, [pc, #16]	@ (80299d8 <PushRod_Contronl+0x4c>)
+ 80299c8:	f7ff ff24 	bl	8029814 <action_perfrom>
+	        sizeof(Set_PushRod_States) / sizeof(transition_t), Current_PushRod_STATE);
+}
+ 80299cc:	bf00      	nop
+ 80299ce:	bd80      	pop	{r7, pc}
+ 80299d0:	2400a3f8 	.word	0x2400a3f8
+ 80299d4:	2400a700 	.word	0x2400a700
+ 80299d8:	240000e0 	.word	0x240000e0
+ 80299dc:	00000000 	.word	0x00000000
+
+080299e0 <Robot_Manual_Operation_Function>:
+
+
+
+
+void Robot_Manual_Operation_Function()
+{
+ 80299e0:	b580      	push	{r7, lr}
+ 80299e2:	b08a      	sub	sp, #40	@ 0x28
+ 80299e4:	af00      	add	r7, sp, #0
+    double y_value = P_MK32->CH2_LY_V; // 假设 Y 是纵向（前后）
+ 80299e6:	4b8a      	ldr	r3, [pc, #552]	@ (8029c10 <Robot_Manual_Operation_Function+0x230>)
+ 80299e8:	681b      	ldr	r3, [r3, #0]
+ 80299ea:	68db      	ldr	r3, [r3, #12]
+ 80299ec:	ee07 3a90 	vmov	s15, r3
+ 80299f0:	eeb8 7be7 	vcvt.f64.s32	d7, s15
+ 80299f4:	ed87 7b08 	vstr	d7, [r7, #32]
+    double x_value = P_MK32->CH3_LY_H; // 假设 X 是横向（左右）
+ 80299f8:	4b85      	ldr	r3, [pc, #532]	@ (8029c10 <Robot_Manual_Operation_Function+0x230>)
+ 80299fa:	681b      	ldr	r3, [r3, #0]
+ 80299fc:	691b      	ldr	r3, [r3, #16]
+ 80299fe:	ee07 3a90 	vmov	s15, r3
+ 8029a02:	eeb8 7be7 	vcvt.f64.s32	d7, s15
+ 8029a06:	ed87 7b06 	vstr	d7, [r7, #24]
+	double w_value = P_MK32->CH0_RY_H; // 假设 X 是横向（左右）
+ 8029a0a:	4b81      	ldr	r3, [pc, #516]	@ (8029c10 <Robot_Manual_Operation_Function+0x230>)
+ 8029a0c:	681b      	ldr	r3, [r3, #0]
+ 8029a0e:	685b      	ldr	r3, [r3, #4]
+ 8029a10:	ee07 3a90 	vmov	s15, r3
+ 8029a14:	eeb8 7be7 	vcvt.f64.s32	d7, s15
+ 8029a18:	ed87 7b04 	vstr	d7, [r7, #16]
+	double z_value = P_MK32->CH1_RY_V; // 假设 X 是横向（左右）
+ 8029a1c:	4b7c      	ldr	r3, [pc, #496]	@ (8029c10 <Robot_Manual_Operation_Function+0x230>)
+ 8029a1e:	681b      	ldr	r3, [r3, #0]
+ 8029a20:	689b      	ldr	r3, [r3, #8]
+ 8029a22:	ee07 3a90 	vmov	s15, r3
+ 8029a26:	eeb8 7be7 	vcvt.f64.s32	d7, s15
+ 8029a2a:	ed87 7b02 	vstr	d7, [r7, #8]
+    static int Horizontal_Manual_Flag ; // 静态局部变量
+    if((fabs(y_value)>=300)||(fabs(x_value)>=300)||(fabs(w_value)>=300)||(fabs(z_value)>=300))
+ 8029a2e:	ed97 7b08 	vldr	d7, [r7, #32]
+ 8029a32:	eeb0 7bc7 	vabs.f64	d7, d7
+ 8029a36:	ed9f 6b66 	vldr	d6, [pc, #408]	@ 8029bd0 <Robot_Manual_Operation_Function+0x1f0>
+ 8029a3a:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 8029a3e:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 8029a42:	da21      	bge.n	8029a88 <Robot_Manual_Operation_Function+0xa8>
+ 8029a44:	ed97 7b06 	vldr	d7, [r7, #24]
+ 8029a48:	eeb0 7bc7 	vabs.f64	d7, d7
+ 8029a4c:	ed9f 6b60 	vldr	d6, [pc, #384]	@ 8029bd0 <Robot_Manual_Operation_Function+0x1f0>
+ 8029a50:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 8029a54:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 8029a58:	da16      	bge.n	8029a88 <Robot_Manual_Operation_Function+0xa8>
+ 8029a5a:	ed97 7b04 	vldr	d7, [r7, #16]
+ 8029a5e:	eeb0 7bc7 	vabs.f64	d7, d7
+ 8029a62:	ed9f 6b5b 	vldr	d6, [pc, #364]	@ 8029bd0 <Robot_Manual_Operation_Function+0x1f0>
+ 8029a66:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 8029a6a:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 8029a6e:	da0b      	bge.n	8029a88 <Robot_Manual_Operation_Function+0xa8>
+ 8029a70:	ed97 7b02 	vldr	d7, [r7, #8]
+ 8029a74:	eeb0 7bc7 	vabs.f64	d7, d7
+ 8029a78:	ed9f 6b55 	vldr	d6, [pc, #340]	@ 8029bd0 <Robot_Manual_Operation_Function+0x1f0>
+ 8029a7c:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 8029a80:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 8029a84:	f2c0 8094 	blt.w	8029bb0 <Robot_Manual_Operation_Function+0x1d0>
+     {
+     	switch(Horizontal_Manual_Flag)
+ 8029a88:	4b62      	ldr	r3, [pc, #392]	@ (8029c14 <Robot_Manual_Operation_Function+0x234>)
+ 8029a8a:	681b      	ldr	r3, [r3, #0]
+ 8029a8c:	2b00      	cmp	r3, #0
+ 8029a8e:	d002      	beq.n	8029a96 <Robot_Manual_Operation_Function+0xb6>
+ 8029a90:	2b01      	cmp	r3, #1
+ 8029a92:	d006      	beq.n	8029aa2 <Robot_Manual_Operation_Function+0xc2>
+ 8029a94:	e095      	b.n	8029bc2 <Robot_Manual_Operation_Function+0x1e2>
+     	{
+     		case 0:
+     			Horizontal_Manual_Flag++;
+ 8029a96:	4b5f      	ldr	r3, [pc, #380]	@ (8029c14 <Robot_Manual_Operation_Function+0x234>)
+ 8029a98:	681b      	ldr	r3, [r3, #0]
+ 8029a9a:	3301      	adds	r3, #1
+ 8029a9c:	4a5d      	ldr	r2, [pc, #372]	@ (8029c14 <Robot_Manual_Operation_Function+0x234>)
+ 8029a9e:	6013      	str	r3, [r2, #0]
+     			break;
+ 8029aa0:	e085      	b.n	8029bae <Robot_Manual_Operation_Function+0x1ce>
+     		case 1:
+				if((fabs(y_value)>=300)||(fabs(x_value)>=300))
+ 8029aa2:	ed97 7b08 	vldr	d7, [r7, #32]
+ 8029aa6:	eeb0 7bc7 	vabs.f64	d7, d7
+ 8029aaa:	ed9f 6b49 	vldr	d6, [pc, #292]	@ 8029bd0 <Robot_Manual_Operation_Function+0x1f0>
+ 8029aae:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 8029ab2:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 8029ab6:	da0a      	bge.n	8029ace <Robot_Manual_Operation_Function+0xee>
+ 8029ab8:	ed97 7b06 	vldr	d7, [r7, #24]
+ 8029abc:	eeb0 7bc7 	vabs.f64	d7, d7
+ 8029ac0:	ed9f 6b43 	vldr	d6, [pc, #268]	@ 8029bd0 <Robot_Manual_Operation_Function+0x1f0>
+ 8029ac4:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 8029ac8:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 8029acc:	db6a      	blt.n	8029ba4 <Robot_Manual_Operation_Function+0x1c4>
+				{
+					double Rock_Angle= atan2(y_value, x_value);
+ 8029ace:	ed97 1b06 	vldr	d1, [r7, #24]
+ 8029ad2:	ed97 0b08 	vldr	d0, [r7, #32]
+ 8029ad6:	f016 ffff 	bl	8040ad8 <atan2>
+ 8029ada:	ed87 0b00 	vstr	d0, [r7]
+					Rock_Angle=Rock_Angle/3.1415926*180;
+ 8029ade:	ed97 6b00 	vldr	d6, [r7]
+ 8029ae2:	ed9f 5b3d 	vldr	d5, [pc, #244]	@ 8029bd8 <Robot_Manual_Operation_Function+0x1f8>
+ 8029ae6:	ee86 7b05 	vdiv.f64	d7, d6, d5
+ 8029aea:	ed9f 6b3d 	vldr	d6, [pc, #244]	@ 8029be0 <Robot_Manual_Operation_Function+0x200>
+ 8029aee:	ee27 7b06 	vmul.f64	d7, d7, d6
+ 8029af2:	ed87 7b00 	vstr	d7, [r7]
+					if((Rock_Angle>=-20)&&(Rock_Angle<=20))
+ 8029af6:	ed97 7b00 	vldr	d7, [r7]
+ 8029afa:	eebb 6b04 	vmov.f64	d6, #180	@ 0xc1a00000 -20.0
+ 8029afe:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 8029b02:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 8029b06:	db0e      	blt.n	8029b26 <Robot_Manual_Operation_Function+0x146>
+ 8029b08:	ed97 7b00 	vldr	d7, [r7]
+ 8029b0c:	eeb3 6b04 	vmov.f64	d6, #52	@ 0x41a00000  20.0
+ 8029b10:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 8029b14:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 8029b18:	d805      	bhi.n	8029b26 <Robot_Manual_Operation_Function+0x146>
+					{
+						TurnRight_State_Do();
+ 8029b1a:	f003 fbc1 	bl	802d2a0 <TurnRight_State_Do>
+						Forward_Flag_Robot_Manual=1;
+ 8029b1e:	4b3e      	ldr	r3, [pc, #248]	@ (8029c18 <Robot_Manual_Operation_Function+0x238>)
+ 8029b20:	2201      	movs	r2, #1
+ 8029b22:	601a      	str	r2, [r3, #0]
+ 8029b24:	e03d      	b.n	8029ba2 <Robot_Manual_Operation_Function+0x1c2>
+					}
+					else if((Rock_Angle>=70)&&(Rock_Angle<=110))
+ 8029b26:	ed97 7b00 	vldr	d7, [r7]
+ 8029b2a:	ed9f 6b2f 	vldr	d6, [pc, #188]	@ 8029be8 <Robot_Manual_Operation_Function+0x208>
+ 8029b2e:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 8029b32:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 8029b36:	db0b      	blt.n	8029b50 <Robot_Manual_Operation_Function+0x170>
+ 8029b38:	ed97 7b00 	vldr	d7, [r7]
+ 8029b3c:	ed9f 6b2c 	vldr	d6, [pc, #176]	@ 8029bf0 <Robot_Manual_Operation_Function+0x210>
+ 8029b40:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 8029b44:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 8029b48:	d802      	bhi.n	8029b50 <Robot_Manual_Operation_Function+0x170>
+					{
+						Forwards_State_Do();
+ 8029b4a:	f003 fb3f 	bl	802d1cc <Forwards_State_Do>
+ 8029b4e:	e028      	b.n	8029ba2 <Robot_Manual_Operation_Function+0x1c2>
+					}
+					else if((Rock_Angle>=-110)&&(Rock_Angle<=-70))
+ 8029b50:	ed97 7b00 	vldr	d7, [r7]
+ 8029b54:	ed9f 6b28 	vldr	d6, [pc, #160]	@ 8029bf8 <Robot_Manual_Operation_Function+0x218>
+ 8029b58:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 8029b5c:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 8029b60:	db0b      	blt.n	8029b7a <Robot_Manual_Operation_Function+0x19a>
+ 8029b62:	ed97 7b00 	vldr	d7, [r7]
+ 8029b66:	ed9f 6b26 	vldr	d6, [pc, #152]	@ 8029c00 <Robot_Manual_Operation_Function+0x220>
+ 8029b6a:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 8029b6e:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 8029b72:	d802      	bhi.n	8029b7a <Robot_Manual_Operation_Function+0x19a>
+					{
+						Backwards_State_Do();
+ 8029b74:	f003 fb4a 	bl	802d20c <Backwards_State_Do>
+ 8029b78:	e013      	b.n	8029ba2 <Robot_Manual_Operation_Function+0x1c2>
+					}
+					else if(fabs(Rock_Angle)>=160)
+ 8029b7a:	ed97 7b00 	vldr	d7, [r7]
+ 8029b7e:	eeb0 7bc7 	vabs.f64	d7, d7
+ 8029b82:	ed9f 6b21 	vldr	d6, [pc, #132]	@ 8029c08 <Robot_Manual_Operation_Function+0x228>
+ 8029b86:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 8029b8a:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 8029b8e:	db05      	blt.n	8029b9c <Robot_Manual_Operation_Function+0x1bc>
+					{
+						TurnLeft_State_Do();
+ 8029b90:	f003 fb5c 	bl	802d24c <TurnLeft_State_Do>
+						Forward_Flag_Robot_Manual=1;
+ 8029b94:	4b20      	ldr	r3, [pc, #128]	@ (8029c18 <Robot_Manual_Operation_Function+0x238>)
+ 8029b96:	2201      	movs	r2, #1
+ 8029b98:	601a      	str	r2, [r3, #0]
+				{
+ 8029b9a:	e005      	b.n	8029ba8 <Robot_Manual_Operation_Function+0x1c8>
+					}
+					else
+					{
+						HALT_State_Do();
+ 8029b9c:	f006 fae4 	bl	8030168 <HALT_State_Do>
+				{
+ 8029ba0:	e002      	b.n	8029ba8 <Robot_Manual_Operation_Function+0x1c8>
+ 8029ba2:	e001      	b.n	8029ba8 <Robot_Manual_Operation_Function+0x1c8>
+					}
+				}
+				else
+				{
+					HALT_State_Do();
+ 8029ba4:	f006 fae0 	bl	8030168 <HALT_State_Do>
+				}
+     	    	Robot_Swing_Operation_Function();//摆臂运动函数
+ 8029ba8:	f000 f838 	bl	8029c1c <Robot_Swing_Operation_Function>
+     			break;
+ 8029bac:	bf00      	nop
+     	switch(Horizontal_Manual_Flag)
+ 8029bae:	e008      	b.n	8029bc2 <Robot_Manual_Operation_Function+0x1e2>
+     	}
+     }
+ 	else
+ 	{
+ 		Horizontal_Manual_Flag=0;
+ 8029bb0:	4b18      	ldr	r3, [pc, #96]	@ (8029c14 <Robot_Manual_Operation_Function+0x234>)
+ 8029bb2:	2200      	movs	r2, #0
+ 8029bb4:	601a      	str	r2, [r3, #0]
+ 		HALT_State_Do();
+ 8029bb6:	f006 fad7 	bl	8030168 <HALT_State_Do>
+ 		//Move_Swing_Halt_F
+ 		//unc_Do();
+ 		Forward_Flag_Robot_Manual=1;
+ 8029bba:	4b17      	ldr	r3, [pc, #92]	@ (8029c18 <Robot_Manual_Operation_Function+0x238>)
+ 8029bbc:	2201      	movs	r2, #1
+ 8029bbe:	601a      	str	r2, [r3, #0]
+ 	}
+}
+ 8029bc0:	bf00      	nop
+ 8029bc2:	bf00      	nop
+ 8029bc4:	3728      	adds	r7, #40	@ 0x28
+ 8029bc6:	46bd      	mov	sp, r7
+ 8029bc8:	bd80      	pop	{r7, pc}
+ 8029bca:	bf00      	nop
+ 8029bcc:	f3af 8000 	nop.w
+ 8029bd0:	00000000 	.word	0x00000000
+ 8029bd4:	4072c000 	.word	0x4072c000
+ 8029bd8:	4d12d84a 	.word	0x4d12d84a
+ 8029bdc:	400921fb 	.word	0x400921fb
+ 8029be0:	00000000 	.word	0x00000000
+ 8029be4:	40668000 	.word	0x40668000
+ 8029be8:	00000000 	.word	0x00000000
+ 8029bec:	40518000 	.word	0x40518000
+ 8029bf0:	00000000 	.word	0x00000000
+ 8029bf4:	405b8000 	.word	0x405b8000
+ 8029bf8:	00000000 	.word	0x00000000
+ 8029bfc:	c05b8000 	.word	0xc05b8000
+ 8029c00:	00000000 	.word	0x00000000
+ 8029c04:	c0518000 	.word	0xc0518000
+ 8029c08:	00000000 	.word	0x00000000
+ 8029c0c:	40640000 	.word	0x40640000
+ 8029c10:	2400a3f8 	.word	0x2400a3f8
+ 8029c14:	2400a88c 	.word	0x2400a88c
+ 8029c18:	24000098 	.word	0x24000098
+
+08029c1c <Robot_Swing_Operation_Function>:
+
+void Robot_Swing_Operation_Function()
+{
+ 8029c1c:	b580      	push	{r7, lr}
+ 8029c1e:	af00      	add	r7, sp, #0
+	if(P_MK32->CH0_RY_H>300)
+ 8029c20:	4b0a      	ldr	r3, [pc, #40]	@ (8029c4c <Robot_Swing_Operation_Function+0x30>)
+ 8029c22:	681b      	ldr	r3, [r3, #0]
+ 8029c24:	685b      	ldr	r3, [r3, #4]
+ 8029c26:	f5b3 7f96 	cmp.w	r3, #300	@ 0x12c
+ 8029c2a:	dd02      	ble.n	8029c32 <Robot_Swing_Operation_Function+0x16>
+	{
+		Move_Swing_Right_Func_Do();
+ 8029c2c:	f003 fbd8 	bl	802d3e0 <Move_Swing_Right_Func_Do>
+	{
+		Move_Swing_Halt_Func_Do();
+	}
+/*	*Swing_Speed = CV.PV.Swing_Speed;*/
+//	action_perfrom(Set_Swing_States,sizeof(Set_Swing_States) / sizeof(transition_t), CurrentSwingState);
+}
+ 8029c30:	e00a      	b.n	8029c48 <Robot_Swing_Operation_Function+0x2c>
+	else if(P_MK32->CH0_RY_H<-300)
+ 8029c32:	4b06      	ldr	r3, [pc, #24]	@ (8029c4c <Robot_Swing_Operation_Function+0x30>)
+ 8029c34:	681b      	ldr	r3, [r3, #0]
+ 8029c36:	685b      	ldr	r3, [r3, #4]
+ 8029c38:	f513 7f96 	cmn.w	r3, #300	@ 0x12c
+ 8029c3c:	da02      	bge.n	8029c44 <Robot_Swing_Operation_Function+0x28>
+		Move_Swing_Left_Func_Do();
+ 8029c3e:	f003 fba5 	bl	802d38c <Move_Swing_Left_Func_Do>
+}
+ 8029c42:	e001      	b.n	8029c48 <Robot_Swing_Operation_Function+0x2c>
+		Move_Swing_Halt_Func_Do();
+ 8029c44:	f003 fbf6 	bl	802d434 <Move_Swing_Halt_Func_Do>
+}
+ 8029c48:	bf00      	nop
+ 8029c4a:	bd80      	pop	{r7, pc}
+ 8029c4c:	2400a3f8 	.word	0x2400a3f8
+
+08029c50 <Horizontal_Operatin_Main_Func>:
+
+int Forward_Flag_Robot_Manual_Count=0; // 静态局部变量
+int Forward_Flag_Robot_Auto=0;
+
+void Horizontal_Operatin_Main_Func()
+{
+ 8029c50:	b580      	push	{r7, lr}
+ 8029c52:	af00      	add	r7, sp, #0
+	Blast_Machine_Control_Fun();
+ 8029c54:	f7fc fbaa 	bl	80263ac <Blast_Machine_Control_Fun>
+	if(P_MK32->CH7_SD==-1000)//自动行驶
+ 8029c58:	4b2d      	ldr	r3, [pc, #180]	@ (8029d10 <Horizontal_Operatin_Main_Func+0xc0>)
+ 8029c5a:	681b      	ldr	r3, [r3, #0]
+ 8029c5c:	6a1b      	ldr	r3, [r3, #32]
+ 8029c5e:	f513 7f7a 	cmn.w	r3, #1000	@ 0x3e8
+ 8029c62:	d110      	bne.n	8029c86 <Horizontal_Operatin_Main_Func+0x36>
+	{
+		Move_Horizontal_Auto_Sub_Func();//自动后退  Forward_Flag_Robot_Auto
+ 8029c64:	f000 f85c 	bl	8029d20 <Move_Horizontal_Auto_Sub_Func>
+		UltraStopReverse(Forward_Flag_Robot_Auto);
+ 8029c68:	4b2a      	ldr	r3, [pc, #168]	@ (8029d14 <Horizontal_Operatin_Main_Func+0xc4>)
+ 8029c6a:	681b      	ldr	r3, [r3, #0]
+ 8029c6c:	4618      	mov	r0, r3
+ 8029c6e:	f7ff fe23 	bl	80298b8 <UltraStopReverse>
+		Change_Road_Jude_Flag=0;
+ 8029c72:	4b29      	ldr	r3, [pc, #164]	@ (8029d18 <Horizontal_Operatin_Main_Func+0xc8>)
+ 8029c74:	2200      	movs	r2, #0
+ 8029c76:	601a      	str	r2, [r3, #0]
+		Forward_Flag_Robot_Manual=1;
+ 8029c78:	4b28      	ldr	r3, [pc, #160]	@ (8029d1c <Horizontal_Operatin_Main_Func+0xcc>)
+ 8029c7a:	2201      	movs	r2, #1
+ 8029c7c:	601a      	str	r2, [r3, #0]
+		Pressure_Adaptive_Function_Uptata(200);
+ 8029c7e:	20c8      	movs	r0, #200	@ 0xc8
+ 8029c80:	f005 fa04 	bl	802f08c <Pressure_Adaptive_Function_Uptata>
+		Robot_Main_Mode_Jude();
+		Swing_Mode_Determination();//摆臂方式确定
+		PushRod_Contronl();
+		UltraStopReverse_Manually_Backward();
+	}
+}
+ 8029c84:	e041      	b.n	8029d0a <Horizontal_Operatin_Main_Func+0xba>
+	else if(P_MK32->CH4_SA==-1000)//换道
+ 8029c86:	4b22      	ldr	r3, [pc, #136]	@ (8029d10 <Horizontal_Operatin_Main_Func+0xc0>)
+ 8029c88:	681b      	ldr	r3, [r3, #0]
+ 8029c8a:	695b      	ldr	r3, [r3, #20]
+ 8029c8c:	f513 7f7a 	cmn.w	r3, #1000	@ 0x3e8
+ 8029c90:	d108      	bne.n	8029ca4 <Horizontal_Operatin_Main_Func+0x54>
+		Change_Road_Down_Left_Right();
+ 8029c92:	f000 f8b1 	bl	8029df8 <Change_Road_Down_Left_Right>
+		Forward_Flag_Robot_Auto=1;
+ 8029c96:	4b1f      	ldr	r3, [pc, #124]	@ (8029d14 <Horizontal_Operatin_Main_Func+0xc4>)
+ 8029c98:	2201      	movs	r2, #1
+ 8029c9a:	601a      	str	r2, [r3, #0]
+		Forward_Flag_Robot_Manual=1;
+ 8029c9c:	4b1f      	ldr	r3, [pc, #124]	@ (8029d1c <Horizontal_Operatin_Main_Func+0xcc>)
+ 8029c9e:	2201      	movs	r2, #1
+ 8029ca0:	601a      	str	r2, [r3, #0]
+}
+ 8029ca2:	e032      	b.n	8029d0a <Horizontal_Operatin_Main_Func+0xba>
+	else if(P_MK32->CH5_SB==-1000)//前进自动巡航
+ 8029ca4:	4b1a      	ldr	r3, [pc, #104]	@ (8029d10 <Horizontal_Operatin_Main_Func+0xc0>)
+ 8029ca6:	681b      	ldr	r3, [r3, #0]
+ 8029ca8:	699b      	ldr	r3, [r3, #24]
+ 8029caa:	f513 7f7a 	cmn.w	r3, #1000	@ 0x3e8
+ 8029cae:	d108      	bne.n	8029cc2 <Horizontal_Operatin_Main_Func+0x72>
+		Move_Horizontal_Manual_Sub_Func_Forwards();
+ 8029cb0:	f001 fc36 	bl	802b520 <Move_Horizontal_Manual_Sub_Func_Forwards>
+		Forward_Flag_Robot_Auto=1;
+ 8029cb4:	4b17      	ldr	r3, [pc, #92]	@ (8029d14 <Horizontal_Operatin_Main_Func+0xc4>)
+ 8029cb6:	2201      	movs	r2, #1
+ 8029cb8:	601a      	str	r2, [r3, #0]
+		Change_Road_Jude_Flag=0;
+ 8029cba:	4b17      	ldr	r3, [pc, #92]	@ (8029d18 <Horizontal_Operatin_Main_Func+0xc8>)
+ 8029cbc:	2200      	movs	r2, #0
+ 8029cbe:	601a      	str	r2, [r3, #0]
+}
+ 8029cc0:	e023      	b.n	8029d0a <Horizontal_Operatin_Main_Func+0xba>
+	else if(P_MK32->CH5_SB==1000)//后退自动巡航
+ 8029cc2:	4b13      	ldr	r3, [pc, #76]	@ (8029d10 <Horizontal_Operatin_Main_Func+0xc0>)
+ 8029cc4:	681b      	ldr	r3, [r3, #0]
+ 8029cc6:	699b      	ldr	r3, [r3, #24]
+ 8029cc8:	f5b3 7f7a 	cmp.w	r3, #1000	@ 0x3e8
+ 8029ccc:	d10d      	bne.n	8029cea <Horizontal_Operatin_Main_Func+0x9a>
+		Move_Horizontal_Manual_Sub_Func_Backwards();
+ 8029cce:	f001 fc71 	bl	802b5b4 <Move_Horizontal_Manual_Sub_Func_Backwards>
+		Forward_Flag_Robot_Auto=1;
+ 8029cd2:	4b10      	ldr	r3, [pc, #64]	@ (8029d14 <Horizontal_Operatin_Main_Func+0xc4>)
+ 8029cd4:	2201      	movs	r2, #1
+ 8029cd6:	601a      	str	r2, [r3, #0]
+		Change_Road_Jude_Flag=0;
+ 8029cd8:	4b0f      	ldr	r3, [pc, #60]	@ (8029d18 <Horizontal_Operatin_Main_Func+0xc8>)
+ 8029cda:	2200      	movs	r2, #0
+ 8029cdc:	601a      	str	r2, [r3, #0]
+		UltraStopReverse(Forward_Flag_Robot_Manual);
+ 8029cde:	4b0f      	ldr	r3, [pc, #60]	@ (8029d1c <Horizontal_Operatin_Main_Func+0xcc>)
+ 8029ce0:	681b      	ldr	r3, [r3, #0]
+ 8029ce2:	4618      	mov	r0, r3
+ 8029ce4:	f7ff fde8 	bl	80298b8 <UltraStopReverse>
+}
+ 8029ce8:	e00f      	b.n	8029d0a <Horizontal_Operatin_Main_Func+0xba>
+		Horizontal_Manual_Operation_Func(); //Forward_Flag_Robot_Manual       Move_Horizontal_Manual_Sub_Func();
+ 8029cea:	f000 f8c9 	bl	8029e80 <Horizontal_Manual_Operation_Func>
+		Forward_Flag_Robot_Auto=1;
+ 8029cee:	4b09      	ldr	r3, [pc, #36]	@ (8029d14 <Horizontal_Operatin_Main_Func+0xc4>)
+ 8029cf0:	2201      	movs	r2, #1
+ 8029cf2:	601a      	str	r2, [r3, #0]
+		Change_Road_Jude_Flag=0;
+ 8029cf4:	4b08      	ldr	r3, [pc, #32]	@ (8029d18 <Horizontal_Operatin_Main_Func+0xc8>)
+ 8029cf6:	2200      	movs	r2, #0
+ 8029cf8:	601a      	str	r2, [r3, #0]
+		Robot_Main_Mode_Jude();
+ 8029cfa:	f004 fbc9 	bl	802e490 <Robot_Main_Mode_Jude>
+		Swing_Mode_Determination();//摆臂方式确定
+ 8029cfe:	f005 f8f7 	bl	802eef0 <Swing_Mode_Determination>
+		PushRod_Contronl();
+ 8029d02:	f7ff fe43 	bl	802998c <PushRod_Contronl>
+		UltraStopReverse_Manually_Backward();
+ 8029d06:	f7ff fe39 	bl	802997c <UltraStopReverse_Manually_Backward>
+}
+ 8029d0a:	bf00      	nop
+ 8029d0c:	bd80      	pop	{r7, pc}
+ 8029d0e:	bf00      	nop
+ 8029d10:	2400a3f8 	.word	0x2400a3f8
+ 8029d14:	2400a798 	.word	0x2400a798
+ 8029d18:	2400a6f0 	.word	0x2400a6f0
+ 8029d1c:	24000098 	.word	0x24000098
+
+08029d20 <Move_Horizontal_Auto_Sub_Func>:
+
+
+void Move_Horizontal_Auto_Sub_Func()
+{
+ 8029d20:	b580      	push	{r7, lr}
+ 8029d22:	af00      	add	r7, sp, #0
+	  switch (Forward_Flag_Robot_Auto)
+ 8029d24:	4b2e      	ldr	r3, [pc, #184]	@ (8029de0 <Move_Horizontal_Auto_Sub_Func+0xc0>)
+ 8029d26:	681b      	ldr	r3, [r3, #0]
+ 8029d28:	3b01      	subs	r3, #1
+ 8029d2a:	2b05      	cmp	r3, #5
+ 8029d2c:	d852      	bhi.n	8029dd4 <Move_Horizontal_Auto_Sub_Func+0xb4>
+ 8029d2e:	a201      	add	r2, pc, #4	@ (adr r2, 8029d34 <Move_Horizontal_Auto_Sub_Func+0x14>)
+ 8029d30:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 8029d34:	08029d4d 	.word	0x08029d4d
+ 8029d38:	08029d5d 	.word	0x08029d5d
+ 8029d3c:	08029d8f 	.word	0x08029d8f
+ 8029d40:	08029d9b 	.word	0x08029d9b
+ 8029d44:	08029dc1 	.word	0x08029dc1
+ 8029d48:	08029dcb 	.word	0x08029dcb
+	  {
+		  case Forward_Attitude_Judge:
+			  Horiz_Angle_Judge();
+ 8029d4c:	f001 fc7c 	bl	802b648 <Horiz_Angle_Judge>
+			  Forward_Flag_Robot_Auto++;
+ 8029d50:	4b23      	ldr	r3, [pc, #140]	@ (8029de0 <Move_Horizontal_Auto_Sub_Func+0xc0>)
+ 8029d52:	681b      	ldr	r3, [r3, #0]
+ 8029d54:	3301      	adds	r3, #1
+ 8029d56:	4a22      	ldr	r2, [pc, #136]	@ (8029de0 <Move_Horizontal_Auto_Sub_Func+0xc0>)
+ 8029d58:	6013      	str	r3, [r2, #0]
+			  break;
+ 8029d5a:	e03e      	b.n	8029dda <Move_Horizontal_Auto_Sub_Func+0xba>
+		  case Forward_Attitude_Adjust:
+			  Robot_Posture_Adjus_Gravity();
+ 8029d5c:	f002 f868 	bl	802be30 <Robot_Posture_Adjus_Gravity>
+			  if(Angle_Error_LLL<Error_Cont_Thresh)
+ 8029d60:	4b20      	ldr	r3, [pc, #128]	@ (8029de4 <Move_Horizontal_Auto_Sub_Func+0xc4>)
+ 8029d62:	ed93 6b00 	vldr	d6, [r3]
+ 8029d66:	4b20      	ldr	r3, [pc, #128]	@ (8029de8 <Move_Horizontal_Auto_Sub_Func+0xc8>)
+ 8029d68:	ed93 7b00 	vldr	d7, [r3]
+ 8029d6c:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 8029d70:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 8029d74:	d504      	bpl.n	8029d80 <Move_Horizontal_Auto_Sub_Func+0x60>
+			  {
+				Forward_Flag_Robot_Auto++;
+ 8029d76:	4b1a      	ldr	r3, [pc, #104]	@ (8029de0 <Move_Horizontal_Auto_Sub_Func+0xc0>)
+ 8029d78:	681b      	ldr	r3, [r3, #0]
+ 8029d7a:	3301      	adds	r3, #1
+ 8029d7c:	4a18      	ldr	r2, [pc, #96]	@ (8029de0 <Move_Horizontal_Auto_Sub_Func+0xc0>)
+ 8029d7e:	6013      	str	r3, [r2, #0]
+			  }
+			  Robot_Platform_Back_Flag=0;
+ 8029d80:	4b1a      	ldr	r3, [pc, #104]	@ (8029dec <Move_Horizontal_Auto_Sub_Func+0xcc>)
+ 8029d82:	2200      	movs	r2, #0
+ 8029d84:	601a      	str	r2, [r3, #0]
+			  Swing_Limit_Flag=0;
+ 8029d86:	4b1a      	ldr	r3, [pc, #104]	@ (8029df0 <Move_Horizontal_Auto_Sub_Func+0xd0>)
+ 8029d88:	2200      	movs	r2, #0
+ 8029d8a:	601a      	str	r2, [r3, #0]
+			  break;
+ 8029d8c:	e025      	b.n	8029dda <Move_Horizontal_Auto_Sub_Func+0xba>
+		  case Forward_Motion:
+			  Forward_Flag_Robot_Auto++;
+ 8029d8e:	4b14      	ldr	r3, [pc, #80]	@ (8029de0 <Move_Horizontal_Auto_Sub_Func+0xc0>)
+ 8029d90:	681b      	ldr	r3, [r3, #0]
+ 8029d92:	3301      	adds	r3, #1
+ 8029d94:	4a12      	ldr	r2, [pc, #72]	@ (8029de0 <Move_Horizontal_Auto_Sub_Func+0xc0>)
+ 8029d96:	6013      	str	r3, [r2, #0]
+			  break;
+ 8029d98:	e01f      	b.n	8029dda <Move_Horizontal_Auto_Sub_Func+0xba>
+		  case Work_Way:
+			  if(GV_Robot_backMode==1)
+ 8029d9a:	4b16      	ldr	r3, [pc, #88]	@ (8029df4 <Move_Horizontal_Auto_Sub_Func+0xd4>)
+ 8029d9c:	681b      	ldr	r3, [r3, #0]
+ 8029d9e:	2b01      	cmp	r3, #1
+ 8029da0:	d103      	bne.n	8029daa <Move_Horizontal_Auto_Sub_Func+0x8a>
+			  {
+				  Forward_Flag_Robot_Auto=Fight_Alternately;
+ 8029da2:	4b0f      	ldr	r3, [pc, #60]	@ (8029de0 <Move_Horizontal_Auto_Sub_Func+0xc0>)
+ 8029da4:	2205      	movs	r2, #5
+ 8029da6:	601a      	str	r2, [r3, #0]
+ 8029da8:	e006      	b.n	8029db8 <Move_Horizontal_Auto_Sub_Func+0x98>
+			  }
+			  else if(GV_Robot_backMode==2)
+ 8029daa:	4b12      	ldr	r3, [pc, #72]	@ (8029df4 <Move_Horizontal_Auto_Sub_Func+0xd4>)
+ 8029dac:	681b      	ldr	r3, [r3, #0]
+ 8029dae:	2b02      	cmp	r3, #2
+ 8029db0:	d102      	bne.n	8029db8 <Move_Horizontal_Auto_Sub_Func+0x98>
+			  {
+				  Forward_Flag_Robot_Auto=Fight_retreating;
+ 8029db2:	4b0b      	ldr	r3, [pc, #44]	@ (8029de0 <Move_Horizontal_Auto_Sub_Func+0xc0>)
+ 8029db4:	2206      	movs	r2, #6
+ 8029db6:	601a      	str	r2, [r3, #0]
+			  }
+			  Robot_Platform_Back_Flag=0;
+ 8029db8:	4b0c      	ldr	r3, [pc, #48]	@ (8029dec <Move_Horizontal_Auto_Sub_Func+0xcc>)
+ 8029dba:	2200      	movs	r2, #0
+ 8029dbc:	601a      	str	r2, [r3, #0]
+
+			  break;
+ 8029dbe:	e00c      	b.n	8029dda <Move_Horizontal_Auto_Sub_Func+0xba>
+		  case Fight_Alternately:
+			  Horiz_Angle_Judge();
+ 8029dc0:	f001 fc42 	bl	802b648 <Horiz_Angle_Judge>
+			  Fight_Alternately_Function_Horizontal();
+ 8029dc4:	f003 fc04 	bl	802d5d0 <Fight_Alternately_Function_Horizontal>
+			  break;
+ 8029dc8:	e007      	b.n	8029dda <Move_Horizontal_Auto_Sub_Func+0xba>
+		  case Fight_retreating:
+			  Horiz_Angle_Judge();
+ 8029dca:	f001 fc3d 	bl	802b648 <Horiz_Angle_Judge>
+			  Fight_Countinus_Function_Horizontal();
+ 8029dce:	f003 fc07 	bl	802d5e0 <Fight_Countinus_Function_Horizontal>
+			  break;
+ 8029dd2:	e002      	b.n	8029dda <Move_Horizontal_Auto_Sub_Func+0xba>
+		  default:
+			  HALT_State_Do();
+ 8029dd4:	f006 f9c8 	bl	8030168 <HALT_State_Do>
+			  break;
+ 8029dd8:	bf00      	nop
+	  }
+
+}
+ 8029dda:	bf00      	nop
+ 8029ddc:	bd80      	pop	{r7, pc}
+ 8029dde:	bf00      	nop
+ 8029de0:	2400a798 	.word	0x2400a798
+ 8029de4:	2400a9e8 	.word	0x2400a9e8
+ 8029de8:	24000090 	.word	0x24000090
+ 8029dec:	2400a6f8 	.word	0x2400a6f8
+ 8029df0:	2400a6f4 	.word	0x2400a6f4
+ 8029df4:	2400a720 	.word	0x2400a720
+
+08029df8 <Change_Road_Down_Left_Right>:
+void Change_Road_Down_Left_Right()
+{
+ 8029df8:	b580      	push	{r7, lr}
+ 8029dfa:	b082      	sub	sp, #8
+ 8029dfc:	af00      	add	r7, sp, #0
+	switch(Change_Road_Jude_Flag)
+ 8029dfe:	4b1c      	ldr	r3, [pc, #112]	@ (8029e70 <Change_Road_Down_Left_Right+0x78>)
+ 8029e00:	681b      	ldr	r3, [r3, #0]
+ 8029e02:	2b02      	cmp	r3, #2
+ 8029e04:	d028      	beq.n	8029e58 <Change_Road_Down_Left_Right+0x60>
+ 8029e06:	2b02      	cmp	r3, #2
+ 8029e08:	dc29      	bgt.n	8029e5e <Change_Road_Down_Left_Right+0x66>
+ 8029e0a:	2b00      	cmp	r3, #0
+ 8029e0c:	d002      	beq.n	8029e14 <Change_Road_Down_Left_Right+0x1c>
+ 8029e0e:	2b01      	cmp	r3, #1
+ 8029e10:	d01f      	beq.n	8029e52 <Change_Road_Down_Left_Right+0x5a>
+		case 2:
+			Change_Road_Right();
+			break;
+		}
+//	  UltraStopReverse(CRLU_Flag);
+}
+ 8029e12:	e024      	b.n	8029e5e <Change_Road_Down_Left_Right+0x66>
+			double Robot_Angle_DEG=((double)GV.TL720DParameters.RF_Angle_Roll)/100;
+ 8029e14:	4b17      	ldr	r3, [pc, #92]	@ (8029e74 <Change_Road_Down_Left_Right+0x7c>)
+ 8029e16:	f8d3 3218 	ldr.w	r3, [r3, #536]	@ 0x218
+ 8029e1a:	ee07 3a90 	vmov	s15, r3
+ 8029e1e:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 8029e22:	ed9f 5b11 	vldr	d5, [pc, #68]	@ 8029e68 <Change_Road_Down_Left_Right+0x70>
+ 8029e26:	ee86 7b05 	vdiv.f64	d7, d6, d5
+ 8029e2a:	ed87 7b00 	vstr	d7, [r7]
+			if(Robot_Angle_DEG>0)
+ 8029e2e:	ed97 7b00 	vldr	d7, [r7]
+ 8029e32:	eeb5 7bc0 	vcmpe.f64	d7, #0.0
+ 8029e36:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 8029e3a:	dd03      	ble.n	8029e44 <Change_Road_Down_Left_Right+0x4c>
+				Change_Road_Jude_Flag=1;
+ 8029e3c:	4b0c      	ldr	r3, [pc, #48]	@ (8029e70 <Change_Road_Down_Left_Right+0x78>)
+ 8029e3e:	2201      	movs	r2, #1
+ 8029e40:	601a      	str	r2, [r3, #0]
+ 8029e42:	e002      	b.n	8029e4a <Change_Road_Down_Left_Right+0x52>
+				Change_Road_Jude_Flag=2;
+ 8029e44:	4b0a      	ldr	r3, [pc, #40]	@ (8029e70 <Change_Road_Down_Left_Right+0x78>)
+ 8029e46:	2202      	movs	r2, #2
+ 8029e48:	601a      	str	r2, [r3, #0]
+			 CRLU_Flag=0;
+ 8029e4a:	4b0b      	ldr	r3, [pc, #44]	@ (8029e78 <Change_Road_Down_Left_Right+0x80>)
+ 8029e4c:	2200      	movs	r2, #0
+ 8029e4e:	601a      	str	r2, [r3, #0]
+			break;
+ 8029e50:	e005      	b.n	8029e5e <Change_Road_Down_Left_Right+0x66>
+			Change_Road_Left();
+ 8029e52:	f003 f86b 	bl	802cf2c <Change_Road_Left>
+			break;
+ 8029e56:	e002      	b.n	8029e5e <Change_Road_Down_Left_Right+0x66>
+			Change_Road_Right();
+ 8029e58:	f003 f910 	bl	802d07c <Change_Road_Right>
+			break;
+ 8029e5c:	bf00      	nop
+}
+ 8029e5e:	bf00      	nop
+ 8029e60:	3708      	adds	r7, #8
+ 8029e62:	46bd      	mov	sp, r7
+ 8029e64:	bd80      	pop	{r7, pc}
+ 8029e66:	bf00      	nop
+ 8029e68:	00000000 	.word	0x00000000
+ 8029e6c:	40590000 	.word	0x40590000
+ 8029e70:	2400a6f0 	.word	0x2400a6f0
+ 8029e74:	24000340 	.word	0x24000340
+ 8029e78:	2400a9f0 	.word	0x2400a9f0
+ 8029e7c:	00000000 	.word	0x00000000
+
+08029e80 <Horizontal_Manual_Operation_Func>:
+
+void Horizontal_Manual_Operation_Func()
+{
+ 8029e80:	b580      	push	{r7, lr}
+ 8029e82:	b088      	sub	sp, #32
+ 8029e84:	af00      	add	r7, sp, #0
+    double y_value = P_MK32->CH2_LY_V; // 假设 Y 是纵向（前后）
+ 8029e86:	4b94      	ldr	r3, [pc, #592]	@ (802a0d8 <Horizontal_Manual_Operation_Func+0x258>)
+ 8029e88:	681b      	ldr	r3, [r3, #0]
+ 8029e8a:	68db      	ldr	r3, [r3, #12]
+ 8029e8c:	ee07 3a90 	vmov	s15, r3
+ 8029e90:	eeb8 7be7 	vcvt.f64.s32	d7, s15
+ 8029e94:	ed87 7b06 	vstr	d7, [r7, #24]
+    double x_value = P_MK32->CH3_LY_H; // 假设 X 是横向（左右）
+ 8029e98:	4b8f      	ldr	r3, [pc, #572]	@ (802a0d8 <Horizontal_Manual_Operation_Func+0x258>)
+ 8029e9a:	681b      	ldr	r3, [r3, #0]
+ 8029e9c:	691b      	ldr	r3, [r3, #16]
+ 8029e9e:	ee07 3a90 	vmov	s15, r3
+ 8029ea2:	eeb8 7be7 	vcvt.f64.s32	d7, s15
+ 8029ea6:	ed87 7b04 	vstr	d7, [r7, #16]
+
+	double w_value = P_MK32->CH0_RY_H; // 假设 X 是横向（左右）
+ 8029eaa:	4b8b      	ldr	r3, [pc, #556]	@ (802a0d8 <Horizontal_Manual_Operation_Func+0x258>)
+ 8029eac:	681b      	ldr	r3, [r3, #0]
+ 8029eae:	685b      	ldr	r3, [r3, #4]
+ 8029eb0:	ee07 3a90 	vmov	s15, r3
+ 8029eb4:	eeb8 7be7 	vcvt.f64.s32	d7, s15
+ 8029eb8:	ed87 7b02 	vstr	d7, [r7, #8]
+	double z_value = P_MK32->CH1_RY_V; // 假设 X 是横向（左右）
+ 8029ebc:	4b86      	ldr	r3, [pc, #536]	@ (802a0d8 <Horizontal_Manual_Operation_Func+0x258>)
+ 8029ebe:	681b      	ldr	r3, [r3, #0]
+ 8029ec0:	689b      	ldr	r3, [r3, #8]
+ 8029ec2:	ee07 3a90 	vmov	s15, r3
+ 8029ec6:	eeb8 7be7 	vcvt.f64.s32	d7, s15
+ 8029eca:	ed87 7b00 	vstr	d7, [r7]
+
+    static int Horizontal_Manual_Flag ; // 静态局部变量
+
+    if((fabs(y_value)>=300)||(fabs(x_value)>=300)||(fabs(w_value)>=300)||(fabs(z_value)>=300))
+ 8029ece:	ed97 7b06 	vldr	d7, [r7, #24]
+ 8029ed2:	eeb0 7bc7 	vabs.f64	d7, d7
+ 8029ed6:	ed9f 6b70 	vldr	d6, [pc, #448]	@ 802a098 <Horizontal_Manual_Operation_Func+0x218>
+ 8029eda:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 8029ede:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 8029ee2:	da21      	bge.n	8029f28 <Horizontal_Manual_Operation_Func+0xa8>
+ 8029ee4:	ed97 7b04 	vldr	d7, [r7, #16]
+ 8029ee8:	eeb0 7bc7 	vabs.f64	d7, d7
+ 8029eec:	ed9f 6b6a 	vldr	d6, [pc, #424]	@ 802a098 <Horizontal_Manual_Operation_Func+0x218>
+ 8029ef0:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 8029ef4:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 8029ef8:	da16      	bge.n	8029f28 <Horizontal_Manual_Operation_Func+0xa8>
+ 8029efa:	ed97 7b02 	vldr	d7, [r7, #8]
+ 8029efe:	eeb0 7bc7 	vabs.f64	d7, d7
+ 8029f02:	ed9f 6b65 	vldr	d6, [pc, #404]	@ 802a098 <Horizontal_Manual_Operation_Func+0x218>
+ 8029f06:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 8029f0a:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 8029f0e:	da0b      	bge.n	8029f28 <Horizontal_Manual_Operation_Func+0xa8>
+ 8029f10:	ed97 7b00 	vldr	d7, [r7]
+ 8029f14:	eeb0 7bc7 	vabs.f64	d7, d7
+ 8029f18:	ed9f 6b5f 	vldr	d6, [pc, #380]	@ 802a098 <Horizontal_Manual_Operation_Func+0x218>
+ 8029f1c:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 8029f20:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 8029f24:	f2c0 80a6 	blt.w	802a074 <Horizontal_Manual_Operation_Func+0x1f4>
+     {
+     	switch(Horizontal_Manual_Flag)
+ 8029f28:	4b6c      	ldr	r3, [pc, #432]	@ (802a0dc <Horizontal_Manual_Operation_Func+0x25c>)
+ 8029f2a:	681b      	ldr	r3, [r3, #0]
+ 8029f2c:	2b00      	cmp	r3, #0
+ 8029f2e:	d002      	beq.n	8029f36 <Horizontal_Manual_Operation_Func+0xb6>
+ 8029f30:	2b01      	cmp	r3, #1
+ 8029f32:	d006      	beq.n	8029f42 <Horizontal_Manual_Operation_Func+0xc2>
+ 8029f34:	e0a9      	b.n	802a08a <Horizontal_Manual_Operation_Func+0x20a>
+     	{
+     		case 0:
+     			Horizontal_Manual_Flag++;
+ 8029f36:	4b69      	ldr	r3, [pc, #420]	@ (802a0dc <Horizontal_Manual_Operation_Func+0x25c>)
+ 8029f38:	681b      	ldr	r3, [r3, #0]
+ 8029f3a:	3301      	adds	r3, #1
+ 8029f3c:	4a67      	ldr	r2, [pc, #412]	@ (802a0dc <Horizontal_Manual_Operation_Func+0x25c>)
+ 8029f3e:	6013      	str	r3, [r2, #0]
+     			break;
+ 8029f40:	e097      	b.n	802a072 <Horizontal_Manual_Operation_Func+0x1f2>
+     		case 1:
+				if((fabs(y_value)>=300)||(fabs(x_value)>=300))
+ 8029f42:	ed97 7b06 	vldr	d7, [r7, #24]
+ 8029f46:	eeb0 7bc7 	vabs.f64	d7, d7
+ 8029f4a:	ed9f 6b53 	vldr	d6, [pc, #332]	@ 802a098 <Horizontal_Manual_Operation_Func+0x218>
+ 8029f4e:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 8029f52:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 8029f56:	da0a      	bge.n	8029f6e <Horizontal_Manual_Operation_Func+0xee>
+ 8029f58:	ed97 7b04 	vldr	d7, [r7, #16]
+ 8029f5c:	eeb0 7bc7 	vabs.f64	d7, d7
+ 8029f60:	ed9f 6b4d 	vldr	d6, [pc, #308]	@ 802a098 <Horizontal_Manual_Operation_Func+0x218>
+ 8029f64:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 8029f68:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 8029f6c:	db79      	blt.n	802a062 <Horizontal_Manual_Operation_Func+0x1e2>
+				{
+					Rock_Angle= atan2(y_value, x_value);
+ 8029f6e:	ed97 1b04 	vldr	d1, [r7, #16]
+ 8029f72:	ed97 0b06 	vldr	d0, [r7, #24]
+ 8029f76:	f016 fdaf 	bl	8040ad8 <atan2>
+ 8029f7a:	eeb0 7b40 	vmov.f64	d7, d0
+ 8029f7e:	4b58      	ldr	r3, [pc, #352]	@ (802a0e0 <Horizontal_Manual_Operation_Func+0x260>)
+ 8029f80:	ed83 7b00 	vstr	d7, [r3]
+					Rock_Angle=Rock_Angle/3.1415926*180;
+ 8029f84:	4b56      	ldr	r3, [pc, #344]	@ (802a0e0 <Horizontal_Manual_Operation_Func+0x260>)
+ 8029f86:	ed93 6b00 	vldr	d6, [r3]
+ 8029f8a:	ed9f 5b45 	vldr	d5, [pc, #276]	@ 802a0a0 <Horizontal_Manual_Operation_Func+0x220>
+ 8029f8e:	ee86 7b05 	vdiv.f64	d7, d6, d5
+ 8029f92:	ed9f 6b45 	vldr	d6, [pc, #276]	@ 802a0a8 <Horizontal_Manual_Operation_Func+0x228>
+ 8029f96:	ee27 7b06 	vmul.f64	d7, d7, d6
+ 8029f9a:	4b51      	ldr	r3, [pc, #324]	@ (802a0e0 <Horizontal_Manual_Operation_Func+0x260>)
+ 8029f9c:	ed83 7b00 	vstr	d7, [r3]
+
+					if((Rock_Angle>=-30)&&(Rock_Angle<=30))
+ 8029fa0:	4b4f      	ldr	r3, [pc, #316]	@ (802a0e0 <Horizontal_Manual_Operation_Func+0x260>)
+ 8029fa2:	ed93 7b00 	vldr	d7, [r3]
+ 8029fa6:	eebb 6b0e 	vmov.f64	d6, #190	@ 0xc1f00000 -30.0
+ 8029faa:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 8029fae:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 8029fb2:	db0f      	blt.n	8029fd4 <Horizontal_Manual_Operation_Func+0x154>
+ 8029fb4:	4b4a      	ldr	r3, [pc, #296]	@ (802a0e0 <Horizontal_Manual_Operation_Func+0x260>)
+ 8029fb6:	ed93 7b00 	vldr	d7, [r3]
+ 8029fba:	eeb3 6b0e 	vmov.f64	d6, #62	@ 0x41f00000  30.0
+ 8029fbe:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 8029fc2:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 8029fc6:	d805      	bhi.n	8029fd4 <Horizontal_Manual_Operation_Func+0x154>
+					{
+						TurnRight_State_Do();
+ 8029fc8:	f003 f96a 	bl	802d2a0 <TurnRight_State_Do>
+						Forward_Flag_Robot_Manual=1;
+ 8029fcc:	4b45      	ldr	r3, [pc, #276]	@ (802a0e4 <Horizontal_Manual_Operation_Func+0x264>)
+ 8029fce:	2201      	movs	r2, #1
+ 8029fd0:	601a      	str	r2, [r3, #0]
+ 8029fd2:	e045      	b.n	802a060 <Horizontal_Manual_Operation_Func+0x1e0>
+					}
+					else if((Rock_Angle>=60)&&(Rock_Angle<=120))
+ 8029fd4:	4b42      	ldr	r3, [pc, #264]	@ (802a0e0 <Horizontal_Manual_Operation_Func+0x260>)
+ 8029fd6:	ed93 7b00 	vldr	d7, [r3]
+ 8029fda:	ed9f 6b35 	vldr	d6, [pc, #212]	@ 802a0b0 <Horizontal_Manual_Operation_Func+0x230>
+ 8029fde:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 8029fe2:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 8029fe6:	db0c      	blt.n	802a002 <Horizontal_Manual_Operation_Func+0x182>
+ 8029fe8:	4b3d      	ldr	r3, [pc, #244]	@ (802a0e0 <Horizontal_Manual_Operation_Func+0x260>)
+ 8029fea:	ed93 7b00 	vldr	d7, [r3]
+ 8029fee:	ed9f 6b32 	vldr	d6, [pc, #200]	@ 802a0b8 <Horizontal_Manual_Operation_Func+0x238>
+ 8029ff2:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 8029ff6:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 8029ffa:	d802      	bhi.n	802a002 <Horizontal_Manual_Operation_Func+0x182>
+					{
+						Move_Horizontal_Manual_Sub_Func_Forwards();
+ 8029ffc:	f001 fa90 	bl	802b520 <Move_Horizontal_Manual_Sub_Func_Forwards>
+					{
+ 802a000:	e02e      	b.n	802a060 <Horizontal_Manual_Operation_Func+0x1e0>
+					}
+					else if((Rock_Angle>=-120)&&(Rock_Angle<=-60))
+ 802a002:	4b37      	ldr	r3, [pc, #220]	@ (802a0e0 <Horizontal_Manual_Operation_Func+0x260>)
+ 802a004:	ed93 7b00 	vldr	d7, [r3]
+ 802a008:	ed9f 6b2d 	vldr	d6, [pc, #180]	@ 802a0c0 <Horizontal_Manual_Operation_Func+0x240>
+ 802a00c:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 802a010:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802a014:	db0c      	blt.n	802a030 <Horizontal_Manual_Operation_Func+0x1b0>
+ 802a016:	4b32      	ldr	r3, [pc, #200]	@ (802a0e0 <Horizontal_Manual_Operation_Func+0x260>)
+ 802a018:	ed93 7b00 	vldr	d7, [r3]
+ 802a01c:	ed9f 6b2a 	vldr	d6, [pc, #168]	@ 802a0c8 <Horizontal_Manual_Operation_Func+0x248>
+ 802a020:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 802a024:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802a028:	d802      	bhi.n	802a030 <Horizontal_Manual_Operation_Func+0x1b0>
+					{
+						Move_Horizontal_Manual_Sub_Func_Backwards();
+ 802a02a:	f001 fac3 	bl	802b5b4 <Move_Horizontal_Manual_Sub_Func_Backwards>
+					{
+ 802a02e:	e017      	b.n	802a060 <Horizontal_Manual_Operation_Func+0x1e0>
+					}
+					else if(fabs(Rock_Angle)>=150)
+ 802a030:	4b2b      	ldr	r3, [pc, #172]	@ (802a0e0 <Horizontal_Manual_Operation_Func+0x260>)
+ 802a032:	ed93 7b00 	vldr	d7, [r3]
+ 802a036:	eeb0 7bc7 	vabs.f64	d7, d7
+ 802a03a:	ed9f 6b25 	vldr	d6, [pc, #148]	@ 802a0d0 <Horizontal_Manual_Operation_Func+0x250>
+ 802a03e:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 802a042:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802a046:	db05      	blt.n	802a054 <Horizontal_Manual_Operation_Func+0x1d4>
+					{
+						TurnLeft_State_Do();
+ 802a048:	f003 f900 	bl	802d24c <TurnLeft_State_Do>
+						Forward_Flag_Robot_Manual=1;
+ 802a04c:	4b25      	ldr	r3, [pc, #148]	@ (802a0e4 <Horizontal_Manual_Operation_Func+0x264>)
+ 802a04e:	2201      	movs	r2, #1
+ 802a050:	601a      	str	r2, [r3, #0]
+					if((Rock_Angle>=-30)&&(Rock_Angle<=30))
+ 802a052:	e00b      	b.n	802a06c <Horizontal_Manual_Operation_Func+0x1ec>
+					}
+					else
+					{
+						HALT_State_Do();
+ 802a054:	f006 f888 	bl	8030168 <HALT_State_Do>
+						Forward_Flag_Robot_Manual=1;
+ 802a058:	4b22      	ldr	r3, [pc, #136]	@ (802a0e4 <Horizontal_Manual_Operation_Func+0x264>)
+ 802a05a:	2201      	movs	r2, #1
+ 802a05c:	601a      	str	r2, [r3, #0]
+					if((Rock_Angle>=-30)&&(Rock_Angle<=30))
+ 802a05e:	e005      	b.n	802a06c <Horizontal_Manual_Operation_Func+0x1ec>
+ 802a060:	e004      	b.n	802a06c <Horizontal_Manual_Operation_Func+0x1ec>
+					}
+				}
+				else
+				{
+					HALT_State_Do();
+ 802a062:	f006 f881 	bl	8030168 <HALT_State_Do>
+					Forward_Flag_Robot_Manual=1;
+ 802a066:	4b1f      	ldr	r3, [pc, #124]	@ (802a0e4 <Horizontal_Manual_Operation_Func+0x264>)
+ 802a068:	2201      	movs	r2, #1
+ 802a06a:	601a      	str	r2, [r3, #0]
+				}
+
+				Robot_Swing_Operation_Function();//摆臂运动函数
+ 802a06c:	f7ff fdd6 	bl	8029c1c <Robot_Swing_Operation_Function>
+     			break;
+ 802a070:	bf00      	nop
+     	switch(Horizontal_Manual_Flag)
+ 802a072:	e00a      	b.n	802a08a <Horizontal_Manual_Operation_Func+0x20a>
+     	}
+     }
+ 	else
+ 	{
+ 		Horizontal_Manual_Flag=0;
+ 802a074:	4b19      	ldr	r3, [pc, #100]	@ (802a0dc <Horizontal_Manual_Operation_Func+0x25c>)
+ 802a076:	2200      	movs	r2, #0
+ 802a078:	601a      	str	r2, [r3, #0]
+ 		HALT_State_Do();
+ 802a07a:	f006 f875 	bl	8030168 <HALT_State_Do>
+ 		Forward_Flag_Robot_Manual=1;
+ 802a07e:	4b19      	ldr	r3, [pc, #100]	@ (802a0e4 <Horizontal_Manual_Operation_Func+0x264>)
+ 802a080:	2201      	movs	r2, #1
+ 802a082:	601a      	str	r2, [r3, #0]
+ 		Move_Swing_Halt_Func_Do();
+ 802a084:	f003 f9d6 	bl	802d434 <Move_Swing_Halt_Func_Do>
+ 	}
+}
+ 802a088:	bf00      	nop
+ 802a08a:	bf00      	nop
+ 802a08c:	3720      	adds	r7, #32
+ 802a08e:	46bd      	mov	sp, r7
+ 802a090:	bd80      	pop	{r7, pc}
+ 802a092:	bf00      	nop
+ 802a094:	f3af 8000 	nop.w
+ 802a098:	00000000 	.word	0x00000000
+ 802a09c:	4072c000 	.word	0x4072c000
+ 802a0a0:	4d12d84a 	.word	0x4d12d84a
+ 802a0a4:	400921fb 	.word	0x400921fb
+ 802a0a8:	00000000 	.word	0x00000000
+ 802a0ac:	40668000 	.word	0x40668000
+ 802a0b0:	00000000 	.word	0x00000000
+ 802a0b4:	404e0000 	.word	0x404e0000
+ 802a0b8:	00000000 	.word	0x00000000
+ 802a0bc:	405e0000 	.word	0x405e0000
+ 802a0c0:	00000000 	.word	0x00000000
+ 802a0c4:	c05e0000 	.word	0xc05e0000
+ 802a0c8:	00000000 	.word	0x00000000
+ 802a0cc:	c04e0000 	.word	0xc04e0000
+ 802a0d0:	00000000 	.word	0x00000000
+ 802a0d4:	4062c000 	.word	0x4062c000
+ 802a0d8:	2400a3f8 	.word	0x2400a3f8
+ 802a0dc:	2400a890 	.word	0x2400a890
+ 802a0e0:	2400a768 	.word	0x2400a768
+ 802a0e4:	24000098 	.word	0x24000098
+
+0802a0e8 <Vertical_Operatin_Main_Func_Left>:
+
+
+
+
+void Vertical_Operatin_Main_Func_Left()
+{
+ 802a0e8:	b580      	push	{r7, lr}
+ 802a0ea:	af00      	add	r7, sp, #0
+	Blast_Machine_Control_Fun();
+ 802a0ec:	f7fc f95e 	bl	80263ac <Blast_Machine_Control_Fun>
+	if(P_MK32->CH7_SD==-1000)//自动行驶
+ 802a0f0:	4b3c      	ldr	r3, [pc, #240]	@ (802a1e4 <Vertical_Operatin_Main_Func_Left+0xfc>)
+ 802a0f2:	681b      	ldr	r3, [r3, #0]
+ 802a0f4:	6a1b      	ldr	r3, [r3, #32]
+ 802a0f6:	f513 7f7a 	cmn.w	r3, #1000	@ 0x3e8
+ 802a0fa:	d113      	bne.n	802a124 <Vertical_Operatin_Main_Func_Left+0x3c>
+	{
+		Move_Vertical_Auto_Sub_Func();
+ 802a0fc:	f000 f9ba 	bl	802a474 <Move_Vertical_Auto_Sub_Func>
+		UltraStopReverse(Forward_Flag_Robot_Auto);
+ 802a100:	4b39      	ldr	r3, [pc, #228]	@ (802a1e8 <Vertical_Operatin_Main_Func_Left+0x100>)
+ 802a102:	681b      	ldr	r3, [r3, #0]
+ 802a104:	4618      	mov	r0, r3
+ 802a106:	f7ff fbd7 	bl	80298b8 <UltraStopReverse>
+		CRLU_Flag=0;
+ 802a10a:	4b38      	ldr	r3, [pc, #224]	@ (802a1ec <Vertical_Operatin_Main_Func_Left+0x104>)
+ 802a10c:	2200      	movs	r2, #0
+ 802a10e:	601a      	str	r2, [r3, #0]
+		Forward_Flag_Robot_Manual=1;
+ 802a110:	4b37      	ldr	r3, [pc, #220]	@ (802a1f0 <Vertical_Operatin_Main_Func_Left+0x108>)
+ 802a112:	2201      	movs	r2, #1
+ 802a114:	601a      	str	r2, [r3, #0]
+		Forward_Flag_Robot_Manual_Count=0;
+ 802a116:	4b37      	ldr	r3, [pc, #220]	@ (802a1f4 <Vertical_Operatin_Main_Func_Left+0x10c>)
+ 802a118:	2200      	movs	r2, #0
+ 802a11a:	601a      	str	r2, [r3, #0]
+		Pressure_Adaptive_Function_Uptata(200);
+ 802a11c:	20c8      	movs	r0, #200	@ 0xc8
+ 802a11e:	f004 ffb5 	bl	802f08c <Pressure_Adaptive_Function_Uptata>
+		Swing_Limit_Flag=0;
+		Forward_Flag_Robot_Manual_Count=0;
+		UltraStopReverse_Manually_Backward();
+		PushRod_Contronl();
+	}
+}
+ 802a122:	e05d      	b.n	802a1e0 <Vertical_Operatin_Main_Func_Left+0xf8>
+	else if(P_MK32->CH4_SA==-1000)//从右向左换道
+ 802a124:	4b2f      	ldr	r3, [pc, #188]	@ (802a1e4 <Vertical_Operatin_Main_Func_Left+0xfc>)
+ 802a126:	681b      	ldr	r3, [r3, #0]
+ 802a128:	695b      	ldr	r3, [r3, #20]
+ 802a12a:	f513 7f7a 	cmn.w	r3, #1000	@ 0x3e8
+ 802a12e:	d10b      	bne.n	802a148 <Vertical_Operatin_Main_Func_Left+0x60>
+		Change_Road_Down_Up_Right_To_Left();
+ 802a130:	f002 f876 	bl	802c220 <Change_Road_Down_Up_Right_To_Left>
+		Forward_Flag_Robot_Auto=1;
+ 802a134:	4b2c      	ldr	r3, [pc, #176]	@ (802a1e8 <Vertical_Operatin_Main_Func_Left+0x100>)
+ 802a136:	2201      	movs	r2, #1
+ 802a138:	601a      	str	r2, [r3, #0]
+		Forward_Flag_Robot_Manual=1;
+ 802a13a:	4b2d      	ldr	r3, [pc, #180]	@ (802a1f0 <Vertical_Operatin_Main_Func_Left+0x108>)
+ 802a13c:	2201      	movs	r2, #1
+ 802a13e:	601a      	str	r2, [r3, #0]
+		Forward_Flag_Robot_Manual_Count=0;
+ 802a140:	4b2c      	ldr	r3, [pc, #176]	@ (802a1f4 <Vertical_Operatin_Main_Func_Left+0x10c>)
+ 802a142:	2200      	movs	r2, #0
+ 802a144:	601a      	str	r2, [r3, #0]
+}
+ 802a146:	e04b      	b.n	802a1e0 <Vertical_Operatin_Main_Func_Left+0xf8>
+	else if(P_MK32->CH5_SB==-1000)//前进自动巡航
+ 802a148:	4b26      	ldr	r3, [pc, #152]	@ (802a1e4 <Vertical_Operatin_Main_Func_Left+0xfc>)
+ 802a14a:	681b      	ldr	r3, [r3, #0]
+ 802a14c:	699b      	ldr	r3, [r3, #24]
+ 802a14e:	f513 7f7a 	cmn.w	r3, #1000	@ 0x3e8
+ 802a152:	d111      	bne.n	802a178 <Vertical_Operatin_Main_Func_Left+0x90>
+		if(Forward_Flag_Robot_Manual_Count<1)
+ 802a154:	4b27      	ldr	r3, [pc, #156]	@ (802a1f4 <Vertical_Operatin_Main_Func_Left+0x10c>)
+ 802a156:	681b      	ldr	r3, [r3, #0]
+ 802a158:	2b00      	cmp	r3, #0
+ 802a15a:	dc07      	bgt.n	802a16c <Vertical_Operatin_Main_Func_Left+0x84>
+			Forward_Flag_Robot_Manual_Count++;
+ 802a15c:	4b25      	ldr	r3, [pc, #148]	@ (802a1f4 <Vertical_Operatin_Main_Func_Left+0x10c>)
+ 802a15e:	681b      	ldr	r3, [r3, #0]
+ 802a160:	3301      	adds	r3, #1
+ 802a162:	4a24      	ldr	r2, [pc, #144]	@ (802a1f4 <Vertical_Operatin_Main_Func_Left+0x10c>)
+ 802a164:	6013      	str	r3, [r2, #0]
+			Forward_Flag_Robot_Manual=1;
+ 802a166:	4b22      	ldr	r3, [pc, #136]	@ (802a1f0 <Vertical_Operatin_Main_Func_Left+0x108>)
+ 802a168:	2201      	movs	r2, #1
+ 802a16a:	601a      	str	r2, [r3, #0]
+		Move_Vertical_Manual_Sub_Func_Forward();
+ 802a16c:	f000 f8d4 	bl	802a318 <Move_Vertical_Manual_Sub_Func_Forward>
+		CRLU_Flag=0;
+ 802a170:	4b1e      	ldr	r3, [pc, #120]	@ (802a1ec <Vertical_Operatin_Main_Func_Left+0x104>)
+ 802a172:	2200      	movs	r2, #0
+ 802a174:	601a      	str	r2, [r3, #0]
+}
+ 802a176:	e033      	b.n	802a1e0 <Vertical_Operatin_Main_Func_Left+0xf8>
+	else if(P_MK32->CH5_SB==1000)//后退自动巡航
+ 802a178:	4b1a      	ldr	r3, [pc, #104]	@ (802a1e4 <Vertical_Operatin_Main_Func_Left+0xfc>)
+ 802a17a:	681b      	ldr	r3, [r3, #0]
+ 802a17c:	699b      	ldr	r3, [r3, #24]
+ 802a17e:	f5b3 7f7a 	cmp.w	r3, #1000	@ 0x3e8
+ 802a182:	d116      	bne.n	802a1b2 <Vertical_Operatin_Main_Func_Left+0xca>
+		if(Forward_Flag_Robot_Manual_Count<1)
+ 802a184:	4b1b      	ldr	r3, [pc, #108]	@ (802a1f4 <Vertical_Operatin_Main_Func_Left+0x10c>)
+ 802a186:	681b      	ldr	r3, [r3, #0]
+ 802a188:	2b00      	cmp	r3, #0
+ 802a18a:	dc07      	bgt.n	802a19c <Vertical_Operatin_Main_Func_Left+0xb4>
+			Forward_Flag_Robot_Manual_Count++;
+ 802a18c:	4b19      	ldr	r3, [pc, #100]	@ (802a1f4 <Vertical_Operatin_Main_Func_Left+0x10c>)
+ 802a18e:	681b      	ldr	r3, [r3, #0]
+ 802a190:	3301      	adds	r3, #1
+ 802a192:	4a18      	ldr	r2, [pc, #96]	@ (802a1f4 <Vertical_Operatin_Main_Func_Left+0x10c>)
+ 802a194:	6013      	str	r3, [r2, #0]
+			Forward_Flag_Robot_Manual=1;
+ 802a196:	4b16      	ldr	r3, [pc, #88]	@ (802a1f0 <Vertical_Operatin_Main_Func_Left+0x108>)
+ 802a198:	2201      	movs	r2, #1
+ 802a19a:	601a      	str	r2, [r3, #0]
+		Move_Vertical_Manual_Sub_Func_Backward();
+ 802a19c:	f000 f914 	bl	802a3c8 <Move_Vertical_Manual_Sub_Func_Backward>
+		UltraStopReverse(Forward_Flag_Robot_Manual);
+ 802a1a0:	4b13      	ldr	r3, [pc, #76]	@ (802a1f0 <Vertical_Operatin_Main_Func_Left+0x108>)
+ 802a1a2:	681b      	ldr	r3, [r3, #0]
+ 802a1a4:	4618      	mov	r0, r3
+ 802a1a6:	f7ff fb87 	bl	80298b8 <UltraStopReverse>
+		CRLU_Flag=0;
+ 802a1aa:	4b10      	ldr	r3, [pc, #64]	@ (802a1ec <Vertical_Operatin_Main_Func_Left+0x104>)
+ 802a1ac:	2200      	movs	r2, #0
+ 802a1ae:	601a      	str	r2, [r3, #0]
+}
+ 802a1b0:	e016      	b.n	802a1e0 <Vertical_Operatin_Main_Func_Left+0xf8>
+		Vertical_Manual_Operation_Func();
+ 802a1b2:	f000 fd6d 	bl	802ac90 <Vertical_Manual_Operation_Func>
+		CRLU_Flag=0;
+ 802a1b6:	4b0d      	ldr	r3, [pc, #52]	@ (802a1ec <Vertical_Operatin_Main_Func_Left+0x104>)
+ 802a1b8:	2200      	movs	r2, #0
+ 802a1ba:	601a      	str	r2, [r3, #0]
+		Forward_Flag_Robot_Auto=1;
+ 802a1bc:	4b0a      	ldr	r3, [pc, #40]	@ (802a1e8 <Vertical_Operatin_Main_Func_Left+0x100>)
+ 802a1be:	2201      	movs	r2, #1
+ 802a1c0:	601a      	str	r2, [r3, #0]
+		Robot_Platform_Back_Flag=0;
+ 802a1c2:	4b0d      	ldr	r3, [pc, #52]	@ (802a1f8 <Vertical_Operatin_Main_Func_Left+0x110>)
+ 802a1c4:	2200      	movs	r2, #0
+ 802a1c6:	601a      	str	r2, [r3, #0]
+		Robot_Main_Mode_Jude();
+ 802a1c8:	f004 f962 	bl	802e490 <Robot_Main_Mode_Jude>
+		Swing_Limit_Flag=0;
+ 802a1cc:	4b0b      	ldr	r3, [pc, #44]	@ (802a1fc <Vertical_Operatin_Main_Func_Left+0x114>)
+ 802a1ce:	2200      	movs	r2, #0
+ 802a1d0:	601a      	str	r2, [r3, #0]
+		Forward_Flag_Robot_Manual_Count=0;
+ 802a1d2:	4b08      	ldr	r3, [pc, #32]	@ (802a1f4 <Vertical_Operatin_Main_Func_Left+0x10c>)
+ 802a1d4:	2200      	movs	r2, #0
+ 802a1d6:	601a      	str	r2, [r3, #0]
+		UltraStopReverse_Manually_Backward();
+ 802a1d8:	f7ff fbd0 	bl	802997c <UltraStopReverse_Manually_Backward>
+		PushRod_Contronl();
+ 802a1dc:	f7ff fbd6 	bl	802998c <PushRod_Contronl>
+}
+ 802a1e0:	bf00      	nop
+ 802a1e2:	bd80      	pop	{r7, pc}
+ 802a1e4:	2400a3f8 	.word	0x2400a3f8
+ 802a1e8:	2400a798 	.word	0x2400a798
+ 802a1ec:	2400a9f0 	.word	0x2400a9f0
+ 802a1f0:	24000098 	.word	0x24000098
+ 802a1f4:	2400a794 	.word	0x2400a794
+ 802a1f8:	2400a6f8 	.word	0x2400a6f8
+ 802a1fc:	2400a6f4 	.word	0x2400a6f4
+
+0802a200 <Vertical_Operatin_Main_Func_Right>:
+void Vertical_Operatin_Main_Func_Right()
+{
+ 802a200:	b580      	push	{r7, lr}
+ 802a202:	af00      	add	r7, sp, #0
+	Blast_Machine_Control_Fun();
+ 802a204:	f7fc f8d2 	bl	80263ac <Blast_Machine_Control_Fun>
+
+	if(P_MK32->CH7_SD==-1000)//自动行驶
+ 802a208:	4b3c      	ldr	r3, [pc, #240]	@ (802a2fc <Vertical_Operatin_Main_Func_Right+0xfc>)
+ 802a20a:	681b      	ldr	r3, [r3, #0]
+ 802a20c:	6a1b      	ldr	r3, [r3, #32]
+ 802a20e:	f513 7f7a 	cmn.w	r3, #1000	@ 0x3e8
+ 802a212:	d113      	bne.n	802a23c <Vertical_Operatin_Main_Func_Right+0x3c>
+	{
+		Move_Vertical_Auto_Sub_Func();
+ 802a214:	f000 f92e 	bl	802a474 <Move_Vertical_Auto_Sub_Func>
+		UltraStopReverse(Forward_Flag_Robot_Auto);
+ 802a218:	4b39      	ldr	r3, [pc, #228]	@ (802a300 <Vertical_Operatin_Main_Func_Right+0x100>)
+ 802a21a:	681b      	ldr	r3, [r3, #0]
+ 802a21c:	4618      	mov	r0, r3
+ 802a21e:	f7ff fb4b 	bl	80298b8 <UltraStopReverse>
+
+		CRLU_Flag=0;
+ 802a222:	4b38      	ldr	r3, [pc, #224]	@ (802a304 <Vertical_Operatin_Main_Func_Right+0x104>)
+ 802a224:	2200      	movs	r2, #0
+ 802a226:	601a      	str	r2, [r3, #0]
+		Forward_Flag_Robot_Manual=1;
+ 802a228:	4b37      	ldr	r3, [pc, #220]	@ (802a308 <Vertical_Operatin_Main_Func_Right+0x108>)
+ 802a22a:	2201      	movs	r2, #1
+ 802a22c:	601a      	str	r2, [r3, #0]
+		Forward_Flag_Robot_Manual_Count=0;
+ 802a22e:	4b37      	ldr	r3, [pc, #220]	@ (802a30c <Vertical_Operatin_Main_Func_Right+0x10c>)
+ 802a230:	2200      	movs	r2, #0
+ 802a232:	601a      	str	r2, [r3, #0]
+		Pressure_Adaptive_Function_Uptata(200);
+ 802a234:	20c8      	movs	r0, #200	@ 0xc8
+ 802a236:	f004 ff29 	bl	802f08c <Pressure_Adaptive_Function_Uptata>
+		Swing_Limit_Flag=0;
+		Forward_Flag_Robot_Manual_Count=0;
+		UltraStopReverse_Manually_Backward();
+		PushRod_Contronl();//推杆上下停止控制
+	}
+}
+ 802a23a:	e05d      	b.n	802a2f8 <Vertical_Operatin_Main_Func_Right+0xf8>
+	else if(P_MK32->CH4_SA==-1000)//从左到右换道
+ 802a23c:	4b2f      	ldr	r3, [pc, #188]	@ (802a2fc <Vertical_Operatin_Main_Func_Right+0xfc>)
+ 802a23e:	681b      	ldr	r3, [r3, #0]
+ 802a240:	695b      	ldr	r3, [r3, #20]
+ 802a242:	f513 7f7a 	cmn.w	r3, #1000	@ 0x3e8
+ 802a246:	d10b      	bne.n	802a260 <Vertical_Operatin_Main_Func_Right+0x60>
+		Change_Road_Down_Up_Left_To_Right();
+ 802a248:	f002 f886 	bl	802c358 <Change_Road_Down_Up_Left_To_Right>
+		Forward_Flag_Robot_Auto=1;
+ 802a24c:	4b2c      	ldr	r3, [pc, #176]	@ (802a300 <Vertical_Operatin_Main_Func_Right+0x100>)
+ 802a24e:	2201      	movs	r2, #1
+ 802a250:	601a      	str	r2, [r3, #0]
+		Forward_Flag_Robot_Manual=1;
+ 802a252:	4b2d      	ldr	r3, [pc, #180]	@ (802a308 <Vertical_Operatin_Main_Func_Right+0x108>)
+ 802a254:	2201      	movs	r2, #1
+ 802a256:	601a      	str	r2, [r3, #0]
+		Forward_Flag_Robot_Manual_Count=0;
+ 802a258:	4b2c      	ldr	r3, [pc, #176]	@ (802a30c <Vertical_Operatin_Main_Func_Right+0x10c>)
+ 802a25a:	2200      	movs	r2, #0
+ 802a25c:	601a      	str	r2, [r3, #0]
+}
+ 802a25e:	e04b      	b.n	802a2f8 <Vertical_Operatin_Main_Func_Right+0xf8>
+	else if(P_MK32->CH5_SB==-1000)//前进自动巡航
+ 802a260:	4b26      	ldr	r3, [pc, #152]	@ (802a2fc <Vertical_Operatin_Main_Func_Right+0xfc>)
+ 802a262:	681b      	ldr	r3, [r3, #0]
+ 802a264:	699b      	ldr	r3, [r3, #24]
+ 802a266:	f513 7f7a 	cmn.w	r3, #1000	@ 0x3e8
+ 802a26a:	d111      	bne.n	802a290 <Vertical_Operatin_Main_Func_Right+0x90>
+		if(Forward_Flag_Robot_Manual_Count<1)
+ 802a26c:	4b27      	ldr	r3, [pc, #156]	@ (802a30c <Vertical_Operatin_Main_Func_Right+0x10c>)
+ 802a26e:	681b      	ldr	r3, [r3, #0]
+ 802a270:	2b00      	cmp	r3, #0
+ 802a272:	dc07      	bgt.n	802a284 <Vertical_Operatin_Main_Func_Right+0x84>
+			Forward_Flag_Robot_Manual_Count++;
+ 802a274:	4b25      	ldr	r3, [pc, #148]	@ (802a30c <Vertical_Operatin_Main_Func_Right+0x10c>)
+ 802a276:	681b      	ldr	r3, [r3, #0]
+ 802a278:	3301      	adds	r3, #1
+ 802a27a:	4a24      	ldr	r2, [pc, #144]	@ (802a30c <Vertical_Operatin_Main_Func_Right+0x10c>)
+ 802a27c:	6013      	str	r3, [r2, #0]
+			Forward_Flag_Robot_Manual=1;
+ 802a27e:	4b22      	ldr	r3, [pc, #136]	@ (802a308 <Vertical_Operatin_Main_Func_Right+0x108>)
+ 802a280:	2201      	movs	r2, #1
+ 802a282:	601a      	str	r2, [r3, #0]
+		Move_Vertical_Manual_Sub_Func_Forward();
+ 802a284:	f000 f848 	bl	802a318 <Move_Vertical_Manual_Sub_Func_Forward>
+		CRLU_Flag=0;
+ 802a288:	4b1e      	ldr	r3, [pc, #120]	@ (802a304 <Vertical_Operatin_Main_Func_Right+0x104>)
+ 802a28a:	2200      	movs	r2, #0
+ 802a28c:	601a      	str	r2, [r3, #0]
+}
+ 802a28e:	e033      	b.n	802a2f8 <Vertical_Operatin_Main_Func_Right+0xf8>
+	else if(P_MK32->CH5_SB==1000)//ho
+ 802a290:	4b1a      	ldr	r3, [pc, #104]	@ (802a2fc <Vertical_Operatin_Main_Func_Right+0xfc>)
+ 802a292:	681b      	ldr	r3, [r3, #0]
+ 802a294:	699b      	ldr	r3, [r3, #24]
+ 802a296:	f5b3 7f7a 	cmp.w	r3, #1000	@ 0x3e8
+ 802a29a:	d116      	bne.n	802a2ca <Vertical_Operatin_Main_Func_Right+0xca>
+		if(Forward_Flag_Robot_Manual_Count<1)
+ 802a29c:	4b1b      	ldr	r3, [pc, #108]	@ (802a30c <Vertical_Operatin_Main_Func_Right+0x10c>)
+ 802a29e:	681b      	ldr	r3, [r3, #0]
+ 802a2a0:	2b00      	cmp	r3, #0
+ 802a2a2:	dc07      	bgt.n	802a2b4 <Vertical_Operatin_Main_Func_Right+0xb4>
+			Forward_Flag_Robot_Manual_Count++;
+ 802a2a4:	4b19      	ldr	r3, [pc, #100]	@ (802a30c <Vertical_Operatin_Main_Func_Right+0x10c>)
+ 802a2a6:	681b      	ldr	r3, [r3, #0]
+ 802a2a8:	3301      	adds	r3, #1
+ 802a2aa:	4a18      	ldr	r2, [pc, #96]	@ (802a30c <Vertical_Operatin_Main_Func_Right+0x10c>)
+ 802a2ac:	6013      	str	r3, [r2, #0]
+			Forward_Flag_Robot_Manual=1;
+ 802a2ae:	4b16      	ldr	r3, [pc, #88]	@ (802a308 <Vertical_Operatin_Main_Func_Right+0x108>)
+ 802a2b0:	2201      	movs	r2, #1
+ 802a2b2:	601a      	str	r2, [r3, #0]
+		Move_Vertical_Manual_Sub_Func_Backward();
+ 802a2b4:	f000 f888 	bl	802a3c8 <Move_Vertical_Manual_Sub_Func_Backward>
+		UltraStopReverse(Forward_Flag_Robot_Manual);
+ 802a2b8:	4b13      	ldr	r3, [pc, #76]	@ (802a308 <Vertical_Operatin_Main_Func_Right+0x108>)
+ 802a2ba:	681b      	ldr	r3, [r3, #0]
+ 802a2bc:	4618      	mov	r0, r3
+ 802a2be:	f7ff fafb 	bl	80298b8 <UltraStopReverse>
+		CRLU_Flag=0;
+ 802a2c2:	4b10      	ldr	r3, [pc, #64]	@ (802a304 <Vertical_Operatin_Main_Func_Right+0x104>)
+ 802a2c4:	2200      	movs	r2, #0
+ 802a2c6:	601a      	str	r2, [r3, #0]
+}
+ 802a2c8:	e016      	b.n	802a2f8 <Vertical_Operatin_Main_Func_Right+0xf8>
+		Vertical_Manual_Operation_Func();
+ 802a2ca:	f000 fce1 	bl	802ac90 <Vertical_Manual_Operation_Func>
+		CRLU_Flag=0;
+ 802a2ce:	4b0d      	ldr	r3, [pc, #52]	@ (802a304 <Vertical_Operatin_Main_Func_Right+0x104>)
+ 802a2d0:	2200      	movs	r2, #0
+ 802a2d2:	601a      	str	r2, [r3, #0]
+		Forward_Flag_Robot_Auto=1;
+ 802a2d4:	4b0a      	ldr	r3, [pc, #40]	@ (802a300 <Vertical_Operatin_Main_Func_Right+0x100>)
+ 802a2d6:	2201      	movs	r2, #1
+ 802a2d8:	601a      	str	r2, [r3, #0]
+		Robot_Platform_Back_Flag=0;
+ 802a2da:	4b0d      	ldr	r3, [pc, #52]	@ (802a310 <Vertical_Operatin_Main_Func_Right+0x110>)
+ 802a2dc:	2200      	movs	r2, #0
+ 802a2de:	601a      	str	r2, [r3, #0]
+		Robot_Main_Mode_Jude();
+ 802a2e0:	f004 f8d6 	bl	802e490 <Robot_Main_Mode_Jude>
+		Swing_Limit_Flag=0;
+ 802a2e4:	4b0b      	ldr	r3, [pc, #44]	@ (802a314 <Vertical_Operatin_Main_Func_Right+0x114>)
+ 802a2e6:	2200      	movs	r2, #0
+ 802a2e8:	601a      	str	r2, [r3, #0]
+		Forward_Flag_Robot_Manual_Count=0;
+ 802a2ea:	4b08      	ldr	r3, [pc, #32]	@ (802a30c <Vertical_Operatin_Main_Func_Right+0x10c>)
+ 802a2ec:	2200      	movs	r2, #0
+ 802a2ee:	601a      	str	r2, [r3, #0]
+		UltraStopReverse_Manually_Backward();
+ 802a2f0:	f7ff fb44 	bl	802997c <UltraStopReverse_Manually_Backward>
+		PushRod_Contronl();//推杆上下停止控制
+ 802a2f4:	f7ff fb4a 	bl	802998c <PushRod_Contronl>
+}
+ 802a2f8:	bf00      	nop
+ 802a2fa:	bd80      	pop	{r7, pc}
+ 802a2fc:	2400a3f8 	.word	0x2400a3f8
+ 802a300:	2400a798 	.word	0x2400a798
+ 802a304:	2400a9f0 	.word	0x2400a9f0
+ 802a308:	24000098 	.word	0x24000098
+ 802a30c:	2400a794 	.word	0x2400a794
+ 802a310:	2400a6f8 	.word	0x2400a6f8
+ 802a314:	2400a6f4 	.word	0x2400a6f4
+
+0802a318 <Move_Vertical_Manual_Sub_Func_Forward>:
+
+
+
+
+void Move_Vertical_Manual_Sub_Func_Forward()
+{
+ 802a318:	b580      	push	{r7, lr}
+ 802a31a:	b082      	sub	sp, #8
+ 802a31c:	af00      	add	r7, sp, #0
+	  switch (Forward_Flag_Robot_Manual)
+ 802a31e:	4b24      	ldr	r3, [pc, #144]	@ (802a3b0 <Move_Vertical_Manual_Sub_Func_Forward+0x98>)
+ 802a320:	681b      	ldr	r3, [r3, #0]
+ 802a322:	2b03      	cmp	r3, #3
+ 802a324:	d024      	beq.n	802a370 <Move_Vertical_Manual_Sub_Func_Forward+0x58>
+ 802a326:	2b03      	cmp	r3, #3
+ 802a328:	dc37      	bgt.n	802a39a <Move_Vertical_Manual_Sub_Func_Forward+0x82>
+ 802a32a:	2b01      	cmp	r3, #1
+ 802a32c:	d002      	beq.n	802a334 <Move_Vertical_Manual_Sub_Func_Forward+0x1c>
+ 802a32e:	2b02      	cmp	r3, #2
+ 802a330:	d008      	beq.n	802a344 <Move_Vertical_Manual_Sub_Func_Forward+0x2c>
+ 802a332:	e032      	b.n	802a39a <Move_Vertical_Manual_Sub_Func_Forward+0x82>
+	  {
+		  case Forward_Attitude_Judge:
+			  Vertical_Angle_Judge();
+ 802a334:	f001 ff14 	bl	802c160 <Vertical_Angle_Judge>
+			  Forward_Flag_Robot_Manual++;
+ 802a338:	4b1d      	ldr	r3, [pc, #116]	@ (802a3b0 <Move_Vertical_Manual_Sub_Func_Forward+0x98>)
+ 802a33a:	681b      	ldr	r3, [r3, #0]
+ 802a33c:	3301      	adds	r3, #1
+ 802a33e:	4a1c      	ldr	r2, [pc, #112]	@ (802a3b0 <Move_Vertical_Manual_Sub_Func_Forward+0x98>)
+ 802a340:	6013      	str	r3, [r2, #0]
+			  break;
+ 802a342:	e02d      	b.n	802a3a0 <Move_Vertical_Manual_Sub_Func_Forward+0x88>
+		  case Forward_Attitude_Adjust:
+			  Robot_Posture_Adjus_Gravity();
+ 802a344:	f001 fd74 	bl	802be30 <Robot_Posture_Adjus_Gravity>
+			  if(Angle_Error_LLL<Error_Cont_Thresh)
+ 802a348:	4b1a      	ldr	r3, [pc, #104]	@ (802a3b4 <Move_Vertical_Manual_Sub_Func_Forward+0x9c>)
+ 802a34a:	ed93 6b00 	vldr	d6, [r3]
+ 802a34e:	4b1a      	ldr	r3, [pc, #104]	@ (802a3b8 <Move_Vertical_Manual_Sub_Func_Forward+0xa0>)
+ 802a350:	ed93 7b00 	vldr	d7, [r3]
+ 802a354:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802a358:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802a35c:	d400      	bmi.n	802a360 <Move_Vertical_Manual_Sub_Func_Forward+0x48>
+			  {
+				Forward_Flag_Robot_Manual++;
+				Robot_Halt_Mode();
+			  }
+			  break;
+ 802a35e:	e01f      	b.n	802a3a0 <Move_Vertical_Manual_Sub_Func_Forward+0x88>
+				Forward_Flag_Robot_Manual++;
+ 802a360:	4b13      	ldr	r3, [pc, #76]	@ (802a3b0 <Move_Vertical_Manual_Sub_Func_Forward+0x98>)
+ 802a362:	681b      	ldr	r3, [r3, #0]
+ 802a364:	3301      	adds	r3, #1
+ 802a366:	4a12      	ldr	r2, [pc, #72]	@ (802a3b0 <Move_Vertical_Manual_Sub_Func_Forward+0x98>)
+ 802a368:	6013      	str	r3, [r2, #0]
+				Robot_Halt_Mode();
+ 802a36a:	f7ff fa89 	bl	8029880 <Robot_Halt_Mode>
+			  break;
+ 802a36e:	e017      	b.n	802a3a0 <Move_Vertical_Manual_Sub_Func_Forward+0x88>
+		  case Forward_Motion:
+//			  Move_Horizontal_Vertical_Task_Forwards_Do_Forwards();
+			  Vertical_Angle_Judge();
+ 802a370:	f001 fef6 	bl	802c160 <Vertical_Angle_Judge>
+			  double Robot_Speed_Base_Vertical_Up=Robot_Speed_Base/0.98;
+ 802a374:	4b11      	ldr	r3, [pc, #68]	@ (802a3bc <Move_Vertical_Manual_Sub_Func_Forward+0xa4>)
+ 802a376:	ed93 6b00 	vldr	d6, [r3]
+ 802a37a:	ed9f 5b0b 	vldr	d5, [pc, #44]	@ 802a3a8 <Move_Vertical_Manual_Sub_Func_Forward+0x90>
+ 802a37e:	ee86 7b05 	vdiv.f64	d7, d6, d5
+ 802a382:	ed87 7b00 	vstr	d7, [r7]
+			  Move_Horizontal_Vertical_Task_Forwards_Do_Forwards(Robot_Speed_Base_Vertical_Up, CV_Robot_Deri_Angle_Deg_Grity);
+ 802a386:	4b0e      	ldr	r3, [pc, #56]	@ (802a3c0 <Move_Vertical_Manual_Sub_Func_Forward+0xa8>)
+ 802a388:	ed93 7b00 	vldr	d7, [r3]
+ 802a38c:	eeb0 1b47 	vmov.f64	d1, d7
+ 802a390:	ed97 0b00 	vldr	d0, [r7]
+ 802a394:	f001 fc74 	bl	802bc80 <Move_Horizontal_Vertical_Task_Forwards_Do_Forwards>
+			  break;
+ 802a398:	e002      	b.n	802a3a0 <Move_Vertical_Manual_Sub_Func_Forward+0x88>
+		  default:
+			  HALT_State_Do();
+ 802a39a:	f005 fee5 	bl	8030168 <HALT_State_Do>
+			  break;
+ 802a39e:	bf00      	nop
+	  }
+
+}
+ 802a3a0:	bf00      	nop
+ 802a3a2:	3708      	adds	r7, #8
+ 802a3a4:	46bd      	mov	sp, r7
+ 802a3a6:	bd80      	pop	{r7, pc}
+ 802a3a8:	f5c28f5c 	.word	0xf5c28f5c
+ 802a3ac:	3fef5c28 	.word	0x3fef5c28
+ 802a3b0:	24000098 	.word	0x24000098
+ 802a3b4:	2400a9e8 	.word	0x2400a9e8
+ 802a3b8:	24000090 	.word	0x24000090
+ 802a3bc:	2400a758 	.word	0x2400a758
+ 802a3c0:	2400a6d0 	.word	0x2400a6d0
+ 802a3c4:	00000000 	.word	0x00000000
+
+0802a3c8 <Move_Vertical_Manual_Sub_Func_Backward>:
+void Move_Vertical_Manual_Sub_Func_Backward()
+{
+ 802a3c8:	b580      	push	{r7, lr}
+ 802a3ca:	b082      	sub	sp, #8
+ 802a3cc:	af00      	add	r7, sp, #0
+	  switch (Forward_Flag_Robot_Manual)
+ 802a3ce:	4b24      	ldr	r3, [pc, #144]	@ (802a460 <Move_Vertical_Manual_Sub_Func_Backward+0x98>)
+ 802a3d0:	681b      	ldr	r3, [r3, #0]
+ 802a3d2:	2b03      	cmp	r3, #3
+ 802a3d4:	d024      	beq.n	802a420 <Move_Vertical_Manual_Sub_Func_Backward+0x58>
+ 802a3d6:	2b03      	cmp	r3, #3
+ 802a3d8:	dc37      	bgt.n	802a44a <Move_Vertical_Manual_Sub_Func_Backward+0x82>
+ 802a3da:	2b01      	cmp	r3, #1
+ 802a3dc:	d002      	beq.n	802a3e4 <Move_Vertical_Manual_Sub_Func_Backward+0x1c>
+ 802a3de:	2b02      	cmp	r3, #2
+ 802a3e0:	d008      	beq.n	802a3f4 <Move_Vertical_Manual_Sub_Func_Backward+0x2c>
+ 802a3e2:	e032      	b.n	802a44a <Move_Vertical_Manual_Sub_Func_Backward+0x82>
+	  {
+		  case Forward_Attitude_Judge:
+
+			  Vertical_Angle_Judge();
+ 802a3e4:	f001 febc 	bl	802c160 <Vertical_Angle_Judge>
+			  Forward_Flag_Robot_Manual++;
+ 802a3e8:	4b1d      	ldr	r3, [pc, #116]	@ (802a460 <Move_Vertical_Manual_Sub_Func_Backward+0x98>)
+ 802a3ea:	681b      	ldr	r3, [r3, #0]
+ 802a3ec:	3301      	adds	r3, #1
+ 802a3ee:	4a1c      	ldr	r2, [pc, #112]	@ (802a460 <Move_Vertical_Manual_Sub_Func_Backward+0x98>)
+ 802a3f0:	6013      	str	r3, [r2, #0]
+			  break;
+ 802a3f2:	e02d      	b.n	802a450 <Move_Vertical_Manual_Sub_Func_Backward+0x88>
+		  case Forward_Attitude_Adjust:
+			  Robot_Posture_Adjus_Gravity();
+ 802a3f4:	f001 fd1c 	bl	802be30 <Robot_Posture_Adjus_Gravity>
+			  if(Angle_Error_LLL<Error_Cont_Thresh)
+ 802a3f8:	4b1a      	ldr	r3, [pc, #104]	@ (802a464 <Move_Vertical_Manual_Sub_Func_Backward+0x9c>)
+ 802a3fa:	ed93 6b00 	vldr	d6, [r3]
+ 802a3fe:	4b1a      	ldr	r3, [pc, #104]	@ (802a468 <Move_Vertical_Manual_Sub_Func_Backward+0xa0>)
+ 802a400:	ed93 7b00 	vldr	d7, [r3]
+ 802a404:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802a408:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802a40c:	d400      	bmi.n	802a410 <Move_Vertical_Manual_Sub_Func_Backward+0x48>
+			  {
+				Forward_Flag_Robot_Manual++;
+				Robot_Halt_Mode();
+			  }
+			  break;
+ 802a40e:	e01f      	b.n	802a450 <Move_Vertical_Manual_Sub_Func_Backward+0x88>
+				Forward_Flag_Robot_Manual++;
+ 802a410:	4b13      	ldr	r3, [pc, #76]	@ (802a460 <Move_Vertical_Manual_Sub_Func_Backward+0x98>)
+ 802a412:	681b      	ldr	r3, [r3, #0]
+ 802a414:	3301      	adds	r3, #1
+ 802a416:	4a12      	ldr	r2, [pc, #72]	@ (802a460 <Move_Vertical_Manual_Sub_Func_Backward+0x98>)
+ 802a418:	6013      	str	r3, [r2, #0]
+				Robot_Halt_Mode();
+ 802a41a:	f7ff fa31 	bl	8029880 <Robot_Halt_Mode>
+			  break;
+ 802a41e:	e017      	b.n	802a450 <Move_Vertical_Manual_Sub_Func_Backward+0x88>
+		  case Forward_Motion:
+			  Vertical_Angle_Judge();
+ 802a420:	f001 fe9e 	bl	802c160 <Vertical_Angle_Judge>
+			  double Robot_Speed_Base_Vertical_Down=Robot_Speed_Base/1.05;
+ 802a424:	4b11      	ldr	r3, [pc, #68]	@ (802a46c <Move_Vertical_Manual_Sub_Func_Backward+0xa4>)
+ 802a426:	ed93 6b00 	vldr	d6, [r3]
+ 802a42a:	ed9f 5b0b 	vldr	d5, [pc, #44]	@ 802a458 <Move_Vertical_Manual_Sub_Func_Backward+0x90>
+ 802a42e:	ee86 7b05 	vdiv.f64	d7, d6, d5
+ 802a432:	ed87 7b00 	vstr	d7, [r7]
+			  Move_Horizontal_Vertical_Task_Backwards_Do_Backward(Robot_Speed_Base_Vertical_Down,CV_Robot_Deri_Angle_Deg_Grity);
+ 802a436:	4b0e      	ldr	r3, [pc, #56]	@ (802a470 <Move_Vertical_Manual_Sub_Func_Backward+0xa8>)
+ 802a438:	ed93 7b00 	vldr	d7, [r3]
+ 802a43c:	eeb0 1b47 	vmov.f64	d1, d7
+ 802a440:	ed97 0b00 	vldr	d0, [r7]
+ 802a444:	f002 fab4 	bl	802c9b0 <Move_Horizontal_Vertical_Task_Backwards_Do_Backward>
+			  break;
+ 802a448:	e002      	b.n	802a450 <Move_Vertical_Manual_Sub_Func_Backward+0x88>
+		  default:
+			  HALT_State_Do();
+ 802a44a:	f005 fe8d 	bl	8030168 <HALT_State_Do>
+			  break;
+ 802a44e:	bf00      	nop
+	  }
+//	  UltraStopReverse(Forward_Flag_Robot_Manual);
+}
+ 802a450:	bf00      	nop
+ 802a452:	3708      	adds	r7, #8
+ 802a454:	46bd      	mov	sp, r7
+ 802a456:	bd80      	pop	{r7, pc}
+ 802a458:	cccccccd 	.word	0xcccccccd
+ 802a45c:	3ff0cccc 	.word	0x3ff0cccc
+ 802a460:	24000098 	.word	0x24000098
+ 802a464:	2400a9e8 	.word	0x2400a9e8
+ 802a468:	24000090 	.word	0x24000090
+ 802a46c:	2400a758 	.word	0x2400a758
+ 802a470:	2400a6d0 	.word	0x2400a6d0
+
+0802a474 <Move_Vertical_Auto_Sub_Func>:
+
+void Move_Vertical_Auto_Sub_Func()
+{
+ 802a474:	b580      	push	{r7, lr}
+ 802a476:	af00      	add	r7, sp, #0
+	  switch (Forward_Flag_Robot_Auto)
+ 802a478:	4b2e      	ldr	r3, [pc, #184]	@ (802a534 <Move_Vertical_Auto_Sub_Func+0xc0>)
+ 802a47a:	681b      	ldr	r3, [r3, #0]
+ 802a47c:	3b01      	subs	r3, #1
+ 802a47e:	2b05      	cmp	r3, #5
+ 802a480:	d852      	bhi.n	802a528 <Move_Vertical_Auto_Sub_Func+0xb4>
+ 802a482:	a201      	add	r2, pc, #4	@ (adr r2, 802a488 <Move_Vertical_Auto_Sub_Func+0x14>)
+ 802a484:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 802a488:	0802a4a1 	.word	0x0802a4a1
+ 802a48c:	0802a4b1 	.word	0x0802a4b1
+ 802a490:	0802a4e3 	.word	0x0802a4e3
+ 802a494:	0802a4ef 	.word	0x0802a4ef
+ 802a498:	0802a515 	.word	0x0802a515
+ 802a49c:	0802a51f 	.word	0x0802a51f
+	  {
+		  case Forward_Attitude_Judge:
+//			  Vertical_Angle_Judge();
+			  Vertical_Angle_Judge_Uptata_1();
+ 802a4a0:	f001 fe8e 	bl	802c1c0 <Vertical_Angle_Judge_Uptata_1>
+			  Forward_Flag_Robot_Auto++;
+ 802a4a4:	4b23      	ldr	r3, [pc, #140]	@ (802a534 <Move_Vertical_Auto_Sub_Func+0xc0>)
+ 802a4a6:	681b      	ldr	r3, [r3, #0]
+ 802a4a8:	3301      	adds	r3, #1
+ 802a4aa:	4a22      	ldr	r2, [pc, #136]	@ (802a534 <Move_Vertical_Auto_Sub_Func+0xc0>)
+ 802a4ac:	6013      	str	r3, [r2, #0]
+			  break;
+ 802a4ae:	e03e      	b.n	802a52e <Move_Vertical_Auto_Sub_Func+0xba>
+		  case Forward_Attitude_Adjust:
+			  Robot_Posture_Adjus_Gravity();
+ 802a4b0:	f001 fcbe 	bl	802be30 <Robot_Posture_Adjus_Gravity>
+			  if(Angle_Error_LLL<Error_Cont_Thresh)
+ 802a4b4:	4b20      	ldr	r3, [pc, #128]	@ (802a538 <Move_Vertical_Auto_Sub_Func+0xc4>)
+ 802a4b6:	ed93 6b00 	vldr	d6, [r3]
+ 802a4ba:	4b20      	ldr	r3, [pc, #128]	@ (802a53c <Move_Vertical_Auto_Sub_Func+0xc8>)
+ 802a4bc:	ed93 7b00 	vldr	d7, [r3]
+ 802a4c0:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802a4c4:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802a4c8:	d504      	bpl.n	802a4d4 <Move_Vertical_Auto_Sub_Func+0x60>
+			  {
+				Forward_Flag_Robot_Auto++;
+ 802a4ca:	4b1a      	ldr	r3, [pc, #104]	@ (802a534 <Move_Vertical_Auto_Sub_Func+0xc0>)
+ 802a4cc:	681b      	ldr	r3, [r3, #0]
+ 802a4ce:	3301      	adds	r3, #1
+ 802a4d0:	4a18      	ldr	r2, [pc, #96]	@ (802a534 <Move_Vertical_Auto_Sub_Func+0xc0>)
+ 802a4d2:	6013      	str	r3, [r2, #0]
+//				Robot_Halt_Mode();
+			  }
+			  Robot_Platform_Back_Flag=0;
+ 802a4d4:	4b1a      	ldr	r3, [pc, #104]	@ (802a540 <Move_Vertical_Auto_Sub_Func+0xcc>)
+ 802a4d6:	2200      	movs	r2, #0
+ 802a4d8:	601a      	str	r2, [r3, #0]
+			  Swing_Limit_Flag=0;
+ 802a4da:	4b1a      	ldr	r3, [pc, #104]	@ (802a544 <Move_Vertical_Auto_Sub_Func+0xd0>)
+ 802a4dc:	2200      	movs	r2, #0
+ 802a4de:	601a      	str	r2, [r3, #0]
+			  break;
+ 802a4e0:	e025      	b.n	802a52e <Move_Vertical_Auto_Sub_Func+0xba>
+		  case Forward_Motion:
+			  Forward_Flag_Robot_Auto++;
+ 802a4e2:	4b14      	ldr	r3, [pc, #80]	@ (802a534 <Move_Vertical_Auto_Sub_Func+0xc0>)
+ 802a4e4:	681b      	ldr	r3, [r3, #0]
+ 802a4e6:	3301      	adds	r3, #1
+ 802a4e8:	4a12      	ldr	r2, [pc, #72]	@ (802a534 <Move_Vertical_Auto_Sub_Func+0xc0>)
+ 802a4ea:	6013      	str	r3, [r2, #0]
+			  break;
+ 802a4ec:	e01f      	b.n	802a52e <Move_Vertical_Auto_Sub_Func+0xba>
+		  case Work_Way:
+			  if(GV_Robot_backMode==1)
+ 802a4ee:	4b16      	ldr	r3, [pc, #88]	@ (802a548 <Move_Vertical_Auto_Sub_Func+0xd4>)
+ 802a4f0:	681b      	ldr	r3, [r3, #0]
+ 802a4f2:	2b01      	cmp	r3, #1
+ 802a4f4:	d103      	bne.n	802a4fe <Move_Vertical_Auto_Sub_Func+0x8a>
+			  {
+				  Forward_Flag_Robot_Auto=Fight_Alternately;
+ 802a4f6:	4b0f      	ldr	r3, [pc, #60]	@ (802a534 <Move_Vertical_Auto_Sub_Func+0xc0>)
+ 802a4f8:	2205      	movs	r2, #5
+ 802a4fa:	601a      	str	r2, [r3, #0]
+ 802a4fc:	e006      	b.n	802a50c <Move_Vertical_Auto_Sub_Func+0x98>
+			  }
+			  else if(GV_Robot_backMode==2)
+ 802a4fe:	4b12      	ldr	r3, [pc, #72]	@ (802a548 <Move_Vertical_Auto_Sub_Func+0xd4>)
+ 802a500:	681b      	ldr	r3, [r3, #0]
+ 802a502:	2b02      	cmp	r3, #2
+ 802a504:	d102      	bne.n	802a50c <Move_Vertical_Auto_Sub_Func+0x98>
+			  {
+				  Forward_Flag_Robot_Auto=Fight_retreating;
+ 802a506:	4b0b      	ldr	r3, [pc, #44]	@ (802a534 <Move_Vertical_Auto_Sub_Func+0xc0>)
+ 802a508:	2206      	movs	r2, #6
+ 802a50a:	601a      	str	r2, [r3, #0]
+			  }
+			  Robot_Platform_Back_Flag=0;
+ 802a50c:	4b0c      	ldr	r3, [pc, #48]	@ (802a540 <Move_Vertical_Auto_Sub_Func+0xcc>)
+ 802a50e:	2200      	movs	r2, #0
+ 802a510:	601a      	str	r2, [r3, #0]
+			  break;
+ 802a512:	e00c      	b.n	802a52e <Move_Vertical_Auto_Sub_Func+0xba>
+		  case Fight_Alternately:
+			  Vertical_Angle_Judge();
+ 802a514:	f001 fe24 	bl	802c160 <Vertical_Angle_Judge>
+			  Fight_Alternately_Function_Vertical();
+ 802a518:	f003 f878 	bl	802d60c <Fight_Alternately_Function_Vertical>
+			  break;
+ 802a51c:	e007      	b.n	802a52e <Move_Vertical_Auto_Sub_Func+0xba>
+		  case Fight_retreating:
+			  Vertical_Angle_Judge();
+ 802a51e:	f001 fe1f 	bl	802c160 <Vertical_Angle_Judge>
+			  Fight_Countinus_Function_Horizontal();
+ 802a522:	f003 f85d 	bl	802d5e0 <Fight_Countinus_Function_Horizontal>
+			  break;
+ 802a526:	e002      	b.n	802a52e <Move_Vertical_Auto_Sub_Func+0xba>
+
+		  default:
+			  HALT_State_Do();
+ 802a528:	f005 fe1e 	bl	8030168 <HALT_State_Do>
+			  break;
+ 802a52c:	bf00      	nop
+	  }
+
+}
+ 802a52e:	bf00      	nop
+ 802a530:	bd80      	pop	{r7, pc}
+ 802a532:	bf00      	nop
+ 802a534:	2400a798 	.word	0x2400a798
+ 802a538:	2400a9e8 	.word	0x2400a9e8
+ 802a53c:	24000090 	.word	0x24000090
+ 802a540:	2400a6f8 	.word	0x2400a6f8
+ 802a544:	2400a6f4 	.word	0x2400a6f4
+ 802a548:	2400a720 	.word	0x2400a720
+
+0802a54c <Plane_Operatin_Main_Func>:
+			  HALT_State_Do();
+			  break;
+	  }
+}
+void Plane_Operatin_Main_Func()
+{
+ 802a54c:	b580      	push	{r7, lr}
+ 802a54e:	af00      	add	r7, sp, #0
+	//PushRod_Contronl();//推杆上下停止控制
+	Blast_Machine_Control_Fun();
+ 802a550:	f7fb ff2c 	bl	80263ac <Blast_Machine_Control_Fun>
+
+	if(P_MK32->CH4_SA==-1000)//换道
+ 802a554:	4b2d      	ldr	r3, [pc, #180]	@ (802a60c <Plane_Operatin_Main_Func+0xc0>)
+ 802a556:	681b      	ldr	r3, [r3, #0]
+ 802a558:	695b      	ldr	r3, [r3, #20]
+ 802a55a:	f513 7f7a 	cmn.w	r3, #1000	@ 0x3e8
+ 802a55e:	d10a      	bne.n	802a576 <Plane_Operatin_Main_Func+0x2a>
+	{
+		Swing_Limit_Contrl();//摆臂限位控制
+ 802a560:	f003 f87a 	bl	802d658 <Swing_Limit_Contrl>
+		Forward_Flag_Robot_Auto=1;
+ 802a564:	4b2a      	ldr	r3, [pc, #168]	@ (802a610 <Plane_Operatin_Main_Func+0xc4>)
+ 802a566:	2201      	movs	r2, #1
+ 802a568:	601a      	str	r2, [r3, #0]
+//		Change_Road_Plane();
+		Change_Road_Plane_Continuous_FanDi_Left();
+ 802a56a:	f001 ff91 	bl	802c490 <Change_Road_Plane_Continuous_FanDi_Left>
+		Region_Task_Falg=0;
+ 802a56e:	4b29      	ldr	r3, [pc, #164]	@ (802a614 <Plane_Operatin_Main_Func+0xc8>)
+ 802a570:	2200      	movs	r2, #0
+ 802a572:	601a      	str	r2, [r3, #0]
+		Forward_Flag_Robot_Auto=1;
+		CRLU_Flag=0;
+		Robot_Main_Mode_Jude();
+		UltraStopReverse_Manually_Backward();
+	}
+}
+ 802a574:	e047      	b.n	802a606 <Plane_Operatin_Main_Func+0xba>
+	else if(P_MK32->CH4_SA==1000)//边打边换道//与边打边退速度相同；
+ 802a576:	4b25      	ldr	r3, [pc, #148]	@ (802a60c <Plane_Operatin_Main_Func+0xc0>)
+ 802a578:	681b      	ldr	r3, [r3, #0]
+ 802a57a:	695b      	ldr	r3, [r3, #20]
+ 802a57c:	f5b3 7f7a 	cmp.w	r3, #1000	@ 0x3e8
+ 802a580:	d10a      	bne.n	802a598 <Plane_Operatin_Main_Func+0x4c>
+		Swing_Limit_Contrl();//摆臂限位控制
+ 802a582:	f003 f869 	bl	802d658 <Swing_Limit_Contrl>
+		Forward_Flag_Robot_Auto=1;
+ 802a586:	4b22      	ldr	r3, [pc, #136]	@ (802a610 <Plane_Operatin_Main_Func+0xc4>)
+ 802a588:	2201      	movs	r2, #1
+ 802a58a:	601a      	str	r2, [r3, #0]
+		Change_Road_Plane_Continuous_FanDi_Right();
+ 802a58c:	f002 f8a4 	bl	802c6d8 <Change_Road_Plane_Continuous_FanDi_Right>
+		Region_Task_Falg=0;
+ 802a590:	4b20      	ldr	r3, [pc, #128]	@ (802a614 <Plane_Operatin_Main_Func+0xc8>)
+ 802a592:	2200      	movs	r2, #0
+ 802a594:	601a      	str	r2, [r3, #0]
+}
+ 802a596:	e036      	b.n	802a606 <Plane_Operatin_Main_Func+0xba>
+	else if(P_MK32->CH7_SD==-1000)//自动行驶
+ 802a598:	4b1c      	ldr	r3, [pc, #112]	@ (802a60c <Plane_Operatin_Main_Func+0xc0>)
+ 802a59a:	681b      	ldr	r3, [r3, #0]
+ 802a59c:	6a1b      	ldr	r3, [r3, #32]
+ 802a59e:	f513 7f7a 	cmn.w	r3, #1000	@ 0x3e8
+ 802a5a2:	d10d      	bne.n	802a5c0 <Plane_Operatin_Main_Func+0x74>
+		Move_Plane_Auto_Sub_Func();
+ 802a5a4:	f000 f83c 	bl	802a620 <Move_Plane_Auto_Sub_Func>
+		UltraStopReverse(Forward_Flag_Robot_Auto);
+ 802a5a8:	4b19      	ldr	r3, [pc, #100]	@ (802a610 <Plane_Operatin_Main_Func+0xc4>)
+ 802a5aa:	681b      	ldr	r3, [r3, #0]
+ 802a5ac:	4618      	mov	r0, r3
+ 802a5ae:	f7ff f983 	bl	80298b8 <UltraStopReverse>
+		CRLU_Flag=0;
+ 802a5b2:	4b19      	ldr	r3, [pc, #100]	@ (802a618 <Plane_Operatin_Main_Func+0xcc>)
+ 802a5b4:	2200      	movs	r2, #0
+ 802a5b6:	601a      	str	r2, [r3, #0]
+		Region_Task_Falg=0;
+ 802a5b8:	4b16      	ldr	r3, [pc, #88]	@ (802a614 <Plane_Operatin_Main_Func+0xc8>)
+ 802a5ba:	2200      	movs	r2, #0
+ 802a5bc:	601a      	str	r2, [r3, #0]
+}
+ 802a5be:	e022      	b.n	802a606 <Plane_Operatin_Main_Func+0xba>
+	else if(P_MK32->CH5_SB==-1000)//前进巡航
+ 802a5c0:	4b12      	ldr	r3, [pc, #72]	@ (802a60c <Plane_Operatin_Main_Func+0xc0>)
+ 802a5c2:	681b      	ldr	r3, [r3, #0]
+ 802a5c4:	699b      	ldr	r3, [r3, #24]
+ 802a5c6:	f513 7f7a 	cmn.w	r3, #1000	@ 0x3e8
+ 802a5ca:	d102      	bne.n	802a5d2 <Plane_Operatin_Main_Func+0x86>
+		Move_Plane_Manual_Sub_Func_Fordwards();
+ 802a5cc:	f000 fdb2 	bl	802b134 <Move_Plane_Manual_Sub_Func_Fordwards>
+}
+ 802a5d0:	e019      	b.n	802a606 <Plane_Operatin_Main_Func+0xba>
+	else if(P_MK32->CH5_SB==1000)//后退巡航
+ 802a5d2:	4b0e      	ldr	r3, [pc, #56]	@ (802a60c <Plane_Operatin_Main_Func+0xc0>)
+ 802a5d4:	681b      	ldr	r3, [r3, #0]
+ 802a5d6:	699b      	ldr	r3, [r3, #24]
+ 802a5d8:	f5b3 7f7a 	cmp.w	r3, #1000	@ 0x3e8
+ 802a5dc:	d107      	bne.n	802a5ee <Plane_Operatin_Main_Func+0xa2>
+		Move_Plane_Manual_Sub_Func_Backwards();
+ 802a5de:	f000 fddd 	bl	802b19c <Move_Plane_Manual_Sub_Func_Backwards>
+		UltraStopReverse(Forward_Flag_Robot_Manual);
+ 802a5e2:	4b0e      	ldr	r3, [pc, #56]	@ (802a61c <Plane_Operatin_Main_Func+0xd0>)
+ 802a5e4:	681b      	ldr	r3, [r3, #0]
+ 802a5e6:	4618      	mov	r0, r3
+ 802a5e8:	f7ff f966 	bl	80298b8 <UltraStopReverse>
+}
+ 802a5ec:	e00b      	b.n	802a606 <Plane_Operatin_Main_Func+0xba>
+		Plane_Manual_Operation_Func();
+ 802a5ee:	f000 fc7b 	bl	802aee8 <Plane_Manual_Operation_Func>
+		Forward_Flag_Robot_Auto=1;
+ 802a5f2:	4b07      	ldr	r3, [pc, #28]	@ (802a610 <Plane_Operatin_Main_Func+0xc4>)
+ 802a5f4:	2201      	movs	r2, #1
+ 802a5f6:	601a      	str	r2, [r3, #0]
+		CRLU_Flag=0;
+ 802a5f8:	4b07      	ldr	r3, [pc, #28]	@ (802a618 <Plane_Operatin_Main_Func+0xcc>)
+ 802a5fa:	2200      	movs	r2, #0
+ 802a5fc:	601a      	str	r2, [r3, #0]
+		Robot_Main_Mode_Jude();
+ 802a5fe:	f003 ff47 	bl	802e490 <Robot_Main_Mode_Jude>
+		UltraStopReverse_Manually_Backward();
+ 802a602:	f7ff f9bb 	bl	802997c <UltraStopReverse_Manually_Backward>
+}
+ 802a606:	bf00      	nop
+ 802a608:	bd80      	pop	{r7, pc}
+ 802a60a:	bf00      	nop
+ 802a60c:	2400a3f8 	.word	0x2400a3f8
+ 802a610:	2400a798 	.word	0x2400a798
+ 802a614:	2400a6c4 	.word	0x2400a6c4
+ 802a618:	2400a9f0 	.word	0x2400a9f0
+ 802a61c:	24000098 	.word	0x24000098
+
+0802a620 <Move_Plane_Auto_Sub_Func>:
+
+void Move_Plane_Auto_Sub_Func()
+{
+ 802a620:	b580      	push	{r7, lr}
+ 802a622:	af00      	add	r7, sp, #0
+	  switch (Forward_Flag_Robot_Auto)
+ 802a624:	4b26      	ldr	r3, [pc, #152]	@ (802a6c0 <Move_Plane_Auto_Sub_Func+0xa0>)
+ 802a626:	681b      	ldr	r3, [r3, #0]
+ 802a628:	3b01      	subs	r3, #1
+ 802a62a:	2b05      	cmp	r3, #5
+ 802a62c:	d841      	bhi.n	802a6b2 <Move_Plane_Auto_Sub_Func+0x92>
+ 802a62e:	a201      	add	r2, pc, #4	@ (adr r2, 802a634 <Move_Plane_Auto_Sub_Func+0x14>)
+ 802a630:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 802a634:	0802a64d 	.word	0x0802a64d
+ 802a638:	0802a65d 	.word	0x0802a65d
+ 802a63c:	0802a67b 	.word	0x0802a67b
+ 802a640:	0802a687 	.word	0x0802a687
+ 802a644:	0802a6a7 	.word	0x0802a6a7
+ 802a648:	0802a6ad 	.word	0x0802a6ad
+	  {
+		  case Forward_Attitude_Judge:
+
+			  Plane_Angle_Judge();
+ 802a64c:	f000 f842 	bl	802a6d4 <Plane_Angle_Judge>
+			  Forward_Flag_Robot_Auto++;
+ 802a650:	4b1b      	ldr	r3, [pc, #108]	@ (802a6c0 <Move_Plane_Auto_Sub_Func+0xa0>)
+ 802a652:	681b      	ldr	r3, [r3, #0]
+ 802a654:	3301      	adds	r3, #1
+ 802a656:	4a1a      	ldr	r2, [pc, #104]	@ (802a6c0 <Move_Plane_Auto_Sub_Func+0xa0>)
+ 802a658:	6013      	str	r3, [r2, #0]
+			  break;
+ 802a65a:	e02e      	b.n	802a6ba <Move_Plane_Auto_Sub_Func+0x9a>
+		  case Forward_Attitude_Adjust:
+			  Forward_Flag_Robot_Auto++;
+ 802a65c:	4b18      	ldr	r3, [pc, #96]	@ (802a6c0 <Move_Plane_Auto_Sub_Func+0xa0>)
+ 802a65e:	681b      	ldr	r3, [r3, #0]
+ 802a660:	3301      	adds	r3, #1
+ 802a662:	4a17      	ldr	r2, [pc, #92]	@ (802a6c0 <Move_Plane_Auto_Sub_Func+0xa0>)
+ 802a664:	6013      	str	r3, [r2, #0]
+			  Auto_Job_Back_Time_MS_Count=0;
+ 802a666:	4b17      	ldr	r3, [pc, #92]	@ (802a6c4 <Move_Plane_Auto_Sub_Func+0xa4>)
+ 802a668:	2200      	movs	r2, #0
+ 802a66a:	601a      	str	r2, [r3, #0]
+			  Robot_Platform_Back_Flag=0;
+ 802a66c:	4b16      	ldr	r3, [pc, #88]	@ (802a6c8 <Move_Plane_Auto_Sub_Func+0xa8>)
+ 802a66e:	2200      	movs	r2, #0
+ 802a670:	601a      	str	r2, [r3, #0]
+			  Swing_Limit_Flag=0;
+ 802a672:	4b16      	ldr	r3, [pc, #88]	@ (802a6cc <Move_Plane_Auto_Sub_Func+0xac>)
+ 802a674:	2200      	movs	r2, #0
+ 802a676:	601a      	str	r2, [r3, #0]
+			  break;
+ 802a678:	e01f      	b.n	802a6ba <Move_Plane_Auto_Sub_Func+0x9a>
+		  case Forward_Motion:
+			 // Move_Plane_Task_Backwards_Do();
+			  Forward_Flag_Robot_Auto++;//默认模式为打一道退一次
+ 802a67a:	4b11      	ldr	r3, [pc, #68]	@ (802a6c0 <Move_Plane_Auto_Sub_Func+0xa0>)
+ 802a67c:	681b      	ldr	r3, [r3, #0]
+ 802a67e:	3301      	adds	r3, #1
+ 802a680:	4a0f      	ldr	r2, [pc, #60]	@ (802a6c0 <Move_Plane_Auto_Sub_Func+0xa0>)
+ 802a682:	6013      	str	r3, [r2, #0]
+			  break;
+ 802a684:	e019      	b.n	802a6ba <Move_Plane_Auto_Sub_Func+0x9a>
+		  case Work_Way:
+			  if(GV_Robot_backMode==1)
+ 802a686:	4b12      	ldr	r3, [pc, #72]	@ (802a6d0 <Move_Plane_Auto_Sub_Func+0xb0>)
+ 802a688:	681b      	ldr	r3, [r3, #0]
+ 802a68a:	2b01      	cmp	r3, #1
+ 802a68c:	d103      	bne.n	802a696 <Move_Plane_Auto_Sub_Func+0x76>
+			  {
+				  Forward_Flag_Robot_Auto=Fight_Alternately;
+ 802a68e:	4b0c      	ldr	r3, [pc, #48]	@ (802a6c0 <Move_Plane_Auto_Sub_Func+0xa0>)
+ 802a690:	2205      	movs	r2, #5
+ 802a692:	601a      	str	r2, [r3, #0]
+			  }
+			  else if(GV_Robot_backMode==2)
+			  {
+				  Forward_Flag_Robot_Auto=Fight_retreating;
+			  }
+			  break;
+ 802a694:	e010      	b.n	802a6b8 <Move_Plane_Auto_Sub_Func+0x98>
+			  else if(GV_Robot_backMode==2)
+ 802a696:	4b0e      	ldr	r3, [pc, #56]	@ (802a6d0 <Move_Plane_Auto_Sub_Func+0xb0>)
+ 802a698:	681b      	ldr	r3, [r3, #0]
+ 802a69a:	2b02      	cmp	r3, #2
+ 802a69c:	d10c      	bne.n	802a6b8 <Move_Plane_Auto_Sub_Func+0x98>
+				  Forward_Flag_Robot_Auto=Fight_retreating;
+ 802a69e:	4b08      	ldr	r3, [pc, #32]	@ (802a6c0 <Move_Plane_Auto_Sub_Func+0xa0>)
+ 802a6a0:	2206      	movs	r2, #6
+ 802a6a2:	601a      	str	r2, [r3, #0]
+			  break;
+ 802a6a4:	e008      	b.n	802a6b8 <Move_Plane_Auto_Sub_Func+0x98>
+		  case Fight_Alternately:
+			  Fight_Alternately_Function_Plane();
+ 802a6a6:	f002 ffb9 	bl	802d61c <Fight_Alternately_Function_Plane>
+			  break;
+ 802a6aa:	e006      	b.n	802a6ba <Move_Plane_Auto_Sub_Func+0x9a>
+		  case Fight_retreating:
+			  Fight_Countinus_Function_Plane();
+ 802a6ac:	f002 ffbe 	bl	802d62c <Fight_Countinus_Function_Plane>
+			  break;
+ 802a6b0:	e003      	b.n	802a6ba <Move_Plane_Auto_Sub_Func+0x9a>
+		  default:
+			  HALT_State_Do();
+ 802a6b2:	f005 fd59 	bl	8030168 <HALT_State_Do>
+			  break;
+ 802a6b6:	e000      	b.n	802a6ba <Move_Plane_Auto_Sub_Func+0x9a>
+			  break;
+ 802a6b8:	bf00      	nop
+	  }
+
+}
+ 802a6ba:	bf00      	nop
+ 802a6bc:	bd80      	pop	{r7, pc}
+ 802a6be:	bf00      	nop
+ 802a6c0:	2400a798 	.word	0x2400a798
+ 802a6c4:	2400a6fc 	.word	0x2400a6fc
+ 802a6c8:	2400a6f8 	.word	0x2400a6f8
+ 802a6cc:	2400a6f4 	.word	0x2400a6f4
+ 802a6d0:	2400a720 	.word	0x2400a720
+
+0802a6d4 <Plane_Angle_Judge>:
+
+void Plane_Angle_Judge()
+{
+ 802a6d4:	b480      	push	{r7}
+ 802a6d6:	af00      	add	r7, sp, #0
+	CV_Robot_Deri_Angle_Deg_Plane=MF40G_Angle_Add_Deg;
+ 802a6d8:	4b05      	ldr	r3, [pc, #20]	@ (802a6f0 <Plane_Angle_Judge+0x1c>)
+ 802a6da:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802a6de:	4905      	ldr	r1, [pc, #20]	@ (802a6f4 <Plane_Angle_Judge+0x20>)
+ 802a6e0:	e9c1 2300 	strd	r2, r3, [r1]
+}
+ 802a6e4:	bf00      	nop
+ 802a6e6:	46bd      	mov	sp, r7
+ 802a6e8:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 802a6ec:	4770      	bx	lr
+ 802a6ee:	bf00      	nop
+ 802a6f0:	2400a788 	.word	0x2400a788
+ 802a6f4:	2400a6d8 	.word	0x2400a6d8
+
+0802a6f8 <Region_Automated_Task_Func_Alternately_Plane>:
+double X_Deri_Angle[2];       //输入给机器人的期望角度
+int Backward_Count_X;   //X向后退时间
+double Backward_Num_X_Total;   //X向后退总次数
+double Lane_Change_Num_Total_Y; //Y向后退次数；
+void Region_Automated_Task_Func_Alternately_Plane()
+{
+ 802a6f8:	b580      	push	{r7, lr}
+ 802a6fa:	b082      	sub	sp, #8
+ 802a6fc:	af00      	add	r7, sp, #0
+	  switch (Region_Task_Falg)
+ 802a6fe:	4ba0      	ldr	r3, [pc, #640]	@ (802a980 <Region_Automated_Task_Func_Alternately_Plane+0x288>)
+ 802a700:	681b      	ldr	r3, [r3, #0]
+ 802a702:	2b05      	cmp	r3, #5
+ 802a704:	f200 8129 	bhi.w	802a95a <Region_Automated_Task_Func_Alternately_Plane+0x262>
+ 802a708:	a201      	add	r2, pc, #4	@ (adr r2, 802a710 <Region_Automated_Task_Func_Alternately_Plane+0x18>)
+ 802a70a:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 802a70e:	bf00      	nop
+ 802a710:	0802a729 	.word	0x0802a729
+ 802a714:	0802a7d3 	.word	0x0802a7d3
+ 802a718:	0802a895 	.word	0x0802a895
+ 802a71c:	0802a8d7 	.word	0x0802a8d7
+ 802a720:	0802a90f 	.word	0x0802a90f
+ 802a724:	0802a943 	.word	0x0802a943
+	  {
+		  case Parameter_Calculation:
+			  Deri_Angle_Deg_X[0]=MF40G_Angle_Add_Deg;
+ 802a728:	4b96      	ldr	r3, [pc, #600]	@ (802a984 <Region_Automated_Task_Func_Alternately_Plane+0x28c>)
+ 802a72a:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802a72e:	4996      	ldr	r1, [pc, #600]	@ (802a988 <Region_Automated_Task_Func_Alternately_Plane+0x290>)
+ 802a730:	e9c1 2300 	strd	r2, r3, [r1]
+			  Plane_Turn_Angle_Deg=MF40G_Angle_Add_Deg+90;
+ 802a734:	4b93      	ldr	r3, [pc, #588]	@ (802a984 <Region_Automated_Task_Func_Alternately_Plane+0x28c>)
+ 802a736:	ed93 7b00 	vldr	d7, [r3]
+ 802a73a:	ed9f 6b8b 	vldr	d6, [pc, #556]	@ 802a968 <Region_Automated_Task_Func_Alternately_Plane+0x270>
+ 802a73e:	ee37 7b06 	vadd.f64	d7, d7, d6
+ 802a742:	4b92      	ldr	r3, [pc, #584]	@ (802a98c <Region_Automated_Task_Func_Alternately_Plane+0x294>)
+ 802a744:	ed83 7b00 	vstr	d7, [r3]
+			  Deri_Angle_Deg_X[1]=Deri_Angle_Deg_X[0]+180;
+ 802a748:	4b8f      	ldr	r3, [pc, #572]	@ (802a988 <Region_Automated_Task_Func_Alternately_Plane+0x290>)
+ 802a74a:	ed93 7b00 	vldr	d7, [r3]
+ 802a74e:	ed9f 6b88 	vldr	d6, [pc, #544]	@ 802a970 <Region_Automated_Task_Func_Alternately_Plane+0x278>
+ 802a752:	ee37 7b06 	vadd.f64	d7, d7, d6
+ 802a756:	4b8c      	ldr	r3, [pc, #560]	@ (802a988 <Region_Automated_Task_Func_Alternately_Plane+0x290>)
+ 802a758:	ed83 7b02 	vstr	d7, [r3, #8]
+			  if(Deri_Angle_Deg_X[1]>180)
+ 802a75c:	4b8a      	ldr	r3, [pc, #552]	@ (802a988 <Region_Automated_Task_Func_Alternately_Plane+0x290>)
+ 802a75e:	ed93 7b02 	vldr	d7, [r3, #8]
+ 802a762:	ed9f 6b83 	vldr	d6, [pc, #524]	@ 802a970 <Region_Automated_Task_Func_Alternately_Plane+0x278>
+ 802a766:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 802a76a:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802a76e:	dd09      	ble.n	802a784 <Region_Automated_Task_Func_Alternately_Plane+0x8c>
+			  {
+				  Deri_Angle_Deg_X[1]=Deri_Angle_Deg_X[1]-360;
+ 802a770:	4b85      	ldr	r3, [pc, #532]	@ (802a988 <Region_Automated_Task_Func_Alternately_Plane+0x290>)
+ 802a772:	ed93 7b02 	vldr	d7, [r3, #8]
+ 802a776:	ed9f 6b80 	vldr	d6, [pc, #512]	@ 802a978 <Region_Automated_Task_Func_Alternately_Plane+0x280>
+ 802a77a:	ee37 7b46 	vsub.f64	d7, d7, d6
+ 802a77e:	4b82      	ldr	r3, [pc, #520]	@ (802a988 <Region_Automated_Task_Func_Alternately_Plane+0x290>)
+ 802a780:	ed83 7b02 	vstr	d7, [r3, #8]
+			  }
+			  Plane_X_Backward_Time_Calculation(&Backward_Num_X_Total);
+ 802a784:	4882      	ldr	r0, [pc, #520]	@ (802a990 <Region_Automated_Task_Func_Alternately_Plane+0x298>)
+ 802a786:	f000 fd3f 	bl	802b208 <Plane_X_Backward_Time_Calculation>
+			  Plane_Change_Road_Backward_Num_Calculation(&Lane_Change_Num_Total_Y);
+ 802a78a:	4882      	ldr	r0, [pc, #520]	@ (802a994 <Region_Automated_Task_Func_Alternately_Plane+0x29c>)
+ 802a78c:	f000 fe28 	bl	802b3e0 <Plane_Change_Road_Backward_Num_Calculation>
+			  Plane_Y_Lane_Change_Time_Calculation(&Plane_Complete_Total_XY);
+ 802a790:	4881      	ldr	r0, [pc, #516]	@ (802a998 <Region_Automated_Task_Func_Alternately_Plane+0x2a0>)
+ 802a792:	f000 fde1 	bl	802b358 <Plane_Y_Lane_Change_Time_Calculation>
+			  Region_Task_Falg++;
+ 802a796:	4b7a      	ldr	r3, [pc, #488]	@ (802a980 <Region_Automated_Task_Func_Alternately_Plane+0x288>)
+ 802a798:	681b      	ldr	r3, [r3, #0]
+ 802a79a:	3301      	adds	r3, #1
+ 802a79c:	4a78      	ldr	r2, [pc, #480]	@ (802a980 <Region_Automated_Task_Func_Alternately_Plane+0x288>)
+ 802a79e:	6013      	str	r3, [r2, #0]
+			  Backward_Count_X=0;
+ 802a7a0:	4b7e      	ldr	r3, [pc, #504]	@ (802a99c <Region_Automated_Task_Func_Alternately_Plane+0x2a4>)
+ 802a7a2:	2200      	movs	r2, #0
+ 802a7a4:	601a      	str	r2, [r3, #0]
+
+			  X_Deri_Angle[0]=Deri_Angle_Deg_X[0];
+ 802a7a6:	4b78      	ldr	r3, [pc, #480]	@ (802a988 <Region_Automated_Task_Func_Alternately_Plane+0x290>)
+ 802a7a8:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802a7ac:	497c      	ldr	r1, [pc, #496]	@ (802a9a0 <Region_Automated_Task_Func_Alternately_Plane+0x2a8>)
+ 802a7ae:	e9c1 2300 	strd	r2, r3, [r1]
+			  Swing_Limit_Flag=0;
+ 802a7b2:	4b7c      	ldr	r3, [pc, #496]	@ (802a9a4 <Region_Automated_Task_Func_Alternately_Plane+0x2ac>)
+ 802a7b4:	2200      	movs	r2, #0
+ 802a7b6:	601a      	str	r2, [r3, #0]
+			  Backward_Num_X_Count=0;
+ 802a7b8:	4b7b      	ldr	r3, [pc, #492]	@ (802a9a8 <Region_Automated_Task_Func_Alternately_Plane+0x2b0>)
+ 802a7ba:	2200      	movs	r2, #0
+ 802a7bc:	601a      	str	r2, [r3, #0]
+			  Plane_Complete_Count=0;
+ 802a7be:	4b7b      	ldr	r3, [pc, #492]	@ (802a9ac <Region_Automated_Task_Func_Alternately_Plane+0x2b4>)
+ 802a7c0:	2200      	movs	r2, #0
+ 802a7c2:	601a      	str	r2, [r3, #0]
+			  Robot_Platform_Back_Flag=0;
+ 802a7c4:	4b7a      	ldr	r3, [pc, #488]	@ (802a9b0 <Region_Automated_Task_Func_Alternately_Plane+0x2b8>)
+ 802a7c6:	2200      	movs	r2, #0
+ 802a7c8:	601a      	str	r2, [r3, #0]
+			  Auto_Job_Back_Time_MS_Count=0;
+ 802a7ca:	4b7a      	ldr	r3, [pc, #488]	@ (802a9b4 <Region_Automated_Task_Func_Alternately_Plane+0x2bc>)
+ 802a7cc:	2200      	movs	r2, #0
+ 802a7ce:	601a      	str	r2, [r3, #0]
+			  break;
+ 802a7d0:	e0c6      	b.n	802a960 <Region_Automated_Task_Func_Alternately_Plane+0x268>
+		  case Backward_Task_X:
+			  	CV_Robot_Deri_Angle_Deg_Plane=X_Deri_Angle[0];
+ 802a7d2:	4b73      	ldr	r3, [pc, #460]	@ (802a9a0 <Region_Automated_Task_Func_Alternately_Plane+0x2a8>)
+ 802a7d4:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802a7d8:	4977      	ldr	r1, [pc, #476]	@ (802a9b8 <Region_Automated_Task_Func_Alternately_Plane+0x2c0>)
+ 802a7da:	e9c1 2300 	strd	r2, r3, [r1]
+				Swing_Limit_Contrl();//摆臂限位控制
+ 802a7de:	f002 ff3b 	bl	802d658 <Swing_Limit_Contrl>
+				Robot_Platform_Back_Contronl_Plane();
+ 802a7e2:	f003 fb31 	bl	802de48 <Robot_Platform_Back_Contronl_Plane>
+				if(Backward_Num_X_Count>=Backward_Num_X_Total)
+ 802a7e6:	4b70      	ldr	r3, [pc, #448]	@ (802a9a8 <Region_Automated_Task_Func_Alternately_Plane+0x2b0>)
+ 802a7e8:	681b      	ldr	r3, [r3, #0]
+ 802a7ea:	ee07 3a90 	vmov	s15, r3
+ 802a7ee:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802a7f2:	4b67      	ldr	r3, [pc, #412]	@ (802a990 <Region_Automated_Task_Func_Alternately_Plane+0x298>)
+ 802a7f4:	ed93 7b00 	vldr	d7, [r3]
+ 802a7f8:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802a7fc:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802a800:	db44      	blt.n	802a88c <Region_Automated_Task_Func_Alternately_Plane+0x194>
+				{
+					Auto_Job_Back_Time_MS_Count=0;
+ 802a802:	4b6c      	ldr	r3, [pc, #432]	@ (802a9b4 <Region_Automated_Task_Func_Alternately_Plane+0x2bc>)
+ 802a804:	2200      	movs	r2, #0
+ 802a806:	601a      	str	r2, [r3, #0]
+					Robot_Platform_Back_Flag=0;
+ 802a808:	4b69      	ldr	r3, [pc, #420]	@ (802a9b0 <Region_Automated_Task_Func_Alternately_Plane+0x2b8>)
+ 802a80a:	2200      	movs	r2, #0
+ 802a80c:	601a      	str	r2, [r3, #0]
+					Region_Task_Falg++;
+ 802a80e:	4b5c      	ldr	r3, [pc, #368]	@ (802a980 <Region_Automated_Task_Func_Alternately_Plane+0x288>)
+ 802a810:	681b      	ldr	r3, [r3, #0]
+ 802a812:	3301      	adds	r3, #1
+ 802a814:	4a5a      	ldr	r2, [pc, #360]	@ (802a980 <Region_Automated_Task_Func_Alternately_Plane+0x288>)
+ 802a816:	6013      	str	r3, [r2, #0]
+					Plane_Complete_Count++;
+ 802a818:	4b64      	ldr	r3, [pc, #400]	@ (802a9ac <Region_Automated_Task_Func_Alternately_Plane+0x2b4>)
+ 802a81a:	681b      	ldr	r3, [r3, #0]
+ 802a81c:	3301      	adds	r3, #1
+ 802a81e:	4a63      	ldr	r2, [pc, #396]	@ (802a9ac <Region_Automated_Task_Func_Alternately_Plane+0x2b4>)
+ 802a820:	6013      	str	r3, [r2, #0]
+					int i=0;
+ 802a822:	2300      	movs	r3, #0
+ 802a824:	607b      	str	r3, [r7, #4]
+					i=Plane_Complete_Count%2;
+ 802a826:	4b61      	ldr	r3, [pc, #388]	@ (802a9ac <Region_Automated_Task_Func_Alternately_Plane+0x2b4>)
+ 802a828:	681b      	ldr	r3, [r3, #0]
+ 802a82a:	2b00      	cmp	r3, #0
+ 802a82c:	f003 0301 	and.w	r3, r3, #1
+ 802a830:	bfb8      	it	lt
+ 802a832:	425b      	neglt	r3, r3
+ 802a834:	607b      	str	r3, [r7, #4]
+					if(i==0)
+ 802a836:	687b      	ldr	r3, [r7, #4]
+ 802a838:	2b00      	cmp	r3, #0
+ 802a83a:	d10c      	bne.n	802a856 <Region_Automated_Task_Func_Alternately_Plane+0x15e>
+					{
+						X_Deri_Angle[0]=Deri_Angle_Deg_X[0];
+ 802a83c:	4b52      	ldr	r3, [pc, #328]	@ (802a988 <Region_Automated_Task_Func_Alternately_Plane+0x290>)
+ 802a83e:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802a842:	4957      	ldr	r1, [pc, #348]	@ (802a9a0 <Region_Automated_Task_Func_Alternately_Plane+0x2a8>)
+ 802a844:	e9c1 2300 	strd	r2, r3, [r1]
+						X_Deri_Angle[1]=Deri_Angle_Deg_X[1];
+ 802a848:	4b4f      	ldr	r3, [pc, #316]	@ (802a988 <Region_Automated_Task_Func_Alternately_Plane+0x290>)
+ 802a84a:	e9d3 2302 	ldrd	r2, r3, [r3, #8]
+ 802a84e:	4954      	ldr	r1, [pc, #336]	@ (802a9a0 <Region_Automated_Task_Func_Alternately_Plane+0x2a8>)
+ 802a850:	e9c1 2302 	strd	r2, r3, [r1, #8]
+ 802a854:	e00b      	b.n	802a86e <Region_Automated_Task_Func_Alternately_Plane+0x176>
+					}
+					else
+					{
+						X_Deri_Angle[0]=Deri_Angle_Deg_X[1];
+ 802a856:	4b4c      	ldr	r3, [pc, #304]	@ (802a988 <Region_Automated_Task_Func_Alternately_Plane+0x290>)
+ 802a858:	e9d3 2302 	ldrd	r2, r3, [r3, #8]
+ 802a85c:	4950      	ldr	r1, [pc, #320]	@ (802a9a0 <Region_Automated_Task_Func_Alternately_Plane+0x2a8>)
+ 802a85e:	e9c1 2300 	strd	r2, r3, [r1]
+						X_Deri_Angle[1]=Deri_Angle_Deg_X[0];
+ 802a862:	4b49      	ldr	r3, [pc, #292]	@ (802a988 <Region_Automated_Task_Func_Alternately_Plane+0x290>)
+ 802a864:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802a868:	494d      	ldr	r1, [pc, #308]	@ (802a9a0 <Region_Automated_Task_Func_Alternately_Plane+0x2a8>)
+ 802a86a:	e9c1 2302 	strd	r2, r3, [r1, #8]
+					}
+					if(Plane_Complete_Count>=Plane_Complete_Total_XY)
+ 802a86e:	4b4f      	ldr	r3, [pc, #316]	@ (802a9ac <Region_Automated_Task_Func_Alternately_Plane+0x2b4>)
+ 802a870:	681a      	ldr	r2, [r3, #0]
+ 802a872:	4b49      	ldr	r3, [pc, #292]	@ (802a998 <Region_Automated_Task_Func_Alternately_Plane+0x2a0>)
+ 802a874:	681b      	ldr	r3, [r3, #0]
+ 802a876:	429a      	cmp	r2, r3
+ 802a878:	db05      	blt.n	802a886 <Region_Automated_Task_Func_Alternately_Plane+0x18e>
+					{
+						ctl_flag_1 = 1;
+ 802a87a:	4b50      	ldr	r3, [pc, #320]	@ (802a9bc <Region_Automated_Task_Func_Alternately_Plane+0x2c4>)
+ 802a87c:	2201      	movs	r2, #1
+ 802a87e:	601a      	str	r2, [r3, #0]
+						Region_Task_Falg=Region_Auto_Close;
+ 802a880:	4b3f      	ldr	r3, [pc, #252]	@ (802a980 <Region_Automated_Task_Func_Alternately_Plane+0x288>)
+ 802a882:	2205      	movs	r2, #5
+ 802a884:	601a      	str	r2, [r3, #0]
+					}
+					Backward_Num_X_Count=0;
+ 802a886:	4b48      	ldr	r3, [pc, #288]	@ (802a9a8 <Region_Automated_Task_Func_Alternately_Plane+0x2b0>)
+ 802a888:	2200      	movs	r2, #0
+ 802a88a:	601a      	str	r2, [r3, #0]
+				}
+				Robot_Platform_Back_Flag_Y=0;
+ 802a88c:	4b4c      	ldr	r3, [pc, #304]	@ (802a9c0 <Region_Automated_Task_Func_Alternately_Plane+0x2c8>)
+ 802a88e:	2200      	movs	r2, #0
+ 802a890:	601a      	str	r2, [r3, #0]
+			  break;
+ 802a892:	e065      	b.n	802a960 <Region_Automated_Task_Func_Alternately_Plane+0x268>
+
+		  case Turn_To_Y:
+			  	Swing_Limit_Contrl();//摆臂限位控制
+ 802a894:	f002 fee0 	bl	802d658 <Swing_Limit_Contrl>
+				CV_Robot_Deri_Angle_Deg_Plane=Plane_Turn_Angle_Deg;
+ 802a898:	4b3c      	ldr	r3, [pc, #240]	@ (802a98c <Region_Automated_Task_Func_Alternately_Plane+0x294>)
+ 802a89a:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802a89e:	4946      	ldr	r1, [pc, #280]	@ (802a9b8 <Region_Automated_Task_Func_Alternately_Plane+0x2c0>)
+ 802a8a0:	e9c1 2300 	strd	r2, r3, [r1]
+				Robot_Posture_Adjus_Plane();
+ 802a8a4:	f001 fb94 	bl	802bfd0 <Robot_Posture_Adjus_Plane>
+				if(Angle_Error_LLL<Error_Cont_Thresh)
+ 802a8a8:	4b46      	ldr	r3, [pc, #280]	@ (802a9c4 <Region_Automated_Task_Func_Alternately_Plane+0x2cc>)
+ 802a8aa:	ed93 6b00 	vldr	d6, [r3]
+ 802a8ae:	4b46      	ldr	r3, [pc, #280]	@ (802a9c8 <Region_Automated_Task_Func_Alternately_Plane+0x2d0>)
+ 802a8b0:	ed93 7b00 	vldr	d7, [r3]
+ 802a8b4:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802a8b8:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802a8bc:	d504      	bpl.n	802a8c8 <Region_Automated_Task_Func_Alternately_Plane+0x1d0>
+				{
+					Region_Task_Falg++;
+ 802a8be:	4b30      	ldr	r3, [pc, #192]	@ (802a980 <Region_Automated_Task_Func_Alternately_Plane+0x288>)
+ 802a8c0:	681b      	ldr	r3, [r3, #0]
+ 802a8c2:	3301      	adds	r3, #1
+ 802a8c4:	4a2e      	ldr	r2, [pc, #184]	@ (802a980 <Region_Automated_Task_Func_Alternately_Plane+0x288>)
+ 802a8c6:	6013      	str	r3, [r2, #0]
+				}
+				Auto_Job_Back_Time_MS_Count=0;
+ 802a8c8:	4b3a      	ldr	r3, [pc, #232]	@ (802a9b4 <Region_Automated_Task_Func_Alternately_Plane+0x2bc>)
+ 802a8ca:	2200      	movs	r2, #0
+ 802a8cc:	601a      	str	r2, [r3, #0]
+				Robot_Platform_Back_Flag=0;
+ 802a8ce:	4b38      	ldr	r3, [pc, #224]	@ (802a9b0 <Region_Automated_Task_Func_Alternately_Plane+0x2b8>)
+ 802a8d0:	2200      	movs	r2, #0
+ 802a8d2:	601a      	str	r2, [r3, #0]
+
+			  break;
+ 802a8d4:	e044      	b.n	802a960 <Region_Automated_Task_Func_Alternately_Plane+0x268>
+		  case Lane_Change_Y:
+			  Swing_Limit_Contrl();//摆臂限位控制
+ 802a8d6:	f002 febf 	bl	802d658 <Swing_Limit_Contrl>
+//			  Platform_Back_Para_Compute_Plane();
+			  Robot_Platform_Back_Contronl_Plane();
+ 802a8da:	f003 fab5 	bl	802de48 <Robot_Platform_Back_Contronl_Plane>
+			  if(Backward_Num_X_Count>=Lane_Change_Num_Total_Y)
+ 802a8de:	4b32      	ldr	r3, [pc, #200]	@ (802a9a8 <Region_Automated_Task_Func_Alternately_Plane+0x2b0>)
+ 802a8e0:	681b      	ldr	r3, [r3, #0]
+ 802a8e2:	ee07 3a90 	vmov	s15, r3
+ 802a8e6:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802a8ea:	4b2a      	ldr	r3, [pc, #168]	@ (802a994 <Region_Automated_Task_Func_Alternately_Plane+0x29c>)
+ 802a8ec:	ed93 7b00 	vldr	d7, [r3]
+ 802a8f0:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802a8f4:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802a8f8:	da00      	bge.n	802a8fc <Region_Automated_Task_Func_Alternately_Plane+0x204>
+			  {
+				  Region_Task_Falg++;
+				  Backward_Num_X_Count=0;
+			  }
+			  break;
+ 802a8fa:	e031      	b.n	802a960 <Region_Automated_Task_Func_Alternately_Plane+0x268>
+				  Region_Task_Falg++;
+ 802a8fc:	4b20      	ldr	r3, [pc, #128]	@ (802a980 <Region_Automated_Task_Func_Alternately_Plane+0x288>)
+ 802a8fe:	681b      	ldr	r3, [r3, #0]
+ 802a900:	3301      	adds	r3, #1
+ 802a902:	4a1f      	ldr	r2, [pc, #124]	@ (802a980 <Region_Automated_Task_Func_Alternately_Plane+0x288>)
+ 802a904:	6013      	str	r3, [r2, #0]
+				  Backward_Num_X_Count=0;
+ 802a906:	4b28      	ldr	r3, [pc, #160]	@ (802a9a8 <Region_Automated_Task_Func_Alternately_Plane+0x2b0>)
+ 802a908:	2200      	movs	r2, #0
+ 802a90a:	601a      	str	r2, [r3, #0]
+			  break;
+ 802a90c:	e028      	b.n	802a960 <Region_Automated_Task_Func_Alternately_Plane+0x268>
+		  case Turn_Back_X:
+			  CV_Robot_Deri_Angle_Deg_Plane=X_Deri_Angle[0];
+ 802a90e:	4b24      	ldr	r3, [pc, #144]	@ (802a9a0 <Region_Automated_Task_Func_Alternately_Plane+0x2a8>)
+ 802a910:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802a914:	4928      	ldr	r1, [pc, #160]	@ (802a9b8 <Region_Automated_Task_Func_Alternately_Plane+0x2c0>)
+ 802a916:	e9c1 2300 	strd	r2, r3, [r1]
+			  Swing_Limit_Contrl();
+ 802a91a:	f002 fe9d 	bl	802d658 <Swing_Limit_Contrl>
+			  Robot_Posture_Adjus_Plane();
+ 802a91e:	f001 fb57 	bl	802bfd0 <Robot_Posture_Adjus_Plane>
+			  if(Angle_Error_LLL<Error_Cont_Thresh)
+ 802a922:	4b28      	ldr	r3, [pc, #160]	@ (802a9c4 <Region_Automated_Task_Func_Alternately_Plane+0x2cc>)
+ 802a924:	ed93 6b00 	vldr	d6, [r3]
+ 802a928:	4b27      	ldr	r3, [pc, #156]	@ (802a9c8 <Region_Automated_Task_Func_Alternately_Plane+0x2d0>)
+ 802a92a:	ed93 7b00 	vldr	d7, [r3]
+ 802a92e:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802a932:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802a936:	d400      	bmi.n	802a93a <Region_Automated_Task_Func_Alternately_Plane+0x242>
+			  {
+				Region_Task_Falg=1;
+			  }
+			  break;
+ 802a938:	e012      	b.n	802a960 <Region_Automated_Task_Func_Alternately_Plane+0x268>
+				Region_Task_Falg=1;
+ 802a93a:	4b11      	ldr	r3, [pc, #68]	@ (802a980 <Region_Automated_Task_Func_Alternately_Plane+0x288>)
+ 802a93c:	2201      	movs	r2, #1
+ 802a93e:	601a      	str	r2, [r3, #0]
+			  break;
+ 802a940:	e00e      	b.n	802a960 <Region_Automated_Task_Func_Alternately_Plane+0x268>
+		  case Region_Auto_Close:
+			  HALT_State_Do();
+ 802a942:	f005 fc11 	bl	8030168 <HALT_State_Do>
+//			  Blast_Machine_Close();//hjb
+			  Blast_Machine_Close_Fun();//hjb
+ 802a946:	f7fb fe3b 	bl	80265c0 <Blast_Machine_Close_Fun>
+			  Plane_Complete_Count=0;
+ 802a94a:	4b18      	ldr	r3, [pc, #96]	@ (802a9ac <Region_Automated_Task_Func_Alternately_Plane+0x2b4>)
+ 802a94c:	2200      	movs	r2, #0
+ 802a94e:	601a      	str	r2, [r3, #0]
+			  GV.SwingMotor.Target_Velcity =0;
+ 802a950:	4b1e      	ldr	r3, [pc, #120]	@ (802a9cc <Region_Automated_Task_Func_Alternately_Plane+0x2d4>)
+ 802a952:	2200      	movs	r2, #0
+ 802a954:	f8c3 2178 	str.w	r2, [r3, #376]	@ 0x178
+			  break;
+ 802a958:	e002      	b.n	802a960 <Region_Automated_Task_Func_Alternately_Plane+0x268>
+		  default:
+			  HALT_State_Do();
+ 802a95a:	f005 fc05 	bl	8030168 <HALT_State_Do>
+			  break;
+ 802a95e:	bf00      	nop
+	  }
+}
+ 802a960:	bf00      	nop
+ 802a962:	3708      	adds	r7, #8
+ 802a964:	46bd      	mov	sp, r7
+ 802a966:	bd80      	pop	{r7, pc}
+ 802a968:	00000000 	.word	0x00000000
+ 802a96c:	40568000 	.word	0x40568000
+ 802a970:	00000000 	.word	0x00000000
+ 802a974:	40668000 	.word	0x40668000
+ 802a978:	00000000 	.word	0x00000000
+ 802a97c:	40768000 	.word	0x40768000
+ 802a980:	2400a6c4 	.word	0x2400a6c4
+ 802a984:	2400a788 	.word	0x2400a788
+ 802a988:	2400a7b0 	.word	0x2400a7b0
+ 802a98c:	2400a7a8 	.word	0x2400a7a8
+ 802a990:	2400a7d8 	.word	0x2400a7d8
+ 802a994:	2400a7e0 	.word	0x2400a7e0
+ 802a998:	2400a7a0 	.word	0x2400a7a0
+ 802a99c:	2400a7d0 	.word	0x2400a7d0
+ 802a9a0:	2400a7c0 	.word	0x2400a7c0
+ 802a9a4:	2400a6f4 	.word	0x2400a6f4
+ 802a9a8:	2400a79c 	.word	0x2400a79c
+ 802a9ac:	2400a7a4 	.word	0x2400a7a4
+ 802a9b0:	2400a6f8 	.word	0x2400a6f8
+ 802a9b4:	2400a6fc 	.word	0x2400a6fc
+ 802a9b8:	2400a6d8 	.word	0x2400a6d8
+ 802a9bc:	2400a774 	.word	0x2400a774
+ 802a9c0:	2400a6e0 	.word	0x2400a6e0
+ 802a9c4:	2400a9e8 	.word	0x2400a9e8
+ 802a9c8:	24000090 	.word	0x24000090
+ 802a9cc:	24000340 	.word	0x24000340
+
+0802a9d0 <Region_Automated_Task_Func_Alternately_Horizontal>:
+double Horizontal_Turn_Angle_Deg;
+int Horizontal_Complete_Total_XY=0;
+///水平区域自动作业，水平区域自动作业
+
+void Region_Automated_Task_Func_Alternately_Horizontal()
+{
+ 802a9d0:	b580      	push	{r7, lr}
+ 802a9d2:	b082      	sub	sp, #8
+ 802a9d4:	af00      	add	r7, sp, #0
+	  switch (Region_Task_Falg)
+ 802a9d6:	4b9c      	ldr	r3, [pc, #624]	@ (802ac48 <Region_Automated_Task_Func_Alternately_Horizontal+0x278>)
+ 802a9d8:	681b      	ldr	r3, [r3, #0]
+ 802a9da:	2b06      	cmp	r3, #6
+ 802a9dc:	f200 812c 	bhi.w	802ac38 <Region_Automated_Task_Func_Alternately_Horizontal+0x268>
+ 802a9e0:	a201      	add	r2, pc, #4	@ (adr r2, 802a9e8 <Region_Automated_Task_Func_Alternately_Horizontal+0x18>)
+ 802a9e2:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 802a9e6:	bf00      	nop
+ 802a9e8:	0802aa05 	.word	0x0802aa05
+ 802a9ec:	0802aa6f 	.word	0x0802aa6f
+ 802a9f0:	0802aaaf 	.word	0x0802aaaf
+ 802a9f4:	0802ab6d 	.word	0x0802ab6d
+ 802a9f8:	0802abb5 	.word	0x0802abb5
+ 802a9fc:	0802abed 	.word	0x0802abed
+ 802aa00:	0802ac21 	.word	0x0802ac21
+	  {
+		  case Parameter_Calculation:
+			  Horiz_Angle_Judge();
+ 802aa04:	f000 fe20 	bl	802b648 <Horiz_Angle_Judge>
+			  Deri_Angle_Deg_X[0]=CV_Robot_Deri_Angle_Deg_Grity;
+ 802aa08:	4b90      	ldr	r3, [pc, #576]	@ (802ac4c <Region_Automated_Task_Func_Alternately_Horizontal+0x27c>)
+ 802aa0a:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802aa0e:	4990      	ldr	r1, [pc, #576]	@ (802ac50 <Region_Automated_Task_Func_Alternately_Horizontal+0x280>)
+ 802aa10:	e9c1 2300 	strd	r2, r3, [r1]
+			  Horiz_Angle_Judge_Region();
+ 802aa14:	f001 f8a4 	bl	802bb60 <Horiz_Angle_Judge_Region>
+			  Horizontal_Turn_Angle_Deg=0;
+ 802aa18:	498e      	ldr	r1, [pc, #568]	@ (802ac54 <Region_Automated_Task_Func_Alternately_Horizontal+0x284>)
+ 802aa1a:	f04f 0200 	mov.w	r2, #0
+ 802aa1e:	f04f 0300 	mov.w	r3, #0
+ 802aa22:	e9c1 2300 	strd	r2, r3, [r1]
+
+			  Horizontal_X_Backward_Num_Calculation(&Backward_Num_X_Total);
+ 802aa26:	488c      	ldr	r0, [pc, #560]	@ (802ac58 <Region_Automated_Task_Func_Alternately_Horizontal+0x288>)
+ 802aa28:	f000 fc42 	bl	802b2b0 <Horizontal_X_Backward_Num_Calculation>
+			  Horizontal_Change_Road_Backward_Num_Calculation(&Lane_Change_Num_Total_Y);
+ 802aa2c:	488b      	ldr	r0, [pc, #556]	@ (802ac5c <Region_Automated_Task_Func_Alternately_Horizontal+0x28c>)
+ 802aa2e:	f000 fd27 	bl	802b480 <Horizontal_Change_Road_Backward_Num_Calculation>
+			  Horizontal_Y_Lane_Change_Time_Calculation(&Horizontal_Complete_Total_XY);
+ 802aa32:	488b      	ldr	r0, [pc, #556]	@ (802ac60 <Region_Automated_Task_Func_Alternately_Horizontal+0x290>)
+ 802aa34:	f000 fcb2 	bl	802b39c <Horizontal_Y_Lane_Change_Time_Calculation>
+			  Region_Task_Falg++;
+ 802aa38:	4b83      	ldr	r3, [pc, #524]	@ (802ac48 <Region_Automated_Task_Func_Alternately_Horizontal+0x278>)
+ 802aa3a:	681b      	ldr	r3, [r3, #0]
+ 802aa3c:	3301      	adds	r3, #1
+ 802aa3e:	4a82      	ldr	r2, [pc, #520]	@ (802ac48 <Region_Automated_Task_Func_Alternately_Horizontal+0x278>)
+ 802aa40:	6013      	str	r3, [r2, #0]
+
+			  X_Deri_Angle[0]=Deri_Angle_Deg_X[0];
+ 802aa42:	4b83      	ldr	r3, [pc, #524]	@ (802ac50 <Region_Automated_Task_Func_Alternately_Horizontal+0x280>)
+ 802aa44:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802aa48:	4986      	ldr	r1, [pc, #536]	@ (802ac64 <Region_Automated_Task_Func_Alternately_Horizontal+0x294>)
+ 802aa4a:	e9c1 2300 	strd	r2, r3, [r1]
+			  Swing_Limit_Flag=0;
+ 802aa4e:	4b86      	ldr	r3, [pc, #536]	@ (802ac68 <Region_Automated_Task_Func_Alternately_Horizontal+0x298>)
+ 802aa50:	2200      	movs	r2, #0
+ 802aa52:	601a      	str	r2, [r3, #0]
+			  Backward_Num_X_Count=0;
+ 802aa54:	4b85      	ldr	r3, [pc, #532]	@ (802ac6c <Region_Automated_Task_Func_Alternately_Horizontal+0x29c>)
+ 802aa56:	2200      	movs	r2, #0
+ 802aa58:	601a      	str	r2, [r3, #0]
+			  Plane_Complete_Count=0;
+ 802aa5a:	4b85      	ldr	r3, [pc, #532]	@ (802ac70 <Region_Automated_Task_Func_Alternately_Horizontal+0x2a0>)
+ 802aa5c:	2200      	movs	r2, #0
+ 802aa5e:	601a      	str	r2, [r3, #0]
+			  Robot_Platform_Back_Flag=0;
+ 802aa60:	4b84      	ldr	r3, [pc, #528]	@ (802ac74 <Region_Automated_Task_Func_Alternately_Horizontal+0x2a4>)
+ 802aa62:	2200      	movs	r2, #0
+ 802aa64:	601a      	str	r2, [r3, #0]
+			  Auto_Job_Back_Time_MS_Count=0;
+ 802aa66:	4b84      	ldr	r3, [pc, #528]	@ (802ac78 <Region_Automated_Task_Func_Alternately_Horizontal+0x2a8>)
+ 802aa68:	2200      	movs	r2, #0
+ 802aa6a:	601a      	str	r2, [r3, #0]
+			  break;
+ 802aa6c:	e0e7      	b.n	802ac3e <Region_Automated_Task_Func_Alternately_Horizontal+0x26e>
+		  case RE_Horizontal_Turn_To_Desire_Angle:
+			  CV_Robot_Deri_Angle_Deg_Grity=X_Deri_Angle[0];
+ 802aa6e:	4b7d      	ldr	r3, [pc, #500]	@ (802ac64 <Region_Automated_Task_Func_Alternately_Horizontal+0x294>)
+ 802aa70:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802aa74:	4975      	ldr	r1, [pc, #468]	@ (802ac4c <Region_Automated_Task_Func_Alternately_Horizontal+0x27c>)
+ 802aa76:	e9c1 2300 	strd	r2, r3, [r1]
+			  Robot_Posture_Adjus_Gravity();
+ 802aa7a:	f001 f9d9 	bl	802be30 <Robot_Posture_Adjus_Gravity>
+			  if(Angle_Error_LLL<Error_Cont_Thresh)
+ 802aa7e:	4b7f      	ldr	r3, [pc, #508]	@ (802ac7c <Region_Automated_Task_Func_Alternately_Horizontal+0x2ac>)
+ 802aa80:	ed93 6b00 	vldr	d6, [r3]
+ 802aa84:	4b7e      	ldr	r3, [pc, #504]	@ (802ac80 <Region_Automated_Task_Func_Alternately_Horizontal+0x2b0>)
+ 802aa86:	ed93 7b00 	vldr	d7, [r3]
+ 802aa8a:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802aa8e:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802aa92:	d400      	bmi.n	802aa96 <Region_Automated_Task_Func_Alternately_Horizontal+0xc6>
+				Region_Task_Falg++;
+				Auto_Job_Back_Time_MS_Count=0;
+				Robot_Platform_Back_Flag=0;
+
+			  }
+			  break;
+ 802aa94:	e0d3      	b.n	802ac3e <Region_Automated_Task_Func_Alternately_Horizontal+0x26e>
+				Region_Task_Falg++;
+ 802aa96:	4b6c      	ldr	r3, [pc, #432]	@ (802ac48 <Region_Automated_Task_Func_Alternately_Horizontal+0x278>)
+ 802aa98:	681b      	ldr	r3, [r3, #0]
+ 802aa9a:	3301      	adds	r3, #1
+ 802aa9c:	4a6a      	ldr	r2, [pc, #424]	@ (802ac48 <Region_Automated_Task_Func_Alternately_Horizontal+0x278>)
+ 802aa9e:	6013      	str	r3, [r2, #0]
+				Auto_Job_Back_Time_MS_Count=0;
+ 802aaa0:	4b75      	ldr	r3, [pc, #468]	@ (802ac78 <Region_Automated_Task_Func_Alternately_Horizontal+0x2a8>)
+ 802aaa2:	2200      	movs	r2, #0
+ 802aaa4:	601a      	str	r2, [r3, #0]
+				Robot_Platform_Back_Flag=0;
+ 802aaa6:	4b73      	ldr	r3, [pc, #460]	@ (802ac74 <Region_Automated_Task_Func_Alternately_Horizontal+0x2a4>)
+ 802aaa8:	2200      	movs	r2, #0
+ 802aaaa:	601a      	str	r2, [r3, #0]
+			  break;
+ 802aaac:	e0c7      	b.n	802ac3e <Region_Automated_Task_Func_Alternately_Horizontal+0x26e>
+		  case RE_Horizontal_Backward_Task_X:
+
+			  Horiz_Angle_Judge();
+ 802aaae:	f000 fdcb 	bl	802b648 <Horiz_Angle_Judge>
+			  Horiz_Angle_Judge_Region();
+ 802aab2:	f001 f855 	bl	802bb60 <Horiz_Angle_Judge_Region>
+			  Swing_Limit_Contrl();//摆臂限位控制
+ 802aab6:	f002 fdcf 	bl	802d658 <Swing_Limit_Contrl>
+
+			  Robot_Platform_Back_Contronl_Horizontal();
+ 802aaba:	f002 ffe1 	bl	802da80 <Robot_Platform_Back_Contronl_Horizontal>
+				if(Backward_Num_X_Count>=Backward_Num_X_Total)
+ 802aabe:	4b6b      	ldr	r3, [pc, #428]	@ (802ac6c <Region_Automated_Task_Func_Alternately_Horizontal+0x29c>)
+ 802aac0:	681b      	ldr	r3, [r3, #0]
+ 802aac2:	ee07 3a90 	vmov	s15, r3
+ 802aac6:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802aaca:	4b63      	ldr	r3, [pc, #396]	@ (802ac58 <Region_Automated_Task_Func_Alternately_Horizontal+0x288>)
+ 802aacc:	ed93 7b00 	vldr	d7, [r3]
+ 802aad0:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802aad4:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802aad8:	db44      	blt.n	802ab64 <Region_Automated_Task_Func_Alternately_Horizontal+0x194>
+				{
+					Auto_Job_Back_Time_MS_Count=0;
+ 802aada:	4b67      	ldr	r3, [pc, #412]	@ (802ac78 <Region_Automated_Task_Func_Alternately_Horizontal+0x2a8>)
+ 802aadc:	2200      	movs	r2, #0
+ 802aade:	601a      	str	r2, [r3, #0]
+					Robot_Platform_Back_Flag=2;
+ 802aae0:	4b64      	ldr	r3, [pc, #400]	@ (802ac74 <Region_Automated_Task_Func_Alternately_Horizontal+0x2a4>)
+ 802aae2:	2202      	movs	r2, #2
+ 802aae4:	601a      	str	r2, [r3, #0]
+					Region_Task_Falg++;
+ 802aae6:	4b58      	ldr	r3, [pc, #352]	@ (802ac48 <Region_Automated_Task_Func_Alternately_Horizontal+0x278>)
+ 802aae8:	681b      	ldr	r3, [r3, #0]
+ 802aaea:	3301      	adds	r3, #1
+ 802aaec:	4a56      	ldr	r2, [pc, #344]	@ (802ac48 <Region_Automated_Task_Func_Alternately_Horizontal+0x278>)
+ 802aaee:	6013      	str	r3, [r2, #0]
+					Plane_Complete_Count++;
+ 802aaf0:	4b5f      	ldr	r3, [pc, #380]	@ (802ac70 <Region_Automated_Task_Func_Alternately_Horizontal+0x2a0>)
+ 802aaf2:	681b      	ldr	r3, [r3, #0]
+ 802aaf4:	3301      	adds	r3, #1
+ 802aaf6:	4a5e      	ldr	r2, [pc, #376]	@ (802ac70 <Region_Automated_Task_Func_Alternately_Horizontal+0x2a0>)
+ 802aaf8:	6013      	str	r3, [r2, #0]
+					int i=0;
+ 802aafa:	2300      	movs	r3, #0
+ 802aafc:	607b      	str	r3, [r7, #4]
+					i=Plane_Complete_Count%2;
+ 802aafe:	4b5c      	ldr	r3, [pc, #368]	@ (802ac70 <Region_Automated_Task_Func_Alternately_Horizontal+0x2a0>)
+ 802ab00:	681b      	ldr	r3, [r3, #0]
+ 802ab02:	2b00      	cmp	r3, #0
+ 802ab04:	f003 0301 	and.w	r3, r3, #1
+ 802ab08:	bfb8      	it	lt
+ 802ab0a:	425b      	neglt	r3, r3
+ 802ab0c:	607b      	str	r3, [r7, #4]
+					if(i==0)
+ 802ab0e:	687b      	ldr	r3, [r7, #4]
+ 802ab10:	2b00      	cmp	r3, #0
+ 802ab12:	d10c      	bne.n	802ab2e <Region_Automated_Task_Func_Alternately_Horizontal+0x15e>
+					{
+						X_Deri_Angle[0]=Deri_Angle_Deg_X[0];
+ 802ab14:	4b4e      	ldr	r3, [pc, #312]	@ (802ac50 <Region_Automated_Task_Func_Alternately_Horizontal+0x280>)
+ 802ab16:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802ab1a:	4952      	ldr	r1, [pc, #328]	@ (802ac64 <Region_Automated_Task_Func_Alternately_Horizontal+0x294>)
+ 802ab1c:	e9c1 2300 	strd	r2, r3, [r1]
+						X_Deri_Angle[1]=Deri_Angle_Deg_X[1];
+ 802ab20:	4b4b      	ldr	r3, [pc, #300]	@ (802ac50 <Region_Automated_Task_Func_Alternately_Horizontal+0x280>)
+ 802ab22:	e9d3 2302 	ldrd	r2, r3, [r3, #8]
+ 802ab26:	494f      	ldr	r1, [pc, #316]	@ (802ac64 <Region_Automated_Task_Func_Alternately_Horizontal+0x294>)
+ 802ab28:	e9c1 2302 	strd	r2, r3, [r1, #8]
+ 802ab2c:	e00b      	b.n	802ab46 <Region_Automated_Task_Func_Alternately_Horizontal+0x176>
+					}
+					else
+					{
+						X_Deri_Angle[0]=Deri_Angle_Deg_X[1];
+ 802ab2e:	4b48      	ldr	r3, [pc, #288]	@ (802ac50 <Region_Automated_Task_Func_Alternately_Horizontal+0x280>)
+ 802ab30:	e9d3 2302 	ldrd	r2, r3, [r3, #8]
+ 802ab34:	494b      	ldr	r1, [pc, #300]	@ (802ac64 <Region_Automated_Task_Func_Alternately_Horizontal+0x294>)
+ 802ab36:	e9c1 2300 	strd	r2, r3, [r1]
+						X_Deri_Angle[1]=Deri_Angle_Deg_X[0];
+ 802ab3a:	4b45      	ldr	r3, [pc, #276]	@ (802ac50 <Region_Automated_Task_Func_Alternately_Horizontal+0x280>)
+ 802ab3c:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802ab40:	4948      	ldr	r1, [pc, #288]	@ (802ac64 <Region_Automated_Task_Func_Alternately_Horizontal+0x294>)
+ 802ab42:	e9c1 2302 	strd	r2, r3, [r1, #8]
+					}
+					if(Plane_Complete_Count>=Horizontal_Complete_Total_XY)
+ 802ab46:	4b4a      	ldr	r3, [pc, #296]	@ (802ac70 <Region_Automated_Task_Func_Alternately_Horizontal+0x2a0>)
+ 802ab48:	681a      	ldr	r2, [r3, #0]
+ 802ab4a:	4b45      	ldr	r3, [pc, #276]	@ (802ac60 <Region_Automated_Task_Func_Alternately_Horizontal+0x290>)
+ 802ab4c:	681b      	ldr	r3, [r3, #0]
+ 802ab4e:	429a      	cmp	r2, r3
+ 802ab50:	db05      	blt.n	802ab5e <Region_Automated_Task_Func_Alternately_Horizontal+0x18e>
+					{
+						ctl_flag_1 = 1;
+ 802ab52:	4b4c      	ldr	r3, [pc, #304]	@ (802ac84 <Region_Automated_Task_Func_Alternately_Horizontal+0x2b4>)
+ 802ab54:	2201      	movs	r2, #1
+ 802ab56:	601a      	str	r2, [r3, #0]
+						Region_Task_Falg=RE_Horizontal_Region_Auto_Close;
+ 802ab58:	4b3b      	ldr	r3, [pc, #236]	@ (802ac48 <Region_Automated_Task_Func_Alternately_Horizontal+0x278>)
+ 802ab5a:	2206      	movs	r2, #6
+ 802ab5c:	601a      	str	r2, [r3, #0]
+					}
+					Backward_Num_X_Count=0;
+ 802ab5e:	4b43      	ldr	r3, [pc, #268]	@ (802ac6c <Region_Automated_Task_Func_Alternately_Horizontal+0x29c>)
+ 802ab60:	2200      	movs	r2, #0
+ 802ab62:	601a      	str	r2, [r3, #0]
+				}
+				Robot_Platform_Back_Flag_Y=0;
+ 802ab64:	4b48      	ldr	r3, [pc, #288]	@ (802ac88 <Region_Automated_Task_Func_Alternately_Horizontal+0x2b8>)
+ 802ab66:	2200      	movs	r2, #0
+ 802ab68:	601a      	str	r2, [r3, #0]
+			  break;
+ 802ab6a:	e068      	b.n	802ac3e <Region_Automated_Task_Func_Alternately_Horizontal+0x26e>
+		  case RE_Horizontal_Turn_To_Y:
+			  Swing_Limit_Contrl();//摆臂限位控制
+ 802ab6c:	f002 fd74 	bl	802d658 <Swing_Limit_Contrl>
+			  CV_Robot_Deri_Angle_Deg_Grity=Horizontal_Turn_Angle_Deg;
+ 802ab70:	4b38      	ldr	r3, [pc, #224]	@ (802ac54 <Region_Automated_Task_Func_Alternately_Horizontal+0x284>)
+ 802ab72:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802ab76:	4935      	ldr	r1, [pc, #212]	@ (802ac4c <Region_Automated_Task_Func_Alternately_Horizontal+0x27c>)
+ 802ab78:	e9c1 2300 	strd	r2, r3, [r1]
+			  Robot_Posture_Adjus_Gravity();
+ 802ab7c:	f001 f958 	bl	802be30 <Robot_Posture_Adjus_Gravity>
+			  if(Angle_Error_LLL<Error_Cont_Thresh)
+ 802ab80:	4b3e      	ldr	r3, [pc, #248]	@ (802ac7c <Region_Automated_Task_Func_Alternately_Horizontal+0x2ac>)
+ 802ab82:	ed93 6b00 	vldr	d6, [r3]
+ 802ab86:	4b3e      	ldr	r3, [pc, #248]	@ (802ac80 <Region_Automated_Task_Func_Alternately_Horizontal+0x2b0>)
+ 802ab88:	ed93 7b00 	vldr	d7, [r3]
+ 802ab8c:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802ab90:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802ab94:	d504      	bpl.n	802aba0 <Region_Automated_Task_Func_Alternately_Horizontal+0x1d0>
+			  {
+				  Region_Task_Falg++;
+ 802ab96:	4b2c      	ldr	r3, [pc, #176]	@ (802ac48 <Region_Automated_Task_Func_Alternately_Horizontal+0x278>)
+ 802ab98:	681b      	ldr	r3, [r3, #0]
+ 802ab9a:	3301      	adds	r3, #1
+ 802ab9c:	4a2a      	ldr	r2, [pc, #168]	@ (802ac48 <Region_Automated_Task_Func_Alternately_Horizontal+0x278>)
+ 802ab9e:	6013      	str	r3, [r2, #0]
+			  }
+			  Auto_Job_Back_Time_MS_Count=0;
+ 802aba0:	4b35      	ldr	r3, [pc, #212]	@ (802ac78 <Region_Automated_Task_Func_Alternately_Horizontal+0x2a8>)
+ 802aba2:	2200      	movs	r2, #0
+ 802aba4:	601a      	str	r2, [r3, #0]
+			  Robot_Platform_Back_Flag=0;
+ 802aba6:	4b33      	ldr	r3, [pc, #204]	@ (802ac74 <Region_Automated_Task_Func_Alternately_Horizontal+0x2a4>)
+ 802aba8:	2200      	movs	r2, #0
+ 802abaa:	601a      	str	r2, [r3, #0]
+			  Backward_Num_X_Count=0;
+ 802abac:	4b2f      	ldr	r3, [pc, #188]	@ (802ac6c <Region_Automated_Task_Func_Alternately_Horizontal+0x29c>)
+ 802abae:	2200      	movs	r2, #0
+ 802abb0:	601a      	str	r2, [r3, #0]
+		  	  break;
+ 802abb2:	e044      	b.n	802ac3e <Region_Automated_Task_Func_Alternately_Horizontal+0x26e>
+		  case RE_Horizontal_Lane_Change_Y:
+			  Swing_Limit_Contrl();//摆臂限位控制
+ 802abb4:	f002 fd50 	bl	802d658 <Swing_Limit_Contrl>
+			  Robot_Platform_Back_Contronl_Horizontal();
+ 802abb8:	f002 ff62 	bl	802da80 <Robot_Platform_Back_Contronl_Horizontal>
+			  if(Backward_Num_X_Count>=Lane_Change_Num_Total_Y)
+ 802abbc:	4b2b      	ldr	r3, [pc, #172]	@ (802ac6c <Region_Automated_Task_Func_Alternately_Horizontal+0x29c>)
+ 802abbe:	681b      	ldr	r3, [r3, #0]
+ 802abc0:	ee07 3a90 	vmov	s15, r3
+ 802abc4:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802abc8:	4b24      	ldr	r3, [pc, #144]	@ (802ac5c <Region_Automated_Task_Func_Alternately_Horizontal+0x28c>)
+ 802abca:	ed93 7b00 	vldr	d7, [r3]
+ 802abce:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802abd2:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802abd6:	da00      	bge.n	802abda <Region_Automated_Task_Func_Alternately_Horizontal+0x20a>
+			  {
+				  Region_Task_Falg++;
+				  Backward_Num_X_Count=0;
+			  }
+			  break;
+ 802abd8:	e031      	b.n	802ac3e <Region_Automated_Task_Func_Alternately_Horizontal+0x26e>
+				  Region_Task_Falg++;
+ 802abda:	4b1b      	ldr	r3, [pc, #108]	@ (802ac48 <Region_Automated_Task_Func_Alternately_Horizontal+0x278>)
+ 802abdc:	681b      	ldr	r3, [r3, #0]
+ 802abde:	3301      	adds	r3, #1
+ 802abe0:	4a19      	ldr	r2, [pc, #100]	@ (802ac48 <Region_Automated_Task_Func_Alternately_Horizontal+0x278>)
+ 802abe2:	6013      	str	r3, [r2, #0]
+				  Backward_Num_X_Count=0;
+ 802abe4:	4b21      	ldr	r3, [pc, #132]	@ (802ac6c <Region_Automated_Task_Func_Alternately_Horizontal+0x29c>)
+ 802abe6:	2200      	movs	r2, #0
+ 802abe8:	601a      	str	r2, [r3, #0]
+			  break;
+ 802abea:	e028      	b.n	802ac3e <Region_Automated_Task_Func_Alternately_Horizontal+0x26e>
+		  case RE_Horizontal_Turn_Back_X:
+			  CV_Robot_Deri_Angle_Deg_Grity=X_Deri_Angle[0];
+ 802abec:	4b1d      	ldr	r3, [pc, #116]	@ (802ac64 <Region_Automated_Task_Func_Alternately_Horizontal+0x294>)
+ 802abee:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802abf2:	4916      	ldr	r1, [pc, #88]	@ (802ac4c <Region_Automated_Task_Func_Alternately_Horizontal+0x27c>)
+ 802abf4:	e9c1 2300 	strd	r2, r3, [r1]
+			  Swing_Limit_Contrl();
+ 802abf8:	f002 fd2e 	bl	802d658 <Swing_Limit_Contrl>
+			  Robot_Posture_Adjus_Gravity();
+ 802abfc:	f001 f918 	bl	802be30 <Robot_Posture_Adjus_Gravity>
+			  if(Angle_Error_LLL<Error_Cont_Thresh)
+ 802ac00:	4b1e      	ldr	r3, [pc, #120]	@ (802ac7c <Region_Automated_Task_Func_Alternately_Horizontal+0x2ac>)
+ 802ac02:	ed93 6b00 	vldr	d6, [r3]
+ 802ac06:	4b1e      	ldr	r3, [pc, #120]	@ (802ac80 <Region_Automated_Task_Func_Alternately_Horizontal+0x2b0>)
+ 802ac08:	ed93 7b00 	vldr	d7, [r3]
+ 802ac0c:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802ac10:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802ac14:	d400      	bmi.n	802ac18 <Region_Automated_Task_Func_Alternately_Horizontal+0x248>
+			  {
+				Region_Task_Falg=RE_Horizontal_Backward_Task_X;
+			  }
+			  break;
+ 802ac16:	e012      	b.n	802ac3e <Region_Automated_Task_Func_Alternately_Horizontal+0x26e>
+				Region_Task_Falg=RE_Horizontal_Backward_Task_X;
+ 802ac18:	4b0b      	ldr	r3, [pc, #44]	@ (802ac48 <Region_Automated_Task_Func_Alternately_Horizontal+0x278>)
+ 802ac1a:	2202      	movs	r2, #2
+ 802ac1c:	601a      	str	r2, [r3, #0]
+			  break;
+ 802ac1e:	e00e      	b.n	802ac3e <Region_Automated_Task_Func_Alternately_Horizontal+0x26e>
+		  case RE_Horizontal_Region_Auto_Close:
+			  HALT_State_Do();
+ 802ac20:	f005 faa2 	bl	8030168 <HALT_State_Do>
+			  Blast_Machine_Close_Fun();//hjb
+ 802ac24:	f7fb fccc 	bl	80265c0 <Blast_Machine_Close_Fun>
+			  Plane_Complete_Count=0;
+ 802ac28:	4b11      	ldr	r3, [pc, #68]	@ (802ac70 <Region_Automated_Task_Func_Alternately_Horizontal+0x2a0>)
+ 802ac2a:	2200      	movs	r2, #0
+ 802ac2c:	601a      	str	r2, [r3, #0]
+			  GV.SwingMotor.Target_Velcity =0;
+ 802ac2e:	4b17      	ldr	r3, [pc, #92]	@ (802ac8c <Region_Automated_Task_Func_Alternately_Horizontal+0x2bc>)
+ 802ac30:	2200      	movs	r2, #0
+ 802ac32:	f8c3 2178 	str.w	r2, [r3, #376]	@ 0x178
+			  break;
+ 802ac36:	e002      	b.n	802ac3e <Region_Automated_Task_Func_Alternately_Horizontal+0x26e>
+		  default:
+			  HALT_State_Do();
+ 802ac38:	f005 fa96 	bl	8030168 <HALT_State_Do>
+			  break;
+ 802ac3c:	bf00      	nop
+	  }
+}
+ 802ac3e:	bf00      	nop
+ 802ac40:	3708      	adds	r7, #8
+ 802ac42:	46bd      	mov	sp, r7
+ 802ac44:	bd80      	pop	{r7, pc}
+ 802ac46:	bf00      	nop
+ 802ac48:	2400a6c4 	.word	0x2400a6c4
+ 802ac4c:	2400a6d0 	.word	0x2400a6d0
+ 802ac50:	2400a7b0 	.word	0x2400a7b0
+ 802ac54:	2400a7e8 	.word	0x2400a7e8
+ 802ac58:	2400a7d8 	.word	0x2400a7d8
+ 802ac5c:	2400a7e0 	.word	0x2400a7e0
+ 802ac60:	2400a7f0 	.word	0x2400a7f0
+ 802ac64:	2400a7c0 	.word	0x2400a7c0
+ 802ac68:	2400a6f4 	.word	0x2400a6f4
+ 802ac6c:	2400a79c 	.word	0x2400a79c
+ 802ac70:	2400a7a4 	.word	0x2400a7a4
+ 802ac74:	2400a6f8 	.word	0x2400a6f8
+ 802ac78:	2400a6fc 	.word	0x2400a6fc
+ 802ac7c:	2400a9e8 	.word	0x2400a9e8
+ 802ac80:	24000090 	.word	0x24000090
+ 802ac84:	2400a774 	.word	0x2400a774
+ 802ac88:	2400a6e0 	.word	0x2400a6e0
+ 802ac8c:	24000340 	.word	0x24000340
+
+0802ac90 <Vertical_Manual_Operation_Func>:
+
+
+
+
+void Vertical_Manual_Operation_Func()
+{
+ 802ac90:	b580      	push	{r7, lr}
+ 802ac92:	b088      	sub	sp, #32
+ 802ac94:	af00      	add	r7, sp, #0
+    double y_value = P_MK32->CH2_LY_V; // 假设 Y 是纵向（前后）
+ 802ac96:	4b90      	ldr	r3, [pc, #576]	@ (802aed8 <Vertical_Manual_Operation_Func+0x248>)
+ 802ac98:	681b      	ldr	r3, [r3, #0]
+ 802ac9a:	68db      	ldr	r3, [r3, #12]
+ 802ac9c:	ee07 3a90 	vmov	s15, r3
+ 802aca0:	eeb8 7be7 	vcvt.f64.s32	d7, s15
+ 802aca4:	ed87 7b06 	vstr	d7, [r7, #24]
+    double x_value = P_MK32->CH3_LY_H; // 假设 X 是横向（左右）
+ 802aca8:	4b8b      	ldr	r3, [pc, #556]	@ (802aed8 <Vertical_Manual_Operation_Func+0x248>)
+ 802acaa:	681b      	ldr	r3, [r3, #0]
+ 802acac:	691b      	ldr	r3, [r3, #16]
+ 802acae:	ee07 3a90 	vmov	s15, r3
+ 802acb2:	eeb8 7be7 	vcvt.f64.s32	d7, s15
+ 802acb6:	ed87 7b04 	vstr	d7, [r7, #16]
+
+	double w_value = P_MK32->CH0_RY_H; // 假设 X 是横向（左右）
+ 802acba:	4b87      	ldr	r3, [pc, #540]	@ (802aed8 <Vertical_Manual_Operation_Func+0x248>)
+ 802acbc:	681b      	ldr	r3, [r3, #0]
+ 802acbe:	685b      	ldr	r3, [r3, #4]
+ 802acc0:	ee07 3a90 	vmov	s15, r3
+ 802acc4:	eeb8 7be7 	vcvt.f64.s32	d7, s15
+ 802acc8:	ed87 7b02 	vstr	d7, [r7, #8]
+	double z_value = P_MK32->CH1_RY_V; // 假设 X 是横向（左右）
+ 802accc:	4b82      	ldr	r3, [pc, #520]	@ (802aed8 <Vertical_Manual_Operation_Func+0x248>)
+ 802acce:	681b      	ldr	r3, [r3, #0]
+ 802acd0:	689b      	ldr	r3, [r3, #8]
+ 802acd2:	ee07 3a90 	vmov	s15, r3
+ 802acd6:	eeb8 7be7 	vcvt.f64.s32	d7, s15
+ 802acda:	ed87 7b00 	vstr	d7, [r7]
+
+    static int Horizontal_Manual_Flag ; // 静态局部变量
+
+    if((fabs(y_value)>=300)||(fabs(x_value)>=300)||(fabs(w_value)>=300)||(fabs(z_value)>=300))
+ 802acde:	ed97 7b06 	vldr	d7, [r7, #24]
+ 802ace2:	eeb0 7bc7 	vabs.f64	d7, d7
+ 802ace6:	ed9f 6b6c 	vldr	d6, [pc, #432]	@ 802ae98 <Vertical_Manual_Operation_Func+0x208>
+ 802acea:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 802acee:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802acf2:	da21      	bge.n	802ad38 <Vertical_Manual_Operation_Func+0xa8>
+ 802acf4:	ed97 7b04 	vldr	d7, [r7, #16]
+ 802acf8:	eeb0 7bc7 	vabs.f64	d7, d7
+ 802acfc:	ed9f 6b66 	vldr	d6, [pc, #408]	@ 802ae98 <Vertical_Manual_Operation_Func+0x208>
+ 802ad00:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 802ad04:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802ad08:	da16      	bge.n	802ad38 <Vertical_Manual_Operation_Func+0xa8>
+ 802ad0a:	ed97 7b02 	vldr	d7, [r7, #8]
+ 802ad0e:	eeb0 7bc7 	vabs.f64	d7, d7
+ 802ad12:	ed9f 6b61 	vldr	d6, [pc, #388]	@ 802ae98 <Vertical_Manual_Operation_Func+0x208>
+ 802ad16:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 802ad1a:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802ad1e:	da0b      	bge.n	802ad38 <Vertical_Manual_Operation_Func+0xa8>
+ 802ad20:	ed97 7b00 	vldr	d7, [r7]
+ 802ad24:	eeb0 7bc7 	vabs.f64	d7, d7
+ 802ad28:	ed9f 6b5b 	vldr	d6, [pc, #364]	@ 802ae98 <Vertical_Manual_Operation_Func+0x208>
+ 802ad2c:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 802ad30:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802ad34:	f2c0 80a0 	blt.w	802ae78 <Vertical_Manual_Operation_Func+0x1e8>
+     {
+     	switch(Horizontal_Manual_Flag)
+ 802ad38:	4b68      	ldr	r3, [pc, #416]	@ (802aedc <Vertical_Manual_Operation_Func+0x24c>)
+ 802ad3a:	681b      	ldr	r3, [r3, #0]
+ 802ad3c:	2b00      	cmp	r3, #0
+ 802ad3e:	d002      	beq.n	802ad46 <Vertical_Manual_Operation_Func+0xb6>
+ 802ad40:	2b01      	cmp	r3, #1
+ 802ad42:	d006      	beq.n	802ad52 <Vertical_Manual_Operation_Func+0xc2>
+ 802ad44:	e0a3      	b.n	802ae8e <Vertical_Manual_Operation_Func+0x1fe>
+     	{
+     		case 0:
+
+     			Horizontal_Manual_Flag++;
+ 802ad46:	4b65      	ldr	r3, [pc, #404]	@ (802aedc <Vertical_Manual_Operation_Func+0x24c>)
+ 802ad48:	681b      	ldr	r3, [r3, #0]
+ 802ad4a:	3301      	adds	r3, #1
+ 802ad4c:	4a63      	ldr	r2, [pc, #396]	@ (802aedc <Vertical_Manual_Operation_Func+0x24c>)
+ 802ad4e:	6013      	str	r3, [r2, #0]
+     			break;
+ 802ad50:	e091      	b.n	802ae76 <Vertical_Manual_Operation_Func+0x1e6>
+     		case 1:
+				if((fabs(y_value)>=300)||(fabs(x_value)>=300))
+ 802ad52:	ed97 7b06 	vldr	d7, [r7, #24]
+ 802ad56:	eeb0 7bc7 	vabs.f64	d7, d7
+ 802ad5a:	ed9f 6b4f 	vldr	d6, [pc, #316]	@ 802ae98 <Vertical_Manual_Operation_Func+0x208>
+ 802ad5e:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 802ad62:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802ad66:	da0a      	bge.n	802ad7e <Vertical_Manual_Operation_Func+0xee>
+ 802ad68:	ed97 7b04 	vldr	d7, [r7, #16]
+ 802ad6c:	eeb0 7bc7 	vabs.f64	d7, d7
+ 802ad70:	ed9f 6b49 	vldr	d6, [pc, #292]	@ 802ae98 <Vertical_Manual_Operation_Func+0x208>
+ 802ad74:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 802ad78:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802ad7c:	db76      	blt.n	802ae6c <Vertical_Manual_Operation_Func+0x1dc>
+				{
+					Rock_Angle= atan2(y_value, x_value);
+ 802ad7e:	ed97 1b04 	vldr	d1, [r7, #16]
+ 802ad82:	ed97 0b06 	vldr	d0, [r7, #24]
+ 802ad86:	f015 fea7 	bl	8040ad8 <atan2>
+ 802ad8a:	eeb0 7b40 	vmov.f64	d7, d0
+ 802ad8e:	4b54      	ldr	r3, [pc, #336]	@ (802aee0 <Vertical_Manual_Operation_Func+0x250>)
+ 802ad90:	ed83 7b00 	vstr	d7, [r3]
+					Rock_Angle=Rock_Angle/3.1415926*180;
+ 802ad94:	4b52      	ldr	r3, [pc, #328]	@ (802aee0 <Vertical_Manual_Operation_Func+0x250>)
+ 802ad96:	ed93 6b00 	vldr	d6, [r3]
+ 802ad9a:	ed9f 5b41 	vldr	d5, [pc, #260]	@ 802aea0 <Vertical_Manual_Operation_Func+0x210>
+ 802ad9e:	ee86 7b05 	vdiv.f64	d7, d6, d5
+ 802ada2:	ed9f 6b41 	vldr	d6, [pc, #260]	@ 802aea8 <Vertical_Manual_Operation_Func+0x218>
+ 802ada6:	ee27 7b06 	vmul.f64	d7, d7, d6
+ 802adaa:	4b4d      	ldr	r3, [pc, #308]	@ (802aee0 <Vertical_Manual_Operation_Func+0x250>)
+ 802adac:	ed83 7b00 	vstr	d7, [r3]
+
+					if((Rock_Angle>=-30)&&(Rock_Angle<=30))
+ 802adb0:	4b4b      	ldr	r3, [pc, #300]	@ (802aee0 <Vertical_Manual_Operation_Func+0x250>)
+ 802adb2:	ed93 7b00 	vldr	d7, [r3]
+ 802adb6:	eebb 6b0e 	vmov.f64	d6, #190	@ 0xc1f00000 -30.0
+ 802adba:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 802adbe:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802adc2:	db0f      	blt.n	802ade4 <Vertical_Manual_Operation_Func+0x154>
+ 802adc4:	4b46      	ldr	r3, [pc, #280]	@ (802aee0 <Vertical_Manual_Operation_Func+0x250>)
+ 802adc6:	ed93 7b00 	vldr	d7, [r3]
+ 802adca:	eeb3 6b0e 	vmov.f64	d6, #62	@ 0x41f00000  30.0
+ 802adce:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 802add2:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802add6:	d805      	bhi.n	802ade4 <Vertical_Manual_Operation_Func+0x154>
+					{
+						TurnRight_State_Do();
+ 802add8:	f002 fa62 	bl	802d2a0 <TurnRight_State_Do>
+						Forward_Flag_Robot_Manual=1;
+ 802addc:	4b41      	ldr	r3, [pc, #260]	@ (802aee4 <Vertical_Manual_Operation_Func+0x254>)
+ 802adde:	2201      	movs	r2, #1
+ 802ade0:	601a      	str	r2, [r3, #0]
+ 802ade2:	e042      	b.n	802ae6a <Vertical_Manual_Operation_Func+0x1da>
+					}
+					else if((Rock_Angle>=60)&&(Rock_Angle<=120))
+ 802ade4:	4b3e      	ldr	r3, [pc, #248]	@ (802aee0 <Vertical_Manual_Operation_Func+0x250>)
+ 802ade6:	ed93 7b00 	vldr	d7, [r3]
+ 802adea:	ed9f 6b31 	vldr	d6, [pc, #196]	@ 802aeb0 <Vertical_Manual_Operation_Func+0x220>
+ 802adee:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 802adf2:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802adf6:	db0c      	blt.n	802ae12 <Vertical_Manual_Operation_Func+0x182>
+ 802adf8:	4b39      	ldr	r3, [pc, #228]	@ (802aee0 <Vertical_Manual_Operation_Func+0x250>)
+ 802adfa:	ed93 7b00 	vldr	d7, [r3]
+ 802adfe:	ed9f 6b2e 	vldr	d6, [pc, #184]	@ 802aeb8 <Vertical_Manual_Operation_Func+0x228>
+ 802ae02:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 802ae06:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802ae0a:	d802      	bhi.n	802ae12 <Vertical_Manual_Operation_Func+0x182>
+					{
+
+						Move_Vertical_Manual_Sub_Func_Forward();
+ 802ae0c:	f7ff fa84 	bl	802a318 <Move_Vertical_Manual_Sub_Func_Forward>
+ 802ae10:	e02b      	b.n	802ae6a <Vertical_Manual_Operation_Func+0x1da>
+					}
+					else if((Rock_Angle>=-120)&&(Rock_Angle<=-60))
+ 802ae12:	4b33      	ldr	r3, [pc, #204]	@ (802aee0 <Vertical_Manual_Operation_Func+0x250>)
+ 802ae14:	ed93 7b00 	vldr	d7, [r3]
+ 802ae18:	ed9f 6b29 	vldr	d6, [pc, #164]	@ 802aec0 <Vertical_Manual_Operation_Func+0x230>
+ 802ae1c:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 802ae20:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802ae24:	db0c      	blt.n	802ae40 <Vertical_Manual_Operation_Func+0x1b0>
+ 802ae26:	4b2e      	ldr	r3, [pc, #184]	@ (802aee0 <Vertical_Manual_Operation_Func+0x250>)
+ 802ae28:	ed93 7b00 	vldr	d7, [r3]
+ 802ae2c:	ed9f 6b26 	vldr	d6, [pc, #152]	@ 802aec8 <Vertical_Manual_Operation_Func+0x238>
+ 802ae30:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 802ae34:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802ae38:	d802      	bhi.n	802ae40 <Vertical_Manual_Operation_Func+0x1b0>
+					{
+						Move_Vertical_Manual_Sub_Func_Backward();
+ 802ae3a:	f7ff fac5 	bl	802a3c8 <Move_Vertical_Manual_Sub_Func_Backward>
+ 802ae3e:	e014      	b.n	802ae6a <Vertical_Manual_Operation_Func+0x1da>
+					}
+					else if(fabs(Rock_Angle)>=150)
+ 802ae40:	4b27      	ldr	r3, [pc, #156]	@ (802aee0 <Vertical_Manual_Operation_Func+0x250>)
+ 802ae42:	ed93 7b00 	vldr	d7, [r3]
+ 802ae46:	eeb0 7bc7 	vabs.f64	d7, d7
+ 802ae4a:	ed9f 6b21 	vldr	d6, [pc, #132]	@ 802aed0 <Vertical_Manual_Operation_Func+0x240>
+ 802ae4e:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 802ae52:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802ae56:	db05      	blt.n	802ae64 <Vertical_Manual_Operation_Func+0x1d4>
+					{
+						TurnLeft_State_Do();
+ 802ae58:	f002 f9f8 	bl	802d24c <TurnLeft_State_Do>
+						Forward_Flag_Robot_Manual=1;
+ 802ae5c:	4b21      	ldr	r3, [pc, #132]	@ (802aee4 <Vertical_Manual_Operation_Func+0x254>)
+ 802ae5e:	2201      	movs	r2, #1
+ 802ae60:	601a      	str	r2, [r3, #0]
+					if((Rock_Angle>=-30)&&(Rock_Angle<=30))
+ 802ae62:	e005      	b.n	802ae70 <Vertical_Manual_Operation_Func+0x1e0>
+					}
+					else
+					{
+						HALT_State_Do();
+ 802ae64:	f005 f980 	bl	8030168 <HALT_State_Do>
+					if((Rock_Angle>=-30)&&(Rock_Angle<=30))
+ 802ae68:	e002      	b.n	802ae70 <Vertical_Manual_Operation_Func+0x1e0>
+ 802ae6a:	e001      	b.n	802ae70 <Vertical_Manual_Operation_Func+0x1e0>
+					}
+				}
+				else
+				{
+					HALT_State_Do();
+ 802ae6c:	f005 f97c 	bl	8030168 <HALT_State_Do>
+				}
+				Robot_Swing_Operation_Function();//摆臂运动函数
+ 802ae70:	f7fe fed4 	bl	8029c1c <Robot_Swing_Operation_Function>
+     			break;
+ 802ae74:	bf00      	nop
+     	switch(Horizontal_Manual_Flag)
+ 802ae76:	e00a      	b.n	802ae8e <Vertical_Manual_Operation_Func+0x1fe>
+     	}
+     }
+ 	else
+ 	{
+ 		Horizontal_Manual_Flag=0;
+ 802ae78:	4b18      	ldr	r3, [pc, #96]	@ (802aedc <Vertical_Manual_Operation_Func+0x24c>)
+ 802ae7a:	2200      	movs	r2, #0
+ 802ae7c:	601a      	str	r2, [r3, #0]
+ 		HALT_State_Do();
+ 802ae7e:	f005 f973 	bl	8030168 <HALT_State_Do>
+ 		Move_Swing_Halt_Func_Do();
+ 802ae82:	f002 fad7 	bl	802d434 <Move_Swing_Halt_Func_Do>
+ 		Forward_Flag_Robot_Manual=1;
+ 802ae86:	4b17      	ldr	r3, [pc, #92]	@ (802aee4 <Vertical_Manual_Operation_Func+0x254>)
+ 802ae88:	2201      	movs	r2, #1
+ 802ae8a:	601a      	str	r2, [r3, #0]
+
+ 	}
+}
+ 802ae8c:	bf00      	nop
+ 802ae8e:	bf00      	nop
+ 802ae90:	3720      	adds	r7, #32
+ 802ae92:	46bd      	mov	sp, r7
+ 802ae94:	bd80      	pop	{r7, pc}
+ 802ae96:	bf00      	nop
+ 802ae98:	00000000 	.word	0x00000000
+ 802ae9c:	4072c000 	.word	0x4072c000
+ 802aea0:	4d12d84a 	.word	0x4d12d84a
+ 802aea4:	400921fb 	.word	0x400921fb
+ 802aea8:	00000000 	.word	0x00000000
+ 802aeac:	40668000 	.word	0x40668000
+ 802aeb0:	00000000 	.word	0x00000000
+ 802aeb4:	404e0000 	.word	0x404e0000
+ 802aeb8:	00000000 	.word	0x00000000
+ 802aebc:	405e0000 	.word	0x405e0000
+ 802aec0:	00000000 	.word	0x00000000
+ 802aec4:	c05e0000 	.word	0xc05e0000
+ 802aec8:	00000000 	.word	0x00000000
+ 802aecc:	c04e0000 	.word	0xc04e0000
+ 802aed0:	00000000 	.word	0x00000000
+ 802aed4:	4062c000 	.word	0x4062c000
+ 802aed8:	2400a3f8 	.word	0x2400a3f8
+ 802aedc:	2400a894 	.word	0x2400a894
+ 802aee0:	2400a768 	.word	0x2400a768
+ 802aee4:	24000098 	.word	0x24000098
+
+0802aee8 <Plane_Manual_Operation_Func>:
+
+void Plane_Manual_Operation_Func()
+{
+ 802aee8:	b580      	push	{r7, lr}
+ 802aeea:	b08a      	sub	sp, #40	@ 0x28
+ 802aeec:	af00      	add	r7, sp, #0
+    double y_value = P_MK32->CH2_LY_V; // 假设 Y 是纵向（前后）
+ 802aeee:	4b8e      	ldr	r3, [pc, #568]	@ (802b128 <Plane_Manual_Operation_Func+0x240>)
+ 802aef0:	681b      	ldr	r3, [r3, #0]
+ 802aef2:	68db      	ldr	r3, [r3, #12]
+ 802aef4:	ee07 3a90 	vmov	s15, r3
+ 802aef8:	eeb8 7be7 	vcvt.f64.s32	d7, s15
+ 802aefc:	ed87 7b08 	vstr	d7, [r7, #32]
+    double x_value = P_MK32->CH3_LY_H; // 假设 X 是横向（左右）
+ 802af00:	4b89      	ldr	r3, [pc, #548]	@ (802b128 <Plane_Manual_Operation_Func+0x240>)
+ 802af02:	681b      	ldr	r3, [r3, #0]
+ 802af04:	691b      	ldr	r3, [r3, #16]
+ 802af06:	ee07 3a90 	vmov	s15, r3
+ 802af0a:	eeb8 7be7 	vcvt.f64.s32	d7, s15
+ 802af0e:	ed87 7b06 	vstr	d7, [r7, #24]
+	double w_value = P_MK32->CH0_RY_H; // 假设 X 是横向（左右）
+ 802af12:	4b85      	ldr	r3, [pc, #532]	@ (802b128 <Plane_Manual_Operation_Func+0x240>)
+ 802af14:	681b      	ldr	r3, [r3, #0]
+ 802af16:	685b      	ldr	r3, [r3, #4]
+ 802af18:	ee07 3a90 	vmov	s15, r3
+ 802af1c:	eeb8 7be7 	vcvt.f64.s32	d7, s15
+ 802af20:	ed87 7b04 	vstr	d7, [r7, #16]
+	double z_value = P_MK32->CH1_RY_V; // 假设 X 是横向（左右）
+ 802af24:	4b80      	ldr	r3, [pc, #512]	@ (802b128 <Plane_Manual_Operation_Func+0x240>)
+ 802af26:	681b      	ldr	r3, [r3, #0]
+ 802af28:	689b      	ldr	r3, [r3, #8]
+ 802af2a:	ee07 3a90 	vmov	s15, r3
+ 802af2e:	eeb8 7be7 	vcvt.f64.s32	d7, s15
+ 802af32:	ed87 7b02 	vstr	d7, [r7, #8]
+
+    static int Horizontal_Manual_Flag ; // 静态局部变量
+
+    if((fabs(y_value)>=300)||(fabs(x_value)>=300)||(fabs(w_value)>=300)||(fabs(z_value)>=300))
+ 802af36:	ed97 7b08 	vldr	d7, [r7, #32]
+ 802af3a:	eeb0 7bc7 	vabs.f64	d7, d7
+ 802af3e:	ed9f 6b6a 	vldr	d6, [pc, #424]	@ 802b0e8 <Plane_Manual_Operation_Func+0x200>
+ 802af42:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 802af46:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802af4a:	da21      	bge.n	802af90 <Plane_Manual_Operation_Func+0xa8>
+ 802af4c:	ed97 7b06 	vldr	d7, [r7, #24]
+ 802af50:	eeb0 7bc7 	vabs.f64	d7, d7
+ 802af54:	ed9f 6b64 	vldr	d6, [pc, #400]	@ 802b0e8 <Plane_Manual_Operation_Func+0x200>
+ 802af58:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 802af5c:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802af60:	da16      	bge.n	802af90 <Plane_Manual_Operation_Func+0xa8>
+ 802af62:	ed97 7b04 	vldr	d7, [r7, #16]
+ 802af66:	eeb0 7bc7 	vabs.f64	d7, d7
+ 802af6a:	ed9f 6b5f 	vldr	d6, [pc, #380]	@ 802b0e8 <Plane_Manual_Operation_Func+0x200>
+ 802af6e:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 802af72:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802af76:	da0b      	bge.n	802af90 <Plane_Manual_Operation_Func+0xa8>
+ 802af78:	ed97 7b02 	vldr	d7, [r7, #8]
+ 802af7c:	eeb0 7bc7 	vabs.f64	d7, d7
+ 802af80:	ed9f 6b59 	vldr	d6, [pc, #356]	@ 802b0e8 <Plane_Manual_Operation_Func+0x200>
+ 802af84:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 802af88:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802af8c:	f2c0 809a 	blt.w	802b0c4 <Plane_Manual_Operation_Func+0x1dc>
+     {
+     	switch(Horizontal_Manual_Flag)
+ 802af90:	4b66      	ldr	r3, [pc, #408]	@ (802b12c <Plane_Manual_Operation_Func+0x244>)
+ 802af92:	681b      	ldr	r3, [r3, #0]
+ 802af94:	2b00      	cmp	r3, #0
+ 802af96:	d002      	beq.n	802af9e <Plane_Manual_Operation_Func+0xb6>
+ 802af98:	2b01      	cmp	r3, #1
+ 802af9a:	d009      	beq.n	802afb0 <Plane_Manual_Operation_Func+0xc8>
+ 802af9c:	e09d      	b.n	802b0da <Plane_Manual_Operation_Func+0x1f2>
+     	{
+     		case 0:
+
+     			Horizontal_Manual_Flag++;
+ 802af9e:	4b63      	ldr	r3, [pc, #396]	@ (802b12c <Plane_Manual_Operation_Func+0x244>)
+ 802afa0:	681b      	ldr	r3, [r3, #0]
+ 802afa2:	3301      	adds	r3, #1
+ 802afa4:	4a61      	ldr	r2, [pc, #388]	@ (802b12c <Plane_Manual_Operation_Func+0x244>)
+ 802afa6:	6013      	str	r3, [r2, #0]
+     			Forward_Flag_Robot_Manual=1;
+ 802afa8:	4b61      	ldr	r3, [pc, #388]	@ (802b130 <Plane_Manual_Operation_Func+0x248>)
+ 802afaa:	2201      	movs	r2, #1
+ 802afac:	601a      	str	r2, [r3, #0]
+     			break;
+ 802afae:	e088      	b.n	802b0c2 <Plane_Manual_Operation_Func+0x1da>
+     		case 1:
+				if((fabs(y_value)>=300)||(fabs(x_value)>=300))
+ 802afb0:	ed97 7b08 	vldr	d7, [r7, #32]
+ 802afb4:	eeb0 7bc7 	vabs.f64	d7, d7
+ 802afb8:	ed9f 6b4b 	vldr	d6, [pc, #300]	@ 802b0e8 <Plane_Manual_Operation_Func+0x200>
+ 802afbc:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 802afc0:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802afc4:	da0a      	bge.n	802afdc <Plane_Manual_Operation_Func+0xf4>
+ 802afc6:	ed97 7b06 	vldr	d7, [r7, #24]
+ 802afca:	eeb0 7bc7 	vabs.f64	d7, d7
+ 802afce:	ed9f 6b46 	vldr	d6, [pc, #280]	@ 802b0e8 <Plane_Manual_Operation_Func+0x200>
+ 802afd2:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 802afd6:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802afda:	db6d      	blt.n	802b0b8 <Plane_Manual_Operation_Func+0x1d0>
+				{
+					double Rock_Angle= atan2(y_value, x_value);
+ 802afdc:	ed97 1b06 	vldr	d1, [r7, #24]
+ 802afe0:	ed97 0b08 	vldr	d0, [r7, #32]
+ 802afe4:	f015 fd78 	bl	8040ad8 <atan2>
+ 802afe8:	ed87 0b00 	vstr	d0, [r7]
+					Rock_Angle=Rock_Angle/3.1415926*180;
+ 802afec:	ed97 6b00 	vldr	d6, [r7]
+ 802aff0:	ed9f 5b3f 	vldr	d5, [pc, #252]	@ 802b0f0 <Plane_Manual_Operation_Func+0x208>
+ 802aff4:	ee86 7b05 	vdiv.f64	d7, d6, d5
+ 802aff8:	ed9f 6b3f 	vldr	d6, [pc, #252]	@ 802b0f8 <Plane_Manual_Operation_Func+0x210>
+ 802affc:	ee27 7b06 	vmul.f64	d7, d7, d6
+ 802b000:	ed87 7b00 	vstr	d7, [r7]
+
+					if((Rock_Angle>=-30)&&(Rock_Angle<=30))
+ 802b004:	ed97 7b00 	vldr	d7, [r7]
+ 802b008:	eebb 6b0e 	vmov.f64	d6, #190	@ 0xc1f00000 -30.0
+ 802b00c:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 802b010:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802b014:	db0e      	blt.n	802b034 <Plane_Manual_Operation_Func+0x14c>
+ 802b016:	ed97 7b00 	vldr	d7, [r7]
+ 802b01a:	eeb3 6b0e 	vmov.f64	d6, #62	@ 0x41f00000  30.0
+ 802b01e:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 802b022:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802b026:	d805      	bhi.n	802b034 <Plane_Manual_Operation_Func+0x14c>
+					{
+						TurnLeft_State_Do_Plane();
+ 802b028:	f002 f98a 	bl	802d340 <TurnLeft_State_Do_Plane>
+						Forward_Flag_Robot_Manual=1;
+ 802b02c:	4b40      	ldr	r3, [pc, #256]	@ (802b130 <Plane_Manual_Operation_Func+0x248>)
+ 802b02e:	2201      	movs	r2, #1
+ 802b030:	601a      	str	r2, [r3, #0]
+					{
+ 802b032:	e040      	b.n	802b0b6 <Plane_Manual_Operation_Func+0x1ce>
+					}
+					else if((Rock_Angle>=60)&&(Rock_Angle<=120))
+ 802b034:	ed97 7b00 	vldr	d7, [r7]
+ 802b038:	ed9f 6b31 	vldr	d6, [pc, #196]	@ 802b100 <Plane_Manual_Operation_Func+0x218>
+ 802b03c:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 802b040:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802b044:	db0b      	blt.n	802b05e <Plane_Manual_Operation_Func+0x176>
+ 802b046:	ed97 7b00 	vldr	d7, [r7]
+ 802b04a:	ed9f 6b2f 	vldr	d6, [pc, #188]	@ 802b108 <Plane_Manual_Operation_Func+0x220>
+ 802b04e:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 802b052:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802b056:	d802      	bhi.n	802b05e <Plane_Manual_Operation_Func+0x176>
+					{
+						Move_Plane_Manual_Sub_Func_Fordwards();
+ 802b058:	f000 f86c 	bl	802b134 <Move_Plane_Manual_Sub_Func_Fordwards>
+					{
+ 802b05c:	e02b      	b.n	802b0b6 <Plane_Manual_Operation_Func+0x1ce>
+					}
+					else if((Rock_Angle>=-120)&&(Rock_Angle<=-60))
+ 802b05e:	ed97 7b00 	vldr	d7, [r7]
+ 802b062:	ed9f 6b2b 	vldr	d6, [pc, #172]	@ 802b110 <Plane_Manual_Operation_Func+0x228>
+ 802b066:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 802b06a:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802b06e:	db0b      	blt.n	802b088 <Plane_Manual_Operation_Func+0x1a0>
+ 802b070:	ed97 7b00 	vldr	d7, [r7]
+ 802b074:	ed9f 6b28 	vldr	d6, [pc, #160]	@ 802b118 <Plane_Manual_Operation_Func+0x230>
+ 802b078:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 802b07c:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802b080:	d802      	bhi.n	802b088 <Plane_Manual_Operation_Func+0x1a0>
+					{
+						Move_Plane_Manual_Sub_Func_Backwards();
+ 802b082:	f000 f88b 	bl	802b19c <Move_Plane_Manual_Sub_Func_Backwards>
+					{
+ 802b086:	e016      	b.n	802b0b6 <Plane_Manual_Operation_Func+0x1ce>
+					}
+					else if(fabs(Rock_Angle)>=150)
+ 802b088:	ed97 7b00 	vldr	d7, [r7]
+ 802b08c:	eeb0 7bc7 	vabs.f64	d7, d7
+ 802b090:	ed9f 6b23 	vldr	d6, [pc, #140]	@ 802b120 <Plane_Manual_Operation_Func+0x238>
+ 802b094:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 802b098:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802b09c:	db05      	blt.n	802b0aa <Plane_Manual_Operation_Func+0x1c2>
+					{
+						TurnRight_State_Do_Plane();
+ 802b09e:	f002 f925 	bl	802d2ec <TurnRight_State_Do_Plane>
+						Forward_Flag_Robot_Manual=1;
+ 802b0a2:	4b23      	ldr	r3, [pc, #140]	@ (802b130 <Plane_Manual_Operation_Func+0x248>)
+ 802b0a4:	2201      	movs	r2, #1
+ 802b0a6:	601a      	str	r2, [r3, #0]
+				{
+ 802b0a8:	e008      	b.n	802b0bc <Plane_Manual_Operation_Func+0x1d4>
+					}
+					else
+					{
+						HALT_State_Do();
+ 802b0aa:	f005 f85d 	bl	8030168 <HALT_State_Do>
+						Forward_Flag_Robot_Manual=1;
+ 802b0ae:	4b20      	ldr	r3, [pc, #128]	@ (802b130 <Plane_Manual_Operation_Func+0x248>)
+ 802b0b0:	2201      	movs	r2, #1
+ 802b0b2:	601a      	str	r2, [r3, #0]
+				{
+ 802b0b4:	e002      	b.n	802b0bc <Plane_Manual_Operation_Func+0x1d4>
+ 802b0b6:	e001      	b.n	802b0bc <Plane_Manual_Operation_Func+0x1d4>
+					}
+				}
+				else
+				{
+					HALT_State_Do();
+ 802b0b8:	f005 f856 	bl	8030168 <HALT_State_Do>
+				}
+				Robot_Swing_Operation_Function();//摆臂运动函数
+ 802b0bc:	f7fe fdae 	bl	8029c1c <Robot_Swing_Operation_Function>
+     			break;
+ 802b0c0:	bf00      	nop
+     	switch(Horizontal_Manual_Flag)
+ 802b0c2:	e00a      	b.n	802b0da <Plane_Manual_Operation_Func+0x1f2>
+     	}
+     }
+ 	else
+ 	{
+ 		Horizontal_Manual_Flag=0;
+ 802b0c4:	4b19      	ldr	r3, [pc, #100]	@ (802b12c <Plane_Manual_Operation_Func+0x244>)
+ 802b0c6:	2200      	movs	r2, #0
+ 802b0c8:	601a      	str	r2, [r3, #0]
+ 		HALT_State_Do();
+ 802b0ca:	f005 f84d 	bl	8030168 <HALT_State_Do>
+ 		Move_Swing_Halt_Func_Do();
+ 802b0ce:	f002 f9b1 	bl	802d434 <Move_Swing_Halt_Func_Do>
+ 		Forward_Flag_Robot_Manual=1;
+ 802b0d2:	4b17      	ldr	r3, [pc, #92]	@ (802b130 <Plane_Manual_Operation_Func+0x248>)
+ 802b0d4:	2201      	movs	r2, #1
+ 802b0d6:	601a      	str	r2, [r3, #0]
+ 	}
+}
+ 802b0d8:	bf00      	nop
+ 802b0da:	bf00      	nop
+ 802b0dc:	3728      	adds	r7, #40	@ 0x28
+ 802b0de:	46bd      	mov	sp, r7
+ 802b0e0:	bd80      	pop	{r7, pc}
+ 802b0e2:	bf00      	nop
+ 802b0e4:	f3af 8000 	nop.w
+ 802b0e8:	00000000 	.word	0x00000000
+ 802b0ec:	4072c000 	.word	0x4072c000
+ 802b0f0:	4d12d84a 	.word	0x4d12d84a
+ 802b0f4:	400921fb 	.word	0x400921fb
+ 802b0f8:	00000000 	.word	0x00000000
+ 802b0fc:	40668000 	.word	0x40668000
+ 802b100:	00000000 	.word	0x00000000
+ 802b104:	404e0000 	.word	0x404e0000
+ 802b108:	00000000 	.word	0x00000000
+ 802b10c:	405e0000 	.word	0x405e0000
+ 802b110:	00000000 	.word	0x00000000
+ 802b114:	c05e0000 	.word	0xc05e0000
+ 802b118:	00000000 	.word	0x00000000
+ 802b11c:	c04e0000 	.word	0xc04e0000
+ 802b120:	00000000 	.word	0x00000000
+ 802b124:	4062c000 	.word	0x4062c000
+ 802b128:	2400a3f8 	.word	0x2400a3f8
+ 802b12c:	2400a898 	.word	0x2400a898
+ 802b130:	24000098 	.word	0x24000098
+
+0802b134 <Move_Plane_Manual_Sub_Func_Fordwards>:
+
+
+void Move_Plane_Manual_Sub_Func_Fordwards()
+{
+ 802b134:	b580      	push	{r7, lr}
+ 802b136:	af00      	add	r7, sp, #0
+	  switch (Forward_Flag_Robot_Manual)
+ 802b138:	4b15      	ldr	r3, [pc, #84]	@ (802b190 <Move_Plane_Manual_Sub_Func_Fordwards+0x5c>)
+ 802b13a:	681b      	ldr	r3, [r3, #0]
+ 802b13c:	2b03      	cmp	r3, #3
+ 802b13e:	d014      	beq.n	802b16a <Move_Plane_Manual_Sub_Func_Fordwards+0x36>
+ 802b140:	2b03      	cmp	r3, #3
+ 802b142:	dc1f      	bgt.n	802b184 <Move_Plane_Manual_Sub_Func_Fordwards+0x50>
+ 802b144:	2b01      	cmp	r3, #1
+ 802b146:	d002      	beq.n	802b14e <Move_Plane_Manual_Sub_Func_Fordwards+0x1a>
+ 802b148:	2b02      	cmp	r3, #2
+ 802b14a:	d008      	beq.n	802b15e <Move_Plane_Manual_Sub_Func_Fordwards+0x2a>
+ 802b14c:	e01a      	b.n	802b184 <Move_Plane_Manual_Sub_Func_Fordwards+0x50>
+	  {
+		  case Forward_Attitude_Judge:
+
+			  Plane_Angle_Judge();
+ 802b14e:	f7ff fac1 	bl	802a6d4 <Plane_Angle_Judge>
+			  Forward_Flag_Robot_Manual++;
+ 802b152:	4b0f      	ldr	r3, [pc, #60]	@ (802b190 <Move_Plane_Manual_Sub_Func_Fordwards+0x5c>)
+ 802b154:	681b      	ldr	r3, [r3, #0]
+ 802b156:	3301      	adds	r3, #1
+ 802b158:	4a0d      	ldr	r2, [pc, #52]	@ (802b190 <Move_Plane_Manual_Sub_Func_Fordwards+0x5c>)
+ 802b15a:	6013      	str	r3, [r2, #0]
+			  break;
+ 802b15c:	e015      	b.n	802b18a <Move_Plane_Manual_Sub_Func_Fordwards+0x56>
+		  case Forward_Attitude_Adjust:
+			  Forward_Flag_Robot_Manual++;
+ 802b15e:	4b0c      	ldr	r3, [pc, #48]	@ (802b190 <Move_Plane_Manual_Sub_Func_Fordwards+0x5c>)
+ 802b160:	681b      	ldr	r3, [r3, #0]
+ 802b162:	3301      	adds	r3, #1
+ 802b164:	4a0a      	ldr	r2, [pc, #40]	@ (802b190 <Move_Plane_Manual_Sub_Func_Fordwards+0x5c>)
+ 802b166:	6013      	str	r3, [r2, #0]
+			  break;
+ 802b168:	e00f      	b.n	802b18a <Move_Plane_Manual_Sub_Func_Fordwards+0x56>
+		  case Forward_Motion:
+			  Move_Plane_Task_Fordwards_Do_Update(Robot_Speed_Base, CV_Robot_Deri_Angle_Deg_Plane);
+ 802b16a:	4b0a      	ldr	r3, [pc, #40]	@ (802b194 <Move_Plane_Manual_Sub_Func_Fordwards+0x60>)
+ 802b16c:	ed93 7b00 	vldr	d7, [r3]
+ 802b170:	4b09      	ldr	r3, [pc, #36]	@ (802b198 <Move_Plane_Manual_Sub_Func_Fordwards+0x64>)
+ 802b172:	ed93 6b00 	vldr	d6, [r3]
+ 802b176:	eeb0 1b46 	vmov.f64	d1, d6
+ 802b17a:	eeb0 0b47 	vmov.f64	d0, d7
+ 802b17e:	f001 fbcd 	bl	802c91c <Move_Plane_Task_Fordwards_Do_Update>
+			  break;
+ 802b182:	e002      	b.n	802b18a <Move_Plane_Manual_Sub_Func_Fordwards+0x56>
+		  default:
+			  HALT_State_Do();
+ 802b184:	f004 fff0 	bl	8030168 <HALT_State_Do>
+			  break;
+ 802b188:	bf00      	nop
+	  }
+}
+ 802b18a:	bf00      	nop
+ 802b18c:	bd80      	pop	{r7, pc}
+ 802b18e:	bf00      	nop
+ 802b190:	24000098 	.word	0x24000098
+ 802b194:	2400a758 	.word	0x2400a758
+ 802b198:	2400a6d8 	.word	0x2400a6d8
+
+0802b19c <Move_Plane_Manual_Sub_Func_Backwards>:
+
+void Move_Plane_Manual_Sub_Func_Backwards()
+{
+ 802b19c:	b580      	push	{r7, lr}
+ 802b19e:	af00      	add	r7, sp, #0
+	  switch (Forward_Flag_Robot_Manual)
+ 802b1a0:	4b15      	ldr	r3, [pc, #84]	@ (802b1f8 <Move_Plane_Manual_Sub_Func_Backwards+0x5c>)
+ 802b1a2:	681b      	ldr	r3, [r3, #0]
+ 802b1a4:	2b03      	cmp	r3, #3
+ 802b1a6:	d014      	beq.n	802b1d2 <Move_Plane_Manual_Sub_Func_Backwards+0x36>
+ 802b1a8:	2b03      	cmp	r3, #3
+ 802b1aa:	dc1f      	bgt.n	802b1ec <Move_Plane_Manual_Sub_Func_Backwards+0x50>
+ 802b1ac:	2b01      	cmp	r3, #1
+ 802b1ae:	d002      	beq.n	802b1b6 <Move_Plane_Manual_Sub_Func_Backwards+0x1a>
+ 802b1b0:	2b02      	cmp	r3, #2
+ 802b1b2:	d008      	beq.n	802b1c6 <Move_Plane_Manual_Sub_Func_Backwards+0x2a>
+ 802b1b4:	e01a      	b.n	802b1ec <Move_Plane_Manual_Sub_Func_Backwards+0x50>
+	  {
+		  case Forward_Attitude_Judge:
+			  Plane_Angle_Judge();
+ 802b1b6:	f7ff fa8d 	bl	802a6d4 <Plane_Angle_Judge>
+			  Forward_Flag_Robot_Manual++;
+ 802b1ba:	4b0f      	ldr	r3, [pc, #60]	@ (802b1f8 <Move_Plane_Manual_Sub_Func_Backwards+0x5c>)
+ 802b1bc:	681b      	ldr	r3, [r3, #0]
+ 802b1be:	3301      	adds	r3, #1
+ 802b1c0:	4a0d      	ldr	r2, [pc, #52]	@ (802b1f8 <Move_Plane_Manual_Sub_Func_Backwards+0x5c>)
+ 802b1c2:	6013      	str	r3, [r2, #0]
+			  break;
+ 802b1c4:	e015      	b.n	802b1f2 <Move_Plane_Manual_Sub_Func_Backwards+0x56>
+		  case Forward_Attitude_Adjust:
+			  Forward_Flag_Robot_Manual++;
+ 802b1c6:	4b0c      	ldr	r3, [pc, #48]	@ (802b1f8 <Move_Plane_Manual_Sub_Func_Backwards+0x5c>)
+ 802b1c8:	681b      	ldr	r3, [r3, #0]
+ 802b1ca:	3301      	adds	r3, #1
+ 802b1cc:	4a0a      	ldr	r2, [pc, #40]	@ (802b1f8 <Move_Plane_Manual_Sub_Func_Backwards+0x5c>)
+ 802b1ce:	6013      	str	r3, [r2, #0]
+			  break;
+ 802b1d0:	e00f      	b.n	802b1f2 <Move_Plane_Manual_Sub_Func_Backwards+0x56>
+		  case Forward_Motion:
+//			  Move_Plane_Task_Fordwards_Do();
+			  Move_Plane_Task_Backwards_Distance_Do_Update(Robot_Speed_Base, CV_Robot_Deri_Angle_Deg_Plane);
+ 802b1d2:	4b0a      	ldr	r3, [pc, #40]	@ (802b1fc <Move_Plane_Manual_Sub_Func_Backwards+0x60>)
+ 802b1d4:	ed93 7b00 	vldr	d7, [r3]
+ 802b1d8:	4b09      	ldr	r3, [pc, #36]	@ (802b200 <Move_Plane_Manual_Sub_Func_Backwards+0x64>)
+ 802b1da:	ed93 6b00 	vldr	d6, [r3]
+ 802b1de:	eeb0 1b46 	vmov.f64	d1, d6
+ 802b1e2:	eeb0 0b47 	vmov.f64	d0, d7
+ 802b1e6:	f001 fc37 	bl	802ca58 <Move_Plane_Task_Backwards_Distance_Do_Update>
+			  break;
+ 802b1ea:	e002      	b.n	802b1f2 <Move_Plane_Manual_Sub_Func_Backwards+0x56>
+		  default:
+			  HALT_State_Do();
+ 802b1ec:	f004 ffbc 	bl	8030168 <HALT_State_Do>
+			  break;
+ 802b1f0:	bf00      	nop
+	  }
+//	  UltraStopReverse(Forward_Flag_Robot_Manual);
+}
+ 802b1f2:	bf00      	nop
+ 802b1f4:	bd80      	pop	{r7, pc}
+ 802b1f6:	bf00      	nop
+ 802b1f8:	24000098 	.word	0x24000098
+ 802b1fc:	2400a758 	.word	0x2400a758
+ 802b200:	2400a6d8 	.word	0x2400a6d8
+ 802b204:	00000000 	.word	0x00000000
+
+0802b208 <Plane_X_Backward_Time_Calculation>:
+
+
+
+
+void Plane_X_Backward_Time_Calculation(double *Num)
+{
+ 802b208:	b480      	push	{r7}
+ 802b20a:	b083      	sub	sp, #12
+ 802b20c:	af00      	add	r7, sp, #0
+ 802b20e:	6078      	str	r0, [r7, #4]
+	*Num=((double)GV_Robot_Length_Homework*100)/GV_Robot_Back_Distance;
+ 802b210:	4b0d      	ldr	r3, [pc, #52]	@ (802b248 <Plane_X_Backward_Time_Calculation+0x40>)
+ 802b212:	681b      	ldr	r3, [r3, #0]
+ 802b214:	ee07 3a90 	vmov	s15, r3
+ 802b218:	eeb8 7be7 	vcvt.f64.s32	d7, s15
+ 802b21c:	ed9f 6b08 	vldr	d6, [pc, #32]	@ 802b240 <Plane_X_Backward_Time_Calculation+0x38>
+ 802b220:	ee27 5b06 	vmul.f64	d5, d7, d6
+ 802b224:	4b09      	ldr	r3, [pc, #36]	@ (802b24c <Plane_X_Backward_Time_Calculation+0x44>)
+ 802b226:	ed93 6b00 	vldr	d6, [r3]
+ 802b22a:	ee85 7b06 	vdiv.f64	d7, d5, d6
+ 802b22e:	687b      	ldr	r3, [r7, #4]
+ 802b230:	ed83 7b00 	vstr	d7, [r3]
+}
+ 802b234:	bf00      	nop
+ 802b236:	370c      	adds	r7, #12
+ 802b238:	46bd      	mov	sp, r7
+ 802b23a:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 802b23e:	4770      	bx	lr
+ 802b240:	00000000 	.word	0x00000000
+ 802b244:	40590000 	.word	0x40590000
+ 802b248:	2400a748 	.word	0x2400a748
+ 802b24c:	2400a728 	.word	0x2400a728
+
+0802b250 <Plane_X_Backward_Time_Calculation_Continuous>:
+void Plane_X_Backward_Time_Calculation_Continuous(int *Time)
+{
+ 802b250:	b480      	push	{r7}
+ 802b252:	b083      	sub	sp, #12
+ 802b254:	af00      	add	r7, sp, #0
+ 802b256:	6078      	str	r0, [r7, #4]
+	*Time=((double)GV_Robot_Length_Homework)/GV_Robot_Back_Speed*60*500;//长度/后退速度=分钟      分钟=60*500毫秒
+ 802b258:	4b13      	ldr	r3, [pc, #76]	@ (802b2a8 <Plane_X_Backward_Time_Calculation_Continuous+0x58>)
+ 802b25a:	681b      	ldr	r3, [r3, #0]
+ 802b25c:	ee07 3a90 	vmov	s15, r3
+ 802b260:	eeb8 5be7 	vcvt.f64.s32	d5, s15
+ 802b264:	4b11      	ldr	r3, [pc, #68]	@ (802b2ac <Plane_X_Backward_Time_Calculation_Continuous+0x5c>)
+ 802b266:	ed93 6b00 	vldr	d6, [r3]
+ 802b26a:	ee85 7b06 	vdiv.f64	d7, d5, d6
+ 802b26e:	ed9f 6b0a 	vldr	d6, [pc, #40]	@ 802b298 <Plane_X_Backward_Time_Calculation_Continuous+0x48>
+ 802b272:	ee27 7b06 	vmul.f64	d7, d7, d6
+ 802b276:	ed9f 6b0a 	vldr	d6, [pc, #40]	@ 802b2a0 <Plane_X_Backward_Time_Calculation_Continuous+0x50>
+ 802b27a:	ee27 7b06 	vmul.f64	d7, d7, d6
+ 802b27e:	eefd 7bc7 	vcvt.s32.f64	s15, d7
+ 802b282:	ee17 2a90 	vmov	r2, s15
+ 802b286:	687b      	ldr	r3, [r7, #4]
+ 802b288:	601a      	str	r2, [r3, #0]
+}
+ 802b28a:	bf00      	nop
+ 802b28c:	370c      	adds	r7, #12
+ 802b28e:	46bd      	mov	sp, r7
+ 802b290:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 802b294:	4770      	bx	lr
+ 802b296:	bf00      	nop
+ 802b298:	00000000 	.word	0x00000000
+ 802b29c:	404e0000 	.word	0x404e0000
+ 802b2a0:	00000000 	.word	0x00000000
+ 802b2a4:	407f4000 	.word	0x407f4000
+ 802b2a8:	2400a748 	.word	0x2400a748
+ 802b2ac:	2400a730 	.word	0x2400a730
+
+0802b2b0 <Horizontal_X_Backward_Num_Calculation>:
+
+void Horizontal_X_Backward_Num_Calculation(double *Num)
+{
+ 802b2b0:	b480      	push	{r7}
+ 802b2b2:	b083      	sub	sp, #12
+ 802b2b4:	af00      	add	r7, sp, #0
+ 802b2b6:	6078      	str	r0, [r7, #4]
+	*Num=((double)GV_Robot_Length_Homework*100)/GV_Robot_Back_Distance;
+ 802b2b8:	4b0d      	ldr	r3, [pc, #52]	@ (802b2f0 <Horizontal_X_Backward_Num_Calculation+0x40>)
+ 802b2ba:	681b      	ldr	r3, [r3, #0]
+ 802b2bc:	ee07 3a90 	vmov	s15, r3
+ 802b2c0:	eeb8 7be7 	vcvt.f64.s32	d7, s15
+ 802b2c4:	ed9f 6b08 	vldr	d6, [pc, #32]	@ 802b2e8 <Horizontal_X_Backward_Num_Calculation+0x38>
+ 802b2c8:	ee27 5b06 	vmul.f64	d5, d7, d6
+ 802b2cc:	4b09      	ldr	r3, [pc, #36]	@ (802b2f4 <Horizontal_X_Backward_Num_Calculation+0x44>)
+ 802b2ce:	ed93 6b00 	vldr	d6, [r3]
+ 802b2d2:	ee85 7b06 	vdiv.f64	d7, d5, d6
+ 802b2d6:	687b      	ldr	r3, [r7, #4]
+ 802b2d8:	ed83 7b00 	vstr	d7, [r3]
+}
+ 802b2dc:	bf00      	nop
+ 802b2de:	370c      	adds	r7, #12
+ 802b2e0:	46bd      	mov	sp, r7
+ 802b2e2:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 802b2e6:	4770      	bx	lr
+ 802b2e8:	00000000 	.word	0x00000000
+ 802b2ec:	40590000 	.word	0x40590000
+ 802b2f0:	2400a748 	.word	0x2400a748
+ 802b2f4:	2400a728 	.word	0x2400a728
+
+0802b2f8 <Horizontal_X_Backward_Time_Calculation_Continuous>:
+
+void Horizontal_X_Backward_Time_Calculation_Continuous(int *Time)
+{
+ 802b2f8:	b480      	push	{r7}
+ 802b2fa:	b083      	sub	sp, #12
+ 802b2fc:	af00      	add	r7, sp, #0
+ 802b2fe:	6078      	str	r0, [r7, #4]
+	*Time=((double)GV_Robot_Length_Homework)/GV_Robot_Back_Speed*60*500;//长度/后退速度=分钟      分钟=60*500毫秒
+ 802b300:	4b13      	ldr	r3, [pc, #76]	@ (802b350 <Horizontal_X_Backward_Time_Calculation_Continuous+0x58>)
+ 802b302:	681b      	ldr	r3, [r3, #0]
+ 802b304:	ee07 3a90 	vmov	s15, r3
+ 802b308:	eeb8 5be7 	vcvt.f64.s32	d5, s15
+ 802b30c:	4b11      	ldr	r3, [pc, #68]	@ (802b354 <Horizontal_X_Backward_Time_Calculation_Continuous+0x5c>)
+ 802b30e:	ed93 6b00 	vldr	d6, [r3]
+ 802b312:	ee85 7b06 	vdiv.f64	d7, d5, d6
+ 802b316:	ed9f 6b0a 	vldr	d6, [pc, #40]	@ 802b340 <Horizontal_X_Backward_Time_Calculation_Continuous+0x48>
+ 802b31a:	ee27 7b06 	vmul.f64	d7, d7, d6
+ 802b31e:	ed9f 6b0a 	vldr	d6, [pc, #40]	@ 802b348 <Horizontal_X_Backward_Time_Calculation_Continuous+0x50>
+ 802b322:	ee27 7b06 	vmul.f64	d7, d7, d6
+ 802b326:	eefd 7bc7 	vcvt.s32.f64	s15, d7
+ 802b32a:	ee17 2a90 	vmov	r2, s15
+ 802b32e:	687b      	ldr	r3, [r7, #4]
+ 802b330:	601a      	str	r2, [r3, #0]
+}
+ 802b332:	bf00      	nop
+ 802b334:	370c      	adds	r7, #12
+ 802b336:	46bd      	mov	sp, r7
+ 802b338:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 802b33c:	4770      	bx	lr
+ 802b33e:	bf00      	nop
+ 802b340:	00000000 	.word	0x00000000
+ 802b344:	404e0000 	.word	0x404e0000
+ 802b348:	00000000 	.word	0x00000000
+ 802b34c:	407f4000 	.word	0x407f4000
+ 802b350:	2400a748 	.word	0x2400a748
+ 802b354:	2400a730 	.word	0x2400a730
+
+0802b358 <Plane_Y_Lane_Change_Time_Calculation>:
+
+
+
+void Plane_Y_Lane_Change_Time_Calculation(int *Num)
+{
+ 802b358:	b480      	push	{r7}
+ 802b35a:	b083      	sub	sp, #12
+ 802b35c:	af00      	add	r7, sp, #0
+ 802b35e:	6078      	str	r0, [r7, #4]
+	*Num=GV_Robot_Width_Homework*100/GV_Robot_Change_Lane_Distance;
+ 802b360:	4b0c      	ldr	r3, [pc, #48]	@ (802b394 <Plane_Y_Lane_Change_Time_Calculation+0x3c>)
+ 802b362:	681b      	ldr	r3, [r3, #0]
+ 802b364:	2264      	movs	r2, #100	@ 0x64
+ 802b366:	fb02 f303 	mul.w	r3, r2, r3
+ 802b36a:	ee07 3a90 	vmov	s15, r3
+ 802b36e:	eeb8 5be7 	vcvt.f64.s32	d5, s15
+ 802b372:	4b09      	ldr	r3, [pc, #36]	@ (802b398 <Plane_Y_Lane_Change_Time_Calculation+0x40>)
+ 802b374:	ed93 6b00 	vldr	d6, [r3]
+ 802b378:	ee85 7b06 	vdiv.f64	d7, d5, d6
+ 802b37c:	eefd 7bc7 	vcvt.s32.f64	s15, d7
+ 802b380:	ee17 2a90 	vmov	r2, s15
+ 802b384:	687b      	ldr	r3, [r7, #4]
+ 802b386:	601a      	str	r2, [r3, #0]
+}
+ 802b388:	bf00      	nop
+ 802b38a:	370c      	adds	r7, #12
+ 802b38c:	46bd      	mov	sp, r7
+ 802b38e:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 802b392:	4770      	bx	lr
+ 802b394:	2400a74c 	.word	0x2400a74c
+ 802b398:	2400a708 	.word	0x2400a708
+
+0802b39c <Horizontal_Y_Lane_Change_Time_Calculation>:
+
+void Horizontal_Y_Lane_Change_Time_Calculation(int *Num)
+{
+ 802b39c:	b480      	push	{r7}
+ 802b39e:	b083      	sub	sp, #12
+ 802b3a0:	af00      	add	r7, sp, #0
+ 802b3a2:	6078      	str	r0, [r7, #4]
+	*Num=GV_Robot_Width_Homework*100/GV_Robot_Change_Lane_Distance;
+ 802b3a4:	4b0c      	ldr	r3, [pc, #48]	@ (802b3d8 <Horizontal_Y_Lane_Change_Time_Calculation+0x3c>)
+ 802b3a6:	681b      	ldr	r3, [r3, #0]
+ 802b3a8:	2264      	movs	r2, #100	@ 0x64
+ 802b3aa:	fb02 f303 	mul.w	r3, r2, r3
+ 802b3ae:	ee07 3a90 	vmov	s15, r3
+ 802b3b2:	eeb8 5be7 	vcvt.f64.s32	d5, s15
+ 802b3b6:	4b09      	ldr	r3, [pc, #36]	@ (802b3dc <Horizontal_Y_Lane_Change_Time_Calculation+0x40>)
+ 802b3b8:	ed93 6b00 	vldr	d6, [r3]
+ 802b3bc:	ee85 7b06 	vdiv.f64	d7, d5, d6
+ 802b3c0:	eefd 7bc7 	vcvt.s32.f64	s15, d7
+ 802b3c4:	ee17 2a90 	vmov	r2, s15
+ 802b3c8:	687b      	ldr	r3, [r7, #4]
+ 802b3ca:	601a      	str	r2, [r3, #0]
+}
+ 802b3cc:	bf00      	nop
+ 802b3ce:	370c      	adds	r7, #12
+ 802b3d0:	46bd      	mov	sp, r7
+ 802b3d2:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 802b3d6:	4770      	bx	lr
+ 802b3d8:	2400a74c 	.word	0x2400a74c
+ 802b3dc:	2400a708 	.word	0x2400a708
+
+0802b3e0 <Plane_Change_Road_Backward_Num_Calculation>:
+
+
+void Plane_Change_Road_Backward_Num_Calculation(double *Num)
+{
+ 802b3e0:	b480      	push	{r7}
+ 802b3e2:	b083      	sub	sp, #12
+ 802b3e4:	af00      	add	r7, sp, #0
+ 802b3e6:	6078      	str	r0, [r7, #4]
+	*Num=((double)GV_Robot_Change_Lane_Distance)/GV_Robot_Back_Distance;
+ 802b3e8:	4b08      	ldr	r3, [pc, #32]	@ (802b40c <Plane_Change_Road_Backward_Num_Calculation+0x2c>)
+ 802b3ea:	ed93 5b00 	vldr	d5, [r3]
+ 802b3ee:	4b08      	ldr	r3, [pc, #32]	@ (802b410 <Plane_Change_Road_Backward_Num_Calculation+0x30>)
+ 802b3f0:	ed93 6b00 	vldr	d6, [r3]
+ 802b3f4:	ee85 7b06 	vdiv.f64	d7, d5, d6
+ 802b3f8:	687b      	ldr	r3, [r7, #4]
+ 802b3fa:	ed83 7b00 	vstr	d7, [r3]
+}
+ 802b3fe:	bf00      	nop
+ 802b400:	370c      	adds	r7, #12
+ 802b402:	46bd      	mov	sp, r7
+ 802b404:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 802b408:	4770      	bx	lr
+ 802b40a:	bf00      	nop
+ 802b40c:	2400a708 	.word	0x2400a708
+ 802b410:	2400a728 	.word	0x2400a728
+ 802b414:	00000000 	.word	0x00000000
+
+0802b418 <Plane_Change_Road_Backward_Time_Calculation_Continuous>:
+
+void Plane_Change_Road_Backward_Time_Calculation_Continuous(int *Time)
+{
+ 802b418:	b480      	push	{r7}
+ 802b41a:	b083      	sub	sp, #12
+ 802b41c:	af00      	add	r7, sp, #0
+ 802b41e:	6078      	str	r0, [r7, #4]
+	*Time=((double)GV_Robot_Change_Lane_Distance/100)/GV_Robot_Back_Speed*60*500;//换道距离/后退速度=分钟      分钟=60*500毫秒
+ 802b420:	4b15      	ldr	r3, [pc, #84]	@ (802b478 <Plane_Change_Road_Backward_Time_Calculation_Continuous+0x60>)
+ 802b422:	ed93 7b00 	vldr	d7, [r3]
+ 802b426:	ed9f 6b0e 	vldr	d6, [pc, #56]	@ 802b460 <Plane_Change_Road_Backward_Time_Calculation_Continuous+0x48>
+ 802b42a:	ee87 5b06 	vdiv.f64	d5, d7, d6
+ 802b42e:	4b13      	ldr	r3, [pc, #76]	@ (802b47c <Plane_Change_Road_Backward_Time_Calculation_Continuous+0x64>)
+ 802b430:	ed93 6b00 	vldr	d6, [r3]
+ 802b434:	ee85 7b06 	vdiv.f64	d7, d5, d6
+ 802b438:	ed9f 6b0b 	vldr	d6, [pc, #44]	@ 802b468 <Plane_Change_Road_Backward_Time_Calculation_Continuous+0x50>
+ 802b43c:	ee27 7b06 	vmul.f64	d7, d7, d6
+ 802b440:	ed9f 6b0b 	vldr	d6, [pc, #44]	@ 802b470 <Plane_Change_Road_Backward_Time_Calculation_Continuous+0x58>
+ 802b444:	ee27 7b06 	vmul.f64	d7, d7, d6
+ 802b448:	eefd 7bc7 	vcvt.s32.f64	s15, d7
+ 802b44c:	ee17 2a90 	vmov	r2, s15
+ 802b450:	687b      	ldr	r3, [r7, #4]
+ 802b452:	601a      	str	r2, [r3, #0]
+}
+ 802b454:	bf00      	nop
+ 802b456:	370c      	adds	r7, #12
+ 802b458:	46bd      	mov	sp, r7
+ 802b45a:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 802b45e:	4770      	bx	lr
+ 802b460:	00000000 	.word	0x00000000
+ 802b464:	40590000 	.word	0x40590000
+ 802b468:	00000000 	.word	0x00000000
+ 802b46c:	404e0000 	.word	0x404e0000
+ 802b470:	00000000 	.word	0x00000000
+ 802b474:	407f4000 	.word	0x407f4000
+ 802b478:	2400a708 	.word	0x2400a708
+ 802b47c:	2400a730 	.word	0x2400a730
+
+0802b480 <Horizontal_Change_Road_Backward_Num_Calculation>:
+
+
+
+void Horizontal_Change_Road_Backward_Num_Calculation(double *Num)
+{
+ 802b480:	b480      	push	{r7}
+ 802b482:	b083      	sub	sp, #12
+ 802b484:	af00      	add	r7, sp, #0
+ 802b486:	6078      	str	r0, [r7, #4]
+	*Num=((double)GV_Robot_Change_Lane_Distance)/GV_Robot_Back_Distance;
+ 802b488:	4b08      	ldr	r3, [pc, #32]	@ (802b4ac <Horizontal_Change_Road_Backward_Num_Calculation+0x2c>)
+ 802b48a:	ed93 5b00 	vldr	d5, [r3]
+ 802b48e:	4b08      	ldr	r3, [pc, #32]	@ (802b4b0 <Horizontal_Change_Road_Backward_Num_Calculation+0x30>)
+ 802b490:	ed93 6b00 	vldr	d6, [r3]
+ 802b494:	ee85 7b06 	vdiv.f64	d7, d5, d6
+ 802b498:	687b      	ldr	r3, [r7, #4]
+ 802b49a:	ed83 7b00 	vstr	d7, [r3]
+}
+ 802b49e:	bf00      	nop
+ 802b4a0:	370c      	adds	r7, #12
+ 802b4a2:	46bd      	mov	sp, r7
+ 802b4a4:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 802b4a8:	4770      	bx	lr
+ 802b4aa:	bf00      	nop
+ 802b4ac:	2400a708 	.word	0x2400a708
+ 802b4b0:	2400a728 	.word	0x2400a728
+ 802b4b4:	00000000 	.word	0x00000000
+
+0802b4b8 <Horizontal_Change_Road_Backward_Time_Calculation_Continuous>:
+
+void Horizontal_Change_Road_Backward_Time_Calculation_Continuous(int *Time)
+{
+ 802b4b8:	b480      	push	{r7}
+ 802b4ba:	b083      	sub	sp, #12
+ 802b4bc:	af00      	add	r7, sp, #0
+ 802b4be:	6078      	str	r0, [r7, #4]
+	*Time=((double)GV_Robot_Change_Lane_Distance/100)/GV_Robot_Back_Speed*60*500;//换道距离/后退速度=分钟      分钟=60*500毫秒
+ 802b4c0:	4b15      	ldr	r3, [pc, #84]	@ (802b518 <Horizontal_Change_Road_Backward_Time_Calculation_Continuous+0x60>)
+ 802b4c2:	ed93 7b00 	vldr	d7, [r3]
+ 802b4c6:	ed9f 6b0e 	vldr	d6, [pc, #56]	@ 802b500 <Horizontal_Change_Road_Backward_Time_Calculation_Continuous+0x48>
+ 802b4ca:	ee87 5b06 	vdiv.f64	d5, d7, d6
+ 802b4ce:	4b13      	ldr	r3, [pc, #76]	@ (802b51c <Horizontal_Change_Road_Backward_Time_Calculation_Continuous+0x64>)
+ 802b4d0:	ed93 6b00 	vldr	d6, [r3]
+ 802b4d4:	ee85 7b06 	vdiv.f64	d7, d5, d6
+ 802b4d8:	ed9f 6b0b 	vldr	d6, [pc, #44]	@ 802b508 <Horizontal_Change_Road_Backward_Time_Calculation_Continuous+0x50>
+ 802b4dc:	ee27 7b06 	vmul.f64	d7, d7, d6
+ 802b4e0:	ed9f 6b0b 	vldr	d6, [pc, #44]	@ 802b510 <Horizontal_Change_Road_Backward_Time_Calculation_Continuous+0x58>
+ 802b4e4:	ee27 7b06 	vmul.f64	d7, d7, d6
+ 802b4e8:	eefd 7bc7 	vcvt.s32.f64	s15, d7
+ 802b4ec:	ee17 2a90 	vmov	r2, s15
+ 802b4f0:	687b      	ldr	r3, [r7, #4]
+ 802b4f2:	601a      	str	r2, [r3, #0]
+}
+ 802b4f4:	bf00      	nop
+ 802b4f6:	370c      	adds	r7, #12
+ 802b4f8:	46bd      	mov	sp, r7
+ 802b4fa:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 802b4fe:	4770      	bx	lr
+ 802b500:	00000000 	.word	0x00000000
+ 802b504:	40590000 	.word	0x40590000
+ 802b508:	00000000 	.word	0x00000000
+ 802b50c:	404e0000 	.word	0x404e0000
+ 802b510:	00000000 	.word	0x00000000
+ 802b514:	407f4000 	.word	0x407f4000
+ 802b518:	2400a708 	.word	0x2400a708
+ 802b51c:	2400a730 	.word	0x2400a730
+
+0802b520 <Move_Horizontal_Manual_Sub_Func_Forwards>:
+
+
+
+
+void Move_Horizontal_Manual_Sub_Func_Forwards()
+{
+ 802b520:	b580      	push	{r7, lr}
+ 802b522:	af00      	add	r7, sp, #0
+	  switch (Forward_Flag_Robot_Manual)
+ 802b524:	4b1e      	ldr	r3, [pc, #120]	@ (802b5a0 <Move_Horizontal_Manual_Sub_Func_Forwards+0x80>)
+ 802b526:	681b      	ldr	r3, [r3, #0]
+ 802b528:	2b03      	cmp	r3, #3
+ 802b52a:	d024      	beq.n	802b576 <Move_Horizontal_Manual_Sub_Func_Forwards+0x56>
+ 802b52c:	2b03      	cmp	r3, #3
+ 802b52e:	dc31      	bgt.n	802b594 <Move_Horizontal_Manual_Sub_Func_Forwards+0x74>
+ 802b530:	2b01      	cmp	r3, #1
+ 802b532:	d002      	beq.n	802b53a <Move_Horizontal_Manual_Sub_Func_Forwards+0x1a>
+ 802b534:	2b02      	cmp	r3, #2
+ 802b536:	d008      	beq.n	802b54a <Move_Horizontal_Manual_Sub_Func_Forwards+0x2a>
+ 802b538:	e02c      	b.n	802b594 <Move_Horizontal_Manual_Sub_Func_Forwards+0x74>
+	  {
+		  case Forward_Attitude_Judge:
+			  Horiz_Angle_Judge_4_Direction();
+ 802b53a:	f000 f97d 	bl	802b838 <Horiz_Angle_Judge_4_Direction>
+			  Forward_Flag_Robot_Manual++;
+ 802b53e:	4b18      	ldr	r3, [pc, #96]	@ (802b5a0 <Move_Horizontal_Manual_Sub_Func_Forwards+0x80>)
+ 802b540:	681b      	ldr	r3, [r3, #0]
+ 802b542:	3301      	adds	r3, #1
+ 802b544:	4a16      	ldr	r2, [pc, #88]	@ (802b5a0 <Move_Horizontal_Manual_Sub_Func_Forwards+0x80>)
+ 802b546:	6013      	str	r3, [r2, #0]
+			  break;
+ 802b548:	e027      	b.n	802b59a <Move_Horizontal_Manual_Sub_Func_Forwards+0x7a>
+		  case Forward_Attitude_Adjust:
+			  Robot_Posture_Adjus_Gravity();
+ 802b54a:	f000 fc71 	bl	802be30 <Robot_Posture_Adjus_Gravity>
+			  if(Angle_Error_LLL<Error_Cont_Thresh)
+ 802b54e:	4b15      	ldr	r3, [pc, #84]	@ (802b5a4 <Move_Horizontal_Manual_Sub_Func_Forwards+0x84>)
+ 802b550:	ed93 6b00 	vldr	d6, [r3]
+ 802b554:	4b14      	ldr	r3, [pc, #80]	@ (802b5a8 <Move_Horizontal_Manual_Sub_Func_Forwards+0x88>)
+ 802b556:	ed93 7b00 	vldr	d7, [r3]
+ 802b55a:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802b55e:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802b562:	d400      	bmi.n	802b566 <Move_Horizontal_Manual_Sub_Func_Forwards+0x46>
+			  {
+				Forward_Flag_Robot_Manual++;
+				Robot_Halt_Mode();
+			  }
+			  break;
+ 802b564:	e019      	b.n	802b59a <Move_Horizontal_Manual_Sub_Func_Forwards+0x7a>
+				Forward_Flag_Robot_Manual++;
+ 802b566:	4b0e      	ldr	r3, [pc, #56]	@ (802b5a0 <Move_Horizontal_Manual_Sub_Func_Forwards+0x80>)
+ 802b568:	681b      	ldr	r3, [r3, #0]
+ 802b56a:	3301      	adds	r3, #1
+ 802b56c:	4a0c      	ldr	r2, [pc, #48]	@ (802b5a0 <Move_Horizontal_Manual_Sub_Func_Forwards+0x80>)
+ 802b56e:	6013      	str	r3, [r2, #0]
+				Robot_Halt_Mode();
+ 802b570:	f7fe f986 	bl	8029880 <Robot_Halt_Mode>
+			  break;
+ 802b574:	e011      	b.n	802b59a <Move_Horizontal_Manual_Sub_Func_Forwards+0x7a>
+		  case Forward_Motion:
+			  Horiz_Angle_Judge_4_Direction();
+ 802b576:	f000 f95f 	bl	802b838 <Horiz_Angle_Judge_4_Direction>
+			  Move_Horizontal_Vertical_Task_Forwards_Do_Forwards(Robot_Speed_Base, CV_Robot_Deri_Angle_Deg_Grity);
+ 802b57a:	4b0c      	ldr	r3, [pc, #48]	@ (802b5ac <Move_Horizontal_Manual_Sub_Func_Forwards+0x8c>)
+ 802b57c:	ed93 7b00 	vldr	d7, [r3]
+ 802b580:	4b0b      	ldr	r3, [pc, #44]	@ (802b5b0 <Move_Horizontal_Manual_Sub_Func_Forwards+0x90>)
+ 802b582:	ed93 6b00 	vldr	d6, [r3]
+ 802b586:	eeb0 1b46 	vmov.f64	d1, d6
+ 802b58a:	eeb0 0b47 	vmov.f64	d0, d7
+ 802b58e:	f000 fb77 	bl	802bc80 <Move_Horizontal_Vertical_Task_Forwards_Do_Forwards>
+			  break;
+ 802b592:	e002      	b.n	802b59a <Move_Horizontal_Manual_Sub_Func_Forwards+0x7a>
+		  default:
+			  HALT_State_Do();
+ 802b594:	f004 fde8 	bl	8030168 <HALT_State_Do>
+			  break;
+ 802b598:	bf00      	nop
+	  }
+}
+ 802b59a:	bf00      	nop
+ 802b59c:	bd80      	pop	{r7, pc}
+ 802b59e:	bf00      	nop
+ 802b5a0:	24000098 	.word	0x24000098
+ 802b5a4:	2400a9e8 	.word	0x2400a9e8
+ 802b5a8:	24000090 	.word	0x24000090
+ 802b5ac:	2400a758 	.word	0x2400a758
+ 802b5b0:	2400a6d0 	.word	0x2400a6d0
+
+0802b5b4 <Move_Horizontal_Manual_Sub_Func_Backwards>:
+
+
+void Move_Horizontal_Manual_Sub_Func_Backwards()
+{
+ 802b5b4:	b580      	push	{r7, lr}
+ 802b5b6:	af00      	add	r7, sp, #0
+	  switch (Forward_Flag_Robot_Manual)
+ 802b5b8:	4b1e      	ldr	r3, [pc, #120]	@ (802b634 <Move_Horizontal_Manual_Sub_Func_Backwards+0x80>)
+ 802b5ba:	681b      	ldr	r3, [r3, #0]
+ 802b5bc:	2b03      	cmp	r3, #3
+ 802b5be:	d024      	beq.n	802b60a <Move_Horizontal_Manual_Sub_Func_Backwards+0x56>
+ 802b5c0:	2b03      	cmp	r3, #3
+ 802b5c2:	dc31      	bgt.n	802b628 <Move_Horizontal_Manual_Sub_Func_Backwards+0x74>
+ 802b5c4:	2b01      	cmp	r3, #1
+ 802b5c6:	d002      	beq.n	802b5ce <Move_Horizontal_Manual_Sub_Func_Backwards+0x1a>
+ 802b5c8:	2b02      	cmp	r3, #2
+ 802b5ca:	d008      	beq.n	802b5de <Move_Horizontal_Manual_Sub_Func_Backwards+0x2a>
+ 802b5cc:	e02c      	b.n	802b628 <Move_Horizontal_Manual_Sub_Func_Backwards+0x74>
+	  {
+		  case Forward_Attitude_Judge:
+			  Horiz_Angle_Judge_4_Direction();
+ 802b5ce:	f000 f933 	bl	802b838 <Horiz_Angle_Judge_4_Direction>
+			  Forward_Flag_Robot_Manual++;
+ 802b5d2:	4b18      	ldr	r3, [pc, #96]	@ (802b634 <Move_Horizontal_Manual_Sub_Func_Backwards+0x80>)
+ 802b5d4:	681b      	ldr	r3, [r3, #0]
+ 802b5d6:	3301      	adds	r3, #1
+ 802b5d8:	4a16      	ldr	r2, [pc, #88]	@ (802b634 <Move_Horizontal_Manual_Sub_Func_Backwards+0x80>)
+ 802b5da:	6013      	str	r3, [r2, #0]
+			  break;
+ 802b5dc:	e027      	b.n	802b62e <Move_Horizontal_Manual_Sub_Func_Backwards+0x7a>
+		  case Forward_Attitude_Adjust:
+			  Robot_Posture_Adjus_Gravity();
+ 802b5de:	f000 fc27 	bl	802be30 <Robot_Posture_Adjus_Gravity>
+			  if(Angle_Error_LLL<Error_Cont_Thresh)
+ 802b5e2:	4b15      	ldr	r3, [pc, #84]	@ (802b638 <Move_Horizontal_Manual_Sub_Func_Backwards+0x84>)
+ 802b5e4:	ed93 6b00 	vldr	d6, [r3]
+ 802b5e8:	4b14      	ldr	r3, [pc, #80]	@ (802b63c <Move_Horizontal_Manual_Sub_Func_Backwards+0x88>)
+ 802b5ea:	ed93 7b00 	vldr	d7, [r3]
+ 802b5ee:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802b5f2:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802b5f6:	d400      	bmi.n	802b5fa <Move_Horizontal_Manual_Sub_Func_Backwards+0x46>
+			  {
+				Forward_Flag_Robot_Manual++;
+				Robot_Halt_Mode();
+			  }
+			  break;
+ 802b5f8:	e019      	b.n	802b62e <Move_Horizontal_Manual_Sub_Func_Backwards+0x7a>
+				Forward_Flag_Robot_Manual++;
+ 802b5fa:	4b0e      	ldr	r3, [pc, #56]	@ (802b634 <Move_Horizontal_Manual_Sub_Func_Backwards+0x80>)
+ 802b5fc:	681b      	ldr	r3, [r3, #0]
+ 802b5fe:	3301      	adds	r3, #1
+ 802b600:	4a0c      	ldr	r2, [pc, #48]	@ (802b634 <Move_Horizontal_Manual_Sub_Func_Backwards+0x80>)
+ 802b602:	6013      	str	r3, [r2, #0]
+				Robot_Halt_Mode();
+ 802b604:	f7fe f93c 	bl	8029880 <Robot_Halt_Mode>
+			  break;
+ 802b608:	e011      	b.n	802b62e <Move_Horizontal_Manual_Sub_Func_Backwards+0x7a>
+		  case Forward_Motion:
+			  Horiz_Angle_Judge_4_Direction();
+ 802b60a:	f000 f915 	bl	802b838 <Horiz_Angle_Judge_4_Direction>
+			  Move_Horizontal_Vertical_Task_Backwards_Do_Backward(Robot_Speed_Base,CV_Robot_Deri_Angle_Deg_Grity);
+ 802b60e:	4b0c      	ldr	r3, [pc, #48]	@ (802b640 <Move_Horizontal_Manual_Sub_Func_Backwards+0x8c>)
+ 802b610:	ed93 7b00 	vldr	d7, [r3]
+ 802b614:	4b0b      	ldr	r3, [pc, #44]	@ (802b644 <Move_Horizontal_Manual_Sub_Func_Backwards+0x90>)
+ 802b616:	ed93 6b00 	vldr	d6, [r3]
+ 802b61a:	eeb0 1b46 	vmov.f64	d1, d6
+ 802b61e:	eeb0 0b47 	vmov.f64	d0, d7
+ 802b622:	f001 f9c5 	bl	802c9b0 <Move_Horizontal_Vertical_Task_Backwards_Do_Backward>
+			  break;
+ 802b626:	e002      	b.n	802b62e <Move_Horizontal_Manual_Sub_Func_Backwards+0x7a>
+		  default:
+			  HALT_State_Do();
+ 802b628:	f004 fd9e 	bl	8030168 <HALT_State_Do>
+			  break;
+ 802b62c:	bf00      	nop
+	  }
+
+}
+ 802b62e:	bf00      	nop
+ 802b630:	bd80      	pop	{r7, pc}
+ 802b632:	bf00      	nop
+ 802b634:	24000098 	.word	0x24000098
+ 802b638:	2400a9e8 	.word	0x2400a9e8
+ 802b63c:	24000090 	.word	0x24000090
+ 802b640:	2400a758 	.word	0x2400a758
+ 802b644:	2400a6d0 	.word	0x2400a6d0
+
+0802b648 <Horiz_Angle_Judge>:
+
+
+void Horiz_Angle_Judge()
+{
+ 802b648:	b480      	push	{r7}
+ 802b64a:	b083      	sub	sp, #12
+ 802b64c:	af00      	add	r7, sp, #0
+	static int Left_Compensation_Count;
+	static int Right_Compensation_Count;
+
+	if(P_MK32->CH14_LT>300)
+ 802b64e:	4b72      	ldr	r3, [pc, #456]	@ (802b818 <Horiz_Angle_Judge+0x1d0>)
+ 802b650:	681b      	ldr	r3, [r3, #0]
+ 802b652:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 802b654:	f5b3 7f96 	cmp.w	r3, #300	@ 0x12c
+ 802b658:	dd1a      	ble.n	802b690 <Horiz_Angle_Judge+0x48>
+	{
+		Left_Compensation_Count++;
+ 802b65a:	4b70      	ldr	r3, [pc, #448]	@ (802b81c <Horiz_Angle_Judge+0x1d4>)
+ 802b65c:	681b      	ldr	r3, [r3, #0]
+ 802b65e:	3301      	adds	r3, #1
+ 802b660:	4a6e      	ldr	r2, [pc, #440]	@ (802b81c <Horiz_Angle_Judge+0x1d4>)
+ 802b662:	6013      	str	r3, [r2, #0]
+		if(Left_Compensation_Count>200)
+ 802b664:	4b6d      	ldr	r3, [pc, #436]	@ (802b81c <Horiz_Angle_Judge+0x1d4>)
+ 802b666:	681b      	ldr	r3, [r3, #0]
+ 802b668:	2bc8      	cmp	r3, #200	@ 0xc8
+ 802b66a:	dd07      	ble.n	802b67c <Horiz_Angle_Judge+0x34>
+		{
+			GV.Left_Compensation=GV.Left_Compensation+25;
+ 802b66c:	4b6c      	ldr	r3, [pc, #432]	@ (802b820 <Horiz_Angle_Judge+0x1d8>)
+ 802b66e:	681b      	ldr	r3, [r3, #0]
+ 802b670:	3319      	adds	r3, #25
+ 802b672:	4a6b      	ldr	r2, [pc, #428]	@ (802b820 <Horiz_Angle_Judge+0x1d8>)
+ 802b674:	6013      	str	r3, [r2, #0]
+			Left_Compensation_Count=0;
+ 802b676:	4b69      	ldr	r3, [pc, #420]	@ (802b81c <Horiz_Angle_Judge+0x1d4>)
+ 802b678:	2200      	movs	r2, #0
+ 802b67a:	601a      	str	r2, [r3, #0]
+		}
+		if(GV.Left_Compensation>1000)
+ 802b67c:	4b68      	ldr	r3, [pc, #416]	@ (802b820 <Horiz_Angle_Judge+0x1d8>)
+ 802b67e:	681b      	ldr	r3, [r3, #0]
+ 802b680:	f5b3 7f7a 	cmp.w	r3, #1000	@ 0x3e8
+ 802b684:	dd28      	ble.n	802b6d8 <Horiz_Angle_Judge+0x90>
+		{
+			GV.Left_Compensation=1000;
+ 802b686:	4b66      	ldr	r3, [pc, #408]	@ (802b820 <Horiz_Angle_Judge+0x1d8>)
+ 802b688:	f44f 727a 	mov.w	r2, #1000	@ 0x3e8
+ 802b68c:	601a      	str	r2, [r3, #0]
+ 802b68e:	e023      	b.n	802b6d8 <Horiz_Angle_Judge+0x90>
+		}
+	}
+	else if(P_MK32->CH14_LT<-300)
+ 802b690:	4b61      	ldr	r3, [pc, #388]	@ (802b818 <Horiz_Angle_Judge+0x1d0>)
+ 802b692:	681b      	ldr	r3, [r3, #0]
+ 802b694:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 802b696:	f513 7f96 	cmn.w	r3, #300	@ 0x12c
+ 802b69a:	da1a      	bge.n	802b6d2 <Horiz_Angle_Judge+0x8a>
+	{
+		Left_Compensation_Count--;
+ 802b69c:	4b5f      	ldr	r3, [pc, #380]	@ (802b81c <Horiz_Angle_Judge+0x1d4>)
+ 802b69e:	681b      	ldr	r3, [r3, #0]
+ 802b6a0:	3b01      	subs	r3, #1
+ 802b6a2:	4a5e      	ldr	r2, [pc, #376]	@ (802b81c <Horiz_Angle_Judge+0x1d4>)
+ 802b6a4:	6013      	str	r3, [r2, #0]
+		if(Left_Compensation_Count<-200)
+ 802b6a6:	4b5d      	ldr	r3, [pc, #372]	@ (802b81c <Horiz_Angle_Judge+0x1d4>)
+ 802b6a8:	681b      	ldr	r3, [r3, #0]
+ 802b6aa:	f113 0fc8 	cmn.w	r3, #200	@ 0xc8
+ 802b6ae:	da13      	bge.n	802b6d8 <Horiz_Angle_Judge+0x90>
+		{
+			GV.Left_Compensation=GV.Left_Compensation-25;
+ 802b6b0:	4b5b      	ldr	r3, [pc, #364]	@ (802b820 <Horiz_Angle_Judge+0x1d8>)
+ 802b6b2:	681b      	ldr	r3, [r3, #0]
+ 802b6b4:	3b19      	subs	r3, #25
+ 802b6b6:	4a5a      	ldr	r2, [pc, #360]	@ (802b820 <Horiz_Angle_Judge+0x1d8>)
+ 802b6b8:	6013      	str	r3, [r2, #0]
+			Left_Compensation_Count=0;
+ 802b6ba:	4b58      	ldr	r3, [pc, #352]	@ (802b81c <Horiz_Angle_Judge+0x1d4>)
+ 802b6bc:	2200      	movs	r2, #0
+ 802b6be:	601a      	str	r2, [r3, #0]
+			if(GV.Left_Compensation<-1000)
+ 802b6c0:	4b57      	ldr	r3, [pc, #348]	@ (802b820 <Horiz_Angle_Judge+0x1d8>)
+ 802b6c2:	681b      	ldr	r3, [r3, #0]
+ 802b6c4:	f513 7f7a 	cmn.w	r3, #1000	@ 0x3e8
+ 802b6c8:	da06      	bge.n	802b6d8 <Horiz_Angle_Judge+0x90>
+			{
+				GV.Left_Compensation=-1000;
+ 802b6ca:	4b55      	ldr	r3, [pc, #340]	@ (802b820 <Horiz_Angle_Judge+0x1d8>)
+ 802b6cc:	4a55      	ldr	r2, [pc, #340]	@ (802b824 <Horiz_Angle_Judge+0x1dc>)
+ 802b6ce:	601a      	str	r2, [r3, #0]
+ 802b6d0:	e002      	b.n	802b6d8 <Horiz_Angle_Judge+0x90>
+			}
+		}
+	}
+	else
+	{
+		Left_Compensation_Count=0;
+ 802b6d2:	4b52      	ldr	r3, [pc, #328]	@ (802b81c <Horiz_Angle_Judge+0x1d4>)
+ 802b6d4:	2200      	movs	r2, #0
+ 802b6d6:	601a      	str	r2, [r3, #0]
+	}
+
+	if(P_MK32->CH15_RT>300)
+ 802b6d8:	4b4f      	ldr	r3, [pc, #316]	@ (802b818 <Horiz_Angle_Judge+0x1d0>)
+ 802b6da:	681b      	ldr	r3, [r3, #0]
+ 802b6dc:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
+ 802b6de:	f5b3 7f96 	cmp.w	r3, #300	@ 0x12c
+ 802b6e2:	dd1a      	ble.n	802b71a <Horiz_Angle_Judge+0xd2>
+	{
+		Right_Compensation_Count++;
+ 802b6e4:	4b50      	ldr	r3, [pc, #320]	@ (802b828 <Horiz_Angle_Judge+0x1e0>)
+ 802b6e6:	681b      	ldr	r3, [r3, #0]
+ 802b6e8:	3301      	adds	r3, #1
+ 802b6ea:	4a4f      	ldr	r2, [pc, #316]	@ (802b828 <Horiz_Angle_Judge+0x1e0>)
+ 802b6ec:	6013      	str	r3, [r2, #0]
+		if(Right_Compensation_Count>200)
+ 802b6ee:	4b4e      	ldr	r3, [pc, #312]	@ (802b828 <Horiz_Angle_Judge+0x1e0>)
+ 802b6f0:	681b      	ldr	r3, [r3, #0]
+ 802b6f2:	2bc8      	cmp	r3, #200	@ 0xc8
+ 802b6f4:	dd35      	ble.n	802b762 <Horiz_Angle_Judge+0x11a>
+		{
+			GV.Right_Compensation=GV.Right_Compensation+25;
+ 802b6f6:	4b4a      	ldr	r3, [pc, #296]	@ (802b820 <Horiz_Angle_Judge+0x1d8>)
+ 802b6f8:	685b      	ldr	r3, [r3, #4]
+ 802b6fa:	3319      	adds	r3, #25
+ 802b6fc:	4a48      	ldr	r2, [pc, #288]	@ (802b820 <Horiz_Angle_Judge+0x1d8>)
+ 802b6fe:	6053      	str	r3, [r2, #4]
+			Right_Compensation_Count=0;
+ 802b700:	4b49      	ldr	r3, [pc, #292]	@ (802b828 <Horiz_Angle_Judge+0x1e0>)
+ 802b702:	2200      	movs	r2, #0
+ 802b704:	601a      	str	r2, [r3, #0]
+			if(GV.Right_Compensation>1000)
+ 802b706:	4b46      	ldr	r3, [pc, #280]	@ (802b820 <Horiz_Angle_Judge+0x1d8>)
+ 802b708:	685b      	ldr	r3, [r3, #4]
+ 802b70a:	f5b3 7f7a 	cmp.w	r3, #1000	@ 0x3e8
+ 802b70e:	dd28      	ble.n	802b762 <Horiz_Angle_Judge+0x11a>
+			{
+				GV.Right_Compensation=1000;
+ 802b710:	4b43      	ldr	r3, [pc, #268]	@ (802b820 <Horiz_Angle_Judge+0x1d8>)
+ 802b712:	f44f 727a 	mov.w	r2, #1000	@ 0x3e8
+ 802b716:	605a      	str	r2, [r3, #4]
+ 802b718:	e023      	b.n	802b762 <Horiz_Angle_Judge+0x11a>
+			}
+		}
+	}
+	else if(P_MK32->CH15_RT<-300)
+ 802b71a:	4b3f      	ldr	r3, [pc, #252]	@ (802b818 <Horiz_Angle_Judge+0x1d0>)
+ 802b71c:	681b      	ldr	r3, [r3, #0]
+ 802b71e:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
+ 802b720:	f513 7f96 	cmn.w	r3, #300	@ 0x12c
+ 802b724:	da1a      	bge.n	802b75c <Horiz_Angle_Judge+0x114>
+	{
+		Right_Compensation_Count--;
+ 802b726:	4b40      	ldr	r3, [pc, #256]	@ (802b828 <Horiz_Angle_Judge+0x1e0>)
+ 802b728:	681b      	ldr	r3, [r3, #0]
+ 802b72a:	3b01      	subs	r3, #1
+ 802b72c:	4a3e      	ldr	r2, [pc, #248]	@ (802b828 <Horiz_Angle_Judge+0x1e0>)
+ 802b72e:	6013      	str	r3, [r2, #0]
+		if(Right_Compensation_Count<-200)
+ 802b730:	4b3d      	ldr	r3, [pc, #244]	@ (802b828 <Horiz_Angle_Judge+0x1e0>)
+ 802b732:	681b      	ldr	r3, [r3, #0]
+ 802b734:	f113 0fc8 	cmn.w	r3, #200	@ 0xc8
+ 802b738:	da13      	bge.n	802b762 <Horiz_Angle_Judge+0x11a>
+		{
+			GV.Right_Compensation=GV.Right_Compensation-25;
+ 802b73a:	4b39      	ldr	r3, [pc, #228]	@ (802b820 <Horiz_Angle_Judge+0x1d8>)
+ 802b73c:	685b      	ldr	r3, [r3, #4]
+ 802b73e:	3b19      	subs	r3, #25
+ 802b740:	4a37      	ldr	r2, [pc, #220]	@ (802b820 <Horiz_Angle_Judge+0x1d8>)
+ 802b742:	6053      	str	r3, [r2, #4]
+			Right_Compensation_Count=0;
+ 802b744:	4b38      	ldr	r3, [pc, #224]	@ (802b828 <Horiz_Angle_Judge+0x1e0>)
+ 802b746:	2200      	movs	r2, #0
+ 802b748:	601a      	str	r2, [r3, #0]
+			if(GV.Right_Compensation<-1000)
+ 802b74a:	4b35      	ldr	r3, [pc, #212]	@ (802b820 <Horiz_Angle_Judge+0x1d8>)
+ 802b74c:	685b      	ldr	r3, [r3, #4]
+ 802b74e:	f513 7f7a 	cmn.w	r3, #1000	@ 0x3e8
+ 802b752:	da06      	bge.n	802b762 <Horiz_Angle_Judge+0x11a>
+			{
+				GV.Right_Compensation=-1000;
+ 802b754:	4b32      	ldr	r3, [pc, #200]	@ (802b820 <Horiz_Angle_Judge+0x1d8>)
+ 802b756:	4a33      	ldr	r2, [pc, #204]	@ (802b824 <Horiz_Angle_Judge+0x1dc>)
+ 802b758:	605a      	str	r2, [r3, #4]
+ 802b75a:	e002      	b.n	802b762 <Horiz_Angle_Judge+0x11a>
+			}
+		}
+	}
+	else
+	{
+		Right_Compensation_Count=0;
+ 802b75c:	4b32      	ldr	r3, [pc, #200]	@ (802b828 <Horiz_Angle_Judge+0x1e0>)
+ 802b75e:	2200      	movs	r2, #0
+ 802b760:	601a      	str	r2, [r3, #0]
+	}
+
+	double Robot_Grity=((double )GV.TL720DParameters.RF_Angle_Roll)/100;
+ 802b762:	4b2f      	ldr	r3, [pc, #188]	@ (802b820 <Horiz_Angle_Judge+0x1d8>)
+ 802b764:	f8d3 3218 	ldr.w	r3, [r3, #536]	@ 0x218
+ 802b768:	ee07 3a90 	vmov	s15, r3
+ 802b76c:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802b770:	ed9f 5b23 	vldr	d5, [pc, #140]	@ 802b800 <Horiz_Angle_Judge+0x1b8>
+ 802b774:	ee86 7b05 	vdiv.f64	d7, d6, d5
+ 802b778:	ed87 7b00 	vstr	d7, [r7]
+	if((Robot_Grity>-180)&&(Robot_Grity<0))
+ 802b77c:	ed97 7b00 	vldr	d7, [r7]
+ 802b780:	ed9f 6b21 	vldr	d6, [pc, #132]	@ 802b808 <Horiz_Angle_Judge+0x1c0>
+ 802b784:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 802b788:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802b78c:	dd18      	ble.n	802b7c0 <Horiz_Angle_Judge+0x178>
+ 802b78e:	ed97 7b00 	vldr	d7, [r7]
+ 802b792:	eeb5 7bc0 	vcmpe.f64	d7, #0.0
+ 802b796:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802b79a:	d511      	bpl.n	802b7c0 <Horiz_Angle_Judge+0x178>
+	{
+		Horzi_Der_Angle_Deg=-90+((double)GV.Right_Compensation)/100;
+ 802b79c:	4b20      	ldr	r3, [pc, #128]	@ (802b820 <Horiz_Angle_Judge+0x1d8>)
+ 802b79e:	685b      	ldr	r3, [r3, #4]
+ 802b7a0:	ee07 3a90 	vmov	s15, r3
+ 802b7a4:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802b7a8:	ed9f 5b15 	vldr	d5, [pc, #84]	@ 802b800 <Horiz_Angle_Judge+0x1b8>
+ 802b7ac:	ee86 7b05 	vdiv.f64	d7, d6, d5
+ 802b7b0:	ed9f 6b17 	vldr	d6, [pc, #92]	@ 802b810 <Horiz_Angle_Judge+0x1c8>
+ 802b7b4:	ee37 7b46 	vsub.f64	d7, d7, d6
+ 802b7b8:	4b1c      	ldr	r3, [pc, #112]	@ (802b82c <Horiz_Angle_Judge+0x1e4>)
+ 802b7ba:	ed83 7b00 	vstr	d7, [r3]
+ 802b7be:	e010      	b.n	802b7e2 <Horiz_Angle_Judge+0x19a>
+	}
+	else
+	{
+		Horzi_Der_Angle_Deg=90+((double)GV.Left_Compensation)/100;
+ 802b7c0:	4b17      	ldr	r3, [pc, #92]	@ (802b820 <Horiz_Angle_Judge+0x1d8>)
+ 802b7c2:	681b      	ldr	r3, [r3, #0]
+ 802b7c4:	ee07 3a90 	vmov	s15, r3
+ 802b7c8:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802b7cc:	ed9f 5b0c 	vldr	d5, [pc, #48]	@ 802b800 <Horiz_Angle_Judge+0x1b8>
+ 802b7d0:	ee86 7b05 	vdiv.f64	d7, d6, d5
+ 802b7d4:	ed9f 6b0e 	vldr	d6, [pc, #56]	@ 802b810 <Horiz_Angle_Judge+0x1c8>
+ 802b7d8:	ee37 7b06 	vadd.f64	d7, d7, d6
+ 802b7dc:	4b13      	ldr	r3, [pc, #76]	@ (802b82c <Horiz_Angle_Judge+0x1e4>)
+ 802b7de:	ed83 7b00 	vstr	d7, [r3]
+	}
+	CV_Robot_Deri_Angle_Deg_Grity=Horzi_Der_Angle_Deg;
+ 802b7e2:	4b12      	ldr	r3, [pc, #72]	@ (802b82c <Horiz_Angle_Judge+0x1e4>)
+ 802b7e4:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802b7e8:	4911      	ldr	r1, [pc, #68]	@ (802b830 <Horiz_Angle_Judge+0x1e8>)
+ 802b7ea:	e9c1 2300 	strd	r2, r3, [r1]
+}
+ 802b7ee:	bf00      	nop
+ 802b7f0:	370c      	adds	r7, #12
+ 802b7f2:	46bd      	mov	sp, r7
+ 802b7f4:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 802b7f8:	4770      	bx	lr
+ 802b7fa:	bf00      	nop
+ 802b7fc:	f3af 8000 	nop.w
+ 802b800:	00000000 	.word	0x00000000
+ 802b804:	40590000 	.word	0x40590000
+ 802b808:	00000000 	.word	0x00000000
+ 802b80c:	c0668000 	.word	0xc0668000
+ 802b810:	00000000 	.word	0x00000000
+ 802b814:	40568000 	.word	0x40568000
+ 802b818:	2400a3f8 	.word	0x2400a3f8
+ 802b81c:	2400a89c 	.word	0x2400a89c
+ 802b820:	24000340 	.word	0x24000340
+ 802b824:	fffffc18 	.word	0xfffffc18
+ 802b828:	2400a8a0 	.word	0x2400a8a0
+ 802b82c:	2400a6c8 	.word	0x2400a6c8
+ 802b830:	2400a6d0 	.word	0x2400a6d0
+ 802b834:	00000000 	.word	0x00000000
+
+0802b838 <Horiz_Angle_Judge_4_Direction>:
+
+
+
+
+void Horiz_Angle_Judge_4_Direction()
+{
+ 802b838:	b480      	push	{r7}
+ 802b83a:	b083      	sub	sp, #12
+ 802b83c:	af00      	add	r7, sp, #0
+	static int Left_Compensation_Count;
+	static int Right_Compensation_Count;
+
+	if(P_MK32->CH14_LT>300)
+ 802b83e:	4b9a      	ldr	r3, [pc, #616]	@ (802baa8 <Horiz_Angle_Judge_4_Direction+0x270>)
+ 802b840:	681b      	ldr	r3, [r3, #0]
+ 802b842:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 802b844:	f5b3 7f96 	cmp.w	r3, #300	@ 0x12c
+ 802b848:	dd1a      	ble.n	802b880 <Horiz_Angle_Judge_4_Direction+0x48>
+	{
+		Left_Compensation_Count++;
+ 802b84a:	4b98      	ldr	r3, [pc, #608]	@ (802baac <Horiz_Angle_Judge_4_Direction+0x274>)
+ 802b84c:	681b      	ldr	r3, [r3, #0]
+ 802b84e:	3301      	adds	r3, #1
+ 802b850:	4a96      	ldr	r2, [pc, #600]	@ (802baac <Horiz_Angle_Judge_4_Direction+0x274>)
+ 802b852:	6013      	str	r3, [r2, #0]
+		if(Left_Compensation_Count>200)
+ 802b854:	4b95      	ldr	r3, [pc, #596]	@ (802baac <Horiz_Angle_Judge_4_Direction+0x274>)
+ 802b856:	681b      	ldr	r3, [r3, #0]
+ 802b858:	2bc8      	cmp	r3, #200	@ 0xc8
+ 802b85a:	dd07      	ble.n	802b86c <Horiz_Angle_Judge_4_Direction+0x34>
+		{
+			GV.Left_Compensation=GV.Left_Compensation+25;
+ 802b85c:	4b94      	ldr	r3, [pc, #592]	@ (802bab0 <Horiz_Angle_Judge_4_Direction+0x278>)
+ 802b85e:	681b      	ldr	r3, [r3, #0]
+ 802b860:	3319      	adds	r3, #25
+ 802b862:	4a93      	ldr	r2, [pc, #588]	@ (802bab0 <Horiz_Angle_Judge_4_Direction+0x278>)
+ 802b864:	6013      	str	r3, [r2, #0]
+			Left_Compensation_Count=0;
+ 802b866:	4b91      	ldr	r3, [pc, #580]	@ (802baac <Horiz_Angle_Judge_4_Direction+0x274>)
+ 802b868:	2200      	movs	r2, #0
+ 802b86a:	601a      	str	r2, [r3, #0]
+		}
+		if(GV.Left_Compensation>1000)
+ 802b86c:	4b90      	ldr	r3, [pc, #576]	@ (802bab0 <Horiz_Angle_Judge_4_Direction+0x278>)
+ 802b86e:	681b      	ldr	r3, [r3, #0]
+ 802b870:	f5b3 7f7a 	cmp.w	r3, #1000	@ 0x3e8
+ 802b874:	dd28      	ble.n	802b8c8 <Horiz_Angle_Judge_4_Direction+0x90>
+		{
+			GV.Left_Compensation=1000;
+ 802b876:	4b8e      	ldr	r3, [pc, #568]	@ (802bab0 <Horiz_Angle_Judge_4_Direction+0x278>)
+ 802b878:	f44f 727a 	mov.w	r2, #1000	@ 0x3e8
+ 802b87c:	601a      	str	r2, [r3, #0]
+ 802b87e:	e023      	b.n	802b8c8 <Horiz_Angle_Judge_4_Direction+0x90>
+		}
+	}
+	else if(P_MK32->CH14_LT<-300)
+ 802b880:	4b89      	ldr	r3, [pc, #548]	@ (802baa8 <Horiz_Angle_Judge_4_Direction+0x270>)
+ 802b882:	681b      	ldr	r3, [r3, #0]
+ 802b884:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 802b886:	f513 7f96 	cmn.w	r3, #300	@ 0x12c
+ 802b88a:	da1a      	bge.n	802b8c2 <Horiz_Angle_Judge_4_Direction+0x8a>
+	{
+		Left_Compensation_Count--;
+ 802b88c:	4b87      	ldr	r3, [pc, #540]	@ (802baac <Horiz_Angle_Judge_4_Direction+0x274>)
+ 802b88e:	681b      	ldr	r3, [r3, #0]
+ 802b890:	3b01      	subs	r3, #1
+ 802b892:	4a86      	ldr	r2, [pc, #536]	@ (802baac <Horiz_Angle_Judge_4_Direction+0x274>)
+ 802b894:	6013      	str	r3, [r2, #0]
+		if(Left_Compensation_Count<-200)
+ 802b896:	4b85      	ldr	r3, [pc, #532]	@ (802baac <Horiz_Angle_Judge_4_Direction+0x274>)
+ 802b898:	681b      	ldr	r3, [r3, #0]
+ 802b89a:	f113 0fc8 	cmn.w	r3, #200	@ 0xc8
+ 802b89e:	da13      	bge.n	802b8c8 <Horiz_Angle_Judge_4_Direction+0x90>
+		{
+			GV.Left_Compensation=GV.Left_Compensation-25;
+ 802b8a0:	4b83      	ldr	r3, [pc, #524]	@ (802bab0 <Horiz_Angle_Judge_4_Direction+0x278>)
+ 802b8a2:	681b      	ldr	r3, [r3, #0]
+ 802b8a4:	3b19      	subs	r3, #25
+ 802b8a6:	4a82      	ldr	r2, [pc, #520]	@ (802bab0 <Horiz_Angle_Judge_4_Direction+0x278>)
+ 802b8a8:	6013      	str	r3, [r2, #0]
+			Left_Compensation_Count=0;
+ 802b8aa:	4b80      	ldr	r3, [pc, #512]	@ (802baac <Horiz_Angle_Judge_4_Direction+0x274>)
+ 802b8ac:	2200      	movs	r2, #0
+ 802b8ae:	601a      	str	r2, [r3, #0]
+			if(GV.Left_Compensation<-1000)
+ 802b8b0:	4b7f      	ldr	r3, [pc, #508]	@ (802bab0 <Horiz_Angle_Judge_4_Direction+0x278>)
+ 802b8b2:	681b      	ldr	r3, [r3, #0]
+ 802b8b4:	f513 7f7a 	cmn.w	r3, #1000	@ 0x3e8
+ 802b8b8:	da06      	bge.n	802b8c8 <Horiz_Angle_Judge_4_Direction+0x90>
+			{
+				GV.Left_Compensation=-1000;
+ 802b8ba:	4b7d      	ldr	r3, [pc, #500]	@ (802bab0 <Horiz_Angle_Judge_4_Direction+0x278>)
+ 802b8bc:	4a7d      	ldr	r2, [pc, #500]	@ (802bab4 <Horiz_Angle_Judge_4_Direction+0x27c>)
+ 802b8be:	601a      	str	r2, [r3, #0]
+ 802b8c0:	e002      	b.n	802b8c8 <Horiz_Angle_Judge_4_Direction+0x90>
+			}
+		}
+	}
+	else
+	{
+		Left_Compensation_Count=0;
+ 802b8c2:	4b7a      	ldr	r3, [pc, #488]	@ (802baac <Horiz_Angle_Judge_4_Direction+0x274>)
+ 802b8c4:	2200      	movs	r2, #0
+ 802b8c6:	601a      	str	r2, [r3, #0]
+	}
+
+	if(P_MK32->CH15_RT>300)
+ 802b8c8:	4b77      	ldr	r3, [pc, #476]	@ (802baa8 <Horiz_Angle_Judge_4_Direction+0x270>)
+ 802b8ca:	681b      	ldr	r3, [r3, #0]
+ 802b8cc:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
+ 802b8ce:	f5b3 7f96 	cmp.w	r3, #300	@ 0x12c
+ 802b8d2:	dd1a      	ble.n	802b90a <Horiz_Angle_Judge_4_Direction+0xd2>
+	{
+		Right_Compensation_Count++;
+ 802b8d4:	4b78      	ldr	r3, [pc, #480]	@ (802bab8 <Horiz_Angle_Judge_4_Direction+0x280>)
+ 802b8d6:	681b      	ldr	r3, [r3, #0]
+ 802b8d8:	3301      	adds	r3, #1
+ 802b8da:	4a77      	ldr	r2, [pc, #476]	@ (802bab8 <Horiz_Angle_Judge_4_Direction+0x280>)
+ 802b8dc:	6013      	str	r3, [r2, #0]
+		if(Right_Compensation_Count>200)
+ 802b8de:	4b76      	ldr	r3, [pc, #472]	@ (802bab8 <Horiz_Angle_Judge_4_Direction+0x280>)
+ 802b8e0:	681b      	ldr	r3, [r3, #0]
+ 802b8e2:	2bc8      	cmp	r3, #200	@ 0xc8
+ 802b8e4:	dd35      	ble.n	802b952 <Horiz_Angle_Judge_4_Direction+0x11a>
+		{
+			GV.Right_Compensation=GV.Right_Compensation+25;
+ 802b8e6:	4b72      	ldr	r3, [pc, #456]	@ (802bab0 <Horiz_Angle_Judge_4_Direction+0x278>)
+ 802b8e8:	685b      	ldr	r3, [r3, #4]
+ 802b8ea:	3319      	adds	r3, #25
+ 802b8ec:	4a70      	ldr	r2, [pc, #448]	@ (802bab0 <Horiz_Angle_Judge_4_Direction+0x278>)
+ 802b8ee:	6053      	str	r3, [r2, #4]
+			Right_Compensation_Count=0;
+ 802b8f0:	4b71      	ldr	r3, [pc, #452]	@ (802bab8 <Horiz_Angle_Judge_4_Direction+0x280>)
+ 802b8f2:	2200      	movs	r2, #0
+ 802b8f4:	601a      	str	r2, [r3, #0]
+			if(GV.Right_Compensation>1000)
+ 802b8f6:	4b6e      	ldr	r3, [pc, #440]	@ (802bab0 <Horiz_Angle_Judge_4_Direction+0x278>)
+ 802b8f8:	685b      	ldr	r3, [r3, #4]
+ 802b8fa:	f5b3 7f7a 	cmp.w	r3, #1000	@ 0x3e8
+ 802b8fe:	dd28      	ble.n	802b952 <Horiz_Angle_Judge_4_Direction+0x11a>
+			{
+				GV.Right_Compensation=1000;
+ 802b900:	4b6b      	ldr	r3, [pc, #428]	@ (802bab0 <Horiz_Angle_Judge_4_Direction+0x278>)
+ 802b902:	f44f 727a 	mov.w	r2, #1000	@ 0x3e8
+ 802b906:	605a      	str	r2, [r3, #4]
+ 802b908:	e023      	b.n	802b952 <Horiz_Angle_Judge_4_Direction+0x11a>
+			}
+		}
+	}
+	else if(P_MK32->CH15_RT<-300)
+ 802b90a:	4b67      	ldr	r3, [pc, #412]	@ (802baa8 <Horiz_Angle_Judge_4_Direction+0x270>)
+ 802b90c:	681b      	ldr	r3, [r3, #0]
+ 802b90e:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
+ 802b910:	f513 7f96 	cmn.w	r3, #300	@ 0x12c
+ 802b914:	da1a      	bge.n	802b94c <Horiz_Angle_Judge_4_Direction+0x114>
+	{
+		Right_Compensation_Count--;
+ 802b916:	4b68      	ldr	r3, [pc, #416]	@ (802bab8 <Horiz_Angle_Judge_4_Direction+0x280>)
+ 802b918:	681b      	ldr	r3, [r3, #0]
+ 802b91a:	3b01      	subs	r3, #1
+ 802b91c:	4a66      	ldr	r2, [pc, #408]	@ (802bab8 <Horiz_Angle_Judge_4_Direction+0x280>)
+ 802b91e:	6013      	str	r3, [r2, #0]
+		if(Right_Compensation_Count<-200)
+ 802b920:	4b65      	ldr	r3, [pc, #404]	@ (802bab8 <Horiz_Angle_Judge_4_Direction+0x280>)
+ 802b922:	681b      	ldr	r3, [r3, #0]
+ 802b924:	f113 0fc8 	cmn.w	r3, #200	@ 0xc8
+ 802b928:	da13      	bge.n	802b952 <Horiz_Angle_Judge_4_Direction+0x11a>
+		{
+			GV.Right_Compensation=GV.Right_Compensation-25;
+ 802b92a:	4b61      	ldr	r3, [pc, #388]	@ (802bab0 <Horiz_Angle_Judge_4_Direction+0x278>)
+ 802b92c:	685b      	ldr	r3, [r3, #4]
+ 802b92e:	3b19      	subs	r3, #25
+ 802b930:	4a5f      	ldr	r2, [pc, #380]	@ (802bab0 <Horiz_Angle_Judge_4_Direction+0x278>)
+ 802b932:	6053      	str	r3, [r2, #4]
+			Right_Compensation_Count=0;
+ 802b934:	4b60      	ldr	r3, [pc, #384]	@ (802bab8 <Horiz_Angle_Judge_4_Direction+0x280>)
+ 802b936:	2200      	movs	r2, #0
+ 802b938:	601a      	str	r2, [r3, #0]
+			if(GV.Right_Compensation<-1000)
+ 802b93a:	4b5d      	ldr	r3, [pc, #372]	@ (802bab0 <Horiz_Angle_Judge_4_Direction+0x278>)
+ 802b93c:	685b      	ldr	r3, [r3, #4]
+ 802b93e:	f513 7f7a 	cmn.w	r3, #1000	@ 0x3e8
+ 802b942:	da06      	bge.n	802b952 <Horiz_Angle_Judge_4_Direction+0x11a>
+			{
+				GV.Right_Compensation=-1000;
+ 802b944:	4b5a      	ldr	r3, [pc, #360]	@ (802bab0 <Horiz_Angle_Judge_4_Direction+0x278>)
+ 802b946:	4a5b      	ldr	r2, [pc, #364]	@ (802bab4 <Horiz_Angle_Judge_4_Direction+0x27c>)
+ 802b948:	605a      	str	r2, [r3, #4]
+ 802b94a:	e002      	b.n	802b952 <Horiz_Angle_Judge_4_Direction+0x11a>
+			}
+		}
+	}
+	else
+	{
+		Right_Compensation_Count=0;
+ 802b94c:	4b5a      	ldr	r3, [pc, #360]	@ (802bab8 <Horiz_Angle_Judge_4_Direction+0x280>)
+ 802b94e:	2200      	movs	r2, #0
+ 802b950:	601a      	str	r2, [r3, #0]
+	}
+
+	double Robot_Grity=((double )GV.TL720DParameters.RF_Angle_Roll)/100;
+ 802b952:	4b57      	ldr	r3, [pc, #348]	@ (802bab0 <Horiz_Angle_Judge_4_Direction+0x278>)
+ 802b954:	f8d3 3218 	ldr.w	r3, [r3, #536]	@ 0x218
+ 802b958:	ee07 3a90 	vmov	s15, r3
+ 802b95c:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802b960:	ed9f 5b47 	vldr	d5, [pc, #284]	@ 802ba80 <Horiz_Angle_Judge_4_Direction+0x248>
+ 802b964:	ee86 7b05 	vdiv.f64	d7, d6, d5
+ 802b968:	ed87 7b00 	vstr	d7, [r7]
+	if((Robot_Grity>-180)&&(Robot_Grity<=0)&&((P_MK32->CH2_LY_V<-300)||P_MK32->CH5_SB==1000))
+ 802b96c:	ed97 7b00 	vldr	d7, [r7]
+ 802b970:	ed9f 6b45 	vldr	d6, [pc, #276]	@ 802ba88 <Horiz_Angle_Judge_4_Direction+0x250>
+ 802b974:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 802b978:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802b97c:	dd24      	ble.n	802b9c8 <Horiz_Angle_Judge_4_Direction+0x190>
+ 802b97e:	ed97 7b00 	vldr	d7, [r7]
+ 802b982:	eeb5 7bc0 	vcmpe.f64	d7, #0.0
+ 802b986:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802b98a:	d81d      	bhi.n	802b9c8 <Horiz_Angle_Judge_4_Direction+0x190>
+ 802b98c:	4b46      	ldr	r3, [pc, #280]	@ (802baa8 <Horiz_Angle_Judge_4_Direction+0x270>)
+ 802b98e:	681b      	ldr	r3, [r3, #0]
+ 802b990:	68db      	ldr	r3, [r3, #12]
+ 802b992:	f513 7f96 	cmn.w	r3, #300	@ 0x12c
+ 802b996:	db05      	blt.n	802b9a4 <Horiz_Angle_Judge_4_Direction+0x16c>
+ 802b998:	4b43      	ldr	r3, [pc, #268]	@ (802baa8 <Horiz_Angle_Judge_4_Direction+0x270>)
+ 802b99a:	681b      	ldr	r3, [r3, #0]
+ 802b99c:	699b      	ldr	r3, [r3, #24]
+ 802b99e:	f5b3 7f7a 	cmp.w	r3, #1000	@ 0x3e8
+ 802b9a2:	d111      	bne.n	802b9c8 <Horiz_Angle_Judge_4_Direction+0x190>
+	{
+		Horzi_Der_Angle_Deg=-90+((double)GV.Right_Compensation)/100;
+ 802b9a4:	4b42      	ldr	r3, [pc, #264]	@ (802bab0 <Horiz_Angle_Judge_4_Direction+0x278>)
+ 802b9a6:	685b      	ldr	r3, [r3, #4]
+ 802b9a8:	ee07 3a90 	vmov	s15, r3
+ 802b9ac:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802b9b0:	ed9f 5b33 	vldr	d5, [pc, #204]	@ 802ba80 <Horiz_Angle_Judge_4_Direction+0x248>
+ 802b9b4:	ee86 7b05 	vdiv.f64	d7, d6, d5
+ 802b9b8:	ed9f 6b35 	vldr	d6, [pc, #212]	@ 802ba90 <Horiz_Angle_Judge_4_Direction+0x258>
+ 802b9bc:	ee37 7b46 	vsub.f64	d7, d7, d6
+ 802b9c0:	4b3e      	ldr	r3, [pc, #248]	@ (802babc <Horiz_Angle_Judge_4_Direction+0x284>)
+ 802b9c2:	ed83 7b00 	vstr	d7, [r3]
+ 802b9c6:	e0a8      	b.n	802bb1a <Horiz_Angle_Judge_4_Direction+0x2e2>
+	}
+	else if((Robot_Grity>-180)&&(Robot_Grity<=0)&&((P_MK32->CH2_LY_V>300)||P_MK32->CH5_SB==-1000))
+ 802b9c8:	ed97 7b00 	vldr	d7, [r7]
+ 802b9cc:	ed9f 6b2e 	vldr	d6, [pc, #184]	@ 802ba88 <Horiz_Angle_Judge_4_Direction+0x250>
+ 802b9d0:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 802b9d4:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802b9d8:	dd24      	ble.n	802ba24 <Horiz_Angle_Judge_4_Direction+0x1ec>
+ 802b9da:	ed97 7b00 	vldr	d7, [r7]
+ 802b9de:	eeb5 7bc0 	vcmpe.f64	d7, #0.0
+ 802b9e2:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802b9e6:	d81d      	bhi.n	802ba24 <Horiz_Angle_Judge_4_Direction+0x1ec>
+ 802b9e8:	4b2f      	ldr	r3, [pc, #188]	@ (802baa8 <Horiz_Angle_Judge_4_Direction+0x270>)
+ 802b9ea:	681b      	ldr	r3, [r3, #0]
+ 802b9ec:	68db      	ldr	r3, [r3, #12]
+ 802b9ee:	f5b3 7f96 	cmp.w	r3, #300	@ 0x12c
+ 802b9f2:	dc05      	bgt.n	802ba00 <Horiz_Angle_Judge_4_Direction+0x1c8>
+ 802b9f4:	4b2c      	ldr	r3, [pc, #176]	@ (802baa8 <Horiz_Angle_Judge_4_Direction+0x270>)
+ 802b9f6:	681b      	ldr	r3, [r3, #0]
+ 802b9f8:	699b      	ldr	r3, [r3, #24]
+ 802b9fa:	f513 7f7a 	cmn.w	r3, #1000	@ 0x3e8
+ 802b9fe:	d111      	bne.n	802ba24 <Horiz_Angle_Judge_4_Direction+0x1ec>
+	{
+		Horzi_Der_Angle_Deg=-90-((double)GV.Right_Compensation)/100;
+ 802ba00:	4b2b      	ldr	r3, [pc, #172]	@ (802bab0 <Horiz_Angle_Judge_4_Direction+0x278>)
+ 802ba02:	685b      	ldr	r3, [r3, #4]
+ 802ba04:	ee07 3a90 	vmov	s15, r3
+ 802ba08:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802ba0c:	ed9f 5b1c 	vldr	d5, [pc, #112]	@ 802ba80 <Horiz_Angle_Judge_4_Direction+0x248>
+ 802ba10:	ee86 7b05 	vdiv.f64	d7, d6, d5
+ 802ba14:	ed9f 6b20 	vldr	d6, [pc, #128]	@ 802ba98 <Horiz_Angle_Judge_4_Direction+0x260>
+ 802ba18:	ee36 7b47 	vsub.f64	d7, d6, d7
+ 802ba1c:	4b27      	ldr	r3, [pc, #156]	@ (802babc <Horiz_Angle_Judge_4_Direction+0x284>)
+ 802ba1e:	ed83 7b00 	vstr	d7, [r3]
+ 802ba22:	e07a      	b.n	802bb1a <Horiz_Angle_Judge_4_Direction+0x2e2>
+	}
+	else if ((Robot_Grity>0)&&(Robot_Grity<180)&&((P_MK32->CH2_LY_V<-300)||P_MK32->CH5_SB==1000))
+ 802ba24:	ed97 7b00 	vldr	d7, [r7]
+ 802ba28:	eeb5 7bc0 	vcmpe.f64	d7, #0.0
+ 802ba2c:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802ba30:	dd46      	ble.n	802bac0 <Horiz_Angle_Judge_4_Direction+0x288>
+ 802ba32:	ed97 7b00 	vldr	d7, [r7]
+ 802ba36:	ed9f 6b1a 	vldr	d6, [pc, #104]	@ 802baa0 <Horiz_Angle_Judge_4_Direction+0x268>
+ 802ba3a:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 802ba3e:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802ba42:	d53d      	bpl.n	802bac0 <Horiz_Angle_Judge_4_Direction+0x288>
+ 802ba44:	4b18      	ldr	r3, [pc, #96]	@ (802baa8 <Horiz_Angle_Judge_4_Direction+0x270>)
+ 802ba46:	681b      	ldr	r3, [r3, #0]
+ 802ba48:	68db      	ldr	r3, [r3, #12]
+ 802ba4a:	f513 7f96 	cmn.w	r3, #300	@ 0x12c
+ 802ba4e:	db05      	blt.n	802ba5c <Horiz_Angle_Judge_4_Direction+0x224>
+ 802ba50:	4b15      	ldr	r3, [pc, #84]	@ (802baa8 <Horiz_Angle_Judge_4_Direction+0x270>)
+ 802ba52:	681b      	ldr	r3, [r3, #0]
+ 802ba54:	699b      	ldr	r3, [r3, #24]
+ 802ba56:	f5b3 7f7a 	cmp.w	r3, #1000	@ 0x3e8
+ 802ba5a:	d131      	bne.n	802bac0 <Horiz_Angle_Judge_4_Direction+0x288>
+	{
+		Horzi_Der_Angle_Deg=90+((double)GV.Left_Compensation)/100;
+ 802ba5c:	4b14      	ldr	r3, [pc, #80]	@ (802bab0 <Horiz_Angle_Judge_4_Direction+0x278>)
+ 802ba5e:	681b      	ldr	r3, [r3, #0]
+ 802ba60:	ee07 3a90 	vmov	s15, r3
+ 802ba64:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802ba68:	ed9f 5b05 	vldr	d5, [pc, #20]	@ 802ba80 <Horiz_Angle_Judge_4_Direction+0x248>
+ 802ba6c:	ee86 7b05 	vdiv.f64	d7, d6, d5
+ 802ba70:	ed9f 6b07 	vldr	d6, [pc, #28]	@ 802ba90 <Horiz_Angle_Judge_4_Direction+0x258>
+ 802ba74:	ee37 7b06 	vadd.f64	d7, d7, d6
+ 802ba78:	4b10      	ldr	r3, [pc, #64]	@ (802babc <Horiz_Angle_Judge_4_Direction+0x284>)
+ 802ba7a:	ed83 7b00 	vstr	d7, [r3]
+ 802ba7e:	e04c      	b.n	802bb1a <Horiz_Angle_Judge_4_Direction+0x2e2>
+ 802ba80:	00000000 	.word	0x00000000
+ 802ba84:	40590000 	.word	0x40590000
+ 802ba88:	00000000 	.word	0x00000000
+ 802ba8c:	c0668000 	.word	0xc0668000
+ 802ba90:	00000000 	.word	0x00000000
+ 802ba94:	40568000 	.word	0x40568000
+ 802ba98:	00000000 	.word	0x00000000
+ 802ba9c:	c0568000 	.word	0xc0568000
+ 802baa0:	00000000 	.word	0x00000000
+ 802baa4:	40668000 	.word	0x40668000
+ 802baa8:	2400a3f8 	.word	0x2400a3f8
+ 802baac:	2400a8a4 	.word	0x2400a8a4
+ 802bab0:	24000340 	.word	0x24000340
+ 802bab4:	fffffc18 	.word	0xfffffc18
+ 802bab8:	2400a8a8 	.word	0x2400a8a8
+ 802babc:	2400a6c8 	.word	0x2400a6c8
+	}
+	else if((Robot_Grity>0)&&(Robot_Grity<180)&&((P_MK32->CH2_LY_V>300)||P_MK32->CH5_SB==-1000))
+ 802bac0:	ed97 7b00 	vldr	d7, [r7]
+ 802bac4:	eeb5 7bc0 	vcmpe.f64	d7, #0.0
+ 802bac8:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802bacc:	dd25      	ble.n	802bb1a <Horiz_Angle_Judge_4_Direction+0x2e2>
+ 802bace:	ed97 7b00 	vldr	d7, [r7]
+ 802bad2:	ed9f 6b19 	vldr	d6, [pc, #100]	@ 802bb38 <Horiz_Angle_Judge_4_Direction+0x300>
+ 802bad6:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 802bada:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802bade:	d51c      	bpl.n	802bb1a <Horiz_Angle_Judge_4_Direction+0x2e2>
+ 802bae0:	4b1b      	ldr	r3, [pc, #108]	@ (802bb50 <Horiz_Angle_Judge_4_Direction+0x318>)
+ 802bae2:	681b      	ldr	r3, [r3, #0]
+ 802bae4:	68db      	ldr	r3, [r3, #12]
+ 802bae6:	f5b3 7f96 	cmp.w	r3, #300	@ 0x12c
+ 802baea:	dc05      	bgt.n	802baf8 <Horiz_Angle_Judge_4_Direction+0x2c0>
+ 802baec:	4b18      	ldr	r3, [pc, #96]	@ (802bb50 <Horiz_Angle_Judge_4_Direction+0x318>)
+ 802baee:	681b      	ldr	r3, [r3, #0]
+ 802baf0:	699b      	ldr	r3, [r3, #24]
+ 802baf2:	f513 7f7a 	cmn.w	r3, #1000	@ 0x3e8
+ 802baf6:	d110      	bne.n	802bb1a <Horiz_Angle_Judge_4_Direction+0x2e2>
+	{
+		Horzi_Der_Angle_Deg=90-((double)GV.Left_Compensation)/100;
+ 802baf8:	4b16      	ldr	r3, [pc, #88]	@ (802bb54 <Horiz_Angle_Judge_4_Direction+0x31c>)
+ 802bafa:	681b      	ldr	r3, [r3, #0]
+ 802bafc:	ee07 3a90 	vmov	s15, r3
+ 802bb00:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802bb04:	ed9f 5b0e 	vldr	d5, [pc, #56]	@ 802bb40 <Horiz_Angle_Judge_4_Direction+0x308>
+ 802bb08:	ee86 7b05 	vdiv.f64	d7, d6, d5
+ 802bb0c:	ed9f 6b0e 	vldr	d6, [pc, #56]	@ 802bb48 <Horiz_Angle_Judge_4_Direction+0x310>
+ 802bb10:	ee36 7b47 	vsub.f64	d7, d6, d7
+ 802bb14:	4b10      	ldr	r3, [pc, #64]	@ (802bb58 <Horiz_Angle_Judge_4_Direction+0x320>)
+ 802bb16:	ed83 7b00 	vstr	d7, [r3]
+	}
+	CV_Robot_Deri_Angle_Deg_Grity=Horzi_Der_Angle_Deg;
+ 802bb1a:	4b0f      	ldr	r3, [pc, #60]	@ (802bb58 <Horiz_Angle_Judge_4_Direction+0x320>)
+ 802bb1c:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802bb20:	490e      	ldr	r1, [pc, #56]	@ (802bb5c <Horiz_Angle_Judge_4_Direction+0x324>)
+ 802bb22:	e9c1 2300 	strd	r2, r3, [r1]
+
+
+
+}
+ 802bb26:	bf00      	nop
+ 802bb28:	370c      	adds	r7, #12
+ 802bb2a:	46bd      	mov	sp, r7
+ 802bb2c:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 802bb30:	4770      	bx	lr
+ 802bb32:	bf00      	nop
+ 802bb34:	f3af 8000 	nop.w
+ 802bb38:	00000000 	.word	0x00000000
+ 802bb3c:	40668000 	.word	0x40668000
+ 802bb40:	00000000 	.word	0x00000000
+ 802bb44:	40590000 	.word	0x40590000
+ 802bb48:	00000000 	.word	0x00000000
+ 802bb4c:	40568000 	.word	0x40568000
+ 802bb50:	2400a3f8 	.word	0x2400a3f8
+ 802bb54:	24000340 	.word	0x24000340
+ 802bb58:	2400a6c8 	.word	0x2400a6c8
+ 802bb5c:	2400a6d0 	.word	0x2400a6d0
+
+0802bb60 <Horiz_Angle_Judge_Region>:
+
+void Horiz_Angle_Judge_Region()
+{
+ 802bb60:	b480      	push	{r7}
+ 802bb62:	af00      	add	r7, sp, #0
+	if(Deri_Angle_Deg_X[0]>0)
+ 802bb64:	4b42      	ldr	r3, [pc, #264]	@ (802bc70 <Horiz_Angle_Judge_Region+0x110>)
+ 802bb66:	ed93 7b00 	vldr	d7, [r3]
+ 802bb6a:	eeb5 7bc0 	vcmpe.f64	d7, #0.0
+ 802bb6e:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802bb72:	dd22      	ble.n	802bbba <Horiz_Angle_Judge_Region+0x5a>
+	{
+		Deri_Angle_Deg_X[0]= 90+((double)GV.Left_Compensation)/100;
+ 802bb74:	4b3f      	ldr	r3, [pc, #252]	@ (802bc74 <Horiz_Angle_Judge_Region+0x114>)
+ 802bb76:	681b      	ldr	r3, [r3, #0]
+ 802bb78:	ee07 3a90 	vmov	s15, r3
+ 802bb7c:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802bb80:	ed9f 5b37 	vldr	d5, [pc, #220]	@ 802bc60 <Horiz_Angle_Judge_Region+0x100>
+ 802bb84:	ee86 7b05 	vdiv.f64	d7, d6, d5
+ 802bb88:	ed9f 6b37 	vldr	d6, [pc, #220]	@ 802bc68 <Horiz_Angle_Judge_Region+0x108>
+ 802bb8c:	ee37 7b06 	vadd.f64	d7, d7, d6
+ 802bb90:	4b37      	ldr	r3, [pc, #220]	@ (802bc70 <Horiz_Angle_Judge_Region+0x110>)
+ 802bb92:	ed83 7b00 	vstr	d7, [r3]
+		Deri_Angle_Deg_X[1]=-90+((double)GV.Right_Compensation)/100;
+ 802bb96:	4b37      	ldr	r3, [pc, #220]	@ (802bc74 <Horiz_Angle_Judge_Region+0x114>)
+ 802bb98:	685b      	ldr	r3, [r3, #4]
+ 802bb9a:	ee07 3a90 	vmov	s15, r3
+ 802bb9e:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802bba2:	ed9f 5b2f 	vldr	d5, [pc, #188]	@ 802bc60 <Horiz_Angle_Judge_Region+0x100>
+ 802bba6:	ee86 7b05 	vdiv.f64	d7, d6, d5
+ 802bbaa:	ed9f 6b2f 	vldr	d6, [pc, #188]	@ 802bc68 <Horiz_Angle_Judge_Region+0x108>
+ 802bbae:	ee37 7b46 	vsub.f64	d7, d7, d6
+ 802bbb2:	4b2f      	ldr	r3, [pc, #188]	@ (802bc70 <Horiz_Angle_Judge_Region+0x110>)
+ 802bbb4:	ed83 7b02 	vstr	d7, [r3, #8]
+ 802bbb8:	e021      	b.n	802bbfe <Horiz_Angle_Judge_Region+0x9e>
+	}
+	else
+	{
+		Deri_Angle_Deg_X[0]= -90+((double)GV.Right_Compensation)/100;
+ 802bbba:	4b2e      	ldr	r3, [pc, #184]	@ (802bc74 <Horiz_Angle_Judge_Region+0x114>)
+ 802bbbc:	685b      	ldr	r3, [r3, #4]
+ 802bbbe:	ee07 3a90 	vmov	s15, r3
+ 802bbc2:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802bbc6:	ed9f 5b26 	vldr	d5, [pc, #152]	@ 802bc60 <Horiz_Angle_Judge_Region+0x100>
+ 802bbca:	ee86 7b05 	vdiv.f64	d7, d6, d5
+ 802bbce:	ed9f 6b26 	vldr	d6, [pc, #152]	@ 802bc68 <Horiz_Angle_Judge_Region+0x108>
+ 802bbd2:	ee37 7b46 	vsub.f64	d7, d7, d6
+ 802bbd6:	4b26      	ldr	r3, [pc, #152]	@ (802bc70 <Horiz_Angle_Judge_Region+0x110>)
+ 802bbd8:	ed83 7b00 	vstr	d7, [r3]
+		Deri_Angle_Deg_X[1]=  90+((double)GV.Left_Compensation)/100;
+ 802bbdc:	4b25      	ldr	r3, [pc, #148]	@ (802bc74 <Horiz_Angle_Judge_Region+0x114>)
+ 802bbde:	681b      	ldr	r3, [r3, #0]
+ 802bbe0:	ee07 3a90 	vmov	s15, r3
+ 802bbe4:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802bbe8:	ed9f 5b1d 	vldr	d5, [pc, #116]	@ 802bc60 <Horiz_Angle_Judge_Region+0x100>
+ 802bbec:	ee86 7b05 	vdiv.f64	d7, d6, d5
+ 802bbf0:	ed9f 6b1d 	vldr	d6, [pc, #116]	@ 802bc68 <Horiz_Angle_Judge_Region+0x108>
+ 802bbf4:	ee37 7b06 	vadd.f64	d7, d7, d6
+ 802bbf8:	4b1d      	ldr	r3, [pc, #116]	@ (802bc70 <Horiz_Angle_Judge_Region+0x110>)
+ 802bbfa:	ed83 7b02 	vstr	d7, [r3, #8]
+	}
+	if(X_Deri_Angle[0]>0)
+ 802bbfe:	4b1e      	ldr	r3, [pc, #120]	@ (802bc78 <Horiz_Angle_Judge_Region+0x118>)
+ 802bc00:	ed93 7b00 	vldr	d7, [r3]
+ 802bc04:	eeb5 7bc0 	vcmpe.f64	d7, #0.0
+ 802bc08:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802bc0c:	dd11      	ble.n	802bc32 <Horiz_Angle_Judge_Region+0xd2>
+	{
+		X_Deri_Angle[0]=90+((double)GV.Left_Compensation)/100;
+ 802bc0e:	4b19      	ldr	r3, [pc, #100]	@ (802bc74 <Horiz_Angle_Judge_Region+0x114>)
+ 802bc10:	681b      	ldr	r3, [r3, #0]
+ 802bc12:	ee07 3a90 	vmov	s15, r3
+ 802bc16:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802bc1a:	ed9f 5b11 	vldr	d5, [pc, #68]	@ 802bc60 <Horiz_Angle_Judge_Region+0x100>
+ 802bc1e:	ee86 7b05 	vdiv.f64	d7, d6, d5
+ 802bc22:	ed9f 6b11 	vldr	d6, [pc, #68]	@ 802bc68 <Horiz_Angle_Judge_Region+0x108>
+ 802bc26:	ee37 7b06 	vadd.f64	d7, d7, d6
+ 802bc2a:	4b13      	ldr	r3, [pc, #76]	@ (802bc78 <Horiz_Angle_Judge_Region+0x118>)
+ 802bc2c:	ed83 7b00 	vstr	d7, [r3]
+	}
+	else
+	{
+		X_Deri_Angle[0]=-90+((double)GV.Right_Compensation)/100;
+	}
+}
+ 802bc30:	e010      	b.n	802bc54 <Horiz_Angle_Judge_Region+0xf4>
+		X_Deri_Angle[0]=-90+((double)GV.Right_Compensation)/100;
+ 802bc32:	4b10      	ldr	r3, [pc, #64]	@ (802bc74 <Horiz_Angle_Judge_Region+0x114>)
+ 802bc34:	685b      	ldr	r3, [r3, #4]
+ 802bc36:	ee07 3a90 	vmov	s15, r3
+ 802bc3a:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802bc3e:	ed9f 5b08 	vldr	d5, [pc, #32]	@ 802bc60 <Horiz_Angle_Judge_Region+0x100>
+ 802bc42:	ee86 7b05 	vdiv.f64	d7, d6, d5
+ 802bc46:	ed9f 6b08 	vldr	d6, [pc, #32]	@ 802bc68 <Horiz_Angle_Judge_Region+0x108>
+ 802bc4a:	ee37 7b46 	vsub.f64	d7, d7, d6
+ 802bc4e:	4b0a      	ldr	r3, [pc, #40]	@ (802bc78 <Horiz_Angle_Judge_Region+0x118>)
+ 802bc50:	ed83 7b00 	vstr	d7, [r3]
+}
+ 802bc54:	bf00      	nop
+ 802bc56:	46bd      	mov	sp, r7
+ 802bc58:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 802bc5c:	4770      	bx	lr
+ 802bc5e:	bf00      	nop
+ 802bc60:	00000000 	.word	0x00000000
+ 802bc64:	40590000 	.word	0x40590000
+ 802bc68:	00000000 	.word	0x00000000
+ 802bc6c:	40568000 	.word	0x40568000
+ 802bc70:	2400a7b0 	.word	0x2400a7b0
+ 802bc74:	24000340 	.word	0x24000340
+ 802bc78:	2400a7c0 	.word	0x2400a7c0
+ 802bc7c:	00000000 	.word	0x00000000
+
+0802bc80 <Move_Horizontal_Vertical_Task_Forwards_Do_Forwards>:
+
+
+void Move_Horizontal_Vertical_Task_Forwards_Do_Forwards(double robotMoveSpeed, double robotDeriAngleDegGrity)
+{
+ 802bc80:	b580      	push	{r7, lr}
+ 802bc82:	b090      	sub	sp, #64	@ 0x40
+ 802bc84:	af00      	add	r7, sp, #0
+ 802bc86:	ed87 0b02 	vstr	d0, [r7, #8]
+ 802bc8a:	ed87 1b00 	vstr	d1, [r7]
+	double Deri_Speed_Robot_MAX = robotMoveSpeed * 1.5;
+ 802bc8e:	ed97 7b02 	vldr	d7, [r7, #8]
+ 802bc92:	eeb7 6b08 	vmov.f64	d6, #120	@ 0x3fc00000  1.5
+ 802bc96:	ee27 7b06 	vmul.f64	d7, d7, d6
+ 802bc9a:	ed87 7b0e 	vstr	d7, [r7, #56]	@ 0x38
+	double Robot_Speed[4] = {0, 0, 0, 0};
+ 802bc9e:	f107 0310 	add.w	r3, r7, #16
+ 802bca2:	2220      	movs	r2, #32
+ 802bca4:	2100      	movs	r1, #0
+ 802bca6:	4618      	mov	r0, r3
+ 802bca8:	f014 fb1e 	bl	80402e8 <memset>
+	double Robot_Grity = ((double)GV.TL720DParameters.RF_Angle_Roll) / 100;
+ 802bcac:	4b1c      	ldr	r3, [pc, #112]	@ (802bd20 <Move_Horizontal_Vertical_Task_Forwards_Do_Forwards+0xa0>)
+ 802bcae:	f8d3 3218 	ldr.w	r3, [r3, #536]	@ 0x218
+ 802bcb2:	ee07 3a90 	vmov	s15, r3
+ 802bcb6:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802bcba:	ed9f 5b17 	vldr	d5, [pc, #92]	@ 802bd18 <Move_Horizontal_Vertical_Task_Forwards_Do_Forwards+0x98>
+ 802bcbe:	ee86 7b05 	vdiv.f64	d7, d6, d5
+ 802bcc2:	ed87 7b0c 	vstr	d7, [r7, #48]	@ 0x30
+
+	GF_MSP_PID_Now_Der_adj_Com_Horizon(Robot_Grity, robotDeriAngleDegGrity, robotMoveSpeed, Deri_Speed_Robot_MAX, System_time_SR, Robot_Speed);
+ 802bcc6:	4b17      	ldr	r3, [pc, #92]	@ (802bd24 <Move_Horizontal_Vertical_Task_Forwards_Do_Forwards+0xa4>)
+ 802bcc8:	ed93 7b00 	vldr	d7, [r3]
+ 802bccc:	f107 0310 	add.w	r3, r7, #16
+ 802bcd0:	4618      	mov	r0, r3
+ 802bcd2:	eeb0 4b47 	vmov.f64	d4, d7
+ 802bcd6:	ed97 3b0e 	vldr	d3, [r7, #56]	@ 0x38
+ 802bcda:	ed97 2b02 	vldr	d2, [r7, #8]
+ 802bcde:	ed97 1b00 	vldr	d1, [r7]
+ 802bce2:	ed97 0b0c 	vldr	d0, [r7, #48]	@ 0x30
+ 802bce6:	f7fb fdc9 	bl	802787c <GF_MSP_PID_Now_Der_adj_Com_Horizon>
+
+	GV.LeftMotor.Target_Velcity = Robot_Speed[0];
+ 802bcea:	ed97 7b04 	vldr	d7, [r7, #16]
+ 802bcee:	eefd 7bc7 	vcvt.s32.f64	s15, d7
+ 802bcf2:	ee17 2a90 	vmov	r2, s15
+ 802bcf6:	4b0a      	ldr	r3, [pc, #40]	@ (802bd20 <Move_Horizontal_Vertical_Task_Forwards_Do_Forwards+0xa0>)
+ 802bcf8:	679a      	str	r2, [r3, #120]	@ 0x78
+	GV.RightMotor.Target_Velcity = -Robot_Speed[1];
+ 802bcfa:	ed97 7b06 	vldr	d7, [r7, #24]
+ 802bcfe:	eeb1 7b47 	vneg.f64	d7, d7
+ 802bd02:	eefd 7bc7 	vcvt.s32.f64	s15, d7
+ 802bd06:	ee17 2a90 	vmov	r2, s15
+ 802bd0a:	4b05      	ldr	r3, [pc, #20]	@ (802bd20 <Move_Horizontal_Vertical_Task_Forwards_Do_Forwards+0xa0>)
+ 802bd0c:	f8c3 20f8 	str.w	r2, [r3, #248]	@ 0xf8
+}
+ 802bd10:	bf00      	nop
+ 802bd12:	3740      	adds	r7, #64	@ 0x40
+ 802bd14:	46bd      	mov	sp, r7
+ 802bd16:	bd80      	pop	{r7, pc}
+ 802bd18:	00000000 	.word	0x00000000
+ 802bd1c:	40590000 	.word	0x40590000
+ 802bd20:	24000340 	.word	0x24000340
+ 802bd24:	240000b0 	.word	0x240000b0
+
+0802bd28 <Move_Horizontal_Task_Change_Road_Backwards_Do>:
+
+
+
+void Move_Horizontal_Task_Change_Road_Backwards_Do()
+{
+ 802bd28:	b580      	push	{r7, lr}
+ 802bd2a:	b08a      	sub	sp, #40	@ 0x28
+ 802bd2c:	af00      	add	r7, sp, #0
+
+	double Robot_Speed[4]={0,0,0,0};
+ 802bd2e:	463b      	mov	r3, r7
+ 802bd30:	2220      	movs	r2, #32
+ 802bd32:	2100      	movs	r1, #0
+ 802bd34:	4618      	mov	r0, r3
+ 802bd36:	f014 fad7 	bl	80402e8 <memset>
+	double Robot_Grity=((double )GV.TL720DParameters.RF_Angle_Roll)/100;
+ 802bd3a:	4b21      	ldr	r3, [pc, #132]	@ (802bdc0 <Move_Horizontal_Task_Change_Road_Backwards_Do+0x98>)
+ 802bd3c:	f8d3 3218 	ldr.w	r3, [r3, #536]	@ 0x218
+ 802bd40:	ee07 3a90 	vmov	s15, r3
+ 802bd44:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802bd48:	ed9f 5b1b 	vldr	d5, [pc, #108]	@ 802bdb8 <Move_Horizontal_Task_Change_Road_Backwards_Do+0x90>
+ 802bd4c:	ee86 7b05 	vdiv.f64	d7, d6, d5
+ 802bd50:	ed87 7b08 	vstr	d7, [r7, #32]
+
+	GF_MSP_PID_Now_Der_adj_Com_Horizon(Robot_Grity, CV_Robot_Deri_Angle_Deg_Grity, Change_Road_Speed, Deri_Speed_Robot_MAX, System_time_SR , Robot_Speed);
+ 802bd54:	4b1b      	ldr	r3, [pc, #108]	@ (802bdc4 <Move_Horizontal_Task_Change_Road_Backwards_Do+0x9c>)
+ 802bd56:	ed93 7b00 	vldr	d7, [r3]
+ 802bd5a:	4b1b      	ldr	r3, [pc, #108]	@ (802bdc8 <Move_Horizontal_Task_Change_Road_Backwards_Do+0xa0>)
+ 802bd5c:	ed93 6b00 	vldr	d6, [r3]
+ 802bd60:	4b1a      	ldr	r3, [pc, #104]	@ (802bdcc <Move_Horizontal_Task_Change_Road_Backwards_Do+0xa4>)
+ 802bd62:	ed93 5b00 	vldr	d5, [r3]
+ 802bd66:	4b1a      	ldr	r3, [pc, #104]	@ (802bdd0 <Move_Horizontal_Task_Change_Road_Backwards_Do+0xa8>)
+ 802bd68:	ed93 4b00 	vldr	d4, [r3]
+ 802bd6c:	463b      	mov	r3, r7
+ 802bd6e:	4618      	mov	r0, r3
+ 802bd70:	eeb0 3b45 	vmov.f64	d3, d5
+ 802bd74:	eeb0 2b46 	vmov.f64	d2, d6
+ 802bd78:	eeb0 1b47 	vmov.f64	d1, d7
+ 802bd7c:	ed97 0b08 	vldr	d0, [r7, #32]
+ 802bd80:	f7fb fd7c 	bl	802787c <GF_MSP_PID_Now_Der_adj_Com_Horizon>
+
+	GV.LeftMotor.Target_Velcity =-Robot_Speed[1];
+ 802bd84:	ed97 7b02 	vldr	d7, [r7, #8]
+ 802bd88:	eeb1 7b47 	vneg.f64	d7, d7
+ 802bd8c:	eefd 7bc7 	vcvt.s32.f64	s15, d7
+ 802bd90:	ee17 2a90 	vmov	r2, s15
+ 802bd94:	4b0a      	ldr	r3, [pc, #40]	@ (802bdc0 <Move_Horizontal_Task_Change_Road_Backwards_Do+0x98>)
+ 802bd96:	679a      	str	r2, [r3, #120]	@ 0x78
+	GV.RightMotor.Target_Velcity =Robot_Speed[0];
+ 802bd98:	ed97 7b00 	vldr	d7, [r7]
+ 802bd9c:	eefd 7bc7 	vcvt.s32.f64	s15, d7
+ 802bda0:	ee17 2a90 	vmov	r2, s15
+ 802bda4:	4b06      	ldr	r3, [pc, #24]	@ (802bdc0 <Move_Horizontal_Task_Change_Road_Backwards_Do+0x98>)
+ 802bda6:	f8c3 20f8 	str.w	r2, [r3, #248]	@ 0xf8
+}
+ 802bdaa:	bf00      	nop
+ 802bdac:	3728      	adds	r7, #40	@ 0x28
+ 802bdae:	46bd      	mov	sp, r7
+ 802bdb0:	bd80      	pop	{r7, pc}
+ 802bdb2:	bf00      	nop
+ 802bdb4:	f3af 8000 	nop.w
+ 802bdb8:	00000000 	.word	0x00000000
+ 802bdbc:	40590000 	.word	0x40590000
+ 802bdc0:	24000340 	.word	0x24000340
+ 802bdc4:	2400a6d0 	.word	0x2400a6d0
+ 802bdc8:	240000d0 	.word	0x240000d0
+ 802bdcc:	240000d8 	.word	0x240000d8
+ 802bdd0:	240000b0 	.word	0x240000b0
+
+0802bdd4 <Move_Speed_Define>:
+}
+
+
+
+void Move_Speed_Define()
+{
+ 802bdd4:	b480      	push	{r7}
+ 802bdd6:	af00      	add	r7, sp, #0
+	Robot_Speed_Base= ((double)GV_Robot_Move_Speed) *Move_Base_Speed_Count_Meter_Min/10;//机器人车体速度
+ 802bdd8:	4b10      	ldr	r3, [pc, #64]	@ (802be1c <Move_Speed_Define+0x48>)
+ 802bdda:	681b      	ldr	r3, [r3, #0]
+ 802bddc:	ee07 3a90 	vmov	s15, r3
+ 802bde0:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802bde4:	4b0e      	ldr	r3, [pc, #56]	@ (802be20 <Move_Speed_Define+0x4c>)
+ 802bde6:	ed93 7b00 	vldr	d7, [r3]
+ 802bdea:	ee26 6b07 	vmul.f64	d6, d6, d7
+ 802bdee:	eeb2 5b04 	vmov.f64	d5, #36	@ 0x41200000  10.0
+ 802bdf2:	ee86 7b05 	vdiv.f64	d7, d6, d5
+ 802bdf6:	4b0b      	ldr	r3, [pc, #44]	@ (802be24 <Move_Speed_Define+0x50>)
+ 802bdf8:	ed83 7b00 	vstr	d7, [r3]
+	Robot_Countinus_Speed=((double)GV_Robot_Back_Speed)*Move_Base_Speed_Count_Meter_Min;//机器人边打边退速度
+ 802bdfc:	4b0a      	ldr	r3, [pc, #40]	@ (802be28 <Move_Speed_Define+0x54>)
+ 802bdfe:	ed93 6b00 	vldr	d6, [r3]
+ 802be02:	4b07      	ldr	r3, [pc, #28]	@ (802be20 <Move_Speed_Define+0x4c>)
+ 802be04:	ed93 7b00 	vldr	d7, [r3]
+ 802be08:	ee26 7b07 	vmul.f64	d7, d6, d7
+ 802be0c:	4b07      	ldr	r3, [pc, #28]	@ (802be2c <Move_Speed_Define+0x58>)
+ 802be0e:	ed83 7b00 	vstr	d7, [r3]
+}
+ 802be12:	bf00      	nop
+ 802be14:	46bd      	mov	sp, r7
+ 802be16:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 802be1a:	4770      	bx	lr
+ 802be1c:	2400a704 	.word	0x2400a704
+ 802be20:	240000a0 	.word	0x240000a0
+ 802be24:	2400a758 	.word	0x2400a758
+ 802be28:	2400a730 	.word	0x2400a730
+ 802be2c:	2400a760 	.word	0x2400a760
+
+0802be30 <Robot_Posture_Adjus_Gravity>:
+
+
+
+
+void Robot_Posture_Adjus_Gravity()
+{
+ 802be30:	b480      	push	{r7}
+ 802be32:	b089      	sub	sp, #36	@ 0x24
+ 802be34:	af00      	add	r7, sp, #0
+	double Sign_Flag=0;
+ 802be36:	f04f 0200 	mov.w	r2, #0
+ 802be3a:	f04f 0300 	mov.w	r3, #0
+ 802be3e:	e9c7 2306 	strd	r2, r3, [r7, #24]
+	double Speed_Factor=0;
+ 802be42:	f04f 0200 	mov.w	r2, #0
+ 802be46:	f04f 0300 	mov.w	r3, #0
+ 802be4a:	e9c7 2304 	strd	r2, r3, [r7, #16]
+	int Speed_Base=201.7*7.64*1;
+ 802be4e:	f240 6304 	movw	r3, #1540	@ 0x604
+ 802be52:	60fb      	str	r3, [r7, #12]
+
+	double Robot_Grity=((double )GV.TL720DParameters.RF_Angle_Roll)/100;
+ 802be54:	4b58      	ldr	r3, [pc, #352]	@ (802bfb8 <Robot_Posture_Adjus_Gravity+0x188>)
+ 802be56:	f8d3 3218 	ldr.w	r3, [r3, #536]	@ 0x218
+ 802be5a:	ee07 3a90 	vmov	s15, r3
+ 802be5e:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802be62:	ed9f 5b4b 	vldr	d5, [pc, #300]	@ 802bf90 <Robot_Posture_Adjus_Gravity+0x160>
+ 802be66:	ee86 7b05 	vdiv.f64	d7, d6, d5
+ 802be6a:	ed87 7b00 	vstr	d7, [r7]
+
+	Angle_Error_LLL= CV_Robot_Deri_Angle_Deg_Grity-Robot_Grity;
+ 802be6e:	4b53      	ldr	r3, [pc, #332]	@ (802bfbc <Robot_Posture_Adjus_Gravity+0x18c>)
+ 802be70:	ed93 6b00 	vldr	d6, [r3]
+ 802be74:	ed97 7b00 	vldr	d7, [r7]
+ 802be78:	ee36 7b47 	vsub.f64	d7, d6, d7
+ 802be7c:	4b50      	ldr	r3, [pc, #320]	@ (802bfc0 <Robot_Posture_Adjus_Gravity+0x190>)
+ 802be7e:	ed83 7b00 	vstr	d7, [r3]
+
+	if(Angle_Error_LLL>=180)
+ 802be82:	4b4f      	ldr	r3, [pc, #316]	@ (802bfc0 <Robot_Posture_Adjus_Gravity+0x190>)
+ 802be84:	ed93 7b00 	vldr	d7, [r3]
+ 802be88:	ed9f 6b43 	vldr	d6, [pc, #268]	@ 802bf98 <Robot_Posture_Adjus_Gravity+0x168>
+ 802be8c:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 802be90:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802be94:	db0a      	blt.n	802beac <Robot_Posture_Adjus_Gravity+0x7c>
+	{
+		Angle_Error_LLL=Angle_Error_LLL-360;
+ 802be96:	4b4a      	ldr	r3, [pc, #296]	@ (802bfc0 <Robot_Posture_Adjus_Gravity+0x190>)
+ 802be98:	ed93 7b00 	vldr	d7, [r3]
+ 802be9c:	ed9f 6b40 	vldr	d6, [pc, #256]	@ 802bfa0 <Robot_Posture_Adjus_Gravity+0x170>
+ 802bea0:	ee37 7b46 	vsub.f64	d7, d7, d6
+ 802bea4:	4b46      	ldr	r3, [pc, #280]	@ (802bfc0 <Robot_Posture_Adjus_Gravity+0x190>)
+ 802bea6:	ed83 7b00 	vstr	d7, [r3]
+ 802beaa:	e013      	b.n	802bed4 <Robot_Posture_Adjus_Gravity+0xa4>
+	}
+	else if(Angle_Error_LLL<=-180)
+ 802beac:	4b44      	ldr	r3, [pc, #272]	@ (802bfc0 <Robot_Posture_Adjus_Gravity+0x190>)
+ 802beae:	ed93 7b00 	vldr	d7, [r3]
+ 802beb2:	ed9f 6b3d 	vldr	d6, [pc, #244]	@ 802bfa8 <Robot_Posture_Adjus_Gravity+0x178>
+ 802beb6:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 802beba:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802bebe:	d809      	bhi.n	802bed4 <Robot_Posture_Adjus_Gravity+0xa4>
+	{
+		Angle_Error_LLL=Angle_Error_LLL+360;
+ 802bec0:	4b3f      	ldr	r3, [pc, #252]	@ (802bfc0 <Robot_Posture_Adjus_Gravity+0x190>)
+ 802bec2:	ed93 7b00 	vldr	d7, [r3]
+ 802bec6:	ed9f 6b36 	vldr	d6, [pc, #216]	@ 802bfa0 <Robot_Posture_Adjus_Gravity+0x170>
+ 802beca:	ee37 7b06 	vadd.f64	d7, d7, d6
+ 802bece:	4b3c      	ldr	r3, [pc, #240]	@ (802bfc0 <Robot_Posture_Adjus_Gravity+0x190>)
+ 802bed0:	ed83 7b00 	vstr	d7, [r3]
+	}
+
+	if(Angle_Error_LLL>=0)
+ 802bed4:	4b3a      	ldr	r3, [pc, #232]	@ (802bfc0 <Robot_Posture_Adjus_Gravity+0x190>)
+ 802bed6:	ed93 7b00 	vldr	d7, [r3]
+ 802beda:	eeb5 7bc0 	vcmpe.f64	d7, #0.0
+ 802bede:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802bee2:	db05      	blt.n	802bef0 <Robot_Posture_Adjus_Gravity+0xc0>
+	{
+		Sign_Flag=1;
+ 802bee4:	f04f 0200 	mov.w	r2, #0
+ 802bee8:	4b36      	ldr	r3, [pc, #216]	@ (802bfc4 <Robot_Posture_Adjus_Gravity+0x194>)
+ 802beea:	e9c7 2306 	strd	r2, r3, [r7, #24]
+ 802beee:	e004      	b.n	802befa <Robot_Posture_Adjus_Gravity+0xca>
+	}
+	else
+	{
+		Sign_Flag=-1;
+ 802bef0:	f04f 0200 	mov.w	r2, #0
+ 802bef4:	4b34      	ldr	r3, [pc, #208]	@ (802bfc8 <Robot_Posture_Adjus_Gravity+0x198>)
+ 802bef6:	e9c7 2306 	strd	r2, r3, [r7, #24]
+	}
+	Angle_Error_LLL=fabs(Angle_Error_LLL);
+ 802befa:	4b31      	ldr	r3, [pc, #196]	@ (802bfc0 <Robot_Posture_Adjus_Gravity+0x190>)
+ 802befc:	ed93 7b00 	vldr	d7, [r3]
+ 802bf00:	eeb0 7bc7 	vabs.f64	d7, d7
+ 802bf04:	4b2e      	ldr	r3, [pc, #184]	@ (802bfc0 <Robot_Posture_Adjus_Gravity+0x190>)
+ 802bf06:	ed83 7b00 	vstr	d7, [r3]
+	if(Angle_Error_LLL>5)
+ 802bf0a:	4b2d      	ldr	r3, [pc, #180]	@ (802bfc0 <Robot_Posture_Adjus_Gravity+0x190>)
+ 802bf0c:	ed93 7b00 	vldr	d7, [r3]
+ 802bf10:	eeb1 6b04 	vmov.f64	d6, #20	@ 0x40a00000  5.0
+ 802bf14:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 802bf18:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802bf1c:	dd06      	ble.n	802bf2c <Robot_Posture_Adjus_Gravity+0xfc>
+	{
+		Speed_Factor=2;
+ 802bf1e:	f04f 0200 	mov.w	r2, #0
+ 802bf22:	f04f 4380 	mov.w	r3, #1073741824	@ 0x40000000
+ 802bf26:	e9c7 2304 	strd	r2, r3, [r7, #16]
+ 802bf2a:	e004      	b.n	802bf36 <Robot_Posture_Adjus_Gravity+0x106>
+	}
+	else
+	{
+		Speed_Factor=0.4;
+ 802bf2c:	a320      	add	r3, pc, #128	@ (adr r3, 802bfb0 <Robot_Posture_Adjus_Gravity+0x180>)
+ 802bf2e:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802bf32:	e9c7 2304 	strd	r2, r3, [r7, #16]
+	}
+	GV.LeftMotor.Target_Velcity=Speed_Factor*Sign_Flag*Speed_Base;
+ 802bf36:	ed97 6b04 	vldr	d6, [r7, #16]
+ 802bf3a:	ed97 7b06 	vldr	d7, [r7, #24]
+ 802bf3e:	ee26 6b07 	vmul.f64	d6, d6, d7
+ 802bf42:	68fb      	ldr	r3, [r7, #12]
+ 802bf44:	ee07 3a90 	vmov	s15, r3
+ 802bf48:	eeb8 7be7 	vcvt.f64.s32	d7, s15
+ 802bf4c:	ee26 7b07 	vmul.f64	d7, d6, d7
+ 802bf50:	eefd 7bc7 	vcvt.s32.f64	s15, d7
+ 802bf54:	ee17 2a90 	vmov	r2, s15
+ 802bf58:	4b17      	ldr	r3, [pc, #92]	@ (802bfb8 <Robot_Posture_Adjus_Gravity+0x188>)
+ 802bf5a:	679a      	str	r2, [r3, #120]	@ 0x78
+	GV.RightMotor.Target_Velcity=Speed_Factor*Sign_Flag*Speed_Base;
+ 802bf5c:	ed97 6b04 	vldr	d6, [r7, #16]
+ 802bf60:	ed97 7b06 	vldr	d7, [r7, #24]
+ 802bf64:	ee26 6b07 	vmul.f64	d6, d6, d7
+ 802bf68:	68fb      	ldr	r3, [r7, #12]
+ 802bf6a:	ee07 3a90 	vmov	s15, r3
+ 802bf6e:	eeb8 7be7 	vcvt.f64.s32	d7, s15
+ 802bf72:	ee26 7b07 	vmul.f64	d7, d6, d7
+ 802bf76:	eefd 7bc7 	vcvt.s32.f64	s15, d7
+ 802bf7a:	ee17 2a90 	vmov	r2, s15
+ 802bf7e:	4b0e      	ldr	r3, [pc, #56]	@ (802bfb8 <Robot_Posture_Adjus_Gravity+0x188>)
+ 802bf80:	f8c3 20f8 	str.w	r2, [r3, #248]	@ 0xf8
+}
+ 802bf84:	bf00      	nop
+ 802bf86:	3724      	adds	r7, #36	@ 0x24
+ 802bf88:	46bd      	mov	sp, r7
+ 802bf8a:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 802bf8e:	4770      	bx	lr
+ 802bf90:	00000000 	.word	0x00000000
+ 802bf94:	40590000 	.word	0x40590000
+ 802bf98:	00000000 	.word	0x00000000
+ 802bf9c:	40668000 	.word	0x40668000
+ 802bfa0:	00000000 	.word	0x00000000
+ 802bfa4:	40768000 	.word	0x40768000
+ 802bfa8:	00000000 	.word	0x00000000
+ 802bfac:	c0668000 	.word	0xc0668000
+ 802bfb0:	9999999a 	.word	0x9999999a
+ 802bfb4:	3fd99999 	.word	0x3fd99999
+ 802bfb8:	24000340 	.word	0x24000340
+ 802bfbc:	2400a6d0 	.word	0x2400a6d0
+ 802bfc0:	2400a9e8 	.word	0x2400a9e8
+ 802bfc4:	3ff00000 	.word	0x3ff00000
+ 802bfc8:	bff00000 	.word	0xbff00000
+ 802bfcc:	00000000 	.word	0x00000000
+
+0802bfd0 <Robot_Posture_Adjus_Plane>:
+
+
+void Robot_Posture_Adjus_Plane()
+{
+ 802bfd0:	b480      	push	{r7}
+ 802bfd2:	b089      	sub	sp, #36	@ 0x24
+ 802bfd4:	af00      	add	r7, sp, #0
+	double Sign_Flag=0;
+ 802bfd6:	f04f 0200 	mov.w	r2, #0
+ 802bfda:	f04f 0300 	mov.w	r3, #0
+ 802bfde:	e9c7 2306 	strd	r2, r3, [r7, #24]
+	double Speed_Factor=0;
+ 802bfe2:	f04f 0200 	mov.w	r2, #0
+ 802bfe6:	f04f 0300 	mov.w	r3, #0
+ 802bfea:	e9c7 2304 	strd	r2, r3, [r7, #16]
+	int Speed_Base=201.7*7.64*1;
+ 802bfee:	f240 6304 	movw	r3, #1540	@ 0x604
+ 802bff2:	60fb      	str	r3, [r7, #12]
+
+	double Robot_Plane=MF40G_Angle_Add_Deg;
+ 802bff4:	4b54      	ldr	r3, [pc, #336]	@ (802c148 <Robot_Posture_Adjus_Plane+0x178>)
+ 802bff6:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802bffa:	e9c7 2300 	strd	r2, r3, [r7]
+
+	Angle_Error_LLL= CV_Robot_Deri_Angle_Deg_Plane-Robot_Plane;
+ 802bffe:	4b53      	ldr	r3, [pc, #332]	@ (802c14c <Robot_Posture_Adjus_Plane+0x17c>)
+ 802c000:	ed93 6b00 	vldr	d6, [r3]
+ 802c004:	ed97 7b00 	vldr	d7, [r7]
+ 802c008:	ee36 7b47 	vsub.f64	d7, d6, d7
+ 802c00c:	4b50      	ldr	r3, [pc, #320]	@ (802c150 <Robot_Posture_Adjus_Plane+0x180>)
+ 802c00e:	ed83 7b00 	vstr	d7, [r3]
+
+	if(Angle_Error_LLL>=180)
+ 802c012:	4b4f      	ldr	r3, [pc, #316]	@ (802c150 <Robot_Posture_Adjus_Plane+0x180>)
+ 802c014:	ed93 7b00 	vldr	d7, [r3]
+ 802c018:	ed9f 6b43 	vldr	d6, [pc, #268]	@ 802c128 <Robot_Posture_Adjus_Plane+0x158>
+ 802c01c:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 802c020:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802c024:	db0a      	blt.n	802c03c <Robot_Posture_Adjus_Plane+0x6c>
+	{
+		Angle_Error_LLL=Angle_Error_LLL-360;
+ 802c026:	4b4a      	ldr	r3, [pc, #296]	@ (802c150 <Robot_Posture_Adjus_Plane+0x180>)
+ 802c028:	ed93 7b00 	vldr	d7, [r3]
+ 802c02c:	ed9f 6b40 	vldr	d6, [pc, #256]	@ 802c130 <Robot_Posture_Adjus_Plane+0x160>
+ 802c030:	ee37 7b46 	vsub.f64	d7, d7, d6
+ 802c034:	4b46      	ldr	r3, [pc, #280]	@ (802c150 <Robot_Posture_Adjus_Plane+0x180>)
+ 802c036:	ed83 7b00 	vstr	d7, [r3]
+ 802c03a:	e013      	b.n	802c064 <Robot_Posture_Adjus_Plane+0x94>
+	}
+	else if(Angle_Error_LLL<=-180)
+ 802c03c:	4b44      	ldr	r3, [pc, #272]	@ (802c150 <Robot_Posture_Adjus_Plane+0x180>)
+ 802c03e:	ed93 7b00 	vldr	d7, [r3]
+ 802c042:	ed9f 6b3d 	vldr	d6, [pc, #244]	@ 802c138 <Robot_Posture_Adjus_Plane+0x168>
+ 802c046:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 802c04a:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802c04e:	d809      	bhi.n	802c064 <Robot_Posture_Adjus_Plane+0x94>
+	{
+		Angle_Error_LLL=Angle_Error_LLL+360;
+ 802c050:	4b3f      	ldr	r3, [pc, #252]	@ (802c150 <Robot_Posture_Adjus_Plane+0x180>)
+ 802c052:	ed93 7b00 	vldr	d7, [r3]
+ 802c056:	ed9f 6b36 	vldr	d6, [pc, #216]	@ 802c130 <Robot_Posture_Adjus_Plane+0x160>
+ 802c05a:	ee37 7b06 	vadd.f64	d7, d7, d6
+ 802c05e:	4b3c      	ldr	r3, [pc, #240]	@ (802c150 <Robot_Posture_Adjus_Plane+0x180>)
+ 802c060:	ed83 7b00 	vstr	d7, [r3]
+	}
+
+	if(Angle_Error_LLL>=0)
+ 802c064:	4b3a      	ldr	r3, [pc, #232]	@ (802c150 <Robot_Posture_Adjus_Plane+0x180>)
+ 802c066:	ed93 7b00 	vldr	d7, [r3]
+ 802c06a:	eeb5 7bc0 	vcmpe.f64	d7, #0.0
+ 802c06e:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802c072:	db05      	blt.n	802c080 <Robot_Posture_Adjus_Plane+0xb0>
+	{
+		Sign_Flag=-1;
+ 802c074:	f04f 0200 	mov.w	r2, #0
+ 802c078:	4b36      	ldr	r3, [pc, #216]	@ (802c154 <Robot_Posture_Adjus_Plane+0x184>)
+ 802c07a:	e9c7 2306 	strd	r2, r3, [r7, #24]
+ 802c07e:	e004      	b.n	802c08a <Robot_Posture_Adjus_Plane+0xba>
+	}
+	else
+	{
+		Sign_Flag=1;
+ 802c080:	f04f 0200 	mov.w	r2, #0
+ 802c084:	4b34      	ldr	r3, [pc, #208]	@ (802c158 <Robot_Posture_Adjus_Plane+0x188>)
+ 802c086:	e9c7 2306 	strd	r2, r3, [r7, #24]
+	}
+	Angle_Error_LLL=fabs(Angle_Error_LLL);
+ 802c08a:	4b31      	ldr	r3, [pc, #196]	@ (802c150 <Robot_Posture_Adjus_Plane+0x180>)
+ 802c08c:	ed93 7b00 	vldr	d7, [r3]
+ 802c090:	eeb0 7bc7 	vabs.f64	d7, d7
+ 802c094:	4b2e      	ldr	r3, [pc, #184]	@ (802c150 <Robot_Posture_Adjus_Plane+0x180>)
+ 802c096:	ed83 7b00 	vstr	d7, [r3]
+	if(Angle_Error_LLL>5)
+ 802c09a:	4b2d      	ldr	r3, [pc, #180]	@ (802c150 <Robot_Posture_Adjus_Plane+0x180>)
+ 802c09c:	ed93 7b00 	vldr	d7, [r3]
+ 802c0a0:	eeb1 6b04 	vmov.f64	d6, #20	@ 0x40a00000  5.0
+ 802c0a4:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 802c0a8:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802c0ac:	dd06      	ble.n	802c0bc <Robot_Posture_Adjus_Plane+0xec>
+	{
+		Speed_Factor=2;
+ 802c0ae:	f04f 0200 	mov.w	r2, #0
+ 802c0b2:	f04f 4380 	mov.w	r3, #1073741824	@ 0x40000000
+ 802c0b6:	e9c7 2304 	strd	r2, r3, [r7, #16]
+ 802c0ba:	e004      	b.n	802c0c6 <Robot_Posture_Adjus_Plane+0xf6>
+	}
+	else
+	{
+		Speed_Factor=0.4;
+ 802c0bc:	a320      	add	r3, pc, #128	@ (adr r3, 802c140 <Robot_Posture_Adjus_Plane+0x170>)
+ 802c0be:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802c0c2:	e9c7 2304 	strd	r2, r3, [r7, #16]
+	}
+	GV.LeftMotor.Target_Velcity=-Speed_Factor*Sign_Flag*Speed_Base;
+ 802c0c6:	ed97 7b04 	vldr	d7, [r7, #16]
+ 802c0ca:	eeb1 6b47 	vneg.f64	d6, d7
+ 802c0ce:	ed97 7b06 	vldr	d7, [r7, #24]
+ 802c0d2:	ee26 6b07 	vmul.f64	d6, d6, d7
+ 802c0d6:	68fb      	ldr	r3, [r7, #12]
+ 802c0d8:	ee07 3a90 	vmov	s15, r3
+ 802c0dc:	eeb8 7be7 	vcvt.f64.s32	d7, s15
+ 802c0e0:	ee26 7b07 	vmul.f64	d7, d6, d7
+ 802c0e4:	eefd 7bc7 	vcvt.s32.f64	s15, d7
+ 802c0e8:	ee17 2a90 	vmov	r2, s15
+ 802c0ec:	4b1b      	ldr	r3, [pc, #108]	@ (802c15c <Robot_Posture_Adjus_Plane+0x18c>)
+ 802c0ee:	679a      	str	r2, [r3, #120]	@ 0x78
+	GV.RightMotor.Target_Velcity=-Speed_Factor*Sign_Flag*Speed_Base;
+ 802c0f0:	ed97 7b04 	vldr	d7, [r7, #16]
+ 802c0f4:	eeb1 6b47 	vneg.f64	d6, d7
+ 802c0f8:	ed97 7b06 	vldr	d7, [r7, #24]
+ 802c0fc:	ee26 6b07 	vmul.f64	d6, d6, d7
+ 802c100:	68fb      	ldr	r3, [r7, #12]
+ 802c102:	ee07 3a90 	vmov	s15, r3
+ 802c106:	eeb8 7be7 	vcvt.f64.s32	d7, s15
+ 802c10a:	ee26 7b07 	vmul.f64	d7, d6, d7
+ 802c10e:	eefd 7bc7 	vcvt.s32.f64	s15, d7
+ 802c112:	ee17 2a90 	vmov	r2, s15
+ 802c116:	4b11      	ldr	r3, [pc, #68]	@ (802c15c <Robot_Posture_Adjus_Plane+0x18c>)
+ 802c118:	f8c3 20f8 	str.w	r2, [r3, #248]	@ 0xf8
+}
+ 802c11c:	bf00      	nop
+ 802c11e:	3724      	adds	r7, #36	@ 0x24
+ 802c120:	46bd      	mov	sp, r7
+ 802c122:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 802c126:	4770      	bx	lr
+ 802c128:	00000000 	.word	0x00000000
+ 802c12c:	40668000 	.word	0x40668000
+ 802c130:	00000000 	.word	0x00000000
+ 802c134:	40768000 	.word	0x40768000
+ 802c138:	00000000 	.word	0x00000000
+ 802c13c:	c0668000 	.word	0xc0668000
+ 802c140:	9999999a 	.word	0x9999999a
+ 802c144:	3fd99999 	.word	0x3fd99999
+ 802c148:	2400a788 	.word	0x2400a788
+ 802c14c:	2400a6d8 	.word	0x2400a6d8
+ 802c150:	2400a9e8 	.word	0x2400a9e8
+ 802c154:	bff00000 	.word	0xbff00000
+ 802c158:	3ff00000 	.word	0x3ff00000
+ 802c15c:	24000340 	.word	0x24000340
+
+0802c160 <Vertical_Angle_Judge>:
+
+
+
+
+void Vertical_Angle_Judge()
+{
+ 802c160:	b480      	push	{r7}
+ 802c162:	b083      	sub	sp, #12
+ 802c164:	af00      	add	r7, sp, #0
+
+	double Robot_Grity=((double )GV.TL720DParameters.RF_Angle_Roll)/100;
+ 802c166:	4b12      	ldr	r3, [pc, #72]	@ (802c1b0 <Vertical_Angle_Judge+0x50>)
+ 802c168:	f8d3 3218 	ldr.w	r3, [r3, #536]	@ 0x218
+ 802c16c:	ee07 3a90 	vmov	s15, r3
+ 802c170:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802c174:	ed9f 5b0c 	vldr	d5, [pc, #48]	@ 802c1a8 <Vertical_Angle_Judge+0x48>
+ 802c178:	ee86 7b05 	vdiv.f64	d7, d6, d5
+ 802c17c:	ed87 7b00 	vstr	d7, [r7]
+	Vertical_Der_Angle_Deg= GV_Robot_Vertical_Adjust;
+ 802c180:	4b0c      	ldr	r3, [pc, #48]	@ (802c1b4 <Vertical_Angle_Judge+0x54>)
+ 802c182:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802c186:	490c      	ldr	r1, [pc, #48]	@ (802c1b8 <Vertical_Angle_Judge+0x58>)
+ 802c188:	e9c1 2300 	strd	r2, r3, [r1]
+//		if(Vertical_Der_Angle_Deg>180)
+//		{
+//			Vertical_Der_Angle_Deg=Vertical_Der_Angle_Deg-360;
+//		}
+//	}
+	CV_Robot_Deri_Angle_Deg_Grity=Vertical_Der_Angle_Deg;
+ 802c18c:	4b0a      	ldr	r3, [pc, #40]	@ (802c1b8 <Vertical_Angle_Judge+0x58>)
+ 802c18e:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802c192:	490a      	ldr	r1, [pc, #40]	@ (802c1bc <Vertical_Angle_Judge+0x5c>)
+ 802c194:	e9c1 2300 	strd	r2, r3, [r1]
+}
+ 802c198:	bf00      	nop
+ 802c19a:	370c      	adds	r7, #12
+ 802c19c:	46bd      	mov	sp, r7
+ 802c19e:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 802c1a2:	4770      	bx	lr
+ 802c1a4:	f3af 8000 	nop.w
+ 802c1a8:	00000000 	.word	0x00000000
+ 802c1ac:	40590000 	.word	0x40590000
+ 802c1b0:	24000340 	.word	0x24000340
+ 802c1b4:	2400a740 	.word	0x2400a740
+ 802c1b8:	2400a6e8 	.word	0x2400a6e8
+ 802c1bc:	2400a6d0 	.word	0x2400a6d0
+
+0802c1c0 <Vertical_Angle_Judge_Uptata_1>:
+
+void Vertical_Angle_Judge_Uptata_1()
+{
+ 802c1c0:	b480      	push	{r7}
+ 802c1c2:	b083      	sub	sp, #12
+ 802c1c4:	af00      	add	r7, sp, #0
+	double Robot_Grity=((double )GV.TL720DParameters.RF_Angle_Roll)/100;
+ 802c1c6:	4b12      	ldr	r3, [pc, #72]	@ (802c210 <Vertical_Angle_Judge_Uptata_1+0x50>)
+ 802c1c8:	f8d3 3218 	ldr.w	r3, [r3, #536]	@ 0x218
+ 802c1cc:	ee07 3a90 	vmov	s15, r3
+ 802c1d0:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802c1d4:	ed9f 5b0c 	vldr	d5, [pc, #48]	@ 802c208 <Vertical_Angle_Judge_Uptata_1+0x48>
+ 802c1d8:	ee86 7b05 	vdiv.f64	d7, d6, d5
+ 802c1dc:	ed87 7b00 	vstr	d7, [r7]
+//	}
+//	else if((Robot_Grity>-90)&&(Robot_Grity<=90))
+//	{
+//		Vertical_Der_Angle_Deg=GV_Robot_Vertical_Adjust;
+//	}
+	Vertical_Der_Angle_Deg=GV_Robot_Vertical_Adjust;
+ 802c1e0:	4b0c      	ldr	r3, [pc, #48]	@ (802c214 <Vertical_Angle_Judge_Uptata_1+0x54>)
+ 802c1e2:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802c1e6:	490c      	ldr	r1, [pc, #48]	@ (802c218 <Vertical_Angle_Judge_Uptata_1+0x58>)
+ 802c1e8:	e9c1 2300 	strd	r2, r3, [r1]
+	CV_Robot_Deri_Angle_Deg_Grity=Vertical_Der_Angle_Deg;
+ 802c1ec:	4b0a      	ldr	r3, [pc, #40]	@ (802c218 <Vertical_Angle_Judge_Uptata_1+0x58>)
+ 802c1ee:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802c1f2:	490a      	ldr	r1, [pc, #40]	@ (802c21c <Vertical_Angle_Judge_Uptata_1+0x5c>)
+ 802c1f4:	e9c1 2300 	strd	r2, r3, [r1]
+}
+ 802c1f8:	bf00      	nop
+ 802c1fa:	370c      	adds	r7, #12
+ 802c1fc:	46bd      	mov	sp, r7
+ 802c1fe:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 802c202:	4770      	bx	lr
+ 802c204:	f3af 8000 	nop.w
+ 802c208:	00000000 	.word	0x00000000
+ 802c20c:	40590000 	.word	0x40590000
+ 802c210:	24000340 	.word	0x24000340
+ 802c214:	2400a740 	.word	0x2400a740
+ 802c218:	2400a6e8 	.word	0x2400a6e8
+ 802c21c:	2400a6d0 	.word	0x2400a6d0
+
+0802c220 <Change_Road_Down_Up_Right_To_Left>:
+
+
+void Change_Road_Down_Up_Right_To_Left()
+{
+ 802c220:	b580      	push	{r7, lr}
+ 802c222:	b084      	sub	sp, #16
+ 802c224:	af00      	add	r7, sp, #0
+	static int Change_R_L_Count;
+	double Der_Angle_Down_Up[2]={90,0};
+ 802c226:	f04f 0200 	mov.w	r2, #0
+ 802c22a:	4b43      	ldr	r3, [pc, #268]	@ (802c338 <Change_Road_Down_Up_Right_To_Left+0x118>)
+ 802c22c:	e9c7 2300 	strd	r2, r3, [r7]
+ 802c230:	f04f 0200 	mov.w	r2, #0
+ 802c234:	f04f 0300 	mov.w	r3, #0
+ 802c238:	e9c7 2302 	strd	r2, r3, [r7, #8]
+	switch(CRLU_Flag)
+ 802c23c:	4b3f      	ldr	r3, [pc, #252]	@ (802c33c <Change_Road_Down_Up_Right_To_Left+0x11c>)
+ 802c23e:	681b      	ldr	r3, [r3, #0]
+ 802c240:	2b04      	cmp	r3, #4
+ 802c242:	d871      	bhi.n	802c328 <Change_Road_Down_Up_Right_To_Left+0x108>
+ 802c244:	a201      	add	r2, pc, #4	@ (adr r2, 802c24c <Change_Road_Down_Up_Right_To_Left+0x2c>)
+ 802c246:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 802c24a:	bf00      	nop
+ 802c24c:	0802c261 	.word	0x0802c261
+ 802c250:	0802c299 	.word	0x0802c299
+ 802c254:	0802c2a9 	.word	0x0802c2a9
+ 802c258:	0802c2e7 	.word	0x0802c2e7
+ 802c25c:	0802c319 	.word	0x0802c319
+	{
+	case 0://两轮速度相同转向
+		CV_Robot_Deri_Angle_Deg_Grity=Der_Angle_Down_Up[0];
+ 802c260:	e9d7 2300 	ldrd	r2, r3, [r7]
+ 802c264:	4936      	ldr	r1, [pc, #216]	@ (802c340 <Change_Road_Down_Up_Right_To_Left+0x120>)
+ 802c266:	e9c1 2300 	strd	r2, r3, [r1]
+		Robot_Posture_Adjus_Gravity();
+ 802c26a:	f7ff fde1 	bl	802be30 <Robot_Posture_Adjus_Gravity>
+		if(Angle_Error_LLL<Error_Cont_Thresh)
+ 802c26e:	4b35      	ldr	r3, [pc, #212]	@ (802c344 <Change_Road_Down_Up_Right_To_Left+0x124>)
+ 802c270:	ed93 6b00 	vldr	d6, [r3]
+ 802c274:	4b34      	ldr	r3, [pc, #208]	@ (802c348 <Change_Road_Down_Up_Right_To_Left+0x128>)
+ 802c276:	ed93 7b00 	vldr	d7, [r3]
+ 802c27a:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802c27e:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802c282:	d400      	bmi.n	802c286 <Change_Road_Down_Up_Right_To_Left+0x66>
+		{
+			CRLU_Flag++;
+			Change_R_L_Count=0;
+		}
+		break;
+ 802c284:	e053      	b.n	802c32e <Change_Road_Down_Up_Right_To_Left+0x10e>
+			CRLU_Flag++;
+ 802c286:	4b2d      	ldr	r3, [pc, #180]	@ (802c33c <Change_Road_Down_Up_Right_To_Left+0x11c>)
+ 802c288:	681b      	ldr	r3, [r3, #0]
+ 802c28a:	3301      	adds	r3, #1
+ 802c28c:	4a2b      	ldr	r2, [pc, #172]	@ (802c33c <Change_Road_Down_Up_Right_To_Left+0x11c>)
+ 802c28e:	6013      	str	r3, [r2, #0]
+			Change_R_L_Count=0;
+ 802c290:	4b2e      	ldr	r3, [pc, #184]	@ (802c34c <Change_Road_Down_Up_Right_To_Left+0x12c>)
+ 802c292:	2200      	movs	r2, #0
+ 802c294:	601a      	str	r2, [r3, #0]
+		break;
+ 802c296:	e04a      	b.n	802c32e <Change_Road_Down_Up_Right_To_Left+0x10e>
+	case 1://计算换道后退时间，设定后退速度
+		Vertical_Change_Road_Back_Time_Compute();
+ 802c298:	f001 f96a 	bl	802d570 <Vertical_Change_Road_Back_Time_Compute>
+		CRLU_Flag++;
+ 802c29c:	4b27      	ldr	r3, [pc, #156]	@ (802c33c <Change_Road_Down_Up_Right_To_Left+0x11c>)
+ 802c29e:	681b      	ldr	r3, [r3, #0]
+ 802c2a0:	3301      	adds	r3, #1
+ 802c2a2:	4a26      	ldr	r2, [pc, #152]	@ (802c33c <Change_Road_Down_Up_Right_To_Left+0x11c>)
+ 802c2a4:	6013      	str	r3, [r2, #0]
+		break;
+ 802c2a6:	e042      	b.n	802c32e <Change_Road_Down_Up_Right_To_Left+0x10e>
+	case 2://PID转向期望角度1
+		Change_R_L_Count++;
+ 802c2a8:	4b28      	ldr	r3, [pc, #160]	@ (802c34c <Change_Road_Down_Up_Right_To_Left+0x12c>)
+ 802c2aa:	681b      	ldr	r3, [r3, #0]
+ 802c2ac:	3301      	adds	r3, #1
+ 802c2ae:	4a27      	ldr	r2, [pc, #156]	@ (802c34c <Change_Road_Down_Up_Right_To_Left+0x12c>)
+ 802c2b0:	6013      	str	r3, [r2, #0]
+		Move_Horizontal_Task_Change_Road_Backwards_Do();
+ 802c2b2:	f7ff fd39 	bl	802bd28 <Move_Horizontal_Task_Change_Road_Backwards_Do>
+		if(Change_R_L_Count>Vertical_Change_Road_Time)
+ 802c2b6:	4b25      	ldr	r3, [pc, #148]	@ (802c34c <Change_Road_Down_Up_Right_To_Left+0x12c>)
+ 802c2b8:	681b      	ldr	r3, [r3, #0]
+ 802c2ba:	ee07 3a90 	vmov	s15, r3
+ 802c2be:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802c2c2:	4b23      	ldr	r3, [pc, #140]	@ (802c350 <Change_Road_Down_Up_Right_To_Left+0x130>)
+ 802c2c4:	ed93 7b00 	vldr	d7, [r3]
+ 802c2c8:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802c2cc:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802c2d0:	dc00      	bgt.n	802c2d4 <Change_Road_Down_Up_Right_To_Left+0xb4>
+		{
+			CRLU_Flag++;
+			Change_R_L_Count=0;
+		}
+		break;
+ 802c2d2:	e02c      	b.n	802c32e <Change_Road_Down_Up_Right_To_Left+0x10e>
+			CRLU_Flag++;
+ 802c2d4:	4b19      	ldr	r3, [pc, #100]	@ (802c33c <Change_Road_Down_Up_Right_To_Left+0x11c>)
+ 802c2d6:	681b      	ldr	r3, [r3, #0]
+ 802c2d8:	3301      	adds	r3, #1
+ 802c2da:	4a18      	ldr	r2, [pc, #96]	@ (802c33c <Change_Road_Down_Up_Right_To_Left+0x11c>)
+ 802c2dc:	6013      	str	r3, [r2, #0]
+			Change_R_L_Count=0;
+ 802c2de:	4b1b      	ldr	r3, [pc, #108]	@ (802c34c <Change_Road_Down_Up_Right_To_Left+0x12c>)
+ 802c2e0:	2200      	movs	r2, #0
+ 802c2e2:	601a      	str	r2, [r3, #0]
+		break;
+ 802c2e4:	e023      	b.n	802c32e <Change_Road_Down_Up_Right_To_Left+0x10e>
+	case 3://后退指定距离
+		CV_Robot_Deri_Angle_Deg_Grity=Der_Angle_Down_Up[1];
+ 802c2e6:	e9d7 2302 	ldrd	r2, r3, [r7, #8]
+ 802c2ea:	4915      	ldr	r1, [pc, #84]	@ (802c340 <Change_Road_Down_Up_Right_To_Left+0x120>)
+ 802c2ec:	e9c1 2300 	strd	r2, r3, [r1]
+		Robot_Posture_Adjus_Gravity();
+ 802c2f0:	f7ff fd9e 	bl	802be30 <Robot_Posture_Adjus_Gravity>
+		if(Angle_Error_LLL<Error_Cont_Thresh)
+ 802c2f4:	4b13      	ldr	r3, [pc, #76]	@ (802c344 <Change_Road_Down_Up_Right_To_Left+0x124>)
+ 802c2f6:	ed93 6b00 	vldr	d6, [r3]
+ 802c2fa:	4b13      	ldr	r3, [pc, #76]	@ (802c348 <Change_Road_Down_Up_Right_To_Left+0x128>)
+ 802c2fc:	ed93 7b00 	vldr	d7, [r3]
+ 802c300:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802c304:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802c308:	d400      	bmi.n	802c30c <Change_Road_Down_Up_Right_To_Left+0xec>
+		{
+			CRLU_Flag++;
+		}
+		break;
+ 802c30a:	e010      	b.n	802c32e <Change_Road_Down_Up_Right_To_Left+0x10e>
+			CRLU_Flag++;
+ 802c30c:	4b0b      	ldr	r3, [pc, #44]	@ (802c33c <Change_Road_Down_Up_Right_To_Left+0x11c>)
+ 802c30e:	681b      	ldr	r3, [r3, #0]
+ 802c310:	3301      	adds	r3, #1
+ 802c312:	4a0a      	ldr	r2, [pc, #40]	@ (802c33c <Change_Road_Down_Up_Right_To_Left+0x11c>)
+ 802c314:	6013      	str	r3, [r2, #0]
+		break;
+ 802c316:	e00a      	b.n	802c32e <Change_Road_Down_Up_Right_To_Left+0x10e>
+	case 4://到达位置
+		GV.LeftMotor.Target_Velcity=0;
+ 802c318:	4b0e      	ldr	r3, [pc, #56]	@ (802c354 <Change_Road_Down_Up_Right_To_Left+0x134>)
+ 802c31a:	2200      	movs	r2, #0
+ 802c31c:	679a      	str	r2, [r3, #120]	@ 0x78
+		GV.RightMotor.Target_Velcity=0;
+ 802c31e:	4b0d      	ldr	r3, [pc, #52]	@ (802c354 <Change_Road_Down_Up_Right_To_Left+0x134>)
+ 802c320:	2200      	movs	r2, #0
+ 802c322:	f8c3 20f8 	str.w	r2, [r3, #248]	@ 0xf8
+		break;
+ 802c326:	e002      	b.n	802c32e <Change_Road_Down_Up_Right_To_Left+0x10e>
+	default:
+		HALT_State_Do();
+ 802c328:	f003 ff1e 	bl	8030168 <HALT_State_Do>
+		break;
+ 802c32c:	bf00      	nop
+	}
+//	  UltraStopReverse(CRLU_Flag);
+}
+ 802c32e:	bf00      	nop
+ 802c330:	3710      	adds	r7, #16
+ 802c332:	46bd      	mov	sp, r7
+ 802c334:	bd80      	pop	{r7, pc}
+ 802c336:	bf00      	nop
+ 802c338:	40568000 	.word	0x40568000
+ 802c33c:	2400a9f0 	.word	0x2400a9f0
+ 802c340:	2400a6d0 	.word	0x2400a6d0
+ 802c344:	2400a9e8 	.word	0x2400a9e8
+ 802c348:	24000090 	.word	0x24000090
+ 802c34c:	2400a8ac 	.word	0x2400a8ac
+ 802c350:	240000b8 	.word	0x240000b8
+ 802c354:	24000340 	.word	0x24000340
+
+0802c358 <Change_Road_Down_Up_Left_To_Right>:
+
+
+void Change_Road_Down_Up_Left_To_Right()
+{
+ 802c358:	b580      	push	{r7, lr}
+ 802c35a:	b084      	sub	sp, #16
+ 802c35c:	af00      	add	r7, sp, #0
+	static int Change_R_L_Count;
+	double Der_Angle_Down_Up[2]={-90,0};
+ 802c35e:	f04f 0200 	mov.w	r2, #0
+ 802c362:	4b43      	ldr	r3, [pc, #268]	@ (802c470 <Change_Road_Down_Up_Left_To_Right+0x118>)
+ 802c364:	e9c7 2300 	strd	r2, r3, [r7]
+ 802c368:	f04f 0200 	mov.w	r2, #0
+ 802c36c:	f04f 0300 	mov.w	r3, #0
+ 802c370:	e9c7 2302 	strd	r2, r3, [r7, #8]
+	switch(CRLU_Flag)
+ 802c374:	4b3f      	ldr	r3, [pc, #252]	@ (802c474 <Change_Road_Down_Up_Left_To_Right+0x11c>)
+ 802c376:	681b      	ldr	r3, [r3, #0]
+ 802c378:	2b04      	cmp	r3, #4
+ 802c37a:	d871      	bhi.n	802c460 <Change_Road_Down_Up_Left_To_Right+0x108>
+ 802c37c:	a201      	add	r2, pc, #4	@ (adr r2, 802c384 <Change_Road_Down_Up_Left_To_Right+0x2c>)
+ 802c37e:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 802c382:	bf00      	nop
+ 802c384:	0802c399 	.word	0x0802c399
+ 802c388:	0802c3d1 	.word	0x0802c3d1
+ 802c38c:	0802c3e1 	.word	0x0802c3e1
+ 802c390:	0802c41f 	.word	0x0802c41f
+ 802c394:	0802c451 	.word	0x0802c451
+	{
+	case 0://两轮速度相同转向
+		CV_Robot_Deri_Angle_Deg_Grity=Der_Angle_Down_Up[0];
+ 802c398:	e9d7 2300 	ldrd	r2, r3, [r7]
+ 802c39c:	4936      	ldr	r1, [pc, #216]	@ (802c478 <Change_Road_Down_Up_Left_To_Right+0x120>)
+ 802c39e:	e9c1 2300 	strd	r2, r3, [r1]
+		Robot_Posture_Adjus_Gravity();
+ 802c3a2:	f7ff fd45 	bl	802be30 <Robot_Posture_Adjus_Gravity>
+		if(Angle_Error_LLL<Error_Cont_Thresh)
+ 802c3a6:	4b35      	ldr	r3, [pc, #212]	@ (802c47c <Change_Road_Down_Up_Left_To_Right+0x124>)
+ 802c3a8:	ed93 6b00 	vldr	d6, [r3]
+ 802c3ac:	4b34      	ldr	r3, [pc, #208]	@ (802c480 <Change_Road_Down_Up_Left_To_Right+0x128>)
+ 802c3ae:	ed93 7b00 	vldr	d7, [r3]
+ 802c3b2:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802c3b6:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802c3ba:	d400      	bmi.n	802c3be <Change_Road_Down_Up_Left_To_Right+0x66>
+		{
+			CRLU_Flag++;
+			Change_R_L_Count=0;
+		}
+		break;
+ 802c3bc:	e053      	b.n	802c466 <Change_Road_Down_Up_Left_To_Right+0x10e>
+			CRLU_Flag++;
+ 802c3be:	4b2d      	ldr	r3, [pc, #180]	@ (802c474 <Change_Road_Down_Up_Left_To_Right+0x11c>)
+ 802c3c0:	681b      	ldr	r3, [r3, #0]
+ 802c3c2:	3301      	adds	r3, #1
+ 802c3c4:	4a2b      	ldr	r2, [pc, #172]	@ (802c474 <Change_Road_Down_Up_Left_To_Right+0x11c>)
+ 802c3c6:	6013      	str	r3, [r2, #0]
+			Change_R_L_Count=0;
+ 802c3c8:	4b2e      	ldr	r3, [pc, #184]	@ (802c484 <Change_Road_Down_Up_Left_To_Right+0x12c>)
+ 802c3ca:	2200      	movs	r2, #0
+ 802c3cc:	601a      	str	r2, [r3, #0]
+		break;
+ 802c3ce:	e04a      	b.n	802c466 <Change_Road_Down_Up_Left_To_Right+0x10e>
+	case 1://计算换道后退时间，设定后退速度
+		Vertical_Change_Road_Back_Time_Compute();
+ 802c3d0:	f001 f8ce 	bl	802d570 <Vertical_Change_Road_Back_Time_Compute>
+		CRLU_Flag++;
+ 802c3d4:	4b27      	ldr	r3, [pc, #156]	@ (802c474 <Change_Road_Down_Up_Left_To_Right+0x11c>)
+ 802c3d6:	681b      	ldr	r3, [r3, #0]
+ 802c3d8:	3301      	adds	r3, #1
+ 802c3da:	4a26      	ldr	r2, [pc, #152]	@ (802c474 <Change_Road_Down_Up_Left_To_Right+0x11c>)
+ 802c3dc:	6013      	str	r3, [r2, #0]
+		break;
+ 802c3de:	e042      	b.n	802c466 <Change_Road_Down_Up_Left_To_Right+0x10e>
+	case 2://PID转向期望角度1
+		Change_R_L_Count++;
+ 802c3e0:	4b28      	ldr	r3, [pc, #160]	@ (802c484 <Change_Road_Down_Up_Left_To_Right+0x12c>)
+ 802c3e2:	681b      	ldr	r3, [r3, #0]
+ 802c3e4:	3301      	adds	r3, #1
+ 802c3e6:	4a27      	ldr	r2, [pc, #156]	@ (802c484 <Change_Road_Down_Up_Left_To_Right+0x12c>)
+ 802c3e8:	6013      	str	r3, [r2, #0]
+		Move_Horizontal_Task_Change_Road_Backwards_Do();
+ 802c3ea:	f7ff fc9d 	bl	802bd28 <Move_Horizontal_Task_Change_Road_Backwards_Do>
+		if(Change_R_L_Count>Vertical_Change_Road_Time)
+ 802c3ee:	4b25      	ldr	r3, [pc, #148]	@ (802c484 <Change_Road_Down_Up_Left_To_Right+0x12c>)
+ 802c3f0:	681b      	ldr	r3, [r3, #0]
+ 802c3f2:	ee07 3a90 	vmov	s15, r3
+ 802c3f6:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802c3fa:	4b23      	ldr	r3, [pc, #140]	@ (802c488 <Change_Road_Down_Up_Left_To_Right+0x130>)
+ 802c3fc:	ed93 7b00 	vldr	d7, [r3]
+ 802c400:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802c404:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802c408:	dc00      	bgt.n	802c40c <Change_Road_Down_Up_Left_To_Right+0xb4>
+		{
+			CRLU_Flag++;
+			Change_R_L_Count=0;
+		}
+		break;
+ 802c40a:	e02c      	b.n	802c466 <Change_Road_Down_Up_Left_To_Right+0x10e>
+			CRLU_Flag++;
+ 802c40c:	4b19      	ldr	r3, [pc, #100]	@ (802c474 <Change_Road_Down_Up_Left_To_Right+0x11c>)
+ 802c40e:	681b      	ldr	r3, [r3, #0]
+ 802c410:	3301      	adds	r3, #1
+ 802c412:	4a18      	ldr	r2, [pc, #96]	@ (802c474 <Change_Road_Down_Up_Left_To_Right+0x11c>)
+ 802c414:	6013      	str	r3, [r2, #0]
+			Change_R_L_Count=0;
+ 802c416:	4b1b      	ldr	r3, [pc, #108]	@ (802c484 <Change_Road_Down_Up_Left_To_Right+0x12c>)
+ 802c418:	2200      	movs	r2, #0
+ 802c41a:	601a      	str	r2, [r3, #0]
+		break;
+ 802c41c:	e023      	b.n	802c466 <Change_Road_Down_Up_Left_To_Right+0x10e>
+	case 3://后退指定距离
+		CV_Robot_Deri_Angle_Deg_Grity=Der_Angle_Down_Up[1];
+ 802c41e:	e9d7 2302 	ldrd	r2, r3, [r7, #8]
+ 802c422:	4915      	ldr	r1, [pc, #84]	@ (802c478 <Change_Road_Down_Up_Left_To_Right+0x120>)
+ 802c424:	e9c1 2300 	strd	r2, r3, [r1]
+		Robot_Posture_Adjus_Gravity();
+ 802c428:	f7ff fd02 	bl	802be30 <Robot_Posture_Adjus_Gravity>
+		if(Angle_Error_LLL<Error_Cont_Thresh)
+ 802c42c:	4b13      	ldr	r3, [pc, #76]	@ (802c47c <Change_Road_Down_Up_Left_To_Right+0x124>)
+ 802c42e:	ed93 6b00 	vldr	d6, [r3]
+ 802c432:	4b13      	ldr	r3, [pc, #76]	@ (802c480 <Change_Road_Down_Up_Left_To_Right+0x128>)
+ 802c434:	ed93 7b00 	vldr	d7, [r3]
+ 802c438:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802c43c:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802c440:	d400      	bmi.n	802c444 <Change_Road_Down_Up_Left_To_Right+0xec>
+		{
+			CRLU_Flag++;
+		}
+		break;
+ 802c442:	e010      	b.n	802c466 <Change_Road_Down_Up_Left_To_Right+0x10e>
+			CRLU_Flag++;
+ 802c444:	4b0b      	ldr	r3, [pc, #44]	@ (802c474 <Change_Road_Down_Up_Left_To_Right+0x11c>)
+ 802c446:	681b      	ldr	r3, [r3, #0]
+ 802c448:	3301      	adds	r3, #1
+ 802c44a:	4a0a      	ldr	r2, [pc, #40]	@ (802c474 <Change_Road_Down_Up_Left_To_Right+0x11c>)
+ 802c44c:	6013      	str	r3, [r2, #0]
+		break;
+ 802c44e:	e00a      	b.n	802c466 <Change_Road_Down_Up_Left_To_Right+0x10e>
+	case 4://到达位置
+		GV.LeftMotor.Target_Velcity=0;
+ 802c450:	4b0e      	ldr	r3, [pc, #56]	@ (802c48c <Change_Road_Down_Up_Left_To_Right+0x134>)
+ 802c452:	2200      	movs	r2, #0
+ 802c454:	679a      	str	r2, [r3, #120]	@ 0x78
+		GV.RightMotor.Target_Velcity=0;
+ 802c456:	4b0d      	ldr	r3, [pc, #52]	@ (802c48c <Change_Road_Down_Up_Left_To_Right+0x134>)
+ 802c458:	2200      	movs	r2, #0
+ 802c45a:	f8c3 20f8 	str.w	r2, [r3, #248]	@ 0xf8
+		break;
+ 802c45e:	e002      	b.n	802c466 <Change_Road_Down_Up_Left_To_Right+0x10e>
+	default:
+		HALT_State_Do();
+ 802c460:	f003 fe82 	bl	8030168 <HALT_State_Do>
+		break;
+ 802c464:	bf00      	nop
+	}
+//	  UltraStopReverse(CRLU_Flag);
+}
+ 802c466:	bf00      	nop
+ 802c468:	3710      	adds	r7, #16
+ 802c46a:	46bd      	mov	sp, r7
+ 802c46c:	bd80      	pop	{r7, pc}
+ 802c46e:	bf00      	nop
+ 802c470:	c0568000 	.word	0xc0568000
+ 802c474:	2400a9f0 	.word	0x2400a9f0
+ 802c478:	2400a6d0 	.word	0x2400a6d0
+ 802c47c:	2400a9e8 	.word	0x2400a9e8
+ 802c480:	24000090 	.word	0x24000090
+ 802c484:	2400a8b0 	.word	0x2400a8b0
+ 802c488:	240000b8 	.word	0x240000b8
+ 802c48c:	24000340 	.word	0x24000340
+
+0802c490 <Change_Road_Plane_Continuous_FanDi_Left>:
+	}
+//	  UltraStopReverse(CRLU_Flag);
+}
+
+void Change_Road_Plane_Continuous_FanDi_Left()
+{
+ 802c490:	b580      	push	{r7, lr}
+ 802c492:	af00      	add	r7, sp, #0
+	static int Change_R_L_Count;
+	switch(CRLU_Flag)
+ 802c494:	4b84      	ldr	r3, [pc, #528]	@ (802c6a8 <Change_Road_Plane_Continuous_FanDi_Left+0x218>)
+ 802c496:	681b      	ldr	r3, [r3, #0]
+ 802c498:	2b04      	cmp	r3, #4
+ 802c49a:	f200 80ed 	bhi.w	802c678 <Change_Road_Plane_Continuous_FanDi_Left+0x1e8>
+ 802c49e:	a201      	add	r2, pc, #4	@ (adr r2, 802c4a4 <Change_Road_Plane_Continuous_FanDi_Left+0x14>)
+ 802c4a0:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 802c4a4:	0802c4b9 	.word	0x0802c4b9
+ 802c4a8:	0802c597 	.word	0x0802c597
+ 802c4ac:	0802c5d5 	.word	0x0802c5d5
+ 802c4b0:	0802c627 	.word	0x0802c627
+ 802c4b4:	0802c661 	.word	0x0802c661
+	{
+	case Expected_Angle_Confir://两轮速度相同转向
+		Swing_Limit_Flag=0;
+ 802c4b8:	4b7c      	ldr	r3, [pc, #496]	@ (802c6ac <Change_Road_Plane_Continuous_FanDi_Left+0x21c>)
+ 802c4ba:	2200      	movs	r2, #0
+ 802c4bc:	601a      	str	r2, [r3, #0]
+		Der_Angle_Plane[0]=MF40G_Angle_Add_Deg-90;
+ 802c4be:	4b7c      	ldr	r3, [pc, #496]	@ (802c6b0 <Change_Road_Plane_Continuous_FanDi_Left+0x220>)
+ 802c4c0:	ed93 7b00 	vldr	d7, [r3]
+ 802c4c4:	ed9f 6b70 	vldr	d6, [pc, #448]	@ 802c688 <Change_Road_Plane_Continuous_FanDi_Left+0x1f8>
+ 802c4c8:	ee37 7b46 	vsub.f64	d7, d7, d6
+ 802c4cc:	4b79      	ldr	r3, [pc, #484]	@ (802c6b4 <Change_Road_Plane_Continuous_FanDi_Left+0x224>)
+ 802c4ce:	ed83 7b00 	vstr	d7, [r3]
+		if(Der_Angle_Plane[0]>180)
+ 802c4d2:	4b78      	ldr	r3, [pc, #480]	@ (802c6b4 <Change_Road_Plane_Continuous_FanDi_Left+0x224>)
+ 802c4d4:	ed93 7b00 	vldr	d7, [r3]
+ 802c4d8:	ed9f 6b6d 	vldr	d6, [pc, #436]	@ 802c690 <Change_Road_Plane_Continuous_FanDi_Left+0x200>
+ 802c4dc:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 802c4e0:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802c4e4:	dd0a      	ble.n	802c4fc <Change_Road_Plane_Continuous_FanDi_Left+0x6c>
+		{
+			Der_Angle_Plane[0]=Der_Angle_Plane[0]-360;
+ 802c4e6:	4b73      	ldr	r3, [pc, #460]	@ (802c6b4 <Change_Road_Plane_Continuous_FanDi_Left+0x224>)
+ 802c4e8:	ed93 7b00 	vldr	d7, [r3]
+ 802c4ec:	ed9f 6b6a 	vldr	d6, [pc, #424]	@ 802c698 <Change_Road_Plane_Continuous_FanDi_Left+0x208>
+ 802c4f0:	ee37 7b46 	vsub.f64	d7, d7, d6
+ 802c4f4:	4b6f      	ldr	r3, [pc, #444]	@ (802c6b4 <Change_Road_Plane_Continuous_FanDi_Left+0x224>)
+ 802c4f6:	ed83 7b00 	vstr	d7, [r3]
+ 802c4fa:	e013      	b.n	802c524 <Change_Road_Plane_Continuous_FanDi_Left+0x94>
+		}
+		else if(Der_Angle_Plane[0]<-180)
+ 802c4fc:	4b6d      	ldr	r3, [pc, #436]	@ (802c6b4 <Change_Road_Plane_Continuous_FanDi_Left+0x224>)
+ 802c4fe:	ed93 7b00 	vldr	d7, [r3]
+ 802c502:	ed9f 6b67 	vldr	d6, [pc, #412]	@ 802c6a0 <Change_Road_Plane_Continuous_FanDi_Left+0x210>
+ 802c506:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 802c50a:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802c50e:	d509      	bpl.n	802c524 <Change_Road_Plane_Continuous_FanDi_Left+0x94>
+		{
+			Der_Angle_Plane[0]=Der_Angle_Plane[0]+360;
+ 802c510:	4b68      	ldr	r3, [pc, #416]	@ (802c6b4 <Change_Road_Plane_Continuous_FanDi_Left+0x224>)
+ 802c512:	ed93 7b00 	vldr	d7, [r3]
+ 802c516:	ed9f 6b60 	vldr	d6, [pc, #384]	@ 802c698 <Change_Road_Plane_Continuous_FanDi_Left+0x208>
+ 802c51a:	ee37 7b06 	vadd.f64	d7, d7, d6
+ 802c51e:	4b65      	ldr	r3, [pc, #404]	@ (802c6b4 <Change_Road_Plane_Continuous_FanDi_Left+0x224>)
+ 802c520:	ed83 7b00 	vstr	d7, [r3]
+		}
+
+		Der_Angle_Plane[1]=MF40G_Angle_Add_Deg-180;
+ 802c524:	4b62      	ldr	r3, [pc, #392]	@ (802c6b0 <Change_Road_Plane_Continuous_FanDi_Left+0x220>)
+ 802c526:	ed93 7b00 	vldr	d7, [r3]
+ 802c52a:	ed9f 6b59 	vldr	d6, [pc, #356]	@ 802c690 <Change_Road_Plane_Continuous_FanDi_Left+0x200>
+ 802c52e:	ee37 7b46 	vsub.f64	d7, d7, d6
+ 802c532:	4b60      	ldr	r3, [pc, #384]	@ (802c6b4 <Change_Road_Plane_Continuous_FanDi_Left+0x224>)
+ 802c534:	ed83 7b02 	vstr	d7, [r3, #8]
+		if(Der_Angle_Plane[1]>180)
+ 802c538:	4b5e      	ldr	r3, [pc, #376]	@ (802c6b4 <Change_Road_Plane_Continuous_FanDi_Left+0x224>)
+ 802c53a:	ed93 7b02 	vldr	d7, [r3, #8]
+ 802c53e:	ed9f 6b54 	vldr	d6, [pc, #336]	@ 802c690 <Change_Road_Plane_Continuous_FanDi_Left+0x200>
+ 802c542:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 802c546:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802c54a:	dd0a      	ble.n	802c562 <Change_Road_Plane_Continuous_FanDi_Left+0xd2>
+		{
+			Der_Angle_Plane[1]=Der_Angle_Plane[1]-360;
+ 802c54c:	4b59      	ldr	r3, [pc, #356]	@ (802c6b4 <Change_Road_Plane_Continuous_FanDi_Left+0x224>)
+ 802c54e:	ed93 7b02 	vldr	d7, [r3, #8]
+ 802c552:	ed9f 6b51 	vldr	d6, [pc, #324]	@ 802c698 <Change_Road_Plane_Continuous_FanDi_Left+0x208>
+ 802c556:	ee37 7b46 	vsub.f64	d7, d7, d6
+ 802c55a:	4b56      	ldr	r3, [pc, #344]	@ (802c6b4 <Change_Road_Plane_Continuous_FanDi_Left+0x224>)
+ 802c55c:	ed83 7b02 	vstr	d7, [r3, #8]
+ 802c560:	e013      	b.n	802c58a <Change_Road_Plane_Continuous_FanDi_Left+0xfa>
+		}
+		else if(Der_Angle_Plane[1]<-180)
+ 802c562:	4b54      	ldr	r3, [pc, #336]	@ (802c6b4 <Change_Road_Plane_Continuous_FanDi_Left+0x224>)
+ 802c564:	ed93 7b02 	vldr	d7, [r3, #8]
+ 802c568:	ed9f 6b4d 	vldr	d6, [pc, #308]	@ 802c6a0 <Change_Road_Plane_Continuous_FanDi_Left+0x210>
+ 802c56c:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 802c570:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802c574:	d509      	bpl.n	802c58a <Change_Road_Plane_Continuous_FanDi_Left+0xfa>
+		{
+			Der_Angle_Plane[1]=Der_Angle_Plane[1]+360;
+ 802c576:	4b4f      	ldr	r3, [pc, #316]	@ (802c6b4 <Change_Road_Plane_Continuous_FanDi_Left+0x224>)
+ 802c578:	ed93 7b02 	vldr	d7, [r3, #8]
+ 802c57c:	ed9f 6b46 	vldr	d6, [pc, #280]	@ 802c698 <Change_Road_Plane_Continuous_FanDi_Left+0x208>
+ 802c580:	ee37 7b06 	vadd.f64	d7, d7, d6
+ 802c584:	4b4b      	ldr	r3, [pc, #300]	@ (802c6b4 <Change_Road_Plane_Continuous_FanDi_Left+0x224>)
+ 802c586:	ed83 7b02 	vstr	d7, [r3, #8]
+		}
+
+
+		CRLU_Flag++;
+ 802c58a:	4b47      	ldr	r3, [pc, #284]	@ (802c6a8 <Change_Road_Plane_Continuous_FanDi_Left+0x218>)
+ 802c58c:	681b      	ldr	r3, [r3, #0]
+ 802c58e:	3301      	adds	r3, #1
+ 802c590:	4a45      	ldr	r2, [pc, #276]	@ (802c6a8 <Change_Road_Plane_Continuous_FanDi_Left+0x218>)
+ 802c592:	6013      	str	r3, [r2, #0]
+		break;
+ 802c594:	e073      	b.n	802c67e <Change_Road_Plane_Continuous_FanDi_Left+0x1ee>
+	case Turn_To_Y_C://转向到期望角度
+		CV_Robot_Deri_Angle_Deg_Plane=Der_Angle_Plane[0];
+ 802c596:	4b47      	ldr	r3, [pc, #284]	@ (802c6b4 <Change_Road_Plane_Continuous_FanDi_Left+0x224>)
+ 802c598:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802c59c:	4946      	ldr	r1, [pc, #280]	@ (802c6b8 <Change_Road_Plane_Continuous_FanDi_Left+0x228>)
+ 802c59e:	e9c1 2300 	strd	r2, r3, [r1]
+		Robot_Posture_Adjus_Plane();
+ 802c5a2:	f7ff fd15 	bl	802bfd0 <Robot_Posture_Adjus_Plane>
+		if(Angle_Error_LLL<Error_Cont_Thresh)
+ 802c5a6:	4b45      	ldr	r3, [pc, #276]	@ (802c6bc <Change_Road_Plane_Continuous_FanDi_Left+0x22c>)
+ 802c5a8:	ed93 6b00 	vldr	d6, [r3]
+ 802c5ac:	4b44      	ldr	r3, [pc, #272]	@ (802c6c0 <Change_Road_Plane_Continuous_FanDi_Left+0x230>)
+ 802c5ae:	ed93 7b00 	vldr	d7, [r3]
+ 802c5b2:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802c5b6:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802c5ba:	d400      	bmi.n	802c5be <Change_Road_Plane_Continuous_FanDi_Left+0x12e>
+		{
+			Plane_Change_Road_Back_Time_Countinus();//后退时间计算
+			CRLU_Flag++;
+			Change_R_L_Count=0;
+		}
+		break;
+ 802c5bc:	e05f      	b.n	802c67e <Change_Road_Plane_Continuous_FanDi_Left+0x1ee>
+			Plane_Change_Road_Back_Time_Countinus();//后退时间计算
+ 802c5be:	f000 ff4f 	bl	802d460 <Plane_Change_Road_Back_Time_Countinus>
+			CRLU_Flag++;
+ 802c5c2:	4b39      	ldr	r3, [pc, #228]	@ (802c6a8 <Change_Road_Plane_Continuous_FanDi_Left+0x218>)
+ 802c5c4:	681b      	ldr	r3, [r3, #0]
+ 802c5c6:	3301      	adds	r3, #1
+ 802c5c8:	4a37      	ldr	r2, [pc, #220]	@ (802c6a8 <Change_Road_Plane_Continuous_FanDi_Left+0x218>)
+ 802c5ca:	6013      	str	r3, [r2, #0]
+			Change_R_L_Count=0;
+ 802c5cc:	4b3d      	ldr	r3, [pc, #244]	@ (802c6c4 <Change_Road_Plane_Continuous_FanDi_Left+0x234>)
+ 802c5ce:	2200      	movs	r2, #0
+ 802c5d0:	601a      	str	r2, [r3, #0]
+		break;
+ 802c5d2:	e054      	b.n	802c67e <Change_Road_Plane_Continuous_FanDi_Left+0x1ee>
+	case Back_Runing_Y://PID转向期望角度1
+		Change_R_L_Count++;
+ 802c5d4:	4b3b      	ldr	r3, [pc, #236]	@ (802c6c4 <Change_Road_Plane_Continuous_FanDi_Left+0x234>)
+ 802c5d6:	681b      	ldr	r3, [r3, #0]
+ 802c5d8:	3301      	adds	r3, #1
+ 802c5da:	4a3a      	ldr	r2, [pc, #232]	@ (802c6c4 <Change_Road_Plane_Continuous_FanDi_Left+0x234>)
+ 802c5dc:	6013      	str	r3, [r2, #0]
+		Move_Plane_Task_Backwards_Distance_Do_Update(Robot_Countinus_Speed, CV_Robot_Deri_Angle_Deg_Plane);
+ 802c5de:	4b3a      	ldr	r3, [pc, #232]	@ (802c6c8 <Change_Road_Plane_Continuous_FanDi_Left+0x238>)
+ 802c5e0:	ed93 7b00 	vldr	d7, [r3]
+ 802c5e4:	4b34      	ldr	r3, [pc, #208]	@ (802c6b8 <Change_Road_Plane_Continuous_FanDi_Left+0x228>)
+ 802c5e6:	ed93 6b00 	vldr	d6, [r3]
+ 802c5ea:	eeb0 1b46 	vmov.f64	d1, d6
+ 802c5ee:	eeb0 0b47 	vmov.f64	d0, d7
+ 802c5f2:	f000 fa31 	bl	802ca58 <Move_Plane_Task_Backwards_Distance_Do_Update>
+		if(Change_R_L_Count>Plane_Change_Road_Time)
+ 802c5f6:	4b33      	ldr	r3, [pc, #204]	@ (802c6c4 <Change_Road_Plane_Continuous_FanDi_Left+0x234>)
+ 802c5f8:	681b      	ldr	r3, [r3, #0]
+ 802c5fa:	ee07 3a90 	vmov	s15, r3
+ 802c5fe:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802c602:	4b32      	ldr	r3, [pc, #200]	@ (802c6cc <Change_Road_Plane_Continuous_FanDi_Left+0x23c>)
+ 802c604:	ed93 7b00 	vldr	d7, [r3]
+ 802c608:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802c60c:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802c610:	dc00      	bgt.n	802c614 <Change_Road_Plane_Continuous_FanDi_Left+0x184>
+		{
+			CRLU_Flag++;
+			Change_R_L_Count=0;
+		}
+		break;
+ 802c612:	e034      	b.n	802c67e <Change_Road_Plane_Continuous_FanDi_Left+0x1ee>
+			CRLU_Flag++;
+ 802c614:	4b24      	ldr	r3, [pc, #144]	@ (802c6a8 <Change_Road_Plane_Continuous_FanDi_Left+0x218>)
+ 802c616:	681b      	ldr	r3, [r3, #0]
+ 802c618:	3301      	adds	r3, #1
+ 802c61a:	4a23      	ldr	r2, [pc, #140]	@ (802c6a8 <Change_Road_Plane_Continuous_FanDi_Left+0x218>)
+ 802c61c:	6013      	str	r3, [r2, #0]
+			Change_R_L_Count=0;
+ 802c61e:	4b29      	ldr	r3, [pc, #164]	@ (802c6c4 <Change_Road_Plane_Continuous_FanDi_Left+0x234>)
+ 802c620:	2200      	movs	r2, #0
+ 802c622:	601a      	str	r2, [r3, #0]
+		break;
+ 802c624:	e02b      	b.n	802c67e <Change_Road_Plane_Continuous_FanDi_Left+0x1ee>
+	case Turn_To_X://后退指定距离
+		CV_Robot_Deri_Angle_Deg_Plane=Der_Angle_Plane[1];
+ 802c626:	4b23      	ldr	r3, [pc, #140]	@ (802c6b4 <Change_Road_Plane_Continuous_FanDi_Left+0x224>)
+ 802c628:	e9d3 2302 	ldrd	r2, r3, [r3, #8]
+ 802c62c:	4922      	ldr	r1, [pc, #136]	@ (802c6b8 <Change_Road_Plane_Continuous_FanDi_Left+0x228>)
+ 802c62e:	e9c1 2300 	strd	r2, r3, [r1]
+		Robot_Posture_Adjus_Plane();
+ 802c632:	f7ff fccd 	bl	802bfd0 <Robot_Posture_Adjus_Plane>
+		if(Angle_Error_LLL<Error_Cont_Thresh)
+ 802c636:	4b21      	ldr	r3, [pc, #132]	@ (802c6bc <Change_Road_Plane_Continuous_FanDi_Left+0x22c>)
+ 802c638:	ed93 6b00 	vldr	d6, [r3]
+ 802c63c:	4b20      	ldr	r3, [pc, #128]	@ (802c6c0 <Change_Road_Plane_Continuous_FanDi_Left+0x230>)
+ 802c63e:	ed93 7b00 	vldr	d7, [r3]
+ 802c642:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802c646:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802c64a:	d400      	bmi.n	802c64e <Change_Road_Plane_Continuous_FanDi_Left+0x1be>
+		{
+			CRLU_Flag++;
+			Change_R_L_Count=0;
+		}
+		break;
+ 802c64c:	e017      	b.n	802c67e <Change_Road_Plane_Continuous_FanDi_Left+0x1ee>
+			CRLU_Flag++;
+ 802c64e:	4b16      	ldr	r3, [pc, #88]	@ (802c6a8 <Change_Road_Plane_Continuous_FanDi_Left+0x218>)
+ 802c650:	681b      	ldr	r3, [r3, #0]
+ 802c652:	3301      	adds	r3, #1
+ 802c654:	4a14      	ldr	r2, [pc, #80]	@ (802c6a8 <Change_Road_Plane_Continuous_FanDi_Left+0x218>)
+ 802c656:	6013      	str	r3, [r2, #0]
+			Change_R_L_Count=0;
+ 802c658:	4b1a      	ldr	r3, [pc, #104]	@ (802c6c4 <Change_Road_Plane_Continuous_FanDi_Left+0x234>)
+ 802c65a:	2200      	movs	r2, #0
+ 802c65c:	601a      	str	r2, [r3, #0]
+		break;
+ 802c65e:	e00e      	b.n	802c67e <Change_Road_Plane_Continuous_FanDi_Left+0x1ee>
+	case Change_Road_Completed://到达位置
+		GV.LeftMotor.Target_Velcity=0;
+ 802c660:	4b1b      	ldr	r3, [pc, #108]	@ (802c6d0 <Change_Road_Plane_Continuous_FanDi_Left+0x240>)
+ 802c662:	2200      	movs	r2, #0
+ 802c664:	679a      	str	r2, [r3, #120]	@ 0x78
+		GV.RightMotor.Target_Velcity=0;
+ 802c666:	4b1a      	ldr	r3, [pc, #104]	@ (802c6d0 <Change_Road_Plane_Continuous_FanDi_Left+0x240>)
+ 802c668:	2200      	movs	r2, #0
+ 802c66a:	f8c3 20f8 	str.w	r2, [r3, #248]	@ 0xf8
+		GV.SwingMotor.Target_Velcity=0;
+ 802c66e:	4b18      	ldr	r3, [pc, #96]	@ (802c6d0 <Change_Road_Plane_Continuous_FanDi_Left+0x240>)
+ 802c670:	2200      	movs	r2, #0
+ 802c672:	f8c3 2178 	str.w	r2, [r3, #376]	@ 0x178
+		break;
+ 802c676:	e002      	b.n	802c67e <Change_Road_Plane_Continuous_FanDi_Left+0x1ee>
+	default:
+		HALT_State_Do();
+ 802c678:	f003 fd76 	bl	8030168 <HALT_State_Do>
+		break;
+ 802c67c:	bf00      	nop
+	}
+//	  UltraStopReverse(CRLU_Flag);
+}
+ 802c67e:	bf00      	nop
+ 802c680:	bd80      	pop	{r7, pc}
+ 802c682:	bf00      	nop
+ 802c684:	f3af 8000 	nop.w
+ 802c688:	00000000 	.word	0x00000000
+ 802c68c:	40568000 	.word	0x40568000
+ 802c690:	00000000 	.word	0x00000000
+ 802c694:	40668000 	.word	0x40668000
+ 802c698:	00000000 	.word	0x00000000
+ 802c69c:	40768000 	.word	0x40768000
+ 802c6a0:	00000000 	.word	0x00000000
+ 802c6a4:	c0668000 	.word	0xc0668000
+ 802c6a8:	2400a9f0 	.word	0x2400a9f0
+ 802c6ac:	2400a6f4 	.word	0x2400a6f4
+ 802c6b0:	2400a788 	.word	0x2400a788
+ 802c6b4:	2400a7f8 	.word	0x2400a7f8
+ 802c6b8:	2400a6d8 	.word	0x2400a6d8
+ 802c6bc:	2400a9e8 	.word	0x2400a9e8
+ 802c6c0:	24000090 	.word	0x24000090
+ 802c6c4:	2400a8b4 	.word	0x2400a8b4
+ 802c6c8:	2400a760 	.word	0x2400a760
+ 802c6cc:	240000c8 	.word	0x240000c8
+ 802c6d0:	24000340 	.word	0x24000340
+ 802c6d4:	00000000 	.word	0x00000000
+
+0802c6d8 <Change_Road_Plane_Continuous_FanDi_Right>:
+
+
+void Change_Road_Plane_Continuous_FanDi_Right()
+{
+ 802c6d8:	b580      	push	{r7, lr}
+ 802c6da:	af00      	add	r7, sp, #0
+	static int Change_R_L_Count;
+	switch(CRLU_Flag)
+ 802c6dc:	4b84      	ldr	r3, [pc, #528]	@ (802c8f0 <Change_Road_Plane_Continuous_FanDi_Right+0x218>)
+ 802c6de:	681b      	ldr	r3, [r3, #0]
+ 802c6e0:	2b04      	cmp	r3, #4
+ 802c6e2:	f200 80ed 	bhi.w	802c8c0 <Change_Road_Plane_Continuous_FanDi_Right+0x1e8>
+ 802c6e6:	a201      	add	r2, pc, #4	@ (adr r2, 802c6ec <Change_Road_Plane_Continuous_FanDi_Right+0x14>)
+ 802c6e8:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 802c6ec:	0802c701 	.word	0x0802c701
+ 802c6f0:	0802c7df 	.word	0x0802c7df
+ 802c6f4:	0802c81d 	.word	0x0802c81d
+ 802c6f8:	0802c86f 	.word	0x0802c86f
+ 802c6fc:	0802c8a9 	.word	0x0802c8a9
+	{
+	case Expected_Angle_Confir://两轮速度相同转向
+		Swing_Limit_Flag=0;
+ 802c700:	4b7c      	ldr	r3, [pc, #496]	@ (802c8f4 <Change_Road_Plane_Continuous_FanDi_Right+0x21c>)
+ 802c702:	2200      	movs	r2, #0
+ 802c704:	601a      	str	r2, [r3, #0]
+		Der_Angle_Plane[0]=MF40G_Angle_Add_Deg+90;
+ 802c706:	4b7c      	ldr	r3, [pc, #496]	@ (802c8f8 <Change_Road_Plane_Continuous_FanDi_Right+0x220>)
+ 802c708:	ed93 7b00 	vldr	d7, [r3]
+ 802c70c:	ed9f 6b70 	vldr	d6, [pc, #448]	@ 802c8d0 <Change_Road_Plane_Continuous_FanDi_Right+0x1f8>
+ 802c710:	ee37 7b06 	vadd.f64	d7, d7, d6
+ 802c714:	4b79      	ldr	r3, [pc, #484]	@ (802c8fc <Change_Road_Plane_Continuous_FanDi_Right+0x224>)
+ 802c716:	ed83 7b00 	vstr	d7, [r3]
+		if(Der_Angle_Plane[0]>180)
+ 802c71a:	4b78      	ldr	r3, [pc, #480]	@ (802c8fc <Change_Road_Plane_Continuous_FanDi_Right+0x224>)
+ 802c71c:	ed93 7b00 	vldr	d7, [r3]
+ 802c720:	ed9f 6b6d 	vldr	d6, [pc, #436]	@ 802c8d8 <Change_Road_Plane_Continuous_FanDi_Right+0x200>
+ 802c724:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 802c728:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802c72c:	dd0a      	ble.n	802c744 <Change_Road_Plane_Continuous_FanDi_Right+0x6c>
+		{
+			Der_Angle_Plane[0]=Der_Angle_Plane[0]-360;
+ 802c72e:	4b73      	ldr	r3, [pc, #460]	@ (802c8fc <Change_Road_Plane_Continuous_FanDi_Right+0x224>)
+ 802c730:	ed93 7b00 	vldr	d7, [r3]
+ 802c734:	ed9f 6b6a 	vldr	d6, [pc, #424]	@ 802c8e0 <Change_Road_Plane_Continuous_FanDi_Right+0x208>
+ 802c738:	ee37 7b46 	vsub.f64	d7, d7, d6
+ 802c73c:	4b6f      	ldr	r3, [pc, #444]	@ (802c8fc <Change_Road_Plane_Continuous_FanDi_Right+0x224>)
+ 802c73e:	ed83 7b00 	vstr	d7, [r3]
+ 802c742:	e013      	b.n	802c76c <Change_Road_Plane_Continuous_FanDi_Right+0x94>
+		}
+		else if(Der_Angle_Plane[0]<-180)
+ 802c744:	4b6d      	ldr	r3, [pc, #436]	@ (802c8fc <Change_Road_Plane_Continuous_FanDi_Right+0x224>)
+ 802c746:	ed93 7b00 	vldr	d7, [r3]
+ 802c74a:	ed9f 6b67 	vldr	d6, [pc, #412]	@ 802c8e8 <Change_Road_Plane_Continuous_FanDi_Right+0x210>
+ 802c74e:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 802c752:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802c756:	d509      	bpl.n	802c76c <Change_Road_Plane_Continuous_FanDi_Right+0x94>
+		{
+			Der_Angle_Plane[0]=Der_Angle_Plane[0]+360;
+ 802c758:	4b68      	ldr	r3, [pc, #416]	@ (802c8fc <Change_Road_Plane_Continuous_FanDi_Right+0x224>)
+ 802c75a:	ed93 7b00 	vldr	d7, [r3]
+ 802c75e:	ed9f 6b60 	vldr	d6, [pc, #384]	@ 802c8e0 <Change_Road_Plane_Continuous_FanDi_Right+0x208>
+ 802c762:	ee37 7b06 	vadd.f64	d7, d7, d6
+ 802c766:	4b65      	ldr	r3, [pc, #404]	@ (802c8fc <Change_Road_Plane_Continuous_FanDi_Right+0x224>)
+ 802c768:	ed83 7b00 	vstr	d7, [r3]
+		}
+
+		Der_Angle_Plane[1]=MF40G_Angle_Add_Deg+180;
+ 802c76c:	4b62      	ldr	r3, [pc, #392]	@ (802c8f8 <Change_Road_Plane_Continuous_FanDi_Right+0x220>)
+ 802c76e:	ed93 7b00 	vldr	d7, [r3]
+ 802c772:	ed9f 6b59 	vldr	d6, [pc, #356]	@ 802c8d8 <Change_Road_Plane_Continuous_FanDi_Right+0x200>
+ 802c776:	ee37 7b06 	vadd.f64	d7, d7, d6
+ 802c77a:	4b60      	ldr	r3, [pc, #384]	@ (802c8fc <Change_Road_Plane_Continuous_FanDi_Right+0x224>)
+ 802c77c:	ed83 7b02 	vstr	d7, [r3, #8]
+		if(Der_Angle_Plane[1]>180)
+ 802c780:	4b5e      	ldr	r3, [pc, #376]	@ (802c8fc <Change_Road_Plane_Continuous_FanDi_Right+0x224>)
+ 802c782:	ed93 7b02 	vldr	d7, [r3, #8]
+ 802c786:	ed9f 6b54 	vldr	d6, [pc, #336]	@ 802c8d8 <Change_Road_Plane_Continuous_FanDi_Right+0x200>
+ 802c78a:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 802c78e:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802c792:	dd0a      	ble.n	802c7aa <Change_Road_Plane_Continuous_FanDi_Right+0xd2>
+		{
+			Der_Angle_Plane[1]=Der_Angle_Plane[1]-360;
+ 802c794:	4b59      	ldr	r3, [pc, #356]	@ (802c8fc <Change_Road_Plane_Continuous_FanDi_Right+0x224>)
+ 802c796:	ed93 7b02 	vldr	d7, [r3, #8]
+ 802c79a:	ed9f 6b51 	vldr	d6, [pc, #324]	@ 802c8e0 <Change_Road_Plane_Continuous_FanDi_Right+0x208>
+ 802c79e:	ee37 7b46 	vsub.f64	d7, d7, d6
+ 802c7a2:	4b56      	ldr	r3, [pc, #344]	@ (802c8fc <Change_Road_Plane_Continuous_FanDi_Right+0x224>)
+ 802c7a4:	ed83 7b02 	vstr	d7, [r3, #8]
+ 802c7a8:	e013      	b.n	802c7d2 <Change_Road_Plane_Continuous_FanDi_Right+0xfa>
+		}
+		else if(Der_Angle_Plane[1]<-180)
+ 802c7aa:	4b54      	ldr	r3, [pc, #336]	@ (802c8fc <Change_Road_Plane_Continuous_FanDi_Right+0x224>)
+ 802c7ac:	ed93 7b02 	vldr	d7, [r3, #8]
+ 802c7b0:	ed9f 6b4d 	vldr	d6, [pc, #308]	@ 802c8e8 <Change_Road_Plane_Continuous_FanDi_Right+0x210>
+ 802c7b4:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 802c7b8:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802c7bc:	d509      	bpl.n	802c7d2 <Change_Road_Plane_Continuous_FanDi_Right+0xfa>
+		{
+			Der_Angle_Plane[1]=Der_Angle_Plane[1]+360;
+ 802c7be:	4b4f      	ldr	r3, [pc, #316]	@ (802c8fc <Change_Road_Plane_Continuous_FanDi_Right+0x224>)
+ 802c7c0:	ed93 7b02 	vldr	d7, [r3, #8]
+ 802c7c4:	ed9f 6b46 	vldr	d6, [pc, #280]	@ 802c8e0 <Change_Road_Plane_Continuous_FanDi_Right+0x208>
+ 802c7c8:	ee37 7b06 	vadd.f64	d7, d7, d6
+ 802c7cc:	4b4b      	ldr	r3, [pc, #300]	@ (802c8fc <Change_Road_Plane_Continuous_FanDi_Right+0x224>)
+ 802c7ce:	ed83 7b02 	vstr	d7, [r3, #8]
+		}
+
+
+		CRLU_Flag++;
+ 802c7d2:	4b47      	ldr	r3, [pc, #284]	@ (802c8f0 <Change_Road_Plane_Continuous_FanDi_Right+0x218>)
+ 802c7d4:	681b      	ldr	r3, [r3, #0]
+ 802c7d6:	3301      	adds	r3, #1
+ 802c7d8:	4a45      	ldr	r2, [pc, #276]	@ (802c8f0 <Change_Road_Plane_Continuous_FanDi_Right+0x218>)
+ 802c7da:	6013      	str	r3, [r2, #0]
+		break;
+ 802c7dc:	e073      	b.n	802c8c6 <Change_Road_Plane_Continuous_FanDi_Right+0x1ee>
+	case Turn_To_Y_C://转向到期望角度
+		CV_Robot_Deri_Angle_Deg_Plane=Der_Angle_Plane[0];
+ 802c7de:	4b47      	ldr	r3, [pc, #284]	@ (802c8fc <Change_Road_Plane_Continuous_FanDi_Right+0x224>)
+ 802c7e0:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802c7e4:	4946      	ldr	r1, [pc, #280]	@ (802c900 <Change_Road_Plane_Continuous_FanDi_Right+0x228>)
+ 802c7e6:	e9c1 2300 	strd	r2, r3, [r1]
+		Robot_Posture_Adjus_Plane();
+ 802c7ea:	f7ff fbf1 	bl	802bfd0 <Robot_Posture_Adjus_Plane>
+		if(Angle_Error_LLL<Error_Cont_Thresh)
+ 802c7ee:	4b45      	ldr	r3, [pc, #276]	@ (802c904 <Change_Road_Plane_Continuous_FanDi_Right+0x22c>)
+ 802c7f0:	ed93 6b00 	vldr	d6, [r3]
+ 802c7f4:	4b44      	ldr	r3, [pc, #272]	@ (802c908 <Change_Road_Plane_Continuous_FanDi_Right+0x230>)
+ 802c7f6:	ed93 7b00 	vldr	d7, [r3]
+ 802c7fa:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802c7fe:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802c802:	d400      	bmi.n	802c806 <Change_Road_Plane_Continuous_FanDi_Right+0x12e>
+		{
+			Plane_Change_Road_Back_Time_Countinus();//后退时间计算
+			CRLU_Flag++;
+			Change_R_L_Count=0;
+		}
+		break;
+ 802c804:	e05f      	b.n	802c8c6 <Change_Road_Plane_Continuous_FanDi_Right+0x1ee>
+			Plane_Change_Road_Back_Time_Countinus();//后退时间计算
+ 802c806:	f000 fe2b 	bl	802d460 <Plane_Change_Road_Back_Time_Countinus>
+			CRLU_Flag++;
+ 802c80a:	4b39      	ldr	r3, [pc, #228]	@ (802c8f0 <Change_Road_Plane_Continuous_FanDi_Right+0x218>)
+ 802c80c:	681b      	ldr	r3, [r3, #0]
+ 802c80e:	3301      	adds	r3, #1
+ 802c810:	4a37      	ldr	r2, [pc, #220]	@ (802c8f0 <Change_Road_Plane_Continuous_FanDi_Right+0x218>)
+ 802c812:	6013      	str	r3, [r2, #0]
+			Change_R_L_Count=0;
+ 802c814:	4b3d      	ldr	r3, [pc, #244]	@ (802c90c <Change_Road_Plane_Continuous_FanDi_Right+0x234>)
+ 802c816:	2200      	movs	r2, #0
+ 802c818:	601a      	str	r2, [r3, #0]
+		break;
+ 802c81a:	e054      	b.n	802c8c6 <Change_Road_Plane_Continuous_FanDi_Right+0x1ee>
+	case Back_Runing_Y://PID转向期望角度1
+		Change_R_L_Count++;
+ 802c81c:	4b3b      	ldr	r3, [pc, #236]	@ (802c90c <Change_Road_Plane_Continuous_FanDi_Right+0x234>)
+ 802c81e:	681b      	ldr	r3, [r3, #0]
+ 802c820:	3301      	adds	r3, #1
+ 802c822:	4a3a      	ldr	r2, [pc, #232]	@ (802c90c <Change_Road_Plane_Continuous_FanDi_Right+0x234>)
+ 802c824:	6013      	str	r3, [r2, #0]
+		Move_Plane_Task_Backwards_Distance_Do_Update(Robot_Countinus_Speed, CV_Robot_Deri_Angle_Deg_Plane);
+ 802c826:	4b3a      	ldr	r3, [pc, #232]	@ (802c910 <Change_Road_Plane_Continuous_FanDi_Right+0x238>)
+ 802c828:	ed93 7b00 	vldr	d7, [r3]
+ 802c82c:	4b34      	ldr	r3, [pc, #208]	@ (802c900 <Change_Road_Plane_Continuous_FanDi_Right+0x228>)
+ 802c82e:	ed93 6b00 	vldr	d6, [r3]
+ 802c832:	eeb0 1b46 	vmov.f64	d1, d6
+ 802c836:	eeb0 0b47 	vmov.f64	d0, d7
+ 802c83a:	f000 f90d 	bl	802ca58 <Move_Plane_Task_Backwards_Distance_Do_Update>
+		if(Change_R_L_Count>Plane_Change_Road_Time)
+ 802c83e:	4b33      	ldr	r3, [pc, #204]	@ (802c90c <Change_Road_Plane_Continuous_FanDi_Right+0x234>)
+ 802c840:	681b      	ldr	r3, [r3, #0]
+ 802c842:	ee07 3a90 	vmov	s15, r3
+ 802c846:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802c84a:	4b32      	ldr	r3, [pc, #200]	@ (802c914 <Change_Road_Plane_Continuous_FanDi_Right+0x23c>)
+ 802c84c:	ed93 7b00 	vldr	d7, [r3]
+ 802c850:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802c854:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802c858:	dc00      	bgt.n	802c85c <Change_Road_Plane_Continuous_FanDi_Right+0x184>
+		{
+			CRLU_Flag++;
+			Change_R_L_Count=0;
+		}
+		break;
+ 802c85a:	e034      	b.n	802c8c6 <Change_Road_Plane_Continuous_FanDi_Right+0x1ee>
+			CRLU_Flag++;
+ 802c85c:	4b24      	ldr	r3, [pc, #144]	@ (802c8f0 <Change_Road_Plane_Continuous_FanDi_Right+0x218>)
+ 802c85e:	681b      	ldr	r3, [r3, #0]
+ 802c860:	3301      	adds	r3, #1
+ 802c862:	4a23      	ldr	r2, [pc, #140]	@ (802c8f0 <Change_Road_Plane_Continuous_FanDi_Right+0x218>)
+ 802c864:	6013      	str	r3, [r2, #0]
+			Change_R_L_Count=0;
+ 802c866:	4b29      	ldr	r3, [pc, #164]	@ (802c90c <Change_Road_Plane_Continuous_FanDi_Right+0x234>)
+ 802c868:	2200      	movs	r2, #0
+ 802c86a:	601a      	str	r2, [r3, #0]
+		break;
+ 802c86c:	e02b      	b.n	802c8c6 <Change_Road_Plane_Continuous_FanDi_Right+0x1ee>
+	case Turn_To_X://后退指定距离
+		CV_Robot_Deri_Angle_Deg_Plane=Der_Angle_Plane[1];
+ 802c86e:	4b23      	ldr	r3, [pc, #140]	@ (802c8fc <Change_Road_Plane_Continuous_FanDi_Right+0x224>)
+ 802c870:	e9d3 2302 	ldrd	r2, r3, [r3, #8]
+ 802c874:	4922      	ldr	r1, [pc, #136]	@ (802c900 <Change_Road_Plane_Continuous_FanDi_Right+0x228>)
+ 802c876:	e9c1 2300 	strd	r2, r3, [r1]
+		Robot_Posture_Adjus_Plane();
+ 802c87a:	f7ff fba9 	bl	802bfd0 <Robot_Posture_Adjus_Plane>
+		if(Angle_Error_LLL<Error_Cont_Thresh)
+ 802c87e:	4b21      	ldr	r3, [pc, #132]	@ (802c904 <Change_Road_Plane_Continuous_FanDi_Right+0x22c>)
+ 802c880:	ed93 6b00 	vldr	d6, [r3]
+ 802c884:	4b20      	ldr	r3, [pc, #128]	@ (802c908 <Change_Road_Plane_Continuous_FanDi_Right+0x230>)
+ 802c886:	ed93 7b00 	vldr	d7, [r3]
+ 802c88a:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802c88e:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802c892:	d400      	bmi.n	802c896 <Change_Road_Plane_Continuous_FanDi_Right+0x1be>
+		{
+			CRLU_Flag++;
+			Change_R_L_Count=0;
+		}
+		break;
+ 802c894:	e017      	b.n	802c8c6 <Change_Road_Plane_Continuous_FanDi_Right+0x1ee>
+			CRLU_Flag++;
+ 802c896:	4b16      	ldr	r3, [pc, #88]	@ (802c8f0 <Change_Road_Plane_Continuous_FanDi_Right+0x218>)
+ 802c898:	681b      	ldr	r3, [r3, #0]
+ 802c89a:	3301      	adds	r3, #1
+ 802c89c:	4a14      	ldr	r2, [pc, #80]	@ (802c8f0 <Change_Road_Plane_Continuous_FanDi_Right+0x218>)
+ 802c89e:	6013      	str	r3, [r2, #0]
+			Change_R_L_Count=0;
+ 802c8a0:	4b1a      	ldr	r3, [pc, #104]	@ (802c90c <Change_Road_Plane_Continuous_FanDi_Right+0x234>)
+ 802c8a2:	2200      	movs	r2, #0
+ 802c8a4:	601a      	str	r2, [r3, #0]
+		break;
+ 802c8a6:	e00e      	b.n	802c8c6 <Change_Road_Plane_Continuous_FanDi_Right+0x1ee>
+	case Change_Road_Completed://到达位置
+		GV.LeftMotor.Target_Velcity=0;
+ 802c8a8:	4b1b      	ldr	r3, [pc, #108]	@ (802c918 <Change_Road_Plane_Continuous_FanDi_Right+0x240>)
+ 802c8aa:	2200      	movs	r2, #0
+ 802c8ac:	679a      	str	r2, [r3, #120]	@ 0x78
+		GV.RightMotor.Target_Velcity=0;
+ 802c8ae:	4b1a      	ldr	r3, [pc, #104]	@ (802c918 <Change_Road_Plane_Continuous_FanDi_Right+0x240>)
+ 802c8b0:	2200      	movs	r2, #0
+ 802c8b2:	f8c3 20f8 	str.w	r2, [r3, #248]	@ 0xf8
+		GV.SwingMotor.Target_Velcity=0;
+ 802c8b6:	4b18      	ldr	r3, [pc, #96]	@ (802c918 <Change_Road_Plane_Continuous_FanDi_Right+0x240>)
+ 802c8b8:	2200      	movs	r2, #0
+ 802c8ba:	f8c3 2178 	str.w	r2, [r3, #376]	@ 0x178
+		break;
+ 802c8be:	e002      	b.n	802c8c6 <Change_Road_Plane_Continuous_FanDi_Right+0x1ee>
+	default:
+		HALT_State_Do();
+ 802c8c0:	f003 fc52 	bl	8030168 <HALT_State_Do>
+		break;
+ 802c8c4:	bf00      	nop
+	}
+//	  UltraStopReverse(CRLU_Flag);
+}
+ 802c8c6:	bf00      	nop
+ 802c8c8:	bd80      	pop	{r7, pc}
+ 802c8ca:	bf00      	nop
+ 802c8cc:	f3af 8000 	nop.w
+ 802c8d0:	00000000 	.word	0x00000000
+ 802c8d4:	40568000 	.word	0x40568000
+ 802c8d8:	00000000 	.word	0x00000000
+ 802c8dc:	40668000 	.word	0x40668000
+ 802c8e0:	00000000 	.word	0x00000000
+ 802c8e4:	40768000 	.word	0x40768000
+ 802c8e8:	00000000 	.word	0x00000000
+ 802c8ec:	c0668000 	.word	0xc0668000
+ 802c8f0:	2400a9f0 	.word	0x2400a9f0
+ 802c8f4:	2400a6f4 	.word	0x2400a6f4
+ 802c8f8:	2400a788 	.word	0x2400a788
+ 802c8fc:	2400a7f8 	.word	0x2400a7f8
+ 802c900:	2400a6d8 	.word	0x2400a6d8
+ 802c904:	2400a9e8 	.word	0x2400a9e8
+ 802c908:	24000090 	.word	0x24000090
+ 802c90c:	2400a8b8 	.word	0x2400a8b8
+ 802c910:	2400a760 	.word	0x2400a760
+ 802c914:	240000c8 	.word	0x240000c8
+ 802c918:	24000340 	.word	0x24000340
+
+0802c91c <Move_Plane_Task_Fordwards_Do_Update>:
+	GF_MSP_PID_Now_Der_adj_Com_Horizon(Robot_Plane, CV_Robot_Deri_Angle_Deg_Plane, GV.Robot_Move_Speed, Deri_Speed_Robot_MAX, System_time_SR , Robot_Speed);
+	GV.LeftMotor.Target_Velcity =Robot_Speed[1];
+	GV.RightMotor.Target_Velcity =-Robot_Speed[0];
+}
+void Move_Plane_Task_Fordwards_Do_Update(double robotMoveSpeed, double robotDeriAngleDegPlane)
+{
+ 802c91c:	b580      	push	{r7, lr}
+ 802c91e:	b090      	sub	sp, #64	@ 0x40
+ 802c920:	af00      	add	r7, sp, #0
+ 802c922:	ed87 0b02 	vstr	d0, [r7, #8]
+ 802c926:	ed87 1b00 	vstr	d1, [r7]
+	double Deri_Speed_Robot_MAX=robotMoveSpeed*1.5;
+ 802c92a:	ed97 7b02 	vldr	d7, [r7, #8]
+ 802c92e:	eeb7 6b08 	vmov.f64	d6, #120	@ 0x3fc00000  1.5
+ 802c932:	ee27 7b06 	vmul.f64	d7, d7, d6
+ 802c936:	ed87 7b0e 	vstr	d7, [r7, #56]	@ 0x38
+	double Robot_Speed[4]={0,0,0,0};
+ 802c93a:	f107 0310 	add.w	r3, r7, #16
+ 802c93e:	2220      	movs	r2, #32
+ 802c940:	2100      	movs	r1, #0
+ 802c942:	4618      	mov	r0, r3
+ 802c944:	f013 fcd0 	bl	80402e8 <memset>
+	double Robot_Plane_Angle=MF40G_Angle_Add_Deg;
+ 802c948:	4b16      	ldr	r3, [pc, #88]	@ (802c9a4 <Move_Plane_Task_Fordwards_Do_Update+0x88>)
+ 802c94a:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802c94e:	e9c7 230c 	strd	r2, r3, [r7, #48]	@ 0x30
+	GF_MSP_PID_Now_Der_adj_Com_Horizon(Robot_Plane_Angle, robotDeriAngleDegPlane, robotMoveSpeed, Deri_Speed_Robot_MAX, System_time_SR , Robot_Speed);
+ 802c952:	4b15      	ldr	r3, [pc, #84]	@ (802c9a8 <Move_Plane_Task_Fordwards_Do_Update+0x8c>)
+ 802c954:	ed93 7b00 	vldr	d7, [r3]
+ 802c958:	f107 0310 	add.w	r3, r7, #16
+ 802c95c:	4618      	mov	r0, r3
+ 802c95e:	eeb0 4b47 	vmov.f64	d4, d7
+ 802c962:	ed97 3b0e 	vldr	d3, [r7, #56]	@ 0x38
+ 802c966:	ed97 2b02 	vldr	d2, [r7, #8]
+ 802c96a:	ed97 1b00 	vldr	d1, [r7]
+ 802c96e:	ed97 0b0c 	vldr	d0, [r7, #48]	@ 0x30
+ 802c972:	f7fa ff83 	bl	802787c <GF_MSP_PID_Now_Der_adj_Com_Horizon>
+	GV.LeftMotor.Target_Velcity =Robot_Speed[0];
+ 802c976:	ed97 7b04 	vldr	d7, [r7, #16]
+ 802c97a:	eefd 7bc7 	vcvt.s32.f64	s15, d7
+ 802c97e:	ee17 2a90 	vmov	r2, s15
+ 802c982:	4b0a      	ldr	r3, [pc, #40]	@ (802c9ac <Move_Plane_Task_Fordwards_Do_Update+0x90>)
+ 802c984:	679a      	str	r2, [r3, #120]	@ 0x78
+	GV.RightMotor.Target_Velcity =-Robot_Speed[1];
+ 802c986:	ed97 7b06 	vldr	d7, [r7, #24]
+ 802c98a:	eeb1 7b47 	vneg.f64	d7, d7
+ 802c98e:	eefd 7bc7 	vcvt.s32.f64	s15, d7
+ 802c992:	ee17 2a90 	vmov	r2, s15
+ 802c996:	4b05      	ldr	r3, [pc, #20]	@ (802c9ac <Move_Plane_Task_Fordwards_Do_Update+0x90>)
+ 802c998:	f8c3 20f8 	str.w	r2, [r3, #248]	@ 0xf8
+}
+ 802c99c:	bf00      	nop
+ 802c99e:	3740      	adds	r7, #64	@ 0x40
+ 802c9a0:	46bd      	mov	sp, r7
+ 802c9a2:	bd80      	pop	{r7, pc}
+ 802c9a4:	2400a788 	.word	0x2400a788
+ 802c9a8:	240000b0 	.word	0x240000b0
+ 802c9ac:	24000340 	.word	0x24000340
+
+0802c9b0 <Move_Horizontal_Vertical_Task_Backwards_Do_Backward>:
+	GV.RightMotor.Target_Velcity =Robot_Speed[1];
+}
+
+
+void Move_Horizontal_Vertical_Task_Backwards_Do_Backward(double robotMoveSpeed, double robotDeriAngleDegGrity)
+{
+ 802c9b0:	b580      	push	{r7, lr}
+ 802c9b2:	b090      	sub	sp, #64	@ 0x40
+ 802c9b4:	af00      	add	r7, sp, #0
+ 802c9b6:	ed87 0b02 	vstr	d0, [r7, #8]
+ 802c9ba:	ed87 1b00 	vstr	d1, [r7]
+	double Deri_Speed_Robot_MAX = robotMoveSpeed * 1.5;
+ 802c9be:	ed97 7b02 	vldr	d7, [r7, #8]
+ 802c9c2:	eeb7 6b08 	vmov.f64	d6, #120	@ 0x3fc00000  1.5
+ 802c9c6:	ee27 7b06 	vmul.f64	d7, d7, d6
+ 802c9ca:	ed87 7b0e 	vstr	d7, [r7, #56]	@ 0x38
+	double Robot_Speed[4] = {0, 0, 0, 0};
+ 802c9ce:	f107 0310 	add.w	r3, r7, #16
+ 802c9d2:	2220      	movs	r2, #32
+ 802c9d4:	2100      	movs	r1, #0
+ 802c9d6:	4618      	mov	r0, r3
+ 802c9d8:	f013 fc86 	bl	80402e8 <memset>
+	double Robot_Grity = ((double)GV.TL720DParameters.RF_Angle_Roll) / 100;
+ 802c9dc:	4b1c      	ldr	r3, [pc, #112]	@ (802ca50 <Move_Horizontal_Vertical_Task_Backwards_Do_Backward+0xa0>)
+ 802c9de:	f8d3 3218 	ldr.w	r3, [r3, #536]	@ 0x218
+ 802c9e2:	ee07 3a90 	vmov	s15, r3
+ 802c9e6:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802c9ea:	ed9f 5b17 	vldr	d5, [pc, #92]	@ 802ca48 <Move_Horizontal_Vertical_Task_Backwards_Do_Backward+0x98>
+ 802c9ee:	ee86 7b05 	vdiv.f64	d7, d6, d5
+ 802c9f2:	ed87 7b0c 	vstr	d7, [r7, #48]	@ 0x30
+	GF_MSP_PID_Now_Der_adj_Com_Horizon(Robot_Grity, robotDeriAngleDegGrity, robotMoveSpeed, Deri_Speed_Robot_MAX, System_time_SR, Robot_Speed);
+ 802c9f6:	4b17      	ldr	r3, [pc, #92]	@ (802ca54 <Move_Horizontal_Vertical_Task_Backwards_Do_Backward+0xa4>)
+ 802c9f8:	ed93 7b00 	vldr	d7, [r3]
+ 802c9fc:	f107 0310 	add.w	r3, r7, #16
+ 802ca00:	4618      	mov	r0, r3
+ 802ca02:	eeb0 4b47 	vmov.f64	d4, d7
+ 802ca06:	ed97 3b0e 	vldr	d3, [r7, #56]	@ 0x38
+ 802ca0a:	ed97 2b02 	vldr	d2, [r7, #8]
+ 802ca0e:	ed97 1b00 	vldr	d1, [r7]
+ 802ca12:	ed97 0b0c 	vldr	d0, [r7, #48]	@ 0x30
+ 802ca16:	f7fa ff31 	bl	802787c <GF_MSP_PID_Now_Der_adj_Com_Horizon>
+
+	GV.LeftMotor.Target_Velcity = -Robot_Speed[1];
+ 802ca1a:	ed97 7b06 	vldr	d7, [r7, #24]
+ 802ca1e:	eeb1 7b47 	vneg.f64	d7, d7
+ 802ca22:	eefd 7bc7 	vcvt.s32.f64	s15, d7
+ 802ca26:	ee17 2a90 	vmov	r2, s15
+ 802ca2a:	4b09      	ldr	r3, [pc, #36]	@ (802ca50 <Move_Horizontal_Vertical_Task_Backwards_Do_Backward+0xa0>)
+ 802ca2c:	679a      	str	r2, [r3, #120]	@ 0x78
+	GV.RightMotor.Target_Velcity = Robot_Speed[0];
+ 802ca2e:	ed97 7b04 	vldr	d7, [r7, #16]
+ 802ca32:	eefd 7bc7 	vcvt.s32.f64	s15, d7
+ 802ca36:	ee17 2a90 	vmov	r2, s15
+ 802ca3a:	4b05      	ldr	r3, [pc, #20]	@ (802ca50 <Move_Horizontal_Vertical_Task_Backwards_Do_Backward+0xa0>)
+ 802ca3c:	f8c3 20f8 	str.w	r2, [r3, #248]	@ 0xf8
+}
+ 802ca40:	bf00      	nop
+ 802ca42:	3740      	adds	r7, #64	@ 0x40
+ 802ca44:	46bd      	mov	sp, r7
+ 802ca46:	bd80      	pop	{r7, pc}
+ 802ca48:	00000000 	.word	0x00000000
+ 802ca4c:	40590000 	.word	0x40590000
+ 802ca50:	24000340 	.word	0x24000340
+ 802ca54:	240000b0 	.word	0x240000b0
+
+0802ca58 <Move_Plane_Task_Backwards_Distance_Do_Update>:
+
+
+
+
+void Move_Plane_Task_Backwards_Distance_Do_Update(double robotMoveSpeed, double robotDeriAngleDegPlane)
+{
+ 802ca58:	b580      	push	{r7, lr}
+ 802ca5a:	b090      	sub	sp, #64	@ 0x40
+ 802ca5c:	af00      	add	r7, sp, #0
+ 802ca5e:	ed87 0b02 	vstr	d0, [r7, #8]
+ 802ca62:	ed87 1b00 	vstr	d1, [r7]
+	double Deri_Speed_Robot_MAX=robotMoveSpeed*1.5;
+ 802ca66:	ed97 7b02 	vldr	d7, [r7, #8]
+ 802ca6a:	eeb7 6b08 	vmov.f64	d6, #120	@ 0x3fc00000  1.5
+ 802ca6e:	ee27 7b06 	vmul.f64	d7, d7, d6
+ 802ca72:	ed87 7b0e 	vstr	d7, [r7, #56]	@ 0x38
+	double Robot_Speed[4]={0,0,0,0};
+ 802ca76:	f107 0310 	add.w	r3, r7, #16
+ 802ca7a:	2220      	movs	r2, #32
+ 802ca7c:	2100      	movs	r1, #0
+ 802ca7e:	4618      	mov	r0, r3
+ 802ca80:	f013 fc32 	bl	80402e8 <memset>
+	double Robot_Plane_Angle=MF40G_Angle_Add_Deg;
+ 802ca84:	4b16      	ldr	r3, [pc, #88]	@ (802cae0 <Move_Plane_Task_Backwards_Distance_Do_Update+0x88>)
+ 802ca86:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802ca8a:	e9c7 230c 	strd	r2, r3, [r7, #48]	@ 0x30
+	GF_MSP_PID_Now_Der_adj_Com_Horizon(Robot_Plane_Angle, robotDeriAngleDegPlane, robotMoveSpeed, Deri_Speed_Robot_MAX, System_time_SR , Robot_Speed);
+ 802ca8e:	4b15      	ldr	r3, [pc, #84]	@ (802cae4 <Move_Plane_Task_Backwards_Distance_Do_Update+0x8c>)
+ 802ca90:	ed93 7b00 	vldr	d7, [r3]
+ 802ca94:	f107 0310 	add.w	r3, r7, #16
+ 802ca98:	4618      	mov	r0, r3
+ 802ca9a:	eeb0 4b47 	vmov.f64	d4, d7
+ 802ca9e:	ed97 3b0e 	vldr	d3, [r7, #56]	@ 0x38
+ 802caa2:	ed97 2b02 	vldr	d2, [r7, #8]
+ 802caa6:	ed97 1b00 	vldr	d1, [r7]
+ 802caaa:	ed97 0b0c 	vldr	d0, [r7, #48]	@ 0x30
+ 802caae:	f7fa fee5 	bl	802787c <GF_MSP_PID_Now_Der_adj_Com_Horizon>
+	GV.LeftMotor.Target_Velcity =-Robot_Speed[1];
+ 802cab2:	ed97 7b06 	vldr	d7, [r7, #24]
+ 802cab6:	eeb1 7b47 	vneg.f64	d7, d7
+ 802caba:	eefd 7bc7 	vcvt.s32.f64	s15, d7
+ 802cabe:	ee17 2a90 	vmov	r2, s15
+ 802cac2:	4b09      	ldr	r3, [pc, #36]	@ (802cae8 <Move_Plane_Task_Backwards_Distance_Do_Update+0x90>)
+ 802cac4:	679a      	str	r2, [r3, #120]	@ 0x78
+	GV.RightMotor.Target_Velcity =Robot_Speed[0];
+ 802cac6:	ed97 7b04 	vldr	d7, [r7, #16]
+ 802caca:	eefd 7bc7 	vcvt.s32.f64	s15, d7
+ 802cace:	ee17 2a90 	vmov	r2, s15
+ 802cad2:	4b05      	ldr	r3, [pc, #20]	@ (802cae8 <Move_Plane_Task_Backwards_Distance_Do_Update+0x90>)
+ 802cad4:	f8c3 20f8 	str.w	r2, [r3, #248]	@ 0xf8
+}
+ 802cad8:	bf00      	nop
+ 802cada:	3740      	adds	r7, #64	@ 0x40
+ 802cadc:	46bd      	mov	sp, r7
+ 802cade:	bd80      	pop	{r7, pc}
+ 802cae0:	2400a788 	.word	0x2400a788
+ 802cae4:	240000b0 	.word	0x240000b0
+ 802cae8:	24000340 	.word	0x24000340
+
+0802caec <Move_Plane_Task_Backwards_Distance_Do_Update_Turn>:
+
+void Move_Plane_Task_Backwards_Distance_Do_Update_Turn(double robotMoveSpeed, double robotDeriAngleDegPlane)
+{
+ 802caec:	b580      	push	{r7, lr}
+ 802caee:	b090      	sub	sp, #64	@ 0x40
+ 802caf0:	af00      	add	r7, sp, #0
+ 802caf2:	ed87 0b02 	vstr	d0, [r7, #8]
+ 802caf6:	ed87 1b00 	vstr	d1, [r7]
+	double Deri_Speed_Robot_MAX=robotMoveSpeed*1.5;
+ 802cafa:	ed97 7b02 	vldr	d7, [r7, #8]
+ 802cafe:	eeb7 6b08 	vmov.f64	d6, #120	@ 0x3fc00000  1.5
+ 802cb02:	ee27 7b06 	vmul.f64	d7, d7, d6
+ 802cb06:	ed87 7b0e 	vstr	d7, [r7, #56]	@ 0x38
+	double Robot_Speed[4]={0,0,0,0};
+ 802cb0a:	f107 0310 	add.w	r3, r7, #16
+ 802cb0e:	2220      	movs	r2, #32
+ 802cb10:	2100      	movs	r1, #0
+ 802cb12:	4618      	mov	r0, r3
+ 802cb14:	f013 fbe8 	bl	80402e8 <memset>
+	double Robot_Plane_Angle=MF40G_Angle_Add_Deg;
+ 802cb18:	4b35      	ldr	r3, [pc, #212]	@ (802cbf0 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn+0x104>)
+ 802cb1a:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802cb1e:	e9c7 230c 	strd	r2, r3, [r7, #48]	@ 0x30
+
+	GF_MSP_PID_Now_Der_adj_Com_Horizon(Robot_Plane_Angle, robotDeriAngleDegPlane, robotMoveSpeed, Deri_Speed_Robot_MAX, System_time_SR , Robot_Speed);
+ 802cb22:	4b34      	ldr	r3, [pc, #208]	@ (802cbf4 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn+0x108>)
+ 802cb24:	ed93 7b00 	vldr	d7, [r3]
+ 802cb28:	f107 0310 	add.w	r3, r7, #16
+ 802cb2c:	4618      	mov	r0, r3
+ 802cb2e:	eeb0 4b47 	vmov.f64	d4, d7
+ 802cb32:	ed97 3b0e 	vldr	d3, [r7, #56]	@ 0x38
+ 802cb36:	ed97 2b02 	vldr	d2, [r7, #8]
+ 802cb3a:	ed97 1b00 	vldr	d1, [r7]
+ 802cb3e:	ed97 0b0c 	vldr	d0, [r7, #48]	@ 0x30
+ 802cb42:	f7fa fe9b 	bl	802787c <GF_MSP_PID_Now_Der_adj_Com_Horizon>
+	static int Turn_Count=0;
+	if(P_MK32->CH3_LY_H<-300)
+ 802cb46:	4b2c      	ldr	r3, [pc, #176]	@ (802cbf8 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn+0x10c>)
+ 802cb48:	681b      	ldr	r3, [r3, #0]
+ 802cb4a:	691b      	ldr	r3, [r3, #16]
+ 802cb4c:	f513 7f96 	cmn.w	r3, #300	@ 0x12c
+ 802cb50:	da16      	bge.n	802cb80 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn+0x94>
+	{
+		Turn_Count++;
+ 802cb52:	4b2a      	ldr	r3, [pc, #168]	@ (802cbfc <Move_Plane_Task_Backwards_Distance_Do_Update_Turn+0x110>)
+ 802cb54:	681b      	ldr	r3, [r3, #0]
+ 802cb56:	3301      	adds	r3, #1
+ 802cb58:	4a28      	ldr	r2, [pc, #160]	@ (802cbfc <Move_Plane_Task_Backwards_Distance_Do_Update_Turn+0x110>)
+ 802cb5a:	6013      	str	r3, [r2, #0]
+		if(Turn_Count>1000)
+ 802cb5c:	4b27      	ldr	r3, [pc, #156]	@ (802cbfc <Move_Plane_Task_Backwards_Distance_Do_Update_Turn+0x110>)
+ 802cb5e:	681b      	ldr	r3, [r3, #0]
+ 802cb60:	f5b3 7f7a 	cmp.w	r3, #1000	@ 0x3e8
+ 802cb64:	dd2c      	ble.n	802cbc0 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn+0xd4>
+		{
+			Robot_Speed[1]=Robot_Speed[1]+Robot_Speed[1]*1;
+ 802cb66:	ed97 7b06 	vldr	d7, [r7, #24]
+ 802cb6a:	ee37 7b07 	vadd.f64	d7, d7, d7
+ 802cb6e:	ed87 7b06 	vstr	d7, [r7, #24]
+			CV_Robot_Deri_Angle_Deg_Plane=MF40G_Angle_Add_Deg;
+ 802cb72:	4b1f      	ldr	r3, [pc, #124]	@ (802cbf0 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn+0x104>)
+ 802cb74:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802cb78:	4921      	ldr	r1, [pc, #132]	@ (802cc00 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn+0x114>)
+ 802cb7a:	e9c1 2300 	strd	r2, r3, [r1]
+ 802cb7e:	e01f      	b.n	802cbc0 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn+0xd4>
+		}
+	}
+	else if(P_MK32->CH3_LY_H>300)
+ 802cb80:	4b1d      	ldr	r3, [pc, #116]	@ (802cbf8 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn+0x10c>)
+ 802cb82:	681b      	ldr	r3, [r3, #0]
+ 802cb84:	691b      	ldr	r3, [r3, #16]
+ 802cb86:	f5b3 7f96 	cmp.w	r3, #300	@ 0x12c
+ 802cb8a:	dd16      	ble.n	802cbba <Move_Plane_Task_Backwards_Distance_Do_Update_Turn+0xce>
+	{
+		Turn_Count++;
+ 802cb8c:	4b1b      	ldr	r3, [pc, #108]	@ (802cbfc <Move_Plane_Task_Backwards_Distance_Do_Update_Turn+0x110>)
+ 802cb8e:	681b      	ldr	r3, [r3, #0]
+ 802cb90:	3301      	adds	r3, #1
+ 802cb92:	4a1a      	ldr	r2, [pc, #104]	@ (802cbfc <Move_Plane_Task_Backwards_Distance_Do_Update_Turn+0x110>)
+ 802cb94:	6013      	str	r3, [r2, #0]
+		if(Turn_Count>1000)
+ 802cb96:	4b19      	ldr	r3, [pc, #100]	@ (802cbfc <Move_Plane_Task_Backwards_Distance_Do_Update_Turn+0x110>)
+ 802cb98:	681b      	ldr	r3, [r3, #0]
+ 802cb9a:	f5b3 7f7a 	cmp.w	r3, #1000	@ 0x3e8
+ 802cb9e:	dd0f      	ble.n	802cbc0 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn+0xd4>
+		{
+			Robot_Speed[0]=Robot_Speed[0]+Robot_Speed[0]*1;
+ 802cba0:	ed97 7b04 	vldr	d7, [r7, #16]
+ 802cba4:	ee37 7b07 	vadd.f64	d7, d7, d7
+ 802cba8:	ed87 7b04 	vstr	d7, [r7, #16]
+			CV_Robot_Deri_Angle_Deg_Plane=MF40G_Angle_Add_Deg;
+ 802cbac:	4b10      	ldr	r3, [pc, #64]	@ (802cbf0 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn+0x104>)
+ 802cbae:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802cbb2:	4913      	ldr	r1, [pc, #76]	@ (802cc00 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn+0x114>)
+ 802cbb4:	e9c1 2300 	strd	r2, r3, [r1]
+ 802cbb8:	e002      	b.n	802cbc0 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn+0xd4>
+		}
+	}
+	else
+	{
+		Turn_Count=0;
+ 802cbba:	4b10      	ldr	r3, [pc, #64]	@ (802cbfc <Move_Plane_Task_Backwards_Distance_Do_Update_Turn+0x110>)
+ 802cbbc:	2200      	movs	r2, #0
+ 802cbbe:	601a      	str	r2, [r3, #0]
+	}
+	GV.LeftMotor.Target_Velcity =-Robot_Speed[1];
+ 802cbc0:	ed97 7b06 	vldr	d7, [r7, #24]
+ 802cbc4:	eeb1 7b47 	vneg.f64	d7, d7
+ 802cbc8:	eefd 7bc7 	vcvt.s32.f64	s15, d7
+ 802cbcc:	ee17 2a90 	vmov	r2, s15
+ 802cbd0:	4b0c      	ldr	r3, [pc, #48]	@ (802cc04 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn+0x118>)
+ 802cbd2:	679a      	str	r2, [r3, #120]	@ 0x78
+	GV.RightMotor.Target_Velcity =Robot_Speed[0];
+ 802cbd4:	ed97 7b04 	vldr	d7, [r7, #16]
+ 802cbd8:	eefd 7bc7 	vcvt.s32.f64	s15, d7
+ 802cbdc:	ee17 2a90 	vmov	r2, s15
+ 802cbe0:	4b08      	ldr	r3, [pc, #32]	@ (802cc04 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn+0x118>)
+ 802cbe2:	f8c3 20f8 	str.w	r2, [r3, #248]	@ 0xf8
+}
+ 802cbe6:	bf00      	nop
+ 802cbe8:	3740      	adds	r7, #64	@ 0x40
+ 802cbea:	46bd      	mov	sp, r7
+ 802cbec:	bd80      	pop	{r7, pc}
+ 802cbee:	bf00      	nop
+ 802cbf0:	2400a788 	.word	0x2400a788
+ 802cbf4:	240000b0 	.word	0x240000b0
+ 802cbf8:	2400a3f8 	.word	0x2400a3f8
+ 802cbfc:	2400a8bc 	.word	0x2400a8bc
+ 802cc00:	2400a6d8 	.word	0x2400a6d8
+ 802cc04:	24000340 	.word	0x24000340
+
+0802cc08 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin>:
+void Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin(double robotMoveSpeed, double robotDeriAngleDegPlane)
+{
+ 802cc08:	b580      	push	{r7, lr}
+ 802cc0a:	b090      	sub	sp, #64	@ 0x40
+ 802cc0c:	af00      	add	r7, sp, #0
+ 802cc0e:	ed87 0b02 	vstr	d0, [r7, #8]
+ 802cc12:	ed87 1b00 	vstr	d1, [r7]
+	double Deri_Speed_Robot_MAX=robotMoveSpeed*1.5;
+ 802cc16:	ed97 7b02 	vldr	d7, [r7, #8]
+ 802cc1a:	eeb7 6b08 	vmov.f64	d6, #120	@ 0x3fc00000  1.5
+ 802cc1e:	ee27 7b06 	vmul.f64	d7, d7, d6
+ 802cc22:	ed87 7b0e 	vstr	d7, [r7, #56]	@ 0x38
+	double Robot_Speed[4]={0,0,0,0};
+ 802cc26:	f107 0310 	add.w	r3, r7, #16
+ 802cc2a:	2220      	movs	r2, #32
+ 802cc2c:	2100      	movs	r1, #0
+ 802cc2e:	4618      	mov	r0, r3
+ 802cc30:	f013 fb5a 	bl	80402e8 <memset>
+	double Robot_Plane_Angle=MF40G_Angle_Add_Deg;
+ 802cc34:	4bb4      	ldr	r3, [pc, #720]	@ (802cf08 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x300>)
+ 802cc36:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802cc3a:	e9c7 230c 	strd	r2, r3, [r7, #48]	@ 0x30
+
+	GF_MSP_PID_Now_Der_adj_Com_Horizon(Robot_Plane_Angle, robotDeriAngleDegPlane, robotMoveSpeed, Deri_Speed_Robot_MAX, System_time_SR , Robot_Speed);
+ 802cc3e:	4bb3      	ldr	r3, [pc, #716]	@ (802cf0c <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x304>)
+ 802cc40:	ed93 7b00 	vldr	d7, [r3]
+ 802cc44:	f107 0310 	add.w	r3, r7, #16
+ 802cc48:	4618      	mov	r0, r3
+ 802cc4a:	eeb0 4b47 	vmov.f64	d4, d7
+ 802cc4e:	ed97 3b0e 	vldr	d3, [r7, #56]	@ 0x38
+ 802cc52:	ed97 2b02 	vldr	d2, [r7, #8]
+ 802cc56:	ed97 1b00 	vldr	d1, [r7]
+ 802cc5a:	ed97 0b0c 	vldr	d0, [r7, #48]	@ 0x30
+ 802cc5e:	f7fa fe0d 	bl	802787c <GF_MSP_PID_Now_Der_adj_Com_Horizon>
+	static int Turn_Count=0;
+	if(P_MK32->CH3_LY_H<-300)
+ 802cc62:	4bab      	ldr	r3, [pc, #684]	@ (802cf10 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x308>)
+ 802cc64:	681b      	ldr	r3, [r3, #0]
+ 802cc66:	691b      	ldr	r3, [r3, #16]
+ 802cc68:	f513 7f96 	cmn.w	r3, #300	@ 0x12c
+ 802cc6c:	f280 808e 	bge.w	802cd8c <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x184>
+	{
+		Turn_Count++;
+ 802cc70:	4ba8      	ldr	r3, [pc, #672]	@ (802cf14 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x30c>)
+ 802cc72:	681b      	ldr	r3, [r3, #0]
+ 802cc74:	3301      	adds	r3, #1
+ 802cc76:	4aa7      	ldr	r2, [pc, #668]	@ (802cf14 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x30c>)
+ 802cc78:	6013      	str	r3, [r2, #0]
+		if(Turn_Count>1000)
+ 802cc7a:	4ba6      	ldr	r3, [pc, #664]	@ (802cf14 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x30c>)
+ 802cc7c:	681b      	ldr	r3, [r3, #0]
+ 802cc7e:	f5b3 7f7a 	cmp.w	r3, #1000	@ 0x3e8
+ 802cc82:	f340 8119 	ble.w	802ceb8 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x2b0>
+		{
+			Robot_Speed[1]=Robot_Speed[1]+Robot_Speed[1]*1;
+ 802cc86:	ed97 7b06 	vldr	d7, [r7, #24]
+ 802cc8a:	ee37 7b07 	vadd.f64	d7, d7, d7
+ 802cc8e:	ed87 7b06 	vstr	d7, [r7, #24]
+			CV_Robot_Deri_Angle_Deg_Plane=MF40G_Angle_Add_Deg;
+ 802cc92:	4b9d      	ldr	r3, [pc, #628]	@ (802cf08 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x300>)
+ 802cc94:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802cc98:	499f      	ldr	r1, [pc, #636]	@ (802cf18 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x310>)
+ 802cc9a:	e9c1 2300 	strd	r2, r3, [r1]
+			if(X_Deri_Angle[0]==Deri_Angle_Deg_X[0])
+ 802cc9e:	4b9f      	ldr	r3, [pc, #636]	@ (802cf1c <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x314>)
+ 802cca0:	ed93 6b00 	vldr	d6, [r3]
+ 802cca4:	4b9e      	ldr	r3, [pc, #632]	@ (802cf20 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x318>)
+ 802cca6:	ed93 7b00 	vldr	d7, [r3]
+ 802ccaa:	eeb4 6b47 	vcmp.f64	d6, d7
+ 802ccae:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802ccb2:	d135      	bne.n	802cd20 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x118>
+			{
+				Deri_Angle_Deg_X[0]=CV_Robot_Deri_Angle_Deg_Plane;
+ 802ccb4:	4b98      	ldr	r3, [pc, #608]	@ (802cf18 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x310>)
+ 802ccb6:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802ccba:	4999      	ldr	r1, [pc, #612]	@ (802cf20 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x318>)
+ 802ccbc:	e9c1 2300 	strd	r2, r3, [r1]
+				Plane_Turn_Angle_Deg=Deri_Angle_Deg_X[0]+90;
+ 802ccc0:	4b97      	ldr	r3, [pc, #604]	@ (802cf20 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x318>)
+ 802ccc2:	ed93 7b00 	vldr	d7, [r3]
+ 802ccc6:	ed9f 6b88 	vldr	d6, [pc, #544]	@ 802cee8 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x2e0>
+ 802ccca:	ee37 7b06 	vadd.f64	d7, d7, d6
+ 802ccce:	4b95      	ldr	r3, [pc, #596]	@ (802cf24 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x31c>)
+ 802ccd0:	ed83 7b00 	vstr	d7, [r3]
+				Deri_Angle_Deg_X[1]=Deri_Angle_Deg_X[0]+180;
+ 802ccd4:	4b92      	ldr	r3, [pc, #584]	@ (802cf20 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x318>)
+ 802ccd6:	ed93 7b00 	vldr	d7, [r3]
+ 802ccda:	ed9f 6b85 	vldr	d6, [pc, #532]	@ 802cef0 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x2e8>
+ 802ccde:	ee37 7b06 	vadd.f64	d7, d7, d6
+ 802cce2:	4b8f      	ldr	r3, [pc, #572]	@ (802cf20 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x318>)
+ 802cce4:	ed83 7b02 	vstr	d7, [r3, #8]
+				X_Deri_Angle[0]=Deri_Angle_Deg_X[0];
+ 802cce8:	4b8d      	ldr	r3, [pc, #564]	@ (802cf20 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x318>)
+ 802ccea:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802ccee:	498b      	ldr	r1, [pc, #556]	@ (802cf1c <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x314>)
+ 802ccf0:	e9c1 2300 	strd	r2, r3, [r1]
+				  if( Deri_Angle_Deg_X[1]>180)
+ 802ccf4:	4b8a      	ldr	r3, [pc, #552]	@ (802cf20 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x318>)
+ 802ccf6:	ed93 7b02 	vldr	d7, [r3, #8]
+ 802ccfa:	ed9f 6b7d 	vldr	d6, [pc, #500]	@ 802cef0 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x2e8>
+ 802ccfe:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 802cd02:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802cd06:	f340 80d7 	ble.w	802ceb8 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x2b0>
+				  {
+					  Deri_Angle_Deg_X[1]= Deri_Angle_Deg_X[1]-360;
+ 802cd0a:	4b85      	ldr	r3, [pc, #532]	@ (802cf20 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x318>)
+ 802cd0c:	ed93 7b02 	vldr	d7, [r3, #8]
+ 802cd10:	ed9f 6b79 	vldr	d6, [pc, #484]	@ 802cef8 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x2f0>
+ 802cd14:	ee37 7b46 	vsub.f64	d7, d7, d6
+ 802cd18:	4b81      	ldr	r3, [pc, #516]	@ (802cf20 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x318>)
+ 802cd1a:	ed83 7b02 	vstr	d7, [r3, #8]
+ 802cd1e:	e0cb      	b.n	802ceb8 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x2b0>
+				  }
+			}
+			else
+			{
+				Deri_Angle_Deg_X[1]=CV_Robot_Deri_Angle_Deg_Plane;
+ 802cd20:	4b7d      	ldr	r3, [pc, #500]	@ (802cf18 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x310>)
+ 802cd22:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802cd26:	497e      	ldr	r1, [pc, #504]	@ (802cf20 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x318>)
+ 802cd28:	e9c1 2302 	strd	r2, r3, [r1, #8]
+				Plane_Turn_Angle_Deg=Deri_Angle_Deg_X[1]-90;
+ 802cd2c:	4b7c      	ldr	r3, [pc, #496]	@ (802cf20 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x318>)
+ 802cd2e:	ed93 7b02 	vldr	d7, [r3, #8]
+ 802cd32:	ed9f 6b6d 	vldr	d6, [pc, #436]	@ 802cee8 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x2e0>
+ 802cd36:	ee37 7b46 	vsub.f64	d7, d7, d6
+ 802cd3a:	4b7a      	ldr	r3, [pc, #488]	@ (802cf24 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x31c>)
+ 802cd3c:	ed83 7b00 	vstr	d7, [r3]
+				Deri_Angle_Deg_X[0]=Deri_Angle_Deg_X[1]-180;
+ 802cd40:	4b77      	ldr	r3, [pc, #476]	@ (802cf20 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x318>)
+ 802cd42:	ed93 7b02 	vldr	d7, [r3, #8]
+ 802cd46:	ed9f 6b6a 	vldr	d6, [pc, #424]	@ 802cef0 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x2e8>
+ 802cd4a:	ee37 7b46 	vsub.f64	d7, d7, d6
+ 802cd4e:	4b74      	ldr	r3, [pc, #464]	@ (802cf20 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x318>)
+ 802cd50:	ed83 7b00 	vstr	d7, [r3]
+				X_Deri_Angle[0]=Deri_Angle_Deg_X[1];
+ 802cd54:	4b72      	ldr	r3, [pc, #456]	@ (802cf20 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x318>)
+ 802cd56:	e9d3 2302 	ldrd	r2, r3, [r3, #8]
+ 802cd5a:	4970      	ldr	r1, [pc, #448]	@ (802cf1c <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x314>)
+ 802cd5c:	e9c1 2300 	strd	r2, r3, [r1]
+				  if( Deri_Angle_Deg_X[1]>180)
+ 802cd60:	4b6f      	ldr	r3, [pc, #444]	@ (802cf20 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x318>)
+ 802cd62:	ed93 7b02 	vldr	d7, [r3, #8]
+ 802cd66:	ed9f 6b62 	vldr	d6, [pc, #392]	@ 802cef0 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x2e8>
+ 802cd6a:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 802cd6e:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802cd72:	f340 80a1 	ble.w	802ceb8 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x2b0>
+				  {
+					  Deri_Angle_Deg_X[1]= Deri_Angle_Deg_X[1]-360;
+ 802cd76:	4b6a      	ldr	r3, [pc, #424]	@ (802cf20 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x318>)
+ 802cd78:	ed93 7b02 	vldr	d7, [r3, #8]
+ 802cd7c:	ed9f 6b5e 	vldr	d6, [pc, #376]	@ 802cef8 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x2f0>
+ 802cd80:	ee37 7b46 	vsub.f64	d7, d7, d6
+ 802cd84:	4b66      	ldr	r3, [pc, #408]	@ (802cf20 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x318>)
+ 802cd86:	ed83 7b02 	vstr	d7, [r3, #8]
+ 802cd8a:	e095      	b.n	802ceb8 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x2b0>
+				  }
+			}
+		}
+	}
+	else if(P_MK32->CH3_LY_H>300)
+ 802cd8c:	4b60      	ldr	r3, [pc, #384]	@ (802cf10 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x308>)
+ 802cd8e:	681b      	ldr	r3, [r3, #0]
+ 802cd90:	691b      	ldr	r3, [r3, #16]
+ 802cd92:	f5b3 7f96 	cmp.w	r3, #300	@ 0x12c
+ 802cd96:	f340 808c 	ble.w	802ceb2 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x2aa>
+	{
+		Turn_Count++;
+ 802cd9a:	4b5e      	ldr	r3, [pc, #376]	@ (802cf14 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x30c>)
+ 802cd9c:	681b      	ldr	r3, [r3, #0]
+ 802cd9e:	3301      	adds	r3, #1
+ 802cda0:	4a5c      	ldr	r2, [pc, #368]	@ (802cf14 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x30c>)
+ 802cda2:	6013      	str	r3, [r2, #0]
+		if(Turn_Count>1000)
+ 802cda4:	4b5b      	ldr	r3, [pc, #364]	@ (802cf14 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x30c>)
+ 802cda6:	681b      	ldr	r3, [r3, #0]
+ 802cda8:	f5b3 7f7a 	cmp.w	r3, #1000	@ 0x3e8
+ 802cdac:	f340 8084 	ble.w	802ceb8 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x2b0>
+		{
+			Robot_Speed[0]=Robot_Speed[0]+Robot_Speed[0]*1;
+ 802cdb0:	ed97 7b04 	vldr	d7, [r7, #16]
+ 802cdb4:	ee37 7b07 	vadd.f64	d7, d7, d7
+ 802cdb8:	ed87 7b04 	vstr	d7, [r7, #16]
+			CV_Robot_Deri_Angle_Deg_Plane=MF40G_Angle_Add_Deg;
+ 802cdbc:	4b52      	ldr	r3, [pc, #328]	@ (802cf08 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x300>)
+ 802cdbe:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802cdc2:	4955      	ldr	r1, [pc, #340]	@ (802cf18 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x310>)
+ 802cdc4:	e9c1 2300 	strd	r2, r3, [r1]
+			if(X_Deri_Angle[0]==Deri_Angle_Deg_X[0])
+ 802cdc8:	4b54      	ldr	r3, [pc, #336]	@ (802cf1c <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x314>)
+ 802cdca:	ed93 6b00 	vldr	d6, [r3]
+ 802cdce:	4b54      	ldr	r3, [pc, #336]	@ (802cf20 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x318>)
+ 802cdd0:	ed93 7b00 	vldr	d7, [r3]
+ 802cdd4:	eeb4 6b47 	vcmp.f64	d6, d7
+ 802cdd8:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802cddc:	d134      	bne.n	802ce48 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x240>
+			{
+				Deri_Angle_Deg_X[0]=CV_Robot_Deri_Angle_Deg_Plane;
+ 802cdde:	4b4e      	ldr	r3, [pc, #312]	@ (802cf18 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x310>)
+ 802cde0:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802cde4:	494e      	ldr	r1, [pc, #312]	@ (802cf20 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x318>)
+ 802cde6:	e9c1 2300 	strd	r2, r3, [r1]
+				Plane_Turn_Angle_Deg=Deri_Angle_Deg_X[0]+90;
+ 802cdea:	4b4d      	ldr	r3, [pc, #308]	@ (802cf20 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x318>)
+ 802cdec:	ed93 7b00 	vldr	d7, [r3]
+ 802cdf0:	ed9f 6b3d 	vldr	d6, [pc, #244]	@ 802cee8 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x2e0>
+ 802cdf4:	ee37 7b06 	vadd.f64	d7, d7, d6
+ 802cdf8:	4b4a      	ldr	r3, [pc, #296]	@ (802cf24 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x31c>)
+ 802cdfa:	ed83 7b00 	vstr	d7, [r3]
+				Deri_Angle_Deg_X[1]=Deri_Angle_Deg_X[0]+180;
+ 802cdfe:	4b48      	ldr	r3, [pc, #288]	@ (802cf20 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x318>)
+ 802ce00:	ed93 7b00 	vldr	d7, [r3]
+ 802ce04:	ed9f 6b3a 	vldr	d6, [pc, #232]	@ 802cef0 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x2e8>
+ 802ce08:	ee37 7b06 	vadd.f64	d7, d7, d6
+ 802ce0c:	4b44      	ldr	r3, [pc, #272]	@ (802cf20 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x318>)
+ 802ce0e:	ed83 7b02 	vstr	d7, [r3, #8]
+				X_Deri_Angle[0]=Deri_Angle_Deg_X[0];
+ 802ce12:	4b43      	ldr	r3, [pc, #268]	@ (802cf20 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x318>)
+ 802ce14:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802ce18:	4940      	ldr	r1, [pc, #256]	@ (802cf1c <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x314>)
+ 802ce1a:	e9c1 2300 	strd	r2, r3, [r1]
+				  if( Deri_Angle_Deg_X[1]>180)
+ 802ce1e:	4b40      	ldr	r3, [pc, #256]	@ (802cf20 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x318>)
+ 802ce20:	ed93 7b02 	vldr	d7, [r3, #8]
+ 802ce24:	ed9f 6b32 	vldr	d6, [pc, #200]	@ 802cef0 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x2e8>
+ 802ce28:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 802ce2c:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802ce30:	dd42      	ble.n	802ceb8 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x2b0>
+				  {
+					  Deri_Angle_Deg_X[1]= Deri_Angle_Deg_X[1]-360;
+ 802ce32:	4b3b      	ldr	r3, [pc, #236]	@ (802cf20 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x318>)
+ 802ce34:	ed93 7b02 	vldr	d7, [r3, #8]
+ 802ce38:	ed9f 6b2f 	vldr	d6, [pc, #188]	@ 802cef8 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x2f0>
+ 802ce3c:	ee37 7b46 	vsub.f64	d7, d7, d6
+ 802ce40:	4b37      	ldr	r3, [pc, #220]	@ (802cf20 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x318>)
+ 802ce42:	ed83 7b02 	vstr	d7, [r3, #8]
+ 802ce46:	e037      	b.n	802ceb8 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x2b0>
+				  }
+			}
+			else
+			{
+				Deri_Angle_Deg_X[1]=CV_Robot_Deri_Angle_Deg_Plane;
+ 802ce48:	4b33      	ldr	r3, [pc, #204]	@ (802cf18 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x310>)
+ 802ce4a:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802ce4e:	4934      	ldr	r1, [pc, #208]	@ (802cf20 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x318>)
+ 802ce50:	e9c1 2302 	strd	r2, r3, [r1, #8]
+				Plane_Turn_Angle_Deg=Deri_Angle_Deg_X[1]-90;
+ 802ce54:	4b32      	ldr	r3, [pc, #200]	@ (802cf20 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x318>)
+ 802ce56:	ed93 7b02 	vldr	d7, [r3, #8]
+ 802ce5a:	ed9f 6b23 	vldr	d6, [pc, #140]	@ 802cee8 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x2e0>
+ 802ce5e:	ee37 7b46 	vsub.f64	d7, d7, d6
+ 802ce62:	4b30      	ldr	r3, [pc, #192]	@ (802cf24 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x31c>)
+ 802ce64:	ed83 7b00 	vstr	d7, [r3]
+				Deri_Angle_Deg_X[0]=Deri_Angle_Deg_X[1]-180;
+ 802ce68:	4b2d      	ldr	r3, [pc, #180]	@ (802cf20 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x318>)
+ 802ce6a:	ed93 7b02 	vldr	d7, [r3, #8]
+ 802ce6e:	ed9f 6b20 	vldr	d6, [pc, #128]	@ 802cef0 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x2e8>
+ 802ce72:	ee37 7b46 	vsub.f64	d7, d7, d6
+ 802ce76:	4b2a      	ldr	r3, [pc, #168]	@ (802cf20 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x318>)
+ 802ce78:	ed83 7b00 	vstr	d7, [r3]
+				X_Deri_Angle[0]=Deri_Angle_Deg_X[1];
+ 802ce7c:	4b28      	ldr	r3, [pc, #160]	@ (802cf20 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x318>)
+ 802ce7e:	e9d3 2302 	ldrd	r2, r3, [r3, #8]
+ 802ce82:	4926      	ldr	r1, [pc, #152]	@ (802cf1c <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x314>)
+ 802ce84:	e9c1 2300 	strd	r2, r3, [r1]
+				  if( Deri_Angle_Deg_X[0]<-180)
+ 802ce88:	4b25      	ldr	r3, [pc, #148]	@ (802cf20 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x318>)
+ 802ce8a:	ed93 7b00 	vldr	d7, [r3]
+ 802ce8e:	ed9f 6b1c 	vldr	d6, [pc, #112]	@ 802cf00 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x2f8>
+ 802ce92:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 802ce96:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802ce9a:	d50d      	bpl.n	802ceb8 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x2b0>
+				  {
+					  Deri_Angle_Deg_X[0]= Deri_Angle_Deg_X[1]+360;
+ 802ce9c:	4b20      	ldr	r3, [pc, #128]	@ (802cf20 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x318>)
+ 802ce9e:	ed93 7b02 	vldr	d7, [r3, #8]
+ 802cea2:	ed9f 6b15 	vldr	d6, [pc, #84]	@ 802cef8 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x2f0>
+ 802cea6:	ee37 7b06 	vadd.f64	d7, d7, d6
+ 802ceaa:	4b1d      	ldr	r3, [pc, #116]	@ (802cf20 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x318>)
+ 802ceac:	ed83 7b00 	vstr	d7, [r3]
+ 802ceb0:	e002      	b.n	802ceb8 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x2b0>
+			}
+		}
+	}
+	else
+	{
+		Turn_Count=0;
+ 802ceb2:	4b18      	ldr	r3, [pc, #96]	@ (802cf14 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x30c>)
+ 802ceb4:	2200      	movs	r2, #0
+ 802ceb6:	601a      	str	r2, [r3, #0]
+	}
+	GV.LeftMotor.Target_Velcity =-Robot_Speed[1];
+ 802ceb8:	ed97 7b06 	vldr	d7, [r7, #24]
+ 802cebc:	eeb1 7b47 	vneg.f64	d7, d7
+ 802cec0:	eefd 7bc7 	vcvt.s32.f64	s15, d7
+ 802cec4:	ee17 2a90 	vmov	r2, s15
+ 802cec8:	4b17      	ldr	r3, [pc, #92]	@ (802cf28 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x320>)
+ 802ceca:	679a      	str	r2, [r3, #120]	@ 0x78
+	GV.RightMotor.Target_Velcity =Robot_Speed[0];
+ 802cecc:	ed97 7b04 	vldr	d7, [r7, #16]
+ 802ced0:	eefd 7bc7 	vcvt.s32.f64	s15, d7
+ 802ced4:	ee17 2a90 	vmov	r2, s15
+ 802ced8:	4b13      	ldr	r3, [pc, #76]	@ (802cf28 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin+0x320>)
+ 802ceda:	f8c3 20f8 	str.w	r2, [r3, #248]	@ 0xf8
+}
+ 802cede:	bf00      	nop
+ 802cee0:	3740      	adds	r7, #64	@ 0x40
+ 802cee2:	46bd      	mov	sp, r7
+ 802cee4:	bd80      	pop	{r7, pc}
+ 802cee6:	bf00      	nop
+ 802cee8:	00000000 	.word	0x00000000
+ 802ceec:	40568000 	.word	0x40568000
+ 802cef0:	00000000 	.word	0x00000000
+ 802cef4:	40668000 	.word	0x40668000
+ 802cef8:	00000000 	.word	0x00000000
+ 802cefc:	40768000 	.word	0x40768000
+ 802cf00:	00000000 	.word	0x00000000
+ 802cf04:	c0668000 	.word	0xc0668000
+ 802cf08:	2400a788 	.word	0x2400a788
+ 802cf0c:	240000b0 	.word	0x240000b0
+ 802cf10:	2400a3f8 	.word	0x2400a3f8
+ 802cf14:	2400a8c0 	.word	0x2400a8c0
+ 802cf18:	2400a6d8 	.word	0x2400a6d8
+ 802cf1c:	2400a7c0 	.word	0x2400a7c0
+ 802cf20:	2400a7b0 	.word	0x2400a7b0
+ 802cf24:	2400a7a8 	.word	0x2400a7a8
+ 802cf28:	24000340 	.word	0x24000340
+
+0802cf2c <Change_Road_Left>:
+
+
+
+int Change_R_L_Count_1;
+void Change_Road_Left()
+{
+ 802cf2c:	b580      	push	{r7, lr}
+ 802cf2e:	b084      	sub	sp, #16
+ 802cf30:	af00      	add	r7, sp, #0
+
+	double Der_Angle_Left[2]={0,-90};
+ 802cf32:	f04f 0200 	mov.w	r2, #0
+ 802cf36:	f04f 0300 	mov.w	r3, #0
+ 802cf3a:	e9c7 2300 	strd	r2, r3, [r7]
+ 802cf3e:	f04f 0200 	mov.w	r2, #0
+ 802cf42:	4b45      	ldr	r3, [pc, #276]	@ (802d058 <Change_Road_Left+0x12c>)
+ 802cf44:	e9c7 2302 	strd	r2, r3, [r7, #8]
+	switch(CRLU_Flag)
+ 802cf48:	4b44      	ldr	r3, [pc, #272]	@ (802d05c <Change_Road_Left+0x130>)
+ 802cf4a:	681b      	ldr	r3, [r3, #0]
+ 802cf4c:	2b04      	cmp	r3, #4
+ 802cf4e:	d87b      	bhi.n	802d048 <Change_Road_Left+0x11c>
+ 802cf50:	a201      	add	r2, pc, #4	@ (adr r2, 802cf58 <Change_Road_Left+0x2c>)
+ 802cf52:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 802cf56:	bf00      	nop
+ 802cf58:	0802cf6d 	.word	0x0802cf6d
+ 802cf5c:	0802cfa5 	.word	0x0802cfa5
+ 802cf60:	0802cfb5 	.word	0x0802cfb5
+ 802cf64:	0802d007 	.word	0x0802d007
+ 802cf68:	0802d039 	.word	0x0802d039
+	{
+	case 0://两轮速度相同转向
+		CV_Robot_Deri_Angle_Deg_Grity=Der_Angle_Left[0];
+ 802cf6c:	e9d7 2300 	ldrd	r2, r3, [r7]
+ 802cf70:	493b      	ldr	r1, [pc, #236]	@ (802d060 <Change_Road_Left+0x134>)
+ 802cf72:	e9c1 2300 	strd	r2, r3, [r1]
+		Robot_Posture_Adjus_Gravity();
+ 802cf76:	f7fe ff5b 	bl	802be30 <Robot_Posture_Adjus_Gravity>
+		if(Angle_Error_LLL<Error_Cont_Thresh)
+ 802cf7a:	4b3a      	ldr	r3, [pc, #232]	@ (802d064 <Change_Road_Left+0x138>)
+ 802cf7c:	ed93 6b00 	vldr	d6, [r3]
+ 802cf80:	4b39      	ldr	r3, [pc, #228]	@ (802d068 <Change_Road_Left+0x13c>)
+ 802cf82:	ed93 7b00 	vldr	d7, [r3]
+ 802cf86:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802cf8a:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802cf8e:	d400      	bmi.n	802cf92 <Change_Road_Left+0x66>
+		{
+			CRLU_Flag++;
+			Change_R_L_Count_1=0;
+		}
+		break;
+ 802cf90:	e05d      	b.n	802d04e <Change_Road_Left+0x122>
+			CRLU_Flag++;
+ 802cf92:	4b32      	ldr	r3, [pc, #200]	@ (802d05c <Change_Road_Left+0x130>)
+ 802cf94:	681b      	ldr	r3, [r3, #0]
+ 802cf96:	3301      	adds	r3, #1
+ 802cf98:	4a30      	ldr	r2, [pc, #192]	@ (802d05c <Change_Road_Left+0x130>)
+ 802cf9a:	6013      	str	r3, [r2, #0]
+			Change_R_L_Count_1=0;
+ 802cf9c:	4b33      	ldr	r3, [pc, #204]	@ (802d06c <Change_Road_Left+0x140>)
+ 802cf9e:	2200      	movs	r2, #0
+ 802cfa0:	601a      	str	r2, [r3, #0]
+		break;
+ 802cfa2:	e054      	b.n	802d04e <Change_Road_Left+0x122>
+	case 1:   //计算后退时间
+		Horizontal_Change_Road_Back_Time_Compute();
+ 802cfa4:	f000 fa90 	bl	802d4c8 <Horizontal_Change_Road_Back_Time_Compute>
+		CRLU_Flag++;
+ 802cfa8:	4b2c      	ldr	r3, [pc, #176]	@ (802d05c <Change_Road_Left+0x130>)
+ 802cfaa:	681b      	ldr	r3, [r3, #0]
+ 802cfac:	3301      	adds	r3, #1
+ 802cfae:	4a2b      	ldr	r2, [pc, #172]	@ (802d05c <Change_Road_Left+0x130>)
+ 802cfb0:	6013      	str	r3, [r2, #0]
+		break;
+ 802cfb2:	e04c      	b.n	802d04e <Change_Road_Left+0x122>
+	case 2://PID转向期望角度1
+		Change_R_L_Count_1++;
+ 802cfb4:	4b2d      	ldr	r3, [pc, #180]	@ (802d06c <Change_Road_Left+0x140>)
+ 802cfb6:	681b      	ldr	r3, [r3, #0]
+ 802cfb8:	3301      	adds	r3, #1
+ 802cfba:	4a2c      	ldr	r2, [pc, #176]	@ (802d06c <Change_Road_Left+0x140>)
+ 802cfbc:	6013      	str	r3, [r2, #0]
+//		Move_Vertical_Task_Change_Road_Backwards_Do();
+
+		Move_Horizontal_Vertical_Task_Backwards_Do_Backward(Change_Road_Speed,CV_Robot_Deri_Angle_Deg_Grity);
+ 802cfbe:	4b2c      	ldr	r3, [pc, #176]	@ (802d070 <Change_Road_Left+0x144>)
+ 802cfc0:	ed93 7b00 	vldr	d7, [r3]
+ 802cfc4:	4b26      	ldr	r3, [pc, #152]	@ (802d060 <Change_Road_Left+0x134>)
+ 802cfc6:	ed93 6b00 	vldr	d6, [r3]
+ 802cfca:	eeb0 1b46 	vmov.f64	d1, d6
+ 802cfce:	eeb0 0b47 	vmov.f64	d0, d7
+ 802cfd2:	f7ff fced 	bl	802c9b0 <Move_Horizontal_Vertical_Task_Backwards_Do_Backward>
+		if(Change_R_L_Count_1>Horizontal_Change_Road_Time)
+ 802cfd6:	4b25      	ldr	r3, [pc, #148]	@ (802d06c <Change_Road_Left+0x140>)
+ 802cfd8:	681b      	ldr	r3, [r3, #0]
+ 802cfda:	ee07 3a90 	vmov	s15, r3
+ 802cfde:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802cfe2:	4b24      	ldr	r3, [pc, #144]	@ (802d074 <Change_Road_Left+0x148>)
+ 802cfe4:	ed93 7b00 	vldr	d7, [r3]
+ 802cfe8:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802cfec:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802cff0:	dc00      	bgt.n	802cff4 <Change_Road_Left+0xc8>
+		{
+			CRLU_Flag++;
+			Change_R_L_Count_1=0;
+		}
+		break;
+ 802cff2:	e02c      	b.n	802d04e <Change_Road_Left+0x122>
+			CRLU_Flag++;
+ 802cff4:	4b19      	ldr	r3, [pc, #100]	@ (802d05c <Change_Road_Left+0x130>)
+ 802cff6:	681b      	ldr	r3, [r3, #0]
+ 802cff8:	3301      	adds	r3, #1
+ 802cffa:	4a18      	ldr	r2, [pc, #96]	@ (802d05c <Change_Road_Left+0x130>)
+ 802cffc:	6013      	str	r3, [r2, #0]
+			Change_R_L_Count_1=0;
+ 802cffe:	4b1b      	ldr	r3, [pc, #108]	@ (802d06c <Change_Road_Left+0x140>)
+ 802d000:	2200      	movs	r2, #0
+ 802d002:	601a      	str	r2, [r3, #0]
+		break;
+ 802d004:	e023      	b.n	802d04e <Change_Road_Left+0x122>
+	case 3://后退指定距离
+		CV_Robot_Deri_Angle_Deg_Grity=Der_Angle_Left[1];
+ 802d006:	e9d7 2302 	ldrd	r2, r3, [r7, #8]
+ 802d00a:	4915      	ldr	r1, [pc, #84]	@ (802d060 <Change_Road_Left+0x134>)
+ 802d00c:	e9c1 2300 	strd	r2, r3, [r1]
+		Robot_Posture_Adjus_Gravity();
+ 802d010:	f7fe ff0e 	bl	802be30 <Robot_Posture_Adjus_Gravity>
+		if(Angle_Error_LLL<Error_Cont_Thresh)
+ 802d014:	4b13      	ldr	r3, [pc, #76]	@ (802d064 <Change_Road_Left+0x138>)
+ 802d016:	ed93 6b00 	vldr	d6, [r3]
+ 802d01a:	4b13      	ldr	r3, [pc, #76]	@ (802d068 <Change_Road_Left+0x13c>)
+ 802d01c:	ed93 7b00 	vldr	d7, [r3]
+ 802d020:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802d024:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802d028:	d400      	bmi.n	802d02c <Change_Road_Left+0x100>
+		{
+			CRLU_Flag++;
+		}
+		break;
+ 802d02a:	e010      	b.n	802d04e <Change_Road_Left+0x122>
+			CRLU_Flag++;
+ 802d02c:	4b0b      	ldr	r3, [pc, #44]	@ (802d05c <Change_Road_Left+0x130>)
+ 802d02e:	681b      	ldr	r3, [r3, #0]
+ 802d030:	3301      	adds	r3, #1
+ 802d032:	4a0a      	ldr	r2, [pc, #40]	@ (802d05c <Change_Road_Left+0x130>)
+ 802d034:	6013      	str	r3, [r2, #0]
+		break;
+ 802d036:	e00a      	b.n	802d04e <Change_Road_Left+0x122>
+	case 4://到达位置
+		GV.LeftMotor.Target_Velcity=0;
+ 802d038:	4b0f      	ldr	r3, [pc, #60]	@ (802d078 <Change_Road_Left+0x14c>)
+ 802d03a:	2200      	movs	r2, #0
+ 802d03c:	679a      	str	r2, [r3, #120]	@ 0x78
+		GV.RightMotor.Target_Velcity=0;
+ 802d03e:	4b0e      	ldr	r3, [pc, #56]	@ (802d078 <Change_Road_Left+0x14c>)
+ 802d040:	2200      	movs	r2, #0
+ 802d042:	f8c3 20f8 	str.w	r2, [r3, #248]	@ 0xf8
+		break;
+ 802d046:	e002      	b.n	802d04e <Change_Road_Left+0x122>
+	default:
+		HALT_State_Do();
+ 802d048:	f003 f88e 	bl	8030168 <HALT_State_Do>
+		break;
+ 802d04c:	bf00      	nop
+	}
+}
+ 802d04e:	bf00      	nop
+ 802d050:	3710      	adds	r7, #16
+ 802d052:	46bd      	mov	sp, r7
+ 802d054:	bd80      	pop	{r7, pc}
+ 802d056:	bf00      	nop
+ 802d058:	c0568000 	.word	0xc0568000
+ 802d05c:	2400a9f0 	.word	0x2400a9f0
+ 802d060:	2400a6d0 	.word	0x2400a6d0
+ 802d064:	2400a9e8 	.word	0x2400a9e8
+ 802d068:	24000090 	.word	0x24000090
+ 802d06c:	2400a808 	.word	0x2400a808
+ 802d070:	240000d0 	.word	0x240000d0
+ 802d074:	240000c0 	.word	0x240000c0
+ 802d078:	24000340 	.word	0x24000340
+
+0802d07c <Change_Road_Right>:
+
+
+
+void Change_Road_Right()
+{
+ 802d07c:	b580      	push	{r7, lr}
+ 802d07e:	b084      	sub	sp, #16
+ 802d080:	af00      	add	r7, sp, #0
+	static int Change_R_L_Count;
+	double Der_Angle_Right[2]={0,90};
+ 802d082:	f04f 0200 	mov.w	r2, #0
+ 802d086:	f04f 0300 	mov.w	r3, #0
+ 802d08a:	e9c7 2300 	strd	r2, r3, [r7]
+ 802d08e:	f04f 0200 	mov.w	r2, #0
+ 802d092:	4b45      	ldr	r3, [pc, #276]	@ (802d1a8 <Change_Road_Right+0x12c>)
+ 802d094:	e9c7 2302 	strd	r2, r3, [r7, #8]
+	switch(CRLU_Flag)
+ 802d098:	4b44      	ldr	r3, [pc, #272]	@ (802d1ac <Change_Road_Right+0x130>)
+ 802d09a:	681b      	ldr	r3, [r3, #0]
+ 802d09c:	2b04      	cmp	r3, #4
+ 802d09e:	d87b      	bhi.n	802d198 <Change_Road_Right+0x11c>
+ 802d0a0:	a201      	add	r2, pc, #4	@ (adr r2, 802d0a8 <Change_Road_Right+0x2c>)
+ 802d0a2:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 802d0a6:	bf00      	nop
+ 802d0a8:	0802d0bd 	.word	0x0802d0bd
+ 802d0ac:	0802d0f5 	.word	0x0802d0f5
+ 802d0b0:	0802d105 	.word	0x0802d105
+ 802d0b4:	0802d157 	.word	0x0802d157
+ 802d0b8:	0802d189 	.word	0x0802d189
+	{
+	case 0://两轮速度相同转向
+		CV_Robot_Deri_Angle_Deg_Grity=Der_Angle_Right[0];
+ 802d0bc:	e9d7 2300 	ldrd	r2, r3, [r7]
+ 802d0c0:	493b      	ldr	r1, [pc, #236]	@ (802d1b0 <Change_Road_Right+0x134>)
+ 802d0c2:	e9c1 2300 	strd	r2, r3, [r1]
+		Robot_Posture_Adjus_Gravity();
+ 802d0c6:	f7fe feb3 	bl	802be30 <Robot_Posture_Adjus_Gravity>
+		if(Angle_Error_LLL<Error_Cont_Thresh)
+ 802d0ca:	4b3a      	ldr	r3, [pc, #232]	@ (802d1b4 <Change_Road_Right+0x138>)
+ 802d0cc:	ed93 6b00 	vldr	d6, [r3]
+ 802d0d0:	4b39      	ldr	r3, [pc, #228]	@ (802d1b8 <Change_Road_Right+0x13c>)
+ 802d0d2:	ed93 7b00 	vldr	d7, [r3]
+ 802d0d6:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802d0da:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802d0de:	d400      	bmi.n	802d0e2 <Change_Road_Right+0x66>
+		{
+			CRLU_Flag++;
+			Change_R_L_Count=0;
+		}
+		break;
+ 802d0e0:	e05d      	b.n	802d19e <Change_Road_Right+0x122>
+			CRLU_Flag++;
+ 802d0e2:	4b32      	ldr	r3, [pc, #200]	@ (802d1ac <Change_Road_Right+0x130>)
+ 802d0e4:	681b      	ldr	r3, [r3, #0]
+ 802d0e6:	3301      	adds	r3, #1
+ 802d0e8:	4a30      	ldr	r2, [pc, #192]	@ (802d1ac <Change_Road_Right+0x130>)
+ 802d0ea:	6013      	str	r3, [r2, #0]
+			Change_R_L_Count=0;
+ 802d0ec:	4b33      	ldr	r3, [pc, #204]	@ (802d1bc <Change_Road_Right+0x140>)
+ 802d0ee:	2200      	movs	r2, #0
+ 802d0f0:	601a      	str	r2, [r3, #0]
+		break;
+ 802d0f2:	e054      	b.n	802d19e <Change_Road_Right+0x122>
+	case 1://计算后退时间，设定后退速度
+		CRLU_Flag++;
+ 802d0f4:	4b2d      	ldr	r3, [pc, #180]	@ (802d1ac <Change_Road_Right+0x130>)
+ 802d0f6:	681b      	ldr	r3, [r3, #0]
+ 802d0f8:	3301      	adds	r3, #1
+ 802d0fa:	4a2c      	ldr	r2, [pc, #176]	@ (802d1ac <Change_Road_Right+0x130>)
+ 802d0fc:	6013      	str	r3, [r2, #0]
+
+		Horizontal_Change_Road_Back_Time_Compute();
+ 802d0fe:	f000 f9e3 	bl	802d4c8 <Horizontal_Change_Road_Back_Time_Compute>
+		break;
+ 802d102:	e04c      	b.n	802d19e <Change_Road_Right+0x122>
+	case 2://PID转向期望角度1
+		Change_R_L_Count++;
+ 802d104:	4b2d      	ldr	r3, [pc, #180]	@ (802d1bc <Change_Road_Right+0x140>)
+ 802d106:	681b      	ldr	r3, [r3, #0]
+ 802d108:	3301      	adds	r3, #1
+ 802d10a:	4a2c      	ldr	r2, [pc, #176]	@ (802d1bc <Change_Road_Right+0x140>)
+ 802d10c:	6013      	str	r3, [r2, #0]
+//		Move_Vertical_Task_Change_Road_Backwards_Do();
+		Move_Horizontal_Vertical_Task_Backwards_Do_Backward(Change_Road_Speed,CV_Robot_Deri_Angle_Deg_Grity);
+ 802d10e:	4b2c      	ldr	r3, [pc, #176]	@ (802d1c0 <Change_Road_Right+0x144>)
+ 802d110:	ed93 7b00 	vldr	d7, [r3]
+ 802d114:	4b26      	ldr	r3, [pc, #152]	@ (802d1b0 <Change_Road_Right+0x134>)
+ 802d116:	ed93 6b00 	vldr	d6, [r3]
+ 802d11a:	eeb0 1b46 	vmov.f64	d1, d6
+ 802d11e:	eeb0 0b47 	vmov.f64	d0, d7
+ 802d122:	f7ff fc45 	bl	802c9b0 <Move_Horizontal_Vertical_Task_Backwards_Do_Backward>
+		if(Change_R_L_Count>Horizontal_Change_Road_Time)
+ 802d126:	4b25      	ldr	r3, [pc, #148]	@ (802d1bc <Change_Road_Right+0x140>)
+ 802d128:	681b      	ldr	r3, [r3, #0]
+ 802d12a:	ee07 3a90 	vmov	s15, r3
+ 802d12e:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802d132:	4b24      	ldr	r3, [pc, #144]	@ (802d1c4 <Change_Road_Right+0x148>)
+ 802d134:	ed93 7b00 	vldr	d7, [r3]
+ 802d138:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802d13c:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802d140:	dc00      	bgt.n	802d144 <Change_Road_Right+0xc8>
+		{
+			CRLU_Flag++;
+			Change_R_L_Count=0;
+		}
+		break;
+ 802d142:	e02c      	b.n	802d19e <Change_Road_Right+0x122>
+			CRLU_Flag++;
+ 802d144:	4b19      	ldr	r3, [pc, #100]	@ (802d1ac <Change_Road_Right+0x130>)
+ 802d146:	681b      	ldr	r3, [r3, #0]
+ 802d148:	3301      	adds	r3, #1
+ 802d14a:	4a18      	ldr	r2, [pc, #96]	@ (802d1ac <Change_Road_Right+0x130>)
+ 802d14c:	6013      	str	r3, [r2, #0]
+			Change_R_L_Count=0;
+ 802d14e:	4b1b      	ldr	r3, [pc, #108]	@ (802d1bc <Change_Road_Right+0x140>)
+ 802d150:	2200      	movs	r2, #0
+ 802d152:	601a      	str	r2, [r3, #0]
+		break;
+ 802d154:	e023      	b.n	802d19e <Change_Road_Right+0x122>
+	case 3://后退指定距离
+		CV_Robot_Deri_Angle_Deg_Grity=Der_Angle_Right[1];
+ 802d156:	e9d7 2302 	ldrd	r2, r3, [r7, #8]
+ 802d15a:	4915      	ldr	r1, [pc, #84]	@ (802d1b0 <Change_Road_Right+0x134>)
+ 802d15c:	e9c1 2300 	strd	r2, r3, [r1]
+		Robot_Posture_Adjus_Gravity();
+ 802d160:	f7fe fe66 	bl	802be30 <Robot_Posture_Adjus_Gravity>
+		if(Angle_Error_LLL<Error_Cont_Thresh)
+ 802d164:	4b13      	ldr	r3, [pc, #76]	@ (802d1b4 <Change_Road_Right+0x138>)
+ 802d166:	ed93 6b00 	vldr	d6, [r3]
+ 802d16a:	4b13      	ldr	r3, [pc, #76]	@ (802d1b8 <Change_Road_Right+0x13c>)
+ 802d16c:	ed93 7b00 	vldr	d7, [r3]
+ 802d170:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802d174:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802d178:	d400      	bmi.n	802d17c <Change_Road_Right+0x100>
+		{
+			CRLU_Flag++;
+		}
+		break;
+ 802d17a:	e010      	b.n	802d19e <Change_Road_Right+0x122>
+			CRLU_Flag++;
+ 802d17c:	4b0b      	ldr	r3, [pc, #44]	@ (802d1ac <Change_Road_Right+0x130>)
+ 802d17e:	681b      	ldr	r3, [r3, #0]
+ 802d180:	3301      	adds	r3, #1
+ 802d182:	4a0a      	ldr	r2, [pc, #40]	@ (802d1ac <Change_Road_Right+0x130>)
+ 802d184:	6013      	str	r3, [r2, #0]
+		break;
+ 802d186:	e00a      	b.n	802d19e <Change_Road_Right+0x122>
+	case 4://到达位置
+		GV.LeftMotor.Target_Velcity=0;
+ 802d188:	4b0f      	ldr	r3, [pc, #60]	@ (802d1c8 <Change_Road_Right+0x14c>)
+ 802d18a:	2200      	movs	r2, #0
+ 802d18c:	679a      	str	r2, [r3, #120]	@ 0x78
+		GV.RightMotor.Target_Velcity=0;
+ 802d18e:	4b0e      	ldr	r3, [pc, #56]	@ (802d1c8 <Change_Road_Right+0x14c>)
+ 802d190:	2200      	movs	r2, #0
+ 802d192:	f8c3 20f8 	str.w	r2, [r3, #248]	@ 0xf8
+		break;
+ 802d196:	e002      	b.n	802d19e <Change_Road_Right+0x122>
+	default:
+		HALT_State_Do();
+ 802d198:	f002 ffe6 	bl	8030168 <HALT_State_Do>
+		break;
+ 802d19c:	bf00      	nop
+	}
+}
+ 802d19e:	bf00      	nop
+ 802d1a0:	3710      	adds	r7, #16
+ 802d1a2:	46bd      	mov	sp, r7
+ 802d1a4:	bd80      	pop	{r7, pc}
+ 802d1a6:	bf00      	nop
+ 802d1a8:	40568000 	.word	0x40568000
+ 802d1ac:	2400a9f0 	.word	0x2400a9f0
+ 802d1b0:	2400a6d0 	.word	0x2400a6d0
+ 802d1b4:	2400a9e8 	.word	0x2400a9e8
+ 802d1b8:	24000090 	.word	0x24000090
+ 802d1bc:	2400a8c4 	.word	0x2400a8c4
+ 802d1c0:	240000d0 	.word	0x240000d0
+ 802d1c4:	240000c0 	.word	0x240000c0
+ 802d1c8:	24000340 	.word	0x24000340
+
+0802d1cc <Forwards_State_Do>:
+
+
+
+void Forwards_State_Do(void)
+{
+ 802d1cc:	b480      	push	{r7}
+ 802d1ce:	af00      	add	r7, sp, #0
+	GV.LeftMotor.Target_Velcity = Robot_Speed_Base;
+ 802d1d0:	4b0c      	ldr	r3, [pc, #48]	@ (802d204 <Forwards_State_Do+0x38>)
+ 802d1d2:	ed93 7b00 	vldr	d7, [r3]
+ 802d1d6:	eefd 7bc7 	vcvt.s32.f64	s15, d7
+ 802d1da:	ee17 2a90 	vmov	r2, s15
+ 802d1de:	4b0a      	ldr	r3, [pc, #40]	@ (802d208 <Forwards_State_Do+0x3c>)
+ 802d1e0:	679a      	str	r2, [r3, #120]	@ 0x78
+	GV.RightMotor.Target_Velcity = -Robot_Speed_Base;
+ 802d1e2:	4b08      	ldr	r3, [pc, #32]	@ (802d204 <Forwards_State_Do+0x38>)
+ 802d1e4:	ed93 7b00 	vldr	d7, [r3]
+ 802d1e8:	eeb1 7b47 	vneg.f64	d7, d7
+ 802d1ec:	eefd 7bc7 	vcvt.s32.f64	s15, d7
+ 802d1f0:	ee17 2a90 	vmov	r2, s15
+ 802d1f4:	4b04      	ldr	r3, [pc, #16]	@ (802d208 <Forwards_State_Do+0x3c>)
+ 802d1f6:	f8c3 20f8 	str.w	r2, [r3, #248]	@ 0xf8
+
+}
+ 802d1fa:	bf00      	nop
+ 802d1fc:	46bd      	mov	sp, r7
+ 802d1fe:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 802d202:	4770      	bx	lr
+ 802d204:	2400a758 	.word	0x2400a758
+ 802d208:	24000340 	.word	0x24000340
+
+0802d20c <Backwards_State_Do>:
+
+void Backwards_State_Do(void)
+{
+ 802d20c:	b480      	push	{r7}
+ 802d20e:	af00      	add	r7, sp, #0
+	GV.LeftMotor.Target_Velcity =  -Robot_Speed_Base;
+ 802d210:	4b0c      	ldr	r3, [pc, #48]	@ (802d244 <Backwards_State_Do+0x38>)
+ 802d212:	ed93 7b00 	vldr	d7, [r3]
+ 802d216:	eeb1 7b47 	vneg.f64	d7, d7
+ 802d21a:	eefd 7bc7 	vcvt.s32.f64	s15, d7
+ 802d21e:	ee17 2a90 	vmov	r2, s15
+ 802d222:	4b09      	ldr	r3, [pc, #36]	@ (802d248 <Backwards_State_Do+0x3c>)
+ 802d224:	679a      	str	r2, [r3, #120]	@ 0x78
+	GV.RightMotor.Target_Velcity = Robot_Speed_Base;
+ 802d226:	4b07      	ldr	r3, [pc, #28]	@ (802d244 <Backwards_State_Do+0x38>)
+ 802d228:	ed93 7b00 	vldr	d7, [r3]
+ 802d22c:	eefd 7bc7 	vcvt.s32.f64	s15, d7
+ 802d230:	ee17 2a90 	vmov	r2, s15
+ 802d234:	4b04      	ldr	r3, [pc, #16]	@ (802d248 <Backwards_State_Do+0x3c>)
+ 802d236:	f8c3 20f8 	str.w	r2, [r3, #248]	@ 0xf8
+}
+ 802d23a:	bf00      	nop
+ 802d23c:	46bd      	mov	sp, r7
+ 802d23e:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 802d242:	4770      	bx	lr
+ 802d244:	2400a758 	.word	0x2400a758
+ 802d248:	24000340 	.word	0x24000340
+
+0802d24c <TurnLeft_State_Do>:
+
+
+void TurnLeft_State_Do(void)
+{
+ 802d24c:	b480      	push	{r7}
+ 802d24e:	af00      	add	r7, sp, #0
+	GV.LeftMotor.Target_Velcity  =-Robot_Speed_Base/8;
+ 802d250:	4b11      	ldr	r3, [pc, #68]	@ (802d298 <TurnLeft_State_Do+0x4c>)
+ 802d252:	ed93 7b00 	vldr	d7, [r3]
+ 802d256:	eeb1 6b47 	vneg.f64	d6, d7
+ 802d25a:	eeb2 5b00 	vmov.f64	d5, #32	@ 0x41000000  8.0
+ 802d25e:	ee86 7b05 	vdiv.f64	d7, d6, d5
+ 802d262:	eefd 7bc7 	vcvt.s32.f64	s15, d7
+ 802d266:	ee17 2a90 	vmov	r2, s15
+ 802d26a:	4b0c      	ldr	r3, [pc, #48]	@ (802d29c <TurnLeft_State_Do+0x50>)
+ 802d26c:	679a      	str	r2, [r3, #120]	@ 0x78
+	GV.RightMotor.Target_Velcity =-Robot_Speed_Base/8;
+ 802d26e:	4b0a      	ldr	r3, [pc, #40]	@ (802d298 <TurnLeft_State_Do+0x4c>)
+ 802d270:	ed93 7b00 	vldr	d7, [r3]
+ 802d274:	eeb1 6b47 	vneg.f64	d6, d7
+ 802d278:	eeb2 5b00 	vmov.f64	d5, #32	@ 0x41000000  8.0
+ 802d27c:	ee86 7b05 	vdiv.f64	d7, d6, d5
+ 802d280:	eefd 7bc7 	vcvt.s32.f64	s15, d7
+ 802d284:	ee17 2a90 	vmov	r2, s15
+ 802d288:	4b04      	ldr	r3, [pc, #16]	@ (802d29c <TurnLeft_State_Do+0x50>)
+ 802d28a:	f8c3 20f8 	str.w	r2, [r3, #248]	@ 0xf8
+}
+ 802d28e:	bf00      	nop
+ 802d290:	46bd      	mov	sp, r7
+ 802d292:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 802d296:	4770      	bx	lr
+ 802d298:	2400a758 	.word	0x2400a758
+ 802d29c:	24000340 	.word	0x24000340
+
+0802d2a0 <TurnRight_State_Do>:
+void TurnRight_State_Do(void)
+{
+ 802d2a0:	b480      	push	{r7}
+ 802d2a2:	af00      	add	r7, sp, #0
+	GV.LeftMotor.Target_Velcity  =Robot_Speed_Base/8;
+ 802d2a4:	4b0f      	ldr	r3, [pc, #60]	@ (802d2e4 <TurnRight_State_Do+0x44>)
+ 802d2a6:	ed93 6b00 	vldr	d6, [r3]
+ 802d2aa:	eeb2 5b00 	vmov.f64	d5, #32	@ 0x41000000  8.0
+ 802d2ae:	ee86 7b05 	vdiv.f64	d7, d6, d5
+ 802d2b2:	eefd 7bc7 	vcvt.s32.f64	s15, d7
+ 802d2b6:	ee17 2a90 	vmov	r2, s15
+ 802d2ba:	4b0b      	ldr	r3, [pc, #44]	@ (802d2e8 <TurnRight_State_Do+0x48>)
+ 802d2bc:	679a      	str	r2, [r3, #120]	@ 0x78
+	GV.RightMotor.Target_Velcity =Robot_Speed_Base/8;
+ 802d2be:	4b09      	ldr	r3, [pc, #36]	@ (802d2e4 <TurnRight_State_Do+0x44>)
+ 802d2c0:	ed93 6b00 	vldr	d6, [r3]
+ 802d2c4:	eeb2 5b00 	vmov.f64	d5, #32	@ 0x41000000  8.0
+ 802d2c8:	ee86 7b05 	vdiv.f64	d7, d6, d5
+ 802d2cc:	eefd 7bc7 	vcvt.s32.f64	s15, d7
+ 802d2d0:	ee17 2a90 	vmov	r2, s15
+ 802d2d4:	4b04      	ldr	r3, [pc, #16]	@ (802d2e8 <TurnRight_State_Do+0x48>)
+ 802d2d6:	f8c3 20f8 	str.w	r2, [r3, #248]	@ 0xf8
+}
+ 802d2da:	bf00      	nop
+ 802d2dc:	46bd      	mov	sp, r7
+ 802d2de:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 802d2e2:	4770      	bx	lr
+ 802d2e4:	2400a758 	.word	0x2400a758
+ 802d2e8:	24000340 	.word	0x24000340
+
+0802d2ec <TurnRight_State_Do_Plane>:
+
+void TurnRight_State_Do_Plane(void)
+{
+ 802d2ec:	b480      	push	{r7}
+ 802d2ee:	af00      	add	r7, sp, #0
+	GV.LeftMotor.Target_Velcity  =-Robot_Speed_Base/8;
+ 802d2f0:	4b11      	ldr	r3, [pc, #68]	@ (802d338 <TurnRight_State_Do_Plane+0x4c>)
+ 802d2f2:	ed93 7b00 	vldr	d7, [r3]
+ 802d2f6:	eeb1 6b47 	vneg.f64	d6, d7
+ 802d2fa:	eeb2 5b00 	vmov.f64	d5, #32	@ 0x41000000  8.0
+ 802d2fe:	ee86 7b05 	vdiv.f64	d7, d6, d5
+ 802d302:	eefd 7bc7 	vcvt.s32.f64	s15, d7
+ 802d306:	ee17 2a90 	vmov	r2, s15
+ 802d30a:	4b0c      	ldr	r3, [pc, #48]	@ (802d33c <TurnRight_State_Do_Plane+0x50>)
+ 802d30c:	679a      	str	r2, [r3, #120]	@ 0x78
+	GV.RightMotor.Target_Velcity =-Robot_Speed_Base/8;
+ 802d30e:	4b0a      	ldr	r3, [pc, #40]	@ (802d338 <TurnRight_State_Do_Plane+0x4c>)
+ 802d310:	ed93 7b00 	vldr	d7, [r3]
+ 802d314:	eeb1 6b47 	vneg.f64	d6, d7
+ 802d318:	eeb2 5b00 	vmov.f64	d5, #32	@ 0x41000000  8.0
+ 802d31c:	ee86 7b05 	vdiv.f64	d7, d6, d5
+ 802d320:	eefd 7bc7 	vcvt.s32.f64	s15, d7
+ 802d324:	ee17 2a90 	vmov	r2, s15
+ 802d328:	4b04      	ldr	r3, [pc, #16]	@ (802d33c <TurnRight_State_Do_Plane+0x50>)
+ 802d32a:	f8c3 20f8 	str.w	r2, [r3, #248]	@ 0xf8
+}
+ 802d32e:	bf00      	nop
+ 802d330:	46bd      	mov	sp, r7
+ 802d332:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 802d336:	4770      	bx	lr
+ 802d338:	2400a758 	.word	0x2400a758
+ 802d33c:	24000340 	.word	0x24000340
+
+0802d340 <TurnLeft_State_Do_Plane>:
+
+void TurnLeft_State_Do_Plane(void)
+{
+ 802d340:	b480      	push	{r7}
+ 802d342:	af00      	add	r7, sp, #0
+	GV.LeftMotor.Target_Velcity  =Robot_Speed_Base/8;
+ 802d344:	4b0f      	ldr	r3, [pc, #60]	@ (802d384 <TurnLeft_State_Do_Plane+0x44>)
+ 802d346:	ed93 6b00 	vldr	d6, [r3]
+ 802d34a:	eeb2 5b00 	vmov.f64	d5, #32	@ 0x41000000  8.0
+ 802d34e:	ee86 7b05 	vdiv.f64	d7, d6, d5
+ 802d352:	eefd 7bc7 	vcvt.s32.f64	s15, d7
+ 802d356:	ee17 2a90 	vmov	r2, s15
+ 802d35a:	4b0b      	ldr	r3, [pc, #44]	@ (802d388 <TurnLeft_State_Do_Plane+0x48>)
+ 802d35c:	679a      	str	r2, [r3, #120]	@ 0x78
+	GV.RightMotor.Target_Velcity =Robot_Speed_Base/8;
+ 802d35e:	4b09      	ldr	r3, [pc, #36]	@ (802d384 <TurnLeft_State_Do_Plane+0x44>)
+ 802d360:	ed93 6b00 	vldr	d6, [r3]
+ 802d364:	eeb2 5b00 	vmov.f64	d5, #32	@ 0x41000000  8.0
+ 802d368:	ee86 7b05 	vdiv.f64	d7, d6, d5
+ 802d36c:	eefd 7bc7 	vcvt.s32.f64	s15, d7
+ 802d370:	ee17 2a90 	vmov	r2, s15
+ 802d374:	4b04      	ldr	r3, [pc, #16]	@ (802d388 <TurnLeft_State_Do_Plane+0x48>)
+ 802d376:	f8c3 20f8 	str.w	r2, [r3, #248]	@ 0xf8
+}
+ 802d37a:	bf00      	nop
+ 802d37c:	46bd      	mov	sp, r7
+ 802d37e:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 802d382:	4770      	bx	lr
+ 802d384:	2400a758 	.word	0x2400a758
+ 802d388:	24000340 	.word	0x24000340
+
+0802d38c <Move_Swing_Left_Func_Do>:
+
+int Left_Limtit_Position=95*TT_One_Deg_Count;
+int Right_Limtit_Position=-95*TT_One_Deg_Count;
+
+void Move_Swing_Left_Func_Do(void)
+{
+ 802d38c:	b480      	push	{r7}
+ 802d38e:	af00      	add	r7, sp, #0
+	GV.SwingMotor.Position_immediately1_Lag2=1;
+ 802d390:	4b0f      	ldr	r3, [pc, #60]	@ (802d3d0 <Move_Swing_Left_Func_Do+0x44>)
+ 802d392:	2201      	movs	r2, #1
+ 802d394:	f8c3 21d4 	str.w	r2, [r3, #468]	@ 0x1d4
+	GV.SwingMotor.Tar_Position_count=Left_Limtit_Position;
+ 802d398:	4b0e      	ldr	r3, [pc, #56]	@ (802d3d4 <Move_Swing_Left_Func_Do+0x48>)
+ 802d39a:	681b      	ldr	r3, [r3, #0]
+ 802d39c:	4a0c      	ldr	r2, [pc, #48]	@ (802d3d0 <Move_Swing_Left_Func_Do+0x44>)
+ 802d39e:	f8c2 31d8 	str.w	r3, [r2, #472]	@ 0x1d8
+	GV.SwingMotor.Tar_Position_Velcity_RPM=GV_Swing_Speed*Swing_Speed_Deg_Sencond;
+ 802d3a2:	4b0d      	ldr	r3, [pc, #52]	@ (802d3d8 <Move_Swing_Left_Func_Do+0x4c>)
+ 802d3a4:	681b      	ldr	r3, [r3, #0]
+ 802d3a6:	ee07 3a90 	vmov	s15, r3
+ 802d3aa:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802d3ae:	4b0b      	ldr	r3, [pc, #44]	@ (802d3dc <Move_Swing_Left_Func_Do+0x50>)
+ 802d3b0:	ed93 7b00 	vldr	d7, [r3]
+ 802d3b4:	ee26 7b07 	vmul.f64	d7, d6, d7
+ 802d3b8:	eefd 7bc7 	vcvt.s32.f64	s15, d7
+ 802d3bc:	ee17 2a90 	vmov	r2, s15
+ 802d3c0:	4b03      	ldr	r3, [pc, #12]	@ (802d3d0 <Move_Swing_Left_Func_Do+0x44>)
+ 802d3c2:	f8c3 21dc 	str.w	r2, [r3, #476]	@ 0x1dc
+//	GV.SwingMotor.Target_Velcity = GV_Swing_Speed*Swing_Speed_Deg_Sencond;
+}
+ 802d3c6:	bf00      	nop
+ 802d3c8:	46bd      	mov	sp, r7
+ 802d3ca:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 802d3ce:	4770      	bx	lr
+ 802d3d0:	24000340 	.word	0x24000340
+ 802d3d4:	24000100 	.word	0x24000100
+ 802d3d8:	2400a710 	.word	0x2400a710
+ 802d3dc:	240000a8 	.word	0x240000a8
+
+0802d3e0 <Move_Swing_Right_Func_Do>:
+
+void Move_Swing_Right_Func_Do(void)
+{
+ 802d3e0:	b480      	push	{r7}
+ 802d3e2:	af00      	add	r7, sp, #0
+	GV.SwingMotor.Position_immediately1_Lag2=1;
+ 802d3e4:	4b0f      	ldr	r3, [pc, #60]	@ (802d424 <Move_Swing_Right_Func_Do+0x44>)
+ 802d3e6:	2201      	movs	r2, #1
+ 802d3e8:	f8c3 21d4 	str.w	r2, [r3, #468]	@ 0x1d4
+	GV.SwingMotor.Tar_Position_count=Right_Limtit_Position;
+ 802d3ec:	4b0e      	ldr	r3, [pc, #56]	@ (802d428 <Move_Swing_Right_Func_Do+0x48>)
+ 802d3ee:	681b      	ldr	r3, [r3, #0]
+ 802d3f0:	4a0c      	ldr	r2, [pc, #48]	@ (802d424 <Move_Swing_Right_Func_Do+0x44>)
+ 802d3f2:	f8c2 31d8 	str.w	r3, [r2, #472]	@ 0x1d8
+	GV.SwingMotor.Tar_Position_Velcity_RPM=GV_Swing_Speed*Swing_Speed_Deg_Sencond;
+ 802d3f6:	4b0d      	ldr	r3, [pc, #52]	@ (802d42c <Move_Swing_Right_Func_Do+0x4c>)
+ 802d3f8:	681b      	ldr	r3, [r3, #0]
+ 802d3fa:	ee07 3a90 	vmov	s15, r3
+ 802d3fe:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802d402:	4b0b      	ldr	r3, [pc, #44]	@ (802d430 <Move_Swing_Right_Func_Do+0x50>)
+ 802d404:	ed93 7b00 	vldr	d7, [r3]
+ 802d408:	ee26 7b07 	vmul.f64	d7, d6, d7
+ 802d40c:	eefd 7bc7 	vcvt.s32.f64	s15, d7
+ 802d410:	ee17 2a90 	vmov	r2, s15
+ 802d414:	4b03      	ldr	r3, [pc, #12]	@ (802d424 <Move_Swing_Right_Func_Do+0x44>)
+ 802d416:	f8c3 21dc 	str.w	r2, [r3, #476]	@ 0x1dc
+
+//	GV.SwingMotor.Target_Velcity =-GV_Swing_Speed*Swing_Speed_Deg_Sencond;
+}
+ 802d41a:	bf00      	nop
+ 802d41c:	46bd      	mov	sp, r7
+ 802d41e:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 802d422:	4770      	bx	lr
+ 802d424:	24000340 	.word	0x24000340
+ 802d428:	24000104 	.word	0x24000104
+ 802d42c:	2400a710 	.word	0x2400a710
+ 802d430:	240000a8 	.word	0x240000a8
+
+0802d434 <Move_Swing_Halt_Func_Do>:
+
+void Move_Swing_Halt_Func_Do(void)
+{
+ 802d434:	b480      	push	{r7}
+ 802d436:	af00      	add	r7, sp, #0
+	GV.SwingMotor.Position_immediately1_Lag2=1;
+ 802d438:	4b08      	ldr	r3, [pc, #32]	@ (802d45c <Move_Swing_Halt_Func_Do+0x28>)
+ 802d43a:	2201      	movs	r2, #1
+ 802d43c:	f8c3 21d4 	str.w	r2, [r3, #468]	@ 0x1d4
+	GV.SwingMotor.Tar_Position_count=0;
+ 802d440:	4b06      	ldr	r3, [pc, #24]	@ (802d45c <Move_Swing_Halt_Func_Do+0x28>)
+ 802d442:	2200      	movs	r2, #0
+ 802d444:	f8c3 21d8 	str.w	r2, [r3, #472]	@ 0x1d8
+	GV.SwingMotor.Tar_Position_Velcity_RPM=0;
+ 802d448:	4b04      	ldr	r3, [pc, #16]	@ (802d45c <Move_Swing_Halt_Func_Do+0x28>)
+ 802d44a:	2200      	movs	r2, #0
+ 802d44c:	f8c3 21dc 	str.w	r2, [r3, #476]	@ 0x1dc
+
+//	GV.SwingMotor.Target_Velcity = 0;
+}
+ 802d450:	bf00      	nop
+ 802d452:	46bd      	mov	sp, r7
+ 802d454:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 802d458:	4770      	bx	lr
+ 802d45a:	bf00      	nop
+ 802d45c:	24000340 	.word	0x24000340
+
+0802d460 <Plane_Change_Road_Back_Time_Countinus>:
+	//	double Change_Road_Speed_MAX=201.7*7.64*3*1.5;//换道最高速度设定为4.5米每分钟
+	Plane_Change_Road_Time=((double)GV_Robot_Change_Lane_Distance)*0.01/3*60*500;//一米的时候超出12cm
+}
+
+void Plane_Change_Road_Back_Time_Countinus()
+{
+ 802d460:	b480      	push	{r7}
+ 802d462:	af00      	add	r7, sp, #0
+	//	double Change_Road_Speed=201.7*7.64*3;//换道速度设定为3米每分钟
+	//	double Change_Road_Speed_MAX=201.7*7.64*3*1.5;//换道最高速度设定为4.5米每分钟
+	Plane_Change_Road_Time=((double)GV_Robot_Change_Lane_Distance)*0.01/GV_Robot_Back_Speed*60*500;//一米的时候超出12cm
+ 802d464:	4b14      	ldr	r3, [pc, #80]	@ (802d4b8 <Plane_Change_Road_Back_Time_Countinus+0x58>)
+ 802d466:	ed93 7b00 	vldr	d7, [r3]
+ 802d46a:	ed9f 6b0d 	vldr	d6, [pc, #52]	@ 802d4a0 <Plane_Change_Road_Back_Time_Countinus+0x40>
+ 802d46e:	ee27 5b06 	vmul.f64	d5, d7, d6
+ 802d472:	4b12      	ldr	r3, [pc, #72]	@ (802d4bc <Plane_Change_Road_Back_Time_Countinus+0x5c>)
+ 802d474:	ed93 6b00 	vldr	d6, [r3]
+ 802d478:	ee85 7b06 	vdiv.f64	d7, d5, d6
+ 802d47c:	ed9f 6b0a 	vldr	d6, [pc, #40]	@ 802d4a8 <Plane_Change_Road_Back_Time_Countinus+0x48>
+ 802d480:	ee27 7b06 	vmul.f64	d7, d7, d6
+ 802d484:	ed9f 6b0a 	vldr	d6, [pc, #40]	@ 802d4b0 <Plane_Change_Road_Back_Time_Countinus+0x50>
+ 802d488:	ee27 7b06 	vmul.f64	d7, d7, d6
+ 802d48c:	4b0c      	ldr	r3, [pc, #48]	@ (802d4c0 <Plane_Change_Road_Back_Time_Countinus+0x60>)
+ 802d48e:	ed83 7b00 	vstr	d7, [r3]
+}
+ 802d492:	bf00      	nop
+ 802d494:	46bd      	mov	sp, r7
+ 802d496:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 802d49a:	4770      	bx	lr
+ 802d49c:	f3af 8000 	nop.w
+ 802d4a0:	47ae147b 	.word	0x47ae147b
+ 802d4a4:	3f847ae1 	.word	0x3f847ae1
+ 802d4a8:	00000000 	.word	0x00000000
+ 802d4ac:	404e0000 	.word	0x404e0000
+ 802d4b0:	00000000 	.word	0x00000000
+ 802d4b4:	407f4000 	.word	0x407f4000
+ 802d4b8:	2400a708 	.word	0x2400a708
+ 802d4bc:	2400a730 	.word	0x2400a730
+ 802d4c0:	240000c8 	.word	0x240000c8
+ 802d4c4:	00000000 	.word	0x00000000
+
+0802d4c8 <Horizontal_Change_Road_Back_Time_Compute>:
+
+
+
+
+void Horizontal_Change_Road_Back_Time_Compute()
+{
+ 802d4c8:	b480      	push	{r7}
+ 802d4ca:	b083      	sub	sp, #12
+ 802d4cc:	af00      	add	r7, sp, #0
+	//	double Change_Road_Speed=201.7*7.64*3;//换道速度设定为3米每分钟
+	//	double Change_Road_Speed_MAX=201.7*7.64*3*1.5;//换道最高速度设定为4.5米每分钟
+	double GV_Robot_Change_Lane_Distance_Updata;
+	if(GV_Robot_Change_Lane_Distance>20)
+ 802d4ce:	4b26      	ldr	r3, [pc, #152]	@ (802d568 <Horizontal_Change_Road_Back_Time_Compute+0xa0>)
+ 802d4d0:	ed93 7b00 	vldr	d7, [r3]
+ 802d4d4:	eeb3 6b04 	vmov.f64	d6, #52	@ 0x41a00000  20.0
+ 802d4d8:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 802d4dc:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802d4e0:	dd0d      	ble.n	802d4fe <Horizontal_Change_Road_Back_Time_Compute+0x36>
+	{
+		GV_Robot_Change_Lane_Distance_Updata=(GV_Robot_Change_Lane_Distance-1.7)/1.046;
+ 802d4e2:	4b21      	ldr	r3, [pc, #132]	@ (802d568 <Horizontal_Change_Road_Back_Time_Compute+0xa0>)
+ 802d4e4:	ed93 7b00 	vldr	d7, [r3]
+ 802d4e8:	ed9f 6b15 	vldr	d6, [pc, #84]	@ 802d540 <Horizontal_Change_Road_Back_Time_Compute+0x78>
+ 802d4ec:	ee37 6b46 	vsub.f64	d6, d7, d6
+ 802d4f0:	ed9f 5b15 	vldr	d5, [pc, #84]	@ 802d548 <Horizontal_Change_Road_Back_Time_Compute+0x80>
+ 802d4f4:	ee86 7b05 	vdiv.f64	d7, d6, d5
+ 802d4f8:	ed87 7b00 	vstr	d7, [r7]
+ 802d4fc:	e004      	b.n	802d508 <Horizontal_Change_Road_Back_Time_Compute+0x40>
+	}
+	else
+	{
+		GV_Robot_Change_Lane_Distance_Updata=GV_Robot_Change_Lane_Distance;
+ 802d4fe:	4b1a      	ldr	r3, [pc, #104]	@ (802d568 <Horizontal_Change_Road_Back_Time_Compute+0xa0>)
+ 802d500:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802d504:	e9c7 2300 	strd	r2, r3, [r7]
+	}
+	Horizontal_Change_Road_Time=((double)GV_Robot_Change_Lane_Distance_Updata)*0.01/3*60*500;//一米的时候超出12cm
+ 802d508:	ed97 7b00 	vldr	d7, [r7]
+ 802d50c:	ed9f 6b10 	vldr	d6, [pc, #64]	@ 802d550 <Horizontal_Change_Road_Back_Time_Compute+0x88>
+ 802d510:	ee27 6b06 	vmul.f64	d6, d7, d6
+ 802d514:	eeb0 5b08 	vmov.f64	d5, #8	@ 0x40400000  3.0
+ 802d518:	ee86 7b05 	vdiv.f64	d7, d6, d5
+ 802d51c:	ed9f 6b0e 	vldr	d6, [pc, #56]	@ 802d558 <Horizontal_Change_Road_Back_Time_Compute+0x90>
+ 802d520:	ee27 7b06 	vmul.f64	d7, d7, d6
+ 802d524:	ed9f 6b0e 	vldr	d6, [pc, #56]	@ 802d560 <Horizontal_Change_Road_Back_Time_Compute+0x98>
+ 802d528:	ee27 7b06 	vmul.f64	d7, d7, d6
+ 802d52c:	4b0f      	ldr	r3, [pc, #60]	@ (802d56c <Horizontal_Change_Road_Back_Time_Compute+0xa4>)
+ 802d52e:	ed83 7b00 	vstr	d7, [r3]
+}
+ 802d532:	bf00      	nop
+ 802d534:	370c      	adds	r7, #12
+ 802d536:	46bd      	mov	sp, r7
+ 802d538:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 802d53c:	4770      	bx	lr
+ 802d53e:	bf00      	nop
+ 802d540:	33333333 	.word	0x33333333
+ 802d544:	3ffb3333 	.word	0x3ffb3333
+ 802d548:	7ef9db23 	.word	0x7ef9db23
+ 802d54c:	3ff0bc6a 	.word	0x3ff0bc6a
+ 802d550:	47ae147b 	.word	0x47ae147b
+ 802d554:	3f847ae1 	.word	0x3f847ae1
+ 802d558:	00000000 	.word	0x00000000
+ 802d55c:	404e0000 	.word	0x404e0000
+ 802d560:	00000000 	.word	0x00000000
+ 802d564:	407f4000 	.word	0x407f4000
+ 802d568:	2400a708 	.word	0x2400a708
+ 802d56c:	240000c0 	.word	0x240000c0
+
+0802d570 <Vertical_Change_Road_Back_Time_Compute>:
+
+void Vertical_Change_Road_Back_Time_Compute()
+{
+ 802d570:	b480      	push	{r7}
+ 802d572:	af00      	add	r7, sp, #0
+
+	Vertical_Change_Road_Time=((double)GV_Robot_Change_Lane_Distance)*0.01/3*60*500;//一米的时候超出12cm
+ 802d574:	4b14      	ldr	r3, [pc, #80]	@ (802d5c8 <Vertical_Change_Road_Back_Time_Compute+0x58>)
+ 802d576:	ed93 7b00 	vldr	d7, [r3]
+ 802d57a:	ed9f 6b0d 	vldr	d6, [pc, #52]	@ 802d5b0 <Vertical_Change_Road_Back_Time_Compute+0x40>
+ 802d57e:	ee27 6b06 	vmul.f64	d6, d7, d6
+ 802d582:	eeb0 5b08 	vmov.f64	d5, #8	@ 0x40400000  3.0
+ 802d586:	ee86 7b05 	vdiv.f64	d7, d6, d5
+ 802d58a:	ed9f 6b0b 	vldr	d6, [pc, #44]	@ 802d5b8 <Vertical_Change_Road_Back_Time_Compute+0x48>
+ 802d58e:	ee27 7b06 	vmul.f64	d7, d7, d6
+ 802d592:	ed9f 6b0b 	vldr	d6, [pc, #44]	@ 802d5c0 <Vertical_Change_Road_Back_Time_Compute+0x50>
+ 802d596:	ee27 7b06 	vmul.f64	d7, d7, d6
+ 802d59a:	4b0c      	ldr	r3, [pc, #48]	@ (802d5cc <Vertical_Change_Road_Back_Time_Compute+0x5c>)
+ 802d59c:	ed83 7b00 	vstr	d7, [r3]
+}
+ 802d5a0:	bf00      	nop
+ 802d5a2:	46bd      	mov	sp, r7
+ 802d5a4:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 802d5a8:	4770      	bx	lr
+ 802d5aa:	bf00      	nop
+ 802d5ac:	f3af 8000 	nop.w
+ 802d5b0:	47ae147b 	.word	0x47ae147b
+ 802d5b4:	3f847ae1 	.word	0x3f847ae1
+ 802d5b8:	00000000 	.word	0x00000000
+ 802d5bc:	404e0000 	.word	0x404e0000
+ 802d5c0:	00000000 	.word	0x00000000
+ 802d5c4:	407f4000 	.word	0x407f4000
+ 802d5c8:	2400a708 	.word	0x2400a708
+ 802d5cc:	240000b8 	.word	0x240000b8
+
+0802d5d0 <Fight_Alternately_Function_Horizontal>:
+
+
+
+//打一道退一次
+void Fight_Alternately_Function_Horizontal()
+{
+ 802d5d0:	b580      	push	{r7, lr}
+ 802d5d2:	af00      	add	r7, sp, #0
+	Swing_Limit_Contrl();//摆臂限位控制
+ 802d5d4:	f000 f840 	bl	802d658 <Swing_Limit_Contrl>
+	Robot_Platform_Back_Contronl_Horizontal();
+ 802d5d8:	f000 fa52 	bl	802da80 <Robot_Platform_Back_Contronl_Horizontal>
+}
+ 802d5dc:	bf00      	nop
+ 802d5de:	bd80      	pop	{r7, pc}
+
+0802d5e0 <Fight_Countinus_Function_Horizontal>:
+//打退连续
+void Fight_Countinus_Function_Horizontal()
+{
+ 802d5e0:	b580      	push	{r7, lr}
+ 802d5e2:	af00      	add	r7, sp, #0
+	Swing_Limit_Contrl();//摆臂限位控制
+ 802d5e4:	f000 f838 	bl	802d658 <Swing_Limit_Contrl>
+	Move_Horizontal_Vertical_Task_Backwards_Do_Backward(Robot_Countinus_Speed,CV_Robot_Deri_Angle_Deg_Grity);
+ 802d5e8:	4b06      	ldr	r3, [pc, #24]	@ (802d604 <Fight_Countinus_Function_Horizontal+0x24>)
+ 802d5ea:	ed93 7b00 	vldr	d7, [r3]
+ 802d5ee:	4b06      	ldr	r3, [pc, #24]	@ (802d608 <Fight_Countinus_Function_Horizontal+0x28>)
+ 802d5f0:	ed93 6b00 	vldr	d6, [r3]
+ 802d5f4:	eeb0 1b46 	vmov.f64	d1, d6
+ 802d5f8:	eeb0 0b47 	vmov.f64	d0, d7
+ 802d5fc:	f7ff f9d8 	bl	802c9b0 <Move_Horizontal_Vertical_Task_Backwards_Do_Backward>
+}
+ 802d600:	bf00      	nop
+ 802d602:	bd80      	pop	{r7, pc}
+ 802d604:	2400a760 	.word	0x2400a760
+ 802d608:	2400a6d0 	.word	0x2400a6d0
+
+0802d60c <Fight_Alternately_Function_Vertical>:
+
+//打一道退一次
+void Fight_Alternately_Function_Vertical()
+{
+ 802d60c:	b580      	push	{r7, lr}
+ 802d60e:	af00      	add	r7, sp, #0
+	Swing_Limit_Contrl();//摆臂限位控制
+ 802d610:	f000 f822 	bl	802d658 <Swing_Limit_Contrl>
+	Robot_Platform_Back_Contronl_Vertical();
+ 802d614:	f000 fb34 	bl	802dc80 <Robot_Platform_Back_Contronl_Vertical>
+}
+ 802d618:	bf00      	nop
+ 802d61a:	bd80      	pop	{r7, pc}
+
+0802d61c <Fight_Alternately_Function_Plane>:
+void Fight_Alternately_Function_Plane()
+{
+ 802d61c:	b580      	push	{r7, lr}
+ 802d61e:	af00      	add	r7, sp, #0
+	Swing_Limit_Contrl();//摆臂限位控制
+ 802d620:	f000 f81a 	bl	802d658 <Swing_Limit_Contrl>
+	Robot_Platform_Back_Contronl_Plane();
+ 802d624:	f000 fc10 	bl	802de48 <Robot_Platform_Back_Contronl_Plane>
+}
+ 802d628:	bf00      	nop
+ 802d62a:	bd80      	pop	{r7, pc}
+
+0802d62c <Fight_Countinus_Function_Plane>:
+void Fight_Countinus_Function_Plane()
+{
+ 802d62c:	b580      	push	{r7, lr}
+ 802d62e:	af00      	add	r7, sp, #0
+	Swing_Limit_Contrl();//摆臂限位控制
+ 802d630:	f000 f812 	bl	802d658 <Swing_Limit_Contrl>
+//	Move_Plane_Task_Backwards_Distance_Do_Update(Robot_Countinus_Speed, CV_Robot_Deri_Angle_Deg_Plane);
+	Move_Plane_Task_Backwards_Distance_Do_Update_Turn(Robot_Countinus_Speed, CV_Robot_Deri_Angle_Deg_Plane);
+ 802d634:	4b06      	ldr	r3, [pc, #24]	@ (802d650 <Fight_Countinus_Function_Plane+0x24>)
+ 802d636:	ed93 7b00 	vldr	d7, [r3]
+ 802d63a:	4b06      	ldr	r3, [pc, #24]	@ (802d654 <Fight_Countinus_Function_Plane+0x28>)
+ 802d63c:	ed93 6b00 	vldr	d6, [r3]
+ 802d640:	eeb0 1b46 	vmov.f64	d1, d6
+ 802d644:	eeb0 0b47 	vmov.f64	d0, d7
+ 802d648:	f7ff fa50 	bl	802caec <Move_Plane_Task_Backwards_Distance_Do_Update_Turn>
+}
+ 802d64c:	bf00      	nop
+ 802d64e:	bd80      	pop	{r7, pc}
+ 802d650:	2400a760 	.word	0x2400a760
+ 802d654:	2400a6d8 	.word	0x2400a6d8
+
+0802d658 <Swing_Limit_Contrl>:
+double Horizontal_Back_Speed_Value=0;
+double Vertical_Back_Speed_Value=0;
+double Plane_Back_Speed_Value=0;
+
+void Swing_Limit_Contrl()
+{
+ 802d658:	b580      	push	{r7, lr}
+ 802d65a:	af00      	add	r7, sp, #0
+//Case 1  向左摆臂
+	switch(Swing_Limit_Flag)
+ 802d65c:	4bb8      	ldr	r3, [pc, #736]	@ (802d940 <Swing_Limit_Contrl+0x2e8>)
+ 802d65e:	681b      	ldr	r3, [r3, #0]
+ 802d660:	2b04      	cmp	r3, #4
+ 802d662:	f200 815d 	bhi.w	802d920 <Swing_Limit_Contrl+0x2c8>
+ 802d666:	a201      	add	r2, pc, #4	@ (adr r2, 802d66c <Swing_Limit_Contrl+0x14>)
+ 802d668:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 802d66c:	0802d681 	.word	0x0802d681
+ 802d670:	0802d6ed 	.word	0x0802d6ed
+ 802d674:	0802d76b 	.word	0x0802d76b
+ 802d678:	0802d7e9 	.word	0x0802d7e9
+ 802d67c:	0802d887 	.word	0x0802d887
+	{
+		case 0:
+			Back_Para_Compute();
+ 802d680:	f000 f96e 	bl	802d960 <Back_Para_Compute>
+			Left_Threshold_Pos==1;
+			if(GV.SwingMotor.Real_Position>=Left_Target_Pos-25000)
+ 802d684:	4baf      	ldr	r3, [pc, #700]	@ (802d944 <Swing_Limit_Contrl+0x2ec>)
+ 802d686:	f8d3 319c 	ldr.w	r3, [r3, #412]	@ 0x19c
+ 802d68a:	ee07 3a90 	vmov	s15, r3
+ 802d68e:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802d692:	4bad      	ldr	r3, [pc, #692]	@ (802d948 <Swing_Limit_Contrl+0x2f0>)
+ 802d694:	ed93 7b00 	vldr	d7, [r3]
+ 802d698:	ed9f 5ba3 	vldr	d5, [pc, #652]	@ 802d928 <Swing_Limit_Contrl+0x2d0>
+ 802d69c:	ee37 7b45 	vsub.f64	d7, d7, d5
+ 802d6a0:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802d6a4:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802d6a8:	db03      	blt.n	802d6b2 <Swing_Limit_Contrl+0x5a>
+			{
+				Swing_Limit_Flag=2;
+ 802d6aa:	4ba5      	ldr	r3, [pc, #660]	@ (802d940 <Swing_Limit_Contrl+0x2e8>)
+ 802d6ac:	2202      	movs	r2, #2
+ 802d6ae:	601a      	str	r2, [r3, #0]
+			else
+			{
+				Swing_Limit_Flag++;
+			}
+
+			break;
+ 802d6b0:	e136      	b.n	802d920 <Swing_Limit_Contrl+0x2c8>
+			else if(GV.SwingMotor.Real_Position<=Right_Target_Pos+25000)
+ 802d6b2:	4ba4      	ldr	r3, [pc, #656]	@ (802d944 <Swing_Limit_Contrl+0x2ec>)
+ 802d6b4:	f8d3 319c 	ldr.w	r3, [r3, #412]	@ 0x19c
+ 802d6b8:	ee07 3a90 	vmov	s15, r3
+ 802d6bc:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802d6c0:	4ba2      	ldr	r3, [pc, #648]	@ (802d94c <Swing_Limit_Contrl+0x2f4>)
+ 802d6c2:	ed93 7b00 	vldr	d7, [r3]
+ 802d6c6:	ed9f 5b98 	vldr	d5, [pc, #608]	@ 802d928 <Swing_Limit_Contrl+0x2d0>
+ 802d6ca:	ee37 7b05 	vadd.f64	d7, d7, d5
+ 802d6ce:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802d6d2:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802d6d6:	d803      	bhi.n	802d6e0 <Swing_Limit_Contrl+0x88>
+				Swing_Limit_Flag=1;
+ 802d6d8:	4b99      	ldr	r3, [pc, #612]	@ (802d940 <Swing_Limit_Contrl+0x2e8>)
+ 802d6da:	2201      	movs	r2, #1
+ 802d6dc:	601a      	str	r2, [r3, #0]
+			break;
+ 802d6de:	e11f      	b.n	802d920 <Swing_Limit_Contrl+0x2c8>
+				Swing_Limit_Flag++;
+ 802d6e0:	4b97      	ldr	r3, [pc, #604]	@ (802d940 <Swing_Limit_Contrl+0x2e8>)
+ 802d6e2:	681b      	ldr	r3, [r3, #0]
+ 802d6e4:	3301      	adds	r3, #1
+ 802d6e6:	4a96      	ldr	r2, [pc, #600]	@ (802d940 <Swing_Limit_Contrl+0x2e8>)
+ 802d6e8:	6013      	str	r3, [r2, #0]
+			break;
+ 802d6ea:	e119      	b.n	802d920 <Swing_Limit_Contrl+0x2c8>
+		case 1://向左到限位；
+			Swing_Time_Count++;
+ 802d6ec:	4b98      	ldr	r3, [pc, #608]	@ (802d950 <Swing_Limit_Contrl+0x2f8>)
+ 802d6ee:	681b      	ldr	r3, [r3, #0]
+ 802d6f0:	3301      	adds	r3, #1
+ 802d6f2:	4a97      	ldr	r2, [pc, #604]	@ (802d950 <Swing_Limit_Contrl+0x2f8>)
+ 802d6f4:	6013      	str	r3, [r2, #0]
+			GV.SwingMotor.Position_immediately1_Lag2=1;
+ 802d6f6:	4b93      	ldr	r3, [pc, #588]	@ (802d944 <Swing_Limit_Contrl+0x2ec>)
+ 802d6f8:	2201      	movs	r2, #1
+ 802d6fa:	f8c3 21d4 	str.w	r2, [r3, #468]	@ 0x1d4
+			GV.SwingMotor.Tar_Position_count=Left_Target_Pos;
+ 802d6fe:	4b92      	ldr	r3, [pc, #584]	@ (802d948 <Swing_Limit_Contrl+0x2f0>)
+ 802d700:	ed93 7b00 	vldr	d7, [r3]
+ 802d704:	eefd 7bc7 	vcvt.s32.f64	s15, d7
+ 802d708:	ee17 2a90 	vmov	r2, s15
+ 802d70c:	4b8d      	ldr	r3, [pc, #564]	@ (802d944 <Swing_Limit_Contrl+0x2ec>)
+ 802d70e:	f8c3 21d8 	str.w	r2, [r3, #472]	@ 0x1d8
+			GV.SwingMotor.Tar_Position_Velcity_RPM=((double)GV_Swing_Speed)*201.7;
+ 802d712:	4b90      	ldr	r3, [pc, #576]	@ (802d954 <Swing_Limit_Contrl+0x2fc>)
+ 802d714:	681b      	ldr	r3, [r3, #0]
+ 802d716:	ee07 3a90 	vmov	s15, r3
+ 802d71a:	eeb8 7be7 	vcvt.f64.s32	d7, s15
+ 802d71e:	ed9f 6b84 	vldr	d6, [pc, #528]	@ 802d930 <Swing_Limit_Contrl+0x2d8>
+ 802d722:	ee27 7b06 	vmul.f64	d7, d7, d6
+ 802d726:	eefd 7bc7 	vcvt.s32.f64	s15, d7
+ 802d72a:	ee17 2a90 	vmov	r2, s15
+ 802d72e:	4b85      	ldr	r3, [pc, #532]	@ (802d944 <Swing_Limit_Contrl+0x2ec>)
+ 802d730:	f8c3 21dc 	str.w	r2, [r3, #476]	@ 0x1dc
+			if(GV.SwingMotor.Real_Position>Left_Target_Pos-25000)
+ 802d734:	4b83      	ldr	r3, [pc, #524]	@ (802d944 <Swing_Limit_Contrl+0x2ec>)
+ 802d736:	f8d3 319c 	ldr.w	r3, [r3, #412]	@ 0x19c
+ 802d73a:	ee07 3a90 	vmov	s15, r3
+ 802d73e:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802d742:	4b81      	ldr	r3, [pc, #516]	@ (802d948 <Swing_Limit_Contrl+0x2f0>)
+ 802d744:	ed93 7b00 	vldr	d7, [r3]
+ 802d748:	ed9f 5b77 	vldr	d5, [pc, #476]	@ 802d928 <Swing_Limit_Contrl+0x2d0>
+ 802d74c:	ee37 7b45 	vsub.f64	d7, d7, d5
+ 802d750:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802d754:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802d758:	dc00      	bgt.n	802d75c <Swing_Limit_Contrl+0x104>
+			{
+				Swing_Limit_Flag=3;
+				Swing_Time_Count=0;
+			}
+			break;
+ 802d75a:	e0e1      	b.n	802d920 <Swing_Limit_Contrl+0x2c8>
+				Swing_Limit_Flag=3;
+ 802d75c:	4b78      	ldr	r3, [pc, #480]	@ (802d940 <Swing_Limit_Contrl+0x2e8>)
+ 802d75e:	2203      	movs	r2, #3
+ 802d760:	601a      	str	r2, [r3, #0]
+				Swing_Time_Count=0;
+ 802d762:	4b7b      	ldr	r3, [pc, #492]	@ (802d950 <Swing_Limit_Contrl+0x2f8>)
+ 802d764:	2200      	movs	r2, #0
+ 802d766:	601a      	str	r2, [r3, #0]
+			break;
+ 802d768:	e0da      	b.n	802d920 <Swing_Limit_Contrl+0x2c8>
+		case 2:
+			Swing_Time_Count++;
+ 802d76a:	4b79      	ldr	r3, [pc, #484]	@ (802d950 <Swing_Limit_Contrl+0x2f8>)
+ 802d76c:	681b      	ldr	r3, [r3, #0]
+ 802d76e:	3301      	adds	r3, #1
+ 802d770:	4a77      	ldr	r2, [pc, #476]	@ (802d950 <Swing_Limit_Contrl+0x2f8>)
+ 802d772:	6013      	str	r3, [r2, #0]
+			GV.SwingMotor.Position_immediately1_Lag2=1;
+ 802d774:	4b73      	ldr	r3, [pc, #460]	@ (802d944 <Swing_Limit_Contrl+0x2ec>)
+ 802d776:	2201      	movs	r2, #1
+ 802d778:	f8c3 21d4 	str.w	r2, [r3, #468]	@ 0x1d4
+			GV.SwingMotor.Tar_Position_count=Right_Target_Pos;
+ 802d77c:	4b73      	ldr	r3, [pc, #460]	@ (802d94c <Swing_Limit_Contrl+0x2f4>)
+ 802d77e:	ed93 7b00 	vldr	d7, [r3]
+ 802d782:	eefd 7bc7 	vcvt.s32.f64	s15, d7
+ 802d786:	ee17 2a90 	vmov	r2, s15
+ 802d78a:	4b6e      	ldr	r3, [pc, #440]	@ (802d944 <Swing_Limit_Contrl+0x2ec>)
+ 802d78c:	f8c3 21d8 	str.w	r2, [r3, #472]	@ 0x1d8
+			GV.SwingMotor.Tar_Position_Velcity_RPM=((double)GV_Swing_Speed)*201.7;
+ 802d790:	4b70      	ldr	r3, [pc, #448]	@ (802d954 <Swing_Limit_Contrl+0x2fc>)
+ 802d792:	681b      	ldr	r3, [r3, #0]
+ 802d794:	ee07 3a90 	vmov	s15, r3
+ 802d798:	eeb8 7be7 	vcvt.f64.s32	d7, s15
+ 802d79c:	ed9f 6b64 	vldr	d6, [pc, #400]	@ 802d930 <Swing_Limit_Contrl+0x2d8>
+ 802d7a0:	ee27 7b06 	vmul.f64	d7, d7, d6
+ 802d7a4:	eefd 7bc7 	vcvt.s32.f64	s15, d7
+ 802d7a8:	ee17 2a90 	vmov	r2, s15
+ 802d7ac:	4b65      	ldr	r3, [pc, #404]	@ (802d944 <Swing_Limit_Contrl+0x2ec>)
+ 802d7ae:	f8c3 21dc 	str.w	r2, [r3, #476]	@ 0x1dc
+			if(GV.SwingMotor.Real_Position<Right_Target_Pos+25000)
+ 802d7b2:	4b64      	ldr	r3, [pc, #400]	@ (802d944 <Swing_Limit_Contrl+0x2ec>)
+ 802d7b4:	f8d3 319c 	ldr.w	r3, [r3, #412]	@ 0x19c
+ 802d7b8:	ee07 3a90 	vmov	s15, r3
+ 802d7bc:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802d7c0:	4b62      	ldr	r3, [pc, #392]	@ (802d94c <Swing_Limit_Contrl+0x2f4>)
+ 802d7c2:	ed93 7b00 	vldr	d7, [r3]
+ 802d7c6:	ed9f 5b58 	vldr	d5, [pc, #352]	@ 802d928 <Swing_Limit_Contrl+0x2d0>
+ 802d7ca:	ee37 7b05 	vadd.f64	d7, d7, d5
+ 802d7ce:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802d7d2:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802d7d6:	d400      	bmi.n	802d7da <Swing_Limit_Contrl+0x182>
+			{
+				Swing_Limit_Flag=4;
+				Swing_Time_Count=0;
+			}
+			break;
+ 802d7d8:	e0a2      	b.n	802d920 <Swing_Limit_Contrl+0x2c8>
+				Swing_Limit_Flag=4;
+ 802d7da:	4b59      	ldr	r3, [pc, #356]	@ (802d940 <Swing_Limit_Contrl+0x2e8>)
+ 802d7dc:	2204      	movs	r2, #4
+ 802d7de:	601a      	str	r2, [r3, #0]
+				Swing_Time_Count=0;
+ 802d7e0:	4b5b      	ldr	r3, [pc, #364]	@ (802d950 <Swing_Limit_Contrl+0x2f8>)
+ 802d7e2:	2200      	movs	r2, #0
+ 802d7e4:	601a      	str	r2, [r3, #0]
+			break;
+ 802d7e6:	e09b      	b.n	802d920 <Swing_Limit_Contrl+0x2c8>
+
+		case 3: //向右旋转
+			Swing_Time_Count++;
+ 802d7e8:	4b59      	ldr	r3, [pc, #356]	@ (802d950 <Swing_Limit_Contrl+0x2f8>)
+ 802d7ea:	681b      	ldr	r3, [r3, #0]
+ 802d7ec:	3301      	adds	r3, #1
+ 802d7ee:	4a58      	ldr	r2, [pc, #352]	@ (802d950 <Swing_Limit_Contrl+0x2f8>)
+ 802d7f0:	6013      	str	r3, [r2, #0]
+			if((GV.SwingMotor.Real_Position>Left_Target_Pos-20000)||(Swing_Time_Count>Swing_Time_All))
+ 802d7f2:	4b54      	ldr	r3, [pc, #336]	@ (802d944 <Swing_Limit_Contrl+0x2ec>)
+ 802d7f4:	f8d3 319c 	ldr.w	r3, [r3, #412]	@ 0x19c
+ 802d7f8:	ee07 3a90 	vmov	s15, r3
+ 802d7fc:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802d800:	4b51      	ldr	r3, [pc, #324]	@ (802d948 <Swing_Limit_Contrl+0x2f0>)
+ 802d802:	ed93 7b00 	vldr	d7, [r3]
+ 802d806:	ed9f 5b4c 	vldr	d5, [pc, #304]	@ 802d938 <Swing_Limit_Contrl+0x2e0>
+ 802d80a:	ee37 7b45 	vsub.f64	d7, d7, d5
+ 802d80e:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802d812:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802d816:	dc0e      	bgt.n	802d836 <Swing_Limit_Contrl+0x1de>
+ 802d818:	4b4d      	ldr	r3, [pc, #308]	@ (802d950 <Swing_Limit_Contrl+0x2f8>)
+ 802d81a:	681b      	ldr	r3, [r3, #0]
+ 802d81c:	ee07 3a90 	vmov	s15, r3
+ 802d820:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802d824:	4b4c      	ldr	r3, [pc, #304]	@ (802d958 <Swing_Limit_Contrl+0x300>)
+ 802d826:	ed93 7b00 	vldr	d7, [r3]
+ 802d82a:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802d82e:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802d832:	dc00      	bgt.n	802d836 <Swing_Limit_Contrl+0x1de>
+				GV.SwingMotor.Position_immediately1_Lag2=2;
+				GV.SwingMotor.Tar_Position_count=Right_Target_Pos;
+				GV.SwingMotor.Tar_Position_Velcity_RPM=((double)GV_Swing_Speed)*201.7;
+			}
+
+			break;
+ 802d834:	e074      	b.n	802d920 <Swing_Limit_Contrl+0x2c8>
+				Swing_Time_Count=0;
+ 802d836:	4b46      	ldr	r3, [pc, #280]	@ (802d950 <Swing_Limit_Contrl+0x2f8>)
+ 802d838:	2200      	movs	r2, #0
+ 802d83a:	601a      	str	r2, [r3, #0]
+				Swing_Limit_Flag++;
+ 802d83c:	4b40      	ldr	r3, [pc, #256]	@ (802d940 <Swing_Limit_Contrl+0x2e8>)
+ 802d83e:	681b      	ldr	r3, [r3, #0]
+ 802d840:	3301      	adds	r3, #1
+ 802d842:	4a3f      	ldr	r2, [pc, #252]	@ (802d940 <Swing_Limit_Contrl+0x2e8>)
+ 802d844:	6013      	str	r3, [r2, #0]
+				GV.SwingMotor.Position_immediately1_Lag2=2;
+ 802d846:	4b3f      	ldr	r3, [pc, #252]	@ (802d944 <Swing_Limit_Contrl+0x2ec>)
+ 802d848:	2202      	movs	r2, #2
+ 802d84a:	f8c3 21d4 	str.w	r2, [r3, #468]	@ 0x1d4
+				GV.SwingMotor.Tar_Position_count=Right_Target_Pos;
+ 802d84e:	4b3f      	ldr	r3, [pc, #252]	@ (802d94c <Swing_Limit_Contrl+0x2f4>)
+ 802d850:	ed93 7b00 	vldr	d7, [r3]
+ 802d854:	eefd 7bc7 	vcvt.s32.f64	s15, d7
+ 802d858:	ee17 2a90 	vmov	r2, s15
+ 802d85c:	4b39      	ldr	r3, [pc, #228]	@ (802d944 <Swing_Limit_Contrl+0x2ec>)
+ 802d85e:	f8c3 21d8 	str.w	r2, [r3, #472]	@ 0x1d8
+				GV.SwingMotor.Tar_Position_Velcity_RPM=((double)GV_Swing_Speed)*201.7;
+ 802d862:	4b3c      	ldr	r3, [pc, #240]	@ (802d954 <Swing_Limit_Contrl+0x2fc>)
+ 802d864:	681b      	ldr	r3, [r3, #0]
+ 802d866:	ee07 3a90 	vmov	s15, r3
+ 802d86a:	eeb8 7be7 	vcvt.f64.s32	d7, s15
+ 802d86e:	ed9f 6b30 	vldr	d6, [pc, #192]	@ 802d930 <Swing_Limit_Contrl+0x2d8>
+ 802d872:	ee27 7b06 	vmul.f64	d7, d7, d6
+ 802d876:	eefd 7bc7 	vcvt.s32.f64	s15, d7
+ 802d87a:	ee17 2a90 	vmov	r2, s15
+ 802d87e:	4b31      	ldr	r3, [pc, #196]	@ (802d944 <Swing_Limit_Contrl+0x2ec>)
+ 802d880:	f8c3 21dc 	str.w	r2, [r3, #476]	@ 0x1dc
+			break;
+ 802d884:	e04c      	b.n	802d920 <Swing_Limit_Contrl+0x2c8>
+		case 4:
+			Swing_Time_Count++;
+ 802d886:	4b32      	ldr	r3, [pc, #200]	@ (802d950 <Swing_Limit_Contrl+0x2f8>)
+ 802d888:	681b      	ldr	r3, [r3, #0]
+ 802d88a:	3301      	adds	r3, #1
+ 802d88c:	4a30      	ldr	r2, [pc, #192]	@ (802d950 <Swing_Limit_Contrl+0x2f8>)
+ 802d88e:	6013      	str	r3, [r2, #0]
+			if((GV.SwingMotor.Real_Position<Right_Target_Pos+20000)||(Swing_Time_Count>Swing_Time_All))
+ 802d890:	4b2c      	ldr	r3, [pc, #176]	@ (802d944 <Swing_Limit_Contrl+0x2ec>)
+ 802d892:	f8d3 319c 	ldr.w	r3, [r3, #412]	@ 0x19c
+ 802d896:	ee07 3a90 	vmov	s15, r3
+ 802d89a:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802d89e:	4b2b      	ldr	r3, [pc, #172]	@ (802d94c <Swing_Limit_Contrl+0x2f4>)
+ 802d8a0:	ed93 7b00 	vldr	d7, [r3]
+ 802d8a4:	ed9f 5b24 	vldr	d5, [pc, #144]	@ 802d938 <Swing_Limit_Contrl+0x2e0>
+ 802d8a8:	ee37 7b05 	vadd.f64	d7, d7, d5
+ 802d8ac:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802d8b0:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802d8b4:	d40e      	bmi.n	802d8d4 <Swing_Limit_Contrl+0x27c>
+ 802d8b6:	4b26      	ldr	r3, [pc, #152]	@ (802d950 <Swing_Limit_Contrl+0x2f8>)
+ 802d8b8:	681b      	ldr	r3, [r3, #0]
+ 802d8ba:	ee07 3a90 	vmov	s15, r3
+ 802d8be:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802d8c2:	4b25      	ldr	r3, [pc, #148]	@ (802d958 <Swing_Limit_Contrl+0x300>)
+ 802d8c4:	ed93 7b00 	vldr	d7, [r3]
+ 802d8c8:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802d8cc:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802d8d0:	dc00      	bgt.n	802d8d4 <Swing_Limit_Contrl+0x27c>
+				Swing_Limit_Flag=3;
+				GV.SwingMotor.Position_immediately1_Lag2=2;
+				GV.SwingMotor.Tar_Position_count=Left_Target_Pos;
+				GV.SwingMotor.Tar_Position_Velcity_RPM=((double)GV_Swing_Speed)*201.7;
+			}
+			break;
+ 802d8d2:	e024      	b.n	802d91e <Swing_Limit_Contrl+0x2c6>
+				Swing_Time_Count=0;
+ 802d8d4:	4b1e      	ldr	r3, [pc, #120]	@ (802d950 <Swing_Limit_Contrl+0x2f8>)
+ 802d8d6:	2200      	movs	r2, #0
+ 802d8d8:	601a      	str	r2, [r3, #0]
+				Swing_Limit_Flag=3;
+ 802d8da:	4b19      	ldr	r3, [pc, #100]	@ (802d940 <Swing_Limit_Contrl+0x2e8>)
+ 802d8dc:	2203      	movs	r2, #3
+ 802d8de:	601a      	str	r2, [r3, #0]
+				GV.SwingMotor.Position_immediately1_Lag2=2;
+ 802d8e0:	4b18      	ldr	r3, [pc, #96]	@ (802d944 <Swing_Limit_Contrl+0x2ec>)
+ 802d8e2:	2202      	movs	r2, #2
+ 802d8e4:	f8c3 21d4 	str.w	r2, [r3, #468]	@ 0x1d4
+				GV.SwingMotor.Tar_Position_count=Left_Target_Pos;
+ 802d8e8:	4b17      	ldr	r3, [pc, #92]	@ (802d948 <Swing_Limit_Contrl+0x2f0>)
+ 802d8ea:	ed93 7b00 	vldr	d7, [r3]
+ 802d8ee:	eefd 7bc7 	vcvt.s32.f64	s15, d7
+ 802d8f2:	ee17 2a90 	vmov	r2, s15
+ 802d8f6:	4b13      	ldr	r3, [pc, #76]	@ (802d944 <Swing_Limit_Contrl+0x2ec>)
+ 802d8f8:	f8c3 21d8 	str.w	r2, [r3, #472]	@ 0x1d8
+				GV.SwingMotor.Tar_Position_Velcity_RPM=((double)GV_Swing_Speed)*201.7;
+ 802d8fc:	4b15      	ldr	r3, [pc, #84]	@ (802d954 <Swing_Limit_Contrl+0x2fc>)
+ 802d8fe:	681b      	ldr	r3, [r3, #0]
+ 802d900:	ee07 3a90 	vmov	s15, r3
+ 802d904:	eeb8 7be7 	vcvt.f64.s32	d7, s15
+ 802d908:	ed9f 6b09 	vldr	d6, [pc, #36]	@ 802d930 <Swing_Limit_Contrl+0x2d8>
+ 802d90c:	ee27 7b06 	vmul.f64	d7, d7, d6
+ 802d910:	eefd 7bc7 	vcvt.s32.f64	s15, d7
+ 802d914:	ee17 2a90 	vmov	r2, s15
+ 802d918:	4b0a      	ldr	r3, [pc, #40]	@ (802d944 <Swing_Limit_Contrl+0x2ec>)
+ 802d91a:	f8c3 21dc 	str.w	r2, [r3, #476]	@ 0x1dc
+			break;
+ 802d91e:	bf00      	nop
+	}
+}
+ 802d920:	bf00      	nop
+ 802d922:	bd80      	pop	{r7, pc}
+ 802d924:	f3af 8000 	nop.w
+ 802d928:	00000000 	.word	0x00000000
+ 802d92c:	40d86a00 	.word	0x40d86a00
+ 802d930:	66666666 	.word	0x66666666
+ 802d934:	40693666 	.word	0x40693666
+ 802d938:	00000000 	.word	0x00000000
+ 802d93c:	40d38800 	.word	0x40d38800
+ 802d940:	2400a6f4 	.word	0x2400a6f4
+ 802d944:	24000340 	.word	0x24000340
+ 802d948:	2400a820 	.word	0x2400a820
+ 802d94c:	2400a828 	.word	0x2400a828
+ 802d950:	2400a80c 	.word	0x2400a80c
+ 802d954:	2400a710 	.word	0x2400a710
+ 802d958:	2400a810 	.word	0x2400a810
+ 802d95c:	00000000 	.word	0x00000000
+
+0802d960 <Back_Para_Compute>:
+
+double Swi_Range_Auto=0;
+void Back_Para_Compute()
+{
+ 802d960:	b480      	push	{r7}
+ 802d962:	b089      	sub	sp, #36	@ 0x24
+ 802d964:	af00      	add	r7, sp, #0
+	double Sw_Rust_Mid_Posi=-6753;//需检测修改
+ 802d966:	a344      	add	r3, pc, #272	@ (adr r3, 802da78 <Back_Para_Compute+0x118>)
+ 802d968:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802d96c:	e9c7 2306 	strd	r2, r3, [r7, #24]
+
+	double Swi_Speed_Auto=((double)CV.PV.Robot_Swing_Speed)*201.7;
+ 802d970:	4b37      	ldr	r3, [pc, #220]	@ (802da50 <Back_Para_Compute+0xf0>)
+ 802d972:	691b      	ldr	r3, [r3, #16]
+ 802d974:	ee07 3a90 	vmov	s15, r3
+ 802d978:	eeb8 7be7 	vcvt.f64.s32	d7, s15
+ 802d97c:	ed9f 6b2e 	vldr	d6, [pc, #184]	@ 802da38 <Back_Para_Compute+0xd8>
+ 802d980:	ee27 7b06 	vmul.f64	d7, d7, d6
+ 802d984:	ed87 7b04 	vstr	d7, [r7, #16]
+	double Back_Angle_Deg=5;
+ 802d988:	f04f 0200 	mov.w	r2, #0
+ 802d98c:	4b31      	ldr	r3, [pc, #196]	@ (802da54 <Back_Para_Compute+0xf4>)
+ 802d98e:	e9c7 2302 	strd	r2, r3, [r7, #8]
+
+	double Turn_Angle_Back=TT_One_Deg_Count*Back_Angle_Deg;	//总后退3S，1.5S在左边，1.5S在右边
+ 802d992:	ed97 7b02 	vldr	d7, [r7, #8]
+ 802d996:	ed9f 6b2a 	vldr	d6, [pc, #168]	@ 802da40 <Back_Para_Compute+0xe0>
+ 802d99a:	ee27 7b06 	vmul.f64	d7, d7, d6
+ 802d99e:	ed87 7b00 	vstr	d7, [r7]
+//	Left_Target_Pos=Sw_Rust_Mid_Posi+Swi_Range_Auto;//左侧边界
+//	Right_Target_Pos=Sw_Rust_Mid_Posi-Swi_Range_Auto;//右侧边界
+	Left_Threshold_Pos=Left_Target_Pos-Turn_Angle_Back;//正向5度阈值
+ 802d9a2:	4b2d      	ldr	r3, [pc, #180]	@ (802da58 <Back_Para_Compute+0xf8>)
+ 802d9a4:	ed93 6b00 	vldr	d6, [r3]
+ 802d9a8:	ed97 7b00 	vldr	d7, [r7]
+ 802d9ac:	ee36 7b47 	vsub.f64	d7, d6, d7
+ 802d9b0:	4b2a      	ldr	r3, [pc, #168]	@ (802da5c <Back_Para_Compute+0xfc>)
+ 802d9b2:	ed83 7b00 	vstr	d7, [r3]
+	Right_Threshold_Pos=Right_Target_Pos+Turn_Angle_Back;//逆向5度阈值
+ 802d9b6:	4b2a      	ldr	r3, [pc, #168]	@ (802da60 <Back_Para_Compute+0x100>)
+ 802d9b8:	ed93 6b00 	vldr	d6, [r3]
+ 802d9bc:	ed97 7b00 	vldr	d7, [r7]
+ 802d9c0:	ee36 7b07 	vadd.f64	d7, d6, d7
+ 802d9c4:	4b27      	ldr	r3, [pc, #156]	@ (802da64 <Back_Para_Compute+0x104>)
+ 802d9c6:	ed83 7b00 	vstr	d7, [r3]
+
+    Swing_Time_All=((double)Swi_Range_Auto)/((double)GV_Swing_Speed)*500+500;//全程摆臂时间计算
+ 802d9ca:	4b27      	ldr	r3, [pc, #156]	@ (802da68 <Back_Para_Compute+0x108>)
+ 802d9cc:	ed93 5b00 	vldr	d5, [r3]
+ 802d9d0:	4b26      	ldr	r3, [pc, #152]	@ (802da6c <Back_Para_Compute+0x10c>)
+ 802d9d2:	681b      	ldr	r3, [r3, #0]
+ 802d9d4:	ee07 3a90 	vmov	s15, r3
+ 802d9d8:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802d9dc:	ee85 7b06 	vdiv.f64	d7, d5, d6
+ 802d9e0:	ed9f 6b19 	vldr	d6, [pc, #100]	@ 802da48 <Back_Para_Compute+0xe8>
+ 802d9e4:	ee27 7b06 	vmul.f64	d7, d7, d6
+ 802d9e8:	ed9f 6b17 	vldr	d6, [pc, #92]	@ 802da48 <Back_Para_Compute+0xe8>
+ 802d9ec:	ee37 7b06 	vadd.f64	d7, d7, d6
+ 802d9f0:	4b1f      	ldr	r3, [pc, #124]	@ (802da70 <Back_Para_Compute+0x110>)
+ 802d9f2:	ed83 7b00 	vstr	d7, [r3]
+    Swing_Time_Threshold=((double)Swi_Range_Auto-5)/((double)GV_Swing_Speed)*500+500;//阈值摆臂时间计算
+ 802d9f6:	4b1c      	ldr	r3, [pc, #112]	@ (802da68 <Back_Para_Compute+0x108>)
+ 802d9f8:	ed93 7b00 	vldr	d7, [r3]
+ 802d9fc:	eeb1 6b04 	vmov.f64	d6, #20	@ 0x40a00000  5.0
+ 802da00:	ee37 5b46 	vsub.f64	d5, d7, d6
+ 802da04:	4b19      	ldr	r3, [pc, #100]	@ (802da6c <Back_Para_Compute+0x10c>)
+ 802da06:	681b      	ldr	r3, [r3, #0]
+ 802da08:	ee07 3a90 	vmov	s15, r3
+ 802da0c:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802da10:	ee85 7b06 	vdiv.f64	d7, d5, d6
+ 802da14:	ed9f 6b0c 	vldr	d6, [pc, #48]	@ 802da48 <Back_Para_Compute+0xe8>
+ 802da18:	ee27 7b06 	vmul.f64	d7, d7, d6
+ 802da1c:	ed9f 6b0a 	vldr	d6, [pc, #40]	@ 802da48 <Back_Para_Compute+0xe8>
+ 802da20:	ee37 7b06 	vadd.f64	d7, d7, d6
+ 802da24:	4b13      	ldr	r3, [pc, #76]	@ (802da74 <Back_Para_Compute+0x114>)
+ 802da26:	ed83 7b00 	vstr	d7, [r3]
+}
+ 802da2a:	bf00      	nop
+ 802da2c:	3724      	adds	r7, #36	@ 0x24
+ 802da2e:	46bd      	mov	sp, r7
+ 802da30:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 802da34:	4770      	bx	lr
+ 802da36:	bf00      	nop
+ 802da38:	66666666 	.word	0x66666666
+ 802da3c:	40693666 	.word	0x40693666
+ 802da40:	00000000 	.word	0x00000000
+ 802da44:	40c58300 	.word	0x40c58300
+ 802da48:	00000000 	.word	0x00000000
+ 802da4c:	407f4000 	.word	0x407f4000
+ 802da50:	240002a0 	.word	0x240002a0
+ 802da54:	40140000 	.word	0x40140000
+ 802da58:	2400a820 	.word	0x2400a820
+ 802da5c:	2400a830 	.word	0x2400a830
+ 802da60:	2400a828 	.word	0x2400a828
+ 802da64:	2400a838 	.word	0x2400a838
+ 802da68:	2400a868 	.word	0x2400a868
+ 802da6c:	2400a710 	.word	0x2400a710
+ 802da70:	2400a810 	.word	0x2400a810
+ 802da74:	2400a818 	.word	0x2400a818
+ 802da78:	00000000 	.word	0x00000000
+ 802da7c:	c0ba6100 	.word	0xc0ba6100
+
+0802da80 <Robot_Platform_Back_Contronl_Horizontal>:
+
+
+
+
+void Robot_Platform_Back_Contronl_Horizontal()
+{
+ 802da80:	b580      	push	{r7, lr}
+ 802da82:	af00      	add	r7, sp, #0
+	//计算后退时间及后退速度
+
+	switch(Robot_Platform_Back_Flag)
+ 802da84:	4b74      	ldr	r3, [pc, #464]	@ (802dc58 <Robot_Platform_Back_Contronl_Horizontal+0x1d8>)
+ 802da86:	681b      	ldr	r3, [r3, #0]
+ 802da88:	2b04      	cmp	r3, #4
+ 802da8a:	f200 80e2 	bhi.w	802dc52 <Robot_Platform_Back_Contronl_Horizontal+0x1d2>
+ 802da8e:	a201      	add	r2, pc, #4	@ (adr r2, 802da94 <Robot_Platform_Back_Contronl_Horizontal+0x14>)
+ 802da90:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 802da94:	0802daa9 	.word	0x0802daa9
+ 802da98:	0802dabf 	.word	0x0802dabf
+ 802da9c:	0802db07 	.word	0x0802db07
+ 802daa0:	0802db9f 	.word	0x0802db9f
+ 802daa4:	0802dbf1 	.word	0x0802dbf1
+	{
+		case 0:
+			Platform_Back_Para_Compute_Horizontal();
+ 802daa8:	f000 fab2 	bl	802e010 <Platform_Back_Para_Compute_Horizontal>
+			Auto_Job_Back_Time_MS_Count=0;
+ 802daac:	4b6b      	ldr	r3, [pc, #428]	@ (802dc5c <Robot_Platform_Back_Contronl_Horizontal+0x1dc>)
+ 802daae:	2200      	movs	r2, #0
+ 802dab0:	601a      	str	r2, [r3, #0]
+			Robot_Platform_Back_Flag++;
+ 802dab2:	4b69      	ldr	r3, [pc, #420]	@ (802dc58 <Robot_Platform_Back_Contronl_Horizontal+0x1d8>)
+ 802dab4:	681b      	ldr	r3, [r3, #0]
+ 802dab6:	3301      	adds	r3, #1
+ 802dab8:	4a67      	ldr	r2, [pc, #412]	@ (802dc58 <Robot_Platform_Back_Contronl_Horizontal+0x1d8>)
+ 802daba:	6013      	str	r3, [r2, #0]
+			break;
+ 802dabc:	e0c9      	b.n	802dc52 <Robot_Platform_Back_Contronl_Horizontal+0x1d2>
+		case 1:
+			Auto_Job_Back_Time_MS_Count++;
+ 802dabe:	4b67      	ldr	r3, [pc, #412]	@ (802dc5c <Robot_Platform_Back_Contronl_Horizontal+0x1dc>)
+ 802dac0:	681b      	ldr	r3, [r3, #0]
+ 802dac2:	3301      	adds	r3, #1
+ 802dac4:	4a65      	ldr	r2, [pc, #404]	@ (802dc5c <Robot_Platform_Back_Contronl_Horizontal+0x1dc>)
+ 802dac6:	6013      	str	r3, [r2, #0]
+			if(GV.SwingMotor.Real_Position>Left_Threshold_Pos)
+ 802dac8:	4b65      	ldr	r3, [pc, #404]	@ (802dc60 <Robot_Platform_Back_Contronl_Horizontal+0x1e0>)
+ 802daca:	f8d3 319c 	ldr.w	r3, [r3, #412]	@ 0x19c
+ 802dace:	ee07 3a90 	vmov	s15, r3
+ 802dad2:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802dad6:	4b63      	ldr	r3, [pc, #396]	@ (802dc64 <Robot_Platform_Back_Contronl_Horizontal+0x1e4>)
+ 802dad8:	ed93 7b00 	vldr	d7, [r3]
+ 802dadc:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802dae0:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802dae4:	dd07      	ble.n	802daf6 <Robot_Platform_Back_Contronl_Horizontal+0x76>
+			{
+				Robot_Platform_Back_Flag++;
+ 802dae6:	4b5c      	ldr	r3, [pc, #368]	@ (802dc58 <Robot_Platform_Back_Contronl_Horizontal+0x1d8>)
+ 802dae8:	681b      	ldr	r3, [r3, #0]
+ 802daea:	3301      	adds	r3, #1
+ 802daec:	4a5a      	ldr	r2, [pc, #360]	@ (802dc58 <Robot_Platform_Back_Contronl_Horizontal+0x1d8>)
+ 802daee:	6013      	str	r3, [r2, #0]
+				Auto_Job_Back_Time_MS_Count=0;
+ 802daf0:	4b5a      	ldr	r3, [pc, #360]	@ (802dc5c <Robot_Platform_Back_Contronl_Horizontal+0x1dc>)
+ 802daf2:	2200      	movs	r2, #0
+ 802daf4:	601a      	str	r2, [r3, #0]
+			}
+			GV.LeftMotor.Target_Velcity  =0;
+ 802daf6:	4b5a      	ldr	r3, [pc, #360]	@ (802dc60 <Robot_Platform_Back_Contronl_Horizontal+0x1e0>)
+ 802daf8:	2200      	movs	r2, #0
+ 802dafa:	679a      	str	r2, [r3, #120]	@ 0x78
+			GV.RightMotor.Target_Velcity =0;
+ 802dafc:	4b58      	ldr	r3, [pc, #352]	@ (802dc60 <Robot_Platform_Back_Contronl_Horizontal+0x1e0>)
+ 802dafe:	2200      	movs	r2, #0
+ 802db00:	f8c3 20f8 	str.w	r2, [r3, #248]	@ 0xf8
+			break;
+ 802db04:	e0a5      	b.n	802dc52 <Robot_Platform_Back_Contronl_Horizontal+0x1d2>
+		case 2:
+			Auto_Job_Back_Time_MS_Count++;
+ 802db06:	4b55      	ldr	r3, [pc, #340]	@ (802dc5c <Robot_Platform_Back_Contronl_Horizontal+0x1dc>)
+ 802db08:	681b      	ldr	r3, [r3, #0]
+ 802db0a:	3301      	adds	r3, #1
+ 802db0c:	4a53      	ldr	r2, [pc, #332]	@ (802dc5c <Robot_Platform_Back_Contronl_Horizontal+0x1dc>)
+ 802db0e:	6013      	str	r3, [r2, #0]
+			if((GV.SwingMotor.Real_Position>Left_Threshold_Pos)||(GV.SwingMotor.Real_Position<Right_Threshold_Pos))
+ 802db10:	4b53      	ldr	r3, [pc, #332]	@ (802dc60 <Robot_Platform_Back_Contronl_Horizontal+0x1e0>)
+ 802db12:	f8d3 319c 	ldr.w	r3, [r3, #412]	@ 0x19c
+ 802db16:	ee07 3a90 	vmov	s15, r3
+ 802db1a:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802db1e:	4b51      	ldr	r3, [pc, #324]	@ (802dc64 <Robot_Platform_Back_Contronl_Horizontal+0x1e4>)
+ 802db20:	ed93 7b00 	vldr	d7, [r3]
+ 802db24:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802db28:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802db2c:	dc0e      	bgt.n	802db4c <Robot_Platform_Back_Contronl_Horizontal+0xcc>
+ 802db2e:	4b4c      	ldr	r3, [pc, #304]	@ (802dc60 <Robot_Platform_Back_Contronl_Horizontal+0x1e0>)
+ 802db30:	f8d3 319c 	ldr.w	r3, [r3, #412]	@ 0x19c
+ 802db34:	ee07 3a90 	vmov	s15, r3
+ 802db38:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802db3c:	4b4a      	ldr	r3, [pc, #296]	@ (802dc68 <Robot_Platform_Back_Contronl_Horizontal+0x1e8>)
+ 802db3e:	ed93 7b00 	vldr	d7, [r3]
+ 802db42:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802db46:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802db4a:	d507      	bpl.n	802db5c <Robot_Platform_Back_Contronl_Horizontal+0xdc>
+			{
+				Robot_Platform_Back_Flag++;
+ 802db4c:	4b42      	ldr	r3, [pc, #264]	@ (802dc58 <Robot_Platform_Back_Contronl_Horizontal+0x1d8>)
+ 802db4e:	681b      	ldr	r3, [r3, #0]
+ 802db50:	3301      	adds	r3, #1
+ 802db52:	4a41      	ldr	r2, [pc, #260]	@ (802dc58 <Robot_Platform_Back_Contronl_Horizontal+0x1d8>)
+ 802db54:	6013      	str	r3, [r2, #0]
+				Auto_Job_Back_Time_MS_Count=0;
+ 802db56:	4b41      	ldr	r3, [pc, #260]	@ (802dc5c <Robot_Platform_Back_Contronl_Horizontal+0x1dc>)
+ 802db58:	2200      	movs	r2, #0
+ 802db5a:	601a      	str	r2, [r3, #0]
+			}
+			if(Auto_Job_Back_Time_MS_Count>Swing_Time_All)
+ 802db5c:	4b3f      	ldr	r3, [pc, #252]	@ (802dc5c <Robot_Platform_Back_Contronl_Horizontal+0x1dc>)
+ 802db5e:	681b      	ldr	r3, [r3, #0]
+ 802db60:	ee07 3a90 	vmov	s15, r3
+ 802db64:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802db68:	4b40      	ldr	r3, [pc, #256]	@ (802dc6c <Robot_Platform_Back_Contronl_Horizontal+0x1ec>)
+ 802db6a:	ed93 7b00 	vldr	d7, [r3]
+ 802db6e:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802db72:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802db76:	dd0a      	ble.n	802db8e <Robot_Platform_Back_Contronl_Horizontal+0x10e>
+			{
+				GV.LeftMotor.Target_Velcity  =0;
+ 802db78:	4b39      	ldr	r3, [pc, #228]	@ (802dc60 <Robot_Platform_Back_Contronl_Horizontal+0x1e0>)
+ 802db7a:	2200      	movs	r2, #0
+ 802db7c:	679a      	str	r2, [r3, #120]	@ 0x78
+				GV.RightMotor.Target_Velcity =0;
+ 802db7e:	4b38      	ldr	r3, [pc, #224]	@ (802dc60 <Robot_Platform_Back_Contronl_Horizontal+0x1e0>)
+ 802db80:	2200      	movs	r2, #0
+ 802db82:	f8c3 20f8 	str.w	r2, [r3, #248]	@ 0xf8
+				GV.SwingMotor.Target_Velcity =0;
+ 802db86:	4b36      	ldr	r3, [pc, #216]	@ (802dc60 <Robot_Platform_Back_Contronl_Horizontal+0x1e0>)
+ 802db88:	2200      	movs	r2, #0
+ 802db8a:	f8c3 2178 	str.w	r2, [r3, #376]	@ 0x178
+			}
+			GV.LeftMotor.Target_Velcity  =0;
+ 802db8e:	4b34      	ldr	r3, [pc, #208]	@ (802dc60 <Robot_Platform_Back_Contronl_Horizontal+0x1e0>)
+ 802db90:	2200      	movs	r2, #0
+ 802db92:	679a      	str	r2, [r3, #120]	@ 0x78
+			GV.RightMotor.Target_Velcity =0;
+ 802db94:	4b32      	ldr	r3, [pc, #200]	@ (802dc60 <Robot_Platform_Back_Contronl_Horizontal+0x1e0>)
+ 802db96:	2200      	movs	r2, #0
+ 802db98:	f8c3 20f8 	str.w	r2, [r3, #248]	@ 0xf8
+			break;
+ 802db9c:	e059      	b.n	802dc52 <Robot_Platform_Back_Contronl_Horizontal+0x1d2>
+		case 3:
+			Move_Horizontal_Vertical_Task_Backwards_Do_Backward(Horizontal_Back_Speed_Value,CV_Robot_Deri_Angle_Deg_Grity);
+ 802db9e:	4b34      	ldr	r3, [pc, #208]	@ (802dc70 <Robot_Platform_Back_Contronl_Horizontal+0x1f0>)
+ 802dba0:	ed93 7b00 	vldr	d7, [r3]
+ 802dba4:	4b33      	ldr	r3, [pc, #204]	@ (802dc74 <Robot_Platform_Back_Contronl_Horizontal+0x1f4>)
+ 802dba6:	ed93 6b00 	vldr	d6, [r3]
+ 802dbaa:	eeb0 1b46 	vmov.f64	d1, d6
+ 802dbae:	eeb0 0b47 	vmov.f64	d0, d7
+ 802dbb2:	f7fe fefd 	bl	802c9b0 <Move_Horizontal_Vertical_Task_Backwards_Do_Backward>
+			Auto_Job_Back_Time_MS_Count++;
+ 802dbb6:	4b29      	ldr	r3, [pc, #164]	@ (802dc5c <Robot_Platform_Back_Contronl_Horizontal+0x1dc>)
+ 802dbb8:	681b      	ldr	r3, [r3, #0]
+ 802dbba:	3301      	adds	r3, #1
+ 802dbbc:	4a27      	ldr	r2, [pc, #156]	@ (802dc5c <Robot_Platform_Back_Contronl_Horizontal+0x1dc>)
+ 802dbbe:	6013      	str	r3, [r2, #0]
+			if(Auto_Job_Back_Time_MS_Count>Auto_Job_Back_Time_MS_Horizontal)
+ 802dbc0:	4b26      	ldr	r3, [pc, #152]	@ (802dc5c <Robot_Platform_Back_Contronl_Horizontal+0x1dc>)
+ 802dbc2:	681b      	ldr	r3, [r3, #0]
+ 802dbc4:	ee07 3a90 	vmov	s15, r3
+ 802dbc8:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802dbcc:	4b2a      	ldr	r3, [pc, #168]	@ (802dc78 <Robot_Platform_Back_Contronl_Horizontal+0x1f8>)
+ 802dbce:	ed93 7b00 	vldr	d7, [r3]
+ 802dbd2:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802dbd6:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802dbda:	dc00      	bgt.n	802dbde <Robot_Platform_Back_Contronl_Horizontal+0x15e>
+			{
+				Robot_Platform_Back_Flag++;
+				Auto_Job_Back_Time_MS_Count=0;
+			}
+			break;
+ 802dbdc:	e039      	b.n	802dc52 <Robot_Platform_Back_Contronl_Horizontal+0x1d2>
+				Robot_Platform_Back_Flag++;
+ 802dbde:	4b1e      	ldr	r3, [pc, #120]	@ (802dc58 <Robot_Platform_Back_Contronl_Horizontal+0x1d8>)
+ 802dbe0:	681b      	ldr	r3, [r3, #0]
+ 802dbe2:	3301      	adds	r3, #1
+ 802dbe4:	4a1c      	ldr	r2, [pc, #112]	@ (802dc58 <Robot_Platform_Back_Contronl_Horizontal+0x1d8>)
+ 802dbe6:	6013      	str	r3, [r2, #0]
+				Auto_Job_Back_Time_MS_Count=0;
+ 802dbe8:	4b1c      	ldr	r3, [pc, #112]	@ (802dc5c <Robot_Platform_Back_Contronl_Horizontal+0x1dc>)
+ 802dbea:	2200      	movs	r2, #0
+ 802dbec:	601a      	str	r2, [r3, #0]
+			break;
+ 802dbee:	e030      	b.n	802dc52 <Robot_Platform_Back_Contronl_Horizontal+0x1d2>
+		case 4:
+			if((GV.SwingMotor.Real_Position<Left_Threshold_Pos)&&(GV.SwingMotor.Real_Position>Right_Threshold_Pos))
+ 802dbf0:	4b1b      	ldr	r3, [pc, #108]	@ (802dc60 <Robot_Platform_Back_Contronl_Horizontal+0x1e0>)
+ 802dbf2:	f8d3 319c 	ldr.w	r3, [r3, #412]	@ 0x19c
+ 802dbf6:	ee07 3a90 	vmov	s15, r3
+ 802dbfa:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802dbfe:	4b19      	ldr	r3, [pc, #100]	@ (802dc64 <Robot_Platform_Back_Contronl_Horizontal+0x1e4>)
+ 802dc00:	ed93 7b00 	vldr	d7, [r3]
+ 802dc04:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802dc08:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802dc0c:	d519      	bpl.n	802dc42 <Robot_Platform_Back_Contronl_Horizontal+0x1c2>
+ 802dc0e:	4b14      	ldr	r3, [pc, #80]	@ (802dc60 <Robot_Platform_Back_Contronl_Horizontal+0x1e0>)
+ 802dc10:	f8d3 319c 	ldr.w	r3, [r3, #412]	@ 0x19c
+ 802dc14:	ee07 3a90 	vmov	s15, r3
+ 802dc18:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802dc1c:	4b12      	ldr	r3, [pc, #72]	@ (802dc68 <Robot_Platform_Back_Contronl_Horizontal+0x1e8>)
+ 802dc1e:	ed93 7b00 	vldr	d7, [r3]
+ 802dc22:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802dc26:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802dc2a:	dd0a      	ble.n	802dc42 <Robot_Platform_Back_Contronl_Horizontal+0x1c2>
+			{
+				Backward_Num_X_Count++;
+ 802dc2c:	4b13      	ldr	r3, [pc, #76]	@ (802dc7c <Robot_Platform_Back_Contronl_Horizontal+0x1fc>)
+ 802dc2e:	681b      	ldr	r3, [r3, #0]
+ 802dc30:	3301      	adds	r3, #1
+ 802dc32:	4a12      	ldr	r2, [pc, #72]	@ (802dc7c <Robot_Platform_Back_Contronl_Horizontal+0x1fc>)
+ 802dc34:	6013      	str	r3, [r2, #0]
+				Robot_Platform_Back_Flag=2;
+ 802dc36:	4b08      	ldr	r3, [pc, #32]	@ (802dc58 <Robot_Platform_Back_Contronl_Horizontal+0x1d8>)
+ 802dc38:	2202      	movs	r2, #2
+ 802dc3a:	601a      	str	r2, [r3, #0]
+				Auto_Job_Back_Time_MS_Count=0;
+ 802dc3c:	4b07      	ldr	r3, [pc, #28]	@ (802dc5c <Robot_Platform_Back_Contronl_Horizontal+0x1dc>)
+ 802dc3e:	2200      	movs	r2, #0
+ 802dc40:	601a      	str	r2, [r3, #0]
+			}
+			GV.LeftMotor.Target_Velcity  =0;
+ 802dc42:	4b07      	ldr	r3, [pc, #28]	@ (802dc60 <Robot_Platform_Back_Contronl_Horizontal+0x1e0>)
+ 802dc44:	2200      	movs	r2, #0
+ 802dc46:	679a      	str	r2, [r3, #120]	@ 0x78
+			GV.RightMotor.Target_Velcity =0;
+ 802dc48:	4b05      	ldr	r3, [pc, #20]	@ (802dc60 <Robot_Platform_Back_Contronl_Horizontal+0x1e0>)
+ 802dc4a:	2200      	movs	r2, #0
+ 802dc4c:	f8c3 20f8 	str.w	r2, [r3, #248]	@ 0xf8
+			break;
+ 802dc50:	bf00      	nop
+	}
+}
+ 802dc52:	bf00      	nop
+ 802dc54:	bd80      	pop	{r7, pc}
+ 802dc56:	bf00      	nop
+ 802dc58:	2400a6f8 	.word	0x2400a6f8
+ 802dc5c:	2400a6fc 	.word	0x2400a6fc
+ 802dc60:	24000340 	.word	0x24000340
+ 802dc64:	2400a830 	.word	0x2400a830
+ 802dc68:	2400a838 	.word	0x2400a838
+ 802dc6c:	2400a810 	.word	0x2400a810
+ 802dc70:	2400a850 	.word	0x2400a850
+ 802dc74:	2400a6d0 	.word	0x2400a6d0
+ 802dc78:	2400a840 	.word	0x2400a840
+ 802dc7c:	2400a79c 	.word	0x2400a79c
+
+0802dc80 <Robot_Platform_Back_Contronl_Vertical>:
+
+
+void Robot_Platform_Back_Contronl_Vertical()
+{
+ 802dc80:	b580      	push	{r7, lr}
+ 802dc82:	af00      	add	r7, sp, #0
+	//计算后退时间及后退速度
+	switch(Robot_Platform_Back_Flag)
+ 802dc84:	4b67      	ldr	r3, [pc, #412]	@ (802de24 <Robot_Platform_Back_Contronl_Vertical+0x1a4>)
+ 802dc86:	681b      	ldr	r3, [r3, #0]
+ 802dc88:	2b04      	cmp	r3, #4
+ 802dc8a:	f200 80c9 	bhi.w	802de20 <Robot_Platform_Back_Contronl_Vertical+0x1a0>
+ 802dc8e:	a201      	add	r2, pc, #4	@ (adr r2, 802dc94 <Robot_Platform_Back_Contronl_Vertical+0x14>)
+ 802dc90:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 802dc94:	0802dca9 	.word	0x0802dca9
+ 802dc98:	0802dcbf 	.word	0x0802dcbf
+ 802dc9c:	0802dd07 	.word	0x0802dd07
+ 802dca0:	0802dd6d 	.word	0x0802dd6d
+ 802dca4:	0802ddbf 	.word	0x0802ddbf
+	{
+		case 0:
+
+			Platform_Back_Para_Compute_Vertical();
+ 802dca8:	f000 fa1e 	bl	802e0e8 <Platform_Back_Para_Compute_Vertical>
+			Auto_Job_Back_Time_MS_Count=0;
+ 802dcac:	4b5e      	ldr	r3, [pc, #376]	@ (802de28 <Robot_Platform_Back_Contronl_Vertical+0x1a8>)
+ 802dcae:	2200      	movs	r2, #0
+ 802dcb0:	601a      	str	r2, [r3, #0]
+			Robot_Platform_Back_Flag++;
+ 802dcb2:	4b5c      	ldr	r3, [pc, #368]	@ (802de24 <Robot_Platform_Back_Contronl_Vertical+0x1a4>)
+ 802dcb4:	681b      	ldr	r3, [r3, #0]
+ 802dcb6:	3301      	adds	r3, #1
+ 802dcb8:	4a5a      	ldr	r2, [pc, #360]	@ (802de24 <Robot_Platform_Back_Contronl_Vertical+0x1a4>)
+ 802dcba:	6013      	str	r3, [r2, #0]
+			break;
+ 802dcbc:	e0b0      	b.n	802de20 <Robot_Platform_Back_Contronl_Vertical+0x1a0>
+		case 1:
+			Auto_Job_Back_Time_MS_Count++;
+ 802dcbe:	4b5a      	ldr	r3, [pc, #360]	@ (802de28 <Robot_Platform_Back_Contronl_Vertical+0x1a8>)
+ 802dcc0:	681b      	ldr	r3, [r3, #0]
+ 802dcc2:	3301      	adds	r3, #1
+ 802dcc4:	4a58      	ldr	r2, [pc, #352]	@ (802de28 <Robot_Platform_Back_Contronl_Vertical+0x1a8>)
+ 802dcc6:	6013      	str	r3, [r2, #0]
+			if(GV.SwingMotor.Real_Position>Left_Threshold_Pos)
+ 802dcc8:	4b58      	ldr	r3, [pc, #352]	@ (802de2c <Robot_Platform_Back_Contronl_Vertical+0x1ac>)
+ 802dcca:	f8d3 319c 	ldr.w	r3, [r3, #412]	@ 0x19c
+ 802dcce:	ee07 3a90 	vmov	s15, r3
+ 802dcd2:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802dcd6:	4b56      	ldr	r3, [pc, #344]	@ (802de30 <Robot_Platform_Back_Contronl_Vertical+0x1b0>)
+ 802dcd8:	ed93 7b00 	vldr	d7, [r3]
+ 802dcdc:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802dce0:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802dce4:	dd07      	ble.n	802dcf6 <Robot_Platform_Back_Contronl_Vertical+0x76>
+			{
+				Robot_Platform_Back_Flag++;
+ 802dce6:	4b4f      	ldr	r3, [pc, #316]	@ (802de24 <Robot_Platform_Back_Contronl_Vertical+0x1a4>)
+ 802dce8:	681b      	ldr	r3, [r3, #0]
+ 802dcea:	3301      	adds	r3, #1
+ 802dcec:	4a4d      	ldr	r2, [pc, #308]	@ (802de24 <Robot_Platform_Back_Contronl_Vertical+0x1a4>)
+ 802dcee:	6013      	str	r3, [r2, #0]
+				Auto_Job_Back_Time_MS_Count=0;
+ 802dcf0:	4b4d      	ldr	r3, [pc, #308]	@ (802de28 <Robot_Platform_Back_Contronl_Vertical+0x1a8>)
+ 802dcf2:	2200      	movs	r2, #0
+ 802dcf4:	601a      	str	r2, [r3, #0]
+			}
+
+			GV.LeftMotor.Target_Velcity  =0;
+ 802dcf6:	4b4d      	ldr	r3, [pc, #308]	@ (802de2c <Robot_Platform_Back_Contronl_Vertical+0x1ac>)
+ 802dcf8:	2200      	movs	r2, #0
+ 802dcfa:	679a      	str	r2, [r3, #120]	@ 0x78
+			GV.RightMotor.Target_Velcity =0;
+ 802dcfc:	4b4b      	ldr	r3, [pc, #300]	@ (802de2c <Robot_Platform_Back_Contronl_Vertical+0x1ac>)
+ 802dcfe:	2200      	movs	r2, #0
+ 802dd00:	f8c3 20f8 	str.w	r2, [r3, #248]	@ 0xf8
+			break;
+ 802dd04:	e08c      	b.n	802de20 <Robot_Platform_Back_Contronl_Vertical+0x1a0>
+		case 2:
+			Auto_Job_Back_Time_MS_Count++;
+ 802dd06:	4b48      	ldr	r3, [pc, #288]	@ (802de28 <Robot_Platform_Back_Contronl_Vertical+0x1a8>)
+ 802dd08:	681b      	ldr	r3, [r3, #0]
+ 802dd0a:	3301      	adds	r3, #1
+ 802dd0c:	4a46      	ldr	r2, [pc, #280]	@ (802de28 <Robot_Platform_Back_Contronl_Vertical+0x1a8>)
+ 802dd0e:	6013      	str	r3, [r2, #0]
+			if((GV.SwingMotor.Real_Position>Left_Threshold_Pos)||(GV.SwingMotor.Real_Position<Right_Threshold_Pos))
+ 802dd10:	4b46      	ldr	r3, [pc, #280]	@ (802de2c <Robot_Platform_Back_Contronl_Vertical+0x1ac>)
+ 802dd12:	f8d3 319c 	ldr.w	r3, [r3, #412]	@ 0x19c
+ 802dd16:	ee07 3a90 	vmov	s15, r3
+ 802dd1a:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802dd1e:	4b44      	ldr	r3, [pc, #272]	@ (802de30 <Robot_Platform_Back_Contronl_Vertical+0x1b0>)
+ 802dd20:	ed93 7b00 	vldr	d7, [r3]
+ 802dd24:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802dd28:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802dd2c:	dc0e      	bgt.n	802dd4c <Robot_Platform_Back_Contronl_Vertical+0xcc>
+ 802dd2e:	4b3f      	ldr	r3, [pc, #252]	@ (802de2c <Robot_Platform_Back_Contronl_Vertical+0x1ac>)
+ 802dd30:	f8d3 319c 	ldr.w	r3, [r3, #412]	@ 0x19c
+ 802dd34:	ee07 3a90 	vmov	s15, r3
+ 802dd38:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802dd3c:	4b3d      	ldr	r3, [pc, #244]	@ (802de34 <Robot_Platform_Back_Contronl_Vertical+0x1b4>)
+ 802dd3e:	ed93 7b00 	vldr	d7, [r3]
+ 802dd42:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802dd46:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802dd4a:	d507      	bpl.n	802dd5c <Robot_Platform_Back_Contronl_Vertical+0xdc>
+			{
+				Robot_Platform_Back_Flag++;
+ 802dd4c:	4b35      	ldr	r3, [pc, #212]	@ (802de24 <Robot_Platform_Back_Contronl_Vertical+0x1a4>)
+ 802dd4e:	681b      	ldr	r3, [r3, #0]
+ 802dd50:	3301      	adds	r3, #1
+ 802dd52:	4a34      	ldr	r2, [pc, #208]	@ (802de24 <Robot_Platform_Back_Contronl_Vertical+0x1a4>)
+ 802dd54:	6013      	str	r3, [r2, #0]
+				Auto_Job_Back_Time_MS_Count=0;
+ 802dd56:	4b34      	ldr	r3, [pc, #208]	@ (802de28 <Robot_Platform_Back_Contronl_Vertical+0x1a8>)
+ 802dd58:	2200      	movs	r2, #0
+ 802dd5a:	601a      	str	r2, [r3, #0]
+			}
+			GV.LeftMotor.Target_Velcity  =0;
+ 802dd5c:	4b33      	ldr	r3, [pc, #204]	@ (802de2c <Robot_Platform_Back_Contronl_Vertical+0x1ac>)
+ 802dd5e:	2200      	movs	r2, #0
+ 802dd60:	679a      	str	r2, [r3, #120]	@ 0x78
+			GV.RightMotor.Target_Velcity =0;
+ 802dd62:	4b32      	ldr	r3, [pc, #200]	@ (802de2c <Robot_Platform_Back_Contronl_Vertical+0x1ac>)
+ 802dd64:	2200      	movs	r2, #0
+ 802dd66:	f8c3 20f8 	str.w	r2, [r3, #248]	@ 0xf8
+			break;
+ 802dd6a:	e059      	b.n	802de20 <Robot_Platform_Back_Contronl_Vertical+0x1a0>
+		case 3:
+
+			Move_Horizontal_Vertical_Task_Backwards_Do_Backward(Vertical_Back_Speed_Value,CV_Robot_Deri_Angle_Deg_Grity);
+ 802dd6c:	4b32      	ldr	r3, [pc, #200]	@ (802de38 <Robot_Platform_Back_Contronl_Vertical+0x1b8>)
+ 802dd6e:	ed93 7b00 	vldr	d7, [r3]
+ 802dd72:	4b32      	ldr	r3, [pc, #200]	@ (802de3c <Robot_Platform_Back_Contronl_Vertical+0x1bc>)
+ 802dd74:	ed93 6b00 	vldr	d6, [r3]
+ 802dd78:	eeb0 1b46 	vmov.f64	d1, d6
+ 802dd7c:	eeb0 0b47 	vmov.f64	d0, d7
+ 802dd80:	f7fe fe16 	bl	802c9b0 <Move_Horizontal_Vertical_Task_Backwards_Do_Backward>
+			Auto_Job_Back_Time_MS_Count++;
+ 802dd84:	4b28      	ldr	r3, [pc, #160]	@ (802de28 <Robot_Platform_Back_Contronl_Vertical+0x1a8>)
+ 802dd86:	681b      	ldr	r3, [r3, #0]
+ 802dd88:	3301      	adds	r3, #1
+ 802dd8a:	4a27      	ldr	r2, [pc, #156]	@ (802de28 <Robot_Platform_Back_Contronl_Vertical+0x1a8>)
+ 802dd8c:	6013      	str	r3, [r2, #0]
+			if(Auto_Job_Back_Time_MS_Count>Auto_Job_Back_Time_MS_Vertical)
+ 802dd8e:	4b26      	ldr	r3, [pc, #152]	@ (802de28 <Robot_Platform_Back_Contronl_Vertical+0x1a8>)
+ 802dd90:	681b      	ldr	r3, [r3, #0]
+ 802dd92:	ee07 3a90 	vmov	s15, r3
+ 802dd96:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802dd9a:	4b29      	ldr	r3, [pc, #164]	@ (802de40 <Robot_Platform_Back_Contronl_Vertical+0x1c0>)
+ 802dd9c:	ed93 7b00 	vldr	d7, [r3]
+ 802dda0:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802dda4:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802dda8:	dc00      	bgt.n	802ddac <Robot_Platform_Back_Contronl_Vertical+0x12c>
+
+			{
+				Robot_Platform_Back_Flag++;
+				Auto_Job_Back_Time_MS_Count=0;
+			}
+			break;
+ 802ddaa:	e039      	b.n	802de20 <Robot_Platform_Back_Contronl_Vertical+0x1a0>
+				Robot_Platform_Back_Flag++;
+ 802ddac:	4b1d      	ldr	r3, [pc, #116]	@ (802de24 <Robot_Platform_Back_Contronl_Vertical+0x1a4>)
+ 802ddae:	681b      	ldr	r3, [r3, #0]
+ 802ddb0:	3301      	adds	r3, #1
+ 802ddb2:	4a1c      	ldr	r2, [pc, #112]	@ (802de24 <Robot_Platform_Back_Contronl_Vertical+0x1a4>)
+ 802ddb4:	6013      	str	r3, [r2, #0]
+				Auto_Job_Back_Time_MS_Count=0;
+ 802ddb6:	4b1c      	ldr	r3, [pc, #112]	@ (802de28 <Robot_Platform_Back_Contronl_Vertical+0x1a8>)
+ 802ddb8:	2200      	movs	r2, #0
+ 802ddba:	601a      	str	r2, [r3, #0]
+			break;
+ 802ddbc:	e030      	b.n	802de20 <Robot_Platform_Back_Contronl_Vertical+0x1a0>
+		case 4:
+			if((GV.SwingMotor.Real_Position<Left_Threshold_Pos)&&(GV.SwingMotor.Real_Position>Right_Threshold_Pos))
+ 802ddbe:	4b1b      	ldr	r3, [pc, #108]	@ (802de2c <Robot_Platform_Back_Contronl_Vertical+0x1ac>)
+ 802ddc0:	f8d3 319c 	ldr.w	r3, [r3, #412]	@ 0x19c
+ 802ddc4:	ee07 3a90 	vmov	s15, r3
+ 802ddc8:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802ddcc:	4b18      	ldr	r3, [pc, #96]	@ (802de30 <Robot_Platform_Back_Contronl_Vertical+0x1b0>)
+ 802ddce:	ed93 7b00 	vldr	d7, [r3]
+ 802ddd2:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802ddd6:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802ddda:	d519      	bpl.n	802de10 <Robot_Platform_Back_Contronl_Vertical+0x190>
+ 802dddc:	4b13      	ldr	r3, [pc, #76]	@ (802de2c <Robot_Platform_Back_Contronl_Vertical+0x1ac>)
+ 802ddde:	f8d3 319c 	ldr.w	r3, [r3, #412]	@ 0x19c
+ 802dde2:	ee07 3a90 	vmov	s15, r3
+ 802dde6:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802ddea:	4b12      	ldr	r3, [pc, #72]	@ (802de34 <Robot_Platform_Back_Contronl_Vertical+0x1b4>)
+ 802ddec:	ed93 7b00 	vldr	d7, [r3]
+ 802ddf0:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802ddf4:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802ddf8:	dd0a      	ble.n	802de10 <Robot_Platform_Back_Contronl_Vertical+0x190>
+			{
+				Backward_Num_X_Count++;
+ 802ddfa:	4b12      	ldr	r3, [pc, #72]	@ (802de44 <Robot_Platform_Back_Contronl_Vertical+0x1c4>)
+ 802ddfc:	681b      	ldr	r3, [r3, #0]
+ 802ddfe:	3301      	adds	r3, #1
+ 802de00:	4a10      	ldr	r2, [pc, #64]	@ (802de44 <Robot_Platform_Back_Contronl_Vertical+0x1c4>)
+ 802de02:	6013      	str	r3, [r2, #0]
+				Robot_Platform_Back_Flag=2;
+ 802de04:	4b07      	ldr	r3, [pc, #28]	@ (802de24 <Robot_Platform_Back_Contronl_Vertical+0x1a4>)
+ 802de06:	2202      	movs	r2, #2
+ 802de08:	601a      	str	r2, [r3, #0]
+				Auto_Job_Back_Time_MS_Count=0;
+ 802de0a:	4b07      	ldr	r3, [pc, #28]	@ (802de28 <Robot_Platform_Back_Contronl_Vertical+0x1a8>)
+ 802de0c:	2200      	movs	r2, #0
+ 802de0e:	601a      	str	r2, [r3, #0]
+			}
+			GV.LeftMotor.Target_Velcity  =0;
+ 802de10:	4b06      	ldr	r3, [pc, #24]	@ (802de2c <Robot_Platform_Back_Contronl_Vertical+0x1ac>)
+ 802de12:	2200      	movs	r2, #0
+ 802de14:	679a      	str	r2, [r3, #120]	@ 0x78
+			GV.RightMotor.Target_Velcity =0;
+ 802de16:	4b05      	ldr	r3, [pc, #20]	@ (802de2c <Robot_Platform_Back_Contronl_Vertical+0x1ac>)
+ 802de18:	2200      	movs	r2, #0
+ 802de1a:	f8c3 20f8 	str.w	r2, [r3, #248]	@ 0xf8
+			break;
+ 802de1e:	bf00      	nop
+	}
+}
+ 802de20:	bf00      	nop
+ 802de22:	bd80      	pop	{r7, pc}
+ 802de24:	2400a6f8 	.word	0x2400a6f8
+ 802de28:	2400a6fc 	.word	0x2400a6fc
+ 802de2c:	24000340 	.word	0x24000340
+ 802de30:	2400a830 	.word	0x2400a830
+ 802de34:	2400a838 	.word	0x2400a838
+ 802de38:	2400a858 	.word	0x2400a858
+ 802de3c:	2400a6d0 	.word	0x2400a6d0
+ 802de40:	2400a848 	.word	0x2400a848
+ 802de44:	2400a79c 	.word	0x2400a79c
+
+0802de48 <Robot_Platform_Back_Contronl_Plane>:
+
+
+
+
+void Robot_Platform_Back_Contronl_Plane()
+{
+ 802de48:	b580      	push	{r7, lr}
+ 802de4a:	af00      	add	r7, sp, #0
+	switch(Robot_Platform_Back_Flag)
+ 802de4c:	4b67      	ldr	r3, [pc, #412]	@ (802dfec <Robot_Platform_Back_Contronl_Plane+0x1a4>)
+ 802de4e:	681b      	ldr	r3, [r3, #0]
+ 802de50:	2b04      	cmp	r3, #4
+ 802de52:	f200 80c9 	bhi.w	802dfe8 <Robot_Platform_Back_Contronl_Plane+0x1a0>
+ 802de56:	a201      	add	r2, pc, #4	@ (adr r2, 802de5c <Robot_Platform_Back_Contronl_Plane+0x14>)
+ 802de58:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 802de5c:	0802de71 	.word	0x0802de71
+ 802de60:	0802de87 	.word	0x0802de87
+ 802de64:	0802decf 	.word	0x0802decf
+ 802de68:	0802df35 	.word	0x0802df35
+ 802de6c:	0802df87 	.word	0x0802df87
+	{
+		case 0:
+			Platform_Back_Para_Compute_Plane();//计算后退时间及后退速度
+ 802de70:	f000 f9a2 	bl	802e1b8 <Platform_Back_Para_Compute_Plane>
+			Auto_Job_Back_Time_MS_Count=0;
+ 802de74:	4b5e      	ldr	r3, [pc, #376]	@ (802dff0 <Robot_Platform_Back_Contronl_Plane+0x1a8>)
+ 802de76:	2200      	movs	r2, #0
+ 802de78:	601a      	str	r2, [r3, #0]
+			Robot_Platform_Back_Flag++;
+ 802de7a:	4b5c      	ldr	r3, [pc, #368]	@ (802dfec <Robot_Platform_Back_Contronl_Plane+0x1a4>)
+ 802de7c:	681b      	ldr	r3, [r3, #0]
+ 802de7e:	3301      	adds	r3, #1
+ 802de80:	4a5a      	ldr	r2, [pc, #360]	@ (802dfec <Robot_Platform_Back_Contronl_Plane+0x1a4>)
+ 802de82:	6013      	str	r3, [r2, #0]
+			break;
+ 802de84:	e0b0      	b.n	802dfe8 <Robot_Platform_Back_Contronl_Plane+0x1a0>
+		case 1:
+			Auto_Job_Back_Time_MS_Count++;
+ 802de86:	4b5a      	ldr	r3, [pc, #360]	@ (802dff0 <Robot_Platform_Back_Contronl_Plane+0x1a8>)
+ 802de88:	681b      	ldr	r3, [r3, #0]
+ 802de8a:	3301      	adds	r3, #1
+ 802de8c:	4a58      	ldr	r2, [pc, #352]	@ (802dff0 <Robot_Platform_Back_Contronl_Plane+0x1a8>)
+ 802de8e:	6013      	str	r3, [r2, #0]
+			if(GV.SwingMotor.Real_Position>Left_Threshold_Pos)
+ 802de90:	4b58      	ldr	r3, [pc, #352]	@ (802dff4 <Robot_Platform_Back_Contronl_Plane+0x1ac>)
+ 802de92:	f8d3 319c 	ldr.w	r3, [r3, #412]	@ 0x19c
+ 802de96:	ee07 3a90 	vmov	s15, r3
+ 802de9a:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802de9e:	4b56      	ldr	r3, [pc, #344]	@ (802dff8 <Robot_Platform_Back_Contronl_Plane+0x1b0>)
+ 802dea0:	ed93 7b00 	vldr	d7, [r3]
+ 802dea4:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802dea8:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802deac:	dd07      	ble.n	802debe <Robot_Platform_Back_Contronl_Plane+0x76>
+			{
+				Robot_Platform_Back_Flag++;
+ 802deae:	4b4f      	ldr	r3, [pc, #316]	@ (802dfec <Robot_Platform_Back_Contronl_Plane+0x1a4>)
+ 802deb0:	681b      	ldr	r3, [r3, #0]
+ 802deb2:	3301      	adds	r3, #1
+ 802deb4:	4a4d      	ldr	r2, [pc, #308]	@ (802dfec <Robot_Platform_Back_Contronl_Plane+0x1a4>)
+ 802deb6:	6013      	str	r3, [r2, #0]
+				Auto_Job_Back_Time_MS_Count=0;
+ 802deb8:	4b4d      	ldr	r3, [pc, #308]	@ (802dff0 <Robot_Platform_Back_Contronl_Plane+0x1a8>)
+ 802deba:	2200      	movs	r2, #0
+ 802debc:	601a      	str	r2, [r3, #0]
+			}
+
+			GV.LeftMotor.Target_Velcity  =0;
+ 802debe:	4b4d      	ldr	r3, [pc, #308]	@ (802dff4 <Robot_Platform_Back_Contronl_Plane+0x1ac>)
+ 802dec0:	2200      	movs	r2, #0
+ 802dec2:	679a      	str	r2, [r3, #120]	@ 0x78
+			GV.RightMotor.Target_Velcity =0;
+ 802dec4:	4b4b      	ldr	r3, [pc, #300]	@ (802dff4 <Robot_Platform_Back_Contronl_Plane+0x1ac>)
+ 802dec6:	2200      	movs	r2, #0
+ 802dec8:	f8c3 20f8 	str.w	r2, [r3, #248]	@ 0xf8
+			break;
+ 802decc:	e08c      	b.n	802dfe8 <Robot_Platform_Back_Contronl_Plane+0x1a0>
+		case 2:
+			Auto_Job_Back_Time_MS_Count++;
+ 802dece:	4b48      	ldr	r3, [pc, #288]	@ (802dff0 <Robot_Platform_Back_Contronl_Plane+0x1a8>)
+ 802ded0:	681b      	ldr	r3, [r3, #0]
+ 802ded2:	3301      	adds	r3, #1
+ 802ded4:	4a46      	ldr	r2, [pc, #280]	@ (802dff0 <Robot_Platform_Back_Contronl_Plane+0x1a8>)
+ 802ded6:	6013      	str	r3, [r2, #0]
+			if((GV.SwingMotor.Real_Position>Left_Threshold_Pos)||(GV.SwingMotor.Real_Position<Right_Threshold_Pos))
+ 802ded8:	4b46      	ldr	r3, [pc, #280]	@ (802dff4 <Robot_Platform_Back_Contronl_Plane+0x1ac>)
+ 802deda:	f8d3 319c 	ldr.w	r3, [r3, #412]	@ 0x19c
+ 802dede:	ee07 3a90 	vmov	s15, r3
+ 802dee2:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802dee6:	4b44      	ldr	r3, [pc, #272]	@ (802dff8 <Robot_Platform_Back_Contronl_Plane+0x1b0>)
+ 802dee8:	ed93 7b00 	vldr	d7, [r3]
+ 802deec:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802def0:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802def4:	dc0e      	bgt.n	802df14 <Robot_Platform_Back_Contronl_Plane+0xcc>
+ 802def6:	4b3f      	ldr	r3, [pc, #252]	@ (802dff4 <Robot_Platform_Back_Contronl_Plane+0x1ac>)
+ 802def8:	f8d3 319c 	ldr.w	r3, [r3, #412]	@ 0x19c
+ 802defc:	ee07 3a90 	vmov	s15, r3
+ 802df00:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802df04:	4b3d      	ldr	r3, [pc, #244]	@ (802dffc <Robot_Platform_Back_Contronl_Plane+0x1b4>)
+ 802df06:	ed93 7b00 	vldr	d7, [r3]
+ 802df0a:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802df0e:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802df12:	d507      	bpl.n	802df24 <Robot_Platform_Back_Contronl_Plane+0xdc>
+			{
+				Robot_Platform_Back_Flag++;
+ 802df14:	4b35      	ldr	r3, [pc, #212]	@ (802dfec <Robot_Platform_Back_Contronl_Plane+0x1a4>)
+ 802df16:	681b      	ldr	r3, [r3, #0]
+ 802df18:	3301      	adds	r3, #1
+ 802df1a:	4a34      	ldr	r2, [pc, #208]	@ (802dfec <Robot_Platform_Back_Contronl_Plane+0x1a4>)
+ 802df1c:	6013      	str	r3, [r2, #0]
+				Auto_Job_Back_Time_MS_Count=0;
+ 802df1e:	4b34      	ldr	r3, [pc, #208]	@ (802dff0 <Robot_Platform_Back_Contronl_Plane+0x1a8>)
+ 802df20:	2200      	movs	r2, #0
+ 802df22:	601a      	str	r2, [r3, #0]
+			}
+
+			GV.LeftMotor.Target_Velcity  =0;
+ 802df24:	4b33      	ldr	r3, [pc, #204]	@ (802dff4 <Robot_Platform_Back_Contronl_Plane+0x1ac>)
+ 802df26:	2200      	movs	r2, #0
+ 802df28:	679a      	str	r2, [r3, #120]	@ 0x78
+			GV.RightMotor.Target_Velcity =0;
+ 802df2a:	4b32      	ldr	r3, [pc, #200]	@ (802dff4 <Robot_Platform_Back_Contronl_Plane+0x1ac>)
+ 802df2c:	2200      	movs	r2, #0
+ 802df2e:	f8c3 20f8 	str.w	r2, [r3, #248]	@ 0xf8
+			break;
+ 802df32:	e059      	b.n	802dfe8 <Robot_Platform_Back_Contronl_Plane+0x1a0>
+		case 3:
+			Move_Plane_Task_Backwards_Distance_Do_Update(Plane_Back_Speed_Value, CV_Robot_Deri_Angle_Deg_Plane);
+ 802df34:	4b32      	ldr	r3, [pc, #200]	@ (802e000 <Robot_Platform_Back_Contronl_Plane+0x1b8>)
+ 802df36:	ed93 7b00 	vldr	d7, [r3]
+ 802df3a:	4b32      	ldr	r3, [pc, #200]	@ (802e004 <Robot_Platform_Back_Contronl_Plane+0x1bc>)
+ 802df3c:	ed93 6b00 	vldr	d6, [r3]
+ 802df40:	eeb0 1b46 	vmov.f64	d1, d6
+ 802df44:	eeb0 0b47 	vmov.f64	d0, d7
+ 802df48:	f7fe fd86 	bl	802ca58 <Move_Plane_Task_Backwards_Distance_Do_Update>
+			Auto_Job_Back_Time_MS_Count++;
+ 802df4c:	4b28      	ldr	r3, [pc, #160]	@ (802dff0 <Robot_Platform_Back_Contronl_Plane+0x1a8>)
+ 802df4e:	681b      	ldr	r3, [r3, #0]
+ 802df50:	3301      	adds	r3, #1
+ 802df52:	4a27      	ldr	r2, [pc, #156]	@ (802dff0 <Robot_Platform_Back_Contronl_Plane+0x1a8>)
+ 802df54:	6013      	str	r3, [r2, #0]
+			if(Auto_Job_Back_Time_MS_Count>Auto_Job_Back_Time_MS_Horizontal)
+ 802df56:	4b26      	ldr	r3, [pc, #152]	@ (802dff0 <Robot_Platform_Back_Contronl_Plane+0x1a8>)
+ 802df58:	681b      	ldr	r3, [r3, #0]
+ 802df5a:	ee07 3a90 	vmov	s15, r3
+ 802df5e:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802df62:	4b29      	ldr	r3, [pc, #164]	@ (802e008 <Robot_Platform_Back_Contronl_Plane+0x1c0>)
+ 802df64:	ed93 7b00 	vldr	d7, [r3]
+ 802df68:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802df6c:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802df70:	dc00      	bgt.n	802df74 <Robot_Platform_Back_Contronl_Plane+0x12c>
+			{
+				Robot_Platform_Back_Flag++;
+				Auto_Job_Back_Time_MS_Count=0;
+			}
+			break;
+ 802df72:	e039      	b.n	802dfe8 <Robot_Platform_Back_Contronl_Plane+0x1a0>
+				Robot_Platform_Back_Flag++;
+ 802df74:	4b1d      	ldr	r3, [pc, #116]	@ (802dfec <Robot_Platform_Back_Contronl_Plane+0x1a4>)
+ 802df76:	681b      	ldr	r3, [r3, #0]
+ 802df78:	3301      	adds	r3, #1
+ 802df7a:	4a1c      	ldr	r2, [pc, #112]	@ (802dfec <Robot_Platform_Back_Contronl_Plane+0x1a4>)
+ 802df7c:	6013      	str	r3, [r2, #0]
+				Auto_Job_Back_Time_MS_Count=0;
+ 802df7e:	4b1c      	ldr	r3, [pc, #112]	@ (802dff0 <Robot_Platform_Back_Contronl_Plane+0x1a8>)
+ 802df80:	2200      	movs	r2, #0
+ 802df82:	601a      	str	r2, [r3, #0]
+			break;
+ 802df84:	e030      	b.n	802dfe8 <Robot_Platform_Back_Contronl_Plane+0x1a0>
+		case 4:
+			if((GV.SwingMotor.Real_Position<Left_Threshold_Pos)&&(GV.SwingMotor.Real_Position>Right_Threshold_Pos))
+ 802df86:	4b1b      	ldr	r3, [pc, #108]	@ (802dff4 <Robot_Platform_Back_Contronl_Plane+0x1ac>)
+ 802df88:	f8d3 319c 	ldr.w	r3, [r3, #412]	@ 0x19c
+ 802df8c:	ee07 3a90 	vmov	s15, r3
+ 802df90:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802df94:	4b18      	ldr	r3, [pc, #96]	@ (802dff8 <Robot_Platform_Back_Contronl_Plane+0x1b0>)
+ 802df96:	ed93 7b00 	vldr	d7, [r3]
+ 802df9a:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802df9e:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802dfa2:	d519      	bpl.n	802dfd8 <Robot_Platform_Back_Contronl_Plane+0x190>
+ 802dfa4:	4b13      	ldr	r3, [pc, #76]	@ (802dff4 <Robot_Platform_Back_Contronl_Plane+0x1ac>)
+ 802dfa6:	f8d3 319c 	ldr.w	r3, [r3, #412]	@ 0x19c
+ 802dfaa:	ee07 3a90 	vmov	s15, r3
+ 802dfae:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802dfb2:	4b12      	ldr	r3, [pc, #72]	@ (802dffc <Robot_Platform_Back_Contronl_Plane+0x1b4>)
+ 802dfb4:	ed93 7b00 	vldr	d7, [r3]
+ 802dfb8:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802dfbc:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802dfc0:	dd0a      	ble.n	802dfd8 <Robot_Platform_Back_Contronl_Plane+0x190>
+			{
+				Backward_Num_X_Count++;
+ 802dfc2:	4b12      	ldr	r3, [pc, #72]	@ (802e00c <Robot_Platform_Back_Contronl_Plane+0x1c4>)
+ 802dfc4:	681b      	ldr	r3, [r3, #0]
+ 802dfc6:	3301      	adds	r3, #1
+ 802dfc8:	4a10      	ldr	r2, [pc, #64]	@ (802e00c <Robot_Platform_Back_Contronl_Plane+0x1c4>)
+ 802dfca:	6013      	str	r3, [r2, #0]
+				Robot_Platform_Back_Flag=2;
+ 802dfcc:	4b07      	ldr	r3, [pc, #28]	@ (802dfec <Robot_Platform_Back_Contronl_Plane+0x1a4>)
+ 802dfce:	2202      	movs	r2, #2
+ 802dfd0:	601a      	str	r2, [r3, #0]
+				Auto_Job_Back_Time_MS_Count=0;
+ 802dfd2:	4b07      	ldr	r3, [pc, #28]	@ (802dff0 <Robot_Platform_Back_Contronl_Plane+0x1a8>)
+ 802dfd4:	2200      	movs	r2, #0
+ 802dfd6:	601a      	str	r2, [r3, #0]
+			}
+
+			GV.LeftMotor.Target_Velcity  =0;
+ 802dfd8:	4b06      	ldr	r3, [pc, #24]	@ (802dff4 <Robot_Platform_Back_Contronl_Plane+0x1ac>)
+ 802dfda:	2200      	movs	r2, #0
+ 802dfdc:	679a      	str	r2, [r3, #120]	@ 0x78
+			GV.RightMotor.Target_Velcity =0;
+ 802dfde:	4b05      	ldr	r3, [pc, #20]	@ (802dff4 <Robot_Platform_Back_Contronl_Plane+0x1ac>)
+ 802dfe0:	2200      	movs	r2, #0
+ 802dfe2:	f8c3 20f8 	str.w	r2, [r3, #248]	@ 0xf8
+			break;
+ 802dfe6:	bf00      	nop
+	}
+}
+ 802dfe8:	bf00      	nop
+ 802dfea:	bd80      	pop	{r7, pc}
+ 802dfec:	2400a6f8 	.word	0x2400a6f8
+ 802dff0:	2400a6fc 	.word	0x2400a6fc
+ 802dff4:	24000340 	.word	0x24000340
+ 802dff8:	2400a830 	.word	0x2400a830
+ 802dffc:	2400a838 	.word	0x2400a838
+ 802e000:	2400a860 	.word	0x2400a860
+ 802e004:	2400a6d8 	.word	0x2400a6d8
+ 802e008:	2400a840 	.word	0x2400a840
+ 802e00c:	2400a79c 	.word	0x2400a79c
+
+0802e010 <Platform_Back_Para_Compute_Horizontal>:
+
+
+
+
+void Platform_Back_Para_Compute_Horizontal()
+{
+ 802e010:	b480      	push	{r7}
+ 802e012:	b085      	sub	sp, #20
+ 802e014:	af00      	add	r7, sp, #0
+	Auto_Job_Back_Time_MS_Horizontal=(5.0/((double)GV_Swing_Speed)*1000+250)*1.025;//5的含义为，摆臂期望角度为90，在85度的时候就要开始后退。
+ 802e016:	4b30      	ldr	r3, [pc, #192]	@ (802e0d8 <Platform_Back_Para_Compute_Horizontal+0xc8>)
+ 802e018:	681b      	ldr	r3, [r3, #0]
+ 802e01a:	ee07 3a90 	vmov	s15, r3
+ 802e01e:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802e022:	eeb1 5b04 	vmov.f64	d5, #20	@ 0x40a00000  5.0
+ 802e026:	ee85 7b06 	vdiv.f64	d7, d5, d6
+ 802e02a:	ed9f 6b1f 	vldr	d6, [pc, #124]	@ 802e0a8 <Platform_Back_Para_Compute_Horizontal+0x98>
+ 802e02e:	ee27 7b06 	vmul.f64	d7, d7, d6
+ 802e032:	ed9f 6b1f 	vldr	d6, [pc, #124]	@ 802e0b0 <Platform_Back_Para_Compute_Horizontal+0xa0>
+ 802e036:	ee37 7b06 	vadd.f64	d7, d7, d6
+ 802e03a:	ed9f 6b1f 	vldr	d6, [pc, #124]	@ 802e0b8 <Platform_Back_Para_Compute_Horizontal+0xa8>
+ 802e03e:	ee27 7b06 	vmul.f64	d7, d7, d6
+ 802e042:	4b26      	ldr	r3, [pc, #152]	@ (802e0dc <Platform_Back_Para_Compute_Horizontal+0xcc>)
+ 802e044:	ed83 7b00 	vstr	d7, [r3]
+	double Speed_Base=201.7*7.64;//其中201.7为电机1m/°的速度值//201.7*7.64（）为天太电机1m/min的数据，以该数据为基础进行1/2/3/4/5/6/7/8/9/14m/min
+ 802e048:	a31d      	add	r3, pc, #116	@ (adr r3, 802e0c0 <Platform_Back_Para_Compute_Horizontal+0xb0>)
+ 802e04a:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802e04e:	e9c7 2302 	strd	r2, r3, [r7, #8]
+	double Deg_Sencend_Compute=((double)GV_Robot_Back_Distance)/100/(Auto_Job_Back_Time_MS_Horizontal/1000)*60;
+ 802e052:	4b23      	ldr	r3, [pc, #140]	@ (802e0e0 <Platform_Back_Para_Compute_Horizontal+0xd0>)
+ 802e054:	ed93 7b00 	vldr	d7, [r3]
+ 802e058:	ed9f 6b1b 	vldr	d6, [pc, #108]	@ 802e0c8 <Platform_Back_Para_Compute_Horizontal+0xb8>
+ 802e05c:	ee87 5b06 	vdiv.f64	d5, d7, d6
+ 802e060:	4b1e      	ldr	r3, [pc, #120]	@ (802e0dc <Platform_Back_Para_Compute_Horizontal+0xcc>)
+ 802e062:	ed93 7b00 	vldr	d7, [r3]
+ 802e066:	ed9f 4b10 	vldr	d4, [pc, #64]	@ 802e0a8 <Platform_Back_Para_Compute_Horizontal+0x98>
+ 802e06a:	ee87 6b04 	vdiv.f64	d6, d7, d4
+ 802e06e:	ee85 7b06 	vdiv.f64	d7, d5, d6
+ 802e072:	ed9f 6b17 	vldr	d6, [pc, #92]	@ 802e0d0 <Platform_Back_Para_Compute_Horizontal+0xc0>
+ 802e076:	ee27 7b06 	vmul.f64	d7, d7, d6
+ 802e07a:	ed87 7b00 	vstr	d7, [r7]
+	Horizontal_Back_Speed_Value=Deg_Sencend_Compute*Speed_Base/2;
+ 802e07e:	ed97 6b00 	vldr	d6, [r7]
+ 802e082:	ed97 7b02 	vldr	d7, [r7, #8]
+ 802e086:	ee26 6b07 	vmul.f64	d6, d6, d7
+ 802e08a:	eeb0 5b00 	vmov.f64	d5, #0	@ 0x40000000  2.0
+ 802e08e:	ee86 7b05 	vdiv.f64	d7, d6, d5
+ 802e092:	4b14      	ldr	r3, [pc, #80]	@ (802e0e4 <Platform_Back_Para_Compute_Horizontal+0xd4>)
+ 802e094:	ed83 7b00 	vstr	d7, [r3]
+}
+ 802e098:	bf00      	nop
+ 802e09a:	3714      	adds	r7, #20
+ 802e09c:	46bd      	mov	sp, r7
+ 802e09e:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 802e0a2:	4770      	bx	lr
+ 802e0a4:	f3af 8000 	nop.w
+ 802e0a8:	00000000 	.word	0x00000000
+ 802e0ac:	408f4000 	.word	0x408f4000
+ 802e0b0:	00000000 	.word	0x00000000
+ 802e0b4:	406f4000 	.word	0x406f4000
+ 802e0b8:	66666666 	.word	0x66666666
+ 802e0bc:	3ff06666 	.word	0x3ff06666
+ 802e0c0:	b645a1ca 	.word	0xb645a1ca
+ 802e0c4:	409813f3 	.word	0x409813f3
+ 802e0c8:	00000000 	.word	0x00000000
+ 802e0cc:	40590000 	.word	0x40590000
+ 802e0d0:	00000000 	.word	0x00000000
+ 802e0d4:	404e0000 	.word	0x404e0000
+ 802e0d8:	2400a710 	.word	0x2400a710
+ 802e0dc:	2400a840 	.word	0x2400a840
+ 802e0e0:	2400a728 	.word	0x2400a728
+ 802e0e4:	2400a850 	.word	0x2400a850
+
+0802e0e8 <Platform_Back_Para_Compute_Vertical>:
+
+void Platform_Back_Para_Compute_Vertical()
+{
+ 802e0e8:	b480      	push	{r7}
+ 802e0ea:	b085      	sub	sp, #20
+ 802e0ec:	af00      	add	r7, sp, #0
+	Auto_Job_Back_Time_MS_Vertical=(5.0/((double)GV_Swing_Speed)*1000+100)*1.025;//5的含义为，摆臂期望角度为90，在85度的时候就要开始后退。
+ 802e0ee:	4b2e      	ldr	r3, [pc, #184]	@ (802e1a8 <Platform_Back_Para_Compute_Vertical+0xc0>)
+ 802e0f0:	681b      	ldr	r3, [r3, #0]
+ 802e0f2:	ee07 3a90 	vmov	s15, r3
+ 802e0f6:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802e0fa:	eeb1 5b04 	vmov.f64	d5, #20	@ 0x40a00000  5.0
+ 802e0fe:	ee85 7b06 	vdiv.f64	d7, d5, d6
+ 802e102:	ed9f 6b1f 	vldr	d6, [pc, #124]	@ 802e180 <Platform_Back_Para_Compute_Vertical+0x98>
+ 802e106:	ee27 7b06 	vmul.f64	d7, d7, d6
+ 802e10a:	ed9f 6b1f 	vldr	d6, [pc, #124]	@ 802e188 <Platform_Back_Para_Compute_Vertical+0xa0>
+ 802e10e:	ee37 7b06 	vadd.f64	d7, d7, d6
+ 802e112:	ed9f 6b1f 	vldr	d6, [pc, #124]	@ 802e190 <Platform_Back_Para_Compute_Vertical+0xa8>
+ 802e116:	ee27 7b06 	vmul.f64	d7, d7, d6
+ 802e11a:	4b24      	ldr	r3, [pc, #144]	@ (802e1ac <Platform_Back_Para_Compute_Vertical+0xc4>)
+ 802e11c:	ed83 7b00 	vstr	d7, [r3]
+	double Speed_Base=201.7*7.64;//其中201.7为电机1m/°的速度值//201.7*7.64（）为天太电机1m/min的数据，以该数据为基础进行1/2/3/4/5/6/7/8/9/14m/min
+ 802e120:	a31d      	add	r3, pc, #116	@ (adr r3, 802e198 <Platform_Back_Para_Compute_Vertical+0xb0>)
+ 802e122:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802e126:	e9c7 2302 	strd	r2, r3, [r7, #8]
+	double Deg_Sencend_Compute=((double)GV_Robot_Back_Distance)/100/(Auto_Job_Back_Time_MS_Vertical/1000)*60;
+ 802e12a:	4b21      	ldr	r3, [pc, #132]	@ (802e1b0 <Platform_Back_Para_Compute_Vertical+0xc8>)
+ 802e12c:	ed93 7b00 	vldr	d7, [r3]
+ 802e130:	ed9f 6b15 	vldr	d6, [pc, #84]	@ 802e188 <Platform_Back_Para_Compute_Vertical+0xa0>
+ 802e134:	ee87 5b06 	vdiv.f64	d5, d7, d6
+ 802e138:	4b1c      	ldr	r3, [pc, #112]	@ (802e1ac <Platform_Back_Para_Compute_Vertical+0xc4>)
+ 802e13a:	ed93 7b00 	vldr	d7, [r3]
+ 802e13e:	ed9f 4b10 	vldr	d4, [pc, #64]	@ 802e180 <Platform_Back_Para_Compute_Vertical+0x98>
+ 802e142:	ee87 6b04 	vdiv.f64	d6, d7, d4
+ 802e146:	ee85 7b06 	vdiv.f64	d7, d5, d6
+ 802e14a:	ed9f 6b15 	vldr	d6, [pc, #84]	@ 802e1a0 <Platform_Back_Para_Compute_Vertical+0xb8>
+ 802e14e:	ee27 7b06 	vmul.f64	d7, d7, d6
+ 802e152:	ed87 7b00 	vstr	d7, [r7]
+	Vertical_Back_Speed_Value=Deg_Sencend_Compute*Speed_Base/2;
+ 802e156:	ed97 6b00 	vldr	d6, [r7]
+ 802e15a:	ed97 7b02 	vldr	d7, [r7, #8]
+ 802e15e:	ee26 6b07 	vmul.f64	d6, d6, d7
+ 802e162:	eeb0 5b00 	vmov.f64	d5, #0	@ 0x40000000  2.0
+ 802e166:	ee86 7b05 	vdiv.f64	d7, d6, d5
+ 802e16a:	4b12      	ldr	r3, [pc, #72]	@ (802e1b4 <Platform_Back_Para_Compute_Vertical+0xcc>)
+ 802e16c:	ed83 7b00 	vstr	d7, [r3]
+}
+ 802e170:	bf00      	nop
+ 802e172:	3714      	adds	r7, #20
+ 802e174:	46bd      	mov	sp, r7
+ 802e176:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 802e17a:	4770      	bx	lr
+ 802e17c:	f3af 8000 	nop.w
+ 802e180:	00000000 	.word	0x00000000
+ 802e184:	408f4000 	.word	0x408f4000
+ 802e188:	00000000 	.word	0x00000000
+ 802e18c:	40590000 	.word	0x40590000
+ 802e190:	66666666 	.word	0x66666666
+ 802e194:	3ff06666 	.word	0x3ff06666
+ 802e198:	b645a1ca 	.word	0xb645a1ca
+ 802e19c:	409813f3 	.word	0x409813f3
+ 802e1a0:	00000000 	.word	0x00000000
+ 802e1a4:	404e0000 	.word	0x404e0000
+ 802e1a8:	2400a710 	.word	0x2400a710
+ 802e1ac:	2400a848 	.word	0x2400a848
+ 802e1b0:	2400a728 	.word	0x2400a728
+ 802e1b4:	2400a858 	.word	0x2400a858
+
+0802e1b8 <Platform_Back_Para_Compute_Plane>:
+
+
+
+
+void Platform_Back_Para_Compute_Plane()
+{
+ 802e1b8:	b480      	push	{r7}
+ 802e1ba:	b085      	sub	sp, #20
+ 802e1bc:	af00      	add	r7, sp, #0
+	Auto_Job_Back_Time_MS_Horizontal=5.0/((double)GV_Swing_Speed)*1000;//5的含义为，摆臂期望角度为90，在85度的时候就要开始后退。
+ 802e1be:	4b28      	ldr	r3, [pc, #160]	@ (802e260 <Platform_Back_Para_Compute_Plane+0xa8>)
+ 802e1c0:	681b      	ldr	r3, [r3, #0]
+ 802e1c2:	ee07 3a90 	vmov	s15, r3
+ 802e1c6:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802e1ca:	eeb1 5b04 	vmov.f64	d5, #20	@ 0x40a00000  5.0
+ 802e1ce:	ee85 7b06 	vdiv.f64	d7, d5, d6
+ 802e1d2:	ed9f 6b1b 	vldr	d6, [pc, #108]	@ 802e240 <Platform_Back_Para_Compute_Plane+0x88>
+ 802e1d6:	ee27 7b06 	vmul.f64	d7, d7, d6
+ 802e1da:	4b22      	ldr	r3, [pc, #136]	@ (802e264 <Platform_Back_Para_Compute_Plane+0xac>)
+ 802e1dc:	ed83 7b00 	vstr	d7, [r3]
+	double Speed_Base=201.7*7.64;//其中201.7为电机1m/°的速度值//201.7*7.64（）为天太电机1m/min的数据，以该数据为基础进行1/2/3/4/5/6/7/8/9/14m/min
+ 802e1e0:	a319      	add	r3, pc, #100	@ (adr r3, 802e248 <Platform_Back_Para_Compute_Plane+0x90>)
+ 802e1e2:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802e1e6:	e9c7 2302 	strd	r2, r3, [r7, #8]
+	double Deg_Sencend_Compute=((double)GV_Robot_Back_Distance)/100/(Auto_Job_Back_Time_MS_Horizontal/1000)*60;
+ 802e1ea:	4b1f      	ldr	r3, [pc, #124]	@ (802e268 <Platform_Back_Para_Compute_Plane+0xb0>)
+ 802e1ec:	ed93 7b00 	vldr	d7, [r3]
+ 802e1f0:	ed9f 6b17 	vldr	d6, [pc, #92]	@ 802e250 <Platform_Back_Para_Compute_Plane+0x98>
+ 802e1f4:	ee87 5b06 	vdiv.f64	d5, d7, d6
+ 802e1f8:	4b1a      	ldr	r3, [pc, #104]	@ (802e264 <Platform_Back_Para_Compute_Plane+0xac>)
+ 802e1fa:	ed93 7b00 	vldr	d7, [r3]
+ 802e1fe:	ed9f 4b10 	vldr	d4, [pc, #64]	@ 802e240 <Platform_Back_Para_Compute_Plane+0x88>
+ 802e202:	ee87 6b04 	vdiv.f64	d6, d7, d4
+ 802e206:	ee85 7b06 	vdiv.f64	d7, d5, d6
+ 802e20a:	ed9f 6b13 	vldr	d6, [pc, #76]	@ 802e258 <Platform_Back_Para_Compute_Plane+0xa0>
+ 802e20e:	ee27 7b06 	vmul.f64	d7, d7, d6
+ 802e212:	ed87 7b00 	vstr	d7, [r7]
+	//计算单位1m/min=1000/60=16.67mm/s
+//	double Deg_Sencend_Compute=MM_Senct/16.67;
+	Plane_Back_Speed_Value=Deg_Sencend_Compute*Speed_Base/2;
+ 802e216:	ed97 6b00 	vldr	d6, [r7]
+ 802e21a:	ed97 7b02 	vldr	d7, [r7, #8]
+ 802e21e:	ee26 6b07 	vmul.f64	d6, d6, d7
+ 802e222:	eeb0 5b00 	vmov.f64	d5, #0	@ 0x40000000  2.0
+ 802e226:	ee86 7b05 	vdiv.f64	d7, d6, d5
+ 802e22a:	4b10      	ldr	r3, [pc, #64]	@ (802e26c <Platform_Back_Para_Compute_Plane+0xb4>)
+ 802e22c:	ed83 7b00 	vstr	d7, [r3]
+}
+ 802e230:	bf00      	nop
+ 802e232:	3714      	adds	r7, #20
+ 802e234:	46bd      	mov	sp, r7
+ 802e236:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 802e23a:	4770      	bx	lr
+ 802e23c:	f3af 8000 	nop.w
+ 802e240:	00000000 	.word	0x00000000
+ 802e244:	408f4000 	.word	0x408f4000
+ 802e248:	b645a1ca 	.word	0xb645a1ca
+ 802e24c:	409813f3 	.word	0x409813f3
+ 802e250:	00000000 	.word	0x00000000
+ 802e254:	40590000 	.word	0x40590000
+ 802e258:	00000000 	.word	0x00000000
+ 802e25c:	404e0000 	.word	0x404e0000
+ 802e260:	2400a710 	.word	0x2400a710
+ 802e264:	2400a840 	.word	0x2400a840
+ 802e268:	2400a728 	.word	0x2400a728
+ 802e26c:	2400a860 	.word	0x2400a860
+
+0802e270 <IV_control_1>:
+
+	IV.Is_Online=P_MK32->IsOnline;
+}
+
+void IV_control_1()
+{
+ 802e270:	b580      	push	{r7, lr}
+ 802e272:	af00      	add	r7, sp, #0
+	IV.Robot_Gyro = Robot_Angle_G_P_Deg;
+ 802e274:	4b45      	ldr	r3, [pc, #276]	@ (802e38c <IV_control_1+0x11c>)
+ 802e276:	ed93 7b00 	vldr	d7, [r3]
+ 802e27a:	eefd 7bc7 	vcvt.s32.f64	s15, d7
+ 802e27e:	ee17 2a90 	vmov	r2, s15
+ 802e282:	4b43      	ldr	r3, [pc, #268]	@ (802e390 <IV_control_1+0x120>)
+ 802e284:	60da      	str	r2, [r3, #12]
+//	IV.RunMode = IV_MCU_Run_State;
+	IV.LeftCompensation = GV.Left_Compensation;
+ 802e286:	4b43      	ldr	r3, [pc, #268]	@ (802e394 <IV_control_1+0x124>)
+ 802e288:	681b      	ldr	r3, [r3, #0]
+ 802e28a:	4a41      	ldr	r2, [pc, #260]	@ (802e390 <IV_control_1+0x120>)
+ 802e28c:	6013      	str	r3, [r2, #0]
+	IV.RightCompensation = GV.Right_Compensation;
+ 802e28e:	4b41      	ldr	r3, [pc, #260]	@ (802e394 <IV_control_1+0x124>)
+ 802e290:	685b      	ldr	r3, [r3, #4]
+ 802e292:	4a3f      	ldr	r2, [pc, #252]	@ (802e390 <IV_control_1+0x120>)
+ 802e294:	6053      	str	r3, [r2, #4]
+//	IV.CurrentAngle = GV.Robot_Angle;
+	if(GV.LeftMotor.Target_Velcity>0)
+ 802e296:	4b3f      	ldr	r3, [pc, #252]	@ (802e394 <IV_control_1+0x124>)
+ 802e298:	6f9b      	ldr	r3, [r3, #120]	@ 0x78
+ 802e29a:	2b00      	cmp	r3, #0
+ 802e29c:	dd16      	ble.n	802e2cc <IV_control_1+0x5c>
+	{
+		IV.Robot_Move_Deri_Speed = (int)(((double)GV.LeftMotor.Target_Velcity)/Move_Base_Speed_Count_Meter_Min*10)+1;
+ 802e29e:	4b3d      	ldr	r3, [pc, #244]	@ (802e394 <IV_control_1+0x124>)
+ 802e2a0:	6f9b      	ldr	r3, [r3, #120]	@ 0x78
+ 802e2a2:	ee07 3a90 	vmov	s15, r3
+ 802e2a6:	eeb8 5be7 	vcvt.f64.s32	d5, s15
+ 802e2aa:	4b3b      	ldr	r3, [pc, #236]	@ (802e398 <IV_control_1+0x128>)
+ 802e2ac:	ed93 6b00 	vldr	d6, [r3]
+ 802e2b0:	ee85 7b06 	vdiv.f64	d7, d5, d6
+ 802e2b4:	eeb2 6b04 	vmov.f64	d6, #36	@ 0x41200000  10.0
+ 802e2b8:	ee27 7b06 	vmul.f64	d7, d7, d6
+ 802e2bc:	eefd 7bc7 	vcvt.s32.f64	s15, d7
+ 802e2c0:	ee17 3a90 	vmov	r3, s15
+ 802e2c4:	3301      	adds	r3, #1
+ 802e2c6:	4a32      	ldr	r2, [pc, #200]	@ (802e390 <IV_control_1+0x120>)
+ 802e2c8:	6093      	str	r3, [r2, #8]
+ 802e2ca:	e01d      	b.n	802e308 <IV_control_1+0x98>
+	}
+	else if(GV.LeftMotor.Target_Velcity<0)
+ 802e2cc:	4b31      	ldr	r3, [pc, #196]	@ (802e394 <IV_control_1+0x124>)
+ 802e2ce:	6f9b      	ldr	r3, [r3, #120]	@ 0x78
+ 802e2d0:	2b00      	cmp	r3, #0
+ 802e2d2:	da16      	bge.n	802e302 <IV_control_1+0x92>
+	{
+		IV.Robot_Move_Deri_Speed = (int)(((double)GV.LeftMotor.Target_Velcity)/Move_Base_Speed_Count_Meter_Min*10)-1;
+ 802e2d4:	4b2f      	ldr	r3, [pc, #188]	@ (802e394 <IV_control_1+0x124>)
+ 802e2d6:	6f9b      	ldr	r3, [r3, #120]	@ 0x78
+ 802e2d8:	ee07 3a90 	vmov	s15, r3
+ 802e2dc:	eeb8 5be7 	vcvt.f64.s32	d5, s15
+ 802e2e0:	4b2d      	ldr	r3, [pc, #180]	@ (802e398 <IV_control_1+0x128>)
+ 802e2e2:	ed93 6b00 	vldr	d6, [r3]
+ 802e2e6:	ee85 7b06 	vdiv.f64	d7, d5, d6
+ 802e2ea:	eeb2 6b04 	vmov.f64	d6, #36	@ 0x41200000  10.0
+ 802e2ee:	ee27 7b06 	vmul.f64	d7, d7, d6
+ 802e2f2:	eefd 7bc7 	vcvt.s32.f64	s15, d7
+ 802e2f6:	ee17 3a90 	vmov	r3, s15
+ 802e2fa:	3b01      	subs	r3, #1
+ 802e2fc:	4a24      	ldr	r2, [pc, #144]	@ (802e390 <IV_control_1+0x120>)
+ 802e2fe:	6093      	str	r3, [r2, #8]
+ 802e300:	e002      	b.n	802e308 <IV_control_1+0x98>
+	}
+	else
+	{
+		IV.Robot_Move_Deri_Speed =0;
+ 802e302:	4b23      	ldr	r3, [pc, #140]	@ (802e390 <IV_control_1+0x120>)
+ 802e304:	2200      	movs	r2, #0
+ 802e306:	609a      	str	r2, [r3, #8]
+	}
+	//IV.Robot_Move_Deri_Speed = (int)(((double)GV.LeftMotor.Target_Velcity)/Move_Base_Speed_Count_Meter_Min*10)+1;
+	IV.SystemError= GV.SystemErrorData.ErrorCode;
+ 802e308:	4b22      	ldr	r3, [pc, #136]	@ (802e394 <IV_control_1+0x124>)
+ 802e30a:	f8d3 3240 	ldr.w	r3, [r3, #576]	@ 0x240
+ 802e30e:	4a20      	ldr	r2, [pc, #128]	@ (802e390 <IV_control_1+0x120>)
+ 802e310:	6153      	str	r3, [r2, #20]
+	IV.SystemError=(IV.SystemError&0xe7f);   //1110 0111 1111
+ 802e312:	4b1f      	ldr	r3, [pc, #124]	@ (802e390 <IV_control_1+0x120>)
+ 802e314:	695a      	ldr	r2, [r3, #20]
+ 802e316:	f640 637f 	movw	r3, #3711	@ 0xe7f
+ 802e31a:	4013      	ands	r3, r2
+ 802e31c:	4a1c      	ldr	r2, [pc, #112]	@ (802e390 <IV_control_1+0x120>)
+ 802e31e:	6153      	str	r3, [r2, #20]
+	IV.Left_Motor_Err= GV.LeftMotor.TT_Motor_Fault;
+ 802e320:	4b1c      	ldr	r3, [pc, #112]	@ (802e394 <IV_control_1+0x124>)
+ 802e322:	f8d3 30ac 	ldr.w	r3, [r3, #172]	@ 0xac
+ 802e326:	4a1a      	ldr	r2, [pc, #104]	@ (802e390 <IV_control_1+0x120>)
+ 802e328:	6193      	str	r3, [r2, #24]
+	IV.Right_Motor_Err= GV.RightMotor.TT_Motor_Fault;
+ 802e32a:	4b1a      	ldr	r3, [pc, #104]	@ (802e394 <IV_control_1+0x124>)
+ 802e32c:	f8d3 312c 	ldr.w	r3, [r3, #300]	@ 0x12c
+ 802e330:	4a17      	ldr	r2, [pc, #92]	@ (802e390 <IV_control_1+0x120>)
+ 802e332:	61d3      	str	r3, [r2, #28]
+	IV.Swing_Motor_Err= GV.SwingMotor.TT_Motor_Fault;
+ 802e334:	4b17      	ldr	r3, [pc, #92]	@ (802e394 <IV_control_1+0x124>)
+ 802e336:	f8d3 31ac 	ldr.w	r3, [r3, #428]	@ 0x1ac
+ 802e33a:	4a15      	ldr	r2, [pc, #84]	@ (802e390 <IV_control_1+0x120>)
+ 802e33c:	6213      	str	r3, [r2, #32]
+	IV.Distance_Sensor=-GV.Force_Value_mN.CMCU_Measuring_value*10;
+ 802e33e:	4b15      	ldr	r3, [pc, #84]	@ (802e394 <IV_control_1+0x124>)
+ 802e340:	f8d3 328c 	ldr.w	r3, [r3, #652]	@ 0x28c
+ 802e344:	f06f 0209 	mvn.w	r2, #9
+ 802e348:	fb02 f303 	mul.w	r3, r2, r3
+ 802e34c:	4a10      	ldr	r2, [pc, #64]	@ (802e390 <IV_control_1+0x120>)
+ 802e34e:	6113      	str	r3, [r2, #16]
+	IV.Is_Online=P_MK32->IsOnline;
+ 802e350:	4b12      	ldr	r3, [pc, #72]	@ (802e39c <IV_control_1+0x12c>)
+ 802e352:	681b      	ldr	r3, [r3, #0]
+ 802e354:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
+ 802e356:	4a0e      	ldr	r2, [pc, #56]	@ (802e390 <IV_control_1+0x120>)
+ 802e358:	6253      	str	r3, [r2, #36]	@ 0x24
+
+	//只要有报错码就关喷砂机，没有的错的话再根据按键开喷砂机
+	if(((IV.SystemError!=0)&&(IV.SystemError!=2))||(IV.Left_Motor_Err!=0)||(IV.Right_Motor_Err!=0)||(IV.Swing_Motor_Err!=0))
+ 802e35a:	4b0d      	ldr	r3, [pc, #52]	@ (802e390 <IV_control_1+0x120>)
+ 802e35c:	695b      	ldr	r3, [r3, #20]
+ 802e35e:	2b00      	cmp	r3, #0
+ 802e360:	d003      	beq.n	802e36a <IV_control_1+0xfa>
+ 802e362:	4b0b      	ldr	r3, [pc, #44]	@ (802e390 <IV_control_1+0x120>)
+ 802e364:	695b      	ldr	r3, [r3, #20]
+ 802e366:	2b02      	cmp	r3, #2
+ 802e368:	d10b      	bne.n	802e382 <IV_control_1+0x112>
+ 802e36a:	4b09      	ldr	r3, [pc, #36]	@ (802e390 <IV_control_1+0x120>)
+ 802e36c:	699b      	ldr	r3, [r3, #24]
+ 802e36e:	2b00      	cmp	r3, #0
+ 802e370:	d107      	bne.n	802e382 <IV_control_1+0x112>
+ 802e372:	4b07      	ldr	r3, [pc, #28]	@ (802e390 <IV_control_1+0x120>)
+ 802e374:	69db      	ldr	r3, [r3, #28]
+ 802e376:	2b00      	cmp	r3, #0
+ 802e378:	d103      	bne.n	802e382 <IV_control_1+0x112>
+ 802e37a:	4b05      	ldr	r3, [pc, #20]	@ (802e390 <IV_control_1+0x120>)
+ 802e37c:	6a1b      	ldr	r3, [r3, #32]
+ 802e37e:	2b00      	cmp	r3, #0
+ 802e380:	d001      	beq.n	802e386 <IV_control_1+0x116>
+	{
+		Blast_Machine_Close_Fun();
+ 802e382:	f7f8 f91d 	bl	80265c0 <Blast_Machine_Close_Fun>
+	}
+}
+ 802e386:	bf00      	nop
+ 802e388:	bd80      	pop	{r7, pc}
+ 802e38a:	bf00      	nop
+ 802e38c:	2400a780 	.word	0x2400a780
+ 802e390:	240005e0 	.word	0x240005e0
+ 802e394:	24000340 	.word	0x24000340
+ 802e398:	240000a0 	.word	0x240000a0
+ 802e39c:	2400a3f8 	.word	0x2400a3f8
+
+0802e3a0 <PV_Data_Reading>:
+
+
+
+
+void PV_Data_Reading()
+{
+ 802e3a0:	b480      	push	{r7}
+ 802e3a2:	af00      	add	r7, sp, #0
+//	  int32 Robot_Length_Homework=13;                  //自动模式下的作业长度
+//    int32 Robot_Width_Homework=14;                   //自动模式下的作业宽度
+
+//	GV_Swing_Range_Angle=(int)CV.PV.Robot_Operation_Mode;                        // 1
+
+	GV_Robot_Move_Speed=(int)CV.PV.Robot_Move_Speed;                             // 2
+ 802e3a4:	4b2c      	ldr	r3, [pc, #176]	@ (802e458 <PV_Data_Reading+0xb8>)
+ 802e3a6:	689b      	ldr	r3, [r3, #8]
+ 802e3a8:	4a2c      	ldr	r2, [pc, #176]	@ (802e45c <PV_Data_Reading+0xbc>)
+ 802e3aa:	6013      	str	r3, [r2, #0]
+	GV_Robot_Change_Lane_Distance=(double)CV.PV.Robot_Change_Lane_Distance;         // 3
+ 802e3ac:	4b2a      	ldr	r3, [pc, #168]	@ (802e458 <PV_Data_Reading+0xb8>)
+ 802e3ae:	68db      	ldr	r3, [r3, #12]
+ 802e3b0:	ee07 3a90 	vmov	s15, r3
+ 802e3b4:	eeb8 7be7 	vcvt.f64.s32	d7, s15
+ 802e3b8:	4b29      	ldr	r3, [pc, #164]	@ (802e460 <PV_Data_Reading+0xc0>)
+ 802e3ba:	ed83 7b00 	vstr	d7, [r3]
+	GV_Swing_Speed=(int)CV.PV.Robot_Swing_Speed;                                 // 4
+ 802e3be:	4b26      	ldr	r3, [pc, #152]	@ (802e458 <PV_Data_Reading+0xb8>)
+ 802e3c0:	691b      	ldr	r3, [r3, #16]
+ 802e3c2:	4a28      	ldr	r2, [pc, #160]	@ (802e464 <PV_Data_Reading+0xc4>)
+ 802e3c4:	6013      	str	r3, [r2, #0]
+	GV_Robot_symmetricalOrNot=(int)CV.PV.Robot_symmetricalOrNot;                 // 5
+ 802e3c6:	4b24      	ldr	r3, [pc, #144]	@ (802e458 <PV_Data_Reading+0xb8>)
+ 802e3c8:	695b      	ldr	r3, [r3, #20]
+ 802e3ca:	4a27      	ldr	r2, [pc, #156]	@ (802e468 <PV_Data_Reading+0xc8>)
+ 802e3cc:	6013      	str	r3, [r2, #0]
+	GV_Robot_Swing_Range_Angle=(int)CV.PV.Robot_Swing_Range_Angle;               // 6
+ 802e3ce:	4b22      	ldr	r3, [pc, #136]	@ (802e458 <PV_Data_Reading+0xb8>)
+ 802e3d0:	699b      	ldr	r3, [r3, #24]
+ 802e3d2:	4a26      	ldr	r2, [pc, #152]	@ (802e46c <PV_Data_Reading+0xcc>)
+ 802e3d4:	6013      	str	r3, [r2, #0]
+	GV_Robot_asymmetricalAngleSetValue=(int)CV.PV.Robot_asymmetricalAngleSetValue;  // 7
+ 802e3d6:	4b20      	ldr	r3, [pc, #128]	@ (802e458 <PV_Data_Reading+0xb8>)
+ 802e3d8:	69db      	ldr	r3, [r3, #28]
+ 802e3da:	4a25      	ldr	r2, [pc, #148]	@ (802e470 <PV_Data_Reading+0xd0>)
+ 802e3dc:	6013      	str	r3, [r2, #0]
+	GV_Robot_backMode=(int)CV.PV.Robot_backMode;                                 // 8
+ 802e3de:	4b1e      	ldr	r3, [pc, #120]	@ (802e458 <PV_Data_Reading+0xb8>)
+ 802e3e0:	6a1b      	ldr	r3, [r3, #32]
+ 802e3e2:	4a24      	ldr	r2, [pc, #144]	@ (802e474 <PV_Data_Reading+0xd4>)
+ 802e3e4:	6013      	str	r3, [r2, #0]
+	GV_Robot_Back_Distance=((double)CV.PV.Robot_Back_Distance)/10;                       // 9
+ 802e3e6:	4b1c      	ldr	r3, [pc, #112]	@ (802e458 <PV_Data_Reading+0xb8>)
+ 802e3e8:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 802e3ea:	ee07 3a90 	vmov	s15, r3
+ 802e3ee:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802e3f2:	eeb2 5b04 	vmov.f64	d5, #36	@ 0x41200000  10.0
+ 802e3f6:	ee86 7b05 	vdiv.f64	d7, d6, d5
+ 802e3fa:	4b1f      	ldr	r3, [pc, #124]	@ (802e478 <PV_Data_Reading+0xd8>)
+ 802e3fc:	ed83 7b00 	vstr	d7, [r3]
+	GV_Robot_Back_Speed=((double)CV.PV.Robot_Back_Speed)/10;                             // 10
+ 802e400:	4b15      	ldr	r3, [pc, #84]	@ (802e458 <PV_Data_Reading+0xb8>)
+ 802e402:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 802e404:	ee07 3a90 	vmov	s15, r3
+ 802e408:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802e40c:	eeb2 5b04 	vmov.f64	d5, #36	@ 0x41200000  10.0
+ 802e410:	ee86 7b05 	vdiv.f64	d7, d6, d5
+ 802e414:	4b19      	ldr	r3, [pc, #100]	@ (802e47c <PV_Data_Reading+0xdc>)
+ 802e416:	ed83 7b00 	vstr	d7, [r3]
+	GV_Robot_Press_Set=(int)CV.PV.Robot_Press_Set;                               // 11
+ 802e41a:	4b0f      	ldr	r3, [pc, #60]	@ (802e458 <PV_Data_Reading+0xb8>)
+ 802e41c:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 802e41e:	4a18      	ldr	r2, [pc, #96]	@ (802e480 <PV_Data_Reading+0xe0>)
+ 802e420:	6013      	str	r3, [r2, #0]
+	GV_Robot_Vertical_Adjust=((double)CV.PV.Robot_Vertical_Adjust)/10;                   // 12
+ 802e422:	4b0d      	ldr	r3, [pc, #52]	@ (802e458 <PV_Data_Reading+0xb8>)
+ 802e424:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
+ 802e426:	ee07 3a90 	vmov	s15, r3
+ 802e42a:	eeb8 6be7 	vcvt.f64.s32	d6, s15
+ 802e42e:	eeb2 5b04 	vmov.f64	d5, #36	@ 0x41200000  10.0
+ 802e432:	ee86 7b05 	vdiv.f64	d7, d6, d5
+ 802e436:	4b13      	ldr	r3, [pc, #76]	@ (802e484 <PV_Data_Reading+0xe4>)
+ 802e438:	ed83 7b00 	vstr	d7, [r3]
+	GV_Robot_Length_Homework=(int)CV.PV.Robot_Length_Homework;                   // 13
+ 802e43c:	4b06      	ldr	r3, [pc, #24]	@ (802e458 <PV_Data_Reading+0xb8>)
+ 802e43e:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
+ 802e440:	4a11      	ldr	r2, [pc, #68]	@ (802e488 <PV_Data_Reading+0xe8>)
+ 802e442:	6013      	str	r3, [r2, #0]
+	GV_Robot_Width_Homework=(int)CV.PV.Robot_Width_Homework;                     // 14
+ 802e444:	4b04      	ldr	r3, [pc, #16]	@ (802e458 <PV_Data_Reading+0xb8>)
+ 802e446:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
+ 802e448:	4a10      	ldr	r2, [pc, #64]	@ (802e48c <PV_Data_Reading+0xec>)
+ 802e44a:	6013      	str	r3, [r2, #0]
+
+}
+ 802e44c:	bf00      	nop
+ 802e44e:	46bd      	mov	sp, r7
+ 802e450:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 802e454:	4770      	bx	lr
+ 802e456:	bf00      	nop
+ 802e458:	240002a0 	.word	0x240002a0
+ 802e45c:	2400a704 	.word	0x2400a704
+ 802e460:	2400a708 	.word	0x2400a708
+ 802e464:	2400a710 	.word	0x2400a710
+ 802e468:	2400a714 	.word	0x2400a714
+ 802e46c:	2400a718 	.word	0x2400a718
+ 802e470:	2400a71c 	.word	0x2400a71c
+ 802e474:	2400a720 	.word	0x2400a720
+ 802e478:	2400a728 	.word	0x2400a728
+ 802e47c:	2400a730 	.word	0x2400a730
+ 802e480:	2400a738 	.word	0x2400a738
+ 802e484:	2400a740 	.word	0x2400a740
+ 802e488:	2400a748 	.word	0x2400a748
+ 802e48c:	2400a74c 	.word	0x2400a74c
+
+0802e490 <Robot_Main_Mode_Jude>:
+
+void Robot_Main_Mode_Jude()
+{
+ 802e490:	b480      	push	{r7}
+ 802e492:	b08d      	sub	sp, #52	@ 0x34
+ 802e494:	af00      	add	r7, sp, #0
+	const double DEADZONE_THRESHOLD = 200.0;
+ 802e496:	f04f 0200 	mov.w	r2, #0
+ 802e49a:	4b3b      	ldr	r3, [pc, #236]	@ (802e588 <Robot_Main_Mode_Jude+0xf8>)
+ 802e49c:	e9c7 230a 	strd	r2, r3, [r7, #40]	@ 0x28
+	double y_value = P_MK32->CH2_LY_V; // 假设 Y 是纵向（前后）
+ 802e4a0:	4b3a      	ldr	r3, [pc, #232]	@ (802e58c <Robot_Main_Mode_Jude+0xfc>)
+ 802e4a2:	681b      	ldr	r3, [r3, #0]
+ 802e4a4:	68db      	ldr	r3, [r3, #12]
+ 802e4a6:	ee07 3a90 	vmov	s15, r3
+ 802e4aa:	eeb8 7be7 	vcvt.f64.s32	d7, s15
+ 802e4ae:	ed87 7b08 	vstr	d7, [r7, #32]
+	double x_value = P_MK32->CH3_LY_H; // 假设 X 是横向（左右）
+ 802e4b2:	4b36      	ldr	r3, [pc, #216]	@ (802e58c <Robot_Main_Mode_Jude+0xfc>)
+ 802e4b4:	681b      	ldr	r3, [r3, #0]
+ 802e4b6:	691b      	ldr	r3, [r3, #16]
+ 802e4b8:	ee07 3a90 	vmov	s15, r3
+ 802e4bc:	eeb8 7be7 	vcvt.f64.s32	d7, s15
+ 802e4c0:	ed87 7b06 	vstr	d7, [r7, #24]
+
+	double w_value = P_MK32->CH0_RY_H; // 假设 X 是横向（左右）
+ 802e4c4:	4b31      	ldr	r3, [pc, #196]	@ (802e58c <Robot_Main_Mode_Jude+0xfc>)
+ 802e4c6:	681b      	ldr	r3, [r3, #0]
+ 802e4c8:	685b      	ldr	r3, [r3, #4]
+ 802e4ca:	ee07 3a90 	vmov	s15, r3
+ 802e4ce:	eeb8 7be7 	vcvt.f64.s32	d7, s15
+ 802e4d2:	ed87 7b04 	vstr	d7, [r7, #16]
+	double z_value = P_MK32->CH1_RY_V; // 假设 X 是横向（左右）
+ 802e4d6:	4b2d      	ldr	r3, [pc, #180]	@ (802e58c <Robot_Main_Mode_Jude+0xfc>)
+ 802e4d8:	681b      	ldr	r3, [r3, #0]
+ 802e4da:	689b      	ldr	r3, [r3, #8]
+ 802e4dc:	ee07 3a90 	vmov	s15, r3
+ 802e4e0:	eeb8 7be7 	vcvt.f64.s32	d7, s15
+ 802e4e4:	ed87 7b02 	vstr	d7, [r7, #8]
+	uint8_t all_in_deadzone =
+			(fabs(y_value) <= DEADZONE_THRESHOLD) &
+ 802e4e8:	ed97 7b08 	vldr	d7, [r7, #32]
+ 802e4ec:	eeb0 7bc7 	vabs.f64	d7, d7
+ 802e4f0:	ed97 6b0a 	vldr	d6, [r7, #40]	@ 0x28
+ 802e4f4:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802e4f8:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802e4fc:	bfac      	ite	ge
+ 802e4fe:	2301      	movge	r3, #1
+ 802e500:	2300      	movlt	r3, #0
+ 802e502:	b2da      	uxtb	r2, r3
+			(fabs(x_value) <= DEADZONE_THRESHOLD) &
+ 802e504:	ed97 7b06 	vldr	d7, [r7, #24]
+ 802e508:	eeb0 7bc7 	vabs.f64	d7, d7
+			(fabs(y_value) <= DEADZONE_THRESHOLD) &
+ 802e50c:	ed97 6b0a 	vldr	d6, [r7, #40]	@ 0x28
+ 802e510:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802e514:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802e518:	bfac      	ite	ge
+ 802e51a:	2301      	movge	r3, #1
+ 802e51c:	2300      	movlt	r3, #0
+ 802e51e:	b2db      	uxtb	r3, r3
+ 802e520:	4013      	ands	r3, r2
+ 802e522:	b2db      	uxtb	r3, r3
+ 802e524:	b25a      	sxtb	r2, r3
+			(fabs(w_value) <= DEADZONE_THRESHOLD) &
+ 802e526:	ed97 7b04 	vldr	d7, [r7, #16]
+ 802e52a:	eeb0 7bc7 	vabs.f64	d7, d7
+ 802e52e:	ed97 6b0a 	vldr	d6, [r7, #40]	@ 0x28
+ 802e532:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802e536:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802e53a:	bfac      	ite	ge
+ 802e53c:	2301      	movge	r3, #1
+ 802e53e:	2300      	movlt	r3, #0
+ 802e540:	b2db      	uxtb	r3, r3
+ 802e542:	b25b      	sxtb	r3, r3
+			(fabs(x_value) <= DEADZONE_THRESHOLD) &
+ 802e544:	4013      	ands	r3, r2
+ 802e546:	b25a      	sxtb	r2, r3
+			(fabs(z_value) <= DEADZONE_THRESHOLD);
+ 802e548:	ed97 7b02 	vldr	d7, [r7, #8]
+ 802e54c:	eeb0 7bc7 	vabs.f64	d7, d7
+ 802e550:	ed97 6b0a 	vldr	d6, [r7, #40]	@ 0x28
+ 802e554:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802e558:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802e55c:	bfac      	ite	ge
+ 802e55e:	2301      	movge	r3, #1
+ 802e560:	2300      	movlt	r3, #0
+ 802e562:	b2db      	uxtb	r3, r3
+ 802e564:	b25b      	sxtb	r3, r3
+			(fabs(w_value) <= DEADZONE_THRESHOLD) &
+ 802e566:	4013      	ands	r3, r2
+ 802e568:	b25b      	sxtb	r3, r3
+	uint8_t all_in_deadzone =
+ 802e56a:	71fb      	strb	r3, [r7, #7]
+
+	    // 根据判断结果更新标志
+	if (all_in_deadzone)
+ 802e56c:	79fb      	ldrb	r3, [r7, #7]
+ 802e56e:	2b00      	cmp	r3, #0
+ 802e570:	d004      	beq.n	802e57c <Robot_Main_Mode_Jude+0xec>
+	{
+	     Robot_Main_Flag++;
+ 802e572:	4b07      	ldr	r3, [pc, #28]	@ (802e590 <Robot_Main_Mode_Jude+0x100>)
+ 802e574:	681b      	ldr	r3, [r3, #0]
+ 802e576:	3301      	adds	r3, #1
+ 802e578:	4a05      	ldr	r2, [pc, #20]	@ (802e590 <Robot_Main_Mode_Jude+0x100>)
+ 802e57a:	6013      	str	r3, [r2, #0]
+	}
+}
+ 802e57c:	bf00      	nop
+ 802e57e:	3734      	adds	r7, #52	@ 0x34
+ 802e580:	46bd      	mov	sp, r7
+ 802e582:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 802e586:	4770      	bx	lr
+ 802e588:	40690000 	.word	0x40690000
+ 802e58c:	2400a3f8 	.word	0x2400a3f8
+ 802e590:	2400a77c 	.word	0x2400a77c
+
+0802e594 <EmergencyStop_Hardware_Communication_Detection>:
+
+
+void EmergencyStop_Hardware_Communication_Detection()
+{
+ 802e594:	b580      	push	{r7, lr}
+ 802e596:	af00      	add	r7, sp, #0
+//	(Get_BIT(SystemErrorCode, ComError_MK32_Serial) == 1)				||
+	if((Get_BIT(SystemErrorCode, ComError_TL720D) == 1)
+ 802e598:	4b6c      	ldr	r3, [pc, #432]	@ (802e74c <EmergencyStop_Hardware_Communication_Detection+0x1b8>)
+ 802e59a:	681b      	ldr	r3, [r3, #0]
+ 802e59c:	2103      	movs	r1, #3
+ 802e59e:	4618      	mov	r0, r3
+ 802e5a0:	f7f2 f8a7 	bl	80206f2 <Get_BIT>
+ 802e5a4:	4603      	mov	r3, r0
+ 802e5a6:	2b01      	cmp	r3, #1
+ 802e5a8:	d020      	beq.n	802e5ec <EmergencyStop_Hardware_Communication_Detection+0x58>
+			||(Get_BIT(SystemErrorCode, ComError_ZQ_CAN_ID3_SwingMotor) == 1)
+ 802e5aa:	4b68      	ldr	r3, [pc, #416]	@ (802e74c <EmergencyStop_Hardware_Communication_Detection+0x1b8>)
+ 802e5ac:	681b      	ldr	r3, [r3, #0]
+ 802e5ae:	2106      	movs	r1, #6
+ 802e5b0:	4618      	mov	r0, r3
+ 802e5b2:	f7f2 f89e 	bl	80206f2 <Get_BIT>
+ 802e5b6:	4603      	mov	r3, r0
+ 802e5b8:	2b01      	cmp	r3, #1
+ 802e5ba:	d017      	beq.n	802e5ec <EmergencyStop_Hardware_Communication_Detection+0x58>
+			||(Get_BIT(SystemErrorCode, ComError_Force_Sensor) == 1)
+ 802e5bc:	4b63      	ldr	r3, [pc, #396]	@ (802e74c <EmergencyStop_Hardware_Communication_Detection+0x1b8>)
+ 802e5be:	681b      	ldr	r3, [r3, #0]
+ 802e5c0:	2107      	movs	r1, #7
+ 802e5c2:	4618      	mov	r0, r3
+ 802e5c4:	f7f2 f895 	bl	80206f2 <Get_BIT>
+ 802e5c8:	4603      	mov	r3, r0
+ 802e5ca:	2b01      	cmp	r3, #1
+ 802e5cc:	d00e      	beq.n	802e5ec <EmergencyStop_Hardware_Communication_Detection+0x58>
+			||(Get_BIT(SystemErrorCode, ComError_Mfog40) == 1)
+ 802e5ce:	4b5f      	ldr	r3, [pc, #380]	@ (802e74c <EmergencyStop_Hardware_Communication_Detection+0x1b8>)
+ 802e5d0:	681b      	ldr	r3, [r3, #0]
+ 802e5d2:	2108      	movs	r1, #8
+ 802e5d4:	4618      	mov	r0, r3
+ 802e5d6:	f7f2 f88c 	bl	80206f2 <Get_BIT>
+ 802e5da:	4603      	mov	r3, r0
+ 802e5dc:	2b01      	cmp	r3, #1
+ 802e5de:	d005      	beq.n	802e5ec <EmergencyStop_Hardware_Communication_Detection+0x58>
+			||(Get_BIT(SystemErrorCode, ComError_Ultrasonic_Sensor) == 1)
+ 802e5e0:	4b5a      	ldr	r3, [pc, #360]	@ (802e74c <EmergencyStop_Hardware_Communication_Detection+0x1b8>)
+ 802e5e2:	681b      	ldr	r3, [r3, #0]
+ 802e5e4:	2109      	movs	r1, #9
+ 802e5e6:	4618      	mov	r0, r3
+ 802e5e8:	f7f2 f883 	bl	80206f2 <Get_BIT>
+	{
+//		CV.PV.Robot_Operation_Mode=1;
+//		GV_Operation_Mode=1;
+	}
+
+	if ((Get_BIT(SystemErrorCode, ComError_Mk32_SBus) == 1)
+ 802e5ec:	4b57      	ldr	r3, [pc, #348]	@ (802e74c <EmergencyStop_Hardware_Communication_Detection+0x1b8>)
+ 802e5ee:	681b      	ldr	r3, [r3, #0]
+ 802e5f0:	2100      	movs	r1, #0
+ 802e5f2:	4618      	mov	r0, r3
+ 802e5f4:	f7f2 f87d 	bl	80206f2 <Get_BIT>
+ 802e5f8:	4603      	mov	r3, r0
+ 802e5fa:	2b01      	cmp	r3, #1
+ 802e5fc:	d011      	beq.n	802e622 <EmergencyStop_Hardware_Communication_Detection+0x8e>
+			||(Get_BIT(SystemErrorCode, ComError_ZQ_CAN_ID1_LeftMotor) == 1)
+ 802e5fe:	4b53      	ldr	r3, [pc, #332]	@ (802e74c <EmergencyStop_Hardware_Communication_Detection+0x1b8>)
+ 802e600:	681b      	ldr	r3, [r3, #0]
+ 802e602:	2104      	movs	r1, #4
+ 802e604:	4618      	mov	r0, r3
+ 802e606:	f7f2 f874 	bl	80206f2 <Get_BIT>
+ 802e60a:	4603      	mov	r3, r0
+ 802e60c:	2b01      	cmp	r3, #1
+ 802e60e:	d008      	beq.n	802e622 <EmergencyStop_Hardware_Communication_Detection+0x8e>
+			||(Get_BIT(SystemErrorCode, ComError_ZQ_CAN_ID2_RightMotor) == 1))
+ 802e610:	4b4e      	ldr	r3, [pc, #312]	@ (802e74c <EmergencyStop_Hardware_Communication_Detection+0x1b8>)
+ 802e612:	681b      	ldr	r3, [r3, #0]
+ 802e614:	2105      	movs	r1, #5
+ 802e616:	4618      	mov	r0, r3
+ 802e618:	f7f2 f86b 	bl	80206f2 <Get_BIT>
+ 802e61c:	4603      	mov	r3, r0
+ 802e61e:	2b01      	cmp	r3, #1
+ 802e620:	d108      	bne.n	802e634 <EmergencyStop_Hardware_Communication_Detection+0xa0>
+	{
+		CV.PV.Robot_Operation_Mode=1;
+ 802e622:	4b4b      	ldr	r3, [pc, #300]	@ (802e750 <EmergencyStop_Hardware_Communication_Detection+0x1bc>)
+ 802e624:	2201      	movs	r2, #1
+ 802e626:	605a      	str	r2, [r3, #4]
+		GV_Operation_Mode=1;
+ 802e628:	4b4a      	ldr	r3, [pc, #296]	@ (802e754 <EmergencyStop_Hardware_Communication_Detection+0x1c0>)
+ 802e62a:	2201      	movs	r2, #1
+ 802e62c:	601a      	str	r2, [r3, #0]
+		Robot_Main_Flag=0;
+ 802e62e:	4b4a      	ldr	r3, [pc, #296]	@ (802e758 <EmergencyStop_Hardware_Communication_Detection+0x1c4>)
+ 802e630:	2200      	movs	r2, #0
+ 802e632:	601a      	str	r2, [r3, #0]
+	}
+
+
+	if((GV.LeftMotor.TT_Motor_Fault==0x0302)||(GV.RightMotor.TT_Motor_Fault==0x0302))
+ 802e634:	4b49      	ldr	r3, [pc, #292]	@ (802e75c <EmergencyStop_Hardware_Communication_Detection+0x1c8>)
+ 802e636:	f8d3 30ac 	ldr.w	r3, [r3, #172]	@ 0xac
+ 802e63a:	f240 3202 	movw	r2, #770	@ 0x302
+ 802e63e:	4293      	cmp	r3, r2
+ 802e640:	d006      	beq.n	802e650 <EmergencyStop_Hardware_Communication_Detection+0xbc>
+ 802e642:	4b46      	ldr	r3, [pc, #280]	@ (802e75c <EmergencyStop_Hardware_Communication_Detection+0x1c8>)
+ 802e644:	f8d3 312c 	ldr.w	r3, [r3, #300]	@ 0x12c
+ 802e648:	f240 3202 	movw	r2, #770	@ 0x302
+ 802e64c:	4293      	cmp	r3, r2
+ 802e64e:	d105      	bne.n	802e65c <EmergencyStop_Hardware_Communication_Detection+0xc8>
+	{
+		CV.PV.Robot_Operation_Mode=1;
+ 802e650:	4b3f      	ldr	r3, [pc, #252]	@ (802e750 <EmergencyStop_Hardware_Communication_Detection+0x1bc>)
+ 802e652:	2201      	movs	r2, #1
+ 802e654:	605a      	str	r2, [r3, #4]
+		GV_Operation_Mode=1;
+ 802e656:	4b3f      	ldr	r3, [pc, #252]	@ (802e754 <EmergencyStop_Hardware_Communication_Detection+0x1c0>)
+ 802e658:	2201      	movs	r2, #1
+ 802e65a:	601a      	str	r2, [r3, #0]
+	}
+
+	static int Initial_Power_Record;
+
+	if(Initial_Power_Record==0)
+ 802e65c:	4b40      	ldr	r3, [pc, #256]	@ (802e760 <EmergencyStop_Hardware_Communication_Detection+0x1cc>)
+ 802e65e:	681b      	ldr	r3, [r3, #0]
+ 802e660:	2b00      	cmp	r3, #0
+ 802e662:	d12b      	bne.n	802e6bc <EmergencyStop_Hardware_Communication_Detection+0x128>
+	{
+		if (P_MK32->RxIndex > 0 && P_MK32->CH4_SA == 0 && P_MK32->CH5_SB == 0 && P_MK32->CH6_SC == 0 && P_MK32->CH7_SD == 0)
+ 802e664:	4b3f      	ldr	r3, [pc, #252]	@ (802e764 <EmergencyStop_Hardware_Communication_Detection+0x1d0>)
+ 802e666:	681b      	ldr	r3, [r3, #0]
+ 802e668:	681b      	ldr	r3, [r3, #0]
+ 802e66a:	2b00      	cmp	r3, #0
+ 802e66c:	dd1d      	ble.n	802e6aa <EmergencyStop_Hardware_Communication_Detection+0x116>
+ 802e66e:	4b3d      	ldr	r3, [pc, #244]	@ (802e764 <EmergencyStop_Hardware_Communication_Detection+0x1d0>)
+ 802e670:	681b      	ldr	r3, [r3, #0]
+ 802e672:	695b      	ldr	r3, [r3, #20]
+ 802e674:	2b00      	cmp	r3, #0
+ 802e676:	d118      	bne.n	802e6aa <EmergencyStop_Hardware_Communication_Detection+0x116>
+ 802e678:	4b3a      	ldr	r3, [pc, #232]	@ (802e764 <EmergencyStop_Hardware_Communication_Detection+0x1d0>)
+ 802e67a:	681b      	ldr	r3, [r3, #0]
+ 802e67c:	699b      	ldr	r3, [r3, #24]
+ 802e67e:	2b00      	cmp	r3, #0
+ 802e680:	d113      	bne.n	802e6aa <EmergencyStop_Hardware_Communication_Detection+0x116>
+ 802e682:	4b38      	ldr	r3, [pc, #224]	@ (802e764 <EmergencyStop_Hardware_Communication_Detection+0x1d0>)
+ 802e684:	681b      	ldr	r3, [r3, #0]
+ 802e686:	69db      	ldr	r3, [r3, #28]
+ 802e688:	2b00      	cmp	r3, #0
+ 802e68a:	d10e      	bne.n	802e6aa <EmergencyStop_Hardware_Communication_Detection+0x116>
+ 802e68c:	4b35      	ldr	r3, [pc, #212]	@ (802e764 <EmergencyStop_Hardware_Communication_Detection+0x1d0>)
+ 802e68e:	681b      	ldr	r3, [r3, #0]
+ 802e690:	6a1b      	ldr	r3, [r3, #32]
+ 802e692:	2b00      	cmp	r3, #0
+ 802e694:	d109      	bne.n	802e6aa <EmergencyStop_Hardware_Communication_Detection+0x116>
+		{
+			Initial_Power_Record=1;
+ 802e696:	4b32      	ldr	r3, [pc, #200]	@ (802e760 <EmergencyStop_Hardware_Communication_Detection+0x1cc>)
+ 802e698:	2201      	movs	r2, #1
+ 802e69a:	601a      	str	r2, [r3, #0]
+			SET_BIT_0(SystemErrorCode, ComError_MK32_InitialState);
+ 802e69c:	4b2b      	ldr	r3, [pc, #172]	@ (802e74c <EmergencyStop_Hardware_Communication_Detection+0x1b8>)
+ 802e69e:	681b      	ldr	r3, [r3, #0]
+ 802e6a0:	2102      	movs	r1, #2
+ 802e6a2:	4618      	mov	r0, r3
+ 802e6a4:	f7f2 f810 	bl	80206c8 <SET_BIT_0>
+ 802e6a8:	e008      	b.n	802e6bc <EmergencyStop_Hardware_Communication_Detection+0x128>
+		}
+		else
+		{
+			SET_BIT_1(SystemErrorCode, ComError_MK32_InitialState);
+ 802e6aa:	4b28      	ldr	r3, [pc, #160]	@ (802e74c <EmergencyStop_Hardware_Communication_Detection+0x1b8>)
+ 802e6ac:	681b      	ldr	r3, [r3, #0]
+ 802e6ae:	2102      	movs	r1, #2
+ 802e6b0:	4618      	mov	r0, r3
+ 802e6b2:	f7f1 fff5 	bl	80206a0 <SET_BIT_1>
+			Robot_Main_Flag=0;
+ 802e6b6:	4b28      	ldr	r3, [pc, #160]	@ (802e758 <EmergencyStop_Hardware_Communication_Detection+0x1c4>)
+ 802e6b8:	2200      	movs	r2, #0
+ 802e6ba:	601a      	str	r2, [r3, #0]
+		}
+	}
+
+	if(P_MK32->IsOnline!=1)
+ 802e6bc:	4b29      	ldr	r3, [pc, #164]	@ (802e764 <EmergencyStop_Hardware_Communication_Detection+0x1d0>)
+ 802e6be:	681b      	ldr	r3, [r3, #0]
+ 802e6c0:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
+ 802e6c2:	2b01      	cmp	r3, #1
+ 802e6c4:	d007      	beq.n	802e6d6 <EmergencyStop_Hardware_Communication_Detection+0x142>
+	{
+		Robot_Halt_Mode();
+ 802e6c6:	f7fb f8db 	bl	8029880 <Robot_Halt_Mode>
+		CV.PV.Robot_Operation_Mode=0;
+ 802e6ca:	4b21      	ldr	r3, [pc, #132]	@ (802e750 <EmergencyStop_Hardware_Communication_Detection+0x1bc>)
+ 802e6cc:	2200      	movs	r2, #0
+ 802e6ce:	605a      	str	r2, [r3, #4]
+		GV_Operation_Mode=0;
+ 802e6d0:	4b20      	ldr	r3, [pc, #128]	@ (802e754 <EmergencyStop_Hardware_Communication_Detection+0x1c0>)
+ 802e6d2:	2200      	movs	r2, #0
+ 802e6d4:	601a      	str	r2, [r3, #0]
+	}
+
+	if((P_MK32->CH8_SE==-1000)&&(P_MK32->CH9_SF==-1000))
+ 802e6d6:	4b23      	ldr	r3, [pc, #140]	@ (802e764 <EmergencyStop_Hardware_Communication_Detection+0x1d0>)
+ 802e6d8:	681b      	ldr	r3, [r3, #0]
+ 802e6da:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 802e6dc:	f513 7f7a 	cmn.w	r3, #1000	@ 0x3e8
+ 802e6e0:	d11e      	bne.n	802e720 <EmergencyStop_Hardware_Communication_Detection+0x18c>
+ 802e6e2:	4b20      	ldr	r3, [pc, #128]	@ (802e764 <EmergencyStop_Hardware_Communication_Detection+0x1d0>)
+ 802e6e4:	681b      	ldr	r3, [r3, #0]
+ 802e6e6:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 802e6e8:	f513 7f7a 	cmn.w	r3, #1000	@ 0x3e8
+ 802e6ec:	d118      	bne.n	802e720 <EmergencyStop_Hardware_Communication_Detection+0x18c>
+	{
+		Switch_Off_Flag=1;
+ 802e6ee:	4b1e      	ldr	r3, [pc, #120]	@ (802e768 <EmergencyStop_Hardware_Communication_Detection+0x1d4>)
+ 802e6f0:	2201      	movs	r2, #1
+ 802e6f2:	701a      	strb	r2, [r3, #0]
+		Robot_Halt_Mode();
+ 802e6f4:	f7fb f8c4 	bl	8029880 <Robot_Halt_Mode>
+		TT_Motor_Need_To_Activate = 0;
+ 802e6f8:	4b1c      	ldr	r3, [pc, #112]	@ (802e76c <EmergencyStop_Hardware_Communication_Detection+0x1d8>)
+ 802e6fa:	2200      	movs	r2, #0
+ 802e6fc:	701a      	strb	r2, [r3, #0]
+		TT_Motor_Need_To_Activate_1=0;
+ 802e6fe:	4b1c      	ldr	r3, [pc, #112]	@ (802e770 <EmergencyStop_Hardware_Communication_Detection+0x1dc>)
+ 802e700:	2200      	movs	r2, #0
+ 802e702:	701a      	strb	r2, [r3, #0]
+		GF_BSP_GPIO_SetIO(Motor_Power_IO_CTL, K_OFF);
+ 802e704:	2101      	movs	r1, #1
+ 802e706:	2000      	movs	r0, #0
+ 802e708:	f7f2 fd84 	bl	8021214 <GF_BSP_GPIO_SetIO>
+//		Move_PushRod_Halt_Func_Do();
+//		Blast_Machine_Close();
+		CV.PV.Robot_Operation_Mode=1;
+ 802e70c:	4b10      	ldr	r3, [pc, #64]	@ (802e750 <EmergencyStop_Hardware_Communication_Detection+0x1bc>)
+ 802e70e:	2201      	movs	r2, #1
+ 802e710:	605a      	str	r2, [r3, #4]
+		GV_Operation_Mode=1;
+ 802e712:	4b10      	ldr	r3, [pc, #64]	@ (802e754 <EmergencyStop_Hardware_Communication_Detection+0x1c0>)
+ 802e714:	2201      	movs	r2, #1
+ 802e716:	601a      	str	r2, [r3, #0]
+		Robot_Main_Flag=0;
+ 802e718:	4b0f      	ldr	r3, [pc, #60]	@ (802e758 <EmergencyStop_Hardware_Communication_Detection+0x1c4>)
+ 802e71a:	2200      	movs	r2, #0
+ 802e71c:	601a      	str	r2, [r3, #0]
+			Initial_Power_Record=0;
+		}
+	}
+
+
+}
+ 802e71e:	e013      	b.n	802e748 <EmergencyStop_Hardware_Communication_Detection+0x1b4>
+		GF_BSP_GPIO_SetIO(Motor_Power_IO_CTL, K_ON);
+ 802e720:	2100      	movs	r1, #0
+ 802e722:	2000      	movs	r0, #0
+ 802e724:	f7f2 fd76 	bl	8021214 <GF_BSP_GPIO_SetIO>
+		if (Switch_Off_Flag == 1)
+ 802e728:	4b0f      	ldr	r3, [pc, #60]	@ (802e768 <EmergencyStop_Hardware_Communication_Detection+0x1d4>)
+ 802e72a:	781b      	ldrb	r3, [r3, #0]
+ 802e72c:	2b01      	cmp	r3, #1
+ 802e72e:	d10b      	bne.n	802e748 <EmergencyStop_Hardware_Communication_Detection+0x1b4>
+			Switch_Off_Flag = 0;
+ 802e730:	4b0d      	ldr	r3, [pc, #52]	@ (802e768 <EmergencyStop_Hardware_Communication_Detection+0x1d4>)
+ 802e732:	2200      	movs	r2, #0
+ 802e734:	701a      	strb	r2, [r3, #0]
+			TT_Motor_Need_To_Activate = 1;
+ 802e736:	4b0d      	ldr	r3, [pc, #52]	@ (802e76c <EmergencyStop_Hardware_Communication_Detection+0x1d8>)
+ 802e738:	2201      	movs	r2, #1
+ 802e73a:	701a      	strb	r2, [r3, #0]
+			TT_Motor_Need_To_Activate_1=1;
+ 802e73c:	4b0c      	ldr	r3, [pc, #48]	@ (802e770 <EmergencyStop_Hardware_Communication_Detection+0x1dc>)
+ 802e73e:	2201      	movs	r2, #1
+ 802e740:	701a      	strb	r2, [r3, #0]
+			Initial_Power_Record=0;
+ 802e742:	4b07      	ldr	r3, [pc, #28]	@ (802e760 <EmergencyStop_Hardware_Communication_Detection+0x1cc>)
+ 802e744:	2200      	movs	r2, #0
+ 802e746:	601a      	str	r2, [r3, #0]
+}
+ 802e748:	bf00      	nop
+ 802e74a:	bd80      	pop	{r7, pc}
+ 802e74c:	2400028c 	.word	0x2400028c
+ 802e750:	240002a0 	.word	0x240002a0
+ 802e754:	2400a750 	.word	0x2400a750
+ 802e758:	2400a77c 	.word	0x2400a77c
+ 802e75c:	24000340 	.word	0x24000340
+ 802e760:	2400a8c8 	.word	0x2400a8c8
+ 802e764:	2400a3f8 	.word	0x2400a3f8
+ 802e768:	2400a778 	.word	0x2400a778
+ 802e76c:	24000128 	.word	0x24000128
+ 802e770:	24000129 	.word	0x24000129
+
+0802e774 <Regional_Horizontal_Automatic_Functionc>:
+
+
+int Regional_Automatic_Flag=0;
+
+void Regional_Horizontal_Automatic_Functionc()
+{
+ 802e774:	b580      	push	{r7, lr}
+ 802e776:	af00      	add	r7, sp, #0
+	if(P_MK32->CH7_SD==-1000)//自动行驶
+ 802e778:	4b2e      	ldr	r3, [pc, #184]	@ (802e834 <Regional_Horizontal_Automatic_Functionc+0xc0>)
+ 802e77a:	681b      	ldr	r3, [r3, #0]
+ 802e77c:	6a1b      	ldr	r3, [r3, #32]
+ 802e77e:	f513 7f7a 	cmn.w	r3, #1000	@ 0x3e8
+ 802e782:	d142      	bne.n	802e80a <Regional_Horizontal_Automatic_Functionc+0x96>
+	{
+		if(GV.SystemErrorData.ErrorCode == 0 || GV.SystemErrorData.ErrorCode == 2)
+ 802e784:	4b2c      	ldr	r3, [pc, #176]	@ (802e838 <Regional_Horizontal_Automatic_Functionc+0xc4>)
+ 802e786:	f8d3 3240 	ldr.w	r3, [r3, #576]	@ 0x240
+ 802e78a:	2b00      	cmp	r3, #0
+ 802e78c:	d004      	beq.n	802e798 <Regional_Horizontal_Automatic_Functionc+0x24>
+ 802e78e:	4b2a      	ldr	r3, [pc, #168]	@ (802e838 <Regional_Horizontal_Automatic_Functionc+0xc4>)
+ 802e790:	f8d3 3240 	ldr.w	r3, [r3, #576]	@ 0x240
+ 802e794:	2b02      	cmp	r3, #2
+ 802e796:	d105      	bne.n	802e7a4 <Regional_Horizontal_Automatic_Functionc+0x30>
+		{
+			if(ctl_flag_1 != 1)
+ 802e798:	4b28      	ldr	r3, [pc, #160]	@ (802e83c <Regional_Horizontal_Automatic_Functionc+0xc8>)
+ 802e79a:	681b      	ldr	r3, [r3, #0]
+ 802e79c:	2b01      	cmp	r3, #1
+ 802e79e:	d001      	beq.n	802e7a4 <Regional_Horizontal_Automatic_Functionc+0x30>
+			{
+				Blast_Machine_Open_Fun();//打开喷砂机hjb
+ 802e7a0:	f7f7 fe66 	bl	8026470 <Blast_Machine_Open_Fun>
+			}
+		}
+		  switch (Regional_Automatic_Flag)
+ 802e7a4:	4b26      	ldr	r3, [pc, #152]	@ (802e840 <Regional_Horizontal_Automatic_Functionc+0xcc>)
+ 802e7a6:	681b      	ldr	r3, [r3, #0]
+ 802e7a8:	2b03      	cmp	r3, #3
+ 802e7aa:	d828      	bhi.n	802e7fe <Regional_Horizontal_Automatic_Functionc+0x8a>
+ 802e7ac:	a201      	add	r2, pc, #4	@ (adr r2, 802e7b4 <Regional_Horizontal_Automatic_Functionc+0x40>)
+ 802e7ae:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 802e7b2:	bf00      	nop
+ 802e7b4:	0802e7c5 	.word	0x0802e7c5
+ 802e7b8:	0802e7d1 	.word	0x0802e7d1
+ 802e7bc:	0802e7f1 	.word	0x0802e7f1
+ 802e7c0:	0802e7f7 	.word	0x0802e7f7
+		  {
+			  case Regional_Parameter_Determination://区域自动作业参数确认
+				  Regional_Automatic_Flag++;
+ 802e7c4:	4b1e      	ldr	r3, [pc, #120]	@ (802e840 <Regional_Horizontal_Automatic_Functionc+0xcc>)
+ 802e7c6:	681b      	ldr	r3, [r3, #0]
+ 802e7c8:	3301      	adds	r3, #1
+ 802e7ca:	4a1d      	ldr	r2, [pc, #116]	@ (802e840 <Regional_Horizontal_Automatic_Functionc+0xcc>)
+ 802e7cc:	6013      	str	r3, [r2, #0]
+				  break;
+ 802e7ce:	e016      	b.n	802e7fe <Regional_Horizontal_Automatic_Functionc+0x8a>
+			  case Regional_Parameter_Calculation:
+				  if(GV_Robot_backMode==1)
+ 802e7d0:	4b1c      	ldr	r3, [pc, #112]	@ (802e844 <Regional_Horizontal_Automatic_Functionc+0xd0>)
+ 802e7d2:	681b      	ldr	r3, [r3, #0]
+ 802e7d4:	2b01      	cmp	r3, #1
+ 802e7d6:	d103      	bne.n	802e7e0 <Regional_Horizontal_Automatic_Functionc+0x6c>
+				  {
+					  Regional_Automatic_Flag=Regional_Alternately;
+ 802e7d8:	4b19      	ldr	r3, [pc, #100]	@ (802e840 <Regional_Horizontal_Automatic_Functionc+0xcc>)
+ 802e7da:	2202      	movs	r2, #2
+ 802e7dc:	601a      	str	r2, [r3, #0]
+				  }
+				  else
+				  {
+
+				  }
+				  break;
+ 802e7de:	e00d      	b.n	802e7fc <Regional_Horizontal_Automatic_Functionc+0x88>
+				  else if(GV_Robot_backMode==2)
+ 802e7e0:	4b18      	ldr	r3, [pc, #96]	@ (802e844 <Regional_Horizontal_Automatic_Functionc+0xd0>)
+ 802e7e2:	681b      	ldr	r3, [r3, #0]
+ 802e7e4:	2b02      	cmp	r3, #2
+ 802e7e6:	d109      	bne.n	802e7fc <Regional_Horizontal_Automatic_Functionc+0x88>
+					  Regional_Automatic_Flag=Regional_Continuous;
+ 802e7e8:	4b15      	ldr	r3, [pc, #84]	@ (802e840 <Regional_Horizontal_Automatic_Functionc+0xcc>)
+ 802e7ea:	2203      	movs	r2, #3
+ 802e7ec:	601a      	str	r2, [r3, #0]
+				  break;
+ 802e7ee:	e005      	b.n	802e7fc <Regional_Horizontal_Automatic_Functionc+0x88>
+			  case Regional_Alternately:
+				  Region_Automated_Task_Func_Alternately_Horizontal();
+ 802e7f0:	f7fc f8ee 	bl	802a9d0 <Region_Automated_Task_Func_Alternately_Horizontal>
+				  break;
+ 802e7f4:	e003      	b.n	802e7fe <Regional_Horizontal_Automatic_Functionc+0x8a>
+			  case Regional_Continuous:
+				  Region_Automated_Task_Func_Continuous_Horizontal();
+ 802e7f6:	f000 fa21 	bl	802ec3c <Region_Automated_Task_Func_Continuous_Horizontal>
+				  break;
+ 802e7fa:	e000      	b.n	802e7fe <Regional_Horizontal_Automatic_Functionc+0x8a>
+				  break;
+ 802e7fc:	bf00      	nop
+		  }
+	  UltraStopReverse(Regional_Automatic_Flag);
+ 802e7fe:	4b10      	ldr	r3, [pc, #64]	@ (802e840 <Regional_Horizontal_Automatic_Functionc+0xcc>)
+ 802e800:	681b      	ldr	r3, [r3, #0]
+ 802e802:	4618      	mov	r0, r3
+ 802e804:	f7fb f858 	bl	80298b8 <UltraStopReverse>
+
+		Robot_Manual_Operation_Function();
+		Robot_Main_Mode_Jude();
+		UltraStopReverse_Manually_Backward();
+	}
+}
+ 802e808:	e011      	b.n	802e82e <Regional_Horizontal_Automatic_Functionc+0xba>
+		Regional_Automatic_Flag=Regional_Parameter_Determination;
+ 802e80a:	4b0d      	ldr	r3, [pc, #52]	@ (802e840 <Regional_Horizontal_Automatic_Functionc+0xcc>)
+ 802e80c:	2200      	movs	r2, #0
+ 802e80e:	601a      	str	r2, [r3, #0]
+		Region_Task_Falg=Parameter_Calculation;
+ 802e810:	4b0d      	ldr	r3, [pc, #52]	@ (802e848 <Regional_Horizontal_Automatic_Functionc+0xd4>)
+ 802e812:	2200      	movs	r2, #0
+ 802e814:	601a      	str	r2, [r3, #0]
+		ctl_flag = 1;
+ 802e816:	4b0d      	ldr	r3, [pc, #52]	@ (802e84c <Regional_Horizontal_Automatic_Functionc+0xd8>)
+ 802e818:	2201      	movs	r2, #1
+ 802e81a:	601a      	str	r2, [r3, #0]
+		ctl_flag_1 = 0;
+ 802e81c:	4b07      	ldr	r3, [pc, #28]	@ (802e83c <Regional_Horizontal_Automatic_Functionc+0xc8>)
+ 802e81e:	2200      	movs	r2, #0
+ 802e820:	601a      	str	r2, [r3, #0]
+		Robot_Manual_Operation_Function();
+ 802e822:	f7fb f8dd 	bl	80299e0 <Robot_Manual_Operation_Function>
+		Robot_Main_Mode_Jude();
+ 802e826:	f7ff fe33 	bl	802e490 <Robot_Main_Mode_Jude>
+		UltraStopReverse_Manually_Backward();
+ 802e82a:	f7fb f8a7 	bl	802997c <UltraStopReverse_Manually_Backward>
+}
+ 802e82e:	bf00      	nop
+ 802e830:	bd80      	pop	{r7, pc}
+ 802e832:	bf00      	nop
+ 802e834:	2400a3f8 	.word	0x2400a3f8
+ 802e838:	24000340 	.word	0x24000340
+ 802e83c:	2400a774 	.word	0x2400a774
+ 802e840:	2400a870 	.word	0x2400a870
+ 802e844:	2400a720 	.word	0x2400a720
+ 802e848:	2400a6c4 	.word	0x2400a6c4
+ 802e84c:	2400a770 	.word	0x2400a770
+
+0802e850 <Regional_Plane_Automatic_Functionc>:
+
+
+void Regional_Plane_Automatic_Functionc()
+{
+ 802e850:	b580      	push	{r7, lr}
+ 802e852:	af00      	add	r7, sp, #0
+	if(P_MK32->CH7_SD==-1000)//自动行驶
+ 802e854:	4b2d      	ldr	r3, [pc, #180]	@ (802e90c <Regional_Plane_Automatic_Functionc+0xbc>)
+ 802e856:	681b      	ldr	r3, [r3, #0]
+ 802e858:	6a1b      	ldr	r3, [r3, #32]
+ 802e85a:	f513 7f7a 	cmn.w	r3, #1000	@ 0x3e8
+ 802e85e:	d142      	bne.n	802e8e6 <Regional_Plane_Automatic_Functionc+0x96>
+	{
+		if(GV.SystemErrorData.ErrorCode == 0 || GV.SystemErrorData.ErrorCode == 2)
+ 802e860:	4b2b      	ldr	r3, [pc, #172]	@ (802e910 <Regional_Plane_Automatic_Functionc+0xc0>)
+ 802e862:	f8d3 3240 	ldr.w	r3, [r3, #576]	@ 0x240
+ 802e866:	2b00      	cmp	r3, #0
+ 802e868:	d004      	beq.n	802e874 <Regional_Plane_Automatic_Functionc+0x24>
+ 802e86a:	4b29      	ldr	r3, [pc, #164]	@ (802e910 <Regional_Plane_Automatic_Functionc+0xc0>)
+ 802e86c:	f8d3 3240 	ldr.w	r3, [r3, #576]	@ 0x240
+ 802e870:	2b02      	cmp	r3, #2
+ 802e872:	d105      	bne.n	802e880 <Regional_Plane_Automatic_Functionc+0x30>
+		{
+			if(ctl_flag_1 != 1)
+ 802e874:	4b27      	ldr	r3, [pc, #156]	@ (802e914 <Regional_Plane_Automatic_Functionc+0xc4>)
+ 802e876:	681b      	ldr	r3, [r3, #0]
+ 802e878:	2b01      	cmp	r3, #1
+ 802e87a:	d001      	beq.n	802e880 <Regional_Plane_Automatic_Functionc+0x30>
+			{
+				Blast_Machine_Open_Fun();//打开喷砂机hjb
+ 802e87c:	f7f7 fdf8 	bl	8026470 <Blast_Machine_Open_Fun>
+			}
+		}
+
+		  switch(Regional_Automatic_Flag)
+ 802e880:	4b25      	ldr	r3, [pc, #148]	@ (802e918 <Regional_Plane_Automatic_Functionc+0xc8>)
+ 802e882:	681b      	ldr	r3, [r3, #0]
+ 802e884:	2b03      	cmp	r3, #3
+ 802e886:	d828      	bhi.n	802e8da <Regional_Plane_Automatic_Functionc+0x8a>
+ 802e888:	a201      	add	r2, pc, #4	@ (adr r2, 802e890 <Regional_Plane_Automatic_Functionc+0x40>)
+ 802e88a:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 802e88e:	bf00      	nop
+ 802e890:	0802e8a1 	.word	0x0802e8a1
+ 802e894:	0802e8ad 	.word	0x0802e8ad
+ 802e898:	0802e8cd 	.word	0x0802e8cd
+ 802e89c:	0802e8d3 	.word	0x0802e8d3
+		  {
+			  case Regional_Parameter_Determination://区域自动作业参数确认
+				  Regional_Automatic_Flag++;
+ 802e8a0:	4b1d      	ldr	r3, [pc, #116]	@ (802e918 <Regional_Plane_Automatic_Functionc+0xc8>)
+ 802e8a2:	681b      	ldr	r3, [r3, #0]
+ 802e8a4:	3301      	adds	r3, #1
+ 802e8a6:	4a1c      	ldr	r2, [pc, #112]	@ (802e918 <Regional_Plane_Automatic_Functionc+0xc8>)
+ 802e8a8:	6013      	str	r3, [r2, #0]
+				  break;
+ 802e8aa:	e016      	b.n	802e8da <Regional_Plane_Automatic_Functionc+0x8a>
+			  case Regional_Parameter_Calculation:
+				  if(GV_Robot_backMode==1)
+ 802e8ac:	4b1b      	ldr	r3, [pc, #108]	@ (802e91c <Regional_Plane_Automatic_Functionc+0xcc>)
+ 802e8ae:	681b      	ldr	r3, [r3, #0]
+ 802e8b0:	2b01      	cmp	r3, #1
+ 802e8b2:	d103      	bne.n	802e8bc <Regional_Plane_Automatic_Functionc+0x6c>
+				  {
+					  Regional_Automatic_Flag=Regional_Alternately;
+ 802e8b4:	4b18      	ldr	r3, [pc, #96]	@ (802e918 <Regional_Plane_Automatic_Functionc+0xc8>)
+ 802e8b6:	2202      	movs	r2, #2
+ 802e8b8:	601a      	str	r2, [r3, #0]
+				  else
+				  {
+
+				  }
+
+				  break;
+ 802e8ba:	e00d      	b.n	802e8d8 <Regional_Plane_Automatic_Functionc+0x88>
+				  else if(GV_Robot_backMode==2)
+ 802e8bc:	4b17      	ldr	r3, [pc, #92]	@ (802e91c <Regional_Plane_Automatic_Functionc+0xcc>)
+ 802e8be:	681b      	ldr	r3, [r3, #0]
+ 802e8c0:	2b02      	cmp	r3, #2
+ 802e8c2:	d109      	bne.n	802e8d8 <Regional_Plane_Automatic_Functionc+0x88>
+					  Regional_Automatic_Flag=Regional_Continuous;
+ 802e8c4:	4b14      	ldr	r3, [pc, #80]	@ (802e918 <Regional_Plane_Automatic_Functionc+0xc8>)
+ 802e8c6:	2203      	movs	r2, #3
+ 802e8c8:	601a      	str	r2, [r3, #0]
+				  break;
+ 802e8ca:	e005      	b.n	802e8d8 <Regional_Plane_Automatic_Functionc+0x88>
+			  case Regional_Alternately:
+				  Region_Automated_Task_Func_Alternately_Plane();
+ 802e8cc:	f7fb ff14 	bl	802a6f8 <Region_Automated_Task_Func_Alternately_Plane>
+				  break;
+ 802e8d0:	e003      	b.n	802e8da <Regional_Plane_Automatic_Functionc+0x8a>
+			  case Regional_Continuous:
+				 // Region_Automated_Task_Func_Continuous_Plane();
+				  Region_Automated_Task_Func_Continuous_Plane_Uptate_1();
+ 802e8d2:	f000 f829 	bl	802e928 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1>
+				  break;
+ 802e8d6:	e000      	b.n	802e8da <Regional_Plane_Automatic_Functionc+0x8a>
+				  break;
+ 802e8d8:	bf00      	nop
+		  }
+		  UltraStopReverse(Regional_Automatic_Flag);
+ 802e8da:	4b0f      	ldr	r3, [pc, #60]	@ (802e918 <Regional_Plane_Automatic_Functionc+0xc8>)
+ 802e8dc:	681b      	ldr	r3, [r3, #0]
+ 802e8de:	4618      	mov	r0, r3
+ 802e8e0:	f7fa ffea 	bl	80298b8 <UltraStopReverse>
+
+		Robot_Manual_Operation_Function();
+		Robot_Main_Mode_Jude();
+//		UltraStopReverse_Manually_Backward();
+	}
+}
+ 802e8e4:	e00f      	b.n	802e906 <Regional_Plane_Automatic_Functionc+0xb6>
+		Regional_Automatic_Flag=0;
+ 802e8e6:	4b0c      	ldr	r3, [pc, #48]	@ (802e918 <Regional_Plane_Automatic_Functionc+0xc8>)
+ 802e8e8:	2200      	movs	r2, #0
+ 802e8ea:	601a      	str	r2, [r3, #0]
+		Region_Task_Falg=0;
+ 802e8ec:	4b0c      	ldr	r3, [pc, #48]	@ (802e920 <Regional_Plane_Automatic_Functionc+0xd0>)
+ 802e8ee:	2200      	movs	r2, #0
+ 802e8f0:	601a      	str	r2, [r3, #0]
+		ctl_flag = 1;
+ 802e8f2:	4b0c      	ldr	r3, [pc, #48]	@ (802e924 <Regional_Plane_Automatic_Functionc+0xd4>)
+ 802e8f4:	2201      	movs	r2, #1
+ 802e8f6:	601a      	str	r2, [r3, #0]
+		ctl_flag_1 = 0;
+ 802e8f8:	4b06      	ldr	r3, [pc, #24]	@ (802e914 <Regional_Plane_Automatic_Functionc+0xc4>)
+ 802e8fa:	2200      	movs	r2, #0
+ 802e8fc:	601a      	str	r2, [r3, #0]
+		Robot_Manual_Operation_Function();
+ 802e8fe:	f7fb f86f 	bl	80299e0 <Robot_Manual_Operation_Function>
+		Robot_Main_Mode_Jude();
+ 802e902:	f7ff fdc5 	bl	802e490 <Robot_Main_Mode_Jude>
+}
+ 802e906:	bf00      	nop
+ 802e908:	bd80      	pop	{r7, pc}
+ 802e90a:	bf00      	nop
+ 802e90c:	2400a3f8 	.word	0x2400a3f8
+ 802e910:	24000340 	.word	0x24000340
+ 802e914:	2400a774 	.word	0x2400a774
+ 802e918:	2400a870 	.word	0x2400a870
+ 802e91c:	2400a720 	.word	0x2400a720
+ 802e920:	2400a6c4 	.word	0x2400a6c4
+ 802e924:	2400a770 	.word	0x2400a770
+
+0802e928 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1>:
+			  break;
+	  }
+}
+
+void Region_Automated_Task_Func_Continuous_Plane_Uptate_1()
+{
+ 802e928:	b580      	push	{r7, lr}
+ 802e92a:	b082      	sub	sp, #8
+ 802e92c:	af00      	add	r7, sp, #0
+	static int Backward_Time_X_Total;
+	static int Backward_Time_Count;
+
+	static int Lane_Change_Time_Total_Y;
+	  switch (Region_Task_Falg)
+ 802e92e:	4ba0      	ldr	r3, [pc, #640]	@ (802ebb0 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x288>)
+ 802e930:	681b      	ldr	r3, [r3, #0]
+ 802e932:	2b05      	cmp	r3, #5
+ 802e934:	f200 8174 	bhi.w	802ec20 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x2f8>
+ 802e938:	a201      	add	r2, pc, #4	@ (adr r2, 802e940 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x18>)
+ 802e93a:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 802e93e:	bf00      	nop
+ 802e940:	0802e959 	.word	0x0802e959
+ 802e944:	0802ea11 	.word	0x0802ea11
+ 802e948:	0802ead3 	.word	0x0802ead3
+ 802e94c:	0802eb1b 	.word	0x0802eb1b
+ 802e950:	0802eb5f 	.word	0x0802eb5f
+ 802e954:	0802ec09 	.word	0x0802ec09
+	  {
+		  case Parameter_Calculation:
+			  Deri_Angle_Deg_X[0]=MF40G_Angle_Add_Deg;
+ 802e958:	4b96      	ldr	r3, [pc, #600]	@ (802ebb4 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x28c>)
+ 802e95a:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802e95e:	4996      	ldr	r1, [pc, #600]	@ (802ebb8 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x290>)
+ 802e960:	e9c1 2300 	strd	r2, r3, [r1]
+			  Plane_Turn_Angle_Deg=MF40G_Angle_Add_Deg+90;
+ 802e964:	4b93      	ldr	r3, [pc, #588]	@ (802ebb4 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x28c>)
+ 802e966:	ed93 7b00 	vldr	d7, [r3]
+ 802e96a:	ed9f 6b8b 	vldr	d6, [pc, #556]	@ 802eb98 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x270>
+ 802e96e:	ee37 7b06 	vadd.f64	d7, d7, d6
+ 802e972:	4b92      	ldr	r3, [pc, #584]	@ (802ebbc <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x294>)
+ 802e974:	ed83 7b00 	vstr	d7, [r3]
+			  Deri_Angle_Deg_X[1]=Deri_Angle_Deg_X[0]+180;
+ 802e978:	4b8f      	ldr	r3, [pc, #572]	@ (802ebb8 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x290>)
+ 802e97a:	ed93 7b00 	vldr	d7, [r3]
+ 802e97e:	ed9f 6b88 	vldr	d6, [pc, #544]	@ 802eba0 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x278>
+ 802e982:	ee37 7b06 	vadd.f64	d7, d7, d6
+ 802e986:	4b8c      	ldr	r3, [pc, #560]	@ (802ebb8 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x290>)
+ 802e988:	ed83 7b02 	vstr	d7, [r3, #8]
+			  if( Deri_Angle_Deg_X[1]>180)
+ 802e98c:	4b8a      	ldr	r3, [pc, #552]	@ (802ebb8 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x290>)
+ 802e98e:	ed93 7b02 	vldr	d7, [r3, #8]
+ 802e992:	ed9f 6b83 	vldr	d6, [pc, #524]	@ 802eba0 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x278>
+ 802e996:	eeb4 7bc6 	vcmpe.f64	d7, d6
+ 802e99a:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802e99e:	dd09      	ble.n	802e9b4 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x8c>
+			  {
+				  Deri_Angle_Deg_X[1]= Deri_Angle_Deg_X[1]-360;
+ 802e9a0:	4b85      	ldr	r3, [pc, #532]	@ (802ebb8 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x290>)
+ 802e9a2:	ed93 7b02 	vldr	d7, [r3, #8]
+ 802e9a6:	ed9f 6b80 	vldr	d6, [pc, #512]	@ 802eba8 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x280>
+ 802e9aa:	ee37 7b46 	vsub.f64	d7, d7, d6
+ 802e9ae:	4b82      	ldr	r3, [pc, #520]	@ (802ebb8 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x290>)
+ 802e9b0:	ed83 7b02 	vstr	d7, [r3, #8]
+			  }
+
+			  Plane_X_Backward_Time_Calculation_Continuous(&Backward_Time_X_Total);
+ 802e9b4:	4882      	ldr	r0, [pc, #520]	@ (802ebc0 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x298>)
+ 802e9b6:	f7fc fc4b 	bl	802b250 <Plane_X_Backward_Time_Calculation_Continuous>
+			  Plane_Change_Road_Backward_Time_Calculation_Continuous(&Lane_Change_Time_Total_Y);
+ 802e9ba:	4882      	ldr	r0, [pc, #520]	@ (802ebc4 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x29c>)
+ 802e9bc:	f7fc fd2c 	bl	802b418 <Plane_Change_Road_Backward_Time_Calculation_Continuous>
+			  Plane_Y_Lane_Change_Time_Calculation(&Plane_Complete_Total_XY);
+ 802e9c0:	4881      	ldr	r0, [pc, #516]	@ (802ebc8 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x2a0>)
+ 802e9c2:	f7fc fcc9 	bl	802b358 <Plane_Y_Lane_Change_Time_Calculation>
+
+			  Backward_Count_X=0;
+ 802e9c6:	4b81      	ldr	r3, [pc, #516]	@ (802ebcc <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x2a4>)
+ 802e9c8:	2200      	movs	r2, #0
+ 802e9ca:	601a      	str	r2, [r3, #0]
+			  X_Deri_Angle[0]=Deri_Angle_Deg_X[0];
+ 802e9cc:	4b7a      	ldr	r3, [pc, #488]	@ (802ebb8 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x290>)
+ 802e9ce:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802e9d2:	497f      	ldr	r1, [pc, #508]	@ (802ebd0 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x2a8>)
+ 802e9d4:	e9c1 2300 	strd	r2, r3, [r1]
+			  Swing_Limit_Flag=0;
+ 802e9d8:	4b7e      	ldr	r3, [pc, #504]	@ (802ebd4 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x2ac>)
+ 802e9da:	2200      	movs	r2, #0
+ 802e9dc:	601a      	str	r2, [r3, #0]
+			  Backward_Num_X_Count=0;
+ 802e9de:	4b7e      	ldr	r3, [pc, #504]	@ (802ebd8 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x2b0>)
+ 802e9e0:	2200      	movs	r2, #0
+ 802e9e2:	601a      	str	r2, [r3, #0]
+			  Plane_Complete_Count=0;
+ 802e9e4:	4b7d      	ldr	r3, [pc, #500]	@ (802ebdc <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x2b4>)
+ 802e9e6:	2200      	movs	r2, #0
+ 802e9e8:	601a      	str	r2, [r3, #0]
+			  Robot_Platform_Back_Flag=0;
+ 802e9ea:	4b7d      	ldr	r3, [pc, #500]	@ (802ebe0 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x2b8>)
+ 802e9ec:	2200      	movs	r2, #0
+ 802e9ee:	601a      	str	r2, [r3, #0]
+			  Auto_Job_Back_Time_MS_Count=0;
+ 802e9f0:	4b7c      	ldr	r3, [pc, #496]	@ (802ebe4 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x2bc>)
+ 802e9f2:	2200      	movs	r2, #0
+ 802e9f4:	601a      	str	r2, [r3, #0]
+			  Region_Task_Falg++;
+ 802e9f6:	4b6e      	ldr	r3, [pc, #440]	@ (802ebb0 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x288>)
+ 802e9f8:	681b      	ldr	r3, [r3, #0]
+ 802e9fa:	3301      	adds	r3, #1
+ 802e9fc:	4a6c      	ldr	r2, [pc, #432]	@ (802ebb0 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x288>)
+ 802e9fe:	6013      	str	r3, [r2, #0]
+			  GV.Robot_Move_Speed=CV.PV.Robot_Back_Speed;
+ 802ea00:	4b79      	ldr	r3, [pc, #484]	@ (802ebe8 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x2c0>)
+ 802ea02:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 802ea04:	4a79      	ldr	r2, [pc, #484]	@ (802ebec <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x2c4>)
+ 802ea06:	60d3      	str	r3, [r2, #12]
+			  Backward_Time_Count=0;
+ 802ea08:	4b79      	ldr	r3, [pc, #484]	@ (802ebf0 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x2c8>)
+ 802ea0a:	2200      	movs	r2, #0
+ 802ea0c:	601a      	str	r2, [r3, #0]
+			  break;
+ 802ea0e:	e10d      	b.n	802ec2c <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x304>
+		  case Backward_Task_X:
+			  	CV_Robot_Deri_Angle_Deg_Plane=X_Deri_Angle[0];
+ 802ea10:	4b6f      	ldr	r3, [pc, #444]	@ (802ebd0 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x2a8>)
+ 802ea12:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802ea16:	4977      	ldr	r1, [pc, #476]	@ (802ebf4 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x2cc>)
+ 802ea18:	e9c1 2300 	strd	r2, r3, [r1]
+				Swing_Limit_Contrl();//摆臂限位控制
+ 802ea1c:	f7fe fe1c 	bl	802d658 <Swing_Limit_Contrl>
+				Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin(Robot_Countinus_Speed, CV_Robot_Deri_Angle_Deg_Plane);
+ 802ea20:	4b75      	ldr	r3, [pc, #468]	@ (802ebf8 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x2d0>)
+ 802ea22:	ed93 7b00 	vldr	d7, [r3]
+ 802ea26:	4b73      	ldr	r3, [pc, #460]	@ (802ebf4 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x2cc>)
+ 802ea28:	ed93 6b00 	vldr	d6, [r3]
+ 802ea2c:	eeb0 1b46 	vmov.f64	d1, d6
+ 802ea30:	eeb0 0b47 	vmov.f64	d0, d7
+ 802ea34:	f7fe f8e8 	bl	802cc08 <Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin>
+				Backward_Time_Count++;
+ 802ea38:	4b6d      	ldr	r3, [pc, #436]	@ (802ebf0 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x2c8>)
+ 802ea3a:	681b      	ldr	r3, [r3, #0]
+ 802ea3c:	3301      	adds	r3, #1
+ 802ea3e:	4a6c      	ldr	r2, [pc, #432]	@ (802ebf0 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x2c8>)
+ 802ea40:	6013      	str	r3, [r2, #0]
+				if(Backward_Time_Count>=Backward_Time_X_Total)
+ 802ea42:	4b6b      	ldr	r3, [pc, #428]	@ (802ebf0 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x2c8>)
+ 802ea44:	681a      	ldr	r2, [r3, #0]
+ 802ea46:	4b5e      	ldr	r3, [pc, #376]	@ (802ebc0 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x298>)
+ 802ea48:	681b      	ldr	r3, [r3, #0]
+ 802ea4a:	429a      	cmp	r2, r3
+ 802ea4c:	f2c0 80eb 	blt.w	802ec26 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x2fe>
+				{
+					Backward_Time_Count=0;
+ 802ea50:	4b67      	ldr	r3, [pc, #412]	@ (802ebf0 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x2c8>)
+ 802ea52:	2200      	movs	r2, #0
+ 802ea54:	601a      	str	r2, [r3, #0]
+					Region_Task_Falg++;
+ 802ea56:	4b56      	ldr	r3, [pc, #344]	@ (802ebb0 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x288>)
+ 802ea58:	681b      	ldr	r3, [r3, #0]
+ 802ea5a:	3301      	adds	r3, #1
+ 802ea5c:	4a54      	ldr	r2, [pc, #336]	@ (802ebb0 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x288>)
+ 802ea5e:	6013      	str	r3, [r2, #0]
+					Plane_Complete_Count++;
+ 802ea60:	4b5e      	ldr	r3, [pc, #376]	@ (802ebdc <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x2b4>)
+ 802ea62:	681b      	ldr	r3, [r3, #0]
+ 802ea64:	3301      	adds	r3, #1
+ 802ea66:	4a5d      	ldr	r2, [pc, #372]	@ (802ebdc <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x2b4>)
+ 802ea68:	6013      	str	r3, [r2, #0]
+					int i=0;
+ 802ea6a:	2300      	movs	r3, #0
+ 802ea6c:	607b      	str	r3, [r7, #4]
+					i=Plane_Complete_Count%2;
+ 802ea6e:	4b5b      	ldr	r3, [pc, #364]	@ (802ebdc <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x2b4>)
+ 802ea70:	681b      	ldr	r3, [r3, #0]
+ 802ea72:	2b00      	cmp	r3, #0
+ 802ea74:	f003 0301 	and.w	r3, r3, #1
+ 802ea78:	bfb8      	it	lt
+ 802ea7a:	425b      	neglt	r3, r3
+ 802ea7c:	607b      	str	r3, [r7, #4]
+					if(i==0)
+ 802ea7e:	687b      	ldr	r3, [r7, #4]
+ 802ea80:	2b00      	cmp	r3, #0
+ 802ea82:	d10c      	bne.n	802ea9e <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x176>
+					{
+						X_Deri_Angle[0]=Deri_Angle_Deg_X[0];
+ 802ea84:	4b4c      	ldr	r3, [pc, #304]	@ (802ebb8 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x290>)
+ 802ea86:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802ea8a:	4951      	ldr	r1, [pc, #324]	@ (802ebd0 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x2a8>)
+ 802ea8c:	e9c1 2300 	strd	r2, r3, [r1]
+						X_Deri_Angle[1]=Deri_Angle_Deg_X[1];
+ 802ea90:	4b49      	ldr	r3, [pc, #292]	@ (802ebb8 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x290>)
+ 802ea92:	e9d3 2302 	ldrd	r2, r3, [r3, #8]
+ 802ea96:	494e      	ldr	r1, [pc, #312]	@ (802ebd0 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x2a8>)
+ 802ea98:	e9c1 2302 	strd	r2, r3, [r1, #8]
+ 802ea9c:	e00b      	b.n	802eab6 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x18e>
+					}
+					else
+					{
+						X_Deri_Angle[0]=Deri_Angle_Deg_X[1];
+ 802ea9e:	4b46      	ldr	r3, [pc, #280]	@ (802ebb8 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x290>)
+ 802eaa0:	e9d3 2302 	ldrd	r2, r3, [r3, #8]
+ 802eaa4:	494a      	ldr	r1, [pc, #296]	@ (802ebd0 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x2a8>)
+ 802eaa6:	e9c1 2300 	strd	r2, r3, [r1]
+						X_Deri_Angle[1]=Deri_Angle_Deg_X[0];
+ 802eaaa:	4b43      	ldr	r3, [pc, #268]	@ (802ebb8 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x290>)
+ 802eaac:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802eab0:	4947      	ldr	r1, [pc, #284]	@ (802ebd0 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x2a8>)
+ 802eab2:	e9c1 2302 	strd	r2, r3, [r1, #8]
+					}
+					if(Plane_Complete_Count>=Plane_Complete_Total_XY)
+ 802eab6:	4b49      	ldr	r3, [pc, #292]	@ (802ebdc <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x2b4>)
+ 802eab8:	681a      	ldr	r2, [r3, #0]
+ 802eaba:	4b43      	ldr	r3, [pc, #268]	@ (802ebc8 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x2a0>)
+ 802eabc:	681b      	ldr	r3, [r3, #0]
+ 802eabe:	429a      	cmp	r2, r3
+ 802eac0:	f2c0 80b1 	blt.w	802ec26 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x2fe>
+					{
+						ctl_flag_1 = 1;
+ 802eac4:	4b4d      	ldr	r3, [pc, #308]	@ (802ebfc <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x2d4>)
+ 802eac6:	2201      	movs	r2, #1
+ 802eac8:	601a      	str	r2, [r3, #0]
+						Region_Task_Falg=Region_Auto_Close;
+ 802eaca:	4b39      	ldr	r3, [pc, #228]	@ (802ebb0 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x288>)
+ 802eacc:	2205      	movs	r2, #5
+ 802eace:	601a      	str	r2, [r3, #0]
+					}
+				}
+			  break;
+ 802ead0:	e0a9      	b.n	802ec26 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x2fe>
+
+		  case Turn_To_Y:
+			  	Swing_Limit_Contrl();//摆臂限位控制
+ 802ead2:	f7fe fdc1 	bl	802d658 <Swing_Limit_Contrl>
+				CV_Robot_Deri_Angle_Deg_Plane=Plane_Turn_Angle_Deg;
+ 802ead6:	4b39      	ldr	r3, [pc, #228]	@ (802ebbc <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x294>)
+ 802ead8:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802eadc:	4945      	ldr	r1, [pc, #276]	@ (802ebf4 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x2cc>)
+ 802eade:	e9c1 2300 	strd	r2, r3, [r1]
+				Robot_Posture_Adjus_Plane();
+ 802eae2:	f7fd fa75 	bl	802bfd0 <Robot_Posture_Adjus_Plane>
+				if(Angle_Error_LLL<Error_Cont_Thresh)
+ 802eae6:	4b46      	ldr	r3, [pc, #280]	@ (802ec00 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x2d8>)
+ 802eae8:	ed93 6b00 	vldr	d6, [r3]
+ 802eaec:	4b45      	ldr	r3, [pc, #276]	@ (802ec04 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x2dc>)
+ 802eaee:	ed93 7b00 	vldr	d7, [r3]
+ 802eaf2:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802eaf6:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802eafa:	d504      	bpl.n	802eb06 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x1de>
+				{
+					Region_Task_Falg++;
+ 802eafc:	4b2c      	ldr	r3, [pc, #176]	@ (802ebb0 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x288>)
+ 802eafe:	681b      	ldr	r3, [r3, #0]
+ 802eb00:	3301      	adds	r3, #1
+ 802eb02:	4a2b      	ldr	r2, [pc, #172]	@ (802ebb0 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x288>)
+ 802eb04:	6013      	str	r3, [r2, #0]
+				}
+				Auto_Job_Back_Time_MS_Count=0;
+ 802eb06:	4b37      	ldr	r3, [pc, #220]	@ (802ebe4 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x2bc>)
+ 802eb08:	2200      	movs	r2, #0
+ 802eb0a:	601a      	str	r2, [r3, #0]
+				Robot_Platform_Back_Flag=0;
+ 802eb0c:	4b34      	ldr	r3, [pc, #208]	@ (802ebe0 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x2b8>)
+ 802eb0e:	2200      	movs	r2, #0
+ 802eb10:	601a      	str	r2, [r3, #0]
+				Backward_Time_Count=0;
+ 802eb12:	4b37      	ldr	r3, [pc, #220]	@ (802ebf0 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x2c8>)
+ 802eb14:	2200      	movs	r2, #0
+ 802eb16:	601a      	str	r2, [r3, #0]
+			  break;
+ 802eb18:	e088      	b.n	802ec2c <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x304>
+		  case Lane_Change_Y:
+			  Swing_Limit_Contrl();//摆臂限位控制
+ 802eb1a:	f7fe fd9d 	bl	802d658 <Swing_Limit_Contrl>
+			  Move_Plane_Task_Backwards_Distance_Do_Update(Robot_Countinus_Speed, CV_Robot_Deri_Angle_Deg_Plane);
+ 802eb1e:	4b36      	ldr	r3, [pc, #216]	@ (802ebf8 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x2d0>)
+ 802eb20:	ed93 7b00 	vldr	d7, [r3]
+ 802eb24:	4b33      	ldr	r3, [pc, #204]	@ (802ebf4 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x2cc>)
+ 802eb26:	ed93 6b00 	vldr	d6, [r3]
+ 802eb2a:	eeb0 1b46 	vmov.f64	d1, d6
+ 802eb2e:	eeb0 0b47 	vmov.f64	d0, d7
+ 802eb32:	f7fd ff91 	bl	802ca58 <Move_Plane_Task_Backwards_Distance_Do_Update>
+			  Backward_Time_Count++;
+ 802eb36:	4b2e      	ldr	r3, [pc, #184]	@ (802ebf0 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x2c8>)
+ 802eb38:	681b      	ldr	r3, [r3, #0]
+ 802eb3a:	3301      	adds	r3, #1
+ 802eb3c:	4a2c      	ldr	r2, [pc, #176]	@ (802ebf0 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x2c8>)
+ 802eb3e:	6013      	str	r3, [r2, #0]
+			  if(Backward_Time_Count>=Lane_Change_Time_Total_Y)
+ 802eb40:	4b2b      	ldr	r3, [pc, #172]	@ (802ebf0 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x2c8>)
+ 802eb42:	681a      	ldr	r2, [r3, #0]
+ 802eb44:	4b1f      	ldr	r3, [pc, #124]	@ (802ebc4 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x29c>)
+ 802eb46:	681b      	ldr	r3, [r3, #0]
+ 802eb48:	429a      	cmp	r2, r3
+ 802eb4a:	db6e      	blt.n	802ec2a <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x302>
+			  {
+				  Region_Task_Falg++;
+ 802eb4c:	4b18      	ldr	r3, [pc, #96]	@ (802ebb0 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x288>)
+ 802eb4e:	681b      	ldr	r3, [r3, #0]
+ 802eb50:	3301      	adds	r3, #1
+ 802eb52:	4a17      	ldr	r2, [pc, #92]	@ (802ebb0 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x288>)
+ 802eb54:	6013      	str	r3, [r2, #0]
+				  Backward_Time_Count=0;
+ 802eb56:	4b26      	ldr	r3, [pc, #152]	@ (802ebf0 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x2c8>)
+ 802eb58:	2200      	movs	r2, #0
+ 802eb5a:	601a      	str	r2, [r3, #0]
+			  }
+			  break;
+ 802eb5c:	e065      	b.n	802ec2a <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x302>
+		  case Turn_Back_X:
+			  CV_Robot_Deri_Angle_Deg_Plane=X_Deri_Angle[0];
+ 802eb5e:	4b1c      	ldr	r3, [pc, #112]	@ (802ebd0 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x2a8>)
+ 802eb60:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802eb64:	4923      	ldr	r1, [pc, #140]	@ (802ebf4 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x2cc>)
+ 802eb66:	e9c1 2300 	strd	r2, r3, [r1]
+			  Swing_Limit_Contrl();
+ 802eb6a:	f7fe fd75 	bl	802d658 <Swing_Limit_Contrl>
+			  Robot_Posture_Adjus_Plane();
+ 802eb6e:	f7fd fa2f 	bl	802bfd0 <Robot_Posture_Adjus_Plane>
+			  if(Angle_Error_LLL<Error_Cont_Thresh)
+ 802eb72:	4b23      	ldr	r3, [pc, #140]	@ (802ec00 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x2d8>)
+ 802eb74:	ed93 6b00 	vldr	d6, [r3]
+ 802eb78:	4b22      	ldr	r3, [pc, #136]	@ (802ec04 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x2dc>)
+ 802eb7a:	ed93 7b00 	vldr	d7, [r3]
+ 802eb7e:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802eb82:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802eb86:	d400      	bmi.n	802eb8a <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x262>
+			  {
+				Region_Task_Falg=1;
+			  }
+			  break;
+ 802eb88:	e050      	b.n	802ec2c <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x304>
+				Region_Task_Falg=1;
+ 802eb8a:	4b09      	ldr	r3, [pc, #36]	@ (802ebb0 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x288>)
+ 802eb8c:	2201      	movs	r2, #1
+ 802eb8e:	601a      	str	r2, [r3, #0]
+			  break;
+ 802eb90:	e04c      	b.n	802ec2c <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x304>
+ 802eb92:	bf00      	nop
+ 802eb94:	f3af 8000 	nop.w
+ 802eb98:	00000000 	.word	0x00000000
+ 802eb9c:	40568000 	.word	0x40568000
+ 802eba0:	00000000 	.word	0x00000000
+ 802eba4:	40668000 	.word	0x40668000
+ 802eba8:	00000000 	.word	0x00000000
+ 802ebac:	40768000 	.word	0x40768000
+ 802ebb0:	2400a6c4 	.word	0x2400a6c4
+ 802ebb4:	2400a788 	.word	0x2400a788
+ 802ebb8:	2400a7b0 	.word	0x2400a7b0
+ 802ebbc:	2400a7a8 	.word	0x2400a7a8
+ 802ebc0:	2400a8cc 	.word	0x2400a8cc
+ 802ebc4:	2400a8d0 	.word	0x2400a8d0
+ 802ebc8:	2400a7a0 	.word	0x2400a7a0
+ 802ebcc:	2400a7d0 	.word	0x2400a7d0
+ 802ebd0:	2400a7c0 	.word	0x2400a7c0
+ 802ebd4:	2400a6f4 	.word	0x2400a6f4
+ 802ebd8:	2400a79c 	.word	0x2400a79c
+ 802ebdc:	2400a7a4 	.word	0x2400a7a4
+ 802ebe0:	2400a6f8 	.word	0x2400a6f8
+ 802ebe4:	2400a6fc 	.word	0x2400a6fc
+ 802ebe8:	240002a0 	.word	0x240002a0
+ 802ebec:	24000340 	.word	0x24000340
+ 802ebf0:	2400a8d4 	.word	0x2400a8d4
+ 802ebf4:	2400a6d8 	.word	0x2400a6d8
+ 802ebf8:	2400a760 	.word	0x2400a760
+ 802ebfc:	2400a774 	.word	0x2400a774
+ 802ec00:	2400a9e8 	.word	0x2400a9e8
+ 802ec04:	24000090 	.word	0x24000090
+		  case Region_Auto_Close:
+			  HALT_State_Do();
+ 802ec08:	f001 faae 	bl	8030168 <HALT_State_Do>
+			  Blast_Machine_Close_Fun();//hjb
+ 802ec0c:	f7f7 fcd8 	bl	80265c0 <Blast_Machine_Close_Fun>
+			  Plane_Complete_Count=0;
+ 802ec10:	4b08      	ldr	r3, [pc, #32]	@ (802ec34 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x30c>)
+ 802ec12:	2200      	movs	r2, #0
+ 802ec14:	601a      	str	r2, [r3, #0]
+			  GV.SwingMotor.Target_Velcity =0;
+ 802ec16:	4b08      	ldr	r3, [pc, #32]	@ (802ec38 <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x310>)
+ 802ec18:	2200      	movs	r2, #0
+ 802ec1a:	f8c3 2178 	str.w	r2, [r3, #376]	@ 0x178
+			  break;
+ 802ec1e:	e005      	b.n	802ec2c <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x304>
+		  default:
+			  HALT_State_Do();
+ 802ec20:	f001 faa2 	bl	8030168 <HALT_State_Do>
+			  break;
+ 802ec24:	e002      	b.n	802ec2c <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x304>
+			  break;
+ 802ec26:	bf00      	nop
+ 802ec28:	e000      	b.n	802ec2c <Region_Automated_Task_Func_Continuous_Plane_Uptate_1+0x304>
+			  break;
+ 802ec2a:	bf00      	nop
+	  }
+}
+ 802ec2c:	bf00      	nop
+ 802ec2e:	3708      	adds	r7, #8
+ 802ec30:	46bd      	mov	sp, r7
+ 802ec32:	bd80      	pop	{r7, pc}
+ 802ec34:	2400a7a4 	.word	0x2400a7a4
+ 802ec38:	24000340 	.word	0x24000340
+
+0802ec3c <Region_Automated_Task_Func_Continuous_Horizontal>:
+
+
+
+
+void Region_Automated_Task_Func_Continuous_Horizontal()
+{
+ 802ec3c:	b580      	push	{r7, lr}
+ 802ec3e:	b082      	sub	sp, #8
+ 802ec40:	af00      	add	r7, sp, #0
+	  static int Backward_Time_X_Total;
+	  static int Backward_Time_Count;
+	  static int Lane_Change_Time_Total_Y;
+	  switch (Region_Task_Falg)
+ 802ec42:	4b9a      	ldr	r3, [pc, #616]	@ (802eeac <Region_Automated_Task_Func_Continuous_Horizontal+0x270>)
+ 802ec44:	681b      	ldr	r3, [r3, #0]
+ 802ec46:	2b06      	cmp	r3, #6
+ 802ec48:	f200 8127 	bhi.w	802ee9a <Region_Automated_Task_Func_Continuous_Horizontal+0x25e>
+ 802ec4c:	a201      	add	r2, pc, #4	@ (adr r2, 802ec54 <Region_Automated_Task_Func_Continuous_Horizontal+0x18>)
+ 802ec4e:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 802ec52:	bf00      	nop
+ 802ec54:	0802ec71 	.word	0x0802ec71
+ 802ec58:	0802ecc3 	.word	0x0802ecc3
+ 802ec5c:	0802ecfb 	.word	0x0802ecfb
+ 802ec60:	0802edc7 	.word	0x0802edc7
+ 802ec64:	0802edff 	.word	0x0802edff
+ 802ec68:	0802ee4f 	.word	0x0802ee4f
+ 802ec6c:	0802ee83 	.word	0x0802ee83
+	  {
+		  case Parameter_Calculation:
+			  Horiz_Angle_Judge();
+ 802ec70:	f7fc fcea 	bl	802b648 <Horiz_Angle_Judge>
+			  Deri_Angle_Deg_X[0]=CV_Robot_Deri_Angle_Deg_Grity;
+ 802ec74:	4b8e      	ldr	r3, [pc, #568]	@ (802eeb0 <Region_Automated_Task_Func_Continuous_Horizontal+0x274>)
+ 802ec76:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802ec7a:	498e      	ldr	r1, [pc, #568]	@ (802eeb4 <Region_Automated_Task_Func_Continuous_Horizontal+0x278>)
+ 802ec7c:	e9c1 2300 	strd	r2, r3, [r1]
+			  Horiz_Angle_Judge_Region();
+ 802ec80:	f7fc ff6e 	bl	802bb60 <Horiz_Angle_Judge_Region>
+			  Horizontal_Turn_Angle_Deg=0;
+ 802ec84:	498c      	ldr	r1, [pc, #560]	@ (802eeb8 <Region_Automated_Task_Func_Continuous_Horizontal+0x27c>)
+ 802ec86:	f04f 0200 	mov.w	r2, #0
+ 802ec8a:	f04f 0300 	mov.w	r3, #0
+ 802ec8e:	e9c1 2300 	strd	r2, r3, [r1]
+
+			  Horizontal_X_Backward_Time_Calculation_Continuous(&Backward_Time_X_Total);
+ 802ec92:	488a      	ldr	r0, [pc, #552]	@ (802eebc <Region_Automated_Task_Func_Continuous_Horizontal+0x280>)
+ 802ec94:	f7fc fb30 	bl	802b2f8 <Horizontal_X_Backward_Time_Calculation_Continuous>
+			  Horizontal_Change_Road_Backward_Time_Calculation_Continuous(&Lane_Change_Time_Total_Y);
+ 802ec98:	4889      	ldr	r0, [pc, #548]	@ (802eec0 <Region_Automated_Task_Func_Continuous_Horizontal+0x284>)
+ 802ec9a:	f7fc fc0d 	bl	802b4b8 <Horizontal_Change_Road_Backward_Time_Calculation_Continuous>
+			  Horizontal_Y_Lane_Change_Time_Calculation(&Horizontal_Complete_Total_XY);
+ 802ec9e:	4889      	ldr	r0, [pc, #548]	@ (802eec4 <Region_Automated_Task_Func_Continuous_Horizontal+0x288>)
+ 802eca0:	f7fc fb7c 	bl	802b39c <Horizontal_Y_Lane_Change_Time_Calculation>
+			  Region_Task_Falg++;
+ 802eca4:	4b81      	ldr	r3, [pc, #516]	@ (802eeac <Region_Automated_Task_Func_Continuous_Horizontal+0x270>)
+ 802eca6:	681b      	ldr	r3, [r3, #0]
+ 802eca8:	3301      	adds	r3, #1
+ 802ecaa:	4a80      	ldr	r2, [pc, #512]	@ (802eeac <Region_Automated_Task_Func_Continuous_Horizontal+0x270>)
+ 802ecac:	6013      	str	r3, [r2, #0]
+			  X_Deri_Angle[0]=Deri_Angle_Deg_X[0];
+ 802ecae:	4b81      	ldr	r3, [pc, #516]	@ (802eeb4 <Region_Automated_Task_Func_Continuous_Horizontal+0x278>)
+ 802ecb0:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802ecb4:	4984      	ldr	r1, [pc, #528]	@ (802eec8 <Region_Automated_Task_Func_Continuous_Horizontal+0x28c>)
+ 802ecb6:	e9c1 2300 	strd	r2, r3, [r1]
+			  Swing_Limit_Flag=0;
+ 802ecba:	4b84      	ldr	r3, [pc, #528]	@ (802eecc <Region_Automated_Task_Func_Continuous_Horizontal+0x290>)
+ 802ecbc:	2200      	movs	r2, #0
+ 802ecbe:	601a      	str	r2, [r3, #0]
+			  break;
+ 802ecc0:	e0ef      	b.n	802eea2 <Region_Automated_Task_Func_Continuous_Horizontal+0x266>
+		  case RE_Horizontal_Turn_To_Desire_Angle:
+			  CV_Robot_Deri_Angle_Deg_Grity=X_Deri_Angle[0];
+ 802ecc2:	4b81      	ldr	r3, [pc, #516]	@ (802eec8 <Region_Automated_Task_Func_Continuous_Horizontal+0x28c>)
+ 802ecc4:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802ecc8:	4979      	ldr	r1, [pc, #484]	@ (802eeb0 <Region_Automated_Task_Func_Continuous_Horizontal+0x274>)
+ 802ecca:	e9c1 2300 	strd	r2, r3, [r1]
+			  Robot_Posture_Adjus_Gravity();
+ 802ecce:	f7fd f8af 	bl	802be30 <Robot_Posture_Adjus_Gravity>
+			  if(Angle_Error_LLL<Error_Cont_Thresh)
+ 802ecd2:	4b7f      	ldr	r3, [pc, #508]	@ (802eed0 <Region_Automated_Task_Func_Continuous_Horizontal+0x294>)
+ 802ecd4:	ed93 6b00 	vldr	d6, [r3]
+ 802ecd8:	4b7e      	ldr	r3, [pc, #504]	@ (802eed4 <Region_Automated_Task_Func_Continuous_Horizontal+0x298>)
+ 802ecda:	ed93 7b00 	vldr	d7, [r3]
+ 802ecde:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802ece2:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802ece6:	d504      	bpl.n	802ecf2 <Region_Automated_Task_Func_Continuous_Horizontal+0xb6>
+			  {
+				Region_Task_Falg++;
+ 802ece8:	4b70      	ldr	r3, [pc, #448]	@ (802eeac <Region_Automated_Task_Func_Continuous_Horizontal+0x270>)
+ 802ecea:	681b      	ldr	r3, [r3, #0]
+ 802ecec:	3301      	adds	r3, #1
+ 802ecee:	4a6f      	ldr	r2, [pc, #444]	@ (802eeac <Region_Automated_Task_Func_Continuous_Horizontal+0x270>)
+ 802ecf0:	6013      	str	r3, [r2, #0]
+			  }
+			  Backward_Time_Count=0;
+ 802ecf2:	4b79      	ldr	r3, [pc, #484]	@ (802eed8 <Region_Automated_Task_Func_Continuous_Horizontal+0x29c>)
+ 802ecf4:	2200      	movs	r2, #0
+ 802ecf6:	601a      	str	r2, [r3, #0]
+			  break;
+ 802ecf8:	e0d3      	b.n	802eea2 <Region_Automated_Task_Func_Continuous_Horizontal+0x266>
+		  case RE_Horizontal_Backward_Task_X:
+			  Horiz_Angle_Judge();
+ 802ecfa:	f7fc fca5 	bl	802b648 <Horiz_Angle_Judge>
+			  Horiz_Angle_Judge_Region();
+ 802ecfe:	f7fc ff2f 	bl	802bb60 <Horiz_Angle_Judge_Region>
+			  Swing_Limit_Contrl();//摆臂限位控制
+ 802ed02:	f7fe fca9 	bl	802d658 <Swing_Limit_Contrl>
+			  CV_Robot_Deri_Angle_Deg_Grity=X_Deri_Angle[0];
+ 802ed06:	4b70      	ldr	r3, [pc, #448]	@ (802eec8 <Region_Automated_Task_Func_Continuous_Horizontal+0x28c>)
+ 802ed08:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802ed0c:	4968      	ldr	r1, [pc, #416]	@ (802eeb0 <Region_Automated_Task_Func_Continuous_Horizontal+0x274>)
+ 802ed0e:	e9c1 2300 	strd	r2, r3, [r1]
+			  Move_Horizontal_Vertical_Task_Backwards_Do_Backward(Robot_Countinus_Speed,CV_Robot_Deri_Angle_Deg_Grity);
+ 802ed12:	4b72      	ldr	r3, [pc, #456]	@ (802eedc <Region_Automated_Task_Func_Continuous_Horizontal+0x2a0>)
+ 802ed14:	ed93 7b00 	vldr	d7, [r3]
+ 802ed18:	4b65      	ldr	r3, [pc, #404]	@ (802eeb0 <Region_Automated_Task_Func_Continuous_Horizontal+0x274>)
+ 802ed1a:	ed93 6b00 	vldr	d6, [r3]
+ 802ed1e:	eeb0 1b46 	vmov.f64	d1, d6
+ 802ed22:	eeb0 0b47 	vmov.f64	d0, d7
+ 802ed26:	f7fd fe43 	bl	802c9b0 <Move_Horizontal_Vertical_Task_Backwards_Do_Backward>
+			  Backward_Time_Count++;
+ 802ed2a:	4b6b      	ldr	r3, [pc, #428]	@ (802eed8 <Region_Automated_Task_Func_Continuous_Horizontal+0x29c>)
+ 802ed2c:	681b      	ldr	r3, [r3, #0]
+ 802ed2e:	3301      	adds	r3, #1
+ 802ed30:	4a69      	ldr	r2, [pc, #420]	@ (802eed8 <Region_Automated_Task_Func_Continuous_Horizontal+0x29c>)
+ 802ed32:	6013      	str	r3, [r2, #0]
+			  if(Backward_Time_Count>=Backward_Time_X_Total)
+ 802ed34:	4b68      	ldr	r3, [pc, #416]	@ (802eed8 <Region_Automated_Task_Func_Continuous_Horizontal+0x29c>)
+ 802ed36:	681a      	ldr	r2, [r3, #0]
+ 802ed38:	4b60      	ldr	r3, [pc, #384]	@ (802eebc <Region_Automated_Task_Func_Continuous_Horizontal+0x280>)
+ 802ed3a:	681b      	ldr	r3, [r3, #0]
+ 802ed3c:	429a      	cmp	r2, r3
+ 802ed3e:	db3e      	blt.n	802edbe <Region_Automated_Task_Func_Continuous_Horizontal+0x182>
+			  {
+					Backward_Time_Count=0;
+ 802ed40:	4b65      	ldr	r3, [pc, #404]	@ (802eed8 <Region_Automated_Task_Func_Continuous_Horizontal+0x29c>)
+ 802ed42:	2200      	movs	r2, #0
+ 802ed44:	601a      	str	r2, [r3, #0]
+					Region_Task_Falg++;
+ 802ed46:	4b59      	ldr	r3, [pc, #356]	@ (802eeac <Region_Automated_Task_Func_Continuous_Horizontal+0x270>)
+ 802ed48:	681b      	ldr	r3, [r3, #0]
+ 802ed4a:	3301      	adds	r3, #1
+ 802ed4c:	4a57      	ldr	r2, [pc, #348]	@ (802eeac <Region_Automated_Task_Func_Continuous_Horizontal+0x270>)
+ 802ed4e:	6013      	str	r3, [r2, #0]
+					Plane_Complete_Count++;
+ 802ed50:	4b63      	ldr	r3, [pc, #396]	@ (802eee0 <Region_Automated_Task_Func_Continuous_Horizontal+0x2a4>)
+ 802ed52:	681b      	ldr	r3, [r3, #0]
+ 802ed54:	3301      	adds	r3, #1
+ 802ed56:	4a62      	ldr	r2, [pc, #392]	@ (802eee0 <Region_Automated_Task_Func_Continuous_Horizontal+0x2a4>)
+ 802ed58:	6013      	str	r3, [r2, #0]
+					int i=0;
+ 802ed5a:	2300      	movs	r3, #0
+ 802ed5c:	607b      	str	r3, [r7, #4]
+					i=Plane_Complete_Count%2;
+ 802ed5e:	4b60      	ldr	r3, [pc, #384]	@ (802eee0 <Region_Automated_Task_Func_Continuous_Horizontal+0x2a4>)
+ 802ed60:	681b      	ldr	r3, [r3, #0]
+ 802ed62:	2b00      	cmp	r3, #0
+ 802ed64:	f003 0301 	and.w	r3, r3, #1
+ 802ed68:	bfb8      	it	lt
+ 802ed6a:	425b      	neglt	r3, r3
+ 802ed6c:	607b      	str	r3, [r7, #4]
+					if(i==0)
+ 802ed6e:	687b      	ldr	r3, [r7, #4]
+ 802ed70:	2b00      	cmp	r3, #0
+ 802ed72:	d10c      	bne.n	802ed8e <Region_Automated_Task_Func_Continuous_Horizontal+0x152>
+					{
+						X_Deri_Angle[0]=Deri_Angle_Deg_X[0];
+ 802ed74:	4b4f      	ldr	r3, [pc, #316]	@ (802eeb4 <Region_Automated_Task_Func_Continuous_Horizontal+0x278>)
+ 802ed76:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802ed7a:	4953      	ldr	r1, [pc, #332]	@ (802eec8 <Region_Automated_Task_Func_Continuous_Horizontal+0x28c>)
+ 802ed7c:	e9c1 2300 	strd	r2, r3, [r1]
+						X_Deri_Angle[1]=Deri_Angle_Deg_X[1];
+ 802ed80:	4b4c      	ldr	r3, [pc, #304]	@ (802eeb4 <Region_Automated_Task_Func_Continuous_Horizontal+0x278>)
+ 802ed82:	e9d3 2302 	ldrd	r2, r3, [r3, #8]
+ 802ed86:	4950      	ldr	r1, [pc, #320]	@ (802eec8 <Region_Automated_Task_Func_Continuous_Horizontal+0x28c>)
+ 802ed88:	e9c1 2302 	strd	r2, r3, [r1, #8]
+ 802ed8c:	e00b      	b.n	802eda6 <Region_Automated_Task_Func_Continuous_Horizontal+0x16a>
+					}
+					else
+					{
+						X_Deri_Angle[0]=Deri_Angle_Deg_X[1];
+ 802ed8e:	4b49      	ldr	r3, [pc, #292]	@ (802eeb4 <Region_Automated_Task_Func_Continuous_Horizontal+0x278>)
+ 802ed90:	e9d3 2302 	ldrd	r2, r3, [r3, #8]
+ 802ed94:	494c      	ldr	r1, [pc, #304]	@ (802eec8 <Region_Automated_Task_Func_Continuous_Horizontal+0x28c>)
+ 802ed96:	e9c1 2300 	strd	r2, r3, [r1]
+						X_Deri_Angle[1]=Deri_Angle_Deg_X[0];
+ 802ed9a:	4b46      	ldr	r3, [pc, #280]	@ (802eeb4 <Region_Automated_Task_Func_Continuous_Horizontal+0x278>)
+ 802ed9c:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802eda0:	4949      	ldr	r1, [pc, #292]	@ (802eec8 <Region_Automated_Task_Func_Continuous_Horizontal+0x28c>)
+ 802eda2:	e9c1 2302 	strd	r2, r3, [r1, #8]
+					}
+					if(Plane_Complete_Count>=Horizontal_Complete_Total_XY)
+ 802eda6:	4b4e      	ldr	r3, [pc, #312]	@ (802eee0 <Region_Automated_Task_Func_Continuous_Horizontal+0x2a4>)
+ 802eda8:	681a      	ldr	r2, [r3, #0]
+ 802edaa:	4b46      	ldr	r3, [pc, #280]	@ (802eec4 <Region_Automated_Task_Func_Continuous_Horizontal+0x288>)
+ 802edac:	681b      	ldr	r3, [r3, #0]
+ 802edae:	429a      	cmp	r2, r3
+ 802edb0:	db05      	blt.n	802edbe <Region_Automated_Task_Func_Continuous_Horizontal+0x182>
+					{
+						ctl_flag_1 = 1;
+ 802edb2:	4b4c      	ldr	r3, [pc, #304]	@ (802eee4 <Region_Automated_Task_Func_Continuous_Horizontal+0x2a8>)
+ 802edb4:	2201      	movs	r2, #1
+ 802edb6:	601a      	str	r2, [r3, #0]
+						Region_Task_Falg=RE_Horizontal_Region_Auto_Close;
+ 802edb8:	4b3c      	ldr	r3, [pc, #240]	@ (802eeac <Region_Automated_Task_Func_Continuous_Horizontal+0x270>)
+ 802edba:	2206      	movs	r2, #6
+ 802edbc:	601a      	str	r2, [r3, #0]
+					}
+				}
+				Robot_Platform_Back_Flag_Y=0;
+ 802edbe:	4b4a      	ldr	r3, [pc, #296]	@ (802eee8 <Region_Automated_Task_Func_Continuous_Horizontal+0x2ac>)
+ 802edc0:	2200      	movs	r2, #0
+ 802edc2:	601a      	str	r2, [r3, #0]
+			  break;
+ 802edc4:	e06d      	b.n	802eea2 <Region_Automated_Task_Func_Continuous_Horizontal+0x266>
+		  case RE_Horizontal_Turn_To_Y:
+			  Swing_Limit_Contrl();//摆臂限位控制
+ 802edc6:	f7fe fc47 	bl	802d658 <Swing_Limit_Contrl>
+			  CV_Robot_Deri_Angle_Deg_Grity=Horizontal_Turn_Angle_Deg;
+ 802edca:	4b3b      	ldr	r3, [pc, #236]	@ (802eeb8 <Region_Automated_Task_Func_Continuous_Horizontal+0x27c>)
+ 802edcc:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802edd0:	4937      	ldr	r1, [pc, #220]	@ (802eeb0 <Region_Automated_Task_Func_Continuous_Horizontal+0x274>)
+ 802edd2:	e9c1 2300 	strd	r2, r3, [r1]
+			  Robot_Posture_Adjus_Gravity();
+ 802edd6:	f7fd f82b 	bl	802be30 <Robot_Posture_Adjus_Gravity>
+			  if(Angle_Error_LLL<Error_Cont_Thresh)
+ 802edda:	4b3d      	ldr	r3, [pc, #244]	@ (802eed0 <Region_Automated_Task_Func_Continuous_Horizontal+0x294>)
+ 802eddc:	ed93 6b00 	vldr	d6, [r3]
+ 802ede0:	4b3c      	ldr	r3, [pc, #240]	@ (802eed4 <Region_Automated_Task_Func_Continuous_Horizontal+0x298>)
+ 802ede2:	ed93 7b00 	vldr	d7, [r3]
+ 802ede6:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802edea:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802edee:	d400      	bmi.n	802edf2 <Region_Automated_Task_Func_Continuous_Horizontal+0x1b6>
+			  {
+				  Region_Task_Falg++;
+			  }
+			  break;
+ 802edf0:	e057      	b.n	802eea2 <Region_Automated_Task_Func_Continuous_Horizontal+0x266>
+				  Region_Task_Falg++;
+ 802edf2:	4b2e      	ldr	r3, [pc, #184]	@ (802eeac <Region_Automated_Task_Func_Continuous_Horizontal+0x270>)
+ 802edf4:	681b      	ldr	r3, [r3, #0]
+ 802edf6:	3301      	adds	r3, #1
+ 802edf8:	4a2c      	ldr	r2, [pc, #176]	@ (802eeac <Region_Automated_Task_Func_Continuous_Horizontal+0x270>)
+ 802edfa:	6013      	str	r3, [r2, #0]
+			  break;
+ 802edfc:	e051      	b.n	802eea2 <Region_Automated_Task_Func_Continuous_Horizontal+0x266>
+		  case RE_Horizontal_Lane_Change_Y:
+			  Swing_Limit_Contrl();//摆臂限位控制
+ 802edfe:	f7fe fc2b 	bl	802d658 <Swing_Limit_Contrl>
+			  CV_Robot_Deri_Angle_Deg_Grity=Horizontal_Turn_Angle_Deg;
+ 802ee02:	4b2d      	ldr	r3, [pc, #180]	@ (802eeb8 <Region_Automated_Task_Func_Continuous_Horizontal+0x27c>)
+ 802ee04:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802ee08:	4929      	ldr	r1, [pc, #164]	@ (802eeb0 <Region_Automated_Task_Func_Continuous_Horizontal+0x274>)
+ 802ee0a:	e9c1 2300 	strd	r2, r3, [r1]
+			  Move_Horizontal_Vertical_Task_Backwards_Do_Backward(Robot_Countinus_Speed,CV_Robot_Deri_Angle_Deg_Grity);
+ 802ee0e:	4b33      	ldr	r3, [pc, #204]	@ (802eedc <Region_Automated_Task_Func_Continuous_Horizontal+0x2a0>)
+ 802ee10:	ed93 7b00 	vldr	d7, [r3]
+ 802ee14:	4b26      	ldr	r3, [pc, #152]	@ (802eeb0 <Region_Automated_Task_Func_Continuous_Horizontal+0x274>)
+ 802ee16:	ed93 6b00 	vldr	d6, [r3]
+ 802ee1a:	eeb0 1b46 	vmov.f64	d1, d6
+ 802ee1e:	eeb0 0b47 	vmov.f64	d0, d7
+ 802ee22:	f7fd fdc5 	bl	802c9b0 <Move_Horizontal_Vertical_Task_Backwards_Do_Backward>
+
+			  Backward_Time_Count++;
+ 802ee26:	4b2c      	ldr	r3, [pc, #176]	@ (802eed8 <Region_Automated_Task_Func_Continuous_Horizontal+0x29c>)
+ 802ee28:	681b      	ldr	r3, [r3, #0]
+ 802ee2a:	3301      	adds	r3, #1
+ 802ee2c:	4a2a      	ldr	r2, [pc, #168]	@ (802eed8 <Region_Automated_Task_Func_Continuous_Horizontal+0x29c>)
+ 802ee2e:	6013      	str	r3, [r2, #0]
+			  if(Backward_Time_Count>=Lane_Change_Time_Total_Y)
+ 802ee30:	4b29      	ldr	r3, [pc, #164]	@ (802eed8 <Region_Automated_Task_Func_Continuous_Horizontal+0x29c>)
+ 802ee32:	681a      	ldr	r2, [r3, #0]
+ 802ee34:	4b22      	ldr	r3, [pc, #136]	@ (802eec0 <Region_Automated_Task_Func_Continuous_Horizontal+0x284>)
+ 802ee36:	681b      	ldr	r3, [r3, #0]
+ 802ee38:	429a      	cmp	r2, r3
+ 802ee3a:	db31      	blt.n	802eea0 <Region_Automated_Task_Func_Continuous_Horizontal+0x264>
+			  {
+				  Backward_Time_Count=0;
+ 802ee3c:	4b26      	ldr	r3, [pc, #152]	@ (802eed8 <Region_Automated_Task_Func_Continuous_Horizontal+0x29c>)
+ 802ee3e:	2200      	movs	r2, #0
+ 802ee40:	601a      	str	r2, [r3, #0]
+				  Region_Task_Falg++;
+ 802ee42:	4b1a      	ldr	r3, [pc, #104]	@ (802eeac <Region_Automated_Task_Func_Continuous_Horizontal+0x270>)
+ 802ee44:	681b      	ldr	r3, [r3, #0]
+ 802ee46:	3301      	adds	r3, #1
+ 802ee48:	4a18      	ldr	r2, [pc, #96]	@ (802eeac <Region_Automated_Task_Func_Continuous_Horizontal+0x270>)
+ 802ee4a:	6013      	str	r3, [r2, #0]
+			  }
+			  break;
+ 802ee4c:	e028      	b.n	802eea0 <Region_Automated_Task_Func_Continuous_Horizontal+0x264>
+		  case RE_Horizontal_Turn_Back_X:
+			  CV_Robot_Deri_Angle_Deg_Grity=X_Deri_Angle[0];
+ 802ee4e:	4b1e      	ldr	r3, [pc, #120]	@ (802eec8 <Region_Automated_Task_Func_Continuous_Horizontal+0x28c>)
+ 802ee50:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802ee54:	4916      	ldr	r1, [pc, #88]	@ (802eeb0 <Region_Automated_Task_Func_Continuous_Horizontal+0x274>)
+ 802ee56:	e9c1 2300 	strd	r2, r3, [r1]
+			  Swing_Limit_Contrl();
+ 802ee5a:	f7fe fbfd 	bl	802d658 <Swing_Limit_Contrl>
+			  Robot_Posture_Adjus_Gravity();
+ 802ee5e:	f7fc ffe7 	bl	802be30 <Robot_Posture_Adjus_Gravity>
+			  if(Angle_Error_LLL<Error_Cont_Thresh)
+ 802ee62:	4b1b      	ldr	r3, [pc, #108]	@ (802eed0 <Region_Automated_Task_Func_Continuous_Horizontal+0x294>)
+ 802ee64:	ed93 6b00 	vldr	d6, [r3]
+ 802ee68:	4b1a      	ldr	r3, [pc, #104]	@ (802eed4 <Region_Automated_Task_Func_Continuous_Horizontal+0x298>)
+ 802ee6a:	ed93 7b00 	vldr	d7, [r3]
+ 802ee6e:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802ee72:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802ee76:	d400      	bmi.n	802ee7a <Region_Automated_Task_Func_Continuous_Horizontal+0x23e>
+			  {
+				Region_Task_Falg=RE_Horizontal_Backward_Task_X;
+			  }
+			  break;
+ 802ee78:	e013      	b.n	802eea2 <Region_Automated_Task_Func_Continuous_Horizontal+0x266>
+				Region_Task_Falg=RE_Horizontal_Backward_Task_X;
+ 802ee7a:	4b0c      	ldr	r3, [pc, #48]	@ (802eeac <Region_Automated_Task_Func_Continuous_Horizontal+0x270>)
+ 802ee7c:	2202      	movs	r2, #2
+ 802ee7e:	601a      	str	r2, [r3, #0]
+			  break;
+ 802ee80:	e00f      	b.n	802eea2 <Region_Automated_Task_Func_Continuous_Horizontal+0x266>
+		  case RE_Horizontal_Region_Auto_Close:
+			  HALT_State_Do();
+ 802ee82:	f001 f971 	bl	8030168 <HALT_State_Do>
+			  Blast_Machine_Close_Fun();//hjb
+ 802ee86:	f7f7 fb9b 	bl	80265c0 <Blast_Machine_Close_Fun>
+			  Plane_Complete_Count=0;
+ 802ee8a:	4b15      	ldr	r3, [pc, #84]	@ (802eee0 <Region_Automated_Task_Func_Continuous_Horizontal+0x2a4>)
+ 802ee8c:	2200      	movs	r2, #0
+ 802ee8e:	601a      	str	r2, [r3, #0]
+			  GV.SwingMotor.Target_Velcity =0;
+ 802ee90:	4b16      	ldr	r3, [pc, #88]	@ (802eeec <Region_Automated_Task_Func_Continuous_Horizontal+0x2b0>)
+ 802ee92:	2200      	movs	r2, #0
+ 802ee94:	f8c3 2178 	str.w	r2, [r3, #376]	@ 0x178
+			  break;
+ 802ee98:	e003      	b.n	802eea2 <Region_Automated_Task_Func_Continuous_Horizontal+0x266>
+		  default:
+			  HALT_State_Do();
+ 802ee9a:	f001 f965 	bl	8030168 <HALT_State_Do>
+			  break;
+ 802ee9e:	e000      	b.n	802eea2 <Region_Automated_Task_Func_Continuous_Horizontal+0x266>
+			  break;
+ 802eea0:	bf00      	nop
+	  }
+}
+ 802eea2:	bf00      	nop
+ 802eea4:	3708      	adds	r7, #8
+ 802eea6:	46bd      	mov	sp, r7
+ 802eea8:	bd80      	pop	{r7, pc}
+ 802eeaa:	bf00      	nop
+ 802eeac:	2400a6c4 	.word	0x2400a6c4
+ 802eeb0:	2400a6d0 	.word	0x2400a6d0
+ 802eeb4:	2400a7b0 	.word	0x2400a7b0
+ 802eeb8:	2400a7e8 	.word	0x2400a7e8
+ 802eebc:	2400a8d8 	.word	0x2400a8d8
+ 802eec0:	2400a8dc 	.word	0x2400a8dc
+ 802eec4:	2400a7f0 	.word	0x2400a7f0
+ 802eec8:	2400a7c0 	.word	0x2400a7c0
+ 802eecc:	2400a6f4 	.word	0x2400a6f4
+ 802eed0:	2400a9e8 	.word	0x2400a9e8
+ 802eed4:	24000090 	.word	0x24000090
+ 802eed8:	2400a8e0 	.word	0x2400a8e0
+ 802eedc:	2400a760 	.word	0x2400a760
+ 802eee0:	2400a7a4 	.word	0x2400a7a4
+ 802eee4:	2400a774 	.word	0x2400a774
+ 802eee8:	2400a6e0 	.word	0x2400a6e0
+ 802eeec:	24000340 	.word	0x24000340
+
+0802eef0 <Swing_Mode_Determination>:
+}
+
+
+
+void Swing_Mode_Determination()
+{
+ 802eef0:	b480      	push	{r7}
+ 802eef2:	b085      	sub	sp, #20
+ 802eef4:	af00      	add	r7, sp, #0
+	static double Right_Position;
+	static int S1_Last_Value;
+	static int S2_Last_Value;
+	static int GV_Robot_Swing_Range_Angle_Last;
+	static double Sw_Rust_Mid_Posi;
+	switch(GV_Robot_symmetricalOrNot)
+ 802eef6:	4b58      	ldr	r3, [pc, #352]	@ (802f058 <Swing_Mode_Determination+0x168>)
+ 802eef8:	681b      	ldr	r3, [r3, #0]
+ 802eefa:	2b01      	cmp	r3, #1
+ 802eefc:	d002      	beq.n	802ef04 <Swing_Mode_Determination+0x14>
+ 802eefe:	2b02      	cmp	r3, #2
+ 802ef00:	d042      	beq.n	802ef88 <Swing_Mode_Determination+0x98>
+			}
+			S1_Last_Value=P_MK32->CH12_S1;
+			S2_Last_Value=P_MK32->CH13_S2;
+			break;
+	}
+}
+ 802ef02:	e09f      	b.n	802f044 <Swing_Mode_Determination+0x154>
+			if(GV_Robot_Swing_Range_Angle_Last!=GV_Robot_Swing_Range_Angle)
+ 802ef04:	4b55      	ldr	r3, [pc, #340]	@ (802f05c <Swing_Mode_Determination+0x16c>)
+ 802ef06:	681a      	ldr	r2, [r3, #0]
+ 802ef08:	4b55      	ldr	r3, [pc, #340]	@ (802f060 <Swing_Mode_Determination+0x170>)
+ 802ef0a:	681b      	ldr	r3, [r3, #0]
+ 802ef0c:	429a      	cmp	r2, r3
+ 802ef0e:	d009      	beq.n	802ef24 <Swing_Mode_Determination+0x34>
+				Sw_Rust_Mid_Posi=GV.SwingMotor.Real_Position;//需检测修改
+ 802ef10:	4b54      	ldr	r3, [pc, #336]	@ (802f064 <Swing_Mode_Determination+0x174>)
+ 802ef12:	f8d3 319c 	ldr.w	r3, [r3, #412]	@ 0x19c
+ 802ef16:	ee07 3a90 	vmov	s15, r3
+ 802ef1a:	eeb8 7be7 	vcvt.f64.s32	d7, s15
+ 802ef1e:	4b52      	ldr	r3, [pc, #328]	@ (802f068 <Swing_Mode_Determination+0x178>)
+ 802ef20:	ed83 7b00 	vstr	d7, [r3]
+			double Swi_Range=((double)GV_Robot_Swing_Range_Angle)*TT_One_Deg_Count/2;
+ 802ef24:	4b4e      	ldr	r3, [pc, #312]	@ (802f060 <Swing_Mode_Determination+0x170>)
+ 802ef26:	681b      	ldr	r3, [r3, #0]
+ 802ef28:	ee07 3a90 	vmov	s15, r3
+ 802ef2c:	eeb8 7be7 	vcvt.f64.s32	d7, s15
+ 802ef30:	ed9f 6b47 	vldr	d6, [pc, #284]	@ 802f050 <Swing_Mode_Determination+0x160>
+ 802ef34:	ee27 6b06 	vmul.f64	d6, d7, d6
+ 802ef38:	eeb0 5b00 	vmov.f64	d5, #0	@ 0x40000000  2.0
+ 802ef3c:	ee86 7b05 	vdiv.f64	d7, d6, d5
+ 802ef40:	ed87 7b00 	vstr	d7, [r7]
+			Left_Target_Pos=Sw_Rust_Mid_Posi+Swi_Range;//左侧边界
+ 802ef44:	4b48      	ldr	r3, [pc, #288]	@ (802f068 <Swing_Mode_Determination+0x178>)
+ 802ef46:	ed93 6b00 	vldr	d6, [r3]
+ 802ef4a:	ed97 7b00 	vldr	d7, [r7]
+ 802ef4e:	ee36 7b07 	vadd.f64	d7, d6, d7
+ 802ef52:	4b46      	ldr	r3, [pc, #280]	@ (802f06c <Swing_Mode_Determination+0x17c>)
+ 802ef54:	ed83 7b00 	vstr	d7, [r3]
+			Right_Target_Pos=Sw_Rust_Mid_Posi-Swi_Range;//右侧边界
+ 802ef58:	4b43      	ldr	r3, [pc, #268]	@ (802f068 <Swing_Mode_Determination+0x178>)
+ 802ef5a:	ed93 6b00 	vldr	d6, [r3]
+ 802ef5e:	ed97 7b00 	vldr	d7, [r7]
+ 802ef62:	ee36 7b47 	vsub.f64	d7, d6, d7
+ 802ef66:	4b42      	ldr	r3, [pc, #264]	@ (802f070 <Swing_Mode_Determination+0x180>)
+ 802ef68:	ed83 7b00 	vstr	d7, [r3]
+			Swi_Range_Auto=GV_Robot_Swing_Range_Angle;
+ 802ef6c:	4b3c      	ldr	r3, [pc, #240]	@ (802f060 <Swing_Mode_Determination+0x170>)
+ 802ef6e:	681b      	ldr	r3, [r3, #0]
+ 802ef70:	ee07 3a90 	vmov	s15, r3
+ 802ef74:	eeb8 7be7 	vcvt.f64.s32	d7, s15
+ 802ef78:	4b3e      	ldr	r3, [pc, #248]	@ (802f074 <Swing_Mode_Determination+0x184>)
+ 802ef7a:	ed83 7b00 	vstr	d7, [r3]
+			GV_Robot_Swing_Range_Angle_Last=GV_Robot_Swing_Range_Angle;
+ 802ef7e:	4b38      	ldr	r3, [pc, #224]	@ (802f060 <Swing_Mode_Determination+0x170>)
+ 802ef80:	681b      	ldr	r3, [r3, #0]
+ 802ef82:	4a36      	ldr	r2, [pc, #216]	@ (802f05c <Swing_Mode_Determination+0x16c>)
+ 802ef84:	6013      	str	r3, [r2, #0]
+			break;
+ 802ef86:	e05d      	b.n	802f044 <Swing_Mode_Determination+0x154>
+			if(P_MK32->CH12_S1!=S1_Last_Value)
+ 802ef88:	4b3b      	ldr	r3, [pc, #236]	@ (802f078 <Swing_Mode_Determination+0x188>)
+ 802ef8a:	681b      	ldr	r3, [r3, #0]
+ 802ef8c:	6b5a      	ldr	r2, [r3, #52]	@ 0x34
+ 802ef8e:	4b3b      	ldr	r3, [pc, #236]	@ (802f07c <Swing_Mode_Determination+0x18c>)
+ 802ef90:	681b      	ldr	r3, [r3, #0]
+ 802ef92:	429a      	cmp	r2, r3
+ 802ef94:	d00a      	beq.n	802efac <Swing_Mode_Determination+0xbc>
+				Left_Position=GV.SwingMotor.Real_Position;
+ 802ef96:	4b33      	ldr	r3, [pc, #204]	@ (802f064 <Swing_Mode_Determination+0x174>)
+ 802ef98:	f8d3 319c 	ldr.w	r3, [r3, #412]	@ 0x19c
+ 802ef9c:	ee07 3a90 	vmov	s15, r3
+ 802efa0:	eeb8 7be7 	vcvt.f64.s32	d7, s15
+ 802efa4:	4b36      	ldr	r3, [pc, #216]	@ (802f080 <Swing_Mode_Determination+0x190>)
+ 802efa6:	ed83 7b00 	vstr	d7, [r3]
+ 802efaa:	e040      	b.n	802f02e <Swing_Mode_Determination+0x13e>
+			else if(P_MK32->CH13_S2!=S2_Last_Value)
+ 802efac:	4b32      	ldr	r3, [pc, #200]	@ (802f078 <Swing_Mode_Determination+0x188>)
+ 802efae:	681b      	ldr	r3, [r3, #0]
+ 802efb0:	6b9a      	ldr	r2, [r3, #56]	@ 0x38
+ 802efb2:	4b34      	ldr	r3, [pc, #208]	@ (802f084 <Swing_Mode_Determination+0x194>)
+ 802efb4:	681b      	ldr	r3, [r3, #0]
+ 802efb6:	429a      	cmp	r2, r3
+ 802efb8:	d00a      	beq.n	802efd0 <Swing_Mode_Determination+0xe0>
+				Right_Position=GV.SwingMotor.Real_Position;
+ 802efba:	4b2a      	ldr	r3, [pc, #168]	@ (802f064 <Swing_Mode_Determination+0x174>)
+ 802efbc:	f8d3 319c 	ldr.w	r3, [r3, #412]	@ 0x19c
+ 802efc0:	ee07 3a90 	vmov	s15, r3
+ 802efc4:	eeb8 7be7 	vcvt.f64.s32	d7, s15
+ 802efc8:	4b2f      	ldr	r3, [pc, #188]	@ (802f088 <Swing_Mode_Determination+0x198>)
+ 802efca:	ed83 7b00 	vstr	d7, [r3]
+ 802efce:	e02e      	b.n	802f02e <Swing_Mode_Determination+0x13e>
+				Left_Target_Pos=Left_Position;
+ 802efd0:	4b2b      	ldr	r3, [pc, #172]	@ (802f080 <Swing_Mode_Determination+0x190>)
+ 802efd2:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802efd6:	4925      	ldr	r1, [pc, #148]	@ (802f06c <Swing_Mode_Determination+0x17c>)
+ 802efd8:	e9c1 2300 	strd	r2, r3, [r1]
+				Right_Target_Pos=Right_Position;
+ 802efdc:	4b2a      	ldr	r3, [pc, #168]	@ (802f088 <Swing_Mode_Determination+0x198>)
+ 802efde:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 802efe2:	4923      	ldr	r1, [pc, #140]	@ (802f070 <Swing_Mode_Determination+0x180>)
+ 802efe4:	e9c1 2300 	strd	r2, r3, [r1]
+				double Angle_Difference=(fabs(Left_Position-Right_Position))/TT_One_Deg_Count;
+ 802efe8:	4b25      	ldr	r3, [pc, #148]	@ (802f080 <Swing_Mode_Determination+0x190>)
+ 802efea:	ed93 6b00 	vldr	d6, [r3]
+ 802efee:	4b26      	ldr	r3, [pc, #152]	@ (802f088 <Swing_Mode_Determination+0x198>)
+ 802eff0:	ed93 7b00 	vldr	d7, [r3]
+ 802eff4:	ee36 7b47 	vsub.f64	d7, d6, d7
+ 802eff8:	eeb0 6bc7 	vabs.f64	d6, d7
+ 802effc:	ed9f 5b14 	vldr	d5, [pc, #80]	@ 802f050 <Swing_Mode_Determination+0x160>
+ 802f000:	ee86 7b05 	vdiv.f64	d7, d6, d5
+ 802f004:	ed87 7b02 	vstr	d7, [r7, #8]
+				Swi_Range_Auto=(Left_Target_Pos-Right_Target_Pos)/TT_One_Deg_Count/2;
+ 802f008:	4b18      	ldr	r3, [pc, #96]	@ (802f06c <Swing_Mode_Determination+0x17c>)
+ 802f00a:	ed93 6b00 	vldr	d6, [r3]
+ 802f00e:	4b18      	ldr	r3, [pc, #96]	@ (802f070 <Swing_Mode_Determination+0x180>)
+ 802f010:	ed93 7b00 	vldr	d7, [r3]
+ 802f014:	ee36 7b47 	vsub.f64	d7, d6, d7
+ 802f018:	ed9f 5b0d 	vldr	d5, [pc, #52]	@ 802f050 <Swing_Mode_Determination+0x160>
+ 802f01c:	ee87 6b05 	vdiv.f64	d6, d7, d5
+ 802f020:	eeb0 5b00 	vmov.f64	d5, #0	@ 0x40000000  2.0
+ 802f024:	ee86 7b05 	vdiv.f64	d7, d6, d5
+ 802f028:	4b12      	ldr	r3, [pc, #72]	@ (802f074 <Swing_Mode_Determination+0x184>)
+ 802f02a:	ed83 7b00 	vstr	d7, [r3]
+			S1_Last_Value=P_MK32->CH12_S1;
+ 802f02e:	4b12      	ldr	r3, [pc, #72]	@ (802f078 <Swing_Mode_Determination+0x188>)
+ 802f030:	681b      	ldr	r3, [r3, #0]
+ 802f032:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
+ 802f034:	4a11      	ldr	r2, [pc, #68]	@ (802f07c <Swing_Mode_Determination+0x18c>)
+ 802f036:	6013      	str	r3, [r2, #0]
+			S2_Last_Value=P_MK32->CH13_S2;
+ 802f038:	4b0f      	ldr	r3, [pc, #60]	@ (802f078 <Swing_Mode_Determination+0x188>)
+ 802f03a:	681b      	ldr	r3, [r3, #0]
+ 802f03c:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
+ 802f03e:	4a11      	ldr	r2, [pc, #68]	@ (802f084 <Swing_Mode_Determination+0x194>)
+ 802f040:	6013      	str	r3, [r2, #0]
+			break;
+ 802f042:	bf00      	nop
+}
+ 802f044:	bf00      	nop
+ 802f046:	3714      	adds	r7, #20
+ 802f048:	46bd      	mov	sp, r7
+ 802f04a:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 802f04e:	4770      	bx	lr
+ 802f050:	00000000 	.word	0x00000000
+ 802f054:	40c58300 	.word	0x40c58300
+ 802f058:	2400a714 	.word	0x2400a714
+ 802f05c:	2400a8e4 	.word	0x2400a8e4
+ 802f060:	2400a718 	.word	0x2400a718
+ 802f064:	24000340 	.word	0x24000340
+ 802f068:	2400a8e8 	.word	0x2400a8e8
+ 802f06c:	2400a820 	.word	0x2400a820
+ 802f070:	2400a828 	.word	0x2400a828
+ 802f074:	2400a868 	.word	0x2400a868
+ 802f078:	2400a3f8 	.word	0x2400a3f8
+ 802f07c:	2400a8f0 	.word	0x2400a8f0
+ 802f080:	2400a8f8 	.word	0x2400a8f8
+ 802f084:	2400a900 	.word	0x2400a900
+ 802f088:	2400a908 	.word	0x2400a908
+
+0802f08c <Pressure_Adaptive_Function_Uptata>:
+	        sizeof(Set_PushRod_States) / sizeof(transition_t), Current_PushRod_STATE);
+}
+
+
+void Pressure_Adaptive_Function_Uptata(double Press_Dis_Value)
+{
+ 802f08c:	b580      	push	{r7, lr}
+ 802f08e:	b084      	sub	sp, #16
+ 802f090:	af00      	add	r7, sp, #0
+ 802f092:	ed87 0b00 	vstr	d0, [r7]
+//	double Desired_Presss=(double)CV.PV.Robot_Press_Set;
+//	Desired_Presss=-500;
+	//向下压为负值，向上运动为正值
+	double Actual_Value=GV.Force_Value_mN.CMCU_Measuring_value;
+ 802f096:	4b3d      	ldr	r3, [pc, #244]	@ (802f18c <Pressure_Adaptive_Function_Uptata+0x100>)
+ 802f098:	f8d3 328c 	ldr.w	r3, [r3, #652]	@ 0x28c
+ 802f09c:	ee07 3a90 	vmov	s15, r3
+ 802f0a0:	eeb8 7be7 	vcvt.f64.s32	d7, s15
+ 802f0a4:	ed87 7b02 	vstr	d7, [r7, #8]
+	Desired_Presss=-GV_Robot_Press_Set;
+ 802f0a8:	4b39      	ldr	r3, [pc, #228]	@ (802f190 <Pressure_Adaptive_Function_Uptata+0x104>)
+ 802f0aa:	681b      	ldr	r3, [r3, #0]
+ 802f0ac:	425b      	negs	r3, r3
+ 802f0ae:	ee07 3a90 	vmov	s15, r3
+ 802f0b2:	eeb8 7be7 	vcvt.f64.s32	d7, s15
+ 802f0b6:	4b37      	ldr	r3, [pc, #220]	@ (802f194 <Pressure_Adaptive_Function_Uptata+0x108>)
+ 802f0b8:	ed83 7b00 	vstr	d7, [r3]
+	D_value=Actual_Value-Desired_Presss;
+ 802f0bc:	4b35      	ldr	r3, [pc, #212]	@ (802f194 <Pressure_Adaptive_Function_Uptata+0x108>)
+ 802f0be:	ed93 7b00 	vldr	d7, [r3]
+ 802f0c2:	ed97 6b02 	vldr	d6, [r7, #8]
+ 802f0c6:	ee36 7b47 	vsub.f64	d7, d6, d7
+ 802f0ca:	4b33      	ldr	r3, [pc, #204]	@ (802f198 <Pressure_Adaptive_Function_Uptata+0x10c>)
+ 802f0cc:	ed83 7b00 	vstr	d7, [r3]
+//			-800--500
+	switch(PushRod_Flag)
+ 802f0d0:	4b32      	ldr	r3, [pc, #200]	@ (802f19c <Pressure_Adaptive_Function_Uptata+0x110>)
+ 802f0d2:	681b      	ldr	r3, [r3, #0]
+ 802f0d4:	2b02      	cmp	r3, #2
+ 802f0d6:	d039      	beq.n	802f14c <Pressure_Adaptive_Function_Uptata+0xc0>
+ 802f0d8:	2b02      	cmp	r3, #2
+ 802f0da:	dc47      	bgt.n	802f16c <Pressure_Adaptive_Function_Uptata+0xe0>
+ 802f0dc:	2b00      	cmp	r3, #0
+ 802f0de:	d002      	beq.n	802f0e6 <Pressure_Adaptive_Function_Uptata+0x5a>
+ 802f0e0:	2b01      	cmp	r3, #1
+ 802f0e2:	d023      	beq.n	802f12c <Pressure_Adaptive_Function_Uptata+0xa0>
+ 802f0e4:	e042      	b.n	802f16c <Pressure_Adaptive_Function_Uptata+0xe0>
+	{
+		case 0:
+			if(D_value>Press_Dis_Value1)
+ 802f0e6:	4b2c      	ldr	r3, [pc, #176]	@ (802f198 <Pressure_Adaptive_Function_Uptata+0x10c>)
+ 802f0e8:	ed93 6b00 	vldr	d6, [r3]
+ 802f0ec:	4b2c      	ldr	r3, [pc, #176]	@ (802f1a0 <Pressure_Adaptive_Function_Uptata+0x114>)
+ 802f0ee:	ed93 7b00 	vldr	d7, [r3]
+ 802f0f2:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802f0f6:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802f0fa:	dd03      	ble.n	802f104 <Pressure_Adaptive_Function_Uptata+0x78>
+			{
+				PushRod_Flag=2;//压力过小//向下调整
+ 802f0fc:	4b27      	ldr	r3, [pc, #156]	@ (802f19c <Pressure_Adaptive_Function_Uptata+0x110>)
+ 802f0fe:	2202      	movs	r2, #2
+ 802f100:	601a      	str	r2, [r3, #0]
+ 802f102:	e00f      	b.n	802f124 <Pressure_Adaptive_Function_Uptata+0x98>
+			}
+			else if (D_value<-Press_Dis_Value1)
+ 802f104:	4b26      	ldr	r3, [pc, #152]	@ (802f1a0 <Pressure_Adaptive_Function_Uptata+0x114>)
+ 802f106:	ed93 7b00 	vldr	d7, [r3]
+ 802f10a:	eeb1 6b47 	vneg.f64	d6, d7
+ 802f10e:	4b22      	ldr	r3, [pc, #136]	@ (802f198 <Pressure_Adaptive_Function_Uptata+0x10c>)
+ 802f110:	ed93 7b00 	vldr	d7, [r3]
+ 802f114:	eeb4 6bc7 	vcmpe.f64	d6, d7
+ 802f118:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802f11c:	dd02      	ble.n	802f124 <Pressure_Adaptive_Function_Uptata+0x98>
+			{
+				PushRod_Flag=1;//压力过大//`向上调整
+ 802f11e:	4b1f      	ldr	r3, [pc, #124]	@ (802f19c <Pressure_Adaptive_Function_Uptata+0x110>)
+ 802f120:	2201      	movs	r2, #1
+ 802f122:	601a      	str	r2, [r3, #0]
+			}
+			Current_PushRod_STATE = PushRod_HALT;
+ 802f124:	4b1f      	ldr	r3, [pc, #124]	@ (802f1a4 <Pressure_Adaptive_Function_Uptata+0x118>)
+ 802f126:	2200      	movs	r2, #0
+ 802f128:	701a      	strb	r2, [r3, #0]
+			break;
+ 802f12a:	e023      	b.n	802f174 <Pressure_Adaptive_Function_Uptata+0xe8>
+		case 1:
+			Current_PushRod_STATE = PushRod_UP;
+ 802f12c:	4b1d      	ldr	r3, [pc, #116]	@ (802f1a4 <Pressure_Adaptive_Function_Uptata+0x118>)
+ 802f12e:	2201      	movs	r2, #1
+ 802f130:	701a      	strb	r2, [r3, #0]
+			if(D_value>0)
+ 802f132:	4b19      	ldr	r3, [pc, #100]	@ (802f198 <Pressure_Adaptive_Function_Uptata+0x10c>)
+ 802f134:	ed93 7b00 	vldr	d7, [r3]
+ 802f138:	eeb5 7bc0 	vcmpe.f64	d7, #0.0
+ 802f13c:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802f140:	dc00      	bgt.n	802f144 <Pressure_Adaptive_Function_Uptata+0xb8>
+			{
+				PushRod_Flag=0;
+			}
+			break;
+ 802f142:	e017      	b.n	802f174 <Pressure_Adaptive_Function_Uptata+0xe8>
+				PushRod_Flag=0;
+ 802f144:	4b15      	ldr	r3, [pc, #84]	@ (802f19c <Pressure_Adaptive_Function_Uptata+0x110>)
+ 802f146:	2200      	movs	r2, #0
+ 802f148:	601a      	str	r2, [r3, #0]
+			break;
+ 802f14a:	e013      	b.n	802f174 <Pressure_Adaptive_Function_Uptata+0xe8>
+		case 2:
+			Current_PushRod_STATE = PushRod_Down;
+ 802f14c:	4b15      	ldr	r3, [pc, #84]	@ (802f1a4 <Pressure_Adaptive_Function_Uptata+0x118>)
+ 802f14e:	2202      	movs	r2, #2
+ 802f150:	701a      	strb	r2, [r3, #0]
+			if(D_value<0)
+ 802f152:	4b11      	ldr	r3, [pc, #68]	@ (802f198 <Pressure_Adaptive_Function_Uptata+0x10c>)
+ 802f154:	ed93 7b00 	vldr	d7, [r3]
+ 802f158:	eeb5 7bc0 	vcmpe.f64	d7, #0.0
+ 802f15c:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 802f160:	d400      	bmi.n	802f164 <Pressure_Adaptive_Function_Uptata+0xd8>
+			{
+				PushRod_Flag=0;
+			}
+			break;
+ 802f162:	e007      	b.n	802f174 <Pressure_Adaptive_Function_Uptata+0xe8>
+				PushRod_Flag=0;
+ 802f164:	4b0d      	ldr	r3, [pc, #52]	@ (802f19c <Pressure_Adaptive_Function_Uptata+0x110>)
+ 802f166:	2200      	movs	r2, #0
+ 802f168:	601a      	str	r2, [r3, #0]
+			break;
+ 802f16a:	e003      	b.n	802f174 <Pressure_Adaptive_Function_Uptata+0xe8>
+		default:
+			Current_PushRod_STATE = PushRod_HALT;
+ 802f16c:	4b0d      	ldr	r3, [pc, #52]	@ (802f1a4 <Pressure_Adaptive_Function_Uptata+0x118>)
+ 802f16e:	2200      	movs	r2, #0
+ 802f170:	701a      	strb	r2, [r3, #0]
+			break;
+ 802f172:	bf00      	nop
+	}
+	action_perfrom(Set_PushRod_States,
+ 802f174:	4b0b      	ldr	r3, [pc, #44]	@ (802f1a4 <Pressure_Adaptive_Function_Uptata+0x118>)
+ 802f176:	781b      	ldrb	r3, [r3, #0]
+ 802f178:	461a      	mov	r2, r3
+ 802f17a:	2103      	movs	r1, #3
+ 802f17c:	480a      	ldr	r0, [pc, #40]	@ (802f1a8 <Pressure_Adaptive_Function_Uptata+0x11c>)
+ 802f17e:	f7fa fb49 	bl	8029814 <action_perfrom>
+	        sizeof(Set_PushRod_States) / sizeof(transition_t), Current_PushRod_STATE);
+}
+ 802f182:	bf00      	nop
+ 802f184:	3710      	adds	r7, #16
+ 802f186:	46bd      	mov	sp, r7
+ 802f188:	bd80      	pop	{r7, pc}
+ 802f18a:	bf00      	nop
+ 802f18c:	24000340 	.word	0x24000340
+ 802f190:	2400a738 	.word	0x2400a738
+ 802f194:	24000108 	.word	0x24000108
+ 802f198:	2400a878 	.word	0x2400a878
+ 802f19c:	2400a874 	.word	0x2400a874
+ 802f1a0:	24000110 	.word	0x24000110
+ 802f1a4:	2400a700 	.word	0x2400a700
+ 802f1a8:	240000e0 	.word	0x240000e0
+
+0802f1ac <MX_GPIO_Init>:
+     PH1-OSC_OUT (PH1)   ------> RCC_OSC_OUT
+     PA13 (JTMS/SWDIO)   ------> DEBUG_JTMS-SWDIO
+     PA14 (JTCK/SWCLK)   ------> DEBUG_JTCK-SWCLK
+*/
+void MX_GPIO_Init(void)
+{
+ 802f1ac:	b580      	push	{r7, lr}
+ 802f1ae:	b08c      	sub	sp, #48	@ 0x30
+ 802f1b0:	af00      	add	r7, sp, #0
+
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+ 802f1b2:	f107 031c 	add.w	r3, r7, #28
+ 802f1b6:	2200      	movs	r2, #0
+ 802f1b8:	601a      	str	r2, [r3, #0]
+ 802f1ba:	605a      	str	r2, [r3, #4]
+ 802f1bc:	609a      	str	r2, [r3, #8]
+ 802f1be:	60da      	str	r2, [r3, #12]
+ 802f1c0:	611a      	str	r2, [r3, #16]
+
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOE_CLK_ENABLE();
+ 802f1c2:	4b84      	ldr	r3, [pc, #528]	@ (802f3d4 <MX_GPIO_Init+0x228>)
+ 802f1c4:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
+ 802f1c8:	4a82      	ldr	r2, [pc, #520]	@ (802f3d4 <MX_GPIO_Init+0x228>)
+ 802f1ca:	f043 0310 	orr.w	r3, r3, #16
+ 802f1ce:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
+ 802f1d2:	4b80      	ldr	r3, [pc, #512]	@ (802f3d4 <MX_GPIO_Init+0x228>)
+ 802f1d4:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
+ 802f1d8:	f003 0310 	and.w	r3, r3, #16
+ 802f1dc:	61bb      	str	r3, [r7, #24]
+ 802f1de:	69bb      	ldr	r3, [r7, #24]
+  __HAL_RCC_GPIOC_CLK_ENABLE();
+ 802f1e0:	4b7c      	ldr	r3, [pc, #496]	@ (802f3d4 <MX_GPIO_Init+0x228>)
+ 802f1e2:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
+ 802f1e6:	4a7b      	ldr	r2, [pc, #492]	@ (802f3d4 <MX_GPIO_Init+0x228>)
+ 802f1e8:	f043 0304 	orr.w	r3, r3, #4
+ 802f1ec:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
+ 802f1f0:	4b78      	ldr	r3, [pc, #480]	@ (802f3d4 <MX_GPIO_Init+0x228>)
+ 802f1f2:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
+ 802f1f6:	f003 0304 	and.w	r3, r3, #4
+ 802f1fa:	617b      	str	r3, [r7, #20]
+ 802f1fc:	697b      	ldr	r3, [r7, #20]
+  __HAL_RCC_GPIOH_CLK_ENABLE();
+ 802f1fe:	4b75      	ldr	r3, [pc, #468]	@ (802f3d4 <MX_GPIO_Init+0x228>)
+ 802f200:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
+ 802f204:	4a73      	ldr	r2, [pc, #460]	@ (802f3d4 <MX_GPIO_Init+0x228>)
+ 802f206:	f043 0380 	orr.w	r3, r3, #128	@ 0x80
+ 802f20a:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
+ 802f20e:	4b71      	ldr	r3, [pc, #452]	@ (802f3d4 <MX_GPIO_Init+0x228>)
+ 802f210:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
+ 802f214:	f003 0380 	and.w	r3, r3, #128	@ 0x80
+ 802f218:	613b      	str	r3, [r7, #16]
+ 802f21a:	693b      	ldr	r3, [r7, #16]
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+ 802f21c:	4b6d      	ldr	r3, [pc, #436]	@ (802f3d4 <MX_GPIO_Init+0x228>)
+ 802f21e:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
+ 802f222:	4a6c      	ldr	r2, [pc, #432]	@ (802f3d4 <MX_GPIO_Init+0x228>)
+ 802f224:	f043 0301 	orr.w	r3, r3, #1
+ 802f228:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
+ 802f22c:	4b69      	ldr	r3, [pc, #420]	@ (802f3d4 <MX_GPIO_Init+0x228>)
+ 802f22e:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
+ 802f232:	f003 0301 	and.w	r3, r3, #1
+ 802f236:	60fb      	str	r3, [r7, #12]
+ 802f238:	68fb      	ldr	r3, [r7, #12]
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+ 802f23a:	4b66      	ldr	r3, [pc, #408]	@ (802f3d4 <MX_GPIO_Init+0x228>)
+ 802f23c:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
+ 802f240:	4a64      	ldr	r2, [pc, #400]	@ (802f3d4 <MX_GPIO_Init+0x228>)
+ 802f242:	f043 0302 	orr.w	r3, r3, #2
+ 802f246:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
+ 802f24a:	4b62      	ldr	r3, [pc, #392]	@ (802f3d4 <MX_GPIO_Init+0x228>)
+ 802f24c:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
+ 802f250:	f003 0302 	and.w	r3, r3, #2
+ 802f254:	60bb      	str	r3, [r7, #8]
+ 802f256:	68bb      	ldr	r3, [r7, #8]
+  __HAL_RCC_GPIOD_CLK_ENABLE();
+ 802f258:	4b5e      	ldr	r3, [pc, #376]	@ (802f3d4 <MX_GPIO_Init+0x228>)
+ 802f25a:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
+ 802f25e:	4a5d      	ldr	r2, [pc, #372]	@ (802f3d4 <MX_GPIO_Init+0x228>)
+ 802f260:	f043 0308 	orr.w	r3, r3, #8
+ 802f264:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
+ 802f268:	4b5a      	ldr	r3, [pc, #360]	@ (802f3d4 <MX_GPIO_Init+0x228>)
+ 802f26a:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
+ 802f26e:	f003 0308 	and.w	r3, r3, #8
+ 802f272:	607b      	str	r3, [r7, #4]
+ 802f274:	687b      	ldr	r3, [r7, #4]
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOC, S0_RESET_Pin|OUT_0_Pin|OUT_1_Pin|RS485_3_DIR_Pin
+ 802f276:	2200      	movs	r2, #0
+ 802f278:	f240 710d 	movw	r1, #1805	@ 0x70d
+ 802f27c:	4856      	ldr	r0, [pc, #344]	@ (802f3d8 <MX_GPIO_Init+0x22c>)
+ 802f27e:	f008 fb5d 	bl	803793c <HAL_GPIO_WritePin>
+                          |RS485_4_DIR_Pin|E22_RST_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOA, OUT_2_Pin|OUT_3_Pin|OUT_4_Pin|OUT_5_Pin, GPIO_PIN_SET);
+ 802f282:	2201      	movs	r2, #1
+ 802f284:	2139      	movs	r1, #57	@ 0x39
+ 802f286:	4855      	ldr	r0, [pc, #340]	@ (802f3dc <MX_GPIO_Init+0x230>)
+ 802f288:	f008 fb58 	bl	803793c <HAL_GPIO_WritePin>
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(ETH_RST_GPIO_Port, ETH_RST_Pin, GPIO_PIN_RESET);
+ 802f28c:	2200      	movs	r2, #0
+ 802f28e:	2140      	movs	r1, #64	@ 0x40
+ 802f290:	4852      	ldr	r0, [pc, #328]	@ (802f3dc <MX_GPIO_Init+0x230>)
+ 802f292:	f008 fb53 	bl	803793c <HAL_GPIO_WritePin>
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOE, EEPROM_WP_Pin|EEPROM_SCL_Pin|E22_M0_Pin, GPIO_PIN_RESET);
+ 802f296:	2200      	movs	r2, #0
+ 802f298:	f641 0101 	movw	r1, #6145	@ 0x1801
+ 802f29c:	4850      	ldr	r0, [pc, #320]	@ (802f3e0 <MX_GPIO_Init+0x234>)
+ 802f29e:	f008 fb4d 	bl	803793c <HAL_GPIO_WritePin>
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOD, RS485_1_DIR_Pin|RS485_2_DIR_Pin|E28_M0_Pin|E28_M1_Pin
+ 802f2a2:	2200      	movs	r2, #0
+ 802f2a4:	f640 410b 	movw	r1, #3083	@ 0xc0b
+ 802f2a8:	484e      	ldr	r0, [pc, #312]	@ (802f3e4 <MX_GPIO_Init+0x238>)
+ 802f2aa:	f008 fb47 	bl	803793c <HAL_GPIO_WritePin>
+                          |E28_M2_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(E22_M1_GPIO_Port, E22_M1_Pin, GPIO_PIN_RESET);
+ 802f2ae:	2200      	movs	r2, #0
+ 802f2b0:	2180      	movs	r1, #128	@ 0x80
+ 802f2b2:	484d      	ldr	r0, [pc, #308]	@ (802f3e8 <MX_GPIO_Init+0x23c>)
+ 802f2b4:	f008 fb42 	bl	803793c <HAL_GPIO_WritePin>
+
+  /*Configure GPIO pins : PEPin PEPin PEPin PEPin
+                           PEPin PEPin */
+  GPIO_InitStruct.Pin = IN_0_Pin|IN_1_Pin|IN_2_Pin|IN_3_Pin
+ 802f2b8:	f242 037c 	movw	r3, #8316	@ 0x207c
+ 802f2bc:	61fb      	str	r3, [r7, #28]
+                          |IN_4_Pin|EEPROM_SDA_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+ 802f2be:	2300      	movs	r3, #0
+ 802f2c0:	623b      	str	r3, [r7, #32]
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 802f2c2:	2300      	movs	r3, #0
+ 802f2c4:	627b      	str	r3, [r7, #36]	@ 0x24
+  HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
+ 802f2c6:	f107 031c 	add.w	r3, r7, #28
+ 802f2ca:	4619      	mov	r1, r3
+ 802f2cc:	4844      	ldr	r0, [pc, #272]	@ (802f3e0 <MX_GPIO_Init+0x234>)
+ 802f2ce:	f008 f985 	bl	80375dc <HAL_GPIO_Init>
+
+  /*Configure GPIO pin : PtPin */
+  GPIO_InitStruct.Pin = IN_5_Pin;
+ 802f2d2:	f44f 5300 	mov.w	r3, #8192	@ 0x2000
+ 802f2d6:	61fb      	str	r3, [r7, #28]
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+ 802f2d8:	2300      	movs	r3, #0
+ 802f2da:	623b      	str	r3, [r7, #32]
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 802f2dc:	2300      	movs	r3, #0
+ 802f2de:	627b      	str	r3, [r7, #36]	@ 0x24
+  HAL_GPIO_Init(IN_5_GPIO_Port, &GPIO_InitStruct);
+ 802f2e0:	f107 031c 	add.w	r3, r7, #28
+ 802f2e4:	4619      	mov	r1, r3
+ 802f2e6:	483c      	ldr	r0, [pc, #240]	@ (802f3d8 <MX_GPIO_Init+0x22c>)
+ 802f2e8:	f008 f978 	bl	80375dc <HAL_GPIO_Init>
+
+  /*Configure GPIO pins : PCPin PCPin PCPin PCPin
+                           PCPin PCPin */
+  GPIO_InitStruct.Pin = S0_RESET_Pin|OUT_0_Pin|OUT_1_Pin|RS485_3_DIR_Pin
+ 802f2ec:	f240 730d 	movw	r3, #1805	@ 0x70d
+ 802f2f0:	61fb      	str	r3, [r7, #28]
+                          |RS485_4_DIR_Pin|E22_RST_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ 802f2f2:	2301      	movs	r3, #1
+ 802f2f4:	623b      	str	r3, [r7, #32]
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 802f2f6:	2300      	movs	r3, #0
+ 802f2f8:	627b      	str	r3, [r7, #36]	@ 0x24
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 802f2fa:	2300      	movs	r3, #0
+ 802f2fc:	62bb      	str	r3, [r7, #40]	@ 0x28
+  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+ 802f2fe:	f107 031c 	add.w	r3, r7, #28
+ 802f302:	4619      	mov	r1, r3
+ 802f304:	4834      	ldr	r0, [pc, #208]	@ (802f3d8 <MX_GPIO_Init+0x22c>)
+ 802f306:	f008 f969 	bl	80375dc <HAL_GPIO_Init>
+
+  /*Configure GPIO pins : PAPin PAPin PAPin PAPin
+                           PAPin */
+  GPIO_InitStruct.Pin = OUT_2_Pin|OUT_3_Pin|OUT_4_Pin|OUT_5_Pin
+ 802f30a:	2379      	movs	r3, #121	@ 0x79
+ 802f30c:	61fb      	str	r3, [r7, #28]
+                          |ETH_RST_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ 802f30e:	2301      	movs	r3, #1
+ 802f310:	623b      	str	r3, [r7, #32]
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 802f312:	2300      	movs	r3, #0
+ 802f314:	627b      	str	r3, [r7, #36]	@ 0x24
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 802f316:	2300      	movs	r3, #0
+ 802f318:	62bb      	str	r3, [r7, #40]	@ 0x28
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 802f31a:	f107 031c 	add.w	r3, r7, #28
+ 802f31e:	4619      	mov	r1, r3
+ 802f320:	482e      	ldr	r0, [pc, #184]	@ (802f3dc <MX_GPIO_Init+0x230>)
+ 802f322:	f008 f95b 	bl	80375dc <HAL_GPIO_Init>
+
+  /*Configure GPIO pins : PEPin PEPin PEPin */
+  GPIO_InitStruct.Pin = EEPROM_WP_Pin|EEPROM_SCL_Pin|E22_M0_Pin;
+ 802f326:	f641 0301 	movw	r3, #6145	@ 0x1801
+ 802f32a:	61fb      	str	r3, [r7, #28]
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ 802f32c:	2301      	movs	r3, #1
+ 802f32e:	623b      	str	r3, [r7, #32]
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 802f330:	2300      	movs	r3, #0
+ 802f332:	627b      	str	r3, [r7, #36]	@ 0x24
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 802f334:	2300      	movs	r3, #0
+ 802f336:	62bb      	str	r3, [r7, #40]	@ 0x28
+  HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
+ 802f338:	f107 031c 	add.w	r3, r7, #28
+ 802f33c:	4619      	mov	r1, r3
+ 802f33e:	4828      	ldr	r0, [pc, #160]	@ (802f3e0 <MX_GPIO_Init+0x234>)
+ 802f340:	f008 f94c 	bl	80375dc <HAL_GPIO_Init>
+
+  /*Configure GPIO pins : PDPin PDPin PDPin PDPin
+                           PDPin */
+  GPIO_InitStruct.Pin = RS485_1_DIR_Pin|RS485_2_DIR_Pin|E28_M0_Pin|E28_M1_Pin
+ 802f344:	f640 430b 	movw	r3, #3083	@ 0xc0b
+ 802f348:	61fb      	str	r3, [r7, #28]
+                          |E28_M2_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ 802f34a:	2301      	movs	r3, #1
+ 802f34c:	623b      	str	r3, [r7, #32]
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 802f34e:	2300      	movs	r3, #0
+ 802f350:	627b      	str	r3, [r7, #36]	@ 0x24
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 802f352:	2300      	movs	r3, #0
+ 802f354:	62bb      	str	r3, [r7, #40]	@ 0x28
+  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+ 802f356:	f107 031c 	add.w	r3, r7, #28
+ 802f35a:	4619      	mov	r1, r3
+ 802f35c:	4821      	ldr	r0, [pc, #132]	@ (802f3e4 <MX_GPIO_Init+0x238>)
+ 802f35e:	f008 f93d 	bl	80375dc <HAL_GPIO_Init>
+
+  /*Configure GPIO pins : PD14 PDPin */
+  GPIO_InitStruct.Pin = GPIO_PIN_14|E28_AUX_Pin;
+ 802f362:	f244 0310 	movw	r3, #16400	@ 0x4010
+ 802f366:	61fb      	str	r3, [r7, #28]
+  GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
+ 802f368:	f44f 1388 	mov.w	r3, #1114112	@ 0x110000
+ 802f36c:	623b      	str	r3, [r7, #32]
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 802f36e:	2300      	movs	r3, #0
+ 802f370:	627b      	str	r3, [r7, #36]	@ 0x24
+  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+ 802f372:	f107 031c 	add.w	r3, r7, #28
+ 802f376:	4619      	mov	r1, r3
+ 802f378:	481a      	ldr	r0, [pc, #104]	@ (802f3e4 <MX_GPIO_Init+0x238>)
+ 802f37a:	f008 f92f 	bl	80375dc <HAL_GPIO_Init>
+
+  /*Configure GPIO pins : PBPin PBPin */
+  GPIO_InitStruct.Pin = S0_NET_Pin|S0_LINKA_Pin;
+ 802f37e:	2318      	movs	r3, #24
+ 802f380:	61fb      	str	r3, [r7, #28]
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+ 802f382:	2300      	movs	r3, #0
+ 802f384:	623b      	str	r3, [r7, #32]
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 802f386:	2300      	movs	r3, #0
+ 802f388:	627b      	str	r3, [r7, #36]	@ 0x24
+  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+ 802f38a:	f107 031c 	add.w	r3, r7, #28
+ 802f38e:	4619      	mov	r1, r3
+ 802f390:	4815      	ldr	r0, [pc, #84]	@ (802f3e8 <MX_GPIO_Init+0x23c>)
+ 802f392:	f008 f923 	bl	80375dc <HAL_GPIO_Init>
+
+  /*Configure GPIO pin : PtPin */
+  GPIO_InitStruct.Pin = E22_M1_Pin;
+ 802f396:	2380      	movs	r3, #128	@ 0x80
+ 802f398:	61fb      	str	r3, [r7, #28]
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ 802f39a:	2301      	movs	r3, #1
+ 802f39c:	623b      	str	r3, [r7, #32]
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 802f39e:	2300      	movs	r3, #0
+ 802f3a0:	627b      	str	r3, [r7, #36]	@ 0x24
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 802f3a2:	2300      	movs	r3, #0
+ 802f3a4:	62bb      	str	r3, [r7, #40]	@ 0x28
+  HAL_GPIO_Init(E22_M1_GPIO_Port, &GPIO_InitStruct);
+ 802f3a6:	f107 031c 	add.w	r3, r7, #28
+ 802f3aa:	4619      	mov	r1, r3
+ 802f3ac:	480e      	ldr	r0, [pc, #56]	@ (802f3e8 <MX_GPIO_Init+0x23c>)
+ 802f3ae:	f008 f915 	bl	80375dc <HAL_GPIO_Init>
+
+  /*Configure GPIO pin : PtPin */
+  GPIO_InitStruct.Pin = E22_AUX_Pin;
+ 802f3b2:	2302      	movs	r3, #2
+ 802f3b4:	61fb      	str	r3, [r7, #28]
+  GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
+ 802f3b6:	f44f 1388 	mov.w	r3, #1114112	@ 0x110000
+ 802f3ba:	623b      	str	r3, [r7, #32]
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 802f3bc:	2300      	movs	r3, #0
+ 802f3be:	627b      	str	r3, [r7, #36]	@ 0x24
+  HAL_GPIO_Init(E22_AUX_GPIO_Port, &GPIO_InitStruct);
+ 802f3c0:	f107 031c 	add.w	r3, r7, #28
+ 802f3c4:	4619      	mov	r1, r3
+ 802f3c6:	4806      	ldr	r0, [pc, #24]	@ (802f3e0 <MX_GPIO_Init+0x234>)
+ 802f3c8:	f008 f908 	bl	80375dc <HAL_GPIO_Init>
+
+}
+ 802f3cc:	bf00      	nop
+ 802f3ce:	3730      	adds	r7, #48	@ 0x30
+ 802f3d0:	46bd      	mov	sp, r7
+ 802f3d2:	bd80      	pop	{r7, pc}
+ 802f3d4:	58024400 	.word	0x58024400
+ 802f3d8:	58020800 	.word	0x58020800
+ 802f3dc:	58020000 	.word	0x58020000
+ 802f3e0:	58021000 	.word	0x58021000
+ 802f3e4:	58020c00 	.word	0x58020c00
+ 802f3e8:	58020400 	.word	0x58020400
+
+0802f3ec <MX_I2C4_Init>:
+
+I2C_HandleTypeDef hi2c4;
+
+/* I2C4 init function */
+void MX_I2C4_Init(void)
+{
+ 802f3ec:	b580      	push	{r7, lr}
+ 802f3ee:	af00      	add	r7, sp, #0
+  /* USER CODE END I2C4_Init 0 */
+
+  /* USER CODE BEGIN I2C4_Init 1 */
+
+  /* USER CODE END I2C4_Init 1 */
+  hi2c4.Instance = I2C4;
+ 802f3f0:	4b1b      	ldr	r3, [pc, #108]	@ (802f460 <MX_I2C4_Init+0x74>)
+ 802f3f2:	4a1c      	ldr	r2, [pc, #112]	@ (802f464 <MX_I2C4_Init+0x78>)
+ 802f3f4:	601a      	str	r2, [r3, #0]
+  hi2c4.Init.Timing = 0x10C0ECFF;
+ 802f3f6:	4b1a      	ldr	r3, [pc, #104]	@ (802f460 <MX_I2C4_Init+0x74>)
+ 802f3f8:	4a1b      	ldr	r2, [pc, #108]	@ (802f468 <MX_I2C4_Init+0x7c>)
+ 802f3fa:	605a      	str	r2, [r3, #4]
+  hi2c4.Init.OwnAddress1 = 0;
+ 802f3fc:	4b18      	ldr	r3, [pc, #96]	@ (802f460 <MX_I2C4_Init+0x74>)
+ 802f3fe:	2200      	movs	r2, #0
+ 802f400:	609a      	str	r2, [r3, #8]
+  hi2c4.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
+ 802f402:	4b17      	ldr	r3, [pc, #92]	@ (802f460 <MX_I2C4_Init+0x74>)
+ 802f404:	2201      	movs	r2, #1
+ 802f406:	60da      	str	r2, [r3, #12]
+  hi2c4.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
+ 802f408:	4b15      	ldr	r3, [pc, #84]	@ (802f460 <MX_I2C4_Init+0x74>)
+ 802f40a:	2200      	movs	r2, #0
+ 802f40c:	611a      	str	r2, [r3, #16]
+  hi2c4.Init.OwnAddress2 = 0;
+ 802f40e:	4b14      	ldr	r3, [pc, #80]	@ (802f460 <MX_I2C4_Init+0x74>)
+ 802f410:	2200      	movs	r2, #0
+ 802f412:	615a      	str	r2, [r3, #20]
+  hi2c4.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
+ 802f414:	4b12      	ldr	r3, [pc, #72]	@ (802f460 <MX_I2C4_Init+0x74>)
+ 802f416:	2200      	movs	r2, #0
+ 802f418:	619a      	str	r2, [r3, #24]
+  hi2c4.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
+ 802f41a:	4b11      	ldr	r3, [pc, #68]	@ (802f460 <MX_I2C4_Init+0x74>)
+ 802f41c:	2200      	movs	r2, #0
+ 802f41e:	61da      	str	r2, [r3, #28]
+  hi2c4.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
+ 802f420:	4b0f      	ldr	r3, [pc, #60]	@ (802f460 <MX_I2C4_Init+0x74>)
+ 802f422:	2200      	movs	r2, #0
+ 802f424:	621a      	str	r2, [r3, #32]
+  if (HAL_I2C_Init(&hi2c4) != HAL_OK)
+ 802f426:	480e      	ldr	r0, [pc, #56]	@ (802f460 <MX_I2C4_Init+0x74>)
+ 802f428:	f008 faa2 	bl	8037970 <HAL_I2C_Init>
+ 802f42c:	4603      	mov	r3, r0
+ 802f42e:	2b00      	cmp	r3, #0
+ 802f430:	d001      	beq.n	802f436 <MX_I2C4_Init+0x4a>
+  {
+    Error_Handler();
+ 802f432:	f000 fb29 	bl	802fa88 <Error_Handler>
+  }
+
+  /** Configure Analogue filter
+  */
+  if (HAL_I2CEx_ConfigAnalogFilter(&hi2c4, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
+ 802f436:	2100      	movs	r1, #0
+ 802f438:	4809      	ldr	r0, [pc, #36]	@ (802f460 <MX_I2C4_Init+0x74>)
+ 802f43a:	f009 fa22 	bl	8038882 <HAL_I2CEx_ConfigAnalogFilter>
+ 802f43e:	4603      	mov	r3, r0
+ 802f440:	2b00      	cmp	r3, #0
+ 802f442:	d001      	beq.n	802f448 <MX_I2C4_Init+0x5c>
+  {
+    Error_Handler();
+ 802f444:	f000 fb20 	bl	802fa88 <Error_Handler>
+  }
+
+  /** Configure Digital filter
+  */
+  if (HAL_I2CEx_ConfigDigitalFilter(&hi2c4, 0) != HAL_OK)
+ 802f448:	2100      	movs	r1, #0
+ 802f44a:	4805      	ldr	r0, [pc, #20]	@ (802f460 <MX_I2C4_Init+0x74>)
+ 802f44c:	f009 fa64 	bl	8038918 <HAL_I2CEx_ConfigDigitalFilter>
+ 802f450:	4603      	mov	r3, r0
+ 802f452:	2b00      	cmp	r3, #0
+ 802f454:	d001      	beq.n	802f45a <MX_I2C4_Init+0x6e>
+  {
+    Error_Handler();
+ 802f456:	f000 fb17 	bl	802fa88 <Error_Handler>
+  }
+  /* USER CODE BEGIN I2C4_Init 2 */
+
+  /* USER CODE END I2C4_Init 2 */
+
+}
+ 802f45a:	bf00      	nop
+ 802f45c:	bd80      	pop	{r7, pc}
+ 802f45e:	bf00      	nop
+ 802f460:	2400a910 	.word	0x2400a910
+ 802f464:	58001c00 	.word	0x58001c00
+ 802f468:	10c0ecff 	.word	0x10c0ecff
+
+0802f46c <HAL_I2C_MspInit>:
+
+void HAL_I2C_MspInit(I2C_HandleTypeDef* i2cHandle)
+{
+ 802f46c:	b580      	push	{r7, lr}
+ 802f46e:	b0ba      	sub	sp, #232	@ 0xe8
+ 802f470:	af00      	add	r7, sp, #0
+ 802f472:	6078      	str	r0, [r7, #4]
+
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+ 802f474:	f107 03d4 	add.w	r3, r7, #212	@ 0xd4
+ 802f478:	2200      	movs	r2, #0
+ 802f47a:	601a      	str	r2, [r3, #0]
+ 802f47c:	605a      	str	r2, [r3, #4]
+ 802f47e:	609a      	str	r2, [r3, #8]
+ 802f480:	60da      	str	r2, [r3, #12]
+ 802f482:	611a      	str	r2, [r3, #16]
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+ 802f484:	f107 0310 	add.w	r3, r7, #16
+ 802f488:	22c0      	movs	r2, #192	@ 0xc0
+ 802f48a:	2100      	movs	r1, #0
+ 802f48c:	4618      	mov	r0, r3
+ 802f48e:	f010 ff2b 	bl	80402e8 <memset>
+  if(i2cHandle->Instance==I2C4)
+ 802f492:	687b      	ldr	r3, [r7, #4]
+ 802f494:	681b      	ldr	r3, [r3, #0]
+ 802f496:	4a2f      	ldr	r2, [pc, #188]	@ (802f554 <HAL_I2C_MspInit+0xe8>)
+ 802f498:	4293      	cmp	r3, r2
+ 802f49a:	d156      	bne.n	802f54a <HAL_I2C_MspInit+0xde>
+
+  /* USER CODE END I2C4_MspInit 0 */
+
+  /** Initializes the peripherals clock
+  */
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_I2C4;
+ 802f49c:	f04f 0210 	mov.w	r2, #16
+ 802f4a0:	f04f 0300 	mov.w	r3, #0
+ 802f4a4:	e9c7 2304 	strd	r2, r3, [r7, #16]
+    PeriphClkInitStruct.I2c4ClockSelection = RCC_I2C4CLKSOURCE_D3PCLK1;
+ 802f4a8:	2300      	movs	r3, #0
+ 802f4aa:	f8c7 30a8 	str.w	r3, [r7, #168]	@ 0xa8
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+ 802f4ae:	f107 0310 	add.w	r3, r7, #16
+ 802f4b2:	4618      	mov	r0, r3
+ 802f4b4:	f00a fde6 	bl	803a084 <HAL_RCCEx_PeriphCLKConfig>
+ 802f4b8:	4603      	mov	r3, r0
+ 802f4ba:	2b00      	cmp	r3, #0
+ 802f4bc:	d001      	beq.n	802f4c2 <HAL_I2C_MspInit+0x56>
+    {
+      Error_Handler();
+ 802f4be:	f000 fae3 	bl	802fa88 <Error_Handler>
+    }
+
+    __HAL_RCC_GPIOD_CLK_ENABLE();
+ 802f4c2:	4b25      	ldr	r3, [pc, #148]	@ (802f558 <HAL_I2C_MspInit+0xec>)
+ 802f4c4:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
+ 802f4c8:	4a23      	ldr	r2, [pc, #140]	@ (802f558 <HAL_I2C_MspInit+0xec>)
+ 802f4ca:	f043 0308 	orr.w	r3, r3, #8
+ 802f4ce:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
+ 802f4d2:	4b21      	ldr	r3, [pc, #132]	@ (802f558 <HAL_I2C_MspInit+0xec>)
+ 802f4d4:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
+ 802f4d8:	f003 0308 	and.w	r3, r3, #8
+ 802f4dc:	60fb      	str	r3, [r7, #12]
+ 802f4de:	68fb      	ldr	r3, [r7, #12]
+    /**I2C4 GPIO Configuration
+    PD12     ------> I2C4_SCL
+    PD13     ------> I2C4_SDA
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_13;
+ 802f4e0:	f44f 5340 	mov.w	r3, #12288	@ 0x3000
+ 802f4e4:	f8c7 30d4 	str.w	r3, [r7, #212]	@ 0xd4
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
+ 802f4e8:	2312      	movs	r3, #18
+ 802f4ea:	f8c7 30d8 	str.w	r3, [r7, #216]	@ 0xd8
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 802f4ee:	2300      	movs	r3, #0
+ 802f4f0:	f8c7 30dc 	str.w	r3, [r7, #220]	@ 0xdc
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 802f4f4:	2300      	movs	r3, #0
+ 802f4f6:	f8c7 30e0 	str.w	r3, [r7, #224]	@ 0xe0
+    GPIO_InitStruct.Alternate = GPIO_AF4_I2C4;
+ 802f4fa:	2304      	movs	r3, #4
+ 802f4fc:	f8c7 30e4 	str.w	r3, [r7, #228]	@ 0xe4
+    HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+ 802f500:	f107 03d4 	add.w	r3, r7, #212	@ 0xd4
+ 802f504:	4619      	mov	r1, r3
+ 802f506:	4815      	ldr	r0, [pc, #84]	@ (802f55c <HAL_I2C_MspInit+0xf0>)
+ 802f508:	f008 f868 	bl	80375dc <HAL_GPIO_Init>
+
+    /* I2C4 clock enable */
+    __HAL_RCC_I2C4_CLK_ENABLE();
+ 802f50c:	4b12      	ldr	r3, [pc, #72]	@ (802f558 <HAL_I2C_MspInit+0xec>)
+ 802f50e:	f8d3 30f4 	ldr.w	r3, [r3, #244]	@ 0xf4
+ 802f512:	4a11      	ldr	r2, [pc, #68]	@ (802f558 <HAL_I2C_MspInit+0xec>)
+ 802f514:	f043 0380 	orr.w	r3, r3, #128	@ 0x80
+ 802f518:	f8c2 30f4 	str.w	r3, [r2, #244]	@ 0xf4
+ 802f51c:	4b0e      	ldr	r3, [pc, #56]	@ (802f558 <HAL_I2C_MspInit+0xec>)
+ 802f51e:	f8d3 30f4 	ldr.w	r3, [r3, #244]	@ 0xf4
+ 802f522:	f003 0380 	and.w	r3, r3, #128	@ 0x80
+ 802f526:	60bb      	str	r3, [r7, #8]
+ 802f528:	68bb      	ldr	r3, [r7, #8]
+
+    /* I2C4 interrupt Init */
+    HAL_NVIC_SetPriority(I2C4_EV_IRQn, 15, 0);
+ 802f52a:	2200      	movs	r2, #0
+ 802f52c:	210f      	movs	r1, #15
+ 802f52e:	205f      	movs	r0, #95	@ 0x5f
+ 802f530:	f003 fabf 	bl	8032ab2 <HAL_NVIC_SetPriority>
+    HAL_NVIC_EnableIRQ(I2C4_EV_IRQn);
+ 802f534:	205f      	movs	r0, #95	@ 0x5f
+ 802f536:	f003 fad6 	bl	8032ae6 <HAL_NVIC_EnableIRQ>
+    HAL_NVIC_SetPriority(I2C4_ER_IRQn, 15, 0);
+ 802f53a:	2200      	movs	r2, #0
+ 802f53c:	210f      	movs	r1, #15
+ 802f53e:	2060      	movs	r0, #96	@ 0x60
+ 802f540:	f003 fab7 	bl	8032ab2 <HAL_NVIC_SetPriority>
+    HAL_NVIC_EnableIRQ(I2C4_ER_IRQn);
+ 802f544:	2060      	movs	r0, #96	@ 0x60
+ 802f546:	f003 face 	bl	8032ae6 <HAL_NVIC_EnableIRQ>
+  /* USER CODE BEGIN I2C4_MspInit 1 */
+
+  /* USER CODE END I2C4_MspInit 1 */
+  }
+}
+ 802f54a:	bf00      	nop
+ 802f54c:	37e8      	adds	r7, #232	@ 0xe8
+ 802f54e:	46bd      	mov	sp, r7
+ 802f550:	bd80      	pop	{r7, pc}
+ 802f552:	bf00      	nop
+ 802f554:	58001c00 	.word	0x58001c00
+ 802f558:	58024400 	.word	0x58024400
+ 802f55c:	58020c00 	.word	0x58020c00
+
+0802f560 <main>:
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+ 802f560:	b580      	push	{r7, lr}
+ 802f562:	b084      	sub	sp, #16
+ 802f564:	af00      	add	r7, sp, #0
+	// tdl720 115200
+  /* USER CODE END 1 */
+
+  /* MPU Configuration--------------------------------------------------------*/
+
+  	MPU_Config();
+ 802f566:	f000 fa41 	bl	802f9ec <MPU_Config>
+    if (SCB->CCR & SCB_CCR_IC_Msk) return;  /* return if ICache is already enabled */
+ 802f56a:	4b54      	ldr	r3, [pc, #336]	@ (802f6bc <main+0x15c>)
+ 802f56c:	695b      	ldr	r3, [r3, #20]
+ 802f56e:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
+ 802f572:	2b00      	cmp	r3, #0
+ 802f574:	d11b      	bne.n	802f5ae <main+0x4e>
+  __ASM volatile ("dsb 0xF":::"memory");
+ 802f576:	f3bf 8f4f 	dsb	sy
+}
+ 802f57a:	bf00      	nop
+  __ASM volatile ("isb 0xF":::"memory");
+ 802f57c:	f3bf 8f6f 	isb	sy
+}
+ 802f580:	bf00      	nop
+    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
+ 802f582:	4b4e      	ldr	r3, [pc, #312]	@ (802f6bc <main+0x15c>)
+ 802f584:	2200      	movs	r2, #0
+ 802f586:	f8c3 2250 	str.w	r2, [r3, #592]	@ 0x250
+  __ASM volatile ("dsb 0xF":::"memory");
+ 802f58a:	f3bf 8f4f 	dsb	sy
+}
+ 802f58e:	bf00      	nop
+  __ASM volatile ("isb 0xF":::"memory");
+ 802f590:	f3bf 8f6f 	isb	sy
+}
+ 802f594:	bf00      	nop
+    SCB->CCR |=  (uint32_t)SCB_CCR_IC_Msk;  /* enable I-Cache */
+ 802f596:	4b49      	ldr	r3, [pc, #292]	@ (802f6bc <main+0x15c>)
+ 802f598:	695b      	ldr	r3, [r3, #20]
+ 802f59a:	4a48      	ldr	r2, [pc, #288]	@ (802f6bc <main+0x15c>)
+ 802f59c:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
+ 802f5a0:	6153      	str	r3, [r2, #20]
+  __ASM volatile ("dsb 0xF":::"memory");
+ 802f5a2:	f3bf 8f4f 	dsb	sy
+}
+ 802f5a6:	bf00      	nop
+  __ASM volatile ("isb 0xF":::"memory");
+ 802f5a8:	f3bf 8f6f 	isb	sy
+}
+ 802f5ac:	e000      	b.n	802f5b0 <main+0x50>
+    if (SCB->CCR & SCB_CCR_IC_Msk) return;  /* return if ICache is already enabled */
+ 802f5ae:	bf00      	nop
+    if (SCB->CCR & SCB_CCR_DC_Msk) return;  /* return if DCache is already enabled */
+ 802f5b0:	4b42      	ldr	r3, [pc, #264]	@ (802f6bc <main+0x15c>)
+ 802f5b2:	695b      	ldr	r3, [r3, #20]
+ 802f5b4:	f403 3380 	and.w	r3, r3, #65536	@ 0x10000
+ 802f5b8:	2b00      	cmp	r3, #0
+ 802f5ba:	d138      	bne.n	802f62e <main+0xce>
+    SCB->CSSELR = 0U;                       /* select Level 1 data cache */
+ 802f5bc:	4b3f      	ldr	r3, [pc, #252]	@ (802f6bc <main+0x15c>)
+ 802f5be:	2200      	movs	r2, #0
+ 802f5c0:	f8c3 2084 	str.w	r2, [r3, #132]	@ 0x84
+  __ASM volatile ("dsb 0xF":::"memory");
+ 802f5c4:	f3bf 8f4f 	dsb	sy
+}
+ 802f5c8:	bf00      	nop
+    ccsidr = SCB->CCSIDR;
+ 802f5ca:	4b3c      	ldr	r3, [pc, #240]	@ (802f6bc <main+0x15c>)
+ 802f5cc:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
+ 802f5d0:	60fb      	str	r3, [r7, #12]
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ 802f5d2:	68fb      	ldr	r3, [r7, #12]
+ 802f5d4:	0b5b      	lsrs	r3, r3, #13
+ 802f5d6:	f3c3 030e 	ubfx	r3, r3, #0, #15
+ 802f5da:	60bb      	str	r3, [r7, #8]
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ 802f5dc:	68fb      	ldr	r3, [r7, #12]
+ 802f5de:	08db      	lsrs	r3, r3, #3
+ 802f5e0:	f3c3 0309 	ubfx	r3, r3, #0, #10
+ 802f5e4:	607b      	str	r3, [r7, #4]
+        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+ 802f5e6:	68bb      	ldr	r3, [r7, #8]
+ 802f5e8:	015a      	lsls	r2, r3, #5
+ 802f5ea:	f643 73e0 	movw	r3, #16352	@ 0x3fe0
+ 802f5ee:	4013      	ands	r3, r2
+                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
+ 802f5f0:	687a      	ldr	r2, [r7, #4]
+ 802f5f2:	0792      	lsls	r2, r2, #30
+        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+ 802f5f4:	4931      	ldr	r1, [pc, #196]	@ (802f6bc <main+0x15c>)
+ 802f5f6:	4313      	orrs	r3, r2
+ 802f5f8:	f8c1 3260 	str.w	r3, [r1, #608]	@ 0x260
+      } while (ways-- != 0U);
+ 802f5fc:	687b      	ldr	r3, [r7, #4]
+ 802f5fe:	1e5a      	subs	r2, r3, #1
+ 802f600:	607a      	str	r2, [r7, #4]
+ 802f602:	2b00      	cmp	r3, #0
+ 802f604:	d1ef      	bne.n	802f5e6 <main+0x86>
+    } while(sets-- != 0U);
+ 802f606:	68bb      	ldr	r3, [r7, #8]
+ 802f608:	1e5a      	subs	r2, r3, #1
+ 802f60a:	60ba      	str	r2, [r7, #8]
+ 802f60c:	2b00      	cmp	r3, #0
+ 802f60e:	d1e5      	bne.n	802f5dc <main+0x7c>
+  __ASM volatile ("dsb 0xF":::"memory");
+ 802f610:	f3bf 8f4f 	dsb	sy
+}
+ 802f614:	bf00      	nop
+    SCB->CCR |=  (uint32_t)SCB_CCR_DC_Msk;  /* enable D-Cache */
+ 802f616:	4b29      	ldr	r3, [pc, #164]	@ (802f6bc <main+0x15c>)
+ 802f618:	695b      	ldr	r3, [r3, #20]
+ 802f61a:	4a28      	ldr	r2, [pc, #160]	@ (802f6bc <main+0x15c>)
+ 802f61c:	f443 3380 	orr.w	r3, r3, #65536	@ 0x10000
+ 802f620:	6153      	str	r3, [r2, #20]
+  __ASM volatile ("dsb 0xF":::"memory");
+ 802f622:	f3bf 8f4f 	dsb	sy
+}
+ 802f626:	bf00      	nop
+  __ASM volatile ("isb 0xF":::"memory");
+ 802f628:	f3bf 8f6f 	isb	sy
+}
+ 802f62c:	e000      	b.n	802f630 <main+0xd0>
+    if (SCB->CCR & SCB_CCR_DC_Msk) return;  /* return if DCache is already enabled */
+ 802f62e:	bf00      	nop
+  SCB_EnableDCache();
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+ 802f630:	f002 f8f8 	bl	8031824 <HAL_Init>
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+ 802f634:	f000 f844 	bl	802f6c0 <SystemClock_Config>
+  /* USER CODE BEGIN SysInit */
+	//__HAL_RCC_D2SRAM3_CLK_ENABLE();
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+ 802f638:	f7ff fdb8 	bl	802f1ac <MX_GPIO_Init>
+  MX_DMA_Init();
+ 802f63c:	f7f9 fc3c 	bl	8028eb8 <MX_DMA_Init>
+  MX_FDCAN1_Init();
+ 802f640:	f7f9 fd92 	bl	8029168 <MX_FDCAN1_Init>
+  MX_FDCAN2_Init();
+ 802f644:	f7f9 fdf4 	bl	8029230 <MX_FDCAN2_Init>
+  MX_I2C4_Init();
+ 802f648:	f7ff fed0 	bl	802f3ec <MX_I2C4_Init>
+  MX_TIM1_Init();
+ 802f64c:	f000 ff9c 	bl	8030588 <MX_TIM1_Init>
+  MX_UART4_Init();
+ 802f650:	f001 f8de 	bl	8030810 <MX_UART4_Init>
+  MX_UART5_Init();
+ 802f654:	f001 f928 	bl	80308a8 <MX_UART5_Init>
+  MX_UART7_Init();
+ 802f658:	f001 f97e 	bl	8030958 <MX_UART7_Init>
+  MX_USART1_UART_Init();
+ 802f65c:	f001 f9d0 	bl	8030a00 <MX_USART1_UART_Init>
+  MX_USART3_UART_Init();
+ 802f660:	f001 fa76 	bl	8030b50 <MX_USART3_UART_Init>
+  MX_USART2_UART_Init();
+ 802f664:	f001 fa20 	bl	8030aa8 <MX_USART2_UART_Init>
+  MX_USART6_UART_Init();
+ 802f668:	f001 fac8 	bl	8030bfc <MX_USART6_UART_Init>
+  MX_TIM8_Init();
+ 802f66c:	f000 ffe0 	bl	8030630 <MX_TIM8_Init>
+  MX_QUADSPI_Init();
+ 802f670:	f000 fc60 	bl	802ff34 <MX_QUADSPI_Init>
+  MX_LPUART1_UART_Init();
+ 802f674:	f001 f878 	bl	8030768 <MX_LPUART1_UART_Init>
+  MX_ADC2_Init();
+ 802f678:	f7f9 fb44 	bl	8028d04 <MX_ADC2_Init>
+  MX_ETH_Init();
+ 802f67c:	f7f9 fc6c 	bl	8028f58 <MX_ETH_Init>
+  /* USER CODE BEGIN 2 */
+    HAL_Delay(5000);
+ 802f680:	f241 3088 	movw	r0, #5000	@ 0x1388
+ 802f684:	f002 f960 	bl	8031948 <HAL_Delay>
+
+	SystemTimer_Intialize();
+ 802f688:	f7f1 f846 	bl	8020718 <SystemTimer_Intialize>
+	GF_BSP_GPIO_SetIO(Lifting_IO_CTL_0, 1);
+ 802f68c:	2101      	movs	r1, #1
+ 802f68e:	2002      	movs	r0, #2
+ 802f690:	f7f1 fdc0 	bl	8021214 <GF_BSP_GPIO_SetIO>
+	GF_BSP_GPIO_SetIO(Lifting_IO_CTL_1, 1);
+ 802f694:	2101      	movs	r1, #1
+ 802f696:	2003      	movs	r0, #3
+ 802f698:	f7f1 fdbc 	bl	8021214 <GF_BSP_GPIO_SetIO>
+	HAL_Delay(1000);
+ 802f69c:	f44f 707a 	mov.w	r0, #1000	@ 0x3e8
+ 802f6a0:	f002 f952 	bl	8031948 <HAL_Delay>
+	Error_Detect_Intialzie(1000);	//every 1 seconds
+ 802f6a4:	f44f 707a 	mov.w	r0, #1000	@ 0x3e8
+ 802f6a8:	f7f1 fae0 	bl	8020c6c <Error_Detect_Intialzie>
+
+	Move_PushRod_Halt_Func_Do_1();
+ 802f6ac:	f000 fd50 	bl	8030150 <Move_PushRod_Halt_Func_Do_1>
+	Move_PushRod_Halt_Func_Do();
+ 802f6b0:	f000 fd2a 	bl	8030108 <Move_PushRod_Halt_Func_Do>
+	GF_Robot_Init();
+ 802f6b4:	f000 f918 	bl	802f8e8 <GF_Robot_Init>
+	//tcp_client_connect();
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+	while (1)
+ 802f6b8:	bf00      	nop
+ 802f6ba:	e7fd      	b.n	802f6b8 <main+0x158>
+ 802f6bc:	e000ed00 	.word	0xe000ed00
+
+0802f6c0 <SystemClock_Config>:
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+ 802f6c0:	b580      	push	{r7, lr}
+ 802f6c2:	b09c      	sub	sp, #112	@ 0x70
+ 802f6c4:	af00      	add	r7, sp, #0
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+ 802f6c6:	f107 0324 	add.w	r3, r7, #36	@ 0x24
+ 802f6ca:	224c      	movs	r2, #76	@ 0x4c
+ 802f6cc:	2100      	movs	r1, #0
+ 802f6ce:	4618      	mov	r0, r3
+ 802f6d0:	f010 fe0a 	bl	80402e8 <memset>
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+ 802f6d4:	1d3b      	adds	r3, r7, #4
+ 802f6d6:	2220      	movs	r2, #32
+ 802f6d8:	2100      	movs	r1, #0
+ 802f6da:	4618      	mov	r0, r3
+ 802f6dc:	f010 fe04 	bl	80402e8 <memset>
+
+  /** Supply configuration update enable
+  */
+  HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
+ 802f6e0:	2002      	movs	r0, #2
+ 802f6e2:	f009 f98d 	bl	8038a00 <HAL_PWREx_ConfigSupply>
+
+  /** Configure the main internal regulator output voltage
+  */
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+ 802f6e6:	2300      	movs	r3, #0
+ 802f6e8:	603b      	str	r3, [r7, #0]
+ 802f6ea:	4b31      	ldr	r3, [pc, #196]	@ (802f7b0 <SystemClock_Config+0xf0>)
+ 802f6ec:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 802f6ee:	4a30      	ldr	r2, [pc, #192]	@ (802f7b0 <SystemClock_Config+0xf0>)
+ 802f6f0:	f023 0301 	bic.w	r3, r3, #1
+ 802f6f4:	62d3      	str	r3, [r2, #44]	@ 0x2c
+ 802f6f6:	4b2e      	ldr	r3, [pc, #184]	@ (802f7b0 <SystemClock_Config+0xf0>)
+ 802f6f8:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 802f6fa:	f003 0301 	and.w	r3, r3, #1
+ 802f6fe:	603b      	str	r3, [r7, #0]
+ 802f700:	4b2c      	ldr	r3, [pc, #176]	@ (802f7b4 <SystemClock_Config+0xf4>)
+ 802f702:	699b      	ldr	r3, [r3, #24]
+ 802f704:	4a2b      	ldr	r2, [pc, #172]	@ (802f7b4 <SystemClock_Config+0xf4>)
+ 802f706:	f443 4340 	orr.w	r3, r3, #49152	@ 0xc000
+ 802f70a:	6193      	str	r3, [r2, #24]
+ 802f70c:	4b29      	ldr	r3, [pc, #164]	@ (802f7b4 <SystemClock_Config+0xf4>)
+ 802f70e:	699b      	ldr	r3, [r3, #24]
+ 802f710:	f403 4340 	and.w	r3, r3, #49152	@ 0xc000
+ 802f714:	603b      	str	r3, [r7, #0]
+ 802f716:	683b      	ldr	r3, [r7, #0]
+
+  while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
+ 802f718:	bf00      	nop
+ 802f71a:	4b26      	ldr	r3, [pc, #152]	@ (802f7b4 <SystemClock_Config+0xf4>)
+ 802f71c:	699b      	ldr	r3, [r3, #24]
+ 802f71e:	f403 5300 	and.w	r3, r3, #8192	@ 0x2000
+ 802f722:	f5b3 5f00 	cmp.w	r3, #8192	@ 0x2000
+ 802f726:	d1f8      	bne.n	802f71a <SystemClock_Config+0x5a>
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ 802f728:	2301      	movs	r3, #1
+ 802f72a:	627b      	str	r3, [r7, #36]	@ 0x24
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+ 802f72c:	f44f 3380 	mov.w	r3, #65536	@ 0x10000
+ 802f730:	62bb      	str	r3, [r7, #40]	@ 0x28
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ 802f732:	2302      	movs	r3, #2
+ 802f734:	64bb      	str	r3, [r7, #72]	@ 0x48
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ 802f736:	2302      	movs	r3, #2
+ 802f738:	64fb      	str	r3, [r7, #76]	@ 0x4c
+  RCC_OscInitStruct.PLL.PLLM = 2;
+ 802f73a:	2302      	movs	r3, #2
+ 802f73c:	653b      	str	r3, [r7, #80]	@ 0x50
+  RCC_OscInitStruct.PLL.PLLN = 64;
+ 802f73e:	2340      	movs	r3, #64	@ 0x40
+ 802f740:	657b      	str	r3, [r7, #84]	@ 0x54
+  RCC_OscInitStruct.PLL.PLLP = 2;
+ 802f742:	2302      	movs	r3, #2
+ 802f744:	65bb      	str	r3, [r7, #88]	@ 0x58
+  RCC_OscInitStruct.PLL.PLLQ = 20;
+ 802f746:	2314      	movs	r3, #20
+ 802f748:	65fb      	str	r3, [r7, #92]	@ 0x5c
+  RCC_OscInitStruct.PLL.PLLR = 4;
+ 802f74a:	2304      	movs	r3, #4
+ 802f74c:	663b      	str	r3, [r7, #96]	@ 0x60
+  RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_3;
+ 802f74e:	230c      	movs	r3, #12
+ 802f750:	667b      	str	r3, [r7, #100]	@ 0x64
+  RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
+ 802f752:	2300      	movs	r3, #0
+ 802f754:	66bb      	str	r3, [r7, #104]	@ 0x68
+  RCC_OscInitStruct.PLL.PLLFRACN = 0;
+ 802f756:	2300      	movs	r3, #0
+ 802f758:	66fb      	str	r3, [r7, #108]	@ 0x6c
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+ 802f75a:	f107 0324 	add.w	r3, r7, #36	@ 0x24
+ 802f75e:	4618      	mov	r0, r3
+ 802f760:	f009 fc7e 	bl	8039060 <HAL_RCC_OscConfig>
+ 802f764:	4603      	mov	r3, r0
+ 802f766:	2b00      	cmp	r3, #0
+ 802f768:	d001      	beq.n	802f76e <SystemClock_Config+0xae>
+  {
+    Error_Handler();
+ 802f76a:	f000 f98d 	bl	802fa88 <Error_Handler>
+  }
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+ 802f76e:	233f      	movs	r3, #63	@ 0x3f
+ 802f770:	607b      	str	r3, [r7, #4]
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
+                              |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ 802f772:	2303      	movs	r3, #3
+ 802f774:	60bb      	str	r3, [r7, #8]
+  RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
+ 802f776:	2300      	movs	r3, #0
+ 802f778:	60fb      	str	r3, [r7, #12]
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
+ 802f77a:	2308      	movs	r3, #8
+ 802f77c:	613b      	str	r3, [r7, #16]
+  RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
+ 802f77e:	2340      	movs	r3, #64	@ 0x40
+ 802f780:	617b      	str	r3, [r7, #20]
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
+ 802f782:	2340      	movs	r3, #64	@ 0x40
+ 802f784:	61bb      	str	r3, [r7, #24]
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
+ 802f786:	f44f 6380 	mov.w	r3, #1024	@ 0x400
+ 802f78a:	61fb      	str	r3, [r7, #28]
+  RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
+ 802f78c:	2340      	movs	r3, #64	@ 0x40
+ 802f78e:	623b      	str	r3, [r7, #32]
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
+ 802f790:	1d3b      	adds	r3, r7, #4
+ 802f792:	2102      	movs	r1, #2
+ 802f794:	4618      	mov	r0, r3
+ 802f796:	f00a f8bd 	bl	8039914 <HAL_RCC_ClockConfig>
+ 802f79a:	4603      	mov	r3, r0
+ 802f79c:	2b00      	cmp	r3, #0
+ 802f79e:	d001      	beq.n	802f7a4 <SystemClock_Config+0xe4>
+  {
+    Error_Handler();
+ 802f7a0:	f000 f972 	bl	802fa88 <Error_Handler>
+  }
+
+  /** Enables the Clock Security System
+  */
+  HAL_RCC_EnableCSS();
+ 802f7a4:	f00a fa6c 	bl	8039c80 <HAL_RCC_EnableCSS>
+}
+ 802f7a8:	bf00      	nop
+ 802f7aa:	3770      	adds	r7, #112	@ 0x70
+ 802f7ac:	46bd      	mov	sp, r7
+ 802f7ae:	bd80      	pop	{r7, pc}
+ 802f7b0:	58000400 	.word	0x58000400
+ 802f7b4:	58024800 	.word	0x58024800
+
+0802f7b8 <CV_GV_Init>:
+
+/* USER CODE BEGIN 4 */
+
+void CV_GV_Init()
+{
+ 802f7b8:	b590      	push	{r4, r7, lr}
+ 802f7ba:	b0a9      	sub	sp, #164	@ 0xa4
+ 802f7bc:	af00      	add	r7, sp, #0
+
+	CV = GF_BSP_EEPROM_Get_CV(); //Read CV
+ 802f7be:	4c30      	ldr	r4, [pc, #192]	@ (802f880 <CV_GV_Init+0xc8>)
+ 802f7c0:	463b      	mov	r3, r7
+ 802f7c2:	4618      	mov	r0, r3
+ 802f7c4:	f7f1 fa34 	bl	8020c30 <GF_BSP_EEPROM_Get_CV>
+ 802f7c8:	4620      	mov	r0, r4
+ 802f7ca:	463b      	mov	r3, r7
+ 802f7cc:	229c      	movs	r2, #156	@ 0x9c
+ 802f7ce:	4619      	mov	r1, r3
+ 802f7d0:	f010 fdf4 	bl	80403bc <memcpy>
+
+
+	//洗舱项目
+	//motor regions
+	TT_Motor[1] = &GV.LeftMotor;
+ 802f7d4:	4b2b      	ldr	r3, [pc, #172]	@ (802f884 <CV_GV_Init+0xcc>)
+ 802f7d6:	4a2c      	ldr	r2, [pc, #176]	@ (802f888 <CV_GV_Init+0xd0>)
+ 802f7d8:	605a      	str	r2, [r3, #4]
+	TT_Motor[2] = &GV.RightMotor;
+ 802f7da:	4b2a      	ldr	r3, [pc, #168]	@ (802f884 <CV_GV_Init+0xcc>)
+ 802f7dc:	4a2b      	ldr	r2, [pc, #172]	@ (802f88c <CV_GV_Init+0xd4>)
+ 802f7de:	609a      	str	r2, [r3, #8]
+	TT_Motor[3] = &GV.SwingMotor;
+ 802f7e0:	4b28      	ldr	r3, [pc, #160]	@ (802f884 <CV_GV_Init+0xcc>)
+ 802f7e2:	4a2b      	ldr	r2, [pc, #172]	@ (802f890 <CV_GV_Init+0xd8>)
+ 802f7e4:	60da      	str	r2, [r3, #12]
+
+	TT_Motor[1]->MotorID = 1;
+ 802f7e6:	4b27      	ldr	r3, [pc, #156]	@ (802f884 <CV_GV_Init+0xcc>)
+ 802f7e8:	685b      	ldr	r3, [r3, #4]
+ 802f7ea:	2201      	movs	r2, #1
+ 802f7ec:	601a      	str	r2, [r3, #0]
+	TT_Motor[2]->MotorID = 2;
+ 802f7ee:	4b25      	ldr	r3, [pc, #148]	@ (802f884 <CV_GV_Init+0xcc>)
+ 802f7f0:	689b      	ldr	r3, [r3, #8]
+ 802f7f2:	2202      	movs	r2, #2
+ 802f7f4:	601a      	str	r2, [r3, #0]
+	TT_Motor[3]->MotorID = 3;
+ 802f7f6:	4b23      	ldr	r3, [pc, #140]	@ (802f884 <CV_GV_Init+0xcc>)
+ 802f7f8:	68db      	ldr	r3, [r3, #12]
+ 802f7fa:	2203      	movs	r2, #3
+ 802f7fc:	601a      	str	r2, [r3, #0]
+
+	//Error Config
+	SystemErrorCode = &GV.SystemErrorData.ErrorCode;
+ 802f7fe:	4b25      	ldr	r3, [pc, #148]	@ (802f894 <CV_GV_Init+0xdc>)
+ 802f800:	4a25      	ldr	r2, [pc, #148]	@ (802f898 <CV_GV_Init+0xe0>)
+ 802f802:	601a      	str	r2, [r3, #0]
+
+
+	CMCU = &GV.Force_Value_mN;
+ 802f804:	4b25      	ldr	r3, [pc, #148]	@ (802f89c <CV_GV_Init+0xe4>)
+ 802f806:	4a26      	ldr	r2, [pc, #152]	@ (802f8a0 <CV_GV_Init+0xe8>)
+ 802f808:	601a      	str	r2, [r3, #0]
+
+	SP_MSP_RF_TL720D_Parameters_In = &GV.TL720DParameters;
+ 802f80a:	4b26      	ldr	r3, [pc, #152]	@ (802f8a4 <CV_GV_Init+0xec>)
+ 802f80c:	4a26      	ldr	r2, [pc, #152]	@ (802f8a8 <CV_GV_Init+0xf0>)
+ 802f80e:	601a      	str	r2, [r3, #0]
+
+	P_MK32 = &GV.P_MK32;
+ 802f810:	4b26      	ldr	r3, [pc, #152]	@ (802f8ac <CV_GV_Init+0xf4>)
+ 802f812:	4a27      	ldr	r2, [pc, #156]	@ (802f8b0 <CV_GV_Init+0xf8>)
+ 802f814:	601a      	str	r2, [r3, #0]
+	KS206  = &GV.Robot_To_Wall_mm;
+ 802f816:	4b27      	ldr	r3, [pc, #156]	@ (802f8b4 <CV_GV_Init+0xfc>)
+ 802f818:	4a27      	ldr	r2, [pc, #156]	@ (802f8b8 <CV_GV_Init+0x100>)
+ 802f81a:	601a      	str	r2, [r3, #0]
+	//遥控器返回数
+	Robot_LeftCompensation = &GV.Left_Compensation;
+ 802f81c:	4b27      	ldr	r3, [pc, #156]	@ (802f8bc <CV_GV_Init+0x104>)
+ 802f81e:	4a28      	ldr	r2, [pc, #160]	@ (802f8c0 <CV_GV_Init+0x108>)
+ 802f820:	601a      	str	r2, [r3, #0]
+	Robot_RightCompensation = &GV.Right_Compensation;
+ 802f822:	4b28      	ldr	r3, [pc, #160]	@ (802f8c4 <CV_GV_Init+0x10c>)
+ 802f824:	4a28      	ldr	r2, [pc, #160]	@ (802f8c8 <CV_GV_Init+0x110>)
+ 802f826:	601a      	str	r2, [r3, #0]
+	Robot_Angle = &GV.TL720DParameters.RF_Angle_Roll;
+ 802f828:	4b28      	ldr	r3, [pc, #160]	@ (802f8cc <CV_GV_Init+0x114>)
+ 802f82a:	4a1f      	ldr	r2, [pc, #124]	@ (802f8a8 <CV_GV_Init+0xf0>)
+ 802f82c:	601a      	str	r2, [r3, #0]
+	Robot_Deri_Speed = &GV.Robot_Move_Speed;
+ 802f82e:	4b28      	ldr	r3, [pc, #160]	@ (802f8d0 <CV_GV_Init+0x118>)
+ 802f830:	4a28      	ldr	r2, [pc, #160]	@ (802f8d4 <CV_GV_Init+0x11c>)
+ 802f832:	601a      	str	r2, [r3, #0]
+	Robot_Angle_Start_BASE = &CV.Robot_Angle_Start_BASE;
+ 802f834:	4b28      	ldr	r3, [pc, #160]	@ (802f8d8 <CV_GV_Init+0x120>)
+ 802f836:	4a29      	ldr	r2, [pc, #164]	@ (802f8dc <CV_GV_Init+0x124>)
+ 802f838:	601a      	str	r2, [r3, #0]
+	RobotAngle = &GV.Robot_Angle;
+ 802f83a:	4b29      	ldr	r3, [pc, #164]	@ (802f8e0 <CV_GV_Init+0x128>)
+ 802f83c:	4a29      	ldr	r2, [pc, #164]	@ (802f8e4 <CV_GV_Init+0x12c>)
+ 802f83e:	601a      	str	r2, [r3, #0]
+	//DMKE Motors
+	GV.has_TL720DParameters = true;
+ 802f840:	4b1f      	ldr	r3, [pc, #124]	@ (802f8c0 <CV_GV_Init+0x108>)
+ 802f842:	2201      	movs	r2, #1
+ 802f844:	f883 2214 	strb.w	r2, [r3, #532]	@ 0x214
+	GV.has_RightMotor = true;
+ 802f848:	4b1d      	ldr	r3, [pc, #116]	@ (802f8c0 <CV_GV_Init+0x108>)
+ 802f84a:	2201      	movs	r2, #1
+ 802f84c:	f883 20e0 	strb.w	r2, [r3, #224]	@ 0xe0
+	GV.has_P_MK32 = true;
+ 802f850:	4b1b      	ldr	r3, [pc, #108]	@ (802f8c0 <CV_GV_Init+0x108>)
+ 802f852:	2201      	movs	r2, #1
+ 802f854:	751a      	strb	r2, [r3, #20]
+	GV.has_LeftMotor = true;
+ 802f856:	4b1a      	ldr	r3, [pc, #104]	@ (802f8c0 <CV_GV_Init+0x108>)
+ 802f858:	2201      	movs	r2, #1
+ 802f85a:	f883 2060 	strb.w	r2, [r3, #96]	@ 0x60
+	GV.has_SwingMotor = true;
+ 802f85e:	4b18      	ldr	r3, [pc, #96]	@ (802f8c0 <CV_GV_Init+0x108>)
+ 802f860:	2201      	movs	r2, #1
+ 802f862:	f883 2160 	strb.w	r2, [r3, #352]	@ 0x160
+	GV.has_IO = true;
+ 802f866:	4b16      	ldr	r3, [pc, #88]	@ (802f8c0 <CV_GV_Init+0x108>)
+ 802f868:	2201      	movs	r2, #1
+ 802f86a:	f883 21e0 	strb.w	r2, [r3, #480]	@ 0x1e0
+
+	GV.has_SystemErrorData = true;
+ 802f86e:	4b14      	ldr	r3, [pc, #80]	@ (802f8c0 <CV_GV_Init+0x108>)
+ 802f870:	2201      	movs	r2, #1
+ 802f872:	f883 223c 	strb.w	r2, [r3, #572]	@ 0x23c
+
+}
+ 802f876:	bf00      	nop
+ 802f878:	37a4      	adds	r7, #164	@ 0xa4
+ 802f87a:	46bd      	mov	sp, r7
+ 802f87c:	bd90      	pop	{r4, r7, pc}
+ 802f87e:	bf00      	nop
+ 802f880:	240002a0 	.word	0x240002a0
+ 802f884:	24000290 	.word	0x24000290
+ 802f888:	240003a8 	.word	0x240003a8
+ 802f88c:	24000428 	.word	0x24000428
+ 802f890:	240004a8 	.word	0x240004a8
+ 802f894:	2400028c 	.word	0x2400028c
+ 802f898:	24000580 	.word	0x24000580
+ 802f89c:	2400a398 	.word	0x2400a398
+ 802f8a0:	240005cc 	.word	0x240005cc
+ 802f8a4:	2400a418 	.word	0x2400a418
+ 802f8a8:	24000558 	.word	0x24000558
+ 802f8ac:	2400a3f8 	.word	0x2400a3f8
+ 802f8b0:	24000358 	.word	0x24000358
+ 802f8b4:	2400a3ac 	.word	0x2400a3ac
+ 802f8b8:	240005d4 	.word	0x240005d4
+ 802f8bc:	2400a9d0 	.word	0x2400a9d0
+ 802f8c0:	24000340 	.word	0x24000340
+ 802f8c4:	2400a9d4 	.word	0x2400a9d4
+ 802f8c8:	24000344 	.word	0x24000344
+ 802f8cc:	2400a9dc 	.word	0x2400a9dc
+ 802f8d0:	2400a9e0 	.word	0x2400a9e0
+ 802f8d4:	2400034c 	.word	0x2400034c
+ 802f8d8:	2400a9d8 	.word	0x2400a9d8
+ 802f8dc:	24000334 	.word	0x24000334
+ 802f8e0:	2400a410 	.word	0x2400a410
+ 802f8e4:	24000348 	.word	0x24000348
+
+0802f8e8 <GF_Robot_Init>:
+
+void GF_Robot_Init()
+{
+ 802f8e8:	b580      	push	{r7, lr}
+ 802f8ea:	b08c      	sub	sp, #48	@ 0x30
+ 802f8ec:	af0c      	add	r7, sp, #48	@ 0x30
+	//GF_BSP_MPU_Init();
+	//2ms调度
+	GF_BSP_EEPROM_Init();
+ 802f8ee:	f7f0 ffdc 	bl	80208aa <GF_BSP_EEPROM_Init>
+	CV_GV_Init();
+ 802f8f2:	f7ff ff61 	bl	802f7b8 <CV_GV_Init>
+
+	//初始化encoder
+	GF_BSP_UARTHandlers_Intialize(
+ 802f8f6:	2364      	movs	r3, #100	@ 0x64
+ 802f8f8:	930b      	str	r3, [sp, #44]	@ 0x2c
+ 802f8fa:	2364      	movs	r3, #100	@ 0x64
+ 802f8fc:	930a      	str	r3, [sp, #40]	@ 0x28
+ 802f8fe:	2364      	movs	r3, #100	@ 0x64
+ 802f900:	9309      	str	r3, [sp, #36]	@ 0x24
+ 802f902:	2364      	movs	r3, #100	@ 0x64
+ 802f904:	9308      	str	r3, [sp, #32]
+ 802f906:	2364      	movs	r3, #100	@ 0x64
+ 802f908:	9307      	str	r3, [sp, #28]
+ 802f90a:	2364      	movs	r3, #100	@ 0x64
+ 802f90c:	9306      	str	r3, [sp, #24]
+ 802f90e:	2364      	movs	r3, #100	@ 0x64
+ 802f910:	9305      	str	r3, [sp, #20]
+ 802f912:	2364      	movs	r3, #100	@ 0x64
+ 802f914:	9304      	str	r3, [sp, #16]
+ 802f916:	2306      	movs	r3, #6
+ 802f918:	9303      	str	r3, [sp, #12]
+ 802f91a:	2304      	movs	r3, #4
+ 802f91c:	9302      	str	r3, [sp, #8]
+ 802f91e:	2306      	movs	r3, #6
+ 802f920:	9301      	str	r3, [sp, #4]
+ 802f922:	2306      	movs	r3, #6
+ 802f924:	9300      	str	r3, [sp, #0]
+ 802f926:	2306      	movs	r3, #6
+ 802f928:	2206      	movs	r2, #6
+ 802f92a:	2106      	movs	r1, #6
+ 802f92c:	2006      	movs	r0, #6
+ 802f92e:	f7f1 fdf7 	bl	8021520 <GF_BSP_UARTHandlers_Intialize>
+	RS485_4_Dispacher_Time,
+	LTE_7S0_Serial_Dispacher_Time,
+	InterCall_DEBUG_Dispacher_Time,
+	E28_SBUS_Dispacher_Time,
+	LPUART1_UART_Dispacher_Time);
+	is_upper_computer_take_over_control = 0;
+ 802f932:	4b1d      	ldr	r3, [pc, #116]	@ (802f9a8 <GF_Robot_Init+0xc0>)
+ 802f934:	2200      	movs	r2, #0
+ 802f936:	701a      	strb	r2, [r3, #0]
+
+	DLT_LOG_ENABLE_LEVEL = 0;	  //7 send all information 	  //0 send nothing
+ 802f938:	4b1c      	ldr	r3, [pc, #112]	@ (802f9ac <GF_Robot_Init+0xc4>)
+ 802f93a:	2200      	movs	r2, #0
+ 802f93c:	701a      	strb	r2, [r3, #0]
+	dLT_Log_intialize(&InterCall_DEBUG_UART_Handler);
+ 802f93e:	481c      	ldr	r0, [pc, #112]	@ (802f9b0 <GF_Robot_Init+0xc8>)
+ 802f940:	f7f0 ff08 	bl	8020754 <dLT_Log_intialize>
+	upper_Computer_UART_Handler_intialize(&RS_485_4_UART_Handler);
+ 802f944:	481b      	ldr	r0, [pc, #108]	@ (802f9b4 <GF_Robot_Init+0xcc>)
+ 802f946:	f7f2 fa81 	bl	8021e4c <upper_Computer_UART_Handler_intialize>
+	TL720D_intialize(&RS_485_1_UART_Handler);
+ 802f94a:	481b      	ldr	r0, [pc, #108]	@ (802f9b8 <GF_Robot_Init+0xd0>)
+ 802f94c:	f7f8 f9e4 	bl	8027d18 <TL720D_intialize>
+	MK32_Sbus_UART_Handler_intialize(&E28_SBUS_UART_Handler);
+ 802f950:	481a      	ldr	r0, [pc, #104]	@ (802f9bc <GF_Robot_Init+0xd4>)
+ 802f952:	f7f7 fecd 	bl	80276f0 <MK32_Sbus_UART_Handler_intialize>
+
+
+	client_setting_intialize(&LPUART1_UART_Handler);
+ 802f956:	481a      	ldr	r0, [pc, #104]	@ (802f9c0 <GF_Robot_Init+0xd8>)
+ 802f958:	f7f2 fabe 	bl	8021ed8 <client_setting_intialize>
+	WH_LTE_7S0_intialize(&LTE_7S0_Serial_UART_Handler);
+ 802f95c:	4819      	ldr	r0, [pc, #100]	@ (802f9c4 <GF_Robot_Init+0xdc>)
+ 802f95e:	f7f9 f8bf 	bl	8028ae0 <WH_LTE_7S0_intialize>
+	GF_BSP_FDCAN_Init();
+ 802f962:	f7f1 f9cd 	bl	8020d00 <GF_BSP_FDCAN_Init>
+	GF_BSP_CANHandler_Init(can1_sendListPeriod, can1_DispacherPeriod,
+ 802f966:	4b18      	ldr	r3, [pc, #96]	@ (802f9c8 <GF_Robot_Init+0xe0>)
+ 802f968:	6818      	ldr	r0, [r3, #0]
+ 802f96a:	4b18      	ldr	r3, [pc, #96]	@ (802f9cc <GF_Robot_Init+0xe4>)
+ 802f96c:	6819      	ldr	r1, [r3, #0]
+ 802f96e:	4b18      	ldr	r3, [pc, #96]	@ (802f9d0 <GF_Robot_Init+0xe8>)
+ 802f970:	681a      	ldr	r2, [r3, #0]
+ 802f972:	4b18      	ldr	r3, [pc, #96]	@ (802f9d4 <GF_Robot_Init+0xec>)
+ 802f974:	681b      	ldr	r3, [r3, #0]
+ 802f976:	f7f1 fa93 	bl	8020ea0 <GF_BSP_CANHandler_Init>
+	        can2_sendListPeriod, can2_DispacherPeriod);
+	Motor_Controller_intialize(&FD_CAN_1_Handler);
+ 802f97a:	4817      	ldr	r0, [pc, #92]	@ (802f9d8 <GF_Robot_Init+0xf0>)
+ 802f97c:	f000 f8ba 	bl	802faf4 <Motor_Controller_intialize>
+	Motor_Controller_intialize_CAN2(&FD_CAN_2_Handler);
+ 802f980:	4816      	ldr	r0, [pc, #88]	@ (802f9dc <GF_Robot_Init+0xf4>)
+ 802f982:	f000 f8f7 	bl	802fb74 <Motor_Controller_intialize_CAN2>
+	GF_MSP_Gyro_MFOG40_Init(&huart3,(MFOG40_Gyro_struct_define*)&GV.MFOG40_Plane);
+ 802f986:	4916      	ldr	r1, [pc, #88]	@ (802f9e0 <GF_Robot_Init+0xf8>)
+ 802f988:	4816      	ldr	r0, [pc, #88]	@ (802f9e4 <GF_Robot_Init+0xfc>)
+ 802f98a:	f7f7 faa3 	bl	8026ed4 <GF_MSP_Gyro_MFOG40_Init>
+	Fsm_Init();
+ 802f98e:	f7f9 fd91 	bl	80294b4 <Fsm_Init>
+	CMCU_sensor_intialize(&RS_485_3_UART_Handler);
+ 802f992:	4815      	ldr	r0, [pc, #84]	@ (802f9e8 <GF_Robot_Init+0x100>)
+ 802f994:	f7f7 f98a 	bl	8026cac <CMCU_sensor_intialize>
+
+//	KS206_sensor_intialize(&RS_485_4_UART_Handler);//115200
+	blast_control_intialize(&RS_485_4_UART_Handler);//喷砂机遥控器控制，共用一个串口
+ 802f998:	4806      	ldr	r0, [pc, #24]	@ (802f9b4 <GF_Robot_Init+0xcc>)
+ 802f99a:	f7f6 fcf7 	bl	802638c <blast_control_intialize>
+
+	GF_BSP_TIMER_Init(); //定时器最后启
+ 802f99e:	f7f1 fd4d 	bl	802143c <GF_BSP_TIMER_Init>
+
+}
+ 802f9a2:	bf00      	nop
+ 802f9a4:	46bd      	mov	sp, r7
+ 802f9a6:	bd80      	pop	{r7, pc}
+ 802f9a8:	2400a6c0 	.word	0x2400a6c0
+ 802f9ac:	24009110 	.word	0x24009110
+ 802f9b0:	24004db4 	.word	0x24004db4
+ 802f9b4:	24003d74 	.word	0x24003d74
+ 802f9b8:	24000cb4 	.word	0x24000cb4
+ 802f9bc:	24005df4 	.word	0x24005df4
+ 802f9c0:	24007e74 	.word	0x24007e74
+ 802f9c4:	24006e34 	.word	0x24006e34
+ 802f9c8:	24000118 	.word	0x24000118
+ 802f9cc:	2400011c 	.word	0x2400011c
+ 802f9d0:	24000120 	.word	0x24000120
+ 802f9d4:	24000124 	.word	0x24000124
+ 802f9d8:	2400061c 	.word	0x2400061c
+ 802f9dc:	24000754 	.word	0x24000754
+ 802f9e0:	240005b0 	.word	0x240005b0
+ 802f9e4:	2400ae08 	.word	0x2400ae08
+ 802f9e8:	24002d34 	.word	0x24002d34
+
+0802f9ec <MPU_Config>:
+/* USER CODE END 4 */
+
+ /* MPU Configuration */
+
+void MPU_Config(void)
+{
+ 802f9ec:	b580      	push	{r7, lr}
+ 802f9ee:	b084      	sub	sp, #16
+ 802f9f0:	af00      	add	r7, sp, #0
+  MPU_Region_InitTypeDef MPU_InitStruct = {0};
+ 802f9f2:	463b      	mov	r3, r7
+ 802f9f4:	2200      	movs	r2, #0
+ 802f9f6:	601a      	str	r2, [r3, #0]
+ 802f9f8:	605a      	str	r2, [r3, #4]
+ 802f9fa:	609a      	str	r2, [r3, #8]
+ 802f9fc:	60da      	str	r2, [r3, #12]
+
+  /* Disables the MPU */
+  HAL_MPU_Disable();
+ 802f9fe:	f003 f88d 	bl	8032b1c <HAL_MPU_Disable>
+
+  /** Initializes and configures the Region and the memory to be protected
+  */
+  MPU_InitStruct.Enable = MPU_REGION_ENABLE;
+ 802fa02:	2301      	movs	r3, #1
+ 802fa04:	703b      	strb	r3, [r7, #0]
+  MPU_InitStruct.Number = MPU_REGION_NUMBER0;
+ 802fa06:	2300      	movs	r3, #0
+ 802fa08:	707b      	strb	r3, [r7, #1]
+  MPU_InitStruct.BaseAddress = 0x30040000;
+ 802fa0a:	4b1d      	ldr	r3, [pc, #116]	@ (802fa80 <MPU_Config+0x94>)
+ 802fa0c:	607b      	str	r3, [r7, #4]
+  MPU_InitStruct.Size = MPU_REGION_SIZE_32KB;
+ 802fa0e:	230e      	movs	r3, #14
+ 802fa10:	723b      	strb	r3, [r7, #8]
+  MPU_InitStruct.SubRegionDisable = 0x0;
+ 802fa12:	2300      	movs	r3, #0
+ 802fa14:	727b      	strb	r3, [r7, #9]
+  MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1;
+ 802fa16:	2301      	movs	r3, #1
+ 802fa18:	72bb      	strb	r3, [r7, #10]
+  MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
+ 802fa1a:	2303      	movs	r3, #3
+ 802fa1c:	72fb      	strb	r3, [r7, #11]
+  MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
+ 802fa1e:	2300      	movs	r3, #0
+ 802fa20:	733b      	strb	r3, [r7, #12]
+  MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
+ 802fa22:	2300      	movs	r3, #0
+ 802fa24:	737b      	strb	r3, [r7, #13]
+  MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
+ 802fa26:	2300      	movs	r3, #0
+ 802fa28:	73bb      	strb	r3, [r7, #14]
+  MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
+ 802fa2a:	2300      	movs	r3, #0
+ 802fa2c:	73fb      	strb	r3, [r7, #15]
+
+  HAL_MPU_ConfigRegion(&MPU_InitStruct);
+ 802fa2e:	463b      	mov	r3, r7
+ 802fa30:	4618      	mov	r0, r3
+ 802fa32:	f003 f8ab 	bl	8032b8c <HAL_MPU_ConfigRegion>
+
+  /** Initializes and configures the Region and the memory to be protected
+  */
+  MPU_InitStruct.Number = MPU_REGION_NUMBER1;
+ 802fa36:	2301      	movs	r3, #1
+ 802fa38:	707b      	strb	r3, [r7, #1]
+  MPU_InitStruct.Size = MPU_REGION_SIZE_1KB;
+ 802fa3a:	2309      	movs	r3, #9
+ 802fa3c:	723b      	strb	r3, [r7, #8]
+  MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
+ 802fa3e:	2300      	movs	r3, #0
+ 802fa40:	72bb      	strb	r3, [r7, #10]
+  MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
+ 802fa42:	2301      	movs	r3, #1
+ 802fa44:	737b      	strb	r3, [r7, #13]
+  MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;
+ 802fa46:	2301      	movs	r3, #1
+ 802fa48:	73fb      	strb	r3, [r7, #15]
+
+  HAL_MPU_ConfigRegion(&MPU_InitStruct);
+ 802fa4a:	463b      	mov	r3, r7
+ 802fa4c:	4618      	mov	r0, r3
+ 802fa4e:	f003 f89d 	bl	8032b8c <HAL_MPU_ConfigRegion>
+
+  /** Initializes and configures the Region and the memory to be protected
+  */
+  MPU_InitStruct.Number = MPU_REGION_NUMBER2;
+ 802fa52:	2302      	movs	r3, #2
+ 802fa54:	707b      	strb	r3, [r7, #1]
+  MPU_InitStruct.BaseAddress = 0x30030000;
+ 802fa56:	4b0b      	ldr	r3, [pc, #44]	@ (802fa84 <MPU_Config+0x98>)
+ 802fa58:	607b      	str	r3, [r7, #4]
+  MPU_InitStruct.Size = MPU_REGION_SIZE_32KB;
+ 802fa5a:	230e      	movs	r3, #14
+ 802fa5c:	723b      	strb	r3, [r7, #8]
+  MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1;
+ 802fa5e:	2301      	movs	r3, #1
+ 802fa60:	72bb      	strb	r3, [r7, #10]
+  MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
+ 802fa62:	2300      	movs	r3, #0
+ 802fa64:	737b      	strb	r3, [r7, #13]
+  MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
+ 802fa66:	2300      	movs	r3, #0
+ 802fa68:	73fb      	strb	r3, [r7, #15]
+
+  HAL_MPU_ConfigRegion(&MPU_InitStruct);
+ 802fa6a:	463b      	mov	r3, r7
+ 802fa6c:	4618      	mov	r0, r3
+ 802fa6e:	f003 f88d 	bl	8032b8c <HAL_MPU_ConfigRegion>
+  /* Enables the MPU */
+  HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
+ 802fa72:	2004      	movs	r0, #4
+ 802fa74:	f003 f86a 	bl	8032b4c <HAL_MPU_Enable>
+
+}
+ 802fa78:	bf00      	nop
+ 802fa7a:	3710      	adds	r7, #16
+ 802fa7c:	46bd      	mov	sp, r7
+ 802fa7e:	bd80      	pop	{r7, pc}
+ 802fa80:	30040000 	.word	0x30040000
+ 802fa84:	30030000 	.word	0x30030000
+
+0802fa88 <Error_Handler>:
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+ 802fa88:	b580      	push	{r7, lr}
+ 802fa8a:	b084      	sub	sp, #16
+ 802fa8c:	af04      	add	r7, sp, #16
+  __ASM volatile ("cpsid i" : : : "memory");
+ 802fa8e:	b672      	cpsid	i
+}
+ 802fa90:	bf00      	nop
+
+	/* User can add his own implementation to report the HAL error return state */
+	__disable_irq();
+	while (1)
+	{
+		HAL_Delay(1000);
+ 802fa92:	f44f 707a 	mov.w	r0, #1000	@ 0x3e8
+ 802fa96:	f001 ff57 	bl	8031948 <HAL_Delay>
+		LOGFF(DL_ERROR, "Something Bad Happened, Now in Error_Handler Function");
+ 802fa9a:	4b12      	ldr	r3, [pc, #72]	@ (802fae4 <Error_Handler+0x5c>)
+ 802fa9c:	781b      	ldrb	r3, [r3, #0]
+ 802fa9e:	2b01      	cmp	r3, #1
+ 802faa0:	d9f7      	bls.n	802fa92 <Error_Handler+0xa>
+ 802faa2:	2330      	movs	r3, #48	@ 0x30
+ 802faa4:	061a      	lsls	r2, r3, #24
+ 802faa6:	2330      	movs	r3, #48	@ 0x30
+ 802faa8:	041b      	lsls	r3, r3, #16
+ 802faaa:	431a      	orrs	r2, r3
+ 802faac:	2330      	movs	r3, #48	@ 0x30
+ 802faae:	021b      	lsls	r3, r3, #8
+ 802fab0:	4313      	orrs	r3, r2
+ 802fab2:	2230      	movs	r2, #48	@ 0x30
+ 802fab4:	ea43 0102 	orr.w	r1, r3, r2
+ 802fab8:	2344      	movs	r3, #68	@ 0x44
+ 802faba:	061a      	lsls	r2, r3, #24
+ 802fabc:	2346      	movs	r3, #70	@ 0x46
+ 802fabe:	041b      	lsls	r3, r3, #16
+ 802fac0:	431a      	orrs	r2, r3
+ 802fac2:	234c      	movs	r3, #76	@ 0x4c
+ 802fac4:	021b      	lsls	r3, r3, #8
+ 802fac6:	4313      	orrs	r3, r2
+ 802fac8:	2254      	movs	r2, #84	@ 0x54
+ 802faca:	431a      	orrs	r2, r3
+ 802facc:	4b06      	ldr	r3, [pc, #24]	@ (802fae8 <Error_Handler+0x60>)
+ 802face:	9302      	str	r3, [sp, #8]
+ 802fad0:	f44f 73d2 	mov.w	r3, #420	@ 0x1a4
+ 802fad4:	9301      	str	r3, [sp, #4]
+ 802fad6:	4b05      	ldr	r3, [pc, #20]	@ (802faec <Error_Handler+0x64>)
+ 802fad8:	9300      	str	r3, [sp, #0]
+ 802fada:	4b05      	ldr	r3, [pc, #20]	@ (802faf0 <Error_Handler+0x68>)
+ 802fadc:	2002      	movs	r0, #2
+ 802fade:	f7f6 fba9 	bl	8026234 <DLTuc_LogOutVarArgs>
+		HAL_Delay(1000);
+ 802fae2:	e7d6      	b.n	802fa92 <Error_Handler+0xa>
+ 802fae4:	24009110 	.word	0x24009110
+ 802fae8:	08041c48 	.word	0x08041c48
+ 802faec:	08041504 	.word	0x08041504
+ 802faf0:	080414b0 	.word	0x080414b0
+
+0802faf4 <Motor_Controller_intialize>:
+void MotorCommandsLoop_2();
+void MotorCommandsLoop_2_Position();
+void Roughening_MotorDecodeCAN(uint32_t canID, uint8_t *buffer, uint32_t length);
+
+void Motor_Controller_intialize(FDCANHandler *Handler)
+{
+ 802faf4:	b590      	push	{r4, r7, lr}
+ 802faf6:	b083      	sub	sp, #12
+ 802faf8:	af00      	add	r7, sp, #0
+ 802fafa:	6078      	str	r0, [r7, #4]
+	//初始化
+
+	Roughening_Motor_Controller = Handler;
+ 802fafc:	4a16      	ldr	r2, [pc, #88]	@ (802fb58 <Motor_Controller_intialize+0x64>)
+ 802fafe:	687b      	ldr	r3, [r7, #4]
+ 802fb00:	6013      	str	r3, [r2, #0]
+	Roughening_Motor_Controller->CAN_Decode = Roughening_MotorDecodeCAN;
+ 802fb02:	4b15      	ldr	r3, [pc, #84]	@ (802fb58 <Motor_Controller_intialize+0x64>)
+ 802fb04:	681b      	ldr	r3, [r3, #0]
+ 802fb06:	4a15      	ldr	r2, [pc, #84]	@ (802fb5c <Motor_Controller_intialize+0x68>)
+ 802fb08:	61da      	str	r2, [r3, #28]
+
+	HardWareErrorController->Add_PCOMHardWare(HardWareErrorController,"ZQ_CAN_ID1_LeftMotor",  0, ComError_ZQ_CAN_ID1_LeftMotor);
+ 802fb0a:	4b15      	ldr	r3, [pc, #84]	@ (802fb60 <Motor_Controller_intialize+0x6c>)
+ 802fb0c:	681b      	ldr	r3, [r3, #0]
+ 802fb0e:	68dc      	ldr	r4, [r3, #12]
+ 802fb10:	4b13      	ldr	r3, [pc, #76]	@ (802fb60 <Motor_Controller_intialize+0x6c>)
+ 802fb12:	6818      	ldr	r0, [r3, #0]
+ 802fb14:	2304      	movs	r3, #4
+ 802fb16:	2200      	movs	r2, #0
+ 802fb18:	4912      	ldr	r1, [pc, #72]	@ (802fb64 <Motor_Controller_intialize+0x70>)
+ 802fb1a:	47a0      	blx	r4
+	HardWareErrorController->Add_PCOMHardWare(HardWareErrorController,"ZQ_CAN_ID2_RightMotor", 0, ComError_ZQ_CAN_ID2_RightMotor);
+ 802fb1c:	4b10      	ldr	r3, [pc, #64]	@ (802fb60 <Motor_Controller_intialize+0x6c>)
+ 802fb1e:	681b      	ldr	r3, [r3, #0]
+ 802fb20:	68dc      	ldr	r4, [r3, #12]
+ 802fb22:	4b0f      	ldr	r3, [pc, #60]	@ (802fb60 <Motor_Controller_intialize+0x6c>)
+ 802fb24:	6818      	ldr	r0, [r3, #0]
+ 802fb26:	2305      	movs	r3, #5
+ 802fb28:	2200      	movs	r2, #0
+ 802fb2a:	490f      	ldr	r1, [pc, #60]	@ (802fb68 <Motor_Controller_intialize+0x74>)
+ 802fb2c:	47a0      	blx	r4
+//	HardWareErrorController->Add_PCOMHardWare(HardWareErrorController,"ZQ_CAN_ID3_SwingMotor", 0, ComError_ZQ_CAN_ID3_SwingMotor);
+
+	Roughening_DispacherController = Handler->dispacherController;
+ 802fb2e:	687b      	ldr	r3, [r7, #4]
+ 802fb30:	685b      	ldr	r3, [r3, #4]
+ 802fb32:	4a0e      	ldr	r2, [pc, #56]	@ (802fb6c <Motor_Controller_intialize+0x78>)
+ 802fb34:	6013      	str	r3, [r2, #0]
+	Roughening_DispacherController->DispacherCallTime = 2;
+ 802fb36:	4b0d      	ldr	r3, [pc, #52]	@ (802fb6c <Motor_Controller_intialize+0x78>)
+ 802fb38:	681b      	ldr	r3, [r3, #0]
+ 802fb3a:	2202      	movs	r2, #2
+ 802fb3c:	815a      	strh	r2, [r3, #10]
+	Roughening_DispacherController->Add_Dispatcher_List(Roughening_DispacherController, MotorCommandsLoop);
+ 802fb3e:	4b0b      	ldr	r3, [pc, #44]	@ (802fb6c <Motor_Controller_intialize+0x78>)
+ 802fb40:	681b      	ldr	r3, [r3, #0]
+ 802fb42:	691b      	ldr	r3, [r3, #16]
+ 802fb44:	4a09      	ldr	r2, [pc, #36]	@ (802fb6c <Motor_Controller_intialize+0x78>)
+ 802fb46:	6812      	ldr	r2, [r2, #0]
+ 802fb48:	4909      	ldr	r1, [pc, #36]	@ (802fb70 <Motor_Controller_intialize+0x7c>)
+ 802fb4a:	4610      	mov	r0, r2
+ 802fb4c:	4798      	blx	r3
+
+}
+ 802fb4e:	bf00      	nop
+ 802fb50:	370c      	adds	r7, #12
+ 802fb52:	46bd      	mov	sp, r7
+ 802fb54:	bd90      	pop	{r4, r7, pc}
+ 802fb56:	bf00      	nop
+ 802fb58:	2400a964 	.word	0x2400a964
+ 802fb5c:	0802fe9d 	.word	0x0802fe9d
+ 802fb60:	24000618 	.word	0x24000618
+ 802fb64:	08041518 	.word	0x08041518
+ 802fb68:	08041530 	.word	0x08041530
+ 802fb6c:	2400a96c 	.word	0x2400a96c
+ 802fb70:	0802fbdd 	.word	0x0802fbdd
+
+0802fb74 <Motor_Controller_intialize_CAN2>:
+void Motor_Controller_intialize_CAN2(FDCANHandler *Handler)
+{
+ 802fb74:	b590      	push	{r4, r7, lr}
+ 802fb76:	b083      	sub	sp, #12
+ 802fb78:	af00      	add	r7, sp, #0
+ 802fb7a:	6078      	str	r0, [r7, #4]
+	//初始化
+
+	Roughening_Motor_Controller_CAN2 = Handler;
+ 802fb7c:	4a11      	ldr	r2, [pc, #68]	@ (802fbc4 <Motor_Controller_intialize_CAN2+0x50>)
+ 802fb7e:	687b      	ldr	r3, [r7, #4]
+ 802fb80:	6013      	str	r3, [r2, #0]
+	Roughening_Motor_Controller_CAN2->CAN_Decode = Roughening_MotorDecodeCAN;
+ 802fb82:	4b10      	ldr	r3, [pc, #64]	@ (802fbc4 <Motor_Controller_intialize_CAN2+0x50>)
+ 802fb84:	681b      	ldr	r3, [r3, #0]
+ 802fb86:	4a10      	ldr	r2, [pc, #64]	@ (802fbc8 <Motor_Controller_intialize_CAN2+0x54>)
+ 802fb88:	61da      	str	r2, [r3, #28]
+
+
+	HardWareErrorController->Add_PCOMHardWare(HardWareErrorController,"ZQ_CAN_ID3_SwingMotor", 0, ComError_ZQ_CAN_ID3_SwingMotor);
+ 802fb8a:	4b10      	ldr	r3, [pc, #64]	@ (802fbcc <Motor_Controller_intialize_CAN2+0x58>)
+ 802fb8c:	681b      	ldr	r3, [r3, #0]
+ 802fb8e:	68dc      	ldr	r4, [r3, #12]
+ 802fb90:	4b0e      	ldr	r3, [pc, #56]	@ (802fbcc <Motor_Controller_intialize_CAN2+0x58>)
+ 802fb92:	6818      	ldr	r0, [r3, #0]
+ 802fb94:	2306      	movs	r3, #6
+ 802fb96:	2200      	movs	r2, #0
+ 802fb98:	490d      	ldr	r1, [pc, #52]	@ (802fbd0 <Motor_Controller_intialize_CAN2+0x5c>)
+ 802fb9a:	47a0      	blx	r4
+
+	Roughening_DispacherController_CAN2 = Handler->dispacherController;
+ 802fb9c:	687b      	ldr	r3, [r7, #4]
+ 802fb9e:	685b      	ldr	r3, [r3, #4]
+ 802fba0:	4a0c      	ldr	r2, [pc, #48]	@ (802fbd4 <Motor_Controller_intialize_CAN2+0x60>)
+ 802fba2:	6013      	str	r3, [r2, #0]
+	Roughening_DispacherController_CAN2->DispacherCallTime = 2;
+ 802fba4:	4b0b      	ldr	r3, [pc, #44]	@ (802fbd4 <Motor_Controller_intialize_CAN2+0x60>)
+ 802fba6:	681b      	ldr	r3, [r3, #0]
+ 802fba8:	2202      	movs	r2, #2
+ 802fbaa:	815a      	strh	r2, [r3, #10]
+	Roughening_DispacherController_CAN2->Add_Dispatcher_List(Roughening_DispacherController_CAN2, MotorCommandsLoop_2_Position);
+ 802fbac:	4b09      	ldr	r3, [pc, #36]	@ (802fbd4 <Motor_Controller_intialize_CAN2+0x60>)
+ 802fbae:	681b      	ldr	r3, [r3, #0]
+ 802fbb0:	691b      	ldr	r3, [r3, #16]
+ 802fbb2:	4a08      	ldr	r2, [pc, #32]	@ (802fbd4 <Motor_Controller_intialize_CAN2+0x60>)
+ 802fbb4:	6812      	ldr	r2, [r2, #0]
+ 802fbb6:	4908      	ldr	r1, [pc, #32]	@ (802fbd8 <Motor_Controller_intialize_CAN2+0x64>)
+ 802fbb8:	4610      	mov	r0, r2
+ 802fbba:	4798      	blx	r3
+
+
+}
+ 802fbbc:	bf00      	nop
+ 802fbbe:	370c      	adds	r7, #12
+ 802fbc0:	46bd      	mov	sp, r7
+ 802fbc2:	bd90      	pop	{r4, r7, pc}
+ 802fbc4:	2400a968 	.word	0x2400a968
+ 802fbc8:	0802fe9d 	.word	0x0802fe9d
+ 802fbcc:	24000618 	.word	0x24000618
+ 802fbd0:	08041548 	.word	0x08041548
+ 802fbd4:	2400a970 	.word	0x2400a970
+ 802fbd8:	0802fdad 	.word	0x0802fdad
+
+0802fbdc <MotorCommandsLoop>:
+
+
+void MotorCommandsLoop()
+{
+ 802fbdc:	b580      	push	{r7, lr}
+ 802fbde:	b084      	sub	sp, #16
+ 802fbe0:	af02      	add	r7, sp, #8
+	static int Heartbeat_Flag_01;
+	if (TT_Motor_Need_To_Activate == 1)
+ 802fbe2:	4b6d      	ldr	r3, [pc, #436]	@ (802fd98 <MotorCommandsLoop+0x1bc>)
+ 802fbe4:	781b      	ldrb	r3, [r3, #0]
+ 802fbe6:	2b01      	cmp	r3, #1
+ 802fbe8:	d175      	bne.n	802fcd6 <MotorCommandsLoop+0xfa>
+	{
+		ActivateMotor(1, Roughening_Motor_Controller, 6000);
+ 802fbea:	4b6c      	ldr	r3, [pc, #432]	@ (802fd9c <MotorCommandsLoop+0x1c0>)
+ 802fbec:	681b      	ldr	r3, [r3, #0]
+ 802fbee:	f241 7270 	movw	r2, #6000	@ 0x1770
+ 802fbf2:	4619      	mov	r1, r3
+ 802fbf4:	2001      	movs	r0, #1
+ 802fbf6:	f7f8 fa3d 	bl	8028074 <ActivateMotor>
+		ActivateMotor(2, Roughening_Motor_Controller, 2000);
+ 802fbfa:	4b68      	ldr	r3, [pc, #416]	@ (802fd9c <MotorCommandsLoop+0x1c0>)
+ 802fbfc:	681b      	ldr	r3, [r3, #0]
+ 802fbfe:	f44f 62fa 	mov.w	r2, #2000	@ 0x7d0
+ 802fc02:	4619      	mov	r1, r3
+ 802fc04:	2002      	movs	r0, #2
+ 802fc06:	f7f8 fa35 	bl	8028074 <ActivateMotor>
+
+		Enable_NMT(000,Roughening_Motor_Controller,01,1000);
+ 802fc0a:	4b64      	ldr	r3, [pc, #400]	@ (802fd9c <MotorCommandsLoop+0x1c0>)
+ 802fc0c:	6819      	ldr	r1, [r3, #0]
+ 802fc0e:	f44f 737a 	mov.w	r3, #1000	@ 0x3e8
+ 802fc12:	2201      	movs	r2, #1
+ 802fc14:	2000      	movs	r0, #0
+ 802fc16:	f7f8 fa4d 	bl	80280b4 <Enable_NMT>
+		Enable_NMT(000,Roughening_Motor_Controller,02,1000);
+ 802fc1a:	4b60      	ldr	r3, [pc, #384]	@ (802fd9c <MotorCommandsLoop+0x1c0>)
+ 802fc1c:	6819      	ldr	r1, [r3, #0]
+ 802fc1e:	f44f 737a 	mov.w	r3, #1000	@ 0x3e8
+ 802fc22:	2202      	movs	r2, #2
+ 802fc24:	2000      	movs	r0, #0
+ 802fc26:	f7f8 fa45 	bl	80280b4 <Enable_NMT>
+
+		Configure_Asynchronous_Mode(1, Roughening_Motor_Controller, 7,600);
+ 802fc2a:	4b5c      	ldr	r3, [pc, #368]	@ (802fd9c <MotorCommandsLoop+0x1c0>)
+ 802fc2c:	6819      	ldr	r1, [r3, #0]
+ 802fc2e:	f44f 7316 	mov.w	r3, #600	@ 0x258
+ 802fc32:	2207      	movs	r2, #7
+ 802fc34:	2001      	movs	r0, #1
+ 802fc36:	f7f8 fa5f 	bl	80280f8 <Configure_Asynchronous_Mode>
+		Consumer_Or_microcontroller_Heartbeat(0x707, Roughening_Motor_Controller,  4);
+ 802fc3a:	4b58      	ldr	r3, [pc, #352]	@ (802fd9c <MotorCommandsLoop+0x1c0>)
+ 802fc3c:	681b      	ldr	r3, [r3, #0]
+ 802fc3e:	2204      	movs	r2, #4
+ 802fc40:	4619      	mov	r1, r3
+ 802fc42:	f240 7007 	movw	r0, #1799	@ 0x707
+ 802fc46:	f7f8 fa95 	bl	8028174 <Consumer_Or_microcontroller_Heartbeat>
+		Configure_Asynchronous_Mode(2, Roughening_Motor_Controller, 8,600);
+ 802fc4a:	4b54      	ldr	r3, [pc, #336]	@ (802fd9c <MotorCommandsLoop+0x1c0>)
+ 802fc4c:	6819      	ldr	r1, [r3, #0]
+ 802fc4e:	f44f 7316 	mov.w	r3, #600	@ 0x258
+ 802fc52:	2208      	movs	r2, #8
+ 802fc54:	2002      	movs	r0, #2
+ 802fc56:	f7f8 fa4f 	bl	80280f8 <Configure_Asynchronous_Mode>
+		Consumer_Or_microcontroller_Heartbeat(0x707, Roughening_Motor_Controller,  4);
+ 802fc5a:	4b50      	ldr	r3, [pc, #320]	@ (802fd9c <MotorCommandsLoop+0x1c0>)
+ 802fc5c:	681b      	ldr	r3, [r3, #0]
+ 802fc5e:	2204      	movs	r2, #4
+ 802fc60:	4619      	mov	r1, r3
+ 802fc62:	f240 7007 	movw	r0, #1799	@ 0x707
+ 802fc66:	f7f8 fa85 	bl	8028174 <Consumer_Or_microcontroller_Heartbeat>
+		SpeedModeSetup(1, Roughening_Motor_Controller, 6, 500, 500, 0);
+ 802fc6a:	4b4c      	ldr	r3, [pc, #304]	@ (802fd9c <MotorCommandsLoop+0x1c0>)
+ 802fc6c:	6819      	ldr	r1, [r3, #0]
+ 802fc6e:	2300      	movs	r3, #0
+ 802fc70:	9301      	str	r3, [sp, #4]
+ 802fc72:	f44f 73fa 	mov.w	r3, #500	@ 0x1f4
+ 802fc76:	9300      	str	r3, [sp, #0]
+ 802fc78:	f44f 73fa 	mov.w	r3, #500	@ 0x1f4
+ 802fc7c:	2206      	movs	r2, #6
+ 802fc7e:	2001      	movs	r0, #1
+ 802fc80:	f7f8 fb66 	bl	8028350 <SpeedModeSetup>
+		Consumer_Or_microcontroller_Heartbeat(0x708, Roughening_Motor_Controller,  4);
+ 802fc84:	4b45      	ldr	r3, [pc, #276]	@ (802fd9c <MotorCommandsLoop+0x1c0>)
+ 802fc86:	681b      	ldr	r3, [r3, #0]
+ 802fc88:	2204      	movs	r2, #4
+ 802fc8a:	4619      	mov	r1, r3
+ 802fc8c:	f44f 60e1 	mov.w	r0, #1800	@ 0x708
+ 802fc90:	f7f8 fa70 	bl	8028174 <Consumer_Or_microcontroller_Heartbeat>
+		SpeedModeSetup(2, Roughening_Motor_Controller, 6, 500, 500, 0);
+ 802fc94:	4b41      	ldr	r3, [pc, #260]	@ (802fd9c <MotorCommandsLoop+0x1c0>)
+ 802fc96:	6819      	ldr	r1, [r3, #0]
+ 802fc98:	2300      	movs	r3, #0
+ 802fc9a:	9301      	str	r3, [sp, #4]
+ 802fc9c:	f44f 73fa 	mov.w	r3, #500	@ 0x1f4
+ 802fca0:	9300      	str	r3, [sp, #0]
+ 802fca2:	f44f 73fa 	mov.w	r3, #500	@ 0x1f4
+ 802fca6:	2206      	movs	r2, #6
+ 802fca8:	2002      	movs	r0, #2
+ 802fcaa:	f7f8 fb51 	bl	8028350 <SpeedModeSetup>
+		Consumer_Or_microcontroller_Heartbeat(0x707, Roughening_Motor_Controller,  4);
+ 802fcae:	4b3b      	ldr	r3, [pc, #236]	@ (802fd9c <MotorCommandsLoop+0x1c0>)
+ 802fcb0:	681b      	ldr	r3, [r3, #0]
+ 802fcb2:	2204      	movs	r2, #4
+ 802fcb4:	4619      	mov	r1, r3
+ 802fcb6:	f240 7007 	movw	r0, #1799	@ 0x707
+ 802fcba:	f7f8 fa5b 	bl	8028174 <Consumer_Or_microcontroller_Heartbeat>
+		Consumer_Or_microcontroller_Heartbeat(0x708, Roughening_Motor_Controller,  4);
+ 802fcbe:	4b37      	ldr	r3, [pc, #220]	@ (802fd9c <MotorCommandsLoop+0x1c0>)
+ 802fcc0:	681b      	ldr	r3, [r3, #0]
+ 802fcc2:	2204      	movs	r2, #4
+ 802fcc4:	4619      	mov	r1, r3
+ 802fcc6:	f44f 60e1 	mov.w	r0, #1800	@ 0x708
+ 802fcca:	f7f8 fa53 	bl	8028174 <Consumer_Or_microcontroller_Heartbeat>
+		TT_Motor_Need_To_Activate = 0;
+ 802fcce:	4b32      	ldr	r3, [pc, #200]	@ (802fd98 <MotorCommandsLoop+0x1bc>)
+ 802fcd0:	2200      	movs	r2, #0
+ 802fcd2:	701a      	strb	r2, [r3, #0]
+ 802fcd4:	e035      	b.n	802fd42 <MotorCommandsLoop+0x166>
+	}
+	else
+	{
+		for (int i = 1; i < 3; i++)//前两个电机
+ 802fcd6:	2301      	movs	r3, #1
+ 802fcd8:	607b      	str	r3, [r7, #4]
+ 802fcda:	e01e      	b.n	802fd1a <MotorCommandsLoop+0x13e>
+		{
+			TT_Request_Position(i, Roughening_Motor_Controller, 6);
+ 802fcdc:	687b      	ldr	r3, [r7, #4]
+ 802fcde:	4a2f      	ldr	r2, [pc, #188]	@ (802fd9c <MotorCommandsLoop+0x1c0>)
+ 802fce0:	6811      	ldr	r1, [r2, #0]
+ 802fce2:	2206      	movs	r2, #6
+ 802fce4:	4618      	mov	r0, r3
+ 802fce6:	f7f8 fbcb 	bl	8028480 <TT_Request_Position>
+			TT_Request_Velocity(i, Roughening_Motor_Controller, 6);
+ 802fcea:	687b      	ldr	r3, [r7, #4]
+ 802fcec:	4a2b      	ldr	r2, [pc, #172]	@ (802fd9c <MotorCommandsLoop+0x1c0>)
+ 802fcee:	6811      	ldr	r1, [r2, #0]
+ 802fcf0:	2206      	movs	r2, #6
+ 802fcf2:	4618      	mov	r0, r3
+ 802fcf4:	f7f8 fc5b 	bl	80285ae <TT_Request_Velocity>
+			TT_Request_Current(i, Roughening_Motor_Controller, 6);
+ 802fcf8:	687b      	ldr	r3, [r7, #4]
+ 802fcfa:	4a28      	ldr	r2, [pc, #160]	@ (802fd9c <MotorCommandsLoop+0x1c0>)
+ 802fcfc:	6811      	ldr	r1, [r2, #0]
+ 802fcfe:	2206      	movs	r2, #6
+ 802fd00:	4618      	mov	r0, r3
+ 802fd02:	f7f8 fc82 	bl	802860a <TT_Request_Current>
+			TT_Request_Fault(i, Roughening_Motor_Controller, 6);
+ 802fd06:	687b      	ldr	r3, [r7, #4]
+ 802fd08:	4a24      	ldr	r2, [pc, #144]	@ (802fd9c <MotorCommandsLoop+0x1c0>)
+ 802fd0a:	6811      	ldr	r1, [r2, #0]
+ 802fd0c:	2206      	movs	r2, #6
+ 802fd0e:	4618      	mov	r0, r3
+ 802fd10:	f7f8 fc64 	bl	80285dc <TT_Request_Fault>
+		for (int i = 1; i < 3; i++)//前两个电机
+ 802fd14:	687b      	ldr	r3, [r7, #4]
+ 802fd16:	3301      	adds	r3, #1
+ 802fd18:	607b      	str	r3, [r7, #4]
+ 802fd1a:	687b      	ldr	r3, [r7, #4]
+ 802fd1c:	2b02      	cmp	r3, #2
+ 802fd1e:	dddd      	ble.n	802fcdc <MotorCommandsLoop+0x100>
+		}
+		TT_SpeedMode_Set_TargetSpeed(1, Roughening_Motor_Controller, 6,GV.LeftMotor.Target_Velcity);
+ 802fd20:	4b1e      	ldr	r3, [pc, #120]	@ (802fd9c <MotorCommandsLoop+0x1c0>)
+ 802fd22:	6819      	ldr	r1, [r3, #0]
+ 802fd24:	4b1e      	ldr	r3, [pc, #120]	@ (802fda0 <MotorCommandsLoop+0x1c4>)
+ 802fd26:	6f9b      	ldr	r3, [r3, #120]	@ 0x78
+ 802fd28:	2206      	movs	r2, #6
+ 802fd2a:	2001      	movs	r0, #1
+ 802fd2c:	f7f8 fb90 	bl	8028450 <TT_SpeedMode_Set_TargetSpeed>
+		TT_SpeedMode_Set_TargetSpeed(2, Roughening_Motor_Controller, 6,GV.RightMotor.Target_Velcity);
+ 802fd30:	4b1a      	ldr	r3, [pc, #104]	@ (802fd9c <MotorCommandsLoop+0x1c0>)
+ 802fd32:	6819      	ldr	r1, [r3, #0]
+ 802fd34:	4b1a      	ldr	r3, [pc, #104]	@ (802fda0 <MotorCommandsLoop+0x1c4>)
+ 802fd36:	f8d3 30f8 	ldr.w	r3, [r3, #248]	@ 0xf8
+ 802fd3a:	2206      	movs	r2, #6
+ 802fd3c:	2002      	movs	r0, #2
+ 802fd3e:	f7f8 fb87 	bl	8028450 <TT_SpeedMode_Set_TargetSpeed>
+	}
+
+	Heartbeat_Flag_01++;
+ 802fd42:	4b18      	ldr	r3, [pc, #96]	@ (802fda4 <MotorCommandsLoop+0x1c8>)
+ 802fd44:	681b      	ldr	r3, [r3, #0]
+ 802fd46:	3301      	adds	r3, #1
+ 802fd48:	4a16      	ldr	r2, [pc, #88]	@ (802fda4 <MotorCommandsLoop+0x1c8>)
+ 802fd4a:	6013      	str	r3, [r2, #0]
+	if(Heartbeat_Flag_01%7==0)
+ 802fd4c:	4b15      	ldr	r3, [pc, #84]	@ (802fda4 <MotorCommandsLoop+0x1c8>)
+ 802fd4e:	681a      	ldr	r2, [r3, #0]
+ 802fd50:	4b15      	ldr	r3, [pc, #84]	@ (802fda8 <MotorCommandsLoop+0x1cc>)
+ 802fd52:	fb83 1302 	smull	r1, r3, r3, r2
+ 802fd56:	4413      	add	r3, r2
+ 802fd58:	1099      	asrs	r1, r3, #2
+ 802fd5a:	17d3      	asrs	r3, r2, #31
+ 802fd5c:	1ac9      	subs	r1, r1, r3
+ 802fd5e:	460b      	mov	r3, r1
+ 802fd60:	00db      	lsls	r3, r3, #3
+ 802fd62:	1a5b      	subs	r3, r3, r1
+ 802fd64:	1ad1      	subs	r1, r2, r3
+ 802fd66:	2900      	cmp	r1, #0
+ 802fd68:	d112      	bne.n	802fd90 <MotorCommandsLoop+0x1b4>
+	{
+		Consumer_Or_microcontroller_Heartbeat(0x707, Roughening_Motor_Controller,  4);
+ 802fd6a:	4b0c      	ldr	r3, [pc, #48]	@ (802fd9c <MotorCommandsLoop+0x1c0>)
+ 802fd6c:	681b      	ldr	r3, [r3, #0]
+ 802fd6e:	2204      	movs	r2, #4
+ 802fd70:	4619      	mov	r1, r3
+ 802fd72:	f240 7007 	movw	r0, #1799	@ 0x707
+ 802fd76:	f7f8 f9fd 	bl	8028174 <Consumer_Or_microcontroller_Heartbeat>
+		Consumer_Or_microcontroller_Heartbeat(0x708, Roughening_Motor_Controller,  4);
+ 802fd7a:	4b08      	ldr	r3, [pc, #32]	@ (802fd9c <MotorCommandsLoop+0x1c0>)
+ 802fd7c:	681b      	ldr	r3, [r3, #0]
+ 802fd7e:	2204      	movs	r2, #4
+ 802fd80:	4619      	mov	r1, r3
+ 802fd82:	f44f 60e1 	mov.w	r0, #1800	@ 0x708
+ 802fd86:	f7f8 f9f5 	bl	8028174 <Consumer_Or_microcontroller_Heartbeat>
+		Heartbeat_Flag_01=0;
+ 802fd8a:	4b06      	ldr	r3, [pc, #24]	@ (802fda4 <MotorCommandsLoop+0x1c8>)
+ 802fd8c:	2200      	movs	r2, #0
+ 802fd8e:	601a      	str	r2, [r3, #0]
+	}
+}
+ 802fd90:	bf00      	nop
+ 802fd92:	3708      	adds	r7, #8
+ 802fd94:	46bd      	mov	sp, r7
+ 802fd96:	bd80      	pop	{r7, pc}
+ 802fd98:	24000128 	.word	0x24000128
+ 802fd9c:	2400a964 	.word	0x2400a964
+ 802fda0:	24000340 	.word	0x24000340
+ 802fda4:	2400a980 	.word	0x2400a980
+ 802fda8:	92492493 	.word	0x92492493
+
+0802fdac <MotorCommandsLoop_2_Position>:
+
+void MotorCommandsLoop_2_Position()
+{
+ 802fdac:	b580      	push	{r7, lr}
+ 802fdae:	b086      	sub	sp, #24
+ 802fdb0:	af04      	add	r7, sp, #16
+	static int Heartbeat_Flag;
+	static int Lag_Sent_Num=0;
+	static int32_t Speed_Last=0;
+	static int32_t Position_Last=0;
+
+	if (TT_Motor_Need_To_Activate_1 == 1)
+ 802fdb2:	4b37      	ldr	r3, [pc, #220]	@ (802fe90 <MotorCommandsLoop_2_Position+0xe4>)
+ 802fdb4:	781b      	ldrb	r3, [r3, #0]
+ 802fdb6:	2b01      	cmp	r3, #1
+ 802fdb8:	d12a      	bne.n	802fe10 <MotorCommandsLoop_2_Position+0x64>
+	{
+		ActivateMotor(3, Roughening_Motor_Controller_CAN2, 6000);
+ 802fdba:	4b36      	ldr	r3, [pc, #216]	@ (802fe94 <MotorCommandsLoop_2_Position+0xe8>)
+ 802fdbc:	681b      	ldr	r3, [r3, #0]
+ 802fdbe:	f241 7270 	movw	r2, #6000	@ 0x1770
+ 802fdc2:	4619      	mov	r1, r3
+ 802fdc4:	2003      	movs	r0, #3
+ 802fdc6:	f7f8 f955 	bl	8028074 <ActivateMotor>
+		ActivateMotor(3, Roughening_Motor_Controller_CAN2, 2000);
+ 802fdca:	4b32      	ldr	r3, [pc, #200]	@ (802fe94 <MotorCommandsLoop_2_Position+0xe8>)
+ 802fdcc:	681b      	ldr	r3, [r3, #0]
+ 802fdce:	f44f 62fa 	mov.w	r2, #2000	@ 0x7d0
+ 802fdd2:	4619      	mov	r1, r3
+ 802fdd4:	2003      	movs	r0, #3
+ 802fdd6:	f7f8 f94d 	bl	8028074 <ActivateMotor>
+		ActivateMotor(3, Roughening_Motor_Controller_CAN2, 2000);
+ 802fdda:	4b2e      	ldr	r3, [pc, #184]	@ (802fe94 <MotorCommandsLoop_2_Position+0xe8>)
+ 802fddc:	681b      	ldr	r3, [r3, #0]
+ 802fdde:	f44f 62fa 	mov.w	r2, #2000	@ 0x7d0
+ 802fde2:	4619      	mov	r1, r3
+ 802fde4:	2003      	movs	r0, #3
+ 802fde6:	f7f8 f945 	bl	8028074 <ActivateMotor>
+
+
+//		void SpeedModeSetup(int32_t MotorID, FDCANHandler *ZQ_Motor_Controller,    int32_t WaitTime, int32_t Acc, int32_t Dec, int32_t TargetVelocity) //设定速度模式，并更改相关速度
+//		SpeedModeSetup(3, Roughening_Motor_Controller_CAN2, 12, 500, 500, 0);
+
+		Postion_Velcocity_Run_SetParameter(                   3,                      0,                    0,             500,             500,  Roughening_Motor_Controller_CAN2,    100   );
+ 802fdea:	4b2a      	ldr	r3, [pc, #168]	@ (802fe94 <MotorCommandsLoop_2_Position+0xe8>)
+ 802fdec:	681b      	ldr	r3, [r3, #0]
+ 802fdee:	2264      	movs	r2, #100	@ 0x64
+ 802fdf0:	9202      	str	r2, [sp, #8]
+ 802fdf2:	9301      	str	r3, [sp, #4]
+ 802fdf4:	f44f 73fa 	mov.w	r3, #500	@ 0x1f4
+ 802fdf8:	9300      	str	r3, [sp, #0]
+ 802fdfa:	f44f 73fa 	mov.w	r3, #500	@ 0x1f4
+ 802fdfe:	2200      	movs	r2, #0
+ 802fe00:	2100      	movs	r1, #0
+ 802fe02:	2003      	movs	r0, #3
+ 802fe04:	f7f8 fa05 	bl	8028212 <Postion_Velcocity_Run_SetParameter>
+//		void Postion_Velcocity_Run_SetParameter(int32_t MotorID, int32_t TargetPosition,  int32_t TargetSpeed, int32_t AccTime, int32_t DecTime, FDCANHandler *ZQ_Motor_Controller, int32_t WaitTime)
+		TT_Motor_Need_To_Activate_1 = 0;
+ 802fe08:	4b21      	ldr	r3, [pc, #132]	@ (802fe90 <MotorCommandsLoop_2_Position+0xe4>)
+ 802fe0a:	2200      	movs	r2, #0
+ 802fe0c:	701a      	strb	r2, [r3, #0]
+//	if(Heartbeat_Flag%5==0)
+//	{
+//		Consumer_Or_microcontroller_Heartbeat(0x709, Roughening_Motor_Controller_CAN2,  4);
+//		Heartbeat_Flag=0;
+//	}
+}
+ 802fe0e:	e03a      	b.n	802fe86 <MotorCommandsLoop_2_Position+0xda>
+		for (int i = 3; i <4 ; i++)//前两个电机
+ 802fe10:	2303      	movs	r3, #3
+ 802fe12:	607b      	str	r3, [r7, #4]
+ 802fe14:	e010      	b.n	802fe38 <MotorCommandsLoop_2_Position+0x8c>
+			TT_Request_Position(3, Roughening_Motor_Controller_CAN2, 10);
+ 802fe16:	4b1f      	ldr	r3, [pc, #124]	@ (802fe94 <MotorCommandsLoop_2_Position+0xe8>)
+ 802fe18:	681b      	ldr	r3, [r3, #0]
+ 802fe1a:	220a      	movs	r2, #10
+ 802fe1c:	4619      	mov	r1, r3
+ 802fe1e:	2003      	movs	r0, #3
+ 802fe20:	f7f8 fb2e 	bl	8028480 <TT_Request_Position>
+			TT_Request_Fault(3, Roughening_Motor_Controller_CAN2, 10);
+ 802fe24:	4b1b      	ldr	r3, [pc, #108]	@ (802fe94 <MotorCommandsLoop_2_Position+0xe8>)
+ 802fe26:	681b      	ldr	r3, [r3, #0]
+ 802fe28:	220a      	movs	r2, #10
+ 802fe2a:	4619      	mov	r1, r3
+ 802fe2c:	2003      	movs	r0, #3
+ 802fe2e:	f7f8 fbd5 	bl	80285dc <TT_Request_Fault>
+		for (int i = 3; i <4 ; i++)//前两个电机
+ 802fe32:	687b      	ldr	r3, [r7, #4]
+ 802fe34:	3301      	adds	r3, #1
+ 802fe36:	607b      	str	r3, [r7, #4]
+ 802fe38:	687b      	ldr	r3, [r7, #4]
+ 802fe3a:	2b03      	cmp	r3, #3
+ 802fe3c:	ddeb      	ble.n	802fe16 <MotorCommandsLoop_2_Position+0x6a>
+		switch(GV.SwingMotor.Position_immediately1_Lag2)
+ 802fe3e:	4b16      	ldr	r3, [pc, #88]	@ (802fe98 <MotorCommandsLoop_2_Position+0xec>)
+ 802fe40:	f8d3 31d4 	ldr.w	r3, [r3, #468]	@ 0x1d4
+ 802fe44:	2b01      	cmp	r3, #1
+ 802fe46:	d002      	beq.n	802fe4e <MotorCommandsLoop_2_Position+0xa2>
+ 802fe48:	2b02      	cmp	r3, #2
+ 802fe4a:	d00e      	beq.n	802fe6a <MotorCommandsLoop_2_Position+0xbe>
+}
+ 802fe4c:	e01b      	b.n	802fe86 <MotorCommandsLoop_2_Position+0xda>
+				Position_Immediately_Setting(3,Roughening_Motor_Controller_CAN2, GV.SwingMotor.Tar_Position_count,GV.SwingMotor.Tar_Position_Velcity_RPM,30);
+ 802fe4e:	4b11      	ldr	r3, [pc, #68]	@ (802fe94 <MotorCommandsLoop_2_Position+0xe8>)
+ 802fe50:	6819      	ldr	r1, [r3, #0]
+ 802fe52:	4b11      	ldr	r3, [pc, #68]	@ (802fe98 <MotorCommandsLoop_2_Position+0xec>)
+ 802fe54:	f8d3 21d8 	ldr.w	r2, [r3, #472]	@ 0x1d8
+ 802fe58:	4b0f      	ldr	r3, [pc, #60]	@ (802fe98 <MotorCommandsLoop_2_Position+0xec>)
+ 802fe5a:	f8d3 31dc 	ldr.w	r3, [r3, #476]	@ 0x1dc
+ 802fe5e:	201e      	movs	r0, #30
+ 802fe60:	9000      	str	r0, [sp, #0]
+ 802fe62:	2003      	movs	r0, #3
+ 802fe64:	f7f8 fb23 	bl	80284ae <Position_Immediately_Setting>
+				break;
+ 802fe68:	e00d      	b.n	802fe86 <MotorCommandsLoop_2_Position+0xda>
+				Position_Lag_Setting(3,Roughening_Motor_Controller_CAN2, GV.SwingMotor.Tar_Position_count,GV.SwingMotor.Tar_Position_Velcity_RPM,30);
+ 802fe6a:	4b0a      	ldr	r3, [pc, #40]	@ (802fe94 <MotorCommandsLoop_2_Position+0xe8>)
+ 802fe6c:	6819      	ldr	r1, [r3, #0]
+ 802fe6e:	4b0a      	ldr	r3, [pc, #40]	@ (802fe98 <MotorCommandsLoop_2_Position+0xec>)
+ 802fe70:	f8d3 21d8 	ldr.w	r2, [r3, #472]	@ 0x1d8
+ 802fe74:	4b08      	ldr	r3, [pc, #32]	@ (802fe98 <MotorCommandsLoop_2_Position+0xec>)
+ 802fe76:	f8d3 31dc 	ldr.w	r3, [r3, #476]	@ 0x1dc
+ 802fe7a:	201e      	movs	r0, #30
+ 802fe7c:	9000      	str	r0, [sp, #0]
+ 802fe7e:	2003      	movs	r0, #3
+ 802fe80:	f7f8 fb55 	bl	802852e <Position_Lag_Setting>
+				break;
+ 802fe84:	bf00      	nop
+}
+ 802fe86:	bf00      	nop
+ 802fe88:	3708      	adds	r7, #8
+ 802fe8a:	46bd      	mov	sp, r7
+ 802fe8c:	bd80      	pop	{r7, pc}
+ 802fe8e:	bf00      	nop
+ 802fe90:	24000129 	.word	0x24000129
+ 802fe94:	2400a968 	.word	0x2400a968
+ 802fe98:	24000340 	.word	0x24000340
+
+0802fe9c <Roughening_MotorDecodeCAN>:
+
+
+
+char a[10];
+void Roughening_MotorDecodeCAN(uint32_t canID, uint8_t *buffer, uint32_t length)
+{
+ 802fe9c:	b580      	push	{r7, lr}
+ 802fe9e:	b084      	sub	sp, #16
+ 802fea0:	af00      	add	r7, sp, #0
+ 802fea2:	60f8      	str	r0, [r7, #12]
+ 802fea4:	60b9      	str	r1, [r7, #8]
+ 802fea6:	607a      	str	r2, [r7, #4]
+
+	memcpy(a,buffer,8);
+ 802fea8:	2208      	movs	r2, #8
+ 802feaa:	68b9      	ldr	r1, [r7, #8]
+ 802feac:	481c      	ldr	r0, [pc, #112]	@ (802ff20 <Roughening_MotorDecodeCAN+0x84>)
+ 802feae:	f010 fa85 	bl	80403bc <memcpy>
+	switch (canID - 0x580)
+ 802feb2:	68fb      	ldr	r3, [r7, #12]
+ 802feb4:	f5a3 63b0 	sub.w	r3, r3, #1408	@ 0x580
+ 802feb8:	2b03      	cmp	r3, #3
+ 802feba:	d020      	beq.n	802fefe <Roughening_MotorDecodeCAN+0x62>
+ 802febc:	2b03      	cmp	r3, #3
+ 802febe:	d82b      	bhi.n	802ff18 <Roughening_MotorDecodeCAN+0x7c>
+ 802fec0:	2b01      	cmp	r3, #1
+ 802fec2:	d002      	beq.n	802feca <Roughening_MotorDecodeCAN+0x2e>
+ 802fec4:	2b02      	cmp	r3, #2
+ 802fec6:	d00d      	beq.n	802fee4 <Roughening_MotorDecodeCAN+0x48>
+			break;
+
+
+	}
+
+}
+ 802fec8:	e026      	b.n	802ff18 <Roughening_MotorDecodeCAN+0x7c>
+			HardWareErrorController->Set_PCOMHardWare(HardWareErrorController,"ZQ_CAN_ID1_LeftMotor", 1);
+ 802feca:	4b16      	ldr	r3, [pc, #88]	@ (802ff24 <Roughening_MotorDecodeCAN+0x88>)
+ 802fecc:	681b      	ldr	r3, [r3, #0]
+ 802fece:	695b      	ldr	r3, [r3, #20]
+ 802fed0:	4a14      	ldr	r2, [pc, #80]	@ (802ff24 <Roughening_MotorDecodeCAN+0x88>)
+ 802fed2:	6810      	ldr	r0, [r2, #0]
+ 802fed4:	2201      	movs	r2, #1
+ 802fed6:	4914      	ldr	r1, [pc, #80]	@ (802ff28 <Roughening_MotorDecodeCAN+0x8c>)
+ 802fed8:	4798      	blx	r3
+			TT_Analytic_Fun(1, buffer);
+ 802feda:	68b9      	ldr	r1, [r7, #8]
+ 802fedc:	2001      	movs	r0, #1
+ 802fede:	f7f8 fbab 	bl	8028638 <TT_Analytic_Fun>
+			break;
+ 802fee2:	e019      	b.n	802ff18 <Roughening_MotorDecodeCAN+0x7c>
+			HardWareErrorController->Set_PCOMHardWare(HardWareErrorController,"ZQ_CAN_ID2_RightMotor", 1);
+ 802fee4:	4b0f      	ldr	r3, [pc, #60]	@ (802ff24 <Roughening_MotorDecodeCAN+0x88>)
+ 802fee6:	681b      	ldr	r3, [r3, #0]
+ 802fee8:	695b      	ldr	r3, [r3, #20]
+ 802feea:	4a0e      	ldr	r2, [pc, #56]	@ (802ff24 <Roughening_MotorDecodeCAN+0x88>)
+ 802feec:	6810      	ldr	r0, [r2, #0]
+ 802feee:	2201      	movs	r2, #1
+ 802fef0:	490e      	ldr	r1, [pc, #56]	@ (802ff2c <Roughening_MotorDecodeCAN+0x90>)
+ 802fef2:	4798      	blx	r3
+			TT_Analytic_Fun(2, buffer);
+ 802fef4:	68b9      	ldr	r1, [r7, #8]
+ 802fef6:	2002      	movs	r0, #2
+ 802fef8:	f7f8 fb9e 	bl	8028638 <TT_Analytic_Fun>
+			break;
+ 802fefc:	e00c      	b.n	802ff18 <Roughening_MotorDecodeCAN+0x7c>
+			HardWareErrorController->Set_PCOMHardWare(HardWareErrorController, "ZQ_CAN_ID3_SwingMotor", 1);
+ 802fefe:	4b09      	ldr	r3, [pc, #36]	@ (802ff24 <Roughening_MotorDecodeCAN+0x88>)
+ 802ff00:	681b      	ldr	r3, [r3, #0]
+ 802ff02:	695b      	ldr	r3, [r3, #20]
+ 802ff04:	4a07      	ldr	r2, [pc, #28]	@ (802ff24 <Roughening_MotorDecodeCAN+0x88>)
+ 802ff06:	6810      	ldr	r0, [r2, #0]
+ 802ff08:	2201      	movs	r2, #1
+ 802ff0a:	4909      	ldr	r1, [pc, #36]	@ (802ff30 <Roughening_MotorDecodeCAN+0x94>)
+ 802ff0c:	4798      	blx	r3
+			TT_Analytic_Fun(3, buffer);
+ 802ff0e:	68b9      	ldr	r1, [r7, #8]
+ 802ff10:	2003      	movs	r0, #3
+ 802ff12:	f7f8 fb91 	bl	8028638 <TT_Analytic_Fun>
+			break;
+ 802ff16:	bf00      	nop
+}
+ 802ff18:	bf00      	nop
+ 802ff1a:	3710      	adds	r7, #16
+ 802ff1c:	46bd      	mov	sp, r7
+ 802ff1e:	bd80      	pop	{r7, pc}
+ 802ff20:	2400a974 	.word	0x2400a974
+ 802ff24:	24000618 	.word	0x24000618
+ 802ff28:	08041518 	.word	0x08041518
+ 802ff2c:	08041530 	.word	0x08041530
+ 802ff30:	08041548 	.word	0x08041548
+
+0802ff34 <MX_QUADSPI_Init>:
+
+QSPI_HandleTypeDef hqspi;
+
+/* QUADSPI init function */
+void MX_QUADSPI_Init(void)
+{
+ 802ff34:	b580      	push	{r7, lr}
+ 802ff36:	af00      	add	r7, sp, #0
+  /* USER CODE END QUADSPI_Init 0 */
+
+  /* USER CODE BEGIN QUADSPI_Init 1 */
+
+  /* USER CODE END QUADSPI_Init 1 */
+  hqspi.Instance = QUADSPI;
+ 802ff38:	4b12      	ldr	r3, [pc, #72]	@ (802ff84 <MX_QUADSPI_Init+0x50>)
+ 802ff3a:	4a13      	ldr	r2, [pc, #76]	@ (802ff88 <MX_QUADSPI_Init+0x54>)
+ 802ff3c:	601a      	str	r2, [r3, #0]
+  hqspi.Init.ClockPrescaler = 2-1;
+ 802ff3e:	4b11      	ldr	r3, [pc, #68]	@ (802ff84 <MX_QUADSPI_Init+0x50>)
+ 802ff40:	2201      	movs	r2, #1
+ 802ff42:	605a      	str	r2, [r3, #4]
+  hqspi.Init.FifoThreshold = 32;
+ 802ff44:	4b0f      	ldr	r3, [pc, #60]	@ (802ff84 <MX_QUADSPI_Init+0x50>)
+ 802ff46:	2220      	movs	r2, #32
+ 802ff48:	609a      	str	r2, [r3, #8]
+  hqspi.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE;
+ 802ff4a:	4b0e      	ldr	r3, [pc, #56]	@ (802ff84 <MX_QUADSPI_Init+0x50>)
+ 802ff4c:	2210      	movs	r2, #16
+ 802ff4e:	60da      	str	r2, [r3, #12]
+  hqspi.Init.FlashSize = 23+1;
+ 802ff50:	4b0c      	ldr	r3, [pc, #48]	@ (802ff84 <MX_QUADSPI_Init+0x50>)
+ 802ff52:	2218      	movs	r2, #24
+ 802ff54:	611a      	str	r2, [r3, #16]
+  hqspi.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_5_CYCLE;
+ 802ff56:	4b0b      	ldr	r3, [pc, #44]	@ (802ff84 <MX_QUADSPI_Init+0x50>)
+ 802ff58:	f44f 6280 	mov.w	r2, #1024	@ 0x400
+ 802ff5c:	615a      	str	r2, [r3, #20]
+  hqspi.Init.ClockMode = QSPI_CLOCK_MODE_3;
+ 802ff5e:	4b09      	ldr	r3, [pc, #36]	@ (802ff84 <MX_QUADSPI_Init+0x50>)
+ 802ff60:	2201      	movs	r2, #1
+ 802ff62:	619a      	str	r2, [r3, #24]
+  hqspi.Init.FlashID = QSPI_FLASH_ID_2;
+ 802ff64:	4b07      	ldr	r3, [pc, #28]	@ (802ff84 <MX_QUADSPI_Init+0x50>)
+ 802ff66:	2280      	movs	r2, #128	@ 0x80
+ 802ff68:	61da      	str	r2, [r3, #28]
+  hqspi.Init.DualFlash = QSPI_DUALFLASH_DISABLE;
+ 802ff6a:	4b06      	ldr	r3, [pc, #24]	@ (802ff84 <MX_QUADSPI_Init+0x50>)
+ 802ff6c:	2200      	movs	r2, #0
+ 802ff6e:	621a      	str	r2, [r3, #32]
+  if (HAL_QSPI_Init(&hqspi) != HAL_OK)
+ 802ff70:	4804      	ldr	r0, [pc, #16]	@ (802ff84 <MX_QUADSPI_Init+0x50>)
+ 802ff72:	f008 fd7f 	bl	8038a74 <HAL_QSPI_Init>
+ 802ff76:	4603      	mov	r3, r0
+ 802ff78:	2b00      	cmp	r3, #0
+ 802ff7a:	d001      	beq.n	802ff80 <MX_QUADSPI_Init+0x4c>
+  {
+    Error_Handler();
+ 802ff7c:	f7ff fd84 	bl	802fa88 <Error_Handler>
+  }
+  /* USER CODE BEGIN QUADSPI_Init 2 */
+
+  /* USER CODE END QUADSPI_Init 2 */
+
+}
+ 802ff80:	bf00      	nop
+ 802ff82:	bd80      	pop	{r7, pc}
+ 802ff84:	2400a984 	.word	0x2400a984
+ 802ff88:	52005000 	.word	0x52005000
+
+0802ff8c <HAL_QSPI_MspInit>:
+
+void HAL_QSPI_MspInit(QSPI_HandleTypeDef* qspiHandle)
+{
+ 802ff8c:	b580      	push	{r7, lr}
+ 802ff8e:	b0bc      	sub	sp, #240	@ 0xf0
+ 802ff90:	af00      	add	r7, sp, #0
+ 802ff92:	6078      	str	r0, [r7, #4]
+
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+ 802ff94:	f107 03dc 	add.w	r3, r7, #220	@ 0xdc
+ 802ff98:	2200      	movs	r2, #0
+ 802ff9a:	601a      	str	r2, [r3, #0]
+ 802ff9c:	605a      	str	r2, [r3, #4]
+ 802ff9e:	609a      	str	r2, [r3, #8]
+ 802ffa0:	60da      	str	r2, [r3, #12]
+ 802ffa2:	611a      	str	r2, [r3, #16]
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+ 802ffa4:	f107 0318 	add.w	r3, r7, #24
+ 802ffa8:	22c0      	movs	r2, #192	@ 0xc0
+ 802ffaa:	2100      	movs	r1, #0
+ 802ffac:	4618      	mov	r0, r3
+ 802ffae:	f010 f99b 	bl	80402e8 <memset>
+  if(qspiHandle->Instance==QUADSPI)
+ 802ffb2:	687b      	ldr	r3, [r7, #4]
+ 802ffb4:	681b      	ldr	r3, [r3, #0]
+ 802ffb6:	4a4f      	ldr	r2, [pc, #316]	@ (80300f4 <HAL_QSPI_MspInit+0x168>)
+ 802ffb8:	4293      	cmp	r3, r2
+ 802ffba:	f040 8097 	bne.w	80300ec <HAL_QSPI_MspInit+0x160>
+
+  /* USER CODE END QUADSPI_MspInit 0 */
+
+  /** Initializes the peripherals clock
+  */
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_QSPI;
+ 802ffbe:	f04f 7200 	mov.w	r2, #33554432	@ 0x2000000
+ 802ffc2:	f04f 0300 	mov.w	r3, #0
+ 802ffc6:	e9c7 2306 	strd	r2, r3, [r7, #24]
+    PeriphClkInitStruct.QspiClockSelection = RCC_QSPICLKSOURCE_D1HCLK;
+ 802ffca:	2300      	movs	r3, #0
+ 802ffcc:	667b      	str	r3, [r7, #100]	@ 0x64
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+ 802ffce:	f107 0318 	add.w	r3, r7, #24
+ 802ffd2:	4618      	mov	r0, r3
+ 802ffd4:	f00a f856 	bl	803a084 <HAL_RCCEx_PeriphCLKConfig>
+ 802ffd8:	4603      	mov	r3, r0
+ 802ffda:	2b00      	cmp	r3, #0
+ 802ffdc:	d001      	beq.n	802ffe2 <HAL_QSPI_MspInit+0x56>
+    {
+      Error_Handler();
+ 802ffde:	f7ff fd53 	bl	802fa88 <Error_Handler>
+    }
+
+    /* QUADSPI clock enable */
+    __HAL_RCC_QSPI_CLK_ENABLE();
+ 802ffe2:	4b45      	ldr	r3, [pc, #276]	@ (80300f8 <HAL_QSPI_MspInit+0x16c>)
+ 802ffe4:	f8d3 30d4 	ldr.w	r3, [r3, #212]	@ 0xd4
+ 802ffe8:	4a43      	ldr	r2, [pc, #268]	@ (80300f8 <HAL_QSPI_MspInit+0x16c>)
+ 802ffea:	f443 4380 	orr.w	r3, r3, #16384	@ 0x4000
+ 802ffee:	f8c2 30d4 	str.w	r3, [r2, #212]	@ 0xd4
+ 802fff2:	4b41      	ldr	r3, [pc, #260]	@ (80300f8 <HAL_QSPI_MspInit+0x16c>)
+ 802fff4:	f8d3 30d4 	ldr.w	r3, [r3, #212]	@ 0xd4
+ 802fff8:	f403 4380 	and.w	r3, r3, #16384	@ 0x4000
+ 802fffc:	617b      	str	r3, [r7, #20]
+ 802fffe:	697b      	ldr	r3, [r7, #20]
+
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+ 8030000:	4b3d      	ldr	r3, [pc, #244]	@ (80300f8 <HAL_QSPI_MspInit+0x16c>)
+ 8030002:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
+ 8030006:	4a3c      	ldr	r2, [pc, #240]	@ (80300f8 <HAL_QSPI_MspInit+0x16c>)
+ 8030008:	f043 0302 	orr.w	r3, r3, #2
+ 803000c:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
+ 8030010:	4b39      	ldr	r3, [pc, #228]	@ (80300f8 <HAL_QSPI_MspInit+0x16c>)
+ 8030012:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
+ 8030016:	f003 0302 	and.w	r3, r3, #2
+ 803001a:	613b      	str	r3, [r7, #16]
+ 803001c:	693b      	ldr	r3, [r7, #16]
+    __HAL_RCC_GPIOE_CLK_ENABLE();
+ 803001e:	4b36      	ldr	r3, [pc, #216]	@ (80300f8 <HAL_QSPI_MspInit+0x16c>)
+ 8030020:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
+ 8030024:	4a34      	ldr	r2, [pc, #208]	@ (80300f8 <HAL_QSPI_MspInit+0x16c>)
+ 8030026:	f043 0310 	orr.w	r3, r3, #16
+ 803002a:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
+ 803002e:	4b32      	ldr	r3, [pc, #200]	@ (80300f8 <HAL_QSPI_MspInit+0x16c>)
+ 8030030:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
+ 8030034:	f003 0310 	and.w	r3, r3, #16
+ 8030038:	60fb      	str	r3, [r7, #12]
+ 803003a:	68fb      	ldr	r3, [r7, #12]
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+ 803003c:	4b2e      	ldr	r3, [pc, #184]	@ (80300f8 <HAL_QSPI_MspInit+0x16c>)
+ 803003e:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
+ 8030042:	4a2d      	ldr	r2, [pc, #180]	@ (80300f8 <HAL_QSPI_MspInit+0x16c>)
+ 8030044:	f043 0304 	orr.w	r3, r3, #4
+ 8030048:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
+ 803004c:	4b2a      	ldr	r3, [pc, #168]	@ (80300f8 <HAL_QSPI_MspInit+0x16c>)
+ 803004e:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
+ 8030052:	f003 0304 	and.w	r3, r3, #4
+ 8030056:	60bb      	str	r3, [r7, #8]
+ 8030058:	68bb      	ldr	r3, [r7, #8]
+    PE8     ------> QUADSPI_BK2_IO1
+    PE9     ------> QUADSPI_BK2_IO2
+    PE10     ------> QUADSPI_BK2_IO3
+    PC11     ------> QUADSPI_BK2_NCS
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_2;
+ 803005a:	2304      	movs	r3, #4
+ 803005c:	f8c7 30dc 	str.w	r3, [r7, #220]	@ 0xdc
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 8030060:	2302      	movs	r3, #2
+ 8030062:	f8c7 30e0 	str.w	r3, [r7, #224]	@ 0xe0
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 8030066:	2300      	movs	r3, #0
+ 8030068:	f8c7 30e4 	str.w	r3, [r7, #228]	@ 0xe4
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ 803006c:	2303      	movs	r3, #3
+ 803006e:	f8c7 30e8 	str.w	r3, [r7, #232]	@ 0xe8
+    GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI;
+ 8030072:	2309      	movs	r3, #9
+ 8030074:	f8c7 30ec 	str.w	r3, [r7, #236]	@ 0xec
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+ 8030078:	f107 03dc 	add.w	r3, r7, #220	@ 0xdc
+ 803007c:	4619      	mov	r1, r3
+ 803007e:	481f      	ldr	r0, [pc, #124]	@ (80300fc <HAL_QSPI_MspInit+0x170>)
+ 8030080:	f007 faac 	bl	80375dc <HAL_GPIO_Init>
+
+    GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10;
+ 8030084:	f44f 63f0 	mov.w	r3, #1920	@ 0x780
+ 8030088:	f8c7 30dc 	str.w	r3, [r7, #220]	@ 0xdc
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 803008c:	2302      	movs	r3, #2
+ 803008e:	f8c7 30e0 	str.w	r3, [r7, #224]	@ 0xe0
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 8030092:	2300      	movs	r3, #0
+ 8030094:	f8c7 30e4 	str.w	r3, [r7, #228]	@ 0xe4
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ 8030098:	2303      	movs	r3, #3
+ 803009a:	f8c7 30e8 	str.w	r3, [r7, #232]	@ 0xe8
+    GPIO_InitStruct.Alternate = GPIO_AF10_QUADSPI;
+ 803009e:	230a      	movs	r3, #10
+ 80300a0:	f8c7 30ec 	str.w	r3, [r7, #236]	@ 0xec
+    HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
+ 80300a4:	f107 03dc 	add.w	r3, r7, #220	@ 0xdc
+ 80300a8:	4619      	mov	r1, r3
+ 80300aa:	4815      	ldr	r0, [pc, #84]	@ (8030100 <HAL_QSPI_MspInit+0x174>)
+ 80300ac:	f007 fa96 	bl	80375dc <HAL_GPIO_Init>
+
+    GPIO_InitStruct.Pin = GPIO_PIN_11;
+ 80300b0:	f44f 6300 	mov.w	r3, #2048	@ 0x800
+ 80300b4:	f8c7 30dc 	str.w	r3, [r7, #220]	@ 0xdc
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 80300b8:	2302      	movs	r3, #2
+ 80300ba:	f8c7 30e0 	str.w	r3, [r7, #224]	@ 0xe0
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 80300be:	2300      	movs	r3, #0
+ 80300c0:	f8c7 30e4 	str.w	r3, [r7, #228]	@ 0xe4
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ 80300c4:	2303      	movs	r3, #3
+ 80300c6:	f8c7 30e8 	str.w	r3, [r7, #232]	@ 0xe8
+    GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI;
+ 80300ca:	2309      	movs	r3, #9
+ 80300cc:	f8c7 30ec 	str.w	r3, [r7, #236]	@ 0xec
+    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+ 80300d0:	f107 03dc 	add.w	r3, r7, #220	@ 0xdc
+ 80300d4:	4619      	mov	r1, r3
+ 80300d6:	480b      	ldr	r0, [pc, #44]	@ (8030104 <HAL_QSPI_MspInit+0x178>)
+ 80300d8:	f007 fa80 	bl	80375dc <HAL_GPIO_Init>
+
+    /* QUADSPI interrupt Init */
+    HAL_NVIC_SetPriority(QUADSPI_IRQn, 0, 0);
+ 80300dc:	2200      	movs	r2, #0
+ 80300de:	2100      	movs	r1, #0
+ 80300e0:	205c      	movs	r0, #92	@ 0x5c
+ 80300e2:	f002 fce6 	bl	8032ab2 <HAL_NVIC_SetPriority>
+    HAL_NVIC_EnableIRQ(QUADSPI_IRQn);
+ 80300e6:	205c      	movs	r0, #92	@ 0x5c
+ 80300e8:	f002 fcfd 	bl	8032ae6 <HAL_NVIC_EnableIRQ>
+  /* USER CODE BEGIN QUADSPI_MspInit 1 */
+
+  /* USER CODE END QUADSPI_MspInit 1 */
+  }
+}
+ 80300ec:	bf00      	nop
+ 80300ee:	37f0      	adds	r7, #240	@ 0xf0
+ 80300f0:	46bd      	mov	sp, r7
+ 80300f2:	bd80      	pop	{r7, pc}
+ 80300f4:	52005000 	.word	0x52005000
+ 80300f8:	58024400 	.word	0x58024400
+ 80300fc:	58020400 	.word	0x58020400
+ 8030100:	58021000 	.word	0x58021000
+ 8030104:	58020800 	.word	0x58020800
+
+08030108 <Move_PushRod_Halt_Func_Do>:
+
+void Move_Forwards_Do(int32_t Target_Angle);
+void Move_Backwards_Do(int32_t Target_Angle);
+
+void Move_PushRod_Halt_Func_Do(void)
+{
+ 8030108:	b580      	push	{r7, lr}
+ 803010a:	af00      	add	r7, sp, #0
+	GF_BSP_GPIO_SetIO(Lifting_IO_CTL_0, 1);
+ 803010c:	2101      	movs	r1, #1
+ 803010e:	2002      	movs	r0, #2
+ 8030110:	f7f1 f880 	bl	8021214 <GF_BSP_GPIO_SetIO>
+	GF_BSP_GPIO_SetIO(3, 1);
+ 8030114:	2101      	movs	r1, #1
+ 8030116:	2003      	movs	r0, #3
+ 8030118:	f7f1 f87c 	bl	8021214 <GF_BSP_GPIO_SetIO>
+}
+ 803011c:	bf00      	nop
+ 803011e:	bd80      	pop	{r7, pc}
+
+08030120 <Move_PushRod_Up_Func_Do>:
+void Move_PushRod_Up_Func_Do(void)
+{
+ 8030120:	b580      	push	{r7, lr}
+ 8030122:	af00      	add	r7, sp, #0
+	GF_BSP_GPIO_SetIO(Lifting_IO_CTL_0, 0);
+ 8030124:	2100      	movs	r1, #0
+ 8030126:	2002      	movs	r0, #2
+ 8030128:	f7f1 f874 	bl	8021214 <GF_BSP_GPIO_SetIO>
+	GF_BSP_GPIO_SetIO(3, 1);
+ 803012c:	2101      	movs	r1, #1
+ 803012e:	2003      	movs	r0, #3
+ 8030130:	f7f1 f870 	bl	8021214 <GF_BSP_GPIO_SetIO>
+
+}
+ 8030134:	bf00      	nop
+ 8030136:	bd80      	pop	{r7, pc}
+
+08030138 <Move_PushRod_Down_Func_Do>:
+void Move_PushRod_Down_Func_Do(void)
+{
+ 8030138:	b580      	push	{r7, lr}
+ 803013a:	af00      	add	r7, sp, #0
+	GF_BSP_GPIO_SetIO(Lifting_IO_CTL_0, 1);
+ 803013c:	2101      	movs	r1, #1
+ 803013e:	2002      	movs	r0, #2
+ 8030140:	f7f1 f868 	bl	8021214 <GF_BSP_GPIO_SetIO>
+	GF_BSP_GPIO_SetIO(3, 0);
+ 8030144:	2100      	movs	r1, #0
+ 8030146:	2003      	movs	r0, #3
+ 8030148:	f7f1 f864 	bl	8021214 <GF_BSP_GPIO_SetIO>
+}
+ 803014c:	bf00      	nop
+ 803014e:	bd80      	pop	{r7, pc}
+
+08030150 <Move_PushRod_Halt_Func_Do_1>:
+
+void Move_PushRod_Halt_Func_Do_1(void)
+{
+ 8030150:	b580      	push	{r7, lr}
+ 8030152:	af00      	add	r7, sp, #0
+	GF_BSP_GPIO_SetIO(4, 1);
+ 8030154:	2101      	movs	r1, #1
+ 8030156:	2004      	movs	r0, #4
+ 8030158:	f7f1 f85c 	bl	8021214 <GF_BSP_GPIO_SetIO>
+	GF_BSP_GPIO_SetIO(5, 1);
+ 803015c:	2101      	movs	r1, #1
+ 803015e:	2005      	movs	r0, #5
+ 8030160:	f7f1 f858 	bl	8021214 <GF_BSP_GPIO_SetIO>
+}
+ 8030164:	bf00      	nop
+ 8030166:	bd80      	pop	{r7, pc}
+
+08030168 <HALT_State_Do>:
+}
+
+
+
+void HALT_State_Do(void)
+{
+ 8030168:	b480      	push	{r7}
+ 803016a:	af00      	add	r7, sp, #0
+	GV.LeftMotor.Target_Velcity = 0;
+ 803016c:	4b05      	ldr	r3, [pc, #20]	@ (8030184 <HALT_State_Do+0x1c>)
+ 803016e:	2200      	movs	r2, #0
+ 8030170:	679a      	str	r2, [r3, #120]	@ 0x78
+	GV.RightMotor.Target_Velcity = 0;
+ 8030172:	4b04      	ldr	r3, [pc, #16]	@ (8030184 <HALT_State_Do+0x1c>)
+ 8030174:	2200      	movs	r2, #0
+ 8030176:	f8c3 20f8 	str.w	r2, [r3, #248]	@ 0xf8
+}
+ 803017a:	bf00      	nop
+ 803017c:	46bd      	mov	sp, r7
+ 803017e:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8030182:	4770      	bx	lr
+ 8030184:	24000340 	.word	0x24000340
+
+08030188 <HAL_MspInit>:
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+ 8030188:	b480      	push	{r7}
+ 803018a:	b083      	sub	sp, #12
+ 803018c:	af00      	add	r7, sp, #0
+
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
+ 803018e:	4b0a      	ldr	r3, [pc, #40]	@ (80301b8 <HAL_MspInit+0x30>)
+ 8030190:	f8d3 30f4 	ldr.w	r3, [r3, #244]	@ 0xf4
+ 8030194:	4a08      	ldr	r2, [pc, #32]	@ (80301b8 <HAL_MspInit+0x30>)
+ 8030196:	f043 0302 	orr.w	r3, r3, #2
+ 803019a:	f8c2 30f4 	str.w	r3, [r2, #244]	@ 0xf4
+ 803019e:	4b06      	ldr	r3, [pc, #24]	@ (80301b8 <HAL_MspInit+0x30>)
+ 80301a0:	f8d3 30f4 	ldr.w	r3, [r3, #244]	@ 0xf4
+ 80301a4:	f003 0302 	and.w	r3, r3, #2
+ 80301a8:	607b      	str	r3, [r7, #4]
+ 80301aa:	687b      	ldr	r3, [r7, #4]
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+ 80301ac:	bf00      	nop
+ 80301ae:	370c      	adds	r7, #12
+ 80301b0:	46bd      	mov	sp, r7
+ 80301b2:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80301b6:	4770      	bx	lr
+ 80301b8:	58024400 	.word	0x58024400
+
+080301bc <NMI_Handler>:
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+ 80301bc:	b580      	push	{r7, lr}
+ 80301be:	af00      	add	r7, sp, #0
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  HAL_RCC_NMI_IRQHandler();
+ 80301c0:	f009 ff44 	bl	803a04c <HAL_RCC_NMI_IRQHandler>
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+  while (1)
+ 80301c4:	bf00      	nop
+ 80301c6:	e7fd      	b.n	80301c4 <NMI_Handler+0x8>
+
+080301c8 <HardFault_Handler>:
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+ 80301c8:	b480      	push	{r7}
+ 80301ca:	af00      	add	r7, sp, #0
+
+
+
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+ 80301cc:	bf00      	nop
+ 80301ce:	e7fd      	b.n	80301cc <HardFault_Handler+0x4>
+
+080301d0 <MemManage_Handler>:
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+ 80301d0:	b480      	push	{r7}
+ 80301d2:	af00      	add	r7, sp, #0
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+ 80301d4:	bf00      	nop
+ 80301d6:	e7fd      	b.n	80301d4 <MemManage_Handler+0x4>
+
+080301d8 <BusFault_Handler>:
+
+/**
+  * @brief This function handles Pre-fetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+ 80301d8:	b480      	push	{r7}
+ 80301da:	af00      	add	r7, sp, #0
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+ 80301dc:	bf00      	nop
+ 80301de:	e7fd      	b.n	80301dc <BusFault_Handler+0x4>
+
+080301e0 <UsageFault_Handler>:
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+ 80301e0:	b480      	push	{r7}
+ 80301e2:	af00      	add	r7, sp, #0
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+ 80301e4:	bf00      	nop
+ 80301e6:	e7fd      	b.n	80301e4 <UsageFault_Handler+0x4>
+
+080301e8 <SVC_Handler>:
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+ 80301e8:	b480      	push	{r7}
+ 80301ea:	af00      	add	r7, sp, #0
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+ 80301ec:	bf00      	nop
+ 80301ee:	46bd      	mov	sp, r7
+ 80301f0:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80301f4:	4770      	bx	lr
+
+080301f6 <DebugMon_Handler>:
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+ 80301f6:	b480      	push	{r7}
+ 80301f8:	af00      	add	r7, sp, #0
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+ 80301fa:	bf00      	nop
+ 80301fc:	46bd      	mov	sp, r7
+ 80301fe:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8030202:	4770      	bx	lr
+
+08030204 <PendSV_Handler>:
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+ 8030204:	b480      	push	{r7}
+ 8030206:	af00      	add	r7, sp, #0
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+ 8030208:	bf00      	nop
+ 803020a:	46bd      	mov	sp, r7
+ 803020c:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8030210:	4770      	bx	lr
+
+08030212 <SysTick_Handler>:
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+ 8030212:	b580      	push	{r7, lr}
+ 8030214:	af00      	add	r7, sp, #0
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+ 8030216:	f001 fb77 	bl	8031908 <HAL_IncTick>
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+ 803021a:	bf00      	nop
+ 803021c:	bd80      	pop	{r7, pc}
+	...
+
+08030220 <DMA1_Stream0_IRQHandler>:
+
+/**
+  * @brief This function handles DMA1 stream0 global interrupt.
+  */
+void DMA1_Stream0_IRQHandler(void)
+{
+ 8030220:	b580      	push	{r7, lr}
+ 8030222:	af00      	add	r7, sp, #0
+  /* USER CODE BEGIN DMA1_Stream0_IRQn 0 */
+
+  /* USER CODE END DMA1_Stream0_IRQn 0 */
+  HAL_DMA_IRQHandler(&hdma_uart4_tx);
+ 8030224:	4802      	ldr	r0, [pc, #8]	@ (8030230 <DMA1_Stream0_IRQHandler+0x10>)
+ 8030226:	f004 f81b 	bl	8034260 <HAL_DMA_IRQHandler>
+  /* USER CODE BEGIN DMA1_Stream0_IRQn 1 */
+
+  /* USER CODE END DMA1_Stream0_IRQn 1 */
+}
+ 803022a:	bf00      	nop
+ 803022c:	bd80      	pop	{r7, pc}
+ 803022e:	bf00      	nop
+ 8030230:	2400af30 	.word	0x2400af30
+
+08030234 <DMA1_Stream1_IRQHandler>:
+
+/**
+  * @brief This function handles DMA1 stream1 global interrupt.
+  */
+void DMA1_Stream1_IRQHandler(void)
+{
+ 8030234:	b580      	push	{r7, lr}
+ 8030236:	af00      	add	r7, sp, #0
+  /* USER CODE BEGIN DMA1_Stream1_IRQn 0 */
+
+  /* USER CODE END DMA1_Stream1_IRQn 0 */
+  HAL_DMA_IRQHandler(&hdma_uart7_tx);
+ 8030238:	4802      	ldr	r0, [pc, #8]	@ (8030244 <DMA1_Stream1_IRQHandler+0x10>)
+ 803023a:	f004 f811 	bl	8034260 <HAL_DMA_IRQHandler>
+  /* USER CODE BEGIN DMA1_Stream1_IRQn 1 */
+
+  /* USER CODE END DMA1_Stream1_IRQn 1 */
+}
+ 803023e:	bf00      	nop
+ 8030240:	bd80      	pop	{r7, pc}
+ 8030242:	bf00      	nop
+ 8030244:	2400b020 	.word	0x2400b020
+
+08030248 <DMA1_Stream2_IRQHandler>:
+
+/**
+  * @brief This function handles DMA1 stream2 global interrupt.
+  */
+void DMA1_Stream2_IRQHandler(void)
+{
+ 8030248:	b580      	push	{r7, lr}
+ 803024a:	af00      	add	r7, sp, #0
+  /* USER CODE BEGIN DMA1_Stream2_IRQn 0 */
+
+  /* USER CODE END DMA1_Stream2_IRQn 0 */
+  HAL_DMA_IRQHandler(&hdma_usart1_tx);
+ 803024c:	4802      	ldr	r0, [pc, #8]	@ (8030258 <DMA1_Stream2_IRQHandler+0x10>)
+ 803024e:	f004 f807 	bl	8034260 <HAL_DMA_IRQHandler>
+  /* USER CODE BEGIN DMA1_Stream2_IRQn 1 */
+
+  /* USER CODE END DMA1_Stream2_IRQn 1 */
+}
+ 8030252:	bf00      	nop
+ 8030254:	bd80      	pop	{r7, pc}
+ 8030256:	bf00      	nop
+ 8030258:	2400b098 	.word	0x2400b098
+
+0803025c <DMA1_Stream3_IRQHandler>:
+
+/**
+  * @brief This function handles DMA1 stream3 global interrupt.
+  */
+void DMA1_Stream3_IRQHandler(void)
+{
+ 803025c:	b580      	push	{r7, lr}
+ 803025e:	af00      	add	r7, sp, #0
+  /* USER CODE BEGIN DMA1_Stream3_IRQn 0 */
+
+  /* USER CODE END DMA1_Stream3_IRQn 0 */
+  HAL_DMA_IRQHandler(&hdma_uart5_tx);
+ 8030260:	4802      	ldr	r0, [pc, #8]	@ (803026c <DMA1_Stream3_IRQHandler+0x10>)
+ 8030262:	f003 fffd 	bl	8034260 <HAL_DMA_IRQHandler>
+  /* USER CODE BEGIN DMA1_Stream3_IRQn 1 */
+
+  /* USER CODE END DMA1_Stream3_IRQn 1 */
+}
+ 8030266:	bf00      	nop
+ 8030268:	bd80      	pop	{r7, pc}
+ 803026a:	bf00      	nop
+ 803026c:	2400afa8 	.word	0x2400afa8
+
+08030270 <DMA1_Stream5_IRQHandler>:
+
+/**
+  * @brief This function handles DMA1 stream5 global interrupt.
+  */
+void DMA1_Stream5_IRQHandler(void)
+{
+ 8030270:	b580      	push	{r7, lr}
+ 8030272:	af00      	add	r7, sp, #0
+  /* USER CODE BEGIN DMA1_Stream5_IRQn 0 */
+
+  /* USER CODE END DMA1_Stream5_IRQn 0 */
+  HAL_DMA_IRQHandler(&hdma_usart2_tx);
+ 8030274:	4802      	ldr	r0, [pc, #8]	@ (8030280 <DMA1_Stream5_IRQHandler+0x10>)
+ 8030276:	f003 fff3 	bl	8034260 <HAL_DMA_IRQHandler>
+  /* USER CODE BEGIN DMA1_Stream5_IRQn 1 */
+
+  /* USER CODE END DMA1_Stream5_IRQn 1 */
+}
+ 803027a:	bf00      	nop
+ 803027c:	bd80      	pop	{r7, pc}
+ 803027e:	bf00      	nop
+ 8030280:	2400b110 	.word	0x2400b110
+
+08030284 <DMA1_Stream6_IRQHandler>:
+
+/**
+  * @brief This function handles DMA1 stream6 global interrupt.
+  */
+void DMA1_Stream6_IRQHandler(void)
+{
+ 8030284:	b580      	push	{r7, lr}
+ 8030286:	af00      	add	r7, sp, #0
+  /* USER CODE BEGIN DMA1_Stream6_IRQn 0 */
+
+  /* USER CODE END DMA1_Stream6_IRQn 0 */
+  HAL_DMA_IRQHandler(&hdma_usart3_tx);
+ 8030288:	4802      	ldr	r0, [pc, #8]	@ (8030294 <DMA1_Stream6_IRQHandler+0x10>)
+ 803028a:	f003 ffe9 	bl	8034260 <HAL_DMA_IRQHandler>
+  /* USER CODE BEGIN DMA1_Stream6_IRQn 1 */
+
+  /* USER CODE END DMA1_Stream6_IRQn 1 */
+}
+ 803028e:	bf00      	nop
+ 8030290:	bd80      	pop	{r7, pc}
+ 8030292:	bf00      	nop
+ 8030294:	2400b188 	.word	0x2400b188
+
+08030298 <FDCAN1_IT0_IRQHandler>:
+
+/**
+  * @brief This function handles FDCAN1 interrupt 0.
+  */
+void FDCAN1_IT0_IRQHandler(void)
+{
+ 8030298:	b580      	push	{r7, lr}
+ 803029a:	af00      	add	r7, sp, #0
+  /* USER CODE BEGIN FDCAN1_IT0_IRQn 0 */
+
+  /* USER CODE END FDCAN1_IT0_IRQn 0 */
+  HAL_FDCAN_IRQHandler(&hfdcan1);
+ 803029c:	4802      	ldr	r0, [pc, #8]	@ (80302a8 <FDCAN1_IT0_IRQHandler+0x10>)
+ 803029e:	f006 fcad 	bl	8036bfc <HAL_FDCAN_IRQHandler>
+  /* USER CODE BEGIN FDCAN1_IT0_IRQn 1 */
+
+  /* USER CODE END FDCAN1_IT0_IRQn 1 */
+}
+ 80302a2:	bf00      	nop
+ 80302a4:	bd80      	pop	{r7, pc}
+ 80302a6:	bf00      	nop
+ 80302a8:	2400a578 	.word	0x2400a578
+
+080302ac <FDCAN2_IT0_IRQHandler>:
+
+/**
+  * @brief This function handles FDCAN2 interrupt 0.
+  */
+void FDCAN2_IT0_IRQHandler(void)
+{
+ 80302ac:	b580      	push	{r7, lr}
+ 80302ae:	af00      	add	r7, sp, #0
+  /* USER CODE BEGIN FDCAN2_IT0_IRQn 0 */
+
+  /* USER CODE END FDCAN2_IT0_IRQn 0 */
+  HAL_FDCAN_IRQHandler(&hfdcan2);
+ 80302b0:	4802      	ldr	r0, [pc, #8]	@ (80302bc <FDCAN2_IT0_IRQHandler+0x10>)
+ 80302b2:	f006 fca3 	bl	8036bfc <HAL_FDCAN_IRQHandler>
+  /* USER CODE BEGIN FDCAN2_IT0_IRQn 1 */
+
+  /* USER CODE END FDCAN2_IT0_IRQn 1 */
+}
+ 80302b6:	bf00      	nop
+ 80302b8:	bd80      	pop	{r7, pc}
+ 80302ba:	bf00      	nop
+ 80302bc:	2400a618 	.word	0x2400a618
+
+080302c0 <TIM1_UP_IRQHandler>:
+
+/**
+  * @brief This function handles TIM1 update interrupt.
+  */
+void TIM1_UP_IRQHandler(void)
+{
+ 80302c0:	b580      	push	{r7, lr}
+ 80302c2:	af00      	add	r7, sp, #0
+  /* USER CODE BEGIN TIM1_UP_IRQn 0 */
+
+  /* USER CODE END TIM1_UP_IRQn 0 */
+  HAL_TIM_IRQHandler(&htim1);
+ 80302c4:	4802      	ldr	r0, [pc, #8]	@ (80302d0 <TIM1_UP_IRQHandler+0x10>)
+ 80302c6:	f00c fcab 	bl	803cc20 <HAL_TIM_IRQHandler>
+  /* USER CODE BEGIN TIM1_UP_IRQn 1 */
+
+  /* USER CODE END TIM1_UP_IRQn 1 */
+}
+ 80302ca:	bf00      	nop
+ 80302cc:	bd80      	pop	{r7, pc}
+ 80302ce:	bf00      	nop
+ 80302d0:	2400a9f8 	.word	0x2400a9f8
+
+080302d4 <USART1_IRQHandler>:
+
+/**
+  * @brief This function handles USART1 global interrupt.
+  */
+void USART1_IRQHandler(void)
+{
+ 80302d4:	b580      	push	{r7, lr}
+ 80302d6:	af00      	add	r7, sp, #0
+  /* USER CODE BEGIN USART1_IRQn 0 */
+
+  /* USER CODE END USART1_IRQn 0 */
+  HAL_UART_IRQHandler(&huart1);
+ 80302d8:	4802      	ldr	r0, [pc, #8]	@ (80302e4 <USART1_IRQHandler+0x10>)
+ 80302da:	f00d fa63 	bl	803d7a4 <HAL_UART_IRQHandler>
+  /* USER CODE BEGIN USART1_IRQn 1 */
+
+  /* USER CODE END USART1_IRQn 1 */
+}
+ 80302de:	bf00      	nop
+ 80302e0:	bd80      	pop	{r7, pc}
+ 80302e2:	bf00      	nop
+ 80302e4:	2400ace0 	.word	0x2400ace0
+
+080302e8 <USART2_IRQHandler>:
+
+/**
+  * @brief This function handles USART2 global interrupt.
+  */
+void USART2_IRQHandler(void)
+{
+ 80302e8:	b580      	push	{r7, lr}
+ 80302ea:	af00      	add	r7, sp, #0
+  /* USER CODE BEGIN USART2_IRQn 0 */
+
+  /* USER CODE END USART2_IRQn 0 */
+  HAL_UART_IRQHandler(&huart2);
+ 80302ec:	4802      	ldr	r0, [pc, #8]	@ (80302f8 <USART2_IRQHandler+0x10>)
+ 80302ee:	f00d fa59 	bl	803d7a4 <HAL_UART_IRQHandler>
+  /* USER CODE BEGIN USART2_IRQn 1 */
+
+  /* USER CODE END USART2_IRQn 1 */
+}
+ 80302f2:	bf00      	nop
+ 80302f4:	bd80      	pop	{r7, pc}
+ 80302f6:	bf00      	nop
+ 80302f8:	2400ad74 	.word	0x2400ad74
+
+080302fc <USART3_IRQHandler>:
+
+/**
+  * @brief This function handles USART3 global interrupt.
+  */
+void USART3_IRQHandler(void)
+{
+ 80302fc:	b580      	push	{r7, lr}
+ 80302fe:	af00      	add	r7, sp, #0
+  /* USER CODE BEGIN USART3_IRQn 0 */
+
+  /* USER CODE END USART3_IRQn 0 */
+  HAL_UART_IRQHandler(&huart3);
+ 8030300:	4802      	ldr	r0, [pc, #8]	@ (803030c <USART3_IRQHandler+0x10>)
+ 8030302:	f00d fa4f 	bl	803d7a4 <HAL_UART_IRQHandler>
+  /* USER CODE BEGIN USART3_IRQn 1 */
+
+  /* USER CODE END USART3_IRQn 1 */
+}
+ 8030306:	bf00      	nop
+ 8030308:	bd80      	pop	{r7, pc}
+ 803030a:	bf00      	nop
+ 803030c:	2400ae08 	.word	0x2400ae08
+
+08030310 <TIM8_UP_TIM13_IRQHandler>:
+
+/**
+  * @brief This function handles TIM8 update interrupt and TIM13 global interrupt.
+  */
+void TIM8_UP_TIM13_IRQHandler(void)
+{
+ 8030310:	b580      	push	{r7, lr}
+ 8030312:	af00      	add	r7, sp, #0
+  /* USER CODE BEGIN TIM8_UP_TIM13_IRQn 0 */
+
+  /* USER CODE END TIM8_UP_TIM13_IRQn 0 */
+  HAL_TIM_IRQHandler(&htim8);
+ 8030314:	4802      	ldr	r0, [pc, #8]	@ (8030320 <TIM8_UP_TIM13_IRQHandler+0x10>)
+ 8030316:	f00c fc83 	bl	803cc20 <HAL_TIM_IRQHandler>
+  /* USER CODE BEGIN TIM8_UP_TIM13_IRQn 1 */
+
+  /* USER CODE END TIM8_UP_TIM13_IRQn 1 */
+}
+ 803031a:	bf00      	nop
+ 803031c:	bd80      	pop	{r7, pc}
+ 803031e:	bf00      	nop
+ 8030320:	2400aa44 	.word	0x2400aa44
+
+08030324 <DMA1_Stream7_IRQHandler>:
+
+/**
+  * @brief This function handles DMA1 stream7 global interrupt.
+  */
+void DMA1_Stream7_IRQHandler(void)
+{
+ 8030324:	b580      	push	{r7, lr}
+ 8030326:	af00      	add	r7, sp, #0
+  /* USER CODE BEGIN DMA1_Stream7_IRQn 0 */
+
+  /* USER CODE END DMA1_Stream7_IRQn 0 */
+  HAL_DMA_IRQHandler(&hdma_usart6_tx);
+ 8030328:	4802      	ldr	r0, [pc, #8]	@ (8030334 <DMA1_Stream7_IRQHandler+0x10>)
+ 803032a:	f003 ff99 	bl	8034260 <HAL_DMA_IRQHandler>
+  /* USER CODE BEGIN DMA1_Stream7_IRQn 1 */
+
+  /* USER CODE END DMA1_Stream7_IRQn 1 */
+}
+ 803032e:	bf00      	nop
+ 8030330:	bd80      	pop	{r7, pc}
+ 8030332:	bf00      	nop
+ 8030334:	2400b200 	.word	0x2400b200
+
+08030338 <UART4_IRQHandler>:
+
+/**
+  * @brief This function handles UART4 global interrupt.
+  */
+void UART4_IRQHandler(void)
+{
+ 8030338:	b580      	push	{r7, lr}
+ 803033a:	af00      	add	r7, sp, #0
+  /* USER CODE BEGIN UART4_IRQn 0 */
+
+  /* USER CODE END UART4_IRQn 0 */
+  HAL_UART_IRQHandler(&huart4);
+ 803033c:	4802      	ldr	r0, [pc, #8]	@ (8030348 <UART4_IRQHandler+0x10>)
+ 803033e:	f00d fa31 	bl	803d7a4 <HAL_UART_IRQHandler>
+  /* USER CODE BEGIN UART4_IRQn 1 */
+
+  /* USER CODE END UART4_IRQn 1 */
+}
+ 8030342:	bf00      	nop
+ 8030344:	bd80      	pop	{r7, pc}
+ 8030346:	bf00      	nop
+ 8030348:	2400ab24 	.word	0x2400ab24
+
+0803034c <UART5_IRQHandler>:
+
+/**
+  * @brief This function handles UART5 global interrupt.
+  */
+void UART5_IRQHandler(void)
+{
+ 803034c:	b580      	push	{r7, lr}
+ 803034e:	af00      	add	r7, sp, #0
+  /* USER CODE BEGIN UART5_IRQn 0 */
+
+  /* USER CODE END UART5_IRQn 0 */
+  HAL_UART_IRQHandler(&huart5);
+ 8030350:	4802      	ldr	r0, [pc, #8]	@ (803035c <UART5_IRQHandler+0x10>)
+ 8030352:	f00d fa27 	bl	803d7a4 <HAL_UART_IRQHandler>
+  /* USER CODE BEGIN UART5_IRQn 1 */
+
+  /* USER CODE END UART5_IRQn 1 */
+}
+ 8030356:	bf00      	nop
+ 8030358:	bd80      	pop	{r7, pc}
+ 803035a:	bf00      	nop
+ 803035c:	2400abb8 	.word	0x2400abb8
+
+08030360 <ETH_IRQHandler>:
+
+/**
+  * @brief This function handles Ethernet global interrupt.
+  */
+void ETH_IRQHandler(void)
+{
+ 8030360:	b580      	push	{r7, lr}
+ 8030362:	af00      	add	r7, sp, #0
+  /* USER CODE BEGIN ETH_IRQn 0 */
+
+  /* USER CODE END ETH_IRQn 0 */
+  HAL_ETH_IRQHandler(&heth);
+ 8030364:	4802      	ldr	r0, [pc, #8]	@ (8030370 <ETH_IRQHandler+0x10>)
+ 8030366:	f005 fb99 	bl	8035a9c <HAL_ETH_IRQHandler>
+  /* USER CODE BEGIN ETH_IRQn 1 */
+
+  /* USER CODE END ETH_IRQn 1 */
+}
+ 803036a:	bf00      	nop
+ 803036c:	bd80      	pop	{r7, pc}
+ 803036e:	bf00      	nop
+ 8030370:	2400a4c0 	.word	0x2400a4c0
+
+08030374 <ETH_WKUP_IRQHandler>:
+
+/**
+  * @brief This function handles Ethernet wake-up interrupt through EXTI line 86.
+  */
+void ETH_WKUP_IRQHandler(void)
+{
+ 8030374:	b580      	push	{r7, lr}
+ 8030376:	af00      	add	r7, sp, #0
+  /* USER CODE BEGIN ETH_WKUP_IRQn 0 */
+
+  /* USER CODE END ETH_WKUP_IRQn 0 */
+  HAL_ETH_IRQHandler(&heth);
+ 8030378:	4802      	ldr	r0, [pc, #8]	@ (8030384 <ETH_WKUP_IRQHandler+0x10>)
+ 803037a:	f005 fb8f 	bl	8035a9c <HAL_ETH_IRQHandler>
+  /* USER CODE BEGIN ETH_WKUP_IRQn 1 */
+
+  /* USER CODE END ETH_WKUP_IRQn 1 */
+}
+ 803037e:	bf00      	nop
+ 8030380:	bd80      	pop	{r7, pc}
+ 8030382:	bf00      	nop
+ 8030384:	2400a4c0 	.word	0x2400a4c0
+
+08030388 <USART6_IRQHandler>:
+
+/**
+  * @brief This function handles USART6 global interrupt.
+  */
+void USART6_IRQHandler(void)
+{
+ 8030388:	b580      	push	{r7, lr}
+ 803038a:	af00      	add	r7, sp, #0
+  /* USER CODE BEGIN USART6_IRQn 0 */
+
+  /* USER CODE END USART6_IRQn 0 */
+  HAL_UART_IRQHandler(&huart6);
+ 803038c:	4802      	ldr	r0, [pc, #8]	@ (8030398 <USART6_IRQHandler+0x10>)
+ 803038e:	f00d fa09 	bl	803d7a4 <HAL_UART_IRQHandler>
+  /* USER CODE BEGIN USART6_IRQn 1 */
+
+  /* USER CODE END USART6_IRQn 1 */
+}
+ 8030392:	bf00      	nop
+ 8030394:	bd80      	pop	{r7, pc}
+ 8030396:	bf00      	nop
+ 8030398:	2400ae9c 	.word	0x2400ae9c
+
+0803039c <UART7_IRQHandler>:
+
+/**
+  * @brief This function handles UART7 global interrupt.
+  */
+void UART7_IRQHandler(void)
+{
+ 803039c:	b580      	push	{r7, lr}
+ 803039e:	af00      	add	r7, sp, #0
+  /* USER CODE BEGIN UART7_IRQn 0 */
+
+  /* USER CODE END UART7_IRQn 0 */
+  HAL_UART_IRQHandler(&huart7);
+ 80303a0:	4802      	ldr	r0, [pc, #8]	@ (80303ac <UART7_IRQHandler+0x10>)
+ 80303a2:	f00d f9ff 	bl	803d7a4 <HAL_UART_IRQHandler>
+  /* USER CODE BEGIN UART7_IRQn 1 */
+
+  /* USER CODE END UART7_IRQn 1 */
+}
+ 80303a6:	bf00      	nop
+ 80303a8:	bd80      	pop	{r7, pc}
+ 80303aa:	bf00      	nop
+ 80303ac:	2400ac4c 	.word	0x2400ac4c
+
+080303b0 <QUADSPI_IRQHandler>:
+
+/**
+  * @brief This function handles QUADSPI global interrupt.
+  */
+void QUADSPI_IRQHandler(void)
+{
+ 80303b0:	b580      	push	{r7, lr}
+ 80303b2:	af00      	add	r7, sp, #0
+  /* USER CODE BEGIN QUADSPI_IRQn 0 */
+
+  /* USER CODE END QUADSPI_IRQn 0 */
+  HAL_QSPI_IRQHandler(&hqspi);
+ 80303b4:	4802      	ldr	r0, [pc, #8]	@ (80303c0 <QUADSPI_IRQHandler+0x10>)
+ 80303b6:	f008 fbd1 	bl	8038b5c <HAL_QSPI_IRQHandler>
+  /* USER CODE BEGIN QUADSPI_IRQn 1 */
+
+  /* USER CODE END QUADSPI_IRQn 1 */
+}
+ 80303ba:	bf00      	nop
+ 80303bc:	bd80      	pop	{r7, pc}
+ 80303be:	bf00      	nop
+ 80303c0:	2400a984 	.word	0x2400a984
+
+080303c4 <I2C4_EV_IRQHandler>:
+
+/**
+  * @brief This function handles I2C4 event interrupt.
+  */
+void I2C4_EV_IRQHandler(void)
+{
+ 80303c4:	b580      	push	{r7, lr}
+ 80303c6:	af00      	add	r7, sp, #0
+  /* USER CODE BEGIN I2C4_EV_IRQn 0 */
+
+  /* USER CODE END I2C4_EV_IRQn 0 */
+  HAL_I2C_EV_IRQHandler(&hi2c4);
+ 80303c8:	4802      	ldr	r0, [pc, #8]	@ (80303d4 <I2C4_EV_IRQHandler+0x10>)
+ 80303ca:	f007 fb6d 	bl	8037aa8 <HAL_I2C_EV_IRQHandler>
+  /* USER CODE BEGIN I2C4_EV_IRQn 1 */
+
+  /* USER CODE END I2C4_EV_IRQn 1 */
+}
+ 80303ce:	bf00      	nop
+ 80303d0:	bd80      	pop	{r7, pc}
+ 80303d2:	bf00      	nop
+ 80303d4:	2400a910 	.word	0x2400a910
+
+080303d8 <I2C4_ER_IRQHandler>:
+
+/**
+  * @brief This function handles I2C4 error interrupt.
+  */
+void I2C4_ER_IRQHandler(void)
+{
+ 80303d8:	b580      	push	{r7, lr}
+ 80303da:	af00      	add	r7, sp, #0
+  /* USER CODE BEGIN I2C4_ER_IRQn 0 */
+
+  /* USER CODE END I2C4_ER_IRQn 0 */
+  HAL_I2C_ER_IRQHandler(&hi2c4);
+ 80303dc:	4802      	ldr	r0, [pc, #8]	@ (80303e8 <I2C4_ER_IRQHandler+0x10>)
+ 80303de:	f007 fb7d 	bl	8037adc <HAL_I2C_ER_IRQHandler>
+  /* USER CODE BEGIN I2C4_ER_IRQn 1 */
+
+  /* USER CODE END I2C4_ER_IRQn 1 */
+}
+ 80303e2:	bf00      	nop
+ 80303e4:	bd80      	pop	{r7, pc}
+ 80303e6:	bf00      	nop
+ 80303e8:	2400a910 	.word	0x2400a910
+
+080303ec <LPUART1_IRQHandler>:
+
+/**
+  * @brief This function handles LPUART1 global interrupt.
+  */
+void LPUART1_IRQHandler(void)
+{
+ 80303ec:	b580      	push	{r7, lr}
+ 80303ee:	af00      	add	r7, sp, #0
+  /* USER CODE BEGIN LPUART1_IRQn 0 */
+
+  /* USER CODE END LPUART1_IRQn 0 */
+  HAL_UART_IRQHandler(&hlpuart1);
+ 80303f0:	4802      	ldr	r0, [pc, #8]	@ (80303fc <LPUART1_IRQHandler+0x10>)
+ 80303f2:	f00d f9d7 	bl	803d7a4 <HAL_UART_IRQHandler>
+  /* USER CODE BEGIN LPUART1_IRQn 1 */
+
+  /* USER CODE END LPUART1_IRQn 1 */
+}
+ 80303f6:	bf00      	nop
+ 80303f8:	bd80      	pop	{r7, pc}
+ 80303fa:	bf00      	nop
+ 80303fc:	2400aa90 	.word	0x2400aa90
+
+08030400 <_sbrk>:
+ *
+ * @param incr Memory size
+ * @return Pointer to allocated memory
+ */
+void *_sbrk(ptrdiff_t incr)
+{
+ 8030400:	b580      	push	{r7, lr}
+ 8030402:	b086      	sub	sp, #24
+ 8030404:	af00      	add	r7, sp, #0
+ 8030406:	6078      	str	r0, [r7, #4]
+  extern uint8_t _end; /* Symbol defined in the linker script */
+  extern uint8_t _estack; /* Symbol defined in the linker script */
+  extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
+  const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
+ 8030408:	4a14      	ldr	r2, [pc, #80]	@ (803045c <_sbrk+0x5c>)
+ 803040a:	4b15      	ldr	r3, [pc, #84]	@ (8030460 <_sbrk+0x60>)
+ 803040c:	1ad3      	subs	r3, r2, r3
+ 803040e:	617b      	str	r3, [r7, #20]
+  const uint8_t *max_heap = (uint8_t *)stack_limit;
+ 8030410:	697b      	ldr	r3, [r7, #20]
+ 8030412:	613b      	str	r3, [r7, #16]
+  uint8_t *prev_heap_end;
+
+  /* Initialize heap end at first call */
+  if (NULL == __sbrk_heap_end)
+ 8030414:	4b13      	ldr	r3, [pc, #76]	@ (8030464 <_sbrk+0x64>)
+ 8030416:	681b      	ldr	r3, [r3, #0]
+ 8030418:	2b00      	cmp	r3, #0
+ 803041a:	d102      	bne.n	8030422 <_sbrk+0x22>
+  {
+    __sbrk_heap_end = &_end;
+ 803041c:	4b11      	ldr	r3, [pc, #68]	@ (8030464 <_sbrk+0x64>)
+ 803041e:	4a12      	ldr	r2, [pc, #72]	@ (8030468 <_sbrk+0x68>)
+ 8030420:	601a      	str	r2, [r3, #0]
+  }
+
+  /* Protect heap from growing into the reserved MSP stack */
+  if (__sbrk_heap_end + incr > max_heap)
+ 8030422:	4b10      	ldr	r3, [pc, #64]	@ (8030464 <_sbrk+0x64>)
+ 8030424:	681a      	ldr	r2, [r3, #0]
+ 8030426:	687b      	ldr	r3, [r7, #4]
+ 8030428:	4413      	add	r3, r2
+ 803042a:	693a      	ldr	r2, [r7, #16]
+ 803042c:	429a      	cmp	r2, r3
+ 803042e:	d207      	bcs.n	8030440 <_sbrk+0x40>
+  {
+    errno = ENOMEM;
+ 8030430:	f00f ff98 	bl	8040364 <__errno>
+ 8030434:	4603      	mov	r3, r0
+ 8030436:	220c      	movs	r2, #12
+ 8030438:	601a      	str	r2, [r3, #0]
+    return (void *)-1;
+ 803043a:	f04f 33ff 	mov.w	r3, #4294967295
+ 803043e:	e009      	b.n	8030454 <_sbrk+0x54>
+  }
+
+  prev_heap_end = __sbrk_heap_end;
+ 8030440:	4b08      	ldr	r3, [pc, #32]	@ (8030464 <_sbrk+0x64>)
+ 8030442:	681b      	ldr	r3, [r3, #0]
+ 8030444:	60fb      	str	r3, [r7, #12]
+  __sbrk_heap_end += incr;
+ 8030446:	4b07      	ldr	r3, [pc, #28]	@ (8030464 <_sbrk+0x64>)
+ 8030448:	681a      	ldr	r2, [r3, #0]
+ 803044a:	687b      	ldr	r3, [r7, #4]
+ 803044c:	4413      	add	r3, r2
+ 803044e:	4a05      	ldr	r2, [pc, #20]	@ (8030464 <_sbrk+0x64>)
+ 8030450:	6013      	str	r3, [r2, #0]
+
+  return (void *)prev_heap_end;
+ 8030452:	68fb      	ldr	r3, [r7, #12]
+}
+ 8030454:	4618      	mov	r0, r3
+ 8030456:	3718      	adds	r7, #24
+ 8030458:	46bd      	mov	sp, r7
+ 803045a:	bd80      	pop	{r7, pc}
+ 803045c:	24080000 	.word	0x24080000
+ 8030460:	00002000 	.word	0x00002000
+ 8030464:	2400a9f4 	.word	0x2400a9f4
+ 8030468:	2400b3c8 	.word	0x2400b3c8
+
+0803046c <SystemInit>:
+  *         configuration.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+ 803046c:	b480      	push	{r7}
+ 803046e:	af00      	add	r7, sp, #0
+ __IO uint32_t tmpreg;
+#endif /* DATA_IN_D2_SRAM */
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2)));  /* set CP10 and CP11 Full Access */
+ 8030470:	4b39      	ldr	r3, [pc, #228]	@ (8030558 <SystemInit+0xec>)
+ 8030472:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
+ 8030476:	4a38      	ldr	r2, [pc, #224]	@ (8030558 <SystemInit+0xec>)
+ 8030478:	f443 0370 	orr.w	r3, r3, #15728640	@ 0xf00000
+ 803047c:	f8c2 3088 	str.w	r3, [r2, #136]	@ 0x88
+  #endif
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+
+   /* Increasing the CPU frequency */
+  if(FLASH_LATENCY_DEFAULT  > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
+ 8030480:	4b36      	ldr	r3, [pc, #216]	@ (803055c <SystemInit+0xf0>)
+ 8030482:	681b      	ldr	r3, [r3, #0]
+ 8030484:	f003 030f 	and.w	r3, r3, #15
+ 8030488:	2b06      	cmp	r3, #6
+ 803048a:	d807      	bhi.n	803049c <SystemInit+0x30>
+  {
+    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+    MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
+ 803048c:	4b33      	ldr	r3, [pc, #204]	@ (803055c <SystemInit+0xf0>)
+ 803048e:	681b      	ldr	r3, [r3, #0]
+ 8030490:	f023 030f 	bic.w	r3, r3, #15
+ 8030494:	4a31      	ldr	r2, [pc, #196]	@ (803055c <SystemInit+0xf0>)
+ 8030496:	f043 0307 	orr.w	r3, r3, #7
+ 803049a:	6013      	str	r3, [r2, #0]
+  }
+
+  /* Set HSION bit */
+  RCC->CR |= RCC_CR_HSION;
+ 803049c:	4b30      	ldr	r3, [pc, #192]	@ (8030560 <SystemInit+0xf4>)
+ 803049e:	681b      	ldr	r3, [r3, #0]
+ 80304a0:	4a2f      	ldr	r2, [pc, #188]	@ (8030560 <SystemInit+0xf4>)
+ 80304a2:	f043 0301 	orr.w	r3, r3, #1
+ 80304a6:	6013      	str	r3, [r2, #0]
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00000000;
+ 80304a8:	4b2d      	ldr	r3, [pc, #180]	@ (8030560 <SystemInit+0xf4>)
+ 80304aa:	2200      	movs	r2, #0
+ 80304ac:	611a      	str	r2, [r3, #16]
+
+  /* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */
+  RCC->CR &= 0xEAF6ED7FU;
+ 80304ae:	4b2c      	ldr	r3, [pc, #176]	@ (8030560 <SystemInit+0xf4>)
+ 80304b0:	681a      	ldr	r2, [r3, #0]
+ 80304b2:	492b      	ldr	r1, [pc, #172]	@ (8030560 <SystemInit+0xf4>)
+ 80304b4:	4b2b      	ldr	r3, [pc, #172]	@ (8030564 <SystemInit+0xf8>)
+ 80304b6:	4013      	ands	r3, r2
+ 80304b8:	600b      	str	r3, [r1, #0]
+
+   /* Decreasing the number of wait states because of lower CPU frequency */
+  if(FLASH_LATENCY_DEFAULT  < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
+ 80304ba:	4b28      	ldr	r3, [pc, #160]	@ (803055c <SystemInit+0xf0>)
+ 80304bc:	681b      	ldr	r3, [r3, #0]
+ 80304be:	f003 0308 	and.w	r3, r3, #8
+ 80304c2:	2b00      	cmp	r3, #0
+ 80304c4:	d007      	beq.n	80304d6 <SystemInit+0x6a>
+  {
+    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+    MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
+ 80304c6:	4b25      	ldr	r3, [pc, #148]	@ (803055c <SystemInit+0xf0>)
+ 80304c8:	681b      	ldr	r3, [r3, #0]
+ 80304ca:	f023 030f 	bic.w	r3, r3, #15
+ 80304ce:	4a23      	ldr	r2, [pc, #140]	@ (803055c <SystemInit+0xf0>)
+ 80304d0:	f043 0307 	orr.w	r3, r3, #7
+ 80304d4:	6013      	str	r3, [r2, #0]
+  }
+
+#if defined(D3_SRAM_BASE)
+  /* Reset D1CFGR register */
+  RCC->D1CFGR = 0x00000000;
+ 80304d6:	4b22      	ldr	r3, [pc, #136]	@ (8030560 <SystemInit+0xf4>)
+ 80304d8:	2200      	movs	r2, #0
+ 80304da:	619a      	str	r2, [r3, #24]
+
+  /* Reset D2CFGR register */
+  RCC->D2CFGR = 0x00000000;
+ 80304dc:	4b20      	ldr	r3, [pc, #128]	@ (8030560 <SystemInit+0xf4>)
+ 80304de:	2200      	movs	r2, #0
+ 80304e0:	61da      	str	r2, [r3, #28]
+
+  /* Reset D3CFGR register */
+  RCC->D3CFGR = 0x00000000;
+ 80304e2:	4b1f      	ldr	r3, [pc, #124]	@ (8030560 <SystemInit+0xf4>)
+ 80304e4:	2200      	movs	r2, #0
+ 80304e6:	621a      	str	r2, [r3, #32]
+
+  /* Reset SRDCFGR register */
+  RCC->SRDCFGR = 0x00000000;
+#endif
+  /* Reset PLLCKSELR register */
+  RCC->PLLCKSELR = 0x02020200;
+ 80304e8:	4b1d      	ldr	r3, [pc, #116]	@ (8030560 <SystemInit+0xf4>)
+ 80304ea:	4a1f      	ldr	r2, [pc, #124]	@ (8030568 <SystemInit+0xfc>)
+ 80304ec:	629a      	str	r2, [r3, #40]	@ 0x28
+
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x01FF0000;
+ 80304ee:	4b1c      	ldr	r3, [pc, #112]	@ (8030560 <SystemInit+0xf4>)
+ 80304f0:	4a1e      	ldr	r2, [pc, #120]	@ (803056c <SystemInit+0x100>)
+ 80304f2:	62da      	str	r2, [r3, #44]	@ 0x2c
+  /* Reset PLL1DIVR register */
+  RCC->PLL1DIVR = 0x01010280;
+ 80304f4:	4b1a      	ldr	r3, [pc, #104]	@ (8030560 <SystemInit+0xf4>)
+ 80304f6:	4a1e      	ldr	r2, [pc, #120]	@ (8030570 <SystemInit+0x104>)
+ 80304f8:	631a      	str	r2, [r3, #48]	@ 0x30
+  /* Reset PLL1FRACR register */
+  RCC->PLL1FRACR = 0x00000000;
+ 80304fa:	4b19      	ldr	r3, [pc, #100]	@ (8030560 <SystemInit+0xf4>)
+ 80304fc:	2200      	movs	r2, #0
+ 80304fe:	635a      	str	r2, [r3, #52]	@ 0x34
+
+  /* Reset PLL2DIVR register */
+  RCC->PLL2DIVR = 0x01010280;
+ 8030500:	4b17      	ldr	r3, [pc, #92]	@ (8030560 <SystemInit+0xf4>)
+ 8030502:	4a1b      	ldr	r2, [pc, #108]	@ (8030570 <SystemInit+0x104>)
+ 8030504:	639a      	str	r2, [r3, #56]	@ 0x38
+
+  /* Reset PLL2FRACR register */
+
+  RCC->PLL2FRACR = 0x00000000;
+ 8030506:	4b16      	ldr	r3, [pc, #88]	@ (8030560 <SystemInit+0xf4>)
+ 8030508:	2200      	movs	r2, #0
+ 803050a:	63da      	str	r2, [r3, #60]	@ 0x3c
+  /* Reset PLL3DIVR register */
+  RCC->PLL3DIVR = 0x01010280;
+ 803050c:	4b14      	ldr	r3, [pc, #80]	@ (8030560 <SystemInit+0xf4>)
+ 803050e:	4a18      	ldr	r2, [pc, #96]	@ (8030570 <SystemInit+0x104>)
+ 8030510:	641a      	str	r2, [r3, #64]	@ 0x40
+
+  /* Reset PLL3FRACR register */
+  RCC->PLL3FRACR = 0x00000000;
+ 8030512:	4b13      	ldr	r3, [pc, #76]	@ (8030560 <SystemInit+0xf4>)
+ 8030514:	2200      	movs	r2, #0
+ 8030516:	645a      	str	r2, [r3, #68]	@ 0x44
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+ 8030518:	4b11      	ldr	r3, [pc, #68]	@ (8030560 <SystemInit+0xf4>)
+ 803051a:	681b      	ldr	r3, [r3, #0]
+ 803051c:	4a10      	ldr	r2, [pc, #64]	@ (8030560 <SystemInit+0xf4>)
+ 803051e:	f423 2380 	bic.w	r3, r3, #262144	@ 0x40000
+ 8030522:	6013      	str	r3, [r2, #0]
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+ 8030524:	4b0e      	ldr	r3, [pc, #56]	@ (8030560 <SystemInit+0xf4>)
+ 8030526:	2200      	movs	r2, #0
+ 8030528:	661a      	str	r2, [r3, #96]	@ 0x60
+
+#if (STM32H7_DEV_ID == 0x450UL)
+  /* dual core CM7 or single core line */
+  if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U)
+ 803052a:	4b12      	ldr	r3, [pc, #72]	@ (8030574 <SystemInit+0x108>)
+ 803052c:	681a      	ldr	r2, [r3, #0]
+ 803052e:	4b12      	ldr	r3, [pc, #72]	@ (8030578 <SystemInit+0x10c>)
+ 8030530:	4013      	ands	r3, r2
+ 8030532:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
+ 8030536:	d202      	bcs.n	803053e <SystemInit+0xd2>
+  {
+    /* if stm32h7 revY*/
+    /* Change  the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
+    *((__IO uint32_t*)0x51008108) = 0x000000001U;
+ 8030538:	4b10      	ldr	r3, [pc, #64]	@ (803057c <SystemInit+0x110>)
+ 803053a:	2201      	movs	r2, #1
+ 803053c:	601a      	str	r2, [r3, #0]
+  /*
+   * Disable the FMC bank1 (enabled after reset).
+   * This, prevents CPU speculation access on this bank which blocks the use of FMC during
+   * 24us. During this time the others FMC master (such as LTDC) cannot use it!
+   */
+  FMC_Bank1_R->BTCR[0] = 0x000030D2;
+ 803053e:	4b10      	ldr	r3, [pc, #64]	@ (8030580 <SystemInit+0x114>)
+ 8030540:	f243 02d2 	movw	r2, #12498	@ 0x30d2
+ 8030544:	601a      	str	r2, [r3, #0]
+
+  /* Configure the Vector Table location -------------------------------------*/
+#if defined(USER_VECT_TAB_ADDRESS)
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM or in Internal FLASH */
+ 8030546:	4b04      	ldr	r3, [pc, #16]	@ (8030558 <SystemInit+0xec>)
+ 8030548:	4a0e      	ldr	r2, [pc, #56]	@ (8030584 <SystemInit+0x118>)
+ 803054a:	609a      	str	r2, [r3, #8]
+#endif /* USER_VECT_TAB_ADDRESS */
+
+#endif /*DUAL_CORE && CORE_CM4*/
+}
+ 803054c:	bf00      	nop
+ 803054e:	46bd      	mov	sp, r7
+ 8030550:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8030554:	4770      	bx	lr
+ 8030556:	bf00      	nop
+ 8030558:	e000ed00 	.word	0xe000ed00
+ 803055c:	52002000 	.word	0x52002000
+ 8030560:	58024400 	.word	0x58024400
+ 8030564:	eaf6ed7f 	.word	0xeaf6ed7f
+ 8030568:	02020200 	.word	0x02020200
+ 803056c:	01ff0000 	.word	0x01ff0000
+ 8030570:	01010280 	.word	0x01010280
+ 8030574:	5c001000 	.word	0x5c001000
+ 8030578:	ffff0000 	.word	0xffff0000
+ 803057c:	51008108 	.word	0x51008108
+ 8030580:	52004000 	.word	0x52004000
+ 8030584:	08020000 	.word	0x08020000
+
+08030588 <MX_TIM1_Init>:
+TIM_HandleTypeDef htim1;
+TIM_HandleTypeDef htim8;
+
+/* TIM1 init function */
+void MX_TIM1_Init(void)
+{
+ 8030588:	b580      	push	{r7, lr}
+ 803058a:	b088      	sub	sp, #32
+ 803058c:	af00      	add	r7, sp, #0
+
+  /* USER CODE BEGIN TIM1_Init 0 */
+
+  /* USER CODE END TIM1_Init 0 */
+
+  TIM_ClockConfigTypeDef sClockSourceConfig = {0};
+ 803058e:	f107 0310 	add.w	r3, r7, #16
+ 8030592:	2200      	movs	r2, #0
+ 8030594:	601a      	str	r2, [r3, #0]
+ 8030596:	605a      	str	r2, [r3, #4]
+ 8030598:	609a      	str	r2, [r3, #8]
+ 803059a:	60da      	str	r2, [r3, #12]
+  TIM_MasterConfigTypeDef sMasterConfig = {0};
+ 803059c:	1d3b      	adds	r3, r7, #4
+ 803059e:	2200      	movs	r2, #0
+ 80305a0:	601a      	str	r2, [r3, #0]
+ 80305a2:	605a      	str	r2, [r3, #4]
+ 80305a4:	609a      	str	r2, [r3, #8]
+
+  /* USER CODE BEGIN TIM1_Init 1 */
+
+  /* USER CODE END TIM1_Init 1 */
+  htim1.Instance = TIM1;
+ 80305a6:	4b20      	ldr	r3, [pc, #128]	@ (8030628 <MX_TIM1_Init+0xa0>)
+ 80305a8:	4a20      	ldr	r2, [pc, #128]	@ (803062c <MX_TIM1_Init+0xa4>)
+ 80305aa:	601a      	str	r2, [r3, #0]
+  htim1.Init.Prescaler = 2000-1;
+ 80305ac:	4b1e      	ldr	r3, [pc, #120]	@ (8030628 <MX_TIM1_Init+0xa0>)
+ 80305ae:	f240 72cf 	movw	r2, #1999	@ 0x7cf
+ 80305b2:	605a      	str	r2, [r3, #4]
+  htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
+ 80305b4:	4b1c      	ldr	r3, [pc, #112]	@ (8030628 <MX_TIM1_Init+0xa0>)
+ 80305b6:	2200      	movs	r2, #0
+ 80305b8:	609a      	str	r2, [r3, #8]
+  htim1.Init.Period = 10000-1;
+ 80305ba:	4b1b      	ldr	r3, [pc, #108]	@ (8030628 <MX_TIM1_Init+0xa0>)
+ 80305bc:	f242 720f 	movw	r2, #9999	@ 0x270f
+ 80305c0:	60da      	str	r2, [r3, #12]
+  htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+ 80305c2:	4b19      	ldr	r3, [pc, #100]	@ (8030628 <MX_TIM1_Init+0xa0>)
+ 80305c4:	2200      	movs	r2, #0
+ 80305c6:	611a      	str	r2, [r3, #16]
+  htim1.Init.RepetitionCounter = 0;
+ 80305c8:	4b17      	ldr	r3, [pc, #92]	@ (8030628 <MX_TIM1_Init+0xa0>)
+ 80305ca:	2200      	movs	r2, #0
+ 80305cc:	615a      	str	r2, [r3, #20]
+  htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE;
+ 80305ce:	4b16      	ldr	r3, [pc, #88]	@ (8030628 <MX_TIM1_Init+0xa0>)
+ 80305d0:	2280      	movs	r2, #128	@ 0x80
+ 80305d2:	619a      	str	r2, [r3, #24]
+  if (HAL_TIM_Base_Init(&htim1) != HAL_OK)
+ 80305d4:	4814      	ldr	r0, [pc, #80]	@ (8030628 <MX_TIM1_Init+0xa0>)
+ 80305d6:	f00c fa53 	bl	803ca80 <HAL_TIM_Base_Init>
+ 80305da:	4603      	mov	r3, r0
+ 80305dc:	2b00      	cmp	r3, #0
+ 80305de:	d001      	beq.n	80305e4 <MX_TIM1_Init+0x5c>
+  {
+    Error_Handler();
+ 80305e0:	f7ff fa52 	bl	802fa88 <Error_Handler>
+  }
+  sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
+ 80305e4:	f44f 5380 	mov.w	r3, #4096	@ 0x1000
+ 80305e8:	613b      	str	r3, [r7, #16]
+  if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK)
+ 80305ea:	f107 0310 	add.w	r3, r7, #16
+ 80305ee:	4619      	mov	r1, r3
+ 80305f0:	480d      	ldr	r0, [pc, #52]	@ (8030628 <MX_TIM1_Init+0xa0>)
+ 80305f2:	f00c fc1d 	bl	803ce30 <HAL_TIM_ConfigClockSource>
+ 80305f6:	4603      	mov	r3, r0
+ 80305f8:	2b00      	cmp	r3, #0
+ 80305fa:	d001      	beq.n	8030600 <MX_TIM1_Init+0x78>
+  {
+    Error_Handler();
+ 80305fc:	f7ff fa44 	bl	802fa88 <Error_Handler>
+  }
+  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
+ 8030600:	2300      	movs	r3, #0
+ 8030602:	607b      	str	r3, [r7, #4]
+  sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET;
+ 8030604:	2300      	movs	r3, #0
+ 8030606:	60bb      	str	r3, [r7, #8]
+  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+ 8030608:	2300      	movs	r3, #0
+ 803060a:	60fb      	str	r3, [r7, #12]
+  if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK)
+ 803060c:	1d3b      	adds	r3, r7, #4
+ 803060e:	4619      	mov	r1, r3
+ 8030610:	4805      	ldr	r0, [pc, #20]	@ (8030628 <MX_TIM1_Init+0xa0>)
+ 8030612:	f00c fe71 	bl	803d2f8 <HAL_TIMEx_MasterConfigSynchronization>
+ 8030616:	4603      	mov	r3, r0
+ 8030618:	2b00      	cmp	r3, #0
+ 803061a:	d001      	beq.n	8030620 <MX_TIM1_Init+0x98>
+  {
+    Error_Handler();
+ 803061c:	f7ff fa34 	bl	802fa88 <Error_Handler>
+  }
+  /* USER CODE BEGIN TIM1_Init 2 */
+
+  /* USER CODE END TIM1_Init 2 */
+
+}
+ 8030620:	bf00      	nop
+ 8030622:	3720      	adds	r7, #32
+ 8030624:	46bd      	mov	sp, r7
+ 8030626:	bd80      	pop	{r7, pc}
+ 8030628:	2400a9f8 	.word	0x2400a9f8
+ 803062c:	40010000 	.word	0x40010000
+
+08030630 <MX_TIM8_Init>:
+/* TIM8 init function */
+void MX_TIM8_Init(void)
+{
+ 8030630:	b580      	push	{r7, lr}
+ 8030632:	b088      	sub	sp, #32
+ 8030634:	af00      	add	r7, sp, #0
+
+  /* USER CODE BEGIN TIM8_Init 0 */
+
+  /* USER CODE END TIM8_Init 0 */
+
+  TIM_ClockConfigTypeDef sClockSourceConfig = {0};
+ 8030636:	f107 0310 	add.w	r3, r7, #16
+ 803063a:	2200      	movs	r2, #0
+ 803063c:	601a      	str	r2, [r3, #0]
+ 803063e:	605a      	str	r2, [r3, #4]
+ 8030640:	609a      	str	r2, [r3, #8]
+ 8030642:	60da      	str	r2, [r3, #12]
+  TIM_MasterConfigTypeDef sMasterConfig = {0};
+ 8030644:	1d3b      	adds	r3, r7, #4
+ 8030646:	2200      	movs	r2, #0
+ 8030648:	601a      	str	r2, [r3, #0]
+ 803064a:	605a      	str	r2, [r3, #4]
+ 803064c:	609a      	str	r2, [r3, #8]
+
+  /* USER CODE BEGIN TIM8_Init 1 */
+
+  /* USER CODE END TIM8_Init 1 */
+  htim8.Instance = TIM8;
+ 803064e:	4b20      	ldr	r3, [pc, #128]	@ (80306d0 <MX_TIM8_Init+0xa0>)
+ 8030650:	4a20      	ldr	r2, [pc, #128]	@ (80306d4 <MX_TIM8_Init+0xa4>)
+ 8030652:	601a      	str	r2, [r3, #0]
+  htim8.Init.Prescaler = 2000-1;
+ 8030654:	4b1e      	ldr	r3, [pc, #120]	@ (80306d0 <MX_TIM8_Init+0xa0>)
+ 8030656:	f240 72cf 	movw	r2, #1999	@ 0x7cf
+ 803065a:	605a      	str	r2, [r3, #4]
+  htim8.Init.CounterMode = TIM_COUNTERMODE_UP;
+ 803065c:	4b1c      	ldr	r3, [pc, #112]	@ (80306d0 <MX_TIM8_Init+0xa0>)
+ 803065e:	2200      	movs	r2, #0
+ 8030660:	609a      	str	r2, [r3, #8]
+  htim8.Init.Period = 200-1;
+ 8030662:	4b1b      	ldr	r3, [pc, #108]	@ (80306d0 <MX_TIM8_Init+0xa0>)
+ 8030664:	22c7      	movs	r2, #199	@ 0xc7
+ 8030666:	60da      	str	r2, [r3, #12]
+  htim8.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+ 8030668:	4b19      	ldr	r3, [pc, #100]	@ (80306d0 <MX_TIM8_Init+0xa0>)
+ 803066a:	2200      	movs	r2, #0
+ 803066c:	611a      	str	r2, [r3, #16]
+  htim8.Init.RepetitionCounter = 0;
+ 803066e:	4b18      	ldr	r3, [pc, #96]	@ (80306d0 <MX_TIM8_Init+0xa0>)
+ 8030670:	2200      	movs	r2, #0
+ 8030672:	615a      	str	r2, [r3, #20]
+  htim8.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+ 8030674:	4b16      	ldr	r3, [pc, #88]	@ (80306d0 <MX_TIM8_Init+0xa0>)
+ 8030676:	2200      	movs	r2, #0
+ 8030678:	619a      	str	r2, [r3, #24]
+  if (HAL_TIM_Base_Init(&htim8) != HAL_OK)
+ 803067a:	4815      	ldr	r0, [pc, #84]	@ (80306d0 <MX_TIM8_Init+0xa0>)
+ 803067c:	f00c fa00 	bl	803ca80 <HAL_TIM_Base_Init>
+ 8030680:	4603      	mov	r3, r0
+ 8030682:	2b00      	cmp	r3, #0
+ 8030684:	d001      	beq.n	803068a <MX_TIM8_Init+0x5a>
+  {
+    Error_Handler();
+ 8030686:	f7ff f9ff 	bl	802fa88 <Error_Handler>
+  }
+  sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
+ 803068a:	f44f 5380 	mov.w	r3, #4096	@ 0x1000
+ 803068e:	613b      	str	r3, [r7, #16]
+  if (HAL_TIM_ConfigClockSource(&htim8, &sClockSourceConfig) != HAL_OK)
+ 8030690:	f107 0310 	add.w	r3, r7, #16
+ 8030694:	4619      	mov	r1, r3
+ 8030696:	480e      	ldr	r0, [pc, #56]	@ (80306d0 <MX_TIM8_Init+0xa0>)
+ 8030698:	f00c fbca 	bl	803ce30 <HAL_TIM_ConfigClockSource>
+ 803069c:	4603      	mov	r3, r0
+ 803069e:	2b00      	cmp	r3, #0
+ 80306a0:	d001      	beq.n	80306a6 <MX_TIM8_Init+0x76>
+  {
+    Error_Handler();
+ 80306a2:	f7ff f9f1 	bl	802fa88 <Error_Handler>
+  }
+  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
+ 80306a6:	2300      	movs	r3, #0
+ 80306a8:	607b      	str	r3, [r7, #4]
+  sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET;
+ 80306aa:	2300      	movs	r3, #0
+ 80306ac:	60bb      	str	r3, [r7, #8]
+  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+ 80306ae:	2300      	movs	r3, #0
+ 80306b0:	60fb      	str	r3, [r7, #12]
+  if (HAL_TIMEx_MasterConfigSynchronization(&htim8, &sMasterConfig) != HAL_OK)
+ 80306b2:	1d3b      	adds	r3, r7, #4
+ 80306b4:	4619      	mov	r1, r3
+ 80306b6:	4806      	ldr	r0, [pc, #24]	@ (80306d0 <MX_TIM8_Init+0xa0>)
+ 80306b8:	f00c fe1e 	bl	803d2f8 <HAL_TIMEx_MasterConfigSynchronization>
+ 80306bc:	4603      	mov	r3, r0
+ 80306be:	2b00      	cmp	r3, #0
+ 80306c0:	d001      	beq.n	80306c6 <MX_TIM8_Init+0x96>
+  {
+    Error_Handler();
+ 80306c2:	f7ff f9e1 	bl	802fa88 <Error_Handler>
+  }
+  /* USER CODE BEGIN TIM8_Init 2 */
+
+  /* USER CODE END TIM8_Init 2 */
+
+}
+ 80306c6:	bf00      	nop
+ 80306c8:	3720      	adds	r7, #32
+ 80306ca:	46bd      	mov	sp, r7
+ 80306cc:	bd80      	pop	{r7, pc}
+ 80306ce:	bf00      	nop
+ 80306d0:	2400aa44 	.word	0x2400aa44
+ 80306d4:	40010400 	.word	0x40010400
+
+080306d8 <HAL_TIM_Base_MspInit>:
+
+void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle)
+{
+ 80306d8:	b580      	push	{r7, lr}
+ 80306da:	b084      	sub	sp, #16
+ 80306dc:	af00      	add	r7, sp, #0
+ 80306de:	6078      	str	r0, [r7, #4]
+
+  if(tim_baseHandle->Instance==TIM1)
+ 80306e0:	687b      	ldr	r3, [r7, #4]
+ 80306e2:	681b      	ldr	r3, [r3, #0]
+ 80306e4:	4a1d      	ldr	r2, [pc, #116]	@ (803075c <HAL_TIM_Base_MspInit+0x84>)
+ 80306e6:	4293      	cmp	r3, r2
+ 80306e8:	d117      	bne.n	803071a <HAL_TIM_Base_MspInit+0x42>
+  {
+  /* USER CODE BEGIN TIM1_MspInit 0 */
+
+  /* USER CODE END TIM1_MspInit 0 */
+    /* TIM1 clock enable */
+    __HAL_RCC_TIM1_CLK_ENABLE();
+ 80306ea:	4b1d      	ldr	r3, [pc, #116]	@ (8030760 <HAL_TIM_Base_MspInit+0x88>)
+ 80306ec:	f8d3 30f0 	ldr.w	r3, [r3, #240]	@ 0xf0
+ 80306f0:	4a1b      	ldr	r2, [pc, #108]	@ (8030760 <HAL_TIM_Base_MspInit+0x88>)
+ 80306f2:	f043 0301 	orr.w	r3, r3, #1
+ 80306f6:	f8c2 30f0 	str.w	r3, [r2, #240]	@ 0xf0
+ 80306fa:	4b19      	ldr	r3, [pc, #100]	@ (8030760 <HAL_TIM_Base_MspInit+0x88>)
+ 80306fc:	f8d3 30f0 	ldr.w	r3, [r3, #240]	@ 0xf0
+ 8030700:	f003 0301 	and.w	r3, r3, #1
+ 8030704:	60fb      	str	r3, [r7, #12]
+ 8030706:	68fb      	ldr	r3, [r7, #12]
+
+    /* TIM1 interrupt Init */
+    HAL_NVIC_SetPriority(TIM1_UP_IRQn, 0, 0);
+ 8030708:	2200      	movs	r2, #0
+ 803070a:	2100      	movs	r1, #0
+ 803070c:	2019      	movs	r0, #25
+ 803070e:	f002 f9d0 	bl	8032ab2 <HAL_NVIC_SetPriority>
+    HAL_NVIC_EnableIRQ(TIM1_UP_IRQn);
+ 8030712:	2019      	movs	r0, #25
+ 8030714:	f002 f9e7 	bl	8032ae6 <HAL_NVIC_EnableIRQ>
+    HAL_NVIC_EnableIRQ(TIM8_UP_TIM13_IRQn);
+  /* USER CODE BEGIN TIM8_MspInit 1 */
+
+  /* USER CODE END TIM8_MspInit 1 */
+  }
+}
+ 8030718:	e01b      	b.n	8030752 <HAL_TIM_Base_MspInit+0x7a>
+  else if(tim_baseHandle->Instance==TIM8)
+ 803071a:	687b      	ldr	r3, [r7, #4]
+ 803071c:	681b      	ldr	r3, [r3, #0]
+ 803071e:	4a11      	ldr	r2, [pc, #68]	@ (8030764 <HAL_TIM_Base_MspInit+0x8c>)
+ 8030720:	4293      	cmp	r3, r2
+ 8030722:	d116      	bne.n	8030752 <HAL_TIM_Base_MspInit+0x7a>
+    __HAL_RCC_TIM8_CLK_ENABLE();
+ 8030724:	4b0e      	ldr	r3, [pc, #56]	@ (8030760 <HAL_TIM_Base_MspInit+0x88>)
+ 8030726:	f8d3 30f0 	ldr.w	r3, [r3, #240]	@ 0xf0
+ 803072a:	4a0d      	ldr	r2, [pc, #52]	@ (8030760 <HAL_TIM_Base_MspInit+0x88>)
+ 803072c:	f043 0302 	orr.w	r3, r3, #2
+ 8030730:	f8c2 30f0 	str.w	r3, [r2, #240]	@ 0xf0
+ 8030734:	4b0a      	ldr	r3, [pc, #40]	@ (8030760 <HAL_TIM_Base_MspInit+0x88>)
+ 8030736:	f8d3 30f0 	ldr.w	r3, [r3, #240]	@ 0xf0
+ 803073a:	f003 0302 	and.w	r3, r3, #2
+ 803073e:	60bb      	str	r3, [r7, #8]
+ 8030740:	68bb      	ldr	r3, [r7, #8]
+    HAL_NVIC_SetPriority(TIM8_UP_TIM13_IRQn, 0, 0);
+ 8030742:	2200      	movs	r2, #0
+ 8030744:	2100      	movs	r1, #0
+ 8030746:	202c      	movs	r0, #44	@ 0x2c
+ 8030748:	f002 f9b3 	bl	8032ab2 <HAL_NVIC_SetPriority>
+    HAL_NVIC_EnableIRQ(TIM8_UP_TIM13_IRQn);
+ 803074c:	202c      	movs	r0, #44	@ 0x2c
+ 803074e:	f002 f9ca 	bl	8032ae6 <HAL_NVIC_EnableIRQ>
+}
+ 8030752:	bf00      	nop
+ 8030754:	3710      	adds	r7, #16
+ 8030756:	46bd      	mov	sp, r7
+ 8030758:	bd80      	pop	{r7, pc}
+ 803075a:	bf00      	nop
+ 803075c:	40010000 	.word	0x40010000
+ 8030760:	58024400 	.word	0x58024400
+ 8030764:	40010400 	.word	0x40010400
+
+08030768 <MX_LPUART1_UART_Init>:
+DMA_HandleTypeDef hdma_usart6_tx;
+
+/* LPUART1 init function */
+
+void MX_LPUART1_UART_Init(void)
+{
+ 8030768:	b580      	push	{r7, lr}
+ 803076a:	af00      	add	r7, sp, #0
+  /* USER CODE END LPUART1_Init 0 */
+
+  /* USER CODE BEGIN LPUART1_Init 1 */
+
+  /* USER CODE END LPUART1_Init 1 */
+  hlpuart1.Instance = LPUART1;
+ 803076c:	4b26      	ldr	r3, [pc, #152]	@ (8030808 <MX_LPUART1_UART_Init+0xa0>)
+ 803076e:	4a27      	ldr	r2, [pc, #156]	@ (803080c <MX_LPUART1_UART_Init+0xa4>)
+ 8030770:	601a      	str	r2, [r3, #0]
+  hlpuart1.Init.BaudRate = 57600;
+ 8030772:	4b25      	ldr	r3, [pc, #148]	@ (8030808 <MX_LPUART1_UART_Init+0xa0>)
+ 8030774:	f44f 4261 	mov.w	r2, #57600	@ 0xe100
+ 8030778:	605a      	str	r2, [r3, #4]
+  hlpuart1.Init.WordLength = UART_WORDLENGTH_8B;
+ 803077a:	4b23      	ldr	r3, [pc, #140]	@ (8030808 <MX_LPUART1_UART_Init+0xa0>)
+ 803077c:	2200      	movs	r2, #0
+ 803077e:	609a      	str	r2, [r3, #8]
+  hlpuart1.Init.StopBits = UART_STOPBITS_1;
+ 8030780:	4b21      	ldr	r3, [pc, #132]	@ (8030808 <MX_LPUART1_UART_Init+0xa0>)
+ 8030782:	2200      	movs	r2, #0
+ 8030784:	60da      	str	r2, [r3, #12]
+  hlpuart1.Init.Parity = UART_PARITY_NONE;
+ 8030786:	4b20      	ldr	r3, [pc, #128]	@ (8030808 <MX_LPUART1_UART_Init+0xa0>)
+ 8030788:	2200      	movs	r2, #0
+ 803078a:	611a      	str	r2, [r3, #16]
+  hlpuart1.Init.Mode = UART_MODE_TX_RX;
+ 803078c:	4b1e      	ldr	r3, [pc, #120]	@ (8030808 <MX_LPUART1_UART_Init+0xa0>)
+ 803078e:	220c      	movs	r2, #12
+ 8030790:	615a      	str	r2, [r3, #20]
+  hlpuart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+ 8030792:	4b1d      	ldr	r3, [pc, #116]	@ (8030808 <MX_LPUART1_UART_Init+0xa0>)
+ 8030794:	2200      	movs	r2, #0
+ 8030796:	619a      	str	r2, [r3, #24]
+  hlpuart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+ 8030798:	4b1b      	ldr	r3, [pc, #108]	@ (8030808 <MX_LPUART1_UART_Init+0xa0>)
+ 803079a:	2200      	movs	r2, #0
+ 803079c:	621a      	str	r2, [r3, #32]
+  hlpuart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+ 803079e:	4b1a      	ldr	r3, [pc, #104]	@ (8030808 <MX_LPUART1_UART_Init+0xa0>)
+ 80307a0:	2200      	movs	r2, #0
+ 80307a2:	625a      	str	r2, [r3, #36]	@ 0x24
+  hlpuart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_RXOVERRUNDISABLE_INIT|UART_ADVFEATURE_DMADISABLEONERROR_INIT;
+ 80307a4:	4b18      	ldr	r3, [pc, #96]	@ (8030808 <MX_LPUART1_UART_Init+0xa0>)
+ 80307a6:	2230      	movs	r2, #48	@ 0x30
+ 80307a8:	629a      	str	r2, [r3, #40]	@ 0x28
+  hlpuart1.AdvancedInit.OverrunDisable = UART_ADVFEATURE_OVERRUN_DISABLE;
+ 80307aa:	4b17      	ldr	r3, [pc, #92]	@ (8030808 <MX_LPUART1_UART_Init+0xa0>)
+ 80307ac:	f44f 5280 	mov.w	r2, #4096	@ 0x1000
+ 80307b0:	63da      	str	r2, [r3, #60]	@ 0x3c
+  hlpuart1.AdvancedInit.DMADisableonRxError = UART_ADVFEATURE_DMA_DISABLEONRXERROR;
+ 80307b2:	4b15      	ldr	r3, [pc, #84]	@ (8030808 <MX_LPUART1_UART_Init+0xa0>)
+ 80307b4:	f44f 5200 	mov.w	r2, #8192	@ 0x2000
+ 80307b8:	641a      	str	r2, [r3, #64]	@ 0x40
+  hlpuart1.FifoMode = UART_FIFOMODE_DISABLE;
+ 80307ba:	4b13      	ldr	r3, [pc, #76]	@ (8030808 <MX_LPUART1_UART_Init+0xa0>)
+ 80307bc:	2200      	movs	r2, #0
+ 80307be:	665a      	str	r2, [r3, #100]	@ 0x64
+  if (HAL_UART_Init(&hlpuart1) != HAL_OK)
+ 80307c0:	4811      	ldr	r0, [pc, #68]	@ (8030808 <MX_LPUART1_UART_Init+0xa0>)
+ 80307c2:	f00c fe45 	bl	803d450 <HAL_UART_Init>
+ 80307c6:	4603      	mov	r3, r0
+ 80307c8:	2b00      	cmp	r3, #0
+ 80307ca:	d001      	beq.n	80307d0 <MX_LPUART1_UART_Init+0x68>
+  {
+    Error_Handler();
+ 80307cc:	f7ff f95c 	bl	802fa88 <Error_Handler>
+  }
+  if (HAL_UARTEx_SetTxFifoThreshold(&hlpuart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
+ 80307d0:	2100      	movs	r1, #0
+ 80307d2:	480d      	ldr	r0, [pc, #52]	@ (8030808 <MX_LPUART1_UART_Init+0xa0>)
+ 80307d4:	f00f fb34 	bl	803fe40 <HAL_UARTEx_SetTxFifoThreshold>
+ 80307d8:	4603      	mov	r3, r0
+ 80307da:	2b00      	cmp	r3, #0
+ 80307dc:	d001      	beq.n	80307e2 <MX_LPUART1_UART_Init+0x7a>
+  {
+    Error_Handler();
+ 80307de:	f7ff f953 	bl	802fa88 <Error_Handler>
+  }
+  if (HAL_UARTEx_SetRxFifoThreshold(&hlpuart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
+ 80307e2:	2100      	movs	r1, #0
+ 80307e4:	4808      	ldr	r0, [pc, #32]	@ (8030808 <MX_LPUART1_UART_Init+0xa0>)
+ 80307e6:	f00f fb69 	bl	803febc <HAL_UARTEx_SetRxFifoThreshold>
+ 80307ea:	4603      	mov	r3, r0
+ 80307ec:	2b00      	cmp	r3, #0
+ 80307ee:	d001      	beq.n	80307f4 <MX_LPUART1_UART_Init+0x8c>
+  {
+    Error_Handler();
+ 80307f0:	f7ff f94a 	bl	802fa88 <Error_Handler>
+  }
+  if (HAL_UARTEx_DisableFifoMode(&hlpuart1) != HAL_OK)
+ 80307f4:	4804      	ldr	r0, [pc, #16]	@ (8030808 <MX_LPUART1_UART_Init+0xa0>)
+ 80307f6:	f00f faea 	bl	803fdce <HAL_UARTEx_DisableFifoMode>
+ 80307fa:	4603      	mov	r3, r0
+ 80307fc:	2b00      	cmp	r3, #0
+ 80307fe:	d001      	beq.n	8030804 <MX_LPUART1_UART_Init+0x9c>
+  {
+    Error_Handler();
+ 8030800:	f7ff f942 	bl	802fa88 <Error_Handler>
+  }
+  /* USER CODE BEGIN LPUART1_Init 2 */
+
+  /* USER CODE END LPUART1_Init 2 */
+
+}
+ 8030804:	bf00      	nop
+ 8030806:	bd80      	pop	{r7, pc}
+ 8030808:	2400aa90 	.word	0x2400aa90
+ 803080c:	58000c00 	.word	0x58000c00
+
+08030810 <MX_UART4_Init>:
+/* UART4 init function */
+void MX_UART4_Init(void)
+{
+ 8030810:	b580      	push	{r7, lr}
+ 8030812:	af00      	add	r7, sp, #0
+  /* USER CODE END UART4_Init 0 */
+
+  /* USER CODE BEGIN UART4_Init 1 */
+
+  /* USER CODE END UART4_Init 1 */
+  huart4.Instance = UART4;
+ 8030814:	4b22      	ldr	r3, [pc, #136]	@ (80308a0 <MX_UART4_Init+0x90>)
+ 8030816:	4a23      	ldr	r2, [pc, #140]	@ (80308a4 <MX_UART4_Init+0x94>)
+ 8030818:	601a      	str	r2, [r3, #0]
+  huart4.Init.BaudRate = 57600;
+ 803081a:	4b21      	ldr	r3, [pc, #132]	@ (80308a0 <MX_UART4_Init+0x90>)
+ 803081c:	f44f 4261 	mov.w	r2, #57600	@ 0xe100
+ 8030820:	605a      	str	r2, [r3, #4]
+  huart4.Init.WordLength = UART_WORDLENGTH_8B;
+ 8030822:	4b1f      	ldr	r3, [pc, #124]	@ (80308a0 <MX_UART4_Init+0x90>)
+ 8030824:	2200      	movs	r2, #0
+ 8030826:	609a      	str	r2, [r3, #8]
+  huart4.Init.StopBits = UART_STOPBITS_1;
+ 8030828:	4b1d      	ldr	r3, [pc, #116]	@ (80308a0 <MX_UART4_Init+0x90>)
+ 803082a:	2200      	movs	r2, #0
+ 803082c:	60da      	str	r2, [r3, #12]
+  huart4.Init.Parity = UART_PARITY_NONE;
+ 803082e:	4b1c      	ldr	r3, [pc, #112]	@ (80308a0 <MX_UART4_Init+0x90>)
+ 8030830:	2200      	movs	r2, #0
+ 8030832:	611a      	str	r2, [r3, #16]
+  huart4.Init.Mode = UART_MODE_TX_RX;
+ 8030834:	4b1a      	ldr	r3, [pc, #104]	@ (80308a0 <MX_UART4_Init+0x90>)
+ 8030836:	220c      	movs	r2, #12
+ 8030838:	615a      	str	r2, [r3, #20]
+  huart4.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+ 803083a:	4b19      	ldr	r3, [pc, #100]	@ (80308a0 <MX_UART4_Init+0x90>)
+ 803083c:	2200      	movs	r2, #0
+ 803083e:	619a      	str	r2, [r3, #24]
+  huart4.Init.OverSampling = UART_OVERSAMPLING_16;
+ 8030840:	4b17      	ldr	r3, [pc, #92]	@ (80308a0 <MX_UART4_Init+0x90>)
+ 8030842:	2200      	movs	r2, #0
+ 8030844:	61da      	str	r2, [r3, #28]
+  huart4.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+ 8030846:	4b16      	ldr	r3, [pc, #88]	@ (80308a0 <MX_UART4_Init+0x90>)
+ 8030848:	2200      	movs	r2, #0
+ 803084a:	621a      	str	r2, [r3, #32]
+  huart4.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+ 803084c:	4b14      	ldr	r3, [pc, #80]	@ (80308a0 <MX_UART4_Init+0x90>)
+ 803084e:	2200      	movs	r2, #0
+ 8030850:	625a      	str	r2, [r3, #36]	@ 0x24
+  huart4.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+ 8030852:	4b13      	ldr	r3, [pc, #76]	@ (80308a0 <MX_UART4_Init+0x90>)
+ 8030854:	2200      	movs	r2, #0
+ 8030856:	629a      	str	r2, [r3, #40]	@ 0x28
+  if (HAL_UART_Init(&huart4) != HAL_OK)
+ 8030858:	4811      	ldr	r0, [pc, #68]	@ (80308a0 <MX_UART4_Init+0x90>)
+ 803085a:	f00c fdf9 	bl	803d450 <HAL_UART_Init>
+ 803085e:	4603      	mov	r3, r0
+ 8030860:	2b00      	cmp	r3, #0
+ 8030862:	d001      	beq.n	8030868 <MX_UART4_Init+0x58>
+  {
+    Error_Handler();
+ 8030864:	f7ff f910 	bl	802fa88 <Error_Handler>
+  }
+  if (HAL_UARTEx_SetTxFifoThreshold(&huart4, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
+ 8030868:	2100      	movs	r1, #0
+ 803086a:	480d      	ldr	r0, [pc, #52]	@ (80308a0 <MX_UART4_Init+0x90>)
+ 803086c:	f00f fae8 	bl	803fe40 <HAL_UARTEx_SetTxFifoThreshold>
+ 8030870:	4603      	mov	r3, r0
+ 8030872:	2b00      	cmp	r3, #0
+ 8030874:	d001      	beq.n	803087a <MX_UART4_Init+0x6a>
+  {
+    Error_Handler();
+ 8030876:	f7ff f907 	bl	802fa88 <Error_Handler>
+  }
+  if (HAL_UARTEx_SetRxFifoThreshold(&huart4, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
+ 803087a:	2100      	movs	r1, #0
+ 803087c:	4808      	ldr	r0, [pc, #32]	@ (80308a0 <MX_UART4_Init+0x90>)
+ 803087e:	f00f fb1d 	bl	803febc <HAL_UARTEx_SetRxFifoThreshold>
+ 8030882:	4603      	mov	r3, r0
+ 8030884:	2b00      	cmp	r3, #0
+ 8030886:	d001      	beq.n	803088c <MX_UART4_Init+0x7c>
+  {
+    Error_Handler();
+ 8030888:	f7ff f8fe 	bl	802fa88 <Error_Handler>
+  }
+  if (HAL_UARTEx_DisableFifoMode(&huart4) != HAL_OK)
+ 803088c:	4804      	ldr	r0, [pc, #16]	@ (80308a0 <MX_UART4_Init+0x90>)
+ 803088e:	f00f fa9e 	bl	803fdce <HAL_UARTEx_DisableFifoMode>
+ 8030892:	4603      	mov	r3, r0
+ 8030894:	2b00      	cmp	r3, #0
+ 8030896:	d001      	beq.n	803089c <MX_UART4_Init+0x8c>
+  {
+    Error_Handler();
+ 8030898:	f7ff f8f6 	bl	802fa88 <Error_Handler>
+  }
+  /* USER CODE BEGIN UART4_Init 2 */
+
+  /* USER CODE END UART4_Init 2 */
+
+}
+ 803089c:	bf00      	nop
+ 803089e:	bd80      	pop	{r7, pc}
+ 80308a0:	2400ab24 	.word	0x2400ab24
+ 80308a4:	40004c00 	.word	0x40004c00
+
+080308a8 <MX_UART5_Init>:
+/* UART5 init function */
+void MX_UART5_Init(void)
+{
+ 80308a8:	b580      	push	{r7, lr}
+ 80308aa:	af00      	add	r7, sp, #0
+  /* USER CODE END UART5_Init 0 */
+
+  /* USER CODE BEGIN UART5_Init 1 */
+
+  /* USER CODE END UART5_Init 1 */
+  huart5.Instance = UART5;
+ 80308ac:	4b27      	ldr	r3, [pc, #156]	@ (803094c <MX_UART5_Init+0xa4>)
+ 80308ae:	4a28      	ldr	r2, [pc, #160]	@ (8030950 <MX_UART5_Init+0xa8>)
+ 80308b0:	601a      	str	r2, [r3, #0]
+  huart5.Init.BaudRate = 100000;
+ 80308b2:	4b26      	ldr	r3, [pc, #152]	@ (803094c <MX_UART5_Init+0xa4>)
+ 80308b4:	4a27      	ldr	r2, [pc, #156]	@ (8030954 <MX_UART5_Init+0xac>)
+ 80308b6:	605a      	str	r2, [r3, #4]
+  huart5.Init.WordLength = UART_WORDLENGTH_9B;
+ 80308b8:	4b24      	ldr	r3, [pc, #144]	@ (803094c <MX_UART5_Init+0xa4>)
+ 80308ba:	f44f 5280 	mov.w	r2, #4096	@ 0x1000
+ 80308be:	609a      	str	r2, [r3, #8]
+  huart5.Init.StopBits = UART_STOPBITS_1;
+ 80308c0:	4b22      	ldr	r3, [pc, #136]	@ (803094c <MX_UART5_Init+0xa4>)
+ 80308c2:	2200      	movs	r2, #0
+ 80308c4:	60da      	str	r2, [r3, #12]
+  huart5.Init.Parity = UART_PARITY_EVEN;
+ 80308c6:	4b21      	ldr	r3, [pc, #132]	@ (803094c <MX_UART5_Init+0xa4>)
+ 80308c8:	f44f 6280 	mov.w	r2, #1024	@ 0x400
+ 80308cc:	611a      	str	r2, [r3, #16]
+  huart5.Init.Mode = UART_MODE_TX_RX;
+ 80308ce:	4b1f      	ldr	r3, [pc, #124]	@ (803094c <MX_UART5_Init+0xa4>)
+ 80308d0:	220c      	movs	r2, #12
+ 80308d2:	615a      	str	r2, [r3, #20]
+  huart5.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+ 80308d4:	4b1d      	ldr	r3, [pc, #116]	@ (803094c <MX_UART5_Init+0xa4>)
+ 80308d6:	2200      	movs	r2, #0
+ 80308d8:	619a      	str	r2, [r3, #24]
+  huart5.Init.OverSampling = UART_OVERSAMPLING_16;
+ 80308da:	4b1c      	ldr	r3, [pc, #112]	@ (803094c <MX_UART5_Init+0xa4>)
+ 80308dc:	2200      	movs	r2, #0
+ 80308de:	61da      	str	r2, [r3, #28]
+  huart5.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+ 80308e0:	4b1a      	ldr	r3, [pc, #104]	@ (803094c <MX_UART5_Init+0xa4>)
+ 80308e2:	2200      	movs	r2, #0
+ 80308e4:	621a      	str	r2, [r3, #32]
+  huart5.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+ 80308e6:	4b19      	ldr	r3, [pc, #100]	@ (803094c <MX_UART5_Init+0xa4>)
+ 80308e8:	2200      	movs	r2, #0
+ 80308ea:	625a      	str	r2, [r3, #36]	@ 0x24
+  huart5.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_RXOVERRUNDISABLE_INIT|UART_ADVFEATURE_DMADISABLEONERROR_INIT;
+ 80308ec:	4b17      	ldr	r3, [pc, #92]	@ (803094c <MX_UART5_Init+0xa4>)
+ 80308ee:	2230      	movs	r2, #48	@ 0x30
+ 80308f0:	629a      	str	r2, [r3, #40]	@ 0x28
+  huart5.AdvancedInit.OverrunDisable = UART_ADVFEATURE_OVERRUN_DISABLE;
+ 80308f2:	4b16      	ldr	r3, [pc, #88]	@ (803094c <MX_UART5_Init+0xa4>)
+ 80308f4:	f44f 5280 	mov.w	r2, #4096	@ 0x1000
+ 80308f8:	63da      	str	r2, [r3, #60]	@ 0x3c
+  huart5.AdvancedInit.DMADisableonRxError = UART_ADVFEATURE_DMA_DISABLEONRXERROR;
+ 80308fa:	4b14      	ldr	r3, [pc, #80]	@ (803094c <MX_UART5_Init+0xa4>)
+ 80308fc:	f44f 5200 	mov.w	r2, #8192	@ 0x2000
+ 8030900:	641a      	str	r2, [r3, #64]	@ 0x40
+  if (HAL_UART_Init(&huart5) != HAL_OK)
+ 8030902:	4812      	ldr	r0, [pc, #72]	@ (803094c <MX_UART5_Init+0xa4>)
+ 8030904:	f00c fda4 	bl	803d450 <HAL_UART_Init>
+ 8030908:	4603      	mov	r3, r0
+ 803090a:	2b00      	cmp	r3, #0
+ 803090c:	d001      	beq.n	8030912 <MX_UART5_Init+0x6a>
+  {
+    Error_Handler();
+ 803090e:	f7ff f8bb 	bl	802fa88 <Error_Handler>
+  }
+  if (HAL_UARTEx_SetTxFifoThreshold(&huart5, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
+ 8030912:	2100      	movs	r1, #0
+ 8030914:	480d      	ldr	r0, [pc, #52]	@ (803094c <MX_UART5_Init+0xa4>)
+ 8030916:	f00f fa93 	bl	803fe40 <HAL_UARTEx_SetTxFifoThreshold>
+ 803091a:	4603      	mov	r3, r0
+ 803091c:	2b00      	cmp	r3, #0
+ 803091e:	d001      	beq.n	8030924 <MX_UART5_Init+0x7c>
+  {
+    Error_Handler();
+ 8030920:	f7ff f8b2 	bl	802fa88 <Error_Handler>
+  }
+  if (HAL_UARTEx_SetRxFifoThreshold(&huart5, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
+ 8030924:	2100      	movs	r1, #0
+ 8030926:	4809      	ldr	r0, [pc, #36]	@ (803094c <MX_UART5_Init+0xa4>)
+ 8030928:	f00f fac8 	bl	803febc <HAL_UARTEx_SetRxFifoThreshold>
+ 803092c:	4603      	mov	r3, r0
+ 803092e:	2b00      	cmp	r3, #0
+ 8030930:	d001      	beq.n	8030936 <MX_UART5_Init+0x8e>
+  {
+    Error_Handler();
+ 8030932:	f7ff f8a9 	bl	802fa88 <Error_Handler>
+  }
+  if (HAL_UARTEx_DisableFifoMode(&huart5) != HAL_OK)
+ 8030936:	4805      	ldr	r0, [pc, #20]	@ (803094c <MX_UART5_Init+0xa4>)
+ 8030938:	f00f fa49 	bl	803fdce <HAL_UARTEx_DisableFifoMode>
+ 803093c:	4603      	mov	r3, r0
+ 803093e:	2b00      	cmp	r3, #0
+ 8030940:	d001      	beq.n	8030946 <MX_UART5_Init+0x9e>
+  {
+    Error_Handler();
+ 8030942:	f7ff f8a1 	bl	802fa88 <Error_Handler>
+  }
+  /* USER CODE BEGIN UART5_Init 2 */
+
+  /* USER CODE END UART5_Init 2 */
+
+}
+ 8030946:	bf00      	nop
+ 8030948:	bd80      	pop	{r7, pc}
+ 803094a:	bf00      	nop
+ 803094c:	2400abb8 	.word	0x2400abb8
+ 8030950:	40005000 	.word	0x40005000
+ 8030954:	000186a0 	.word	0x000186a0
+
+08030958 <MX_UART7_Init>:
+/* UART7 init function */
+void MX_UART7_Init(void)
+{
+ 8030958:	b580      	push	{r7, lr}
+ 803095a:	af00      	add	r7, sp, #0
+  /* USER CODE END UART7_Init 0 */
+
+  /* USER CODE BEGIN UART7_Init 1 */
+
+  /* USER CODE END UART7_Init 1 */
+  huart7.Instance = UART7;
+ 803095c:	4b26      	ldr	r3, [pc, #152]	@ (80309f8 <MX_UART7_Init+0xa0>)
+ 803095e:	4a27      	ldr	r2, [pc, #156]	@ (80309fc <MX_UART7_Init+0xa4>)
+ 8030960:	601a      	str	r2, [r3, #0]
+  huart7.Init.BaudRate = 115200;
+ 8030962:	4b25      	ldr	r3, [pc, #148]	@ (80309f8 <MX_UART7_Init+0xa0>)
+ 8030964:	f44f 32e1 	mov.w	r2, #115200	@ 0x1c200
+ 8030968:	605a      	str	r2, [r3, #4]
+  huart7.Init.WordLength = UART_WORDLENGTH_8B;
+ 803096a:	4b23      	ldr	r3, [pc, #140]	@ (80309f8 <MX_UART7_Init+0xa0>)
+ 803096c:	2200      	movs	r2, #0
+ 803096e:	609a      	str	r2, [r3, #8]
+  huart7.Init.StopBits = UART_STOPBITS_1;
+ 8030970:	4b21      	ldr	r3, [pc, #132]	@ (80309f8 <MX_UART7_Init+0xa0>)
+ 8030972:	2200      	movs	r2, #0
+ 8030974:	60da      	str	r2, [r3, #12]
+  huart7.Init.Parity = UART_PARITY_NONE;
+ 8030976:	4b20      	ldr	r3, [pc, #128]	@ (80309f8 <MX_UART7_Init+0xa0>)
+ 8030978:	2200      	movs	r2, #0
+ 803097a:	611a      	str	r2, [r3, #16]
+  huart7.Init.Mode = UART_MODE_TX_RX;
+ 803097c:	4b1e      	ldr	r3, [pc, #120]	@ (80309f8 <MX_UART7_Init+0xa0>)
+ 803097e:	220c      	movs	r2, #12
+ 8030980:	615a      	str	r2, [r3, #20]
+  huart7.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+ 8030982:	4b1d      	ldr	r3, [pc, #116]	@ (80309f8 <MX_UART7_Init+0xa0>)
+ 8030984:	2200      	movs	r2, #0
+ 8030986:	619a      	str	r2, [r3, #24]
+  huart7.Init.OverSampling = UART_OVERSAMPLING_16;
+ 8030988:	4b1b      	ldr	r3, [pc, #108]	@ (80309f8 <MX_UART7_Init+0xa0>)
+ 803098a:	2200      	movs	r2, #0
+ 803098c:	61da      	str	r2, [r3, #28]
+  huart7.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+ 803098e:	4b1a      	ldr	r3, [pc, #104]	@ (80309f8 <MX_UART7_Init+0xa0>)
+ 8030990:	2200      	movs	r2, #0
+ 8030992:	621a      	str	r2, [r3, #32]
+  huart7.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+ 8030994:	4b18      	ldr	r3, [pc, #96]	@ (80309f8 <MX_UART7_Init+0xa0>)
+ 8030996:	2200      	movs	r2, #0
+ 8030998:	625a      	str	r2, [r3, #36]	@ 0x24
+  huart7.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_RXOVERRUNDISABLE_INIT|UART_ADVFEATURE_DMADISABLEONERROR_INIT;
+ 803099a:	4b17      	ldr	r3, [pc, #92]	@ (80309f8 <MX_UART7_Init+0xa0>)
+ 803099c:	2230      	movs	r2, #48	@ 0x30
+ 803099e:	629a      	str	r2, [r3, #40]	@ 0x28
+  huart7.AdvancedInit.OverrunDisable = UART_ADVFEATURE_OVERRUN_DISABLE;
+ 80309a0:	4b15      	ldr	r3, [pc, #84]	@ (80309f8 <MX_UART7_Init+0xa0>)
+ 80309a2:	f44f 5280 	mov.w	r2, #4096	@ 0x1000
+ 80309a6:	63da      	str	r2, [r3, #60]	@ 0x3c
+  huart7.AdvancedInit.DMADisableonRxError = UART_ADVFEATURE_DMA_DISABLEONRXERROR;
+ 80309a8:	4b13      	ldr	r3, [pc, #76]	@ (80309f8 <MX_UART7_Init+0xa0>)
+ 80309aa:	f44f 5200 	mov.w	r2, #8192	@ 0x2000
+ 80309ae:	641a      	str	r2, [r3, #64]	@ 0x40
+  if (HAL_UART_Init(&huart7) != HAL_OK)
+ 80309b0:	4811      	ldr	r0, [pc, #68]	@ (80309f8 <MX_UART7_Init+0xa0>)
+ 80309b2:	f00c fd4d 	bl	803d450 <HAL_UART_Init>
+ 80309b6:	4603      	mov	r3, r0
+ 80309b8:	2b00      	cmp	r3, #0
+ 80309ba:	d001      	beq.n	80309c0 <MX_UART7_Init+0x68>
+  {
+    Error_Handler();
+ 80309bc:	f7ff f864 	bl	802fa88 <Error_Handler>
+  }
+  if (HAL_UARTEx_SetTxFifoThreshold(&huart7, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
+ 80309c0:	2100      	movs	r1, #0
+ 80309c2:	480d      	ldr	r0, [pc, #52]	@ (80309f8 <MX_UART7_Init+0xa0>)
+ 80309c4:	f00f fa3c 	bl	803fe40 <HAL_UARTEx_SetTxFifoThreshold>
+ 80309c8:	4603      	mov	r3, r0
+ 80309ca:	2b00      	cmp	r3, #0
+ 80309cc:	d001      	beq.n	80309d2 <MX_UART7_Init+0x7a>
+  {
+    Error_Handler();
+ 80309ce:	f7ff f85b 	bl	802fa88 <Error_Handler>
+  }
+  if (HAL_UARTEx_SetRxFifoThreshold(&huart7, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
+ 80309d2:	2100      	movs	r1, #0
+ 80309d4:	4808      	ldr	r0, [pc, #32]	@ (80309f8 <MX_UART7_Init+0xa0>)
+ 80309d6:	f00f fa71 	bl	803febc <HAL_UARTEx_SetRxFifoThreshold>
+ 80309da:	4603      	mov	r3, r0
+ 80309dc:	2b00      	cmp	r3, #0
+ 80309de:	d001      	beq.n	80309e4 <MX_UART7_Init+0x8c>
+  {
+    Error_Handler();
+ 80309e0:	f7ff f852 	bl	802fa88 <Error_Handler>
+  }
+  if (HAL_UARTEx_DisableFifoMode(&huart7) != HAL_OK)
+ 80309e4:	4804      	ldr	r0, [pc, #16]	@ (80309f8 <MX_UART7_Init+0xa0>)
+ 80309e6:	f00f f9f2 	bl	803fdce <HAL_UARTEx_DisableFifoMode>
+ 80309ea:	4603      	mov	r3, r0
+ 80309ec:	2b00      	cmp	r3, #0
+ 80309ee:	d001      	beq.n	80309f4 <MX_UART7_Init+0x9c>
+  {
+    Error_Handler();
+ 80309f0:	f7ff f84a 	bl	802fa88 <Error_Handler>
+  }
+  /* USER CODE BEGIN UART7_Init 2 */
+
+  /* USER CODE END UART7_Init 2 */
+
+}
+ 80309f4:	bf00      	nop
+ 80309f6:	bd80      	pop	{r7, pc}
+ 80309f8:	2400ac4c 	.word	0x2400ac4c
+ 80309fc:	40007800 	.word	0x40007800
+
+08030a00 <MX_USART1_UART_Init>:
+/* USART1 init function */
+
+void MX_USART1_UART_Init(void)
+{
+ 8030a00:	b580      	push	{r7, lr}
+ 8030a02:	af00      	add	r7, sp, #0
+  /* USER CODE END USART1_Init 0 */
+
+  /* USER CODE BEGIN USART1_Init 1 */
+
+  /* USER CODE END USART1_Init 1 */
+  huart1.Instance = USART1;
+ 8030a04:	4b26      	ldr	r3, [pc, #152]	@ (8030aa0 <MX_USART1_UART_Init+0xa0>)
+ 8030a06:	4a27      	ldr	r2, [pc, #156]	@ (8030aa4 <MX_USART1_UART_Init+0xa4>)
+ 8030a08:	601a      	str	r2, [r3, #0]
+  huart1.Init.BaudRate = 115200;
+ 8030a0a:	4b25      	ldr	r3, [pc, #148]	@ (8030aa0 <MX_USART1_UART_Init+0xa0>)
+ 8030a0c:	f44f 32e1 	mov.w	r2, #115200	@ 0x1c200
+ 8030a10:	605a      	str	r2, [r3, #4]
+  huart1.Init.WordLength = UART_WORDLENGTH_8B;
+ 8030a12:	4b23      	ldr	r3, [pc, #140]	@ (8030aa0 <MX_USART1_UART_Init+0xa0>)
+ 8030a14:	2200      	movs	r2, #0
+ 8030a16:	609a      	str	r2, [r3, #8]
+  huart1.Init.StopBits = UART_STOPBITS_1;
+ 8030a18:	4b21      	ldr	r3, [pc, #132]	@ (8030aa0 <MX_USART1_UART_Init+0xa0>)
+ 8030a1a:	2200      	movs	r2, #0
+ 8030a1c:	60da      	str	r2, [r3, #12]
+  huart1.Init.Parity = UART_PARITY_NONE;
+ 8030a1e:	4b20      	ldr	r3, [pc, #128]	@ (8030aa0 <MX_USART1_UART_Init+0xa0>)
+ 8030a20:	2200      	movs	r2, #0
+ 8030a22:	611a      	str	r2, [r3, #16]
+  huart1.Init.Mode = UART_MODE_TX_RX;
+ 8030a24:	4b1e      	ldr	r3, [pc, #120]	@ (8030aa0 <MX_USART1_UART_Init+0xa0>)
+ 8030a26:	220c      	movs	r2, #12
+ 8030a28:	615a      	str	r2, [r3, #20]
+  huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+ 8030a2a:	4b1d      	ldr	r3, [pc, #116]	@ (8030aa0 <MX_USART1_UART_Init+0xa0>)
+ 8030a2c:	2200      	movs	r2, #0
+ 8030a2e:	619a      	str	r2, [r3, #24]
+  huart1.Init.OverSampling = UART_OVERSAMPLING_16;
+ 8030a30:	4b1b      	ldr	r3, [pc, #108]	@ (8030aa0 <MX_USART1_UART_Init+0xa0>)
+ 8030a32:	2200      	movs	r2, #0
+ 8030a34:	61da      	str	r2, [r3, #28]
+  huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+ 8030a36:	4b1a      	ldr	r3, [pc, #104]	@ (8030aa0 <MX_USART1_UART_Init+0xa0>)
+ 8030a38:	2200      	movs	r2, #0
+ 8030a3a:	621a      	str	r2, [r3, #32]
+  huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+ 8030a3c:	4b18      	ldr	r3, [pc, #96]	@ (8030aa0 <MX_USART1_UART_Init+0xa0>)
+ 8030a3e:	2200      	movs	r2, #0
+ 8030a40:	625a      	str	r2, [r3, #36]	@ 0x24
+  huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_RXOVERRUNDISABLE_INIT|UART_ADVFEATURE_DMADISABLEONERROR_INIT;
+ 8030a42:	4b17      	ldr	r3, [pc, #92]	@ (8030aa0 <MX_USART1_UART_Init+0xa0>)
+ 8030a44:	2230      	movs	r2, #48	@ 0x30
+ 8030a46:	629a      	str	r2, [r3, #40]	@ 0x28
+  huart1.AdvancedInit.OverrunDisable = UART_ADVFEATURE_OVERRUN_DISABLE;
+ 8030a48:	4b15      	ldr	r3, [pc, #84]	@ (8030aa0 <MX_USART1_UART_Init+0xa0>)
+ 8030a4a:	f44f 5280 	mov.w	r2, #4096	@ 0x1000
+ 8030a4e:	63da      	str	r2, [r3, #60]	@ 0x3c
+  huart1.AdvancedInit.DMADisableonRxError = UART_ADVFEATURE_DMA_DISABLEONRXERROR;
+ 8030a50:	4b13      	ldr	r3, [pc, #76]	@ (8030aa0 <MX_USART1_UART_Init+0xa0>)
+ 8030a52:	f44f 5200 	mov.w	r2, #8192	@ 0x2000
+ 8030a56:	641a      	str	r2, [r3, #64]	@ 0x40
+  if (HAL_UART_Init(&huart1) != HAL_OK)
+ 8030a58:	4811      	ldr	r0, [pc, #68]	@ (8030aa0 <MX_USART1_UART_Init+0xa0>)
+ 8030a5a:	f00c fcf9 	bl	803d450 <HAL_UART_Init>
+ 8030a5e:	4603      	mov	r3, r0
+ 8030a60:	2b00      	cmp	r3, #0
+ 8030a62:	d001      	beq.n	8030a68 <MX_USART1_UART_Init+0x68>
+  {
+    Error_Handler();
+ 8030a64:	f7ff f810 	bl	802fa88 <Error_Handler>
+  }
+  if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
+ 8030a68:	2100      	movs	r1, #0
+ 8030a6a:	480d      	ldr	r0, [pc, #52]	@ (8030aa0 <MX_USART1_UART_Init+0xa0>)
+ 8030a6c:	f00f f9e8 	bl	803fe40 <HAL_UARTEx_SetTxFifoThreshold>
+ 8030a70:	4603      	mov	r3, r0
+ 8030a72:	2b00      	cmp	r3, #0
+ 8030a74:	d001      	beq.n	8030a7a <MX_USART1_UART_Init+0x7a>
+  {
+    Error_Handler();
+ 8030a76:	f7ff f807 	bl	802fa88 <Error_Handler>
+  }
+  if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
+ 8030a7a:	2100      	movs	r1, #0
+ 8030a7c:	4808      	ldr	r0, [pc, #32]	@ (8030aa0 <MX_USART1_UART_Init+0xa0>)
+ 8030a7e:	f00f fa1d 	bl	803febc <HAL_UARTEx_SetRxFifoThreshold>
+ 8030a82:	4603      	mov	r3, r0
+ 8030a84:	2b00      	cmp	r3, #0
+ 8030a86:	d001      	beq.n	8030a8c <MX_USART1_UART_Init+0x8c>
+  {
+    Error_Handler();
+ 8030a88:	f7fe fffe 	bl	802fa88 <Error_Handler>
+  }
+  if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK)
+ 8030a8c:	4804      	ldr	r0, [pc, #16]	@ (8030aa0 <MX_USART1_UART_Init+0xa0>)
+ 8030a8e:	f00f f99e 	bl	803fdce <HAL_UARTEx_DisableFifoMode>
+ 8030a92:	4603      	mov	r3, r0
+ 8030a94:	2b00      	cmp	r3, #0
+ 8030a96:	d001      	beq.n	8030a9c <MX_USART1_UART_Init+0x9c>
+  {
+    Error_Handler();
+ 8030a98:	f7fe fff6 	bl	802fa88 <Error_Handler>
+  }
+  /* USER CODE BEGIN USART1_Init 2 */
+
+  /* USER CODE END USART1_Init 2 */
+
+}
+ 8030a9c:	bf00      	nop
+ 8030a9e:	bd80      	pop	{r7, pc}
+ 8030aa0:	2400ace0 	.word	0x2400ace0
+ 8030aa4:	40011000 	.word	0x40011000
+
+08030aa8 <MX_USART2_UART_Init>:
+/* USART2 init function */
+
+void MX_USART2_UART_Init(void)
+{
+ 8030aa8:	b580      	push	{r7, lr}
+ 8030aaa:	af00      	add	r7, sp, #0
+  /* USER CODE END USART2_Init 0 */
+
+  /* USER CODE BEGIN USART2_Init 1 */
+
+  /* USER CODE END USART2_Init 1 */
+  huart2.Instance = USART2;
+ 8030aac:	4b26      	ldr	r3, [pc, #152]	@ (8030b48 <MX_USART2_UART_Init+0xa0>)
+ 8030aae:	4a27      	ldr	r2, [pc, #156]	@ (8030b4c <MX_USART2_UART_Init+0xa4>)
+ 8030ab0:	601a      	str	r2, [r3, #0]
+  huart2.Init.BaudRate = 115200;
+ 8030ab2:	4b25      	ldr	r3, [pc, #148]	@ (8030b48 <MX_USART2_UART_Init+0xa0>)
+ 8030ab4:	f44f 32e1 	mov.w	r2, #115200	@ 0x1c200
+ 8030ab8:	605a      	str	r2, [r3, #4]
+  huart2.Init.WordLength = UART_WORDLENGTH_8B;
+ 8030aba:	4b23      	ldr	r3, [pc, #140]	@ (8030b48 <MX_USART2_UART_Init+0xa0>)
+ 8030abc:	2200      	movs	r2, #0
+ 8030abe:	609a      	str	r2, [r3, #8]
+  huart2.Init.StopBits = UART_STOPBITS_1;
+ 8030ac0:	4b21      	ldr	r3, [pc, #132]	@ (8030b48 <MX_USART2_UART_Init+0xa0>)
+ 8030ac2:	2200      	movs	r2, #0
+ 8030ac4:	60da      	str	r2, [r3, #12]
+  huart2.Init.Parity = UART_PARITY_NONE;
+ 8030ac6:	4b20      	ldr	r3, [pc, #128]	@ (8030b48 <MX_USART2_UART_Init+0xa0>)
+ 8030ac8:	2200      	movs	r2, #0
+ 8030aca:	611a      	str	r2, [r3, #16]
+  huart2.Init.Mode = UART_MODE_TX_RX;
+ 8030acc:	4b1e      	ldr	r3, [pc, #120]	@ (8030b48 <MX_USART2_UART_Init+0xa0>)
+ 8030ace:	220c      	movs	r2, #12
+ 8030ad0:	615a      	str	r2, [r3, #20]
+  huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+ 8030ad2:	4b1d      	ldr	r3, [pc, #116]	@ (8030b48 <MX_USART2_UART_Init+0xa0>)
+ 8030ad4:	2200      	movs	r2, #0
+ 8030ad6:	619a      	str	r2, [r3, #24]
+  huart2.Init.OverSampling = UART_OVERSAMPLING_16;
+ 8030ad8:	4b1b      	ldr	r3, [pc, #108]	@ (8030b48 <MX_USART2_UART_Init+0xa0>)
+ 8030ada:	2200      	movs	r2, #0
+ 8030adc:	61da      	str	r2, [r3, #28]
+  huart2.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+ 8030ade:	4b1a      	ldr	r3, [pc, #104]	@ (8030b48 <MX_USART2_UART_Init+0xa0>)
+ 8030ae0:	2200      	movs	r2, #0
+ 8030ae2:	621a      	str	r2, [r3, #32]
+  huart2.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+ 8030ae4:	4b18      	ldr	r3, [pc, #96]	@ (8030b48 <MX_USART2_UART_Init+0xa0>)
+ 8030ae6:	2200      	movs	r2, #0
+ 8030ae8:	625a      	str	r2, [r3, #36]	@ 0x24
+  huart2.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_RXOVERRUNDISABLE_INIT|UART_ADVFEATURE_DMADISABLEONERROR_INIT;
+ 8030aea:	4b17      	ldr	r3, [pc, #92]	@ (8030b48 <MX_USART2_UART_Init+0xa0>)
+ 8030aec:	2230      	movs	r2, #48	@ 0x30
+ 8030aee:	629a      	str	r2, [r3, #40]	@ 0x28
+  huart2.AdvancedInit.OverrunDisable = UART_ADVFEATURE_OVERRUN_DISABLE;
+ 8030af0:	4b15      	ldr	r3, [pc, #84]	@ (8030b48 <MX_USART2_UART_Init+0xa0>)
+ 8030af2:	f44f 5280 	mov.w	r2, #4096	@ 0x1000
+ 8030af6:	63da      	str	r2, [r3, #60]	@ 0x3c
+  huart2.AdvancedInit.DMADisableonRxError = UART_ADVFEATURE_DMA_DISABLEONRXERROR;
+ 8030af8:	4b13      	ldr	r3, [pc, #76]	@ (8030b48 <MX_USART2_UART_Init+0xa0>)
+ 8030afa:	f44f 5200 	mov.w	r2, #8192	@ 0x2000
+ 8030afe:	641a      	str	r2, [r3, #64]	@ 0x40
+  if (HAL_UART_Init(&huart2) != HAL_OK)
+ 8030b00:	4811      	ldr	r0, [pc, #68]	@ (8030b48 <MX_USART2_UART_Init+0xa0>)
+ 8030b02:	f00c fca5 	bl	803d450 <HAL_UART_Init>
+ 8030b06:	4603      	mov	r3, r0
+ 8030b08:	2b00      	cmp	r3, #0
+ 8030b0a:	d001      	beq.n	8030b10 <MX_USART2_UART_Init+0x68>
+  {
+    Error_Handler();
+ 8030b0c:	f7fe ffbc 	bl	802fa88 <Error_Handler>
+  }
+  if (HAL_UARTEx_SetTxFifoThreshold(&huart2, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
+ 8030b10:	2100      	movs	r1, #0
+ 8030b12:	480d      	ldr	r0, [pc, #52]	@ (8030b48 <MX_USART2_UART_Init+0xa0>)
+ 8030b14:	f00f f994 	bl	803fe40 <HAL_UARTEx_SetTxFifoThreshold>
+ 8030b18:	4603      	mov	r3, r0
+ 8030b1a:	2b00      	cmp	r3, #0
+ 8030b1c:	d001      	beq.n	8030b22 <MX_USART2_UART_Init+0x7a>
+  {
+    Error_Handler();
+ 8030b1e:	f7fe ffb3 	bl	802fa88 <Error_Handler>
+  }
+  if (HAL_UARTEx_SetRxFifoThreshold(&huart2, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
+ 8030b22:	2100      	movs	r1, #0
+ 8030b24:	4808      	ldr	r0, [pc, #32]	@ (8030b48 <MX_USART2_UART_Init+0xa0>)
+ 8030b26:	f00f f9c9 	bl	803febc <HAL_UARTEx_SetRxFifoThreshold>
+ 8030b2a:	4603      	mov	r3, r0
+ 8030b2c:	2b00      	cmp	r3, #0
+ 8030b2e:	d001      	beq.n	8030b34 <MX_USART2_UART_Init+0x8c>
+  {
+    Error_Handler();
+ 8030b30:	f7fe ffaa 	bl	802fa88 <Error_Handler>
+  }
+  if (HAL_UARTEx_DisableFifoMode(&huart2) != HAL_OK)
+ 8030b34:	4804      	ldr	r0, [pc, #16]	@ (8030b48 <MX_USART2_UART_Init+0xa0>)
+ 8030b36:	f00f f94a 	bl	803fdce <HAL_UARTEx_DisableFifoMode>
+ 8030b3a:	4603      	mov	r3, r0
+ 8030b3c:	2b00      	cmp	r3, #0
+ 8030b3e:	d001      	beq.n	8030b44 <MX_USART2_UART_Init+0x9c>
+  {
+    Error_Handler();
+ 8030b40:	f7fe ffa2 	bl	802fa88 <Error_Handler>
+
+
+
+  /* USER CODE END USART2_Init 2 */
+
+}
+ 8030b44:	bf00      	nop
+ 8030b46:	bd80      	pop	{r7, pc}
+ 8030b48:	2400ad74 	.word	0x2400ad74
+ 8030b4c:	40004400 	.word	0x40004400
+
+08030b50 <MX_USART3_UART_Init>:
+/* USART3 init function */
+
+void MX_USART3_UART_Init(void)
+{
+ 8030b50:	b580      	push	{r7, lr}
+ 8030b52:	af00      	add	r7, sp, #0
+  /* USER CODE END USART3_Init 0 */
+
+  /* USER CODE BEGIN USART3_Init 1 */
+
+  /* USER CODE END USART3_Init 1 */
+  huart3.Instance = USART3;
+ 8030b54:	4b27      	ldr	r3, [pc, #156]	@ (8030bf4 <MX_USART3_UART_Init+0xa4>)
+ 8030b56:	4a28      	ldr	r2, [pc, #160]	@ (8030bf8 <MX_USART3_UART_Init+0xa8>)
+ 8030b58:	601a      	str	r2, [r3, #0]
+  huart3.Init.BaudRate = 921600;
+ 8030b5a:	4b26      	ldr	r3, [pc, #152]	@ (8030bf4 <MX_USART3_UART_Init+0xa4>)
+ 8030b5c:	f44f 2261 	mov.w	r2, #921600	@ 0xe1000
+ 8030b60:	605a      	str	r2, [r3, #4]
+  huart3.Init.WordLength = UART_WORDLENGTH_9B;
+ 8030b62:	4b24      	ldr	r3, [pc, #144]	@ (8030bf4 <MX_USART3_UART_Init+0xa4>)
+ 8030b64:	f44f 5280 	mov.w	r2, #4096	@ 0x1000
+ 8030b68:	609a      	str	r2, [r3, #8]
+  huart3.Init.StopBits = UART_STOPBITS_1;
+ 8030b6a:	4b22      	ldr	r3, [pc, #136]	@ (8030bf4 <MX_USART3_UART_Init+0xa4>)
+ 8030b6c:	2200      	movs	r2, #0
+ 8030b6e:	60da      	str	r2, [r3, #12]
+  huart3.Init.Parity = UART_PARITY_EVEN;
+ 8030b70:	4b20      	ldr	r3, [pc, #128]	@ (8030bf4 <MX_USART3_UART_Init+0xa4>)
+ 8030b72:	f44f 6280 	mov.w	r2, #1024	@ 0x400
+ 8030b76:	611a      	str	r2, [r3, #16]
+  huart3.Init.Mode = UART_MODE_TX_RX;
+ 8030b78:	4b1e      	ldr	r3, [pc, #120]	@ (8030bf4 <MX_USART3_UART_Init+0xa4>)
+ 8030b7a:	220c      	movs	r2, #12
+ 8030b7c:	615a      	str	r2, [r3, #20]
+  huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+ 8030b7e:	4b1d      	ldr	r3, [pc, #116]	@ (8030bf4 <MX_USART3_UART_Init+0xa4>)
+ 8030b80:	2200      	movs	r2, #0
+ 8030b82:	619a      	str	r2, [r3, #24]
+  huart3.Init.OverSampling = UART_OVERSAMPLING_16;
+ 8030b84:	4b1b      	ldr	r3, [pc, #108]	@ (8030bf4 <MX_USART3_UART_Init+0xa4>)
+ 8030b86:	2200      	movs	r2, #0
+ 8030b88:	61da      	str	r2, [r3, #28]
+  huart3.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+ 8030b8a:	4b1a      	ldr	r3, [pc, #104]	@ (8030bf4 <MX_USART3_UART_Init+0xa4>)
+ 8030b8c:	2200      	movs	r2, #0
+ 8030b8e:	621a      	str	r2, [r3, #32]
+  huart3.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+ 8030b90:	4b18      	ldr	r3, [pc, #96]	@ (8030bf4 <MX_USART3_UART_Init+0xa4>)
+ 8030b92:	2200      	movs	r2, #0
+ 8030b94:	625a      	str	r2, [r3, #36]	@ 0x24
+  huart3.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_RXOVERRUNDISABLE_INIT|UART_ADVFEATURE_DMADISABLEONERROR_INIT;
+ 8030b96:	4b17      	ldr	r3, [pc, #92]	@ (8030bf4 <MX_USART3_UART_Init+0xa4>)
+ 8030b98:	2230      	movs	r2, #48	@ 0x30
+ 8030b9a:	629a      	str	r2, [r3, #40]	@ 0x28
+  huart3.AdvancedInit.OverrunDisable = UART_ADVFEATURE_OVERRUN_DISABLE;
+ 8030b9c:	4b15      	ldr	r3, [pc, #84]	@ (8030bf4 <MX_USART3_UART_Init+0xa4>)
+ 8030b9e:	f44f 5280 	mov.w	r2, #4096	@ 0x1000
+ 8030ba2:	63da      	str	r2, [r3, #60]	@ 0x3c
+  huart3.AdvancedInit.DMADisableonRxError = UART_ADVFEATURE_DMA_DISABLEONRXERROR;
+ 8030ba4:	4b13      	ldr	r3, [pc, #76]	@ (8030bf4 <MX_USART3_UART_Init+0xa4>)
+ 8030ba6:	f44f 5200 	mov.w	r2, #8192	@ 0x2000
+ 8030baa:	641a      	str	r2, [r3, #64]	@ 0x40
+  if (HAL_UART_Init(&huart3) != HAL_OK)
+ 8030bac:	4811      	ldr	r0, [pc, #68]	@ (8030bf4 <MX_USART3_UART_Init+0xa4>)
+ 8030bae:	f00c fc4f 	bl	803d450 <HAL_UART_Init>
+ 8030bb2:	4603      	mov	r3, r0
+ 8030bb4:	2b00      	cmp	r3, #0
+ 8030bb6:	d001      	beq.n	8030bbc <MX_USART3_UART_Init+0x6c>
+  {
+    Error_Handler();
+ 8030bb8:	f7fe ff66 	bl	802fa88 <Error_Handler>
+  }
+  if (HAL_UARTEx_SetTxFifoThreshold(&huart3, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
+ 8030bbc:	2100      	movs	r1, #0
+ 8030bbe:	480d      	ldr	r0, [pc, #52]	@ (8030bf4 <MX_USART3_UART_Init+0xa4>)
+ 8030bc0:	f00f f93e 	bl	803fe40 <HAL_UARTEx_SetTxFifoThreshold>
+ 8030bc4:	4603      	mov	r3, r0
+ 8030bc6:	2b00      	cmp	r3, #0
+ 8030bc8:	d001      	beq.n	8030bce <MX_USART3_UART_Init+0x7e>
+  {
+    Error_Handler();
+ 8030bca:	f7fe ff5d 	bl	802fa88 <Error_Handler>
+  }
+  if (HAL_UARTEx_SetRxFifoThreshold(&huart3, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
+ 8030bce:	2100      	movs	r1, #0
+ 8030bd0:	4808      	ldr	r0, [pc, #32]	@ (8030bf4 <MX_USART3_UART_Init+0xa4>)
+ 8030bd2:	f00f f973 	bl	803febc <HAL_UARTEx_SetRxFifoThreshold>
+ 8030bd6:	4603      	mov	r3, r0
+ 8030bd8:	2b00      	cmp	r3, #0
+ 8030bda:	d001      	beq.n	8030be0 <MX_USART3_UART_Init+0x90>
+  {
+    Error_Handler();
+ 8030bdc:	f7fe ff54 	bl	802fa88 <Error_Handler>
+  }
+  if (HAL_UARTEx_EnableFifoMode(&huart3) != HAL_OK)
+ 8030be0:	4804      	ldr	r0, [pc, #16]	@ (8030bf4 <MX_USART3_UART_Init+0xa4>)
+ 8030be2:	f00f f8b9 	bl	803fd58 <HAL_UARTEx_EnableFifoMode>
+ 8030be6:	4603      	mov	r3, r0
+ 8030be8:	2b00      	cmp	r3, #0
+ 8030bea:	d001      	beq.n	8030bf0 <MX_USART3_UART_Init+0xa0>
+  {
+    Error_Handler();
+ 8030bec:	f7fe ff4c 	bl	802fa88 <Error_Handler>
+  }
+  /* USER CODE BEGIN USART3_Init 2 */
+
+  /* USER CODE END USART3_Init 2 */
+
+}
+ 8030bf0:	bf00      	nop
+ 8030bf2:	bd80      	pop	{r7, pc}
+ 8030bf4:	2400ae08 	.word	0x2400ae08
+ 8030bf8:	40004800 	.word	0x40004800
+
+08030bfc <MX_USART6_UART_Init>:
+/* USART6 init function */
+
+void MX_USART6_UART_Init(void)
+{
+ 8030bfc:	b580      	push	{r7, lr}
+ 8030bfe:	af00      	add	r7, sp, #0
+  /* USER CODE END USART6_Init 0 */
+
+  /* USER CODE BEGIN USART6_Init 1 */
+
+  /* USER CODE END USART6_Init 1 */
+  huart6.Instance = USART6;
+ 8030c00:	4b24      	ldr	r3, [pc, #144]	@ (8030c94 <MX_USART6_UART_Init+0x98>)
+ 8030c02:	4a25      	ldr	r2, [pc, #148]	@ (8030c98 <MX_USART6_UART_Init+0x9c>)
+ 8030c04:	601a      	str	r2, [r3, #0]
+  huart6.Init.BaudRate = 9600;
+ 8030c06:	4b23      	ldr	r3, [pc, #140]	@ (8030c94 <MX_USART6_UART_Init+0x98>)
+ 8030c08:	f44f 5216 	mov.w	r2, #9600	@ 0x2580
+ 8030c0c:	605a      	str	r2, [r3, #4]
+  huart6.Init.WordLength = UART_WORDLENGTH_8B;
+ 8030c0e:	4b21      	ldr	r3, [pc, #132]	@ (8030c94 <MX_USART6_UART_Init+0x98>)
+ 8030c10:	2200      	movs	r2, #0
+ 8030c12:	609a      	str	r2, [r3, #8]
+  huart6.Init.StopBits = UART_STOPBITS_1;
+ 8030c14:	4b1f      	ldr	r3, [pc, #124]	@ (8030c94 <MX_USART6_UART_Init+0x98>)
+ 8030c16:	2200      	movs	r2, #0
+ 8030c18:	60da      	str	r2, [r3, #12]
+  huart6.Init.Parity = UART_PARITY_NONE;
+ 8030c1a:	4b1e      	ldr	r3, [pc, #120]	@ (8030c94 <MX_USART6_UART_Init+0x98>)
+ 8030c1c:	2200      	movs	r2, #0
+ 8030c1e:	611a      	str	r2, [r3, #16]
+  huart6.Init.Mode = UART_MODE_TX_RX;
+ 8030c20:	4b1c      	ldr	r3, [pc, #112]	@ (8030c94 <MX_USART6_UART_Init+0x98>)
+ 8030c22:	220c      	movs	r2, #12
+ 8030c24:	615a      	str	r2, [r3, #20]
+  huart6.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+ 8030c26:	4b1b      	ldr	r3, [pc, #108]	@ (8030c94 <MX_USART6_UART_Init+0x98>)
+ 8030c28:	2200      	movs	r2, #0
+ 8030c2a:	619a      	str	r2, [r3, #24]
+  huart6.Init.OverSampling = UART_OVERSAMPLING_16;
+ 8030c2c:	4b19      	ldr	r3, [pc, #100]	@ (8030c94 <MX_USART6_UART_Init+0x98>)
+ 8030c2e:	2200      	movs	r2, #0
+ 8030c30:	61da      	str	r2, [r3, #28]
+  huart6.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+ 8030c32:	4b18      	ldr	r3, [pc, #96]	@ (8030c94 <MX_USART6_UART_Init+0x98>)
+ 8030c34:	2200      	movs	r2, #0
+ 8030c36:	621a      	str	r2, [r3, #32]
+  huart6.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+ 8030c38:	4b16      	ldr	r3, [pc, #88]	@ (8030c94 <MX_USART6_UART_Init+0x98>)
+ 8030c3a:	2200      	movs	r2, #0
+ 8030c3c:	625a      	str	r2, [r3, #36]	@ 0x24
+  huart6.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_RXOVERRUNDISABLE_INIT;
+ 8030c3e:	4b15      	ldr	r3, [pc, #84]	@ (8030c94 <MX_USART6_UART_Init+0x98>)
+ 8030c40:	2210      	movs	r2, #16
+ 8030c42:	629a      	str	r2, [r3, #40]	@ 0x28
+  huart6.AdvancedInit.OverrunDisable = UART_ADVFEATURE_OVERRUN_DISABLE;
+ 8030c44:	4b13      	ldr	r3, [pc, #76]	@ (8030c94 <MX_USART6_UART_Init+0x98>)
+ 8030c46:	f44f 5280 	mov.w	r2, #4096	@ 0x1000
+ 8030c4a:	63da      	str	r2, [r3, #60]	@ 0x3c
+  if (HAL_UART_Init(&huart6) != HAL_OK)
+ 8030c4c:	4811      	ldr	r0, [pc, #68]	@ (8030c94 <MX_USART6_UART_Init+0x98>)
+ 8030c4e:	f00c fbff 	bl	803d450 <HAL_UART_Init>
+ 8030c52:	4603      	mov	r3, r0
+ 8030c54:	2b00      	cmp	r3, #0
+ 8030c56:	d001      	beq.n	8030c5c <MX_USART6_UART_Init+0x60>
+  {
+    Error_Handler();
+ 8030c58:	f7fe ff16 	bl	802fa88 <Error_Handler>
+  }
+  if (HAL_UARTEx_SetTxFifoThreshold(&huart6, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
+ 8030c5c:	2100      	movs	r1, #0
+ 8030c5e:	480d      	ldr	r0, [pc, #52]	@ (8030c94 <MX_USART6_UART_Init+0x98>)
+ 8030c60:	f00f f8ee 	bl	803fe40 <HAL_UARTEx_SetTxFifoThreshold>
+ 8030c64:	4603      	mov	r3, r0
+ 8030c66:	2b00      	cmp	r3, #0
+ 8030c68:	d001      	beq.n	8030c6e <MX_USART6_UART_Init+0x72>
+  {
+    Error_Handler();
+ 8030c6a:	f7fe ff0d 	bl	802fa88 <Error_Handler>
+  }
+  if (HAL_UARTEx_SetRxFifoThreshold(&huart6, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
+ 8030c6e:	2100      	movs	r1, #0
+ 8030c70:	4808      	ldr	r0, [pc, #32]	@ (8030c94 <MX_USART6_UART_Init+0x98>)
+ 8030c72:	f00f f923 	bl	803febc <HAL_UARTEx_SetRxFifoThreshold>
+ 8030c76:	4603      	mov	r3, r0
+ 8030c78:	2b00      	cmp	r3, #0
+ 8030c7a:	d001      	beq.n	8030c80 <MX_USART6_UART_Init+0x84>
+  {
+    Error_Handler();
+ 8030c7c:	f7fe ff04 	bl	802fa88 <Error_Handler>
+  }
+  if (HAL_UARTEx_EnableFifoMode(&huart6) != HAL_OK)
+ 8030c80:	4804      	ldr	r0, [pc, #16]	@ (8030c94 <MX_USART6_UART_Init+0x98>)
+ 8030c82:	f00f f869 	bl	803fd58 <HAL_UARTEx_EnableFifoMode>
+ 8030c86:	4603      	mov	r3, r0
+ 8030c88:	2b00      	cmp	r3, #0
+ 8030c8a:	d001      	beq.n	8030c90 <MX_USART6_UART_Init+0x94>
+  {
+    Error_Handler();
+ 8030c8c:	f7fe fefc 	bl	802fa88 <Error_Handler>
+  }
+  /* USER CODE BEGIN USART6_Init 2 */
+
+  /* USER CODE END USART6_Init 2 */
+
+}
+ 8030c90:	bf00      	nop
+ 8030c92:	bd80      	pop	{r7, pc}
+ 8030c94:	2400ae9c 	.word	0x2400ae9c
+ 8030c98:	40011400 	.word	0x40011400
+
+08030c9c <HAL_UART_MspInit>:
+
+void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle)
+{
+ 8030c9c:	b580      	push	{r7, lr}
+ 8030c9e:	b0ca      	sub	sp, #296	@ 0x128
+ 8030ca0:	af00      	add	r7, sp, #0
+ 8030ca2:	f507 7394 	add.w	r3, r7, #296	@ 0x128
+ 8030ca6:	f5a3 7392 	sub.w	r3, r3, #292	@ 0x124
+ 8030caa:	6018      	str	r0, [r3, #0]
+
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+ 8030cac:	f507 738a 	add.w	r3, r7, #276	@ 0x114
+ 8030cb0:	2200      	movs	r2, #0
+ 8030cb2:	601a      	str	r2, [r3, #0]
+ 8030cb4:	605a      	str	r2, [r3, #4]
+ 8030cb6:	609a      	str	r2, [r3, #8]
+ 8030cb8:	60da      	str	r2, [r3, #12]
+ 8030cba:	611a      	str	r2, [r3, #16]
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+ 8030cbc:	f107 0350 	add.w	r3, r7, #80	@ 0x50
+ 8030cc0:	22c0      	movs	r2, #192	@ 0xc0
+ 8030cc2:	2100      	movs	r1, #0
+ 8030cc4:	4618      	mov	r0, r3
+ 8030cc6:	f00f fb0f 	bl	80402e8 <memset>
+  if(uartHandle->Instance==LPUART1)
+ 8030cca:	f507 7394 	add.w	r3, r7, #296	@ 0x128
+ 8030cce:	f5a3 7392 	sub.w	r3, r3, #292	@ 0x124
+ 8030cd2:	681b      	ldr	r3, [r3, #0]
+ 8030cd4:	681b      	ldr	r3, [r3, #0]
+ 8030cd6:	4a81      	ldr	r2, [pc, #516]	@ (8030edc <HAL_UART_MspInit+0x240>)
+ 8030cd8:	4293      	cmp	r3, r2
+ 8030cda:	d150      	bne.n	8030d7e <HAL_UART_MspInit+0xe2>
+
+  /* USER CODE END LPUART1_MspInit 0 */
+
+  /** Initializes the peripherals clock
+  */
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1;
+ 8030cdc:	f04f 0204 	mov.w	r2, #4
+ 8030ce0:	f04f 0300 	mov.w	r3, #0
+ 8030ce4:	e9c7 2314 	strd	r2, r3, [r7, #80]	@ 0x50
+    PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_D3PCLK1;
+ 8030ce8:	2300      	movs	r3, #0
+ 8030cea:	f8c7 30e4 	str.w	r3, [r7, #228]	@ 0xe4
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+ 8030cee:	f107 0350 	add.w	r3, r7, #80	@ 0x50
+ 8030cf2:	4618      	mov	r0, r3
+ 8030cf4:	f009 f9c6 	bl	803a084 <HAL_RCCEx_PeriphCLKConfig>
+ 8030cf8:	4603      	mov	r3, r0
+ 8030cfa:	2b00      	cmp	r3, #0
+ 8030cfc:	d001      	beq.n	8030d02 <HAL_UART_MspInit+0x66>
+    {
+      Error_Handler();
+ 8030cfe:	f7fe fec3 	bl	802fa88 <Error_Handler>
+    }
+
+    /* LPUART1 clock enable */
+    __HAL_RCC_LPUART1_CLK_ENABLE();
+ 8030d02:	4b77      	ldr	r3, [pc, #476]	@ (8030ee0 <HAL_UART_MspInit+0x244>)
+ 8030d04:	f8d3 30f4 	ldr.w	r3, [r3, #244]	@ 0xf4
+ 8030d08:	4a75      	ldr	r2, [pc, #468]	@ (8030ee0 <HAL_UART_MspInit+0x244>)
+ 8030d0a:	f043 0308 	orr.w	r3, r3, #8
+ 8030d0e:	f8c2 30f4 	str.w	r3, [r2, #244]	@ 0xf4
+ 8030d12:	4b73      	ldr	r3, [pc, #460]	@ (8030ee0 <HAL_UART_MspInit+0x244>)
+ 8030d14:	f8d3 30f4 	ldr.w	r3, [r3, #244]	@ 0xf4
+ 8030d18:	f003 0308 	and.w	r3, r3, #8
+ 8030d1c:	64fb      	str	r3, [r7, #76]	@ 0x4c
+ 8030d1e:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
+
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+ 8030d20:	4b6f      	ldr	r3, [pc, #444]	@ (8030ee0 <HAL_UART_MspInit+0x244>)
+ 8030d22:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
+ 8030d26:	4a6e      	ldr	r2, [pc, #440]	@ (8030ee0 <HAL_UART_MspInit+0x244>)
+ 8030d28:	f043 0301 	orr.w	r3, r3, #1
+ 8030d2c:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
+ 8030d30:	4b6b      	ldr	r3, [pc, #428]	@ (8030ee0 <HAL_UART_MspInit+0x244>)
+ 8030d32:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
+ 8030d36:	f003 0301 	and.w	r3, r3, #1
+ 8030d3a:	64bb      	str	r3, [r7, #72]	@ 0x48
+ 8030d3c:	6cbb      	ldr	r3, [r7, #72]	@ 0x48
+    /**LPUART1 GPIO Configuration
+    PA9     ------> LPUART1_TX
+    PA10     ------> LPUART1_RX
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10;
+ 8030d3e:	f44f 63c0 	mov.w	r3, #1536	@ 0x600
+ 8030d42:	f8c7 3114 	str.w	r3, [r7, #276]	@ 0x114
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 8030d46:	2302      	movs	r3, #2
+ 8030d48:	f8c7 3118 	str.w	r3, [r7, #280]	@ 0x118
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 8030d4c:	2300      	movs	r3, #0
+ 8030d4e:	f8c7 311c 	str.w	r3, [r7, #284]	@ 0x11c
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 8030d52:	2300      	movs	r3, #0
+ 8030d54:	f8c7 3120 	str.w	r3, [r7, #288]	@ 0x120
+    GPIO_InitStruct.Alternate = GPIO_AF3_LPUART;
+ 8030d58:	2303      	movs	r3, #3
+ 8030d5a:	f8c7 3124 	str.w	r3, [r7, #292]	@ 0x124
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 8030d5e:	f507 738a 	add.w	r3, r7, #276	@ 0x114
+ 8030d62:	4619      	mov	r1, r3
+ 8030d64:	485f      	ldr	r0, [pc, #380]	@ (8030ee4 <HAL_UART_MspInit+0x248>)
+ 8030d66:	f006 fc39 	bl	80375dc <HAL_GPIO_Init>
+
+    /* LPUART1 interrupt Init */
+    HAL_NVIC_SetPriority(LPUART1_IRQn, 0, 0);
+ 8030d6a:	2200      	movs	r2, #0
+ 8030d6c:	2100      	movs	r1, #0
+ 8030d6e:	208e      	movs	r0, #142	@ 0x8e
+ 8030d70:	f001 fe9f 	bl	8032ab2 <HAL_NVIC_SetPriority>
+    HAL_NVIC_EnableIRQ(LPUART1_IRQn);
+ 8030d74:	208e      	movs	r0, #142	@ 0x8e
+ 8030d76:	f001 feb6 	bl	8032ae6 <HAL_NVIC_EnableIRQ>
+    HAL_NVIC_EnableIRQ(USART6_IRQn);
+  /* USER CODE BEGIN USART6_MspInit 1 */
+
+  /* USER CODE END USART6_MspInit 1 */
+  }
+}
+ 8030d7a:	f000 bd12 	b.w	80317a2 <HAL_UART_MspInit+0xb06>
+  else if(uartHandle->Instance==UART4)
+ 8030d7e:	f507 7394 	add.w	r3, r7, #296	@ 0x128
+ 8030d82:	f5a3 7392 	sub.w	r3, r3, #292	@ 0x124
+ 8030d86:	681b      	ldr	r3, [r3, #0]
+ 8030d88:	681b      	ldr	r3, [r3, #0]
+ 8030d8a:	4a57      	ldr	r2, [pc, #348]	@ (8030ee8 <HAL_UART_MspInit+0x24c>)
+ 8030d8c:	4293      	cmp	r3, r2
+ 8030d8e:	f040 80b1 	bne.w	8030ef4 <HAL_UART_MspInit+0x258>
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_UART4;
+ 8030d92:	f04f 0202 	mov.w	r2, #2
+ 8030d96:	f04f 0300 	mov.w	r3, #0
+ 8030d9a:	e9c7 2314 	strd	r2, r3, [r7, #80]	@ 0x50
+    PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1;
+ 8030d9e:	2300      	movs	r3, #0
+ 8030da0:	f8c7 30c8 	str.w	r3, [r7, #200]	@ 0xc8
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+ 8030da4:	f107 0350 	add.w	r3, r7, #80	@ 0x50
+ 8030da8:	4618      	mov	r0, r3
+ 8030daa:	f009 f96b 	bl	803a084 <HAL_RCCEx_PeriphCLKConfig>
+ 8030dae:	4603      	mov	r3, r0
+ 8030db0:	2b00      	cmp	r3, #0
+ 8030db2:	d001      	beq.n	8030db8 <HAL_UART_MspInit+0x11c>
+      Error_Handler();
+ 8030db4:	f7fe fe68 	bl	802fa88 <Error_Handler>
+    __HAL_RCC_UART4_CLK_ENABLE();
+ 8030db8:	4b49      	ldr	r3, [pc, #292]	@ (8030ee0 <HAL_UART_MspInit+0x244>)
+ 8030dba:	f8d3 30e8 	ldr.w	r3, [r3, #232]	@ 0xe8
+ 8030dbe:	4a48      	ldr	r2, [pc, #288]	@ (8030ee0 <HAL_UART_MspInit+0x244>)
+ 8030dc0:	f443 2300 	orr.w	r3, r3, #524288	@ 0x80000
+ 8030dc4:	f8c2 30e8 	str.w	r3, [r2, #232]	@ 0xe8
+ 8030dc8:	4b45      	ldr	r3, [pc, #276]	@ (8030ee0 <HAL_UART_MspInit+0x244>)
+ 8030dca:	f8d3 30e8 	ldr.w	r3, [r3, #232]	@ 0xe8
+ 8030dce:	f403 2300 	and.w	r3, r3, #524288	@ 0x80000
+ 8030dd2:	647b      	str	r3, [r7, #68]	@ 0x44
+ 8030dd4:	6c7b      	ldr	r3, [r7, #68]	@ 0x44
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+ 8030dd6:	4b42      	ldr	r3, [pc, #264]	@ (8030ee0 <HAL_UART_MspInit+0x244>)
+ 8030dd8:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
+ 8030ddc:	4a40      	ldr	r2, [pc, #256]	@ (8030ee0 <HAL_UART_MspInit+0x244>)
+ 8030dde:	f043 0301 	orr.w	r3, r3, #1
+ 8030de2:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
+ 8030de6:	4b3e      	ldr	r3, [pc, #248]	@ (8030ee0 <HAL_UART_MspInit+0x244>)
+ 8030de8:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
+ 8030dec:	f003 0301 	and.w	r3, r3, #1
+ 8030df0:	643b      	str	r3, [r7, #64]	@ 0x40
+ 8030df2:	6c3b      	ldr	r3, [r7, #64]	@ 0x40
+    GPIO_InitStruct.Pin = GPIO_PIN_11;
+ 8030df4:	f44f 6300 	mov.w	r3, #2048	@ 0x800
+ 8030df8:	f8c7 3114 	str.w	r3, [r7, #276]	@ 0x114
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 8030dfc:	2302      	movs	r3, #2
+ 8030dfe:	f8c7 3118 	str.w	r3, [r7, #280]	@ 0x118
+    GPIO_InitStruct.Pull = GPIO_PULLUP;
+ 8030e02:	2301      	movs	r3, #1
+ 8030e04:	f8c7 311c 	str.w	r3, [r7, #284]	@ 0x11c
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ 8030e08:	2303      	movs	r3, #3
+ 8030e0a:	f8c7 3120 	str.w	r3, [r7, #288]	@ 0x120
+    GPIO_InitStruct.Alternate = GPIO_AF6_UART4;
+ 8030e0e:	2306      	movs	r3, #6
+ 8030e10:	f8c7 3124 	str.w	r3, [r7, #292]	@ 0x124
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 8030e14:	f507 738a 	add.w	r3, r7, #276	@ 0x114
+ 8030e18:	4619      	mov	r1, r3
+ 8030e1a:	4832      	ldr	r0, [pc, #200]	@ (8030ee4 <HAL_UART_MspInit+0x248>)
+ 8030e1c:	f006 fbde 	bl	80375dc <HAL_GPIO_Init>
+    GPIO_InitStruct.Pin = GPIO_PIN_12;
+ 8030e20:	f44f 5380 	mov.w	r3, #4096	@ 0x1000
+ 8030e24:	f8c7 3114 	str.w	r3, [r7, #276]	@ 0x114
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 8030e28:	2302      	movs	r3, #2
+ 8030e2a:	f8c7 3118 	str.w	r3, [r7, #280]	@ 0x118
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 8030e2e:	2300      	movs	r3, #0
+ 8030e30:	f8c7 311c 	str.w	r3, [r7, #284]	@ 0x11c
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 8030e34:	2300      	movs	r3, #0
+ 8030e36:	f8c7 3120 	str.w	r3, [r7, #288]	@ 0x120
+    GPIO_InitStruct.Alternate = GPIO_AF6_UART4;
+ 8030e3a:	2306      	movs	r3, #6
+ 8030e3c:	f8c7 3124 	str.w	r3, [r7, #292]	@ 0x124
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 8030e40:	f507 738a 	add.w	r3, r7, #276	@ 0x114
+ 8030e44:	4619      	mov	r1, r3
+ 8030e46:	4827      	ldr	r0, [pc, #156]	@ (8030ee4 <HAL_UART_MspInit+0x248>)
+ 8030e48:	f006 fbc8 	bl	80375dc <HAL_GPIO_Init>
+    hdma_uart4_tx.Instance = DMA1_Stream0;
+ 8030e4c:	4b27      	ldr	r3, [pc, #156]	@ (8030eec <HAL_UART_MspInit+0x250>)
+ 8030e4e:	4a28      	ldr	r2, [pc, #160]	@ (8030ef0 <HAL_UART_MspInit+0x254>)
+ 8030e50:	601a      	str	r2, [r3, #0]
+    hdma_uart4_tx.Init.Request = DMA_REQUEST_UART4_TX;
+ 8030e52:	4b26      	ldr	r3, [pc, #152]	@ (8030eec <HAL_UART_MspInit+0x250>)
+ 8030e54:	2240      	movs	r2, #64	@ 0x40
+ 8030e56:	605a      	str	r2, [r3, #4]
+    hdma_uart4_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
+ 8030e58:	4b24      	ldr	r3, [pc, #144]	@ (8030eec <HAL_UART_MspInit+0x250>)
+ 8030e5a:	2240      	movs	r2, #64	@ 0x40
+ 8030e5c:	609a      	str	r2, [r3, #8]
+    hdma_uart4_tx.Init.PeriphInc = DMA_PINC_DISABLE;
+ 8030e5e:	4b23      	ldr	r3, [pc, #140]	@ (8030eec <HAL_UART_MspInit+0x250>)
+ 8030e60:	2200      	movs	r2, #0
+ 8030e62:	60da      	str	r2, [r3, #12]
+    hdma_uart4_tx.Init.MemInc = DMA_MINC_ENABLE;
+ 8030e64:	4b21      	ldr	r3, [pc, #132]	@ (8030eec <HAL_UART_MspInit+0x250>)
+ 8030e66:	f44f 6280 	mov.w	r2, #1024	@ 0x400
+ 8030e6a:	611a      	str	r2, [r3, #16]
+    hdma_uart4_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+ 8030e6c:	4b1f      	ldr	r3, [pc, #124]	@ (8030eec <HAL_UART_MspInit+0x250>)
+ 8030e6e:	2200      	movs	r2, #0
+ 8030e70:	615a      	str	r2, [r3, #20]
+    hdma_uart4_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+ 8030e72:	4b1e      	ldr	r3, [pc, #120]	@ (8030eec <HAL_UART_MspInit+0x250>)
+ 8030e74:	2200      	movs	r2, #0
+ 8030e76:	619a      	str	r2, [r3, #24]
+    hdma_uart4_tx.Init.Mode = DMA_NORMAL;
+ 8030e78:	4b1c      	ldr	r3, [pc, #112]	@ (8030eec <HAL_UART_MspInit+0x250>)
+ 8030e7a:	2200      	movs	r2, #0
+ 8030e7c:	61da      	str	r2, [r3, #28]
+    hdma_uart4_tx.Init.Priority = DMA_PRIORITY_LOW;
+ 8030e7e:	4b1b      	ldr	r3, [pc, #108]	@ (8030eec <HAL_UART_MspInit+0x250>)
+ 8030e80:	2200      	movs	r2, #0
+ 8030e82:	621a      	str	r2, [r3, #32]
+    hdma_uart4_tx.Init.FIFOMode = DMA_FIFOMODE_ENABLE;
+ 8030e84:	4b19      	ldr	r3, [pc, #100]	@ (8030eec <HAL_UART_MspInit+0x250>)
+ 8030e86:	2204      	movs	r2, #4
+ 8030e88:	625a      	str	r2, [r3, #36]	@ 0x24
+    hdma_uart4_tx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
+ 8030e8a:	4b18      	ldr	r3, [pc, #96]	@ (8030eec <HAL_UART_MspInit+0x250>)
+ 8030e8c:	2203      	movs	r2, #3
+ 8030e8e:	629a      	str	r2, [r3, #40]	@ 0x28
+    hdma_uart4_tx.Init.MemBurst = DMA_MBURST_SINGLE;
+ 8030e90:	4b16      	ldr	r3, [pc, #88]	@ (8030eec <HAL_UART_MspInit+0x250>)
+ 8030e92:	2200      	movs	r2, #0
+ 8030e94:	62da      	str	r2, [r3, #44]	@ 0x2c
+    hdma_uart4_tx.Init.PeriphBurst = DMA_PBURST_SINGLE;
+ 8030e96:	4b15      	ldr	r3, [pc, #84]	@ (8030eec <HAL_UART_MspInit+0x250>)
+ 8030e98:	2200      	movs	r2, #0
+ 8030e9a:	631a      	str	r2, [r3, #48]	@ 0x30
+    if (HAL_DMA_Init(&hdma_uart4_tx) != HAL_OK)
+ 8030e9c:	4813      	ldr	r0, [pc, #76]	@ (8030eec <HAL_UART_MspInit+0x250>)
+ 8030e9e:	f001 feb5 	bl	8032c0c <HAL_DMA_Init>
+ 8030ea2:	4603      	mov	r3, r0
+ 8030ea4:	2b00      	cmp	r3, #0
+ 8030ea6:	d001      	beq.n	8030eac <HAL_UART_MspInit+0x210>
+      Error_Handler();
+ 8030ea8:	f7fe fdee 	bl	802fa88 <Error_Handler>
+    __HAL_LINKDMA(uartHandle,hdmatx,hdma_uart4_tx);
+ 8030eac:	f507 7394 	add.w	r3, r7, #296	@ 0x128
+ 8030eb0:	f5a3 7392 	sub.w	r3, r3, #292	@ 0x124
+ 8030eb4:	681b      	ldr	r3, [r3, #0]
+ 8030eb6:	4a0d      	ldr	r2, [pc, #52]	@ (8030eec <HAL_UART_MspInit+0x250>)
+ 8030eb8:	67da      	str	r2, [r3, #124]	@ 0x7c
+ 8030eba:	4a0c      	ldr	r2, [pc, #48]	@ (8030eec <HAL_UART_MspInit+0x250>)
+ 8030ebc:	f507 7394 	add.w	r3, r7, #296	@ 0x128
+ 8030ec0:	f5a3 7392 	sub.w	r3, r3, #292	@ 0x124
+ 8030ec4:	681b      	ldr	r3, [r3, #0]
+ 8030ec6:	6393      	str	r3, [r2, #56]	@ 0x38
+    HAL_NVIC_SetPriority(UART4_IRQn, 0, 0);
+ 8030ec8:	2200      	movs	r2, #0
+ 8030eca:	2100      	movs	r1, #0
+ 8030ecc:	2034      	movs	r0, #52	@ 0x34
+ 8030ece:	f001 fdf0 	bl	8032ab2 <HAL_NVIC_SetPriority>
+    HAL_NVIC_EnableIRQ(UART4_IRQn);
+ 8030ed2:	2034      	movs	r0, #52	@ 0x34
+ 8030ed4:	f001 fe07 	bl	8032ae6 <HAL_NVIC_EnableIRQ>
+}
+ 8030ed8:	f000 bc63 	b.w	80317a2 <HAL_UART_MspInit+0xb06>
+ 8030edc:	58000c00 	.word	0x58000c00
+ 8030ee0:	58024400 	.word	0x58024400
+ 8030ee4:	58020000 	.word	0x58020000
+ 8030ee8:	40004c00 	.word	0x40004c00
+ 8030eec:	2400af30 	.word	0x2400af30
+ 8030ef0:	40020010 	.word	0x40020010
+  else if(uartHandle->Instance==UART5)
+ 8030ef4:	f507 7394 	add.w	r3, r7, #296	@ 0x128
+ 8030ef8:	f5a3 7392 	sub.w	r3, r3, #292	@ 0x124
+ 8030efc:	681b      	ldr	r3, [r3, #0]
+ 8030efe:	681b      	ldr	r3, [r3, #0]
+ 8030f00:	4aa8      	ldr	r2, [pc, #672]	@ (80311a4 <HAL_UART_MspInit+0x508>)
+ 8030f02:	4293      	cmp	r3, r2
+ 8030f04:	f040 80a9 	bne.w	803105a <HAL_UART_MspInit+0x3be>
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_UART5;
+ 8030f08:	f04f 0202 	mov.w	r2, #2
+ 8030f0c:	f04f 0300 	mov.w	r3, #0
+ 8030f10:	e9c7 2314 	strd	r2, r3, [r7, #80]	@ 0x50
+    PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1;
+ 8030f14:	2300      	movs	r3, #0
+ 8030f16:	f8c7 30c8 	str.w	r3, [r7, #200]	@ 0xc8
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+ 8030f1a:	f107 0350 	add.w	r3, r7, #80	@ 0x50
+ 8030f1e:	4618      	mov	r0, r3
+ 8030f20:	f009 f8b0 	bl	803a084 <HAL_RCCEx_PeriphCLKConfig>
+ 8030f24:	4603      	mov	r3, r0
+ 8030f26:	2b00      	cmp	r3, #0
+ 8030f28:	d001      	beq.n	8030f2e <HAL_UART_MspInit+0x292>
+      Error_Handler();
+ 8030f2a:	f7fe fdad 	bl	802fa88 <Error_Handler>
+    __HAL_RCC_UART5_CLK_ENABLE();
+ 8030f2e:	4b9e      	ldr	r3, [pc, #632]	@ (80311a8 <HAL_UART_MspInit+0x50c>)
+ 8030f30:	f8d3 30e8 	ldr.w	r3, [r3, #232]	@ 0xe8
+ 8030f34:	4a9c      	ldr	r2, [pc, #624]	@ (80311a8 <HAL_UART_MspInit+0x50c>)
+ 8030f36:	f443 1380 	orr.w	r3, r3, #1048576	@ 0x100000
+ 8030f3a:	f8c2 30e8 	str.w	r3, [r2, #232]	@ 0xe8
+ 8030f3e:	4b9a      	ldr	r3, [pc, #616]	@ (80311a8 <HAL_UART_MspInit+0x50c>)
+ 8030f40:	f8d3 30e8 	ldr.w	r3, [r3, #232]	@ 0xe8
+ 8030f44:	f403 1380 	and.w	r3, r3, #1048576	@ 0x100000
+ 8030f48:	63fb      	str	r3, [r7, #60]	@ 0x3c
+ 8030f4a:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+ 8030f4c:	4b96      	ldr	r3, [pc, #600]	@ (80311a8 <HAL_UART_MspInit+0x50c>)
+ 8030f4e:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
+ 8030f52:	4a95      	ldr	r2, [pc, #596]	@ (80311a8 <HAL_UART_MspInit+0x50c>)
+ 8030f54:	f043 0304 	orr.w	r3, r3, #4
+ 8030f58:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
+ 8030f5c:	4b92      	ldr	r3, [pc, #584]	@ (80311a8 <HAL_UART_MspInit+0x50c>)
+ 8030f5e:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
+ 8030f62:	f003 0304 	and.w	r3, r3, #4
+ 8030f66:	63bb      	str	r3, [r7, #56]	@ 0x38
+ 8030f68:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+    __HAL_RCC_GPIOD_CLK_ENABLE();
+ 8030f6a:	4b8f      	ldr	r3, [pc, #572]	@ (80311a8 <HAL_UART_MspInit+0x50c>)
+ 8030f6c:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
+ 8030f70:	4a8d      	ldr	r2, [pc, #564]	@ (80311a8 <HAL_UART_MspInit+0x50c>)
+ 8030f72:	f043 0308 	orr.w	r3, r3, #8
+ 8030f76:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
+ 8030f7a:	4b8b      	ldr	r3, [pc, #556]	@ (80311a8 <HAL_UART_MspInit+0x50c>)
+ 8030f7c:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
+ 8030f80:	f003 0308 	and.w	r3, r3, #8
+ 8030f84:	637b      	str	r3, [r7, #52]	@ 0x34
+ 8030f86:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
+    GPIO_InitStruct.Pin = GPIO_PIN_12;
+ 8030f88:	f44f 5380 	mov.w	r3, #4096	@ 0x1000
+ 8030f8c:	f8c7 3114 	str.w	r3, [r7, #276]	@ 0x114
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 8030f90:	2302      	movs	r3, #2
+ 8030f92:	f8c7 3118 	str.w	r3, [r7, #280]	@ 0x118
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 8030f96:	2300      	movs	r3, #0
+ 8030f98:	f8c7 311c 	str.w	r3, [r7, #284]	@ 0x11c
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 8030f9c:	2300      	movs	r3, #0
+ 8030f9e:	f8c7 3120 	str.w	r3, [r7, #288]	@ 0x120
+    GPIO_InitStruct.Alternate = GPIO_AF8_UART5;
+ 8030fa2:	2308      	movs	r3, #8
+ 8030fa4:	f8c7 3124 	str.w	r3, [r7, #292]	@ 0x124
+    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+ 8030fa8:	f507 738a 	add.w	r3, r7, #276	@ 0x114
+ 8030fac:	4619      	mov	r1, r3
+ 8030fae:	487f      	ldr	r0, [pc, #508]	@ (80311ac <HAL_UART_MspInit+0x510>)
+ 8030fb0:	f006 fb14 	bl	80375dc <HAL_GPIO_Init>
+    GPIO_InitStruct.Pin = GPIO_PIN_2;
+ 8030fb4:	2304      	movs	r3, #4
+ 8030fb6:	f8c7 3114 	str.w	r3, [r7, #276]	@ 0x114
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 8030fba:	2302      	movs	r3, #2
+ 8030fbc:	f8c7 3118 	str.w	r3, [r7, #280]	@ 0x118
+    GPIO_InitStruct.Pull = GPIO_PULLUP;
+ 8030fc0:	2301      	movs	r3, #1
+ 8030fc2:	f8c7 311c 	str.w	r3, [r7, #284]	@ 0x11c
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ 8030fc6:	2303      	movs	r3, #3
+ 8030fc8:	f8c7 3120 	str.w	r3, [r7, #288]	@ 0x120
+    GPIO_InitStruct.Alternate = GPIO_AF8_UART5;
+ 8030fcc:	2308      	movs	r3, #8
+ 8030fce:	f8c7 3124 	str.w	r3, [r7, #292]	@ 0x124
+    HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+ 8030fd2:	f507 738a 	add.w	r3, r7, #276	@ 0x114
+ 8030fd6:	4619      	mov	r1, r3
+ 8030fd8:	4875      	ldr	r0, [pc, #468]	@ (80311b0 <HAL_UART_MspInit+0x514>)
+ 8030fda:	f006 faff 	bl	80375dc <HAL_GPIO_Init>
+    hdma_uart5_tx.Instance = DMA1_Stream3;
+ 8030fde:	4b75      	ldr	r3, [pc, #468]	@ (80311b4 <HAL_UART_MspInit+0x518>)
+ 8030fe0:	4a75      	ldr	r2, [pc, #468]	@ (80311b8 <HAL_UART_MspInit+0x51c>)
+ 8030fe2:	601a      	str	r2, [r3, #0]
+    hdma_uart5_tx.Init.Request = DMA_REQUEST_UART5_TX;
+ 8030fe4:	4b73      	ldr	r3, [pc, #460]	@ (80311b4 <HAL_UART_MspInit+0x518>)
+ 8030fe6:	2242      	movs	r2, #66	@ 0x42
+ 8030fe8:	605a      	str	r2, [r3, #4]
+    hdma_uart5_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
+ 8030fea:	4b72      	ldr	r3, [pc, #456]	@ (80311b4 <HAL_UART_MspInit+0x518>)
+ 8030fec:	2240      	movs	r2, #64	@ 0x40
+ 8030fee:	609a      	str	r2, [r3, #8]
+    hdma_uart5_tx.Init.PeriphInc = DMA_PINC_DISABLE;
+ 8030ff0:	4b70      	ldr	r3, [pc, #448]	@ (80311b4 <HAL_UART_MspInit+0x518>)
+ 8030ff2:	2200      	movs	r2, #0
+ 8030ff4:	60da      	str	r2, [r3, #12]
+    hdma_uart5_tx.Init.MemInc = DMA_MINC_ENABLE;
+ 8030ff6:	4b6f      	ldr	r3, [pc, #444]	@ (80311b4 <HAL_UART_MspInit+0x518>)
+ 8030ff8:	f44f 6280 	mov.w	r2, #1024	@ 0x400
+ 8030ffc:	611a      	str	r2, [r3, #16]
+    hdma_uart5_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+ 8030ffe:	4b6d      	ldr	r3, [pc, #436]	@ (80311b4 <HAL_UART_MspInit+0x518>)
+ 8031000:	2200      	movs	r2, #0
+ 8031002:	615a      	str	r2, [r3, #20]
+    hdma_uart5_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+ 8031004:	4b6b      	ldr	r3, [pc, #428]	@ (80311b4 <HAL_UART_MspInit+0x518>)
+ 8031006:	2200      	movs	r2, #0
+ 8031008:	619a      	str	r2, [r3, #24]
+    hdma_uart5_tx.Init.Mode = DMA_NORMAL;
+ 803100a:	4b6a      	ldr	r3, [pc, #424]	@ (80311b4 <HAL_UART_MspInit+0x518>)
+ 803100c:	2200      	movs	r2, #0
+ 803100e:	61da      	str	r2, [r3, #28]
+    hdma_uart5_tx.Init.Priority = DMA_PRIORITY_LOW;
+ 8031010:	4b68      	ldr	r3, [pc, #416]	@ (80311b4 <HAL_UART_MspInit+0x518>)
+ 8031012:	2200      	movs	r2, #0
+ 8031014:	621a      	str	r2, [r3, #32]
+    hdma_uart5_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
+ 8031016:	4b67      	ldr	r3, [pc, #412]	@ (80311b4 <HAL_UART_MspInit+0x518>)
+ 8031018:	2200      	movs	r2, #0
+ 803101a:	625a      	str	r2, [r3, #36]	@ 0x24
+    if (HAL_DMA_Init(&hdma_uart5_tx) != HAL_OK)
+ 803101c:	4865      	ldr	r0, [pc, #404]	@ (80311b4 <HAL_UART_MspInit+0x518>)
+ 803101e:	f001 fdf5 	bl	8032c0c <HAL_DMA_Init>
+ 8031022:	4603      	mov	r3, r0
+ 8031024:	2b00      	cmp	r3, #0
+ 8031026:	d001      	beq.n	803102c <HAL_UART_MspInit+0x390>
+      Error_Handler();
+ 8031028:	f7fe fd2e 	bl	802fa88 <Error_Handler>
+    __HAL_LINKDMA(uartHandle,hdmatx,hdma_uart5_tx);
+ 803102c:	f507 7394 	add.w	r3, r7, #296	@ 0x128
+ 8031030:	f5a3 7392 	sub.w	r3, r3, #292	@ 0x124
+ 8031034:	681b      	ldr	r3, [r3, #0]
+ 8031036:	4a5f      	ldr	r2, [pc, #380]	@ (80311b4 <HAL_UART_MspInit+0x518>)
+ 8031038:	67da      	str	r2, [r3, #124]	@ 0x7c
+ 803103a:	4a5e      	ldr	r2, [pc, #376]	@ (80311b4 <HAL_UART_MspInit+0x518>)
+ 803103c:	f507 7394 	add.w	r3, r7, #296	@ 0x128
+ 8031040:	f5a3 7392 	sub.w	r3, r3, #292	@ 0x124
+ 8031044:	681b      	ldr	r3, [r3, #0]
+ 8031046:	6393      	str	r3, [r2, #56]	@ 0x38
+    HAL_NVIC_SetPriority(UART5_IRQn, 0, 0);
+ 8031048:	2200      	movs	r2, #0
+ 803104a:	2100      	movs	r1, #0
+ 803104c:	2035      	movs	r0, #53	@ 0x35
+ 803104e:	f001 fd30 	bl	8032ab2 <HAL_NVIC_SetPriority>
+    HAL_NVIC_EnableIRQ(UART5_IRQn);
+ 8031052:	2035      	movs	r0, #53	@ 0x35
+ 8031054:	f001 fd47 	bl	8032ae6 <HAL_NVIC_EnableIRQ>
+}
+ 8031058:	e3a3      	b.n	80317a2 <HAL_UART_MspInit+0xb06>
+  else if(uartHandle->Instance==UART7)
+ 803105a:	f507 7394 	add.w	r3, r7, #296	@ 0x128
+ 803105e:	f5a3 7392 	sub.w	r3, r3, #292	@ 0x124
+ 8031062:	681b      	ldr	r3, [r3, #0]
+ 8031064:	681b      	ldr	r3, [r3, #0]
+ 8031066:	4a55      	ldr	r2, [pc, #340]	@ (80311bc <HAL_UART_MspInit+0x520>)
+ 8031068:	4293      	cmp	r3, r2
+ 803106a:	f040 80af 	bne.w	80311cc <HAL_UART_MspInit+0x530>
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_UART7;
+ 803106e:	f04f 0202 	mov.w	r2, #2
+ 8031072:	f04f 0300 	mov.w	r3, #0
+ 8031076:	e9c7 2314 	strd	r2, r3, [r7, #80]	@ 0x50
+    PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1;
+ 803107a:	2300      	movs	r3, #0
+ 803107c:	f8c7 30c8 	str.w	r3, [r7, #200]	@ 0xc8
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+ 8031080:	f107 0350 	add.w	r3, r7, #80	@ 0x50
+ 8031084:	4618      	mov	r0, r3
+ 8031086:	f008 fffd 	bl	803a084 <HAL_RCCEx_PeriphCLKConfig>
+ 803108a:	4603      	mov	r3, r0
+ 803108c:	2b00      	cmp	r3, #0
+ 803108e:	d001      	beq.n	8031094 <HAL_UART_MspInit+0x3f8>
+      Error_Handler();
+ 8031090:	f7fe fcfa 	bl	802fa88 <Error_Handler>
+    __HAL_RCC_UART7_CLK_ENABLE();
+ 8031094:	4b44      	ldr	r3, [pc, #272]	@ (80311a8 <HAL_UART_MspInit+0x50c>)
+ 8031096:	f8d3 30e8 	ldr.w	r3, [r3, #232]	@ 0xe8
+ 803109a:	4a43      	ldr	r2, [pc, #268]	@ (80311a8 <HAL_UART_MspInit+0x50c>)
+ 803109c:	f043 4380 	orr.w	r3, r3, #1073741824	@ 0x40000000
+ 80310a0:	f8c2 30e8 	str.w	r3, [r2, #232]	@ 0xe8
+ 80310a4:	4b40      	ldr	r3, [pc, #256]	@ (80311a8 <HAL_UART_MspInit+0x50c>)
+ 80310a6:	f8d3 30e8 	ldr.w	r3, [r3, #232]	@ 0xe8
+ 80310aa:	f003 4380 	and.w	r3, r3, #1073741824	@ 0x40000000
+ 80310ae:	633b      	str	r3, [r7, #48]	@ 0x30
+ 80310b0:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+ 80310b2:	4b3d      	ldr	r3, [pc, #244]	@ (80311a8 <HAL_UART_MspInit+0x50c>)
+ 80310b4:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
+ 80310b8:	4a3b      	ldr	r2, [pc, #236]	@ (80311a8 <HAL_UART_MspInit+0x50c>)
+ 80310ba:	f043 0301 	orr.w	r3, r3, #1
+ 80310be:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
+ 80310c2:	4b39      	ldr	r3, [pc, #228]	@ (80311a8 <HAL_UART_MspInit+0x50c>)
+ 80310c4:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
+ 80310c8:	f003 0301 	and.w	r3, r3, #1
+ 80310cc:	62fb      	str	r3, [r7, #44]	@ 0x2c
+ 80310ce:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
+    GPIO_InitStruct.Pin = GPIO_PIN_8;
+ 80310d0:	f44f 7380 	mov.w	r3, #256	@ 0x100
+ 80310d4:	f8c7 3114 	str.w	r3, [r7, #276]	@ 0x114
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 80310d8:	2302      	movs	r3, #2
+ 80310da:	f8c7 3118 	str.w	r3, [r7, #280]	@ 0x118
+    GPIO_InitStruct.Pull = GPIO_PULLUP;
+ 80310de:	2301      	movs	r3, #1
+ 80310e0:	f8c7 311c 	str.w	r3, [r7, #284]	@ 0x11c
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ 80310e4:	2303      	movs	r3, #3
+ 80310e6:	f8c7 3120 	str.w	r3, [r7, #288]	@ 0x120
+    GPIO_InitStruct.Alternate = GPIO_AF11_UART7;
+ 80310ea:	230b      	movs	r3, #11
+ 80310ec:	f8c7 3124 	str.w	r3, [r7, #292]	@ 0x124
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 80310f0:	f507 738a 	add.w	r3, r7, #276	@ 0x114
+ 80310f4:	4619      	mov	r1, r3
+ 80310f6:	4832      	ldr	r0, [pc, #200]	@ (80311c0 <HAL_UART_MspInit+0x524>)
+ 80310f8:	f006 fa70 	bl	80375dc <HAL_GPIO_Init>
+    GPIO_InitStruct.Pin = GPIO_PIN_15;
+ 80310fc:	f44f 4300 	mov.w	r3, #32768	@ 0x8000
+ 8031100:	f8c7 3114 	str.w	r3, [r7, #276]	@ 0x114
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 8031104:	2302      	movs	r3, #2
+ 8031106:	f8c7 3118 	str.w	r3, [r7, #280]	@ 0x118
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 803110a:	2300      	movs	r3, #0
+ 803110c:	f8c7 311c 	str.w	r3, [r7, #284]	@ 0x11c
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 8031110:	2300      	movs	r3, #0
+ 8031112:	f8c7 3120 	str.w	r3, [r7, #288]	@ 0x120
+    GPIO_InitStruct.Alternate = GPIO_AF11_UART7;
+ 8031116:	230b      	movs	r3, #11
+ 8031118:	f8c7 3124 	str.w	r3, [r7, #292]	@ 0x124
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 803111c:	f507 738a 	add.w	r3, r7, #276	@ 0x114
+ 8031120:	4619      	mov	r1, r3
+ 8031122:	4827      	ldr	r0, [pc, #156]	@ (80311c0 <HAL_UART_MspInit+0x524>)
+ 8031124:	f006 fa5a 	bl	80375dc <HAL_GPIO_Init>
+    hdma_uart7_tx.Instance = DMA1_Stream1;
+ 8031128:	4b26      	ldr	r3, [pc, #152]	@ (80311c4 <HAL_UART_MspInit+0x528>)
+ 803112a:	4a27      	ldr	r2, [pc, #156]	@ (80311c8 <HAL_UART_MspInit+0x52c>)
+ 803112c:	601a      	str	r2, [r3, #0]
+    hdma_uart7_tx.Init.Request = DMA_REQUEST_UART7_TX;
+ 803112e:	4b25      	ldr	r3, [pc, #148]	@ (80311c4 <HAL_UART_MspInit+0x528>)
+ 8031130:	2250      	movs	r2, #80	@ 0x50
+ 8031132:	605a      	str	r2, [r3, #4]
+    hdma_uart7_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
+ 8031134:	4b23      	ldr	r3, [pc, #140]	@ (80311c4 <HAL_UART_MspInit+0x528>)
+ 8031136:	2240      	movs	r2, #64	@ 0x40
+ 8031138:	609a      	str	r2, [r3, #8]
+    hdma_uart7_tx.Init.PeriphInc = DMA_PINC_DISABLE;
+ 803113a:	4b22      	ldr	r3, [pc, #136]	@ (80311c4 <HAL_UART_MspInit+0x528>)
+ 803113c:	2200      	movs	r2, #0
+ 803113e:	60da      	str	r2, [r3, #12]
+    hdma_uart7_tx.Init.MemInc = DMA_MINC_ENABLE;
+ 8031140:	4b20      	ldr	r3, [pc, #128]	@ (80311c4 <HAL_UART_MspInit+0x528>)
+ 8031142:	f44f 6280 	mov.w	r2, #1024	@ 0x400
+ 8031146:	611a      	str	r2, [r3, #16]
+    hdma_uart7_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+ 8031148:	4b1e      	ldr	r3, [pc, #120]	@ (80311c4 <HAL_UART_MspInit+0x528>)
+ 803114a:	2200      	movs	r2, #0
+ 803114c:	615a      	str	r2, [r3, #20]
+    hdma_uart7_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+ 803114e:	4b1d      	ldr	r3, [pc, #116]	@ (80311c4 <HAL_UART_MspInit+0x528>)
+ 8031150:	2200      	movs	r2, #0
+ 8031152:	619a      	str	r2, [r3, #24]
+    hdma_uart7_tx.Init.Mode = DMA_NORMAL;
+ 8031154:	4b1b      	ldr	r3, [pc, #108]	@ (80311c4 <HAL_UART_MspInit+0x528>)
+ 8031156:	2200      	movs	r2, #0
+ 8031158:	61da      	str	r2, [r3, #28]
+    hdma_uart7_tx.Init.Priority = DMA_PRIORITY_LOW;
+ 803115a:	4b1a      	ldr	r3, [pc, #104]	@ (80311c4 <HAL_UART_MspInit+0x528>)
+ 803115c:	2200      	movs	r2, #0
+ 803115e:	621a      	str	r2, [r3, #32]
+    hdma_uart7_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
+ 8031160:	4b18      	ldr	r3, [pc, #96]	@ (80311c4 <HAL_UART_MspInit+0x528>)
+ 8031162:	2200      	movs	r2, #0
+ 8031164:	625a      	str	r2, [r3, #36]	@ 0x24
+    if (HAL_DMA_Init(&hdma_uart7_tx) != HAL_OK)
+ 8031166:	4817      	ldr	r0, [pc, #92]	@ (80311c4 <HAL_UART_MspInit+0x528>)
+ 8031168:	f001 fd50 	bl	8032c0c <HAL_DMA_Init>
+ 803116c:	4603      	mov	r3, r0
+ 803116e:	2b00      	cmp	r3, #0
+ 8031170:	d001      	beq.n	8031176 <HAL_UART_MspInit+0x4da>
+      Error_Handler();
+ 8031172:	f7fe fc89 	bl	802fa88 <Error_Handler>
+    __HAL_LINKDMA(uartHandle,hdmatx,hdma_uart7_tx);
+ 8031176:	f507 7394 	add.w	r3, r7, #296	@ 0x128
+ 803117a:	f5a3 7392 	sub.w	r3, r3, #292	@ 0x124
+ 803117e:	681b      	ldr	r3, [r3, #0]
+ 8031180:	4a10      	ldr	r2, [pc, #64]	@ (80311c4 <HAL_UART_MspInit+0x528>)
+ 8031182:	67da      	str	r2, [r3, #124]	@ 0x7c
+ 8031184:	4a0f      	ldr	r2, [pc, #60]	@ (80311c4 <HAL_UART_MspInit+0x528>)
+ 8031186:	f507 7394 	add.w	r3, r7, #296	@ 0x128
+ 803118a:	f5a3 7392 	sub.w	r3, r3, #292	@ 0x124
+ 803118e:	681b      	ldr	r3, [r3, #0]
+ 8031190:	6393      	str	r3, [r2, #56]	@ 0x38
+    HAL_NVIC_SetPriority(UART7_IRQn, 0, 0);
+ 8031192:	2200      	movs	r2, #0
+ 8031194:	2100      	movs	r1, #0
+ 8031196:	2052      	movs	r0, #82	@ 0x52
+ 8031198:	f001 fc8b 	bl	8032ab2 <HAL_NVIC_SetPriority>
+    HAL_NVIC_EnableIRQ(UART7_IRQn);
+ 803119c:	2052      	movs	r0, #82	@ 0x52
+ 803119e:	f001 fca2 	bl	8032ae6 <HAL_NVIC_EnableIRQ>
+}
+ 80311a2:	e2fe      	b.n	80317a2 <HAL_UART_MspInit+0xb06>
+ 80311a4:	40005000 	.word	0x40005000
+ 80311a8:	58024400 	.word	0x58024400
+ 80311ac:	58020800 	.word	0x58020800
+ 80311b0:	58020c00 	.word	0x58020c00
+ 80311b4:	2400afa8 	.word	0x2400afa8
+ 80311b8:	40020058 	.word	0x40020058
+ 80311bc:	40007800 	.word	0x40007800
+ 80311c0:	58020000 	.word	0x58020000
+ 80311c4:	2400b020 	.word	0x2400b020
+ 80311c8:	40020028 	.word	0x40020028
+  else if(uartHandle->Instance==USART1)
+ 80311cc:	f507 7394 	add.w	r3, r7, #296	@ 0x128
+ 80311d0:	f5a3 7392 	sub.w	r3, r3, #292	@ 0x124
+ 80311d4:	681b      	ldr	r3, [r3, #0]
+ 80311d6:	681b      	ldr	r3, [r3, #0]
+ 80311d8:	4ab5      	ldr	r2, [pc, #724]	@ (80314b0 <HAL_UART_MspInit+0x814>)
+ 80311da:	4293      	cmp	r3, r2
+ 80311dc:	f040 80b4 	bne.w	8031348 <HAL_UART_MspInit+0x6ac>
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART1;
+ 80311e0:	f04f 0201 	mov.w	r2, #1
+ 80311e4:	f04f 0300 	mov.w	r3, #0
+ 80311e8:	e9c7 2314 	strd	r2, r3, [r7, #80]	@ 0x50
+    PeriphClkInitStruct.Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2;
+ 80311ec:	2300      	movs	r3, #0
+ 80311ee:	f8c7 30cc 	str.w	r3, [r7, #204]	@ 0xcc
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+ 80311f2:	f107 0350 	add.w	r3, r7, #80	@ 0x50
+ 80311f6:	4618      	mov	r0, r3
+ 80311f8:	f008 ff44 	bl	803a084 <HAL_RCCEx_PeriphCLKConfig>
+ 80311fc:	4603      	mov	r3, r0
+ 80311fe:	2b00      	cmp	r3, #0
+ 8031200:	d001      	beq.n	8031206 <HAL_UART_MspInit+0x56a>
+      Error_Handler();
+ 8031202:	f7fe fc41 	bl	802fa88 <Error_Handler>
+    __HAL_RCC_USART1_CLK_ENABLE();
+ 8031206:	4bab      	ldr	r3, [pc, #684]	@ (80314b4 <HAL_UART_MspInit+0x818>)
+ 8031208:	f8d3 30f0 	ldr.w	r3, [r3, #240]	@ 0xf0
+ 803120c:	4aa9      	ldr	r2, [pc, #676]	@ (80314b4 <HAL_UART_MspInit+0x818>)
+ 803120e:	f043 0310 	orr.w	r3, r3, #16
+ 8031212:	f8c2 30f0 	str.w	r3, [r2, #240]	@ 0xf0
+ 8031216:	4ba7      	ldr	r3, [pc, #668]	@ (80314b4 <HAL_UART_MspInit+0x818>)
+ 8031218:	f8d3 30f0 	ldr.w	r3, [r3, #240]	@ 0xf0
+ 803121c:	f003 0210 	and.w	r2, r3, #16
+ 8031220:	f507 7394 	add.w	r3, r7, #296	@ 0x128
+ 8031224:	f5a3 7380 	sub.w	r3, r3, #256	@ 0x100
+ 8031228:	601a      	str	r2, [r3, #0]
+ 803122a:	f507 7394 	add.w	r3, r7, #296	@ 0x128
+ 803122e:	f5a3 7380 	sub.w	r3, r3, #256	@ 0x100
+ 8031232:	681b      	ldr	r3, [r3, #0]
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+ 8031234:	4b9f      	ldr	r3, [pc, #636]	@ (80314b4 <HAL_UART_MspInit+0x818>)
+ 8031236:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
+ 803123a:	4a9e      	ldr	r2, [pc, #632]	@ (80314b4 <HAL_UART_MspInit+0x818>)
+ 803123c:	f043 0302 	orr.w	r3, r3, #2
+ 8031240:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
+ 8031244:	4b9b      	ldr	r3, [pc, #620]	@ (80314b4 <HAL_UART_MspInit+0x818>)
+ 8031246:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
+ 803124a:	f003 0202 	and.w	r2, r3, #2
+ 803124e:	f507 7394 	add.w	r3, r7, #296	@ 0x128
+ 8031252:	f5a3 7382 	sub.w	r3, r3, #260	@ 0x104
+ 8031256:	601a      	str	r2, [r3, #0]
+ 8031258:	f507 7394 	add.w	r3, r7, #296	@ 0x128
+ 803125c:	f5a3 7382 	sub.w	r3, r3, #260	@ 0x104
+ 8031260:	681b      	ldr	r3, [r3, #0]
+    GPIO_InitStruct.Pin = GPIO_PIN_14;
+ 8031262:	f44f 4380 	mov.w	r3, #16384	@ 0x4000
+ 8031266:	f8c7 3114 	str.w	r3, [r7, #276]	@ 0x114
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 803126a:	2302      	movs	r3, #2
+ 803126c:	f8c7 3118 	str.w	r3, [r7, #280]	@ 0x118
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 8031270:	2300      	movs	r3, #0
+ 8031272:	f8c7 311c 	str.w	r3, [r7, #284]	@ 0x11c
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 8031276:	2300      	movs	r3, #0
+ 8031278:	f8c7 3120 	str.w	r3, [r7, #288]	@ 0x120
+    GPIO_InitStruct.Alternate = GPIO_AF4_USART1;
+ 803127c:	2304      	movs	r3, #4
+ 803127e:	f8c7 3124 	str.w	r3, [r7, #292]	@ 0x124
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+ 8031282:	f507 738a 	add.w	r3, r7, #276	@ 0x114
+ 8031286:	4619      	mov	r1, r3
+ 8031288:	488b      	ldr	r0, [pc, #556]	@ (80314b8 <HAL_UART_MspInit+0x81c>)
+ 803128a:	f006 f9a7 	bl	80375dc <HAL_GPIO_Init>
+    GPIO_InitStruct.Pin = GPIO_PIN_15;
+ 803128e:	f44f 4300 	mov.w	r3, #32768	@ 0x8000
+ 8031292:	f8c7 3114 	str.w	r3, [r7, #276]	@ 0x114
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 8031296:	2302      	movs	r3, #2
+ 8031298:	f8c7 3118 	str.w	r3, [r7, #280]	@ 0x118
+    GPIO_InitStruct.Pull = GPIO_PULLUP;
+ 803129c:	2301      	movs	r3, #1
+ 803129e:	f8c7 311c 	str.w	r3, [r7, #284]	@ 0x11c
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ 80312a2:	2303      	movs	r3, #3
+ 80312a4:	f8c7 3120 	str.w	r3, [r7, #288]	@ 0x120
+    GPIO_InitStruct.Alternate = GPIO_AF4_USART1;
+ 80312a8:	2304      	movs	r3, #4
+ 80312aa:	f8c7 3124 	str.w	r3, [r7, #292]	@ 0x124
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+ 80312ae:	f507 738a 	add.w	r3, r7, #276	@ 0x114
+ 80312b2:	4619      	mov	r1, r3
+ 80312b4:	4880      	ldr	r0, [pc, #512]	@ (80314b8 <HAL_UART_MspInit+0x81c>)
+ 80312b6:	f006 f991 	bl	80375dc <HAL_GPIO_Init>
+    hdma_usart1_tx.Instance = DMA1_Stream2;
+ 80312ba:	4b80      	ldr	r3, [pc, #512]	@ (80314bc <HAL_UART_MspInit+0x820>)
+ 80312bc:	4a80      	ldr	r2, [pc, #512]	@ (80314c0 <HAL_UART_MspInit+0x824>)
+ 80312be:	601a      	str	r2, [r3, #0]
+    hdma_usart1_tx.Init.Request = DMA_REQUEST_USART1_TX;
+ 80312c0:	4b7e      	ldr	r3, [pc, #504]	@ (80314bc <HAL_UART_MspInit+0x820>)
+ 80312c2:	222a      	movs	r2, #42	@ 0x2a
+ 80312c4:	605a      	str	r2, [r3, #4]
+    hdma_usart1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
+ 80312c6:	4b7d      	ldr	r3, [pc, #500]	@ (80314bc <HAL_UART_MspInit+0x820>)
+ 80312c8:	2240      	movs	r2, #64	@ 0x40
+ 80312ca:	609a      	str	r2, [r3, #8]
+    hdma_usart1_tx.Init.PeriphInc = DMA_PINC_DISABLE;
+ 80312cc:	4b7b      	ldr	r3, [pc, #492]	@ (80314bc <HAL_UART_MspInit+0x820>)
+ 80312ce:	2200      	movs	r2, #0
+ 80312d0:	60da      	str	r2, [r3, #12]
+    hdma_usart1_tx.Init.MemInc = DMA_MINC_ENABLE;
+ 80312d2:	4b7a      	ldr	r3, [pc, #488]	@ (80314bc <HAL_UART_MspInit+0x820>)
+ 80312d4:	f44f 6280 	mov.w	r2, #1024	@ 0x400
+ 80312d8:	611a      	str	r2, [r3, #16]
+    hdma_usart1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+ 80312da:	4b78      	ldr	r3, [pc, #480]	@ (80314bc <HAL_UART_MspInit+0x820>)
+ 80312dc:	2200      	movs	r2, #0
+ 80312de:	615a      	str	r2, [r3, #20]
+    hdma_usart1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+ 80312e0:	4b76      	ldr	r3, [pc, #472]	@ (80314bc <HAL_UART_MspInit+0x820>)
+ 80312e2:	2200      	movs	r2, #0
+ 80312e4:	619a      	str	r2, [r3, #24]
+    hdma_usart1_tx.Init.Mode = DMA_NORMAL;
+ 80312e6:	4b75      	ldr	r3, [pc, #468]	@ (80314bc <HAL_UART_MspInit+0x820>)
+ 80312e8:	2200      	movs	r2, #0
+ 80312ea:	61da      	str	r2, [r3, #28]
+    hdma_usart1_tx.Init.Priority = DMA_PRIORITY_LOW;
+ 80312ec:	4b73      	ldr	r3, [pc, #460]	@ (80314bc <HAL_UART_MspInit+0x820>)
+ 80312ee:	2200      	movs	r2, #0
+ 80312f0:	621a      	str	r2, [r3, #32]
+    hdma_usart1_tx.Init.FIFOMode = DMA_FIFOMODE_ENABLE;
+ 80312f2:	4b72      	ldr	r3, [pc, #456]	@ (80314bc <HAL_UART_MspInit+0x820>)
+ 80312f4:	2204      	movs	r2, #4
+ 80312f6:	625a      	str	r2, [r3, #36]	@ 0x24
+    hdma_usart1_tx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
+ 80312f8:	4b70      	ldr	r3, [pc, #448]	@ (80314bc <HAL_UART_MspInit+0x820>)
+ 80312fa:	2203      	movs	r2, #3
+ 80312fc:	629a      	str	r2, [r3, #40]	@ 0x28
+    hdma_usart1_tx.Init.MemBurst = DMA_MBURST_SINGLE;
+ 80312fe:	4b6f      	ldr	r3, [pc, #444]	@ (80314bc <HAL_UART_MspInit+0x820>)
+ 8031300:	2200      	movs	r2, #0
+ 8031302:	62da      	str	r2, [r3, #44]	@ 0x2c
+    hdma_usart1_tx.Init.PeriphBurst = DMA_PBURST_SINGLE;
+ 8031304:	4b6d      	ldr	r3, [pc, #436]	@ (80314bc <HAL_UART_MspInit+0x820>)
+ 8031306:	2200      	movs	r2, #0
+ 8031308:	631a      	str	r2, [r3, #48]	@ 0x30
+    if (HAL_DMA_Init(&hdma_usart1_tx) != HAL_OK)
+ 803130a:	486c      	ldr	r0, [pc, #432]	@ (80314bc <HAL_UART_MspInit+0x820>)
+ 803130c:	f001 fc7e 	bl	8032c0c <HAL_DMA_Init>
+ 8031310:	4603      	mov	r3, r0
+ 8031312:	2b00      	cmp	r3, #0
+ 8031314:	d001      	beq.n	803131a <HAL_UART_MspInit+0x67e>
+      Error_Handler();
+ 8031316:	f7fe fbb7 	bl	802fa88 <Error_Handler>
+    __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart1_tx);
+ 803131a:	f507 7394 	add.w	r3, r7, #296	@ 0x128
+ 803131e:	f5a3 7392 	sub.w	r3, r3, #292	@ 0x124
+ 8031322:	681b      	ldr	r3, [r3, #0]
+ 8031324:	4a65      	ldr	r2, [pc, #404]	@ (80314bc <HAL_UART_MspInit+0x820>)
+ 8031326:	67da      	str	r2, [r3, #124]	@ 0x7c
+ 8031328:	4a64      	ldr	r2, [pc, #400]	@ (80314bc <HAL_UART_MspInit+0x820>)
+ 803132a:	f507 7394 	add.w	r3, r7, #296	@ 0x128
+ 803132e:	f5a3 7392 	sub.w	r3, r3, #292	@ 0x124
+ 8031332:	681b      	ldr	r3, [r3, #0]
+ 8031334:	6393      	str	r3, [r2, #56]	@ 0x38
+    HAL_NVIC_SetPriority(USART1_IRQn, 0, 0);
+ 8031336:	2200      	movs	r2, #0
+ 8031338:	2100      	movs	r1, #0
+ 803133a:	2025      	movs	r0, #37	@ 0x25
+ 803133c:	f001 fbb9 	bl	8032ab2 <HAL_NVIC_SetPriority>
+    HAL_NVIC_EnableIRQ(USART1_IRQn);
+ 8031340:	2025      	movs	r0, #37	@ 0x25
+ 8031342:	f001 fbd0 	bl	8032ae6 <HAL_NVIC_EnableIRQ>
+}
+ 8031346:	e22c      	b.n	80317a2 <HAL_UART_MspInit+0xb06>
+  else if(uartHandle->Instance==USART2)
+ 8031348:	f507 7394 	add.w	r3, r7, #296	@ 0x128
+ 803134c:	f5a3 7392 	sub.w	r3, r3, #292	@ 0x124
+ 8031350:	681b      	ldr	r3, [r3, #0]
+ 8031352:	681b      	ldr	r3, [r3, #0]
+ 8031354:	4a5b      	ldr	r2, [pc, #364]	@ (80314c4 <HAL_UART_MspInit+0x828>)
+ 8031356:	4293      	cmp	r3, r2
+ 8031358:	f040 80bc 	bne.w	80314d4 <HAL_UART_MspInit+0x838>
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART2;
+ 803135c:	f04f 0202 	mov.w	r2, #2
+ 8031360:	f04f 0300 	mov.w	r3, #0
+ 8031364:	e9c7 2314 	strd	r2, r3, [r7, #80]	@ 0x50
+    PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1;
+ 8031368:	2300      	movs	r3, #0
+ 803136a:	f8c7 30c8 	str.w	r3, [r7, #200]	@ 0xc8
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+ 803136e:	f107 0350 	add.w	r3, r7, #80	@ 0x50
+ 8031372:	4618      	mov	r0, r3
+ 8031374:	f008 fe86 	bl	803a084 <HAL_RCCEx_PeriphCLKConfig>
+ 8031378:	4603      	mov	r3, r0
+ 803137a:	2b00      	cmp	r3, #0
+ 803137c:	d001      	beq.n	8031382 <HAL_UART_MspInit+0x6e6>
+      Error_Handler();
+ 803137e:	f7fe fb83 	bl	802fa88 <Error_Handler>
+    __HAL_RCC_USART2_CLK_ENABLE();
+ 8031382:	4b4c      	ldr	r3, [pc, #304]	@ (80314b4 <HAL_UART_MspInit+0x818>)
+ 8031384:	f8d3 30e8 	ldr.w	r3, [r3, #232]	@ 0xe8
+ 8031388:	4a4a      	ldr	r2, [pc, #296]	@ (80314b4 <HAL_UART_MspInit+0x818>)
+ 803138a:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
+ 803138e:	f8c2 30e8 	str.w	r3, [r2, #232]	@ 0xe8
+ 8031392:	4b48      	ldr	r3, [pc, #288]	@ (80314b4 <HAL_UART_MspInit+0x818>)
+ 8031394:	f8d3 30e8 	ldr.w	r3, [r3, #232]	@ 0xe8
+ 8031398:	f403 3200 	and.w	r2, r3, #131072	@ 0x20000
+ 803139c:	f507 7394 	add.w	r3, r7, #296	@ 0x128
+ 80313a0:	f5a3 7384 	sub.w	r3, r3, #264	@ 0x108
+ 80313a4:	601a      	str	r2, [r3, #0]
+ 80313a6:	f507 7394 	add.w	r3, r7, #296	@ 0x128
+ 80313aa:	f5a3 7384 	sub.w	r3, r3, #264	@ 0x108
+ 80313ae:	681b      	ldr	r3, [r3, #0]
+    __HAL_RCC_GPIOD_CLK_ENABLE();
+ 80313b0:	4b40      	ldr	r3, [pc, #256]	@ (80314b4 <HAL_UART_MspInit+0x818>)
+ 80313b2:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
+ 80313b6:	4a3f      	ldr	r2, [pc, #252]	@ (80314b4 <HAL_UART_MspInit+0x818>)
+ 80313b8:	f043 0308 	orr.w	r3, r3, #8
+ 80313bc:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
+ 80313c0:	4b3c      	ldr	r3, [pc, #240]	@ (80314b4 <HAL_UART_MspInit+0x818>)
+ 80313c2:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
+ 80313c6:	f003 0208 	and.w	r2, r3, #8
+ 80313ca:	f507 7394 	add.w	r3, r7, #296	@ 0x128
+ 80313ce:	f5a3 7386 	sub.w	r3, r3, #268	@ 0x10c
+ 80313d2:	601a      	str	r2, [r3, #0]
+ 80313d4:	f507 7394 	add.w	r3, r7, #296	@ 0x128
+ 80313d8:	f5a3 7386 	sub.w	r3, r3, #268	@ 0x10c
+ 80313dc:	681b      	ldr	r3, [r3, #0]
+    GPIO_InitStruct.Pin = GPIO_PIN_5;
+ 80313de:	2320      	movs	r3, #32
+ 80313e0:	f8c7 3114 	str.w	r3, [r7, #276]	@ 0x114
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 80313e4:	2302      	movs	r3, #2
+ 80313e6:	f8c7 3118 	str.w	r3, [r7, #280]	@ 0x118
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 80313ea:	2300      	movs	r3, #0
+ 80313ec:	f8c7 311c 	str.w	r3, [r7, #284]	@ 0x11c
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 80313f0:	2300      	movs	r3, #0
+ 80313f2:	f8c7 3120 	str.w	r3, [r7, #288]	@ 0x120
+    GPIO_InitStruct.Alternate = GPIO_AF7_USART2;
+ 80313f6:	2307      	movs	r3, #7
+ 80313f8:	f8c7 3124 	str.w	r3, [r7, #292]	@ 0x124
+    HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+ 80313fc:	f507 738a 	add.w	r3, r7, #276	@ 0x114
+ 8031400:	4619      	mov	r1, r3
+ 8031402:	4831      	ldr	r0, [pc, #196]	@ (80314c8 <HAL_UART_MspInit+0x82c>)
+ 8031404:	f006 f8ea 	bl	80375dc <HAL_GPIO_Init>
+    GPIO_InitStruct.Pin = GPIO_PIN_6;
+ 8031408:	2340      	movs	r3, #64	@ 0x40
+ 803140a:	f8c7 3114 	str.w	r3, [r7, #276]	@ 0x114
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 803140e:	2302      	movs	r3, #2
+ 8031410:	f8c7 3118 	str.w	r3, [r7, #280]	@ 0x118
+    GPIO_InitStruct.Pull = GPIO_PULLUP;
+ 8031414:	2301      	movs	r3, #1
+ 8031416:	f8c7 311c 	str.w	r3, [r7, #284]	@ 0x11c
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ 803141a:	2303      	movs	r3, #3
+ 803141c:	f8c7 3120 	str.w	r3, [r7, #288]	@ 0x120
+    GPIO_InitStruct.Alternate = GPIO_AF7_USART2;
+ 8031420:	2307      	movs	r3, #7
+ 8031422:	f8c7 3124 	str.w	r3, [r7, #292]	@ 0x124
+    HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+ 8031426:	f507 738a 	add.w	r3, r7, #276	@ 0x114
+ 803142a:	4619      	mov	r1, r3
+ 803142c:	4826      	ldr	r0, [pc, #152]	@ (80314c8 <HAL_UART_MspInit+0x82c>)
+ 803142e:	f006 f8d5 	bl	80375dc <HAL_GPIO_Init>
+    hdma_usart2_tx.Instance = DMA1_Stream5;
+ 8031432:	4b26      	ldr	r3, [pc, #152]	@ (80314cc <HAL_UART_MspInit+0x830>)
+ 8031434:	4a26      	ldr	r2, [pc, #152]	@ (80314d0 <HAL_UART_MspInit+0x834>)
+ 8031436:	601a      	str	r2, [r3, #0]
+    hdma_usart2_tx.Init.Request = DMA_REQUEST_USART2_TX;
+ 8031438:	4b24      	ldr	r3, [pc, #144]	@ (80314cc <HAL_UART_MspInit+0x830>)
+ 803143a:	222c      	movs	r2, #44	@ 0x2c
+ 803143c:	605a      	str	r2, [r3, #4]
+    hdma_usart2_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
+ 803143e:	4b23      	ldr	r3, [pc, #140]	@ (80314cc <HAL_UART_MspInit+0x830>)
+ 8031440:	2240      	movs	r2, #64	@ 0x40
+ 8031442:	609a      	str	r2, [r3, #8]
+    hdma_usart2_tx.Init.PeriphInc = DMA_PINC_DISABLE;
+ 8031444:	4b21      	ldr	r3, [pc, #132]	@ (80314cc <HAL_UART_MspInit+0x830>)
+ 8031446:	2200      	movs	r2, #0
+ 8031448:	60da      	str	r2, [r3, #12]
+    hdma_usart2_tx.Init.MemInc = DMA_MINC_ENABLE;
+ 803144a:	4b20      	ldr	r3, [pc, #128]	@ (80314cc <HAL_UART_MspInit+0x830>)
+ 803144c:	f44f 6280 	mov.w	r2, #1024	@ 0x400
+ 8031450:	611a      	str	r2, [r3, #16]
+    hdma_usart2_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+ 8031452:	4b1e      	ldr	r3, [pc, #120]	@ (80314cc <HAL_UART_MspInit+0x830>)
+ 8031454:	2200      	movs	r2, #0
+ 8031456:	615a      	str	r2, [r3, #20]
+    hdma_usart2_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+ 8031458:	4b1c      	ldr	r3, [pc, #112]	@ (80314cc <HAL_UART_MspInit+0x830>)
+ 803145a:	2200      	movs	r2, #0
+ 803145c:	619a      	str	r2, [r3, #24]
+    hdma_usart2_tx.Init.Mode = DMA_NORMAL;
+ 803145e:	4b1b      	ldr	r3, [pc, #108]	@ (80314cc <HAL_UART_MspInit+0x830>)
+ 8031460:	2200      	movs	r2, #0
+ 8031462:	61da      	str	r2, [r3, #28]
+    hdma_usart2_tx.Init.Priority = DMA_PRIORITY_LOW;
+ 8031464:	4b19      	ldr	r3, [pc, #100]	@ (80314cc <HAL_UART_MspInit+0x830>)
+ 8031466:	2200      	movs	r2, #0
+ 8031468:	621a      	str	r2, [r3, #32]
+    hdma_usart2_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
+ 803146a:	4b18      	ldr	r3, [pc, #96]	@ (80314cc <HAL_UART_MspInit+0x830>)
+ 803146c:	2200      	movs	r2, #0
+ 803146e:	625a      	str	r2, [r3, #36]	@ 0x24
+    if (HAL_DMA_Init(&hdma_usart2_tx) != HAL_OK)
+ 8031470:	4816      	ldr	r0, [pc, #88]	@ (80314cc <HAL_UART_MspInit+0x830>)
+ 8031472:	f001 fbcb 	bl	8032c0c <HAL_DMA_Init>
+ 8031476:	4603      	mov	r3, r0
+ 8031478:	2b00      	cmp	r3, #0
+ 803147a:	d001      	beq.n	8031480 <HAL_UART_MspInit+0x7e4>
+      Error_Handler();
+ 803147c:	f7fe fb04 	bl	802fa88 <Error_Handler>
+    __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart2_tx);
+ 8031480:	f507 7394 	add.w	r3, r7, #296	@ 0x128
+ 8031484:	f5a3 7392 	sub.w	r3, r3, #292	@ 0x124
+ 8031488:	681b      	ldr	r3, [r3, #0]
+ 803148a:	4a10      	ldr	r2, [pc, #64]	@ (80314cc <HAL_UART_MspInit+0x830>)
+ 803148c:	67da      	str	r2, [r3, #124]	@ 0x7c
+ 803148e:	4a0f      	ldr	r2, [pc, #60]	@ (80314cc <HAL_UART_MspInit+0x830>)
+ 8031490:	f507 7394 	add.w	r3, r7, #296	@ 0x128
+ 8031494:	f5a3 7392 	sub.w	r3, r3, #292	@ 0x124
+ 8031498:	681b      	ldr	r3, [r3, #0]
+ 803149a:	6393      	str	r3, [r2, #56]	@ 0x38
+    HAL_NVIC_SetPriority(USART2_IRQn, 0, 0);
+ 803149c:	2200      	movs	r2, #0
+ 803149e:	2100      	movs	r1, #0
+ 80314a0:	2026      	movs	r0, #38	@ 0x26
+ 80314a2:	f001 fb06 	bl	8032ab2 <HAL_NVIC_SetPriority>
+    HAL_NVIC_EnableIRQ(USART2_IRQn);
+ 80314a6:	2026      	movs	r0, #38	@ 0x26
+ 80314a8:	f001 fb1d 	bl	8032ae6 <HAL_NVIC_EnableIRQ>
+}
+ 80314ac:	e179      	b.n	80317a2 <HAL_UART_MspInit+0xb06>
+ 80314ae:	bf00      	nop
+ 80314b0:	40011000 	.word	0x40011000
+ 80314b4:	58024400 	.word	0x58024400
+ 80314b8:	58020400 	.word	0x58020400
+ 80314bc:	2400b098 	.word	0x2400b098
+ 80314c0:	40020040 	.word	0x40020040
+ 80314c4:	40004400 	.word	0x40004400
+ 80314c8:	58020c00 	.word	0x58020c00
+ 80314cc:	2400b110 	.word	0x2400b110
+ 80314d0:	40020088 	.word	0x40020088
+  else if(uartHandle->Instance==USART3)
+ 80314d4:	f507 7394 	add.w	r3, r7, #296	@ 0x128
+ 80314d8:	f5a3 7392 	sub.w	r3, r3, #292	@ 0x124
+ 80314dc:	681b      	ldr	r3, [r3, #0]
+ 80314de:	681b      	ldr	r3, [r3, #0]
+ 80314e0:	4ab2      	ldr	r2, [pc, #712]	@ (80317ac <HAL_UART_MspInit+0xb10>)
+ 80314e2:	4293      	cmp	r3, r2
+ 80314e4:	f040 80ab 	bne.w	803163e <HAL_UART_MspInit+0x9a2>
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART3;
+ 80314e8:	f04f 0202 	mov.w	r2, #2
+ 80314ec:	f04f 0300 	mov.w	r3, #0
+ 80314f0:	e9c7 2314 	strd	r2, r3, [r7, #80]	@ 0x50
+    PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1;
+ 80314f4:	2300      	movs	r3, #0
+ 80314f6:	f8c7 30c8 	str.w	r3, [r7, #200]	@ 0xc8
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+ 80314fa:	f107 0350 	add.w	r3, r7, #80	@ 0x50
+ 80314fe:	4618      	mov	r0, r3
+ 8031500:	f008 fdc0 	bl	803a084 <HAL_RCCEx_PeriphCLKConfig>
+ 8031504:	4603      	mov	r3, r0
+ 8031506:	2b00      	cmp	r3, #0
+ 8031508:	d001      	beq.n	803150e <HAL_UART_MspInit+0x872>
+      Error_Handler();
+ 803150a:	f7fe fabd 	bl	802fa88 <Error_Handler>
+    __HAL_RCC_USART3_CLK_ENABLE();
+ 803150e:	4ba8      	ldr	r3, [pc, #672]	@ (80317b0 <HAL_UART_MspInit+0xb14>)
+ 8031510:	f8d3 30e8 	ldr.w	r3, [r3, #232]	@ 0xe8
+ 8031514:	4aa6      	ldr	r2, [pc, #664]	@ (80317b0 <HAL_UART_MspInit+0xb14>)
+ 8031516:	f443 2380 	orr.w	r3, r3, #262144	@ 0x40000
+ 803151a:	f8c2 30e8 	str.w	r3, [r2, #232]	@ 0xe8
+ 803151e:	4ba4      	ldr	r3, [pc, #656]	@ (80317b0 <HAL_UART_MspInit+0xb14>)
+ 8031520:	f8d3 30e8 	ldr.w	r3, [r3, #232]	@ 0xe8
+ 8031524:	f403 2280 	and.w	r2, r3, #262144	@ 0x40000
+ 8031528:	f507 7394 	add.w	r3, r7, #296	@ 0x128
+ 803152c:	f5a3 7388 	sub.w	r3, r3, #272	@ 0x110
+ 8031530:	601a      	str	r2, [r3, #0]
+ 8031532:	f507 7394 	add.w	r3, r7, #296	@ 0x128
+ 8031536:	f5a3 7388 	sub.w	r3, r3, #272	@ 0x110
+ 803153a:	681b      	ldr	r3, [r3, #0]
+    __HAL_RCC_GPIOD_CLK_ENABLE();
+ 803153c:	4b9c      	ldr	r3, [pc, #624]	@ (80317b0 <HAL_UART_MspInit+0xb14>)
+ 803153e:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
+ 8031542:	4a9b      	ldr	r2, [pc, #620]	@ (80317b0 <HAL_UART_MspInit+0xb14>)
+ 8031544:	f043 0308 	orr.w	r3, r3, #8
+ 8031548:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
+ 803154c:	4b98      	ldr	r3, [pc, #608]	@ (80317b0 <HAL_UART_MspInit+0xb14>)
+ 803154e:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
+ 8031552:	f003 0208 	and.w	r2, r3, #8
+ 8031556:	f507 7394 	add.w	r3, r7, #296	@ 0x128
+ 803155a:	f5a3 738a 	sub.w	r3, r3, #276	@ 0x114
+ 803155e:	601a      	str	r2, [r3, #0]
+ 8031560:	f507 7394 	add.w	r3, r7, #296	@ 0x128
+ 8031564:	f5a3 738a 	sub.w	r3, r3, #276	@ 0x114
+ 8031568:	681b      	ldr	r3, [r3, #0]
+    GPIO_InitStruct.Pin = GPIO_PIN_8;
+ 803156a:	f44f 7380 	mov.w	r3, #256	@ 0x100
+ 803156e:	f8c7 3114 	str.w	r3, [r7, #276]	@ 0x114
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 8031572:	2302      	movs	r3, #2
+ 8031574:	f8c7 3118 	str.w	r3, [r7, #280]	@ 0x118
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 8031578:	2300      	movs	r3, #0
+ 803157a:	f8c7 311c 	str.w	r3, [r7, #284]	@ 0x11c
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 803157e:	2300      	movs	r3, #0
+ 8031580:	f8c7 3120 	str.w	r3, [r7, #288]	@ 0x120
+    GPIO_InitStruct.Alternate = GPIO_AF7_USART3;
+ 8031584:	2307      	movs	r3, #7
+ 8031586:	f8c7 3124 	str.w	r3, [r7, #292]	@ 0x124
+    HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+ 803158a:	f507 738a 	add.w	r3, r7, #276	@ 0x114
+ 803158e:	4619      	mov	r1, r3
+ 8031590:	4888      	ldr	r0, [pc, #544]	@ (80317b4 <HAL_UART_MspInit+0xb18>)
+ 8031592:	f006 f823 	bl	80375dc <HAL_GPIO_Init>
+    GPIO_InitStruct.Pin = GPIO_PIN_9;
+ 8031596:	f44f 7300 	mov.w	r3, #512	@ 0x200
+ 803159a:	f8c7 3114 	str.w	r3, [r7, #276]	@ 0x114
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 803159e:	2302      	movs	r3, #2
+ 80315a0:	f8c7 3118 	str.w	r3, [r7, #280]	@ 0x118
+    GPIO_InitStruct.Pull = GPIO_PULLUP;
+ 80315a4:	2301      	movs	r3, #1
+ 80315a6:	f8c7 311c 	str.w	r3, [r7, #284]	@ 0x11c
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ 80315aa:	2303      	movs	r3, #3
+ 80315ac:	f8c7 3120 	str.w	r3, [r7, #288]	@ 0x120
+    GPIO_InitStruct.Alternate = GPIO_AF7_USART3;
+ 80315b0:	2307      	movs	r3, #7
+ 80315b2:	f8c7 3124 	str.w	r3, [r7, #292]	@ 0x124
+    HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+ 80315b6:	f507 738a 	add.w	r3, r7, #276	@ 0x114
+ 80315ba:	4619      	mov	r1, r3
+ 80315bc:	487d      	ldr	r0, [pc, #500]	@ (80317b4 <HAL_UART_MspInit+0xb18>)
+ 80315be:	f006 f80d 	bl	80375dc <HAL_GPIO_Init>
+    hdma_usart3_tx.Instance = DMA1_Stream6;
+ 80315c2:	4b7d      	ldr	r3, [pc, #500]	@ (80317b8 <HAL_UART_MspInit+0xb1c>)
+ 80315c4:	4a7d      	ldr	r2, [pc, #500]	@ (80317bc <HAL_UART_MspInit+0xb20>)
+ 80315c6:	601a      	str	r2, [r3, #0]
+    hdma_usart3_tx.Init.Request = DMA_REQUEST_USART3_TX;
+ 80315c8:	4b7b      	ldr	r3, [pc, #492]	@ (80317b8 <HAL_UART_MspInit+0xb1c>)
+ 80315ca:	222e      	movs	r2, #46	@ 0x2e
+ 80315cc:	605a      	str	r2, [r3, #4]
+    hdma_usart3_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
+ 80315ce:	4b7a      	ldr	r3, [pc, #488]	@ (80317b8 <HAL_UART_MspInit+0xb1c>)
+ 80315d0:	2240      	movs	r2, #64	@ 0x40
+ 80315d2:	609a      	str	r2, [r3, #8]
+    hdma_usart3_tx.Init.PeriphInc = DMA_PINC_DISABLE;
+ 80315d4:	4b78      	ldr	r3, [pc, #480]	@ (80317b8 <HAL_UART_MspInit+0xb1c>)
+ 80315d6:	2200      	movs	r2, #0
+ 80315d8:	60da      	str	r2, [r3, #12]
+    hdma_usart3_tx.Init.MemInc = DMA_MINC_ENABLE;
+ 80315da:	4b77      	ldr	r3, [pc, #476]	@ (80317b8 <HAL_UART_MspInit+0xb1c>)
+ 80315dc:	f44f 6280 	mov.w	r2, #1024	@ 0x400
+ 80315e0:	611a      	str	r2, [r3, #16]
+    hdma_usart3_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+ 80315e2:	4b75      	ldr	r3, [pc, #468]	@ (80317b8 <HAL_UART_MspInit+0xb1c>)
+ 80315e4:	2200      	movs	r2, #0
+ 80315e6:	615a      	str	r2, [r3, #20]
+    hdma_usart3_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+ 80315e8:	4b73      	ldr	r3, [pc, #460]	@ (80317b8 <HAL_UART_MspInit+0xb1c>)
+ 80315ea:	2200      	movs	r2, #0
+ 80315ec:	619a      	str	r2, [r3, #24]
+    hdma_usart3_tx.Init.Mode = DMA_NORMAL;
+ 80315ee:	4b72      	ldr	r3, [pc, #456]	@ (80317b8 <HAL_UART_MspInit+0xb1c>)
+ 80315f0:	2200      	movs	r2, #0
+ 80315f2:	61da      	str	r2, [r3, #28]
+    hdma_usart3_tx.Init.Priority = DMA_PRIORITY_LOW;
+ 80315f4:	4b70      	ldr	r3, [pc, #448]	@ (80317b8 <HAL_UART_MspInit+0xb1c>)
+ 80315f6:	2200      	movs	r2, #0
+ 80315f8:	621a      	str	r2, [r3, #32]
+    hdma_usart3_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
+ 80315fa:	4b6f      	ldr	r3, [pc, #444]	@ (80317b8 <HAL_UART_MspInit+0xb1c>)
+ 80315fc:	2200      	movs	r2, #0
+ 80315fe:	625a      	str	r2, [r3, #36]	@ 0x24
+    if (HAL_DMA_Init(&hdma_usart3_tx) != HAL_OK)
+ 8031600:	486d      	ldr	r0, [pc, #436]	@ (80317b8 <HAL_UART_MspInit+0xb1c>)
+ 8031602:	f001 fb03 	bl	8032c0c <HAL_DMA_Init>
+ 8031606:	4603      	mov	r3, r0
+ 8031608:	2b00      	cmp	r3, #0
+ 803160a:	d001      	beq.n	8031610 <HAL_UART_MspInit+0x974>
+      Error_Handler();
+ 803160c:	f7fe fa3c 	bl	802fa88 <Error_Handler>
+    __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart3_tx);
+ 8031610:	f507 7394 	add.w	r3, r7, #296	@ 0x128
+ 8031614:	f5a3 7392 	sub.w	r3, r3, #292	@ 0x124
+ 8031618:	681b      	ldr	r3, [r3, #0]
+ 803161a:	4a67      	ldr	r2, [pc, #412]	@ (80317b8 <HAL_UART_MspInit+0xb1c>)
+ 803161c:	67da      	str	r2, [r3, #124]	@ 0x7c
+ 803161e:	4a66      	ldr	r2, [pc, #408]	@ (80317b8 <HAL_UART_MspInit+0xb1c>)
+ 8031620:	f507 7394 	add.w	r3, r7, #296	@ 0x128
+ 8031624:	f5a3 7392 	sub.w	r3, r3, #292	@ 0x124
+ 8031628:	681b      	ldr	r3, [r3, #0]
+ 803162a:	6393      	str	r3, [r2, #56]	@ 0x38
+    HAL_NVIC_SetPriority(USART3_IRQn, 0, 0);
+ 803162c:	2200      	movs	r2, #0
+ 803162e:	2100      	movs	r1, #0
+ 8031630:	2027      	movs	r0, #39	@ 0x27
+ 8031632:	f001 fa3e 	bl	8032ab2 <HAL_NVIC_SetPriority>
+    HAL_NVIC_EnableIRQ(USART3_IRQn);
+ 8031636:	2027      	movs	r0, #39	@ 0x27
+ 8031638:	f001 fa55 	bl	8032ae6 <HAL_NVIC_EnableIRQ>
+}
+ 803163c:	e0b1      	b.n	80317a2 <HAL_UART_MspInit+0xb06>
+  else if(uartHandle->Instance==USART6)
+ 803163e:	f507 7394 	add.w	r3, r7, #296	@ 0x128
+ 8031642:	f5a3 7392 	sub.w	r3, r3, #292	@ 0x124
+ 8031646:	681b      	ldr	r3, [r3, #0]
+ 8031648:	681b      	ldr	r3, [r3, #0]
+ 803164a:	4a5d      	ldr	r2, [pc, #372]	@ (80317c0 <HAL_UART_MspInit+0xb24>)
+ 803164c:	4293      	cmp	r3, r2
+ 803164e:	f040 80a8 	bne.w	80317a2 <HAL_UART_MspInit+0xb06>
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART6;
+ 8031652:	f04f 0201 	mov.w	r2, #1
+ 8031656:	f04f 0300 	mov.w	r3, #0
+ 803165a:	e9c7 2314 	strd	r2, r3, [r7, #80]	@ 0x50
+    PeriphClkInitStruct.Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2;
+ 803165e:	2300      	movs	r3, #0
+ 8031660:	f8c7 30cc 	str.w	r3, [r7, #204]	@ 0xcc
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+ 8031664:	f107 0350 	add.w	r3, r7, #80	@ 0x50
+ 8031668:	4618      	mov	r0, r3
+ 803166a:	f008 fd0b 	bl	803a084 <HAL_RCCEx_PeriphCLKConfig>
+ 803166e:	4603      	mov	r3, r0
+ 8031670:	2b00      	cmp	r3, #0
+ 8031672:	d001      	beq.n	8031678 <HAL_UART_MspInit+0x9dc>
+      Error_Handler();
+ 8031674:	f7fe fa08 	bl	802fa88 <Error_Handler>
+    __HAL_RCC_USART6_CLK_ENABLE();
+ 8031678:	4b4d      	ldr	r3, [pc, #308]	@ (80317b0 <HAL_UART_MspInit+0xb14>)
+ 803167a:	f8d3 30f0 	ldr.w	r3, [r3, #240]	@ 0xf0
+ 803167e:	4a4c      	ldr	r2, [pc, #304]	@ (80317b0 <HAL_UART_MspInit+0xb14>)
+ 8031680:	f043 0320 	orr.w	r3, r3, #32
+ 8031684:	f8c2 30f0 	str.w	r3, [r2, #240]	@ 0xf0
+ 8031688:	4b49      	ldr	r3, [pc, #292]	@ (80317b0 <HAL_UART_MspInit+0xb14>)
+ 803168a:	f8d3 30f0 	ldr.w	r3, [r3, #240]	@ 0xf0
+ 803168e:	f003 0220 	and.w	r2, r3, #32
+ 8031692:	f507 7394 	add.w	r3, r7, #296	@ 0x128
+ 8031696:	f5a3 738c 	sub.w	r3, r3, #280	@ 0x118
+ 803169a:	601a      	str	r2, [r3, #0]
+ 803169c:	f507 7394 	add.w	r3, r7, #296	@ 0x128
+ 80316a0:	f5a3 738c 	sub.w	r3, r3, #280	@ 0x118
+ 80316a4:	681b      	ldr	r3, [r3, #0]
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+ 80316a6:	4b42      	ldr	r3, [pc, #264]	@ (80317b0 <HAL_UART_MspInit+0xb14>)
+ 80316a8:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
+ 80316ac:	4a40      	ldr	r2, [pc, #256]	@ (80317b0 <HAL_UART_MspInit+0xb14>)
+ 80316ae:	f043 0304 	orr.w	r3, r3, #4
+ 80316b2:	f8c2 30e0 	str.w	r3, [r2, #224]	@ 0xe0
+ 80316b6:	4b3e      	ldr	r3, [pc, #248]	@ (80317b0 <HAL_UART_MspInit+0xb14>)
+ 80316b8:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
+ 80316bc:	f003 0204 	and.w	r2, r3, #4
+ 80316c0:	f507 7394 	add.w	r3, r7, #296	@ 0x128
+ 80316c4:	f5a3 738e 	sub.w	r3, r3, #284	@ 0x11c
+ 80316c8:	601a      	str	r2, [r3, #0]
+ 80316ca:	f507 7394 	add.w	r3, r7, #296	@ 0x128
+ 80316ce:	f5a3 738e 	sub.w	r3, r3, #284	@ 0x11c
+ 80316d2:	681b      	ldr	r3, [r3, #0]
+    GPIO_InitStruct.Pin = GPIO_PIN_6;
+ 80316d4:	2340      	movs	r3, #64	@ 0x40
+ 80316d6:	f8c7 3114 	str.w	r3, [r7, #276]	@ 0x114
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 80316da:	2302      	movs	r3, #2
+ 80316dc:	f8c7 3118 	str.w	r3, [r7, #280]	@ 0x118
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 80316e0:	2300      	movs	r3, #0
+ 80316e2:	f8c7 311c 	str.w	r3, [r7, #284]	@ 0x11c
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 80316e6:	2300      	movs	r3, #0
+ 80316e8:	f8c7 3120 	str.w	r3, [r7, #288]	@ 0x120
+    GPIO_InitStruct.Alternate = GPIO_AF7_USART6;
+ 80316ec:	2307      	movs	r3, #7
+ 80316ee:	f8c7 3124 	str.w	r3, [r7, #292]	@ 0x124
+    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+ 80316f2:	f507 738a 	add.w	r3, r7, #276	@ 0x114
+ 80316f6:	4619      	mov	r1, r3
+ 80316f8:	4832      	ldr	r0, [pc, #200]	@ (80317c4 <HAL_UART_MspInit+0xb28>)
+ 80316fa:	f005 ff6f 	bl	80375dc <HAL_GPIO_Init>
+    GPIO_InitStruct.Pin = GPIO_PIN_7;
+ 80316fe:	2380      	movs	r3, #128	@ 0x80
+ 8031700:	f8c7 3114 	str.w	r3, [r7, #276]	@ 0x114
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 8031704:	2302      	movs	r3, #2
+ 8031706:	f8c7 3118 	str.w	r3, [r7, #280]	@ 0x118
+    GPIO_InitStruct.Pull = GPIO_PULLUP;
+ 803170a:	2301      	movs	r3, #1
+ 803170c:	f8c7 311c 	str.w	r3, [r7, #284]	@ 0x11c
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ 8031710:	2303      	movs	r3, #3
+ 8031712:	f8c7 3120 	str.w	r3, [r7, #288]	@ 0x120
+    GPIO_InitStruct.Alternate = GPIO_AF7_USART6;
+ 8031716:	2307      	movs	r3, #7
+ 8031718:	f8c7 3124 	str.w	r3, [r7, #292]	@ 0x124
+    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+ 803171c:	f507 738a 	add.w	r3, r7, #276	@ 0x114
+ 8031720:	4619      	mov	r1, r3
+ 8031722:	4828      	ldr	r0, [pc, #160]	@ (80317c4 <HAL_UART_MspInit+0xb28>)
+ 8031724:	f005 ff5a 	bl	80375dc <HAL_GPIO_Init>
+    hdma_usart6_tx.Instance = DMA1_Stream7;
+ 8031728:	4b27      	ldr	r3, [pc, #156]	@ (80317c8 <HAL_UART_MspInit+0xb2c>)
+ 803172a:	4a28      	ldr	r2, [pc, #160]	@ (80317cc <HAL_UART_MspInit+0xb30>)
+ 803172c:	601a      	str	r2, [r3, #0]
+    hdma_usart6_tx.Init.Request = DMA_REQUEST_USART6_TX;
+ 803172e:	4b26      	ldr	r3, [pc, #152]	@ (80317c8 <HAL_UART_MspInit+0xb2c>)
+ 8031730:	2248      	movs	r2, #72	@ 0x48
+ 8031732:	605a      	str	r2, [r3, #4]
+    hdma_usart6_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
+ 8031734:	4b24      	ldr	r3, [pc, #144]	@ (80317c8 <HAL_UART_MspInit+0xb2c>)
+ 8031736:	2240      	movs	r2, #64	@ 0x40
+ 8031738:	609a      	str	r2, [r3, #8]
+    hdma_usart6_tx.Init.PeriphInc = DMA_PINC_DISABLE;
+ 803173a:	4b23      	ldr	r3, [pc, #140]	@ (80317c8 <HAL_UART_MspInit+0xb2c>)
+ 803173c:	2200      	movs	r2, #0
+ 803173e:	60da      	str	r2, [r3, #12]
+    hdma_usart6_tx.Init.MemInc = DMA_MINC_ENABLE;
+ 8031740:	4b21      	ldr	r3, [pc, #132]	@ (80317c8 <HAL_UART_MspInit+0xb2c>)
+ 8031742:	f44f 6280 	mov.w	r2, #1024	@ 0x400
+ 8031746:	611a      	str	r2, [r3, #16]
+    hdma_usart6_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+ 8031748:	4b1f      	ldr	r3, [pc, #124]	@ (80317c8 <HAL_UART_MspInit+0xb2c>)
+ 803174a:	2200      	movs	r2, #0
+ 803174c:	615a      	str	r2, [r3, #20]
+    hdma_usart6_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+ 803174e:	4b1e      	ldr	r3, [pc, #120]	@ (80317c8 <HAL_UART_MspInit+0xb2c>)
+ 8031750:	2200      	movs	r2, #0
+ 8031752:	619a      	str	r2, [r3, #24]
+    hdma_usart6_tx.Init.Mode = DMA_NORMAL;
+ 8031754:	4b1c      	ldr	r3, [pc, #112]	@ (80317c8 <HAL_UART_MspInit+0xb2c>)
+ 8031756:	2200      	movs	r2, #0
+ 8031758:	61da      	str	r2, [r3, #28]
+    hdma_usart6_tx.Init.Priority = DMA_PRIORITY_LOW;
+ 803175a:	4b1b      	ldr	r3, [pc, #108]	@ (80317c8 <HAL_UART_MspInit+0xb2c>)
+ 803175c:	2200      	movs	r2, #0
+ 803175e:	621a      	str	r2, [r3, #32]
+    hdma_usart6_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
+ 8031760:	4b19      	ldr	r3, [pc, #100]	@ (80317c8 <HAL_UART_MspInit+0xb2c>)
+ 8031762:	2200      	movs	r2, #0
+ 8031764:	625a      	str	r2, [r3, #36]	@ 0x24
+    if (HAL_DMA_Init(&hdma_usart6_tx) != HAL_OK)
+ 8031766:	4818      	ldr	r0, [pc, #96]	@ (80317c8 <HAL_UART_MspInit+0xb2c>)
+ 8031768:	f001 fa50 	bl	8032c0c <HAL_DMA_Init>
+ 803176c:	4603      	mov	r3, r0
+ 803176e:	2b00      	cmp	r3, #0
+ 8031770:	d001      	beq.n	8031776 <HAL_UART_MspInit+0xada>
+      Error_Handler();
+ 8031772:	f7fe f989 	bl	802fa88 <Error_Handler>
+    __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart6_tx);
+ 8031776:	f507 7394 	add.w	r3, r7, #296	@ 0x128
+ 803177a:	f5a3 7392 	sub.w	r3, r3, #292	@ 0x124
+ 803177e:	681b      	ldr	r3, [r3, #0]
+ 8031780:	4a11      	ldr	r2, [pc, #68]	@ (80317c8 <HAL_UART_MspInit+0xb2c>)
+ 8031782:	67da      	str	r2, [r3, #124]	@ 0x7c
+ 8031784:	4a10      	ldr	r2, [pc, #64]	@ (80317c8 <HAL_UART_MspInit+0xb2c>)
+ 8031786:	f507 7394 	add.w	r3, r7, #296	@ 0x128
+ 803178a:	f5a3 7392 	sub.w	r3, r3, #292	@ 0x124
+ 803178e:	681b      	ldr	r3, [r3, #0]
+ 8031790:	6393      	str	r3, [r2, #56]	@ 0x38
+    HAL_NVIC_SetPriority(USART6_IRQn, 0, 0);
+ 8031792:	2200      	movs	r2, #0
+ 8031794:	2100      	movs	r1, #0
+ 8031796:	2047      	movs	r0, #71	@ 0x47
+ 8031798:	f001 f98b 	bl	8032ab2 <HAL_NVIC_SetPriority>
+    HAL_NVIC_EnableIRQ(USART6_IRQn);
+ 803179c:	2047      	movs	r0, #71	@ 0x47
+ 803179e:	f001 f9a2 	bl	8032ae6 <HAL_NVIC_EnableIRQ>
+}
+ 80317a2:	bf00      	nop
+ 80317a4:	f507 7794 	add.w	r7, r7, #296	@ 0x128
+ 80317a8:	46bd      	mov	sp, r7
+ 80317aa:	bd80      	pop	{r7, pc}
+ 80317ac:	40004800 	.word	0x40004800
+ 80317b0:	58024400 	.word	0x58024400
+ 80317b4:	58020c00 	.word	0x58020c00
+ 80317b8:	2400b188 	.word	0x2400b188
+ 80317bc:	400200a0 	.word	0x400200a0
+ 80317c0:	40011400 	.word	0x40011400
+ 80317c4:	58020800 	.word	0x58020800
+ 80317c8:	2400b200 	.word	0x2400b200
+ 80317cc:	400200b8 	.word	0x400200b8
+
+080317d0 <Reset_Handler>:
+ 80317d0:	f8df d034 	ldr.w	sp, [pc, #52]	@ 8031808 <LoopFillZerobss+0xe>
+ 80317d4:	f7fe fe4a 	bl	803046c <SystemInit>
+ 80317d8:	480c      	ldr	r0, [pc, #48]	@ (803180c <LoopFillZerobss+0x12>)
+ 80317da:	490d      	ldr	r1, [pc, #52]	@ (8031810 <LoopFillZerobss+0x16>)
+ 80317dc:	4a0d      	ldr	r2, [pc, #52]	@ (8031814 <LoopFillZerobss+0x1a>)
+ 80317de:	2300      	movs	r3, #0
+ 80317e0:	e002      	b.n	80317e8 <LoopCopyDataInit>
+
+080317e2 <CopyDataInit>:
+ 80317e2:	58d4      	ldr	r4, [r2, r3]
+ 80317e4:	50c4      	str	r4, [r0, r3]
+ 80317e6:	3304      	adds	r3, #4
+
+080317e8 <LoopCopyDataInit>:
+ 80317e8:	18c4      	adds	r4, r0, r3
+ 80317ea:	428c      	cmp	r4, r1
+ 80317ec:	d3f9      	bcc.n	80317e2 <CopyDataInit>
+ 80317ee:	4a0a      	ldr	r2, [pc, #40]	@ (8031818 <LoopFillZerobss+0x1e>)
+ 80317f0:	4c0a      	ldr	r4, [pc, #40]	@ (803181c <LoopFillZerobss+0x22>)
+ 80317f2:	2300      	movs	r3, #0
+ 80317f4:	e001      	b.n	80317fa <LoopFillZerobss>
+
+080317f6 <FillZerobss>:
+ 80317f6:	6013      	str	r3, [r2, #0]
+ 80317f8:	3204      	adds	r2, #4
+
+080317fa <LoopFillZerobss>:
+ 80317fa:	42a2      	cmp	r2, r4
+ 80317fc:	d3fb      	bcc.n	80317f6 <FillZerobss>
+ 80317fe:	f00e fdb7 	bl	8040370 <__libc_init_array>
+ 8031802:	f7fd fead 	bl	802f560 <main>
+ 8031806:	4770      	bx	lr
+ 8031808:	24080000 	.word	0x24080000
+ 803180c:	24000000 	.word	0x24000000
+ 8031810:	2400018c 	.word	0x2400018c
+ 8031814:	08041e60 	.word	0x08041e60
+ 8031818:	24000250 	.word	0x24000250
+ 803181c:	2400b3c4 	.word	0x2400b3c4
+
+08031820 <ADC3_IRQHandler>:
+ 8031820:	e7fe      	b.n	8031820 <ADC3_IRQHandler>
+	...
+
+08031824 <HAL_Init>:
+  *         need to ensure that the SysTick time base is always set to 1 millisecond
+  *         to have correct HAL operation.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_Init(void)
+{
+ 8031824:	b580      	push	{r7, lr}
+ 8031826:	b082      	sub	sp, #8
+ 8031828:	af00      	add	r7, sp, #0
+   __HAL_ART_CONFIG_BASE_ADDRESS(0x08100000UL);  /* Configure the Cortex-M4 ART Base address to the Flash Bank 2 : */
+   __HAL_ART_ENABLE();                           /* Enable the Cortex-M4 ART */
+#endif /* DUAL_CORE &&  CORE_CM4 */
+
+  /* Set Interrupt Group Priority */
+  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+ 803182a:	2003      	movs	r0, #3
+ 803182c:	f001 f936 	bl	8032a9c <HAL_NVIC_SetPriorityGrouping>
+
+  /* Update the SystemCoreClock global variable */
+#if defined(RCC_D1CFGR_D1CPRE)
+  common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
+ 8031830:	f008 fa36 	bl	8039ca0 <HAL_RCC_GetSysClockFreq>
+ 8031834:	4602      	mov	r2, r0
+ 8031836:	4b15      	ldr	r3, [pc, #84]	@ (803188c <HAL_Init+0x68>)
+ 8031838:	699b      	ldr	r3, [r3, #24]
+ 803183a:	0a1b      	lsrs	r3, r3, #8
+ 803183c:	f003 030f 	and.w	r3, r3, #15
+ 8031840:	4913      	ldr	r1, [pc, #76]	@ (8031890 <HAL_Init+0x6c>)
+ 8031842:	5ccb      	ldrb	r3, [r1, r3]
+ 8031844:	f003 031f 	and.w	r3, r3, #31
+ 8031848:	fa22 f303 	lsr.w	r3, r2, r3
+ 803184c:	607b      	str	r3, [r7, #4]
+  common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU);
+#endif
+
+  /* Update the SystemD2Clock global variable */
+#if defined(RCC_D1CFGR_HPRE)
+  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
+ 803184e:	4b0f      	ldr	r3, [pc, #60]	@ (803188c <HAL_Init+0x68>)
+ 8031850:	699b      	ldr	r3, [r3, #24]
+ 8031852:	f003 030f 	and.w	r3, r3, #15
+ 8031856:	4a0e      	ldr	r2, [pc, #56]	@ (8031890 <HAL_Init+0x6c>)
+ 8031858:	5cd3      	ldrb	r3, [r2, r3]
+ 803185a:	f003 031f 	and.w	r3, r3, #31
+ 803185e:	687a      	ldr	r2, [r7, #4]
+ 8031860:	fa22 f303 	lsr.w	r3, r2, r3
+ 8031864:	4a0b      	ldr	r2, [pc, #44]	@ (8031894 <HAL_Init+0x70>)
+ 8031866:	6013      	str	r3, [r2, #0]
+#endif
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+  SystemCoreClock = SystemD2Clock;
+#else
+  SystemCoreClock = common_system_clock;
+ 8031868:	4a0b      	ldr	r2, [pc, #44]	@ (8031898 <HAL_Init+0x74>)
+ 803186a:	687b      	ldr	r3, [r7, #4]
+ 803186c:	6013      	str	r3, [r2, #0]
+#endif /* DUAL_CORE && CORE_CM4 */
+
+  /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
+  if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
+ 803186e:	200f      	movs	r0, #15
+ 8031870:	f000 f814 	bl	803189c <HAL_InitTick>
+ 8031874:	4603      	mov	r3, r0
+ 8031876:	2b00      	cmp	r3, #0
+ 8031878:	d001      	beq.n	803187e <HAL_Init+0x5a>
+  {
+    return HAL_ERROR;
+ 803187a:	2301      	movs	r3, #1
+ 803187c:	e002      	b.n	8031884 <HAL_Init+0x60>
+  }
+
+  /* Init the low level hardware */
+  HAL_MspInit();
+ 803187e:	f7fe fc83 	bl	8030188 <HAL_MspInit>
+
+  /* Return function status */
+  return HAL_OK;
+ 8031882:	2300      	movs	r3, #0
+}
+ 8031884:	4618      	mov	r0, r3
+ 8031886:	3708      	adds	r7, #8
+ 8031888:	46bd      	mov	sp, r7
+ 803188a:	bd80      	pop	{r7, pc}
+ 803188c:	58024400 	.word	0x58024400
+ 8031890:	08041c58 	.word	0x08041c58
+ 8031894:	24000130 	.word	0x24000130
+ 8031898:	2400012c 	.word	0x2400012c
+
+0803189c <HAL_InitTick>:
+  *       implementation  in user file.
+  * @param TickPriority: Tick interrupt priority.
+  * @retval HAL status
+  */
+__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+{
+ 803189c:	b580      	push	{r7, lr}
+ 803189e:	b082      	sub	sp, #8
+ 80318a0:	af00      	add	r7, sp, #0
+ 80318a2:	6078      	str	r0, [r7, #4]
+  /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that don't take the value zero)*/
+  if((uint32_t)uwTickFreq == 0UL)
+ 80318a4:	4b15      	ldr	r3, [pc, #84]	@ (80318fc <HAL_InitTick+0x60>)
+ 80318a6:	781b      	ldrb	r3, [r3, #0]
+ 80318a8:	2b00      	cmp	r3, #0
+ 80318aa:	d101      	bne.n	80318b0 <HAL_InitTick+0x14>
+  {
+    return HAL_ERROR;
+ 80318ac:	2301      	movs	r3, #1
+ 80318ae:	e021      	b.n	80318f4 <HAL_InitTick+0x58>
+  }
+
+    /* Configure the SysTick to have interrupt in 1ms time basis*/
+    if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U)
+ 80318b0:	4b13      	ldr	r3, [pc, #76]	@ (8031900 <HAL_InitTick+0x64>)
+ 80318b2:	681a      	ldr	r2, [r3, #0]
+ 80318b4:	4b11      	ldr	r3, [pc, #68]	@ (80318fc <HAL_InitTick+0x60>)
+ 80318b6:	781b      	ldrb	r3, [r3, #0]
+ 80318b8:	4619      	mov	r1, r3
+ 80318ba:	f44f 737a 	mov.w	r3, #1000	@ 0x3e8
+ 80318be:	fbb3 f3f1 	udiv	r3, r3, r1
+ 80318c2:	fbb2 f3f3 	udiv	r3, r2, r3
+ 80318c6:	4618      	mov	r0, r3
+ 80318c8:	f001 f91b 	bl	8032b02 <HAL_SYSTICK_Config>
+ 80318cc:	4603      	mov	r3, r0
+ 80318ce:	2b00      	cmp	r3, #0
+ 80318d0:	d001      	beq.n	80318d6 <HAL_InitTick+0x3a>
+    {
+      return HAL_ERROR;
+ 80318d2:	2301      	movs	r3, #1
+ 80318d4:	e00e      	b.n	80318f4 <HAL_InitTick+0x58>
+    }
+
+  /* Configure the SysTick IRQ priority */
+  if (TickPriority < (1UL << __NVIC_PRIO_BITS))
+ 80318d6:	687b      	ldr	r3, [r7, #4]
+ 80318d8:	2b0f      	cmp	r3, #15
+ 80318da:	d80a      	bhi.n	80318f2 <HAL_InitTick+0x56>
+  {
+    HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
+ 80318dc:	2200      	movs	r2, #0
+ 80318de:	6879      	ldr	r1, [r7, #4]
+ 80318e0:	f04f 30ff 	mov.w	r0, #4294967295
+ 80318e4:	f001 f8e5 	bl	8032ab2 <HAL_NVIC_SetPriority>
+    uwTickPrio = TickPriority;
+ 80318e8:	4a06      	ldr	r2, [pc, #24]	@ (8031904 <HAL_InitTick+0x68>)
+ 80318ea:	687b      	ldr	r3, [r7, #4]
+ 80318ec:	6013      	str	r3, [r2, #0]
+  {
+    return HAL_ERROR;
+  }
+
+  /* Return function status */
+  return HAL_OK;
+ 80318ee:	2300      	movs	r3, #0
+ 80318f0:	e000      	b.n	80318f4 <HAL_InitTick+0x58>
+    return HAL_ERROR;
+ 80318f2:	2301      	movs	r3, #1
+}
+ 80318f4:	4618      	mov	r0, r3
+ 80318f6:	3708      	adds	r7, #8
+ 80318f8:	46bd      	mov	sp, r7
+ 80318fa:	bd80      	pop	{r7, pc}
+ 80318fc:	24000138 	.word	0x24000138
+ 8031900:	2400012c 	.word	0x2400012c
+ 8031904:	24000134 	.word	0x24000134
+
+08031908 <HAL_IncTick>:
+ * @note This function is declared as __weak to be overwritten in case of other
+  *      implementations in user file.
+  * @retval None
+  */
+__weak void HAL_IncTick(void)
+{
+ 8031908:	b480      	push	{r7}
+ 803190a:	af00      	add	r7, sp, #0
+  uwTick += (uint32_t)uwTickFreq;
+ 803190c:	4b06      	ldr	r3, [pc, #24]	@ (8031928 <HAL_IncTick+0x20>)
+ 803190e:	781b      	ldrb	r3, [r3, #0]
+ 8031910:	461a      	mov	r2, r3
+ 8031912:	4b06      	ldr	r3, [pc, #24]	@ (803192c <HAL_IncTick+0x24>)
+ 8031914:	681b      	ldr	r3, [r3, #0]
+ 8031916:	4413      	add	r3, r2
+ 8031918:	4a04      	ldr	r2, [pc, #16]	@ (803192c <HAL_IncTick+0x24>)
+ 803191a:	6013      	str	r3, [r2, #0]
+}
+ 803191c:	bf00      	nop
+ 803191e:	46bd      	mov	sp, r7
+ 8031920:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8031924:	4770      	bx	lr
+ 8031926:	bf00      	nop
+ 8031928:	24000138 	.word	0x24000138
+ 803192c:	2400b278 	.word	0x2400b278
+
+08031930 <HAL_GetTick>:
+  * @note This function is declared as __weak to be overwritten in case of other
+  *       implementations in user file.
+  * @retval tick value
+  */
+__weak uint32_t HAL_GetTick(void)
+{
+ 8031930:	b480      	push	{r7}
+ 8031932:	af00      	add	r7, sp, #0
+  return uwTick;
+ 8031934:	4b03      	ldr	r3, [pc, #12]	@ (8031944 <HAL_GetTick+0x14>)
+ 8031936:	681b      	ldr	r3, [r3, #0]
+}
+ 8031938:	4618      	mov	r0, r3
+ 803193a:	46bd      	mov	sp, r7
+ 803193c:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8031940:	4770      	bx	lr
+ 8031942:	bf00      	nop
+ 8031944:	2400b278 	.word	0x2400b278
+
+08031948 <HAL_Delay>:
+  *       implementations in user file.
+  * @param Delay  specifies the delay time length, in milliseconds.
+  * @retval None
+  */
+__weak void HAL_Delay(uint32_t Delay)
+{
+ 8031948:	b580      	push	{r7, lr}
+ 803194a:	b084      	sub	sp, #16
+ 803194c:	af00      	add	r7, sp, #0
+ 803194e:	6078      	str	r0, [r7, #4]
+  uint32_t tickstart = HAL_GetTick();
+ 8031950:	f7ff ffee 	bl	8031930 <HAL_GetTick>
+ 8031954:	60b8      	str	r0, [r7, #8]
+  uint32_t wait = Delay;
+ 8031956:	687b      	ldr	r3, [r7, #4]
+ 8031958:	60fb      	str	r3, [r7, #12]
+
+  /* Add a freq to guarantee minimum wait */
+  if (wait < HAL_MAX_DELAY)
+ 803195a:	68fb      	ldr	r3, [r7, #12]
+ 803195c:	f1b3 3fff 	cmp.w	r3, #4294967295
+ 8031960:	d005      	beq.n	803196e <HAL_Delay+0x26>
+  {
+    wait += (uint32_t)(uwTickFreq);
+ 8031962:	4b0a      	ldr	r3, [pc, #40]	@ (803198c <HAL_Delay+0x44>)
+ 8031964:	781b      	ldrb	r3, [r3, #0]
+ 8031966:	461a      	mov	r2, r3
+ 8031968:	68fb      	ldr	r3, [r7, #12]
+ 803196a:	4413      	add	r3, r2
+ 803196c:	60fb      	str	r3, [r7, #12]
+  }
+
+  while ((HAL_GetTick() - tickstart) < wait)
+ 803196e:	bf00      	nop
+ 8031970:	f7ff ffde 	bl	8031930 <HAL_GetTick>
+ 8031974:	4602      	mov	r2, r0
+ 8031976:	68bb      	ldr	r3, [r7, #8]
+ 8031978:	1ad3      	subs	r3, r2, r3
+ 803197a:	68fa      	ldr	r2, [r7, #12]
+ 803197c:	429a      	cmp	r2, r3
+ 803197e:	d8f7      	bhi.n	8031970 <HAL_Delay+0x28>
+  {
+  }
+}
+ 8031980:	bf00      	nop
+ 8031982:	bf00      	nop
+ 8031984:	3710      	adds	r7, #16
+ 8031986:	46bd      	mov	sp, r7
+ 8031988:	bd80      	pop	{r7, pc}
+ 803198a:	bf00      	nop
+ 803198c:	24000138 	.word	0x24000138
+
+08031990 <HAL_GetREVID>:
+/**
+  * @brief  Returns the device revision identifier.
+  * @retval Device revision identifier
+  */
+uint32_t HAL_GetREVID(void)
+{
+ 8031990:	b480      	push	{r7}
+ 8031992:	af00      	add	r7, sp, #0
+   return((DBGMCU->IDCODE) >> 16);
+ 8031994:	4b03      	ldr	r3, [pc, #12]	@ (80319a4 <HAL_GetREVID+0x14>)
+ 8031996:	681b      	ldr	r3, [r3, #0]
+ 8031998:	0c1b      	lsrs	r3, r3, #16
+}
+ 803199a:	4618      	mov	r0, r3
+ 803199c:	46bd      	mov	sp, r7
+ 803199e:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80319a2:	4770      	bx	lr
+ 80319a4:	5c001000 	.word	0x5c001000
+
+080319a8 <HAL_SYSCFG_ETHInterfaceSelect>:
+  *   @arg SYSCFG_ETH_MII : Select the Media Independent Interface
+  *   @arg SYSCFG_ETH_RMII: Select the Reduced Media Independent Interface
+  * @retval None
+  */
+void HAL_SYSCFG_ETHInterfaceSelect(uint32_t SYSCFG_ETHInterface)
+{
+ 80319a8:	b480      	push	{r7}
+ 80319aa:	b083      	sub	sp, #12
+ 80319ac:	af00      	add	r7, sp, #0
+ 80319ae:	6078      	str	r0, [r7, #4]
+  /* Check the parameter */
+  assert_param(IS_SYSCFG_ETHERNET_CONFIG(SYSCFG_ETHInterface));
+
+  MODIFY_REG(SYSCFG->PMCR, SYSCFG_PMCR_EPIS_SEL, (uint32_t)(SYSCFG_ETHInterface));
+ 80319b0:	4b06      	ldr	r3, [pc, #24]	@ (80319cc <HAL_SYSCFG_ETHInterfaceSelect+0x24>)
+ 80319b2:	685b      	ldr	r3, [r3, #4]
+ 80319b4:	f423 0260 	bic.w	r2, r3, #14680064	@ 0xe00000
+ 80319b8:	4904      	ldr	r1, [pc, #16]	@ (80319cc <HAL_SYSCFG_ETHInterfaceSelect+0x24>)
+ 80319ba:	687b      	ldr	r3, [r7, #4]
+ 80319bc:	4313      	orrs	r3, r2
+ 80319be:	604b      	str	r3, [r1, #4]
+}
+ 80319c0:	bf00      	nop
+ 80319c2:	370c      	adds	r7, #12
+ 80319c4:	46bd      	mov	sp, r7
+ 80319c6:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80319ca:	4770      	bx	lr
+ 80319cc:	58000400 	.word	0x58000400
+
+080319d0 <LL_ADC_SetCommonClock>:
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
+{
+ 80319d0:	b480      	push	{r7}
+ 80319d2:	b083      	sub	sp, #12
+ 80319d4:	af00      	add	r7, sp, #0
+ 80319d6:	6078      	str	r0, [r7, #4]
+ 80319d8:	6039      	str	r1, [r7, #0]
+  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock);
+ 80319da:	687b      	ldr	r3, [r7, #4]
+ 80319dc:	689b      	ldr	r3, [r3, #8]
+ 80319de:	f423 127c 	bic.w	r2, r3, #4128768	@ 0x3f0000
+ 80319e2:	683b      	ldr	r3, [r7, #0]
+ 80319e4:	431a      	orrs	r2, r3
+ 80319e6:	687b      	ldr	r3, [r7, #4]
+ 80319e8:	609a      	str	r2, [r3, #8]
+}
+ 80319ea:	bf00      	nop
+ 80319ec:	370c      	adds	r7, #12
+ 80319ee:	46bd      	mov	sp, r7
+ 80319f0:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80319f4:	4770      	bx	lr
+
+080319f6 <LL_ADC_SetCommonPathInternalCh>:
+  *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
+  *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
+{
+ 80319f6:	b480      	push	{r7}
+ 80319f8:	b083      	sub	sp, #12
+ 80319fa:	af00      	add	r7, sp, #0
+ 80319fc:	6078      	str	r0, [r7, #4]
+ 80319fe:	6039      	str	r1, [r7, #0]
+  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal);
+ 8031a00:	687b      	ldr	r3, [r7, #4]
+ 8031a02:	689b      	ldr	r3, [r3, #8]
+ 8031a04:	f023 72e0 	bic.w	r2, r3, #29360128	@ 0x1c00000
+ 8031a08:	683b      	ldr	r3, [r7, #0]
+ 8031a0a:	431a      	orrs	r2, r3
+ 8031a0c:	687b      	ldr	r3, [r7, #4]
+ 8031a0e:	609a      	str	r2, [r3, #8]
+}
+ 8031a10:	bf00      	nop
+ 8031a12:	370c      	adds	r7, #12
+ 8031a14:	46bd      	mov	sp, r7
+ 8031a16:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8031a1a:	4770      	bx	lr
+
+08031a1c <LL_ADC_GetCommonPathInternalCh>:
+  *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+  *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
+  *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ 8031a1c:	b480      	push	{r7}
+ 8031a1e:	b083      	sub	sp, #12
+ 8031a20:	af00      	add	r7, sp, #0
+ 8031a22:	6078      	str	r0, [r7, #4]
+  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN));
+ 8031a24:	687b      	ldr	r3, [r7, #4]
+ 8031a26:	689b      	ldr	r3, [r3, #8]
+ 8031a28:	f003 73e0 	and.w	r3, r3, #29360128	@ 0x1c00000
+}
+ 8031a2c:	4618      	mov	r0, r3
+ 8031a2e:	370c      	adds	r7, #12
+ 8031a30:	46bd      	mov	sp, r7
+ 8031a32:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8031a36:	4770      	bx	lr
+
+08031a38 <LL_ADC_SetOffset>:
+  *             Other channels are slow channels (conversion rate: refer to reference manual).
+  * @param  OffsetLevel Value between Min_Data=0x000 and Max_Data=0x3FFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
+{
+ 8031a38:	b480      	push	{r7}
+ 8031a3a:	b087      	sub	sp, #28
+ 8031a3c:	af00      	add	r7, sp, #0
+ 8031a3e:	60f8      	str	r0, [r7, #12]
+ 8031a40:	60b9      	str	r1, [r7, #8]
+ 8031a42:	607a      	str	r2, [r7, #4]
+ 8031a44:	603b      	str	r3, [r7, #0]
+  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+ 8031a46:	68fb      	ldr	r3, [r7, #12]
+ 8031a48:	3360      	adds	r3, #96	@ 0x60
+ 8031a4a:	461a      	mov	r2, r3
+ 8031a4c:	68bb      	ldr	r3, [r7, #8]
+ 8031a4e:	009b      	lsls	r3, r3, #2
+ 8031a50:	4413      	add	r3, r2
+ 8031a52:	617b      	str	r3, [r7, #20]
+               ADC3_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel);
+  }
+  else
+#endif /* ADC_VER_V5_V90 */
+  {
+    MODIFY_REG(*preg,
+ 8031a54:	697b      	ldr	r3, [r7, #20]
+ 8031a56:	681b      	ldr	r3, [r3, #0]
+ 8031a58:	f003 4200 	and.w	r2, r3, #2147483648	@ 0x80000000
+ 8031a5c:	687b      	ldr	r3, [r7, #4]
+ 8031a5e:	f003 41f8 	and.w	r1, r3, #2080374784	@ 0x7c000000
+ 8031a62:	683b      	ldr	r3, [r7, #0]
+ 8031a64:	430b      	orrs	r3, r1
+ 8031a66:	431a      	orrs	r2, r3
+ 8031a68:	697b      	ldr	r3, [r7, #20]
+ 8031a6a:	601a      	str	r2, [r3, #0]
+               ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
+               (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel);
+  }
+}
+ 8031a6c:	bf00      	nop
+ 8031a6e:	371c      	adds	r7, #28
+ 8031a70:	46bd      	mov	sp, r7
+ 8031a72:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8031a76:	4770      	bx	lr
+
+08031a78 <LL_ADC_SetDataRightShift>:
+  *         @arg @ref LL_ADC_OFFSET_RSHIFT_ENABLE
+  *         @arg @ref LL_ADC_OFFSET_RSHIFT_DISABLE
+  * @retval Returned None
+  */
+__STATIC_INLINE void LL_ADC_SetDataRightShift(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t RigthShift)
+{
+ 8031a78:	b480      	push	{r7}
+ 8031a7a:	b085      	sub	sp, #20
+ 8031a7c:	af00      	add	r7, sp, #0
+ 8031a7e:	60f8      	str	r0, [r7, #12]
+ 8031a80:	60b9      	str	r1, [r7, #8]
+ 8031a82:	607a      	str	r2, [r7, #4]
+  MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_RSHIFT1 | ADC_CFGR2_RSHIFT2 | ADC_CFGR2_RSHIFT3 | ADC_CFGR2_RSHIFT4), RigthShift << (Offsety & 0x1FUL));
+ 8031a84:	68fb      	ldr	r3, [r7, #12]
+ 8031a86:	691b      	ldr	r3, [r3, #16]
+ 8031a88:	f423 42f0 	bic.w	r2, r3, #30720	@ 0x7800
+ 8031a8c:	68bb      	ldr	r3, [r7, #8]
+ 8031a8e:	f003 031f 	and.w	r3, r3, #31
+ 8031a92:	6879      	ldr	r1, [r7, #4]
+ 8031a94:	fa01 f303 	lsl.w	r3, r1, r3
+ 8031a98:	431a      	orrs	r2, r3
+ 8031a9a:	68fb      	ldr	r3, [r7, #12]
+ 8031a9c:	611a      	str	r2, [r3, #16]
+}
+ 8031a9e:	bf00      	nop
+ 8031aa0:	3714      	adds	r7, #20
+ 8031aa2:	46bd      	mov	sp, r7
+ 8031aa4:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8031aa8:	4770      	bx	lr
+
+08031aaa <LL_ADC_SetOffsetSignedSaturation>:
+  *         @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE
+  *         @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE
+  * @retval Returned None
+  */
+__STATIC_INLINE void LL_ADC_SetOffsetSignedSaturation(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSignedSaturation)
+{
+ 8031aaa:	b480      	push	{r7}
+ 8031aac:	b087      	sub	sp, #28
+ 8031aae:	af00      	add	r7, sp, #0
+ 8031ab0:	60f8      	str	r0, [r7, #12]
+ 8031ab2:	60b9      	str	r1, [r7, #8]
+ 8031ab4:	607a      	str	r2, [r7, #4]
+    /* Function not available on this instance */
+  }
+  else
+#endif  /* ADC_VER_V5_V90 */
+  {
+    __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+ 8031ab6:	68fb      	ldr	r3, [r7, #12]
+ 8031ab8:	3360      	adds	r3, #96	@ 0x60
+ 8031aba:	461a      	mov	r2, r3
+ 8031abc:	68bb      	ldr	r3, [r7, #8]
+ 8031abe:	009b      	lsls	r3, r3, #2
+ 8031ac0:	4413      	add	r3, r2
+ 8031ac2:	617b      	str	r3, [r7, #20]
+    MODIFY_REG(*preg, ADC_OFR1_SSATE, OffsetSignedSaturation);
+ 8031ac4:	697b      	ldr	r3, [r7, #20]
+ 8031ac6:	681b      	ldr	r3, [r3, #0]
+ 8031ac8:	f023 4200 	bic.w	r2, r3, #2147483648	@ 0x80000000
+ 8031acc:	687b      	ldr	r3, [r7, #4]
+ 8031ace:	431a      	orrs	r2, r3
+ 8031ad0:	697b      	ldr	r3, [r7, #20]
+ 8031ad2:	601a      	str	r2, [r3, #0]
+  }
+}
+ 8031ad4:	bf00      	nop
+ 8031ad6:	371c      	adds	r7, #28
+ 8031ad8:	46bd      	mov	sp, r7
+ 8031ada:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8031ade:	4770      	bx	lr
+
+08031ae0 <LL_ADC_REG_SetSequencerRanks>:
+  *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
+  *             Other channels are slow channels (conversion rate: refer to reference manual).
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
+{
+ 8031ae0:	b480      	push	{r7}
+ 8031ae2:	b087      	sub	sp, #28
+ 8031ae4:	af00      	add	r7, sp, #0
+ 8031ae6:	60f8      	str	r0, [r7, #12]
+ 8031ae8:	60b9      	str	r1, [r7, #8]
+ 8031aea:	607a      	str	r2, [r7, #4]
+  /* Set bits with content of parameter "Channel" with bits position          */
+  /* in register and register position depending on parameter "Rank".         */
+  /* Parameters "Rank" and "Channel" are used with masks because containing   */
+  /* other bits reserved for other purpose.                                   */
+  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
+ 8031aec:	68fb      	ldr	r3, [r7, #12]
+ 8031aee:	3330      	adds	r3, #48	@ 0x30
+ 8031af0:	461a      	mov	r2, r3
+ 8031af2:	68bb      	ldr	r3, [r7, #8]
+ 8031af4:	0a1b      	lsrs	r3, r3, #8
+ 8031af6:	009b      	lsls	r3, r3, #2
+ 8031af8:	f003 030c 	and.w	r3, r3, #12
+ 8031afc:	4413      	add	r3, r2
+ 8031afe:	617b      	str	r3, [r7, #20]
+
+  MODIFY_REG(*preg,
+ 8031b00:	697b      	ldr	r3, [r7, #20]
+ 8031b02:	681a      	ldr	r2, [r3, #0]
+ 8031b04:	68bb      	ldr	r3, [r7, #8]
+ 8031b06:	f003 031f 	and.w	r3, r3, #31
+ 8031b0a:	211f      	movs	r1, #31
+ 8031b0c:	fa01 f303 	lsl.w	r3, r1, r3
+ 8031b10:	43db      	mvns	r3, r3
+ 8031b12:	401a      	ands	r2, r3
+ 8031b14:	687b      	ldr	r3, [r7, #4]
+ 8031b16:	0e9b      	lsrs	r3, r3, #26
+ 8031b18:	f003 011f 	and.w	r1, r3, #31
+ 8031b1c:	68bb      	ldr	r3, [r7, #8]
+ 8031b1e:	f003 031f 	and.w	r3, r3, #31
+ 8031b22:	fa01 f303 	lsl.w	r3, r1, r3
+ 8031b26:	431a      	orrs	r2, r3
+ 8031b28:	697b      	ldr	r3, [r7, #20]
+ 8031b2a:	601a      	str	r2, [r3, #0]
+             ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
+             ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
+}
+ 8031b2c:	bf00      	nop
+ 8031b2e:	371c      	adds	r7, #28
+ 8031b30:	46bd      	mov	sp, r7
+ 8031b32:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8031b36:	4770      	bx	lr
+
+08031b38 <LL_ADC_SetChannelSamplingTime>:
+  *         @arg @ref LL_ADC_SAMPLINGTIME_387CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_810CYCLES_5
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
+{
+ 8031b38:	b480      	push	{r7}
+ 8031b3a:	b087      	sub	sp, #28
+ 8031b3c:	af00      	add	r7, sp, #0
+ 8031b3e:	60f8      	str	r0, [r7, #12]
+ 8031b40:	60b9      	str	r1, [r7, #8]
+ 8031b42:	607a      	str	r2, [r7, #4]
+  /* Set bits with content of parameter "SamplingTime" with bits position     */
+  /* in register and register position depending on parameter "Channel".      */
+  /* Parameter "Channel" is used with masks because containing                */
+  /* other bits reserved for other purpose.                                   */
+  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
+ 8031b44:	68fb      	ldr	r3, [r7, #12]
+ 8031b46:	3314      	adds	r3, #20
+ 8031b48:	461a      	mov	r2, r3
+ 8031b4a:	68bb      	ldr	r3, [r7, #8]
+ 8031b4c:	0e5b      	lsrs	r3, r3, #25
+ 8031b4e:	009b      	lsls	r3, r3, #2
+ 8031b50:	f003 0304 	and.w	r3, r3, #4
+ 8031b54:	4413      	add	r3, r2
+ 8031b56:	617b      	str	r3, [r7, #20]
+
+  MODIFY_REG(*preg,
+ 8031b58:	697b      	ldr	r3, [r7, #20]
+ 8031b5a:	681a      	ldr	r2, [r3, #0]
+ 8031b5c:	68bb      	ldr	r3, [r7, #8]
+ 8031b5e:	0d1b      	lsrs	r3, r3, #20
+ 8031b60:	f003 031f 	and.w	r3, r3, #31
+ 8031b64:	2107      	movs	r1, #7
+ 8031b66:	fa01 f303 	lsl.w	r3, r1, r3
+ 8031b6a:	43db      	mvns	r3, r3
+ 8031b6c:	401a      	ands	r2, r3
+ 8031b6e:	68bb      	ldr	r3, [r7, #8]
+ 8031b70:	0d1b      	lsrs	r3, r3, #20
+ 8031b72:	f003 031f 	and.w	r3, r3, #31
+ 8031b76:	6879      	ldr	r1, [r7, #4]
+ 8031b78:	fa01 f303 	lsl.w	r3, r1, r3
+ 8031b7c:	431a      	orrs	r2, r3
+ 8031b7e:	697b      	ldr	r3, [r7, #20]
+ 8031b80:	601a      	str	r2, [r3, #0]
+             ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS),
+             SamplingTime   << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS));
+}
+ 8031b82:	bf00      	nop
+ 8031b84:	371c      	adds	r7, #28
+ 8031b86:	46bd      	mov	sp, r7
+ 8031b88:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8031b8c:	4770      	bx	lr
+	...
+
+08031b90 <LL_ADC_SetChannelSingleDiff>:
+  *         @arg @ref LL_ADC_SINGLE_ENDED
+  *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
+{
+ 8031b90:	b480      	push	{r7}
+ 8031b92:	b085      	sub	sp, #20
+ 8031b94:	af00      	add	r7, sp, #0
+ 8031b96:	60f8      	str	r0, [r7, #12]
+ 8031b98:	60b9      	str	r1, [r7, #8]
+ 8031b9a:	607a      	str	r2, [r7, #4]
+  }
+#else  /* ADC_VER_V5_V90 */
+  /* Bits of channels in single or differential mode are set only for         */
+  /* differential mode (for single mode, mask of bits allowed to be set is    */
+  /* shifted out of range of bits of channels in single or differential mode. */
+  MODIFY_REG(ADCx->DIFSEL,
+ 8031b9c:	68fb      	ldr	r3, [r7, #12]
+ 8031b9e:	f8d3 20c0 	ldr.w	r2, [r3, #192]	@ 0xc0
+ 8031ba2:	68bb      	ldr	r3, [r7, #8]
+ 8031ba4:	f3c3 0313 	ubfx	r3, r3, #0, #20
+ 8031ba8:	43db      	mvns	r3, r3
+ 8031baa:	401a      	ands	r2, r3
+ 8031bac:	687b      	ldr	r3, [r7, #4]
+ 8031bae:	f003 0318 	and.w	r3, r3, #24
+ 8031bb2:	4908      	ldr	r1, [pc, #32]	@ (8031bd4 <LL_ADC_SetChannelSingleDiff+0x44>)
+ 8031bb4:	40d9      	lsrs	r1, r3
+ 8031bb6:	68bb      	ldr	r3, [r7, #8]
+ 8031bb8:	400b      	ands	r3, r1
+ 8031bba:	f3c3 0313 	ubfx	r3, r3, #0, #20
+ 8031bbe:	431a      	orrs	r2, r3
+ 8031bc0:	68fb      	ldr	r3, [r7, #12]
+ 8031bc2:	f8c3 20c0 	str.w	r2, [r3, #192]	@ 0xc0
+             Channel & ADC_SINGLEDIFF_CHANNEL_MASK,
+             (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));
+#endif /* ADC_VER_V5_V90 */
+}
+ 8031bc6:	bf00      	nop
+ 8031bc8:	3714      	adds	r7, #20
+ 8031bca:	46bd      	mov	sp, r7
+ 8031bcc:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8031bd0:	4770      	bx	lr
+ 8031bd2:	bf00      	nop
+ 8031bd4:	000fffff 	.word	0x000fffff
+
+08031bd8 <LL_ADC_DisableDeepPowerDown>:
+  * @rmtoll CR       DEEPPWD        LL_ADC_DisableDeepPowerDown
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx)
+{
+ 8031bd8:	b480      	push	{r7}
+ 8031bda:	b083      	sub	sp, #12
+ 8031bdc:	af00      	add	r7, sp, #0
+ 8031bde:	6078      	str	r0, [r7, #4]
+  /* Note: Write register with some additional bits forced to state reset     */
+  /*       instead of modifying only the selected bit for this function,      */
+  /*       to not interfere with bits with HW property "rs".                  */
+  CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS));
+ 8031be0:	687b      	ldr	r3, [r7, #4]
+ 8031be2:	689a      	ldr	r2, [r3, #8]
+ 8031be4:	4b04      	ldr	r3, [pc, #16]	@ (8031bf8 <LL_ADC_DisableDeepPowerDown+0x20>)
+ 8031be6:	4013      	ands	r3, r2
+ 8031be8:	687a      	ldr	r2, [r7, #4]
+ 8031bea:	6093      	str	r3, [r2, #8]
+}
+ 8031bec:	bf00      	nop
+ 8031bee:	370c      	adds	r7, #12
+ 8031bf0:	46bd      	mov	sp, r7
+ 8031bf2:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8031bf6:	4770      	bx	lr
+ 8031bf8:	5fffffc0 	.word	0x5fffffc0
+
+08031bfc <LL_ADC_IsDeepPowerDownEnabled>:
+  * @rmtoll CR       DEEPPWD        LL_ADC_IsDeepPowerDownEnabled
+  * @param  ADCx ADC instance
+  * @retval 0: deep power down is disabled, 1: deep power down is enabled.
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx)
+{
+ 8031bfc:	b480      	push	{r7}
+ 8031bfe:	b083      	sub	sp, #12
+ 8031c00:	af00      	add	r7, sp, #0
+ 8031c02:	6078      	str	r0, [r7, #4]
+  return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL);
+ 8031c04:	687b      	ldr	r3, [r7, #4]
+ 8031c06:	689b      	ldr	r3, [r3, #8]
+ 8031c08:	f003 5300 	and.w	r3, r3, #536870912	@ 0x20000000
+ 8031c0c:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
+ 8031c10:	d101      	bne.n	8031c16 <LL_ADC_IsDeepPowerDownEnabled+0x1a>
+ 8031c12:	2301      	movs	r3, #1
+ 8031c14:	e000      	b.n	8031c18 <LL_ADC_IsDeepPowerDownEnabled+0x1c>
+ 8031c16:	2300      	movs	r3, #0
+}
+ 8031c18:	4618      	mov	r0, r3
+ 8031c1a:	370c      	adds	r7, #12
+ 8031c1c:	46bd      	mov	sp, r7
+ 8031c1e:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8031c22:	4770      	bx	lr
+
+08031c24 <LL_ADC_EnableInternalRegulator>:
+  * @rmtoll CR       ADVREGEN       LL_ADC_EnableInternalRegulator
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
+{
+ 8031c24:	b480      	push	{r7}
+ 8031c26:	b083      	sub	sp, #12
+ 8031c28:	af00      	add	r7, sp, #0
+ 8031c2a:	6078      	str	r0, [r7, #4]
+  /* Note: Write register with some additional bits forced to state reset     */
+  /*       instead of modifying only the selected bit for this function,      */
+  /*       to not interfere with bits with HW property "rs".                  */
+  MODIFY_REG(ADCx->CR,
+ 8031c2c:	687b      	ldr	r3, [r7, #4]
+ 8031c2e:	689a      	ldr	r2, [r3, #8]
+ 8031c30:	4b05      	ldr	r3, [pc, #20]	@ (8031c48 <LL_ADC_EnableInternalRegulator+0x24>)
+ 8031c32:	4013      	ands	r3, r2
+ 8031c34:	f043 5280 	orr.w	r2, r3, #268435456	@ 0x10000000
+ 8031c38:	687b      	ldr	r3, [r7, #4]
+ 8031c3a:	609a      	str	r2, [r3, #8]
+             ADC_CR_BITS_PROPERTY_RS,
+             ADC_CR_ADVREGEN);
+}
+ 8031c3c:	bf00      	nop
+ 8031c3e:	370c      	adds	r7, #12
+ 8031c40:	46bd      	mov	sp, r7
+ 8031c42:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8031c46:	4770      	bx	lr
+ 8031c48:	6fffffc0 	.word	0x6fffffc0
+
+08031c4c <LL_ADC_IsInternalRegulatorEnabled>:
+  * @rmtoll CR       ADVREGEN       LL_ADC_IsInternalRegulatorEnabled
+  * @param  ADCx ADC instance
+  * @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx)
+{
+ 8031c4c:	b480      	push	{r7}
+ 8031c4e:	b083      	sub	sp, #12
+ 8031c50:	af00      	add	r7, sp, #0
+ 8031c52:	6078      	str	r0, [r7, #4]
+  return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
+ 8031c54:	687b      	ldr	r3, [r7, #4]
+ 8031c56:	689b      	ldr	r3, [r3, #8]
+ 8031c58:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
+ 8031c5c:	f1b3 5f80 	cmp.w	r3, #268435456	@ 0x10000000
+ 8031c60:	d101      	bne.n	8031c66 <LL_ADC_IsInternalRegulatorEnabled+0x1a>
+ 8031c62:	2301      	movs	r3, #1
+ 8031c64:	e000      	b.n	8031c68 <LL_ADC_IsInternalRegulatorEnabled+0x1c>
+ 8031c66:	2300      	movs	r3, #0
+}
+ 8031c68:	4618      	mov	r0, r3
+ 8031c6a:	370c      	adds	r7, #12
+ 8031c6c:	46bd      	mov	sp, r7
+ 8031c6e:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8031c72:	4770      	bx	lr
+
+08031c74 <LL_ADC_IsEnabled>:
+  * @rmtoll CR       ADEN           LL_ADC_IsEnabled
+  * @param  ADCx ADC instance
+  * @retval 0: ADC is disabled, 1: ADC is enabled.
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
+{
+ 8031c74:	b480      	push	{r7}
+ 8031c76:	b083      	sub	sp, #12
+ 8031c78:	af00      	add	r7, sp, #0
+ 8031c7a:	6078      	str	r0, [r7, #4]
+  return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
+ 8031c7c:	687b      	ldr	r3, [r7, #4]
+ 8031c7e:	689b      	ldr	r3, [r3, #8]
+ 8031c80:	f003 0301 	and.w	r3, r3, #1
+ 8031c84:	2b01      	cmp	r3, #1
+ 8031c86:	d101      	bne.n	8031c8c <LL_ADC_IsEnabled+0x18>
+ 8031c88:	2301      	movs	r3, #1
+ 8031c8a:	e000      	b.n	8031c8e <LL_ADC_IsEnabled+0x1a>
+ 8031c8c:	2300      	movs	r3, #0
+}
+ 8031c8e:	4618      	mov	r0, r3
+ 8031c90:	370c      	adds	r7, #12
+ 8031c92:	46bd      	mov	sp, r7
+ 8031c94:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8031c98:	4770      	bx	lr
+
+08031c9a <LL_ADC_REG_IsConversionOngoing>:
+  * @rmtoll CR       ADSTART        LL_ADC_REG_IsConversionOngoing
+  * @param  ADCx ADC instance
+  * @retval 0: no conversion is on going on ADC group regular.
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx)
+{
+ 8031c9a:	b480      	push	{r7}
+ 8031c9c:	b083      	sub	sp, #12
+ 8031c9e:	af00      	add	r7, sp, #0
+ 8031ca0:	6078      	str	r0, [r7, #4]
+  return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
+ 8031ca2:	687b      	ldr	r3, [r7, #4]
+ 8031ca4:	689b      	ldr	r3, [r3, #8]
+ 8031ca6:	f003 0304 	and.w	r3, r3, #4
+ 8031caa:	2b04      	cmp	r3, #4
+ 8031cac:	d101      	bne.n	8031cb2 <LL_ADC_REG_IsConversionOngoing+0x18>
+ 8031cae:	2301      	movs	r3, #1
+ 8031cb0:	e000      	b.n	8031cb4 <LL_ADC_REG_IsConversionOngoing+0x1a>
+ 8031cb2:	2300      	movs	r3, #0
+}
+ 8031cb4:	4618      	mov	r0, r3
+ 8031cb6:	370c      	adds	r7, #12
+ 8031cb8:	46bd      	mov	sp, r7
+ 8031cba:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8031cbe:	4770      	bx	lr
+
+08031cc0 <LL_ADC_INJ_IsConversionOngoing>:
+  * @rmtoll CR       JADSTART       LL_ADC_INJ_IsConversionOngoing
+  * @param  ADCx ADC instance
+  * @retval 0: no conversion is on going on ADC group injected.
+  */
+__STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx)
+{
+ 8031cc0:	b480      	push	{r7}
+ 8031cc2:	b083      	sub	sp, #12
+ 8031cc4:	af00      	add	r7, sp, #0
+ 8031cc6:	6078      	str	r0, [r7, #4]
+  return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);
+ 8031cc8:	687b      	ldr	r3, [r7, #4]
+ 8031cca:	689b      	ldr	r3, [r3, #8]
+ 8031ccc:	f003 0308 	and.w	r3, r3, #8
+ 8031cd0:	2b08      	cmp	r3, #8
+ 8031cd2:	d101      	bne.n	8031cd8 <LL_ADC_INJ_IsConversionOngoing+0x18>
+ 8031cd4:	2301      	movs	r3, #1
+ 8031cd6:	e000      	b.n	8031cda <LL_ADC_INJ_IsConversionOngoing+0x1a>
+ 8031cd8:	2300      	movs	r3, #0
+}
+ 8031cda:	4618      	mov	r0, r3
+ 8031cdc:	370c      	adds	r7, #12
+ 8031cde:	46bd      	mov	sp, r7
+ 8031ce0:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8031ce4:	4770      	bx	lr
+	...
+
+08031ce8 <HAL_ADC_Init>:
+  *         without  disabling the other ADCs.
+  * @param hadc ADC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
+{
+ 8031ce8:	b590      	push	{r4, r7, lr}
+ 8031cea:	b089      	sub	sp, #36	@ 0x24
+ 8031cec:	af00      	add	r7, sp, #0
+ 8031cee:	6078      	str	r0, [r7, #4]
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ 8031cf0:	2300      	movs	r3, #0
+ 8031cf2:	77fb      	strb	r3, [r7, #31]
+  uint32_t tmpCFGR;
+  uint32_t tmp_adc_reg_is_conversion_on_going;
+  __IO uint32_t wait_loop_index = 0UL;
+ 8031cf4:	2300      	movs	r3, #0
+ 8031cf6:	60bb      	str	r3, [r7, #8]
+  uint32_t tmp_adc_is_conversion_on_going_regular;
+  uint32_t tmp_adc_is_conversion_on_going_injected;
+
+  /* Check ADC handle */
+  if (hadc == NULL)
+ 8031cf8:	687b      	ldr	r3, [r7, #4]
+ 8031cfa:	2b00      	cmp	r3, #0
+ 8031cfc:	d101      	bne.n	8031d02 <HAL_ADC_Init+0x1a>
+  {
+    return HAL_ERROR;
+ 8031cfe:	2301      	movs	r3, #1
+ 8031d00:	e18f      	b.n	8032022 <HAL_ADC_Init+0x33a>
+  assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
+  assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode));
+
+  if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
+ 8031d02:	687b      	ldr	r3, [r7, #4]
+ 8031d04:	68db      	ldr	r3, [r3, #12]
+ 8031d06:	2b00      	cmp	r3, #0
+  /* DISCEN and CONT bits cannot be set at the same time */
+  assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE)));
+
+  /* Actions performed only if ADC is coming from state reset:                */
+  /* - Initialization of ADC MSP                                              */
+  if (hadc->State == HAL_ADC_STATE_RESET)
+ 8031d08:	687b      	ldr	r3, [r7, #4]
+ 8031d0a:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
+ 8031d0c:	2b00      	cmp	r3, #0
+ 8031d0e:	d109      	bne.n	8031d24 <HAL_ADC_Init+0x3c>
+
+    /* Init the low level hardware */
+    hadc->MspInitCallback(hadc);
+#else
+    /* Init the low level hardware */
+    HAL_ADC_MspInit(hadc);
+ 8031d10:	6878      	ldr	r0, [r7, #4]
+ 8031d12:	f7f7 f85d 	bl	8028dd0 <HAL_ADC_MspInit>
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+    /* Set ADC error code to none */
+    ADC_CLEAR_ERRORCODE(hadc);
+ 8031d16:	687b      	ldr	r3, [r7, #4]
+ 8031d18:	2200      	movs	r2, #0
+ 8031d1a:	659a      	str	r2, [r3, #88]	@ 0x58
+
+    /* Initialize Lock */
+    hadc->Lock = HAL_UNLOCKED;
+ 8031d1c:	687b      	ldr	r3, [r7, #4]
+ 8031d1e:	2200      	movs	r2, #0
+ 8031d20:	f883 2050 	strb.w	r2, [r3, #80]	@ 0x50
+  }
+
+  /* - Exit from deep-power-down mode and ADC voltage regulator enable        */
+  if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL)
+ 8031d24:	687b      	ldr	r3, [r7, #4]
+ 8031d26:	681b      	ldr	r3, [r3, #0]
+ 8031d28:	4618      	mov	r0, r3
+ 8031d2a:	f7ff ff67 	bl	8031bfc <LL_ADC_IsDeepPowerDownEnabled>
+ 8031d2e:	4603      	mov	r3, r0
+ 8031d30:	2b00      	cmp	r3, #0
+ 8031d32:	d004      	beq.n	8031d3e <HAL_ADC_Init+0x56>
+  {
+    /* Disable ADC deep power down mode */
+    LL_ADC_DisableDeepPowerDown(hadc->Instance);
+ 8031d34:	687b      	ldr	r3, [r7, #4]
+ 8031d36:	681b      	ldr	r3, [r3, #0]
+ 8031d38:	4618      	mov	r0, r3
+ 8031d3a:	f7ff ff4d 	bl	8031bd8 <LL_ADC_DisableDeepPowerDown>
+    /* System was in deep power down mode, calibration must
+     be relaunched or a previously saved calibration factor
+     re-applied once the ADC voltage regulator is enabled */
+  }
+
+  if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
+ 8031d3e:	687b      	ldr	r3, [r7, #4]
+ 8031d40:	681b      	ldr	r3, [r3, #0]
+ 8031d42:	4618      	mov	r0, r3
+ 8031d44:	f7ff ff82 	bl	8031c4c <LL_ADC_IsInternalRegulatorEnabled>
+ 8031d48:	4603      	mov	r3, r0
+ 8031d4a:	2b00      	cmp	r3, #0
+ 8031d4c:	d114      	bne.n	8031d78 <HAL_ADC_Init+0x90>
+  {
+    /* Enable ADC internal voltage regulator */
+    LL_ADC_EnableInternalRegulator(hadc->Instance);
+ 8031d4e:	687b      	ldr	r3, [r7, #4]
+ 8031d50:	681b      	ldr	r3, [r3, #0]
+ 8031d52:	4618      	mov	r0, r3
+ 8031d54:	f7ff ff66 	bl	8031c24 <LL_ADC_EnableInternalRegulator>
+
+    /* Note: Variable divided by 2 to compensate partially              */
+    /*       CPU processing cycles, scaling in us split to not          */
+    /*       exceed 32 bits register capacity and handle low frequency. */
+    wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
+ 8031d58:	4b87      	ldr	r3, [pc, #540]	@ (8031f78 <HAL_ADC_Init+0x290>)
+ 8031d5a:	681b      	ldr	r3, [r3, #0]
+ 8031d5c:	099b      	lsrs	r3, r3, #6
+ 8031d5e:	4a87      	ldr	r2, [pc, #540]	@ (8031f7c <HAL_ADC_Init+0x294>)
+ 8031d60:	fba2 2303 	umull	r2, r3, r2, r3
+ 8031d64:	099b      	lsrs	r3, r3, #6
+ 8031d66:	3301      	adds	r3, #1
+ 8031d68:	60bb      	str	r3, [r7, #8]
+    while (wait_loop_index != 0UL)
+ 8031d6a:	e002      	b.n	8031d72 <HAL_ADC_Init+0x8a>
+    {
+      wait_loop_index--;
+ 8031d6c:	68bb      	ldr	r3, [r7, #8]
+ 8031d6e:	3b01      	subs	r3, #1
+ 8031d70:	60bb      	str	r3, [r7, #8]
+    while (wait_loop_index != 0UL)
+ 8031d72:	68bb      	ldr	r3, [r7, #8]
+ 8031d74:	2b00      	cmp	r3, #0
+ 8031d76:	d1f9      	bne.n	8031d6c <HAL_ADC_Init+0x84>
+  }
+
+  /* Verification that ADC voltage regulator is correctly enabled, whether    */
+  /* or not ADC is coming from state reset (if any potential problem of       */
+  /* clocking, voltage regulator would not be enabled).                       */
+  if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
+ 8031d78:	687b      	ldr	r3, [r7, #4]
+ 8031d7a:	681b      	ldr	r3, [r3, #0]
+ 8031d7c:	4618      	mov	r0, r3
+ 8031d7e:	f7ff ff65 	bl	8031c4c <LL_ADC_IsInternalRegulatorEnabled>
+ 8031d82:	4603      	mov	r3, r0
+ 8031d84:	2b00      	cmp	r3, #0
+ 8031d86:	d10d      	bne.n	8031da4 <HAL_ADC_Init+0xbc>
+  {
+    /* Update ADC state machine to error */
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+ 8031d88:	687b      	ldr	r3, [r7, #4]
+ 8031d8a:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
+ 8031d8c:	f043 0210 	orr.w	r2, r3, #16
+ 8031d90:	687b      	ldr	r3, [r7, #4]
+ 8031d92:	655a      	str	r2, [r3, #84]	@ 0x54
+
+    /* Set ADC error code to ADC peripheral internal error */
+    SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ 8031d94:	687b      	ldr	r3, [r7, #4]
+ 8031d96:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
+ 8031d98:	f043 0201 	orr.w	r2, r3, #1
+ 8031d9c:	687b      	ldr	r3, [r7, #4]
+ 8031d9e:	659a      	str	r2, [r3, #88]	@ 0x58
+
+    tmp_hal_status = HAL_ERROR;
+ 8031da0:	2301      	movs	r3, #1
+ 8031da2:	77fb      	strb	r3, [r7, #31]
+
+  /* Configuration of ADC parameters if previous preliminary actions are      */
+  /* correctly completed and if there is no conversion on going on regular    */
+  /* group (ADC may already be enabled at this point if HAL_ADC_Init() is     */
+  /* called to update a parameter on the fly).                                */
+  tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+ 8031da4:	687b      	ldr	r3, [r7, #4]
+ 8031da6:	681b      	ldr	r3, [r3, #0]
+ 8031da8:	4618      	mov	r0, r3
+ 8031daa:	f7ff ff76 	bl	8031c9a <LL_ADC_REG_IsConversionOngoing>
+ 8031dae:	6178      	str	r0, [r7, #20]
+
+  if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
+ 8031db0:	687b      	ldr	r3, [r7, #4]
+ 8031db2:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
+ 8031db4:	f003 0310 	and.w	r3, r3, #16
+ 8031db8:	2b00      	cmp	r3, #0
+ 8031dba:	f040 8129 	bne.w	8032010 <HAL_ADC_Init+0x328>
+      && (tmp_adc_reg_is_conversion_on_going == 0UL)
+ 8031dbe:	697b      	ldr	r3, [r7, #20]
+ 8031dc0:	2b00      	cmp	r3, #0
+ 8031dc2:	f040 8125 	bne.w	8032010 <HAL_ADC_Init+0x328>
+     )
+  {
+    /* Set ADC state */
+    ADC_STATE_CLR_SET(hadc->State,
+ 8031dc6:	687b      	ldr	r3, [r7, #4]
+ 8031dc8:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
+ 8031dca:	f423 7381 	bic.w	r3, r3, #258	@ 0x102
+ 8031dce:	f043 0202 	orr.w	r2, r3, #2
+ 8031dd2:	687b      	ldr	r3, [r7, #4]
+ 8031dd4:	655a      	str	r2, [r3, #84]	@ 0x54
+    /* Configuration of common ADC parameters                                 */
+
+    /* Parameters update conditioned to ADC state:                            */
+    /* Parameters that can be updated only when ADC is disabled:              */
+    /*  - clock configuration                                                 */
+    if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+ 8031dd6:	687b      	ldr	r3, [r7, #4]
+ 8031dd8:	681b      	ldr	r3, [r3, #0]
+ 8031dda:	4618      	mov	r0, r3
+ 8031ddc:	f7ff ff4a 	bl	8031c74 <LL_ADC_IsEnabled>
+ 8031de0:	4603      	mov	r3, r0
+ 8031de2:	2b00      	cmp	r3, #0
+ 8031de4:	d136      	bne.n	8031e54 <HAL_ADC_Init+0x16c>
+    {
+      if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
+ 8031de6:	687b      	ldr	r3, [r7, #4]
+ 8031de8:	681b      	ldr	r3, [r3, #0]
+ 8031dea:	4a65      	ldr	r2, [pc, #404]	@ (8031f80 <HAL_ADC_Init+0x298>)
+ 8031dec:	4293      	cmp	r3, r2
+ 8031dee:	d004      	beq.n	8031dfa <HAL_ADC_Init+0x112>
+ 8031df0:	687b      	ldr	r3, [r7, #4]
+ 8031df2:	681b      	ldr	r3, [r3, #0]
+ 8031df4:	4a63      	ldr	r2, [pc, #396]	@ (8031f84 <HAL_ADC_Init+0x29c>)
+ 8031df6:	4293      	cmp	r3, r2
+ 8031df8:	d10e      	bne.n	8031e18 <HAL_ADC_Init+0x130>
+ 8031dfa:	4861      	ldr	r0, [pc, #388]	@ (8031f80 <HAL_ADC_Init+0x298>)
+ 8031dfc:	f7ff ff3a 	bl	8031c74 <LL_ADC_IsEnabled>
+ 8031e00:	4604      	mov	r4, r0
+ 8031e02:	4860      	ldr	r0, [pc, #384]	@ (8031f84 <HAL_ADC_Init+0x29c>)
+ 8031e04:	f7ff ff36 	bl	8031c74 <LL_ADC_IsEnabled>
+ 8031e08:	4603      	mov	r3, r0
+ 8031e0a:	4323      	orrs	r3, r4
+ 8031e0c:	2b00      	cmp	r3, #0
+ 8031e0e:	bf0c      	ite	eq
+ 8031e10:	2301      	moveq	r3, #1
+ 8031e12:	2300      	movne	r3, #0
+ 8031e14:	b2db      	uxtb	r3, r3
+ 8031e16:	e008      	b.n	8031e2a <HAL_ADC_Init+0x142>
+ 8031e18:	485b      	ldr	r0, [pc, #364]	@ (8031f88 <HAL_ADC_Init+0x2a0>)
+ 8031e1a:	f7ff ff2b 	bl	8031c74 <LL_ADC_IsEnabled>
+ 8031e1e:	4603      	mov	r3, r0
+ 8031e20:	2b00      	cmp	r3, #0
+ 8031e22:	bf0c      	ite	eq
+ 8031e24:	2301      	moveq	r3, #1
+ 8031e26:	2300      	movne	r3, #0
+ 8031e28:	b2db      	uxtb	r3, r3
+ 8031e2a:	2b00      	cmp	r3, #0
+ 8031e2c:	d012      	beq.n	8031e54 <HAL_ADC_Init+0x16c>
+        /*     parameters: MDMA, DMACFG, DELAY, DUAL (set by API                */
+        /*     HAL_ADCEx_MultiModeConfigChannel() )                             */
+        /*   - internal measurement paths: Vbat, temperature sensor, Vref       */
+        /*     (set into HAL_ADC_ConfigChannel() or                             */
+        /*     HAL_ADCEx_InjectedConfigChannel() )                              */
+        LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler);
+ 8031e2e:	687b      	ldr	r3, [r7, #4]
+ 8031e30:	681b      	ldr	r3, [r3, #0]
+ 8031e32:	4a53      	ldr	r2, [pc, #332]	@ (8031f80 <HAL_ADC_Init+0x298>)
+ 8031e34:	4293      	cmp	r3, r2
+ 8031e36:	d004      	beq.n	8031e42 <HAL_ADC_Init+0x15a>
+ 8031e38:	687b      	ldr	r3, [r7, #4]
+ 8031e3a:	681b      	ldr	r3, [r3, #0]
+ 8031e3c:	4a51      	ldr	r2, [pc, #324]	@ (8031f84 <HAL_ADC_Init+0x29c>)
+ 8031e3e:	4293      	cmp	r3, r2
+ 8031e40:	d101      	bne.n	8031e46 <HAL_ADC_Init+0x15e>
+ 8031e42:	4a52      	ldr	r2, [pc, #328]	@ (8031f8c <HAL_ADC_Init+0x2a4>)
+ 8031e44:	e000      	b.n	8031e48 <HAL_ADC_Init+0x160>
+ 8031e46:	4a52      	ldr	r2, [pc, #328]	@ (8031f90 <HAL_ADC_Init+0x2a8>)
+ 8031e48:	687b      	ldr	r3, [r7, #4]
+ 8031e4a:	685b      	ldr	r3, [r3, #4]
+ 8031e4c:	4619      	mov	r1, r3
+ 8031e4e:	4610      	mov	r0, r2
+ 8031e50:	f7ff fdbe 	bl	80319d0 <LL_ADC_SetCommonClock>
+                  ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode));
+    }
+
+#else
+
+    if ((HAL_GetREVID() > REV_ID_Y) && (ADC_RESOLUTION_8B == hadc->Init.Resolution))
+ 8031e54:	f7ff fd9c 	bl	8031990 <HAL_GetREVID>
+ 8031e58:	4603      	mov	r3, r0
+ 8031e5a:	f241 0203 	movw	r2, #4099	@ 0x1003
+ 8031e5e:	4293      	cmp	r3, r2
+ 8031e60:	d914      	bls.n	8031e8c <HAL_ADC_Init+0x1a4>
+ 8031e62:	687b      	ldr	r3, [r7, #4]
+ 8031e64:	689b      	ldr	r3, [r3, #8]
+ 8031e66:	2b10      	cmp	r3, #16
+ 8031e68:	d110      	bne.n	8031e8c <HAL_ADC_Init+0x1a4>
+    {
+      /* for STM32H7 silicon rev.B and above , ADC_CFGR_RES value for 8bits resolution is : b111 */
+      tmpCFGR  = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode)          |
+ 8031e6a:	687b      	ldr	r3, [r7, #4]
+ 8031e6c:	7d5b      	ldrb	r3, [r3, #21]
+ 8031e6e:	035a      	lsls	r2, r3, #13
+                  hadc->Init.Overrun                                                    |
+ 8031e70:	687b      	ldr	r3, [r7, #4]
+ 8031e72:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
+      tmpCFGR  = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode)          |
+ 8031e74:	431a      	orrs	r2, r3
+                  hadc->Init.Resolution | (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)                |
+ 8031e76:	687b      	ldr	r3, [r7, #4]
+ 8031e78:	689b      	ldr	r3, [r3, #8]
+                  hadc->Init.Overrun                                                    |
+ 8031e7a:	431a      	orrs	r2, r3
+                  ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode));
+ 8031e7c:	687b      	ldr	r3, [r7, #4]
+ 8031e7e:	7f1b      	ldrb	r3, [r3, #28]
+ 8031e80:	041b      	lsls	r3, r3, #16
+                  hadc->Init.Resolution | (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)                |
+ 8031e82:	4313      	orrs	r3, r2
+      tmpCFGR  = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode)          |
+ 8031e84:	f043 030c 	orr.w	r3, r3, #12
+ 8031e88:	61bb      	str	r3, [r7, #24]
+ 8031e8a:	e00d      	b.n	8031ea8 <HAL_ADC_Init+0x1c0>
+    }
+    else
+    {
+
+      tmpCFGR  = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode)          |
+ 8031e8c:	687b      	ldr	r3, [r7, #4]
+ 8031e8e:	7d5b      	ldrb	r3, [r3, #21]
+ 8031e90:	035a      	lsls	r2, r3, #13
+                  hadc->Init.Overrun                                                    |
+ 8031e92:	687b      	ldr	r3, [r7, #4]
+ 8031e94:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
+      tmpCFGR  = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode)          |
+ 8031e96:	431a      	orrs	r2, r3
+                  hadc->Init.Resolution                                                 |
+ 8031e98:	687b      	ldr	r3, [r7, #4]
+ 8031e9a:	689b      	ldr	r3, [r3, #8]
+                  hadc->Init.Overrun                                                    |
+ 8031e9c:	431a      	orrs	r2, r3
+                  ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode));
+ 8031e9e:	687b      	ldr	r3, [r7, #4]
+ 8031ea0:	7f1b      	ldrb	r3, [r3, #28]
+ 8031ea2:	041b      	lsls	r3, r3, #16
+      tmpCFGR  = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode)          |
+ 8031ea4:	4313      	orrs	r3, r2
+ 8031ea6:	61bb      	str	r3, [r7, #24]
+    }
+
+#endif /* ADC_VER_V5_3 */
+
+    if (hadc->Init.DiscontinuousConvMode == ENABLE)
+ 8031ea8:	687b      	ldr	r3, [r7, #4]
+ 8031eaa:	7f1b      	ldrb	r3, [r3, #28]
+ 8031eac:	2b01      	cmp	r3, #1
+ 8031eae:	d106      	bne.n	8031ebe <HAL_ADC_Init+0x1d6>
+    {
+      tmpCFGR |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion);
+ 8031eb0:	687b      	ldr	r3, [r7, #4]
+ 8031eb2:	6a1b      	ldr	r3, [r3, #32]
+ 8031eb4:	3b01      	subs	r3, #1
+ 8031eb6:	045b      	lsls	r3, r3, #17
+ 8031eb8:	69ba      	ldr	r2, [r7, #24]
+ 8031eba:	4313      	orrs	r3, r2
+ 8031ebc:	61bb      	str	r3, [r7, #24]
+    /* Enable external trigger if trigger selection is different of software  */
+    /* start.                                                                 */
+    /* Note: This configuration keeps the hardware feature of parameter       */
+    /*       ExternalTrigConvEdge "trigger edge none" equivalent to           */
+    /*       software start.                                                  */
+    if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
+ 8031ebe:	687b      	ldr	r3, [r7, #4]
+ 8031ec0:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 8031ec2:	2b00      	cmp	r3, #0
+ 8031ec4:	d009      	beq.n	8031eda <HAL_ADC_Init+0x1f2>
+    {
+      tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL)
+ 8031ec6:	687b      	ldr	r3, [r7, #4]
+ 8031ec8:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 8031eca:	f403 7278 	and.w	r2, r3, #992	@ 0x3e0
+                  | hadc->Init.ExternalTrigConvEdge
+ 8031ece:	687b      	ldr	r3, [r7, #4]
+ 8031ed0:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 8031ed2:	4313      	orrs	r3, r2
+      tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL)
+ 8031ed4:	69ba      	ldr	r2, [r7, #24]
+ 8031ed6:	4313      	orrs	r3, r2
+ 8031ed8:	61bb      	str	r3, [r7, #24]
+      /* Update Configuration Register CFGR */
+      MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR);
+    }
+#else
+    /* Update Configuration Register CFGR */
+    MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR);
+ 8031eda:	687b      	ldr	r3, [r7, #4]
+ 8031edc:	681b      	ldr	r3, [r3, #0]
+ 8031ede:	68da      	ldr	r2, [r3, #12]
+ 8031ee0:	4b2c      	ldr	r3, [pc, #176]	@ (8031f94 <HAL_ADC_Init+0x2ac>)
+ 8031ee2:	4013      	ands	r3, r2
+ 8031ee4:	687a      	ldr	r2, [r7, #4]
+ 8031ee6:	6812      	ldr	r2, [r2, #0]
+ 8031ee8:	69b9      	ldr	r1, [r7, #24]
+ 8031eea:	430b      	orrs	r3, r1
+ 8031eec:	60d3      	str	r3, [r2, #12]
+    /* Parameters that can be updated when ADC is disabled or enabled without */
+    /* conversion on going on regular and injected groups:                    */
+    /*  - Conversion data management      Init.ConversionDataManagement       */
+    /*  - LowPowerAutoWait feature        Init.LowPowerAutoWait               */
+    /*  - Oversampling parameters         Init.Oversampling                   */
+    tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+ 8031eee:	687b      	ldr	r3, [r7, #4]
+ 8031ef0:	681b      	ldr	r3, [r3, #0]
+ 8031ef2:	4618      	mov	r0, r3
+ 8031ef4:	f7ff fed1 	bl	8031c9a <LL_ADC_REG_IsConversionOngoing>
+ 8031ef8:	6138      	str	r0, [r7, #16]
+    tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+ 8031efa:	687b      	ldr	r3, [r7, #4]
+ 8031efc:	681b      	ldr	r3, [r3, #0]
+ 8031efe:	4618      	mov	r0, r3
+ 8031f00:	f7ff fede 	bl	8031cc0 <LL_ADC_INJ_IsConversionOngoing>
+ 8031f04:	60f8      	str	r0, [r7, #12]
+    if ((tmp_adc_is_conversion_on_going_regular == 0UL)
+ 8031f06:	693b      	ldr	r3, [r7, #16]
+ 8031f08:	2b00      	cmp	r3, #0
+ 8031f0a:	d15f      	bne.n	8031fcc <HAL_ADC_Init+0x2e4>
+        && (tmp_adc_is_conversion_on_going_injected == 0UL)
+ 8031f0c:	68fb      	ldr	r3, [r7, #12]
+ 8031f0e:	2b00      	cmp	r3, #0
+ 8031f10:	d15c      	bne.n	8031fcc <HAL_ADC_Init+0x2e4>
+                    ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait)        |
+                    ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.ConversionDataManagement));
+      }
+#else
+      tmpCFGR = (
+                  ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait)        |
+ 8031f12:	687b      	ldr	r3, [r7, #4]
+ 8031f14:	7d1b      	ldrb	r3, [r3, #20]
+ 8031f16:	039a      	lsls	r2, r3, #14
+                  ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.ConversionDataManagement));
+ 8031f18:	687b      	ldr	r3, [r7, #4]
+ 8031f1a:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+      tmpCFGR = (
+ 8031f1c:	4313      	orrs	r3, r2
+ 8031f1e:	61bb      	str	r3, [r7, #24]
+#endif
+
+      MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR);
+ 8031f20:	687b      	ldr	r3, [r7, #4]
+ 8031f22:	681b      	ldr	r3, [r3, #0]
+ 8031f24:	68da      	ldr	r2, [r3, #12]
+ 8031f26:	4b1c      	ldr	r3, [pc, #112]	@ (8031f98 <HAL_ADC_Init+0x2b0>)
+ 8031f28:	4013      	ands	r3, r2
+ 8031f2a:	687a      	ldr	r2, [r7, #4]
+ 8031f2c:	6812      	ldr	r2, [r2, #0]
+ 8031f2e:	69b9      	ldr	r1, [r7, #24]
+ 8031f30:	430b      	orrs	r3, r1
+ 8031f32:	60d3      	str	r3, [r2, #12]
+
+      if (hadc->Init.OversamplingMode == ENABLE)
+ 8031f34:	687b      	ldr	r3, [r7, #4]
+ 8031f36:	f893 3038 	ldrb.w	r3, [r3, #56]	@ 0x38
+ 8031f3a:	2b01      	cmp	r3, #1
+ 8031f3c:	d130      	bne.n	8031fa0 <HAL_ADC_Init+0x2b8>
+#endif
+        assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift));
+        assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode));
+        assert_param(IS_ADC_REGOVERSAMPLING_MODE(hadc->Init.Oversampling.OversamplingStopReset));
+
+        if ((hadc->Init.ExternalTrigConv == ADC_SOFTWARE_START)
+ 8031f3e:	687b      	ldr	r3, [r7, #4]
+ 8031f40:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 8031f42:	2b00      	cmp	r3, #0
+        /*  - Oversampling Ratio                                               */
+        /*  - Right bit shift                                                  */
+        /*  - Left bit shift                                                   */
+        /*  - Triggered mode                                                   */
+        /*  - Oversampling mode (continued/resumed)                            */
+        MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_FIELDS,
+ 8031f44:	687b      	ldr	r3, [r7, #4]
+ 8031f46:	681b      	ldr	r3, [r3, #0]
+ 8031f48:	691a      	ldr	r2, [r3, #16]
+ 8031f4a:	4b14      	ldr	r3, [pc, #80]	@ (8031f9c <HAL_ADC_Init+0x2b4>)
+ 8031f4c:	4013      	ands	r3, r2
+ 8031f4e:	687a      	ldr	r2, [r7, #4]
+ 8031f50:	6bd2      	ldr	r2, [r2, #60]	@ 0x3c
+ 8031f52:	3a01      	subs	r2, #1
+ 8031f54:	0411      	lsls	r1, r2, #16
+ 8031f56:	687a      	ldr	r2, [r7, #4]
+ 8031f58:	6c12      	ldr	r2, [r2, #64]	@ 0x40
+ 8031f5a:	4311      	orrs	r1, r2
+ 8031f5c:	687a      	ldr	r2, [r7, #4]
+ 8031f5e:	6c52      	ldr	r2, [r2, #68]	@ 0x44
+ 8031f60:	4311      	orrs	r1, r2
+ 8031f62:	687a      	ldr	r2, [r7, #4]
+ 8031f64:	6c92      	ldr	r2, [r2, #72]	@ 0x48
+ 8031f66:	430a      	orrs	r2, r1
+ 8031f68:	431a      	orrs	r2, r3
+ 8031f6a:	687b      	ldr	r3, [r7, #4]
+ 8031f6c:	681b      	ldr	r3, [r3, #0]
+ 8031f6e:	f042 0201 	orr.w	r2, r2, #1
+ 8031f72:	611a      	str	r2, [r3, #16]
+ 8031f74:	e01c      	b.n	8031fb0 <HAL_ADC_Init+0x2c8>
+ 8031f76:	bf00      	nop
+ 8031f78:	2400012c 	.word	0x2400012c
+ 8031f7c:	053e2d63 	.word	0x053e2d63
+ 8031f80:	40022000 	.word	0x40022000
+ 8031f84:	40022100 	.word	0x40022100
+ 8031f88:	58026000 	.word	0x58026000
+ 8031f8c:	40022300 	.word	0x40022300
+ 8031f90:	58026300 	.word	0x58026300
+ 8031f94:	fff0c003 	.word	0xfff0c003
+ 8031f98:	ffffbffc 	.word	0xffffbffc
+ 8031f9c:	fc00f81e 	.word	0xfc00f81e
+
+      }
+      else
+      {
+        /* Disable ADC oversampling scope on ADC group regular */
+        CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE);
+ 8031fa0:	687b      	ldr	r3, [r7, #4]
+ 8031fa2:	681b      	ldr	r3, [r3, #0]
+ 8031fa4:	691a      	ldr	r2, [r3, #16]
+ 8031fa6:	687b      	ldr	r3, [r7, #4]
+ 8031fa8:	681b      	ldr	r3, [r3, #0]
+ 8031faa:	f022 0201 	bic.w	r2, r2, #1
+ 8031fae:	611a      	str	r2, [r3, #16]
+      }
+
+      /* Set the LeftShift parameter: it is applied to the final result with or without oversampling */
+      MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_LSHIFT, hadc->Init.LeftBitShift);
+ 8031fb0:	687b      	ldr	r3, [r7, #4]
+ 8031fb2:	681b      	ldr	r3, [r3, #0]
+ 8031fb4:	691b      	ldr	r3, [r3, #16]
+ 8031fb6:	f023 4170 	bic.w	r1, r3, #4026531840	@ 0xf0000000
+ 8031fba:	687b      	ldr	r3, [r7, #4]
+ 8031fbc:	6b5a      	ldr	r2, [r3, #52]	@ 0x34
+ 8031fbe:	687b      	ldr	r3, [r7, #4]
+ 8031fc0:	681b      	ldr	r3, [r3, #0]
+ 8031fc2:	430a      	orrs	r2, r1
+ 8031fc4:	611a      	str	r2, [r3, #16]
+        /* Configure the BOOST Mode */
+        ADC_ConfigureBoostMode(hadc);
+      }
+#else
+      /* Configure the BOOST Mode */
+      ADC_ConfigureBoostMode(hadc);
+ 8031fc6:	6878      	ldr	r0, [r7, #4]
+ 8031fc8:	f000 fb8c 	bl	80326e4 <ADC_ConfigureBoostMode>
+    /*   Note: Scan mode is not present by hardware on this device, but       */
+    /*   emulated by software for alignment over all STM32 devices.           */
+    /* - if scan mode is enabled, regular channels sequence length is set to  */
+    /*   parameter "NbrOfConversion".                                         */
+
+    if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
+ 8031fcc:	687b      	ldr	r3, [r7, #4]
+ 8031fce:	68db      	ldr	r3, [r3, #12]
+ 8031fd0:	2b01      	cmp	r3, #1
+ 8031fd2:	d10c      	bne.n	8031fee <HAL_ADC_Init+0x306>
+    {
+      /* Set number of ranks in regular group sequencer */
+      MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1));
+ 8031fd4:	687b      	ldr	r3, [r7, #4]
+ 8031fd6:	681b      	ldr	r3, [r3, #0]
+ 8031fd8:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
+ 8031fda:	f023 010f 	bic.w	r1, r3, #15
+ 8031fde:	687b      	ldr	r3, [r7, #4]
+ 8031fe0:	699b      	ldr	r3, [r3, #24]
+ 8031fe2:	1e5a      	subs	r2, r3, #1
+ 8031fe4:	687b      	ldr	r3, [r7, #4]
+ 8031fe6:	681b      	ldr	r3, [r3, #0]
+ 8031fe8:	430a      	orrs	r2, r1
+ 8031fea:	631a      	str	r2, [r3, #48]	@ 0x30
+ 8031fec:	e007      	b.n	8031ffe <HAL_ADC_Init+0x316>
+    }
+    else
+    {
+      CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L);
+ 8031fee:	687b      	ldr	r3, [r7, #4]
+ 8031ff0:	681b      	ldr	r3, [r3, #0]
+ 8031ff2:	6b1a      	ldr	r2, [r3, #48]	@ 0x30
+ 8031ff4:	687b      	ldr	r3, [r7, #4]
+ 8031ff6:	681b      	ldr	r3, [r3, #0]
+ 8031ff8:	f022 020f 	bic.w	r2, r2, #15
+ 8031ffc:	631a      	str	r2, [r3, #48]	@ 0x30
+    }
+
+    /* Initialize the ADC state */
+    /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */
+    ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
+ 8031ffe:	687b      	ldr	r3, [r7, #4]
+ 8032000:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
+ 8032002:	f023 0303 	bic.w	r3, r3, #3
+ 8032006:	f043 0201 	orr.w	r2, r3, #1
+ 803200a:	687b      	ldr	r3, [r7, #4]
+ 803200c:	655a      	str	r2, [r3, #84]	@ 0x54
+ 803200e:	e007      	b.n	8032020 <HAL_ADC_Init+0x338>
+  }
+  else
+  {
+    /* Update ADC state machine to error */
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+ 8032010:	687b      	ldr	r3, [r7, #4]
+ 8032012:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
+ 8032014:	f043 0210 	orr.w	r2, r3, #16
+ 8032018:	687b      	ldr	r3, [r7, #4]
+ 803201a:	655a      	str	r2, [r3, #84]	@ 0x54
+
+    tmp_hal_status = HAL_ERROR;
+ 803201c:	2301      	movs	r3, #1
+ 803201e:	77fb      	strb	r3, [r7, #31]
+  }
+
+  /* Return function status */
+  return tmp_hal_status;
+ 8032020:	7ffb      	ldrb	r3, [r7, #31]
+}
+ 8032022:	4618      	mov	r0, r3
+ 8032024:	3724      	adds	r7, #36	@ 0x24
+ 8032026:	46bd      	mov	sp, r7
+ 8032028:	bd90      	pop	{r4, r7, pc}
+ 803202a:	bf00      	nop
+
+0803202c <HAL_ADC_ConfigChannel>:
+  * @param hadc ADC handle
+  * @param sConfig Structure of ADC channel assigned to ADC group regular.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig)
+{
+ 803202c:	b590      	push	{r4, r7, lr}
+ 803202e:	b0a1      	sub	sp, #132	@ 0x84
+ 8032030:	af00      	add	r7, sp, #0
+ 8032032:	6078      	str	r0, [r7, #4]
+ 8032034:	6039      	str	r1, [r7, #0]
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ 8032036:	2300      	movs	r3, #0
+ 8032038:	f887 307f 	strb.w	r3, [r7, #127]	@ 0x7f
+  uint32_t tmpOffsetShifted;
+  uint32_t tmp_config_internal_channel;
+  __IO uint32_t wait_loop_index = 0;
+ 803203c:	2300      	movs	r3, #0
+ 803203e:	60bb      	str	r3, [r7, #8]
+  /* if ROVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is
+     ignored (considered as reset) */
+  assert_param(!((sConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENABLE)));
+
+  /* Verification of channel number */
+  if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
+ 8032040:	683b      	ldr	r3, [r7, #0]
+ 8032042:	68db      	ldr	r3, [r3, #12]
+ 8032044:	4a65      	ldr	r2, [pc, #404]	@ (80321dc <HAL_ADC_ConfigChannel+0x1b0>)
+ 8032046:	4293      	cmp	r3, r2
+    }
+#endif
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+ 8032048:	687b      	ldr	r3, [r7, #4]
+ 803204a:	f893 3050 	ldrb.w	r3, [r3, #80]	@ 0x50
+ 803204e:	2b01      	cmp	r3, #1
+ 8032050:	d101      	bne.n	8032056 <HAL_ADC_ConfigChannel+0x2a>
+ 8032052:	2302      	movs	r3, #2
+ 8032054:	e32e      	b.n	80326b4 <HAL_ADC_ConfigChannel+0x688>
+ 8032056:	687b      	ldr	r3, [r7, #4]
+ 8032058:	2201      	movs	r2, #1
+ 803205a:	f883 2050 	strb.w	r2, [r3, #80]	@ 0x50
+  /* Parameters update conditioned to ADC state:                              */
+  /* Parameters that can be updated when ADC is disabled or enabled without   */
+  /* conversion on going on regular group:                                    */
+  /*  - Channel number                                                        */
+  /*  - Channel rank                                                          */
+  if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+ 803205e:	687b      	ldr	r3, [r7, #4]
+ 8032060:	681b      	ldr	r3, [r3, #0]
+ 8032062:	4618      	mov	r0, r3
+ 8032064:	f7ff fe19 	bl	8031c9a <LL_ADC_REG_IsConversionOngoing>
+ 8032068:	4603      	mov	r3, r0
+ 803206a:	2b00      	cmp	r3, #0
+ 803206c:	f040 8313 	bne.w	8032696 <HAL_ADC_ConfigChannel+0x66a>
+  {
+    if (!(__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)))
+ 8032070:	683b      	ldr	r3, [r7, #0]
+ 8032072:	681b      	ldr	r3, [r3, #0]
+ 8032074:	2b00      	cmp	r3, #0
+ 8032076:	db2c      	blt.n	80320d2 <HAL_ADC_ConfigChannel+0xa6>
+        /* ADC channels preselection */
+        hadc->Instance->PCSEL_RES0 |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) & 0x1FUL));
+      }
+#else
+      /* ADC channels preselection */
+      hadc->Instance->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) & 0x1FUL));
+ 8032078:	683b      	ldr	r3, [r7, #0]
+ 803207a:	681b      	ldr	r3, [r3, #0]
+ 803207c:	f3c3 0313 	ubfx	r3, r3, #0, #20
+ 8032080:	2b00      	cmp	r3, #0
+ 8032082:	d108      	bne.n	8032096 <HAL_ADC_ConfigChannel+0x6a>
+ 8032084:	683b      	ldr	r3, [r7, #0]
+ 8032086:	681b      	ldr	r3, [r3, #0]
+ 8032088:	0e9b      	lsrs	r3, r3, #26
+ 803208a:	f003 031f 	and.w	r3, r3, #31
+ 803208e:	2201      	movs	r2, #1
+ 8032090:	fa02 f303 	lsl.w	r3, r2, r3
+ 8032094:	e016      	b.n	80320c4 <HAL_ADC_ConfigChannel+0x98>
+ 8032096:	683b      	ldr	r3, [r7, #0]
+ 8032098:	681b      	ldr	r3, [r3, #0]
+ 803209a:	667b      	str	r3, [r7, #100]	@ 0x64
+  uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+ 803209c:	6e7b      	ldr	r3, [r7, #100]	@ 0x64
+ 803209e:	fa93 f3a3 	rbit	r3, r3
+ 80320a2:	663b      	str	r3, [r7, #96]	@ 0x60
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+#endif
+  return result;
+ 80320a4:	6e3b      	ldr	r3, [r7, #96]	@ 0x60
+ 80320a6:	66bb      	str	r3, [r7, #104]	@ 0x68
+     optimisations using the logic "value was passed to __builtin_clz, so it
+     is non-zero".
+     ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
+     single CLZ instruction.
+   */
+  if (value == 0U)
+ 80320a8:	6ebb      	ldr	r3, [r7, #104]	@ 0x68
+ 80320aa:	2b00      	cmp	r3, #0
+ 80320ac:	d101      	bne.n	80320b2 <HAL_ADC_ConfigChannel+0x86>
+  {
+    return 32U;
+ 80320ae:	2320      	movs	r3, #32
+ 80320b0:	e003      	b.n	80320ba <HAL_ADC_ConfigChannel+0x8e>
+  }
+  return __builtin_clz(value);
+ 80320b2:	6ebb      	ldr	r3, [r7, #104]	@ 0x68
+ 80320b4:	fab3 f383 	clz	r3, r3
+ 80320b8:	b2db      	uxtb	r3, r3
+ 80320ba:	f003 031f 	and.w	r3, r3, #31
+ 80320be:	2201      	movs	r2, #1
+ 80320c0:	fa02 f303 	lsl.w	r3, r2, r3
+ 80320c4:	687a      	ldr	r2, [r7, #4]
+ 80320c6:	6812      	ldr	r2, [r2, #0]
+ 80320c8:	69d1      	ldr	r1, [r2, #28]
+ 80320ca:	687a      	ldr	r2, [r7, #4]
+ 80320cc:	6812      	ldr	r2, [r2, #0]
+ 80320ce:	430b      	orrs	r3, r1
+ 80320d0:	61d3      	str	r3, [r2, #28]
+#endif /* ADC_VER_V5_V90 */
+    }
+
+    /* Set ADC group regular sequence: channel on the selected scan sequence rank */
+    LL_ADC_REG_SetSequencerRanks(hadc->Instance, sConfig->Rank, sConfig->Channel);
+ 80320d2:	687b      	ldr	r3, [r7, #4]
+ 80320d4:	6818      	ldr	r0, [r3, #0]
+ 80320d6:	683b      	ldr	r3, [r7, #0]
+ 80320d8:	6859      	ldr	r1, [r3, #4]
+ 80320da:	683b      	ldr	r3, [r7, #0]
+ 80320dc:	681b      	ldr	r3, [r3, #0]
+ 80320de:	461a      	mov	r2, r3
+ 80320e0:	f7ff fcfe 	bl	8031ae0 <LL_ADC_REG_SetSequencerRanks>
+    /* Parameters update conditioned to ADC state:                              */
+    /* Parameters that can be updated when ADC is disabled or enabled without   */
+    /* conversion on going on regular group:                                    */
+    /*  - Channel sampling time                                                 */
+    /*  - Channel offset                                                        */
+    tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+ 80320e4:	687b      	ldr	r3, [r7, #4]
+ 80320e6:	681b      	ldr	r3, [r3, #0]
+ 80320e8:	4618      	mov	r0, r3
+ 80320ea:	f7ff fdd6 	bl	8031c9a <LL_ADC_REG_IsConversionOngoing>
+ 80320ee:	67b8      	str	r0, [r7, #120]	@ 0x78
+    tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+ 80320f0:	687b      	ldr	r3, [r7, #4]
+ 80320f2:	681b      	ldr	r3, [r3, #0]
+ 80320f4:	4618      	mov	r0, r3
+ 80320f6:	f7ff fde3 	bl	8031cc0 <LL_ADC_INJ_IsConversionOngoing>
+ 80320fa:	6778      	str	r0, [r7, #116]	@ 0x74
+    if ((tmp_adc_is_conversion_on_going_regular == 0UL)
+ 80320fc:	6fbb      	ldr	r3, [r7, #120]	@ 0x78
+ 80320fe:	2b00      	cmp	r3, #0
+ 8032100:	f040 80b8 	bne.w	8032274 <HAL_ADC_ConfigChannel+0x248>
+        && (tmp_adc_is_conversion_on_going_injected == 0UL)
+ 8032104:	6f7b      	ldr	r3, [r7, #116]	@ 0x74
+ 8032106:	2b00      	cmp	r3, #0
+ 8032108:	f040 80b4 	bne.w	8032274 <HAL_ADC_ConfigChannel+0x248>
+       )
+    {
+      /* Set sampling time of the selected ADC channel */
+      LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime);
+ 803210c:	687b      	ldr	r3, [r7, #4]
+ 803210e:	6818      	ldr	r0, [r3, #0]
+ 8032110:	683b      	ldr	r3, [r7, #0]
+ 8032112:	6819      	ldr	r1, [r3, #0]
+ 8032114:	683b      	ldr	r3, [r7, #0]
+ 8032116:	689b      	ldr	r3, [r3, #8]
+ 8032118:	461a      	mov	r2, r3
+ 803211a:	f7ff fd0d 	bl	8031b38 <LL_ADC_SetChannelSamplingTime>
+        tmpOffsetShifted = ADC3_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset);
+      }
+      else
+#endif /* ADC_VER_V5_V90 */
+      {
+        tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset);
+ 803211e:	4b30      	ldr	r3, [pc, #192]	@ (80321e0 <HAL_ADC_ConfigChannel+0x1b4>)
+ 8032120:	681b      	ldr	r3, [r3, #0]
+ 8032122:	f003 4370 	and.w	r3, r3, #4026531840	@ 0xf0000000
+ 8032126:	f1b3 5f80 	cmp.w	r3, #268435456	@ 0x10000000
+ 803212a:	d10b      	bne.n	8032144 <HAL_ADC_ConfigChannel+0x118>
+ 803212c:	683b      	ldr	r3, [r7, #0]
+ 803212e:	695a      	ldr	r2, [r3, #20]
+ 8032130:	687b      	ldr	r3, [r7, #4]
+ 8032132:	681b      	ldr	r3, [r3, #0]
+ 8032134:	68db      	ldr	r3, [r3, #12]
+ 8032136:	089b      	lsrs	r3, r3, #2
+ 8032138:	f003 0307 	and.w	r3, r3, #7
+ 803213c:	005b      	lsls	r3, r3, #1
+ 803213e:	fa02 f303 	lsl.w	r3, r2, r3
+ 8032142:	e01d      	b.n	8032180 <HAL_ADC_ConfigChannel+0x154>
+ 8032144:	687b      	ldr	r3, [r7, #4]
+ 8032146:	681b      	ldr	r3, [r3, #0]
+ 8032148:	68db      	ldr	r3, [r3, #12]
+ 803214a:	f003 0310 	and.w	r3, r3, #16
+ 803214e:	2b00      	cmp	r3, #0
+ 8032150:	d10b      	bne.n	803216a <HAL_ADC_ConfigChannel+0x13e>
+ 8032152:	683b      	ldr	r3, [r7, #0]
+ 8032154:	695a      	ldr	r2, [r3, #20]
+ 8032156:	687b      	ldr	r3, [r7, #4]
+ 8032158:	681b      	ldr	r3, [r3, #0]
+ 803215a:	68db      	ldr	r3, [r3, #12]
+ 803215c:	089b      	lsrs	r3, r3, #2
+ 803215e:	f003 0307 	and.w	r3, r3, #7
+ 8032162:	005b      	lsls	r3, r3, #1
+ 8032164:	fa02 f303 	lsl.w	r3, r2, r3
+ 8032168:	e00a      	b.n	8032180 <HAL_ADC_ConfigChannel+0x154>
+ 803216a:	683b      	ldr	r3, [r7, #0]
+ 803216c:	695a      	ldr	r2, [r3, #20]
+ 803216e:	687b      	ldr	r3, [r7, #4]
+ 8032170:	681b      	ldr	r3, [r3, #0]
+ 8032172:	68db      	ldr	r3, [r3, #12]
+ 8032174:	089b      	lsrs	r3, r3, #2
+ 8032176:	f003 0304 	and.w	r3, r3, #4
+ 803217a:	005b      	lsls	r3, r3, #1
+ 803217c:	fa02 f303 	lsl.w	r3, r2, r3
+ 8032180:	673b      	str	r3, [r7, #112]	@ 0x70
+      }
+      
+      if (sConfig->OffsetNumber != ADC_OFFSET_NONE)
+ 8032182:	683b      	ldr	r3, [r7, #0]
+ 8032184:	691b      	ldr	r3, [r3, #16]
+ 8032186:	2b04      	cmp	r3, #4
+ 8032188:	d02c      	beq.n	80321e4 <HAL_ADC_ConfigChannel+0x1b8>
+      {
+        /* Set ADC selected offset number */
+        LL_ADC_SetOffset(hadc->Instance, sConfig->OffsetNumber, sConfig->Channel, tmpOffsetShifted);
+ 803218a:	687b      	ldr	r3, [r7, #4]
+ 803218c:	6818      	ldr	r0, [r3, #0]
+ 803218e:	683b      	ldr	r3, [r7, #0]
+ 8032190:	6919      	ldr	r1, [r3, #16]
+ 8032192:	683b      	ldr	r3, [r7, #0]
+ 8032194:	681a      	ldr	r2, [r3, #0]
+ 8032196:	6f3b      	ldr	r3, [r7, #112]	@ 0x70
+ 8032198:	f7ff fc4e 	bl	8031a38 <LL_ADC_SetOffset>
+        else
+#endif /* ADC_VER_V5_V90 */
+        {
+          assert_param(IS_FUNCTIONAL_STATE(sConfig->OffsetSignedSaturation));
+          /* Set ADC selected offset signed saturation */
+          LL_ADC_SetOffsetSignedSaturation(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetSignedSaturation == ENABLE) ? LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE : LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
+ 803219c:	687b      	ldr	r3, [r7, #4]
+ 803219e:	6818      	ldr	r0, [r3, #0]
+ 80321a0:	683b      	ldr	r3, [r7, #0]
+ 80321a2:	6919      	ldr	r1, [r3, #16]
+ 80321a4:	683b      	ldr	r3, [r7, #0]
+ 80321a6:	7e5b      	ldrb	r3, [r3, #25]
+ 80321a8:	2b01      	cmp	r3, #1
+ 80321aa:	d102      	bne.n	80321b2 <HAL_ADC_ConfigChannel+0x186>
+ 80321ac:	f04f 4300 	mov.w	r3, #2147483648	@ 0x80000000
+ 80321b0:	e000      	b.n	80321b4 <HAL_ADC_ConfigChannel+0x188>
+ 80321b2:	2300      	movs	r3, #0
+ 80321b4:	461a      	mov	r2, r3
+ 80321b6:	f7ff fc78 	bl	8031aaa <LL_ADC_SetOffsetSignedSaturation>
+
+          assert_param(IS_FUNCTIONAL_STATE(sConfig->OffsetRightShift));
+          /* Set ADC selected offset right shift */
+          LL_ADC_SetDataRightShift(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetRightShift == ENABLE) ? LL_ADC_OFFSET_RSHIFT_ENABLE : LL_ADC_OFFSET_RSHIFT_DISABLE);
+ 80321ba:	687b      	ldr	r3, [r7, #4]
+ 80321bc:	6818      	ldr	r0, [r3, #0]
+ 80321be:	683b      	ldr	r3, [r7, #0]
+ 80321c0:	6919      	ldr	r1, [r3, #16]
+ 80321c2:	683b      	ldr	r3, [r7, #0]
+ 80321c4:	7e1b      	ldrb	r3, [r3, #24]
+ 80321c6:	2b01      	cmp	r3, #1
+ 80321c8:	d102      	bne.n	80321d0 <HAL_ADC_ConfigChannel+0x1a4>
+ 80321ca:	f44f 6300 	mov.w	r3, #2048	@ 0x800
+ 80321ce:	e000      	b.n	80321d2 <HAL_ADC_ConfigChannel+0x1a6>
+ 80321d0:	2300      	movs	r3, #0
+ 80321d2:	461a      	mov	r2, r3
+ 80321d4:	f7ff fc50 	bl	8031a78 <LL_ADC_SetDataRightShift>
+ 80321d8:	e04c      	b.n	8032274 <HAL_ADC_ConfigChannel+0x248>
+ 80321da:	bf00      	nop
+ 80321dc:	47ff0000 	.word	0x47ff0000
+ 80321e0:	5c001000 	.word	0x5c001000
+          }
+        }
+        else
+#endif /* ADC_VER_V5_V90 */
+        {
+          if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
+ 80321e4:	687b      	ldr	r3, [r7, #4]
+ 80321e6:	681b      	ldr	r3, [r3, #0]
+ 80321e8:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
+ 80321ea:	f003 42f8 	and.w	r2, r3, #2080374784	@ 0x7c000000
+ 80321ee:	683b      	ldr	r3, [r7, #0]
+ 80321f0:	681b      	ldr	r3, [r3, #0]
+ 80321f2:	069b      	lsls	r3, r3, #26
+ 80321f4:	429a      	cmp	r2, r3
+ 80321f6:	d107      	bne.n	8032208 <HAL_ADC_ConfigChannel+0x1dc>
+          {
+            CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_SSATE);
+ 80321f8:	687b      	ldr	r3, [r7, #4]
+ 80321fa:	681b      	ldr	r3, [r3, #0]
+ 80321fc:	6e1a      	ldr	r2, [r3, #96]	@ 0x60
+ 80321fe:	687b      	ldr	r3, [r7, #4]
+ 8032200:	681b      	ldr	r3, [r3, #0]
+ 8032202:	f022 4200 	bic.w	r2, r2, #2147483648	@ 0x80000000
+ 8032206:	661a      	str	r2, [r3, #96]	@ 0x60
+          }
+          if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
+ 8032208:	687b      	ldr	r3, [r7, #4]
+ 803220a:	681b      	ldr	r3, [r3, #0]
+ 803220c:	6e5b      	ldr	r3, [r3, #100]	@ 0x64
+ 803220e:	f003 42f8 	and.w	r2, r3, #2080374784	@ 0x7c000000
+ 8032212:	683b      	ldr	r3, [r7, #0]
+ 8032214:	681b      	ldr	r3, [r3, #0]
+ 8032216:	069b      	lsls	r3, r3, #26
+ 8032218:	429a      	cmp	r2, r3
+ 803221a:	d107      	bne.n	803222c <HAL_ADC_ConfigChannel+0x200>
+          {
+            CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_SSATE);
+ 803221c:	687b      	ldr	r3, [r7, #4]
+ 803221e:	681b      	ldr	r3, [r3, #0]
+ 8032220:	6e5a      	ldr	r2, [r3, #100]	@ 0x64
+ 8032222:	687b      	ldr	r3, [r7, #4]
+ 8032224:	681b      	ldr	r3, [r3, #0]
+ 8032226:	f022 4200 	bic.w	r2, r2, #2147483648	@ 0x80000000
+ 803222a:	665a      	str	r2, [r3, #100]	@ 0x64
+          }
+          if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
+ 803222c:	687b      	ldr	r3, [r7, #4]
+ 803222e:	681b      	ldr	r3, [r3, #0]
+ 8032230:	6e9b      	ldr	r3, [r3, #104]	@ 0x68
+ 8032232:	f003 42f8 	and.w	r2, r3, #2080374784	@ 0x7c000000
+ 8032236:	683b      	ldr	r3, [r7, #0]
+ 8032238:	681b      	ldr	r3, [r3, #0]
+ 803223a:	069b      	lsls	r3, r3, #26
+ 803223c:	429a      	cmp	r2, r3
+ 803223e:	d107      	bne.n	8032250 <HAL_ADC_ConfigChannel+0x224>
+          {
+            CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_SSATE);
+ 8032240:	687b      	ldr	r3, [r7, #4]
+ 8032242:	681b      	ldr	r3, [r3, #0]
+ 8032244:	6e9a      	ldr	r2, [r3, #104]	@ 0x68
+ 8032246:	687b      	ldr	r3, [r7, #4]
+ 8032248:	681b      	ldr	r3, [r3, #0]
+ 803224a:	f022 4200 	bic.w	r2, r2, #2147483648	@ 0x80000000
+ 803224e:	669a      	str	r2, [r3, #104]	@ 0x68
+          }
+          if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
+ 8032250:	687b      	ldr	r3, [r7, #4]
+ 8032252:	681b      	ldr	r3, [r3, #0]
+ 8032254:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
+ 8032256:	f003 42f8 	and.w	r2, r3, #2080374784	@ 0x7c000000
+ 803225a:	683b      	ldr	r3, [r7, #0]
+ 803225c:	681b      	ldr	r3, [r3, #0]
+ 803225e:	069b      	lsls	r3, r3, #26
+ 8032260:	429a      	cmp	r2, r3
+ 8032262:	d107      	bne.n	8032274 <HAL_ADC_ConfigChannel+0x248>
+          {
+            CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_SSATE);
+ 8032264:	687b      	ldr	r3, [r7, #4]
+ 8032266:	681b      	ldr	r3, [r3, #0]
+ 8032268:	6eda      	ldr	r2, [r3, #108]	@ 0x6c
+ 803226a:	687b      	ldr	r3, [r7, #4]
+ 803226c:	681b      	ldr	r3, [r3, #0]
+ 803226e:	f022 4200 	bic.w	r2, r2, #2147483648	@ 0x80000000
+ 8032272:	66da      	str	r2, [r3, #108]	@ 0x6c
+
+    /* Parameters update conditioned to ADC state:                              */
+    /* Parameters that can be updated only when ADC is disabled:                */
+    /*  - Single or differential mode                                           */
+    /*  - Internal measurement channels: Vbat/VrefInt/TempSensor                */
+    if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+ 8032274:	687b      	ldr	r3, [r7, #4]
+ 8032276:	681b      	ldr	r3, [r3, #0]
+ 8032278:	4618      	mov	r0, r3
+ 803227a:	f7ff fcfb 	bl	8031c74 <LL_ADC_IsEnabled>
+ 803227e:	4603      	mov	r3, r0
+ 8032280:	2b00      	cmp	r3, #0
+ 8032282:	f040 8211 	bne.w	80326a8 <HAL_ADC_ConfigChannel+0x67c>
+    {
+      /* Set mode single-ended or differential input of the selected ADC channel */
+      LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfig->Channel, sConfig->SingleDiff);
+ 8032286:	687b      	ldr	r3, [r7, #4]
+ 8032288:	6818      	ldr	r0, [r3, #0]
+ 803228a:	683b      	ldr	r3, [r7, #0]
+ 803228c:	6819      	ldr	r1, [r3, #0]
+ 803228e:	683b      	ldr	r3, [r7, #0]
+ 8032290:	68db      	ldr	r3, [r3, #12]
+ 8032292:	461a      	mov	r2, r3
+ 8032294:	f7ff fc7c 	bl	8031b90 <LL_ADC_SetChannelSingleDiff>
+
+      /* Configuration of differential mode */
+      if (sConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED)
+ 8032298:	683b      	ldr	r3, [r7, #0]
+ 803229a:	68db      	ldr	r3, [r3, #12]
+ 803229c:	4aa1      	ldr	r2, [pc, #644]	@ (8032524 <HAL_ADC_ConfigChannel+0x4f8>)
+ 803229e:	4293      	cmp	r3, r2
+ 80322a0:	f040 812e 	bne.w	8032500 <HAL_ADC_ConfigChannel+0x4d4>
+      {
+        /* Set sampling time of the selected ADC channel */
+        /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */
+        LL_ADC_SetChannelSamplingTime(hadc->Instance,
+ 80322a4:	687b      	ldr	r3, [r7, #4]
+ 80322a6:	6818      	ldr	r0, [r3, #0]
+                                      (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)),
+ 80322a8:	683b      	ldr	r3, [r7, #0]
+ 80322aa:	681b      	ldr	r3, [r3, #0]
+ 80322ac:	f3c3 0313 	ubfx	r3, r3, #0, #20
+ 80322b0:	2b00      	cmp	r3, #0
+ 80322b2:	d10b      	bne.n	80322cc <HAL_ADC_ConfigChannel+0x2a0>
+ 80322b4:	683b      	ldr	r3, [r7, #0]
+ 80322b6:	681b      	ldr	r3, [r3, #0]
+ 80322b8:	0e9b      	lsrs	r3, r3, #26
+ 80322ba:	3301      	adds	r3, #1
+ 80322bc:	f003 031f 	and.w	r3, r3, #31
+ 80322c0:	2b09      	cmp	r3, #9
+ 80322c2:	bf94      	ite	ls
+ 80322c4:	2301      	movls	r3, #1
+ 80322c6:	2300      	movhi	r3, #0
+ 80322c8:	b2db      	uxtb	r3, r3
+ 80322ca:	e019      	b.n	8032300 <HAL_ADC_ConfigChannel+0x2d4>
+ 80322cc:	683b      	ldr	r3, [r7, #0]
+ 80322ce:	681b      	ldr	r3, [r3, #0]
+ 80322d0:	65bb      	str	r3, [r7, #88]	@ 0x58
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+ 80322d2:	6dbb      	ldr	r3, [r7, #88]	@ 0x58
+ 80322d4:	fa93 f3a3 	rbit	r3, r3
+ 80322d8:	657b      	str	r3, [r7, #84]	@ 0x54
+  return result;
+ 80322da:	6d7b      	ldr	r3, [r7, #84]	@ 0x54
+ 80322dc:	65fb      	str	r3, [r7, #92]	@ 0x5c
+  if (value == 0U)
+ 80322de:	6dfb      	ldr	r3, [r7, #92]	@ 0x5c
+ 80322e0:	2b00      	cmp	r3, #0
+ 80322e2:	d101      	bne.n	80322e8 <HAL_ADC_ConfigChannel+0x2bc>
+    return 32U;
+ 80322e4:	2320      	movs	r3, #32
+ 80322e6:	e003      	b.n	80322f0 <HAL_ADC_ConfigChannel+0x2c4>
+  return __builtin_clz(value);
+ 80322e8:	6dfb      	ldr	r3, [r7, #92]	@ 0x5c
+ 80322ea:	fab3 f383 	clz	r3, r3
+ 80322ee:	b2db      	uxtb	r3, r3
+ 80322f0:	3301      	adds	r3, #1
+ 80322f2:	f003 031f 	and.w	r3, r3, #31
+ 80322f6:	2b09      	cmp	r3, #9
+ 80322f8:	bf94      	ite	ls
+ 80322fa:	2301      	movls	r3, #1
+ 80322fc:	2300      	movhi	r3, #0
+ 80322fe:	b2db      	uxtb	r3, r3
+        LL_ADC_SetChannelSamplingTime(hadc->Instance,
+ 8032300:	2b00      	cmp	r3, #0
+ 8032302:	d079      	beq.n	80323f8 <HAL_ADC_ConfigChannel+0x3cc>
+                                      (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)),
+ 8032304:	683b      	ldr	r3, [r7, #0]
+ 8032306:	681b      	ldr	r3, [r3, #0]
+ 8032308:	f3c3 0313 	ubfx	r3, r3, #0, #20
+ 803230c:	2b00      	cmp	r3, #0
+ 803230e:	d107      	bne.n	8032320 <HAL_ADC_ConfigChannel+0x2f4>
+ 8032310:	683b      	ldr	r3, [r7, #0]
+ 8032312:	681b      	ldr	r3, [r3, #0]
+ 8032314:	0e9b      	lsrs	r3, r3, #26
+ 8032316:	3301      	adds	r3, #1
+ 8032318:	069b      	lsls	r3, r3, #26
+ 803231a:	f003 42f8 	and.w	r2, r3, #2080374784	@ 0x7c000000
+ 803231e:	e015      	b.n	803234c <HAL_ADC_ConfigChannel+0x320>
+ 8032320:	683b      	ldr	r3, [r7, #0]
+ 8032322:	681b      	ldr	r3, [r3, #0]
+ 8032324:	64fb      	str	r3, [r7, #76]	@ 0x4c
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+ 8032326:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
+ 8032328:	fa93 f3a3 	rbit	r3, r3
+ 803232c:	64bb      	str	r3, [r7, #72]	@ 0x48
+  return result;
+ 803232e:	6cbb      	ldr	r3, [r7, #72]	@ 0x48
+ 8032330:	653b      	str	r3, [r7, #80]	@ 0x50
+  if (value == 0U)
+ 8032332:	6d3b      	ldr	r3, [r7, #80]	@ 0x50
+ 8032334:	2b00      	cmp	r3, #0
+ 8032336:	d101      	bne.n	803233c <HAL_ADC_ConfigChannel+0x310>
+    return 32U;
+ 8032338:	2320      	movs	r3, #32
+ 803233a:	e003      	b.n	8032344 <HAL_ADC_ConfigChannel+0x318>
+  return __builtin_clz(value);
+ 803233c:	6d3b      	ldr	r3, [r7, #80]	@ 0x50
+ 803233e:	fab3 f383 	clz	r3, r3
+ 8032342:	b2db      	uxtb	r3, r3
+ 8032344:	3301      	adds	r3, #1
+ 8032346:	069b      	lsls	r3, r3, #26
+ 8032348:	f003 42f8 	and.w	r2, r3, #2080374784	@ 0x7c000000
+ 803234c:	683b      	ldr	r3, [r7, #0]
+ 803234e:	681b      	ldr	r3, [r3, #0]
+ 8032350:	f3c3 0313 	ubfx	r3, r3, #0, #20
+ 8032354:	2b00      	cmp	r3, #0
+ 8032356:	d109      	bne.n	803236c <HAL_ADC_ConfigChannel+0x340>
+ 8032358:	683b      	ldr	r3, [r7, #0]
+ 803235a:	681b      	ldr	r3, [r3, #0]
+ 803235c:	0e9b      	lsrs	r3, r3, #26
+ 803235e:	3301      	adds	r3, #1
+ 8032360:	f003 031f 	and.w	r3, r3, #31
+ 8032364:	2101      	movs	r1, #1
+ 8032366:	fa01 f303 	lsl.w	r3, r1, r3
+ 803236a:	e017      	b.n	803239c <HAL_ADC_ConfigChannel+0x370>
+ 803236c:	683b      	ldr	r3, [r7, #0]
+ 803236e:	681b      	ldr	r3, [r3, #0]
+ 8032370:	643b      	str	r3, [r7, #64]	@ 0x40
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+ 8032372:	6c3b      	ldr	r3, [r7, #64]	@ 0x40
+ 8032374:	fa93 f3a3 	rbit	r3, r3
+ 8032378:	63fb      	str	r3, [r7, #60]	@ 0x3c
+  return result;
+ 803237a:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
+ 803237c:	647b      	str	r3, [r7, #68]	@ 0x44
+  if (value == 0U)
+ 803237e:	6c7b      	ldr	r3, [r7, #68]	@ 0x44
+ 8032380:	2b00      	cmp	r3, #0
+ 8032382:	d101      	bne.n	8032388 <HAL_ADC_ConfigChannel+0x35c>
+    return 32U;
+ 8032384:	2320      	movs	r3, #32
+ 8032386:	e003      	b.n	8032390 <HAL_ADC_ConfigChannel+0x364>
+  return __builtin_clz(value);
+ 8032388:	6c7b      	ldr	r3, [r7, #68]	@ 0x44
+ 803238a:	fab3 f383 	clz	r3, r3
+ 803238e:	b2db      	uxtb	r3, r3
+ 8032390:	3301      	adds	r3, #1
+ 8032392:	f003 031f 	and.w	r3, r3, #31
+ 8032396:	2101      	movs	r1, #1
+ 8032398:	fa01 f303 	lsl.w	r3, r1, r3
+ 803239c:	ea42 0103 	orr.w	r1, r2, r3
+ 80323a0:	683b      	ldr	r3, [r7, #0]
+ 80323a2:	681b      	ldr	r3, [r3, #0]
+ 80323a4:	f3c3 0313 	ubfx	r3, r3, #0, #20
+ 80323a8:	2b00      	cmp	r3, #0
+ 80323aa:	d10a      	bne.n	80323c2 <HAL_ADC_ConfigChannel+0x396>
+ 80323ac:	683b      	ldr	r3, [r7, #0]
+ 80323ae:	681b      	ldr	r3, [r3, #0]
+ 80323b0:	0e9b      	lsrs	r3, r3, #26
+ 80323b2:	3301      	adds	r3, #1
+ 80323b4:	f003 021f 	and.w	r2, r3, #31
+ 80323b8:	4613      	mov	r3, r2
+ 80323ba:	005b      	lsls	r3, r3, #1
+ 80323bc:	4413      	add	r3, r2
+ 80323be:	051b      	lsls	r3, r3, #20
+ 80323c0:	e018      	b.n	80323f4 <HAL_ADC_ConfigChannel+0x3c8>
+ 80323c2:	683b      	ldr	r3, [r7, #0]
+ 80323c4:	681b      	ldr	r3, [r3, #0]
+ 80323c6:	637b      	str	r3, [r7, #52]	@ 0x34
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+ 80323c8:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
+ 80323ca:	fa93 f3a3 	rbit	r3, r3
+ 80323ce:	633b      	str	r3, [r7, #48]	@ 0x30
+  return result;
+ 80323d0:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
+ 80323d2:	63bb      	str	r3, [r7, #56]	@ 0x38
+  if (value == 0U)
+ 80323d4:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 80323d6:	2b00      	cmp	r3, #0
+ 80323d8:	d101      	bne.n	80323de <HAL_ADC_ConfigChannel+0x3b2>
+    return 32U;
+ 80323da:	2320      	movs	r3, #32
+ 80323dc:	e003      	b.n	80323e6 <HAL_ADC_ConfigChannel+0x3ba>
+  return __builtin_clz(value);
+ 80323de:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 80323e0:	fab3 f383 	clz	r3, r3
+ 80323e4:	b2db      	uxtb	r3, r3
+ 80323e6:	3301      	adds	r3, #1
+ 80323e8:	f003 021f 	and.w	r2, r3, #31
+ 80323ec:	4613      	mov	r3, r2
+ 80323ee:	005b      	lsls	r3, r3, #1
+ 80323f0:	4413      	add	r3, r2
+ 80323f2:	051b      	lsls	r3, r3, #20
+        LL_ADC_SetChannelSamplingTime(hadc->Instance,
+ 80323f4:	430b      	orrs	r3, r1
+ 80323f6:	e07e      	b.n	80324f6 <HAL_ADC_ConfigChannel+0x4ca>
+                                      (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)),
+ 80323f8:	683b      	ldr	r3, [r7, #0]
+ 80323fa:	681b      	ldr	r3, [r3, #0]
+ 80323fc:	f3c3 0313 	ubfx	r3, r3, #0, #20
+ 8032400:	2b00      	cmp	r3, #0
+ 8032402:	d107      	bne.n	8032414 <HAL_ADC_ConfigChannel+0x3e8>
+ 8032404:	683b      	ldr	r3, [r7, #0]
+ 8032406:	681b      	ldr	r3, [r3, #0]
+ 8032408:	0e9b      	lsrs	r3, r3, #26
+ 803240a:	3301      	adds	r3, #1
+ 803240c:	069b      	lsls	r3, r3, #26
+ 803240e:	f003 42f8 	and.w	r2, r3, #2080374784	@ 0x7c000000
+ 8032412:	e015      	b.n	8032440 <HAL_ADC_ConfigChannel+0x414>
+ 8032414:	683b      	ldr	r3, [r7, #0]
+ 8032416:	681b      	ldr	r3, [r3, #0]
+ 8032418:	62bb      	str	r3, [r7, #40]	@ 0x28
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+ 803241a:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 803241c:	fa93 f3a3 	rbit	r3, r3
+ 8032420:	627b      	str	r3, [r7, #36]	@ 0x24
+  return result;
+ 8032422:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 8032424:	62fb      	str	r3, [r7, #44]	@ 0x2c
+  if (value == 0U)
+ 8032426:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
+ 8032428:	2b00      	cmp	r3, #0
+ 803242a:	d101      	bne.n	8032430 <HAL_ADC_ConfigChannel+0x404>
+    return 32U;
+ 803242c:	2320      	movs	r3, #32
+ 803242e:	e003      	b.n	8032438 <HAL_ADC_ConfigChannel+0x40c>
+  return __builtin_clz(value);
+ 8032430:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
+ 8032432:	fab3 f383 	clz	r3, r3
+ 8032436:	b2db      	uxtb	r3, r3
+ 8032438:	3301      	adds	r3, #1
+ 803243a:	069b      	lsls	r3, r3, #26
+ 803243c:	f003 42f8 	and.w	r2, r3, #2080374784	@ 0x7c000000
+ 8032440:	683b      	ldr	r3, [r7, #0]
+ 8032442:	681b      	ldr	r3, [r3, #0]
+ 8032444:	f3c3 0313 	ubfx	r3, r3, #0, #20
+ 8032448:	2b00      	cmp	r3, #0
+ 803244a:	d109      	bne.n	8032460 <HAL_ADC_ConfigChannel+0x434>
+ 803244c:	683b      	ldr	r3, [r7, #0]
+ 803244e:	681b      	ldr	r3, [r3, #0]
+ 8032450:	0e9b      	lsrs	r3, r3, #26
+ 8032452:	3301      	adds	r3, #1
+ 8032454:	f003 031f 	and.w	r3, r3, #31
+ 8032458:	2101      	movs	r1, #1
+ 803245a:	fa01 f303 	lsl.w	r3, r1, r3
+ 803245e:	e017      	b.n	8032490 <HAL_ADC_ConfigChannel+0x464>
+ 8032460:	683b      	ldr	r3, [r7, #0]
+ 8032462:	681b      	ldr	r3, [r3, #0]
+ 8032464:	61fb      	str	r3, [r7, #28]
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+ 8032466:	69fb      	ldr	r3, [r7, #28]
+ 8032468:	fa93 f3a3 	rbit	r3, r3
+ 803246c:	61bb      	str	r3, [r7, #24]
+  return result;
+ 803246e:	69bb      	ldr	r3, [r7, #24]
+ 8032470:	623b      	str	r3, [r7, #32]
+  if (value == 0U)
+ 8032472:	6a3b      	ldr	r3, [r7, #32]
+ 8032474:	2b00      	cmp	r3, #0
+ 8032476:	d101      	bne.n	803247c <HAL_ADC_ConfigChannel+0x450>
+    return 32U;
+ 8032478:	2320      	movs	r3, #32
+ 803247a:	e003      	b.n	8032484 <HAL_ADC_ConfigChannel+0x458>
+  return __builtin_clz(value);
+ 803247c:	6a3b      	ldr	r3, [r7, #32]
+ 803247e:	fab3 f383 	clz	r3, r3
+ 8032482:	b2db      	uxtb	r3, r3
+ 8032484:	3301      	adds	r3, #1
+ 8032486:	f003 031f 	and.w	r3, r3, #31
+ 803248a:	2101      	movs	r1, #1
+ 803248c:	fa01 f303 	lsl.w	r3, r1, r3
+ 8032490:	ea42 0103 	orr.w	r1, r2, r3
+ 8032494:	683b      	ldr	r3, [r7, #0]
+ 8032496:	681b      	ldr	r3, [r3, #0]
+ 8032498:	f3c3 0313 	ubfx	r3, r3, #0, #20
+ 803249c:	2b00      	cmp	r3, #0
+ 803249e:	d10d      	bne.n	80324bc <HAL_ADC_ConfigChannel+0x490>
+ 80324a0:	683b      	ldr	r3, [r7, #0]
+ 80324a2:	681b      	ldr	r3, [r3, #0]
+ 80324a4:	0e9b      	lsrs	r3, r3, #26
+ 80324a6:	3301      	adds	r3, #1
+ 80324a8:	f003 021f 	and.w	r2, r3, #31
+ 80324ac:	4613      	mov	r3, r2
+ 80324ae:	005b      	lsls	r3, r3, #1
+ 80324b0:	4413      	add	r3, r2
+ 80324b2:	3b1e      	subs	r3, #30
+ 80324b4:	051b      	lsls	r3, r3, #20
+ 80324b6:	f043 7300 	orr.w	r3, r3, #33554432	@ 0x2000000
+ 80324ba:	e01b      	b.n	80324f4 <HAL_ADC_ConfigChannel+0x4c8>
+ 80324bc:	683b      	ldr	r3, [r7, #0]
+ 80324be:	681b      	ldr	r3, [r3, #0]
+ 80324c0:	613b      	str	r3, [r7, #16]
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+ 80324c2:	693b      	ldr	r3, [r7, #16]
+ 80324c4:	fa93 f3a3 	rbit	r3, r3
+ 80324c8:	60fb      	str	r3, [r7, #12]
+  return result;
+ 80324ca:	68fb      	ldr	r3, [r7, #12]
+ 80324cc:	617b      	str	r3, [r7, #20]
+  if (value == 0U)
+ 80324ce:	697b      	ldr	r3, [r7, #20]
+ 80324d0:	2b00      	cmp	r3, #0
+ 80324d2:	d101      	bne.n	80324d8 <HAL_ADC_ConfigChannel+0x4ac>
+    return 32U;
+ 80324d4:	2320      	movs	r3, #32
+ 80324d6:	e003      	b.n	80324e0 <HAL_ADC_ConfigChannel+0x4b4>
+  return __builtin_clz(value);
+ 80324d8:	697b      	ldr	r3, [r7, #20]
+ 80324da:	fab3 f383 	clz	r3, r3
+ 80324de:	b2db      	uxtb	r3, r3
+ 80324e0:	3301      	adds	r3, #1
+ 80324e2:	f003 021f 	and.w	r2, r3, #31
+ 80324e6:	4613      	mov	r3, r2
+ 80324e8:	005b      	lsls	r3, r3, #1
+ 80324ea:	4413      	add	r3, r2
+ 80324ec:	3b1e      	subs	r3, #30
+ 80324ee:	051b      	lsls	r3, r3, #20
+ 80324f0:	f043 7300 	orr.w	r3, r3, #33554432	@ 0x2000000
+        LL_ADC_SetChannelSamplingTime(hadc->Instance,
+ 80324f4:	430b      	orrs	r3, r1
+ 80324f6:	683a      	ldr	r2, [r7, #0]
+ 80324f8:	6892      	ldr	r2, [r2, #8]
+ 80324fa:	4619      	mov	r1, r3
+ 80324fc:	f7ff fb1c 	bl	8031b38 <LL_ADC_SetChannelSamplingTime>
+      /* If internal channel selected, enable dedicated internal buffers and    */
+      /* paths.                                                                 */
+      /* Note: these internal measurement paths can be disabled using           */
+      /* HAL_ADC_DeInit().                                                      */
+
+      if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
+ 8032500:	683b      	ldr	r3, [r7, #0]
+ 8032502:	681b      	ldr	r3, [r3, #0]
+ 8032504:	2b00      	cmp	r3, #0
+ 8032506:	f280 80cf 	bge.w	80326a8 <HAL_ADC_ConfigChannel+0x67c>
+      {
+        /* Configuration of common ADC parameters                                 */
+
+        tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+ 803250a:	687b      	ldr	r3, [r7, #4]
+ 803250c:	681b      	ldr	r3, [r3, #0]
+ 803250e:	4a06      	ldr	r2, [pc, #24]	@ (8032528 <HAL_ADC_ConfigChannel+0x4fc>)
+ 8032510:	4293      	cmp	r3, r2
+ 8032512:	d004      	beq.n	803251e <HAL_ADC_ConfigChannel+0x4f2>
+ 8032514:	687b      	ldr	r3, [r7, #4]
+ 8032516:	681b      	ldr	r3, [r3, #0]
+ 8032518:	4a04      	ldr	r2, [pc, #16]	@ (803252c <HAL_ADC_ConfigChannel+0x500>)
+ 803251a:	4293      	cmp	r3, r2
+ 803251c:	d10a      	bne.n	8032534 <HAL_ADC_ConfigChannel+0x508>
+ 803251e:	4b04      	ldr	r3, [pc, #16]	@ (8032530 <HAL_ADC_ConfigChannel+0x504>)
+ 8032520:	e009      	b.n	8032536 <HAL_ADC_ConfigChannel+0x50a>
+ 8032522:	bf00      	nop
+ 8032524:	47ff0000 	.word	0x47ff0000
+ 8032528:	40022000 	.word	0x40022000
+ 803252c:	40022100 	.word	0x40022100
+ 8032530:	40022300 	.word	0x40022300
+ 8032534:	4b61      	ldr	r3, [pc, #388]	@ (80326bc <HAL_ADC_ConfigChannel+0x690>)
+ 8032536:	4618      	mov	r0, r3
+ 8032538:	f7ff fa70 	bl	8031a1c <LL_ADC_GetCommonPathInternalCh>
+ 803253c:	66f8      	str	r0, [r7, #108]	@ 0x6c
+
+        /* Software is allowed to change common parameters only when all ADCs   */
+        /* of the common group are disabled.                                    */
+        if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
+ 803253e:	687b      	ldr	r3, [r7, #4]
+ 8032540:	681b      	ldr	r3, [r3, #0]
+ 8032542:	4a5f      	ldr	r2, [pc, #380]	@ (80326c0 <HAL_ADC_ConfigChannel+0x694>)
+ 8032544:	4293      	cmp	r3, r2
+ 8032546:	d004      	beq.n	8032552 <HAL_ADC_ConfigChannel+0x526>
+ 8032548:	687b      	ldr	r3, [r7, #4]
+ 803254a:	681b      	ldr	r3, [r3, #0]
+ 803254c:	4a5d      	ldr	r2, [pc, #372]	@ (80326c4 <HAL_ADC_ConfigChannel+0x698>)
+ 803254e:	4293      	cmp	r3, r2
+ 8032550:	d10e      	bne.n	8032570 <HAL_ADC_ConfigChannel+0x544>
+ 8032552:	485b      	ldr	r0, [pc, #364]	@ (80326c0 <HAL_ADC_ConfigChannel+0x694>)
+ 8032554:	f7ff fb8e 	bl	8031c74 <LL_ADC_IsEnabled>
+ 8032558:	4604      	mov	r4, r0
+ 803255a:	485a      	ldr	r0, [pc, #360]	@ (80326c4 <HAL_ADC_ConfigChannel+0x698>)
+ 803255c:	f7ff fb8a 	bl	8031c74 <LL_ADC_IsEnabled>
+ 8032560:	4603      	mov	r3, r0
+ 8032562:	4323      	orrs	r3, r4
+ 8032564:	2b00      	cmp	r3, #0
+ 8032566:	bf0c      	ite	eq
+ 8032568:	2301      	moveq	r3, #1
+ 803256a:	2300      	movne	r3, #0
+ 803256c:	b2db      	uxtb	r3, r3
+ 803256e:	e008      	b.n	8032582 <HAL_ADC_ConfigChannel+0x556>
+ 8032570:	4855      	ldr	r0, [pc, #340]	@ (80326c8 <HAL_ADC_ConfigChannel+0x69c>)
+ 8032572:	f7ff fb7f 	bl	8031c74 <LL_ADC_IsEnabled>
+ 8032576:	4603      	mov	r3, r0
+ 8032578:	2b00      	cmp	r3, #0
+ 803257a:	bf0c      	ite	eq
+ 803257c:	2301      	moveq	r3, #1
+ 803257e:	2300      	movne	r3, #0
+ 8032580:	b2db      	uxtb	r3, r3
+ 8032582:	2b00      	cmp	r3, #0
+ 8032584:	d07d      	beq.n	8032682 <HAL_ADC_ConfigChannel+0x656>
+        {
+          /* If the requested internal measurement path has already been enabled, */
+          /* bypass the configuration processing.                                 */
+          if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
+ 8032586:	683b      	ldr	r3, [r7, #0]
+ 8032588:	681b      	ldr	r3, [r3, #0]
+ 803258a:	4a50      	ldr	r2, [pc, #320]	@ (80326cc <HAL_ADC_ConfigChannel+0x6a0>)
+ 803258c:	4293      	cmp	r3, r2
+ 803258e:	d130      	bne.n	80325f2 <HAL_ADC_ConfigChannel+0x5c6>
+ 8032590:	6efb      	ldr	r3, [r7, #108]	@ 0x6c
+ 8032592:	f403 0300 	and.w	r3, r3, #8388608	@ 0x800000
+ 8032596:	2b00      	cmp	r3, #0
+ 8032598:	d12b      	bne.n	80325f2 <HAL_ADC_ConfigChannel+0x5c6>
+          {
+            if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
+ 803259a:	687b      	ldr	r3, [r7, #4]
+ 803259c:	681b      	ldr	r3, [r3, #0]
+ 803259e:	4a4a      	ldr	r2, [pc, #296]	@ (80326c8 <HAL_ADC_ConfigChannel+0x69c>)
+ 80325a0:	4293      	cmp	r3, r2
+ 80325a2:	f040 8081 	bne.w	80326a8 <HAL_ADC_ConfigChannel+0x67c>
+            {
+              LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel);
+ 80325a6:	687b      	ldr	r3, [r7, #4]
+ 80325a8:	681b      	ldr	r3, [r3, #0]
+ 80325aa:	4a45      	ldr	r2, [pc, #276]	@ (80326c0 <HAL_ADC_ConfigChannel+0x694>)
+ 80325ac:	4293      	cmp	r3, r2
+ 80325ae:	d004      	beq.n	80325ba <HAL_ADC_ConfigChannel+0x58e>
+ 80325b0:	687b      	ldr	r3, [r7, #4]
+ 80325b2:	681b      	ldr	r3, [r3, #0]
+ 80325b4:	4a43      	ldr	r2, [pc, #268]	@ (80326c4 <HAL_ADC_ConfigChannel+0x698>)
+ 80325b6:	4293      	cmp	r3, r2
+ 80325b8:	d101      	bne.n	80325be <HAL_ADC_ConfigChannel+0x592>
+ 80325ba:	4a45      	ldr	r2, [pc, #276]	@ (80326d0 <HAL_ADC_ConfigChannel+0x6a4>)
+ 80325bc:	e000      	b.n	80325c0 <HAL_ADC_ConfigChannel+0x594>
+ 80325be:	4a3f      	ldr	r2, [pc, #252]	@ (80326bc <HAL_ADC_ConfigChannel+0x690>)
+ 80325c0:	6efb      	ldr	r3, [r7, #108]	@ 0x6c
+ 80325c2:	f443 0300 	orr.w	r3, r3, #8388608	@ 0x800000
+ 80325c6:	4619      	mov	r1, r3
+ 80325c8:	4610      	mov	r0, r2
+ 80325ca:	f7ff fa14 	bl	80319f6 <LL_ADC_SetCommonPathInternalCh>
+              /* Delay for temperature sensor stabilization time */
+              /* Wait loop initialization and execution */
+              /* Note: Variable divided by 2 to compensate partially              */
+              /*       CPU processing cycles, scaling in us split to not          */
+              /*       exceed 32 bits register capacity and handle low frequency. */
+              wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
+ 80325ce:	4b41      	ldr	r3, [pc, #260]	@ (80326d4 <HAL_ADC_ConfigChannel+0x6a8>)
+ 80325d0:	681b      	ldr	r3, [r3, #0]
+ 80325d2:	099b      	lsrs	r3, r3, #6
+ 80325d4:	4a40      	ldr	r2, [pc, #256]	@ (80326d8 <HAL_ADC_ConfigChannel+0x6ac>)
+ 80325d6:	fba2 2303 	umull	r2, r3, r2, r3
+ 80325da:	099b      	lsrs	r3, r3, #6
+ 80325dc:	3301      	adds	r3, #1
+ 80325de:	005b      	lsls	r3, r3, #1
+ 80325e0:	60bb      	str	r3, [r7, #8]
+              while (wait_loop_index != 0UL)
+ 80325e2:	e002      	b.n	80325ea <HAL_ADC_ConfigChannel+0x5be>
+              {
+                wait_loop_index--;
+ 80325e4:	68bb      	ldr	r3, [r7, #8]
+ 80325e6:	3b01      	subs	r3, #1
+ 80325e8:	60bb      	str	r3, [r7, #8]
+              while (wait_loop_index != 0UL)
+ 80325ea:	68bb      	ldr	r3, [r7, #8]
+ 80325ec:	2b00      	cmp	r3, #0
+ 80325ee:	d1f9      	bne.n	80325e4 <HAL_ADC_ConfigChannel+0x5b8>
+            if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
+ 80325f0:	e05a      	b.n	80326a8 <HAL_ADC_ConfigChannel+0x67c>
+              }
+            }
+          }
+          else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
+ 80325f2:	683b      	ldr	r3, [r7, #0]
+ 80325f4:	681b      	ldr	r3, [r3, #0]
+ 80325f6:	4a39      	ldr	r2, [pc, #228]	@ (80326dc <HAL_ADC_ConfigChannel+0x6b0>)
+ 80325f8:	4293      	cmp	r3, r2
+ 80325fa:	d11e      	bne.n	803263a <HAL_ADC_ConfigChannel+0x60e>
+ 80325fc:	6efb      	ldr	r3, [r7, #108]	@ 0x6c
+ 80325fe:	f003 7380 	and.w	r3, r3, #16777216	@ 0x1000000
+ 8032602:	2b00      	cmp	r3, #0
+ 8032604:	d119      	bne.n	803263a <HAL_ADC_ConfigChannel+0x60e>
+          {
+            if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
+ 8032606:	687b      	ldr	r3, [r7, #4]
+ 8032608:	681b      	ldr	r3, [r3, #0]
+ 803260a:	4a2f      	ldr	r2, [pc, #188]	@ (80326c8 <HAL_ADC_ConfigChannel+0x69c>)
+ 803260c:	4293      	cmp	r3, r2
+ 803260e:	d14b      	bne.n	80326a8 <HAL_ADC_ConfigChannel+0x67c>
+            {
+              LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
+ 8032610:	687b      	ldr	r3, [r7, #4]
+ 8032612:	681b      	ldr	r3, [r3, #0]
+ 8032614:	4a2a      	ldr	r2, [pc, #168]	@ (80326c0 <HAL_ADC_ConfigChannel+0x694>)
+ 8032616:	4293      	cmp	r3, r2
+ 8032618:	d004      	beq.n	8032624 <HAL_ADC_ConfigChannel+0x5f8>
+ 803261a:	687b      	ldr	r3, [r7, #4]
+ 803261c:	681b      	ldr	r3, [r3, #0]
+ 803261e:	4a29      	ldr	r2, [pc, #164]	@ (80326c4 <HAL_ADC_ConfigChannel+0x698>)
+ 8032620:	4293      	cmp	r3, r2
+ 8032622:	d101      	bne.n	8032628 <HAL_ADC_ConfigChannel+0x5fc>
+ 8032624:	4a2a      	ldr	r2, [pc, #168]	@ (80326d0 <HAL_ADC_ConfigChannel+0x6a4>)
+ 8032626:	e000      	b.n	803262a <HAL_ADC_ConfigChannel+0x5fe>
+ 8032628:	4a24      	ldr	r2, [pc, #144]	@ (80326bc <HAL_ADC_ConfigChannel+0x690>)
+ 803262a:	6efb      	ldr	r3, [r7, #108]	@ 0x6c
+ 803262c:	f043 7380 	orr.w	r3, r3, #16777216	@ 0x1000000
+ 8032630:	4619      	mov	r1, r3
+ 8032632:	4610      	mov	r0, r2
+ 8032634:	f7ff f9df 	bl	80319f6 <LL_ADC_SetCommonPathInternalCh>
+            if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
+ 8032638:	e036      	b.n	80326a8 <HAL_ADC_ConfigChannel+0x67c>
+            }
+          }
+          else if ((sConfig->Channel == ADC_CHANNEL_VREFINT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
+ 803263a:	683b      	ldr	r3, [r7, #0]
+ 803263c:	681b      	ldr	r3, [r3, #0]
+ 803263e:	4a28      	ldr	r2, [pc, #160]	@ (80326e0 <HAL_ADC_ConfigChannel+0x6b4>)
+ 8032640:	4293      	cmp	r3, r2
+ 8032642:	d131      	bne.n	80326a8 <HAL_ADC_ConfigChannel+0x67c>
+ 8032644:	6efb      	ldr	r3, [r7, #108]	@ 0x6c
+ 8032646:	f403 0380 	and.w	r3, r3, #4194304	@ 0x400000
+ 803264a:	2b00      	cmp	r3, #0
+ 803264c:	d12c      	bne.n	80326a8 <HAL_ADC_ConfigChannel+0x67c>
+          {
+            if (ADC_VREFINT_INSTANCE(hadc))
+ 803264e:	687b      	ldr	r3, [r7, #4]
+ 8032650:	681b      	ldr	r3, [r3, #0]
+ 8032652:	4a1d      	ldr	r2, [pc, #116]	@ (80326c8 <HAL_ADC_ConfigChannel+0x69c>)
+ 8032654:	4293      	cmp	r3, r2
+ 8032656:	d127      	bne.n	80326a8 <HAL_ADC_ConfigChannel+0x67c>
+            {
+              LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel);
+ 8032658:	687b      	ldr	r3, [r7, #4]
+ 803265a:	681b      	ldr	r3, [r3, #0]
+ 803265c:	4a18      	ldr	r2, [pc, #96]	@ (80326c0 <HAL_ADC_ConfigChannel+0x694>)
+ 803265e:	4293      	cmp	r3, r2
+ 8032660:	d004      	beq.n	803266c <HAL_ADC_ConfigChannel+0x640>
+ 8032662:	687b      	ldr	r3, [r7, #4]
+ 8032664:	681b      	ldr	r3, [r3, #0]
+ 8032666:	4a17      	ldr	r2, [pc, #92]	@ (80326c4 <HAL_ADC_ConfigChannel+0x698>)
+ 8032668:	4293      	cmp	r3, r2
+ 803266a:	d101      	bne.n	8032670 <HAL_ADC_ConfigChannel+0x644>
+ 803266c:	4a18      	ldr	r2, [pc, #96]	@ (80326d0 <HAL_ADC_ConfigChannel+0x6a4>)
+ 803266e:	e000      	b.n	8032672 <HAL_ADC_ConfigChannel+0x646>
+ 8032670:	4a12      	ldr	r2, [pc, #72]	@ (80326bc <HAL_ADC_ConfigChannel+0x690>)
+ 8032672:	6efb      	ldr	r3, [r7, #108]	@ 0x6c
+ 8032674:	f443 0380 	orr.w	r3, r3, #4194304	@ 0x400000
+ 8032678:	4619      	mov	r1, r3
+ 803267a:	4610      	mov	r0, r2
+ 803267c:	f7ff f9bb 	bl	80319f6 <LL_ADC_SetCommonPathInternalCh>
+ 8032680:	e012      	b.n	80326a8 <HAL_ADC_ConfigChannel+0x67c>
+        /* enabled and other ADC of the common group are enabled, internal      */
+        /* measurement paths cannot be enabled.                                 */
+        else
+        {
+          /* Update ADC state machine to error */
+          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+ 8032682:	687b      	ldr	r3, [r7, #4]
+ 8032684:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
+ 8032686:	f043 0220 	orr.w	r2, r3, #32
+ 803268a:	687b      	ldr	r3, [r7, #4]
+ 803268c:	655a      	str	r2, [r3, #84]	@ 0x54
+
+          tmp_hal_status = HAL_ERROR;
+ 803268e:	2301      	movs	r3, #1
+ 8032690:	f887 307f 	strb.w	r3, [r7, #127]	@ 0x7f
+ 8032694:	e008      	b.n	80326a8 <HAL_ADC_ConfigChannel+0x67c>
+  /* channel could be done on neither of the channel configuration structure  */
+  /* parameters.                                                              */
+  else
+  {
+    /* Update ADC state machine to error */
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+ 8032696:	687b      	ldr	r3, [r7, #4]
+ 8032698:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
+ 803269a:	f043 0220 	orr.w	r2, r3, #32
+ 803269e:	687b      	ldr	r3, [r7, #4]
+ 80326a0:	655a      	str	r2, [r3, #84]	@ 0x54
+
+    tmp_hal_status = HAL_ERROR;
+ 80326a2:	2301      	movs	r3, #1
+ 80326a4:	f887 307f 	strb.w	r3, [r7, #127]	@ 0x7f
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+ 80326a8:	687b      	ldr	r3, [r7, #4]
+ 80326aa:	2200      	movs	r2, #0
+ 80326ac:	f883 2050 	strb.w	r2, [r3, #80]	@ 0x50
+
+  /* Return function status */
+  return tmp_hal_status;
+ 80326b0:	f897 307f 	ldrb.w	r3, [r7, #127]	@ 0x7f
+}
+ 80326b4:	4618      	mov	r0, r3
+ 80326b6:	3784      	adds	r7, #132	@ 0x84
+ 80326b8:	46bd      	mov	sp, r7
+ 80326ba:	bd90      	pop	{r4, r7, pc}
+ 80326bc:	58026300 	.word	0x58026300
+ 80326c0:	40022000 	.word	0x40022000
+ 80326c4:	40022100 	.word	0x40022100
+ 80326c8:	58026000 	.word	0x58026000
+ 80326cc:	cb840000 	.word	0xcb840000
+ 80326d0:	40022300 	.word	0x40022300
+ 80326d4:	2400012c 	.word	0x2400012c
+ 80326d8:	053e2d63 	.word	0x053e2d63
+ 80326dc:	c7520000 	.word	0xc7520000
+ 80326e0:	cfb80000 	.word	0xcfb80000
+
+080326e4 <ADC_ConfigureBoostMode>:
+  *         stopped.
+  * @param  hadc ADC handle
+  * @retval None.
+  */
+void ADC_ConfigureBoostMode(ADC_HandleTypeDef *hadc)
+{
+ 80326e4:	b580      	push	{r7, lr}
+ 80326e6:	b084      	sub	sp, #16
+ 80326e8:	af00      	add	r7, sp, #0
+ 80326ea:	6078      	str	r0, [r7, #4]
+  uint32_t freq;
+  if (ADC_IS_SYNCHRONOUS_CLOCK_MODE(hadc))
+ 80326ec:	687b      	ldr	r3, [r7, #4]
+ 80326ee:	681b      	ldr	r3, [r3, #0]
+ 80326f0:	4a7a      	ldr	r2, [pc, #488]	@ (80328dc <ADC_ConfigureBoostMode+0x1f8>)
+ 80326f2:	4293      	cmp	r3, r2
+ 80326f4:	d004      	beq.n	8032700 <ADC_ConfigureBoostMode+0x1c>
+ 80326f6:	687b      	ldr	r3, [r7, #4]
+ 80326f8:	681b      	ldr	r3, [r3, #0]
+ 80326fa:	4a79      	ldr	r2, [pc, #484]	@ (80328e0 <ADC_ConfigureBoostMode+0x1fc>)
+ 80326fc:	4293      	cmp	r3, r2
+ 80326fe:	d109      	bne.n	8032714 <ADC_ConfigureBoostMode+0x30>
+ 8032700:	4b78      	ldr	r3, [pc, #480]	@ (80328e4 <ADC_ConfigureBoostMode+0x200>)
+ 8032702:	689b      	ldr	r3, [r3, #8]
+ 8032704:	f403 3340 	and.w	r3, r3, #196608	@ 0x30000
+ 8032708:	2b00      	cmp	r3, #0
+ 803270a:	bf14      	ite	ne
+ 803270c:	2301      	movne	r3, #1
+ 803270e:	2300      	moveq	r3, #0
+ 8032710:	b2db      	uxtb	r3, r3
+ 8032712:	e008      	b.n	8032726 <ADC_ConfigureBoostMode+0x42>
+ 8032714:	4b74      	ldr	r3, [pc, #464]	@ (80328e8 <ADC_ConfigureBoostMode+0x204>)
+ 8032716:	689b      	ldr	r3, [r3, #8]
+ 8032718:	f403 3340 	and.w	r3, r3, #196608	@ 0x30000
+ 803271c:	2b00      	cmp	r3, #0
+ 803271e:	bf14      	ite	ne
+ 8032720:	2301      	movne	r3, #1
+ 8032722:	2300      	moveq	r3, #0
+ 8032724:	b2db      	uxtb	r3, r3
+ 8032726:	2b00      	cmp	r3, #0
+ 8032728:	d01c      	beq.n	8032764 <ADC_ConfigureBoostMode+0x80>
+  {
+    freq = HAL_RCC_GetHCLKFreq();
+ 803272a:	f007 fc33 	bl	8039f94 <HAL_RCC_GetHCLKFreq>
+ 803272e:	60f8      	str	r0, [r7, #12]
+    switch (hadc->Init.ClockPrescaler)
+ 8032730:	687b      	ldr	r3, [r7, #4]
+ 8032732:	685b      	ldr	r3, [r3, #4]
+ 8032734:	f5b3 3f40 	cmp.w	r3, #196608	@ 0x30000
+ 8032738:	d010      	beq.n	803275c <ADC_ConfigureBoostMode+0x78>
+ 803273a:	f5b3 3f40 	cmp.w	r3, #196608	@ 0x30000
+ 803273e:	d873      	bhi.n	8032828 <ADC_ConfigureBoostMode+0x144>
+ 8032740:	f5b3 3f80 	cmp.w	r3, #65536	@ 0x10000
+ 8032744:	d002      	beq.n	803274c <ADC_ConfigureBoostMode+0x68>
+ 8032746:	f5b3 3f00 	cmp.w	r3, #131072	@ 0x20000
+ 803274a:	d16d      	bne.n	8032828 <ADC_ConfigureBoostMode+0x144>
+    {
+      case ADC_CLOCK_SYNC_PCLK_DIV1:
+      case ADC_CLOCK_SYNC_PCLK_DIV2:
+        freq /= (hadc->Init.ClockPrescaler >> ADC_CCR_CKMODE_Pos);
+ 803274c:	687b      	ldr	r3, [r7, #4]
+ 803274e:	685b      	ldr	r3, [r3, #4]
+ 8032750:	0c1b      	lsrs	r3, r3, #16
+ 8032752:	68fa      	ldr	r2, [r7, #12]
+ 8032754:	fbb2 f3f3 	udiv	r3, r2, r3
+ 8032758:	60fb      	str	r3, [r7, #12]
+        break;
+ 803275a:	e068      	b.n	803282e <ADC_ConfigureBoostMode+0x14a>
+      case ADC_CLOCK_SYNC_PCLK_DIV4:
+        freq /= 4UL;
+ 803275c:	68fb      	ldr	r3, [r7, #12]
+ 803275e:	089b      	lsrs	r3, r3, #2
+ 8032760:	60fb      	str	r3, [r7, #12]
+        break;
+ 8032762:	e064      	b.n	803282e <ADC_ConfigureBoostMode+0x14a>
+        break;
+    }
+  }
+  else
+  {
+    freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC);
+ 8032764:	f44f 2000 	mov.w	r0, #524288	@ 0x80000
+ 8032768:	f04f 0100 	mov.w	r1, #0
+ 803276c:	f008 fe94 	bl	803b498 <HAL_RCCEx_GetPeriphCLKFreq>
+ 8032770:	60f8      	str	r0, [r7, #12]
+    switch (hadc->Init.ClockPrescaler)
+ 8032772:	687b      	ldr	r3, [r7, #4]
+ 8032774:	685b      	ldr	r3, [r3, #4]
+ 8032776:	f5b3 1f30 	cmp.w	r3, #2883584	@ 0x2c0000
+ 803277a:	d051      	beq.n	8032820 <ADC_ConfigureBoostMode+0x13c>
+ 803277c:	f5b3 1f30 	cmp.w	r3, #2883584	@ 0x2c0000
+ 8032780:	d854      	bhi.n	803282c <ADC_ConfigureBoostMode+0x148>
+ 8032782:	f5b3 1f20 	cmp.w	r3, #2621440	@ 0x280000
+ 8032786:	d047      	beq.n	8032818 <ADC_ConfigureBoostMode+0x134>
+ 8032788:	f5b3 1f20 	cmp.w	r3, #2621440	@ 0x280000
+ 803278c:	d84e      	bhi.n	803282c <ADC_ConfigureBoostMode+0x148>
+ 803278e:	f5b3 1f10 	cmp.w	r3, #2359296	@ 0x240000
+ 8032792:	d03d      	beq.n	8032810 <ADC_ConfigureBoostMode+0x12c>
+ 8032794:	f5b3 1f10 	cmp.w	r3, #2359296	@ 0x240000
+ 8032798:	d848      	bhi.n	803282c <ADC_ConfigureBoostMode+0x148>
+ 803279a:	f5b3 1f00 	cmp.w	r3, #2097152	@ 0x200000
+ 803279e:	d033      	beq.n	8032808 <ADC_ConfigureBoostMode+0x124>
+ 80327a0:	f5b3 1f00 	cmp.w	r3, #2097152	@ 0x200000
+ 80327a4:	d842      	bhi.n	803282c <ADC_ConfigureBoostMode+0x148>
+ 80327a6:	f5b3 1fe0 	cmp.w	r3, #1835008	@ 0x1c0000
+ 80327aa:	d029      	beq.n	8032800 <ADC_ConfigureBoostMode+0x11c>
+ 80327ac:	f5b3 1fe0 	cmp.w	r3, #1835008	@ 0x1c0000
+ 80327b0:	d83c      	bhi.n	803282c <ADC_ConfigureBoostMode+0x148>
+ 80327b2:	f5b3 1fc0 	cmp.w	r3, #1572864	@ 0x180000
+ 80327b6:	d01a      	beq.n	80327ee <ADC_ConfigureBoostMode+0x10a>
+ 80327b8:	f5b3 1fc0 	cmp.w	r3, #1572864	@ 0x180000
+ 80327bc:	d836      	bhi.n	803282c <ADC_ConfigureBoostMode+0x148>
+ 80327be:	f5b3 1fa0 	cmp.w	r3, #1310720	@ 0x140000
+ 80327c2:	d014      	beq.n	80327ee <ADC_ConfigureBoostMode+0x10a>
+ 80327c4:	f5b3 1fa0 	cmp.w	r3, #1310720	@ 0x140000
+ 80327c8:	d830      	bhi.n	803282c <ADC_ConfigureBoostMode+0x148>
+ 80327ca:	f5b3 1f80 	cmp.w	r3, #1048576	@ 0x100000
+ 80327ce:	d00e      	beq.n	80327ee <ADC_ConfigureBoostMode+0x10a>
+ 80327d0:	f5b3 1f80 	cmp.w	r3, #1048576	@ 0x100000
+ 80327d4:	d82a      	bhi.n	803282c <ADC_ConfigureBoostMode+0x148>
+ 80327d6:	f5b3 2f40 	cmp.w	r3, #786432	@ 0xc0000
+ 80327da:	d008      	beq.n	80327ee <ADC_ConfigureBoostMode+0x10a>
+ 80327dc:	f5b3 2f40 	cmp.w	r3, #786432	@ 0xc0000
+ 80327e0:	d824      	bhi.n	803282c <ADC_ConfigureBoostMode+0x148>
+ 80327e2:	f5b3 2f80 	cmp.w	r3, #262144	@ 0x40000
+ 80327e6:	d002      	beq.n	80327ee <ADC_ConfigureBoostMode+0x10a>
+ 80327e8:	f5b3 2f00 	cmp.w	r3, #524288	@ 0x80000
+ 80327ec:	d11e      	bne.n	803282c <ADC_ConfigureBoostMode+0x148>
+      case ADC_CLOCK_ASYNC_DIV4:
+      case ADC_CLOCK_ASYNC_DIV6:
+      case ADC_CLOCK_ASYNC_DIV8:
+      case ADC_CLOCK_ASYNC_DIV10:
+      case ADC_CLOCK_ASYNC_DIV12:
+        freq /= ((hadc->Init.ClockPrescaler >> ADC_CCR_PRESC_Pos) << 1UL);
+ 80327ee:	687b      	ldr	r3, [r7, #4]
+ 80327f0:	685b      	ldr	r3, [r3, #4]
+ 80327f2:	0c9b      	lsrs	r3, r3, #18
+ 80327f4:	005b      	lsls	r3, r3, #1
+ 80327f6:	68fa      	ldr	r2, [r7, #12]
+ 80327f8:	fbb2 f3f3 	udiv	r3, r2, r3
+ 80327fc:	60fb      	str	r3, [r7, #12]
+        break;
+ 80327fe:	e016      	b.n	803282e <ADC_ConfigureBoostMode+0x14a>
+      case ADC_CLOCK_ASYNC_DIV16:
+        freq /= 16UL;
+ 8032800:	68fb      	ldr	r3, [r7, #12]
+ 8032802:	091b      	lsrs	r3, r3, #4
+ 8032804:	60fb      	str	r3, [r7, #12]
+        break;
+ 8032806:	e012      	b.n	803282e <ADC_ConfigureBoostMode+0x14a>
+      case ADC_CLOCK_ASYNC_DIV32:
+        freq /= 32UL;
+ 8032808:	68fb      	ldr	r3, [r7, #12]
+ 803280a:	095b      	lsrs	r3, r3, #5
+ 803280c:	60fb      	str	r3, [r7, #12]
+        break;
+ 803280e:	e00e      	b.n	803282e <ADC_ConfigureBoostMode+0x14a>
+      case ADC_CLOCK_ASYNC_DIV64:
+        freq /= 64UL;
+ 8032810:	68fb      	ldr	r3, [r7, #12]
+ 8032812:	099b      	lsrs	r3, r3, #6
+ 8032814:	60fb      	str	r3, [r7, #12]
+        break;
+ 8032816:	e00a      	b.n	803282e <ADC_ConfigureBoostMode+0x14a>
+      case ADC_CLOCK_ASYNC_DIV128:
+        freq /= 128UL;
+ 8032818:	68fb      	ldr	r3, [r7, #12]
+ 803281a:	09db      	lsrs	r3, r3, #7
+ 803281c:	60fb      	str	r3, [r7, #12]
+        break;
+ 803281e:	e006      	b.n	803282e <ADC_ConfigureBoostMode+0x14a>
+      case ADC_CLOCK_ASYNC_DIV256:
+        freq /= 256UL;
+ 8032820:	68fb      	ldr	r3, [r7, #12]
+ 8032822:	0a1b      	lsrs	r3, r3, #8
+ 8032824:	60fb      	str	r3, [r7, #12]
+        break;
+ 8032826:	e002      	b.n	803282e <ADC_ConfigureBoostMode+0x14a>
+        break;
+ 8032828:	bf00      	nop
+ 803282a:	e000      	b.n	803282e <ADC_ConfigureBoostMode+0x14a>
+      default:
+        break;
+ 803282c:	bf00      	nop
+  else /* if(freq > 25000000UL) */
+  {
+    MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1 | ADC_CR_BOOST_0);
+  }
+#else
+  if (HAL_GetREVID() <= REV_ID_Y) /* STM32H7 silicon Rev.Y */
+ 803282e:	f7ff f8af 	bl	8031990 <HAL_GetREVID>
+ 8032832:	4603      	mov	r3, r0
+ 8032834:	f241 0203 	movw	r2, #4099	@ 0x1003
+ 8032838:	4293      	cmp	r3, r2
+ 803283a:	d815      	bhi.n	8032868 <ADC_ConfigureBoostMode+0x184>
+  {
+    if (freq > 20000000UL)
+ 803283c:	68fb      	ldr	r3, [r7, #12]
+ 803283e:	4a2b      	ldr	r2, [pc, #172]	@ (80328ec <ADC_ConfigureBoostMode+0x208>)
+ 8032840:	4293      	cmp	r3, r2
+ 8032842:	d908      	bls.n	8032856 <ADC_ConfigureBoostMode+0x172>
+    {
+      SET_BIT(hadc->Instance->CR, ADC_CR_BOOST_0);
+ 8032844:	687b      	ldr	r3, [r7, #4]
+ 8032846:	681b      	ldr	r3, [r3, #0]
+ 8032848:	689a      	ldr	r2, [r3, #8]
+ 803284a:	687b      	ldr	r3, [r7, #4]
+ 803284c:	681b      	ldr	r3, [r3, #0]
+ 803284e:	f442 7280 	orr.w	r2, r2, #256	@ 0x100
+ 8032852:	609a      	str	r2, [r3, #8]
+    {
+      MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1 | ADC_CR_BOOST_0);
+    }
+  }
+#endif /* ADC_VER_V5_3 */
+}
+ 8032854:	e03e      	b.n	80328d4 <ADC_ConfigureBoostMode+0x1f0>
+      CLEAR_BIT(hadc->Instance->CR, ADC_CR_BOOST_0);
+ 8032856:	687b      	ldr	r3, [r7, #4]
+ 8032858:	681b      	ldr	r3, [r3, #0]
+ 803285a:	689a      	ldr	r2, [r3, #8]
+ 803285c:	687b      	ldr	r3, [r7, #4]
+ 803285e:	681b      	ldr	r3, [r3, #0]
+ 8032860:	f422 7280 	bic.w	r2, r2, #256	@ 0x100
+ 8032864:	609a      	str	r2, [r3, #8]
+}
+ 8032866:	e035      	b.n	80328d4 <ADC_ConfigureBoostMode+0x1f0>
+    freq /= 2U; /* divider by 2 for Rev.V */
+ 8032868:	68fb      	ldr	r3, [r7, #12]
+ 803286a:	085b      	lsrs	r3, r3, #1
+ 803286c:	60fb      	str	r3, [r7, #12]
+    if (freq <= 6250000UL)
+ 803286e:	68fb      	ldr	r3, [r7, #12]
+ 8032870:	4a1f      	ldr	r2, [pc, #124]	@ (80328f0 <ADC_ConfigureBoostMode+0x20c>)
+ 8032872:	4293      	cmp	r3, r2
+ 8032874:	d808      	bhi.n	8032888 <ADC_ConfigureBoostMode+0x1a4>
+      MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, 0UL);
+ 8032876:	687b      	ldr	r3, [r7, #4]
+ 8032878:	681b      	ldr	r3, [r3, #0]
+ 803287a:	689a      	ldr	r2, [r3, #8]
+ 803287c:	687b      	ldr	r3, [r7, #4]
+ 803287e:	681b      	ldr	r3, [r3, #0]
+ 8032880:	f422 7240 	bic.w	r2, r2, #768	@ 0x300
+ 8032884:	609a      	str	r2, [r3, #8]
+}
+ 8032886:	e025      	b.n	80328d4 <ADC_ConfigureBoostMode+0x1f0>
+    else if (freq <= 12500000UL)
+ 8032888:	68fb      	ldr	r3, [r7, #12]
+ 803288a:	4a1a      	ldr	r2, [pc, #104]	@ (80328f4 <ADC_ConfigureBoostMode+0x210>)
+ 803288c:	4293      	cmp	r3, r2
+ 803288e:	d80a      	bhi.n	80328a6 <ADC_ConfigureBoostMode+0x1c2>
+      MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_0);
+ 8032890:	687b      	ldr	r3, [r7, #4]
+ 8032892:	681b      	ldr	r3, [r3, #0]
+ 8032894:	689b      	ldr	r3, [r3, #8]
+ 8032896:	f423 7240 	bic.w	r2, r3, #768	@ 0x300
+ 803289a:	687b      	ldr	r3, [r7, #4]
+ 803289c:	681b      	ldr	r3, [r3, #0]
+ 803289e:	f442 7280 	orr.w	r2, r2, #256	@ 0x100
+ 80328a2:	609a      	str	r2, [r3, #8]
+}
+ 80328a4:	e016      	b.n	80328d4 <ADC_ConfigureBoostMode+0x1f0>
+    else if (freq <= 25000000UL)
+ 80328a6:	68fb      	ldr	r3, [r7, #12]
+ 80328a8:	4a13      	ldr	r2, [pc, #76]	@ (80328f8 <ADC_ConfigureBoostMode+0x214>)
+ 80328aa:	4293      	cmp	r3, r2
+ 80328ac:	d80a      	bhi.n	80328c4 <ADC_ConfigureBoostMode+0x1e0>
+      MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1);
+ 80328ae:	687b      	ldr	r3, [r7, #4]
+ 80328b0:	681b      	ldr	r3, [r3, #0]
+ 80328b2:	689b      	ldr	r3, [r3, #8]
+ 80328b4:	f423 7240 	bic.w	r2, r3, #768	@ 0x300
+ 80328b8:	687b      	ldr	r3, [r7, #4]
+ 80328ba:	681b      	ldr	r3, [r3, #0]
+ 80328bc:	f442 7200 	orr.w	r2, r2, #512	@ 0x200
+ 80328c0:	609a      	str	r2, [r3, #8]
+}
+ 80328c2:	e007      	b.n	80328d4 <ADC_ConfigureBoostMode+0x1f0>
+      MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1 | ADC_CR_BOOST_0);
+ 80328c4:	687b      	ldr	r3, [r7, #4]
+ 80328c6:	681b      	ldr	r3, [r3, #0]
+ 80328c8:	689a      	ldr	r2, [r3, #8]
+ 80328ca:	687b      	ldr	r3, [r7, #4]
+ 80328cc:	681b      	ldr	r3, [r3, #0]
+ 80328ce:	f442 7240 	orr.w	r2, r2, #768	@ 0x300
+ 80328d2:	609a      	str	r2, [r3, #8]
+}
+ 80328d4:	bf00      	nop
+ 80328d6:	3710      	adds	r7, #16
+ 80328d8:	46bd      	mov	sp, r7
+ 80328da:	bd80      	pop	{r7, pc}
+ 80328dc:	40022000 	.word	0x40022000
+ 80328e0:	40022100 	.word	0x40022100
+ 80328e4:	40022300 	.word	0x40022300
+ 80328e8:	58026300 	.word	0x58026300
+ 80328ec:	01312d00 	.word	0x01312d00
+ 80328f0:	005f5e10 	.word	0x005f5e10
+ 80328f4:	00bebc20 	.word	0x00bebc20
+ 80328f8:	017d7840 	.word	0x017d7840
+
+080328fc <__NVIC_SetPriorityGrouping>:
+{
+ 80328fc:	b480      	push	{r7}
+ 80328fe:	b085      	sub	sp, #20
+ 8032900:	af00      	add	r7, sp, #0
+ 8032902:	6078      	str	r0, [r7, #4]
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+ 8032904:	687b      	ldr	r3, [r7, #4]
+ 8032906:	f003 0307 	and.w	r3, r3, #7
+ 803290a:	60fb      	str	r3, [r7, #12]
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+ 803290c:	4b0b      	ldr	r3, [pc, #44]	@ (803293c <__NVIC_SetPriorityGrouping+0x40>)
+ 803290e:	68db      	ldr	r3, [r3, #12]
+ 8032910:	60bb      	str	r3, [r7, #8]
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+ 8032912:	68ba      	ldr	r2, [r7, #8]
+ 8032914:	f64f 03ff 	movw	r3, #63743	@ 0xf8ff
+ 8032918:	4013      	ands	r3, r2
+ 803291a:	60bb      	str	r3, [r7, #8]
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
+ 803291c:	68fb      	ldr	r3, [r7, #12]
+ 803291e:	021a      	lsls	r2, r3, #8
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ 8032920:	68bb      	ldr	r3, [r7, #8]
+ 8032922:	431a      	orrs	r2, r3
+  reg_value  =  (reg_value                                   |
+ 8032924:	4b06      	ldr	r3, [pc, #24]	@ (8032940 <__NVIC_SetPriorityGrouping+0x44>)
+ 8032926:	4313      	orrs	r3, r2
+ 8032928:	60bb      	str	r3, [r7, #8]
+  SCB->AIRCR =  reg_value;
+ 803292a:	4a04      	ldr	r2, [pc, #16]	@ (803293c <__NVIC_SetPriorityGrouping+0x40>)
+ 803292c:	68bb      	ldr	r3, [r7, #8]
+ 803292e:	60d3      	str	r3, [r2, #12]
+}
+ 8032930:	bf00      	nop
+ 8032932:	3714      	adds	r7, #20
+ 8032934:	46bd      	mov	sp, r7
+ 8032936:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 803293a:	4770      	bx	lr
+ 803293c:	e000ed00 	.word	0xe000ed00
+ 8032940:	05fa0000 	.word	0x05fa0000
+
+08032944 <__NVIC_GetPriorityGrouping>:
+{
+ 8032944:	b480      	push	{r7}
+ 8032946:	af00      	add	r7, sp, #0
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+ 8032948:	4b04      	ldr	r3, [pc, #16]	@ (803295c <__NVIC_GetPriorityGrouping+0x18>)
+ 803294a:	68db      	ldr	r3, [r3, #12]
+ 803294c:	0a1b      	lsrs	r3, r3, #8
+ 803294e:	f003 0307 	and.w	r3, r3, #7
+}
+ 8032952:	4618      	mov	r0, r3
+ 8032954:	46bd      	mov	sp, r7
+ 8032956:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 803295a:	4770      	bx	lr
+ 803295c:	e000ed00 	.word	0xe000ed00
+
+08032960 <__NVIC_EnableIRQ>:
+{
+ 8032960:	b480      	push	{r7}
+ 8032962:	b083      	sub	sp, #12
+ 8032964:	af00      	add	r7, sp, #0
+ 8032966:	4603      	mov	r3, r0
+ 8032968:	80fb      	strh	r3, [r7, #6]
+  if ((int32_t)(IRQn) >= 0)
+ 803296a:	f9b7 3006 	ldrsh.w	r3, [r7, #6]
+ 803296e:	2b00      	cmp	r3, #0
+ 8032970:	db0b      	blt.n	803298a <__NVIC_EnableIRQ+0x2a>
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ 8032972:	88fb      	ldrh	r3, [r7, #6]
+ 8032974:	f003 021f 	and.w	r2, r3, #31
+ 8032978:	4907      	ldr	r1, [pc, #28]	@ (8032998 <__NVIC_EnableIRQ+0x38>)
+ 803297a:	f9b7 3006 	ldrsh.w	r3, [r7, #6]
+ 803297e:	095b      	lsrs	r3, r3, #5
+ 8032980:	2001      	movs	r0, #1
+ 8032982:	fa00 f202 	lsl.w	r2, r0, r2
+ 8032986:	f841 2023 	str.w	r2, [r1, r3, lsl #2]
+}
+ 803298a:	bf00      	nop
+ 803298c:	370c      	adds	r7, #12
+ 803298e:	46bd      	mov	sp, r7
+ 8032990:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8032994:	4770      	bx	lr
+ 8032996:	bf00      	nop
+ 8032998:	e000e100 	.word	0xe000e100
+
+0803299c <__NVIC_SetPriority>:
+{
+ 803299c:	b480      	push	{r7}
+ 803299e:	b083      	sub	sp, #12
+ 80329a0:	af00      	add	r7, sp, #0
+ 80329a2:	4603      	mov	r3, r0
+ 80329a4:	6039      	str	r1, [r7, #0]
+ 80329a6:	80fb      	strh	r3, [r7, #6]
+  if ((int32_t)(IRQn) >= 0)
+ 80329a8:	f9b7 3006 	ldrsh.w	r3, [r7, #6]
+ 80329ac:	2b00      	cmp	r3, #0
+ 80329ae:	db0a      	blt.n	80329c6 <__NVIC_SetPriority+0x2a>
+    NVIC->IP[((uint32_t)IRQn)]                = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ 80329b0:	683b      	ldr	r3, [r7, #0]
+ 80329b2:	b2da      	uxtb	r2, r3
+ 80329b4:	490c      	ldr	r1, [pc, #48]	@ (80329e8 <__NVIC_SetPriority+0x4c>)
+ 80329b6:	f9b7 3006 	ldrsh.w	r3, [r7, #6]
+ 80329ba:	0112      	lsls	r2, r2, #4
+ 80329bc:	b2d2      	uxtb	r2, r2
+ 80329be:	440b      	add	r3, r1
+ 80329c0:	f883 2300 	strb.w	r2, [r3, #768]	@ 0x300
+}
+ 80329c4:	e00a      	b.n	80329dc <__NVIC_SetPriority+0x40>
+    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ 80329c6:	683b      	ldr	r3, [r7, #0]
+ 80329c8:	b2da      	uxtb	r2, r3
+ 80329ca:	4908      	ldr	r1, [pc, #32]	@ (80329ec <__NVIC_SetPriority+0x50>)
+ 80329cc:	88fb      	ldrh	r3, [r7, #6]
+ 80329ce:	f003 030f 	and.w	r3, r3, #15
+ 80329d2:	3b04      	subs	r3, #4
+ 80329d4:	0112      	lsls	r2, r2, #4
+ 80329d6:	b2d2      	uxtb	r2, r2
+ 80329d8:	440b      	add	r3, r1
+ 80329da:	761a      	strb	r2, [r3, #24]
+}
+ 80329dc:	bf00      	nop
+ 80329de:	370c      	adds	r7, #12
+ 80329e0:	46bd      	mov	sp, r7
+ 80329e2:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80329e6:	4770      	bx	lr
+ 80329e8:	e000e100 	.word	0xe000e100
+ 80329ec:	e000ed00 	.word	0xe000ed00
+
+080329f0 <NVIC_EncodePriority>:
+{
+ 80329f0:	b480      	push	{r7}
+ 80329f2:	b089      	sub	sp, #36	@ 0x24
+ 80329f4:	af00      	add	r7, sp, #0
+ 80329f6:	60f8      	str	r0, [r7, #12]
+ 80329f8:	60b9      	str	r1, [r7, #8]
+ 80329fa:	607a      	str	r2, [r7, #4]
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+ 80329fc:	68fb      	ldr	r3, [r7, #12]
+ 80329fe:	f003 0307 	and.w	r3, r3, #7
+ 8032a02:	61fb      	str	r3, [r7, #28]
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ 8032a04:	69fb      	ldr	r3, [r7, #28]
+ 8032a06:	f1c3 0307 	rsb	r3, r3, #7
+ 8032a0a:	2b04      	cmp	r3, #4
+ 8032a0c:	bf28      	it	cs
+ 8032a0e:	2304      	movcs	r3, #4
+ 8032a10:	61bb      	str	r3, [r7, #24]
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+ 8032a12:	69fb      	ldr	r3, [r7, #28]
+ 8032a14:	3304      	adds	r3, #4
+ 8032a16:	2b06      	cmp	r3, #6
+ 8032a18:	d902      	bls.n	8032a20 <NVIC_EncodePriority+0x30>
+ 8032a1a:	69fb      	ldr	r3, [r7, #28]
+ 8032a1c:	3b03      	subs	r3, #3
+ 8032a1e:	e000      	b.n	8032a22 <NVIC_EncodePriority+0x32>
+ 8032a20:	2300      	movs	r3, #0
+ 8032a22:	617b      	str	r3, [r7, #20]
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ 8032a24:	f04f 32ff 	mov.w	r2, #4294967295
+ 8032a28:	69bb      	ldr	r3, [r7, #24]
+ 8032a2a:	fa02 f303 	lsl.w	r3, r2, r3
+ 8032a2e:	43da      	mvns	r2, r3
+ 8032a30:	68bb      	ldr	r3, [r7, #8]
+ 8032a32:	401a      	ands	r2, r3
+ 8032a34:	697b      	ldr	r3, [r7, #20]
+ 8032a36:	409a      	lsls	r2, r3
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+ 8032a38:	f04f 31ff 	mov.w	r1, #4294967295
+ 8032a3c:	697b      	ldr	r3, [r7, #20]
+ 8032a3e:	fa01 f303 	lsl.w	r3, r1, r3
+ 8032a42:	43d9      	mvns	r1, r3
+ 8032a44:	687b      	ldr	r3, [r7, #4]
+ 8032a46:	400b      	ands	r3, r1
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ 8032a48:	4313      	orrs	r3, r2
+}
+ 8032a4a:	4618      	mov	r0, r3
+ 8032a4c:	3724      	adds	r7, #36	@ 0x24
+ 8032a4e:	46bd      	mov	sp, r7
+ 8032a50:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8032a54:	4770      	bx	lr
+	...
+
+08032a58 <SysTick_Config>:
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ 8032a58:	b580      	push	{r7, lr}
+ 8032a5a:	b082      	sub	sp, #8
+ 8032a5c:	af00      	add	r7, sp, #0
+ 8032a5e:	6078      	str	r0, [r7, #4]
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ 8032a60:	687b      	ldr	r3, [r7, #4]
+ 8032a62:	3b01      	subs	r3, #1
+ 8032a64:	f1b3 7f80 	cmp.w	r3, #16777216	@ 0x1000000
+ 8032a68:	d301      	bcc.n	8032a6e <SysTick_Config+0x16>
+  {
+    return (1UL);                                                   /* Reload value impossible */
+ 8032a6a:	2301      	movs	r3, #1
+ 8032a6c:	e00f      	b.n	8032a8e <SysTick_Config+0x36>
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+ 8032a6e:	4a0a      	ldr	r2, [pc, #40]	@ (8032a98 <SysTick_Config+0x40>)
+ 8032a70:	687b      	ldr	r3, [r7, #4]
+ 8032a72:	3b01      	subs	r3, #1
+ 8032a74:	6053      	str	r3, [r2, #4]
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ 8032a76:	210f      	movs	r1, #15
+ 8032a78:	f04f 30ff 	mov.w	r0, #4294967295
+ 8032a7c:	f7ff ff8e 	bl	803299c <__NVIC_SetPriority>
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+ 8032a80:	4b05      	ldr	r3, [pc, #20]	@ (8032a98 <SysTick_Config+0x40>)
+ 8032a82:	2200      	movs	r2, #0
+ 8032a84:	609a      	str	r2, [r3, #8]
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+ 8032a86:	4b04      	ldr	r3, [pc, #16]	@ (8032a98 <SysTick_Config+0x40>)
+ 8032a88:	2207      	movs	r2, #7
+ 8032a8a:	601a      	str	r2, [r3, #0]
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+ 8032a8c:	2300      	movs	r3, #0
+}
+ 8032a8e:	4618      	mov	r0, r3
+ 8032a90:	3708      	adds	r7, #8
+ 8032a92:	46bd      	mov	sp, r7
+ 8032a94:	bd80      	pop	{r7, pc}
+ 8032a96:	bf00      	nop
+ 8032a98:	e000e010 	.word	0xe000e010
+
+08032a9c <HAL_NVIC_SetPriorityGrouping>:
+  * @note   When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
+  *         The pending IRQ priority will be managed only by the subpriority.
+  * @retval None
+  */
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ 8032a9c:	b580      	push	{r7, lr}
+ 8032a9e:	b082      	sub	sp, #8
+ 8032aa0:	af00      	add	r7, sp, #0
+ 8032aa2:	6078      	str	r0, [r7, #4]
+  /* Check the parameters */
+  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
+
+  /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
+  NVIC_SetPriorityGrouping(PriorityGroup);
+ 8032aa4:	6878      	ldr	r0, [r7, #4]
+ 8032aa6:	f7ff ff29 	bl	80328fc <__NVIC_SetPriorityGrouping>
+}
+ 8032aaa:	bf00      	nop
+ 8032aac:	3708      	adds	r7, #8
+ 8032aae:	46bd      	mov	sp, r7
+ 8032ab0:	bd80      	pop	{r7, pc}
+
+08032ab2 <HAL_NVIC_SetPriority>:
+  *         This parameter can be a value between 0 and 15
+  *         A lower priority value indicates a higher priority.
+  * @retval None
+  */
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ 8032ab2:	b580      	push	{r7, lr}
+ 8032ab4:	b086      	sub	sp, #24
+ 8032ab6:	af00      	add	r7, sp, #0
+ 8032ab8:	4603      	mov	r3, r0
+ 8032aba:	60b9      	str	r1, [r7, #8]
+ 8032abc:	607a      	str	r2, [r7, #4]
+ 8032abe:	81fb      	strh	r3, [r7, #14]
+
+  /* Check the parameters */
+  assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
+  assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
+
+  prioritygroup = NVIC_GetPriorityGrouping();
+ 8032ac0:	f7ff ff40 	bl	8032944 <__NVIC_GetPriorityGrouping>
+ 8032ac4:	6178      	str	r0, [r7, #20]
+
+  NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
+ 8032ac6:	687a      	ldr	r2, [r7, #4]
+ 8032ac8:	68b9      	ldr	r1, [r7, #8]
+ 8032aca:	6978      	ldr	r0, [r7, #20]
+ 8032acc:	f7ff ff90 	bl	80329f0 <NVIC_EncodePriority>
+ 8032ad0:	4602      	mov	r2, r0
+ 8032ad2:	f9b7 300e 	ldrsh.w	r3, [r7, #14]
+ 8032ad6:	4611      	mov	r1, r2
+ 8032ad8:	4618      	mov	r0, r3
+ 8032ada:	f7ff ff5f 	bl	803299c <__NVIC_SetPriority>
+}
+ 8032ade:	bf00      	nop
+ 8032ae0:	3718      	adds	r7, #24
+ 8032ae2:	46bd      	mov	sp, r7
+ 8032ae4:	bd80      	pop	{r7, pc}
+
+08032ae6 <HAL_NVIC_EnableIRQ>:
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
+  * @retval None
+  */
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ 8032ae6:	b580      	push	{r7, lr}
+ 8032ae8:	b082      	sub	sp, #8
+ 8032aea:	af00      	add	r7, sp, #0
+ 8032aec:	4603      	mov	r3, r0
+ 8032aee:	80fb      	strh	r3, [r7, #6]
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
+  /* Enable interrupt */
+  NVIC_EnableIRQ(IRQn);
+ 8032af0:	f9b7 3006 	ldrsh.w	r3, [r7, #6]
+ 8032af4:	4618      	mov	r0, r3
+ 8032af6:	f7ff ff33 	bl	8032960 <__NVIC_EnableIRQ>
+}
+ 8032afa:	bf00      	nop
+ 8032afc:	3708      	adds	r7, #8
+ 8032afe:	46bd      	mov	sp, r7
+ 8032b00:	bd80      	pop	{r7, pc}
+
+08032b02 <HAL_SYSTICK_Config>:
+  * @param  TicksNumb Specifies the ticks Number of ticks between two interrupts.
+  * @retval status   - 0  Function succeeded.
+  *                  - 1  Function failed.
+  */
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
+{
+ 8032b02:	b580      	push	{r7, lr}
+ 8032b04:	b082      	sub	sp, #8
+ 8032b06:	af00      	add	r7, sp, #0
+ 8032b08:	6078      	str	r0, [r7, #4]
+   return SysTick_Config(TicksNumb);
+ 8032b0a:	6878      	ldr	r0, [r7, #4]
+ 8032b0c:	f7ff ffa4 	bl	8032a58 <SysTick_Config>
+ 8032b10:	4603      	mov	r3, r0
+}
+ 8032b12:	4618      	mov	r0, r3
+ 8032b14:	3708      	adds	r7, #8
+ 8032b16:	46bd      	mov	sp, r7
+ 8032b18:	bd80      	pop	{r7, pc}
+	...
+
+08032b1c <HAL_MPU_Disable>:
+/**
+  * @brief  Disables the MPU
+  * @retval None
+  */
+void HAL_MPU_Disable(void)
+{
+ 8032b1c:	b480      	push	{r7}
+ 8032b1e:	af00      	add	r7, sp, #0
+  __ASM volatile ("dmb 0xF":::"memory");
+ 8032b20:	f3bf 8f5f 	dmb	sy
+}
+ 8032b24:	bf00      	nop
+  /* Make sure outstanding transfers are done */
+  __DMB();
+
+  /* Disable fault exceptions */
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+ 8032b26:	4b07      	ldr	r3, [pc, #28]	@ (8032b44 <HAL_MPU_Disable+0x28>)
+ 8032b28:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 8032b2a:	4a06      	ldr	r2, [pc, #24]	@ (8032b44 <HAL_MPU_Disable+0x28>)
+ 8032b2c:	f423 3380 	bic.w	r3, r3, #65536	@ 0x10000
+ 8032b30:	6253      	str	r3, [r2, #36]	@ 0x24
+
+  /* Disable the MPU and clear the control register*/
+  MPU->CTRL = 0;
+ 8032b32:	4b05      	ldr	r3, [pc, #20]	@ (8032b48 <HAL_MPU_Disable+0x2c>)
+ 8032b34:	2200      	movs	r2, #0
+ 8032b36:	605a      	str	r2, [r3, #4]
+}
+ 8032b38:	bf00      	nop
+ 8032b3a:	46bd      	mov	sp, r7
+ 8032b3c:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8032b40:	4770      	bx	lr
+ 8032b42:	bf00      	nop
+ 8032b44:	e000ed00 	.word	0xe000ed00
+ 8032b48:	e000ed90 	.word	0xe000ed90
+
+08032b4c <HAL_MPU_Enable>:
+  *            @arg MPU_PRIVILEGED_DEFAULT
+  *            @arg MPU_HFNMI_PRIVDEF
+  * @retval None
+  */
+void HAL_MPU_Enable(uint32_t MPU_Control)
+{
+ 8032b4c:	b480      	push	{r7}
+ 8032b4e:	b083      	sub	sp, #12
+ 8032b50:	af00      	add	r7, sp, #0
+ 8032b52:	6078      	str	r0, [r7, #4]
+  /* Enable the MPU */
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+ 8032b54:	4a0b      	ldr	r2, [pc, #44]	@ (8032b84 <HAL_MPU_Enable+0x38>)
+ 8032b56:	687b      	ldr	r3, [r7, #4]
+ 8032b58:	f043 0301 	orr.w	r3, r3, #1
+ 8032b5c:	6053      	str	r3, [r2, #4]
+
+  /* Enable fault exceptions */
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+ 8032b5e:	4b0a      	ldr	r3, [pc, #40]	@ (8032b88 <HAL_MPU_Enable+0x3c>)
+ 8032b60:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 8032b62:	4a09      	ldr	r2, [pc, #36]	@ (8032b88 <HAL_MPU_Enable+0x3c>)
+ 8032b64:	f443 3380 	orr.w	r3, r3, #65536	@ 0x10000
+ 8032b68:	6253      	str	r3, [r2, #36]	@ 0x24
+  __ASM volatile ("dsb 0xF":::"memory");
+ 8032b6a:	f3bf 8f4f 	dsb	sy
+}
+ 8032b6e:	bf00      	nop
+  __ASM volatile ("isb 0xF":::"memory");
+ 8032b70:	f3bf 8f6f 	isb	sy
+}
+ 8032b74:	bf00      	nop
+
+  /* Ensure MPU setting take effects */
+  __DSB();
+  __ISB();
+}
+ 8032b76:	bf00      	nop
+ 8032b78:	370c      	adds	r7, #12
+ 8032b7a:	46bd      	mov	sp, r7
+ 8032b7c:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8032b80:	4770      	bx	lr
+ 8032b82:	bf00      	nop
+ 8032b84:	e000ed90 	.word	0xe000ed90
+ 8032b88:	e000ed00 	.word	0xe000ed00
+
+08032b8c <HAL_MPU_ConfigRegion>:
+  * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
+  *                the initialization and configuration information.
+  * @retval None
+  */
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
+{
+ 8032b8c:	b480      	push	{r7}
+ 8032b8e:	b083      	sub	sp, #12
+ 8032b90:	af00      	add	r7, sp, #0
+ 8032b92:	6078      	str	r0, [r7, #4]
+  assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
+  assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
+  assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
+
+  /* Set the Region number */
+  MPU->RNR = MPU_Init->Number;
+ 8032b94:	687b      	ldr	r3, [r7, #4]
+ 8032b96:	785a      	ldrb	r2, [r3, #1]
+ 8032b98:	4b1b      	ldr	r3, [pc, #108]	@ (8032c08 <HAL_MPU_ConfigRegion+0x7c>)
+ 8032b9a:	609a      	str	r2, [r3, #8]
+
+  /* Disable the Region */
+  CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+ 8032b9c:	4b1a      	ldr	r3, [pc, #104]	@ (8032c08 <HAL_MPU_ConfigRegion+0x7c>)
+ 8032b9e:	691b      	ldr	r3, [r3, #16]
+ 8032ba0:	4a19      	ldr	r2, [pc, #100]	@ (8032c08 <HAL_MPU_ConfigRegion+0x7c>)
+ 8032ba2:	f023 0301 	bic.w	r3, r3, #1
+ 8032ba6:	6113      	str	r3, [r2, #16]
+
+  /* Apply configuration */
+  MPU->RBAR = MPU_Init->BaseAddress;
+ 8032ba8:	4a17      	ldr	r2, [pc, #92]	@ (8032c08 <HAL_MPU_ConfigRegion+0x7c>)
+ 8032baa:	687b      	ldr	r3, [r7, #4]
+ 8032bac:	685b      	ldr	r3, [r3, #4]
+ 8032bae:	60d3      	str	r3, [r2, #12]
+  MPU->RASR = ((uint32_t)MPU_Init->DisableExec             << MPU_RASR_XN_Pos)   |
+ 8032bb0:	687b      	ldr	r3, [r7, #4]
+ 8032bb2:	7b1b      	ldrb	r3, [r3, #12]
+ 8032bb4:	071a      	lsls	r2, r3, #28
+              ((uint32_t)MPU_Init->AccessPermission        << MPU_RASR_AP_Pos)   |
+ 8032bb6:	687b      	ldr	r3, [r7, #4]
+ 8032bb8:	7adb      	ldrb	r3, [r3, #11]
+ 8032bba:	061b      	lsls	r3, r3, #24
+  MPU->RASR = ((uint32_t)MPU_Init->DisableExec             << MPU_RASR_XN_Pos)   |
+ 8032bbc:	431a      	orrs	r2, r3
+              ((uint32_t)MPU_Init->TypeExtField            << MPU_RASR_TEX_Pos)  |
+ 8032bbe:	687b      	ldr	r3, [r7, #4]
+ 8032bc0:	7a9b      	ldrb	r3, [r3, #10]
+ 8032bc2:	04db      	lsls	r3, r3, #19
+              ((uint32_t)MPU_Init->AccessPermission        << MPU_RASR_AP_Pos)   |
+ 8032bc4:	431a      	orrs	r2, r3
+              ((uint32_t)MPU_Init->IsShareable             << MPU_RASR_S_Pos)    |
+ 8032bc6:	687b      	ldr	r3, [r7, #4]
+ 8032bc8:	7b5b      	ldrb	r3, [r3, #13]
+ 8032bca:	049b      	lsls	r3, r3, #18
+              ((uint32_t)MPU_Init->TypeExtField            << MPU_RASR_TEX_Pos)  |
+ 8032bcc:	431a      	orrs	r2, r3
+              ((uint32_t)MPU_Init->IsCacheable             << MPU_RASR_C_Pos)    |
+ 8032bce:	687b      	ldr	r3, [r7, #4]
+ 8032bd0:	7b9b      	ldrb	r3, [r3, #14]
+ 8032bd2:	045b      	lsls	r3, r3, #17
+              ((uint32_t)MPU_Init->IsShareable             << MPU_RASR_S_Pos)    |
+ 8032bd4:	431a      	orrs	r2, r3
+              ((uint32_t)MPU_Init->IsBufferable            << MPU_RASR_B_Pos)    |
+ 8032bd6:	687b      	ldr	r3, [r7, #4]
+ 8032bd8:	7bdb      	ldrb	r3, [r3, #15]
+ 8032bda:	041b      	lsls	r3, r3, #16
+              ((uint32_t)MPU_Init->IsCacheable             << MPU_RASR_C_Pos)    |
+ 8032bdc:	431a      	orrs	r2, r3
+              ((uint32_t)MPU_Init->SubRegionDisable        << MPU_RASR_SRD_Pos)  |
+ 8032bde:	687b      	ldr	r3, [r7, #4]
+ 8032be0:	7a5b      	ldrb	r3, [r3, #9]
+ 8032be2:	021b      	lsls	r3, r3, #8
+              ((uint32_t)MPU_Init->IsBufferable            << MPU_RASR_B_Pos)    |
+ 8032be4:	431a      	orrs	r2, r3
+              ((uint32_t)MPU_Init->Size                    << MPU_RASR_SIZE_Pos) |
+ 8032be6:	687b      	ldr	r3, [r7, #4]
+ 8032be8:	7a1b      	ldrb	r3, [r3, #8]
+ 8032bea:	005b      	lsls	r3, r3, #1
+              ((uint32_t)MPU_Init->SubRegionDisable        << MPU_RASR_SRD_Pos)  |
+ 8032bec:	4313      	orrs	r3, r2
+              ((uint32_t)MPU_Init->Enable                  << MPU_RASR_ENABLE_Pos);
+ 8032bee:	687a      	ldr	r2, [r7, #4]
+ 8032bf0:	7812      	ldrb	r2, [r2, #0]
+ 8032bf2:	4611      	mov	r1, r2
+  MPU->RASR = ((uint32_t)MPU_Init->DisableExec             << MPU_RASR_XN_Pos)   |
+ 8032bf4:	4a04      	ldr	r2, [pc, #16]	@ (8032c08 <HAL_MPU_ConfigRegion+0x7c>)
+              ((uint32_t)MPU_Init->Size                    << MPU_RASR_SIZE_Pos) |
+ 8032bf6:	430b      	orrs	r3, r1
+  MPU->RASR = ((uint32_t)MPU_Init->DisableExec             << MPU_RASR_XN_Pos)   |
+ 8032bf8:	6113      	str	r3, [r2, #16]
+}
+ 8032bfa:	bf00      	nop
+ 8032bfc:	370c      	adds	r7, #12
+ 8032bfe:	46bd      	mov	sp, r7
+ 8032c00:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8032c04:	4770      	bx	lr
+ 8032c06:	bf00      	nop
+ 8032c08:	e000ed90 	.word	0xe000ed90
+
+08032c0c <HAL_DMA_Init>:
+  * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Stream.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
+{
+ 8032c0c:	b580      	push	{r7, lr}
+ 8032c0e:	b086      	sub	sp, #24
+ 8032c10:	af00      	add	r7, sp, #0
+ 8032c12:	6078      	str	r0, [r7, #4]
+  uint32_t registerValue;
+  uint32_t tickstart = HAL_GetTick();
+ 8032c14:	f7fe fe8c 	bl	8031930 <HAL_GetTick>
+ 8032c18:	6138      	str	r0, [r7, #16]
+  DMA_Base_Registers *regs_dma;
+  BDMA_Base_Registers *regs_bdma;
+
+  /* Check the DMA peripheral handle */
+  if(hdma == NULL)
+ 8032c1a:	687b      	ldr	r3, [r7, #4]
+ 8032c1c:	2b00      	cmp	r3, #0
+ 8032c1e:	d101      	bne.n	8032c24 <HAL_DMA_Init+0x18>
+  {
+    return HAL_ERROR;
+ 8032c20:	2301      	movs	r3, #1
+ 8032c22:	e316      	b.n	8033252 <HAL_DMA_Init+0x646>
+  assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
+  assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
+  assert_param(IS_DMA_MODE(hdma->Init.Mode));
+  assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
+
+  if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+ 8032c24:	687b      	ldr	r3, [r7, #4]
+ 8032c26:	681b      	ldr	r3, [r3, #0]
+ 8032c28:	4a66      	ldr	r2, [pc, #408]	@ (8032dc4 <HAL_DMA_Init+0x1b8>)
+ 8032c2a:	4293      	cmp	r3, r2
+ 8032c2c:	d04a      	beq.n	8032cc4 <HAL_DMA_Init+0xb8>
+ 8032c2e:	687b      	ldr	r3, [r7, #4]
+ 8032c30:	681b      	ldr	r3, [r3, #0]
+ 8032c32:	4a65      	ldr	r2, [pc, #404]	@ (8032dc8 <HAL_DMA_Init+0x1bc>)
+ 8032c34:	4293      	cmp	r3, r2
+ 8032c36:	d045      	beq.n	8032cc4 <HAL_DMA_Init+0xb8>
+ 8032c38:	687b      	ldr	r3, [r7, #4]
+ 8032c3a:	681b      	ldr	r3, [r3, #0]
+ 8032c3c:	4a63      	ldr	r2, [pc, #396]	@ (8032dcc <HAL_DMA_Init+0x1c0>)
+ 8032c3e:	4293      	cmp	r3, r2
+ 8032c40:	d040      	beq.n	8032cc4 <HAL_DMA_Init+0xb8>
+ 8032c42:	687b      	ldr	r3, [r7, #4]
+ 8032c44:	681b      	ldr	r3, [r3, #0]
+ 8032c46:	4a62      	ldr	r2, [pc, #392]	@ (8032dd0 <HAL_DMA_Init+0x1c4>)
+ 8032c48:	4293      	cmp	r3, r2
+ 8032c4a:	d03b      	beq.n	8032cc4 <HAL_DMA_Init+0xb8>
+ 8032c4c:	687b      	ldr	r3, [r7, #4]
+ 8032c4e:	681b      	ldr	r3, [r3, #0]
+ 8032c50:	4a60      	ldr	r2, [pc, #384]	@ (8032dd4 <HAL_DMA_Init+0x1c8>)
+ 8032c52:	4293      	cmp	r3, r2
+ 8032c54:	d036      	beq.n	8032cc4 <HAL_DMA_Init+0xb8>
+ 8032c56:	687b      	ldr	r3, [r7, #4]
+ 8032c58:	681b      	ldr	r3, [r3, #0]
+ 8032c5a:	4a5f      	ldr	r2, [pc, #380]	@ (8032dd8 <HAL_DMA_Init+0x1cc>)
+ 8032c5c:	4293      	cmp	r3, r2
+ 8032c5e:	d031      	beq.n	8032cc4 <HAL_DMA_Init+0xb8>
+ 8032c60:	687b      	ldr	r3, [r7, #4]
+ 8032c62:	681b      	ldr	r3, [r3, #0]
+ 8032c64:	4a5d      	ldr	r2, [pc, #372]	@ (8032ddc <HAL_DMA_Init+0x1d0>)
+ 8032c66:	4293      	cmp	r3, r2
+ 8032c68:	d02c      	beq.n	8032cc4 <HAL_DMA_Init+0xb8>
+ 8032c6a:	687b      	ldr	r3, [r7, #4]
+ 8032c6c:	681b      	ldr	r3, [r3, #0]
+ 8032c6e:	4a5c      	ldr	r2, [pc, #368]	@ (8032de0 <HAL_DMA_Init+0x1d4>)
+ 8032c70:	4293      	cmp	r3, r2
+ 8032c72:	d027      	beq.n	8032cc4 <HAL_DMA_Init+0xb8>
+ 8032c74:	687b      	ldr	r3, [r7, #4]
+ 8032c76:	681b      	ldr	r3, [r3, #0]
+ 8032c78:	4a5a      	ldr	r2, [pc, #360]	@ (8032de4 <HAL_DMA_Init+0x1d8>)
+ 8032c7a:	4293      	cmp	r3, r2
+ 8032c7c:	d022      	beq.n	8032cc4 <HAL_DMA_Init+0xb8>
+ 8032c7e:	687b      	ldr	r3, [r7, #4]
+ 8032c80:	681b      	ldr	r3, [r3, #0]
+ 8032c82:	4a59      	ldr	r2, [pc, #356]	@ (8032de8 <HAL_DMA_Init+0x1dc>)
+ 8032c84:	4293      	cmp	r3, r2
+ 8032c86:	d01d      	beq.n	8032cc4 <HAL_DMA_Init+0xb8>
+ 8032c88:	687b      	ldr	r3, [r7, #4]
+ 8032c8a:	681b      	ldr	r3, [r3, #0]
+ 8032c8c:	4a57      	ldr	r2, [pc, #348]	@ (8032dec <HAL_DMA_Init+0x1e0>)
+ 8032c8e:	4293      	cmp	r3, r2
+ 8032c90:	d018      	beq.n	8032cc4 <HAL_DMA_Init+0xb8>
+ 8032c92:	687b      	ldr	r3, [r7, #4]
+ 8032c94:	681b      	ldr	r3, [r3, #0]
+ 8032c96:	4a56      	ldr	r2, [pc, #344]	@ (8032df0 <HAL_DMA_Init+0x1e4>)
+ 8032c98:	4293      	cmp	r3, r2
+ 8032c9a:	d013      	beq.n	8032cc4 <HAL_DMA_Init+0xb8>
+ 8032c9c:	687b      	ldr	r3, [r7, #4]
+ 8032c9e:	681b      	ldr	r3, [r3, #0]
+ 8032ca0:	4a54      	ldr	r2, [pc, #336]	@ (8032df4 <HAL_DMA_Init+0x1e8>)
+ 8032ca2:	4293      	cmp	r3, r2
+ 8032ca4:	d00e      	beq.n	8032cc4 <HAL_DMA_Init+0xb8>
+ 8032ca6:	687b      	ldr	r3, [r7, #4]
+ 8032ca8:	681b      	ldr	r3, [r3, #0]
+ 8032caa:	4a53      	ldr	r2, [pc, #332]	@ (8032df8 <HAL_DMA_Init+0x1ec>)
+ 8032cac:	4293      	cmp	r3, r2
+ 8032cae:	d009      	beq.n	8032cc4 <HAL_DMA_Init+0xb8>
+ 8032cb0:	687b      	ldr	r3, [r7, #4]
+ 8032cb2:	681b      	ldr	r3, [r3, #0]
+ 8032cb4:	4a51      	ldr	r2, [pc, #324]	@ (8032dfc <HAL_DMA_Init+0x1f0>)
+ 8032cb6:	4293      	cmp	r3, r2
+ 8032cb8:	d004      	beq.n	8032cc4 <HAL_DMA_Init+0xb8>
+ 8032cba:	687b      	ldr	r3, [r7, #4]
+ 8032cbc:	681b      	ldr	r3, [r3, #0]
+ 8032cbe:	4a50      	ldr	r2, [pc, #320]	@ (8032e00 <HAL_DMA_Init+0x1f4>)
+ 8032cc0:	4293      	cmp	r3, r2
+ 8032cc2:	d101      	bne.n	8032cc8 <HAL_DMA_Init+0xbc>
+ 8032cc4:	2301      	movs	r3, #1
+ 8032cc6:	e000      	b.n	8032cca <HAL_DMA_Init+0xbe>
+ 8032cc8:	2300      	movs	r3, #0
+ 8032cca:	2b00      	cmp	r3, #0
+ 8032ccc:	f000 813b 	beq.w	8032f46 <HAL_DMA_Init+0x33a>
+      assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst));
+      assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));
+    }
+
+    /* Change DMA peripheral state */
+    hdma->State = HAL_DMA_STATE_BUSY;
+ 8032cd0:	687b      	ldr	r3, [r7, #4]
+ 8032cd2:	2202      	movs	r2, #2
+ 8032cd4:	f883 2035 	strb.w	r2, [r3, #53]	@ 0x35
+
+    /* Allocate lock resource */
+    __HAL_UNLOCK(hdma);
+ 8032cd8:	687b      	ldr	r3, [r7, #4]
+ 8032cda:	2200      	movs	r2, #0
+ 8032cdc:	f883 2034 	strb.w	r2, [r3, #52]	@ 0x34
+
+    /* Disable the peripheral */
+    __HAL_DMA_DISABLE(hdma);
+ 8032ce0:	687b      	ldr	r3, [r7, #4]
+ 8032ce2:	681b      	ldr	r3, [r3, #0]
+ 8032ce4:	4a37      	ldr	r2, [pc, #220]	@ (8032dc4 <HAL_DMA_Init+0x1b8>)
+ 8032ce6:	4293      	cmp	r3, r2
+ 8032ce8:	d04a      	beq.n	8032d80 <HAL_DMA_Init+0x174>
+ 8032cea:	687b      	ldr	r3, [r7, #4]
+ 8032cec:	681b      	ldr	r3, [r3, #0]
+ 8032cee:	4a36      	ldr	r2, [pc, #216]	@ (8032dc8 <HAL_DMA_Init+0x1bc>)
+ 8032cf0:	4293      	cmp	r3, r2
+ 8032cf2:	d045      	beq.n	8032d80 <HAL_DMA_Init+0x174>
+ 8032cf4:	687b      	ldr	r3, [r7, #4]
+ 8032cf6:	681b      	ldr	r3, [r3, #0]
+ 8032cf8:	4a34      	ldr	r2, [pc, #208]	@ (8032dcc <HAL_DMA_Init+0x1c0>)
+ 8032cfa:	4293      	cmp	r3, r2
+ 8032cfc:	d040      	beq.n	8032d80 <HAL_DMA_Init+0x174>
+ 8032cfe:	687b      	ldr	r3, [r7, #4]
+ 8032d00:	681b      	ldr	r3, [r3, #0]
+ 8032d02:	4a33      	ldr	r2, [pc, #204]	@ (8032dd0 <HAL_DMA_Init+0x1c4>)
+ 8032d04:	4293      	cmp	r3, r2
+ 8032d06:	d03b      	beq.n	8032d80 <HAL_DMA_Init+0x174>
+ 8032d08:	687b      	ldr	r3, [r7, #4]
+ 8032d0a:	681b      	ldr	r3, [r3, #0]
+ 8032d0c:	4a31      	ldr	r2, [pc, #196]	@ (8032dd4 <HAL_DMA_Init+0x1c8>)
+ 8032d0e:	4293      	cmp	r3, r2
+ 8032d10:	d036      	beq.n	8032d80 <HAL_DMA_Init+0x174>
+ 8032d12:	687b      	ldr	r3, [r7, #4]
+ 8032d14:	681b      	ldr	r3, [r3, #0]
+ 8032d16:	4a30      	ldr	r2, [pc, #192]	@ (8032dd8 <HAL_DMA_Init+0x1cc>)
+ 8032d18:	4293      	cmp	r3, r2
+ 8032d1a:	d031      	beq.n	8032d80 <HAL_DMA_Init+0x174>
+ 8032d1c:	687b      	ldr	r3, [r7, #4]
+ 8032d1e:	681b      	ldr	r3, [r3, #0]
+ 8032d20:	4a2e      	ldr	r2, [pc, #184]	@ (8032ddc <HAL_DMA_Init+0x1d0>)
+ 8032d22:	4293      	cmp	r3, r2
+ 8032d24:	d02c      	beq.n	8032d80 <HAL_DMA_Init+0x174>
+ 8032d26:	687b      	ldr	r3, [r7, #4]
+ 8032d28:	681b      	ldr	r3, [r3, #0]
+ 8032d2a:	4a2d      	ldr	r2, [pc, #180]	@ (8032de0 <HAL_DMA_Init+0x1d4>)
+ 8032d2c:	4293      	cmp	r3, r2
+ 8032d2e:	d027      	beq.n	8032d80 <HAL_DMA_Init+0x174>
+ 8032d30:	687b      	ldr	r3, [r7, #4]
+ 8032d32:	681b      	ldr	r3, [r3, #0]
+ 8032d34:	4a2b      	ldr	r2, [pc, #172]	@ (8032de4 <HAL_DMA_Init+0x1d8>)
+ 8032d36:	4293      	cmp	r3, r2
+ 8032d38:	d022      	beq.n	8032d80 <HAL_DMA_Init+0x174>
+ 8032d3a:	687b      	ldr	r3, [r7, #4]
+ 8032d3c:	681b      	ldr	r3, [r3, #0]
+ 8032d3e:	4a2a      	ldr	r2, [pc, #168]	@ (8032de8 <HAL_DMA_Init+0x1dc>)
+ 8032d40:	4293      	cmp	r3, r2
+ 8032d42:	d01d      	beq.n	8032d80 <HAL_DMA_Init+0x174>
+ 8032d44:	687b      	ldr	r3, [r7, #4]
+ 8032d46:	681b      	ldr	r3, [r3, #0]
+ 8032d48:	4a28      	ldr	r2, [pc, #160]	@ (8032dec <HAL_DMA_Init+0x1e0>)
+ 8032d4a:	4293      	cmp	r3, r2
+ 8032d4c:	d018      	beq.n	8032d80 <HAL_DMA_Init+0x174>
+ 8032d4e:	687b      	ldr	r3, [r7, #4]
+ 8032d50:	681b      	ldr	r3, [r3, #0]
+ 8032d52:	4a27      	ldr	r2, [pc, #156]	@ (8032df0 <HAL_DMA_Init+0x1e4>)
+ 8032d54:	4293      	cmp	r3, r2
+ 8032d56:	d013      	beq.n	8032d80 <HAL_DMA_Init+0x174>
+ 8032d58:	687b      	ldr	r3, [r7, #4]
+ 8032d5a:	681b      	ldr	r3, [r3, #0]
+ 8032d5c:	4a25      	ldr	r2, [pc, #148]	@ (8032df4 <HAL_DMA_Init+0x1e8>)
+ 8032d5e:	4293      	cmp	r3, r2
+ 8032d60:	d00e      	beq.n	8032d80 <HAL_DMA_Init+0x174>
+ 8032d62:	687b      	ldr	r3, [r7, #4]
+ 8032d64:	681b      	ldr	r3, [r3, #0]
+ 8032d66:	4a24      	ldr	r2, [pc, #144]	@ (8032df8 <HAL_DMA_Init+0x1ec>)
+ 8032d68:	4293      	cmp	r3, r2
+ 8032d6a:	d009      	beq.n	8032d80 <HAL_DMA_Init+0x174>
+ 8032d6c:	687b      	ldr	r3, [r7, #4]
+ 8032d6e:	681b      	ldr	r3, [r3, #0]
+ 8032d70:	4a22      	ldr	r2, [pc, #136]	@ (8032dfc <HAL_DMA_Init+0x1f0>)
+ 8032d72:	4293      	cmp	r3, r2
+ 8032d74:	d004      	beq.n	8032d80 <HAL_DMA_Init+0x174>
+ 8032d76:	687b      	ldr	r3, [r7, #4]
+ 8032d78:	681b      	ldr	r3, [r3, #0]
+ 8032d7a:	4a21      	ldr	r2, [pc, #132]	@ (8032e00 <HAL_DMA_Init+0x1f4>)
+ 8032d7c:	4293      	cmp	r3, r2
+ 8032d7e:	d108      	bne.n	8032d92 <HAL_DMA_Init+0x186>
+ 8032d80:	687b      	ldr	r3, [r7, #4]
+ 8032d82:	681b      	ldr	r3, [r3, #0]
+ 8032d84:	681a      	ldr	r2, [r3, #0]
+ 8032d86:	687b      	ldr	r3, [r7, #4]
+ 8032d88:	681b      	ldr	r3, [r3, #0]
+ 8032d8a:	f022 0201 	bic.w	r2, r2, #1
+ 8032d8e:	601a      	str	r2, [r3, #0]
+ 8032d90:	e007      	b.n	8032da2 <HAL_DMA_Init+0x196>
+ 8032d92:	687b      	ldr	r3, [r7, #4]
+ 8032d94:	681b      	ldr	r3, [r3, #0]
+ 8032d96:	681a      	ldr	r2, [r3, #0]
+ 8032d98:	687b      	ldr	r3, [r7, #4]
+ 8032d9a:	681b      	ldr	r3, [r3, #0]
+ 8032d9c:	f022 0201 	bic.w	r2, r2, #1
+ 8032da0:	601a      	str	r2, [r3, #0]
+
+    /* Check if the DMA Stream is effectively disabled */
+    while((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U)
+ 8032da2:	e02f      	b.n	8032e04 <HAL_DMA_Init+0x1f8>
+    {
+      /* Check for the Timeout */
+      if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
+ 8032da4:	f7fe fdc4 	bl	8031930 <HAL_GetTick>
+ 8032da8:	4602      	mov	r2, r0
+ 8032daa:	693b      	ldr	r3, [r7, #16]
+ 8032dac:	1ad3      	subs	r3, r2, r3
+ 8032dae:	2b05      	cmp	r3, #5
+ 8032db0:	d928      	bls.n	8032e04 <HAL_DMA_Init+0x1f8>
+      {
+        /* Update error code */
+        hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
+ 8032db2:	687b      	ldr	r3, [r7, #4]
+ 8032db4:	2220      	movs	r2, #32
+ 8032db6:	655a      	str	r2, [r3, #84]	@ 0x54
+
+        /* Change the DMA state */
+        hdma->State = HAL_DMA_STATE_ERROR;
+ 8032db8:	687b      	ldr	r3, [r7, #4]
+ 8032dba:	2203      	movs	r2, #3
+ 8032dbc:	f883 2035 	strb.w	r2, [r3, #53]	@ 0x35
+
+        return HAL_ERROR;
+ 8032dc0:	2301      	movs	r3, #1
+ 8032dc2:	e246      	b.n	8033252 <HAL_DMA_Init+0x646>
+ 8032dc4:	40020010 	.word	0x40020010
+ 8032dc8:	40020028 	.word	0x40020028
+ 8032dcc:	40020040 	.word	0x40020040
+ 8032dd0:	40020058 	.word	0x40020058
+ 8032dd4:	40020070 	.word	0x40020070
+ 8032dd8:	40020088 	.word	0x40020088
+ 8032ddc:	400200a0 	.word	0x400200a0
+ 8032de0:	400200b8 	.word	0x400200b8
+ 8032de4:	40020410 	.word	0x40020410
+ 8032de8:	40020428 	.word	0x40020428
+ 8032dec:	40020440 	.word	0x40020440
+ 8032df0:	40020458 	.word	0x40020458
+ 8032df4:	40020470 	.word	0x40020470
+ 8032df8:	40020488 	.word	0x40020488
+ 8032dfc:	400204a0 	.word	0x400204a0
+ 8032e00:	400204b8 	.word	0x400204b8
+    while((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U)
+ 8032e04:	687b      	ldr	r3, [r7, #4]
+ 8032e06:	681b      	ldr	r3, [r3, #0]
+ 8032e08:	681b      	ldr	r3, [r3, #0]
+ 8032e0a:	f003 0301 	and.w	r3, r3, #1
+ 8032e0e:	2b00      	cmp	r3, #0
+ 8032e10:	d1c8      	bne.n	8032da4 <HAL_DMA_Init+0x198>
+      }
+    }
+
+    /* Get the CR register value */
+    registerValue = ((DMA_Stream_TypeDef   *)hdma->Instance)->CR;
+ 8032e12:	687b      	ldr	r3, [r7, #4]
+ 8032e14:	681b      	ldr	r3, [r3, #0]
+ 8032e16:	681b      	ldr	r3, [r3, #0]
+ 8032e18:	617b      	str	r3, [r7, #20]
+
+    /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */
+    registerValue &= ((uint32_t)~(DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
+ 8032e1a:	697a      	ldr	r2, [r7, #20]
+ 8032e1c:	4b83      	ldr	r3, [pc, #524]	@ (803302c <HAL_DMA_Init+0x420>)
+ 8032e1e:	4013      	ands	r3, r2
+ 8032e20:	617b      	str	r3, [r7, #20]
+                        DMA_SxCR_PL    | DMA_SxCR_MSIZE  | DMA_SxCR_PSIZE  | \
+                        DMA_SxCR_MINC  | DMA_SxCR_PINC   | DMA_SxCR_CIRC   | \
+                        DMA_SxCR_DIR   | DMA_SxCR_CT     | DMA_SxCR_DBM));
+
+    /* Prepare the DMA Stream configuration */
+    registerValue |=  hdma->Init.Direction           |
+ 8032e22:	687b      	ldr	r3, [r7, #4]
+ 8032e24:	689a      	ldr	r2, [r3, #8]
+            hdma->Init.PeriphInc           | hdma->Init.MemInc           |
+ 8032e26:	687b      	ldr	r3, [r7, #4]
+ 8032e28:	68db      	ldr	r3, [r3, #12]
+    registerValue |=  hdma->Init.Direction           |
+ 8032e2a:	431a      	orrs	r2, r3
+            hdma->Init.PeriphInc           | hdma->Init.MemInc           |
+ 8032e2c:	687b      	ldr	r3, [r7, #4]
+ 8032e2e:	691b      	ldr	r3, [r3, #16]
+ 8032e30:	431a      	orrs	r2, r3
+            hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
+ 8032e32:	687b      	ldr	r3, [r7, #4]
+ 8032e34:	695b      	ldr	r3, [r3, #20]
+            hdma->Init.PeriphInc           | hdma->Init.MemInc           |
+ 8032e36:	431a      	orrs	r2, r3
+            hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
+ 8032e38:	687b      	ldr	r3, [r7, #4]
+ 8032e3a:	699b      	ldr	r3, [r3, #24]
+ 8032e3c:	431a      	orrs	r2, r3
+            hdma->Init.Mode                | hdma->Init.Priority;
+ 8032e3e:	687b      	ldr	r3, [r7, #4]
+ 8032e40:	69db      	ldr	r3, [r3, #28]
+            hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
+ 8032e42:	431a      	orrs	r2, r3
+            hdma->Init.Mode                | hdma->Init.Priority;
+ 8032e44:	687b      	ldr	r3, [r7, #4]
+ 8032e46:	6a1b      	ldr	r3, [r3, #32]
+ 8032e48:	4313      	orrs	r3, r2
+    registerValue |=  hdma->Init.Direction           |
+ 8032e4a:	697a      	ldr	r2, [r7, #20]
+ 8032e4c:	4313      	orrs	r3, r2
+ 8032e4e:	617b      	str	r3, [r7, #20]
+
+    /* the Memory burst and peripheral burst are not used when the FIFO is disabled */
+    if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
+ 8032e50:	687b      	ldr	r3, [r7, #4]
+ 8032e52:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 8032e54:	2b04      	cmp	r3, #4
+ 8032e56:	d107      	bne.n	8032e68 <HAL_DMA_Init+0x25c>
+    {
+      /* Get memory burst and peripheral burst */
+      registerValue |=  hdma->Init.MemBurst | hdma->Init.PeriphBurst;
+ 8032e58:	687b      	ldr	r3, [r7, #4]
+ 8032e5a:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
+ 8032e5c:	687b      	ldr	r3, [r7, #4]
+ 8032e5e:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
+ 8032e60:	4313      	orrs	r3, r2
+ 8032e62:	697a      	ldr	r2, [r7, #20]
+ 8032e64:	4313      	orrs	r3, r2
+ 8032e66:	617b      	str	r3, [r7, #20]
+    }
+
+    /* Work around for Errata 2.22: UART/USART- DMA transfer lock: DMA stream could be
+                                    lock when transferring data to/from USART/UART */
+#if (STM32H7_DEV_ID == 0x450UL)
+    if((DBGMCU->IDCODE & 0xFFFF0000U) >= 0x20000000U)
+ 8032e68:	4b71      	ldr	r3, [pc, #452]	@ (8033030 <HAL_DMA_Init+0x424>)
+ 8032e6a:	681a      	ldr	r2, [r3, #0]
+ 8032e6c:	4b71      	ldr	r3, [pc, #452]	@ (8033034 <HAL_DMA_Init+0x428>)
+ 8032e6e:	4013      	ands	r3, r2
+ 8032e70:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
+ 8032e74:	d328      	bcc.n	8032ec8 <HAL_DMA_Init+0x2bc>
+    {
+#endif /* STM32H7_DEV_ID == 0x450UL */
+      if(IS_DMA_UART_USART_REQUEST(hdma->Init.Request) != 0U)
+ 8032e76:	687b      	ldr	r3, [r7, #4]
+ 8032e78:	685b      	ldr	r3, [r3, #4]
+ 8032e7a:	2b28      	cmp	r3, #40	@ 0x28
+ 8032e7c:	d903      	bls.n	8032e86 <HAL_DMA_Init+0x27a>
+ 8032e7e:	687b      	ldr	r3, [r7, #4]
+ 8032e80:	685b      	ldr	r3, [r3, #4]
+ 8032e82:	2b2e      	cmp	r3, #46	@ 0x2e
+ 8032e84:	d917      	bls.n	8032eb6 <HAL_DMA_Init+0x2aa>
+ 8032e86:	687b      	ldr	r3, [r7, #4]
+ 8032e88:	685b      	ldr	r3, [r3, #4]
+ 8032e8a:	2b3e      	cmp	r3, #62	@ 0x3e
+ 8032e8c:	d903      	bls.n	8032e96 <HAL_DMA_Init+0x28a>
+ 8032e8e:	687b      	ldr	r3, [r7, #4]
+ 8032e90:	685b      	ldr	r3, [r3, #4]
+ 8032e92:	2b42      	cmp	r3, #66	@ 0x42
+ 8032e94:	d90f      	bls.n	8032eb6 <HAL_DMA_Init+0x2aa>
+ 8032e96:	687b      	ldr	r3, [r7, #4]
+ 8032e98:	685b      	ldr	r3, [r3, #4]
+ 8032e9a:	2b46      	cmp	r3, #70	@ 0x46
+ 8032e9c:	d903      	bls.n	8032ea6 <HAL_DMA_Init+0x29a>
+ 8032e9e:	687b      	ldr	r3, [r7, #4]
+ 8032ea0:	685b      	ldr	r3, [r3, #4]
+ 8032ea2:	2b48      	cmp	r3, #72	@ 0x48
+ 8032ea4:	d907      	bls.n	8032eb6 <HAL_DMA_Init+0x2aa>
+ 8032ea6:	687b      	ldr	r3, [r7, #4]
+ 8032ea8:	685b      	ldr	r3, [r3, #4]
+ 8032eaa:	2b4e      	cmp	r3, #78	@ 0x4e
+ 8032eac:	d905      	bls.n	8032eba <HAL_DMA_Init+0x2ae>
+ 8032eae:	687b      	ldr	r3, [r7, #4]
+ 8032eb0:	685b      	ldr	r3, [r3, #4]
+ 8032eb2:	2b52      	cmp	r3, #82	@ 0x52
+ 8032eb4:	d801      	bhi.n	8032eba <HAL_DMA_Init+0x2ae>
+ 8032eb6:	2301      	movs	r3, #1
+ 8032eb8:	e000      	b.n	8032ebc <HAL_DMA_Init+0x2b0>
+ 8032eba:	2300      	movs	r3, #0
+ 8032ebc:	2b00      	cmp	r3, #0
+ 8032ebe:	d003      	beq.n	8032ec8 <HAL_DMA_Init+0x2bc>
+      {
+        registerValue |= DMA_SxCR_TRBUFF;
+ 8032ec0:	697b      	ldr	r3, [r7, #20]
+ 8032ec2:	f443 1380 	orr.w	r3, r3, #1048576	@ 0x100000
+ 8032ec6:	617b      	str	r3, [r7, #20]
+#if (STM32H7_DEV_ID == 0x450UL)
+    }
+#endif /* STM32H7_DEV_ID == 0x450UL */
+
+    /* Write to DMA Stream CR register */
+    ((DMA_Stream_TypeDef   *)hdma->Instance)->CR = registerValue;
+ 8032ec8:	687b      	ldr	r3, [r7, #4]
+ 8032eca:	681b      	ldr	r3, [r3, #0]
+ 8032ecc:	697a      	ldr	r2, [r7, #20]
+ 8032ece:	601a      	str	r2, [r3, #0]
+
+    /* Get the FCR register value */
+    registerValue = ((DMA_Stream_TypeDef   *)hdma->Instance)->FCR;
+ 8032ed0:	687b      	ldr	r3, [r7, #4]
+ 8032ed2:	681b      	ldr	r3, [r3, #0]
+ 8032ed4:	695b      	ldr	r3, [r3, #20]
+ 8032ed6:	617b      	str	r3, [r7, #20]
+
+    /* Clear Direct mode and FIFO threshold bits */
+    registerValue &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);
+ 8032ed8:	697b      	ldr	r3, [r7, #20]
+ 8032eda:	f023 0307 	bic.w	r3, r3, #7
+ 8032ede:	617b      	str	r3, [r7, #20]
+
+    /* Prepare the DMA Stream FIFO configuration */
+    registerValue |= hdma->Init.FIFOMode;
+ 8032ee0:	687b      	ldr	r3, [r7, #4]
+ 8032ee2:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 8032ee4:	697a      	ldr	r2, [r7, #20]
+ 8032ee6:	4313      	orrs	r3, r2
+ 8032ee8:	617b      	str	r3, [r7, #20]
+
+    /* the FIFO threshold is not used when the FIFO mode is disabled */
+    if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
+ 8032eea:	687b      	ldr	r3, [r7, #4]
+ 8032eec:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 8032eee:	2b04      	cmp	r3, #4
+ 8032ef0:	d117      	bne.n	8032f22 <HAL_DMA_Init+0x316>
+    {
+      /* Get the FIFO threshold */
+      registerValue |= hdma->Init.FIFOThreshold;
+ 8032ef2:	687b      	ldr	r3, [r7, #4]
+ 8032ef4:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 8032ef6:	697a      	ldr	r2, [r7, #20]
+ 8032ef8:	4313      	orrs	r3, r2
+ 8032efa:	617b      	str	r3, [r7, #20]
+
+      /* Check compatibility between FIFO threshold level and size of the memory burst */
+      /* for INCR4, INCR8, INCR16 */
+      if(hdma->Init.MemBurst != DMA_MBURST_SINGLE)
+ 8032efc:	687b      	ldr	r3, [r7, #4]
+ 8032efe:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 8032f00:	2b00      	cmp	r3, #0
+ 8032f02:	d00e      	beq.n	8032f22 <HAL_DMA_Init+0x316>
+      {
+        if (DMA_CheckFifoParam(hdma) != HAL_OK)
+ 8032f04:	6878      	ldr	r0, [r7, #4]
+ 8032f06:	f002 fb41 	bl	803558c <DMA_CheckFifoParam>
+ 8032f0a:	4603      	mov	r3, r0
+ 8032f0c:	2b00      	cmp	r3, #0
+ 8032f0e:	d008      	beq.n	8032f22 <HAL_DMA_Init+0x316>
+        {
+          /* Update error code */
+          hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
+ 8032f10:	687b      	ldr	r3, [r7, #4]
+ 8032f12:	2240      	movs	r2, #64	@ 0x40
+ 8032f14:	655a      	str	r2, [r3, #84]	@ 0x54
+
+          /* Change the DMA state */
+          hdma->State = HAL_DMA_STATE_READY;
+ 8032f16:	687b      	ldr	r3, [r7, #4]
+ 8032f18:	2201      	movs	r2, #1
+ 8032f1a:	f883 2035 	strb.w	r2, [r3, #53]	@ 0x35
+
+          return HAL_ERROR;
+ 8032f1e:	2301      	movs	r3, #1
+ 8032f20:	e197      	b.n	8033252 <HAL_DMA_Init+0x646>
+        }
+      }
+    }
+
+    /* Write to DMA Stream FCR */
+    ((DMA_Stream_TypeDef   *)hdma->Instance)->FCR = registerValue;
+ 8032f22:	687b      	ldr	r3, [r7, #4]
+ 8032f24:	681b      	ldr	r3, [r3, #0]
+ 8032f26:	697a      	ldr	r2, [r7, #20]
+ 8032f28:	615a      	str	r2, [r3, #20]
+
+    /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate
+       DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
+    regs_dma = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
+ 8032f2a:	6878      	ldr	r0, [r7, #4]
+ 8032f2c:	f002 fa7c 	bl	8035428 <DMA_CalcBaseAndBitshift>
+ 8032f30:	4603      	mov	r3, r0
+ 8032f32:	60bb      	str	r3, [r7, #8]
+
+    /* Clear all interrupt flags */
+    regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);
+ 8032f34:	687b      	ldr	r3, [r7, #4]
+ 8032f36:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
+ 8032f38:	f003 031f 	and.w	r3, r3, #31
+ 8032f3c:	223f      	movs	r2, #63	@ 0x3f
+ 8032f3e:	409a      	lsls	r2, r3
+ 8032f40:	68bb      	ldr	r3, [r7, #8]
+ 8032f42:	609a      	str	r2, [r3, #8]
+ 8032f44:	e0cd      	b.n	80330e2 <HAL_DMA_Init+0x4d6>
+  }
+  else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */
+ 8032f46:	687b      	ldr	r3, [r7, #4]
+ 8032f48:	681b      	ldr	r3, [r3, #0]
+ 8032f4a:	4a3b      	ldr	r2, [pc, #236]	@ (8033038 <HAL_DMA_Init+0x42c>)
+ 8032f4c:	4293      	cmp	r3, r2
+ 8032f4e:	d022      	beq.n	8032f96 <HAL_DMA_Init+0x38a>
+ 8032f50:	687b      	ldr	r3, [r7, #4]
+ 8032f52:	681b      	ldr	r3, [r3, #0]
+ 8032f54:	4a39      	ldr	r2, [pc, #228]	@ (803303c <HAL_DMA_Init+0x430>)
+ 8032f56:	4293      	cmp	r3, r2
+ 8032f58:	d01d      	beq.n	8032f96 <HAL_DMA_Init+0x38a>
+ 8032f5a:	687b      	ldr	r3, [r7, #4]
+ 8032f5c:	681b      	ldr	r3, [r3, #0]
+ 8032f5e:	4a38      	ldr	r2, [pc, #224]	@ (8033040 <HAL_DMA_Init+0x434>)
+ 8032f60:	4293      	cmp	r3, r2
+ 8032f62:	d018      	beq.n	8032f96 <HAL_DMA_Init+0x38a>
+ 8032f64:	687b      	ldr	r3, [r7, #4]
+ 8032f66:	681b      	ldr	r3, [r3, #0]
+ 8032f68:	4a36      	ldr	r2, [pc, #216]	@ (8033044 <HAL_DMA_Init+0x438>)
+ 8032f6a:	4293      	cmp	r3, r2
+ 8032f6c:	d013      	beq.n	8032f96 <HAL_DMA_Init+0x38a>
+ 8032f6e:	687b      	ldr	r3, [r7, #4]
+ 8032f70:	681b      	ldr	r3, [r3, #0]
+ 8032f72:	4a35      	ldr	r2, [pc, #212]	@ (8033048 <HAL_DMA_Init+0x43c>)
+ 8032f74:	4293      	cmp	r3, r2
+ 8032f76:	d00e      	beq.n	8032f96 <HAL_DMA_Init+0x38a>
+ 8032f78:	687b      	ldr	r3, [r7, #4]
+ 8032f7a:	681b      	ldr	r3, [r3, #0]
+ 8032f7c:	4a33      	ldr	r2, [pc, #204]	@ (803304c <HAL_DMA_Init+0x440>)
+ 8032f7e:	4293      	cmp	r3, r2
+ 8032f80:	d009      	beq.n	8032f96 <HAL_DMA_Init+0x38a>
+ 8032f82:	687b      	ldr	r3, [r7, #4]
+ 8032f84:	681b      	ldr	r3, [r3, #0]
+ 8032f86:	4a32      	ldr	r2, [pc, #200]	@ (8033050 <HAL_DMA_Init+0x444>)
+ 8032f88:	4293      	cmp	r3, r2
+ 8032f8a:	d004      	beq.n	8032f96 <HAL_DMA_Init+0x38a>
+ 8032f8c:	687b      	ldr	r3, [r7, #4]
+ 8032f8e:	681b      	ldr	r3, [r3, #0]
+ 8032f90:	4a30      	ldr	r2, [pc, #192]	@ (8033054 <HAL_DMA_Init+0x448>)
+ 8032f92:	4293      	cmp	r3, r2
+ 8032f94:	d101      	bne.n	8032f9a <HAL_DMA_Init+0x38e>
+ 8032f96:	2301      	movs	r3, #1
+ 8032f98:	e000      	b.n	8032f9c <HAL_DMA_Init+0x390>
+ 8032f9a:	2300      	movs	r3, #0
+ 8032f9c:	2b00      	cmp	r3, #0
+ 8032f9e:	f000 8097 	beq.w	80330d0 <HAL_DMA_Init+0x4c4>
+  {
+    if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U)
+ 8032fa2:	687b      	ldr	r3, [r7, #4]
+ 8032fa4:	681b      	ldr	r3, [r3, #0]
+ 8032fa6:	4a24      	ldr	r2, [pc, #144]	@ (8033038 <HAL_DMA_Init+0x42c>)
+ 8032fa8:	4293      	cmp	r3, r2
+ 8032faa:	d021      	beq.n	8032ff0 <HAL_DMA_Init+0x3e4>
+ 8032fac:	687b      	ldr	r3, [r7, #4]
+ 8032fae:	681b      	ldr	r3, [r3, #0]
+ 8032fb0:	4a22      	ldr	r2, [pc, #136]	@ (803303c <HAL_DMA_Init+0x430>)
+ 8032fb2:	4293      	cmp	r3, r2
+ 8032fb4:	d01c      	beq.n	8032ff0 <HAL_DMA_Init+0x3e4>
+ 8032fb6:	687b      	ldr	r3, [r7, #4]
+ 8032fb8:	681b      	ldr	r3, [r3, #0]
+ 8032fba:	4a21      	ldr	r2, [pc, #132]	@ (8033040 <HAL_DMA_Init+0x434>)
+ 8032fbc:	4293      	cmp	r3, r2
+ 8032fbe:	d017      	beq.n	8032ff0 <HAL_DMA_Init+0x3e4>
+ 8032fc0:	687b      	ldr	r3, [r7, #4]
+ 8032fc2:	681b      	ldr	r3, [r3, #0]
+ 8032fc4:	4a1f      	ldr	r2, [pc, #124]	@ (8033044 <HAL_DMA_Init+0x438>)
+ 8032fc6:	4293      	cmp	r3, r2
+ 8032fc8:	d012      	beq.n	8032ff0 <HAL_DMA_Init+0x3e4>
+ 8032fca:	687b      	ldr	r3, [r7, #4]
+ 8032fcc:	681b      	ldr	r3, [r3, #0]
+ 8032fce:	4a1e      	ldr	r2, [pc, #120]	@ (8033048 <HAL_DMA_Init+0x43c>)
+ 8032fd0:	4293      	cmp	r3, r2
+ 8032fd2:	d00d      	beq.n	8032ff0 <HAL_DMA_Init+0x3e4>
+ 8032fd4:	687b      	ldr	r3, [r7, #4]
+ 8032fd6:	681b      	ldr	r3, [r3, #0]
+ 8032fd8:	4a1c      	ldr	r2, [pc, #112]	@ (803304c <HAL_DMA_Init+0x440>)
+ 8032fda:	4293      	cmp	r3, r2
+ 8032fdc:	d008      	beq.n	8032ff0 <HAL_DMA_Init+0x3e4>
+ 8032fde:	687b      	ldr	r3, [r7, #4]
+ 8032fe0:	681b      	ldr	r3, [r3, #0]
+ 8032fe2:	4a1b      	ldr	r2, [pc, #108]	@ (8033050 <HAL_DMA_Init+0x444>)
+ 8032fe4:	4293      	cmp	r3, r2
+ 8032fe6:	d003      	beq.n	8032ff0 <HAL_DMA_Init+0x3e4>
+ 8032fe8:	687b      	ldr	r3, [r7, #4]
+ 8032fea:	681b      	ldr	r3, [r3, #0]
+ 8032fec:	4a19      	ldr	r2, [pc, #100]	@ (8033054 <HAL_DMA_Init+0x448>)
+ 8032fee:	4293      	cmp	r3, r2
+      /* Check the request parameter */
+      assert_param(IS_BDMA_REQUEST(hdma->Init.Request));
+    }
+
+    /* Change DMA peripheral state */
+    hdma->State = HAL_DMA_STATE_BUSY;
+ 8032ff0:	687b      	ldr	r3, [r7, #4]
+ 8032ff2:	2202      	movs	r2, #2
+ 8032ff4:	f883 2035 	strb.w	r2, [r3, #53]	@ 0x35
+
+    /* Allocate lock resource */
+    __HAL_UNLOCK(hdma);
+ 8032ff8:	687b      	ldr	r3, [r7, #4]
+ 8032ffa:	2200      	movs	r2, #0
+ 8032ffc:	f883 2034 	strb.w	r2, [r3, #52]	@ 0x34
+
+    /* Get the CR register value */
+    registerValue = ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR;
+ 8033000:	687b      	ldr	r3, [r7, #4]
+ 8033002:	681b      	ldr	r3, [r3, #0]
+ 8033004:	681b      	ldr	r3, [r3, #0]
+ 8033006:	617b      	str	r3, [r7, #20]
+
+    /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, MEM2MEM, DBM and CT bits */
+    registerValue &= ((uint32_t)~(BDMA_CCR_PL    | BDMA_CCR_MSIZE   | BDMA_CCR_PSIZE  | \
+ 8033008:	697a      	ldr	r2, [r7, #20]
+ 803300a:	4b13      	ldr	r3, [pc, #76]	@ (8033058 <HAL_DMA_Init+0x44c>)
+ 803300c:	4013      	ands	r3, r2
+ 803300e:	617b      	str	r3, [r7, #20]
+                                  BDMA_CCR_MINC  | BDMA_CCR_PINC    | BDMA_CCR_CIRC   | \
+                                  BDMA_CCR_DIR   | BDMA_CCR_MEM2MEM | BDMA_CCR_DBM    | \
+                                  BDMA_CCR_CT));
+
+    /* Prepare the DMA Channel configuration */
+    registerValue |=  DMA_TO_BDMA_DIRECTION(hdma->Init.Direction)            |
+ 8033010:	687b      	ldr	r3, [r7, #4]
+ 8033012:	689b      	ldr	r3, [r3, #8]
+ 8033014:	2b40      	cmp	r3, #64	@ 0x40
+ 8033016:	d021      	beq.n	803305c <HAL_DMA_Init+0x450>
+ 8033018:	687b      	ldr	r3, [r7, #4]
+ 803301a:	689b      	ldr	r3, [r3, #8]
+ 803301c:	2b80      	cmp	r3, #128	@ 0x80
+ 803301e:	d102      	bne.n	8033026 <HAL_DMA_Init+0x41a>
+ 8033020:	f44f 4380 	mov.w	r3, #16384	@ 0x4000
+ 8033024:	e01b      	b.n	803305e <HAL_DMA_Init+0x452>
+ 8033026:	2300      	movs	r3, #0
+ 8033028:	e019      	b.n	803305e <HAL_DMA_Init+0x452>
+ 803302a:	bf00      	nop
+ 803302c:	fe10803f 	.word	0xfe10803f
+ 8033030:	5c001000 	.word	0x5c001000
+ 8033034:	ffff0000 	.word	0xffff0000
+ 8033038:	58025408 	.word	0x58025408
+ 803303c:	5802541c 	.word	0x5802541c
+ 8033040:	58025430 	.word	0x58025430
+ 8033044:	58025444 	.word	0x58025444
+ 8033048:	58025458 	.word	0x58025458
+ 803304c:	5802546c 	.word	0x5802546c
+ 8033050:	58025480 	.word	0x58025480
+ 8033054:	58025494 	.word	0x58025494
+ 8033058:	fffe000f 	.word	0xfffe000f
+ 803305c:	2310      	movs	r3, #16
+                      DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc)       |
+ 803305e:	687a      	ldr	r2, [r7, #4]
+ 8033060:	68d2      	ldr	r2, [r2, #12]
+ 8033062:	08d2      	lsrs	r2, r2, #3
+    registerValue |=  DMA_TO_BDMA_DIRECTION(hdma->Init.Direction)            |
+ 8033064:	431a      	orrs	r2, r3
+                      DMA_TO_BDMA_MEMORY_INC(hdma->Init.MemInc)              |
+ 8033066:	687b      	ldr	r3, [r7, #4]
+ 8033068:	691b      	ldr	r3, [r3, #16]
+ 803306a:	08db      	lsrs	r3, r3, #3
+                      DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc)       |
+ 803306c:	431a      	orrs	r2, r3
+                      DMA_TO_BDMA_PDATA_SIZE(hdma->Init.PeriphDataAlignment) |
+ 803306e:	687b      	ldr	r3, [r7, #4]
+ 8033070:	695b      	ldr	r3, [r3, #20]
+ 8033072:	08db      	lsrs	r3, r3, #3
+                      DMA_TO_BDMA_MEMORY_INC(hdma->Init.MemInc)              |
+ 8033074:	431a      	orrs	r2, r3
+                      DMA_TO_BDMA_MDATA_SIZE(hdma->Init.MemDataAlignment)    |
+ 8033076:	687b      	ldr	r3, [r7, #4]
+ 8033078:	699b      	ldr	r3, [r3, #24]
+ 803307a:	08db      	lsrs	r3, r3, #3
+                      DMA_TO_BDMA_PDATA_SIZE(hdma->Init.PeriphDataAlignment) |
+ 803307c:	431a      	orrs	r2, r3
+                      DMA_TO_BDMA_MODE(hdma->Init.Mode)                      |
+ 803307e:	687b      	ldr	r3, [r7, #4]
+ 8033080:	69db      	ldr	r3, [r3, #28]
+ 8033082:	08db      	lsrs	r3, r3, #3
+                      DMA_TO_BDMA_MDATA_SIZE(hdma->Init.MemDataAlignment)    |
+ 8033084:	431a      	orrs	r2, r3
+                      DMA_TO_BDMA_PRIORITY(hdma->Init.Priority);
+ 8033086:	687b      	ldr	r3, [r7, #4]
+ 8033088:	6a1b      	ldr	r3, [r3, #32]
+ 803308a:	091b      	lsrs	r3, r3, #4
+                      DMA_TO_BDMA_MODE(hdma->Init.Mode)                      |
+ 803308c:	4313      	orrs	r3, r2
+    registerValue |=  DMA_TO_BDMA_DIRECTION(hdma->Init.Direction)            |
+ 803308e:	697a      	ldr	r2, [r7, #20]
+ 8033090:	4313      	orrs	r3, r2
+ 8033092:	617b      	str	r3, [r7, #20]
+
+    /* Write to DMA Channel CR register */
+    ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR = registerValue;
+ 8033094:	687b      	ldr	r3, [r7, #4]
+ 8033096:	681b      	ldr	r3, [r3, #0]
+ 8033098:	697a      	ldr	r2, [r7, #20]
+ 803309a:	601a      	str	r2, [r3, #0]
+
+    /* calculation of the channel index */
+    hdma->StreamIndex = (((uint32_t)((uint32_t*)hdma->Instance) - (uint32_t)BDMA_Channel0) / ((uint32_t)BDMA_Channel1 - (uint32_t)BDMA_Channel0)) << 2U;
+ 803309c:	687b      	ldr	r3, [r7, #4]
+ 803309e:	681b      	ldr	r3, [r3, #0]
+ 80330a0:	461a      	mov	r2, r3
+ 80330a2:	4b6e      	ldr	r3, [pc, #440]	@ (803325c <HAL_DMA_Init+0x650>)
+ 80330a4:	4413      	add	r3, r2
+ 80330a6:	4a6e      	ldr	r2, [pc, #440]	@ (8033260 <HAL_DMA_Init+0x654>)
+ 80330a8:	fba2 2303 	umull	r2, r3, r2, r3
+ 80330ac:	091b      	lsrs	r3, r3, #4
+ 80330ae:	009a      	lsls	r2, r3, #2
+ 80330b0:	687b      	ldr	r3, [r7, #4]
+ 80330b2:	65da      	str	r2, [r3, #92]	@ 0x5c
+
+    /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate
+    DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
+    regs_bdma = (BDMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
+ 80330b4:	6878      	ldr	r0, [r7, #4]
+ 80330b6:	f002 f9b7 	bl	8035428 <DMA_CalcBaseAndBitshift>
+ 80330ba:	4603      	mov	r3, r0
+ 80330bc:	60fb      	str	r3, [r7, #12]
+
+    /* Clear all interrupt flags */
+    regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU));
+ 80330be:	687b      	ldr	r3, [r7, #4]
+ 80330c0:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
+ 80330c2:	f003 031f 	and.w	r3, r3, #31
+ 80330c6:	2201      	movs	r2, #1
+ 80330c8:	409a      	lsls	r2, r3
+ 80330ca:	68fb      	ldr	r3, [r7, #12]
+ 80330cc:	605a      	str	r2, [r3, #4]
+ 80330ce:	e008      	b.n	80330e2 <HAL_DMA_Init+0x4d6>
+  }
+  else
+  {
+    hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
+ 80330d0:	687b      	ldr	r3, [r7, #4]
+ 80330d2:	2240      	movs	r2, #64	@ 0x40
+ 80330d4:	655a      	str	r2, [r3, #84]	@ 0x54
+    hdma->State     = HAL_DMA_STATE_ERROR;
+ 80330d6:	687b      	ldr	r3, [r7, #4]
+ 80330d8:	2203      	movs	r2, #3
+ 80330da:	f883 2035 	strb.w	r2, [r3, #53]	@ 0x35
+
+    return HAL_ERROR;
+ 80330de:	2301      	movs	r3, #1
+ 80330e0:	e0b7      	b.n	8033252 <HAL_DMA_Init+0x646>
+  }
+
+  if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
+ 80330e2:	687b      	ldr	r3, [r7, #4]
+ 80330e4:	681b      	ldr	r3, [r3, #0]
+ 80330e6:	4a5f      	ldr	r2, [pc, #380]	@ (8033264 <HAL_DMA_Init+0x658>)
+ 80330e8:	4293      	cmp	r3, r2
+ 80330ea:	d072      	beq.n	80331d2 <HAL_DMA_Init+0x5c6>
+ 80330ec:	687b      	ldr	r3, [r7, #4]
+ 80330ee:	681b      	ldr	r3, [r3, #0]
+ 80330f0:	4a5d      	ldr	r2, [pc, #372]	@ (8033268 <HAL_DMA_Init+0x65c>)
+ 80330f2:	4293      	cmp	r3, r2
+ 80330f4:	d06d      	beq.n	80331d2 <HAL_DMA_Init+0x5c6>
+ 80330f6:	687b      	ldr	r3, [r7, #4]
+ 80330f8:	681b      	ldr	r3, [r3, #0]
+ 80330fa:	4a5c      	ldr	r2, [pc, #368]	@ (803326c <HAL_DMA_Init+0x660>)
+ 80330fc:	4293      	cmp	r3, r2
+ 80330fe:	d068      	beq.n	80331d2 <HAL_DMA_Init+0x5c6>
+ 8033100:	687b      	ldr	r3, [r7, #4]
+ 8033102:	681b      	ldr	r3, [r3, #0]
+ 8033104:	4a5a      	ldr	r2, [pc, #360]	@ (8033270 <HAL_DMA_Init+0x664>)
+ 8033106:	4293      	cmp	r3, r2
+ 8033108:	d063      	beq.n	80331d2 <HAL_DMA_Init+0x5c6>
+ 803310a:	687b      	ldr	r3, [r7, #4]
+ 803310c:	681b      	ldr	r3, [r3, #0]
+ 803310e:	4a59      	ldr	r2, [pc, #356]	@ (8033274 <HAL_DMA_Init+0x668>)
+ 8033110:	4293      	cmp	r3, r2
+ 8033112:	d05e      	beq.n	80331d2 <HAL_DMA_Init+0x5c6>
+ 8033114:	687b      	ldr	r3, [r7, #4]
+ 8033116:	681b      	ldr	r3, [r3, #0]
+ 8033118:	4a57      	ldr	r2, [pc, #348]	@ (8033278 <HAL_DMA_Init+0x66c>)
+ 803311a:	4293      	cmp	r3, r2
+ 803311c:	d059      	beq.n	80331d2 <HAL_DMA_Init+0x5c6>
+ 803311e:	687b      	ldr	r3, [r7, #4]
+ 8033120:	681b      	ldr	r3, [r3, #0]
+ 8033122:	4a56      	ldr	r2, [pc, #344]	@ (803327c <HAL_DMA_Init+0x670>)
+ 8033124:	4293      	cmp	r3, r2
+ 8033126:	d054      	beq.n	80331d2 <HAL_DMA_Init+0x5c6>
+ 8033128:	687b      	ldr	r3, [r7, #4]
+ 803312a:	681b      	ldr	r3, [r3, #0]
+ 803312c:	4a54      	ldr	r2, [pc, #336]	@ (8033280 <HAL_DMA_Init+0x674>)
+ 803312e:	4293      	cmp	r3, r2
+ 8033130:	d04f      	beq.n	80331d2 <HAL_DMA_Init+0x5c6>
+ 8033132:	687b      	ldr	r3, [r7, #4]
+ 8033134:	681b      	ldr	r3, [r3, #0]
+ 8033136:	4a53      	ldr	r2, [pc, #332]	@ (8033284 <HAL_DMA_Init+0x678>)
+ 8033138:	4293      	cmp	r3, r2
+ 803313a:	d04a      	beq.n	80331d2 <HAL_DMA_Init+0x5c6>
+ 803313c:	687b      	ldr	r3, [r7, #4]
+ 803313e:	681b      	ldr	r3, [r3, #0]
+ 8033140:	4a51      	ldr	r2, [pc, #324]	@ (8033288 <HAL_DMA_Init+0x67c>)
+ 8033142:	4293      	cmp	r3, r2
+ 8033144:	d045      	beq.n	80331d2 <HAL_DMA_Init+0x5c6>
+ 8033146:	687b      	ldr	r3, [r7, #4]
+ 8033148:	681b      	ldr	r3, [r3, #0]
+ 803314a:	4a50      	ldr	r2, [pc, #320]	@ (803328c <HAL_DMA_Init+0x680>)
+ 803314c:	4293      	cmp	r3, r2
+ 803314e:	d040      	beq.n	80331d2 <HAL_DMA_Init+0x5c6>
+ 8033150:	687b      	ldr	r3, [r7, #4]
+ 8033152:	681b      	ldr	r3, [r3, #0]
+ 8033154:	4a4e      	ldr	r2, [pc, #312]	@ (8033290 <HAL_DMA_Init+0x684>)
+ 8033156:	4293      	cmp	r3, r2
+ 8033158:	d03b      	beq.n	80331d2 <HAL_DMA_Init+0x5c6>
+ 803315a:	687b      	ldr	r3, [r7, #4]
+ 803315c:	681b      	ldr	r3, [r3, #0]
+ 803315e:	4a4d      	ldr	r2, [pc, #308]	@ (8033294 <HAL_DMA_Init+0x688>)
+ 8033160:	4293      	cmp	r3, r2
+ 8033162:	d036      	beq.n	80331d2 <HAL_DMA_Init+0x5c6>
+ 8033164:	687b      	ldr	r3, [r7, #4]
+ 8033166:	681b      	ldr	r3, [r3, #0]
+ 8033168:	4a4b      	ldr	r2, [pc, #300]	@ (8033298 <HAL_DMA_Init+0x68c>)
+ 803316a:	4293      	cmp	r3, r2
+ 803316c:	d031      	beq.n	80331d2 <HAL_DMA_Init+0x5c6>
+ 803316e:	687b      	ldr	r3, [r7, #4]
+ 8033170:	681b      	ldr	r3, [r3, #0]
+ 8033172:	4a4a      	ldr	r2, [pc, #296]	@ (803329c <HAL_DMA_Init+0x690>)
+ 8033174:	4293      	cmp	r3, r2
+ 8033176:	d02c      	beq.n	80331d2 <HAL_DMA_Init+0x5c6>
+ 8033178:	687b      	ldr	r3, [r7, #4]
+ 803317a:	681b      	ldr	r3, [r3, #0]
+ 803317c:	4a48      	ldr	r2, [pc, #288]	@ (80332a0 <HAL_DMA_Init+0x694>)
+ 803317e:	4293      	cmp	r3, r2
+ 8033180:	d027      	beq.n	80331d2 <HAL_DMA_Init+0x5c6>
+ 8033182:	687b      	ldr	r3, [r7, #4]
+ 8033184:	681b      	ldr	r3, [r3, #0]
+ 8033186:	4a47      	ldr	r2, [pc, #284]	@ (80332a4 <HAL_DMA_Init+0x698>)
+ 8033188:	4293      	cmp	r3, r2
+ 803318a:	d022      	beq.n	80331d2 <HAL_DMA_Init+0x5c6>
+ 803318c:	687b      	ldr	r3, [r7, #4]
+ 803318e:	681b      	ldr	r3, [r3, #0]
+ 8033190:	4a45      	ldr	r2, [pc, #276]	@ (80332a8 <HAL_DMA_Init+0x69c>)
+ 8033192:	4293      	cmp	r3, r2
+ 8033194:	d01d      	beq.n	80331d2 <HAL_DMA_Init+0x5c6>
+ 8033196:	687b      	ldr	r3, [r7, #4]
+ 8033198:	681b      	ldr	r3, [r3, #0]
+ 803319a:	4a44      	ldr	r2, [pc, #272]	@ (80332ac <HAL_DMA_Init+0x6a0>)
+ 803319c:	4293      	cmp	r3, r2
+ 803319e:	d018      	beq.n	80331d2 <HAL_DMA_Init+0x5c6>
+ 80331a0:	687b      	ldr	r3, [r7, #4]
+ 80331a2:	681b      	ldr	r3, [r3, #0]
+ 80331a4:	4a42      	ldr	r2, [pc, #264]	@ (80332b0 <HAL_DMA_Init+0x6a4>)
+ 80331a6:	4293      	cmp	r3, r2
+ 80331a8:	d013      	beq.n	80331d2 <HAL_DMA_Init+0x5c6>
+ 80331aa:	687b      	ldr	r3, [r7, #4]
+ 80331ac:	681b      	ldr	r3, [r3, #0]
+ 80331ae:	4a41      	ldr	r2, [pc, #260]	@ (80332b4 <HAL_DMA_Init+0x6a8>)
+ 80331b0:	4293      	cmp	r3, r2
+ 80331b2:	d00e      	beq.n	80331d2 <HAL_DMA_Init+0x5c6>
+ 80331b4:	687b      	ldr	r3, [r7, #4]
+ 80331b6:	681b      	ldr	r3, [r3, #0]
+ 80331b8:	4a3f      	ldr	r2, [pc, #252]	@ (80332b8 <HAL_DMA_Init+0x6ac>)
+ 80331ba:	4293      	cmp	r3, r2
+ 80331bc:	d009      	beq.n	80331d2 <HAL_DMA_Init+0x5c6>
+ 80331be:	687b      	ldr	r3, [r7, #4]
+ 80331c0:	681b      	ldr	r3, [r3, #0]
+ 80331c2:	4a3e      	ldr	r2, [pc, #248]	@ (80332bc <HAL_DMA_Init+0x6b0>)
+ 80331c4:	4293      	cmp	r3, r2
+ 80331c6:	d004      	beq.n	80331d2 <HAL_DMA_Init+0x5c6>
+ 80331c8:	687b      	ldr	r3, [r7, #4]
+ 80331ca:	681b      	ldr	r3, [r3, #0]
+ 80331cc:	4a3c      	ldr	r2, [pc, #240]	@ (80332c0 <HAL_DMA_Init+0x6b4>)
+ 80331ce:	4293      	cmp	r3, r2
+ 80331d0:	d101      	bne.n	80331d6 <HAL_DMA_Init+0x5ca>
+ 80331d2:	2301      	movs	r3, #1
+ 80331d4:	e000      	b.n	80331d8 <HAL_DMA_Init+0x5cc>
+ 80331d6:	2300      	movs	r3, #0
+ 80331d8:	2b00      	cmp	r3, #0
+ 80331da:	d032      	beq.n	8033242 <HAL_DMA_Init+0x636>
+  {
+    /* Initialize parameters for DMAMUX channel :
+    DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask
+    */
+    DMA_CalcDMAMUXChannelBaseAndMask(hdma);
+ 80331dc:	6878      	ldr	r0, [r7, #4]
+ 80331de:	f002 fa51 	bl	8035684 <DMA_CalcDMAMUXChannelBaseAndMask>
+
+    if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
+ 80331e2:	687b      	ldr	r3, [r7, #4]
+ 80331e4:	689b      	ldr	r3, [r3, #8]
+ 80331e6:	2b80      	cmp	r3, #128	@ 0x80
+ 80331e8:	d102      	bne.n	80331f0 <HAL_DMA_Init+0x5e4>
+    {
+      /* if memory to memory force the request to 0*/
+      hdma->Init.Request = DMA_REQUEST_MEM2MEM;
+ 80331ea:	687b      	ldr	r3, [r7, #4]
+ 80331ec:	2200      	movs	r2, #0
+ 80331ee:	605a      	str	r2, [r3, #4]
+    }
+
+    /* Set peripheral request  to DMAMUX channel */
+    hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID);
+ 80331f0:	687b      	ldr	r3, [r7, #4]
+ 80331f2:	685a      	ldr	r2, [r3, #4]
+ 80331f4:	687b      	ldr	r3, [r7, #4]
+ 80331f6:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
+ 80331f8:	b2d2      	uxtb	r2, r2
+ 80331fa:	601a      	str	r2, [r3, #0]
+
+    /* Clear the DMAMUX synchro overrun flag */
+    hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+ 80331fc:	687b      	ldr	r3, [r7, #4]
+ 80331fe:	6e5b      	ldr	r3, [r3, #100]	@ 0x64
+ 8033200:	687a      	ldr	r2, [r7, #4]
+ 8033202:	6e92      	ldr	r2, [r2, #104]	@ 0x68
+ 8033204:	605a      	str	r2, [r3, #4]
+
+    /* Initialize parameters for DMAMUX request generator :
+    if the DMA request is DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR7
+    */
+    if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7))
+ 8033206:	687b      	ldr	r3, [r7, #4]
+ 8033208:	685b      	ldr	r3, [r3, #4]
+ 803320a:	2b00      	cmp	r3, #0
+ 803320c:	d010      	beq.n	8033230 <HAL_DMA_Init+0x624>
+ 803320e:	687b      	ldr	r3, [r7, #4]
+ 8033210:	685b      	ldr	r3, [r3, #4]
+ 8033212:	2b08      	cmp	r3, #8
+ 8033214:	d80c      	bhi.n	8033230 <HAL_DMA_Init+0x624>
+    {
+      /* Initialize parameters for DMAMUX request generator :
+      DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */
+      DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
+ 8033216:	6878      	ldr	r0, [r7, #4]
+ 8033218:	f002 face 	bl	80357b8 <DMA_CalcDMAMUXRequestGenBaseAndMask>
+
+      /* Reset the DMAMUX request generator register */
+      hdma->DMAmuxRequestGen->RGCR = 0U;
+ 803321c:	687b      	ldr	r3, [r7, #4]
+ 803321e:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
+ 8033220:	2200      	movs	r2, #0
+ 8033222:	601a      	str	r2, [r3, #0]
+
+      /* Clear the DMAMUX request generator overrun flag */
+      hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+ 8033224:	687b      	ldr	r3, [r7, #4]
+ 8033226:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
+ 8033228:	687a      	ldr	r2, [r7, #4]
+ 803322a:	6f52      	ldr	r2, [r2, #116]	@ 0x74
+ 803322c:	605a      	str	r2, [r3, #4]
+ 803322e:	e008      	b.n	8033242 <HAL_DMA_Init+0x636>
+    }
+    else
+    {
+      hdma->DMAmuxRequestGen = 0U;
+ 8033230:	687b      	ldr	r3, [r7, #4]
+ 8033232:	2200      	movs	r2, #0
+ 8033234:	66da      	str	r2, [r3, #108]	@ 0x6c
+      hdma->DMAmuxRequestGenStatus = 0U;
+ 8033236:	687b      	ldr	r3, [r7, #4]
+ 8033238:	2200      	movs	r2, #0
+ 803323a:	671a      	str	r2, [r3, #112]	@ 0x70
+      hdma->DMAmuxRequestGenStatusMask = 0U;
+ 803323c:	687b      	ldr	r3, [r7, #4]
+ 803323e:	2200      	movs	r2, #0
+ 8033240:	675a      	str	r2, [r3, #116]	@ 0x74
+    }
+  }
+
+  /* Initialize the error code */
+  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+ 8033242:	687b      	ldr	r3, [r7, #4]
+ 8033244:	2200      	movs	r2, #0
+ 8033246:	655a      	str	r2, [r3, #84]	@ 0x54
+
+  /* Initialize the DMA state */
+  hdma->State = HAL_DMA_STATE_READY;
+ 8033248:	687b      	ldr	r3, [r7, #4]
+ 803324a:	2201      	movs	r2, #1
+ 803324c:	f883 2035 	strb.w	r2, [r3, #53]	@ 0x35
+
+  return HAL_OK;
+ 8033250:	2300      	movs	r3, #0
+}
+ 8033252:	4618      	mov	r0, r3
+ 8033254:	3718      	adds	r7, #24
+ 8033256:	46bd      	mov	sp, r7
+ 8033258:	bd80      	pop	{r7, pc}
+ 803325a:	bf00      	nop
+ 803325c:	a7fdabf8 	.word	0xa7fdabf8
+ 8033260:	cccccccd 	.word	0xcccccccd
+ 8033264:	40020010 	.word	0x40020010
+ 8033268:	40020028 	.word	0x40020028
+ 803326c:	40020040 	.word	0x40020040
+ 8033270:	40020058 	.word	0x40020058
+ 8033274:	40020070 	.word	0x40020070
+ 8033278:	40020088 	.word	0x40020088
+ 803327c:	400200a0 	.word	0x400200a0
+ 8033280:	400200b8 	.word	0x400200b8
+ 8033284:	40020410 	.word	0x40020410
+ 8033288:	40020428 	.word	0x40020428
+ 803328c:	40020440 	.word	0x40020440
+ 8033290:	40020458 	.word	0x40020458
+ 8033294:	40020470 	.word	0x40020470
+ 8033298:	40020488 	.word	0x40020488
+ 803329c:	400204a0 	.word	0x400204a0
+ 80332a0:	400204b8 	.word	0x400204b8
+ 80332a4:	58025408 	.word	0x58025408
+ 80332a8:	5802541c 	.word	0x5802541c
+ 80332ac:	58025430 	.word	0x58025430
+ 80332b0:	58025444 	.word	0x58025444
+ 80332b4:	58025458 	.word	0x58025458
+ 80332b8:	5802546c 	.word	0x5802546c
+ 80332bc:	58025480 	.word	0x58025480
+ 80332c0:	58025494 	.word	0x58025494
+
+080332c4 <HAL_DMA_Start_IT>:
+  * @param  DstAddress: The destination memory Buffer address
+  * @param  DataLength: The length of data to be transferred from source to destination
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+ 80332c4:	b580      	push	{r7, lr}
+ 80332c6:	b086      	sub	sp, #24
+ 80332c8:	af00      	add	r7, sp, #0
+ 80332ca:	60f8      	str	r0, [r7, #12]
+ 80332cc:	60b9      	str	r1, [r7, #8]
+ 80332ce:	607a      	str	r2, [r7, #4]
+ 80332d0:	603b      	str	r3, [r7, #0]
+  HAL_StatusTypeDef status = HAL_OK;
+ 80332d2:	2300      	movs	r3, #0
+ 80332d4:	75fb      	strb	r3, [r7, #23]
+
+  /* Check the parameters */
+  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+
+  /* Check the DMA peripheral handle */
+  if(hdma == NULL)
+ 80332d6:	68fb      	ldr	r3, [r7, #12]
+ 80332d8:	2b00      	cmp	r3, #0
+ 80332da:	d101      	bne.n	80332e0 <HAL_DMA_Start_IT+0x1c>
+  {
+    return HAL_ERROR;
+ 80332dc:	2301      	movs	r3, #1
+ 80332de:	e226      	b.n	803372e <HAL_DMA_Start_IT+0x46a>
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hdma);
+ 80332e0:	68fb      	ldr	r3, [r7, #12]
+ 80332e2:	f893 3034 	ldrb.w	r3, [r3, #52]	@ 0x34
+ 80332e6:	2b01      	cmp	r3, #1
+ 80332e8:	d101      	bne.n	80332ee <HAL_DMA_Start_IT+0x2a>
+ 80332ea:	2302      	movs	r3, #2
+ 80332ec:	e21f      	b.n	803372e <HAL_DMA_Start_IT+0x46a>
+ 80332ee:	68fb      	ldr	r3, [r7, #12]
+ 80332f0:	2201      	movs	r2, #1
+ 80332f2:	f883 2034 	strb.w	r2, [r3, #52]	@ 0x34
+
+  if(HAL_DMA_STATE_READY == hdma->State)
+ 80332f6:	68fb      	ldr	r3, [r7, #12]
+ 80332f8:	f893 3035 	ldrb.w	r3, [r3, #53]	@ 0x35
+ 80332fc:	b2db      	uxtb	r3, r3
+ 80332fe:	2b01      	cmp	r3, #1
+ 8033300:	f040 820a 	bne.w	8033718 <HAL_DMA_Start_IT+0x454>
+  {
+    /* Change DMA peripheral state */
+    hdma->State = HAL_DMA_STATE_BUSY;
+ 8033304:	68fb      	ldr	r3, [r7, #12]
+ 8033306:	2202      	movs	r2, #2
+ 8033308:	f883 2035 	strb.w	r2, [r3, #53]	@ 0x35
+
+    /* Initialize the error code */
+    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+ 803330c:	68fb      	ldr	r3, [r7, #12]
+ 803330e:	2200      	movs	r2, #0
+ 8033310:	655a      	str	r2, [r3, #84]	@ 0x54
+
+    /* Disable the peripheral */
+    __HAL_DMA_DISABLE(hdma);
+ 8033312:	68fb      	ldr	r3, [r7, #12]
+ 8033314:	681b      	ldr	r3, [r3, #0]
+ 8033316:	4a68      	ldr	r2, [pc, #416]	@ (80334b8 <HAL_DMA_Start_IT+0x1f4>)
+ 8033318:	4293      	cmp	r3, r2
+ 803331a:	d04a      	beq.n	80333b2 <HAL_DMA_Start_IT+0xee>
+ 803331c:	68fb      	ldr	r3, [r7, #12]
+ 803331e:	681b      	ldr	r3, [r3, #0]
+ 8033320:	4a66      	ldr	r2, [pc, #408]	@ (80334bc <HAL_DMA_Start_IT+0x1f8>)
+ 8033322:	4293      	cmp	r3, r2
+ 8033324:	d045      	beq.n	80333b2 <HAL_DMA_Start_IT+0xee>
+ 8033326:	68fb      	ldr	r3, [r7, #12]
+ 8033328:	681b      	ldr	r3, [r3, #0]
+ 803332a:	4a65      	ldr	r2, [pc, #404]	@ (80334c0 <HAL_DMA_Start_IT+0x1fc>)
+ 803332c:	4293      	cmp	r3, r2
+ 803332e:	d040      	beq.n	80333b2 <HAL_DMA_Start_IT+0xee>
+ 8033330:	68fb      	ldr	r3, [r7, #12]
+ 8033332:	681b      	ldr	r3, [r3, #0]
+ 8033334:	4a63      	ldr	r2, [pc, #396]	@ (80334c4 <HAL_DMA_Start_IT+0x200>)
+ 8033336:	4293      	cmp	r3, r2
+ 8033338:	d03b      	beq.n	80333b2 <HAL_DMA_Start_IT+0xee>
+ 803333a:	68fb      	ldr	r3, [r7, #12]
+ 803333c:	681b      	ldr	r3, [r3, #0]
+ 803333e:	4a62      	ldr	r2, [pc, #392]	@ (80334c8 <HAL_DMA_Start_IT+0x204>)
+ 8033340:	4293      	cmp	r3, r2
+ 8033342:	d036      	beq.n	80333b2 <HAL_DMA_Start_IT+0xee>
+ 8033344:	68fb      	ldr	r3, [r7, #12]
+ 8033346:	681b      	ldr	r3, [r3, #0]
+ 8033348:	4a60      	ldr	r2, [pc, #384]	@ (80334cc <HAL_DMA_Start_IT+0x208>)
+ 803334a:	4293      	cmp	r3, r2
+ 803334c:	d031      	beq.n	80333b2 <HAL_DMA_Start_IT+0xee>
+ 803334e:	68fb      	ldr	r3, [r7, #12]
+ 8033350:	681b      	ldr	r3, [r3, #0]
+ 8033352:	4a5f      	ldr	r2, [pc, #380]	@ (80334d0 <HAL_DMA_Start_IT+0x20c>)
+ 8033354:	4293      	cmp	r3, r2
+ 8033356:	d02c      	beq.n	80333b2 <HAL_DMA_Start_IT+0xee>
+ 8033358:	68fb      	ldr	r3, [r7, #12]
+ 803335a:	681b      	ldr	r3, [r3, #0]
+ 803335c:	4a5d      	ldr	r2, [pc, #372]	@ (80334d4 <HAL_DMA_Start_IT+0x210>)
+ 803335e:	4293      	cmp	r3, r2
+ 8033360:	d027      	beq.n	80333b2 <HAL_DMA_Start_IT+0xee>
+ 8033362:	68fb      	ldr	r3, [r7, #12]
+ 8033364:	681b      	ldr	r3, [r3, #0]
+ 8033366:	4a5c      	ldr	r2, [pc, #368]	@ (80334d8 <HAL_DMA_Start_IT+0x214>)
+ 8033368:	4293      	cmp	r3, r2
+ 803336a:	d022      	beq.n	80333b2 <HAL_DMA_Start_IT+0xee>
+ 803336c:	68fb      	ldr	r3, [r7, #12]
+ 803336e:	681b      	ldr	r3, [r3, #0]
+ 8033370:	4a5a      	ldr	r2, [pc, #360]	@ (80334dc <HAL_DMA_Start_IT+0x218>)
+ 8033372:	4293      	cmp	r3, r2
+ 8033374:	d01d      	beq.n	80333b2 <HAL_DMA_Start_IT+0xee>
+ 8033376:	68fb      	ldr	r3, [r7, #12]
+ 8033378:	681b      	ldr	r3, [r3, #0]
+ 803337a:	4a59      	ldr	r2, [pc, #356]	@ (80334e0 <HAL_DMA_Start_IT+0x21c>)
+ 803337c:	4293      	cmp	r3, r2
+ 803337e:	d018      	beq.n	80333b2 <HAL_DMA_Start_IT+0xee>
+ 8033380:	68fb      	ldr	r3, [r7, #12]
+ 8033382:	681b      	ldr	r3, [r3, #0]
+ 8033384:	4a57      	ldr	r2, [pc, #348]	@ (80334e4 <HAL_DMA_Start_IT+0x220>)
+ 8033386:	4293      	cmp	r3, r2
+ 8033388:	d013      	beq.n	80333b2 <HAL_DMA_Start_IT+0xee>
+ 803338a:	68fb      	ldr	r3, [r7, #12]
+ 803338c:	681b      	ldr	r3, [r3, #0]
+ 803338e:	4a56      	ldr	r2, [pc, #344]	@ (80334e8 <HAL_DMA_Start_IT+0x224>)
+ 8033390:	4293      	cmp	r3, r2
+ 8033392:	d00e      	beq.n	80333b2 <HAL_DMA_Start_IT+0xee>
+ 8033394:	68fb      	ldr	r3, [r7, #12]
+ 8033396:	681b      	ldr	r3, [r3, #0]
+ 8033398:	4a54      	ldr	r2, [pc, #336]	@ (80334ec <HAL_DMA_Start_IT+0x228>)
+ 803339a:	4293      	cmp	r3, r2
+ 803339c:	d009      	beq.n	80333b2 <HAL_DMA_Start_IT+0xee>
+ 803339e:	68fb      	ldr	r3, [r7, #12]
+ 80333a0:	681b      	ldr	r3, [r3, #0]
+ 80333a2:	4a53      	ldr	r2, [pc, #332]	@ (80334f0 <HAL_DMA_Start_IT+0x22c>)
+ 80333a4:	4293      	cmp	r3, r2
+ 80333a6:	d004      	beq.n	80333b2 <HAL_DMA_Start_IT+0xee>
+ 80333a8:	68fb      	ldr	r3, [r7, #12]
+ 80333aa:	681b      	ldr	r3, [r3, #0]
+ 80333ac:	4a51      	ldr	r2, [pc, #324]	@ (80334f4 <HAL_DMA_Start_IT+0x230>)
+ 80333ae:	4293      	cmp	r3, r2
+ 80333b0:	d108      	bne.n	80333c4 <HAL_DMA_Start_IT+0x100>
+ 80333b2:	68fb      	ldr	r3, [r7, #12]
+ 80333b4:	681b      	ldr	r3, [r3, #0]
+ 80333b6:	681a      	ldr	r2, [r3, #0]
+ 80333b8:	68fb      	ldr	r3, [r7, #12]
+ 80333ba:	681b      	ldr	r3, [r3, #0]
+ 80333bc:	f022 0201 	bic.w	r2, r2, #1
+ 80333c0:	601a      	str	r2, [r3, #0]
+ 80333c2:	e007      	b.n	80333d4 <HAL_DMA_Start_IT+0x110>
+ 80333c4:	68fb      	ldr	r3, [r7, #12]
+ 80333c6:	681b      	ldr	r3, [r3, #0]
+ 80333c8:	681a      	ldr	r2, [r3, #0]
+ 80333ca:	68fb      	ldr	r3, [r7, #12]
+ 80333cc:	681b      	ldr	r3, [r3, #0]
+ 80333ce:	f022 0201 	bic.w	r2, r2, #1
+ 80333d2:	601a      	str	r2, [r3, #0]
+
+    /* Configure the source, destination address and the data length */
+    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+ 80333d4:	683b      	ldr	r3, [r7, #0]
+ 80333d6:	687a      	ldr	r2, [r7, #4]
+ 80333d8:	68b9      	ldr	r1, [r7, #8]
+ 80333da:	68f8      	ldr	r0, [r7, #12]
+ 80333dc:	f001 fe78 	bl	80350d0 <DMA_SetConfig>
+
+    if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+ 80333e0:	68fb      	ldr	r3, [r7, #12]
+ 80333e2:	681b      	ldr	r3, [r3, #0]
+ 80333e4:	4a34      	ldr	r2, [pc, #208]	@ (80334b8 <HAL_DMA_Start_IT+0x1f4>)
+ 80333e6:	4293      	cmp	r3, r2
+ 80333e8:	d04a      	beq.n	8033480 <HAL_DMA_Start_IT+0x1bc>
+ 80333ea:	68fb      	ldr	r3, [r7, #12]
+ 80333ec:	681b      	ldr	r3, [r3, #0]
+ 80333ee:	4a33      	ldr	r2, [pc, #204]	@ (80334bc <HAL_DMA_Start_IT+0x1f8>)
+ 80333f0:	4293      	cmp	r3, r2
+ 80333f2:	d045      	beq.n	8033480 <HAL_DMA_Start_IT+0x1bc>
+ 80333f4:	68fb      	ldr	r3, [r7, #12]
+ 80333f6:	681b      	ldr	r3, [r3, #0]
+ 80333f8:	4a31      	ldr	r2, [pc, #196]	@ (80334c0 <HAL_DMA_Start_IT+0x1fc>)
+ 80333fa:	4293      	cmp	r3, r2
+ 80333fc:	d040      	beq.n	8033480 <HAL_DMA_Start_IT+0x1bc>
+ 80333fe:	68fb      	ldr	r3, [r7, #12]
+ 8033400:	681b      	ldr	r3, [r3, #0]
+ 8033402:	4a30      	ldr	r2, [pc, #192]	@ (80334c4 <HAL_DMA_Start_IT+0x200>)
+ 8033404:	4293      	cmp	r3, r2
+ 8033406:	d03b      	beq.n	8033480 <HAL_DMA_Start_IT+0x1bc>
+ 8033408:	68fb      	ldr	r3, [r7, #12]
+ 803340a:	681b      	ldr	r3, [r3, #0]
+ 803340c:	4a2e      	ldr	r2, [pc, #184]	@ (80334c8 <HAL_DMA_Start_IT+0x204>)
+ 803340e:	4293      	cmp	r3, r2
+ 8033410:	d036      	beq.n	8033480 <HAL_DMA_Start_IT+0x1bc>
+ 8033412:	68fb      	ldr	r3, [r7, #12]
+ 8033414:	681b      	ldr	r3, [r3, #0]
+ 8033416:	4a2d      	ldr	r2, [pc, #180]	@ (80334cc <HAL_DMA_Start_IT+0x208>)
+ 8033418:	4293      	cmp	r3, r2
+ 803341a:	d031      	beq.n	8033480 <HAL_DMA_Start_IT+0x1bc>
+ 803341c:	68fb      	ldr	r3, [r7, #12]
+ 803341e:	681b      	ldr	r3, [r3, #0]
+ 8033420:	4a2b      	ldr	r2, [pc, #172]	@ (80334d0 <HAL_DMA_Start_IT+0x20c>)
+ 8033422:	4293      	cmp	r3, r2
+ 8033424:	d02c      	beq.n	8033480 <HAL_DMA_Start_IT+0x1bc>
+ 8033426:	68fb      	ldr	r3, [r7, #12]
+ 8033428:	681b      	ldr	r3, [r3, #0]
+ 803342a:	4a2a      	ldr	r2, [pc, #168]	@ (80334d4 <HAL_DMA_Start_IT+0x210>)
+ 803342c:	4293      	cmp	r3, r2
+ 803342e:	d027      	beq.n	8033480 <HAL_DMA_Start_IT+0x1bc>
+ 8033430:	68fb      	ldr	r3, [r7, #12]
+ 8033432:	681b      	ldr	r3, [r3, #0]
+ 8033434:	4a28      	ldr	r2, [pc, #160]	@ (80334d8 <HAL_DMA_Start_IT+0x214>)
+ 8033436:	4293      	cmp	r3, r2
+ 8033438:	d022      	beq.n	8033480 <HAL_DMA_Start_IT+0x1bc>
+ 803343a:	68fb      	ldr	r3, [r7, #12]
+ 803343c:	681b      	ldr	r3, [r3, #0]
+ 803343e:	4a27      	ldr	r2, [pc, #156]	@ (80334dc <HAL_DMA_Start_IT+0x218>)
+ 8033440:	4293      	cmp	r3, r2
+ 8033442:	d01d      	beq.n	8033480 <HAL_DMA_Start_IT+0x1bc>
+ 8033444:	68fb      	ldr	r3, [r7, #12]
+ 8033446:	681b      	ldr	r3, [r3, #0]
+ 8033448:	4a25      	ldr	r2, [pc, #148]	@ (80334e0 <HAL_DMA_Start_IT+0x21c>)
+ 803344a:	4293      	cmp	r3, r2
+ 803344c:	d018      	beq.n	8033480 <HAL_DMA_Start_IT+0x1bc>
+ 803344e:	68fb      	ldr	r3, [r7, #12]
+ 8033450:	681b      	ldr	r3, [r3, #0]
+ 8033452:	4a24      	ldr	r2, [pc, #144]	@ (80334e4 <HAL_DMA_Start_IT+0x220>)
+ 8033454:	4293      	cmp	r3, r2
+ 8033456:	d013      	beq.n	8033480 <HAL_DMA_Start_IT+0x1bc>
+ 8033458:	68fb      	ldr	r3, [r7, #12]
+ 803345a:	681b      	ldr	r3, [r3, #0]
+ 803345c:	4a22      	ldr	r2, [pc, #136]	@ (80334e8 <HAL_DMA_Start_IT+0x224>)
+ 803345e:	4293      	cmp	r3, r2
+ 8033460:	d00e      	beq.n	8033480 <HAL_DMA_Start_IT+0x1bc>
+ 8033462:	68fb      	ldr	r3, [r7, #12]
+ 8033464:	681b      	ldr	r3, [r3, #0]
+ 8033466:	4a21      	ldr	r2, [pc, #132]	@ (80334ec <HAL_DMA_Start_IT+0x228>)
+ 8033468:	4293      	cmp	r3, r2
+ 803346a:	d009      	beq.n	8033480 <HAL_DMA_Start_IT+0x1bc>
+ 803346c:	68fb      	ldr	r3, [r7, #12]
+ 803346e:	681b      	ldr	r3, [r3, #0]
+ 8033470:	4a1f      	ldr	r2, [pc, #124]	@ (80334f0 <HAL_DMA_Start_IT+0x22c>)
+ 8033472:	4293      	cmp	r3, r2
+ 8033474:	d004      	beq.n	8033480 <HAL_DMA_Start_IT+0x1bc>
+ 8033476:	68fb      	ldr	r3, [r7, #12]
+ 8033478:	681b      	ldr	r3, [r3, #0]
+ 803347a:	4a1e      	ldr	r2, [pc, #120]	@ (80334f4 <HAL_DMA_Start_IT+0x230>)
+ 803347c:	4293      	cmp	r3, r2
+ 803347e:	d101      	bne.n	8033484 <HAL_DMA_Start_IT+0x1c0>
+ 8033480:	2301      	movs	r3, #1
+ 8033482:	e000      	b.n	8033486 <HAL_DMA_Start_IT+0x1c2>
+ 8033484:	2300      	movs	r3, #0
+ 8033486:	2b00      	cmp	r3, #0
+ 8033488:	d036      	beq.n	80334f8 <HAL_DMA_Start_IT+0x234>
+    {
+      /* Enable Common interrupts*/
+      MODIFY_REG(((DMA_Stream_TypeDef   *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME));
+ 803348a:	68fb      	ldr	r3, [r7, #12]
+ 803348c:	681b      	ldr	r3, [r3, #0]
+ 803348e:	681b      	ldr	r3, [r3, #0]
+ 8033490:	f023 021e 	bic.w	r2, r3, #30
+ 8033494:	68fb      	ldr	r3, [r7, #12]
+ 8033496:	681b      	ldr	r3, [r3, #0]
+ 8033498:	f042 0216 	orr.w	r2, r2, #22
+ 803349c:	601a      	str	r2, [r3, #0]
+
+      if(hdma->XferHalfCpltCallback != NULL)
+ 803349e:	68fb      	ldr	r3, [r7, #12]
+ 80334a0:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
+ 80334a2:	2b00      	cmp	r3, #0
+ 80334a4:	d03e      	beq.n	8033524 <HAL_DMA_Start_IT+0x260>
+      {
+        /* Enable Half Transfer IT if corresponding Callback is set */
+        ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  |= DMA_IT_HT;
+ 80334a6:	68fb      	ldr	r3, [r7, #12]
+ 80334a8:	681b      	ldr	r3, [r3, #0]
+ 80334aa:	681a      	ldr	r2, [r3, #0]
+ 80334ac:	68fb      	ldr	r3, [r7, #12]
+ 80334ae:	681b      	ldr	r3, [r3, #0]
+ 80334b0:	f042 0208 	orr.w	r2, r2, #8
+ 80334b4:	601a      	str	r2, [r3, #0]
+ 80334b6:	e035      	b.n	8033524 <HAL_DMA_Start_IT+0x260>
+ 80334b8:	40020010 	.word	0x40020010
+ 80334bc:	40020028 	.word	0x40020028
+ 80334c0:	40020040 	.word	0x40020040
+ 80334c4:	40020058 	.word	0x40020058
+ 80334c8:	40020070 	.word	0x40020070
+ 80334cc:	40020088 	.word	0x40020088
+ 80334d0:	400200a0 	.word	0x400200a0
+ 80334d4:	400200b8 	.word	0x400200b8
+ 80334d8:	40020410 	.word	0x40020410
+ 80334dc:	40020428 	.word	0x40020428
+ 80334e0:	40020440 	.word	0x40020440
+ 80334e4:	40020458 	.word	0x40020458
+ 80334e8:	40020470 	.word	0x40020470
+ 80334ec:	40020488 	.word	0x40020488
+ 80334f0:	400204a0 	.word	0x400204a0
+ 80334f4:	400204b8 	.word	0x400204b8
+      }
+    }
+    else /* BDMA channel */
+    {
+      /* Enable Common interrupts */
+      MODIFY_REG(((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR, (BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE), (BDMA_CCR_TCIE | BDMA_CCR_TEIE));
+ 80334f8:	68fb      	ldr	r3, [r7, #12]
+ 80334fa:	681b      	ldr	r3, [r3, #0]
+ 80334fc:	681b      	ldr	r3, [r3, #0]
+ 80334fe:	f023 020e 	bic.w	r2, r3, #14
+ 8033502:	68fb      	ldr	r3, [r7, #12]
+ 8033504:	681b      	ldr	r3, [r3, #0]
+ 8033506:	f042 020a 	orr.w	r2, r2, #10
+ 803350a:	601a      	str	r2, [r3, #0]
+
+      if(hdma->XferHalfCpltCallback != NULL)
+ 803350c:	68fb      	ldr	r3, [r7, #12]
+ 803350e:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
+ 8033510:	2b00      	cmp	r3, #0
+ 8033512:	d007      	beq.n	8033524 <HAL_DMA_Start_IT+0x260>
+      {
+        /*Enable Half Transfer IT if corresponding Callback is set */
+        ((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR  |= BDMA_CCR_HTIE;
+ 8033514:	68fb      	ldr	r3, [r7, #12]
+ 8033516:	681b      	ldr	r3, [r3, #0]
+ 8033518:	681a      	ldr	r2, [r3, #0]
+ 803351a:	68fb      	ldr	r3, [r7, #12]
+ 803351c:	681b      	ldr	r3, [r3, #0]
+ 803351e:	f042 0204 	orr.w	r2, r2, #4
+ 8033522:	601a      	str	r2, [r3, #0]
+      }
+    }
+
+    if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
+ 8033524:	68fb      	ldr	r3, [r7, #12]
+ 8033526:	681b      	ldr	r3, [r3, #0]
+ 8033528:	4a83      	ldr	r2, [pc, #524]	@ (8033738 <HAL_DMA_Start_IT+0x474>)
+ 803352a:	4293      	cmp	r3, r2
+ 803352c:	d072      	beq.n	8033614 <HAL_DMA_Start_IT+0x350>
+ 803352e:	68fb      	ldr	r3, [r7, #12]
+ 8033530:	681b      	ldr	r3, [r3, #0]
+ 8033532:	4a82      	ldr	r2, [pc, #520]	@ (803373c <HAL_DMA_Start_IT+0x478>)
+ 8033534:	4293      	cmp	r3, r2
+ 8033536:	d06d      	beq.n	8033614 <HAL_DMA_Start_IT+0x350>
+ 8033538:	68fb      	ldr	r3, [r7, #12]
+ 803353a:	681b      	ldr	r3, [r3, #0]
+ 803353c:	4a80      	ldr	r2, [pc, #512]	@ (8033740 <HAL_DMA_Start_IT+0x47c>)
+ 803353e:	4293      	cmp	r3, r2
+ 8033540:	d068      	beq.n	8033614 <HAL_DMA_Start_IT+0x350>
+ 8033542:	68fb      	ldr	r3, [r7, #12]
+ 8033544:	681b      	ldr	r3, [r3, #0]
+ 8033546:	4a7f      	ldr	r2, [pc, #508]	@ (8033744 <HAL_DMA_Start_IT+0x480>)
+ 8033548:	4293      	cmp	r3, r2
+ 803354a:	d063      	beq.n	8033614 <HAL_DMA_Start_IT+0x350>
+ 803354c:	68fb      	ldr	r3, [r7, #12]
+ 803354e:	681b      	ldr	r3, [r3, #0]
+ 8033550:	4a7d      	ldr	r2, [pc, #500]	@ (8033748 <HAL_DMA_Start_IT+0x484>)
+ 8033552:	4293      	cmp	r3, r2
+ 8033554:	d05e      	beq.n	8033614 <HAL_DMA_Start_IT+0x350>
+ 8033556:	68fb      	ldr	r3, [r7, #12]
+ 8033558:	681b      	ldr	r3, [r3, #0]
+ 803355a:	4a7c      	ldr	r2, [pc, #496]	@ (803374c <HAL_DMA_Start_IT+0x488>)
+ 803355c:	4293      	cmp	r3, r2
+ 803355e:	d059      	beq.n	8033614 <HAL_DMA_Start_IT+0x350>
+ 8033560:	68fb      	ldr	r3, [r7, #12]
+ 8033562:	681b      	ldr	r3, [r3, #0]
+ 8033564:	4a7a      	ldr	r2, [pc, #488]	@ (8033750 <HAL_DMA_Start_IT+0x48c>)
+ 8033566:	4293      	cmp	r3, r2
+ 8033568:	d054      	beq.n	8033614 <HAL_DMA_Start_IT+0x350>
+ 803356a:	68fb      	ldr	r3, [r7, #12]
+ 803356c:	681b      	ldr	r3, [r3, #0]
+ 803356e:	4a79      	ldr	r2, [pc, #484]	@ (8033754 <HAL_DMA_Start_IT+0x490>)
+ 8033570:	4293      	cmp	r3, r2
+ 8033572:	d04f      	beq.n	8033614 <HAL_DMA_Start_IT+0x350>
+ 8033574:	68fb      	ldr	r3, [r7, #12]
+ 8033576:	681b      	ldr	r3, [r3, #0]
+ 8033578:	4a77      	ldr	r2, [pc, #476]	@ (8033758 <HAL_DMA_Start_IT+0x494>)
+ 803357a:	4293      	cmp	r3, r2
+ 803357c:	d04a      	beq.n	8033614 <HAL_DMA_Start_IT+0x350>
+ 803357e:	68fb      	ldr	r3, [r7, #12]
+ 8033580:	681b      	ldr	r3, [r3, #0]
+ 8033582:	4a76      	ldr	r2, [pc, #472]	@ (803375c <HAL_DMA_Start_IT+0x498>)
+ 8033584:	4293      	cmp	r3, r2
+ 8033586:	d045      	beq.n	8033614 <HAL_DMA_Start_IT+0x350>
+ 8033588:	68fb      	ldr	r3, [r7, #12]
+ 803358a:	681b      	ldr	r3, [r3, #0]
+ 803358c:	4a74      	ldr	r2, [pc, #464]	@ (8033760 <HAL_DMA_Start_IT+0x49c>)
+ 803358e:	4293      	cmp	r3, r2
+ 8033590:	d040      	beq.n	8033614 <HAL_DMA_Start_IT+0x350>
+ 8033592:	68fb      	ldr	r3, [r7, #12]
+ 8033594:	681b      	ldr	r3, [r3, #0]
+ 8033596:	4a73      	ldr	r2, [pc, #460]	@ (8033764 <HAL_DMA_Start_IT+0x4a0>)
+ 8033598:	4293      	cmp	r3, r2
+ 803359a:	d03b      	beq.n	8033614 <HAL_DMA_Start_IT+0x350>
+ 803359c:	68fb      	ldr	r3, [r7, #12]
+ 803359e:	681b      	ldr	r3, [r3, #0]
+ 80335a0:	4a71      	ldr	r2, [pc, #452]	@ (8033768 <HAL_DMA_Start_IT+0x4a4>)
+ 80335a2:	4293      	cmp	r3, r2
+ 80335a4:	d036      	beq.n	8033614 <HAL_DMA_Start_IT+0x350>
+ 80335a6:	68fb      	ldr	r3, [r7, #12]
+ 80335a8:	681b      	ldr	r3, [r3, #0]
+ 80335aa:	4a70      	ldr	r2, [pc, #448]	@ (803376c <HAL_DMA_Start_IT+0x4a8>)
+ 80335ac:	4293      	cmp	r3, r2
+ 80335ae:	d031      	beq.n	8033614 <HAL_DMA_Start_IT+0x350>
+ 80335b0:	68fb      	ldr	r3, [r7, #12]
+ 80335b2:	681b      	ldr	r3, [r3, #0]
+ 80335b4:	4a6e      	ldr	r2, [pc, #440]	@ (8033770 <HAL_DMA_Start_IT+0x4ac>)
+ 80335b6:	4293      	cmp	r3, r2
+ 80335b8:	d02c      	beq.n	8033614 <HAL_DMA_Start_IT+0x350>
+ 80335ba:	68fb      	ldr	r3, [r7, #12]
+ 80335bc:	681b      	ldr	r3, [r3, #0]
+ 80335be:	4a6d      	ldr	r2, [pc, #436]	@ (8033774 <HAL_DMA_Start_IT+0x4b0>)
+ 80335c0:	4293      	cmp	r3, r2
+ 80335c2:	d027      	beq.n	8033614 <HAL_DMA_Start_IT+0x350>
+ 80335c4:	68fb      	ldr	r3, [r7, #12]
+ 80335c6:	681b      	ldr	r3, [r3, #0]
+ 80335c8:	4a6b      	ldr	r2, [pc, #428]	@ (8033778 <HAL_DMA_Start_IT+0x4b4>)
+ 80335ca:	4293      	cmp	r3, r2
+ 80335cc:	d022      	beq.n	8033614 <HAL_DMA_Start_IT+0x350>
+ 80335ce:	68fb      	ldr	r3, [r7, #12]
+ 80335d0:	681b      	ldr	r3, [r3, #0]
+ 80335d2:	4a6a      	ldr	r2, [pc, #424]	@ (803377c <HAL_DMA_Start_IT+0x4b8>)
+ 80335d4:	4293      	cmp	r3, r2
+ 80335d6:	d01d      	beq.n	8033614 <HAL_DMA_Start_IT+0x350>
+ 80335d8:	68fb      	ldr	r3, [r7, #12]
+ 80335da:	681b      	ldr	r3, [r3, #0]
+ 80335dc:	4a68      	ldr	r2, [pc, #416]	@ (8033780 <HAL_DMA_Start_IT+0x4bc>)
+ 80335de:	4293      	cmp	r3, r2
+ 80335e0:	d018      	beq.n	8033614 <HAL_DMA_Start_IT+0x350>
+ 80335e2:	68fb      	ldr	r3, [r7, #12]
+ 80335e4:	681b      	ldr	r3, [r3, #0]
+ 80335e6:	4a67      	ldr	r2, [pc, #412]	@ (8033784 <HAL_DMA_Start_IT+0x4c0>)
+ 80335e8:	4293      	cmp	r3, r2
+ 80335ea:	d013      	beq.n	8033614 <HAL_DMA_Start_IT+0x350>
+ 80335ec:	68fb      	ldr	r3, [r7, #12]
+ 80335ee:	681b      	ldr	r3, [r3, #0]
+ 80335f0:	4a65      	ldr	r2, [pc, #404]	@ (8033788 <HAL_DMA_Start_IT+0x4c4>)
+ 80335f2:	4293      	cmp	r3, r2
+ 80335f4:	d00e      	beq.n	8033614 <HAL_DMA_Start_IT+0x350>
+ 80335f6:	68fb      	ldr	r3, [r7, #12]
+ 80335f8:	681b      	ldr	r3, [r3, #0]
+ 80335fa:	4a64      	ldr	r2, [pc, #400]	@ (803378c <HAL_DMA_Start_IT+0x4c8>)
+ 80335fc:	4293      	cmp	r3, r2
+ 80335fe:	d009      	beq.n	8033614 <HAL_DMA_Start_IT+0x350>
+ 8033600:	68fb      	ldr	r3, [r7, #12]
+ 8033602:	681b      	ldr	r3, [r3, #0]
+ 8033604:	4a62      	ldr	r2, [pc, #392]	@ (8033790 <HAL_DMA_Start_IT+0x4cc>)
+ 8033606:	4293      	cmp	r3, r2
+ 8033608:	d004      	beq.n	8033614 <HAL_DMA_Start_IT+0x350>
+ 803360a:	68fb      	ldr	r3, [r7, #12]
+ 803360c:	681b      	ldr	r3, [r3, #0]
+ 803360e:	4a61      	ldr	r2, [pc, #388]	@ (8033794 <HAL_DMA_Start_IT+0x4d0>)
+ 8033610:	4293      	cmp	r3, r2
+ 8033612:	d101      	bne.n	8033618 <HAL_DMA_Start_IT+0x354>
+ 8033614:	2301      	movs	r3, #1
+ 8033616:	e000      	b.n	803361a <HAL_DMA_Start_IT+0x356>
+ 8033618:	2300      	movs	r3, #0
+ 803361a:	2b00      	cmp	r3, #0
+ 803361c:	d01a      	beq.n	8033654 <HAL_DMA_Start_IT+0x390>
+    {
+      /* Check if DMAMUX Synchronization is enabled */
+      if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
+ 803361e:	68fb      	ldr	r3, [r7, #12]
+ 8033620:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
+ 8033622:	681b      	ldr	r3, [r3, #0]
+ 8033624:	f403 3380 	and.w	r3, r3, #65536	@ 0x10000
+ 8033628:	2b00      	cmp	r3, #0
+ 803362a:	d007      	beq.n	803363c <HAL_DMA_Start_IT+0x378>
+      {
+        /* Enable DMAMUX sync overrun IT*/
+        hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
+ 803362c:	68fb      	ldr	r3, [r7, #12]
+ 803362e:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
+ 8033630:	681a      	ldr	r2, [r3, #0]
+ 8033632:	68fb      	ldr	r3, [r7, #12]
+ 8033634:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
+ 8033636:	f442 7280 	orr.w	r2, r2, #256	@ 0x100
+ 803363a:	601a      	str	r2, [r3, #0]
+      }
+
+      if(hdma->DMAmuxRequestGen != 0U)
+ 803363c:	68fb      	ldr	r3, [r7, #12]
+ 803363e:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
+ 8033640:	2b00      	cmp	r3, #0
+ 8033642:	d007      	beq.n	8033654 <HAL_DMA_Start_IT+0x390>
+      {
+        /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/
+        /* enable the request gen overrun IT */
+        hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
+ 8033644:	68fb      	ldr	r3, [r7, #12]
+ 8033646:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
+ 8033648:	681a      	ldr	r2, [r3, #0]
+ 803364a:	68fb      	ldr	r3, [r7, #12]
+ 803364c:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
+ 803364e:	f442 7280 	orr.w	r2, r2, #256	@ 0x100
+ 8033652:	601a      	str	r2, [r3, #0]
+      }
+    }
+
+    /* Enable the Peripheral */
+    __HAL_DMA_ENABLE(hdma);
+ 8033654:	68fb      	ldr	r3, [r7, #12]
+ 8033656:	681b      	ldr	r3, [r3, #0]
+ 8033658:	4a37      	ldr	r2, [pc, #220]	@ (8033738 <HAL_DMA_Start_IT+0x474>)
+ 803365a:	4293      	cmp	r3, r2
+ 803365c:	d04a      	beq.n	80336f4 <HAL_DMA_Start_IT+0x430>
+ 803365e:	68fb      	ldr	r3, [r7, #12]
+ 8033660:	681b      	ldr	r3, [r3, #0]
+ 8033662:	4a36      	ldr	r2, [pc, #216]	@ (803373c <HAL_DMA_Start_IT+0x478>)
+ 8033664:	4293      	cmp	r3, r2
+ 8033666:	d045      	beq.n	80336f4 <HAL_DMA_Start_IT+0x430>
+ 8033668:	68fb      	ldr	r3, [r7, #12]
+ 803366a:	681b      	ldr	r3, [r3, #0]
+ 803366c:	4a34      	ldr	r2, [pc, #208]	@ (8033740 <HAL_DMA_Start_IT+0x47c>)
+ 803366e:	4293      	cmp	r3, r2
+ 8033670:	d040      	beq.n	80336f4 <HAL_DMA_Start_IT+0x430>
+ 8033672:	68fb      	ldr	r3, [r7, #12]
+ 8033674:	681b      	ldr	r3, [r3, #0]
+ 8033676:	4a33      	ldr	r2, [pc, #204]	@ (8033744 <HAL_DMA_Start_IT+0x480>)
+ 8033678:	4293      	cmp	r3, r2
+ 803367a:	d03b      	beq.n	80336f4 <HAL_DMA_Start_IT+0x430>
+ 803367c:	68fb      	ldr	r3, [r7, #12]
+ 803367e:	681b      	ldr	r3, [r3, #0]
+ 8033680:	4a31      	ldr	r2, [pc, #196]	@ (8033748 <HAL_DMA_Start_IT+0x484>)
+ 8033682:	4293      	cmp	r3, r2
+ 8033684:	d036      	beq.n	80336f4 <HAL_DMA_Start_IT+0x430>
+ 8033686:	68fb      	ldr	r3, [r7, #12]
+ 8033688:	681b      	ldr	r3, [r3, #0]
+ 803368a:	4a30      	ldr	r2, [pc, #192]	@ (803374c <HAL_DMA_Start_IT+0x488>)
+ 803368c:	4293      	cmp	r3, r2
+ 803368e:	d031      	beq.n	80336f4 <HAL_DMA_Start_IT+0x430>
+ 8033690:	68fb      	ldr	r3, [r7, #12]
+ 8033692:	681b      	ldr	r3, [r3, #0]
+ 8033694:	4a2e      	ldr	r2, [pc, #184]	@ (8033750 <HAL_DMA_Start_IT+0x48c>)
+ 8033696:	4293      	cmp	r3, r2
+ 8033698:	d02c      	beq.n	80336f4 <HAL_DMA_Start_IT+0x430>
+ 803369a:	68fb      	ldr	r3, [r7, #12]
+ 803369c:	681b      	ldr	r3, [r3, #0]
+ 803369e:	4a2d      	ldr	r2, [pc, #180]	@ (8033754 <HAL_DMA_Start_IT+0x490>)
+ 80336a0:	4293      	cmp	r3, r2
+ 80336a2:	d027      	beq.n	80336f4 <HAL_DMA_Start_IT+0x430>
+ 80336a4:	68fb      	ldr	r3, [r7, #12]
+ 80336a6:	681b      	ldr	r3, [r3, #0]
+ 80336a8:	4a2b      	ldr	r2, [pc, #172]	@ (8033758 <HAL_DMA_Start_IT+0x494>)
+ 80336aa:	4293      	cmp	r3, r2
+ 80336ac:	d022      	beq.n	80336f4 <HAL_DMA_Start_IT+0x430>
+ 80336ae:	68fb      	ldr	r3, [r7, #12]
+ 80336b0:	681b      	ldr	r3, [r3, #0]
+ 80336b2:	4a2a      	ldr	r2, [pc, #168]	@ (803375c <HAL_DMA_Start_IT+0x498>)
+ 80336b4:	4293      	cmp	r3, r2
+ 80336b6:	d01d      	beq.n	80336f4 <HAL_DMA_Start_IT+0x430>
+ 80336b8:	68fb      	ldr	r3, [r7, #12]
+ 80336ba:	681b      	ldr	r3, [r3, #0]
+ 80336bc:	4a28      	ldr	r2, [pc, #160]	@ (8033760 <HAL_DMA_Start_IT+0x49c>)
+ 80336be:	4293      	cmp	r3, r2
+ 80336c0:	d018      	beq.n	80336f4 <HAL_DMA_Start_IT+0x430>
+ 80336c2:	68fb      	ldr	r3, [r7, #12]
+ 80336c4:	681b      	ldr	r3, [r3, #0]
+ 80336c6:	4a27      	ldr	r2, [pc, #156]	@ (8033764 <HAL_DMA_Start_IT+0x4a0>)
+ 80336c8:	4293      	cmp	r3, r2
+ 80336ca:	d013      	beq.n	80336f4 <HAL_DMA_Start_IT+0x430>
+ 80336cc:	68fb      	ldr	r3, [r7, #12]
+ 80336ce:	681b      	ldr	r3, [r3, #0]
+ 80336d0:	4a25      	ldr	r2, [pc, #148]	@ (8033768 <HAL_DMA_Start_IT+0x4a4>)
+ 80336d2:	4293      	cmp	r3, r2
+ 80336d4:	d00e      	beq.n	80336f4 <HAL_DMA_Start_IT+0x430>
+ 80336d6:	68fb      	ldr	r3, [r7, #12]
+ 80336d8:	681b      	ldr	r3, [r3, #0]
+ 80336da:	4a24      	ldr	r2, [pc, #144]	@ (803376c <HAL_DMA_Start_IT+0x4a8>)
+ 80336dc:	4293      	cmp	r3, r2
+ 80336de:	d009      	beq.n	80336f4 <HAL_DMA_Start_IT+0x430>
+ 80336e0:	68fb      	ldr	r3, [r7, #12]
+ 80336e2:	681b      	ldr	r3, [r3, #0]
+ 80336e4:	4a22      	ldr	r2, [pc, #136]	@ (8033770 <HAL_DMA_Start_IT+0x4ac>)
+ 80336e6:	4293      	cmp	r3, r2
+ 80336e8:	d004      	beq.n	80336f4 <HAL_DMA_Start_IT+0x430>
+ 80336ea:	68fb      	ldr	r3, [r7, #12]
+ 80336ec:	681b      	ldr	r3, [r3, #0]
+ 80336ee:	4a21      	ldr	r2, [pc, #132]	@ (8033774 <HAL_DMA_Start_IT+0x4b0>)
+ 80336f0:	4293      	cmp	r3, r2
+ 80336f2:	d108      	bne.n	8033706 <HAL_DMA_Start_IT+0x442>
+ 80336f4:	68fb      	ldr	r3, [r7, #12]
+ 80336f6:	681b      	ldr	r3, [r3, #0]
+ 80336f8:	681a      	ldr	r2, [r3, #0]
+ 80336fa:	68fb      	ldr	r3, [r7, #12]
+ 80336fc:	681b      	ldr	r3, [r3, #0]
+ 80336fe:	f042 0201 	orr.w	r2, r2, #1
+ 8033702:	601a      	str	r2, [r3, #0]
+ 8033704:	e012      	b.n	803372c <HAL_DMA_Start_IT+0x468>
+ 8033706:	68fb      	ldr	r3, [r7, #12]
+ 8033708:	681b      	ldr	r3, [r3, #0]
+ 803370a:	681a      	ldr	r2, [r3, #0]
+ 803370c:	68fb      	ldr	r3, [r7, #12]
+ 803370e:	681b      	ldr	r3, [r3, #0]
+ 8033710:	f042 0201 	orr.w	r2, r2, #1
+ 8033714:	601a      	str	r2, [r3, #0]
+ 8033716:	e009      	b.n	803372c <HAL_DMA_Start_IT+0x468>
+  }
+  else
+  {
+    /* Set the error code to busy */
+    hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
+ 8033718:	68fb      	ldr	r3, [r7, #12]
+ 803371a:	f44f 6200 	mov.w	r2, #2048	@ 0x800
+ 803371e:	655a      	str	r2, [r3, #84]	@ 0x54
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hdma);
+ 8033720:	68fb      	ldr	r3, [r7, #12]
+ 8033722:	2200      	movs	r2, #0
+ 8033724:	f883 2034 	strb.w	r2, [r3, #52]	@ 0x34
+
+    /* Return error status */
+    status = HAL_ERROR;
+ 8033728:	2301      	movs	r3, #1
+ 803372a:	75fb      	strb	r3, [r7, #23]
+  }
+
+  return status;
+ 803372c:	7dfb      	ldrb	r3, [r7, #23]
+}
+ 803372e:	4618      	mov	r0, r3
+ 8033730:	3718      	adds	r7, #24
+ 8033732:	46bd      	mov	sp, r7
+ 8033734:	bd80      	pop	{r7, pc}
+ 8033736:	bf00      	nop
+ 8033738:	40020010 	.word	0x40020010
+ 803373c:	40020028 	.word	0x40020028
+ 8033740:	40020040 	.word	0x40020040
+ 8033744:	40020058 	.word	0x40020058
+ 8033748:	40020070 	.word	0x40020070
+ 803374c:	40020088 	.word	0x40020088
+ 8033750:	400200a0 	.word	0x400200a0
+ 8033754:	400200b8 	.word	0x400200b8
+ 8033758:	40020410 	.word	0x40020410
+ 803375c:	40020428 	.word	0x40020428
+ 8033760:	40020440 	.word	0x40020440
+ 8033764:	40020458 	.word	0x40020458
+ 8033768:	40020470 	.word	0x40020470
+ 803376c:	40020488 	.word	0x40020488
+ 8033770:	400204a0 	.word	0x400204a0
+ 8033774:	400204b8 	.word	0x400204b8
+ 8033778:	58025408 	.word	0x58025408
+ 803377c:	5802541c 	.word	0x5802541c
+ 8033780:	58025430 	.word	0x58025430
+ 8033784:	58025444 	.word	0x58025444
+ 8033788:	58025458 	.word	0x58025458
+ 803378c:	5802546c 	.word	0x5802546c
+ 8033790:	58025480 	.word	0x58025480
+ 8033794:	58025494 	.word	0x58025494
+
+08033798 <HAL_DMA_Abort>:
+  *        and the Stream will be effectively disabled only after the transfer of
+  *        this single data is finished.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
+{
+ 8033798:	b580      	push	{r7, lr}
+ 803379a:	b086      	sub	sp, #24
+ 803379c:	af00      	add	r7, sp, #0
+ 803379e:	6078      	str	r0, [r7, #4]
+  /* calculate DMA base and stream number */
+  DMA_Base_Registers *regs_dma;
+  BDMA_Base_Registers *regs_bdma;
+  const __IO uint32_t *enableRegister;
+
+  uint32_t tickstart = HAL_GetTick();
+ 80337a0:	f7fe f8c6 	bl	8031930 <HAL_GetTick>
+ 80337a4:	6138      	str	r0, [r7, #16]
+
+ /* Check the DMA peripheral handle */
+  if(hdma == NULL)
+ 80337a6:	687b      	ldr	r3, [r7, #4]
+ 80337a8:	2b00      	cmp	r3, #0
+ 80337aa:	d101      	bne.n	80337b0 <HAL_DMA_Abort+0x18>
+  {
+    return HAL_ERROR;
+ 80337ac:	2301      	movs	r3, #1
+ 80337ae:	e2dc      	b.n	8033d6a <HAL_DMA_Abort+0x5d2>
+  }
+
+  /* Check the DMA peripheral state */
+  if(hdma->State != HAL_DMA_STATE_BUSY)
+ 80337b0:	687b      	ldr	r3, [r7, #4]
+ 80337b2:	f893 3035 	ldrb.w	r3, [r3, #53]	@ 0x35
+ 80337b6:	b2db      	uxtb	r3, r3
+ 80337b8:	2b02      	cmp	r3, #2
+ 80337ba:	d008      	beq.n	80337ce <HAL_DMA_Abort+0x36>
+  {
+    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+ 80337bc:	687b      	ldr	r3, [r7, #4]
+ 80337be:	2280      	movs	r2, #128	@ 0x80
+ 80337c0:	655a      	str	r2, [r3, #84]	@ 0x54
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
+ 80337c2:	687b      	ldr	r3, [r7, #4]
+ 80337c4:	2200      	movs	r2, #0
+ 80337c6:	f883 2034 	strb.w	r2, [r3, #52]	@ 0x34
+
+    return HAL_ERROR;
+ 80337ca:	2301      	movs	r3, #1
+ 80337cc:	e2cd      	b.n	8033d6a <HAL_DMA_Abort+0x5d2>
+  }
+  else
+  {
+    /* Disable all the transfer interrupts */
+    if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+ 80337ce:	687b      	ldr	r3, [r7, #4]
+ 80337d0:	681b      	ldr	r3, [r3, #0]
+ 80337d2:	4a76      	ldr	r2, [pc, #472]	@ (80339ac <HAL_DMA_Abort+0x214>)
+ 80337d4:	4293      	cmp	r3, r2
+ 80337d6:	d04a      	beq.n	803386e <HAL_DMA_Abort+0xd6>
+ 80337d8:	687b      	ldr	r3, [r7, #4]
+ 80337da:	681b      	ldr	r3, [r3, #0]
+ 80337dc:	4a74      	ldr	r2, [pc, #464]	@ (80339b0 <HAL_DMA_Abort+0x218>)
+ 80337de:	4293      	cmp	r3, r2
+ 80337e0:	d045      	beq.n	803386e <HAL_DMA_Abort+0xd6>
+ 80337e2:	687b      	ldr	r3, [r7, #4]
+ 80337e4:	681b      	ldr	r3, [r3, #0]
+ 80337e6:	4a73      	ldr	r2, [pc, #460]	@ (80339b4 <HAL_DMA_Abort+0x21c>)
+ 80337e8:	4293      	cmp	r3, r2
+ 80337ea:	d040      	beq.n	803386e <HAL_DMA_Abort+0xd6>
+ 80337ec:	687b      	ldr	r3, [r7, #4]
+ 80337ee:	681b      	ldr	r3, [r3, #0]
+ 80337f0:	4a71      	ldr	r2, [pc, #452]	@ (80339b8 <HAL_DMA_Abort+0x220>)
+ 80337f2:	4293      	cmp	r3, r2
+ 80337f4:	d03b      	beq.n	803386e <HAL_DMA_Abort+0xd6>
+ 80337f6:	687b      	ldr	r3, [r7, #4]
+ 80337f8:	681b      	ldr	r3, [r3, #0]
+ 80337fa:	4a70      	ldr	r2, [pc, #448]	@ (80339bc <HAL_DMA_Abort+0x224>)
+ 80337fc:	4293      	cmp	r3, r2
+ 80337fe:	d036      	beq.n	803386e <HAL_DMA_Abort+0xd6>
+ 8033800:	687b      	ldr	r3, [r7, #4]
+ 8033802:	681b      	ldr	r3, [r3, #0]
+ 8033804:	4a6e      	ldr	r2, [pc, #440]	@ (80339c0 <HAL_DMA_Abort+0x228>)
+ 8033806:	4293      	cmp	r3, r2
+ 8033808:	d031      	beq.n	803386e <HAL_DMA_Abort+0xd6>
+ 803380a:	687b      	ldr	r3, [r7, #4]
+ 803380c:	681b      	ldr	r3, [r3, #0]
+ 803380e:	4a6d      	ldr	r2, [pc, #436]	@ (80339c4 <HAL_DMA_Abort+0x22c>)
+ 8033810:	4293      	cmp	r3, r2
+ 8033812:	d02c      	beq.n	803386e <HAL_DMA_Abort+0xd6>
+ 8033814:	687b      	ldr	r3, [r7, #4]
+ 8033816:	681b      	ldr	r3, [r3, #0]
+ 8033818:	4a6b      	ldr	r2, [pc, #428]	@ (80339c8 <HAL_DMA_Abort+0x230>)
+ 803381a:	4293      	cmp	r3, r2
+ 803381c:	d027      	beq.n	803386e <HAL_DMA_Abort+0xd6>
+ 803381e:	687b      	ldr	r3, [r7, #4]
+ 8033820:	681b      	ldr	r3, [r3, #0]
+ 8033822:	4a6a      	ldr	r2, [pc, #424]	@ (80339cc <HAL_DMA_Abort+0x234>)
+ 8033824:	4293      	cmp	r3, r2
+ 8033826:	d022      	beq.n	803386e <HAL_DMA_Abort+0xd6>
+ 8033828:	687b      	ldr	r3, [r7, #4]
+ 803382a:	681b      	ldr	r3, [r3, #0]
+ 803382c:	4a68      	ldr	r2, [pc, #416]	@ (80339d0 <HAL_DMA_Abort+0x238>)
+ 803382e:	4293      	cmp	r3, r2
+ 8033830:	d01d      	beq.n	803386e <HAL_DMA_Abort+0xd6>
+ 8033832:	687b      	ldr	r3, [r7, #4]
+ 8033834:	681b      	ldr	r3, [r3, #0]
+ 8033836:	4a67      	ldr	r2, [pc, #412]	@ (80339d4 <HAL_DMA_Abort+0x23c>)
+ 8033838:	4293      	cmp	r3, r2
+ 803383a:	d018      	beq.n	803386e <HAL_DMA_Abort+0xd6>
+ 803383c:	687b      	ldr	r3, [r7, #4]
+ 803383e:	681b      	ldr	r3, [r3, #0]
+ 8033840:	4a65      	ldr	r2, [pc, #404]	@ (80339d8 <HAL_DMA_Abort+0x240>)
+ 8033842:	4293      	cmp	r3, r2
+ 8033844:	d013      	beq.n	803386e <HAL_DMA_Abort+0xd6>
+ 8033846:	687b      	ldr	r3, [r7, #4]
+ 8033848:	681b      	ldr	r3, [r3, #0]
+ 803384a:	4a64      	ldr	r2, [pc, #400]	@ (80339dc <HAL_DMA_Abort+0x244>)
+ 803384c:	4293      	cmp	r3, r2
+ 803384e:	d00e      	beq.n	803386e <HAL_DMA_Abort+0xd6>
+ 8033850:	687b      	ldr	r3, [r7, #4]
+ 8033852:	681b      	ldr	r3, [r3, #0]
+ 8033854:	4a62      	ldr	r2, [pc, #392]	@ (80339e0 <HAL_DMA_Abort+0x248>)
+ 8033856:	4293      	cmp	r3, r2
+ 8033858:	d009      	beq.n	803386e <HAL_DMA_Abort+0xd6>
+ 803385a:	687b      	ldr	r3, [r7, #4]
+ 803385c:	681b      	ldr	r3, [r3, #0]
+ 803385e:	4a61      	ldr	r2, [pc, #388]	@ (80339e4 <HAL_DMA_Abort+0x24c>)
+ 8033860:	4293      	cmp	r3, r2
+ 8033862:	d004      	beq.n	803386e <HAL_DMA_Abort+0xd6>
+ 8033864:	687b      	ldr	r3, [r7, #4]
+ 8033866:	681b      	ldr	r3, [r3, #0]
+ 8033868:	4a5f      	ldr	r2, [pc, #380]	@ (80339e8 <HAL_DMA_Abort+0x250>)
+ 803386a:	4293      	cmp	r3, r2
+ 803386c:	d101      	bne.n	8033872 <HAL_DMA_Abort+0xda>
+ 803386e:	2301      	movs	r3, #1
+ 8033870:	e000      	b.n	8033874 <HAL_DMA_Abort+0xdc>
+ 8033872:	2300      	movs	r3, #0
+ 8033874:	2b00      	cmp	r3, #0
+ 8033876:	d013      	beq.n	80338a0 <HAL_DMA_Abort+0x108>
+    {
+       /* Disable DMA All Interrupts  */
+      ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT);
+ 8033878:	687b      	ldr	r3, [r7, #4]
+ 803387a:	681b      	ldr	r3, [r3, #0]
+ 803387c:	681a      	ldr	r2, [r3, #0]
+ 803387e:	687b      	ldr	r3, [r7, #4]
+ 8033880:	681b      	ldr	r3, [r3, #0]
+ 8033882:	f022 021e 	bic.w	r2, r2, #30
+ 8033886:	601a      	str	r2, [r3, #0]
+      ((DMA_Stream_TypeDef   *)hdma->Instance)->FCR &= ~(DMA_IT_FE);
+ 8033888:	687b      	ldr	r3, [r7, #4]
+ 803388a:	681b      	ldr	r3, [r3, #0]
+ 803388c:	695a      	ldr	r2, [r3, #20]
+ 803388e:	687b      	ldr	r3, [r7, #4]
+ 8033890:	681b      	ldr	r3, [r3, #0]
+ 8033892:	f022 0280 	bic.w	r2, r2, #128	@ 0x80
+ 8033896:	615a      	str	r2, [r3, #20]
+
+      enableRegister = (__IO uint32_t *)(&(((DMA_Stream_TypeDef   *)hdma->Instance)->CR));
+ 8033898:	687b      	ldr	r3, [r7, #4]
+ 803389a:	681b      	ldr	r3, [r3, #0]
+ 803389c:	617b      	str	r3, [r7, #20]
+ 803389e:	e00a      	b.n	80338b6 <HAL_DMA_Abort+0x11e>
+    }
+    else /* BDMA channel */
+    {
+      /* Disable DMA All Interrupts */
+      ((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR  &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE);
+ 80338a0:	687b      	ldr	r3, [r7, #4]
+ 80338a2:	681b      	ldr	r3, [r3, #0]
+ 80338a4:	681a      	ldr	r2, [r3, #0]
+ 80338a6:	687b      	ldr	r3, [r7, #4]
+ 80338a8:	681b      	ldr	r3, [r3, #0]
+ 80338aa:	f022 020e 	bic.w	r2, r2, #14
+ 80338ae:	601a      	str	r2, [r3, #0]
+
+      enableRegister = (__IO uint32_t *)(&(((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR));
+ 80338b0:	687b      	ldr	r3, [r7, #4]
+ 80338b2:	681b      	ldr	r3, [r3, #0]
+ 80338b4:	617b      	str	r3, [r7, #20]
+    }
+
+    if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
+ 80338b6:	687b      	ldr	r3, [r7, #4]
+ 80338b8:	681b      	ldr	r3, [r3, #0]
+ 80338ba:	4a3c      	ldr	r2, [pc, #240]	@ (80339ac <HAL_DMA_Abort+0x214>)
+ 80338bc:	4293      	cmp	r3, r2
+ 80338be:	d072      	beq.n	80339a6 <HAL_DMA_Abort+0x20e>
+ 80338c0:	687b      	ldr	r3, [r7, #4]
+ 80338c2:	681b      	ldr	r3, [r3, #0]
+ 80338c4:	4a3a      	ldr	r2, [pc, #232]	@ (80339b0 <HAL_DMA_Abort+0x218>)
+ 80338c6:	4293      	cmp	r3, r2
+ 80338c8:	d06d      	beq.n	80339a6 <HAL_DMA_Abort+0x20e>
+ 80338ca:	687b      	ldr	r3, [r7, #4]
+ 80338cc:	681b      	ldr	r3, [r3, #0]
+ 80338ce:	4a39      	ldr	r2, [pc, #228]	@ (80339b4 <HAL_DMA_Abort+0x21c>)
+ 80338d0:	4293      	cmp	r3, r2
+ 80338d2:	d068      	beq.n	80339a6 <HAL_DMA_Abort+0x20e>
+ 80338d4:	687b      	ldr	r3, [r7, #4]
+ 80338d6:	681b      	ldr	r3, [r3, #0]
+ 80338d8:	4a37      	ldr	r2, [pc, #220]	@ (80339b8 <HAL_DMA_Abort+0x220>)
+ 80338da:	4293      	cmp	r3, r2
+ 80338dc:	d063      	beq.n	80339a6 <HAL_DMA_Abort+0x20e>
+ 80338de:	687b      	ldr	r3, [r7, #4]
+ 80338e0:	681b      	ldr	r3, [r3, #0]
+ 80338e2:	4a36      	ldr	r2, [pc, #216]	@ (80339bc <HAL_DMA_Abort+0x224>)
+ 80338e4:	4293      	cmp	r3, r2
+ 80338e6:	d05e      	beq.n	80339a6 <HAL_DMA_Abort+0x20e>
+ 80338e8:	687b      	ldr	r3, [r7, #4]
+ 80338ea:	681b      	ldr	r3, [r3, #0]
+ 80338ec:	4a34      	ldr	r2, [pc, #208]	@ (80339c0 <HAL_DMA_Abort+0x228>)
+ 80338ee:	4293      	cmp	r3, r2
+ 80338f0:	d059      	beq.n	80339a6 <HAL_DMA_Abort+0x20e>
+ 80338f2:	687b      	ldr	r3, [r7, #4]
+ 80338f4:	681b      	ldr	r3, [r3, #0]
+ 80338f6:	4a33      	ldr	r2, [pc, #204]	@ (80339c4 <HAL_DMA_Abort+0x22c>)
+ 80338f8:	4293      	cmp	r3, r2
+ 80338fa:	d054      	beq.n	80339a6 <HAL_DMA_Abort+0x20e>
+ 80338fc:	687b      	ldr	r3, [r7, #4]
+ 80338fe:	681b      	ldr	r3, [r3, #0]
+ 8033900:	4a31      	ldr	r2, [pc, #196]	@ (80339c8 <HAL_DMA_Abort+0x230>)
+ 8033902:	4293      	cmp	r3, r2
+ 8033904:	d04f      	beq.n	80339a6 <HAL_DMA_Abort+0x20e>
+ 8033906:	687b      	ldr	r3, [r7, #4]
+ 8033908:	681b      	ldr	r3, [r3, #0]
+ 803390a:	4a30      	ldr	r2, [pc, #192]	@ (80339cc <HAL_DMA_Abort+0x234>)
+ 803390c:	4293      	cmp	r3, r2
+ 803390e:	d04a      	beq.n	80339a6 <HAL_DMA_Abort+0x20e>
+ 8033910:	687b      	ldr	r3, [r7, #4]
+ 8033912:	681b      	ldr	r3, [r3, #0]
+ 8033914:	4a2e      	ldr	r2, [pc, #184]	@ (80339d0 <HAL_DMA_Abort+0x238>)
+ 8033916:	4293      	cmp	r3, r2
+ 8033918:	d045      	beq.n	80339a6 <HAL_DMA_Abort+0x20e>
+ 803391a:	687b      	ldr	r3, [r7, #4]
+ 803391c:	681b      	ldr	r3, [r3, #0]
+ 803391e:	4a2d      	ldr	r2, [pc, #180]	@ (80339d4 <HAL_DMA_Abort+0x23c>)
+ 8033920:	4293      	cmp	r3, r2
+ 8033922:	d040      	beq.n	80339a6 <HAL_DMA_Abort+0x20e>
+ 8033924:	687b      	ldr	r3, [r7, #4]
+ 8033926:	681b      	ldr	r3, [r3, #0]
+ 8033928:	4a2b      	ldr	r2, [pc, #172]	@ (80339d8 <HAL_DMA_Abort+0x240>)
+ 803392a:	4293      	cmp	r3, r2
+ 803392c:	d03b      	beq.n	80339a6 <HAL_DMA_Abort+0x20e>
+ 803392e:	687b      	ldr	r3, [r7, #4]
+ 8033930:	681b      	ldr	r3, [r3, #0]
+ 8033932:	4a2a      	ldr	r2, [pc, #168]	@ (80339dc <HAL_DMA_Abort+0x244>)
+ 8033934:	4293      	cmp	r3, r2
+ 8033936:	d036      	beq.n	80339a6 <HAL_DMA_Abort+0x20e>
+ 8033938:	687b      	ldr	r3, [r7, #4]
+ 803393a:	681b      	ldr	r3, [r3, #0]
+ 803393c:	4a28      	ldr	r2, [pc, #160]	@ (80339e0 <HAL_DMA_Abort+0x248>)
+ 803393e:	4293      	cmp	r3, r2
+ 8033940:	d031      	beq.n	80339a6 <HAL_DMA_Abort+0x20e>
+ 8033942:	687b      	ldr	r3, [r7, #4]
+ 8033944:	681b      	ldr	r3, [r3, #0]
+ 8033946:	4a27      	ldr	r2, [pc, #156]	@ (80339e4 <HAL_DMA_Abort+0x24c>)
+ 8033948:	4293      	cmp	r3, r2
+ 803394a:	d02c      	beq.n	80339a6 <HAL_DMA_Abort+0x20e>
+ 803394c:	687b      	ldr	r3, [r7, #4]
+ 803394e:	681b      	ldr	r3, [r3, #0]
+ 8033950:	4a25      	ldr	r2, [pc, #148]	@ (80339e8 <HAL_DMA_Abort+0x250>)
+ 8033952:	4293      	cmp	r3, r2
+ 8033954:	d027      	beq.n	80339a6 <HAL_DMA_Abort+0x20e>
+ 8033956:	687b      	ldr	r3, [r7, #4]
+ 8033958:	681b      	ldr	r3, [r3, #0]
+ 803395a:	4a24      	ldr	r2, [pc, #144]	@ (80339ec <HAL_DMA_Abort+0x254>)
+ 803395c:	4293      	cmp	r3, r2
+ 803395e:	d022      	beq.n	80339a6 <HAL_DMA_Abort+0x20e>
+ 8033960:	687b      	ldr	r3, [r7, #4]
+ 8033962:	681b      	ldr	r3, [r3, #0]
+ 8033964:	4a22      	ldr	r2, [pc, #136]	@ (80339f0 <HAL_DMA_Abort+0x258>)
+ 8033966:	4293      	cmp	r3, r2
+ 8033968:	d01d      	beq.n	80339a6 <HAL_DMA_Abort+0x20e>
+ 803396a:	687b      	ldr	r3, [r7, #4]
+ 803396c:	681b      	ldr	r3, [r3, #0]
+ 803396e:	4a21      	ldr	r2, [pc, #132]	@ (80339f4 <HAL_DMA_Abort+0x25c>)
+ 8033970:	4293      	cmp	r3, r2
+ 8033972:	d018      	beq.n	80339a6 <HAL_DMA_Abort+0x20e>
+ 8033974:	687b      	ldr	r3, [r7, #4]
+ 8033976:	681b      	ldr	r3, [r3, #0]
+ 8033978:	4a1f      	ldr	r2, [pc, #124]	@ (80339f8 <HAL_DMA_Abort+0x260>)
+ 803397a:	4293      	cmp	r3, r2
+ 803397c:	d013      	beq.n	80339a6 <HAL_DMA_Abort+0x20e>
+ 803397e:	687b      	ldr	r3, [r7, #4]
+ 8033980:	681b      	ldr	r3, [r3, #0]
+ 8033982:	4a1e      	ldr	r2, [pc, #120]	@ (80339fc <HAL_DMA_Abort+0x264>)
+ 8033984:	4293      	cmp	r3, r2
+ 8033986:	d00e      	beq.n	80339a6 <HAL_DMA_Abort+0x20e>
+ 8033988:	687b      	ldr	r3, [r7, #4]
+ 803398a:	681b      	ldr	r3, [r3, #0]
+ 803398c:	4a1c      	ldr	r2, [pc, #112]	@ (8033a00 <HAL_DMA_Abort+0x268>)
+ 803398e:	4293      	cmp	r3, r2
+ 8033990:	d009      	beq.n	80339a6 <HAL_DMA_Abort+0x20e>
+ 8033992:	687b      	ldr	r3, [r7, #4]
+ 8033994:	681b      	ldr	r3, [r3, #0]
+ 8033996:	4a1b      	ldr	r2, [pc, #108]	@ (8033a04 <HAL_DMA_Abort+0x26c>)
+ 8033998:	4293      	cmp	r3, r2
+ 803399a:	d004      	beq.n	80339a6 <HAL_DMA_Abort+0x20e>
+ 803399c:	687b      	ldr	r3, [r7, #4]
+ 803399e:	681b      	ldr	r3, [r3, #0]
+ 80339a0:	4a19      	ldr	r2, [pc, #100]	@ (8033a08 <HAL_DMA_Abort+0x270>)
+ 80339a2:	4293      	cmp	r3, r2
+ 80339a4:	d132      	bne.n	8033a0c <HAL_DMA_Abort+0x274>
+ 80339a6:	2301      	movs	r3, #1
+ 80339a8:	e031      	b.n	8033a0e <HAL_DMA_Abort+0x276>
+ 80339aa:	bf00      	nop
+ 80339ac:	40020010 	.word	0x40020010
+ 80339b0:	40020028 	.word	0x40020028
+ 80339b4:	40020040 	.word	0x40020040
+ 80339b8:	40020058 	.word	0x40020058
+ 80339bc:	40020070 	.word	0x40020070
+ 80339c0:	40020088 	.word	0x40020088
+ 80339c4:	400200a0 	.word	0x400200a0
+ 80339c8:	400200b8 	.word	0x400200b8
+ 80339cc:	40020410 	.word	0x40020410
+ 80339d0:	40020428 	.word	0x40020428
+ 80339d4:	40020440 	.word	0x40020440
+ 80339d8:	40020458 	.word	0x40020458
+ 80339dc:	40020470 	.word	0x40020470
+ 80339e0:	40020488 	.word	0x40020488
+ 80339e4:	400204a0 	.word	0x400204a0
+ 80339e8:	400204b8 	.word	0x400204b8
+ 80339ec:	58025408 	.word	0x58025408
+ 80339f0:	5802541c 	.word	0x5802541c
+ 80339f4:	58025430 	.word	0x58025430
+ 80339f8:	58025444 	.word	0x58025444
+ 80339fc:	58025458 	.word	0x58025458
+ 8033a00:	5802546c 	.word	0x5802546c
+ 8033a04:	58025480 	.word	0x58025480
+ 8033a08:	58025494 	.word	0x58025494
+ 8033a0c:	2300      	movs	r3, #0
+ 8033a0e:	2b00      	cmp	r3, #0
+ 8033a10:	d007      	beq.n	8033a22 <HAL_DMA_Abort+0x28a>
+    {
+      /* disable the DMAMUX sync overrun IT */
+      hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
+ 8033a12:	687b      	ldr	r3, [r7, #4]
+ 8033a14:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
+ 8033a16:	681a      	ldr	r2, [r3, #0]
+ 8033a18:	687b      	ldr	r3, [r7, #4]
+ 8033a1a:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
+ 8033a1c:	f422 7280 	bic.w	r2, r2, #256	@ 0x100
+ 8033a20:	601a      	str	r2, [r3, #0]
+    }
+
+    /* Disable the stream */
+    __HAL_DMA_DISABLE(hdma);
+ 8033a22:	687b      	ldr	r3, [r7, #4]
+ 8033a24:	681b      	ldr	r3, [r3, #0]
+ 8033a26:	4a6d      	ldr	r2, [pc, #436]	@ (8033bdc <HAL_DMA_Abort+0x444>)
+ 8033a28:	4293      	cmp	r3, r2
+ 8033a2a:	d04a      	beq.n	8033ac2 <HAL_DMA_Abort+0x32a>
+ 8033a2c:	687b      	ldr	r3, [r7, #4]
+ 8033a2e:	681b      	ldr	r3, [r3, #0]
+ 8033a30:	4a6b      	ldr	r2, [pc, #428]	@ (8033be0 <HAL_DMA_Abort+0x448>)
+ 8033a32:	4293      	cmp	r3, r2
+ 8033a34:	d045      	beq.n	8033ac2 <HAL_DMA_Abort+0x32a>
+ 8033a36:	687b      	ldr	r3, [r7, #4]
+ 8033a38:	681b      	ldr	r3, [r3, #0]
+ 8033a3a:	4a6a      	ldr	r2, [pc, #424]	@ (8033be4 <HAL_DMA_Abort+0x44c>)
+ 8033a3c:	4293      	cmp	r3, r2
+ 8033a3e:	d040      	beq.n	8033ac2 <HAL_DMA_Abort+0x32a>
+ 8033a40:	687b      	ldr	r3, [r7, #4]
+ 8033a42:	681b      	ldr	r3, [r3, #0]
+ 8033a44:	4a68      	ldr	r2, [pc, #416]	@ (8033be8 <HAL_DMA_Abort+0x450>)
+ 8033a46:	4293      	cmp	r3, r2
+ 8033a48:	d03b      	beq.n	8033ac2 <HAL_DMA_Abort+0x32a>
+ 8033a4a:	687b      	ldr	r3, [r7, #4]
+ 8033a4c:	681b      	ldr	r3, [r3, #0]
+ 8033a4e:	4a67      	ldr	r2, [pc, #412]	@ (8033bec <HAL_DMA_Abort+0x454>)
+ 8033a50:	4293      	cmp	r3, r2
+ 8033a52:	d036      	beq.n	8033ac2 <HAL_DMA_Abort+0x32a>
+ 8033a54:	687b      	ldr	r3, [r7, #4]
+ 8033a56:	681b      	ldr	r3, [r3, #0]
+ 8033a58:	4a65      	ldr	r2, [pc, #404]	@ (8033bf0 <HAL_DMA_Abort+0x458>)
+ 8033a5a:	4293      	cmp	r3, r2
+ 8033a5c:	d031      	beq.n	8033ac2 <HAL_DMA_Abort+0x32a>
+ 8033a5e:	687b      	ldr	r3, [r7, #4]
+ 8033a60:	681b      	ldr	r3, [r3, #0]
+ 8033a62:	4a64      	ldr	r2, [pc, #400]	@ (8033bf4 <HAL_DMA_Abort+0x45c>)
+ 8033a64:	4293      	cmp	r3, r2
+ 8033a66:	d02c      	beq.n	8033ac2 <HAL_DMA_Abort+0x32a>
+ 8033a68:	687b      	ldr	r3, [r7, #4]
+ 8033a6a:	681b      	ldr	r3, [r3, #0]
+ 8033a6c:	4a62      	ldr	r2, [pc, #392]	@ (8033bf8 <HAL_DMA_Abort+0x460>)
+ 8033a6e:	4293      	cmp	r3, r2
+ 8033a70:	d027      	beq.n	8033ac2 <HAL_DMA_Abort+0x32a>
+ 8033a72:	687b      	ldr	r3, [r7, #4]
+ 8033a74:	681b      	ldr	r3, [r3, #0]
+ 8033a76:	4a61      	ldr	r2, [pc, #388]	@ (8033bfc <HAL_DMA_Abort+0x464>)
+ 8033a78:	4293      	cmp	r3, r2
+ 8033a7a:	d022      	beq.n	8033ac2 <HAL_DMA_Abort+0x32a>
+ 8033a7c:	687b      	ldr	r3, [r7, #4]
+ 8033a7e:	681b      	ldr	r3, [r3, #0]
+ 8033a80:	4a5f      	ldr	r2, [pc, #380]	@ (8033c00 <HAL_DMA_Abort+0x468>)
+ 8033a82:	4293      	cmp	r3, r2
+ 8033a84:	d01d      	beq.n	8033ac2 <HAL_DMA_Abort+0x32a>
+ 8033a86:	687b      	ldr	r3, [r7, #4]
+ 8033a88:	681b      	ldr	r3, [r3, #0]
+ 8033a8a:	4a5e      	ldr	r2, [pc, #376]	@ (8033c04 <HAL_DMA_Abort+0x46c>)
+ 8033a8c:	4293      	cmp	r3, r2
+ 8033a8e:	d018      	beq.n	8033ac2 <HAL_DMA_Abort+0x32a>
+ 8033a90:	687b      	ldr	r3, [r7, #4]
+ 8033a92:	681b      	ldr	r3, [r3, #0]
+ 8033a94:	4a5c      	ldr	r2, [pc, #368]	@ (8033c08 <HAL_DMA_Abort+0x470>)
+ 8033a96:	4293      	cmp	r3, r2
+ 8033a98:	d013      	beq.n	8033ac2 <HAL_DMA_Abort+0x32a>
+ 8033a9a:	687b      	ldr	r3, [r7, #4]
+ 8033a9c:	681b      	ldr	r3, [r3, #0]
+ 8033a9e:	4a5b      	ldr	r2, [pc, #364]	@ (8033c0c <HAL_DMA_Abort+0x474>)
+ 8033aa0:	4293      	cmp	r3, r2
+ 8033aa2:	d00e      	beq.n	8033ac2 <HAL_DMA_Abort+0x32a>
+ 8033aa4:	687b      	ldr	r3, [r7, #4]
+ 8033aa6:	681b      	ldr	r3, [r3, #0]
+ 8033aa8:	4a59      	ldr	r2, [pc, #356]	@ (8033c10 <HAL_DMA_Abort+0x478>)
+ 8033aaa:	4293      	cmp	r3, r2
+ 8033aac:	d009      	beq.n	8033ac2 <HAL_DMA_Abort+0x32a>
+ 8033aae:	687b      	ldr	r3, [r7, #4]
+ 8033ab0:	681b      	ldr	r3, [r3, #0]
+ 8033ab2:	4a58      	ldr	r2, [pc, #352]	@ (8033c14 <HAL_DMA_Abort+0x47c>)
+ 8033ab4:	4293      	cmp	r3, r2
+ 8033ab6:	d004      	beq.n	8033ac2 <HAL_DMA_Abort+0x32a>
+ 8033ab8:	687b      	ldr	r3, [r7, #4]
+ 8033aba:	681b      	ldr	r3, [r3, #0]
+ 8033abc:	4a56      	ldr	r2, [pc, #344]	@ (8033c18 <HAL_DMA_Abort+0x480>)
+ 8033abe:	4293      	cmp	r3, r2
+ 8033ac0:	d108      	bne.n	8033ad4 <HAL_DMA_Abort+0x33c>
+ 8033ac2:	687b      	ldr	r3, [r7, #4]
+ 8033ac4:	681b      	ldr	r3, [r3, #0]
+ 8033ac6:	681a      	ldr	r2, [r3, #0]
+ 8033ac8:	687b      	ldr	r3, [r7, #4]
+ 8033aca:	681b      	ldr	r3, [r3, #0]
+ 8033acc:	f022 0201 	bic.w	r2, r2, #1
+ 8033ad0:	601a      	str	r2, [r3, #0]
+ 8033ad2:	e007      	b.n	8033ae4 <HAL_DMA_Abort+0x34c>
+ 8033ad4:	687b      	ldr	r3, [r7, #4]
+ 8033ad6:	681b      	ldr	r3, [r3, #0]
+ 8033ad8:	681a      	ldr	r2, [r3, #0]
+ 8033ada:	687b      	ldr	r3, [r7, #4]
+ 8033adc:	681b      	ldr	r3, [r3, #0]
+ 8033ade:	f022 0201 	bic.w	r2, r2, #1
+ 8033ae2:	601a      	str	r2, [r3, #0]
+
+    /* Check if the DMA Stream is effectively disabled */
+    while(((*enableRegister) & DMA_SxCR_EN) != 0U)
+ 8033ae4:	e013      	b.n	8033b0e <HAL_DMA_Abort+0x376>
+    {
+      /* Check for the Timeout */
+      if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
+ 8033ae6:	f7fd ff23 	bl	8031930 <HAL_GetTick>
+ 8033aea:	4602      	mov	r2, r0
+ 8033aec:	693b      	ldr	r3, [r7, #16]
+ 8033aee:	1ad3      	subs	r3, r2, r3
+ 8033af0:	2b05      	cmp	r3, #5
+ 8033af2:	d90c      	bls.n	8033b0e <HAL_DMA_Abort+0x376>
+      {
+        /* Update error code */
+        hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
+ 8033af4:	687b      	ldr	r3, [r7, #4]
+ 8033af6:	2220      	movs	r2, #32
+ 8033af8:	655a      	str	r2, [r3, #84]	@ 0x54
+
+        /* Change the DMA state */
+        hdma->State = HAL_DMA_STATE_ERROR;
+ 8033afa:	687b      	ldr	r3, [r7, #4]
+ 8033afc:	2203      	movs	r2, #3
+ 8033afe:	f883 2035 	strb.w	r2, [r3, #53]	@ 0x35
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hdma);
+ 8033b02:	687b      	ldr	r3, [r7, #4]
+ 8033b04:	2200      	movs	r2, #0
+ 8033b06:	f883 2034 	strb.w	r2, [r3, #52]	@ 0x34
+
+        return HAL_ERROR;
+ 8033b0a:	2301      	movs	r3, #1
+ 8033b0c:	e12d      	b.n	8033d6a <HAL_DMA_Abort+0x5d2>
+    while(((*enableRegister) & DMA_SxCR_EN) != 0U)
+ 8033b0e:	697b      	ldr	r3, [r7, #20]
+ 8033b10:	681b      	ldr	r3, [r3, #0]
+ 8033b12:	f003 0301 	and.w	r3, r3, #1
+ 8033b16:	2b00      	cmp	r3, #0
+ 8033b18:	d1e5      	bne.n	8033ae6 <HAL_DMA_Abort+0x34e>
+      }
+    }
+
+    /* Clear all interrupt flags at correct offset within the register */
+    if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+ 8033b1a:	687b      	ldr	r3, [r7, #4]
+ 8033b1c:	681b      	ldr	r3, [r3, #0]
+ 8033b1e:	4a2f      	ldr	r2, [pc, #188]	@ (8033bdc <HAL_DMA_Abort+0x444>)
+ 8033b20:	4293      	cmp	r3, r2
+ 8033b22:	d04a      	beq.n	8033bba <HAL_DMA_Abort+0x422>
+ 8033b24:	687b      	ldr	r3, [r7, #4]
+ 8033b26:	681b      	ldr	r3, [r3, #0]
+ 8033b28:	4a2d      	ldr	r2, [pc, #180]	@ (8033be0 <HAL_DMA_Abort+0x448>)
+ 8033b2a:	4293      	cmp	r3, r2
+ 8033b2c:	d045      	beq.n	8033bba <HAL_DMA_Abort+0x422>
+ 8033b2e:	687b      	ldr	r3, [r7, #4]
+ 8033b30:	681b      	ldr	r3, [r3, #0]
+ 8033b32:	4a2c      	ldr	r2, [pc, #176]	@ (8033be4 <HAL_DMA_Abort+0x44c>)
+ 8033b34:	4293      	cmp	r3, r2
+ 8033b36:	d040      	beq.n	8033bba <HAL_DMA_Abort+0x422>
+ 8033b38:	687b      	ldr	r3, [r7, #4]
+ 8033b3a:	681b      	ldr	r3, [r3, #0]
+ 8033b3c:	4a2a      	ldr	r2, [pc, #168]	@ (8033be8 <HAL_DMA_Abort+0x450>)
+ 8033b3e:	4293      	cmp	r3, r2
+ 8033b40:	d03b      	beq.n	8033bba <HAL_DMA_Abort+0x422>
+ 8033b42:	687b      	ldr	r3, [r7, #4]
+ 8033b44:	681b      	ldr	r3, [r3, #0]
+ 8033b46:	4a29      	ldr	r2, [pc, #164]	@ (8033bec <HAL_DMA_Abort+0x454>)
+ 8033b48:	4293      	cmp	r3, r2
+ 8033b4a:	d036      	beq.n	8033bba <HAL_DMA_Abort+0x422>
+ 8033b4c:	687b      	ldr	r3, [r7, #4]
+ 8033b4e:	681b      	ldr	r3, [r3, #0]
+ 8033b50:	4a27      	ldr	r2, [pc, #156]	@ (8033bf0 <HAL_DMA_Abort+0x458>)
+ 8033b52:	4293      	cmp	r3, r2
+ 8033b54:	d031      	beq.n	8033bba <HAL_DMA_Abort+0x422>
+ 8033b56:	687b      	ldr	r3, [r7, #4]
+ 8033b58:	681b      	ldr	r3, [r3, #0]
+ 8033b5a:	4a26      	ldr	r2, [pc, #152]	@ (8033bf4 <HAL_DMA_Abort+0x45c>)
+ 8033b5c:	4293      	cmp	r3, r2
+ 8033b5e:	d02c      	beq.n	8033bba <HAL_DMA_Abort+0x422>
+ 8033b60:	687b      	ldr	r3, [r7, #4]
+ 8033b62:	681b      	ldr	r3, [r3, #0]
+ 8033b64:	4a24      	ldr	r2, [pc, #144]	@ (8033bf8 <HAL_DMA_Abort+0x460>)
+ 8033b66:	4293      	cmp	r3, r2
+ 8033b68:	d027      	beq.n	8033bba <HAL_DMA_Abort+0x422>
+ 8033b6a:	687b      	ldr	r3, [r7, #4]
+ 8033b6c:	681b      	ldr	r3, [r3, #0]
+ 8033b6e:	4a23      	ldr	r2, [pc, #140]	@ (8033bfc <HAL_DMA_Abort+0x464>)
+ 8033b70:	4293      	cmp	r3, r2
+ 8033b72:	d022      	beq.n	8033bba <HAL_DMA_Abort+0x422>
+ 8033b74:	687b      	ldr	r3, [r7, #4]
+ 8033b76:	681b      	ldr	r3, [r3, #0]
+ 8033b78:	4a21      	ldr	r2, [pc, #132]	@ (8033c00 <HAL_DMA_Abort+0x468>)
+ 8033b7a:	4293      	cmp	r3, r2
+ 8033b7c:	d01d      	beq.n	8033bba <HAL_DMA_Abort+0x422>
+ 8033b7e:	687b      	ldr	r3, [r7, #4]
+ 8033b80:	681b      	ldr	r3, [r3, #0]
+ 8033b82:	4a20      	ldr	r2, [pc, #128]	@ (8033c04 <HAL_DMA_Abort+0x46c>)
+ 8033b84:	4293      	cmp	r3, r2
+ 8033b86:	d018      	beq.n	8033bba <HAL_DMA_Abort+0x422>
+ 8033b88:	687b      	ldr	r3, [r7, #4]
+ 8033b8a:	681b      	ldr	r3, [r3, #0]
+ 8033b8c:	4a1e      	ldr	r2, [pc, #120]	@ (8033c08 <HAL_DMA_Abort+0x470>)
+ 8033b8e:	4293      	cmp	r3, r2
+ 8033b90:	d013      	beq.n	8033bba <HAL_DMA_Abort+0x422>
+ 8033b92:	687b      	ldr	r3, [r7, #4]
+ 8033b94:	681b      	ldr	r3, [r3, #0]
+ 8033b96:	4a1d      	ldr	r2, [pc, #116]	@ (8033c0c <HAL_DMA_Abort+0x474>)
+ 8033b98:	4293      	cmp	r3, r2
+ 8033b9a:	d00e      	beq.n	8033bba <HAL_DMA_Abort+0x422>
+ 8033b9c:	687b      	ldr	r3, [r7, #4]
+ 8033b9e:	681b      	ldr	r3, [r3, #0]
+ 8033ba0:	4a1b      	ldr	r2, [pc, #108]	@ (8033c10 <HAL_DMA_Abort+0x478>)
+ 8033ba2:	4293      	cmp	r3, r2
+ 8033ba4:	d009      	beq.n	8033bba <HAL_DMA_Abort+0x422>
+ 8033ba6:	687b      	ldr	r3, [r7, #4]
+ 8033ba8:	681b      	ldr	r3, [r3, #0]
+ 8033baa:	4a1a      	ldr	r2, [pc, #104]	@ (8033c14 <HAL_DMA_Abort+0x47c>)
+ 8033bac:	4293      	cmp	r3, r2
+ 8033bae:	d004      	beq.n	8033bba <HAL_DMA_Abort+0x422>
+ 8033bb0:	687b      	ldr	r3, [r7, #4]
+ 8033bb2:	681b      	ldr	r3, [r3, #0]
+ 8033bb4:	4a18      	ldr	r2, [pc, #96]	@ (8033c18 <HAL_DMA_Abort+0x480>)
+ 8033bb6:	4293      	cmp	r3, r2
+ 8033bb8:	d101      	bne.n	8033bbe <HAL_DMA_Abort+0x426>
+ 8033bba:	2301      	movs	r3, #1
+ 8033bbc:	e000      	b.n	8033bc0 <HAL_DMA_Abort+0x428>
+ 8033bbe:	2300      	movs	r3, #0
+ 8033bc0:	2b00      	cmp	r3, #0
+ 8033bc2:	d02b      	beq.n	8033c1c <HAL_DMA_Abort+0x484>
+    {
+      regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress;
+ 8033bc4:	687b      	ldr	r3, [r7, #4]
+ 8033bc6:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
+ 8033bc8:	60bb      	str	r3, [r7, #8]
+      regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);
+ 8033bca:	687b      	ldr	r3, [r7, #4]
+ 8033bcc:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
+ 8033bce:	f003 031f 	and.w	r3, r3, #31
+ 8033bd2:	223f      	movs	r2, #63	@ 0x3f
+ 8033bd4:	409a      	lsls	r2, r3
+ 8033bd6:	68bb      	ldr	r3, [r7, #8]
+ 8033bd8:	609a      	str	r2, [r3, #8]
+ 8033bda:	e02a      	b.n	8033c32 <HAL_DMA_Abort+0x49a>
+ 8033bdc:	40020010 	.word	0x40020010
+ 8033be0:	40020028 	.word	0x40020028
+ 8033be4:	40020040 	.word	0x40020040
+ 8033be8:	40020058 	.word	0x40020058
+ 8033bec:	40020070 	.word	0x40020070
+ 8033bf0:	40020088 	.word	0x40020088
+ 8033bf4:	400200a0 	.word	0x400200a0
+ 8033bf8:	400200b8 	.word	0x400200b8
+ 8033bfc:	40020410 	.word	0x40020410
+ 8033c00:	40020428 	.word	0x40020428
+ 8033c04:	40020440 	.word	0x40020440
+ 8033c08:	40020458 	.word	0x40020458
+ 8033c0c:	40020470 	.word	0x40020470
+ 8033c10:	40020488 	.word	0x40020488
+ 8033c14:	400204a0 	.word	0x400204a0
+ 8033c18:	400204b8 	.word	0x400204b8
+    }
+    else /* BDMA channel */
+    {
+      regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress;
+ 8033c1c:	687b      	ldr	r3, [r7, #4]
+ 8033c1e:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
+ 8033c20:	60fb      	str	r3, [r7, #12]
+      regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU));
+ 8033c22:	687b      	ldr	r3, [r7, #4]
+ 8033c24:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
+ 8033c26:	f003 031f 	and.w	r3, r3, #31
+ 8033c2a:	2201      	movs	r2, #1
+ 8033c2c:	409a      	lsls	r2, r3
+ 8033c2e:	68fb      	ldr	r3, [r7, #12]
+ 8033c30:	605a      	str	r2, [r3, #4]
+    }
+
+    if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
+ 8033c32:	687b      	ldr	r3, [r7, #4]
+ 8033c34:	681b      	ldr	r3, [r3, #0]
+ 8033c36:	4a4f      	ldr	r2, [pc, #316]	@ (8033d74 <HAL_DMA_Abort+0x5dc>)
+ 8033c38:	4293      	cmp	r3, r2
+ 8033c3a:	d072      	beq.n	8033d22 <HAL_DMA_Abort+0x58a>
+ 8033c3c:	687b      	ldr	r3, [r7, #4]
+ 8033c3e:	681b      	ldr	r3, [r3, #0]
+ 8033c40:	4a4d      	ldr	r2, [pc, #308]	@ (8033d78 <HAL_DMA_Abort+0x5e0>)
+ 8033c42:	4293      	cmp	r3, r2
+ 8033c44:	d06d      	beq.n	8033d22 <HAL_DMA_Abort+0x58a>
+ 8033c46:	687b      	ldr	r3, [r7, #4]
+ 8033c48:	681b      	ldr	r3, [r3, #0]
+ 8033c4a:	4a4c      	ldr	r2, [pc, #304]	@ (8033d7c <HAL_DMA_Abort+0x5e4>)
+ 8033c4c:	4293      	cmp	r3, r2
+ 8033c4e:	d068      	beq.n	8033d22 <HAL_DMA_Abort+0x58a>
+ 8033c50:	687b      	ldr	r3, [r7, #4]
+ 8033c52:	681b      	ldr	r3, [r3, #0]
+ 8033c54:	4a4a      	ldr	r2, [pc, #296]	@ (8033d80 <HAL_DMA_Abort+0x5e8>)
+ 8033c56:	4293      	cmp	r3, r2
+ 8033c58:	d063      	beq.n	8033d22 <HAL_DMA_Abort+0x58a>
+ 8033c5a:	687b      	ldr	r3, [r7, #4]
+ 8033c5c:	681b      	ldr	r3, [r3, #0]
+ 8033c5e:	4a49      	ldr	r2, [pc, #292]	@ (8033d84 <HAL_DMA_Abort+0x5ec>)
+ 8033c60:	4293      	cmp	r3, r2
+ 8033c62:	d05e      	beq.n	8033d22 <HAL_DMA_Abort+0x58a>
+ 8033c64:	687b      	ldr	r3, [r7, #4]
+ 8033c66:	681b      	ldr	r3, [r3, #0]
+ 8033c68:	4a47      	ldr	r2, [pc, #284]	@ (8033d88 <HAL_DMA_Abort+0x5f0>)
+ 8033c6a:	4293      	cmp	r3, r2
+ 8033c6c:	d059      	beq.n	8033d22 <HAL_DMA_Abort+0x58a>
+ 8033c6e:	687b      	ldr	r3, [r7, #4]
+ 8033c70:	681b      	ldr	r3, [r3, #0]
+ 8033c72:	4a46      	ldr	r2, [pc, #280]	@ (8033d8c <HAL_DMA_Abort+0x5f4>)
+ 8033c74:	4293      	cmp	r3, r2
+ 8033c76:	d054      	beq.n	8033d22 <HAL_DMA_Abort+0x58a>
+ 8033c78:	687b      	ldr	r3, [r7, #4]
+ 8033c7a:	681b      	ldr	r3, [r3, #0]
+ 8033c7c:	4a44      	ldr	r2, [pc, #272]	@ (8033d90 <HAL_DMA_Abort+0x5f8>)
+ 8033c7e:	4293      	cmp	r3, r2
+ 8033c80:	d04f      	beq.n	8033d22 <HAL_DMA_Abort+0x58a>
+ 8033c82:	687b      	ldr	r3, [r7, #4]
+ 8033c84:	681b      	ldr	r3, [r3, #0]
+ 8033c86:	4a43      	ldr	r2, [pc, #268]	@ (8033d94 <HAL_DMA_Abort+0x5fc>)
+ 8033c88:	4293      	cmp	r3, r2
+ 8033c8a:	d04a      	beq.n	8033d22 <HAL_DMA_Abort+0x58a>
+ 8033c8c:	687b      	ldr	r3, [r7, #4]
+ 8033c8e:	681b      	ldr	r3, [r3, #0]
+ 8033c90:	4a41      	ldr	r2, [pc, #260]	@ (8033d98 <HAL_DMA_Abort+0x600>)
+ 8033c92:	4293      	cmp	r3, r2
+ 8033c94:	d045      	beq.n	8033d22 <HAL_DMA_Abort+0x58a>
+ 8033c96:	687b      	ldr	r3, [r7, #4]
+ 8033c98:	681b      	ldr	r3, [r3, #0]
+ 8033c9a:	4a40      	ldr	r2, [pc, #256]	@ (8033d9c <HAL_DMA_Abort+0x604>)
+ 8033c9c:	4293      	cmp	r3, r2
+ 8033c9e:	d040      	beq.n	8033d22 <HAL_DMA_Abort+0x58a>
+ 8033ca0:	687b      	ldr	r3, [r7, #4]
+ 8033ca2:	681b      	ldr	r3, [r3, #0]
+ 8033ca4:	4a3e      	ldr	r2, [pc, #248]	@ (8033da0 <HAL_DMA_Abort+0x608>)
+ 8033ca6:	4293      	cmp	r3, r2
+ 8033ca8:	d03b      	beq.n	8033d22 <HAL_DMA_Abort+0x58a>
+ 8033caa:	687b      	ldr	r3, [r7, #4]
+ 8033cac:	681b      	ldr	r3, [r3, #0]
+ 8033cae:	4a3d      	ldr	r2, [pc, #244]	@ (8033da4 <HAL_DMA_Abort+0x60c>)
+ 8033cb0:	4293      	cmp	r3, r2
+ 8033cb2:	d036      	beq.n	8033d22 <HAL_DMA_Abort+0x58a>
+ 8033cb4:	687b      	ldr	r3, [r7, #4]
+ 8033cb6:	681b      	ldr	r3, [r3, #0]
+ 8033cb8:	4a3b      	ldr	r2, [pc, #236]	@ (8033da8 <HAL_DMA_Abort+0x610>)
+ 8033cba:	4293      	cmp	r3, r2
+ 8033cbc:	d031      	beq.n	8033d22 <HAL_DMA_Abort+0x58a>
+ 8033cbe:	687b      	ldr	r3, [r7, #4]
+ 8033cc0:	681b      	ldr	r3, [r3, #0]
+ 8033cc2:	4a3a      	ldr	r2, [pc, #232]	@ (8033dac <HAL_DMA_Abort+0x614>)
+ 8033cc4:	4293      	cmp	r3, r2
+ 8033cc6:	d02c      	beq.n	8033d22 <HAL_DMA_Abort+0x58a>
+ 8033cc8:	687b      	ldr	r3, [r7, #4]
+ 8033cca:	681b      	ldr	r3, [r3, #0]
+ 8033ccc:	4a38      	ldr	r2, [pc, #224]	@ (8033db0 <HAL_DMA_Abort+0x618>)
+ 8033cce:	4293      	cmp	r3, r2
+ 8033cd0:	d027      	beq.n	8033d22 <HAL_DMA_Abort+0x58a>
+ 8033cd2:	687b      	ldr	r3, [r7, #4]
+ 8033cd4:	681b      	ldr	r3, [r3, #0]
+ 8033cd6:	4a37      	ldr	r2, [pc, #220]	@ (8033db4 <HAL_DMA_Abort+0x61c>)
+ 8033cd8:	4293      	cmp	r3, r2
+ 8033cda:	d022      	beq.n	8033d22 <HAL_DMA_Abort+0x58a>
+ 8033cdc:	687b      	ldr	r3, [r7, #4]
+ 8033cde:	681b      	ldr	r3, [r3, #0]
+ 8033ce0:	4a35      	ldr	r2, [pc, #212]	@ (8033db8 <HAL_DMA_Abort+0x620>)
+ 8033ce2:	4293      	cmp	r3, r2
+ 8033ce4:	d01d      	beq.n	8033d22 <HAL_DMA_Abort+0x58a>
+ 8033ce6:	687b      	ldr	r3, [r7, #4]
+ 8033ce8:	681b      	ldr	r3, [r3, #0]
+ 8033cea:	4a34      	ldr	r2, [pc, #208]	@ (8033dbc <HAL_DMA_Abort+0x624>)
+ 8033cec:	4293      	cmp	r3, r2
+ 8033cee:	d018      	beq.n	8033d22 <HAL_DMA_Abort+0x58a>
+ 8033cf0:	687b      	ldr	r3, [r7, #4]
+ 8033cf2:	681b      	ldr	r3, [r3, #0]
+ 8033cf4:	4a32      	ldr	r2, [pc, #200]	@ (8033dc0 <HAL_DMA_Abort+0x628>)
+ 8033cf6:	4293      	cmp	r3, r2
+ 8033cf8:	d013      	beq.n	8033d22 <HAL_DMA_Abort+0x58a>
+ 8033cfa:	687b      	ldr	r3, [r7, #4]
+ 8033cfc:	681b      	ldr	r3, [r3, #0]
+ 8033cfe:	4a31      	ldr	r2, [pc, #196]	@ (8033dc4 <HAL_DMA_Abort+0x62c>)
+ 8033d00:	4293      	cmp	r3, r2
+ 8033d02:	d00e      	beq.n	8033d22 <HAL_DMA_Abort+0x58a>
+ 8033d04:	687b      	ldr	r3, [r7, #4]
+ 8033d06:	681b      	ldr	r3, [r3, #0]
+ 8033d08:	4a2f      	ldr	r2, [pc, #188]	@ (8033dc8 <HAL_DMA_Abort+0x630>)
+ 8033d0a:	4293      	cmp	r3, r2
+ 8033d0c:	d009      	beq.n	8033d22 <HAL_DMA_Abort+0x58a>
+ 8033d0e:	687b      	ldr	r3, [r7, #4]
+ 8033d10:	681b      	ldr	r3, [r3, #0]
+ 8033d12:	4a2e      	ldr	r2, [pc, #184]	@ (8033dcc <HAL_DMA_Abort+0x634>)
+ 8033d14:	4293      	cmp	r3, r2
+ 8033d16:	d004      	beq.n	8033d22 <HAL_DMA_Abort+0x58a>
+ 8033d18:	687b      	ldr	r3, [r7, #4]
+ 8033d1a:	681b      	ldr	r3, [r3, #0]
+ 8033d1c:	4a2c      	ldr	r2, [pc, #176]	@ (8033dd0 <HAL_DMA_Abort+0x638>)
+ 8033d1e:	4293      	cmp	r3, r2
+ 8033d20:	d101      	bne.n	8033d26 <HAL_DMA_Abort+0x58e>
+ 8033d22:	2301      	movs	r3, #1
+ 8033d24:	e000      	b.n	8033d28 <HAL_DMA_Abort+0x590>
+ 8033d26:	2300      	movs	r3, #0
+ 8033d28:	2b00      	cmp	r3, #0
+ 8033d2a:	d015      	beq.n	8033d58 <HAL_DMA_Abort+0x5c0>
+    {
+      /* Clear the DMAMUX synchro overrun flag */
+      hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+ 8033d2c:	687b      	ldr	r3, [r7, #4]
+ 8033d2e:	6e5b      	ldr	r3, [r3, #100]	@ 0x64
+ 8033d30:	687a      	ldr	r2, [r7, #4]
+ 8033d32:	6e92      	ldr	r2, [r2, #104]	@ 0x68
+ 8033d34:	605a      	str	r2, [r3, #4]
+
+      if(hdma->DMAmuxRequestGen != 0U)
+ 8033d36:	687b      	ldr	r3, [r7, #4]
+ 8033d38:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
+ 8033d3a:	2b00      	cmp	r3, #0
+ 8033d3c:	d00c      	beq.n	8033d58 <HAL_DMA_Abort+0x5c0>
+      {
+        /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT */
+        /* disable the request gen overrun IT */
+        hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
+ 8033d3e:	687b      	ldr	r3, [r7, #4]
+ 8033d40:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
+ 8033d42:	681a      	ldr	r2, [r3, #0]
+ 8033d44:	687b      	ldr	r3, [r7, #4]
+ 8033d46:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
+ 8033d48:	f422 7280 	bic.w	r2, r2, #256	@ 0x100
+ 8033d4c:	601a      	str	r2, [r3, #0]
+
+        /* Clear the DMAMUX request generator overrun flag */
+        hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+ 8033d4e:	687b      	ldr	r3, [r7, #4]
+ 8033d50:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
+ 8033d52:	687a      	ldr	r2, [r7, #4]
+ 8033d54:	6f52      	ldr	r2, [r2, #116]	@ 0x74
+ 8033d56:	605a      	str	r2, [r3, #4]
+      }
+    }
+
+    /* Change the DMA state */
+    hdma->State = HAL_DMA_STATE_READY;
+ 8033d58:	687b      	ldr	r3, [r7, #4]
+ 8033d5a:	2201      	movs	r2, #1
+ 8033d5c:	f883 2035 	strb.w	r2, [r3, #53]	@ 0x35
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
+ 8033d60:	687b      	ldr	r3, [r7, #4]
+ 8033d62:	2200      	movs	r2, #0
+ 8033d64:	f883 2034 	strb.w	r2, [r3, #52]	@ 0x34
+  }
+
+  return HAL_OK;
+ 8033d68:	2300      	movs	r3, #0
+}
+ 8033d6a:	4618      	mov	r0, r3
+ 8033d6c:	3718      	adds	r7, #24
+ 8033d6e:	46bd      	mov	sp, r7
+ 8033d70:	bd80      	pop	{r7, pc}
+ 8033d72:	bf00      	nop
+ 8033d74:	40020010 	.word	0x40020010
+ 8033d78:	40020028 	.word	0x40020028
+ 8033d7c:	40020040 	.word	0x40020040
+ 8033d80:	40020058 	.word	0x40020058
+ 8033d84:	40020070 	.word	0x40020070
+ 8033d88:	40020088 	.word	0x40020088
+ 8033d8c:	400200a0 	.word	0x400200a0
+ 8033d90:	400200b8 	.word	0x400200b8
+ 8033d94:	40020410 	.word	0x40020410
+ 8033d98:	40020428 	.word	0x40020428
+ 8033d9c:	40020440 	.word	0x40020440
+ 8033da0:	40020458 	.word	0x40020458
+ 8033da4:	40020470 	.word	0x40020470
+ 8033da8:	40020488 	.word	0x40020488
+ 8033dac:	400204a0 	.word	0x400204a0
+ 8033db0:	400204b8 	.word	0x400204b8
+ 8033db4:	58025408 	.word	0x58025408
+ 8033db8:	5802541c 	.word	0x5802541c
+ 8033dbc:	58025430 	.word	0x58025430
+ 8033dc0:	58025444 	.word	0x58025444
+ 8033dc4:	58025458 	.word	0x58025458
+ 8033dc8:	5802546c 	.word	0x5802546c
+ 8033dcc:	58025480 	.word	0x58025480
+ 8033dd0:	58025494 	.word	0x58025494
+
+08033dd4 <HAL_DMA_Abort_IT>:
+  * @param  hdma  : pointer to a DMA_HandleTypeDef structure that contains
+  *                 the configuration information for the specified DMA Stream.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
+{
+ 8033dd4:	b580      	push	{r7, lr}
+ 8033dd6:	b084      	sub	sp, #16
+ 8033dd8:	af00      	add	r7, sp, #0
+ 8033dda:	6078      	str	r0, [r7, #4]
+  BDMA_Base_Registers *regs_bdma;
+
+  /* Check the DMA peripheral handle */
+  if(hdma == NULL)
+ 8033ddc:	687b      	ldr	r3, [r7, #4]
+ 8033dde:	2b00      	cmp	r3, #0
+ 8033de0:	d101      	bne.n	8033de6 <HAL_DMA_Abort_IT+0x12>
+  {
+    return HAL_ERROR;
+ 8033de2:	2301      	movs	r3, #1
+ 8033de4:	e237      	b.n	8034256 <HAL_DMA_Abort_IT+0x482>
+  }
+
+  if(hdma->State != HAL_DMA_STATE_BUSY)
+ 8033de6:	687b      	ldr	r3, [r7, #4]
+ 8033de8:	f893 3035 	ldrb.w	r3, [r3, #53]	@ 0x35
+ 8033dec:	b2db      	uxtb	r3, r3
+ 8033dee:	2b02      	cmp	r3, #2
+ 8033df0:	d004      	beq.n	8033dfc <HAL_DMA_Abort_IT+0x28>
+  {
+    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+ 8033df2:	687b      	ldr	r3, [r7, #4]
+ 8033df4:	2280      	movs	r2, #128	@ 0x80
+ 8033df6:	655a      	str	r2, [r3, #84]	@ 0x54
+    return HAL_ERROR;
+ 8033df8:	2301      	movs	r3, #1
+ 8033dfa:	e22c      	b.n	8034256 <HAL_DMA_Abort_IT+0x482>
+  }
+  else
+  {
+    if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+ 8033dfc:	687b      	ldr	r3, [r7, #4]
+ 8033dfe:	681b      	ldr	r3, [r3, #0]
+ 8033e00:	4a5c      	ldr	r2, [pc, #368]	@ (8033f74 <HAL_DMA_Abort_IT+0x1a0>)
+ 8033e02:	4293      	cmp	r3, r2
+ 8033e04:	d04a      	beq.n	8033e9c <HAL_DMA_Abort_IT+0xc8>
+ 8033e06:	687b      	ldr	r3, [r7, #4]
+ 8033e08:	681b      	ldr	r3, [r3, #0]
+ 8033e0a:	4a5b      	ldr	r2, [pc, #364]	@ (8033f78 <HAL_DMA_Abort_IT+0x1a4>)
+ 8033e0c:	4293      	cmp	r3, r2
+ 8033e0e:	d045      	beq.n	8033e9c <HAL_DMA_Abort_IT+0xc8>
+ 8033e10:	687b      	ldr	r3, [r7, #4]
+ 8033e12:	681b      	ldr	r3, [r3, #0]
+ 8033e14:	4a59      	ldr	r2, [pc, #356]	@ (8033f7c <HAL_DMA_Abort_IT+0x1a8>)
+ 8033e16:	4293      	cmp	r3, r2
+ 8033e18:	d040      	beq.n	8033e9c <HAL_DMA_Abort_IT+0xc8>
+ 8033e1a:	687b      	ldr	r3, [r7, #4]
+ 8033e1c:	681b      	ldr	r3, [r3, #0]
+ 8033e1e:	4a58      	ldr	r2, [pc, #352]	@ (8033f80 <HAL_DMA_Abort_IT+0x1ac>)
+ 8033e20:	4293      	cmp	r3, r2
+ 8033e22:	d03b      	beq.n	8033e9c <HAL_DMA_Abort_IT+0xc8>
+ 8033e24:	687b      	ldr	r3, [r7, #4]
+ 8033e26:	681b      	ldr	r3, [r3, #0]
+ 8033e28:	4a56      	ldr	r2, [pc, #344]	@ (8033f84 <HAL_DMA_Abort_IT+0x1b0>)
+ 8033e2a:	4293      	cmp	r3, r2
+ 8033e2c:	d036      	beq.n	8033e9c <HAL_DMA_Abort_IT+0xc8>
+ 8033e2e:	687b      	ldr	r3, [r7, #4]
+ 8033e30:	681b      	ldr	r3, [r3, #0]
+ 8033e32:	4a55      	ldr	r2, [pc, #340]	@ (8033f88 <HAL_DMA_Abort_IT+0x1b4>)
+ 8033e34:	4293      	cmp	r3, r2
+ 8033e36:	d031      	beq.n	8033e9c <HAL_DMA_Abort_IT+0xc8>
+ 8033e38:	687b      	ldr	r3, [r7, #4]
+ 8033e3a:	681b      	ldr	r3, [r3, #0]
+ 8033e3c:	4a53      	ldr	r2, [pc, #332]	@ (8033f8c <HAL_DMA_Abort_IT+0x1b8>)
+ 8033e3e:	4293      	cmp	r3, r2
+ 8033e40:	d02c      	beq.n	8033e9c <HAL_DMA_Abort_IT+0xc8>
+ 8033e42:	687b      	ldr	r3, [r7, #4]
+ 8033e44:	681b      	ldr	r3, [r3, #0]
+ 8033e46:	4a52      	ldr	r2, [pc, #328]	@ (8033f90 <HAL_DMA_Abort_IT+0x1bc>)
+ 8033e48:	4293      	cmp	r3, r2
+ 8033e4a:	d027      	beq.n	8033e9c <HAL_DMA_Abort_IT+0xc8>
+ 8033e4c:	687b      	ldr	r3, [r7, #4]
+ 8033e4e:	681b      	ldr	r3, [r3, #0]
+ 8033e50:	4a50      	ldr	r2, [pc, #320]	@ (8033f94 <HAL_DMA_Abort_IT+0x1c0>)
+ 8033e52:	4293      	cmp	r3, r2
+ 8033e54:	d022      	beq.n	8033e9c <HAL_DMA_Abort_IT+0xc8>
+ 8033e56:	687b      	ldr	r3, [r7, #4]
+ 8033e58:	681b      	ldr	r3, [r3, #0]
+ 8033e5a:	4a4f      	ldr	r2, [pc, #316]	@ (8033f98 <HAL_DMA_Abort_IT+0x1c4>)
+ 8033e5c:	4293      	cmp	r3, r2
+ 8033e5e:	d01d      	beq.n	8033e9c <HAL_DMA_Abort_IT+0xc8>
+ 8033e60:	687b      	ldr	r3, [r7, #4]
+ 8033e62:	681b      	ldr	r3, [r3, #0]
+ 8033e64:	4a4d      	ldr	r2, [pc, #308]	@ (8033f9c <HAL_DMA_Abort_IT+0x1c8>)
+ 8033e66:	4293      	cmp	r3, r2
+ 8033e68:	d018      	beq.n	8033e9c <HAL_DMA_Abort_IT+0xc8>
+ 8033e6a:	687b      	ldr	r3, [r7, #4]
+ 8033e6c:	681b      	ldr	r3, [r3, #0]
+ 8033e6e:	4a4c      	ldr	r2, [pc, #304]	@ (8033fa0 <HAL_DMA_Abort_IT+0x1cc>)
+ 8033e70:	4293      	cmp	r3, r2
+ 8033e72:	d013      	beq.n	8033e9c <HAL_DMA_Abort_IT+0xc8>
+ 8033e74:	687b      	ldr	r3, [r7, #4]
+ 8033e76:	681b      	ldr	r3, [r3, #0]
+ 8033e78:	4a4a      	ldr	r2, [pc, #296]	@ (8033fa4 <HAL_DMA_Abort_IT+0x1d0>)
+ 8033e7a:	4293      	cmp	r3, r2
+ 8033e7c:	d00e      	beq.n	8033e9c <HAL_DMA_Abort_IT+0xc8>
+ 8033e7e:	687b      	ldr	r3, [r7, #4]
+ 8033e80:	681b      	ldr	r3, [r3, #0]
+ 8033e82:	4a49      	ldr	r2, [pc, #292]	@ (8033fa8 <HAL_DMA_Abort_IT+0x1d4>)
+ 8033e84:	4293      	cmp	r3, r2
+ 8033e86:	d009      	beq.n	8033e9c <HAL_DMA_Abort_IT+0xc8>
+ 8033e88:	687b      	ldr	r3, [r7, #4]
+ 8033e8a:	681b      	ldr	r3, [r3, #0]
+ 8033e8c:	4a47      	ldr	r2, [pc, #284]	@ (8033fac <HAL_DMA_Abort_IT+0x1d8>)
+ 8033e8e:	4293      	cmp	r3, r2
+ 8033e90:	d004      	beq.n	8033e9c <HAL_DMA_Abort_IT+0xc8>
+ 8033e92:	687b      	ldr	r3, [r7, #4]
+ 8033e94:	681b      	ldr	r3, [r3, #0]
+ 8033e96:	4a46      	ldr	r2, [pc, #280]	@ (8033fb0 <HAL_DMA_Abort_IT+0x1dc>)
+ 8033e98:	4293      	cmp	r3, r2
+ 8033e9a:	d101      	bne.n	8033ea0 <HAL_DMA_Abort_IT+0xcc>
+ 8033e9c:	2301      	movs	r3, #1
+ 8033e9e:	e000      	b.n	8033ea2 <HAL_DMA_Abort_IT+0xce>
+ 8033ea0:	2300      	movs	r3, #0
+ 8033ea2:	2b00      	cmp	r3, #0
+ 8033ea4:	f000 8086 	beq.w	8033fb4 <HAL_DMA_Abort_IT+0x1e0>
+    {
+      /* Set Abort State  */
+      hdma->State = HAL_DMA_STATE_ABORT;
+ 8033ea8:	687b      	ldr	r3, [r7, #4]
+ 8033eaa:	2204      	movs	r2, #4
+ 8033eac:	f883 2035 	strb.w	r2, [r3, #53]	@ 0x35
+
+      /* Disable the stream */
+      __HAL_DMA_DISABLE(hdma);
+ 8033eb0:	687b      	ldr	r3, [r7, #4]
+ 8033eb2:	681b      	ldr	r3, [r3, #0]
+ 8033eb4:	4a2f      	ldr	r2, [pc, #188]	@ (8033f74 <HAL_DMA_Abort_IT+0x1a0>)
+ 8033eb6:	4293      	cmp	r3, r2
+ 8033eb8:	d04a      	beq.n	8033f50 <HAL_DMA_Abort_IT+0x17c>
+ 8033eba:	687b      	ldr	r3, [r7, #4]
+ 8033ebc:	681b      	ldr	r3, [r3, #0]
+ 8033ebe:	4a2e      	ldr	r2, [pc, #184]	@ (8033f78 <HAL_DMA_Abort_IT+0x1a4>)
+ 8033ec0:	4293      	cmp	r3, r2
+ 8033ec2:	d045      	beq.n	8033f50 <HAL_DMA_Abort_IT+0x17c>
+ 8033ec4:	687b      	ldr	r3, [r7, #4]
+ 8033ec6:	681b      	ldr	r3, [r3, #0]
+ 8033ec8:	4a2c      	ldr	r2, [pc, #176]	@ (8033f7c <HAL_DMA_Abort_IT+0x1a8>)
+ 8033eca:	4293      	cmp	r3, r2
+ 8033ecc:	d040      	beq.n	8033f50 <HAL_DMA_Abort_IT+0x17c>
+ 8033ece:	687b      	ldr	r3, [r7, #4]
+ 8033ed0:	681b      	ldr	r3, [r3, #0]
+ 8033ed2:	4a2b      	ldr	r2, [pc, #172]	@ (8033f80 <HAL_DMA_Abort_IT+0x1ac>)
+ 8033ed4:	4293      	cmp	r3, r2
+ 8033ed6:	d03b      	beq.n	8033f50 <HAL_DMA_Abort_IT+0x17c>
+ 8033ed8:	687b      	ldr	r3, [r7, #4]
+ 8033eda:	681b      	ldr	r3, [r3, #0]
+ 8033edc:	4a29      	ldr	r2, [pc, #164]	@ (8033f84 <HAL_DMA_Abort_IT+0x1b0>)
+ 8033ede:	4293      	cmp	r3, r2
+ 8033ee0:	d036      	beq.n	8033f50 <HAL_DMA_Abort_IT+0x17c>
+ 8033ee2:	687b      	ldr	r3, [r7, #4]
+ 8033ee4:	681b      	ldr	r3, [r3, #0]
+ 8033ee6:	4a28      	ldr	r2, [pc, #160]	@ (8033f88 <HAL_DMA_Abort_IT+0x1b4>)
+ 8033ee8:	4293      	cmp	r3, r2
+ 8033eea:	d031      	beq.n	8033f50 <HAL_DMA_Abort_IT+0x17c>
+ 8033eec:	687b      	ldr	r3, [r7, #4]
+ 8033eee:	681b      	ldr	r3, [r3, #0]
+ 8033ef0:	4a26      	ldr	r2, [pc, #152]	@ (8033f8c <HAL_DMA_Abort_IT+0x1b8>)
+ 8033ef2:	4293      	cmp	r3, r2
+ 8033ef4:	d02c      	beq.n	8033f50 <HAL_DMA_Abort_IT+0x17c>
+ 8033ef6:	687b      	ldr	r3, [r7, #4]
+ 8033ef8:	681b      	ldr	r3, [r3, #0]
+ 8033efa:	4a25      	ldr	r2, [pc, #148]	@ (8033f90 <HAL_DMA_Abort_IT+0x1bc>)
+ 8033efc:	4293      	cmp	r3, r2
+ 8033efe:	d027      	beq.n	8033f50 <HAL_DMA_Abort_IT+0x17c>
+ 8033f00:	687b      	ldr	r3, [r7, #4]
+ 8033f02:	681b      	ldr	r3, [r3, #0]
+ 8033f04:	4a23      	ldr	r2, [pc, #140]	@ (8033f94 <HAL_DMA_Abort_IT+0x1c0>)
+ 8033f06:	4293      	cmp	r3, r2
+ 8033f08:	d022      	beq.n	8033f50 <HAL_DMA_Abort_IT+0x17c>
+ 8033f0a:	687b      	ldr	r3, [r7, #4]
+ 8033f0c:	681b      	ldr	r3, [r3, #0]
+ 8033f0e:	4a22      	ldr	r2, [pc, #136]	@ (8033f98 <HAL_DMA_Abort_IT+0x1c4>)
+ 8033f10:	4293      	cmp	r3, r2
+ 8033f12:	d01d      	beq.n	8033f50 <HAL_DMA_Abort_IT+0x17c>
+ 8033f14:	687b      	ldr	r3, [r7, #4]
+ 8033f16:	681b      	ldr	r3, [r3, #0]
+ 8033f18:	4a20      	ldr	r2, [pc, #128]	@ (8033f9c <HAL_DMA_Abort_IT+0x1c8>)
+ 8033f1a:	4293      	cmp	r3, r2
+ 8033f1c:	d018      	beq.n	8033f50 <HAL_DMA_Abort_IT+0x17c>
+ 8033f1e:	687b      	ldr	r3, [r7, #4]
+ 8033f20:	681b      	ldr	r3, [r3, #0]
+ 8033f22:	4a1f      	ldr	r2, [pc, #124]	@ (8033fa0 <HAL_DMA_Abort_IT+0x1cc>)
+ 8033f24:	4293      	cmp	r3, r2
+ 8033f26:	d013      	beq.n	8033f50 <HAL_DMA_Abort_IT+0x17c>
+ 8033f28:	687b      	ldr	r3, [r7, #4]
+ 8033f2a:	681b      	ldr	r3, [r3, #0]
+ 8033f2c:	4a1d      	ldr	r2, [pc, #116]	@ (8033fa4 <HAL_DMA_Abort_IT+0x1d0>)
+ 8033f2e:	4293      	cmp	r3, r2
+ 8033f30:	d00e      	beq.n	8033f50 <HAL_DMA_Abort_IT+0x17c>
+ 8033f32:	687b      	ldr	r3, [r7, #4]
+ 8033f34:	681b      	ldr	r3, [r3, #0]
+ 8033f36:	4a1c      	ldr	r2, [pc, #112]	@ (8033fa8 <HAL_DMA_Abort_IT+0x1d4>)
+ 8033f38:	4293      	cmp	r3, r2
+ 8033f3a:	d009      	beq.n	8033f50 <HAL_DMA_Abort_IT+0x17c>
+ 8033f3c:	687b      	ldr	r3, [r7, #4]
+ 8033f3e:	681b      	ldr	r3, [r3, #0]
+ 8033f40:	4a1a      	ldr	r2, [pc, #104]	@ (8033fac <HAL_DMA_Abort_IT+0x1d8>)
+ 8033f42:	4293      	cmp	r3, r2
+ 8033f44:	d004      	beq.n	8033f50 <HAL_DMA_Abort_IT+0x17c>
+ 8033f46:	687b      	ldr	r3, [r7, #4]
+ 8033f48:	681b      	ldr	r3, [r3, #0]
+ 8033f4a:	4a19      	ldr	r2, [pc, #100]	@ (8033fb0 <HAL_DMA_Abort_IT+0x1dc>)
+ 8033f4c:	4293      	cmp	r3, r2
+ 8033f4e:	d108      	bne.n	8033f62 <HAL_DMA_Abort_IT+0x18e>
+ 8033f50:	687b      	ldr	r3, [r7, #4]
+ 8033f52:	681b      	ldr	r3, [r3, #0]
+ 8033f54:	681a      	ldr	r2, [r3, #0]
+ 8033f56:	687b      	ldr	r3, [r7, #4]
+ 8033f58:	681b      	ldr	r3, [r3, #0]
+ 8033f5a:	f022 0201 	bic.w	r2, r2, #1
+ 8033f5e:	601a      	str	r2, [r3, #0]
+ 8033f60:	e178      	b.n	8034254 <HAL_DMA_Abort_IT+0x480>
+ 8033f62:	687b      	ldr	r3, [r7, #4]
+ 8033f64:	681b      	ldr	r3, [r3, #0]
+ 8033f66:	681a      	ldr	r2, [r3, #0]
+ 8033f68:	687b      	ldr	r3, [r7, #4]
+ 8033f6a:	681b      	ldr	r3, [r3, #0]
+ 8033f6c:	f022 0201 	bic.w	r2, r2, #1
+ 8033f70:	601a      	str	r2, [r3, #0]
+ 8033f72:	e16f      	b.n	8034254 <HAL_DMA_Abort_IT+0x480>
+ 8033f74:	40020010 	.word	0x40020010
+ 8033f78:	40020028 	.word	0x40020028
+ 8033f7c:	40020040 	.word	0x40020040
+ 8033f80:	40020058 	.word	0x40020058
+ 8033f84:	40020070 	.word	0x40020070
+ 8033f88:	40020088 	.word	0x40020088
+ 8033f8c:	400200a0 	.word	0x400200a0
+ 8033f90:	400200b8 	.word	0x400200b8
+ 8033f94:	40020410 	.word	0x40020410
+ 8033f98:	40020428 	.word	0x40020428
+ 8033f9c:	40020440 	.word	0x40020440
+ 8033fa0:	40020458 	.word	0x40020458
+ 8033fa4:	40020470 	.word	0x40020470
+ 8033fa8:	40020488 	.word	0x40020488
+ 8033fac:	400204a0 	.word	0x400204a0
+ 8033fb0:	400204b8 	.word	0x400204b8
+    }
+    else /* BDMA channel */
+    {
+      /* Disable DMA All Interrupts  */
+      ((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR  &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE);
+ 8033fb4:	687b      	ldr	r3, [r7, #4]
+ 8033fb6:	681b      	ldr	r3, [r3, #0]
+ 8033fb8:	681a      	ldr	r2, [r3, #0]
+ 8033fba:	687b      	ldr	r3, [r7, #4]
+ 8033fbc:	681b      	ldr	r3, [r3, #0]
+ 8033fbe:	f022 020e 	bic.w	r2, r2, #14
+ 8033fc2:	601a      	str	r2, [r3, #0]
+
+      /* Disable the channel */
+      __HAL_DMA_DISABLE(hdma);
+ 8033fc4:	687b      	ldr	r3, [r7, #4]
+ 8033fc6:	681b      	ldr	r3, [r3, #0]
+ 8033fc8:	4a6c      	ldr	r2, [pc, #432]	@ (803417c <HAL_DMA_Abort_IT+0x3a8>)
+ 8033fca:	4293      	cmp	r3, r2
+ 8033fcc:	d04a      	beq.n	8034064 <HAL_DMA_Abort_IT+0x290>
+ 8033fce:	687b      	ldr	r3, [r7, #4]
+ 8033fd0:	681b      	ldr	r3, [r3, #0]
+ 8033fd2:	4a6b      	ldr	r2, [pc, #428]	@ (8034180 <HAL_DMA_Abort_IT+0x3ac>)
+ 8033fd4:	4293      	cmp	r3, r2
+ 8033fd6:	d045      	beq.n	8034064 <HAL_DMA_Abort_IT+0x290>
+ 8033fd8:	687b      	ldr	r3, [r7, #4]
+ 8033fda:	681b      	ldr	r3, [r3, #0]
+ 8033fdc:	4a69      	ldr	r2, [pc, #420]	@ (8034184 <HAL_DMA_Abort_IT+0x3b0>)
+ 8033fde:	4293      	cmp	r3, r2
+ 8033fe0:	d040      	beq.n	8034064 <HAL_DMA_Abort_IT+0x290>
+ 8033fe2:	687b      	ldr	r3, [r7, #4]
+ 8033fe4:	681b      	ldr	r3, [r3, #0]
+ 8033fe6:	4a68      	ldr	r2, [pc, #416]	@ (8034188 <HAL_DMA_Abort_IT+0x3b4>)
+ 8033fe8:	4293      	cmp	r3, r2
+ 8033fea:	d03b      	beq.n	8034064 <HAL_DMA_Abort_IT+0x290>
+ 8033fec:	687b      	ldr	r3, [r7, #4]
+ 8033fee:	681b      	ldr	r3, [r3, #0]
+ 8033ff0:	4a66      	ldr	r2, [pc, #408]	@ (803418c <HAL_DMA_Abort_IT+0x3b8>)
+ 8033ff2:	4293      	cmp	r3, r2
+ 8033ff4:	d036      	beq.n	8034064 <HAL_DMA_Abort_IT+0x290>
+ 8033ff6:	687b      	ldr	r3, [r7, #4]
+ 8033ff8:	681b      	ldr	r3, [r3, #0]
+ 8033ffa:	4a65      	ldr	r2, [pc, #404]	@ (8034190 <HAL_DMA_Abort_IT+0x3bc>)
+ 8033ffc:	4293      	cmp	r3, r2
+ 8033ffe:	d031      	beq.n	8034064 <HAL_DMA_Abort_IT+0x290>
+ 8034000:	687b      	ldr	r3, [r7, #4]
+ 8034002:	681b      	ldr	r3, [r3, #0]
+ 8034004:	4a63      	ldr	r2, [pc, #396]	@ (8034194 <HAL_DMA_Abort_IT+0x3c0>)
+ 8034006:	4293      	cmp	r3, r2
+ 8034008:	d02c      	beq.n	8034064 <HAL_DMA_Abort_IT+0x290>
+ 803400a:	687b      	ldr	r3, [r7, #4]
+ 803400c:	681b      	ldr	r3, [r3, #0]
+ 803400e:	4a62      	ldr	r2, [pc, #392]	@ (8034198 <HAL_DMA_Abort_IT+0x3c4>)
+ 8034010:	4293      	cmp	r3, r2
+ 8034012:	d027      	beq.n	8034064 <HAL_DMA_Abort_IT+0x290>
+ 8034014:	687b      	ldr	r3, [r7, #4]
+ 8034016:	681b      	ldr	r3, [r3, #0]
+ 8034018:	4a60      	ldr	r2, [pc, #384]	@ (803419c <HAL_DMA_Abort_IT+0x3c8>)
+ 803401a:	4293      	cmp	r3, r2
+ 803401c:	d022      	beq.n	8034064 <HAL_DMA_Abort_IT+0x290>
+ 803401e:	687b      	ldr	r3, [r7, #4]
+ 8034020:	681b      	ldr	r3, [r3, #0]
+ 8034022:	4a5f      	ldr	r2, [pc, #380]	@ (80341a0 <HAL_DMA_Abort_IT+0x3cc>)
+ 8034024:	4293      	cmp	r3, r2
+ 8034026:	d01d      	beq.n	8034064 <HAL_DMA_Abort_IT+0x290>
+ 8034028:	687b      	ldr	r3, [r7, #4]
+ 803402a:	681b      	ldr	r3, [r3, #0]
+ 803402c:	4a5d      	ldr	r2, [pc, #372]	@ (80341a4 <HAL_DMA_Abort_IT+0x3d0>)
+ 803402e:	4293      	cmp	r3, r2
+ 8034030:	d018      	beq.n	8034064 <HAL_DMA_Abort_IT+0x290>
+ 8034032:	687b      	ldr	r3, [r7, #4]
+ 8034034:	681b      	ldr	r3, [r3, #0]
+ 8034036:	4a5c      	ldr	r2, [pc, #368]	@ (80341a8 <HAL_DMA_Abort_IT+0x3d4>)
+ 8034038:	4293      	cmp	r3, r2
+ 803403a:	d013      	beq.n	8034064 <HAL_DMA_Abort_IT+0x290>
+ 803403c:	687b      	ldr	r3, [r7, #4]
+ 803403e:	681b      	ldr	r3, [r3, #0]
+ 8034040:	4a5a      	ldr	r2, [pc, #360]	@ (80341ac <HAL_DMA_Abort_IT+0x3d8>)
+ 8034042:	4293      	cmp	r3, r2
+ 8034044:	d00e      	beq.n	8034064 <HAL_DMA_Abort_IT+0x290>
+ 8034046:	687b      	ldr	r3, [r7, #4]
+ 8034048:	681b      	ldr	r3, [r3, #0]
+ 803404a:	4a59      	ldr	r2, [pc, #356]	@ (80341b0 <HAL_DMA_Abort_IT+0x3dc>)
+ 803404c:	4293      	cmp	r3, r2
+ 803404e:	d009      	beq.n	8034064 <HAL_DMA_Abort_IT+0x290>
+ 8034050:	687b      	ldr	r3, [r7, #4]
+ 8034052:	681b      	ldr	r3, [r3, #0]
+ 8034054:	4a57      	ldr	r2, [pc, #348]	@ (80341b4 <HAL_DMA_Abort_IT+0x3e0>)
+ 8034056:	4293      	cmp	r3, r2
+ 8034058:	d004      	beq.n	8034064 <HAL_DMA_Abort_IT+0x290>
+ 803405a:	687b      	ldr	r3, [r7, #4]
+ 803405c:	681b      	ldr	r3, [r3, #0]
+ 803405e:	4a56      	ldr	r2, [pc, #344]	@ (80341b8 <HAL_DMA_Abort_IT+0x3e4>)
+ 8034060:	4293      	cmp	r3, r2
+ 8034062:	d108      	bne.n	8034076 <HAL_DMA_Abort_IT+0x2a2>
+ 8034064:	687b      	ldr	r3, [r7, #4]
+ 8034066:	681b      	ldr	r3, [r3, #0]
+ 8034068:	681a      	ldr	r2, [r3, #0]
+ 803406a:	687b      	ldr	r3, [r7, #4]
+ 803406c:	681b      	ldr	r3, [r3, #0]
+ 803406e:	f022 0201 	bic.w	r2, r2, #1
+ 8034072:	601a      	str	r2, [r3, #0]
+ 8034074:	e007      	b.n	8034086 <HAL_DMA_Abort_IT+0x2b2>
+ 8034076:	687b      	ldr	r3, [r7, #4]
+ 8034078:	681b      	ldr	r3, [r3, #0]
+ 803407a:	681a      	ldr	r2, [r3, #0]
+ 803407c:	687b      	ldr	r3, [r7, #4]
+ 803407e:	681b      	ldr	r3, [r3, #0]
+ 8034080:	f022 0201 	bic.w	r2, r2, #1
+ 8034084:	601a      	str	r2, [r3, #0]
+
+      if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
+ 8034086:	687b      	ldr	r3, [r7, #4]
+ 8034088:	681b      	ldr	r3, [r3, #0]
+ 803408a:	4a3c      	ldr	r2, [pc, #240]	@ (803417c <HAL_DMA_Abort_IT+0x3a8>)
+ 803408c:	4293      	cmp	r3, r2
+ 803408e:	d072      	beq.n	8034176 <HAL_DMA_Abort_IT+0x3a2>
+ 8034090:	687b      	ldr	r3, [r7, #4]
+ 8034092:	681b      	ldr	r3, [r3, #0]
+ 8034094:	4a3a      	ldr	r2, [pc, #232]	@ (8034180 <HAL_DMA_Abort_IT+0x3ac>)
+ 8034096:	4293      	cmp	r3, r2
+ 8034098:	d06d      	beq.n	8034176 <HAL_DMA_Abort_IT+0x3a2>
+ 803409a:	687b      	ldr	r3, [r7, #4]
+ 803409c:	681b      	ldr	r3, [r3, #0]
+ 803409e:	4a39      	ldr	r2, [pc, #228]	@ (8034184 <HAL_DMA_Abort_IT+0x3b0>)
+ 80340a0:	4293      	cmp	r3, r2
+ 80340a2:	d068      	beq.n	8034176 <HAL_DMA_Abort_IT+0x3a2>
+ 80340a4:	687b      	ldr	r3, [r7, #4]
+ 80340a6:	681b      	ldr	r3, [r3, #0]
+ 80340a8:	4a37      	ldr	r2, [pc, #220]	@ (8034188 <HAL_DMA_Abort_IT+0x3b4>)
+ 80340aa:	4293      	cmp	r3, r2
+ 80340ac:	d063      	beq.n	8034176 <HAL_DMA_Abort_IT+0x3a2>
+ 80340ae:	687b      	ldr	r3, [r7, #4]
+ 80340b0:	681b      	ldr	r3, [r3, #0]
+ 80340b2:	4a36      	ldr	r2, [pc, #216]	@ (803418c <HAL_DMA_Abort_IT+0x3b8>)
+ 80340b4:	4293      	cmp	r3, r2
+ 80340b6:	d05e      	beq.n	8034176 <HAL_DMA_Abort_IT+0x3a2>
+ 80340b8:	687b      	ldr	r3, [r7, #4]
+ 80340ba:	681b      	ldr	r3, [r3, #0]
+ 80340bc:	4a34      	ldr	r2, [pc, #208]	@ (8034190 <HAL_DMA_Abort_IT+0x3bc>)
+ 80340be:	4293      	cmp	r3, r2
+ 80340c0:	d059      	beq.n	8034176 <HAL_DMA_Abort_IT+0x3a2>
+ 80340c2:	687b      	ldr	r3, [r7, #4]
+ 80340c4:	681b      	ldr	r3, [r3, #0]
+ 80340c6:	4a33      	ldr	r2, [pc, #204]	@ (8034194 <HAL_DMA_Abort_IT+0x3c0>)
+ 80340c8:	4293      	cmp	r3, r2
+ 80340ca:	d054      	beq.n	8034176 <HAL_DMA_Abort_IT+0x3a2>
+ 80340cc:	687b      	ldr	r3, [r7, #4]
+ 80340ce:	681b      	ldr	r3, [r3, #0]
+ 80340d0:	4a31      	ldr	r2, [pc, #196]	@ (8034198 <HAL_DMA_Abort_IT+0x3c4>)
+ 80340d2:	4293      	cmp	r3, r2
+ 80340d4:	d04f      	beq.n	8034176 <HAL_DMA_Abort_IT+0x3a2>
+ 80340d6:	687b      	ldr	r3, [r7, #4]
+ 80340d8:	681b      	ldr	r3, [r3, #0]
+ 80340da:	4a30      	ldr	r2, [pc, #192]	@ (803419c <HAL_DMA_Abort_IT+0x3c8>)
+ 80340dc:	4293      	cmp	r3, r2
+ 80340de:	d04a      	beq.n	8034176 <HAL_DMA_Abort_IT+0x3a2>
+ 80340e0:	687b      	ldr	r3, [r7, #4]
+ 80340e2:	681b      	ldr	r3, [r3, #0]
+ 80340e4:	4a2e      	ldr	r2, [pc, #184]	@ (80341a0 <HAL_DMA_Abort_IT+0x3cc>)
+ 80340e6:	4293      	cmp	r3, r2
+ 80340e8:	d045      	beq.n	8034176 <HAL_DMA_Abort_IT+0x3a2>
+ 80340ea:	687b      	ldr	r3, [r7, #4]
+ 80340ec:	681b      	ldr	r3, [r3, #0]
+ 80340ee:	4a2d      	ldr	r2, [pc, #180]	@ (80341a4 <HAL_DMA_Abort_IT+0x3d0>)
+ 80340f0:	4293      	cmp	r3, r2
+ 80340f2:	d040      	beq.n	8034176 <HAL_DMA_Abort_IT+0x3a2>
+ 80340f4:	687b      	ldr	r3, [r7, #4]
+ 80340f6:	681b      	ldr	r3, [r3, #0]
+ 80340f8:	4a2b      	ldr	r2, [pc, #172]	@ (80341a8 <HAL_DMA_Abort_IT+0x3d4>)
+ 80340fa:	4293      	cmp	r3, r2
+ 80340fc:	d03b      	beq.n	8034176 <HAL_DMA_Abort_IT+0x3a2>
+ 80340fe:	687b      	ldr	r3, [r7, #4]
+ 8034100:	681b      	ldr	r3, [r3, #0]
+ 8034102:	4a2a      	ldr	r2, [pc, #168]	@ (80341ac <HAL_DMA_Abort_IT+0x3d8>)
+ 8034104:	4293      	cmp	r3, r2
+ 8034106:	d036      	beq.n	8034176 <HAL_DMA_Abort_IT+0x3a2>
+ 8034108:	687b      	ldr	r3, [r7, #4]
+ 803410a:	681b      	ldr	r3, [r3, #0]
+ 803410c:	4a28      	ldr	r2, [pc, #160]	@ (80341b0 <HAL_DMA_Abort_IT+0x3dc>)
+ 803410e:	4293      	cmp	r3, r2
+ 8034110:	d031      	beq.n	8034176 <HAL_DMA_Abort_IT+0x3a2>
+ 8034112:	687b      	ldr	r3, [r7, #4]
+ 8034114:	681b      	ldr	r3, [r3, #0]
+ 8034116:	4a27      	ldr	r2, [pc, #156]	@ (80341b4 <HAL_DMA_Abort_IT+0x3e0>)
+ 8034118:	4293      	cmp	r3, r2
+ 803411a:	d02c      	beq.n	8034176 <HAL_DMA_Abort_IT+0x3a2>
+ 803411c:	687b      	ldr	r3, [r7, #4]
+ 803411e:	681b      	ldr	r3, [r3, #0]
+ 8034120:	4a25      	ldr	r2, [pc, #148]	@ (80341b8 <HAL_DMA_Abort_IT+0x3e4>)
+ 8034122:	4293      	cmp	r3, r2
+ 8034124:	d027      	beq.n	8034176 <HAL_DMA_Abort_IT+0x3a2>
+ 8034126:	687b      	ldr	r3, [r7, #4]
+ 8034128:	681b      	ldr	r3, [r3, #0]
+ 803412a:	4a24      	ldr	r2, [pc, #144]	@ (80341bc <HAL_DMA_Abort_IT+0x3e8>)
+ 803412c:	4293      	cmp	r3, r2
+ 803412e:	d022      	beq.n	8034176 <HAL_DMA_Abort_IT+0x3a2>
+ 8034130:	687b      	ldr	r3, [r7, #4]
+ 8034132:	681b      	ldr	r3, [r3, #0]
+ 8034134:	4a22      	ldr	r2, [pc, #136]	@ (80341c0 <HAL_DMA_Abort_IT+0x3ec>)
+ 8034136:	4293      	cmp	r3, r2
+ 8034138:	d01d      	beq.n	8034176 <HAL_DMA_Abort_IT+0x3a2>
+ 803413a:	687b      	ldr	r3, [r7, #4]
+ 803413c:	681b      	ldr	r3, [r3, #0]
+ 803413e:	4a21      	ldr	r2, [pc, #132]	@ (80341c4 <HAL_DMA_Abort_IT+0x3f0>)
+ 8034140:	4293      	cmp	r3, r2
+ 8034142:	d018      	beq.n	8034176 <HAL_DMA_Abort_IT+0x3a2>
+ 8034144:	687b      	ldr	r3, [r7, #4]
+ 8034146:	681b      	ldr	r3, [r3, #0]
+ 8034148:	4a1f      	ldr	r2, [pc, #124]	@ (80341c8 <HAL_DMA_Abort_IT+0x3f4>)
+ 803414a:	4293      	cmp	r3, r2
+ 803414c:	d013      	beq.n	8034176 <HAL_DMA_Abort_IT+0x3a2>
+ 803414e:	687b      	ldr	r3, [r7, #4]
+ 8034150:	681b      	ldr	r3, [r3, #0]
+ 8034152:	4a1e      	ldr	r2, [pc, #120]	@ (80341cc <HAL_DMA_Abort_IT+0x3f8>)
+ 8034154:	4293      	cmp	r3, r2
+ 8034156:	d00e      	beq.n	8034176 <HAL_DMA_Abort_IT+0x3a2>
+ 8034158:	687b      	ldr	r3, [r7, #4]
+ 803415a:	681b      	ldr	r3, [r3, #0]
+ 803415c:	4a1c      	ldr	r2, [pc, #112]	@ (80341d0 <HAL_DMA_Abort_IT+0x3fc>)
+ 803415e:	4293      	cmp	r3, r2
+ 8034160:	d009      	beq.n	8034176 <HAL_DMA_Abort_IT+0x3a2>
+ 8034162:	687b      	ldr	r3, [r7, #4]
+ 8034164:	681b      	ldr	r3, [r3, #0]
+ 8034166:	4a1b      	ldr	r2, [pc, #108]	@ (80341d4 <HAL_DMA_Abort_IT+0x400>)
+ 8034168:	4293      	cmp	r3, r2
+ 803416a:	d004      	beq.n	8034176 <HAL_DMA_Abort_IT+0x3a2>
+ 803416c:	687b      	ldr	r3, [r7, #4]
+ 803416e:	681b      	ldr	r3, [r3, #0]
+ 8034170:	4a19      	ldr	r2, [pc, #100]	@ (80341d8 <HAL_DMA_Abort_IT+0x404>)
+ 8034172:	4293      	cmp	r3, r2
+ 8034174:	d132      	bne.n	80341dc <HAL_DMA_Abort_IT+0x408>
+ 8034176:	2301      	movs	r3, #1
+ 8034178:	e031      	b.n	80341de <HAL_DMA_Abort_IT+0x40a>
+ 803417a:	bf00      	nop
+ 803417c:	40020010 	.word	0x40020010
+ 8034180:	40020028 	.word	0x40020028
+ 8034184:	40020040 	.word	0x40020040
+ 8034188:	40020058 	.word	0x40020058
+ 803418c:	40020070 	.word	0x40020070
+ 8034190:	40020088 	.word	0x40020088
+ 8034194:	400200a0 	.word	0x400200a0
+ 8034198:	400200b8 	.word	0x400200b8
+ 803419c:	40020410 	.word	0x40020410
+ 80341a0:	40020428 	.word	0x40020428
+ 80341a4:	40020440 	.word	0x40020440
+ 80341a8:	40020458 	.word	0x40020458
+ 80341ac:	40020470 	.word	0x40020470
+ 80341b0:	40020488 	.word	0x40020488
+ 80341b4:	400204a0 	.word	0x400204a0
+ 80341b8:	400204b8 	.word	0x400204b8
+ 80341bc:	58025408 	.word	0x58025408
+ 80341c0:	5802541c 	.word	0x5802541c
+ 80341c4:	58025430 	.word	0x58025430
+ 80341c8:	58025444 	.word	0x58025444
+ 80341cc:	58025458 	.word	0x58025458
+ 80341d0:	5802546c 	.word	0x5802546c
+ 80341d4:	58025480 	.word	0x58025480
+ 80341d8:	58025494 	.word	0x58025494
+ 80341dc:	2300      	movs	r3, #0
+ 80341de:	2b00      	cmp	r3, #0
+ 80341e0:	d028      	beq.n	8034234 <HAL_DMA_Abort_IT+0x460>
+      {
+        /* disable the DMAMUX sync overrun IT */
+        hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
+ 80341e2:	687b      	ldr	r3, [r7, #4]
+ 80341e4:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
+ 80341e6:	681a      	ldr	r2, [r3, #0]
+ 80341e8:	687b      	ldr	r3, [r7, #4]
+ 80341ea:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
+ 80341ec:	f422 7280 	bic.w	r2, r2, #256	@ 0x100
+ 80341f0:	601a      	str	r2, [r3, #0]
+
+        /* Clear all flags */
+        regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress;
+ 80341f2:	687b      	ldr	r3, [r7, #4]
+ 80341f4:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
+ 80341f6:	60fb      	str	r3, [r7, #12]
+        regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU));
+ 80341f8:	687b      	ldr	r3, [r7, #4]
+ 80341fa:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
+ 80341fc:	f003 031f 	and.w	r3, r3, #31
+ 8034200:	2201      	movs	r2, #1
+ 8034202:	409a      	lsls	r2, r3
+ 8034204:	68fb      	ldr	r3, [r7, #12]
+ 8034206:	605a      	str	r2, [r3, #4]
+
+        /* Clear the DMAMUX synchro overrun flag */
+        hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+ 8034208:	687b      	ldr	r3, [r7, #4]
+ 803420a:	6e5b      	ldr	r3, [r3, #100]	@ 0x64
+ 803420c:	687a      	ldr	r2, [r7, #4]
+ 803420e:	6e92      	ldr	r2, [r2, #104]	@ 0x68
+ 8034210:	605a      	str	r2, [r3, #4]
+
+        if(hdma->DMAmuxRequestGen != 0U)
+ 8034212:	687b      	ldr	r3, [r7, #4]
+ 8034214:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
+ 8034216:	2b00      	cmp	r3, #0
+ 8034218:	d00c      	beq.n	8034234 <HAL_DMA_Abort_IT+0x460>
+        {
+          /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
+          /* disable the request gen overrun IT */
+          hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
+ 803421a:	687b      	ldr	r3, [r7, #4]
+ 803421c:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
+ 803421e:	681a      	ldr	r2, [r3, #0]
+ 8034220:	687b      	ldr	r3, [r7, #4]
+ 8034222:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
+ 8034224:	f422 7280 	bic.w	r2, r2, #256	@ 0x100
+ 8034228:	601a      	str	r2, [r3, #0]
+
+          /* Clear the DMAMUX request generator overrun flag */
+          hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+ 803422a:	687b      	ldr	r3, [r7, #4]
+ 803422c:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
+ 803422e:	687a      	ldr	r2, [r7, #4]
+ 8034230:	6f52      	ldr	r2, [r2, #116]	@ 0x74
+ 8034232:	605a      	str	r2, [r3, #4]
+        }
+      }
+
+      /* Change the DMA state */
+      hdma->State = HAL_DMA_STATE_READY;
+ 8034234:	687b      	ldr	r3, [r7, #4]
+ 8034236:	2201      	movs	r2, #1
+ 8034238:	f883 2035 	strb.w	r2, [r3, #53]	@ 0x35
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma);
+ 803423c:	687b      	ldr	r3, [r7, #4]
+ 803423e:	2200      	movs	r2, #0
+ 8034240:	f883 2034 	strb.w	r2, [r3, #52]	@ 0x34
+
+      /* Call User Abort callback */
+      if(hdma->XferAbortCallback != NULL)
+ 8034244:	687b      	ldr	r3, [r7, #4]
+ 8034246:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
+ 8034248:	2b00      	cmp	r3, #0
+ 803424a:	d003      	beq.n	8034254 <HAL_DMA_Abort_IT+0x480>
+      {
+        hdma->XferAbortCallback(hdma);
+ 803424c:	687b      	ldr	r3, [r7, #4]
+ 803424e:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
+ 8034250:	6878      	ldr	r0, [r7, #4]
+ 8034252:	4798      	blx	r3
+      }
+    }
+  }
+
+  return HAL_OK;
+ 8034254:	2300      	movs	r3, #0
+}
+ 8034256:	4618      	mov	r0, r3
+ 8034258:	3710      	adds	r7, #16
+ 803425a:	46bd      	mov	sp, r7
+ 803425c:	bd80      	pop	{r7, pc}
+ 803425e:	bf00      	nop
+
+08034260 <HAL_DMA_IRQHandler>:
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Stream.
+  * @retval None
+  */
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
+{
+ 8034260:	b580      	push	{r7, lr}
+ 8034262:	b08a      	sub	sp, #40	@ 0x28
+ 8034264:	af00      	add	r7, sp, #0
+ 8034266:	6078      	str	r0, [r7, #4]
+  uint32_t tmpisr_dma, tmpisr_bdma;
+  uint32_t ccr_reg;
+  __IO uint32_t count = 0U;
+ 8034268:	2300      	movs	r3, #0
+ 803426a:	60fb      	str	r3, [r7, #12]
+  uint32_t timeout = SystemCoreClock / 9600U;
+ 803426c:	4b67      	ldr	r3, [pc, #412]	@ (803440c <HAL_DMA_IRQHandler+0x1ac>)
+ 803426e:	681b      	ldr	r3, [r3, #0]
+ 8034270:	4a67      	ldr	r2, [pc, #412]	@ (8034410 <HAL_DMA_IRQHandler+0x1b0>)
+ 8034272:	fba2 2303 	umull	r2, r3, r2, r3
+ 8034276:	0a9b      	lsrs	r3, r3, #10
+ 8034278:	627b      	str	r3, [r7, #36]	@ 0x24
+
+  /* calculate DMA base and stream number */
+  DMA_Base_Registers  *regs_dma  = (DMA_Base_Registers *)hdma->StreamBaseAddress;
+ 803427a:	687b      	ldr	r3, [r7, #4]
+ 803427c:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
+ 803427e:	623b      	str	r3, [r7, #32]
+  BDMA_Base_Registers *regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress;
+ 8034280:	687b      	ldr	r3, [r7, #4]
+ 8034282:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
+ 8034284:	61fb      	str	r3, [r7, #28]
+
+  tmpisr_dma  = regs_dma->ISR;
+ 8034286:	6a3b      	ldr	r3, [r7, #32]
+ 8034288:	681b      	ldr	r3, [r3, #0]
+ 803428a:	61bb      	str	r3, [r7, #24]
+  tmpisr_bdma = regs_bdma->ISR;
+ 803428c:	69fb      	ldr	r3, [r7, #28]
+ 803428e:	681b      	ldr	r3, [r3, #0]
+ 8034290:	617b      	str	r3, [r7, #20]
+
+  if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U)  /* DMA1 or DMA2 instance */
+ 8034292:	687b      	ldr	r3, [r7, #4]
+ 8034294:	681b      	ldr	r3, [r3, #0]
+ 8034296:	4a5f      	ldr	r2, [pc, #380]	@ (8034414 <HAL_DMA_IRQHandler+0x1b4>)
+ 8034298:	4293      	cmp	r3, r2
+ 803429a:	d04a      	beq.n	8034332 <HAL_DMA_IRQHandler+0xd2>
+ 803429c:	687b      	ldr	r3, [r7, #4]
+ 803429e:	681b      	ldr	r3, [r3, #0]
+ 80342a0:	4a5d      	ldr	r2, [pc, #372]	@ (8034418 <HAL_DMA_IRQHandler+0x1b8>)
+ 80342a2:	4293      	cmp	r3, r2
+ 80342a4:	d045      	beq.n	8034332 <HAL_DMA_IRQHandler+0xd2>
+ 80342a6:	687b      	ldr	r3, [r7, #4]
+ 80342a8:	681b      	ldr	r3, [r3, #0]
+ 80342aa:	4a5c      	ldr	r2, [pc, #368]	@ (803441c <HAL_DMA_IRQHandler+0x1bc>)
+ 80342ac:	4293      	cmp	r3, r2
+ 80342ae:	d040      	beq.n	8034332 <HAL_DMA_IRQHandler+0xd2>
+ 80342b0:	687b      	ldr	r3, [r7, #4]
+ 80342b2:	681b      	ldr	r3, [r3, #0]
+ 80342b4:	4a5a      	ldr	r2, [pc, #360]	@ (8034420 <HAL_DMA_IRQHandler+0x1c0>)
+ 80342b6:	4293      	cmp	r3, r2
+ 80342b8:	d03b      	beq.n	8034332 <HAL_DMA_IRQHandler+0xd2>
+ 80342ba:	687b      	ldr	r3, [r7, #4]
+ 80342bc:	681b      	ldr	r3, [r3, #0]
+ 80342be:	4a59      	ldr	r2, [pc, #356]	@ (8034424 <HAL_DMA_IRQHandler+0x1c4>)
+ 80342c0:	4293      	cmp	r3, r2
+ 80342c2:	d036      	beq.n	8034332 <HAL_DMA_IRQHandler+0xd2>
+ 80342c4:	687b      	ldr	r3, [r7, #4]
+ 80342c6:	681b      	ldr	r3, [r3, #0]
+ 80342c8:	4a57      	ldr	r2, [pc, #348]	@ (8034428 <HAL_DMA_IRQHandler+0x1c8>)
+ 80342ca:	4293      	cmp	r3, r2
+ 80342cc:	d031      	beq.n	8034332 <HAL_DMA_IRQHandler+0xd2>
+ 80342ce:	687b      	ldr	r3, [r7, #4]
+ 80342d0:	681b      	ldr	r3, [r3, #0]
+ 80342d2:	4a56      	ldr	r2, [pc, #344]	@ (803442c <HAL_DMA_IRQHandler+0x1cc>)
+ 80342d4:	4293      	cmp	r3, r2
+ 80342d6:	d02c      	beq.n	8034332 <HAL_DMA_IRQHandler+0xd2>
+ 80342d8:	687b      	ldr	r3, [r7, #4]
+ 80342da:	681b      	ldr	r3, [r3, #0]
+ 80342dc:	4a54      	ldr	r2, [pc, #336]	@ (8034430 <HAL_DMA_IRQHandler+0x1d0>)
+ 80342de:	4293      	cmp	r3, r2
+ 80342e0:	d027      	beq.n	8034332 <HAL_DMA_IRQHandler+0xd2>
+ 80342e2:	687b      	ldr	r3, [r7, #4]
+ 80342e4:	681b      	ldr	r3, [r3, #0]
+ 80342e6:	4a53      	ldr	r2, [pc, #332]	@ (8034434 <HAL_DMA_IRQHandler+0x1d4>)
+ 80342e8:	4293      	cmp	r3, r2
+ 80342ea:	d022      	beq.n	8034332 <HAL_DMA_IRQHandler+0xd2>
+ 80342ec:	687b      	ldr	r3, [r7, #4]
+ 80342ee:	681b      	ldr	r3, [r3, #0]
+ 80342f0:	4a51      	ldr	r2, [pc, #324]	@ (8034438 <HAL_DMA_IRQHandler+0x1d8>)
+ 80342f2:	4293      	cmp	r3, r2
+ 80342f4:	d01d      	beq.n	8034332 <HAL_DMA_IRQHandler+0xd2>
+ 80342f6:	687b      	ldr	r3, [r7, #4]
+ 80342f8:	681b      	ldr	r3, [r3, #0]
+ 80342fa:	4a50      	ldr	r2, [pc, #320]	@ (803443c <HAL_DMA_IRQHandler+0x1dc>)
+ 80342fc:	4293      	cmp	r3, r2
+ 80342fe:	d018      	beq.n	8034332 <HAL_DMA_IRQHandler+0xd2>
+ 8034300:	687b      	ldr	r3, [r7, #4]
+ 8034302:	681b      	ldr	r3, [r3, #0]
+ 8034304:	4a4e      	ldr	r2, [pc, #312]	@ (8034440 <HAL_DMA_IRQHandler+0x1e0>)
+ 8034306:	4293      	cmp	r3, r2
+ 8034308:	d013      	beq.n	8034332 <HAL_DMA_IRQHandler+0xd2>
+ 803430a:	687b      	ldr	r3, [r7, #4]
+ 803430c:	681b      	ldr	r3, [r3, #0]
+ 803430e:	4a4d      	ldr	r2, [pc, #308]	@ (8034444 <HAL_DMA_IRQHandler+0x1e4>)
+ 8034310:	4293      	cmp	r3, r2
+ 8034312:	d00e      	beq.n	8034332 <HAL_DMA_IRQHandler+0xd2>
+ 8034314:	687b      	ldr	r3, [r7, #4]
+ 8034316:	681b      	ldr	r3, [r3, #0]
+ 8034318:	4a4b      	ldr	r2, [pc, #300]	@ (8034448 <HAL_DMA_IRQHandler+0x1e8>)
+ 803431a:	4293      	cmp	r3, r2
+ 803431c:	d009      	beq.n	8034332 <HAL_DMA_IRQHandler+0xd2>
+ 803431e:	687b      	ldr	r3, [r7, #4]
+ 8034320:	681b      	ldr	r3, [r3, #0]
+ 8034322:	4a4a      	ldr	r2, [pc, #296]	@ (803444c <HAL_DMA_IRQHandler+0x1ec>)
+ 8034324:	4293      	cmp	r3, r2
+ 8034326:	d004      	beq.n	8034332 <HAL_DMA_IRQHandler+0xd2>
+ 8034328:	687b      	ldr	r3, [r7, #4]
+ 803432a:	681b      	ldr	r3, [r3, #0]
+ 803432c:	4a48      	ldr	r2, [pc, #288]	@ (8034450 <HAL_DMA_IRQHandler+0x1f0>)
+ 803432e:	4293      	cmp	r3, r2
+ 8034330:	d101      	bne.n	8034336 <HAL_DMA_IRQHandler+0xd6>
+ 8034332:	2301      	movs	r3, #1
+ 8034334:	e000      	b.n	8034338 <HAL_DMA_IRQHandler+0xd8>
+ 8034336:	2300      	movs	r3, #0
+ 8034338:	2b00      	cmp	r3, #0
+ 803433a:	f000 842b 	beq.w	8034b94 <HAL_DMA_IRQHandler+0x934>
+  {
+    /* Transfer Error Interrupt management ***************************************/
+    if ((tmpisr_dma & (DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
+ 803433e:	687b      	ldr	r3, [r7, #4]
+ 8034340:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
+ 8034342:	f003 031f 	and.w	r3, r3, #31
+ 8034346:	2208      	movs	r2, #8
+ 8034348:	409a      	lsls	r2, r3
+ 803434a:	69bb      	ldr	r3, [r7, #24]
+ 803434c:	4013      	ands	r3, r2
+ 803434e:	2b00      	cmp	r3, #0
+ 8034350:	f000 80a2 	beq.w	8034498 <HAL_DMA_IRQHandler+0x238>
+    {
+      if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != 0U)
+ 8034354:	687b      	ldr	r3, [r7, #4]
+ 8034356:	681b      	ldr	r3, [r3, #0]
+ 8034358:	4a2e      	ldr	r2, [pc, #184]	@ (8034414 <HAL_DMA_IRQHandler+0x1b4>)
+ 803435a:	4293      	cmp	r3, r2
+ 803435c:	d04a      	beq.n	80343f4 <HAL_DMA_IRQHandler+0x194>
+ 803435e:	687b      	ldr	r3, [r7, #4]
+ 8034360:	681b      	ldr	r3, [r3, #0]
+ 8034362:	4a2d      	ldr	r2, [pc, #180]	@ (8034418 <HAL_DMA_IRQHandler+0x1b8>)
+ 8034364:	4293      	cmp	r3, r2
+ 8034366:	d045      	beq.n	80343f4 <HAL_DMA_IRQHandler+0x194>
+ 8034368:	687b      	ldr	r3, [r7, #4]
+ 803436a:	681b      	ldr	r3, [r3, #0]
+ 803436c:	4a2b      	ldr	r2, [pc, #172]	@ (803441c <HAL_DMA_IRQHandler+0x1bc>)
+ 803436e:	4293      	cmp	r3, r2
+ 8034370:	d040      	beq.n	80343f4 <HAL_DMA_IRQHandler+0x194>
+ 8034372:	687b      	ldr	r3, [r7, #4]
+ 8034374:	681b      	ldr	r3, [r3, #0]
+ 8034376:	4a2a      	ldr	r2, [pc, #168]	@ (8034420 <HAL_DMA_IRQHandler+0x1c0>)
+ 8034378:	4293      	cmp	r3, r2
+ 803437a:	d03b      	beq.n	80343f4 <HAL_DMA_IRQHandler+0x194>
+ 803437c:	687b      	ldr	r3, [r7, #4]
+ 803437e:	681b      	ldr	r3, [r3, #0]
+ 8034380:	4a28      	ldr	r2, [pc, #160]	@ (8034424 <HAL_DMA_IRQHandler+0x1c4>)
+ 8034382:	4293      	cmp	r3, r2
+ 8034384:	d036      	beq.n	80343f4 <HAL_DMA_IRQHandler+0x194>
+ 8034386:	687b      	ldr	r3, [r7, #4]
+ 8034388:	681b      	ldr	r3, [r3, #0]
+ 803438a:	4a27      	ldr	r2, [pc, #156]	@ (8034428 <HAL_DMA_IRQHandler+0x1c8>)
+ 803438c:	4293      	cmp	r3, r2
+ 803438e:	d031      	beq.n	80343f4 <HAL_DMA_IRQHandler+0x194>
+ 8034390:	687b      	ldr	r3, [r7, #4]
+ 8034392:	681b      	ldr	r3, [r3, #0]
+ 8034394:	4a25      	ldr	r2, [pc, #148]	@ (803442c <HAL_DMA_IRQHandler+0x1cc>)
+ 8034396:	4293      	cmp	r3, r2
+ 8034398:	d02c      	beq.n	80343f4 <HAL_DMA_IRQHandler+0x194>
+ 803439a:	687b      	ldr	r3, [r7, #4]
+ 803439c:	681b      	ldr	r3, [r3, #0]
+ 803439e:	4a24      	ldr	r2, [pc, #144]	@ (8034430 <HAL_DMA_IRQHandler+0x1d0>)
+ 80343a0:	4293      	cmp	r3, r2
+ 80343a2:	d027      	beq.n	80343f4 <HAL_DMA_IRQHandler+0x194>
+ 80343a4:	687b      	ldr	r3, [r7, #4]
+ 80343a6:	681b      	ldr	r3, [r3, #0]
+ 80343a8:	4a22      	ldr	r2, [pc, #136]	@ (8034434 <HAL_DMA_IRQHandler+0x1d4>)
+ 80343aa:	4293      	cmp	r3, r2
+ 80343ac:	d022      	beq.n	80343f4 <HAL_DMA_IRQHandler+0x194>
+ 80343ae:	687b      	ldr	r3, [r7, #4]
+ 80343b0:	681b      	ldr	r3, [r3, #0]
+ 80343b2:	4a21      	ldr	r2, [pc, #132]	@ (8034438 <HAL_DMA_IRQHandler+0x1d8>)
+ 80343b4:	4293      	cmp	r3, r2
+ 80343b6:	d01d      	beq.n	80343f4 <HAL_DMA_IRQHandler+0x194>
+ 80343b8:	687b      	ldr	r3, [r7, #4]
+ 80343ba:	681b      	ldr	r3, [r3, #0]
+ 80343bc:	4a1f      	ldr	r2, [pc, #124]	@ (803443c <HAL_DMA_IRQHandler+0x1dc>)
+ 80343be:	4293      	cmp	r3, r2
+ 80343c0:	d018      	beq.n	80343f4 <HAL_DMA_IRQHandler+0x194>
+ 80343c2:	687b      	ldr	r3, [r7, #4]
+ 80343c4:	681b      	ldr	r3, [r3, #0]
+ 80343c6:	4a1e      	ldr	r2, [pc, #120]	@ (8034440 <HAL_DMA_IRQHandler+0x1e0>)
+ 80343c8:	4293      	cmp	r3, r2
+ 80343ca:	d013      	beq.n	80343f4 <HAL_DMA_IRQHandler+0x194>
+ 80343cc:	687b      	ldr	r3, [r7, #4]
+ 80343ce:	681b      	ldr	r3, [r3, #0]
+ 80343d0:	4a1c      	ldr	r2, [pc, #112]	@ (8034444 <HAL_DMA_IRQHandler+0x1e4>)
+ 80343d2:	4293      	cmp	r3, r2
+ 80343d4:	d00e      	beq.n	80343f4 <HAL_DMA_IRQHandler+0x194>
+ 80343d6:	687b      	ldr	r3, [r7, #4]
+ 80343d8:	681b      	ldr	r3, [r3, #0]
+ 80343da:	4a1b      	ldr	r2, [pc, #108]	@ (8034448 <HAL_DMA_IRQHandler+0x1e8>)
+ 80343dc:	4293      	cmp	r3, r2
+ 80343de:	d009      	beq.n	80343f4 <HAL_DMA_IRQHandler+0x194>
+ 80343e0:	687b      	ldr	r3, [r7, #4]
+ 80343e2:	681b      	ldr	r3, [r3, #0]
+ 80343e4:	4a19      	ldr	r2, [pc, #100]	@ (803444c <HAL_DMA_IRQHandler+0x1ec>)
+ 80343e6:	4293      	cmp	r3, r2
+ 80343e8:	d004      	beq.n	80343f4 <HAL_DMA_IRQHandler+0x194>
+ 80343ea:	687b      	ldr	r3, [r7, #4]
+ 80343ec:	681b      	ldr	r3, [r3, #0]
+ 80343ee:	4a18      	ldr	r2, [pc, #96]	@ (8034450 <HAL_DMA_IRQHandler+0x1f0>)
+ 80343f0:	4293      	cmp	r3, r2
+ 80343f2:	d12f      	bne.n	8034454 <HAL_DMA_IRQHandler+0x1f4>
+ 80343f4:	687b      	ldr	r3, [r7, #4]
+ 80343f6:	681b      	ldr	r3, [r3, #0]
+ 80343f8:	681b      	ldr	r3, [r3, #0]
+ 80343fa:	f003 0304 	and.w	r3, r3, #4
+ 80343fe:	2b00      	cmp	r3, #0
+ 8034400:	bf14      	ite	ne
+ 8034402:	2301      	movne	r3, #1
+ 8034404:	2300      	moveq	r3, #0
+ 8034406:	b2db      	uxtb	r3, r3
+ 8034408:	e02e      	b.n	8034468 <HAL_DMA_IRQHandler+0x208>
+ 803440a:	bf00      	nop
+ 803440c:	2400012c 	.word	0x2400012c
+ 8034410:	1b4e81b5 	.word	0x1b4e81b5
+ 8034414:	40020010 	.word	0x40020010
+ 8034418:	40020028 	.word	0x40020028
+ 803441c:	40020040 	.word	0x40020040
+ 8034420:	40020058 	.word	0x40020058
+ 8034424:	40020070 	.word	0x40020070
+ 8034428:	40020088 	.word	0x40020088
+ 803442c:	400200a0 	.word	0x400200a0
+ 8034430:	400200b8 	.word	0x400200b8
+ 8034434:	40020410 	.word	0x40020410
+ 8034438:	40020428 	.word	0x40020428
+ 803443c:	40020440 	.word	0x40020440
+ 8034440:	40020458 	.word	0x40020458
+ 8034444:	40020470 	.word	0x40020470
+ 8034448:	40020488 	.word	0x40020488
+ 803444c:	400204a0 	.word	0x400204a0
+ 8034450:	400204b8 	.word	0x400204b8
+ 8034454:	687b      	ldr	r3, [r7, #4]
+ 8034456:	681b      	ldr	r3, [r3, #0]
+ 8034458:	681b      	ldr	r3, [r3, #0]
+ 803445a:	f003 0308 	and.w	r3, r3, #8
+ 803445e:	2b00      	cmp	r3, #0
+ 8034460:	bf14      	ite	ne
+ 8034462:	2301      	movne	r3, #1
+ 8034464:	2300      	moveq	r3, #0
+ 8034466:	b2db      	uxtb	r3, r3
+ 8034468:	2b00      	cmp	r3, #0
+ 803446a:	d015      	beq.n	8034498 <HAL_DMA_IRQHandler+0x238>
+      {
+        /* Disable the transfer error interrupt */
+        ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_TE);
+ 803446c:	687b      	ldr	r3, [r7, #4]
+ 803446e:	681b      	ldr	r3, [r3, #0]
+ 8034470:	681a      	ldr	r2, [r3, #0]
+ 8034472:	687b      	ldr	r3, [r7, #4]
+ 8034474:	681b      	ldr	r3, [r3, #0]
+ 8034476:	f022 0204 	bic.w	r2, r2, #4
+ 803447a:	601a      	str	r2, [r3, #0]
+
+        /* Clear the transfer error flag */
+        regs_dma->IFCR = DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU);
+ 803447c:	687b      	ldr	r3, [r7, #4]
+ 803447e:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
+ 8034480:	f003 031f 	and.w	r3, r3, #31
+ 8034484:	2208      	movs	r2, #8
+ 8034486:	409a      	lsls	r2, r3
+ 8034488:	6a3b      	ldr	r3, [r7, #32]
+ 803448a:	609a      	str	r2, [r3, #8]
+
+        /* Update error code */
+        hdma->ErrorCode |= HAL_DMA_ERROR_TE;
+ 803448c:	687b      	ldr	r3, [r7, #4]
+ 803448e:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
+ 8034490:	f043 0201 	orr.w	r2, r3, #1
+ 8034494:	687b      	ldr	r3, [r7, #4]
+ 8034496:	655a      	str	r2, [r3, #84]	@ 0x54
+      }
+    }
+    /* FIFO Error Interrupt management ******************************************/
+    if ((tmpisr_dma & (DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
+ 8034498:	687b      	ldr	r3, [r7, #4]
+ 803449a:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
+ 803449c:	f003 031f 	and.w	r3, r3, #31
+ 80344a0:	69ba      	ldr	r2, [r7, #24]
+ 80344a2:	fa22 f303 	lsr.w	r3, r2, r3
+ 80344a6:	f003 0301 	and.w	r3, r3, #1
+ 80344aa:	2b00      	cmp	r3, #0
+ 80344ac:	d06e      	beq.n	803458c <HAL_DMA_IRQHandler+0x32c>
+    {
+      if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != 0U)
+ 80344ae:	687b      	ldr	r3, [r7, #4]
+ 80344b0:	681b      	ldr	r3, [r3, #0]
+ 80344b2:	4a69      	ldr	r2, [pc, #420]	@ (8034658 <HAL_DMA_IRQHandler+0x3f8>)
+ 80344b4:	4293      	cmp	r3, r2
+ 80344b6:	d04a      	beq.n	803454e <HAL_DMA_IRQHandler+0x2ee>
+ 80344b8:	687b      	ldr	r3, [r7, #4]
+ 80344ba:	681b      	ldr	r3, [r3, #0]
+ 80344bc:	4a67      	ldr	r2, [pc, #412]	@ (803465c <HAL_DMA_IRQHandler+0x3fc>)
+ 80344be:	4293      	cmp	r3, r2
+ 80344c0:	d045      	beq.n	803454e <HAL_DMA_IRQHandler+0x2ee>
+ 80344c2:	687b      	ldr	r3, [r7, #4]
+ 80344c4:	681b      	ldr	r3, [r3, #0]
+ 80344c6:	4a66      	ldr	r2, [pc, #408]	@ (8034660 <HAL_DMA_IRQHandler+0x400>)
+ 80344c8:	4293      	cmp	r3, r2
+ 80344ca:	d040      	beq.n	803454e <HAL_DMA_IRQHandler+0x2ee>
+ 80344cc:	687b      	ldr	r3, [r7, #4]
+ 80344ce:	681b      	ldr	r3, [r3, #0]
+ 80344d0:	4a64      	ldr	r2, [pc, #400]	@ (8034664 <HAL_DMA_IRQHandler+0x404>)
+ 80344d2:	4293      	cmp	r3, r2
+ 80344d4:	d03b      	beq.n	803454e <HAL_DMA_IRQHandler+0x2ee>
+ 80344d6:	687b      	ldr	r3, [r7, #4]
+ 80344d8:	681b      	ldr	r3, [r3, #0]
+ 80344da:	4a63      	ldr	r2, [pc, #396]	@ (8034668 <HAL_DMA_IRQHandler+0x408>)
+ 80344dc:	4293      	cmp	r3, r2
+ 80344de:	d036      	beq.n	803454e <HAL_DMA_IRQHandler+0x2ee>
+ 80344e0:	687b      	ldr	r3, [r7, #4]
+ 80344e2:	681b      	ldr	r3, [r3, #0]
+ 80344e4:	4a61      	ldr	r2, [pc, #388]	@ (803466c <HAL_DMA_IRQHandler+0x40c>)
+ 80344e6:	4293      	cmp	r3, r2
+ 80344e8:	d031      	beq.n	803454e <HAL_DMA_IRQHandler+0x2ee>
+ 80344ea:	687b      	ldr	r3, [r7, #4]
+ 80344ec:	681b      	ldr	r3, [r3, #0]
+ 80344ee:	4a60      	ldr	r2, [pc, #384]	@ (8034670 <HAL_DMA_IRQHandler+0x410>)
+ 80344f0:	4293      	cmp	r3, r2
+ 80344f2:	d02c      	beq.n	803454e <HAL_DMA_IRQHandler+0x2ee>
+ 80344f4:	687b      	ldr	r3, [r7, #4]
+ 80344f6:	681b      	ldr	r3, [r3, #0]
+ 80344f8:	4a5e      	ldr	r2, [pc, #376]	@ (8034674 <HAL_DMA_IRQHandler+0x414>)
+ 80344fa:	4293      	cmp	r3, r2
+ 80344fc:	d027      	beq.n	803454e <HAL_DMA_IRQHandler+0x2ee>
+ 80344fe:	687b      	ldr	r3, [r7, #4]
+ 8034500:	681b      	ldr	r3, [r3, #0]
+ 8034502:	4a5d      	ldr	r2, [pc, #372]	@ (8034678 <HAL_DMA_IRQHandler+0x418>)
+ 8034504:	4293      	cmp	r3, r2
+ 8034506:	d022      	beq.n	803454e <HAL_DMA_IRQHandler+0x2ee>
+ 8034508:	687b      	ldr	r3, [r7, #4]
+ 803450a:	681b      	ldr	r3, [r3, #0]
+ 803450c:	4a5b      	ldr	r2, [pc, #364]	@ (803467c <HAL_DMA_IRQHandler+0x41c>)
+ 803450e:	4293      	cmp	r3, r2
+ 8034510:	d01d      	beq.n	803454e <HAL_DMA_IRQHandler+0x2ee>
+ 8034512:	687b      	ldr	r3, [r7, #4]
+ 8034514:	681b      	ldr	r3, [r3, #0]
+ 8034516:	4a5a      	ldr	r2, [pc, #360]	@ (8034680 <HAL_DMA_IRQHandler+0x420>)
+ 8034518:	4293      	cmp	r3, r2
+ 803451a:	d018      	beq.n	803454e <HAL_DMA_IRQHandler+0x2ee>
+ 803451c:	687b      	ldr	r3, [r7, #4]
+ 803451e:	681b      	ldr	r3, [r3, #0]
+ 8034520:	4a58      	ldr	r2, [pc, #352]	@ (8034684 <HAL_DMA_IRQHandler+0x424>)
+ 8034522:	4293      	cmp	r3, r2
+ 8034524:	d013      	beq.n	803454e <HAL_DMA_IRQHandler+0x2ee>
+ 8034526:	687b      	ldr	r3, [r7, #4]
+ 8034528:	681b      	ldr	r3, [r3, #0]
+ 803452a:	4a57      	ldr	r2, [pc, #348]	@ (8034688 <HAL_DMA_IRQHandler+0x428>)
+ 803452c:	4293      	cmp	r3, r2
+ 803452e:	d00e      	beq.n	803454e <HAL_DMA_IRQHandler+0x2ee>
+ 8034530:	687b      	ldr	r3, [r7, #4]
+ 8034532:	681b      	ldr	r3, [r3, #0]
+ 8034534:	4a55      	ldr	r2, [pc, #340]	@ (803468c <HAL_DMA_IRQHandler+0x42c>)
+ 8034536:	4293      	cmp	r3, r2
+ 8034538:	d009      	beq.n	803454e <HAL_DMA_IRQHandler+0x2ee>
+ 803453a:	687b      	ldr	r3, [r7, #4]
+ 803453c:	681b      	ldr	r3, [r3, #0]
+ 803453e:	4a54      	ldr	r2, [pc, #336]	@ (8034690 <HAL_DMA_IRQHandler+0x430>)
+ 8034540:	4293      	cmp	r3, r2
+ 8034542:	d004      	beq.n	803454e <HAL_DMA_IRQHandler+0x2ee>
+ 8034544:	687b      	ldr	r3, [r7, #4]
+ 8034546:	681b      	ldr	r3, [r3, #0]
+ 8034548:	4a52      	ldr	r2, [pc, #328]	@ (8034694 <HAL_DMA_IRQHandler+0x434>)
+ 803454a:	4293      	cmp	r3, r2
+ 803454c:	d10a      	bne.n	8034564 <HAL_DMA_IRQHandler+0x304>
+ 803454e:	687b      	ldr	r3, [r7, #4]
+ 8034550:	681b      	ldr	r3, [r3, #0]
+ 8034552:	695b      	ldr	r3, [r3, #20]
+ 8034554:	f003 0380 	and.w	r3, r3, #128	@ 0x80
+ 8034558:	2b00      	cmp	r3, #0
+ 803455a:	bf14      	ite	ne
+ 803455c:	2301      	movne	r3, #1
+ 803455e:	2300      	moveq	r3, #0
+ 8034560:	b2db      	uxtb	r3, r3
+ 8034562:	e003      	b.n	803456c <HAL_DMA_IRQHandler+0x30c>
+ 8034564:	687b      	ldr	r3, [r7, #4]
+ 8034566:	681b      	ldr	r3, [r3, #0]
+ 8034568:	681b      	ldr	r3, [r3, #0]
+ 803456a:	2300      	movs	r3, #0
+ 803456c:	2b00      	cmp	r3, #0
+ 803456e:	d00d      	beq.n	803458c <HAL_DMA_IRQHandler+0x32c>
+      {
+        /* Clear the FIFO error flag */
+        regs_dma->IFCR = DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU);
+ 8034570:	687b      	ldr	r3, [r7, #4]
+ 8034572:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
+ 8034574:	f003 031f 	and.w	r3, r3, #31
+ 8034578:	2201      	movs	r2, #1
+ 803457a:	409a      	lsls	r2, r3
+ 803457c:	6a3b      	ldr	r3, [r7, #32]
+ 803457e:	609a      	str	r2, [r3, #8]
+
+        /* Update error code */
+        hdma->ErrorCode |= HAL_DMA_ERROR_FE;
+ 8034580:	687b      	ldr	r3, [r7, #4]
+ 8034582:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
+ 8034584:	f043 0202 	orr.w	r2, r3, #2
+ 8034588:	687b      	ldr	r3, [r7, #4]
+ 803458a:	655a      	str	r2, [r3, #84]	@ 0x54
+      }
+    }
+    /* Direct Mode Error Interrupt management ***********************************/
+    if ((tmpisr_dma & (DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
+ 803458c:	687b      	ldr	r3, [r7, #4]
+ 803458e:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
+ 8034590:	f003 031f 	and.w	r3, r3, #31
+ 8034594:	2204      	movs	r2, #4
+ 8034596:	409a      	lsls	r2, r3
+ 8034598:	69bb      	ldr	r3, [r7, #24]
+ 803459a:	4013      	ands	r3, r2
+ 803459c:	2b00      	cmp	r3, #0
+ 803459e:	f000 808f 	beq.w	80346c0 <HAL_DMA_IRQHandler+0x460>
+    {
+      if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != 0U)
+ 80345a2:	687b      	ldr	r3, [r7, #4]
+ 80345a4:	681b      	ldr	r3, [r3, #0]
+ 80345a6:	4a2c      	ldr	r2, [pc, #176]	@ (8034658 <HAL_DMA_IRQHandler+0x3f8>)
+ 80345a8:	4293      	cmp	r3, r2
+ 80345aa:	d04a      	beq.n	8034642 <HAL_DMA_IRQHandler+0x3e2>
+ 80345ac:	687b      	ldr	r3, [r7, #4]
+ 80345ae:	681b      	ldr	r3, [r3, #0]
+ 80345b0:	4a2a      	ldr	r2, [pc, #168]	@ (803465c <HAL_DMA_IRQHandler+0x3fc>)
+ 80345b2:	4293      	cmp	r3, r2
+ 80345b4:	d045      	beq.n	8034642 <HAL_DMA_IRQHandler+0x3e2>
+ 80345b6:	687b      	ldr	r3, [r7, #4]
+ 80345b8:	681b      	ldr	r3, [r3, #0]
+ 80345ba:	4a29      	ldr	r2, [pc, #164]	@ (8034660 <HAL_DMA_IRQHandler+0x400>)
+ 80345bc:	4293      	cmp	r3, r2
+ 80345be:	d040      	beq.n	8034642 <HAL_DMA_IRQHandler+0x3e2>
+ 80345c0:	687b      	ldr	r3, [r7, #4]
+ 80345c2:	681b      	ldr	r3, [r3, #0]
+ 80345c4:	4a27      	ldr	r2, [pc, #156]	@ (8034664 <HAL_DMA_IRQHandler+0x404>)
+ 80345c6:	4293      	cmp	r3, r2
+ 80345c8:	d03b      	beq.n	8034642 <HAL_DMA_IRQHandler+0x3e2>
+ 80345ca:	687b      	ldr	r3, [r7, #4]
+ 80345cc:	681b      	ldr	r3, [r3, #0]
+ 80345ce:	4a26      	ldr	r2, [pc, #152]	@ (8034668 <HAL_DMA_IRQHandler+0x408>)
+ 80345d0:	4293      	cmp	r3, r2
+ 80345d2:	d036      	beq.n	8034642 <HAL_DMA_IRQHandler+0x3e2>
+ 80345d4:	687b      	ldr	r3, [r7, #4]
+ 80345d6:	681b      	ldr	r3, [r3, #0]
+ 80345d8:	4a24      	ldr	r2, [pc, #144]	@ (803466c <HAL_DMA_IRQHandler+0x40c>)
+ 80345da:	4293      	cmp	r3, r2
+ 80345dc:	d031      	beq.n	8034642 <HAL_DMA_IRQHandler+0x3e2>
+ 80345de:	687b      	ldr	r3, [r7, #4]
+ 80345e0:	681b      	ldr	r3, [r3, #0]
+ 80345e2:	4a23      	ldr	r2, [pc, #140]	@ (8034670 <HAL_DMA_IRQHandler+0x410>)
+ 80345e4:	4293      	cmp	r3, r2
+ 80345e6:	d02c      	beq.n	8034642 <HAL_DMA_IRQHandler+0x3e2>
+ 80345e8:	687b      	ldr	r3, [r7, #4]
+ 80345ea:	681b      	ldr	r3, [r3, #0]
+ 80345ec:	4a21      	ldr	r2, [pc, #132]	@ (8034674 <HAL_DMA_IRQHandler+0x414>)
+ 80345ee:	4293      	cmp	r3, r2
+ 80345f0:	d027      	beq.n	8034642 <HAL_DMA_IRQHandler+0x3e2>
+ 80345f2:	687b      	ldr	r3, [r7, #4]
+ 80345f4:	681b      	ldr	r3, [r3, #0]
+ 80345f6:	4a20      	ldr	r2, [pc, #128]	@ (8034678 <HAL_DMA_IRQHandler+0x418>)
+ 80345f8:	4293      	cmp	r3, r2
+ 80345fa:	d022      	beq.n	8034642 <HAL_DMA_IRQHandler+0x3e2>
+ 80345fc:	687b      	ldr	r3, [r7, #4]
+ 80345fe:	681b      	ldr	r3, [r3, #0]
+ 8034600:	4a1e      	ldr	r2, [pc, #120]	@ (803467c <HAL_DMA_IRQHandler+0x41c>)
+ 8034602:	4293      	cmp	r3, r2
+ 8034604:	d01d      	beq.n	8034642 <HAL_DMA_IRQHandler+0x3e2>
+ 8034606:	687b      	ldr	r3, [r7, #4]
+ 8034608:	681b      	ldr	r3, [r3, #0]
+ 803460a:	4a1d      	ldr	r2, [pc, #116]	@ (8034680 <HAL_DMA_IRQHandler+0x420>)
+ 803460c:	4293      	cmp	r3, r2
+ 803460e:	d018      	beq.n	8034642 <HAL_DMA_IRQHandler+0x3e2>
+ 8034610:	687b      	ldr	r3, [r7, #4]
+ 8034612:	681b      	ldr	r3, [r3, #0]
+ 8034614:	4a1b      	ldr	r2, [pc, #108]	@ (8034684 <HAL_DMA_IRQHandler+0x424>)
+ 8034616:	4293      	cmp	r3, r2
+ 8034618:	d013      	beq.n	8034642 <HAL_DMA_IRQHandler+0x3e2>
+ 803461a:	687b      	ldr	r3, [r7, #4]
+ 803461c:	681b      	ldr	r3, [r3, #0]
+ 803461e:	4a1a      	ldr	r2, [pc, #104]	@ (8034688 <HAL_DMA_IRQHandler+0x428>)
+ 8034620:	4293      	cmp	r3, r2
+ 8034622:	d00e      	beq.n	8034642 <HAL_DMA_IRQHandler+0x3e2>
+ 8034624:	687b      	ldr	r3, [r7, #4]
+ 8034626:	681b      	ldr	r3, [r3, #0]
+ 8034628:	4a18      	ldr	r2, [pc, #96]	@ (803468c <HAL_DMA_IRQHandler+0x42c>)
+ 803462a:	4293      	cmp	r3, r2
+ 803462c:	d009      	beq.n	8034642 <HAL_DMA_IRQHandler+0x3e2>
+ 803462e:	687b      	ldr	r3, [r7, #4]
+ 8034630:	681b      	ldr	r3, [r3, #0]
+ 8034632:	4a17      	ldr	r2, [pc, #92]	@ (8034690 <HAL_DMA_IRQHandler+0x430>)
+ 8034634:	4293      	cmp	r3, r2
+ 8034636:	d004      	beq.n	8034642 <HAL_DMA_IRQHandler+0x3e2>
+ 8034638:	687b      	ldr	r3, [r7, #4]
+ 803463a:	681b      	ldr	r3, [r3, #0]
+ 803463c:	4a15      	ldr	r2, [pc, #84]	@ (8034694 <HAL_DMA_IRQHandler+0x434>)
+ 803463e:	4293      	cmp	r3, r2
+ 8034640:	d12a      	bne.n	8034698 <HAL_DMA_IRQHandler+0x438>
+ 8034642:	687b      	ldr	r3, [r7, #4]
+ 8034644:	681b      	ldr	r3, [r3, #0]
+ 8034646:	681b      	ldr	r3, [r3, #0]
+ 8034648:	f003 0302 	and.w	r3, r3, #2
+ 803464c:	2b00      	cmp	r3, #0
+ 803464e:	bf14      	ite	ne
+ 8034650:	2301      	movne	r3, #1
+ 8034652:	2300      	moveq	r3, #0
+ 8034654:	b2db      	uxtb	r3, r3
+ 8034656:	e023      	b.n	80346a0 <HAL_DMA_IRQHandler+0x440>
+ 8034658:	40020010 	.word	0x40020010
+ 803465c:	40020028 	.word	0x40020028
+ 8034660:	40020040 	.word	0x40020040
+ 8034664:	40020058 	.word	0x40020058
+ 8034668:	40020070 	.word	0x40020070
+ 803466c:	40020088 	.word	0x40020088
+ 8034670:	400200a0 	.word	0x400200a0
+ 8034674:	400200b8 	.word	0x400200b8
+ 8034678:	40020410 	.word	0x40020410
+ 803467c:	40020428 	.word	0x40020428
+ 8034680:	40020440 	.word	0x40020440
+ 8034684:	40020458 	.word	0x40020458
+ 8034688:	40020470 	.word	0x40020470
+ 803468c:	40020488 	.word	0x40020488
+ 8034690:	400204a0 	.word	0x400204a0
+ 8034694:	400204b8 	.word	0x400204b8
+ 8034698:	687b      	ldr	r3, [r7, #4]
+ 803469a:	681b      	ldr	r3, [r3, #0]
+ 803469c:	681b      	ldr	r3, [r3, #0]
+ 803469e:	2300      	movs	r3, #0
+ 80346a0:	2b00      	cmp	r3, #0
+ 80346a2:	d00d      	beq.n	80346c0 <HAL_DMA_IRQHandler+0x460>
+      {
+        /* Clear the direct mode error flag */
+        regs_dma->IFCR = DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU);
+ 80346a4:	687b      	ldr	r3, [r7, #4]
+ 80346a6:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
+ 80346a8:	f003 031f 	and.w	r3, r3, #31
+ 80346ac:	2204      	movs	r2, #4
+ 80346ae:	409a      	lsls	r2, r3
+ 80346b0:	6a3b      	ldr	r3, [r7, #32]
+ 80346b2:	609a      	str	r2, [r3, #8]
+
+        /* Update error code */
+        hdma->ErrorCode |= HAL_DMA_ERROR_DME;
+ 80346b4:	687b      	ldr	r3, [r7, #4]
+ 80346b6:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
+ 80346b8:	f043 0204 	orr.w	r2, r3, #4
+ 80346bc:	687b      	ldr	r3, [r7, #4]
+ 80346be:	655a      	str	r2, [r3, #84]	@ 0x54
+      }
+    }
+    /* Half Transfer Complete Interrupt management ******************************/
+    if ((tmpisr_dma & (DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
+ 80346c0:	687b      	ldr	r3, [r7, #4]
+ 80346c2:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
+ 80346c4:	f003 031f 	and.w	r3, r3, #31
+ 80346c8:	2210      	movs	r2, #16
+ 80346ca:	409a      	lsls	r2, r3
+ 80346cc:	69bb      	ldr	r3, [r7, #24]
+ 80346ce:	4013      	ands	r3, r2
+ 80346d0:	2b00      	cmp	r3, #0
+ 80346d2:	f000 80a6 	beq.w	8034822 <HAL_DMA_IRQHandler+0x5c2>
+    {
+      if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != 0U)
+ 80346d6:	687b      	ldr	r3, [r7, #4]
+ 80346d8:	681b      	ldr	r3, [r3, #0]
+ 80346da:	4a85      	ldr	r2, [pc, #532]	@ (80348f0 <HAL_DMA_IRQHandler+0x690>)
+ 80346dc:	4293      	cmp	r3, r2
+ 80346de:	d04a      	beq.n	8034776 <HAL_DMA_IRQHandler+0x516>
+ 80346e0:	687b      	ldr	r3, [r7, #4]
+ 80346e2:	681b      	ldr	r3, [r3, #0]
+ 80346e4:	4a83      	ldr	r2, [pc, #524]	@ (80348f4 <HAL_DMA_IRQHandler+0x694>)
+ 80346e6:	4293      	cmp	r3, r2
+ 80346e8:	d045      	beq.n	8034776 <HAL_DMA_IRQHandler+0x516>
+ 80346ea:	687b      	ldr	r3, [r7, #4]
+ 80346ec:	681b      	ldr	r3, [r3, #0]
+ 80346ee:	4a82      	ldr	r2, [pc, #520]	@ (80348f8 <HAL_DMA_IRQHandler+0x698>)
+ 80346f0:	4293      	cmp	r3, r2
+ 80346f2:	d040      	beq.n	8034776 <HAL_DMA_IRQHandler+0x516>
+ 80346f4:	687b      	ldr	r3, [r7, #4]
+ 80346f6:	681b      	ldr	r3, [r3, #0]
+ 80346f8:	4a80      	ldr	r2, [pc, #512]	@ (80348fc <HAL_DMA_IRQHandler+0x69c>)
+ 80346fa:	4293      	cmp	r3, r2
+ 80346fc:	d03b      	beq.n	8034776 <HAL_DMA_IRQHandler+0x516>
+ 80346fe:	687b      	ldr	r3, [r7, #4]
+ 8034700:	681b      	ldr	r3, [r3, #0]
+ 8034702:	4a7f      	ldr	r2, [pc, #508]	@ (8034900 <HAL_DMA_IRQHandler+0x6a0>)
+ 8034704:	4293      	cmp	r3, r2
+ 8034706:	d036      	beq.n	8034776 <HAL_DMA_IRQHandler+0x516>
+ 8034708:	687b      	ldr	r3, [r7, #4]
+ 803470a:	681b      	ldr	r3, [r3, #0]
+ 803470c:	4a7d      	ldr	r2, [pc, #500]	@ (8034904 <HAL_DMA_IRQHandler+0x6a4>)
+ 803470e:	4293      	cmp	r3, r2
+ 8034710:	d031      	beq.n	8034776 <HAL_DMA_IRQHandler+0x516>
+ 8034712:	687b      	ldr	r3, [r7, #4]
+ 8034714:	681b      	ldr	r3, [r3, #0]
+ 8034716:	4a7c      	ldr	r2, [pc, #496]	@ (8034908 <HAL_DMA_IRQHandler+0x6a8>)
+ 8034718:	4293      	cmp	r3, r2
+ 803471a:	d02c      	beq.n	8034776 <HAL_DMA_IRQHandler+0x516>
+ 803471c:	687b      	ldr	r3, [r7, #4]
+ 803471e:	681b      	ldr	r3, [r3, #0]
+ 8034720:	4a7a      	ldr	r2, [pc, #488]	@ (803490c <HAL_DMA_IRQHandler+0x6ac>)
+ 8034722:	4293      	cmp	r3, r2
+ 8034724:	d027      	beq.n	8034776 <HAL_DMA_IRQHandler+0x516>
+ 8034726:	687b      	ldr	r3, [r7, #4]
+ 8034728:	681b      	ldr	r3, [r3, #0]
+ 803472a:	4a79      	ldr	r2, [pc, #484]	@ (8034910 <HAL_DMA_IRQHandler+0x6b0>)
+ 803472c:	4293      	cmp	r3, r2
+ 803472e:	d022      	beq.n	8034776 <HAL_DMA_IRQHandler+0x516>
+ 8034730:	687b      	ldr	r3, [r7, #4]
+ 8034732:	681b      	ldr	r3, [r3, #0]
+ 8034734:	4a77      	ldr	r2, [pc, #476]	@ (8034914 <HAL_DMA_IRQHandler+0x6b4>)
+ 8034736:	4293      	cmp	r3, r2
+ 8034738:	d01d      	beq.n	8034776 <HAL_DMA_IRQHandler+0x516>
+ 803473a:	687b      	ldr	r3, [r7, #4]
+ 803473c:	681b      	ldr	r3, [r3, #0]
+ 803473e:	4a76      	ldr	r2, [pc, #472]	@ (8034918 <HAL_DMA_IRQHandler+0x6b8>)
+ 8034740:	4293      	cmp	r3, r2
+ 8034742:	d018      	beq.n	8034776 <HAL_DMA_IRQHandler+0x516>
+ 8034744:	687b      	ldr	r3, [r7, #4]
+ 8034746:	681b      	ldr	r3, [r3, #0]
+ 8034748:	4a74      	ldr	r2, [pc, #464]	@ (803491c <HAL_DMA_IRQHandler+0x6bc>)
+ 803474a:	4293      	cmp	r3, r2
+ 803474c:	d013      	beq.n	8034776 <HAL_DMA_IRQHandler+0x516>
+ 803474e:	687b      	ldr	r3, [r7, #4]
+ 8034750:	681b      	ldr	r3, [r3, #0]
+ 8034752:	4a73      	ldr	r2, [pc, #460]	@ (8034920 <HAL_DMA_IRQHandler+0x6c0>)
+ 8034754:	4293      	cmp	r3, r2
+ 8034756:	d00e      	beq.n	8034776 <HAL_DMA_IRQHandler+0x516>
+ 8034758:	687b      	ldr	r3, [r7, #4]
+ 803475a:	681b      	ldr	r3, [r3, #0]
+ 803475c:	4a71      	ldr	r2, [pc, #452]	@ (8034924 <HAL_DMA_IRQHandler+0x6c4>)
+ 803475e:	4293      	cmp	r3, r2
+ 8034760:	d009      	beq.n	8034776 <HAL_DMA_IRQHandler+0x516>
+ 8034762:	687b      	ldr	r3, [r7, #4]
+ 8034764:	681b      	ldr	r3, [r3, #0]
+ 8034766:	4a70      	ldr	r2, [pc, #448]	@ (8034928 <HAL_DMA_IRQHandler+0x6c8>)
+ 8034768:	4293      	cmp	r3, r2
+ 803476a:	d004      	beq.n	8034776 <HAL_DMA_IRQHandler+0x516>
+ 803476c:	687b      	ldr	r3, [r7, #4]
+ 803476e:	681b      	ldr	r3, [r3, #0]
+ 8034770:	4a6e      	ldr	r2, [pc, #440]	@ (803492c <HAL_DMA_IRQHandler+0x6cc>)
+ 8034772:	4293      	cmp	r3, r2
+ 8034774:	d10a      	bne.n	803478c <HAL_DMA_IRQHandler+0x52c>
+ 8034776:	687b      	ldr	r3, [r7, #4]
+ 8034778:	681b      	ldr	r3, [r3, #0]
+ 803477a:	681b      	ldr	r3, [r3, #0]
+ 803477c:	f003 0308 	and.w	r3, r3, #8
+ 8034780:	2b00      	cmp	r3, #0
+ 8034782:	bf14      	ite	ne
+ 8034784:	2301      	movne	r3, #1
+ 8034786:	2300      	moveq	r3, #0
+ 8034788:	b2db      	uxtb	r3, r3
+ 803478a:	e009      	b.n	80347a0 <HAL_DMA_IRQHandler+0x540>
+ 803478c:	687b      	ldr	r3, [r7, #4]
+ 803478e:	681b      	ldr	r3, [r3, #0]
+ 8034790:	681b      	ldr	r3, [r3, #0]
+ 8034792:	f003 0304 	and.w	r3, r3, #4
+ 8034796:	2b00      	cmp	r3, #0
+ 8034798:	bf14      	ite	ne
+ 803479a:	2301      	movne	r3, #1
+ 803479c:	2300      	moveq	r3, #0
+ 803479e:	b2db      	uxtb	r3, r3
+ 80347a0:	2b00      	cmp	r3, #0
+ 80347a2:	d03e      	beq.n	8034822 <HAL_DMA_IRQHandler+0x5c2>
+      {
+        /* Clear the half transfer complete flag */
+        regs_dma->IFCR = DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU);
+ 80347a4:	687b      	ldr	r3, [r7, #4]
+ 80347a6:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
+ 80347a8:	f003 031f 	and.w	r3, r3, #31
+ 80347ac:	2210      	movs	r2, #16
+ 80347ae:	409a      	lsls	r2, r3
+ 80347b0:	6a3b      	ldr	r3, [r7, #32]
+ 80347b2:	609a      	str	r2, [r3, #8]
+
+        /* Multi_Buffering mode enabled */
+        if(((((DMA_Stream_TypeDef   *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U)
+ 80347b4:	687b      	ldr	r3, [r7, #4]
+ 80347b6:	681b      	ldr	r3, [r3, #0]
+ 80347b8:	681b      	ldr	r3, [r3, #0]
+ 80347ba:	f403 2380 	and.w	r3, r3, #262144	@ 0x40000
+ 80347be:	2b00      	cmp	r3, #0
+ 80347c0:	d018      	beq.n	80347f4 <HAL_DMA_IRQHandler+0x594>
+        {
+          /* Current memory buffer used is Memory 0 */
+          if((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U)
+ 80347c2:	687b      	ldr	r3, [r7, #4]
+ 80347c4:	681b      	ldr	r3, [r3, #0]
+ 80347c6:	681b      	ldr	r3, [r3, #0]
+ 80347c8:	f403 2300 	and.w	r3, r3, #524288	@ 0x80000
+ 80347cc:	2b00      	cmp	r3, #0
+ 80347ce:	d108      	bne.n	80347e2 <HAL_DMA_IRQHandler+0x582>
+          {
+            if(hdma->XferHalfCpltCallback != NULL)
+ 80347d0:	687b      	ldr	r3, [r7, #4]
+ 80347d2:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
+ 80347d4:	2b00      	cmp	r3, #0
+ 80347d6:	d024      	beq.n	8034822 <HAL_DMA_IRQHandler+0x5c2>
+            {
+              /* Half transfer callback */
+              hdma->XferHalfCpltCallback(hdma);
+ 80347d8:	687b      	ldr	r3, [r7, #4]
+ 80347da:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
+ 80347dc:	6878      	ldr	r0, [r7, #4]
+ 80347de:	4798      	blx	r3
+ 80347e0:	e01f      	b.n	8034822 <HAL_DMA_IRQHandler+0x5c2>
+            }
+          }
+          /* Current memory buffer used is Memory 1 */
+          else
+          {
+            if(hdma->XferM1HalfCpltCallback != NULL)
+ 80347e2:	687b      	ldr	r3, [r7, #4]
+ 80347e4:	6c9b      	ldr	r3, [r3, #72]	@ 0x48
+ 80347e6:	2b00      	cmp	r3, #0
+ 80347e8:	d01b      	beq.n	8034822 <HAL_DMA_IRQHandler+0x5c2>
+            {
+              /* Half transfer callback */
+              hdma->XferM1HalfCpltCallback(hdma);
+ 80347ea:	687b      	ldr	r3, [r7, #4]
+ 80347ec:	6c9b      	ldr	r3, [r3, #72]	@ 0x48
+ 80347ee:	6878      	ldr	r0, [r7, #4]
+ 80347f0:	4798      	blx	r3
+ 80347f2:	e016      	b.n	8034822 <HAL_DMA_IRQHandler+0x5c2>
+          }
+        }
+        else
+        {
+          /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
+          if((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U)
+ 80347f4:	687b      	ldr	r3, [r7, #4]
+ 80347f6:	681b      	ldr	r3, [r3, #0]
+ 80347f8:	681b      	ldr	r3, [r3, #0]
+ 80347fa:	f403 7380 	and.w	r3, r3, #256	@ 0x100
+ 80347fe:	2b00      	cmp	r3, #0
+ 8034800:	d107      	bne.n	8034812 <HAL_DMA_IRQHandler+0x5b2>
+          {
+            /* Disable the half transfer interrupt */
+            ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_HT);
+ 8034802:	687b      	ldr	r3, [r7, #4]
+ 8034804:	681b      	ldr	r3, [r3, #0]
+ 8034806:	681a      	ldr	r2, [r3, #0]
+ 8034808:	687b      	ldr	r3, [r7, #4]
+ 803480a:	681b      	ldr	r3, [r3, #0]
+ 803480c:	f022 0208 	bic.w	r2, r2, #8
+ 8034810:	601a      	str	r2, [r3, #0]
+          }
+
+          if(hdma->XferHalfCpltCallback != NULL)
+ 8034812:	687b      	ldr	r3, [r7, #4]
+ 8034814:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
+ 8034816:	2b00      	cmp	r3, #0
+ 8034818:	d003      	beq.n	8034822 <HAL_DMA_IRQHandler+0x5c2>
+          {
+            /* Half transfer callback */
+            hdma->XferHalfCpltCallback(hdma);
+ 803481a:	687b      	ldr	r3, [r7, #4]
+ 803481c:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
+ 803481e:	6878      	ldr	r0, [r7, #4]
+ 8034820:	4798      	blx	r3
+          }
+        }
+      }
+    }
+    /* Transfer Complete Interrupt management ***********************************/
+    if ((tmpisr_dma & (DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U)
+ 8034822:	687b      	ldr	r3, [r7, #4]
+ 8034824:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
+ 8034826:	f003 031f 	and.w	r3, r3, #31
+ 803482a:	2220      	movs	r2, #32
+ 803482c:	409a      	lsls	r2, r3
+ 803482e:	69bb      	ldr	r3, [r7, #24]
+ 8034830:	4013      	ands	r3, r2
+ 8034832:	2b00      	cmp	r3, #0
+ 8034834:	f000 8110 	beq.w	8034a58 <HAL_DMA_IRQHandler+0x7f8>
+    {
+      if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != 0U)
+ 8034838:	687b      	ldr	r3, [r7, #4]
+ 803483a:	681b      	ldr	r3, [r3, #0]
+ 803483c:	4a2c      	ldr	r2, [pc, #176]	@ (80348f0 <HAL_DMA_IRQHandler+0x690>)
+ 803483e:	4293      	cmp	r3, r2
+ 8034840:	d04a      	beq.n	80348d8 <HAL_DMA_IRQHandler+0x678>
+ 8034842:	687b      	ldr	r3, [r7, #4]
+ 8034844:	681b      	ldr	r3, [r3, #0]
+ 8034846:	4a2b      	ldr	r2, [pc, #172]	@ (80348f4 <HAL_DMA_IRQHandler+0x694>)
+ 8034848:	4293      	cmp	r3, r2
+ 803484a:	d045      	beq.n	80348d8 <HAL_DMA_IRQHandler+0x678>
+ 803484c:	687b      	ldr	r3, [r7, #4]
+ 803484e:	681b      	ldr	r3, [r3, #0]
+ 8034850:	4a29      	ldr	r2, [pc, #164]	@ (80348f8 <HAL_DMA_IRQHandler+0x698>)
+ 8034852:	4293      	cmp	r3, r2
+ 8034854:	d040      	beq.n	80348d8 <HAL_DMA_IRQHandler+0x678>
+ 8034856:	687b      	ldr	r3, [r7, #4]
+ 8034858:	681b      	ldr	r3, [r3, #0]
+ 803485a:	4a28      	ldr	r2, [pc, #160]	@ (80348fc <HAL_DMA_IRQHandler+0x69c>)
+ 803485c:	4293      	cmp	r3, r2
+ 803485e:	d03b      	beq.n	80348d8 <HAL_DMA_IRQHandler+0x678>
+ 8034860:	687b      	ldr	r3, [r7, #4]
+ 8034862:	681b      	ldr	r3, [r3, #0]
+ 8034864:	4a26      	ldr	r2, [pc, #152]	@ (8034900 <HAL_DMA_IRQHandler+0x6a0>)
+ 8034866:	4293      	cmp	r3, r2
+ 8034868:	d036      	beq.n	80348d8 <HAL_DMA_IRQHandler+0x678>
+ 803486a:	687b      	ldr	r3, [r7, #4]
+ 803486c:	681b      	ldr	r3, [r3, #0]
+ 803486e:	4a25      	ldr	r2, [pc, #148]	@ (8034904 <HAL_DMA_IRQHandler+0x6a4>)
+ 8034870:	4293      	cmp	r3, r2
+ 8034872:	d031      	beq.n	80348d8 <HAL_DMA_IRQHandler+0x678>
+ 8034874:	687b      	ldr	r3, [r7, #4]
+ 8034876:	681b      	ldr	r3, [r3, #0]
+ 8034878:	4a23      	ldr	r2, [pc, #140]	@ (8034908 <HAL_DMA_IRQHandler+0x6a8>)
+ 803487a:	4293      	cmp	r3, r2
+ 803487c:	d02c      	beq.n	80348d8 <HAL_DMA_IRQHandler+0x678>
+ 803487e:	687b      	ldr	r3, [r7, #4]
+ 8034880:	681b      	ldr	r3, [r3, #0]
+ 8034882:	4a22      	ldr	r2, [pc, #136]	@ (803490c <HAL_DMA_IRQHandler+0x6ac>)
+ 8034884:	4293      	cmp	r3, r2
+ 8034886:	d027      	beq.n	80348d8 <HAL_DMA_IRQHandler+0x678>
+ 8034888:	687b      	ldr	r3, [r7, #4]
+ 803488a:	681b      	ldr	r3, [r3, #0]
+ 803488c:	4a20      	ldr	r2, [pc, #128]	@ (8034910 <HAL_DMA_IRQHandler+0x6b0>)
+ 803488e:	4293      	cmp	r3, r2
+ 8034890:	d022      	beq.n	80348d8 <HAL_DMA_IRQHandler+0x678>
+ 8034892:	687b      	ldr	r3, [r7, #4]
+ 8034894:	681b      	ldr	r3, [r3, #0]
+ 8034896:	4a1f      	ldr	r2, [pc, #124]	@ (8034914 <HAL_DMA_IRQHandler+0x6b4>)
+ 8034898:	4293      	cmp	r3, r2
+ 803489a:	d01d      	beq.n	80348d8 <HAL_DMA_IRQHandler+0x678>
+ 803489c:	687b      	ldr	r3, [r7, #4]
+ 803489e:	681b      	ldr	r3, [r3, #0]
+ 80348a0:	4a1d      	ldr	r2, [pc, #116]	@ (8034918 <HAL_DMA_IRQHandler+0x6b8>)
+ 80348a2:	4293      	cmp	r3, r2
+ 80348a4:	d018      	beq.n	80348d8 <HAL_DMA_IRQHandler+0x678>
+ 80348a6:	687b      	ldr	r3, [r7, #4]
+ 80348a8:	681b      	ldr	r3, [r3, #0]
+ 80348aa:	4a1c      	ldr	r2, [pc, #112]	@ (803491c <HAL_DMA_IRQHandler+0x6bc>)
+ 80348ac:	4293      	cmp	r3, r2
+ 80348ae:	d013      	beq.n	80348d8 <HAL_DMA_IRQHandler+0x678>
+ 80348b0:	687b      	ldr	r3, [r7, #4]
+ 80348b2:	681b      	ldr	r3, [r3, #0]
+ 80348b4:	4a1a      	ldr	r2, [pc, #104]	@ (8034920 <HAL_DMA_IRQHandler+0x6c0>)
+ 80348b6:	4293      	cmp	r3, r2
+ 80348b8:	d00e      	beq.n	80348d8 <HAL_DMA_IRQHandler+0x678>
+ 80348ba:	687b      	ldr	r3, [r7, #4]
+ 80348bc:	681b      	ldr	r3, [r3, #0]
+ 80348be:	4a19      	ldr	r2, [pc, #100]	@ (8034924 <HAL_DMA_IRQHandler+0x6c4>)
+ 80348c0:	4293      	cmp	r3, r2
+ 80348c2:	d009      	beq.n	80348d8 <HAL_DMA_IRQHandler+0x678>
+ 80348c4:	687b      	ldr	r3, [r7, #4]
+ 80348c6:	681b      	ldr	r3, [r3, #0]
+ 80348c8:	4a17      	ldr	r2, [pc, #92]	@ (8034928 <HAL_DMA_IRQHandler+0x6c8>)
+ 80348ca:	4293      	cmp	r3, r2
+ 80348cc:	d004      	beq.n	80348d8 <HAL_DMA_IRQHandler+0x678>
+ 80348ce:	687b      	ldr	r3, [r7, #4]
+ 80348d0:	681b      	ldr	r3, [r3, #0]
+ 80348d2:	4a16      	ldr	r2, [pc, #88]	@ (803492c <HAL_DMA_IRQHandler+0x6cc>)
+ 80348d4:	4293      	cmp	r3, r2
+ 80348d6:	d12b      	bne.n	8034930 <HAL_DMA_IRQHandler+0x6d0>
+ 80348d8:	687b      	ldr	r3, [r7, #4]
+ 80348da:	681b      	ldr	r3, [r3, #0]
+ 80348dc:	681b      	ldr	r3, [r3, #0]
+ 80348de:	f003 0310 	and.w	r3, r3, #16
+ 80348e2:	2b00      	cmp	r3, #0
+ 80348e4:	bf14      	ite	ne
+ 80348e6:	2301      	movne	r3, #1
+ 80348e8:	2300      	moveq	r3, #0
+ 80348ea:	b2db      	uxtb	r3, r3
+ 80348ec:	e02a      	b.n	8034944 <HAL_DMA_IRQHandler+0x6e4>
+ 80348ee:	bf00      	nop
+ 80348f0:	40020010 	.word	0x40020010
+ 80348f4:	40020028 	.word	0x40020028
+ 80348f8:	40020040 	.word	0x40020040
+ 80348fc:	40020058 	.word	0x40020058
+ 8034900:	40020070 	.word	0x40020070
+ 8034904:	40020088 	.word	0x40020088
+ 8034908:	400200a0 	.word	0x400200a0
+ 803490c:	400200b8 	.word	0x400200b8
+ 8034910:	40020410 	.word	0x40020410
+ 8034914:	40020428 	.word	0x40020428
+ 8034918:	40020440 	.word	0x40020440
+ 803491c:	40020458 	.word	0x40020458
+ 8034920:	40020470 	.word	0x40020470
+ 8034924:	40020488 	.word	0x40020488
+ 8034928:	400204a0 	.word	0x400204a0
+ 803492c:	400204b8 	.word	0x400204b8
+ 8034930:	687b      	ldr	r3, [r7, #4]
+ 8034932:	681b      	ldr	r3, [r3, #0]
+ 8034934:	681b      	ldr	r3, [r3, #0]
+ 8034936:	f003 0302 	and.w	r3, r3, #2
+ 803493a:	2b00      	cmp	r3, #0
+ 803493c:	bf14      	ite	ne
+ 803493e:	2301      	movne	r3, #1
+ 8034940:	2300      	moveq	r3, #0
+ 8034942:	b2db      	uxtb	r3, r3
+ 8034944:	2b00      	cmp	r3, #0
+ 8034946:	f000 8087 	beq.w	8034a58 <HAL_DMA_IRQHandler+0x7f8>
+      {
+        /* Clear the transfer complete flag */
+        regs_dma->IFCR = DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU);
+ 803494a:	687b      	ldr	r3, [r7, #4]
+ 803494c:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
+ 803494e:	f003 031f 	and.w	r3, r3, #31
+ 8034952:	2220      	movs	r2, #32
+ 8034954:	409a      	lsls	r2, r3
+ 8034956:	6a3b      	ldr	r3, [r7, #32]
+ 8034958:	609a      	str	r2, [r3, #8]
+
+        if(HAL_DMA_STATE_ABORT == hdma->State)
+ 803495a:	687b      	ldr	r3, [r7, #4]
+ 803495c:	f893 3035 	ldrb.w	r3, [r3, #53]	@ 0x35
+ 8034960:	b2db      	uxtb	r3, r3
+ 8034962:	2b04      	cmp	r3, #4
+ 8034964:	d139      	bne.n	80349da <HAL_DMA_IRQHandler+0x77a>
+        {
+          /* Disable all the transfer interrupts */
+          ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);
+ 8034966:	687b      	ldr	r3, [r7, #4]
+ 8034968:	681b      	ldr	r3, [r3, #0]
+ 803496a:	681a      	ldr	r2, [r3, #0]
+ 803496c:	687b      	ldr	r3, [r7, #4]
+ 803496e:	681b      	ldr	r3, [r3, #0]
+ 8034970:	f022 0216 	bic.w	r2, r2, #22
+ 8034974:	601a      	str	r2, [r3, #0]
+          ((DMA_Stream_TypeDef   *)hdma->Instance)->FCR &= ~(DMA_IT_FE);
+ 8034976:	687b      	ldr	r3, [r7, #4]
+ 8034978:	681b      	ldr	r3, [r3, #0]
+ 803497a:	695a      	ldr	r2, [r3, #20]
+ 803497c:	687b      	ldr	r3, [r7, #4]
+ 803497e:	681b      	ldr	r3, [r3, #0]
+ 8034980:	f022 0280 	bic.w	r2, r2, #128	@ 0x80
+ 8034984:	615a      	str	r2, [r3, #20]
+
+          if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
+ 8034986:	687b      	ldr	r3, [r7, #4]
+ 8034988:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
+ 803498a:	2b00      	cmp	r3, #0
+ 803498c:	d103      	bne.n	8034996 <HAL_DMA_IRQHandler+0x736>
+ 803498e:	687b      	ldr	r3, [r7, #4]
+ 8034990:	6c9b      	ldr	r3, [r3, #72]	@ 0x48
+ 8034992:	2b00      	cmp	r3, #0
+ 8034994:	d007      	beq.n	80349a6 <HAL_DMA_IRQHandler+0x746>
+          {
+            ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_HT);
+ 8034996:	687b      	ldr	r3, [r7, #4]
+ 8034998:	681b      	ldr	r3, [r3, #0]
+ 803499a:	681a      	ldr	r2, [r3, #0]
+ 803499c:	687b      	ldr	r3, [r7, #4]
+ 803499e:	681b      	ldr	r3, [r3, #0]
+ 80349a0:	f022 0208 	bic.w	r2, r2, #8
+ 80349a4:	601a      	str	r2, [r3, #0]
+          }
+
+          /* Clear all interrupt flags at correct offset within the register */
+          regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);
+ 80349a6:	687b      	ldr	r3, [r7, #4]
+ 80349a8:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
+ 80349aa:	f003 031f 	and.w	r3, r3, #31
+ 80349ae:	223f      	movs	r2, #63	@ 0x3f
+ 80349b0:	409a      	lsls	r2, r3
+ 80349b2:	6a3b      	ldr	r3, [r7, #32]
+ 80349b4:	609a      	str	r2, [r3, #8]
+
+          /* Change the DMA state */
+          hdma->State = HAL_DMA_STATE_READY;
+ 80349b6:	687b      	ldr	r3, [r7, #4]
+ 80349b8:	2201      	movs	r2, #1
+ 80349ba:	f883 2035 	strb.w	r2, [r3, #53]	@ 0x35
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hdma);
+ 80349be:	687b      	ldr	r3, [r7, #4]
+ 80349c0:	2200      	movs	r2, #0
+ 80349c2:	f883 2034 	strb.w	r2, [r3, #52]	@ 0x34
+
+          if(hdma->XferAbortCallback != NULL)
+ 80349c6:	687b      	ldr	r3, [r7, #4]
+ 80349c8:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
+ 80349ca:	2b00      	cmp	r3, #0
+ 80349cc:	f000 834a 	beq.w	8035064 <HAL_DMA_IRQHandler+0xe04>
+          {
+            hdma->XferAbortCallback(hdma);
+ 80349d0:	687b      	ldr	r3, [r7, #4]
+ 80349d2:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
+ 80349d4:	6878      	ldr	r0, [r7, #4]
+ 80349d6:	4798      	blx	r3
+          }
+          return;
+ 80349d8:	e344      	b.n	8035064 <HAL_DMA_IRQHandler+0xe04>
+        }
+
+        if(((((DMA_Stream_TypeDef   *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U)
+ 80349da:	687b      	ldr	r3, [r7, #4]
+ 80349dc:	681b      	ldr	r3, [r3, #0]
+ 80349de:	681b      	ldr	r3, [r3, #0]
+ 80349e0:	f403 2380 	and.w	r3, r3, #262144	@ 0x40000
+ 80349e4:	2b00      	cmp	r3, #0
+ 80349e6:	d018      	beq.n	8034a1a <HAL_DMA_IRQHandler+0x7ba>
+        {
+          /* Current memory buffer used is Memory 0 */
+          if((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U)
+ 80349e8:	687b      	ldr	r3, [r7, #4]
+ 80349ea:	681b      	ldr	r3, [r3, #0]
+ 80349ec:	681b      	ldr	r3, [r3, #0]
+ 80349ee:	f403 2300 	and.w	r3, r3, #524288	@ 0x80000
+ 80349f2:	2b00      	cmp	r3, #0
+ 80349f4:	d108      	bne.n	8034a08 <HAL_DMA_IRQHandler+0x7a8>
+          {
+            if(hdma->XferM1CpltCallback != NULL)
+ 80349f6:	687b      	ldr	r3, [r7, #4]
+ 80349f8:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
+ 80349fa:	2b00      	cmp	r3, #0
+ 80349fc:	d02c      	beq.n	8034a58 <HAL_DMA_IRQHandler+0x7f8>
+            {
+              /* Transfer complete Callback for memory1 */
+              hdma->XferM1CpltCallback(hdma);
+ 80349fe:	687b      	ldr	r3, [r7, #4]
+ 8034a00:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
+ 8034a02:	6878      	ldr	r0, [r7, #4]
+ 8034a04:	4798      	blx	r3
+ 8034a06:	e027      	b.n	8034a58 <HAL_DMA_IRQHandler+0x7f8>
+            }
+          }
+          /* Current memory buffer used is Memory 1 */
+          else
+          {
+            if(hdma->XferCpltCallback != NULL)
+ 8034a08:	687b      	ldr	r3, [r7, #4]
+ 8034a0a:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 8034a0c:	2b00      	cmp	r3, #0
+ 8034a0e:	d023      	beq.n	8034a58 <HAL_DMA_IRQHandler+0x7f8>
+            {
+              /* Transfer complete Callback for memory0 */
+              hdma->XferCpltCallback(hdma);
+ 8034a10:	687b      	ldr	r3, [r7, #4]
+ 8034a12:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 8034a14:	6878      	ldr	r0, [r7, #4]
+ 8034a16:	4798      	blx	r3
+ 8034a18:	e01e      	b.n	8034a58 <HAL_DMA_IRQHandler+0x7f8>
+          }
+        }
+        /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */
+        else
+        {
+          if((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U)
+ 8034a1a:	687b      	ldr	r3, [r7, #4]
+ 8034a1c:	681b      	ldr	r3, [r3, #0]
+ 8034a1e:	681b      	ldr	r3, [r3, #0]
+ 8034a20:	f403 7380 	and.w	r3, r3, #256	@ 0x100
+ 8034a24:	2b00      	cmp	r3, #0
+ 8034a26:	d10f      	bne.n	8034a48 <HAL_DMA_IRQHandler+0x7e8>
+          {
+            /* Disable the transfer complete interrupt */
+            ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_TC);
+ 8034a28:	687b      	ldr	r3, [r7, #4]
+ 8034a2a:	681b      	ldr	r3, [r3, #0]
+ 8034a2c:	681a      	ldr	r2, [r3, #0]
+ 8034a2e:	687b      	ldr	r3, [r7, #4]
+ 8034a30:	681b      	ldr	r3, [r3, #0]
+ 8034a32:	f022 0210 	bic.w	r2, r2, #16
+ 8034a36:	601a      	str	r2, [r3, #0]
+
+            /* Change the DMA state */
+            hdma->State = HAL_DMA_STATE_READY;
+ 8034a38:	687b      	ldr	r3, [r7, #4]
+ 8034a3a:	2201      	movs	r2, #1
+ 8034a3c:	f883 2035 	strb.w	r2, [r3, #53]	@ 0x35
+
+            /* Process Unlocked */
+            __HAL_UNLOCK(hdma);
+ 8034a40:	687b      	ldr	r3, [r7, #4]
+ 8034a42:	2200      	movs	r2, #0
+ 8034a44:	f883 2034 	strb.w	r2, [r3, #52]	@ 0x34
+          }
+
+          if(hdma->XferCpltCallback != NULL)
+ 8034a48:	687b      	ldr	r3, [r7, #4]
+ 8034a4a:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 8034a4c:	2b00      	cmp	r3, #0
+ 8034a4e:	d003      	beq.n	8034a58 <HAL_DMA_IRQHandler+0x7f8>
+          {
+            /* Transfer complete callback */
+            hdma->XferCpltCallback(hdma);
+ 8034a50:	687b      	ldr	r3, [r7, #4]
+ 8034a52:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 8034a54:	6878      	ldr	r0, [r7, #4]
+ 8034a56:	4798      	blx	r3
+        }
+      }
+    }
+
+    /* manage error case */
+    if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
+ 8034a58:	687b      	ldr	r3, [r7, #4]
+ 8034a5a:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
+ 8034a5c:	2b00      	cmp	r3, #0
+ 8034a5e:	f000 8306 	beq.w	803506e <HAL_DMA_IRQHandler+0xe0e>
+    {
+      if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != 0U)
+ 8034a62:	687b      	ldr	r3, [r7, #4]
+ 8034a64:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
+ 8034a66:	f003 0301 	and.w	r3, r3, #1
+ 8034a6a:	2b00      	cmp	r3, #0
+ 8034a6c:	f000 8088 	beq.w	8034b80 <HAL_DMA_IRQHandler+0x920>
+      {
+        hdma->State = HAL_DMA_STATE_ABORT;
+ 8034a70:	687b      	ldr	r3, [r7, #4]
+ 8034a72:	2204      	movs	r2, #4
+ 8034a74:	f883 2035 	strb.w	r2, [r3, #53]	@ 0x35
+
+        /* Disable the stream */
+        __HAL_DMA_DISABLE(hdma);
+ 8034a78:	687b      	ldr	r3, [r7, #4]
+ 8034a7a:	681b      	ldr	r3, [r3, #0]
+ 8034a7c:	4a7a      	ldr	r2, [pc, #488]	@ (8034c68 <HAL_DMA_IRQHandler+0xa08>)
+ 8034a7e:	4293      	cmp	r3, r2
+ 8034a80:	d04a      	beq.n	8034b18 <HAL_DMA_IRQHandler+0x8b8>
+ 8034a82:	687b      	ldr	r3, [r7, #4]
+ 8034a84:	681b      	ldr	r3, [r3, #0]
+ 8034a86:	4a79      	ldr	r2, [pc, #484]	@ (8034c6c <HAL_DMA_IRQHandler+0xa0c>)
+ 8034a88:	4293      	cmp	r3, r2
+ 8034a8a:	d045      	beq.n	8034b18 <HAL_DMA_IRQHandler+0x8b8>
+ 8034a8c:	687b      	ldr	r3, [r7, #4]
+ 8034a8e:	681b      	ldr	r3, [r3, #0]
+ 8034a90:	4a77      	ldr	r2, [pc, #476]	@ (8034c70 <HAL_DMA_IRQHandler+0xa10>)
+ 8034a92:	4293      	cmp	r3, r2
+ 8034a94:	d040      	beq.n	8034b18 <HAL_DMA_IRQHandler+0x8b8>
+ 8034a96:	687b      	ldr	r3, [r7, #4]
+ 8034a98:	681b      	ldr	r3, [r3, #0]
+ 8034a9a:	4a76      	ldr	r2, [pc, #472]	@ (8034c74 <HAL_DMA_IRQHandler+0xa14>)
+ 8034a9c:	4293      	cmp	r3, r2
+ 8034a9e:	d03b      	beq.n	8034b18 <HAL_DMA_IRQHandler+0x8b8>
+ 8034aa0:	687b      	ldr	r3, [r7, #4]
+ 8034aa2:	681b      	ldr	r3, [r3, #0]
+ 8034aa4:	4a74      	ldr	r2, [pc, #464]	@ (8034c78 <HAL_DMA_IRQHandler+0xa18>)
+ 8034aa6:	4293      	cmp	r3, r2
+ 8034aa8:	d036      	beq.n	8034b18 <HAL_DMA_IRQHandler+0x8b8>
+ 8034aaa:	687b      	ldr	r3, [r7, #4]
+ 8034aac:	681b      	ldr	r3, [r3, #0]
+ 8034aae:	4a73      	ldr	r2, [pc, #460]	@ (8034c7c <HAL_DMA_IRQHandler+0xa1c>)
+ 8034ab0:	4293      	cmp	r3, r2
+ 8034ab2:	d031      	beq.n	8034b18 <HAL_DMA_IRQHandler+0x8b8>
+ 8034ab4:	687b      	ldr	r3, [r7, #4]
+ 8034ab6:	681b      	ldr	r3, [r3, #0]
+ 8034ab8:	4a71      	ldr	r2, [pc, #452]	@ (8034c80 <HAL_DMA_IRQHandler+0xa20>)
+ 8034aba:	4293      	cmp	r3, r2
+ 8034abc:	d02c      	beq.n	8034b18 <HAL_DMA_IRQHandler+0x8b8>
+ 8034abe:	687b      	ldr	r3, [r7, #4]
+ 8034ac0:	681b      	ldr	r3, [r3, #0]
+ 8034ac2:	4a70      	ldr	r2, [pc, #448]	@ (8034c84 <HAL_DMA_IRQHandler+0xa24>)
+ 8034ac4:	4293      	cmp	r3, r2
+ 8034ac6:	d027      	beq.n	8034b18 <HAL_DMA_IRQHandler+0x8b8>
+ 8034ac8:	687b      	ldr	r3, [r7, #4]
+ 8034aca:	681b      	ldr	r3, [r3, #0]
+ 8034acc:	4a6e      	ldr	r2, [pc, #440]	@ (8034c88 <HAL_DMA_IRQHandler+0xa28>)
+ 8034ace:	4293      	cmp	r3, r2
+ 8034ad0:	d022      	beq.n	8034b18 <HAL_DMA_IRQHandler+0x8b8>
+ 8034ad2:	687b      	ldr	r3, [r7, #4]
+ 8034ad4:	681b      	ldr	r3, [r3, #0]
+ 8034ad6:	4a6d      	ldr	r2, [pc, #436]	@ (8034c8c <HAL_DMA_IRQHandler+0xa2c>)
+ 8034ad8:	4293      	cmp	r3, r2
+ 8034ada:	d01d      	beq.n	8034b18 <HAL_DMA_IRQHandler+0x8b8>
+ 8034adc:	687b      	ldr	r3, [r7, #4]
+ 8034ade:	681b      	ldr	r3, [r3, #0]
+ 8034ae0:	4a6b      	ldr	r2, [pc, #428]	@ (8034c90 <HAL_DMA_IRQHandler+0xa30>)
+ 8034ae2:	4293      	cmp	r3, r2
+ 8034ae4:	d018      	beq.n	8034b18 <HAL_DMA_IRQHandler+0x8b8>
+ 8034ae6:	687b      	ldr	r3, [r7, #4]
+ 8034ae8:	681b      	ldr	r3, [r3, #0]
+ 8034aea:	4a6a      	ldr	r2, [pc, #424]	@ (8034c94 <HAL_DMA_IRQHandler+0xa34>)
+ 8034aec:	4293      	cmp	r3, r2
+ 8034aee:	d013      	beq.n	8034b18 <HAL_DMA_IRQHandler+0x8b8>
+ 8034af0:	687b      	ldr	r3, [r7, #4]
+ 8034af2:	681b      	ldr	r3, [r3, #0]
+ 8034af4:	4a68      	ldr	r2, [pc, #416]	@ (8034c98 <HAL_DMA_IRQHandler+0xa38>)
+ 8034af6:	4293      	cmp	r3, r2
+ 8034af8:	d00e      	beq.n	8034b18 <HAL_DMA_IRQHandler+0x8b8>
+ 8034afa:	687b      	ldr	r3, [r7, #4]
+ 8034afc:	681b      	ldr	r3, [r3, #0]
+ 8034afe:	4a67      	ldr	r2, [pc, #412]	@ (8034c9c <HAL_DMA_IRQHandler+0xa3c>)
+ 8034b00:	4293      	cmp	r3, r2
+ 8034b02:	d009      	beq.n	8034b18 <HAL_DMA_IRQHandler+0x8b8>
+ 8034b04:	687b      	ldr	r3, [r7, #4]
+ 8034b06:	681b      	ldr	r3, [r3, #0]
+ 8034b08:	4a65      	ldr	r2, [pc, #404]	@ (8034ca0 <HAL_DMA_IRQHandler+0xa40>)
+ 8034b0a:	4293      	cmp	r3, r2
+ 8034b0c:	d004      	beq.n	8034b18 <HAL_DMA_IRQHandler+0x8b8>
+ 8034b0e:	687b      	ldr	r3, [r7, #4]
+ 8034b10:	681b      	ldr	r3, [r3, #0]
+ 8034b12:	4a64      	ldr	r2, [pc, #400]	@ (8034ca4 <HAL_DMA_IRQHandler+0xa44>)
+ 8034b14:	4293      	cmp	r3, r2
+ 8034b16:	d108      	bne.n	8034b2a <HAL_DMA_IRQHandler+0x8ca>
+ 8034b18:	687b      	ldr	r3, [r7, #4]
+ 8034b1a:	681b      	ldr	r3, [r3, #0]
+ 8034b1c:	681a      	ldr	r2, [r3, #0]
+ 8034b1e:	687b      	ldr	r3, [r7, #4]
+ 8034b20:	681b      	ldr	r3, [r3, #0]
+ 8034b22:	f022 0201 	bic.w	r2, r2, #1
+ 8034b26:	601a      	str	r2, [r3, #0]
+ 8034b28:	e007      	b.n	8034b3a <HAL_DMA_IRQHandler+0x8da>
+ 8034b2a:	687b      	ldr	r3, [r7, #4]
+ 8034b2c:	681b      	ldr	r3, [r3, #0]
+ 8034b2e:	681a      	ldr	r2, [r3, #0]
+ 8034b30:	687b      	ldr	r3, [r7, #4]
+ 8034b32:	681b      	ldr	r3, [r3, #0]
+ 8034b34:	f022 0201 	bic.w	r2, r2, #1
+ 8034b38:	601a      	str	r2, [r3, #0]
+
+        do
+        {
+          if (++count > timeout)
+ 8034b3a:	68fb      	ldr	r3, [r7, #12]
+ 8034b3c:	3301      	adds	r3, #1
+ 8034b3e:	60fb      	str	r3, [r7, #12]
+ 8034b40:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
+ 8034b42:	429a      	cmp	r2, r3
+ 8034b44:	d307      	bcc.n	8034b56 <HAL_DMA_IRQHandler+0x8f6>
+          {
+            break;
+          }
+        }
+        while((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U);
+ 8034b46:	687b      	ldr	r3, [r7, #4]
+ 8034b48:	681b      	ldr	r3, [r3, #0]
+ 8034b4a:	681b      	ldr	r3, [r3, #0]
+ 8034b4c:	f003 0301 	and.w	r3, r3, #1
+ 8034b50:	2b00      	cmp	r3, #0
+ 8034b52:	d1f2      	bne.n	8034b3a <HAL_DMA_IRQHandler+0x8da>
+ 8034b54:	e000      	b.n	8034b58 <HAL_DMA_IRQHandler+0x8f8>
+            break;
+ 8034b56:	bf00      	nop
+
+        if((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U)
+ 8034b58:	687b      	ldr	r3, [r7, #4]
+ 8034b5a:	681b      	ldr	r3, [r3, #0]
+ 8034b5c:	681b      	ldr	r3, [r3, #0]
+ 8034b5e:	f003 0301 	and.w	r3, r3, #1
+ 8034b62:	2b00      	cmp	r3, #0
+ 8034b64:	d004      	beq.n	8034b70 <HAL_DMA_IRQHandler+0x910>
+        {
+          /* Change the DMA state to error if DMA disable fails */
+          hdma->State = HAL_DMA_STATE_ERROR;
+ 8034b66:	687b      	ldr	r3, [r7, #4]
+ 8034b68:	2203      	movs	r2, #3
+ 8034b6a:	f883 2035 	strb.w	r2, [r3, #53]	@ 0x35
+ 8034b6e:	e003      	b.n	8034b78 <HAL_DMA_IRQHandler+0x918>
+        }
+        else
+        {
+          /* Change the DMA state to Ready if DMA disable success */
+          hdma->State = HAL_DMA_STATE_READY;
+ 8034b70:	687b      	ldr	r3, [r7, #4]
+ 8034b72:	2201      	movs	r2, #1
+ 8034b74:	f883 2035 	strb.w	r2, [r3, #53]	@ 0x35
+        }
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hdma);
+ 8034b78:	687b      	ldr	r3, [r7, #4]
+ 8034b7a:	2200      	movs	r2, #0
+ 8034b7c:	f883 2034 	strb.w	r2, [r3, #52]	@ 0x34
+      }
+
+      if(hdma->XferErrorCallback != NULL)
+ 8034b80:	687b      	ldr	r3, [r7, #4]
+ 8034b82:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
+ 8034b84:	2b00      	cmp	r3, #0
+ 8034b86:	f000 8272 	beq.w	803506e <HAL_DMA_IRQHandler+0xe0e>
+      {
+        /* Transfer error callback */
+        hdma->XferErrorCallback(hdma);
+ 8034b8a:	687b      	ldr	r3, [r7, #4]
+ 8034b8c:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
+ 8034b8e:	6878      	ldr	r0, [r7, #4]
+ 8034b90:	4798      	blx	r3
+ 8034b92:	e26c      	b.n	803506e <HAL_DMA_IRQHandler+0xe0e>
+      }
+    }
+  }
+  else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U)  /* BDMA instance(s) */
+ 8034b94:	687b      	ldr	r3, [r7, #4]
+ 8034b96:	681b      	ldr	r3, [r3, #0]
+ 8034b98:	4a43      	ldr	r2, [pc, #268]	@ (8034ca8 <HAL_DMA_IRQHandler+0xa48>)
+ 8034b9a:	4293      	cmp	r3, r2
+ 8034b9c:	d022      	beq.n	8034be4 <HAL_DMA_IRQHandler+0x984>
+ 8034b9e:	687b      	ldr	r3, [r7, #4]
+ 8034ba0:	681b      	ldr	r3, [r3, #0]
+ 8034ba2:	4a42      	ldr	r2, [pc, #264]	@ (8034cac <HAL_DMA_IRQHandler+0xa4c>)
+ 8034ba4:	4293      	cmp	r3, r2
+ 8034ba6:	d01d      	beq.n	8034be4 <HAL_DMA_IRQHandler+0x984>
+ 8034ba8:	687b      	ldr	r3, [r7, #4]
+ 8034baa:	681b      	ldr	r3, [r3, #0]
+ 8034bac:	4a40      	ldr	r2, [pc, #256]	@ (8034cb0 <HAL_DMA_IRQHandler+0xa50>)
+ 8034bae:	4293      	cmp	r3, r2
+ 8034bb0:	d018      	beq.n	8034be4 <HAL_DMA_IRQHandler+0x984>
+ 8034bb2:	687b      	ldr	r3, [r7, #4]
+ 8034bb4:	681b      	ldr	r3, [r3, #0]
+ 8034bb6:	4a3f      	ldr	r2, [pc, #252]	@ (8034cb4 <HAL_DMA_IRQHandler+0xa54>)
+ 8034bb8:	4293      	cmp	r3, r2
+ 8034bba:	d013      	beq.n	8034be4 <HAL_DMA_IRQHandler+0x984>
+ 8034bbc:	687b      	ldr	r3, [r7, #4]
+ 8034bbe:	681b      	ldr	r3, [r3, #0]
+ 8034bc0:	4a3d      	ldr	r2, [pc, #244]	@ (8034cb8 <HAL_DMA_IRQHandler+0xa58>)
+ 8034bc2:	4293      	cmp	r3, r2
+ 8034bc4:	d00e      	beq.n	8034be4 <HAL_DMA_IRQHandler+0x984>
+ 8034bc6:	687b      	ldr	r3, [r7, #4]
+ 8034bc8:	681b      	ldr	r3, [r3, #0]
+ 8034bca:	4a3c      	ldr	r2, [pc, #240]	@ (8034cbc <HAL_DMA_IRQHandler+0xa5c>)
+ 8034bcc:	4293      	cmp	r3, r2
+ 8034bce:	d009      	beq.n	8034be4 <HAL_DMA_IRQHandler+0x984>
+ 8034bd0:	687b      	ldr	r3, [r7, #4]
+ 8034bd2:	681b      	ldr	r3, [r3, #0]
+ 8034bd4:	4a3a      	ldr	r2, [pc, #232]	@ (8034cc0 <HAL_DMA_IRQHandler+0xa60>)
+ 8034bd6:	4293      	cmp	r3, r2
+ 8034bd8:	d004      	beq.n	8034be4 <HAL_DMA_IRQHandler+0x984>
+ 8034bda:	687b      	ldr	r3, [r7, #4]
+ 8034bdc:	681b      	ldr	r3, [r3, #0]
+ 8034bde:	4a39      	ldr	r2, [pc, #228]	@ (8034cc4 <HAL_DMA_IRQHandler+0xa64>)
+ 8034be0:	4293      	cmp	r3, r2
+ 8034be2:	d101      	bne.n	8034be8 <HAL_DMA_IRQHandler+0x988>
+ 8034be4:	2301      	movs	r3, #1
+ 8034be6:	e000      	b.n	8034bea <HAL_DMA_IRQHandler+0x98a>
+ 8034be8:	2300      	movs	r3, #0
+ 8034bea:	2b00      	cmp	r3, #0
+ 8034bec:	f000 823f 	beq.w	803506e <HAL_DMA_IRQHandler+0xe0e>
+  {
+    ccr_reg = (((BDMA_Channel_TypeDef   *)hdma->Instance)->CCR);
+ 8034bf0:	687b      	ldr	r3, [r7, #4]
+ 8034bf2:	681b      	ldr	r3, [r3, #0]
+ 8034bf4:	681b      	ldr	r3, [r3, #0]
+ 8034bf6:	613b      	str	r3, [r7, #16]
+
+    /* Half Transfer Complete Interrupt management ******************************/
+    if (((tmpisr_bdma & (BDMA_FLAG_HT0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_HTIE) != 0U))
+ 8034bf8:	687b      	ldr	r3, [r7, #4]
+ 8034bfa:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
+ 8034bfc:	f003 031f 	and.w	r3, r3, #31
+ 8034c00:	2204      	movs	r2, #4
+ 8034c02:	409a      	lsls	r2, r3
+ 8034c04:	697b      	ldr	r3, [r7, #20]
+ 8034c06:	4013      	ands	r3, r2
+ 8034c08:	2b00      	cmp	r3, #0
+ 8034c0a:	f000 80cd 	beq.w	8034da8 <HAL_DMA_IRQHandler+0xb48>
+ 8034c0e:	693b      	ldr	r3, [r7, #16]
+ 8034c10:	f003 0304 	and.w	r3, r3, #4
+ 8034c14:	2b00      	cmp	r3, #0
+ 8034c16:	f000 80c7 	beq.w	8034da8 <HAL_DMA_IRQHandler+0xb48>
+    {
+      /* Clear the half transfer complete flag */
+      regs_bdma->IFCR = (BDMA_ISR_HTIF0 << (hdma->StreamIndex & 0x1FU));
+ 8034c1a:	687b      	ldr	r3, [r7, #4]
+ 8034c1c:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
+ 8034c1e:	f003 031f 	and.w	r3, r3, #31
+ 8034c22:	2204      	movs	r2, #4
+ 8034c24:	409a      	lsls	r2, r3
+ 8034c26:	69fb      	ldr	r3, [r7, #28]
+ 8034c28:	605a      	str	r2, [r3, #4]
+
+      /* Disable the transfer complete interrupt if the DMA mode is Double Buffering */
+      if((ccr_reg & BDMA_CCR_DBM) != 0U)
+ 8034c2a:	693b      	ldr	r3, [r7, #16]
+ 8034c2c:	f403 4300 	and.w	r3, r3, #32768	@ 0x8000
+ 8034c30:	2b00      	cmp	r3, #0
+ 8034c32:	d049      	beq.n	8034cc8 <HAL_DMA_IRQHandler+0xa68>
+      {
+        /* Current memory buffer used is Memory 0 */
+        if((ccr_reg & BDMA_CCR_CT) == 0U)
+ 8034c34:	693b      	ldr	r3, [r7, #16]
+ 8034c36:	f403 3380 	and.w	r3, r3, #65536	@ 0x10000
+ 8034c3a:	2b00      	cmp	r3, #0
+ 8034c3c:	d109      	bne.n	8034c52 <HAL_DMA_IRQHandler+0x9f2>
+        {
+          if(hdma->XferM1HalfCpltCallback != NULL)
+ 8034c3e:	687b      	ldr	r3, [r7, #4]
+ 8034c40:	6c9b      	ldr	r3, [r3, #72]	@ 0x48
+ 8034c42:	2b00      	cmp	r3, #0
+ 8034c44:	f000 8210 	beq.w	8035068 <HAL_DMA_IRQHandler+0xe08>
+          {
+            /* Half transfer Callback for Memory 1 */
+            hdma->XferM1HalfCpltCallback(hdma);
+ 8034c48:	687b      	ldr	r3, [r7, #4]
+ 8034c4a:	6c9b      	ldr	r3, [r3, #72]	@ 0x48
+ 8034c4c:	6878      	ldr	r0, [r7, #4]
+ 8034c4e:	4798      	blx	r3
+      if((ccr_reg & BDMA_CCR_DBM) != 0U)
+ 8034c50:	e20a      	b.n	8035068 <HAL_DMA_IRQHandler+0xe08>
+          }
+        }
+        /* Current memory buffer used is Memory 1 */
+        else
+        {
+          if(hdma->XferHalfCpltCallback != NULL)
+ 8034c52:	687b      	ldr	r3, [r7, #4]
+ 8034c54:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
+ 8034c56:	2b00      	cmp	r3, #0
+ 8034c58:	f000 8206 	beq.w	8035068 <HAL_DMA_IRQHandler+0xe08>
+          {
+            /* Half transfer Callback for Memory 0 */
+            hdma->XferHalfCpltCallback(hdma);
+ 8034c5c:	687b      	ldr	r3, [r7, #4]
+ 8034c5e:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
+ 8034c60:	6878      	ldr	r0, [r7, #4]
+ 8034c62:	4798      	blx	r3
+      if((ccr_reg & BDMA_CCR_DBM) != 0U)
+ 8034c64:	e200      	b.n	8035068 <HAL_DMA_IRQHandler+0xe08>
+ 8034c66:	bf00      	nop
+ 8034c68:	40020010 	.word	0x40020010
+ 8034c6c:	40020028 	.word	0x40020028
+ 8034c70:	40020040 	.word	0x40020040
+ 8034c74:	40020058 	.word	0x40020058
+ 8034c78:	40020070 	.word	0x40020070
+ 8034c7c:	40020088 	.word	0x40020088
+ 8034c80:	400200a0 	.word	0x400200a0
+ 8034c84:	400200b8 	.word	0x400200b8
+ 8034c88:	40020410 	.word	0x40020410
+ 8034c8c:	40020428 	.word	0x40020428
+ 8034c90:	40020440 	.word	0x40020440
+ 8034c94:	40020458 	.word	0x40020458
+ 8034c98:	40020470 	.word	0x40020470
+ 8034c9c:	40020488 	.word	0x40020488
+ 8034ca0:	400204a0 	.word	0x400204a0
+ 8034ca4:	400204b8 	.word	0x400204b8
+ 8034ca8:	58025408 	.word	0x58025408
+ 8034cac:	5802541c 	.word	0x5802541c
+ 8034cb0:	58025430 	.word	0x58025430
+ 8034cb4:	58025444 	.word	0x58025444
+ 8034cb8:	58025458 	.word	0x58025458
+ 8034cbc:	5802546c 	.word	0x5802546c
+ 8034cc0:	58025480 	.word	0x58025480
+ 8034cc4:	58025494 	.word	0x58025494
+          }
+        }
+      }
+      else
+      {
+        if((ccr_reg & BDMA_CCR_CIRC) == 0U)
+ 8034cc8:	693b      	ldr	r3, [r7, #16]
+ 8034cca:	f003 0320 	and.w	r3, r3, #32
+ 8034cce:	2b00      	cmp	r3, #0
+ 8034cd0:	d160      	bne.n	8034d94 <HAL_DMA_IRQHandler+0xb34>
+        {
+          /* Disable the half transfer interrupt */
+          __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
+ 8034cd2:	687b      	ldr	r3, [r7, #4]
+ 8034cd4:	681b      	ldr	r3, [r3, #0]
+ 8034cd6:	4a7f      	ldr	r2, [pc, #508]	@ (8034ed4 <HAL_DMA_IRQHandler+0xc74>)
+ 8034cd8:	4293      	cmp	r3, r2
+ 8034cda:	d04a      	beq.n	8034d72 <HAL_DMA_IRQHandler+0xb12>
+ 8034cdc:	687b      	ldr	r3, [r7, #4]
+ 8034cde:	681b      	ldr	r3, [r3, #0]
+ 8034ce0:	4a7d      	ldr	r2, [pc, #500]	@ (8034ed8 <HAL_DMA_IRQHandler+0xc78>)
+ 8034ce2:	4293      	cmp	r3, r2
+ 8034ce4:	d045      	beq.n	8034d72 <HAL_DMA_IRQHandler+0xb12>
+ 8034ce6:	687b      	ldr	r3, [r7, #4]
+ 8034ce8:	681b      	ldr	r3, [r3, #0]
+ 8034cea:	4a7c      	ldr	r2, [pc, #496]	@ (8034edc <HAL_DMA_IRQHandler+0xc7c>)
+ 8034cec:	4293      	cmp	r3, r2
+ 8034cee:	d040      	beq.n	8034d72 <HAL_DMA_IRQHandler+0xb12>
+ 8034cf0:	687b      	ldr	r3, [r7, #4]
+ 8034cf2:	681b      	ldr	r3, [r3, #0]
+ 8034cf4:	4a7a      	ldr	r2, [pc, #488]	@ (8034ee0 <HAL_DMA_IRQHandler+0xc80>)
+ 8034cf6:	4293      	cmp	r3, r2
+ 8034cf8:	d03b      	beq.n	8034d72 <HAL_DMA_IRQHandler+0xb12>
+ 8034cfa:	687b      	ldr	r3, [r7, #4]
+ 8034cfc:	681b      	ldr	r3, [r3, #0]
+ 8034cfe:	4a79      	ldr	r2, [pc, #484]	@ (8034ee4 <HAL_DMA_IRQHandler+0xc84>)
+ 8034d00:	4293      	cmp	r3, r2
+ 8034d02:	d036      	beq.n	8034d72 <HAL_DMA_IRQHandler+0xb12>
+ 8034d04:	687b      	ldr	r3, [r7, #4]
+ 8034d06:	681b      	ldr	r3, [r3, #0]
+ 8034d08:	4a77      	ldr	r2, [pc, #476]	@ (8034ee8 <HAL_DMA_IRQHandler+0xc88>)
+ 8034d0a:	4293      	cmp	r3, r2
+ 8034d0c:	d031      	beq.n	8034d72 <HAL_DMA_IRQHandler+0xb12>
+ 8034d0e:	687b      	ldr	r3, [r7, #4]
+ 8034d10:	681b      	ldr	r3, [r3, #0]
+ 8034d12:	4a76      	ldr	r2, [pc, #472]	@ (8034eec <HAL_DMA_IRQHandler+0xc8c>)
+ 8034d14:	4293      	cmp	r3, r2
+ 8034d16:	d02c      	beq.n	8034d72 <HAL_DMA_IRQHandler+0xb12>
+ 8034d18:	687b      	ldr	r3, [r7, #4]
+ 8034d1a:	681b      	ldr	r3, [r3, #0]
+ 8034d1c:	4a74      	ldr	r2, [pc, #464]	@ (8034ef0 <HAL_DMA_IRQHandler+0xc90>)
+ 8034d1e:	4293      	cmp	r3, r2
+ 8034d20:	d027      	beq.n	8034d72 <HAL_DMA_IRQHandler+0xb12>
+ 8034d22:	687b      	ldr	r3, [r7, #4]
+ 8034d24:	681b      	ldr	r3, [r3, #0]
+ 8034d26:	4a73      	ldr	r2, [pc, #460]	@ (8034ef4 <HAL_DMA_IRQHandler+0xc94>)
+ 8034d28:	4293      	cmp	r3, r2
+ 8034d2a:	d022      	beq.n	8034d72 <HAL_DMA_IRQHandler+0xb12>
+ 8034d2c:	687b      	ldr	r3, [r7, #4]
+ 8034d2e:	681b      	ldr	r3, [r3, #0]
+ 8034d30:	4a71      	ldr	r2, [pc, #452]	@ (8034ef8 <HAL_DMA_IRQHandler+0xc98>)
+ 8034d32:	4293      	cmp	r3, r2
+ 8034d34:	d01d      	beq.n	8034d72 <HAL_DMA_IRQHandler+0xb12>
+ 8034d36:	687b      	ldr	r3, [r7, #4]
+ 8034d38:	681b      	ldr	r3, [r3, #0]
+ 8034d3a:	4a70      	ldr	r2, [pc, #448]	@ (8034efc <HAL_DMA_IRQHandler+0xc9c>)
+ 8034d3c:	4293      	cmp	r3, r2
+ 8034d3e:	d018      	beq.n	8034d72 <HAL_DMA_IRQHandler+0xb12>
+ 8034d40:	687b      	ldr	r3, [r7, #4]
+ 8034d42:	681b      	ldr	r3, [r3, #0]
+ 8034d44:	4a6e      	ldr	r2, [pc, #440]	@ (8034f00 <HAL_DMA_IRQHandler+0xca0>)
+ 8034d46:	4293      	cmp	r3, r2
+ 8034d48:	d013      	beq.n	8034d72 <HAL_DMA_IRQHandler+0xb12>
+ 8034d4a:	687b      	ldr	r3, [r7, #4]
+ 8034d4c:	681b      	ldr	r3, [r3, #0]
+ 8034d4e:	4a6d      	ldr	r2, [pc, #436]	@ (8034f04 <HAL_DMA_IRQHandler+0xca4>)
+ 8034d50:	4293      	cmp	r3, r2
+ 8034d52:	d00e      	beq.n	8034d72 <HAL_DMA_IRQHandler+0xb12>
+ 8034d54:	687b      	ldr	r3, [r7, #4]
+ 8034d56:	681b      	ldr	r3, [r3, #0]
+ 8034d58:	4a6b      	ldr	r2, [pc, #428]	@ (8034f08 <HAL_DMA_IRQHandler+0xca8>)
+ 8034d5a:	4293      	cmp	r3, r2
+ 8034d5c:	d009      	beq.n	8034d72 <HAL_DMA_IRQHandler+0xb12>
+ 8034d5e:	687b      	ldr	r3, [r7, #4]
+ 8034d60:	681b      	ldr	r3, [r3, #0]
+ 8034d62:	4a6a      	ldr	r2, [pc, #424]	@ (8034f0c <HAL_DMA_IRQHandler+0xcac>)
+ 8034d64:	4293      	cmp	r3, r2
+ 8034d66:	d004      	beq.n	8034d72 <HAL_DMA_IRQHandler+0xb12>
+ 8034d68:	687b      	ldr	r3, [r7, #4]
+ 8034d6a:	681b      	ldr	r3, [r3, #0]
+ 8034d6c:	4a68      	ldr	r2, [pc, #416]	@ (8034f10 <HAL_DMA_IRQHandler+0xcb0>)
+ 8034d6e:	4293      	cmp	r3, r2
+ 8034d70:	d108      	bne.n	8034d84 <HAL_DMA_IRQHandler+0xb24>
+ 8034d72:	687b      	ldr	r3, [r7, #4]
+ 8034d74:	681b      	ldr	r3, [r3, #0]
+ 8034d76:	681a      	ldr	r2, [r3, #0]
+ 8034d78:	687b      	ldr	r3, [r7, #4]
+ 8034d7a:	681b      	ldr	r3, [r3, #0]
+ 8034d7c:	f022 0208 	bic.w	r2, r2, #8
+ 8034d80:	601a      	str	r2, [r3, #0]
+ 8034d82:	e007      	b.n	8034d94 <HAL_DMA_IRQHandler+0xb34>
+ 8034d84:	687b      	ldr	r3, [r7, #4]
+ 8034d86:	681b      	ldr	r3, [r3, #0]
+ 8034d88:	681a      	ldr	r2, [r3, #0]
+ 8034d8a:	687b      	ldr	r3, [r7, #4]
+ 8034d8c:	681b      	ldr	r3, [r3, #0]
+ 8034d8e:	f022 0204 	bic.w	r2, r2, #4
+ 8034d92:	601a      	str	r2, [r3, #0]
+        }
+
+        /* DMA peripheral state is not updated in Half Transfer */
+        /* but in Transfer Complete case */
+
+       if(hdma->XferHalfCpltCallback != NULL)
+ 8034d94:	687b      	ldr	r3, [r7, #4]
+ 8034d96:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
+ 8034d98:	2b00      	cmp	r3, #0
+ 8034d9a:	f000 8165 	beq.w	8035068 <HAL_DMA_IRQHandler+0xe08>
+        {
+          /* Half transfer callback */
+          hdma->XferHalfCpltCallback(hdma);
+ 8034d9e:	687b      	ldr	r3, [r7, #4]
+ 8034da0:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
+ 8034da2:	6878      	ldr	r0, [r7, #4]
+ 8034da4:	4798      	blx	r3
+      if((ccr_reg & BDMA_CCR_DBM) != 0U)
+ 8034da6:	e15f      	b.n	8035068 <HAL_DMA_IRQHandler+0xe08>
+        }
+      }
+    }
+
+    /* Transfer Complete Interrupt management ***********************************/
+    else if (((tmpisr_bdma & (BDMA_FLAG_TC0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_TCIE) != 0U))
+ 8034da8:	687b      	ldr	r3, [r7, #4]
+ 8034daa:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
+ 8034dac:	f003 031f 	and.w	r3, r3, #31
+ 8034db0:	2202      	movs	r2, #2
+ 8034db2:	409a      	lsls	r2, r3
+ 8034db4:	697b      	ldr	r3, [r7, #20]
+ 8034db6:	4013      	ands	r3, r2
+ 8034db8:	2b00      	cmp	r3, #0
+ 8034dba:	f000 80c5 	beq.w	8034f48 <HAL_DMA_IRQHandler+0xce8>
+ 8034dbe:	693b      	ldr	r3, [r7, #16]
+ 8034dc0:	f003 0302 	and.w	r3, r3, #2
+ 8034dc4:	2b00      	cmp	r3, #0
+ 8034dc6:	f000 80bf 	beq.w	8034f48 <HAL_DMA_IRQHandler+0xce8>
+    {
+      /* Clear the transfer complete flag */
+      regs_bdma->IFCR = (BDMA_ISR_TCIF0) << (hdma->StreamIndex & 0x1FU);
+ 8034dca:	687b      	ldr	r3, [r7, #4]
+ 8034dcc:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
+ 8034dce:	f003 031f 	and.w	r3, r3, #31
+ 8034dd2:	2202      	movs	r2, #2
+ 8034dd4:	409a      	lsls	r2, r3
+ 8034dd6:	69fb      	ldr	r3, [r7, #28]
+ 8034dd8:	605a      	str	r2, [r3, #4]
+
+      /* Disable the transfer complete interrupt if the DMA mode is Double Buffering */
+      if((ccr_reg & BDMA_CCR_DBM) != 0U)
+ 8034dda:	693b      	ldr	r3, [r7, #16]
+ 8034ddc:	f403 4300 	and.w	r3, r3, #32768	@ 0x8000
+ 8034de0:	2b00      	cmp	r3, #0
+ 8034de2:	d018      	beq.n	8034e16 <HAL_DMA_IRQHandler+0xbb6>
+      {
+        /* Current memory buffer used is Memory 0 */
+        if((ccr_reg & BDMA_CCR_CT) == 0U)
+ 8034de4:	693b      	ldr	r3, [r7, #16]
+ 8034de6:	f403 3380 	and.w	r3, r3, #65536	@ 0x10000
+ 8034dea:	2b00      	cmp	r3, #0
+ 8034dec:	d109      	bne.n	8034e02 <HAL_DMA_IRQHandler+0xba2>
+        {
+          if(hdma->XferM1CpltCallback != NULL)
+ 8034dee:	687b      	ldr	r3, [r7, #4]
+ 8034df0:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
+ 8034df2:	2b00      	cmp	r3, #0
+ 8034df4:	f000 813a 	beq.w	803506c <HAL_DMA_IRQHandler+0xe0c>
+          {
+            /* Transfer complete Callback for Memory 1 */
+            hdma->XferM1CpltCallback(hdma);
+ 8034df8:	687b      	ldr	r3, [r7, #4]
+ 8034dfa:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
+ 8034dfc:	6878      	ldr	r0, [r7, #4]
+ 8034dfe:	4798      	blx	r3
+      if((ccr_reg & BDMA_CCR_DBM) != 0U)
+ 8034e00:	e134      	b.n	803506c <HAL_DMA_IRQHandler+0xe0c>
+          }
+        }
+        /* Current memory buffer used is Memory 1 */
+        else
+        {
+          if(hdma->XferCpltCallback != NULL)
+ 8034e02:	687b      	ldr	r3, [r7, #4]
+ 8034e04:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 8034e06:	2b00      	cmp	r3, #0
+ 8034e08:	f000 8130 	beq.w	803506c <HAL_DMA_IRQHandler+0xe0c>
+          {
+            /* Transfer complete Callback for Memory 0 */
+            hdma->XferCpltCallback(hdma);
+ 8034e0c:	687b      	ldr	r3, [r7, #4]
+ 8034e0e:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 8034e10:	6878      	ldr	r0, [r7, #4]
+ 8034e12:	4798      	blx	r3
+      if((ccr_reg & BDMA_CCR_DBM) != 0U)
+ 8034e14:	e12a      	b.n	803506c <HAL_DMA_IRQHandler+0xe0c>
+          }
+        }
+      }
+      else
+      {
+        if((ccr_reg & BDMA_CCR_CIRC) == 0U)
+ 8034e16:	693b      	ldr	r3, [r7, #16]
+ 8034e18:	f003 0320 	and.w	r3, r3, #32
+ 8034e1c:	2b00      	cmp	r3, #0
+ 8034e1e:	f040 8089 	bne.w	8034f34 <HAL_DMA_IRQHandler+0xcd4>
+        {
+          /* Disable the transfer complete and error interrupt, if the DMA mode is not CIRCULAR */
+          __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
+ 8034e22:	687b      	ldr	r3, [r7, #4]
+ 8034e24:	681b      	ldr	r3, [r3, #0]
+ 8034e26:	4a2b      	ldr	r2, [pc, #172]	@ (8034ed4 <HAL_DMA_IRQHandler+0xc74>)
+ 8034e28:	4293      	cmp	r3, r2
+ 8034e2a:	d04a      	beq.n	8034ec2 <HAL_DMA_IRQHandler+0xc62>
+ 8034e2c:	687b      	ldr	r3, [r7, #4]
+ 8034e2e:	681b      	ldr	r3, [r3, #0]
+ 8034e30:	4a29      	ldr	r2, [pc, #164]	@ (8034ed8 <HAL_DMA_IRQHandler+0xc78>)
+ 8034e32:	4293      	cmp	r3, r2
+ 8034e34:	d045      	beq.n	8034ec2 <HAL_DMA_IRQHandler+0xc62>
+ 8034e36:	687b      	ldr	r3, [r7, #4]
+ 8034e38:	681b      	ldr	r3, [r3, #0]
+ 8034e3a:	4a28      	ldr	r2, [pc, #160]	@ (8034edc <HAL_DMA_IRQHandler+0xc7c>)
+ 8034e3c:	4293      	cmp	r3, r2
+ 8034e3e:	d040      	beq.n	8034ec2 <HAL_DMA_IRQHandler+0xc62>
+ 8034e40:	687b      	ldr	r3, [r7, #4]
+ 8034e42:	681b      	ldr	r3, [r3, #0]
+ 8034e44:	4a26      	ldr	r2, [pc, #152]	@ (8034ee0 <HAL_DMA_IRQHandler+0xc80>)
+ 8034e46:	4293      	cmp	r3, r2
+ 8034e48:	d03b      	beq.n	8034ec2 <HAL_DMA_IRQHandler+0xc62>
+ 8034e4a:	687b      	ldr	r3, [r7, #4]
+ 8034e4c:	681b      	ldr	r3, [r3, #0]
+ 8034e4e:	4a25      	ldr	r2, [pc, #148]	@ (8034ee4 <HAL_DMA_IRQHandler+0xc84>)
+ 8034e50:	4293      	cmp	r3, r2
+ 8034e52:	d036      	beq.n	8034ec2 <HAL_DMA_IRQHandler+0xc62>
+ 8034e54:	687b      	ldr	r3, [r7, #4]
+ 8034e56:	681b      	ldr	r3, [r3, #0]
+ 8034e58:	4a23      	ldr	r2, [pc, #140]	@ (8034ee8 <HAL_DMA_IRQHandler+0xc88>)
+ 8034e5a:	4293      	cmp	r3, r2
+ 8034e5c:	d031      	beq.n	8034ec2 <HAL_DMA_IRQHandler+0xc62>
+ 8034e5e:	687b      	ldr	r3, [r7, #4]
+ 8034e60:	681b      	ldr	r3, [r3, #0]
+ 8034e62:	4a22      	ldr	r2, [pc, #136]	@ (8034eec <HAL_DMA_IRQHandler+0xc8c>)
+ 8034e64:	4293      	cmp	r3, r2
+ 8034e66:	d02c      	beq.n	8034ec2 <HAL_DMA_IRQHandler+0xc62>
+ 8034e68:	687b      	ldr	r3, [r7, #4]
+ 8034e6a:	681b      	ldr	r3, [r3, #0]
+ 8034e6c:	4a20      	ldr	r2, [pc, #128]	@ (8034ef0 <HAL_DMA_IRQHandler+0xc90>)
+ 8034e6e:	4293      	cmp	r3, r2
+ 8034e70:	d027      	beq.n	8034ec2 <HAL_DMA_IRQHandler+0xc62>
+ 8034e72:	687b      	ldr	r3, [r7, #4]
+ 8034e74:	681b      	ldr	r3, [r3, #0]
+ 8034e76:	4a1f      	ldr	r2, [pc, #124]	@ (8034ef4 <HAL_DMA_IRQHandler+0xc94>)
+ 8034e78:	4293      	cmp	r3, r2
+ 8034e7a:	d022      	beq.n	8034ec2 <HAL_DMA_IRQHandler+0xc62>
+ 8034e7c:	687b      	ldr	r3, [r7, #4]
+ 8034e7e:	681b      	ldr	r3, [r3, #0]
+ 8034e80:	4a1d      	ldr	r2, [pc, #116]	@ (8034ef8 <HAL_DMA_IRQHandler+0xc98>)
+ 8034e82:	4293      	cmp	r3, r2
+ 8034e84:	d01d      	beq.n	8034ec2 <HAL_DMA_IRQHandler+0xc62>
+ 8034e86:	687b      	ldr	r3, [r7, #4]
+ 8034e88:	681b      	ldr	r3, [r3, #0]
+ 8034e8a:	4a1c      	ldr	r2, [pc, #112]	@ (8034efc <HAL_DMA_IRQHandler+0xc9c>)
+ 8034e8c:	4293      	cmp	r3, r2
+ 8034e8e:	d018      	beq.n	8034ec2 <HAL_DMA_IRQHandler+0xc62>
+ 8034e90:	687b      	ldr	r3, [r7, #4]
+ 8034e92:	681b      	ldr	r3, [r3, #0]
+ 8034e94:	4a1a      	ldr	r2, [pc, #104]	@ (8034f00 <HAL_DMA_IRQHandler+0xca0>)
+ 8034e96:	4293      	cmp	r3, r2
+ 8034e98:	d013      	beq.n	8034ec2 <HAL_DMA_IRQHandler+0xc62>
+ 8034e9a:	687b      	ldr	r3, [r7, #4]
+ 8034e9c:	681b      	ldr	r3, [r3, #0]
+ 8034e9e:	4a19      	ldr	r2, [pc, #100]	@ (8034f04 <HAL_DMA_IRQHandler+0xca4>)
+ 8034ea0:	4293      	cmp	r3, r2
+ 8034ea2:	d00e      	beq.n	8034ec2 <HAL_DMA_IRQHandler+0xc62>
+ 8034ea4:	687b      	ldr	r3, [r7, #4]
+ 8034ea6:	681b      	ldr	r3, [r3, #0]
+ 8034ea8:	4a17      	ldr	r2, [pc, #92]	@ (8034f08 <HAL_DMA_IRQHandler+0xca8>)
+ 8034eaa:	4293      	cmp	r3, r2
+ 8034eac:	d009      	beq.n	8034ec2 <HAL_DMA_IRQHandler+0xc62>
+ 8034eae:	687b      	ldr	r3, [r7, #4]
+ 8034eb0:	681b      	ldr	r3, [r3, #0]
+ 8034eb2:	4a16      	ldr	r2, [pc, #88]	@ (8034f0c <HAL_DMA_IRQHandler+0xcac>)
+ 8034eb4:	4293      	cmp	r3, r2
+ 8034eb6:	d004      	beq.n	8034ec2 <HAL_DMA_IRQHandler+0xc62>
+ 8034eb8:	687b      	ldr	r3, [r7, #4]
+ 8034eba:	681b      	ldr	r3, [r3, #0]
+ 8034ebc:	4a14      	ldr	r2, [pc, #80]	@ (8034f10 <HAL_DMA_IRQHandler+0xcb0>)
+ 8034ebe:	4293      	cmp	r3, r2
+ 8034ec0:	d128      	bne.n	8034f14 <HAL_DMA_IRQHandler+0xcb4>
+ 8034ec2:	687b      	ldr	r3, [r7, #4]
+ 8034ec4:	681b      	ldr	r3, [r3, #0]
+ 8034ec6:	681a      	ldr	r2, [r3, #0]
+ 8034ec8:	687b      	ldr	r3, [r7, #4]
+ 8034eca:	681b      	ldr	r3, [r3, #0]
+ 8034ecc:	f022 0214 	bic.w	r2, r2, #20
+ 8034ed0:	601a      	str	r2, [r3, #0]
+ 8034ed2:	e027      	b.n	8034f24 <HAL_DMA_IRQHandler+0xcc4>
+ 8034ed4:	40020010 	.word	0x40020010
+ 8034ed8:	40020028 	.word	0x40020028
+ 8034edc:	40020040 	.word	0x40020040
+ 8034ee0:	40020058 	.word	0x40020058
+ 8034ee4:	40020070 	.word	0x40020070
+ 8034ee8:	40020088 	.word	0x40020088
+ 8034eec:	400200a0 	.word	0x400200a0
+ 8034ef0:	400200b8 	.word	0x400200b8
+ 8034ef4:	40020410 	.word	0x40020410
+ 8034ef8:	40020428 	.word	0x40020428
+ 8034efc:	40020440 	.word	0x40020440
+ 8034f00:	40020458 	.word	0x40020458
+ 8034f04:	40020470 	.word	0x40020470
+ 8034f08:	40020488 	.word	0x40020488
+ 8034f0c:	400204a0 	.word	0x400204a0
+ 8034f10:	400204b8 	.word	0x400204b8
+ 8034f14:	687b      	ldr	r3, [r7, #4]
+ 8034f16:	681b      	ldr	r3, [r3, #0]
+ 8034f18:	681a      	ldr	r2, [r3, #0]
+ 8034f1a:	687b      	ldr	r3, [r7, #4]
+ 8034f1c:	681b      	ldr	r3, [r3, #0]
+ 8034f1e:	f022 020a 	bic.w	r2, r2, #10
+ 8034f22:	601a      	str	r2, [r3, #0]
+
+          /* Change the DMA state */
+          hdma->State = HAL_DMA_STATE_READY;
+ 8034f24:	687b      	ldr	r3, [r7, #4]
+ 8034f26:	2201      	movs	r2, #1
+ 8034f28:	f883 2035 	strb.w	r2, [r3, #53]	@ 0x35
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hdma);
+ 8034f2c:	687b      	ldr	r3, [r7, #4]
+ 8034f2e:	2200      	movs	r2, #0
+ 8034f30:	f883 2034 	strb.w	r2, [r3, #52]	@ 0x34
+        }
+
+        if(hdma->XferCpltCallback != NULL)
+ 8034f34:	687b      	ldr	r3, [r7, #4]
+ 8034f36:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 8034f38:	2b00      	cmp	r3, #0
+ 8034f3a:	f000 8097 	beq.w	803506c <HAL_DMA_IRQHandler+0xe0c>
+        {
+          /* Transfer complete callback */
+          hdma->XferCpltCallback(hdma);
+ 8034f3e:	687b      	ldr	r3, [r7, #4]
+ 8034f40:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 8034f42:	6878      	ldr	r0, [r7, #4]
+ 8034f44:	4798      	blx	r3
+      if((ccr_reg & BDMA_CCR_DBM) != 0U)
+ 8034f46:	e091      	b.n	803506c <HAL_DMA_IRQHandler+0xe0c>
+        }
+      }
+    }
+    /* Transfer Error Interrupt management **************************************/
+    else if (((tmpisr_bdma & (BDMA_FLAG_TE0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_TEIE) != 0U))
+ 8034f48:	687b      	ldr	r3, [r7, #4]
+ 8034f4a:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
+ 8034f4c:	f003 031f 	and.w	r3, r3, #31
+ 8034f50:	2208      	movs	r2, #8
+ 8034f52:	409a      	lsls	r2, r3
+ 8034f54:	697b      	ldr	r3, [r7, #20]
+ 8034f56:	4013      	ands	r3, r2
+ 8034f58:	2b00      	cmp	r3, #0
+ 8034f5a:	f000 8088 	beq.w	803506e <HAL_DMA_IRQHandler+0xe0e>
+ 8034f5e:	693b      	ldr	r3, [r7, #16]
+ 8034f60:	f003 0308 	and.w	r3, r3, #8
+ 8034f64:	2b00      	cmp	r3, #0
+ 8034f66:	f000 8082 	beq.w	803506e <HAL_DMA_IRQHandler+0xe0e>
+    {
+      /* When a DMA transfer error occurs */
+      /* A hardware clear of its EN bits is performed */
+      /* Disable ALL DMA IT */
+      __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
+ 8034f6a:	687b      	ldr	r3, [r7, #4]
+ 8034f6c:	681b      	ldr	r3, [r3, #0]
+ 8034f6e:	4a41      	ldr	r2, [pc, #260]	@ (8035074 <HAL_DMA_IRQHandler+0xe14>)
+ 8034f70:	4293      	cmp	r3, r2
+ 8034f72:	d04a      	beq.n	803500a <HAL_DMA_IRQHandler+0xdaa>
+ 8034f74:	687b      	ldr	r3, [r7, #4]
+ 8034f76:	681b      	ldr	r3, [r3, #0]
+ 8034f78:	4a3f      	ldr	r2, [pc, #252]	@ (8035078 <HAL_DMA_IRQHandler+0xe18>)
+ 8034f7a:	4293      	cmp	r3, r2
+ 8034f7c:	d045      	beq.n	803500a <HAL_DMA_IRQHandler+0xdaa>
+ 8034f7e:	687b      	ldr	r3, [r7, #4]
+ 8034f80:	681b      	ldr	r3, [r3, #0]
+ 8034f82:	4a3e      	ldr	r2, [pc, #248]	@ (803507c <HAL_DMA_IRQHandler+0xe1c>)
+ 8034f84:	4293      	cmp	r3, r2
+ 8034f86:	d040      	beq.n	803500a <HAL_DMA_IRQHandler+0xdaa>
+ 8034f88:	687b      	ldr	r3, [r7, #4]
+ 8034f8a:	681b      	ldr	r3, [r3, #0]
+ 8034f8c:	4a3c      	ldr	r2, [pc, #240]	@ (8035080 <HAL_DMA_IRQHandler+0xe20>)
+ 8034f8e:	4293      	cmp	r3, r2
+ 8034f90:	d03b      	beq.n	803500a <HAL_DMA_IRQHandler+0xdaa>
+ 8034f92:	687b      	ldr	r3, [r7, #4]
+ 8034f94:	681b      	ldr	r3, [r3, #0]
+ 8034f96:	4a3b      	ldr	r2, [pc, #236]	@ (8035084 <HAL_DMA_IRQHandler+0xe24>)
+ 8034f98:	4293      	cmp	r3, r2
+ 8034f9a:	d036      	beq.n	803500a <HAL_DMA_IRQHandler+0xdaa>
+ 8034f9c:	687b      	ldr	r3, [r7, #4]
+ 8034f9e:	681b      	ldr	r3, [r3, #0]
+ 8034fa0:	4a39      	ldr	r2, [pc, #228]	@ (8035088 <HAL_DMA_IRQHandler+0xe28>)
+ 8034fa2:	4293      	cmp	r3, r2
+ 8034fa4:	d031      	beq.n	803500a <HAL_DMA_IRQHandler+0xdaa>
+ 8034fa6:	687b      	ldr	r3, [r7, #4]
+ 8034fa8:	681b      	ldr	r3, [r3, #0]
+ 8034faa:	4a38      	ldr	r2, [pc, #224]	@ (803508c <HAL_DMA_IRQHandler+0xe2c>)
+ 8034fac:	4293      	cmp	r3, r2
+ 8034fae:	d02c      	beq.n	803500a <HAL_DMA_IRQHandler+0xdaa>
+ 8034fb0:	687b      	ldr	r3, [r7, #4]
+ 8034fb2:	681b      	ldr	r3, [r3, #0]
+ 8034fb4:	4a36      	ldr	r2, [pc, #216]	@ (8035090 <HAL_DMA_IRQHandler+0xe30>)
+ 8034fb6:	4293      	cmp	r3, r2
+ 8034fb8:	d027      	beq.n	803500a <HAL_DMA_IRQHandler+0xdaa>
+ 8034fba:	687b      	ldr	r3, [r7, #4]
+ 8034fbc:	681b      	ldr	r3, [r3, #0]
+ 8034fbe:	4a35      	ldr	r2, [pc, #212]	@ (8035094 <HAL_DMA_IRQHandler+0xe34>)
+ 8034fc0:	4293      	cmp	r3, r2
+ 8034fc2:	d022      	beq.n	803500a <HAL_DMA_IRQHandler+0xdaa>
+ 8034fc4:	687b      	ldr	r3, [r7, #4]
+ 8034fc6:	681b      	ldr	r3, [r3, #0]
+ 8034fc8:	4a33      	ldr	r2, [pc, #204]	@ (8035098 <HAL_DMA_IRQHandler+0xe38>)
+ 8034fca:	4293      	cmp	r3, r2
+ 8034fcc:	d01d      	beq.n	803500a <HAL_DMA_IRQHandler+0xdaa>
+ 8034fce:	687b      	ldr	r3, [r7, #4]
+ 8034fd0:	681b      	ldr	r3, [r3, #0]
+ 8034fd2:	4a32      	ldr	r2, [pc, #200]	@ (803509c <HAL_DMA_IRQHandler+0xe3c>)
+ 8034fd4:	4293      	cmp	r3, r2
+ 8034fd6:	d018      	beq.n	803500a <HAL_DMA_IRQHandler+0xdaa>
+ 8034fd8:	687b      	ldr	r3, [r7, #4]
+ 8034fda:	681b      	ldr	r3, [r3, #0]
+ 8034fdc:	4a30      	ldr	r2, [pc, #192]	@ (80350a0 <HAL_DMA_IRQHandler+0xe40>)
+ 8034fde:	4293      	cmp	r3, r2
+ 8034fe0:	d013      	beq.n	803500a <HAL_DMA_IRQHandler+0xdaa>
+ 8034fe2:	687b      	ldr	r3, [r7, #4]
+ 8034fe4:	681b      	ldr	r3, [r3, #0]
+ 8034fe6:	4a2f      	ldr	r2, [pc, #188]	@ (80350a4 <HAL_DMA_IRQHandler+0xe44>)
+ 8034fe8:	4293      	cmp	r3, r2
+ 8034fea:	d00e      	beq.n	803500a <HAL_DMA_IRQHandler+0xdaa>
+ 8034fec:	687b      	ldr	r3, [r7, #4]
+ 8034fee:	681b      	ldr	r3, [r3, #0]
+ 8034ff0:	4a2d      	ldr	r2, [pc, #180]	@ (80350a8 <HAL_DMA_IRQHandler+0xe48>)
+ 8034ff2:	4293      	cmp	r3, r2
+ 8034ff4:	d009      	beq.n	803500a <HAL_DMA_IRQHandler+0xdaa>
+ 8034ff6:	687b      	ldr	r3, [r7, #4]
+ 8034ff8:	681b      	ldr	r3, [r3, #0]
+ 8034ffa:	4a2c      	ldr	r2, [pc, #176]	@ (80350ac <HAL_DMA_IRQHandler+0xe4c>)
+ 8034ffc:	4293      	cmp	r3, r2
+ 8034ffe:	d004      	beq.n	803500a <HAL_DMA_IRQHandler+0xdaa>
+ 8035000:	687b      	ldr	r3, [r7, #4]
+ 8035002:	681b      	ldr	r3, [r3, #0]
+ 8035004:	4a2a      	ldr	r2, [pc, #168]	@ (80350b0 <HAL_DMA_IRQHandler+0xe50>)
+ 8035006:	4293      	cmp	r3, r2
+ 8035008:	d108      	bne.n	803501c <HAL_DMA_IRQHandler+0xdbc>
+ 803500a:	687b      	ldr	r3, [r7, #4]
+ 803500c:	681b      	ldr	r3, [r3, #0]
+ 803500e:	681a      	ldr	r2, [r3, #0]
+ 8035010:	687b      	ldr	r3, [r7, #4]
+ 8035012:	681b      	ldr	r3, [r3, #0]
+ 8035014:	f022 021c 	bic.w	r2, r2, #28
+ 8035018:	601a      	str	r2, [r3, #0]
+ 803501a:	e007      	b.n	803502c <HAL_DMA_IRQHandler+0xdcc>
+ 803501c:	687b      	ldr	r3, [r7, #4]
+ 803501e:	681b      	ldr	r3, [r3, #0]
+ 8035020:	681a      	ldr	r2, [r3, #0]
+ 8035022:	687b      	ldr	r3, [r7, #4]
+ 8035024:	681b      	ldr	r3, [r3, #0]
+ 8035026:	f022 020e 	bic.w	r2, r2, #14
+ 803502a:	601a      	str	r2, [r3, #0]
+
+      /* Clear all flags */
+      regs_bdma->IFCR = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU);
+ 803502c:	687b      	ldr	r3, [r7, #4]
+ 803502e:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
+ 8035030:	f003 031f 	and.w	r3, r3, #31
+ 8035034:	2201      	movs	r2, #1
+ 8035036:	409a      	lsls	r2, r3
+ 8035038:	69fb      	ldr	r3, [r7, #28]
+ 803503a:	605a      	str	r2, [r3, #4]
+
+      /* Update error code */
+      hdma->ErrorCode = HAL_DMA_ERROR_TE;
+ 803503c:	687b      	ldr	r3, [r7, #4]
+ 803503e:	2201      	movs	r2, #1
+ 8035040:	655a      	str	r2, [r3, #84]	@ 0x54
+
+      /* Change the DMA state */
+      hdma->State = HAL_DMA_STATE_READY;
+ 8035042:	687b      	ldr	r3, [r7, #4]
+ 8035044:	2201      	movs	r2, #1
+ 8035046:	f883 2035 	strb.w	r2, [r3, #53]	@ 0x35
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma);
+ 803504a:	687b      	ldr	r3, [r7, #4]
+ 803504c:	2200      	movs	r2, #0
+ 803504e:	f883 2034 	strb.w	r2, [r3, #52]	@ 0x34
+
+      if (hdma->XferErrorCallback != NULL)
+ 8035052:	687b      	ldr	r3, [r7, #4]
+ 8035054:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
+ 8035056:	2b00      	cmp	r3, #0
+ 8035058:	d009      	beq.n	803506e <HAL_DMA_IRQHandler+0xe0e>
+      {
+        /* Transfer error callback */
+        hdma->XferErrorCallback(hdma);
+ 803505a:	687b      	ldr	r3, [r7, #4]
+ 803505c:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
+ 803505e:	6878      	ldr	r0, [r7, #4]
+ 8035060:	4798      	blx	r3
+ 8035062:	e004      	b.n	803506e <HAL_DMA_IRQHandler+0xe0e>
+          return;
+ 8035064:	bf00      	nop
+ 8035066:	e002      	b.n	803506e <HAL_DMA_IRQHandler+0xe0e>
+      if((ccr_reg & BDMA_CCR_DBM) != 0U)
+ 8035068:	bf00      	nop
+ 803506a:	e000      	b.n	803506e <HAL_DMA_IRQHandler+0xe0e>
+      if((ccr_reg & BDMA_CCR_DBM) != 0U)
+ 803506c:	bf00      	nop
+  }
+  else
+  {
+    /* Nothing To Do */
+  }
+}
+ 803506e:	3728      	adds	r7, #40	@ 0x28
+ 8035070:	46bd      	mov	sp, r7
+ 8035072:	bd80      	pop	{r7, pc}
+ 8035074:	40020010 	.word	0x40020010
+ 8035078:	40020028 	.word	0x40020028
+ 803507c:	40020040 	.word	0x40020040
+ 8035080:	40020058 	.word	0x40020058
+ 8035084:	40020070 	.word	0x40020070
+ 8035088:	40020088 	.word	0x40020088
+ 803508c:	400200a0 	.word	0x400200a0
+ 8035090:	400200b8 	.word	0x400200b8
+ 8035094:	40020410 	.word	0x40020410
+ 8035098:	40020428 	.word	0x40020428
+ 803509c:	40020440 	.word	0x40020440
+ 80350a0:	40020458 	.word	0x40020458
+ 80350a4:	40020470 	.word	0x40020470
+ 80350a8:	40020488 	.word	0x40020488
+ 80350ac:	400204a0 	.word	0x400204a0
+ 80350b0:	400204b8 	.word	0x400204b8
+
+080350b4 <HAL_DMA_GetState>:
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Stream.
+  * @retval HAL state
+  */
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
+{
+ 80350b4:	b480      	push	{r7}
+ 80350b6:	b083      	sub	sp, #12
+ 80350b8:	af00      	add	r7, sp, #0
+ 80350ba:	6078      	str	r0, [r7, #4]
+  return hdma->State;
+ 80350bc:	687b      	ldr	r3, [r7, #4]
+ 80350be:	f893 3035 	ldrb.w	r3, [r3, #53]	@ 0x35
+ 80350c2:	b2db      	uxtb	r3, r3
+}
+ 80350c4:	4618      	mov	r0, r3
+ 80350c6:	370c      	adds	r7, #12
+ 80350c8:	46bd      	mov	sp, r7
+ 80350ca:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80350ce:	4770      	bx	lr
+
+080350d0 <DMA_SetConfig>:
+  * @param  DstAddress: The destination memory Buffer address
+  * @param  DataLength: The length of data to be transferred from source to destination
+  * @retval None
+  */
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+ 80350d0:	b480      	push	{r7}
+ 80350d2:	b087      	sub	sp, #28
+ 80350d4:	af00      	add	r7, sp, #0
+ 80350d6:	60f8      	str	r0, [r7, #12]
+ 80350d8:	60b9      	str	r1, [r7, #8]
+ 80350da:	607a      	str	r2, [r7, #4]
+ 80350dc:	603b      	str	r3, [r7, #0]
+  /* calculate DMA base and stream number */
+  DMA_Base_Registers  *regs_dma  = (DMA_Base_Registers *)hdma->StreamBaseAddress;
+ 80350de:	68fb      	ldr	r3, [r7, #12]
+ 80350e0:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
+ 80350e2:	617b      	str	r3, [r7, #20]
+  BDMA_Base_Registers *regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress;
+ 80350e4:	68fb      	ldr	r3, [r7, #12]
+ 80350e6:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
+ 80350e8:	613b      	str	r3, [r7, #16]
+
+  if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
+ 80350ea:	68fb      	ldr	r3, [r7, #12]
+ 80350ec:	681b      	ldr	r3, [r3, #0]
+ 80350ee:	4a7f      	ldr	r2, [pc, #508]	@ (80352ec <DMA_SetConfig+0x21c>)
+ 80350f0:	4293      	cmp	r3, r2
+ 80350f2:	d072      	beq.n	80351da <DMA_SetConfig+0x10a>
+ 80350f4:	68fb      	ldr	r3, [r7, #12]
+ 80350f6:	681b      	ldr	r3, [r3, #0]
+ 80350f8:	4a7d      	ldr	r2, [pc, #500]	@ (80352f0 <DMA_SetConfig+0x220>)
+ 80350fa:	4293      	cmp	r3, r2
+ 80350fc:	d06d      	beq.n	80351da <DMA_SetConfig+0x10a>
+ 80350fe:	68fb      	ldr	r3, [r7, #12]
+ 8035100:	681b      	ldr	r3, [r3, #0]
+ 8035102:	4a7c      	ldr	r2, [pc, #496]	@ (80352f4 <DMA_SetConfig+0x224>)
+ 8035104:	4293      	cmp	r3, r2
+ 8035106:	d068      	beq.n	80351da <DMA_SetConfig+0x10a>
+ 8035108:	68fb      	ldr	r3, [r7, #12]
+ 803510a:	681b      	ldr	r3, [r3, #0]
+ 803510c:	4a7a      	ldr	r2, [pc, #488]	@ (80352f8 <DMA_SetConfig+0x228>)
+ 803510e:	4293      	cmp	r3, r2
+ 8035110:	d063      	beq.n	80351da <DMA_SetConfig+0x10a>
+ 8035112:	68fb      	ldr	r3, [r7, #12]
+ 8035114:	681b      	ldr	r3, [r3, #0]
+ 8035116:	4a79      	ldr	r2, [pc, #484]	@ (80352fc <DMA_SetConfig+0x22c>)
+ 8035118:	4293      	cmp	r3, r2
+ 803511a:	d05e      	beq.n	80351da <DMA_SetConfig+0x10a>
+ 803511c:	68fb      	ldr	r3, [r7, #12]
+ 803511e:	681b      	ldr	r3, [r3, #0]
+ 8035120:	4a77      	ldr	r2, [pc, #476]	@ (8035300 <DMA_SetConfig+0x230>)
+ 8035122:	4293      	cmp	r3, r2
+ 8035124:	d059      	beq.n	80351da <DMA_SetConfig+0x10a>
+ 8035126:	68fb      	ldr	r3, [r7, #12]
+ 8035128:	681b      	ldr	r3, [r3, #0]
+ 803512a:	4a76      	ldr	r2, [pc, #472]	@ (8035304 <DMA_SetConfig+0x234>)
+ 803512c:	4293      	cmp	r3, r2
+ 803512e:	d054      	beq.n	80351da <DMA_SetConfig+0x10a>
+ 8035130:	68fb      	ldr	r3, [r7, #12]
+ 8035132:	681b      	ldr	r3, [r3, #0]
+ 8035134:	4a74      	ldr	r2, [pc, #464]	@ (8035308 <DMA_SetConfig+0x238>)
+ 8035136:	4293      	cmp	r3, r2
+ 8035138:	d04f      	beq.n	80351da <DMA_SetConfig+0x10a>
+ 803513a:	68fb      	ldr	r3, [r7, #12]
+ 803513c:	681b      	ldr	r3, [r3, #0]
+ 803513e:	4a73      	ldr	r2, [pc, #460]	@ (803530c <DMA_SetConfig+0x23c>)
+ 8035140:	4293      	cmp	r3, r2
+ 8035142:	d04a      	beq.n	80351da <DMA_SetConfig+0x10a>
+ 8035144:	68fb      	ldr	r3, [r7, #12]
+ 8035146:	681b      	ldr	r3, [r3, #0]
+ 8035148:	4a71      	ldr	r2, [pc, #452]	@ (8035310 <DMA_SetConfig+0x240>)
+ 803514a:	4293      	cmp	r3, r2
+ 803514c:	d045      	beq.n	80351da <DMA_SetConfig+0x10a>
+ 803514e:	68fb      	ldr	r3, [r7, #12]
+ 8035150:	681b      	ldr	r3, [r3, #0]
+ 8035152:	4a70      	ldr	r2, [pc, #448]	@ (8035314 <DMA_SetConfig+0x244>)
+ 8035154:	4293      	cmp	r3, r2
+ 8035156:	d040      	beq.n	80351da <DMA_SetConfig+0x10a>
+ 8035158:	68fb      	ldr	r3, [r7, #12]
+ 803515a:	681b      	ldr	r3, [r3, #0]
+ 803515c:	4a6e      	ldr	r2, [pc, #440]	@ (8035318 <DMA_SetConfig+0x248>)
+ 803515e:	4293      	cmp	r3, r2
+ 8035160:	d03b      	beq.n	80351da <DMA_SetConfig+0x10a>
+ 8035162:	68fb      	ldr	r3, [r7, #12]
+ 8035164:	681b      	ldr	r3, [r3, #0]
+ 8035166:	4a6d      	ldr	r2, [pc, #436]	@ (803531c <DMA_SetConfig+0x24c>)
+ 8035168:	4293      	cmp	r3, r2
+ 803516a:	d036      	beq.n	80351da <DMA_SetConfig+0x10a>
+ 803516c:	68fb      	ldr	r3, [r7, #12]
+ 803516e:	681b      	ldr	r3, [r3, #0]
+ 8035170:	4a6b      	ldr	r2, [pc, #428]	@ (8035320 <DMA_SetConfig+0x250>)
+ 8035172:	4293      	cmp	r3, r2
+ 8035174:	d031      	beq.n	80351da <DMA_SetConfig+0x10a>
+ 8035176:	68fb      	ldr	r3, [r7, #12]
+ 8035178:	681b      	ldr	r3, [r3, #0]
+ 803517a:	4a6a      	ldr	r2, [pc, #424]	@ (8035324 <DMA_SetConfig+0x254>)
+ 803517c:	4293      	cmp	r3, r2
+ 803517e:	d02c      	beq.n	80351da <DMA_SetConfig+0x10a>
+ 8035180:	68fb      	ldr	r3, [r7, #12]
+ 8035182:	681b      	ldr	r3, [r3, #0]
+ 8035184:	4a68      	ldr	r2, [pc, #416]	@ (8035328 <DMA_SetConfig+0x258>)
+ 8035186:	4293      	cmp	r3, r2
+ 8035188:	d027      	beq.n	80351da <DMA_SetConfig+0x10a>
+ 803518a:	68fb      	ldr	r3, [r7, #12]
+ 803518c:	681b      	ldr	r3, [r3, #0]
+ 803518e:	4a67      	ldr	r2, [pc, #412]	@ (803532c <DMA_SetConfig+0x25c>)
+ 8035190:	4293      	cmp	r3, r2
+ 8035192:	d022      	beq.n	80351da <DMA_SetConfig+0x10a>
+ 8035194:	68fb      	ldr	r3, [r7, #12]
+ 8035196:	681b      	ldr	r3, [r3, #0]
+ 8035198:	4a65      	ldr	r2, [pc, #404]	@ (8035330 <DMA_SetConfig+0x260>)
+ 803519a:	4293      	cmp	r3, r2
+ 803519c:	d01d      	beq.n	80351da <DMA_SetConfig+0x10a>
+ 803519e:	68fb      	ldr	r3, [r7, #12]
+ 80351a0:	681b      	ldr	r3, [r3, #0]
+ 80351a2:	4a64      	ldr	r2, [pc, #400]	@ (8035334 <DMA_SetConfig+0x264>)
+ 80351a4:	4293      	cmp	r3, r2
+ 80351a6:	d018      	beq.n	80351da <DMA_SetConfig+0x10a>
+ 80351a8:	68fb      	ldr	r3, [r7, #12]
+ 80351aa:	681b      	ldr	r3, [r3, #0]
+ 80351ac:	4a62      	ldr	r2, [pc, #392]	@ (8035338 <DMA_SetConfig+0x268>)
+ 80351ae:	4293      	cmp	r3, r2
+ 80351b0:	d013      	beq.n	80351da <DMA_SetConfig+0x10a>
+ 80351b2:	68fb      	ldr	r3, [r7, #12]
+ 80351b4:	681b      	ldr	r3, [r3, #0]
+ 80351b6:	4a61      	ldr	r2, [pc, #388]	@ (803533c <DMA_SetConfig+0x26c>)
+ 80351b8:	4293      	cmp	r3, r2
+ 80351ba:	d00e      	beq.n	80351da <DMA_SetConfig+0x10a>
+ 80351bc:	68fb      	ldr	r3, [r7, #12]
+ 80351be:	681b      	ldr	r3, [r3, #0]
+ 80351c0:	4a5f      	ldr	r2, [pc, #380]	@ (8035340 <DMA_SetConfig+0x270>)
+ 80351c2:	4293      	cmp	r3, r2
+ 80351c4:	d009      	beq.n	80351da <DMA_SetConfig+0x10a>
+ 80351c6:	68fb      	ldr	r3, [r7, #12]
+ 80351c8:	681b      	ldr	r3, [r3, #0]
+ 80351ca:	4a5e      	ldr	r2, [pc, #376]	@ (8035344 <DMA_SetConfig+0x274>)
+ 80351cc:	4293      	cmp	r3, r2
+ 80351ce:	d004      	beq.n	80351da <DMA_SetConfig+0x10a>
+ 80351d0:	68fb      	ldr	r3, [r7, #12]
+ 80351d2:	681b      	ldr	r3, [r3, #0]
+ 80351d4:	4a5c      	ldr	r2, [pc, #368]	@ (8035348 <DMA_SetConfig+0x278>)
+ 80351d6:	4293      	cmp	r3, r2
+ 80351d8:	d101      	bne.n	80351de <DMA_SetConfig+0x10e>
+ 80351da:	2301      	movs	r3, #1
+ 80351dc:	e000      	b.n	80351e0 <DMA_SetConfig+0x110>
+ 80351de:	2300      	movs	r3, #0
+ 80351e0:	2b00      	cmp	r3, #0
+ 80351e2:	d00d      	beq.n	8035200 <DMA_SetConfig+0x130>
+  {
+    /* Clear the DMAMUX synchro overrun flag */
+    hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+ 80351e4:	68fb      	ldr	r3, [r7, #12]
+ 80351e6:	6e5b      	ldr	r3, [r3, #100]	@ 0x64
+ 80351e8:	68fa      	ldr	r2, [r7, #12]
+ 80351ea:	6e92      	ldr	r2, [r2, #104]	@ 0x68
+ 80351ec:	605a      	str	r2, [r3, #4]
+
+    if(hdma->DMAmuxRequestGen != 0U)
+ 80351ee:	68fb      	ldr	r3, [r7, #12]
+ 80351f0:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
+ 80351f2:	2b00      	cmp	r3, #0
+ 80351f4:	d004      	beq.n	8035200 <DMA_SetConfig+0x130>
+    {
+      /* Clear the DMAMUX request generator overrun flag */
+      hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+ 80351f6:	68fb      	ldr	r3, [r7, #12]
+ 80351f8:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
+ 80351fa:	68fa      	ldr	r2, [r7, #12]
+ 80351fc:	6f52      	ldr	r2, [r2, #116]	@ 0x74
+ 80351fe:	605a      	str	r2, [r3, #4]
+    }
+  }
+
+  if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+ 8035200:	68fb      	ldr	r3, [r7, #12]
+ 8035202:	681b      	ldr	r3, [r3, #0]
+ 8035204:	4a39      	ldr	r2, [pc, #228]	@ (80352ec <DMA_SetConfig+0x21c>)
+ 8035206:	4293      	cmp	r3, r2
+ 8035208:	d04a      	beq.n	80352a0 <DMA_SetConfig+0x1d0>
+ 803520a:	68fb      	ldr	r3, [r7, #12]
+ 803520c:	681b      	ldr	r3, [r3, #0]
+ 803520e:	4a38      	ldr	r2, [pc, #224]	@ (80352f0 <DMA_SetConfig+0x220>)
+ 8035210:	4293      	cmp	r3, r2
+ 8035212:	d045      	beq.n	80352a0 <DMA_SetConfig+0x1d0>
+ 8035214:	68fb      	ldr	r3, [r7, #12]
+ 8035216:	681b      	ldr	r3, [r3, #0]
+ 8035218:	4a36      	ldr	r2, [pc, #216]	@ (80352f4 <DMA_SetConfig+0x224>)
+ 803521a:	4293      	cmp	r3, r2
+ 803521c:	d040      	beq.n	80352a0 <DMA_SetConfig+0x1d0>
+ 803521e:	68fb      	ldr	r3, [r7, #12]
+ 8035220:	681b      	ldr	r3, [r3, #0]
+ 8035222:	4a35      	ldr	r2, [pc, #212]	@ (80352f8 <DMA_SetConfig+0x228>)
+ 8035224:	4293      	cmp	r3, r2
+ 8035226:	d03b      	beq.n	80352a0 <DMA_SetConfig+0x1d0>
+ 8035228:	68fb      	ldr	r3, [r7, #12]
+ 803522a:	681b      	ldr	r3, [r3, #0]
+ 803522c:	4a33      	ldr	r2, [pc, #204]	@ (80352fc <DMA_SetConfig+0x22c>)
+ 803522e:	4293      	cmp	r3, r2
+ 8035230:	d036      	beq.n	80352a0 <DMA_SetConfig+0x1d0>
+ 8035232:	68fb      	ldr	r3, [r7, #12]
+ 8035234:	681b      	ldr	r3, [r3, #0]
+ 8035236:	4a32      	ldr	r2, [pc, #200]	@ (8035300 <DMA_SetConfig+0x230>)
+ 8035238:	4293      	cmp	r3, r2
+ 803523a:	d031      	beq.n	80352a0 <DMA_SetConfig+0x1d0>
+ 803523c:	68fb      	ldr	r3, [r7, #12]
+ 803523e:	681b      	ldr	r3, [r3, #0]
+ 8035240:	4a30      	ldr	r2, [pc, #192]	@ (8035304 <DMA_SetConfig+0x234>)
+ 8035242:	4293      	cmp	r3, r2
+ 8035244:	d02c      	beq.n	80352a0 <DMA_SetConfig+0x1d0>
+ 8035246:	68fb      	ldr	r3, [r7, #12]
+ 8035248:	681b      	ldr	r3, [r3, #0]
+ 803524a:	4a2f      	ldr	r2, [pc, #188]	@ (8035308 <DMA_SetConfig+0x238>)
+ 803524c:	4293      	cmp	r3, r2
+ 803524e:	d027      	beq.n	80352a0 <DMA_SetConfig+0x1d0>
+ 8035250:	68fb      	ldr	r3, [r7, #12]
+ 8035252:	681b      	ldr	r3, [r3, #0]
+ 8035254:	4a2d      	ldr	r2, [pc, #180]	@ (803530c <DMA_SetConfig+0x23c>)
+ 8035256:	4293      	cmp	r3, r2
+ 8035258:	d022      	beq.n	80352a0 <DMA_SetConfig+0x1d0>
+ 803525a:	68fb      	ldr	r3, [r7, #12]
+ 803525c:	681b      	ldr	r3, [r3, #0]
+ 803525e:	4a2c      	ldr	r2, [pc, #176]	@ (8035310 <DMA_SetConfig+0x240>)
+ 8035260:	4293      	cmp	r3, r2
+ 8035262:	d01d      	beq.n	80352a0 <DMA_SetConfig+0x1d0>
+ 8035264:	68fb      	ldr	r3, [r7, #12]
+ 8035266:	681b      	ldr	r3, [r3, #0]
+ 8035268:	4a2a      	ldr	r2, [pc, #168]	@ (8035314 <DMA_SetConfig+0x244>)
+ 803526a:	4293      	cmp	r3, r2
+ 803526c:	d018      	beq.n	80352a0 <DMA_SetConfig+0x1d0>
+ 803526e:	68fb      	ldr	r3, [r7, #12]
+ 8035270:	681b      	ldr	r3, [r3, #0]
+ 8035272:	4a29      	ldr	r2, [pc, #164]	@ (8035318 <DMA_SetConfig+0x248>)
+ 8035274:	4293      	cmp	r3, r2
+ 8035276:	d013      	beq.n	80352a0 <DMA_SetConfig+0x1d0>
+ 8035278:	68fb      	ldr	r3, [r7, #12]
+ 803527a:	681b      	ldr	r3, [r3, #0]
+ 803527c:	4a27      	ldr	r2, [pc, #156]	@ (803531c <DMA_SetConfig+0x24c>)
+ 803527e:	4293      	cmp	r3, r2
+ 8035280:	d00e      	beq.n	80352a0 <DMA_SetConfig+0x1d0>
+ 8035282:	68fb      	ldr	r3, [r7, #12]
+ 8035284:	681b      	ldr	r3, [r3, #0]
+ 8035286:	4a26      	ldr	r2, [pc, #152]	@ (8035320 <DMA_SetConfig+0x250>)
+ 8035288:	4293      	cmp	r3, r2
+ 803528a:	d009      	beq.n	80352a0 <DMA_SetConfig+0x1d0>
+ 803528c:	68fb      	ldr	r3, [r7, #12]
+ 803528e:	681b      	ldr	r3, [r3, #0]
+ 8035290:	4a24      	ldr	r2, [pc, #144]	@ (8035324 <DMA_SetConfig+0x254>)
+ 8035292:	4293      	cmp	r3, r2
+ 8035294:	d004      	beq.n	80352a0 <DMA_SetConfig+0x1d0>
+ 8035296:	68fb      	ldr	r3, [r7, #12]
+ 8035298:	681b      	ldr	r3, [r3, #0]
+ 803529a:	4a23      	ldr	r2, [pc, #140]	@ (8035328 <DMA_SetConfig+0x258>)
+ 803529c:	4293      	cmp	r3, r2
+ 803529e:	d101      	bne.n	80352a4 <DMA_SetConfig+0x1d4>
+ 80352a0:	2301      	movs	r3, #1
+ 80352a2:	e000      	b.n	80352a6 <DMA_SetConfig+0x1d6>
+ 80352a4:	2300      	movs	r3, #0
+ 80352a6:	2b00      	cmp	r3, #0
+ 80352a8:	d059      	beq.n	803535e <DMA_SetConfig+0x28e>
+  {
+    /* Clear all interrupt flags at correct offset within the register */
+    regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);
+ 80352aa:	68fb      	ldr	r3, [r7, #12]
+ 80352ac:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
+ 80352ae:	f003 031f 	and.w	r3, r3, #31
+ 80352b2:	223f      	movs	r2, #63	@ 0x3f
+ 80352b4:	409a      	lsls	r2, r3
+ 80352b6:	697b      	ldr	r3, [r7, #20]
+ 80352b8:	609a      	str	r2, [r3, #8]
+
+    /* Clear DBM bit */
+    ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= (uint32_t)(~DMA_SxCR_DBM);
+ 80352ba:	68fb      	ldr	r3, [r7, #12]
+ 80352bc:	681b      	ldr	r3, [r3, #0]
+ 80352be:	681a      	ldr	r2, [r3, #0]
+ 80352c0:	68fb      	ldr	r3, [r7, #12]
+ 80352c2:	681b      	ldr	r3, [r3, #0]
+ 80352c4:	f422 2280 	bic.w	r2, r2, #262144	@ 0x40000
+ 80352c8:	601a      	str	r2, [r3, #0]
+
+    /* Configure DMA Stream data length */
+    ((DMA_Stream_TypeDef *)hdma->Instance)->NDTR = DataLength;
+ 80352ca:	68fb      	ldr	r3, [r7, #12]
+ 80352cc:	681b      	ldr	r3, [r3, #0]
+ 80352ce:	683a      	ldr	r2, [r7, #0]
+ 80352d0:	605a      	str	r2, [r3, #4]
+
+    /* Peripheral to Memory */
+    if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
+ 80352d2:	68fb      	ldr	r3, [r7, #12]
+ 80352d4:	689b      	ldr	r3, [r3, #8]
+ 80352d6:	2b40      	cmp	r3, #64	@ 0x40
+ 80352d8:	d138      	bne.n	803534c <DMA_SetConfig+0x27c>
+    {
+      /* Configure DMA Stream destination address */
+      ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = DstAddress;
+ 80352da:	68fb      	ldr	r3, [r7, #12]
+ 80352dc:	681b      	ldr	r3, [r3, #0]
+ 80352de:	687a      	ldr	r2, [r7, #4]
+ 80352e0:	609a      	str	r2, [r3, #8]
+
+      /* Configure DMA Stream source address */
+      ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = SrcAddress;
+ 80352e2:	68fb      	ldr	r3, [r7, #12]
+ 80352e4:	681b      	ldr	r3, [r3, #0]
+ 80352e6:	68ba      	ldr	r2, [r7, #8]
+ 80352e8:	60da      	str	r2, [r3, #12]
+  }
+  else
+  {
+    /* Nothing To Do */
+  }
+}
+ 80352ea:	e086      	b.n	80353fa <DMA_SetConfig+0x32a>
+ 80352ec:	40020010 	.word	0x40020010
+ 80352f0:	40020028 	.word	0x40020028
+ 80352f4:	40020040 	.word	0x40020040
+ 80352f8:	40020058 	.word	0x40020058
+ 80352fc:	40020070 	.word	0x40020070
+ 8035300:	40020088 	.word	0x40020088
+ 8035304:	400200a0 	.word	0x400200a0
+ 8035308:	400200b8 	.word	0x400200b8
+ 803530c:	40020410 	.word	0x40020410
+ 8035310:	40020428 	.word	0x40020428
+ 8035314:	40020440 	.word	0x40020440
+ 8035318:	40020458 	.word	0x40020458
+ 803531c:	40020470 	.word	0x40020470
+ 8035320:	40020488 	.word	0x40020488
+ 8035324:	400204a0 	.word	0x400204a0
+ 8035328:	400204b8 	.word	0x400204b8
+ 803532c:	58025408 	.word	0x58025408
+ 8035330:	5802541c 	.word	0x5802541c
+ 8035334:	58025430 	.word	0x58025430
+ 8035338:	58025444 	.word	0x58025444
+ 803533c:	58025458 	.word	0x58025458
+ 8035340:	5802546c 	.word	0x5802546c
+ 8035344:	58025480 	.word	0x58025480
+ 8035348:	58025494 	.word	0x58025494
+      ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = SrcAddress;
+ 803534c:	68fb      	ldr	r3, [r7, #12]
+ 803534e:	681b      	ldr	r3, [r3, #0]
+ 8035350:	68ba      	ldr	r2, [r7, #8]
+ 8035352:	609a      	str	r2, [r3, #8]
+      ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = DstAddress;
+ 8035354:	68fb      	ldr	r3, [r7, #12]
+ 8035356:	681b      	ldr	r3, [r3, #0]
+ 8035358:	687a      	ldr	r2, [r7, #4]
+ 803535a:	60da      	str	r2, [r3, #12]
+}
+ 803535c:	e04d      	b.n	80353fa <DMA_SetConfig+0x32a>
+  else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */
+ 803535e:	68fb      	ldr	r3, [r7, #12]
+ 8035360:	681b      	ldr	r3, [r3, #0]
+ 8035362:	4a29      	ldr	r2, [pc, #164]	@ (8035408 <DMA_SetConfig+0x338>)
+ 8035364:	4293      	cmp	r3, r2
+ 8035366:	d022      	beq.n	80353ae <DMA_SetConfig+0x2de>
+ 8035368:	68fb      	ldr	r3, [r7, #12]
+ 803536a:	681b      	ldr	r3, [r3, #0]
+ 803536c:	4a27      	ldr	r2, [pc, #156]	@ (803540c <DMA_SetConfig+0x33c>)
+ 803536e:	4293      	cmp	r3, r2
+ 8035370:	d01d      	beq.n	80353ae <DMA_SetConfig+0x2de>
+ 8035372:	68fb      	ldr	r3, [r7, #12]
+ 8035374:	681b      	ldr	r3, [r3, #0]
+ 8035376:	4a26      	ldr	r2, [pc, #152]	@ (8035410 <DMA_SetConfig+0x340>)
+ 8035378:	4293      	cmp	r3, r2
+ 803537a:	d018      	beq.n	80353ae <DMA_SetConfig+0x2de>
+ 803537c:	68fb      	ldr	r3, [r7, #12]
+ 803537e:	681b      	ldr	r3, [r3, #0]
+ 8035380:	4a24      	ldr	r2, [pc, #144]	@ (8035414 <DMA_SetConfig+0x344>)
+ 8035382:	4293      	cmp	r3, r2
+ 8035384:	d013      	beq.n	80353ae <DMA_SetConfig+0x2de>
+ 8035386:	68fb      	ldr	r3, [r7, #12]
+ 8035388:	681b      	ldr	r3, [r3, #0]
+ 803538a:	4a23      	ldr	r2, [pc, #140]	@ (8035418 <DMA_SetConfig+0x348>)
+ 803538c:	4293      	cmp	r3, r2
+ 803538e:	d00e      	beq.n	80353ae <DMA_SetConfig+0x2de>
+ 8035390:	68fb      	ldr	r3, [r7, #12]
+ 8035392:	681b      	ldr	r3, [r3, #0]
+ 8035394:	4a21      	ldr	r2, [pc, #132]	@ (803541c <DMA_SetConfig+0x34c>)
+ 8035396:	4293      	cmp	r3, r2
+ 8035398:	d009      	beq.n	80353ae <DMA_SetConfig+0x2de>
+ 803539a:	68fb      	ldr	r3, [r7, #12]
+ 803539c:	681b      	ldr	r3, [r3, #0]
+ 803539e:	4a20      	ldr	r2, [pc, #128]	@ (8035420 <DMA_SetConfig+0x350>)
+ 80353a0:	4293      	cmp	r3, r2
+ 80353a2:	d004      	beq.n	80353ae <DMA_SetConfig+0x2de>
+ 80353a4:	68fb      	ldr	r3, [r7, #12]
+ 80353a6:	681b      	ldr	r3, [r3, #0]
+ 80353a8:	4a1e      	ldr	r2, [pc, #120]	@ (8035424 <DMA_SetConfig+0x354>)
+ 80353aa:	4293      	cmp	r3, r2
+ 80353ac:	d101      	bne.n	80353b2 <DMA_SetConfig+0x2e2>
+ 80353ae:	2301      	movs	r3, #1
+ 80353b0:	e000      	b.n	80353b4 <DMA_SetConfig+0x2e4>
+ 80353b2:	2300      	movs	r3, #0
+ 80353b4:	2b00      	cmp	r3, #0
+ 80353b6:	d020      	beq.n	80353fa <DMA_SetConfig+0x32a>
+    regs_bdma->IFCR = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU);
+ 80353b8:	68fb      	ldr	r3, [r7, #12]
+ 80353ba:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
+ 80353bc:	f003 031f 	and.w	r3, r3, #31
+ 80353c0:	2201      	movs	r2, #1
+ 80353c2:	409a      	lsls	r2, r3
+ 80353c4:	693b      	ldr	r3, [r7, #16]
+ 80353c6:	605a      	str	r2, [r3, #4]
+    ((BDMA_Channel_TypeDef *)hdma->Instance)->CNDTR = DataLength;
+ 80353c8:	68fb      	ldr	r3, [r7, #12]
+ 80353ca:	681b      	ldr	r3, [r3, #0]
+ 80353cc:	683a      	ldr	r2, [r7, #0]
+ 80353ce:	605a      	str	r2, [r3, #4]
+    if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
+ 80353d0:	68fb      	ldr	r3, [r7, #12]
+ 80353d2:	689b      	ldr	r3, [r3, #8]
+ 80353d4:	2b40      	cmp	r3, #64	@ 0x40
+ 80353d6:	d108      	bne.n	80353ea <DMA_SetConfig+0x31a>
+      ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = DstAddress;
+ 80353d8:	68fb      	ldr	r3, [r7, #12]
+ 80353da:	681b      	ldr	r3, [r3, #0]
+ 80353dc:	687a      	ldr	r2, [r7, #4]
+ 80353de:	609a      	str	r2, [r3, #8]
+      ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = SrcAddress;
+ 80353e0:	68fb      	ldr	r3, [r7, #12]
+ 80353e2:	681b      	ldr	r3, [r3, #0]
+ 80353e4:	68ba      	ldr	r2, [r7, #8]
+ 80353e6:	60da      	str	r2, [r3, #12]
+}
+ 80353e8:	e007      	b.n	80353fa <DMA_SetConfig+0x32a>
+      ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = SrcAddress;
+ 80353ea:	68fb      	ldr	r3, [r7, #12]
+ 80353ec:	681b      	ldr	r3, [r3, #0]
+ 80353ee:	68ba      	ldr	r2, [r7, #8]
+ 80353f0:	609a      	str	r2, [r3, #8]
+      ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = DstAddress;
+ 80353f2:	68fb      	ldr	r3, [r7, #12]
+ 80353f4:	681b      	ldr	r3, [r3, #0]
+ 80353f6:	687a      	ldr	r2, [r7, #4]
+ 80353f8:	60da      	str	r2, [r3, #12]
+}
+ 80353fa:	bf00      	nop
+ 80353fc:	371c      	adds	r7, #28
+ 80353fe:	46bd      	mov	sp, r7
+ 8035400:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8035404:	4770      	bx	lr
+ 8035406:	bf00      	nop
+ 8035408:	58025408 	.word	0x58025408
+ 803540c:	5802541c 	.word	0x5802541c
+ 8035410:	58025430 	.word	0x58025430
+ 8035414:	58025444 	.word	0x58025444
+ 8035418:	58025458 	.word	0x58025458
+ 803541c:	5802546c 	.word	0x5802546c
+ 8035420:	58025480 	.word	0x58025480
+ 8035424:	58025494 	.word	0x58025494
+
+08035428 <DMA_CalcBaseAndBitshift>:
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @retval Stream base address
+  */
+static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
+{
+ 8035428:	b480      	push	{r7}
+ 803542a:	b085      	sub	sp, #20
+ 803542c:	af00      	add	r7, sp, #0
+ 803542e:	6078      	str	r0, [r7, #4]
+  if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
+ 8035430:	687b      	ldr	r3, [r7, #4]
+ 8035432:	681b      	ldr	r3, [r3, #0]
+ 8035434:	4a42      	ldr	r2, [pc, #264]	@ (8035540 <DMA_CalcBaseAndBitshift+0x118>)
+ 8035436:	4293      	cmp	r3, r2
+ 8035438:	d04a      	beq.n	80354d0 <DMA_CalcBaseAndBitshift+0xa8>
+ 803543a:	687b      	ldr	r3, [r7, #4]
+ 803543c:	681b      	ldr	r3, [r3, #0]
+ 803543e:	4a41      	ldr	r2, [pc, #260]	@ (8035544 <DMA_CalcBaseAndBitshift+0x11c>)
+ 8035440:	4293      	cmp	r3, r2
+ 8035442:	d045      	beq.n	80354d0 <DMA_CalcBaseAndBitshift+0xa8>
+ 8035444:	687b      	ldr	r3, [r7, #4]
+ 8035446:	681b      	ldr	r3, [r3, #0]
+ 8035448:	4a3f      	ldr	r2, [pc, #252]	@ (8035548 <DMA_CalcBaseAndBitshift+0x120>)
+ 803544a:	4293      	cmp	r3, r2
+ 803544c:	d040      	beq.n	80354d0 <DMA_CalcBaseAndBitshift+0xa8>
+ 803544e:	687b      	ldr	r3, [r7, #4]
+ 8035450:	681b      	ldr	r3, [r3, #0]
+ 8035452:	4a3e      	ldr	r2, [pc, #248]	@ (803554c <DMA_CalcBaseAndBitshift+0x124>)
+ 8035454:	4293      	cmp	r3, r2
+ 8035456:	d03b      	beq.n	80354d0 <DMA_CalcBaseAndBitshift+0xa8>
+ 8035458:	687b      	ldr	r3, [r7, #4]
+ 803545a:	681b      	ldr	r3, [r3, #0]
+ 803545c:	4a3c      	ldr	r2, [pc, #240]	@ (8035550 <DMA_CalcBaseAndBitshift+0x128>)
+ 803545e:	4293      	cmp	r3, r2
+ 8035460:	d036      	beq.n	80354d0 <DMA_CalcBaseAndBitshift+0xa8>
+ 8035462:	687b      	ldr	r3, [r7, #4]
+ 8035464:	681b      	ldr	r3, [r3, #0]
+ 8035466:	4a3b      	ldr	r2, [pc, #236]	@ (8035554 <DMA_CalcBaseAndBitshift+0x12c>)
+ 8035468:	4293      	cmp	r3, r2
+ 803546a:	d031      	beq.n	80354d0 <DMA_CalcBaseAndBitshift+0xa8>
+ 803546c:	687b      	ldr	r3, [r7, #4]
+ 803546e:	681b      	ldr	r3, [r3, #0]
+ 8035470:	4a39      	ldr	r2, [pc, #228]	@ (8035558 <DMA_CalcBaseAndBitshift+0x130>)
+ 8035472:	4293      	cmp	r3, r2
+ 8035474:	d02c      	beq.n	80354d0 <DMA_CalcBaseAndBitshift+0xa8>
+ 8035476:	687b      	ldr	r3, [r7, #4]
+ 8035478:	681b      	ldr	r3, [r3, #0]
+ 803547a:	4a38      	ldr	r2, [pc, #224]	@ (803555c <DMA_CalcBaseAndBitshift+0x134>)
+ 803547c:	4293      	cmp	r3, r2
+ 803547e:	d027      	beq.n	80354d0 <DMA_CalcBaseAndBitshift+0xa8>
+ 8035480:	687b      	ldr	r3, [r7, #4]
+ 8035482:	681b      	ldr	r3, [r3, #0]
+ 8035484:	4a36      	ldr	r2, [pc, #216]	@ (8035560 <DMA_CalcBaseAndBitshift+0x138>)
+ 8035486:	4293      	cmp	r3, r2
+ 8035488:	d022      	beq.n	80354d0 <DMA_CalcBaseAndBitshift+0xa8>
+ 803548a:	687b      	ldr	r3, [r7, #4]
+ 803548c:	681b      	ldr	r3, [r3, #0]
+ 803548e:	4a35      	ldr	r2, [pc, #212]	@ (8035564 <DMA_CalcBaseAndBitshift+0x13c>)
+ 8035490:	4293      	cmp	r3, r2
+ 8035492:	d01d      	beq.n	80354d0 <DMA_CalcBaseAndBitshift+0xa8>
+ 8035494:	687b      	ldr	r3, [r7, #4]
+ 8035496:	681b      	ldr	r3, [r3, #0]
+ 8035498:	4a33      	ldr	r2, [pc, #204]	@ (8035568 <DMA_CalcBaseAndBitshift+0x140>)
+ 803549a:	4293      	cmp	r3, r2
+ 803549c:	d018      	beq.n	80354d0 <DMA_CalcBaseAndBitshift+0xa8>
+ 803549e:	687b      	ldr	r3, [r7, #4]
+ 80354a0:	681b      	ldr	r3, [r3, #0]
+ 80354a2:	4a32      	ldr	r2, [pc, #200]	@ (803556c <DMA_CalcBaseAndBitshift+0x144>)
+ 80354a4:	4293      	cmp	r3, r2
+ 80354a6:	d013      	beq.n	80354d0 <DMA_CalcBaseAndBitshift+0xa8>
+ 80354a8:	687b      	ldr	r3, [r7, #4]
+ 80354aa:	681b      	ldr	r3, [r3, #0]
+ 80354ac:	4a30      	ldr	r2, [pc, #192]	@ (8035570 <DMA_CalcBaseAndBitshift+0x148>)
+ 80354ae:	4293      	cmp	r3, r2
+ 80354b0:	d00e      	beq.n	80354d0 <DMA_CalcBaseAndBitshift+0xa8>
+ 80354b2:	687b      	ldr	r3, [r7, #4]
+ 80354b4:	681b      	ldr	r3, [r3, #0]
+ 80354b6:	4a2f      	ldr	r2, [pc, #188]	@ (8035574 <DMA_CalcBaseAndBitshift+0x14c>)
+ 80354b8:	4293      	cmp	r3, r2
+ 80354ba:	d009      	beq.n	80354d0 <DMA_CalcBaseAndBitshift+0xa8>
+ 80354bc:	687b      	ldr	r3, [r7, #4]
+ 80354be:	681b      	ldr	r3, [r3, #0]
+ 80354c0:	4a2d      	ldr	r2, [pc, #180]	@ (8035578 <DMA_CalcBaseAndBitshift+0x150>)
+ 80354c2:	4293      	cmp	r3, r2
+ 80354c4:	d004      	beq.n	80354d0 <DMA_CalcBaseAndBitshift+0xa8>
+ 80354c6:	687b      	ldr	r3, [r7, #4]
+ 80354c8:	681b      	ldr	r3, [r3, #0]
+ 80354ca:	4a2c      	ldr	r2, [pc, #176]	@ (803557c <DMA_CalcBaseAndBitshift+0x154>)
+ 80354cc:	4293      	cmp	r3, r2
+ 80354ce:	d101      	bne.n	80354d4 <DMA_CalcBaseAndBitshift+0xac>
+ 80354d0:	2301      	movs	r3, #1
+ 80354d2:	e000      	b.n	80354d6 <DMA_CalcBaseAndBitshift+0xae>
+ 80354d4:	2300      	movs	r3, #0
+ 80354d6:	2b00      	cmp	r3, #0
+ 80354d8:	d024      	beq.n	8035524 <DMA_CalcBaseAndBitshift+0xfc>
+  {
+    uint32_t stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U;
+ 80354da:	687b      	ldr	r3, [r7, #4]
+ 80354dc:	681b      	ldr	r3, [r3, #0]
+ 80354de:	b2db      	uxtb	r3, r3
+ 80354e0:	3b10      	subs	r3, #16
+ 80354e2:	4a27      	ldr	r2, [pc, #156]	@ (8035580 <DMA_CalcBaseAndBitshift+0x158>)
+ 80354e4:	fba2 2303 	umull	r2, r3, r2, r3
+ 80354e8:	091b      	lsrs	r3, r3, #4
+ 80354ea:	60fb      	str	r3, [r7, #12]
+
+    /* lookup table for necessary bitshift of flags within status registers */
+    static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U};
+    hdma->StreamIndex = flagBitshiftOffset[stream_number & 0x7U];
+ 80354ec:	68fb      	ldr	r3, [r7, #12]
+ 80354ee:	f003 0307 	and.w	r3, r3, #7
+ 80354f2:	4a24      	ldr	r2, [pc, #144]	@ (8035584 <DMA_CalcBaseAndBitshift+0x15c>)
+ 80354f4:	5cd3      	ldrb	r3, [r2, r3]
+ 80354f6:	461a      	mov	r2, r3
+ 80354f8:	687b      	ldr	r3, [r7, #4]
+ 80354fa:	65da      	str	r2, [r3, #92]	@ 0x5c
+
+    if (stream_number > 3U)
+ 80354fc:	68fb      	ldr	r3, [r7, #12]
+ 80354fe:	2b03      	cmp	r3, #3
+ 8035500:	d908      	bls.n	8035514 <DMA_CalcBaseAndBitshift+0xec>
+    {
+      /* return pointer to HISR and HIFCR */
+      hdma->StreamBaseAddress = (((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU)) + 4U);
+ 8035502:	687b      	ldr	r3, [r7, #4]
+ 8035504:	681b      	ldr	r3, [r3, #0]
+ 8035506:	461a      	mov	r2, r3
+ 8035508:	4b1f      	ldr	r3, [pc, #124]	@ (8035588 <DMA_CalcBaseAndBitshift+0x160>)
+ 803550a:	4013      	ands	r3, r2
+ 803550c:	1d1a      	adds	r2, r3, #4
+ 803550e:	687b      	ldr	r3, [r7, #4]
+ 8035510:	659a      	str	r2, [r3, #88]	@ 0x58
+ 8035512:	e00d      	b.n	8035530 <DMA_CalcBaseAndBitshift+0x108>
+    }
+    else
+    {
+      /* return pointer to LISR and LIFCR */
+      hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU));
+ 8035514:	687b      	ldr	r3, [r7, #4]
+ 8035516:	681b      	ldr	r3, [r3, #0]
+ 8035518:	461a      	mov	r2, r3
+ 803551a:	4b1b      	ldr	r3, [pc, #108]	@ (8035588 <DMA_CalcBaseAndBitshift+0x160>)
+ 803551c:	4013      	ands	r3, r2
+ 803551e:	687a      	ldr	r2, [r7, #4]
+ 8035520:	6593      	str	r3, [r2, #88]	@ 0x58
+ 8035522:	e005      	b.n	8035530 <DMA_CalcBaseAndBitshift+0x108>
+    }
+  }
+  else /* BDMA instance(s) */
+  {
+    /* return pointer to ISR and IFCR */
+    hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0xFFU));
+ 8035524:	687b      	ldr	r3, [r7, #4]
+ 8035526:	681b      	ldr	r3, [r3, #0]
+ 8035528:	f023 02ff 	bic.w	r2, r3, #255	@ 0xff
+ 803552c:	687b      	ldr	r3, [r7, #4]
+ 803552e:	659a      	str	r2, [r3, #88]	@ 0x58
+  }
+
+  return hdma->StreamBaseAddress;
+ 8035530:	687b      	ldr	r3, [r7, #4]
+ 8035532:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
+}
+ 8035534:	4618      	mov	r0, r3
+ 8035536:	3714      	adds	r7, #20
+ 8035538:	46bd      	mov	sp, r7
+ 803553a:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 803553e:	4770      	bx	lr
+ 8035540:	40020010 	.word	0x40020010
+ 8035544:	40020028 	.word	0x40020028
+ 8035548:	40020040 	.word	0x40020040
+ 803554c:	40020058 	.word	0x40020058
+ 8035550:	40020070 	.word	0x40020070
+ 8035554:	40020088 	.word	0x40020088
+ 8035558:	400200a0 	.word	0x400200a0
+ 803555c:	400200b8 	.word	0x400200b8
+ 8035560:	40020410 	.word	0x40020410
+ 8035564:	40020428 	.word	0x40020428
+ 8035568:	40020440 	.word	0x40020440
+ 803556c:	40020458 	.word	0x40020458
+ 8035570:	40020470 	.word	0x40020470
+ 8035574:	40020488 	.word	0x40020488
+ 8035578:	400204a0 	.word	0x400204a0
+ 803557c:	400204b8 	.word	0x400204b8
+ 8035580:	aaaaaaab 	.word	0xaaaaaaab
+ 8035584:	08041c68 	.word	0x08041c68
+ 8035588:	fffffc00 	.word	0xfffffc00
+
+0803558c <DMA_CheckFifoParam>:
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma)
+{
+ 803558c:	b480      	push	{r7}
+ 803558e:	b085      	sub	sp, #20
+ 8035590:	af00      	add	r7, sp, #0
+ 8035592:	6078      	str	r0, [r7, #4]
+  HAL_StatusTypeDef status = HAL_OK;
+ 8035594:	2300      	movs	r3, #0
+ 8035596:	73fb      	strb	r3, [r7, #15]
+
+  /* Memory Data size equal to Byte */
+  if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE)
+ 8035598:	687b      	ldr	r3, [r7, #4]
+ 803559a:	699b      	ldr	r3, [r3, #24]
+ 803559c:	2b00      	cmp	r3, #0
+ 803559e:	d120      	bne.n	80355e2 <DMA_CheckFifoParam+0x56>
+  {
+    switch (hdma->Init.FIFOThreshold)
+ 80355a0:	687b      	ldr	r3, [r7, #4]
+ 80355a2:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 80355a4:	2b03      	cmp	r3, #3
+ 80355a6:	d858      	bhi.n	803565a <DMA_CheckFifoParam+0xce>
+ 80355a8:	a201      	add	r2, pc, #4	@ (adr r2, 80355b0 <DMA_CheckFifoParam+0x24>)
+ 80355aa:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 80355ae:	bf00      	nop
+ 80355b0:	080355c1 	.word	0x080355c1
+ 80355b4:	080355d3 	.word	0x080355d3
+ 80355b8:	080355c1 	.word	0x080355c1
+ 80355bc:	0803565b 	.word	0x0803565b
+    {
+      case DMA_FIFO_THRESHOLD_1QUARTERFULL:
+      case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
+
+        if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
+ 80355c0:	687b      	ldr	r3, [r7, #4]
+ 80355c2:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 80355c4:	f003 7380 	and.w	r3, r3, #16777216	@ 0x1000000
+ 80355c8:	2b00      	cmp	r3, #0
+ 80355ca:	d048      	beq.n	803565e <DMA_CheckFifoParam+0xd2>
+        {
+          status = HAL_ERROR;
+ 80355cc:	2301      	movs	r3, #1
+ 80355ce:	73fb      	strb	r3, [r7, #15]
+        }
+        break;
+ 80355d0:	e045      	b.n	803565e <DMA_CheckFifoParam+0xd2>
+
+      case DMA_FIFO_THRESHOLD_HALFFULL:
+        if (hdma->Init.MemBurst == DMA_MBURST_INC16)
+ 80355d2:	687b      	ldr	r3, [r7, #4]
+ 80355d4:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 80355d6:	f1b3 7fc0 	cmp.w	r3, #25165824	@ 0x1800000
+ 80355da:	d142      	bne.n	8035662 <DMA_CheckFifoParam+0xd6>
+        {
+          status = HAL_ERROR;
+ 80355dc:	2301      	movs	r3, #1
+ 80355de:	73fb      	strb	r3, [r7, #15]
+        }
+        break;
+ 80355e0:	e03f      	b.n	8035662 <DMA_CheckFifoParam+0xd6>
+        break;
+    }
+  }
+
+  /* Memory Data size equal to Half-Word */
+  else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
+ 80355e2:	687b      	ldr	r3, [r7, #4]
+ 80355e4:	699b      	ldr	r3, [r3, #24]
+ 80355e6:	f5b3 5f00 	cmp.w	r3, #8192	@ 0x2000
+ 80355ea:	d123      	bne.n	8035634 <DMA_CheckFifoParam+0xa8>
+  {
+    switch (hdma->Init.FIFOThreshold)
+ 80355ec:	687b      	ldr	r3, [r7, #4]
+ 80355ee:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 80355f0:	2b03      	cmp	r3, #3
+ 80355f2:	d838      	bhi.n	8035666 <DMA_CheckFifoParam+0xda>
+ 80355f4:	a201      	add	r2, pc, #4	@ (adr r2, 80355fc <DMA_CheckFifoParam+0x70>)
+ 80355f6:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 80355fa:	bf00      	nop
+ 80355fc:	0803560d 	.word	0x0803560d
+ 8035600:	08035613 	.word	0x08035613
+ 8035604:	0803560d 	.word	0x0803560d
+ 8035608:	08035625 	.word	0x08035625
+    {
+      case DMA_FIFO_THRESHOLD_1QUARTERFULL:
+      case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
+        status = HAL_ERROR;
+ 803560c:	2301      	movs	r3, #1
+ 803560e:	73fb      	strb	r3, [r7, #15]
+        break;
+ 8035610:	e030      	b.n	8035674 <DMA_CheckFifoParam+0xe8>
+
+      case DMA_FIFO_THRESHOLD_HALFFULL:
+        if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
+ 8035612:	687b      	ldr	r3, [r7, #4]
+ 8035614:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 8035616:	f003 7380 	and.w	r3, r3, #16777216	@ 0x1000000
+ 803561a:	2b00      	cmp	r3, #0
+ 803561c:	d025      	beq.n	803566a <DMA_CheckFifoParam+0xde>
+        {
+          status = HAL_ERROR;
+ 803561e:	2301      	movs	r3, #1
+ 8035620:	73fb      	strb	r3, [r7, #15]
+        }
+        break;
+ 8035622:	e022      	b.n	803566a <DMA_CheckFifoParam+0xde>
+
+      case DMA_FIFO_THRESHOLD_FULL:
+        if (hdma->Init.MemBurst == DMA_MBURST_INC16)
+ 8035624:	687b      	ldr	r3, [r7, #4]
+ 8035626:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 8035628:	f1b3 7fc0 	cmp.w	r3, #25165824	@ 0x1800000
+ 803562c:	d11f      	bne.n	803566e <DMA_CheckFifoParam+0xe2>
+        {
+          status = HAL_ERROR;
+ 803562e:	2301      	movs	r3, #1
+ 8035630:	73fb      	strb	r3, [r7, #15]
+        }
+        break;
+ 8035632:	e01c      	b.n	803566e <DMA_CheckFifoParam+0xe2>
+  }
+
+  /* Memory Data size equal to Word */
+  else
+  {
+    switch (hdma->Init.FIFOThreshold)
+ 8035634:	687b      	ldr	r3, [r7, #4]
+ 8035636:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 8035638:	2b02      	cmp	r3, #2
+ 803563a:	d902      	bls.n	8035642 <DMA_CheckFifoParam+0xb6>
+ 803563c:	2b03      	cmp	r3, #3
+ 803563e:	d003      	beq.n	8035648 <DMA_CheckFifoParam+0xbc>
+          status = HAL_ERROR;
+        }
+    break;
+
+      default:
+        break;
+ 8035640:	e018      	b.n	8035674 <DMA_CheckFifoParam+0xe8>
+        status = HAL_ERROR;
+ 8035642:	2301      	movs	r3, #1
+ 8035644:	73fb      	strb	r3, [r7, #15]
+        break;
+ 8035646:	e015      	b.n	8035674 <DMA_CheckFifoParam+0xe8>
+        if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
+ 8035648:	687b      	ldr	r3, [r7, #4]
+ 803564a:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 803564c:	f003 7380 	and.w	r3, r3, #16777216	@ 0x1000000
+ 8035650:	2b00      	cmp	r3, #0
+ 8035652:	d00e      	beq.n	8035672 <DMA_CheckFifoParam+0xe6>
+          status = HAL_ERROR;
+ 8035654:	2301      	movs	r3, #1
+ 8035656:	73fb      	strb	r3, [r7, #15]
+    break;
+ 8035658:	e00b      	b.n	8035672 <DMA_CheckFifoParam+0xe6>
+        break;
+ 803565a:	bf00      	nop
+ 803565c:	e00a      	b.n	8035674 <DMA_CheckFifoParam+0xe8>
+        break;
+ 803565e:	bf00      	nop
+ 8035660:	e008      	b.n	8035674 <DMA_CheckFifoParam+0xe8>
+        break;
+ 8035662:	bf00      	nop
+ 8035664:	e006      	b.n	8035674 <DMA_CheckFifoParam+0xe8>
+        break;
+ 8035666:	bf00      	nop
+ 8035668:	e004      	b.n	8035674 <DMA_CheckFifoParam+0xe8>
+        break;
+ 803566a:	bf00      	nop
+ 803566c:	e002      	b.n	8035674 <DMA_CheckFifoParam+0xe8>
+        break;
+ 803566e:	bf00      	nop
+ 8035670:	e000      	b.n	8035674 <DMA_CheckFifoParam+0xe8>
+    break;
+ 8035672:	bf00      	nop
+    }
+  }
+
+  return status;
+ 8035674:	7bfb      	ldrb	r3, [r7, #15]
+}
+ 8035676:	4618      	mov	r0, r3
+ 8035678:	3714      	adds	r7, #20
+ 803567a:	46bd      	mov	sp, r7
+ 803567c:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8035680:	4770      	bx	lr
+ 8035682:	bf00      	nop
+
+08035684 <DMA_CalcDMAMUXChannelBaseAndMask>:
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @retval HAL status
+  */
+static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma)
+{
+ 8035684:	b480      	push	{r7}
+ 8035686:	b085      	sub	sp, #20
+ 8035688:	af00      	add	r7, sp, #0
+ 803568a:	6078      	str	r0, [r7, #4]
+  uint32_t stream_number;
+  uint32_t stream_baseaddress = (uint32_t)((uint32_t*)hdma->Instance);
+ 803568c:	687b      	ldr	r3, [r7, #4]
+ 803568e:	681b      	ldr	r3, [r3, #0]
+ 8035690:	60bb      	str	r3, [r7, #8]
+
+  if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U)
+ 8035692:	687b      	ldr	r3, [r7, #4]
+ 8035694:	681b      	ldr	r3, [r3, #0]
+ 8035696:	4a38      	ldr	r2, [pc, #224]	@ (8035778 <DMA_CalcDMAMUXChannelBaseAndMask+0xf4>)
+ 8035698:	4293      	cmp	r3, r2
+ 803569a:	d022      	beq.n	80356e2 <DMA_CalcDMAMUXChannelBaseAndMask+0x5e>
+ 803569c:	687b      	ldr	r3, [r7, #4]
+ 803569e:	681b      	ldr	r3, [r3, #0]
+ 80356a0:	4a36      	ldr	r2, [pc, #216]	@ (803577c <DMA_CalcDMAMUXChannelBaseAndMask+0xf8>)
+ 80356a2:	4293      	cmp	r3, r2
+ 80356a4:	d01d      	beq.n	80356e2 <DMA_CalcDMAMUXChannelBaseAndMask+0x5e>
+ 80356a6:	687b      	ldr	r3, [r7, #4]
+ 80356a8:	681b      	ldr	r3, [r3, #0]
+ 80356aa:	4a35      	ldr	r2, [pc, #212]	@ (8035780 <DMA_CalcDMAMUXChannelBaseAndMask+0xfc>)
+ 80356ac:	4293      	cmp	r3, r2
+ 80356ae:	d018      	beq.n	80356e2 <DMA_CalcDMAMUXChannelBaseAndMask+0x5e>
+ 80356b0:	687b      	ldr	r3, [r7, #4]
+ 80356b2:	681b      	ldr	r3, [r3, #0]
+ 80356b4:	4a33      	ldr	r2, [pc, #204]	@ (8035784 <DMA_CalcDMAMUXChannelBaseAndMask+0x100>)
+ 80356b6:	4293      	cmp	r3, r2
+ 80356b8:	d013      	beq.n	80356e2 <DMA_CalcDMAMUXChannelBaseAndMask+0x5e>
+ 80356ba:	687b      	ldr	r3, [r7, #4]
+ 80356bc:	681b      	ldr	r3, [r3, #0]
+ 80356be:	4a32      	ldr	r2, [pc, #200]	@ (8035788 <DMA_CalcDMAMUXChannelBaseAndMask+0x104>)
+ 80356c0:	4293      	cmp	r3, r2
+ 80356c2:	d00e      	beq.n	80356e2 <DMA_CalcDMAMUXChannelBaseAndMask+0x5e>
+ 80356c4:	687b      	ldr	r3, [r7, #4]
+ 80356c6:	681b      	ldr	r3, [r3, #0]
+ 80356c8:	4a30      	ldr	r2, [pc, #192]	@ (803578c <DMA_CalcDMAMUXChannelBaseAndMask+0x108>)
+ 80356ca:	4293      	cmp	r3, r2
+ 80356cc:	d009      	beq.n	80356e2 <DMA_CalcDMAMUXChannelBaseAndMask+0x5e>
+ 80356ce:	687b      	ldr	r3, [r7, #4]
+ 80356d0:	681b      	ldr	r3, [r3, #0]
+ 80356d2:	4a2f      	ldr	r2, [pc, #188]	@ (8035790 <DMA_CalcDMAMUXChannelBaseAndMask+0x10c>)
+ 80356d4:	4293      	cmp	r3, r2
+ 80356d6:	d004      	beq.n	80356e2 <DMA_CalcDMAMUXChannelBaseAndMask+0x5e>
+ 80356d8:	687b      	ldr	r3, [r7, #4]
+ 80356da:	681b      	ldr	r3, [r3, #0]
+ 80356dc:	4a2d      	ldr	r2, [pc, #180]	@ (8035794 <DMA_CalcDMAMUXChannelBaseAndMask+0x110>)
+ 80356de:	4293      	cmp	r3, r2
+ 80356e0:	d101      	bne.n	80356e6 <DMA_CalcDMAMUXChannelBaseAndMask+0x62>
+ 80356e2:	2301      	movs	r3, #1
+ 80356e4:	e000      	b.n	80356e8 <DMA_CalcDMAMUXChannelBaseAndMask+0x64>
+ 80356e6:	2300      	movs	r3, #0
+ 80356e8:	2b00      	cmp	r3, #0
+ 80356ea:	d01a      	beq.n	8035722 <DMA_CalcDMAMUXChannelBaseAndMask+0x9e>
+  {
+    /* BDMA Channels are connected to DMAMUX2 channels */
+    stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 8U) / 20U;
+ 80356ec:	687b      	ldr	r3, [r7, #4]
+ 80356ee:	681b      	ldr	r3, [r3, #0]
+ 80356f0:	b2db      	uxtb	r3, r3
+ 80356f2:	3b08      	subs	r3, #8
+ 80356f4:	4a28      	ldr	r2, [pc, #160]	@ (8035798 <DMA_CalcDMAMUXChannelBaseAndMask+0x114>)
+ 80356f6:	fba2 2303 	umull	r2, r3, r2, r3
+ 80356fa:	091b      	lsrs	r3, r3, #4
+ 80356fc:	60fb      	str	r3, [r7, #12]
+    hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_Channel0) + (stream_number * 4U)));
+ 80356fe:	68fa      	ldr	r2, [r7, #12]
+ 8035700:	4b26      	ldr	r3, [pc, #152]	@ (803579c <DMA_CalcDMAMUXChannelBaseAndMask+0x118>)
+ 8035702:	4413      	add	r3, r2
+ 8035704:	009b      	lsls	r3, r3, #2
+ 8035706:	461a      	mov	r2, r3
+ 8035708:	687b      	ldr	r3, [r7, #4]
+ 803570a:	661a      	str	r2, [r3, #96]	@ 0x60
+    hdma->DMAmuxChannelStatus = DMAMUX2_ChannelStatus;
+ 803570c:	687b      	ldr	r3, [r7, #4]
+ 803570e:	4a24      	ldr	r2, [pc, #144]	@ (80357a0 <DMA_CalcDMAMUXChannelBaseAndMask+0x11c>)
+ 8035710:	665a      	str	r2, [r3, #100]	@ 0x64
+    hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU);
+ 8035712:	68fb      	ldr	r3, [r7, #12]
+ 8035714:	f003 031f 	and.w	r3, r3, #31
+ 8035718:	2201      	movs	r2, #1
+ 803571a:	409a      	lsls	r2, r3
+ 803571c:	687b      	ldr	r3, [r7, #4]
+ 803571e:	669a      	str	r2, [r3, #104]	@ 0x68
+    }
+    hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_Channel0) + (stream_number * 4U)));
+    hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus;
+    hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU);
+  }
+}
+ 8035720:	e024      	b.n	803576c <DMA_CalcDMAMUXChannelBaseAndMask+0xe8>
+    stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U;
+ 8035722:	687b      	ldr	r3, [r7, #4]
+ 8035724:	681b      	ldr	r3, [r3, #0]
+ 8035726:	b2db      	uxtb	r3, r3
+ 8035728:	3b10      	subs	r3, #16
+ 803572a:	4a1e      	ldr	r2, [pc, #120]	@ (80357a4 <DMA_CalcDMAMUXChannelBaseAndMask+0x120>)
+ 803572c:	fba2 2303 	umull	r2, r3, r2, r3
+ 8035730:	091b      	lsrs	r3, r3, #4
+ 8035732:	60fb      	str	r3, [r7, #12]
+    if((stream_baseaddress <= ((uint32_t)DMA2_Stream7) ) && \
+ 8035734:	68bb      	ldr	r3, [r7, #8]
+ 8035736:	4a1c      	ldr	r2, [pc, #112]	@ (80357a8 <DMA_CalcDMAMUXChannelBaseAndMask+0x124>)
+ 8035738:	4293      	cmp	r3, r2
+ 803573a:	d806      	bhi.n	803574a <DMA_CalcDMAMUXChannelBaseAndMask+0xc6>
+ 803573c:	68bb      	ldr	r3, [r7, #8]
+ 803573e:	4a1b      	ldr	r2, [pc, #108]	@ (80357ac <DMA_CalcDMAMUXChannelBaseAndMask+0x128>)
+ 8035740:	4293      	cmp	r3, r2
+ 8035742:	d902      	bls.n	803574a <DMA_CalcDMAMUXChannelBaseAndMask+0xc6>
+      stream_number += 8U;
+ 8035744:	68fb      	ldr	r3, [r7, #12]
+ 8035746:	3308      	adds	r3, #8
+ 8035748:	60fb      	str	r3, [r7, #12]
+    hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_Channel0) + (stream_number * 4U)));
+ 803574a:	68fa      	ldr	r2, [r7, #12]
+ 803574c:	4b18      	ldr	r3, [pc, #96]	@ (80357b0 <DMA_CalcDMAMUXChannelBaseAndMask+0x12c>)
+ 803574e:	4413      	add	r3, r2
+ 8035750:	009b      	lsls	r3, r3, #2
+ 8035752:	461a      	mov	r2, r3
+ 8035754:	687b      	ldr	r3, [r7, #4]
+ 8035756:	661a      	str	r2, [r3, #96]	@ 0x60
+    hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus;
+ 8035758:	687b      	ldr	r3, [r7, #4]
+ 803575a:	4a16      	ldr	r2, [pc, #88]	@ (80357b4 <DMA_CalcDMAMUXChannelBaseAndMask+0x130>)
+ 803575c:	665a      	str	r2, [r3, #100]	@ 0x64
+    hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU);
+ 803575e:	68fb      	ldr	r3, [r7, #12]
+ 8035760:	f003 031f 	and.w	r3, r3, #31
+ 8035764:	2201      	movs	r2, #1
+ 8035766:	409a      	lsls	r2, r3
+ 8035768:	687b      	ldr	r3, [r7, #4]
+ 803576a:	669a      	str	r2, [r3, #104]	@ 0x68
+}
+ 803576c:	bf00      	nop
+ 803576e:	3714      	adds	r7, #20
+ 8035770:	46bd      	mov	sp, r7
+ 8035772:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8035776:	4770      	bx	lr
+ 8035778:	58025408 	.word	0x58025408
+ 803577c:	5802541c 	.word	0x5802541c
+ 8035780:	58025430 	.word	0x58025430
+ 8035784:	58025444 	.word	0x58025444
+ 8035788:	58025458 	.word	0x58025458
+ 803578c:	5802546c 	.word	0x5802546c
+ 8035790:	58025480 	.word	0x58025480
+ 8035794:	58025494 	.word	0x58025494
+ 8035798:	cccccccd 	.word	0xcccccccd
+ 803579c:	16009600 	.word	0x16009600
+ 80357a0:	58025880 	.word	0x58025880
+ 80357a4:	aaaaaaab 	.word	0xaaaaaaab
+ 80357a8:	400204b8 	.word	0x400204b8
+ 80357ac:	4002040f 	.word	0x4002040f
+ 80357b0:	10008200 	.word	0x10008200
+ 80357b4:	40020880 	.word	0x40020880
+
+080357b8 <DMA_CalcDMAMUXRequestGenBaseAndMask>:
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @retval HAL status
+  */
+static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma)
+{
+ 80357b8:	b480      	push	{r7}
+ 80357ba:	b085      	sub	sp, #20
+ 80357bc:	af00      	add	r7, sp, #0
+ 80357be:	6078      	str	r0, [r7, #4]
+  uint32_t request =  hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID;
+ 80357c0:	687b      	ldr	r3, [r7, #4]
+ 80357c2:	685b      	ldr	r3, [r3, #4]
+ 80357c4:	b2db      	uxtb	r3, r3
+ 80357c6:	60fb      	str	r3, [r7, #12]
+
+  if((request >= DMA_REQUEST_GENERATOR0) && (request <= DMA_REQUEST_GENERATOR7))
+ 80357c8:	68fb      	ldr	r3, [r7, #12]
+ 80357ca:	2b00      	cmp	r3, #0
+ 80357cc:	d04a      	beq.n	8035864 <DMA_CalcDMAMUXRequestGenBaseAndMask+0xac>
+ 80357ce:	68fb      	ldr	r3, [r7, #12]
+ 80357d0:	2b08      	cmp	r3, #8
+ 80357d2:	d847      	bhi.n	8035864 <DMA_CalcDMAMUXRequestGenBaseAndMask+0xac>
+  {
+    if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U)
+ 80357d4:	687b      	ldr	r3, [r7, #4]
+ 80357d6:	681b      	ldr	r3, [r3, #0]
+ 80357d8:	4a25      	ldr	r2, [pc, #148]	@ (8035870 <DMA_CalcDMAMUXRequestGenBaseAndMask+0xb8>)
+ 80357da:	4293      	cmp	r3, r2
+ 80357dc:	d022      	beq.n	8035824 <DMA_CalcDMAMUXRequestGenBaseAndMask+0x6c>
+ 80357de:	687b      	ldr	r3, [r7, #4]
+ 80357e0:	681b      	ldr	r3, [r3, #0]
+ 80357e2:	4a24      	ldr	r2, [pc, #144]	@ (8035874 <DMA_CalcDMAMUXRequestGenBaseAndMask+0xbc>)
+ 80357e4:	4293      	cmp	r3, r2
+ 80357e6:	d01d      	beq.n	8035824 <DMA_CalcDMAMUXRequestGenBaseAndMask+0x6c>
+ 80357e8:	687b      	ldr	r3, [r7, #4]
+ 80357ea:	681b      	ldr	r3, [r3, #0]
+ 80357ec:	4a22      	ldr	r2, [pc, #136]	@ (8035878 <DMA_CalcDMAMUXRequestGenBaseAndMask+0xc0>)
+ 80357ee:	4293      	cmp	r3, r2
+ 80357f0:	d018      	beq.n	8035824 <DMA_CalcDMAMUXRequestGenBaseAndMask+0x6c>
+ 80357f2:	687b      	ldr	r3, [r7, #4]
+ 80357f4:	681b      	ldr	r3, [r3, #0]
+ 80357f6:	4a21      	ldr	r2, [pc, #132]	@ (803587c <DMA_CalcDMAMUXRequestGenBaseAndMask+0xc4>)
+ 80357f8:	4293      	cmp	r3, r2
+ 80357fa:	d013      	beq.n	8035824 <DMA_CalcDMAMUXRequestGenBaseAndMask+0x6c>
+ 80357fc:	687b      	ldr	r3, [r7, #4]
+ 80357fe:	681b      	ldr	r3, [r3, #0]
+ 8035800:	4a1f      	ldr	r2, [pc, #124]	@ (8035880 <DMA_CalcDMAMUXRequestGenBaseAndMask+0xc8>)
+ 8035802:	4293      	cmp	r3, r2
+ 8035804:	d00e      	beq.n	8035824 <DMA_CalcDMAMUXRequestGenBaseAndMask+0x6c>
+ 8035806:	687b      	ldr	r3, [r7, #4]
+ 8035808:	681b      	ldr	r3, [r3, #0]
+ 803580a:	4a1e      	ldr	r2, [pc, #120]	@ (8035884 <DMA_CalcDMAMUXRequestGenBaseAndMask+0xcc>)
+ 803580c:	4293      	cmp	r3, r2
+ 803580e:	d009      	beq.n	8035824 <DMA_CalcDMAMUXRequestGenBaseAndMask+0x6c>
+ 8035810:	687b      	ldr	r3, [r7, #4]
+ 8035812:	681b      	ldr	r3, [r3, #0]
+ 8035814:	4a1c      	ldr	r2, [pc, #112]	@ (8035888 <DMA_CalcDMAMUXRequestGenBaseAndMask+0xd0>)
+ 8035816:	4293      	cmp	r3, r2
+ 8035818:	d004      	beq.n	8035824 <DMA_CalcDMAMUXRequestGenBaseAndMask+0x6c>
+ 803581a:	687b      	ldr	r3, [r7, #4]
+ 803581c:	681b      	ldr	r3, [r3, #0]
+ 803581e:	4a1b      	ldr	r2, [pc, #108]	@ (803588c <DMA_CalcDMAMUXRequestGenBaseAndMask+0xd4>)
+ 8035820:	4293      	cmp	r3, r2
+ 8035822:	d101      	bne.n	8035828 <DMA_CalcDMAMUXRequestGenBaseAndMask+0x70>
+ 8035824:	2301      	movs	r3, #1
+ 8035826:	e000      	b.n	803582a <DMA_CalcDMAMUXRequestGenBaseAndMask+0x72>
+ 8035828:	2300      	movs	r3, #0
+ 803582a:	2b00      	cmp	r3, #0
+ 803582c:	d00a      	beq.n	8035844 <DMA_CalcDMAMUXRequestGenBaseAndMask+0x8c>
+    {
+      /* BDMA Channels are connected to DMAMUX2 request generator blocks */
+      hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_RequestGenerator0) + ((request - 1U) * 4U)));
+ 803582e:	68fa      	ldr	r2, [r7, #12]
+ 8035830:	4b17      	ldr	r3, [pc, #92]	@ (8035890 <DMA_CalcDMAMUXRequestGenBaseAndMask+0xd8>)
+ 8035832:	4413      	add	r3, r2
+ 8035834:	009b      	lsls	r3, r3, #2
+ 8035836:	461a      	mov	r2, r3
+ 8035838:	687b      	ldr	r3, [r7, #4]
+ 803583a:	66da      	str	r2, [r3, #108]	@ 0x6c
+
+      hdma->DMAmuxRequestGenStatus = DMAMUX2_RequestGenStatus;
+ 803583c:	687b      	ldr	r3, [r7, #4]
+ 803583e:	4a15      	ldr	r2, [pc, #84]	@ (8035894 <DMA_CalcDMAMUXRequestGenBaseAndMask+0xdc>)
+ 8035840:	671a      	str	r2, [r3, #112]	@ 0x70
+ 8035842:	e009      	b.n	8035858 <DMA_CalcDMAMUXRequestGenBaseAndMask+0xa0>
+    }
+    else
+    {
+      /* DMA1 and DMA2 Streams use DMAMUX1 request generator blocks */
+      hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U)));
+ 8035844:	68fa      	ldr	r2, [r7, #12]
+ 8035846:	4b14      	ldr	r3, [pc, #80]	@ (8035898 <DMA_CalcDMAMUXRequestGenBaseAndMask+0xe0>)
+ 8035848:	4413      	add	r3, r2
+ 803584a:	009b      	lsls	r3, r3, #2
+ 803584c:	461a      	mov	r2, r3
+ 803584e:	687b      	ldr	r3, [r7, #4]
+ 8035850:	66da      	str	r2, [r3, #108]	@ 0x6c
+
+      hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus;
+ 8035852:	687b      	ldr	r3, [r7, #4]
+ 8035854:	4a11      	ldr	r2, [pc, #68]	@ (803589c <DMA_CalcDMAMUXRequestGenBaseAndMask+0xe4>)
+ 8035856:	671a      	str	r2, [r3, #112]	@ 0x70
+    }
+
+    hdma->DMAmuxRequestGenStatusMask = 1UL << (request - 1U);
+ 8035858:	68fb      	ldr	r3, [r7, #12]
+ 803585a:	3b01      	subs	r3, #1
+ 803585c:	2201      	movs	r2, #1
+ 803585e:	409a      	lsls	r2, r3
+ 8035860:	687b      	ldr	r3, [r7, #4]
+ 8035862:	675a      	str	r2, [r3, #116]	@ 0x74
+  }
+}
+ 8035864:	bf00      	nop
+ 8035866:	3714      	adds	r7, #20
+ 8035868:	46bd      	mov	sp, r7
+ 803586a:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 803586e:	4770      	bx	lr
+ 8035870:	58025408 	.word	0x58025408
+ 8035874:	5802541c 	.word	0x5802541c
+ 8035878:	58025430 	.word	0x58025430
+ 803587c:	58025444 	.word	0x58025444
+ 8035880:	58025458 	.word	0x58025458
+ 8035884:	5802546c 	.word	0x5802546c
+ 8035888:	58025480 	.word	0x58025480
+ 803588c:	58025494 	.word	0x58025494
+ 8035890:	1600963f 	.word	0x1600963f
+ 8035894:	58025940 	.word	0x58025940
+ 8035898:	1000823f 	.word	0x1000823f
+ 803589c:	40020940 	.word	0x40020940
+
+080358a0 <HAL_ETH_Init>:
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
+{
+ 80358a0:	b580      	push	{r7, lr}
+ 80358a2:	b084      	sub	sp, #16
+ 80358a4:	af00      	add	r7, sp, #0
+ 80358a6:	6078      	str	r0, [r7, #4]
+  uint32_t tickstart;
+
+  if (heth == NULL)
+ 80358a8:	687b      	ldr	r3, [r7, #4]
+ 80358aa:	2b00      	cmp	r3, #0
+ 80358ac:	d101      	bne.n	80358b2 <HAL_ETH_Init+0x12>
+  {
+    return HAL_ERROR;
+ 80358ae:	2301      	movs	r3, #1
+ 80358b0:	e0e3      	b.n	8035a7a <HAL_ETH_Init+0x1da>
+  }
+  if (heth->gState == HAL_ETH_STATE_RESET)
+ 80358b2:	687b      	ldr	r3, [r7, #4]
+ 80358b4:	f8d3 3084 	ldr.w	r3, [r3, #132]	@ 0x84
+ 80358b8:	2b00      	cmp	r3, #0
+ 80358ba:	d106      	bne.n	80358ca <HAL_ETH_Init+0x2a>
+  {
+    heth->gState = HAL_ETH_STATE_BUSY;
+ 80358bc:	687b      	ldr	r3, [r7, #4]
+ 80358be:	2223      	movs	r2, #35	@ 0x23
+ 80358c0:	f8c3 2084 	str.w	r2, [r3, #132]	@ 0x84
+
+    /* Init the low level hardware */
+    heth->MspInitCallback(heth);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC. */
+    HAL_ETH_MspInit(heth);
+ 80358c4:	6878      	ldr	r0, [r7, #4]
+ 80358c6:	f7f3 fb93 	bl	8028ff0 <HAL_ETH_MspInit>
+
+#endif /* (USE_HAL_ETH_REGISTER_CALLBACKS) */
+  }
+
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
+ 80358ca:	4b6e      	ldr	r3, [pc, #440]	@ (8035a84 <HAL_ETH_Init+0x1e4>)
+ 80358cc:	f8d3 30f4 	ldr.w	r3, [r3, #244]	@ 0xf4
+ 80358d0:	4a6c      	ldr	r2, [pc, #432]	@ (8035a84 <HAL_ETH_Init+0x1e4>)
+ 80358d2:	f043 0302 	orr.w	r3, r3, #2
+ 80358d6:	f8c2 30f4 	str.w	r3, [r2, #244]	@ 0xf4
+ 80358da:	4b6a      	ldr	r3, [pc, #424]	@ (8035a84 <HAL_ETH_Init+0x1e4>)
+ 80358dc:	f8d3 30f4 	ldr.w	r3, [r3, #244]	@ 0xf4
+ 80358e0:	f003 0302 	and.w	r3, r3, #2
+ 80358e4:	60bb      	str	r3, [r7, #8]
+ 80358e6:	68bb      	ldr	r3, [r7, #8]
+
+  if (heth->Init.MediaInterface == HAL_ETH_MII_MODE)
+ 80358e8:	687b      	ldr	r3, [r7, #4]
+ 80358ea:	7a1b      	ldrb	r3, [r3, #8]
+ 80358ec:	2b00      	cmp	r3, #0
+ 80358ee:	d103      	bne.n	80358f8 <HAL_ETH_Init+0x58>
+  {
+    HAL_SYSCFG_ETHInterfaceSelect(SYSCFG_ETH_MII);
+ 80358f0:	2000      	movs	r0, #0
+ 80358f2:	f7fc f859 	bl	80319a8 <HAL_SYSCFG_ETHInterfaceSelect>
+ 80358f6:	e003      	b.n	8035900 <HAL_ETH_Init+0x60>
+  }
+  else
+  {
+    HAL_SYSCFG_ETHInterfaceSelect(SYSCFG_ETH_RMII);
+ 80358f8:	f44f 0000 	mov.w	r0, #8388608	@ 0x800000
+ 80358fc:	f7fc f854 	bl	80319a8 <HAL_SYSCFG_ETHInterfaceSelect>
+  }
+
+  /* Dummy read to sync with ETH */
+  (void)SYSCFG->PMCR;
+ 8035900:	4b61      	ldr	r3, [pc, #388]	@ (8035a88 <HAL_ETH_Init+0x1e8>)
+ 8035902:	685b      	ldr	r3, [r3, #4]
+
+  /* Ethernet Software reset */
+  /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
+  /* After reset all the registers holds their respective reset values */
+  SET_BIT(heth->Instance->DMAMR, ETH_DMAMR_SWR);
+ 8035904:	687b      	ldr	r3, [r7, #4]
+ 8035906:	681b      	ldr	r3, [r3, #0]
+ 8035908:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 803590c:	681b      	ldr	r3, [r3, #0]
+ 803590e:	687a      	ldr	r2, [r7, #4]
+ 8035910:	6812      	ldr	r2, [r2, #0]
+ 8035912:	f043 0301 	orr.w	r3, r3, #1
+ 8035916:	f502 5280 	add.w	r2, r2, #4096	@ 0x1000
+ 803591a:	6013      	str	r3, [r2, #0]
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+ 803591c:	f7fc f808 	bl	8031930 <HAL_GetTick>
+ 8035920:	60f8      	str	r0, [r7, #12]
+
+  /* Wait for software reset */
+  while (READ_BIT(heth->Instance->DMAMR, ETH_DMAMR_SWR) > 0U)
+ 8035922:	e011      	b.n	8035948 <HAL_ETH_Init+0xa8>
+  {
+    if (((HAL_GetTick() - tickstart) > ETH_SWRESET_TIMEOUT))
+ 8035924:	f7fc f804 	bl	8031930 <HAL_GetTick>
+ 8035928:	4602      	mov	r2, r0
+ 803592a:	68fb      	ldr	r3, [r7, #12]
+ 803592c:	1ad3      	subs	r3, r2, r3
+ 803592e:	f5b3 7ffa 	cmp.w	r3, #500	@ 0x1f4
+ 8035932:	d909      	bls.n	8035948 <HAL_ETH_Init+0xa8>
+    {
+      /* Set Error Code */
+      heth->ErrorCode = HAL_ETH_ERROR_TIMEOUT;
+ 8035934:	687b      	ldr	r3, [r7, #4]
+ 8035936:	2204      	movs	r2, #4
+ 8035938:	f8c3 2088 	str.w	r2, [r3, #136]	@ 0x88
+      /* Set State as Error */
+      heth->gState = HAL_ETH_STATE_ERROR;
+ 803593c:	687b      	ldr	r3, [r7, #4]
+ 803593e:	22e0      	movs	r2, #224	@ 0xe0
+ 8035940:	f8c3 2084 	str.w	r2, [r3, #132]	@ 0x84
+      /* Return Error */
+      return HAL_ERROR;
+ 8035944:	2301      	movs	r3, #1
+ 8035946:	e098      	b.n	8035a7a <HAL_ETH_Init+0x1da>
+  while (READ_BIT(heth->Instance->DMAMR, ETH_DMAMR_SWR) > 0U)
+ 8035948:	687b      	ldr	r3, [r7, #4]
+ 803594a:	681b      	ldr	r3, [r3, #0]
+ 803594c:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8035950:	681b      	ldr	r3, [r3, #0]
+ 8035952:	f003 0301 	and.w	r3, r3, #1
+ 8035956:	2b00      	cmp	r3, #0
+ 8035958:	d1e4      	bne.n	8035924 <HAL_ETH_Init+0x84>
+    }
+  }
+
+  /*------------------ MDIO CSR Clock Range Configuration --------------------*/
+  HAL_ETH_SetMDIOClockRange(heth);
+ 803595a:	6878      	ldr	r0, [r7, #4]
+ 803595c:	f000 f9ce 	bl	8035cfc <HAL_ETH_SetMDIOClockRange>
+
+  /*------------------ MAC LPI 1US Tic Counter Configuration --------------------*/
+  WRITE_REG(heth->Instance->MAC1USTCR, (((uint32_t)HAL_RCC_GetHCLKFreq() / ETH_MAC_US_TICK) - 1U));
+ 8035960:	f004 fb18 	bl	8039f94 <HAL_RCC_GetHCLKFreq>
+ 8035964:	4603      	mov	r3, r0
+ 8035966:	4a49      	ldr	r2, [pc, #292]	@ (8035a8c <HAL_ETH_Init+0x1ec>)
+ 8035968:	fba2 2303 	umull	r2, r3, r2, r3
+ 803596c:	0c9a      	lsrs	r2, r3, #18
+ 803596e:	687b      	ldr	r3, [r7, #4]
+ 8035970:	681b      	ldr	r3, [r3, #0]
+ 8035972:	3a01      	subs	r2, #1
+ 8035974:	f8c3 20dc 	str.w	r2, [r3, #220]	@ 0xdc
+
+  /*------------------ MAC, MTL and DMA default Configuration ----------------*/
+  ETH_MACDMAConfig(heth);
+ 8035978:	6878      	ldr	r0, [r7, #4]
+ 803597a:	f000 fbb1 	bl	80360e0 <ETH_MACDMAConfig>
+
+  /* SET DSL to 64 bit */
+  MODIFY_REG(heth->Instance->DMACCR, ETH_DMACCR_DSL, ETH_DMACCR_DSL_64BIT);
+ 803597e:	687b      	ldr	r3, [r7, #4]
+ 8035980:	681b      	ldr	r3, [r3, #0]
+ 8035982:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8035986:	f8d3 3100 	ldr.w	r3, [r3, #256]	@ 0x100
+ 803598a:	f423 13e0 	bic.w	r3, r3, #1835008	@ 0x1c0000
+ 803598e:	687a      	ldr	r2, [r7, #4]
+ 8035990:	6812      	ldr	r2, [r2, #0]
+ 8035992:	f443 2300 	orr.w	r3, r3, #524288	@ 0x80000
+ 8035996:	f502 5280 	add.w	r2, r2, #4096	@ 0x1000
+ 803599a:	f8c2 3100 	str.w	r3, [r2, #256]	@ 0x100
+
+  /* Set Receive Buffers Length (must be a multiple of 4) */
+  if ((heth->Init.RxBuffLen % 0x4U) != 0x0U)
+ 803599e:	687b      	ldr	r3, [r7, #4]
+ 80359a0:	695b      	ldr	r3, [r3, #20]
+ 80359a2:	f003 0303 	and.w	r3, r3, #3
+ 80359a6:	2b00      	cmp	r3, #0
+ 80359a8:	d009      	beq.n	80359be <HAL_ETH_Init+0x11e>
+  {
+    /* Set Error Code */
+    heth->ErrorCode = HAL_ETH_ERROR_PARAM;
+ 80359aa:	687b      	ldr	r3, [r7, #4]
+ 80359ac:	2201      	movs	r2, #1
+ 80359ae:	f8c3 2088 	str.w	r2, [r3, #136]	@ 0x88
+    /* Set State as Error */
+    heth->gState = HAL_ETH_STATE_ERROR;
+ 80359b2:	687b      	ldr	r3, [r7, #4]
+ 80359b4:	22e0      	movs	r2, #224	@ 0xe0
+ 80359b6:	f8c3 2084 	str.w	r2, [r3, #132]	@ 0x84
+    /* Return Error */
+    return HAL_ERROR;
+ 80359ba:	2301      	movs	r3, #1
+ 80359bc:	e05d      	b.n	8035a7a <HAL_ETH_Init+0x1da>
+  }
+  else
+  {
+    MODIFY_REG(heth->Instance->DMACRCR, ETH_DMACRCR_RBSZ, ((heth->Init.RxBuffLen) << 1));
+ 80359be:	687b      	ldr	r3, [r7, #4]
+ 80359c0:	681b      	ldr	r3, [r3, #0]
+ 80359c2:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 80359c6:	f8d3 2108 	ldr.w	r2, [r3, #264]	@ 0x108
+ 80359ca:	4b31      	ldr	r3, [pc, #196]	@ (8035a90 <HAL_ETH_Init+0x1f0>)
+ 80359cc:	4013      	ands	r3, r2
+ 80359ce:	687a      	ldr	r2, [r7, #4]
+ 80359d0:	6952      	ldr	r2, [r2, #20]
+ 80359d2:	0051      	lsls	r1, r2, #1
+ 80359d4:	687a      	ldr	r2, [r7, #4]
+ 80359d6:	6812      	ldr	r2, [r2, #0]
+ 80359d8:	430b      	orrs	r3, r1
+ 80359da:	f502 5280 	add.w	r2, r2, #4096	@ 0x1000
+ 80359de:	f8c2 3108 	str.w	r3, [r2, #264]	@ 0x108
+  }
+
+  /*------------------ DMA Tx Descriptors Configuration ----------------------*/
+  ETH_DMATxDescListInit(heth);
+ 80359e2:	6878      	ldr	r0, [r7, #4]
+ 80359e4:	f000 fc19 	bl	803621a <ETH_DMATxDescListInit>
+
+  /*------------------ DMA Rx Descriptors Configuration ----------------------*/
+  ETH_DMARxDescListInit(heth);
+ 80359e8:	6878      	ldr	r0, [r7, #4]
+ 80359ea:	f000 fc5f 	bl	80362ac <ETH_DMARxDescListInit>
+
+  /*--------------------- ETHERNET MAC Address Configuration ------------------*/
+  /* Set MAC addr bits 32 to 47 */
+  heth->Instance->MACA0HR = (((uint32_t)(heth->Init.MACAddr[5]) << 8) | (uint32_t)heth->Init.MACAddr[4]);
+ 80359ee:	687b      	ldr	r3, [r7, #4]
+ 80359f0:	685b      	ldr	r3, [r3, #4]
+ 80359f2:	3305      	adds	r3, #5
+ 80359f4:	781b      	ldrb	r3, [r3, #0]
+ 80359f6:	021a      	lsls	r2, r3, #8
+ 80359f8:	687b      	ldr	r3, [r7, #4]
+ 80359fa:	685b      	ldr	r3, [r3, #4]
+ 80359fc:	3304      	adds	r3, #4
+ 80359fe:	781b      	ldrb	r3, [r3, #0]
+ 8035a00:	4619      	mov	r1, r3
+ 8035a02:	687b      	ldr	r3, [r7, #4]
+ 8035a04:	681b      	ldr	r3, [r3, #0]
+ 8035a06:	430a      	orrs	r2, r1
+ 8035a08:	f8c3 2300 	str.w	r2, [r3, #768]	@ 0x300
+  /* Set MAC addr bits 0 to 31 */
+  heth->Instance->MACA0LR = (((uint32_t)(heth->Init.MACAddr[3]) << 24) | ((uint32_t)(heth->Init.MACAddr[2]) << 16) |
+ 8035a0c:	687b      	ldr	r3, [r7, #4]
+ 8035a0e:	685b      	ldr	r3, [r3, #4]
+ 8035a10:	3303      	adds	r3, #3
+ 8035a12:	781b      	ldrb	r3, [r3, #0]
+ 8035a14:	061a      	lsls	r2, r3, #24
+ 8035a16:	687b      	ldr	r3, [r7, #4]
+ 8035a18:	685b      	ldr	r3, [r3, #4]
+ 8035a1a:	3302      	adds	r3, #2
+ 8035a1c:	781b      	ldrb	r3, [r3, #0]
+ 8035a1e:	041b      	lsls	r3, r3, #16
+ 8035a20:	431a      	orrs	r2, r3
+                             ((uint32_t)(heth->Init.MACAddr[1]) << 8) | (uint32_t)heth->Init.MACAddr[0]);
+ 8035a22:	687b      	ldr	r3, [r7, #4]
+ 8035a24:	685b      	ldr	r3, [r3, #4]
+ 8035a26:	3301      	adds	r3, #1
+ 8035a28:	781b      	ldrb	r3, [r3, #0]
+ 8035a2a:	021b      	lsls	r3, r3, #8
+  heth->Instance->MACA0LR = (((uint32_t)(heth->Init.MACAddr[3]) << 24) | ((uint32_t)(heth->Init.MACAddr[2]) << 16) |
+ 8035a2c:	431a      	orrs	r2, r3
+                             ((uint32_t)(heth->Init.MACAddr[1]) << 8) | (uint32_t)heth->Init.MACAddr[0]);
+ 8035a2e:	687b      	ldr	r3, [r7, #4]
+ 8035a30:	685b      	ldr	r3, [r3, #4]
+ 8035a32:	781b      	ldrb	r3, [r3, #0]
+ 8035a34:	4619      	mov	r1, r3
+  heth->Instance->MACA0LR = (((uint32_t)(heth->Init.MACAddr[3]) << 24) | ((uint32_t)(heth->Init.MACAddr[2]) << 16) |
+ 8035a36:	687b      	ldr	r3, [r7, #4]
+ 8035a38:	681b      	ldr	r3, [r3, #0]
+                             ((uint32_t)(heth->Init.MACAddr[1]) << 8) | (uint32_t)heth->Init.MACAddr[0]);
+ 8035a3a:	430a      	orrs	r2, r1
+  heth->Instance->MACA0LR = (((uint32_t)(heth->Init.MACAddr[3]) << 24) | ((uint32_t)(heth->Init.MACAddr[2]) << 16) |
+ 8035a3c:	f8c3 2304 	str.w	r2, [r3, #772]	@ 0x304
+
+  /* Disable Rx MMC Interrupts */
+  SET_BIT(heth->Instance->MMCRIMR, ETH_MMCRIMR_RXLPITRCIM | ETH_MMCRIMR_RXLPIUSCIM | \
+ 8035a40:	687b      	ldr	r3, [r7, #4]
+ 8035a42:	681b      	ldr	r3, [r3, #0]
+ 8035a44:	f8d3 170c 	ldr.w	r1, [r3, #1804]	@ 0x70c
+ 8035a48:	687b      	ldr	r3, [r7, #4]
+ 8035a4a:	681a      	ldr	r2, [r3, #0]
+ 8035a4c:	4b11      	ldr	r3, [pc, #68]	@ (8035a94 <HAL_ETH_Init+0x1f4>)
+ 8035a4e:	430b      	orrs	r3, r1
+ 8035a50:	f8c2 370c 	str.w	r3, [r2, #1804]	@ 0x70c
+          ETH_MMCRIMR_RXUCGPIM | ETH_MMCRIMR_RXALGNERPIM | ETH_MMCRIMR_RXCRCERPIM);
+
+  /* Disable Tx MMC Interrupts */
+  SET_BIT(heth->Instance->MMCTIMR, ETH_MMCTIMR_TXLPITRCIM | ETH_MMCTIMR_TXLPIUSCIM | \
+ 8035a54:	687b      	ldr	r3, [r7, #4]
+ 8035a56:	681b      	ldr	r3, [r3, #0]
+ 8035a58:	f8d3 1710 	ldr.w	r1, [r3, #1808]	@ 0x710
+ 8035a5c:	687b      	ldr	r3, [r7, #4]
+ 8035a5e:	681a      	ldr	r2, [r3, #0]
+ 8035a60:	4b0d      	ldr	r3, [pc, #52]	@ (8035a98 <HAL_ETH_Init+0x1f8>)
+ 8035a62:	430b      	orrs	r3, r1
+ 8035a64:	f8c2 3710 	str.w	r3, [r2, #1808]	@ 0x710
+          ETH_MMCTIMR_TXGPKTIM | ETH_MMCTIMR_TXMCOLGPIM | ETH_MMCTIMR_TXSCOLGPIM);
+
+  heth->ErrorCode = HAL_ETH_ERROR_NONE;
+ 8035a68:	687b      	ldr	r3, [r7, #4]
+ 8035a6a:	2200      	movs	r2, #0
+ 8035a6c:	f8c3 2088 	str.w	r2, [r3, #136]	@ 0x88
+  heth->gState = HAL_ETH_STATE_READY;
+ 8035a70:	687b      	ldr	r3, [r7, #4]
+ 8035a72:	2210      	movs	r2, #16
+ 8035a74:	f8c3 2084 	str.w	r2, [r3, #132]	@ 0x84
+
+  return HAL_OK;
+ 8035a78:	2300      	movs	r3, #0
+}
+ 8035a7a:	4618      	mov	r0, r3
+ 8035a7c:	3710      	adds	r7, #16
+ 8035a7e:	46bd      	mov	sp, r7
+ 8035a80:	bd80      	pop	{r7, pc}
+ 8035a82:	bf00      	nop
+ 8035a84:	58024400 	.word	0x58024400
+ 8035a88:	58000400 	.word	0x58000400
+ 8035a8c:	431bde83 	.word	0x431bde83
+ 8035a90:	ffff8001 	.word	0xffff8001
+ 8035a94:	0c020060 	.word	0x0c020060
+ 8035a98:	0c20c000 	.word	0x0c20c000
+
+08035a9c <HAL_ETH_IRQHandler>:
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval HAL status
+  */
+void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
+{
+ 8035a9c:	b580      	push	{r7, lr}
+ 8035a9e:	b086      	sub	sp, #24
+ 8035aa0:	af00      	add	r7, sp, #0
+ 8035aa2:	6078      	str	r0, [r7, #4]
+  uint32_t mac_flag = READ_REG(heth->Instance->MACISR);
+ 8035aa4:	687b      	ldr	r3, [r7, #4]
+ 8035aa6:	681b      	ldr	r3, [r3, #0]
+ 8035aa8:	f8d3 30b0 	ldr.w	r3, [r3, #176]	@ 0xb0
+ 8035aac:	617b      	str	r3, [r7, #20]
+  uint32_t dma_flag = READ_REG(heth->Instance->DMACSR);
+ 8035aae:	687b      	ldr	r3, [r7, #4]
+ 8035ab0:	681b      	ldr	r3, [r3, #0]
+ 8035ab2:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8035ab6:	f8d3 3160 	ldr.w	r3, [r3, #352]	@ 0x160
+ 8035aba:	613b      	str	r3, [r7, #16]
+  uint32_t dma_itsource = READ_REG(heth->Instance->DMACIER);
+ 8035abc:	687b      	ldr	r3, [r7, #4]
+ 8035abe:	681b      	ldr	r3, [r3, #0]
+ 8035ac0:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8035ac4:	f8d3 3134 	ldr.w	r3, [r3, #308]	@ 0x134
+ 8035ac8:	60fb      	str	r3, [r7, #12]
+  uint32_t exti_d1_flag = READ_REG(EXTI_D1->PR3);
+ 8035aca:	4b6d      	ldr	r3, [pc, #436]	@ (8035c80 <HAL_ETH_IRQHandler+0x1e4>)
+ 8035acc:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 8035ace:	60bb      	str	r3, [r7, #8]
+#if defined(DUAL_CORE)
+  uint32_t exti_d2_flag = READ_REG(EXTI_D2->PR3);
+#endif /* DUAL_CORE */
+
+  /* Packet received */
+  if (((dma_flag & ETH_DMACSR_RI) != 0U) && ((dma_itsource & ETH_DMACIER_RIE) != 0U))
+ 8035ad0:	693b      	ldr	r3, [r7, #16]
+ 8035ad2:	f003 0340 	and.w	r3, r3, #64	@ 0x40
+ 8035ad6:	2b00      	cmp	r3, #0
+ 8035ad8:	d010      	beq.n	8035afc <HAL_ETH_IRQHandler+0x60>
+ 8035ada:	68fb      	ldr	r3, [r7, #12]
+ 8035adc:	f003 0340 	and.w	r3, r3, #64	@ 0x40
+ 8035ae0:	2b00      	cmp	r3, #0
+ 8035ae2:	d00b      	beq.n	8035afc <HAL_ETH_IRQHandler+0x60>
+  {
+    /* Clear the Eth DMA Rx IT pending bits */
+    __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMACSR_RI | ETH_DMACSR_NIS);
+ 8035ae4:	687b      	ldr	r3, [r7, #4]
+ 8035ae6:	681b      	ldr	r3, [r3, #0]
+ 8035ae8:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8035aec:	461a      	mov	r2, r3
+ 8035aee:	f248 0340 	movw	r3, #32832	@ 0x8040
+ 8035af2:	f8c2 3160 	str.w	r3, [r2, #352]	@ 0x160
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+    /*Call registered Receive complete callback*/
+    heth->RxCpltCallback(heth);
+#else
+    /* Receive complete callback */
+    HAL_ETH_RxCpltCallback(heth);
+ 8035af6:	6878      	ldr	r0, [r7, #4]
+ 8035af8:	f000 f8ce 	bl	8035c98 <HAL_ETH_RxCpltCallback>
+#endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
+  }
+
+  /* Packet transmitted */
+  if (((dma_flag & ETH_DMACSR_TI) != 0U) && ((dma_itsource & ETH_DMACIER_TIE) != 0U))
+ 8035afc:	693b      	ldr	r3, [r7, #16]
+ 8035afe:	f003 0301 	and.w	r3, r3, #1
+ 8035b02:	2b00      	cmp	r3, #0
+ 8035b04:	d010      	beq.n	8035b28 <HAL_ETH_IRQHandler+0x8c>
+ 8035b06:	68fb      	ldr	r3, [r7, #12]
+ 8035b08:	f003 0301 	and.w	r3, r3, #1
+ 8035b0c:	2b00      	cmp	r3, #0
+ 8035b0e:	d00b      	beq.n	8035b28 <HAL_ETH_IRQHandler+0x8c>
+  {
+    /* Clear the Eth DMA Tx IT pending bits */
+    __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMACSR_TI | ETH_DMACSR_NIS);
+ 8035b10:	687b      	ldr	r3, [r7, #4]
+ 8035b12:	681b      	ldr	r3, [r3, #0]
+ 8035b14:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8035b18:	461a      	mov	r2, r3
+ 8035b1a:	f248 0301 	movw	r3, #32769	@ 0x8001
+ 8035b1e:	f8c2 3160 	str.w	r3, [r2, #352]	@ 0x160
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+    /*Call registered Transmit complete callback*/
+    heth->TxCpltCallback(heth);
+#else
+    /* Transfer complete callback */
+    HAL_ETH_TxCpltCallback(heth);
+ 8035b22:	6878      	ldr	r0, [r7, #4]
+ 8035b24:	f000 f8ae 	bl	8035c84 <HAL_ETH_TxCpltCallback>
+#endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
+  }
+
+  /* ETH DMA Error */
+  if (((dma_flag & ETH_DMACSR_AIS) != 0U) && ((dma_itsource & ETH_DMACIER_AIE) != 0U))
+ 8035b28:	693b      	ldr	r3, [r7, #16]
+ 8035b2a:	f403 4380 	and.w	r3, r3, #16384	@ 0x4000
+ 8035b2e:	2b00      	cmp	r3, #0
+ 8035b30:	d047      	beq.n	8035bc2 <HAL_ETH_IRQHandler+0x126>
+ 8035b32:	68fb      	ldr	r3, [r7, #12]
+ 8035b34:	f403 4380 	and.w	r3, r3, #16384	@ 0x4000
+ 8035b38:	2b00      	cmp	r3, #0
+ 8035b3a:	d042      	beq.n	8035bc2 <HAL_ETH_IRQHandler+0x126>
+  {
+    heth->ErrorCode |= HAL_ETH_ERROR_DMA;
+ 8035b3c:	687b      	ldr	r3, [r7, #4]
+ 8035b3e:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
+ 8035b42:	f043 0208 	orr.w	r2, r3, #8
+ 8035b46:	687b      	ldr	r3, [r7, #4]
+ 8035b48:	f8c3 2088 	str.w	r2, [r3, #136]	@ 0x88
+    /* if fatal bus error occurred */
+    if ((dma_flag & ETH_DMACSR_FBE) != 0U)
+ 8035b4c:	693b      	ldr	r3, [r7, #16]
+ 8035b4e:	f403 5380 	and.w	r3, r3, #4096	@ 0x1000
+ 8035b52:	2b00      	cmp	r3, #0
+ 8035b54:	d01e      	beq.n	8035b94 <HAL_ETH_IRQHandler+0xf8>
+    {
+      /* Get DMA error code  */
+      heth->DMAErrorCode = READ_BIT(heth->Instance->DMACSR, (ETH_DMACSR_FBE | ETH_DMACSR_TPS | ETH_DMACSR_RPS));
+ 8035b56:	687b      	ldr	r3, [r7, #4]
+ 8035b58:	681b      	ldr	r3, [r3, #0]
+ 8035b5a:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8035b5e:	f8d3 2160 	ldr.w	r2, [r3, #352]	@ 0x160
+ 8035b62:	f241 1302 	movw	r3, #4354	@ 0x1102
+ 8035b66:	4013      	ands	r3, r2
+ 8035b68:	687a      	ldr	r2, [r7, #4]
+ 8035b6a:	f8c2 308c 	str.w	r3, [r2, #140]	@ 0x8c
+
+      /* Disable all interrupts */
+      __HAL_ETH_DMA_DISABLE_IT(heth, ETH_DMACIER_NIE | ETH_DMACIER_AIE);
+ 8035b6e:	687b      	ldr	r3, [r7, #4]
+ 8035b70:	681b      	ldr	r3, [r3, #0]
+ 8035b72:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8035b76:	f8d3 3134 	ldr.w	r3, [r3, #308]	@ 0x134
+ 8035b7a:	687a      	ldr	r2, [r7, #4]
+ 8035b7c:	6812      	ldr	r2, [r2, #0]
+ 8035b7e:	f423 4340 	bic.w	r3, r3, #49152	@ 0xc000
+ 8035b82:	f502 5280 	add.w	r2, r2, #4096	@ 0x1000
+ 8035b86:	f8c2 3134 	str.w	r3, [r2, #308]	@ 0x134
+
+      /* Set HAL state to ERROR */
+      heth->gState = HAL_ETH_STATE_ERROR;
+ 8035b8a:	687b      	ldr	r3, [r7, #4]
+ 8035b8c:	22e0      	movs	r2, #224	@ 0xe0
+ 8035b8e:	f8c3 2084 	str.w	r2, [r3, #132]	@ 0x84
+ 8035b92:	e013      	b.n	8035bbc <HAL_ETH_IRQHandler+0x120>
+    }
+    else
+    {
+      /* Get DMA error status  */
+      heth->DMAErrorCode = READ_BIT(heth->Instance->DMACSR, (ETH_DMACSR_CDE | ETH_DMACSR_ETI | ETH_DMACSR_RWT |
+ 8035b94:	687b      	ldr	r3, [r7, #4]
+ 8035b96:	681b      	ldr	r3, [r3, #0]
+ 8035b98:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8035b9c:	f8d3 3160 	ldr.w	r3, [r3, #352]	@ 0x160
+ 8035ba0:	f403 42cd 	and.w	r2, r3, #26240	@ 0x6680
+ 8035ba4:	687b      	ldr	r3, [r7, #4]
+ 8035ba6:	f8c3 208c 	str.w	r2, [r3, #140]	@ 0x8c
+                                                             ETH_DMACSR_RBU | ETH_DMACSR_AIS));
+
+      /* Clear the interrupt summary flag */
+      __HAL_ETH_DMA_CLEAR_IT(heth, (ETH_DMACSR_CDE | ETH_DMACSR_ETI | ETH_DMACSR_RWT |
+ 8035baa:	687b      	ldr	r3, [r7, #4]
+ 8035bac:	681b      	ldr	r3, [r3, #0]
+ 8035bae:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8035bb2:	461a      	mov	r2, r3
+ 8035bb4:	f44f 43cd 	mov.w	r3, #26240	@ 0x6680
+ 8035bb8:	f8c2 3160 	str.w	r3, [r2, #352]	@ 0x160
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+    /* Call registered Error callback*/
+    heth->ErrorCallback(heth);
+#else
+    /* Ethernet DMA Error callback */
+    HAL_ETH_ErrorCallback(heth);
+ 8035bbc:	6878      	ldr	r0, [r7, #4]
+ 8035bbe:	f000 f875 	bl	8035cac <HAL_ETH_ErrorCallback>
+#endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
+  }
+
+  /* ETH MAC Error IT */
+  if (((mac_flag & ETH_MACIER_RXSTSIE) == ETH_MACIER_RXSTSIE) || \
+ 8035bc2:	697b      	ldr	r3, [r7, #20]
+ 8035bc4:	f403 4380 	and.w	r3, r3, #16384	@ 0x4000
+ 8035bc8:	2b00      	cmp	r3, #0
+ 8035bca:	d104      	bne.n	8035bd6 <HAL_ETH_IRQHandler+0x13a>
+      ((mac_flag & ETH_MACIER_TXSTSIE) == ETH_MACIER_TXSTSIE))
+ 8035bcc:	697b      	ldr	r3, [r7, #20]
+ 8035bce:	f403 5300 	and.w	r3, r3, #8192	@ 0x2000
+  if (((mac_flag & ETH_MACIER_RXSTSIE) == ETH_MACIER_RXSTSIE) || \
+ 8035bd2:	2b00      	cmp	r3, #0
+ 8035bd4:	d019      	beq.n	8035c0a <HAL_ETH_IRQHandler+0x16e>
+  {
+    heth->ErrorCode |= HAL_ETH_ERROR_MAC;
+ 8035bd6:	687b      	ldr	r3, [r7, #4]
+ 8035bd8:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
+ 8035bdc:	f043 0210 	orr.w	r2, r3, #16
+ 8035be0:	687b      	ldr	r3, [r7, #4]
+ 8035be2:	f8c3 2088 	str.w	r2, [r3, #136]	@ 0x88
+
+    /* Get MAC Rx Tx status and clear Status register pending bit */
+    heth->MACErrorCode = READ_REG(heth->Instance->MACRXTXSR);
+ 8035be6:	687b      	ldr	r3, [r7, #4]
+ 8035be8:	681b      	ldr	r3, [r3, #0]
+ 8035bea:	f8d3 20b8 	ldr.w	r2, [r3, #184]	@ 0xb8
+ 8035bee:	687b      	ldr	r3, [r7, #4]
+ 8035bf0:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90
+
+    heth->gState = HAL_ETH_STATE_ERROR;
+ 8035bf4:	687b      	ldr	r3, [r7, #4]
+ 8035bf6:	22e0      	movs	r2, #224	@ 0xe0
+ 8035bf8:	f8c3 2084 	str.w	r2, [r3, #132]	@ 0x84
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+    /* Call registered Error callback*/
+    heth->ErrorCallback(heth);
+#else
+    /* Ethernet Error callback */
+    HAL_ETH_ErrorCallback(heth);
+ 8035bfc:	6878      	ldr	r0, [r7, #4]
+ 8035bfe:	f000 f855 	bl	8035cac <HAL_ETH_ErrorCallback>
+#endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
+    heth->MACErrorCode = (uint32_t)(0x0U);
+ 8035c02:	687b      	ldr	r3, [r7, #4]
+ 8035c04:	2200      	movs	r2, #0
+ 8035c06:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90
+  }
+
+  /* ETH PMT IT */
+  if ((mac_flag & ETH_MAC_PMT_IT) != 0U)
+ 8035c0a:	697b      	ldr	r3, [r7, #20]
+ 8035c0c:	f003 0310 	and.w	r3, r3, #16
+ 8035c10:	2b00      	cmp	r3, #0
+ 8035c12:	d00f      	beq.n	8035c34 <HAL_ETH_IRQHandler+0x198>
+  {
+    /* Get MAC Wake-up source and clear the status register pending bit */
+    heth->MACWakeUpEvent = READ_BIT(heth->Instance->MACPCSR, (ETH_MACPCSR_RWKPRCVD | ETH_MACPCSR_MGKPRCVD));
+ 8035c14:	687b      	ldr	r3, [r7, #4]
+ 8035c16:	681b      	ldr	r3, [r3, #0]
+ 8035c18:	f8d3 30c0 	ldr.w	r3, [r3, #192]	@ 0xc0
+ 8035c1c:	f003 0260 	and.w	r2, r3, #96	@ 0x60
+ 8035c20:	687b      	ldr	r3, [r7, #4]
+ 8035c22:	f8c3 2094 	str.w	r2, [r3, #148]	@ 0x94
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+    /* Call registered PMT callback*/
+    heth->PMTCallback(heth);
+#else
+    /* Ethernet PMT callback */
+    HAL_ETH_PMTCallback(heth);
+ 8035c26:	6878      	ldr	r0, [r7, #4]
+ 8035c28:	f000 f84a 	bl	8035cc0 <HAL_ETH_PMTCallback>
+#endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
+
+    heth->MACWakeUpEvent = (uint32_t)(0x0U);
+ 8035c2c:	687b      	ldr	r3, [r7, #4]
+ 8035c2e:	2200      	movs	r2, #0
+ 8035c30:	f8c3 2094 	str.w	r2, [r3, #148]	@ 0x94
+  }
+
+  /* ETH EEE IT */
+  if ((mac_flag & ETH_MAC_LPI_IT) != 0U)
+ 8035c34:	697b      	ldr	r3, [r7, #20]
+ 8035c36:	f003 0320 	and.w	r3, r3, #32
+ 8035c3a:	2b00      	cmp	r3, #0
+ 8035c3c:	d00f      	beq.n	8035c5e <HAL_ETH_IRQHandler+0x1c2>
+  {
+    /* Get MAC LPI interrupt source and clear the status register pending bit */
+    heth->MACLPIEvent = READ_BIT(heth->Instance->MACLCSR, 0x0000000FU);
+ 8035c3e:	687b      	ldr	r3, [r7, #4]
+ 8035c40:	681b      	ldr	r3, [r3, #0]
+ 8035c42:	f8d3 30d0 	ldr.w	r3, [r3, #208]	@ 0xd0
+ 8035c46:	f003 020f 	and.w	r2, r3, #15
+ 8035c4a:	687b      	ldr	r3, [r7, #4]
+ 8035c4c:	f8c3 2098 	str.w	r2, [r3, #152]	@ 0x98
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+    /* Call registered EEE callback*/
+    heth->EEECallback(heth);
+#else
+    /* Ethernet EEE callback */
+    HAL_ETH_EEECallback(heth);
+ 8035c50:	6878      	ldr	r0, [r7, #4]
+ 8035c52:	f000 f83f 	bl	8035cd4 <HAL_ETH_EEECallback>
+#endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
+
+    heth->MACLPIEvent = (uint32_t)(0x0U);
+ 8035c56:	687b      	ldr	r3, [r7, #4]
+ 8035c58:	2200      	movs	r2, #0
+ 8035c5a:	f8c3 2098 	str.w	r2, [r3, #152]	@ 0x98
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
+    }
+  }
+#else /* DUAL_CORE not defined */
+  /* check ETH WAKEUP exti flag */
+  if ((exti_d1_flag & ETH_WAKEUP_EXTI_LINE) != 0U)
+ 8035c5e:	68bb      	ldr	r3, [r7, #8]
+ 8035c60:	f403 0380 	and.w	r3, r3, #4194304	@ 0x400000
+ 8035c64:	2b00      	cmp	r3, #0
+ 8035c66:	d006      	beq.n	8035c76 <HAL_ETH_IRQHandler+0x1da>
+  {
+    /* Clear ETH WAKEUP Exti pending bit */
+    __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(ETH_WAKEUP_EXTI_LINE);
+ 8035c68:	4b05      	ldr	r3, [pc, #20]	@ (8035c80 <HAL_ETH_IRQHandler+0x1e4>)
+ 8035c6a:	f44f 0280 	mov.w	r2, #4194304	@ 0x400000
+ 8035c6e:	629a      	str	r2, [r3, #40]	@ 0x28
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+    /* Call registered WakeUp callback*/
+    heth->WakeUpCallback(heth);
+#else
+    /* ETH WAKEUP callback */
+    HAL_ETH_WakeUpCallback(heth);
+ 8035c70:	6878      	ldr	r0, [r7, #4]
+ 8035c72:	f000 f839 	bl	8035ce8 <HAL_ETH_WakeUpCallback>
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
+  }
+#endif /* DUAL_CORE */
+}
+ 8035c76:	bf00      	nop
+ 8035c78:	3718      	adds	r7, #24
+ 8035c7a:	46bd      	mov	sp, r7
+ 8035c7c:	bd80      	pop	{r7, pc}
+ 8035c7e:	bf00      	nop
+ 8035c80:	58000080 	.word	0x58000080
+
+08035c84 <HAL_ETH_TxCpltCallback>:
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None
+  */
+__weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
+{
+ 8035c84:	b480      	push	{r7}
+ 8035c86:	b083      	sub	sp, #12
+ 8035c88:	af00      	add	r7, sp, #0
+ 8035c8a:	6078      	str	r0, [r7, #4]
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(heth);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+  the HAL_ETH_TxCpltCallback could be implemented in the user file
+  */
+}
+ 8035c8c:	bf00      	nop
+ 8035c8e:	370c      	adds	r7, #12
+ 8035c90:	46bd      	mov	sp, r7
+ 8035c92:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8035c96:	4770      	bx	lr
+
+08035c98 <HAL_ETH_RxCpltCallback>:
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None
+  */
+__weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
+{
+ 8035c98:	b480      	push	{r7}
+ 8035c9a:	b083      	sub	sp, #12
+ 8035c9c:	af00      	add	r7, sp, #0
+ 8035c9e:	6078      	str	r0, [r7, #4]
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(heth);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+  the HAL_ETH_RxCpltCallback could be implemented in the user file
+  */
+}
+ 8035ca0:	bf00      	nop
+ 8035ca2:	370c      	adds	r7, #12
+ 8035ca4:	46bd      	mov	sp, r7
+ 8035ca6:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8035caa:	4770      	bx	lr
+
+08035cac <HAL_ETH_ErrorCallback>:
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None
+  */
+__weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
+{
+ 8035cac:	b480      	push	{r7}
+ 8035cae:	b083      	sub	sp, #12
+ 8035cb0:	af00      	add	r7, sp, #0
+ 8035cb2:	6078      	str	r0, [r7, #4]
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(heth);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+  the HAL_ETH_ErrorCallback could be implemented in the user file
+  */
+}
+ 8035cb4:	bf00      	nop
+ 8035cb6:	370c      	adds	r7, #12
+ 8035cb8:	46bd      	mov	sp, r7
+ 8035cba:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8035cbe:	4770      	bx	lr
+
+08035cc0 <HAL_ETH_PMTCallback>:
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None
+  */
+__weak void HAL_ETH_PMTCallback(ETH_HandleTypeDef *heth)
+{
+ 8035cc0:	b480      	push	{r7}
+ 8035cc2:	b083      	sub	sp, #12
+ 8035cc4:	af00      	add	r7, sp, #0
+ 8035cc6:	6078      	str	r0, [r7, #4]
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(heth);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+  the HAL_ETH_PMTCallback could be implemented in the user file
+  */
+}
+ 8035cc8:	bf00      	nop
+ 8035cca:	370c      	adds	r7, #12
+ 8035ccc:	46bd      	mov	sp, r7
+ 8035cce:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8035cd2:	4770      	bx	lr
+
+08035cd4 <HAL_ETH_EEECallback>:
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None
+  */
+__weak void HAL_ETH_EEECallback(ETH_HandleTypeDef *heth)
+{
+ 8035cd4:	b480      	push	{r7}
+ 8035cd6:	b083      	sub	sp, #12
+ 8035cd8:	af00      	add	r7, sp, #0
+ 8035cda:	6078      	str	r0, [r7, #4]
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(heth);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+  the HAL_ETH_EEECallback could be implemented in the user file
+  */
+}
+ 8035cdc:	bf00      	nop
+ 8035cde:	370c      	adds	r7, #12
+ 8035ce0:	46bd      	mov	sp, r7
+ 8035ce2:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8035ce6:	4770      	bx	lr
+
+08035ce8 <HAL_ETH_WakeUpCallback>:
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None
+  */
+__weak void HAL_ETH_WakeUpCallback(ETH_HandleTypeDef *heth)
+{
+ 8035ce8:	b480      	push	{r7}
+ 8035cea:	b083      	sub	sp, #12
+ 8035cec:	af00      	add	r7, sp, #0
+ 8035cee:	6078      	str	r0, [r7, #4]
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(heth);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_ETH_WakeUpCallback could be implemented in the user file
+   */
+}
+ 8035cf0:	bf00      	nop
+ 8035cf2:	370c      	adds	r7, #12
+ 8035cf4:	46bd      	mov	sp, r7
+ 8035cf6:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8035cfa:	4770      	bx	lr
+
+08035cfc <HAL_ETH_SetMDIOClockRange>:
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None
+  */
+void HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth)
+{
+ 8035cfc:	b580      	push	{r7, lr}
+ 8035cfe:	b084      	sub	sp, #16
+ 8035d00:	af00      	add	r7, sp, #0
+ 8035d02:	6078      	str	r0, [r7, #4]
+  uint32_t hclk;
+  uint32_t tmpreg;
+
+  /* Get the ETHERNET MACMDIOAR value */
+  tmpreg = (heth->Instance)->MACMDIOAR;
+ 8035d04:	687b      	ldr	r3, [r7, #4]
+ 8035d06:	681b      	ldr	r3, [r3, #0]
+ 8035d08:	f8d3 3200 	ldr.w	r3, [r3, #512]	@ 0x200
+ 8035d0c:	60fb      	str	r3, [r7, #12]
+
+  /* Clear CSR Clock Range bits */
+  tmpreg &= ~ETH_MACMDIOAR_CR;
+ 8035d0e:	68fb      	ldr	r3, [r7, #12]
+ 8035d10:	f423 6370 	bic.w	r3, r3, #3840	@ 0xf00
+ 8035d14:	60fb      	str	r3, [r7, #12]
+
+  /* Get hclk frequency value */
+  hclk = HAL_RCC_GetHCLKFreq();
+ 8035d16:	f004 f93d 	bl	8039f94 <HAL_RCC_GetHCLKFreq>
+ 8035d1a:	60b8      	str	r0, [r7, #8]
+
+  /* Set CR bits depending on hclk value */
+  if (hclk < 35000000U)
+ 8035d1c:	68bb      	ldr	r3, [r7, #8]
+ 8035d1e:	4a1a      	ldr	r2, [pc, #104]	@ (8035d88 <HAL_ETH_SetMDIOClockRange+0x8c>)
+ 8035d20:	4293      	cmp	r3, r2
+ 8035d22:	d804      	bhi.n	8035d2e <HAL_ETH_SetMDIOClockRange+0x32>
+  {
+    /* CSR Clock Range between 0-35 MHz */
+    tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV16;
+ 8035d24:	68fb      	ldr	r3, [r7, #12]
+ 8035d26:	f443 7300 	orr.w	r3, r3, #512	@ 0x200
+ 8035d2a:	60fb      	str	r3, [r7, #12]
+ 8035d2c:	e022      	b.n	8035d74 <HAL_ETH_SetMDIOClockRange+0x78>
+  }
+  else if (hclk < 60000000U)
+ 8035d2e:	68bb      	ldr	r3, [r7, #8]
+ 8035d30:	4a16      	ldr	r2, [pc, #88]	@ (8035d8c <HAL_ETH_SetMDIOClockRange+0x90>)
+ 8035d32:	4293      	cmp	r3, r2
+ 8035d34:	d204      	bcs.n	8035d40 <HAL_ETH_SetMDIOClockRange+0x44>
+  {
+    /* CSR Clock Range between 35-60 MHz */
+    tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV26;
+ 8035d36:	68fb      	ldr	r3, [r7, #12]
+ 8035d38:	f443 7340 	orr.w	r3, r3, #768	@ 0x300
+ 8035d3c:	60fb      	str	r3, [r7, #12]
+ 8035d3e:	e019      	b.n	8035d74 <HAL_ETH_SetMDIOClockRange+0x78>
+  }
+  else if (hclk < 100000000U)
+ 8035d40:	68bb      	ldr	r3, [r7, #8]
+ 8035d42:	4a13      	ldr	r2, [pc, #76]	@ (8035d90 <HAL_ETH_SetMDIOClockRange+0x94>)
+ 8035d44:	4293      	cmp	r3, r2
+ 8035d46:	d915      	bls.n	8035d74 <HAL_ETH_SetMDIOClockRange+0x78>
+  {
+    /* CSR Clock Range between 60-100 MHz */
+    tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV42;
+  }
+  else if (hclk < 150000000U)
+ 8035d48:	68bb      	ldr	r3, [r7, #8]
+ 8035d4a:	4a12      	ldr	r2, [pc, #72]	@ (8035d94 <HAL_ETH_SetMDIOClockRange+0x98>)
+ 8035d4c:	4293      	cmp	r3, r2
+ 8035d4e:	d804      	bhi.n	8035d5a <HAL_ETH_SetMDIOClockRange+0x5e>
+  {
+    /* CSR Clock Range between 100-150 MHz */
+    tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV62;
+ 8035d50:	68fb      	ldr	r3, [r7, #12]
+ 8035d52:	f443 7380 	orr.w	r3, r3, #256	@ 0x100
+ 8035d56:	60fb      	str	r3, [r7, #12]
+ 8035d58:	e00c      	b.n	8035d74 <HAL_ETH_SetMDIOClockRange+0x78>
+  }
+  else if (hclk < 250000000U)
+ 8035d5a:	68bb      	ldr	r3, [r7, #8]
+ 8035d5c:	4a0e      	ldr	r2, [pc, #56]	@ (8035d98 <HAL_ETH_SetMDIOClockRange+0x9c>)
+ 8035d5e:	4293      	cmp	r3, r2
+ 8035d60:	d804      	bhi.n	8035d6c <HAL_ETH_SetMDIOClockRange+0x70>
+  {
+    /* CSR Clock Range between 150-250 MHz */
+    tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV102;
+ 8035d62:	68fb      	ldr	r3, [r7, #12]
+ 8035d64:	f443 6380 	orr.w	r3, r3, #1024	@ 0x400
+ 8035d68:	60fb      	str	r3, [r7, #12]
+ 8035d6a:	e003      	b.n	8035d74 <HAL_ETH_SetMDIOClockRange+0x78>
+  }
+  else /* (hclk >= 250000000U) */
+  {
+    /* CSR Clock >= 250 MHz */
+    tmpreg |= (uint32_t)(ETH_MACMDIOAR_CR_DIV124);
+ 8035d6c:	68fb      	ldr	r3, [r7, #12]
+ 8035d6e:	f443 63a0 	orr.w	r3, r3, #1280	@ 0x500
+ 8035d72:	60fb      	str	r3, [r7, #12]
+  }
+
+  /* Configure the CSR Clock Range */
+  (heth->Instance)->MACMDIOAR = (uint32_t)tmpreg;
+ 8035d74:	687b      	ldr	r3, [r7, #4]
+ 8035d76:	681b      	ldr	r3, [r3, #0]
+ 8035d78:	68fa      	ldr	r2, [r7, #12]
+ 8035d7a:	f8c3 2200 	str.w	r2, [r3, #512]	@ 0x200
+}
+ 8035d7e:	bf00      	nop
+ 8035d80:	3710      	adds	r7, #16
+ 8035d82:	46bd      	mov	sp, r7
+ 8035d84:	bd80      	pop	{r7, pc}
+ 8035d86:	bf00      	nop
+ 8035d88:	02160ebf 	.word	0x02160ebf
+ 8035d8c:	03938700 	.word	0x03938700
+ 8035d90:	05f5e0ff 	.word	0x05f5e0ff
+ 8035d94:	08f0d17f 	.word	0x08f0d17f
+ 8035d98:	0ee6b27f 	.word	0x0ee6b27f
+
+08035d9c <ETH_SetMACConfig>:
+/** @addtogroup ETH_Private_Functions   ETH Private Functions
+  * @{
+  */
+
+static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, const ETH_MACConfigTypeDef *macconf)
+{
+ 8035d9c:	b480      	push	{r7}
+ 8035d9e:	b085      	sub	sp, #20
+ 8035da0:	af00      	add	r7, sp, #0
+ 8035da2:	6078      	str	r0, [r7, #4]
+ 8035da4:	6039      	str	r1, [r7, #0]
+  uint32_t macregval;
+
+  /*------------------------ MACCR Configuration --------------------*/
+  macregval = (macconf->InterPacketGapVal |
+ 8035da6:	683b      	ldr	r3, [r7, #0]
+ 8035da8:	689a      	ldr	r2, [r3, #8]
+               macconf->SourceAddrControl |
+ 8035daa:	683b      	ldr	r3, [r7, #0]
+ 8035dac:	681b      	ldr	r3, [r3, #0]
+  macregval = (macconf->InterPacketGapVal |
+ 8035dae:	431a      	orrs	r2, r3
+               ((uint32_t)macconf->ChecksumOffload << 27) |
+ 8035db0:	683b      	ldr	r3, [r7, #0]
+ 8035db2:	791b      	ldrb	r3, [r3, #4]
+ 8035db4:	06db      	lsls	r3, r3, #27
+               macconf->SourceAddrControl |
+ 8035db6:	431a      	orrs	r2, r3
+               ((uint32_t)macconf->GiantPacketSizeLimitControl << 23) |
+ 8035db8:	683b      	ldr	r3, [r7, #0]
+ 8035dba:	7b1b      	ldrb	r3, [r3, #12]
+ 8035dbc:	05db      	lsls	r3, r3, #23
+               ((uint32_t)macconf->ChecksumOffload << 27) |
+ 8035dbe:	431a      	orrs	r2, r3
+               ((uint32_t)macconf->Support2KPacket  << 22) |
+ 8035dc0:	683b      	ldr	r3, [r7, #0]
+ 8035dc2:	7b5b      	ldrb	r3, [r3, #13]
+ 8035dc4:	059b      	lsls	r3, r3, #22
+               ((uint32_t)macconf->GiantPacketSizeLimitControl << 23) |
+ 8035dc6:	431a      	orrs	r2, r3
+               ((uint32_t)macconf->CRCStripTypePacket << 21) |
+ 8035dc8:	683b      	ldr	r3, [r7, #0]
+ 8035dca:	7b9b      	ldrb	r3, [r3, #14]
+ 8035dcc:	055b      	lsls	r3, r3, #21
+               ((uint32_t)macconf->Support2KPacket  << 22) |
+ 8035dce:	431a      	orrs	r2, r3
+               ((uint32_t)macconf->AutomaticPadCRCStrip << 20) |
+ 8035dd0:	683b      	ldr	r3, [r7, #0]
+ 8035dd2:	7bdb      	ldrb	r3, [r3, #15]
+ 8035dd4:	051b      	lsls	r3, r3, #20
+               ((uint32_t)macconf->CRCStripTypePacket << 21) |
+ 8035dd6:	4313      	orrs	r3, r2
+               ((uint32_t)((macconf->Watchdog == DISABLE) ? 1U : 0U) << 19) |
+ 8035dd8:	683a      	ldr	r2, [r7, #0]
+ 8035dda:	7c12      	ldrb	r2, [r2, #16]
+ 8035ddc:	2a00      	cmp	r2, #0
+ 8035dde:	d102      	bne.n	8035de6 <ETH_SetMACConfig+0x4a>
+ 8035de0:	f44f 2200 	mov.w	r2, #524288	@ 0x80000
+ 8035de4:	e000      	b.n	8035de8 <ETH_SetMACConfig+0x4c>
+ 8035de6:	2200      	movs	r2, #0
+               ((uint32_t)macconf->AutomaticPadCRCStrip << 20) |
+ 8035de8:	4313      	orrs	r3, r2
+               ((uint32_t)((macconf->Jabber == DISABLE) ? 1U : 0U) << 17) |
+ 8035dea:	683a      	ldr	r2, [r7, #0]
+ 8035dec:	7c52      	ldrb	r2, [r2, #17]
+ 8035dee:	2a00      	cmp	r2, #0
+ 8035df0:	d102      	bne.n	8035df8 <ETH_SetMACConfig+0x5c>
+ 8035df2:	f44f 3200 	mov.w	r2, #131072	@ 0x20000
+ 8035df6:	e000      	b.n	8035dfa <ETH_SetMACConfig+0x5e>
+ 8035df8:	2200      	movs	r2, #0
+               ((uint32_t)((macconf->Watchdog == DISABLE) ? 1U : 0U) << 19) |
+ 8035dfa:	431a      	orrs	r2, r3
+               ((uint32_t)macconf->JumboPacket << 16) |
+ 8035dfc:	683b      	ldr	r3, [r7, #0]
+ 8035dfe:	7c9b      	ldrb	r3, [r3, #18]
+ 8035e00:	041b      	lsls	r3, r3, #16
+               ((uint32_t)((macconf->Jabber == DISABLE) ? 1U : 0U) << 17) |
+ 8035e02:	431a      	orrs	r2, r3
+               macconf->Speed |
+ 8035e04:	683b      	ldr	r3, [r7, #0]
+ 8035e06:	695b      	ldr	r3, [r3, #20]
+               ((uint32_t)macconf->JumboPacket << 16) |
+ 8035e08:	431a      	orrs	r2, r3
+               macconf->DuplexMode |
+ 8035e0a:	683b      	ldr	r3, [r7, #0]
+ 8035e0c:	699b      	ldr	r3, [r3, #24]
+               macconf->Speed |
+ 8035e0e:	431a      	orrs	r2, r3
+               ((uint32_t)macconf->LoopbackMode << 12) |
+ 8035e10:	683b      	ldr	r3, [r7, #0]
+ 8035e12:	7f1b      	ldrb	r3, [r3, #28]
+ 8035e14:	031b      	lsls	r3, r3, #12
+               macconf->DuplexMode |
+ 8035e16:	431a      	orrs	r2, r3
+               ((uint32_t)macconf->CarrierSenseBeforeTransmit << 11) |
+ 8035e18:	683b      	ldr	r3, [r7, #0]
+ 8035e1a:	7f5b      	ldrb	r3, [r3, #29]
+ 8035e1c:	02db      	lsls	r3, r3, #11
+               ((uint32_t)macconf->LoopbackMode << 12) |
+ 8035e1e:	4313      	orrs	r3, r2
+               ((uint32_t)((macconf->ReceiveOwn == DISABLE) ? 1U : 0U) << 10) |
+ 8035e20:	683a      	ldr	r2, [r7, #0]
+ 8035e22:	7f92      	ldrb	r2, [r2, #30]
+ 8035e24:	2a00      	cmp	r2, #0
+ 8035e26:	d102      	bne.n	8035e2e <ETH_SetMACConfig+0x92>
+ 8035e28:	f44f 6280 	mov.w	r2, #1024	@ 0x400
+ 8035e2c:	e000      	b.n	8035e30 <ETH_SetMACConfig+0x94>
+ 8035e2e:	2200      	movs	r2, #0
+               ((uint32_t)macconf->CarrierSenseBeforeTransmit << 11) |
+ 8035e30:	431a      	orrs	r2, r3
+               ((uint32_t)macconf->CarrierSenseDuringTransmit << 9) |
+ 8035e32:	683b      	ldr	r3, [r7, #0]
+ 8035e34:	7fdb      	ldrb	r3, [r3, #31]
+ 8035e36:	025b      	lsls	r3, r3, #9
+               ((uint32_t)((macconf->ReceiveOwn == DISABLE) ? 1U : 0U) << 10) |
+ 8035e38:	4313      	orrs	r3, r2
+               ((uint32_t)((macconf->RetryTransmission == DISABLE) ? 1U : 0U) << 8) |
+ 8035e3a:	683a      	ldr	r2, [r7, #0]
+ 8035e3c:	f892 2020 	ldrb.w	r2, [r2, #32]
+ 8035e40:	2a00      	cmp	r2, #0
+ 8035e42:	d102      	bne.n	8035e4a <ETH_SetMACConfig+0xae>
+ 8035e44:	f44f 7280 	mov.w	r2, #256	@ 0x100
+ 8035e48:	e000      	b.n	8035e4c <ETH_SetMACConfig+0xb0>
+ 8035e4a:	2200      	movs	r2, #0
+               ((uint32_t)macconf->CarrierSenseDuringTransmit << 9) |
+ 8035e4c:	431a      	orrs	r2, r3
+               macconf->BackOffLimit |
+ 8035e4e:	683b      	ldr	r3, [r7, #0]
+ 8035e50:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+               ((uint32_t)((macconf->RetryTransmission == DISABLE) ? 1U : 0U) << 8) |
+ 8035e52:	431a      	orrs	r2, r3
+               ((uint32_t)macconf->DeferralCheck << 4) |
+ 8035e54:	683b      	ldr	r3, [r7, #0]
+ 8035e56:	f893 3028 	ldrb.w	r3, [r3, #40]	@ 0x28
+ 8035e5a:	011b      	lsls	r3, r3, #4
+               macconf->BackOffLimit |
+ 8035e5c:	431a      	orrs	r2, r3
+               macconf->PreambleLength);
+ 8035e5e:	683b      	ldr	r3, [r7, #0]
+ 8035e60:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+  macregval = (macconf->InterPacketGapVal |
+ 8035e62:	4313      	orrs	r3, r2
+ 8035e64:	60fb      	str	r3, [r7, #12]
+
+  /* Write to MACCR */
+  MODIFY_REG(heth->Instance->MACCR, ETH_MACCR_MASK, macregval);
+ 8035e66:	687b      	ldr	r3, [r7, #4]
+ 8035e68:	681b      	ldr	r3, [r3, #0]
+ 8035e6a:	681a      	ldr	r2, [r3, #0]
+ 8035e6c:	4b56      	ldr	r3, [pc, #344]	@ (8035fc8 <ETH_SetMACConfig+0x22c>)
+ 8035e6e:	4013      	ands	r3, r2
+ 8035e70:	687a      	ldr	r2, [r7, #4]
+ 8035e72:	6812      	ldr	r2, [r2, #0]
+ 8035e74:	68f9      	ldr	r1, [r7, #12]
+ 8035e76:	430b      	orrs	r3, r1
+ 8035e78:	6013      	str	r3, [r2, #0]
+
+  /*------------------------ MACECR Configuration --------------------*/
+  macregval = ((macconf->ExtendedInterPacketGapVal << 25) |
+ 8035e7a:	683b      	ldr	r3, [r7, #0]
+ 8035e7c:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 8035e7e:	065a      	lsls	r2, r3, #25
+               ((uint32_t)macconf->ExtendedInterPacketGap << 24) |
+ 8035e80:	683b      	ldr	r3, [r7, #0]
+ 8035e82:	f893 3038 	ldrb.w	r3, [r3, #56]	@ 0x38
+ 8035e86:	061b      	lsls	r3, r3, #24
+  macregval = ((macconf->ExtendedInterPacketGapVal << 25) |
+ 8035e88:	431a      	orrs	r2, r3
+               ((uint32_t)macconf->UnicastSlowProtocolPacketDetect << 18) |
+ 8035e8a:	683b      	ldr	r3, [r7, #0]
+ 8035e8c:	f893 3030 	ldrb.w	r3, [r3, #48]	@ 0x30
+ 8035e90:	049b      	lsls	r3, r3, #18
+               ((uint32_t)macconf->ExtendedInterPacketGap << 24) |
+ 8035e92:	431a      	orrs	r2, r3
+               ((uint32_t)macconf->SlowProtocolDetect << 17) |
+ 8035e94:	683b      	ldr	r3, [r7, #0]
+ 8035e96:	f893 3031 	ldrb.w	r3, [r3, #49]	@ 0x31
+ 8035e9a:	045b      	lsls	r3, r3, #17
+               ((uint32_t)macconf->UnicastSlowProtocolPacketDetect << 18) |
+ 8035e9c:	4313      	orrs	r3, r2
+               ((uint32_t)((macconf->CRCCheckingRxPackets == DISABLE) ? 1U : 0U) << 16) |
+ 8035e9e:	683a      	ldr	r2, [r7, #0]
+ 8035ea0:	f892 2032 	ldrb.w	r2, [r2, #50]	@ 0x32
+ 8035ea4:	2a00      	cmp	r2, #0
+ 8035ea6:	d102      	bne.n	8035eae <ETH_SetMACConfig+0x112>
+ 8035ea8:	f44f 3280 	mov.w	r2, #65536	@ 0x10000
+ 8035eac:	e000      	b.n	8035eb0 <ETH_SetMACConfig+0x114>
+ 8035eae:	2200      	movs	r2, #0
+               ((uint32_t)macconf->SlowProtocolDetect << 17) |
+ 8035eb0:	431a      	orrs	r2, r3
+               macconf->GiantPacketSizeLimit);
+ 8035eb2:	683b      	ldr	r3, [r7, #0]
+ 8035eb4:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
+  macregval = ((macconf->ExtendedInterPacketGapVal << 25) |
+ 8035eb6:	4313      	orrs	r3, r2
+ 8035eb8:	60fb      	str	r3, [r7, #12]
+
+  /* Write to MACECR */
+  MODIFY_REG(heth->Instance->MACECR, ETH_MACECR_MASK, macregval);
+ 8035eba:	687b      	ldr	r3, [r7, #4]
+ 8035ebc:	681b      	ldr	r3, [r3, #0]
+ 8035ebe:	685a      	ldr	r2, [r3, #4]
+ 8035ec0:	4b42      	ldr	r3, [pc, #264]	@ (8035fcc <ETH_SetMACConfig+0x230>)
+ 8035ec2:	4013      	ands	r3, r2
+ 8035ec4:	687a      	ldr	r2, [r7, #4]
+ 8035ec6:	6812      	ldr	r2, [r2, #0]
+ 8035ec8:	68f9      	ldr	r1, [r7, #12]
+ 8035eca:	430b      	orrs	r3, r1
+ 8035ecc:	6053      	str	r3, [r2, #4]
+
+  /*------------------------ MACWTR Configuration --------------------*/
+  macregval = (((uint32_t)macconf->ProgrammableWatchdog << 8) |
+ 8035ece:	683b      	ldr	r3, [r7, #0]
+ 8035ed0:	f893 3040 	ldrb.w	r3, [r3, #64]	@ 0x40
+ 8035ed4:	021a      	lsls	r2, r3, #8
+               macconf->WatchdogTimeout);
+ 8035ed6:	683b      	ldr	r3, [r7, #0]
+ 8035ed8:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
+  macregval = (((uint32_t)macconf->ProgrammableWatchdog << 8) |
+ 8035eda:	4313      	orrs	r3, r2
+ 8035edc:	60fb      	str	r3, [r7, #12]
+
+  /* Write to MACWTR */
+  MODIFY_REG(heth->Instance->MACWTR, ETH_MACWTR_MASK, macregval);
+ 8035ede:	687b      	ldr	r3, [r7, #4]
+ 8035ee0:	681b      	ldr	r3, [r3, #0]
+ 8035ee2:	68da      	ldr	r2, [r3, #12]
+ 8035ee4:	4b3a      	ldr	r3, [pc, #232]	@ (8035fd0 <ETH_SetMACConfig+0x234>)
+ 8035ee6:	4013      	ands	r3, r2
+ 8035ee8:	687a      	ldr	r2, [r7, #4]
+ 8035eea:	6812      	ldr	r2, [r2, #0]
+ 8035eec:	68f9      	ldr	r1, [r7, #12]
+ 8035eee:	430b      	orrs	r3, r1
+ 8035ef0:	60d3      	str	r3, [r2, #12]
+
+  /*------------------------ MACTFCR Configuration --------------------*/
+  macregval = (((uint32_t)macconf->TransmitFlowControl << 1) |
+ 8035ef2:	683b      	ldr	r3, [r7, #0]
+ 8035ef4:	f893 3054 	ldrb.w	r3, [r3, #84]	@ 0x54
+ 8035ef8:	005a      	lsls	r2, r3, #1
+               macconf->PauseLowThreshold |
+ 8035efa:	683b      	ldr	r3, [r7, #0]
+ 8035efc:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
+  macregval = (((uint32_t)macconf->TransmitFlowControl << 1) |
+ 8035efe:	4313      	orrs	r3, r2
+               ((uint32_t)((macconf->ZeroQuantaPause == DISABLE) ? 1U : 0U) << 7) |
+ 8035f00:	683a      	ldr	r2, [r7, #0]
+ 8035f02:	f892 204c 	ldrb.w	r2, [r2, #76]	@ 0x4c
+ 8035f06:	2a00      	cmp	r2, #0
+ 8035f08:	d101      	bne.n	8035f0e <ETH_SetMACConfig+0x172>
+ 8035f0a:	2280      	movs	r2, #128	@ 0x80
+ 8035f0c:	e000      	b.n	8035f10 <ETH_SetMACConfig+0x174>
+ 8035f0e:	2200      	movs	r2, #0
+               macconf->PauseLowThreshold |
+ 8035f10:	431a      	orrs	r2, r3
+               (macconf->PauseTime << 16));
+ 8035f12:	683b      	ldr	r3, [r7, #0]
+ 8035f14:	6c9b      	ldr	r3, [r3, #72]	@ 0x48
+ 8035f16:	041b      	lsls	r3, r3, #16
+  macregval = (((uint32_t)macconf->TransmitFlowControl << 1) |
+ 8035f18:	4313      	orrs	r3, r2
+ 8035f1a:	60fb      	str	r3, [r7, #12]
+
+  /* Write to MACTFCR */
+  MODIFY_REG(heth->Instance->MACTFCR, ETH_MACTFCR_MASK, macregval);
+ 8035f1c:	687b      	ldr	r3, [r7, #4]
+ 8035f1e:	681b      	ldr	r3, [r3, #0]
+ 8035f20:	6f1a      	ldr	r2, [r3, #112]	@ 0x70
+ 8035f22:	f64f 730d 	movw	r3, #65293	@ 0xff0d
+ 8035f26:	4013      	ands	r3, r2
+ 8035f28:	687a      	ldr	r2, [r7, #4]
+ 8035f2a:	6812      	ldr	r2, [r2, #0]
+ 8035f2c:	68f9      	ldr	r1, [r7, #12]
+ 8035f2e:	430b      	orrs	r3, r1
+ 8035f30:	6713      	str	r3, [r2, #112]	@ 0x70
+
+  /*------------------------ MACRFCR Configuration --------------------*/
+  macregval = ((uint32_t)macconf->ReceiveFlowControl |
+ 8035f32:	683b      	ldr	r3, [r7, #0]
+ 8035f34:	f893 3056 	ldrb.w	r3, [r3, #86]	@ 0x56
+ 8035f38:	461a      	mov	r2, r3
+               ((uint32_t)macconf->UnicastPausePacketDetect << 1));
+ 8035f3a:	683b      	ldr	r3, [r7, #0]
+ 8035f3c:	f893 3055 	ldrb.w	r3, [r3, #85]	@ 0x55
+ 8035f40:	005b      	lsls	r3, r3, #1
+  macregval = ((uint32_t)macconf->ReceiveFlowControl |
+ 8035f42:	4313      	orrs	r3, r2
+ 8035f44:	60fb      	str	r3, [r7, #12]
+
+  /* Write to MACRFCR */
+  MODIFY_REG(heth->Instance->MACRFCR, ETH_MACRFCR_MASK, macregval);
+ 8035f46:	687b      	ldr	r3, [r7, #4]
+ 8035f48:	681b      	ldr	r3, [r3, #0]
+ 8035f4a:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
+ 8035f4e:	f023 0103 	bic.w	r1, r3, #3
+ 8035f52:	687b      	ldr	r3, [r7, #4]
+ 8035f54:	681b      	ldr	r3, [r3, #0]
+ 8035f56:	68fa      	ldr	r2, [r7, #12]
+ 8035f58:	430a      	orrs	r2, r1
+ 8035f5a:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90
+
+  /*------------------------ MTLTQOMR Configuration --------------------*/
+  /* Write to MTLTQOMR */
+  MODIFY_REG(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_MASK, macconf->TransmitQueueMode);
+ 8035f5e:	687b      	ldr	r3, [r7, #4]
+ 8035f60:	681b      	ldr	r3, [r3, #0]
+ 8035f62:	f8d3 3d00 	ldr.w	r3, [r3, #3328]	@ 0xd00
+ 8035f66:	f023 0172 	bic.w	r1, r3, #114	@ 0x72
+ 8035f6a:	683b      	ldr	r3, [r7, #0]
+ 8035f6c:	6d9a      	ldr	r2, [r3, #88]	@ 0x58
+ 8035f6e:	687b      	ldr	r3, [r7, #4]
+ 8035f70:	681b      	ldr	r3, [r3, #0]
+ 8035f72:	430a      	orrs	r2, r1
+ 8035f74:	f8c3 2d00 	str.w	r2, [r3, #3328]	@ 0xd00
+
+  /*------------------------ MTLRQOMR Configuration --------------------*/
+  macregval = (macconf->ReceiveQueueMode |
+ 8035f78:	683b      	ldr	r3, [r7, #0]
+ 8035f7a:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
+               ((uint32_t)((macconf->DropTCPIPChecksumErrorPacket == DISABLE) ? 1U : 0U) << 6) |
+ 8035f7c:	683a      	ldr	r2, [r7, #0]
+ 8035f7e:	f892 2060 	ldrb.w	r2, [r2, #96]	@ 0x60
+ 8035f82:	2a00      	cmp	r2, #0
+ 8035f84:	d101      	bne.n	8035f8a <ETH_SetMACConfig+0x1ee>
+ 8035f86:	2240      	movs	r2, #64	@ 0x40
+ 8035f88:	e000      	b.n	8035f8c <ETH_SetMACConfig+0x1f0>
+ 8035f8a:	2200      	movs	r2, #0
+  macregval = (macconf->ReceiveQueueMode |
+ 8035f8c:	431a      	orrs	r2, r3
+               ((uint32_t)macconf->ForwardRxErrorPacket << 4) |
+ 8035f8e:	683b      	ldr	r3, [r7, #0]
+ 8035f90:	f893 3061 	ldrb.w	r3, [r3, #97]	@ 0x61
+ 8035f94:	011b      	lsls	r3, r3, #4
+               ((uint32_t)((macconf->DropTCPIPChecksumErrorPacket == DISABLE) ? 1U : 0U) << 6) |
+ 8035f96:	431a      	orrs	r2, r3
+               ((uint32_t)macconf->ForwardRxUndersizedGoodPacket << 3));
+ 8035f98:	683b      	ldr	r3, [r7, #0]
+ 8035f9a:	f893 3062 	ldrb.w	r3, [r3, #98]	@ 0x62
+ 8035f9e:	00db      	lsls	r3, r3, #3
+  macregval = (macconf->ReceiveQueueMode |
+ 8035fa0:	4313      	orrs	r3, r2
+ 8035fa2:	60fb      	str	r3, [r7, #12]
+
+  /* Write to MTLRQOMR */
+  MODIFY_REG(heth->Instance->MTLRQOMR, ETH_MTLRQOMR_MASK, macregval);
+ 8035fa4:	687b      	ldr	r3, [r7, #4]
+ 8035fa6:	681b      	ldr	r3, [r3, #0]
+ 8035fa8:	f8d3 3d30 	ldr.w	r3, [r3, #3376]	@ 0xd30
+ 8035fac:	f023 017b 	bic.w	r1, r3, #123	@ 0x7b
+ 8035fb0:	687b      	ldr	r3, [r7, #4]
+ 8035fb2:	681b      	ldr	r3, [r3, #0]
+ 8035fb4:	68fa      	ldr	r2, [r7, #12]
+ 8035fb6:	430a      	orrs	r2, r1
+ 8035fb8:	f8c3 2d30 	str.w	r2, [r3, #3376]	@ 0xd30
+}
+ 8035fbc:	bf00      	nop
+ 8035fbe:	3714      	adds	r7, #20
+ 8035fc0:	46bd      	mov	sp, r7
+ 8035fc2:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8035fc6:	4770      	bx	lr
+ 8035fc8:	00048083 	.word	0x00048083
+ 8035fcc:	c0f88000 	.word	0xc0f88000
+ 8035fd0:	fffffef0 	.word	0xfffffef0
+
+08035fd4 <ETH_SetDMAConfig>:
+
+static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, const ETH_DMAConfigTypeDef *dmaconf)
+{
+ 8035fd4:	b480      	push	{r7}
+ 8035fd6:	b085      	sub	sp, #20
+ 8035fd8:	af00      	add	r7, sp, #0
+ 8035fda:	6078      	str	r0, [r7, #4]
+ 8035fdc:	6039      	str	r1, [r7, #0]
+  uint32_t dmaregval;
+
+  /*------------------------ DMAMR Configuration --------------------*/
+  MODIFY_REG(heth->Instance->DMAMR, ETH_DMAMR_MASK, dmaconf->DMAArbitration);
+ 8035fde:	687b      	ldr	r3, [r7, #4]
+ 8035fe0:	681b      	ldr	r3, [r3, #0]
+ 8035fe2:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8035fe6:	681a      	ldr	r2, [r3, #0]
+ 8035fe8:	4b38      	ldr	r3, [pc, #224]	@ (80360cc <ETH_SetDMAConfig+0xf8>)
+ 8035fea:	4013      	ands	r3, r2
+ 8035fec:	683a      	ldr	r2, [r7, #0]
+ 8035fee:	6811      	ldr	r1, [r2, #0]
+ 8035ff0:	687a      	ldr	r2, [r7, #4]
+ 8035ff2:	6812      	ldr	r2, [r2, #0]
+ 8035ff4:	430b      	orrs	r3, r1
+ 8035ff6:	f502 5280 	add.w	r2, r2, #4096	@ 0x1000
+ 8035ffa:	6013      	str	r3, [r2, #0]
+
+  /*------------------------ DMASBMR Configuration --------------------*/
+  dmaregval = (((uint32_t)dmaconf->AddressAlignedBeats << 12) |
+ 8035ffc:	683b      	ldr	r3, [r7, #0]
+ 8035ffe:	791b      	ldrb	r3, [r3, #4]
+ 8036000:	031a      	lsls	r2, r3, #12
+               dmaconf->BurstMode |
+ 8036002:	683b      	ldr	r3, [r7, #0]
+ 8036004:	689b      	ldr	r3, [r3, #8]
+  dmaregval = (((uint32_t)dmaconf->AddressAlignedBeats << 12) |
+ 8036006:	431a      	orrs	r2, r3
+               ((uint32_t)dmaconf->RebuildINCRxBurst << 15));
+ 8036008:	683b      	ldr	r3, [r7, #0]
+ 803600a:	7b1b      	ldrb	r3, [r3, #12]
+ 803600c:	03db      	lsls	r3, r3, #15
+  dmaregval = (((uint32_t)dmaconf->AddressAlignedBeats << 12) |
+ 803600e:	4313      	orrs	r3, r2
+ 8036010:	60fb      	str	r3, [r7, #12]
+
+  MODIFY_REG(heth->Instance->DMASBMR, ETH_DMASBMR_MASK, dmaregval);
+ 8036012:	687b      	ldr	r3, [r7, #4]
+ 8036014:	681b      	ldr	r3, [r3, #0]
+ 8036016:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 803601a:	685a      	ldr	r2, [r3, #4]
+ 803601c:	4b2c      	ldr	r3, [pc, #176]	@ (80360d0 <ETH_SetDMAConfig+0xfc>)
+ 803601e:	4013      	ands	r3, r2
+ 8036020:	687a      	ldr	r2, [r7, #4]
+ 8036022:	6812      	ldr	r2, [r2, #0]
+ 8036024:	68f9      	ldr	r1, [r7, #12]
+ 8036026:	430b      	orrs	r3, r1
+ 8036028:	f502 5280 	add.w	r2, r2, #4096	@ 0x1000
+ 803602c:	6053      	str	r3, [r2, #4]
+
+  /*------------------------ DMACCR Configuration --------------------*/
+  dmaregval = (((uint32_t)dmaconf->PBLx8Mode << 16) |
+ 803602e:	683b      	ldr	r3, [r7, #0]
+ 8036030:	7b5b      	ldrb	r3, [r3, #13]
+ 8036032:	041a      	lsls	r2, r3, #16
+               dmaconf->MaximumSegmentSize);
+ 8036034:	683b      	ldr	r3, [r7, #0]
+ 8036036:	6a1b      	ldr	r3, [r3, #32]
+  dmaregval = (((uint32_t)dmaconf->PBLx8Mode << 16) |
+ 8036038:	4313      	orrs	r3, r2
+ 803603a:	60fb      	str	r3, [r7, #12]
+  MODIFY_REG(heth->Instance->DMACCR, ETH_DMACCR_MASK, dmaregval);
+ 803603c:	687b      	ldr	r3, [r7, #4]
+ 803603e:	681b      	ldr	r3, [r3, #0]
+ 8036040:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8036044:	f8d3 2100 	ldr.w	r2, [r3, #256]	@ 0x100
+ 8036048:	4b22      	ldr	r3, [pc, #136]	@ (80360d4 <ETH_SetDMAConfig+0x100>)
+ 803604a:	4013      	ands	r3, r2
+ 803604c:	687a      	ldr	r2, [r7, #4]
+ 803604e:	6812      	ldr	r2, [r2, #0]
+ 8036050:	68f9      	ldr	r1, [r7, #12]
+ 8036052:	430b      	orrs	r3, r1
+ 8036054:	f502 5280 	add.w	r2, r2, #4096	@ 0x1000
+ 8036058:	f8c2 3100 	str.w	r3, [r2, #256]	@ 0x100
+
+  /*------------------------ DMACTCR Configuration --------------------*/
+  dmaregval = (dmaconf->TxDMABurstLength |
+ 803605c:	683b      	ldr	r3, [r7, #0]
+ 803605e:	691a      	ldr	r2, [r3, #16]
+               ((uint32_t)dmaconf->SecondPacketOperate << 4) |
+ 8036060:	683b      	ldr	r3, [r7, #0]
+ 8036062:	7d1b      	ldrb	r3, [r3, #20]
+ 8036064:	011b      	lsls	r3, r3, #4
+  dmaregval = (dmaconf->TxDMABurstLength |
+ 8036066:	431a      	orrs	r2, r3
+               ((uint32_t)dmaconf->TCPSegmentation << 12));
+ 8036068:	683b      	ldr	r3, [r7, #0]
+ 803606a:	7f5b      	ldrb	r3, [r3, #29]
+ 803606c:	031b      	lsls	r3, r3, #12
+  dmaregval = (dmaconf->TxDMABurstLength |
+ 803606e:	4313      	orrs	r3, r2
+ 8036070:	60fb      	str	r3, [r7, #12]
+
+  MODIFY_REG(heth->Instance->DMACTCR, ETH_DMACTCR_MASK, dmaregval);
+ 8036072:	687b      	ldr	r3, [r7, #4]
+ 8036074:	681b      	ldr	r3, [r3, #0]
+ 8036076:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 803607a:	f8d3 2104 	ldr.w	r2, [r3, #260]	@ 0x104
+ 803607e:	4b16      	ldr	r3, [pc, #88]	@ (80360d8 <ETH_SetDMAConfig+0x104>)
+ 8036080:	4013      	ands	r3, r2
+ 8036082:	687a      	ldr	r2, [r7, #4]
+ 8036084:	6812      	ldr	r2, [r2, #0]
+ 8036086:	68f9      	ldr	r1, [r7, #12]
+ 8036088:	430b      	orrs	r3, r1
+ 803608a:	f502 5280 	add.w	r2, r2, #4096	@ 0x1000
+ 803608e:	f8c2 3104 	str.w	r3, [r2, #260]	@ 0x104
+
+  /*------------------------ DMACRCR Configuration --------------------*/
+  dmaregval = (((uint32_t)dmaconf->FlushRxPacket  << 31) |
+ 8036092:	683b      	ldr	r3, [r7, #0]
+ 8036094:	7f1b      	ldrb	r3, [r3, #28]
+ 8036096:	07da      	lsls	r2, r3, #31
+               dmaconf->RxDMABurstLength);
+ 8036098:	683b      	ldr	r3, [r7, #0]
+ 803609a:	699b      	ldr	r3, [r3, #24]
+  dmaregval = (((uint32_t)dmaconf->FlushRxPacket  << 31) |
+ 803609c:	4313      	orrs	r3, r2
+ 803609e:	60fb      	str	r3, [r7, #12]
+
+  /* Write to DMACRCR */
+  MODIFY_REG(heth->Instance->DMACRCR, ETH_DMACRCR_MASK, dmaregval);
+ 80360a0:	687b      	ldr	r3, [r7, #4]
+ 80360a2:	681b      	ldr	r3, [r3, #0]
+ 80360a4:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 80360a8:	f8d3 2108 	ldr.w	r2, [r3, #264]	@ 0x108
+ 80360ac:	4b0b      	ldr	r3, [pc, #44]	@ (80360dc <ETH_SetDMAConfig+0x108>)
+ 80360ae:	4013      	ands	r3, r2
+ 80360b0:	687a      	ldr	r2, [r7, #4]
+ 80360b2:	6812      	ldr	r2, [r2, #0]
+ 80360b4:	68f9      	ldr	r1, [r7, #12]
+ 80360b6:	430b      	orrs	r3, r1
+ 80360b8:	f502 5280 	add.w	r2, r2, #4096	@ 0x1000
+ 80360bc:	f8c2 3108 	str.w	r3, [r2, #264]	@ 0x108
+}
+ 80360c0:	bf00      	nop
+ 80360c2:	3714      	adds	r7, #20
+ 80360c4:	46bd      	mov	sp, r7
+ 80360c6:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80360ca:	4770      	bx	lr
+ 80360cc:	ffff87fd 	.word	0xffff87fd
+ 80360d0:	ffff2ffe 	.word	0xffff2ffe
+ 80360d4:	fffec000 	.word	0xfffec000
+ 80360d8:	ffc0efef 	.word	0xffc0efef
+ 80360dc:	7fc0ffff 	.word	0x7fc0ffff
+
+080360e0 <ETH_MACDMAConfig>:
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval HAL status
+  */
+static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth)
+{
+ 80360e0:	b580      	push	{r7, lr}
+ 80360e2:	b0a4      	sub	sp, #144	@ 0x90
+ 80360e4:	af00      	add	r7, sp, #0
+ 80360e6:	6078      	str	r0, [r7, #4]
+  ETH_MACConfigTypeDef macDefaultConf;
+  ETH_DMAConfigTypeDef dmaDefaultConf;
+
+  /*--------------- ETHERNET MAC registers default Configuration --------------*/
+  macDefaultConf.AutomaticPadCRCStrip = ENABLE;
+ 80360e8:	2301      	movs	r3, #1
+ 80360ea:	f887 303b 	strb.w	r3, [r7, #59]	@ 0x3b
+  macDefaultConf.BackOffLimit = ETH_BACKOFFLIMIT_10;
+ 80360ee:	2300      	movs	r3, #0
+ 80360f0:	653b      	str	r3, [r7, #80]	@ 0x50
+  macDefaultConf.CarrierSenseBeforeTransmit = DISABLE;
+ 80360f2:	2300      	movs	r3, #0
+ 80360f4:	f887 3049 	strb.w	r3, [r7, #73]	@ 0x49
+  macDefaultConf.CarrierSenseDuringTransmit = DISABLE;
+ 80360f8:	2300      	movs	r3, #0
+ 80360fa:	f887 304b 	strb.w	r3, [r7, #75]	@ 0x4b
+  macDefaultConf.ChecksumOffload = ENABLE;
+ 80360fe:	2301      	movs	r3, #1
+ 8036100:	f887 3030 	strb.w	r3, [r7, #48]	@ 0x30
+  macDefaultConf.CRCCheckingRxPackets = ENABLE;
+ 8036104:	2301      	movs	r3, #1
+ 8036106:	f887 305e 	strb.w	r3, [r7, #94]	@ 0x5e
+  macDefaultConf.CRCStripTypePacket = ENABLE;
+ 803610a:	2301      	movs	r3, #1
+ 803610c:	f887 303a 	strb.w	r3, [r7, #58]	@ 0x3a
+  macDefaultConf.DeferralCheck = DISABLE;
+ 8036110:	2300      	movs	r3, #0
+ 8036112:	f887 3054 	strb.w	r3, [r7, #84]	@ 0x54
+  macDefaultConf.DropTCPIPChecksumErrorPacket = ENABLE;
+ 8036116:	2301      	movs	r3, #1
+ 8036118:	f887 308c 	strb.w	r3, [r7, #140]	@ 0x8c
+  macDefaultConf.DuplexMode = ETH_FULLDUPLEX_MODE;
+ 803611c:	f44f 5300 	mov.w	r3, #8192	@ 0x2000
+ 8036120:	647b      	str	r3, [r7, #68]	@ 0x44
+  macDefaultConf.ExtendedInterPacketGap = DISABLE;
+ 8036122:	2300      	movs	r3, #0
+ 8036124:	f887 3064 	strb.w	r3, [r7, #100]	@ 0x64
+  macDefaultConf.ExtendedInterPacketGapVal = 0x0U;
+ 8036128:	2300      	movs	r3, #0
+ 803612a:	66bb      	str	r3, [r7, #104]	@ 0x68
+  macDefaultConf.ForwardRxErrorPacket = DISABLE;
+ 803612c:	2300      	movs	r3, #0
+ 803612e:	f887 308d 	strb.w	r3, [r7, #141]	@ 0x8d
+  macDefaultConf.ForwardRxUndersizedGoodPacket = DISABLE;
+ 8036132:	2300      	movs	r3, #0
+ 8036134:	f887 308e 	strb.w	r3, [r7, #142]	@ 0x8e
+  macDefaultConf.GiantPacketSizeLimit = 0x618U;
+ 8036138:	f44f 63c3 	mov.w	r3, #1560	@ 0x618
+ 803613c:	663b      	str	r3, [r7, #96]	@ 0x60
+  macDefaultConf.GiantPacketSizeLimitControl = DISABLE;
+ 803613e:	2300      	movs	r3, #0
+ 8036140:	f887 3038 	strb.w	r3, [r7, #56]	@ 0x38
+  macDefaultConf.InterPacketGapVal = ETH_INTERPACKETGAP_96BIT;
+ 8036144:	2300      	movs	r3, #0
+ 8036146:	637b      	str	r3, [r7, #52]	@ 0x34
+  macDefaultConf.Jabber = ENABLE;
+ 8036148:	2301      	movs	r3, #1
+ 803614a:	f887 303d 	strb.w	r3, [r7, #61]	@ 0x3d
+  macDefaultConf.JumboPacket = DISABLE;
+ 803614e:	2300      	movs	r3, #0
+ 8036150:	f887 303e 	strb.w	r3, [r7, #62]	@ 0x3e
+  macDefaultConf.LoopbackMode = DISABLE;
+ 8036154:	2300      	movs	r3, #0
+ 8036156:	f887 3048 	strb.w	r3, [r7, #72]	@ 0x48
+  macDefaultConf.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS_4;
+ 803615a:	2300      	movs	r3, #0
+ 803615c:	67fb      	str	r3, [r7, #124]	@ 0x7c
+  macDefaultConf.PauseTime = 0x0U;
+ 803615e:	2300      	movs	r3, #0
+ 8036160:	677b      	str	r3, [r7, #116]	@ 0x74
+  macDefaultConf.PreambleLength = ETH_PREAMBLELENGTH_7;
+ 8036162:	2300      	movs	r3, #0
+ 8036164:	65bb      	str	r3, [r7, #88]	@ 0x58
+  macDefaultConf.ProgrammableWatchdog = DISABLE;
+ 8036166:	2300      	movs	r3, #0
+ 8036168:	f887 306c 	strb.w	r3, [r7, #108]	@ 0x6c
+  macDefaultConf.ReceiveFlowControl = DISABLE;
+ 803616c:	2300      	movs	r3, #0
+ 803616e:	f887 3082 	strb.w	r3, [r7, #130]	@ 0x82
+  macDefaultConf.ReceiveOwn = ENABLE;
+ 8036172:	2301      	movs	r3, #1
+ 8036174:	f887 304a 	strb.w	r3, [r7, #74]	@ 0x4a
+  macDefaultConf.ReceiveQueueMode = ETH_RECEIVESTOREFORWARD;
+ 8036178:	2320      	movs	r3, #32
+ 803617a:	f8c7 3088 	str.w	r3, [r7, #136]	@ 0x88
+  macDefaultConf.RetryTransmission = ENABLE;
+ 803617e:	2301      	movs	r3, #1
+ 8036180:	f887 304c 	strb.w	r3, [r7, #76]	@ 0x4c
+  macDefaultConf.SlowProtocolDetect = DISABLE;
+ 8036184:	2300      	movs	r3, #0
+ 8036186:	f887 305d 	strb.w	r3, [r7, #93]	@ 0x5d
+  macDefaultConf.SourceAddrControl = ETH_SOURCEADDRESS_REPLACE_ADDR0;
+ 803618a:	f04f 5340 	mov.w	r3, #805306368	@ 0x30000000
+ 803618e:	62fb      	str	r3, [r7, #44]	@ 0x2c
+  macDefaultConf.Speed = ETH_SPEED_100M;
+ 8036190:	f44f 4380 	mov.w	r3, #16384	@ 0x4000
+ 8036194:	643b      	str	r3, [r7, #64]	@ 0x40
+  macDefaultConf.Support2KPacket = DISABLE;
+ 8036196:	2300      	movs	r3, #0
+ 8036198:	f887 3039 	strb.w	r3, [r7, #57]	@ 0x39
+  macDefaultConf.TransmitQueueMode = ETH_TRANSMITSTOREFORWARD;
+ 803619c:	2302      	movs	r3, #2
+ 803619e:	f8c7 3084 	str.w	r3, [r7, #132]	@ 0x84
+  macDefaultConf.TransmitFlowControl = DISABLE;
+ 80361a2:	2300      	movs	r3, #0
+ 80361a4:	f887 3080 	strb.w	r3, [r7, #128]	@ 0x80
+  macDefaultConf.UnicastPausePacketDetect = DISABLE;
+ 80361a8:	2300      	movs	r3, #0
+ 80361aa:	f887 3081 	strb.w	r3, [r7, #129]	@ 0x81
+  macDefaultConf.UnicastSlowProtocolPacketDetect = DISABLE;
+ 80361ae:	2300      	movs	r3, #0
+ 80361b0:	f887 305c 	strb.w	r3, [r7, #92]	@ 0x5c
+  macDefaultConf.Watchdog = ENABLE;
+ 80361b4:	2301      	movs	r3, #1
+ 80361b6:	f887 303c 	strb.w	r3, [r7, #60]	@ 0x3c
+  macDefaultConf.WatchdogTimeout =  ETH_MACWTR_WTO_2KB;
+ 80361ba:	2300      	movs	r3, #0
+ 80361bc:	673b      	str	r3, [r7, #112]	@ 0x70
+  macDefaultConf.ZeroQuantaPause = ENABLE;
+ 80361be:	2301      	movs	r3, #1
+ 80361c0:	f887 3078 	strb.w	r3, [r7, #120]	@ 0x78
+
+  /* MAC default configuration */
+  ETH_SetMACConfig(heth, &macDefaultConf);
+ 80361c4:	f107 032c 	add.w	r3, r7, #44	@ 0x2c
+ 80361c8:	4619      	mov	r1, r3
+ 80361ca:	6878      	ldr	r0, [r7, #4]
+ 80361cc:	f7ff fde6 	bl	8035d9c <ETH_SetMACConfig>
+
+  /*--------------- ETHERNET DMA registers default Configuration --------------*/
+  dmaDefaultConf.AddressAlignedBeats = ENABLE;
+ 80361d0:	2301      	movs	r3, #1
+ 80361d2:	733b      	strb	r3, [r7, #12]
+  dmaDefaultConf.BurstMode = ETH_BURSTLENGTH_FIXED;
+ 80361d4:	2301      	movs	r3, #1
+ 80361d6:	613b      	str	r3, [r7, #16]
+  dmaDefaultConf.DMAArbitration = ETH_DMAARBITRATION_RX1_TX1;
+ 80361d8:	2300      	movs	r3, #0
+ 80361da:	60bb      	str	r3, [r7, #8]
+  dmaDefaultConf.FlushRxPacket = DISABLE;
+ 80361dc:	2300      	movs	r3, #0
+ 80361de:	f887 3024 	strb.w	r3, [r7, #36]	@ 0x24
+  dmaDefaultConf.PBLx8Mode = DISABLE;
+ 80361e2:	2300      	movs	r3, #0
+ 80361e4:	757b      	strb	r3, [r7, #21]
+  dmaDefaultConf.RebuildINCRxBurst = DISABLE;
+ 80361e6:	2300      	movs	r3, #0
+ 80361e8:	753b      	strb	r3, [r7, #20]
+  dmaDefaultConf.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
+ 80361ea:	f44f 1300 	mov.w	r3, #2097152	@ 0x200000
+ 80361ee:	623b      	str	r3, [r7, #32]
+  dmaDefaultConf.SecondPacketOperate = DISABLE;
+ 80361f0:	2300      	movs	r3, #0
+ 80361f2:	773b      	strb	r3, [r7, #28]
+  dmaDefaultConf.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
+ 80361f4:	f44f 1300 	mov.w	r3, #2097152	@ 0x200000
+ 80361f8:	61bb      	str	r3, [r7, #24]
+  dmaDefaultConf.TCPSegmentation = DISABLE;
+ 80361fa:	2300      	movs	r3, #0
+ 80361fc:	f887 3025 	strb.w	r3, [r7, #37]	@ 0x25
+  dmaDefaultConf.MaximumSegmentSize = ETH_SEGMENT_SIZE_DEFAULT;
+ 8036200:	f44f 7306 	mov.w	r3, #536	@ 0x218
+ 8036204:	62bb      	str	r3, [r7, #40]	@ 0x28
+
+  /* DMA default configuration */
+  ETH_SetDMAConfig(heth, &dmaDefaultConf);
+ 8036206:	f107 0308 	add.w	r3, r7, #8
+ 803620a:	4619      	mov	r1, r3
+ 803620c:	6878      	ldr	r0, [r7, #4]
+ 803620e:	f7ff fee1 	bl	8035fd4 <ETH_SetDMAConfig>
+}
+ 8036212:	bf00      	nop
+ 8036214:	3790      	adds	r7, #144	@ 0x90
+ 8036216:	46bd      	mov	sp, r7
+ 8036218:	bd80      	pop	{r7, pc}
+
+0803621a <ETH_DMATxDescListInit>:
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None
+  */
+static void ETH_DMATxDescListInit(ETH_HandleTypeDef *heth)
+{
+ 803621a:	b480      	push	{r7}
+ 803621c:	b085      	sub	sp, #20
+ 803621e:	af00      	add	r7, sp, #0
+ 8036220:	6078      	str	r0, [r7, #4]
+  ETH_DMADescTypeDef *dmatxdesc;
+  uint32_t i;
+
+  /* Fill each DMATxDesc descriptor with the right values */
+  for (i = 0; i < (uint32_t)ETH_TX_DESC_CNT; i++)
+ 8036222:	2300      	movs	r3, #0
+ 8036224:	60fb      	str	r3, [r7, #12]
+ 8036226:	e01d      	b.n	8036264 <ETH_DMATxDescListInit+0x4a>
+  {
+    dmatxdesc = heth->Init.TxDesc + i;
+ 8036228:	687b      	ldr	r3, [r7, #4]
+ 803622a:	68d9      	ldr	r1, [r3, #12]
+ 803622c:	68fa      	ldr	r2, [r7, #12]
+ 803622e:	4613      	mov	r3, r2
+ 8036230:	005b      	lsls	r3, r3, #1
+ 8036232:	4413      	add	r3, r2
+ 8036234:	00db      	lsls	r3, r3, #3
+ 8036236:	440b      	add	r3, r1
+ 8036238:	60bb      	str	r3, [r7, #8]
+
+    WRITE_REG(dmatxdesc->DESC0, 0x0U);
+ 803623a:	68bb      	ldr	r3, [r7, #8]
+ 803623c:	2200      	movs	r2, #0
+ 803623e:	601a      	str	r2, [r3, #0]
+    WRITE_REG(dmatxdesc->DESC1, 0x0U);
+ 8036240:	68bb      	ldr	r3, [r7, #8]
+ 8036242:	2200      	movs	r2, #0
+ 8036244:	605a      	str	r2, [r3, #4]
+    WRITE_REG(dmatxdesc->DESC2, 0x0U);
+ 8036246:	68bb      	ldr	r3, [r7, #8]
+ 8036248:	2200      	movs	r2, #0
+ 803624a:	609a      	str	r2, [r3, #8]
+    WRITE_REG(dmatxdesc->DESC3, 0x0U);
+ 803624c:	68bb      	ldr	r3, [r7, #8]
+ 803624e:	2200      	movs	r2, #0
+ 8036250:	60da      	str	r2, [r3, #12]
+
+    WRITE_REG(heth->TxDescList.TxDesc[i], (uint32_t)dmatxdesc);
+ 8036252:	68b9      	ldr	r1, [r7, #8]
+ 8036254:	687b      	ldr	r3, [r7, #4]
+ 8036256:	68fa      	ldr	r2, [r7, #12]
+ 8036258:	3206      	adds	r2, #6
+ 803625a:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
+  for (i = 0; i < (uint32_t)ETH_TX_DESC_CNT; i++)
+ 803625e:	68fb      	ldr	r3, [r7, #12]
+ 8036260:	3301      	adds	r3, #1
+ 8036262:	60fb      	str	r3, [r7, #12]
+ 8036264:	68fb      	ldr	r3, [r7, #12]
+ 8036266:	2b03      	cmp	r3, #3
+ 8036268:	d9de      	bls.n	8036228 <ETH_DMATxDescListInit+0xe>
+
+  }
+
+  heth->TxDescList.CurTxDesc = 0;
+ 803626a:	687b      	ldr	r3, [r7, #4]
+ 803626c:	2200      	movs	r2, #0
+ 803626e:	629a      	str	r2, [r3, #40]	@ 0x28
+
+  /* Set Transmit Descriptor Ring Length */
+  WRITE_REG(heth->Instance->DMACTDRLR, (ETH_TX_DESC_CNT - 1U));
+ 8036270:	687b      	ldr	r3, [r7, #4]
+ 8036272:	681b      	ldr	r3, [r3, #0]
+ 8036274:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8036278:	461a      	mov	r2, r3
+ 803627a:	2303      	movs	r3, #3
+ 803627c:	f8c2 312c 	str.w	r3, [r2, #300]	@ 0x12c
+
+  /* Set Transmit Descriptor List Address */
+  WRITE_REG(heth->Instance->DMACTDLAR, (uint32_t) heth->Init.TxDesc);
+ 8036280:	687b      	ldr	r3, [r7, #4]
+ 8036282:	68da      	ldr	r2, [r3, #12]
+ 8036284:	687b      	ldr	r3, [r7, #4]
+ 8036286:	681b      	ldr	r3, [r3, #0]
+ 8036288:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 803628c:	f8c3 2114 	str.w	r2, [r3, #276]	@ 0x114
+
+  /* Set Transmit Descriptor Tail pointer */
+  WRITE_REG(heth->Instance->DMACTDTPR, (uint32_t) heth->Init.TxDesc);
+ 8036290:	687b      	ldr	r3, [r7, #4]
+ 8036292:	68da      	ldr	r2, [r3, #12]
+ 8036294:	687b      	ldr	r3, [r7, #4]
+ 8036296:	681b      	ldr	r3, [r3, #0]
+ 8036298:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 803629c:	f8c3 2120 	str.w	r2, [r3, #288]	@ 0x120
+}
+ 80362a0:	bf00      	nop
+ 80362a2:	3714      	adds	r7, #20
+ 80362a4:	46bd      	mov	sp, r7
+ 80362a6:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80362aa:	4770      	bx	lr
+
+080362ac <ETH_DMARxDescListInit>:
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None
+  */
+static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth)
+{
+ 80362ac:	b480      	push	{r7}
+ 80362ae:	b085      	sub	sp, #20
+ 80362b0:	af00      	add	r7, sp, #0
+ 80362b2:	6078      	str	r0, [r7, #4]
+  ETH_DMADescTypeDef *dmarxdesc;
+  uint32_t i;
+
+  for (i = 0; i < (uint32_t)ETH_RX_DESC_CNT; i++)
+ 80362b4:	2300      	movs	r3, #0
+ 80362b6:	60fb      	str	r3, [r7, #12]
+ 80362b8:	e023      	b.n	8036302 <ETH_DMARxDescListInit+0x56>
+  {
+    dmarxdesc =  heth->Init.RxDesc + i;
+ 80362ba:	687b      	ldr	r3, [r7, #4]
+ 80362bc:	6919      	ldr	r1, [r3, #16]
+ 80362be:	68fa      	ldr	r2, [r7, #12]
+ 80362c0:	4613      	mov	r3, r2
+ 80362c2:	005b      	lsls	r3, r3, #1
+ 80362c4:	4413      	add	r3, r2
+ 80362c6:	00db      	lsls	r3, r3, #3
+ 80362c8:	440b      	add	r3, r1
+ 80362ca:	60bb      	str	r3, [r7, #8]
+
+    WRITE_REG(dmarxdesc->DESC0, 0x0U);
+ 80362cc:	68bb      	ldr	r3, [r7, #8]
+ 80362ce:	2200      	movs	r2, #0
+ 80362d0:	601a      	str	r2, [r3, #0]
+    WRITE_REG(dmarxdesc->DESC1, 0x0U);
+ 80362d2:	68bb      	ldr	r3, [r7, #8]
+ 80362d4:	2200      	movs	r2, #0
+ 80362d6:	605a      	str	r2, [r3, #4]
+    WRITE_REG(dmarxdesc->DESC2, 0x0U);
+ 80362d8:	68bb      	ldr	r3, [r7, #8]
+ 80362da:	2200      	movs	r2, #0
+ 80362dc:	609a      	str	r2, [r3, #8]
+    WRITE_REG(dmarxdesc->DESC3, 0x0U);
+ 80362de:	68bb      	ldr	r3, [r7, #8]
+ 80362e0:	2200      	movs	r2, #0
+ 80362e2:	60da      	str	r2, [r3, #12]
+    WRITE_REG(dmarxdesc->BackupAddr0, 0x0U);
+ 80362e4:	68bb      	ldr	r3, [r7, #8]
+ 80362e6:	2200      	movs	r2, #0
+ 80362e8:	611a      	str	r2, [r3, #16]
+    WRITE_REG(dmarxdesc->BackupAddr1, 0x0U);
+ 80362ea:	68bb      	ldr	r3, [r7, #8]
+ 80362ec:	2200      	movs	r2, #0
+ 80362ee:	615a      	str	r2, [r3, #20]
+
+    /* Set Rx descritors addresses */
+    WRITE_REG(heth->RxDescList.RxDesc[i], (uint32_t)dmarxdesc);
+ 80362f0:	68b9      	ldr	r1, [r7, #8]
+ 80362f2:	687b      	ldr	r3, [r7, #4]
+ 80362f4:	68fa      	ldr	r2, [r7, #12]
+ 80362f6:	3212      	adds	r2, #18
+ 80362f8:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
+  for (i = 0; i < (uint32_t)ETH_RX_DESC_CNT; i++)
+ 80362fc:	68fb      	ldr	r3, [r7, #12]
+ 80362fe:	3301      	adds	r3, #1
+ 8036300:	60fb      	str	r3, [r7, #12]
+ 8036302:	68fb      	ldr	r3, [r7, #12]
+ 8036304:	2b03      	cmp	r3, #3
+ 8036306:	d9d8      	bls.n	80362ba <ETH_DMARxDescListInit+0xe>
+
+  }
+
+  WRITE_REG(heth->RxDescList.RxDescIdx, 0U);
+ 8036308:	687b      	ldr	r3, [r7, #4]
+ 803630a:	2200      	movs	r2, #0
+ 803630c:	65da      	str	r2, [r3, #92]	@ 0x5c
+  WRITE_REG(heth->RxDescList.RxDescCnt, 0U);
+ 803630e:	687b      	ldr	r3, [r7, #4]
+ 8036310:	2200      	movs	r2, #0
+ 8036312:	661a      	str	r2, [r3, #96]	@ 0x60
+  WRITE_REG(heth->RxDescList.RxBuildDescIdx, 0U);
+ 8036314:	687b      	ldr	r3, [r7, #4]
+ 8036316:	2200      	movs	r2, #0
+ 8036318:	669a      	str	r2, [r3, #104]	@ 0x68
+  WRITE_REG(heth->RxDescList.RxBuildDescCnt, 0U);
+ 803631a:	687b      	ldr	r3, [r7, #4]
+ 803631c:	2200      	movs	r2, #0
+ 803631e:	66da      	str	r2, [r3, #108]	@ 0x6c
+  WRITE_REG(heth->RxDescList.ItMode, 0U);
+ 8036320:	687b      	ldr	r3, [r7, #4]
+ 8036322:	2200      	movs	r2, #0
+ 8036324:	659a      	str	r2, [r3, #88]	@ 0x58
+
+  /* Set Receive Descriptor Ring Length */
+  WRITE_REG(heth->Instance->DMACRDRLR, ((uint32_t)(ETH_RX_DESC_CNT - 1U)));
+ 8036326:	687b      	ldr	r3, [r7, #4]
+ 8036328:	681b      	ldr	r3, [r3, #0]
+ 803632a:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 803632e:	461a      	mov	r2, r3
+ 8036330:	2303      	movs	r3, #3
+ 8036332:	f8c2 3130 	str.w	r3, [r2, #304]	@ 0x130
+
+  /* Set Receive Descriptor List Address */
+  WRITE_REG(heth->Instance->DMACRDLAR, (uint32_t) heth->Init.RxDesc);
+ 8036336:	687b      	ldr	r3, [r7, #4]
+ 8036338:	691a      	ldr	r2, [r3, #16]
+ 803633a:	687b      	ldr	r3, [r7, #4]
+ 803633c:	681b      	ldr	r3, [r3, #0]
+ 803633e:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8036342:	f8c3 211c 	str.w	r2, [r3, #284]	@ 0x11c
+
+  /* Set Receive Descriptor Tail pointer Address */
+  WRITE_REG(heth->Instance->DMACRDTPR, ((uint32_t)(heth->Init.RxDesc + (uint32_t)(ETH_RX_DESC_CNT - 1U))));
+ 8036346:	687b      	ldr	r3, [r7, #4]
+ 8036348:	691b      	ldr	r3, [r3, #16]
+ 803634a:	f103 0248 	add.w	r2, r3, #72	@ 0x48
+ 803634e:	687b      	ldr	r3, [r7, #4]
+ 8036350:	681b      	ldr	r3, [r3, #0]
+ 8036352:	f503 5380 	add.w	r3, r3, #4096	@ 0x1000
+ 8036356:	f8c3 2128 	str.w	r2, [r3, #296]	@ 0x128
+}
+ 803635a:	bf00      	nop
+ 803635c:	3714      	adds	r7, #20
+ 803635e:	46bd      	mov	sp, r7
+ 8036360:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8036364:	4770      	bx	lr
+	...
+
+08036368 <HAL_FDCAN_Init>:
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan)
+{
+ 8036368:	b580      	push	{r7, lr}
+ 803636a:	b098      	sub	sp, #96	@ 0x60
+ 803636c:	af00      	add	r7, sp, #0
+ 803636e:	6078      	str	r0, [r7, #4]
+  uint32_t tickstart;
+  HAL_StatusTypeDef status;
+  const uint32_t CvtEltSize[] = {0, 0, 0, 0, 0, 1, 2, 3, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0, 7};
+ 8036370:	4a84      	ldr	r2, [pc, #528]	@ (8036584 <HAL_FDCAN_Init+0x21c>)
+ 8036372:	f107 030c 	add.w	r3, r7, #12
+ 8036376:	4611      	mov	r1, r2
+ 8036378:	224c      	movs	r2, #76	@ 0x4c
+ 803637a:	4618      	mov	r0, r3
+ 803637c:	f00a f81e 	bl	80403bc <memcpy>
+
+  /* Check FDCAN handle */
+  if (hfdcan == NULL)
+ 8036380:	687b      	ldr	r3, [r7, #4]
+ 8036382:	2b00      	cmp	r3, #0
+ 8036384:	d101      	bne.n	803638a <HAL_FDCAN_Init+0x22>
+  {
+    return HAL_ERROR;
+ 8036386:	2301      	movs	r3, #1
+ 8036388:	e1c6      	b.n	8036718 <HAL_FDCAN_Init+0x3b0>
+  }
+
+  /* Check FDCAN instance */
+  if (hfdcan->Instance == FDCAN1)
+ 803638a:	687b      	ldr	r3, [r7, #4]
+ 803638c:	681b      	ldr	r3, [r3, #0]
+ 803638e:	4a7e      	ldr	r2, [pc, #504]	@ (8036588 <HAL_FDCAN_Init+0x220>)
+ 8036390:	4293      	cmp	r3, r2
+ 8036392:	d106      	bne.n	80363a2 <HAL_FDCAN_Init+0x3a>
+  {
+    hfdcan->ttcan = (TTCAN_TypeDef *)((uint32_t)hfdcan->Instance + 0x100U);
+ 8036394:	687b      	ldr	r3, [r7, #4]
+ 8036396:	681b      	ldr	r3, [r3, #0]
+ 8036398:	f503 7380 	add.w	r3, r3, #256	@ 0x100
+ 803639c:	461a      	mov	r2, r3
+ 803639e:	687b      	ldr	r3, [r7, #4]
+ 80363a0:	605a      	str	r2, [r3, #4]
+
+    /* Init the low level hardware: CLOCK, NVIC */
+    hfdcan->MspInitCallback(hfdcan);
+  }
+#else
+  if (hfdcan->State == HAL_FDCAN_STATE_RESET)
+ 80363a2:	687b      	ldr	r3, [r7, #4]
+ 80363a4:	f893 3098 	ldrb.w	r3, [r3, #152]	@ 0x98
+ 80363a8:	b2db      	uxtb	r3, r3
+ 80363aa:	2b00      	cmp	r3, #0
+ 80363ac:	d106      	bne.n	80363bc <HAL_FDCAN_Init+0x54>
+  {
+    /* Allocate lock resource and initialize it */
+    hfdcan->Lock = HAL_UNLOCKED;
+ 80363ae:	687b      	ldr	r3, [r7, #4]
+ 80363b0:	2200      	movs	r2, #0
+ 80363b2:	f883 2099 	strb.w	r2, [r3, #153]	@ 0x99
+
+    /* Init the low level hardware: CLOCK, NVIC */
+    HAL_FDCAN_MspInit(hfdcan);
+ 80363b6:	6878      	ldr	r0, [r7, #4]
+ 80363b8:	f7f2 ff9e 	bl	80292f8 <HAL_FDCAN_MspInit>
+  }
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+
+  /* Exit from Sleep mode */
+  CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
+ 80363bc:	687b      	ldr	r3, [r7, #4]
+ 80363be:	681b      	ldr	r3, [r3, #0]
+ 80363c0:	699a      	ldr	r2, [r3, #24]
+ 80363c2:	687b      	ldr	r3, [r7, #4]
+ 80363c4:	681b      	ldr	r3, [r3, #0]
+ 80363c6:	f022 0210 	bic.w	r2, r2, #16
+ 80363ca:	619a      	str	r2, [r3, #24]
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+ 80363cc:	f7fb fab0 	bl	8031930 <HAL_GetTick>
+ 80363d0:	65f8      	str	r0, [r7, #92]	@ 0x5c
+
+  /* Check Sleep mode acknowledge */
+  while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA)
+ 80363d2:	e014      	b.n	80363fe <HAL_FDCAN_Init+0x96>
+  {
+    if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
+ 80363d4:	f7fb faac 	bl	8031930 <HAL_GetTick>
+ 80363d8:	4602      	mov	r2, r0
+ 80363da:	6dfb      	ldr	r3, [r7, #92]	@ 0x5c
+ 80363dc:	1ad3      	subs	r3, r2, r3
+ 80363de:	2b0a      	cmp	r3, #10
+ 80363e0:	d90d      	bls.n	80363fe <HAL_FDCAN_Init+0x96>
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+ 80363e2:	687b      	ldr	r3, [r7, #4]
+ 80363e4:	f8d3 309c 	ldr.w	r3, [r3, #156]	@ 0x9c
+ 80363e8:	f043 0201 	orr.w	r2, r3, #1
+ 80363ec:	687b      	ldr	r3, [r7, #4]
+ 80363ee:	f8c3 209c 	str.w	r2, [r3, #156]	@ 0x9c
+
+      /* Change FDCAN state */
+      hfdcan->State = HAL_FDCAN_STATE_ERROR;
+ 80363f2:	687b      	ldr	r3, [r7, #4]
+ 80363f4:	2203      	movs	r2, #3
+ 80363f6:	f883 2098 	strb.w	r2, [r3, #152]	@ 0x98
+
+      return HAL_ERROR;
+ 80363fa:	2301      	movs	r3, #1
+ 80363fc:	e18c      	b.n	8036718 <HAL_FDCAN_Init+0x3b0>
+  while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA)
+ 80363fe:	687b      	ldr	r3, [r7, #4]
+ 8036400:	681b      	ldr	r3, [r3, #0]
+ 8036402:	699b      	ldr	r3, [r3, #24]
+ 8036404:	f003 0308 	and.w	r3, r3, #8
+ 8036408:	2b08      	cmp	r3, #8
+ 803640a:	d0e3      	beq.n	80363d4 <HAL_FDCAN_Init+0x6c>
+    }
+  }
+
+  /* Request initialisation */
+  SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
+ 803640c:	687b      	ldr	r3, [r7, #4]
+ 803640e:	681b      	ldr	r3, [r3, #0]
+ 8036410:	699a      	ldr	r2, [r3, #24]
+ 8036412:	687b      	ldr	r3, [r7, #4]
+ 8036414:	681b      	ldr	r3, [r3, #0]
+ 8036416:	f042 0201 	orr.w	r2, r2, #1
+ 803641a:	619a      	str	r2, [r3, #24]
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+ 803641c:	f7fb fa88 	bl	8031930 <HAL_GetTick>
+ 8036420:	65f8      	str	r0, [r7, #92]	@ 0x5c
+
+  /* Wait until the INIT bit into CCCR register is set */
+  while ((hfdcan->Instance->CCCR & FDCAN_CCCR_INIT) == 0U)
+ 8036422:	e014      	b.n	803644e <HAL_FDCAN_Init+0xe6>
+  {
+    /* Check for the Timeout */
+    if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
+ 8036424:	f7fb fa84 	bl	8031930 <HAL_GetTick>
+ 8036428:	4602      	mov	r2, r0
+ 803642a:	6dfb      	ldr	r3, [r7, #92]	@ 0x5c
+ 803642c:	1ad3      	subs	r3, r2, r3
+ 803642e:	2b0a      	cmp	r3, #10
+ 8036430:	d90d      	bls.n	803644e <HAL_FDCAN_Init+0xe6>
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
+ 8036432:	687b      	ldr	r3, [r7, #4]
+ 8036434:	f8d3 309c 	ldr.w	r3, [r3, #156]	@ 0x9c
+ 8036438:	f043 0201 	orr.w	r2, r3, #1
+ 803643c:	687b      	ldr	r3, [r7, #4]
+ 803643e:	f8c3 209c 	str.w	r2, [r3, #156]	@ 0x9c
+
+      /* Change FDCAN state */
+      hfdcan->State = HAL_FDCAN_STATE_ERROR;
+ 8036442:	687b      	ldr	r3, [r7, #4]
+ 8036444:	2203      	movs	r2, #3
+ 8036446:	f883 2098 	strb.w	r2, [r3, #152]	@ 0x98
+
+      return HAL_ERROR;
+ 803644a:	2301      	movs	r3, #1
+ 803644c:	e164      	b.n	8036718 <HAL_FDCAN_Init+0x3b0>
+  while ((hfdcan->Instance->CCCR & FDCAN_CCCR_INIT) == 0U)
+ 803644e:	687b      	ldr	r3, [r7, #4]
+ 8036450:	681b      	ldr	r3, [r3, #0]
+ 8036452:	699b      	ldr	r3, [r3, #24]
+ 8036454:	f003 0301 	and.w	r3, r3, #1
+ 8036458:	2b00      	cmp	r3, #0
+ 803645a:	d0e3      	beq.n	8036424 <HAL_FDCAN_Init+0xbc>
+    }
+  }
+
+  /* Enable configuration change */
+  SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CCE);
+ 803645c:	687b      	ldr	r3, [r7, #4]
+ 803645e:	681b      	ldr	r3, [r3, #0]
+ 8036460:	699a      	ldr	r2, [r3, #24]
+ 8036462:	687b      	ldr	r3, [r7, #4]
+ 8036464:	681b      	ldr	r3, [r3, #0]
+ 8036466:	f042 0202 	orr.w	r2, r2, #2
+ 803646a:	619a      	str	r2, [r3, #24]
+
+  /* Set the no automatic retransmission */
+  if (hfdcan->Init.AutoRetransmission == ENABLE)
+ 803646c:	687b      	ldr	r3, [r7, #4]
+ 803646e:	7c1b      	ldrb	r3, [r3, #16]
+ 8036470:	2b01      	cmp	r3, #1
+ 8036472:	d108      	bne.n	8036486 <HAL_FDCAN_Init+0x11e>
+  {
+    CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_DAR);
+ 8036474:	687b      	ldr	r3, [r7, #4]
+ 8036476:	681b      	ldr	r3, [r3, #0]
+ 8036478:	699a      	ldr	r2, [r3, #24]
+ 803647a:	687b      	ldr	r3, [r7, #4]
+ 803647c:	681b      	ldr	r3, [r3, #0]
+ 803647e:	f022 0240 	bic.w	r2, r2, #64	@ 0x40
+ 8036482:	619a      	str	r2, [r3, #24]
+ 8036484:	e007      	b.n	8036496 <HAL_FDCAN_Init+0x12e>
+  }
+  else
+  {
+    SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_DAR);
+ 8036486:	687b      	ldr	r3, [r7, #4]
+ 8036488:	681b      	ldr	r3, [r3, #0]
+ 803648a:	699a      	ldr	r2, [r3, #24]
+ 803648c:	687b      	ldr	r3, [r7, #4]
+ 803648e:	681b      	ldr	r3, [r3, #0]
+ 8036490:	f042 0240 	orr.w	r2, r2, #64	@ 0x40
+ 8036494:	619a      	str	r2, [r3, #24]
+  }
+
+  /* Set the transmit pause feature */
+  if (hfdcan->Init.TransmitPause == ENABLE)
+ 8036496:	687b      	ldr	r3, [r7, #4]
+ 8036498:	7c5b      	ldrb	r3, [r3, #17]
+ 803649a:	2b01      	cmp	r3, #1
+ 803649c:	d108      	bne.n	80364b0 <HAL_FDCAN_Init+0x148>
+  {
+    SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TXP);
+ 803649e:	687b      	ldr	r3, [r7, #4]
+ 80364a0:	681b      	ldr	r3, [r3, #0]
+ 80364a2:	699a      	ldr	r2, [r3, #24]
+ 80364a4:	687b      	ldr	r3, [r7, #4]
+ 80364a6:	681b      	ldr	r3, [r3, #0]
+ 80364a8:	f442 4280 	orr.w	r2, r2, #16384	@ 0x4000
+ 80364ac:	619a      	str	r2, [r3, #24]
+ 80364ae:	e007      	b.n	80364c0 <HAL_FDCAN_Init+0x158>
+  }
+  else
+  {
+    CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TXP);
+ 80364b0:	687b      	ldr	r3, [r7, #4]
+ 80364b2:	681b      	ldr	r3, [r3, #0]
+ 80364b4:	699a      	ldr	r2, [r3, #24]
+ 80364b6:	687b      	ldr	r3, [r7, #4]
+ 80364b8:	681b      	ldr	r3, [r3, #0]
+ 80364ba:	f422 4280 	bic.w	r2, r2, #16384	@ 0x4000
+ 80364be:	619a      	str	r2, [r3, #24]
+  }
+
+  /* Set the Protocol Exception Handling */
+  if (hfdcan->Init.ProtocolException == ENABLE)
+ 80364c0:	687b      	ldr	r3, [r7, #4]
+ 80364c2:	7c9b      	ldrb	r3, [r3, #18]
+ 80364c4:	2b01      	cmp	r3, #1
+ 80364c6:	d108      	bne.n	80364da <HAL_FDCAN_Init+0x172>
+  {
+    CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_PXHD);
+ 80364c8:	687b      	ldr	r3, [r7, #4]
+ 80364ca:	681b      	ldr	r3, [r3, #0]
+ 80364cc:	699a      	ldr	r2, [r3, #24]
+ 80364ce:	687b      	ldr	r3, [r7, #4]
+ 80364d0:	681b      	ldr	r3, [r3, #0]
+ 80364d2:	f422 5280 	bic.w	r2, r2, #4096	@ 0x1000
+ 80364d6:	619a      	str	r2, [r3, #24]
+ 80364d8:	e007      	b.n	80364ea <HAL_FDCAN_Init+0x182>
+  }
+  else
+  {
+    SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_PXHD);
+ 80364da:	687b      	ldr	r3, [r7, #4]
+ 80364dc:	681b      	ldr	r3, [r3, #0]
+ 80364de:	699a      	ldr	r2, [r3, #24]
+ 80364e0:	687b      	ldr	r3, [r7, #4]
+ 80364e2:	681b      	ldr	r3, [r3, #0]
+ 80364e4:	f442 5280 	orr.w	r2, r2, #4096	@ 0x1000
+ 80364e8:	619a      	str	r2, [r3, #24]
+  }
+
+  /* Set FDCAN Frame Format */
+  MODIFY_REG(hfdcan->Instance->CCCR, FDCAN_FRAME_FD_BRS, hfdcan->Init.FrameFormat);
+ 80364ea:	687b      	ldr	r3, [r7, #4]
+ 80364ec:	681b      	ldr	r3, [r3, #0]
+ 80364ee:	699b      	ldr	r3, [r3, #24]
+ 80364f0:	f423 7140 	bic.w	r1, r3, #768	@ 0x300
+ 80364f4:	687b      	ldr	r3, [r7, #4]
+ 80364f6:	689a      	ldr	r2, [r3, #8]
+ 80364f8:	687b      	ldr	r3, [r7, #4]
+ 80364fa:	681b      	ldr	r3, [r3, #0]
+ 80364fc:	430a      	orrs	r2, r1
+ 80364fe:	619a      	str	r2, [r3, #24]
+
+  /* Reset FDCAN Operation Mode */
+  CLEAR_BIT(hfdcan->Instance->CCCR, (FDCAN_CCCR_TEST | FDCAN_CCCR_MON | FDCAN_CCCR_ASM));
+ 8036500:	687b      	ldr	r3, [r7, #4]
+ 8036502:	681b      	ldr	r3, [r3, #0]
+ 8036504:	699a      	ldr	r2, [r3, #24]
+ 8036506:	687b      	ldr	r3, [r7, #4]
+ 8036508:	681b      	ldr	r3, [r3, #0]
+ 803650a:	f022 02a4 	bic.w	r2, r2, #164	@ 0xa4
+ 803650e:	619a      	str	r2, [r3, #24]
+  CLEAR_BIT(hfdcan->Instance->TEST, FDCAN_TEST_LBCK);
+ 8036510:	687b      	ldr	r3, [r7, #4]
+ 8036512:	681b      	ldr	r3, [r3, #0]
+ 8036514:	691a      	ldr	r2, [r3, #16]
+ 8036516:	687b      	ldr	r3, [r7, #4]
+ 8036518:	681b      	ldr	r3, [r3, #0]
+ 803651a:	f022 0210 	bic.w	r2, r2, #16
+ 803651e:	611a      	str	r2, [r3, #16]
+     CCCR.TEST |   0    |     0      |     0      |    1     |    1
+     CCCR.MON  |   0    |     0      |     1      |    1     |    0
+     TEST.LBCK |   0    |     0      |     0      |    1     |    1
+     CCCR.ASM  |   0    |     1      |     0      |    0     |    0
+  */
+  if (hfdcan->Init.Mode == FDCAN_MODE_RESTRICTED_OPERATION)
+ 8036520:	687b      	ldr	r3, [r7, #4]
+ 8036522:	68db      	ldr	r3, [r3, #12]
+ 8036524:	2b01      	cmp	r3, #1
+ 8036526:	d108      	bne.n	803653a <HAL_FDCAN_Init+0x1d2>
+  {
+    /* Enable Restricted Operation mode */
+    SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_ASM);
+ 8036528:	687b      	ldr	r3, [r7, #4]
+ 803652a:	681b      	ldr	r3, [r3, #0]
+ 803652c:	699a      	ldr	r2, [r3, #24]
+ 803652e:	687b      	ldr	r3, [r7, #4]
+ 8036530:	681b      	ldr	r3, [r3, #0]
+ 8036532:	f042 0204 	orr.w	r2, r2, #4
+ 8036536:	619a      	str	r2, [r3, #24]
+ 8036538:	e030      	b.n	803659c <HAL_FDCAN_Init+0x234>
+  }
+  else if (hfdcan->Init.Mode != FDCAN_MODE_NORMAL)
+ 803653a:	687b      	ldr	r3, [r7, #4]
+ 803653c:	68db      	ldr	r3, [r3, #12]
+ 803653e:	2b00      	cmp	r3, #0
+ 8036540:	d02c      	beq.n	803659c <HAL_FDCAN_Init+0x234>
+  {
+    if (hfdcan->Init.Mode != FDCAN_MODE_BUS_MONITORING)
+ 8036542:	687b      	ldr	r3, [r7, #4]
+ 8036544:	68db      	ldr	r3, [r3, #12]
+ 8036546:	2b02      	cmp	r3, #2
+ 8036548:	d020      	beq.n	803658c <HAL_FDCAN_Init+0x224>
+    {
+      /* Enable write access to TEST register */
+      SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TEST);
+ 803654a:	687b      	ldr	r3, [r7, #4]
+ 803654c:	681b      	ldr	r3, [r3, #0]
+ 803654e:	699a      	ldr	r2, [r3, #24]
+ 8036550:	687b      	ldr	r3, [r7, #4]
+ 8036552:	681b      	ldr	r3, [r3, #0]
+ 8036554:	f042 0280 	orr.w	r2, r2, #128	@ 0x80
+ 8036558:	619a      	str	r2, [r3, #24]
+
+      /* Enable LoopBack mode */
+      SET_BIT(hfdcan->Instance->TEST, FDCAN_TEST_LBCK);
+ 803655a:	687b      	ldr	r3, [r7, #4]
+ 803655c:	681b      	ldr	r3, [r3, #0]
+ 803655e:	691a      	ldr	r2, [r3, #16]
+ 8036560:	687b      	ldr	r3, [r7, #4]
+ 8036562:	681b      	ldr	r3, [r3, #0]
+ 8036564:	f042 0210 	orr.w	r2, r2, #16
+ 8036568:	611a      	str	r2, [r3, #16]
+
+      if (hfdcan->Init.Mode == FDCAN_MODE_INTERNAL_LOOPBACK)
+ 803656a:	687b      	ldr	r3, [r7, #4]
+ 803656c:	68db      	ldr	r3, [r3, #12]
+ 803656e:	2b03      	cmp	r3, #3
+ 8036570:	d114      	bne.n	803659c <HAL_FDCAN_Init+0x234>
+      {
+        SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_MON);
+ 8036572:	687b      	ldr	r3, [r7, #4]
+ 8036574:	681b      	ldr	r3, [r3, #0]
+ 8036576:	699a      	ldr	r2, [r3, #24]
+ 8036578:	687b      	ldr	r3, [r7, #4]
+ 803657a:	681b      	ldr	r3, [r3, #0]
+ 803657c:	f042 0220 	orr.w	r2, r2, #32
+ 8036580:	619a      	str	r2, [r3, #24]
+ 8036582:	e00b      	b.n	803659c <HAL_FDCAN_Init+0x234>
+ 8036584:	08041560 	.word	0x08041560
+ 8036588:	4000a000 	.word	0x4000a000
+      }
+    }
+    else
+    {
+      /* Enable bus monitoring mode */
+      SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_MON);
+ 803658c:	687b      	ldr	r3, [r7, #4]
+ 803658e:	681b      	ldr	r3, [r3, #0]
+ 8036590:	699a      	ldr	r2, [r3, #24]
+ 8036592:	687b      	ldr	r3, [r7, #4]
+ 8036594:	681b      	ldr	r3, [r3, #0]
+ 8036596:	f042 0220 	orr.w	r2, r2, #32
+ 803659a:	619a      	str	r2, [r3, #24]
+  {
+    /* Nothing to do: normal mode */
+  }
+
+  /* Set the nominal bit timing register */
+  hfdcan->Instance->NBTP = ((((uint32_t)hfdcan->Init.NominalSyncJumpWidth - 1U) << FDCAN_NBTP_NSJW_Pos) | \
+ 803659c:	687b      	ldr	r3, [r7, #4]
+ 803659e:	699b      	ldr	r3, [r3, #24]
+ 80365a0:	3b01      	subs	r3, #1
+ 80365a2:	065a      	lsls	r2, r3, #25
+                            (((uint32_t)hfdcan->Init.NominalTimeSeg1 - 1U) << FDCAN_NBTP_NTSEG1_Pos)    | \
+ 80365a4:	687b      	ldr	r3, [r7, #4]
+ 80365a6:	69db      	ldr	r3, [r3, #28]
+ 80365a8:	3b01      	subs	r3, #1
+ 80365aa:	021b      	lsls	r3, r3, #8
+  hfdcan->Instance->NBTP = ((((uint32_t)hfdcan->Init.NominalSyncJumpWidth - 1U) << FDCAN_NBTP_NSJW_Pos) | \
+ 80365ac:	431a      	orrs	r2, r3
+                            (((uint32_t)hfdcan->Init.NominalTimeSeg2 - 1U) << FDCAN_NBTP_NTSEG2_Pos)    | \
+ 80365ae:	687b      	ldr	r3, [r7, #4]
+ 80365b0:	6a1b      	ldr	r3, [r3, #32]
+ 80365b2:	3b01      	subs	r3, #1
+                            (((uint32_t)hfdcan->Init.NominalTimeSeg1 - 1U) << FDCAN_NBTP_NTSEG1_Pos)    | \
+ 80365b4:	ea42 0103 	orr.w	r1, r2, r3
+                            (((uint32_t)hfdcan->Init.NominalPrescaler - 1U) << FDCAN_NBTP_NBRP_Pos));
+ 80365b8:	687b      	ldr	r3, [r7, #4]
+ 80365ba:	695b      	ldr	r3, [r3, #20]
+ 80365bc:	3b01      	subs	r3, #1
+ 80365be:	041a      	lsls	r2, r3, #16
+  hfdcan->Instance->NBTP = ((((uint32_t)hfdcan->Init.NominalSyncJumpWidth - 1U) << FDCAN_NBTP_NSJW_Pos) | \
+ 80365c0:	687b      	ldr	r3, [r7, #4]
+ 80365c2:	681b      	ldr	r3, [r3, #0]
+                            (((uint32_t)hfdcan->Init.NominalTimeSeg2 - 1U) << FDCAN_NBTP_NTSEG2_Pos)    | \
+ 80365c4:	430a      	orrs	r2, r1
+  hfdcan->Instance->NBTP = ((((uint32_t)hfdcan->Init.NominalSyncJumpWidth - 1U) << FDCAN_NBTP_NSJW_Pos) | \
+ 80365c6:	61da      	str	r2, [r3, #28]
+
+  /* If FD operation with BRS is selected, set the data bit timing register */
+  if (hfdcan->Init.FrameFormat == FDCAN_FRAME_FD_BRS)
+ 80365c8:	687b      	ldr	r3, [r7, #4]
+ 80365ca:	689b      	ldr	r3, [r3, #8]
+ 80365cc:	f5b3 7f40 	cmp.w	r3, #768	@ 0x300
+ 80365d0:	d115      	bne.n	80365fe <HAL_FDCAN_Init+0x296>
+  {
+    hfdcan->Instance->DBTP = ((((uint32_t)hfdcan->Init.DataSyncJumpWidth - 1U) << FDCAN_DBTP_DSJW_Pos)  | \
+ 80365d2:	687b      	ldr	r3, [r7, #4]
+ 80365d4:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 80365d6:	1e5a      	subs	r2, r3, #1
+                              (((uint32_t)hfdcan->Init.DataTimeSeg1 - 1U) << FDCAN_DBTP_DTSEG1_Pos)     | \
+ 80365d8:	687b      	ldr	r3, [r7, #4]
+ 80365da:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 80365dc:	3b01      	subs	r3, #1
+ 80365de:	021b      	lsls	r3, r3, #8
+    hfdcan->Instance->DBTP = ((((uint32_t)hfdcan->Init.DataSyncJumpWidth - 1U) << FDCAN_DBTP_DSJW_Pos)  | \
+ 80365e0:	431a      	orrs	r2, r3
+                              (((uint32_t)hfdcan->Init.DataTimeSeg2 - 1U) << FDCAN_DBTP_DTSEG2_Pos)     | \
+ 80365e2:	687b      	ldr	r3, [r7, #4]
+ 80365e4:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
+ 80365e6:	3b01      	subs	r3, #1
+ 80365e8:	011b      	lsls	r3, r3, #4
+                              (((uint32_t)hfdcan->Init.DataTimeSeg1 - 1U) << FDCAN_DBTP_DTSEG1_Pos)     | \
+ 80365ea:	ea42 0103 	orr.w	r1, r2, r3
+                              (((uint32_t)hfdcan->Init.DataPrescaler - 1U) << FDCAN_DBTP_DBRP_Pos));
+ 80365ee:	687b      	ldr	r3, [r7, #4]
+ 80365f0:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 80365f2:	3b01      	subs	r3, #1
+ 80365f4:	041a      	lsls	r2, r3, #16
+    hfdcan->Instance->DBTP = ((((uint32_t)hfdcan->Init.DataSyncJumpWidth - 1U) << FDCAN_DBTP_DSJW_Pos)  | \
+ 80365f6:	687b      	ldr	r3, [r7, #4]
+ 80365f8:	681b      	ldr	r3, [r3, #0]
+                              (((uint32_t)hfdcan->Init.DataTimeSeg2 - 1U) << FDCAN_DBTP_DTSEG2_Pos)     | \
+ 80365fa:	430a      	orrs	r2, r1
+    hfdcan->Instance->DBTP = ((((uint32_t)hfdcan->Init.DataSyncJumpWidth - 1U) << FDCAN_DBTP_DSJW_Pos)  | \
+ 80365fc:	60da      	str	r2, [r3, #12]
+  }
+
+  if (hfdcan->Init.TxFifoQueueElmtsNbr > 0U)
+ 80365fe:	687b      	ldr	r3, [r7, #4]
+ 8036600:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
+ 8036602:	2b00      	cmp	r3, #0
+ 8036604:	d00a      	beq.n	803661c <HAL_FDCAN_Init+0x2b4>
+  {
+    /* Select between Tx FIFO and Tx Queue operation modes */
+    SET_BIT(hfdcan->Instance->TXBC, hfdcan->Init.TxFifoQueueMode);
+ 8036606:	687b      	ldr	r3, [r7, #4]
+ 8036608:	681b      	ldr	r3, [r3, #0]
+ 803660a:	f8d3 10c0 	ldr.w	r1, [r3, #192]	@ 0xc0
+ 803660e:	687b      	ldr	r3, [r7, #4]
+ 8036610:	6e5a      	ldr	r2, [r3, #100]	@ 0x64
+ 8036612:	687b      	ldr	r3, [r7, #4]
+ 8036614:	681b      	ldr	r3, [r3, #0]
+ 8036616:	430a      	orrs	r2, r1
+ 8036618:	f8c3 20c0 	str.w	r2, [r3, #192]	@ 0xc0
+  }
+
+  /* Configure Tx element size */
+  if ((hfdcan->Init.TxBuffersNbr + hfdcan->Init.TxFifoQueueElmtsNbr) > 0U)
+ 803661c:	687b      	ldr	r3, [r7, #4]
+ 803661e:	6dda      	ldr	r2, [r3, #92]	@ 0x5c
+ 8036620:	687b      	ldr	r3, [r7, #4]
+ 8036622:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
+ 8036624:	4413      	add	r3, r2
+ 8036626:	2b00      	cmp	r3, #0
+ 8036628:	d011      	beq.n	803664e <HAL_FDCAN_Init+0x2e6>
+  {
+    MODIFY_REG(hfdcan->Instance->TXESC, FDCAN_TXESC_TBDS, CvtEltSize[hfdcan->Init.TxElmtSize]);
+ 803662a:	687b      	ldr	r3, [r7, #4]
+ 803662c:	681b      	ldr	r3, [r3, #0]
+ 803662e:	f8d3 30c8 	ldr.w	r3, [r3, #200]	@ 0xc8
+ 8036632:	f023 0107 	bic.w	r1, r3, #7
+ 8036636:	687b      	ldr	r3, [r7, #4]
+ 8036638:	6e9b      	ldr	r3, [r3, #104]	@ 0x68
+ 803663a:	009b      	lsls	r3, r3, #2
+ 803663c:	3360      	adds	r3, #96	@ 0x60
+ 803663e:	443b      	add	r3, r7
+ 8036640:	f853 2c54 	ldr.w	r2, [r3, #-84]
+ 8036644:	687b      	ldr	r3, [r7, #4]
+ 8036646:	681b      	ldr	r3, [r3, #0]
+ 8036648:	430a      	orrs	r2, r1
+ 803664a:	f8c3 20c8 	str.w	r2, [r3, #200]	@ 0xc8
+  }
+
+  /* Configure Rx FIFO 0 element size */
+  if (hfdcan->Init.RxFifo0ElmtsNbr > 0U)
+ 803664e:	687b      	ldr	r3, [r7, #4]
+ 8036650:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
+ 8036652:	2b00      	cmp	r3, #0
+ 8036654:	d011      	beq.n	803667a <HAL_FDCAN_Init+0x312>
+  {
+    MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_F0DS,
+ 8036656:	687b      	ldr	r3, [r7, #4]
+ 8036658:	681b      	ldr	r3, [r3, #0]
+ 803665a:	f8d3 30bc 	ldr.w	r3, [r3, #188]	@ 0xbc
+ 803665e:	f023 0107 	bic.w	r1, r3, #7
+ 8036662:	687b      	ldr	r3, [r7, #4]
+ 8036664:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
+ 8036666:	009b      	lsls	r3, r3, #2
+ 8036668:	3360      	adds	r3, #96	@ 0x60
+ 803666a:	443b      	add	r3, r7
+ 803666c:	f853 2c54 	ldr.w	r2, [r3, #-84]
+ 8036670:	687b      	ldr	r3, [r7, #4]
+ 8036672:	681b      	ldr	r3, [r3, #0]
+ 8036674:	430a      	orrs	r2, r1
+ 8036676:	f8c3 20bc 	str.w	r2, [r3, #188]	@ 0xbc
+               (CvtEltSize[hfdcan->Init.RxFifo0ElmtSize] << FDCAN_RXESC_F0DS_Pos));
+  }
+
+  /* Configure Rx FIFO 1 element size */
+  if (hfdcan->Init.RxFifo1ElmtsNbr > 0U)
+ 803667a:	687b      	ldr	r3, [r7, #4]
+ 803667c:	6c9b      	ldr	r3, [r3, #72]	@ 0x48
+ 803667e:	2b00      	cmp	r3, #0
+ 8036680:	d012      	beq.n	80366a8 <HAL_FDCAN_Init+0x340>
+  {
+    MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_F1DS,
+ 8036682:	687b      	ldr	r3, [r7, #4]
+ 8036684:	681b      	ldr	r3, [r3, #0]
+ 8036686:	f8d3 30bc 	ldr.w	r3, [r3, #188]	@ 0xbc
+ 803668a:	f023 0170 	bic.w	r1, r3, #112	@ 0x70
+ 803668e:	687b      	ldr	r3, [r7, #4]
+ 8036690:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
+ 8036692:	009b      	lsls	r3, r3, #2
+ 8036694:	3360      	adds	r3, #96	@ 0x60
+ 8036696:	443b      	add	r3, r7
+ 8036698:	f853 3c54 	ldr.w	r3, [r3, #-84]
+ 803669c:	011a      	lsls	r2, r3, #4
+ 803669e:	687b      	ldr	r3, [r7, #4]
+ 80366a0:	681b      	ldr	r3, [r3, #0]
+ 80366a2:	430a      	orrs	r2, r1
+ 80366a4:	f8c3 20bc 	str.w	r2, [r3, #188]	@ 0xbc
+               (CvtEltSize[hfdcan->Init.RxFifo1ElmtSize] << FDCAN_RXESC_F1DS_Pos));
+  }
+
+  /* Configure Rx buffer element size */
+  if (hfdcan->Init.RxBuffersNbr > 0U)
+ 80366a8:	687b      	ldr	r3, [r7, #4]
+ 80366aa:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
+ 80366ac:	2b00      	cmp	r3, #0
+ 80366ae:	d012      	beq.n	80366d6 <HAL_FDCAN_Init+0x36e>
+  {
+    MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_RBDS,
+ 80366b0:	687b      	ldr	r3, [r7, #4]
+ 80366b2:	681b      	ldr	r3, [r3, #0]
+ 80366b4:	f8d3 30bc 	ldr.w	r3, [r3, #188]	@ 0xbc
+ 80366b8:	f423 61e0 	bic.w	r1, r3, #1792	@ 0x700
+ 80366bc:	687b      	ldr	r3, [r7, #4]
+ 80366be:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
+ 80366c0:	009b      	lsls	r3, r3, #2
+ 80366c2:	3360      	adds	r3, #96	@ 0x60
+ 80366c4:	443b      	add	r3, r7
+ 80366c6:	f853 3c54 	ldr.w	r3, [r3, #-84]
+ 80366ca:	021a      	lsls	r2, r3, #8
+ 80366cc:	687b      	ldr	r3, [r7, #4]
+ 80366ce:	681b      	ldr	r3, [r3, #0]
+ 80366d0:	430a      	orrs	r2, r1
+ 80366d2:	f8c3 20bc 	str.w	r2, [r3, #188]	@ 0xbc
+  }
+
+  /* By default operation mode is set to Event-driven communication.
+     If Time-triggered communication is needed, user should call the
+     HAL_FDCAN_TT_ConfigOperation function just after the HAL_FDCAN_Init */
+  if (hfdcan->Instance == FDCAN1)
+ 80366d6:	687b      	ldr	r3, [r7, #4]
+ 80366d8:	681b      	ldr	r3, [r3, #0]
+ 80366da:	4a11      	ldr	r2, [pc, #68]	@ (8036720 <HAL_FDCAN_Init+0x3b8>)
+ 80366dc:	4293      	cmp	r3, r2
+ 80366de:	d107      	bne.n	80366f0 <HAL_FDCAN_Init+0x388>
+  {
+    CLEAR_BIT(hfdcan->ttcan->TTOCF, FDCAN_TTOCF_OM);
+ 80366e0:	687b      	ldr	r3, [r7, #4]
+ 80366e2:	685b      	ldr	r3, [r3, #4]
+ 80366e4:	689a      	ldr	r2, [r3, #8]
+ 80366e6:	687b      	ldr	r3, [r7, #4]
+ 80366e8:	685b      	ldr	r3, [r3, #4]
+ 80366ea:	f022 0203 	bic.w	r2, r2, #3
+ 80366ee:	609a      	str	r2, [r3, #8]
+  }
+
+  /* Initialize the Latest Tx FIFO/Queue request buffer index */
+  hfdcan->LatestTxFifoQRequest = 0U;
+ 80366f0:	687b      	ldr	r3, [r7, #4]
+ 80366f2:	2200      	movs	r2, #0
+ 80366f4:	f8c3 2094 	str.w	r2, [r3, #148]	@ 0x94
+
+  /* Initialize the error code */
+  hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE;
+ 80366f8:	687b      	ldr	r3, [r7, #4]
+ 80366fa:	2200      	movs	r2, #0
+ 80366fc:	f8c3 209c 	str.w	r2, [r3, #156]	@ 0x9c
+
+  /* Initialize the FDCAN state */
+  hfdcan->State = HAL_FDCAN_STATE_READY;
+ 8036700:	687b      	ldr	r3, [r7, #4]
+ 8036702:	2201      	movs	r2, #1
+ 8036704:	f883 2098 	strb.w	r2, [r3, #152]	@ 0x98
+
+  /* Calculate each RAM block address */
+  status = FDCAN_CalcultateRamBlockAddresses(hfdcan);
+ 8036708:	6878      	ldr	r0, [r7, #4]
+ 803670a:	f000 fd63 	bl	80371d4 <FDCAN_CalcultateRamBlockAddresses>
+ 803670e:	4603      	mov	r3, r0
+ 8036710:	f887 305b 	strb.w	r3, [r7, #91]	@ 0x5b
+
+  /* Return function status */
+  return status;
+ 8036714:	f897 305b 	ldrb.w	r3, [r7, #91]	@ 0x5b
+}
+ 8036718:	4618      	mov	r0, r3
+ 803671a:	3760      	adds	r7, #96	@ 0x60
+ 803671c:	46bd      	mov	sp, r7
+ 803671e:	bd80      	pop	{r7, pc}
+ 8036720:	4000a000 	.word	0x4000a000
+
+08036724 <HAL_FDCAN_Start>:
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan)
+{
+ 8036724:	b480      	push	{r7}
+ 8036726:	b083      	sub	sp, #12
+ 8036728:	af00      	add	r7, sp, #0
+ 803672a:	6078      	str	r0, [r7, #4]
+  if (hfdcan->State == HAL_FDCAN_STATE_READY)
+ 803672c:	687b      	ldr	r3, [r7, #4]
+ 803672e:	f893 3098 	ldrb.w	r3, [r3, #152]	@ 0x98
+ 8036732:	b2db      	uxtb	r3, r3
+ 8036734:	2b01      	cmp	r3, #1
+ 8036736:	d111      	bne.n	803675c <HAL_FDCAN_Start+0x38>
+  {
+    /* Change FDCAN peripheral state */
+    hfdcan->State = HAL_FDCAN_STATE_BUSY;
+ 8036738:	687b      	ldr	r3, [r7, #4]
+ 803673a:	2202      	movs	r2, #2
+ 803673c:	f883 2098 	strb.w	r2, [r3, #152]	@ 0x98
+
+    /* Request leave initialisation */
+    CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
+ 8036740:	687b      	ldr	r3, [r7, #4]
+ 8036742:	681b      	ldr	r3, [r3, #0]
+ 8036744:	699a      	ldr	r2, [r3, #24]
+ 8036746:	687b      	ldr	r3, [r7, #4]
+ 8036748:	681b      	ldr	r3, [r3, #0]
+ 803674a:	f022 0201 	bic.w	r2, r2, #1
+ 803674e:	619a      	str	r2, [r3, #24]
+
+    /* Reset the FDCAN ErrorCode */
+    hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE;
+ 8036750:	687b      	ldr	r3, [r7, #4]
+ 8036752:	2200      	movs	r2, #0
+ 8036754:	f8c3 209c 	str.w	r2, [r3, #156]	@ 0x9c
+
+    /* Return function status */
+    return HAL_OK;
+ 8036758:	2300      	movs	r3, #0
+ 803675a:	e008      	b.n	803676e <HAL_FDCAN_Start+0x4a>
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY;
+ 803675c:	687b      	ldr	r3, [r7, #4]
+ 803675e:	f8d3 309c 	ldr.w	r3, [r3, #156]	@ 0x9c
+ 8036762:	f043 0204 	orr.w	r2, r3, #4
+ 8036766:	687b      	ldr	r3, [r7, #4]
+ 8036768:	f8c3 209c 	str.w	r2, [r3, #156]	@ 0x9c
+
+    return HAL_ERROR;
+ 803676c:	2301      	movs	r3, #1
+  }
+}
+ 803676e:	4618      	mov	r0, r3
+ 8036770:	370c      	adds	r7, #12
+ 8036772:	46bd      	mov	sp, r7
+ 8036774:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8036778:	4770      	bx	lr
+
+0803677a <HAL_FDCAN_AddMessageToTxFifoQ>:
+  * @param  pTxData pointer to a buffer containing the payload of the Tx frame.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader,
+                                                const uint8_t *pTxData)
+{
+ 803677a:	b580      	push	{r7, lr}
+ 803677c:	b086      	sub	sp, #24
+ 803677e:	af00      	add	r7, sp, #0
+ 8036780:	60f8      	str	r0, [r7, #12]
+ 8036782:	60b9      	str	r1, [r7, #8]
+ 8036784:	607a      	str	r2, [r7, #4]
+  assert_param(IS_FDCAN_BRS(pTxHeader->BitRateSwitch));
+  assert_param(IS_FDCAN_FDF(pTxHeader->FDFormat));
+  assert_param(IS_FDCAN_EFC(pTxHeader->TxEventFifoControl));
+  assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->MessageMarker, 0xFFU));
+
+  if (hfdcan->State == HAL_FDCAN_STATE_BUSY)
+ 8036786:	68fb      	ldr	r3, [r7, #12]
+ 8036788:	f893 3098 	ldrb.w	r3, [r3, #152]	@ 0x98
+ 803678c:	b2db      	uxtb	r3, r3
+ 803678e:	2b02      	cmp	r3, #2
+ 8036790:	d141      	bne.n	8036816 <HAL_FDCAN_AddMessageToTxFifoQ+0x9c>
+  {
+    /* Check that the Tx FIFO/Queue has an allocated area into the RAM */
+    if ((hfdcan->Instance->TXBC & FDCAN_TXBC_TFQS) == 0U)
+ 8036792:	68fb      	ldr	r3, [r7, #12]
+ 8036794:	681b      	ldr	r3, [r3, #0]
+ 8036796:	f8d3 30c0 	ldr.w	r3, [r3, #192]	@ 0xc0
+ 803679a:	f003 537c 	and.w	r3, r3, #1056964608	@ 0x3f000000
+ 803679e:	2b00      	cmp	r3, #0
+ 80367a0:	d109      	bne.n	80367b6 <HAL_FDCAN_AddMessageToTxFifoQ+0x3c>
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+ 80367a2:	68fb      	ldr	r3, [r7, #12]
+ 80367a4:	f8d3 309c 	ldr.w	r3, [r3, #156]	@ 0x9c
+ 80367a8:	f043 0220 	orr.w	r2, r3, #32
+ 80367ac:	68fb      	ldr	r3, [r7, #12]
+ 80367ae:	f8c3 209c 	str.w	r2, [r3, #156]	@ 0x9c
+
+      return HAL_ERROR;
+ 80367b2:	2301      	movs	r3, #1
+ 80367b4:	e038      	b.n	8036828 <HAL_FDCAN_AddMessageToTxFifoQ+0xae>
+    }
+
+    /* Check that the Tx FIFO/Queue is not full */
+    if ((hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFQF) != 0U)
+ 80367b6:	68fb      	ldr	r3, [r7, #12]
+ 80367b8:	681b      	ldr	r3, [r3, #0]
+ 80367ba:	f8d3 30c4 	ldr.w	r3, [r3, #196]	@ 0xc4
+ 80367be:	f403 1300 	and.w	r3, r3, #2097152	@ 0x200000
+ 80367c2:	2b00      	cmp	r3, #0
+ 80367c4:	d009      	beq.n	80367da <HAL_FDCAN_AddMessageToTxFifoQ+0x60>
+    {
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_FULL;
+ 80367c6:	68fb      	ldr	r3, [r7, #12]
+ 80367c8:	f8d3 309c 	ldr.w	r3, [r3, #156]	@ 0x9c
+ 80367cc:	f443 7200 	orr.w	r2, r3, #512	@ 0x200
+ 80367d0:	68fb      	ldr	r3, [r7, #12]
+ 80367d2:	f8c3 209c 	str.w	r2, [r3, #156]	@ 0x9c
+
+      return HAL_ERROR;
+ 80367d6:	2301      	movs	r3, #1
+ 80367d8:	e026      	b.n	8036828 <HAL_FDCAN_AddMessageToTxFifoQ+0xae>
+    }
+    else
+    {
+      /* Retrieve the Tx FIFO PutIndex */
+      PutIndex = ((hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFQPI) >> FDCAN_TXFQS_TFQPI_Pos);
+ 80367da:	68fb      	ldr	r3, [r7, #12]
+ 80367dc:	681b      	ldr	r3, [r3, #0]
+ 80367de:	f8d3 30c4 	ldr.w	r3, [r3, #196]	@ 0xc4
+ 80367e2:	0c1b      	lsrs	r3, r3, #16
+ 80367e4:	f003 031f 	and.w	r3, r3, #31
+ 80367e8:	617b      	str	r3, [r7, #20]
+
+      /* Add the message to the Tx FIFO/Queue */
+      FDCAN_CopyMessageToRAM(hfdcan, pTxHeader, pTxData, PutIndex);
+ 80367ea:	697b      	ldr	r3, [r7, #20]
+ 80367ec:	687a      	ldr	r2, [r7, #4]
+ 80367ee:	68b9      	ldr	r1, [r7, #8]
+ 80367f0:	68f8      	ldr	r0, [r7, #12]
+ 80367f2:	f000 fe75 	bl	80374e0 <FDCAN_CopyMessageToRAM>
+
+      /* Activate the corresponding transmission request */
+      hfdcan->Instance->TXBAR = ((uint32_t)1 << PutIndex);
+ 80367f6:	68fb      	ldr	r3, [r7, #12]
+ 80367f8:	681b      	ldr	r3, [r3, #0]
+ 80367fa:	2101      	movs	r1, #1
+ 80367fc:	697a      	ldr	r2, [r7, #20]
+ 80367fe:	fa01 f202 	lsl.w	r2, r1, r2
+ 8036802:	f8c3 20d0 	str.w	r2, [r3, #208]	@ 0xd0
+
+      /* Store the Latest Tx FIFO/Queue Request Buffer Index */
+      hfdcan->LatestTxFifoQRequest = ((uint32_t)1 << PutIndex);
+ 8036806:	2201      	movs	r2, #1
+ 8036808:	697b      	ldr	r3, [r7, #20]
+ 803680a:	409a      	lsls	r2, r3
+ 803680c:	68fb      	ldr	r3, [r7, #12]
+ 803680e:	f8c3 2094 	str.w	r2, [r3, #148]	@ 0x94
+    }
+
+    /* Return function status */
+    return HAL_OK;
+ 8036812:	2300      	movs	r3, #0
+ 8036814:	e008      	b.n	8036828 <HAL_FDCAN_AddMessageToTxFifoQ+0xae>
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
+ 8036816:	68fb      	ldr	r3, [r7, #12]
+ 8036818:	f8d3 309c 	ldr.w	r3, [r3, #156]	@ 0x9c
+ 803681c:	f043 0208 	orr.w	r2, r3, #8
+ 8036820:	68fb      	ldr	r3, [r7, #12]
+ 8036822:	f8c3 209c 	str.w	r2, [r3, #156]	@ 0x9c
+
+    return HAL_ERROR;
+ 8036826:	2301      	movs	r3, #1
+  }
+}
+ 8036828:	4618      	mov	r0, r3
+ 803682a:	3718      	adds	r7, #24
+ 803682c:	46bd      	mov	sp, r7
+ 803682e:	bd80      	pop	{r7, pc}
+
+08036830 <HAL_FDCAN_GetRxMessage>:
+  * @param  pRxData pointer to a buffer where the payload of the Rx frame will be stored.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation,
+                                         FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData)
+{
+ 8036830:	b480      	push	{r7}
+ 8036832:	b08b      	sub	sp, #44	@ 0x2c
+ 8036834:	af00      	add	r7, sp, #0
+ 8036836:	60f8      	str	r0, [r7, #12]
+ 8036838:	60b9      	str	r1, [r7, #8]
+ 803683a:	607a      	str	r2, [r7, #4]
+ 803683c:	603b      	str	r3, [r7, #0]
+  uint32_t *RxAddress;
+  uint8_t  *pData;
+  uint32_t ByteCounter;
+  uint32_t GetIndex = 0;
+ 803683e:	2300      	movs	r3, #0
+ 8036840:	61fb      	str	r3, [r7, #28]
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+ 8036842:	68fb      	ldr	r3, [r7, #12]
+ 8036844:	f893 3098 	ldrb.w	r3, [r3, #152]	@ 0x98
+ 8036848:	76fb      	strb	r3, [r7, #27]
+
+  if (state == HAL_FDCAN_STATE_BUSY)
+ 803684a:	7efb      	ldrb	r3, [r7, #27]
+ 803684c:	2b02      	cmp	r3, #2
+ 803684e:	f040 8149 	bne.w	8036ae4 <HAL_FDCAN_GetRxMessage+0x2b4>
+  {
+    if (RxLocation == FDCAN_RX_FIFO0) /* Rx element is assigned to the Rx FIFO 0 */
+ 8036852:	68bb      	ldr	r3, [r7, #8]
+ 8036854:	2b40      	cmp	r3, #64	@ 0x40
+ 8036856:	d14c      	bne.n	80368f2 <HAL_FDCAN_GetRxMessage+0xc2>
+    {
+      /* Check that the Rx FIFO 0 has an allocated area into the RAM */
+      if ((hfdcan->Instance->RXF0C & FDCAN_RXF0C_F0S) == 0U)
+ 8036858:	68fb      	ldr	r3, [r7, #12]
+ 803685a:	681b      	ldr	r3, [r3, #0]
+ 803685c:	f8d3 30a0 	ldr.w	r3, [r3, #160]	@ 0xa0
+ 8036860:	f403 03fe 	and.w	r3, r3, #8323072	@ 0x7f0000
+ 8036864:	2b00      	cmp	r3, #0
+ 8036866:	d109      	bne.n	803687c <HAL_FDCAN_GetRxMessage+0x4c>
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+ 8036868:	68fb      	ldr	r3, [r7, #12]
+ 803686a:	f8d3 309c 	ldr.w	r3, [r3, #156]	@ 0x9c
+ 803686e:	f043 0220 	orr.w	r2, r3, #32
+ 8036872:	68fb      	ldr	r3, [r7, #12]
+ 8036874:	f8c3 209c 	str.w	r2, [r3, #156]	@ 0x9c
+
+        return HAL_ERROR;
+ 8036878:	2301      	movs	r3, #1
+ 803687a:	e13c      	b.n	8036af6 <HAL_FDCAN_GetRxMessage+0x2c6>
+      }
+
+      /* Check that the Rx FIFO 0 is not empty */
+      if ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0FL) == 0U)
+ 803687c:	68fb      	ldr	r3, [r7, #12]
+ 803687e:	681b      	ldr	r3, [r3, #0]
+ 8036880:	f8d3 30a4 	ldr.w	r3, [r3, #164]	@ 0xa4
+ 8036884:	f003 037f 	and.w	r3, r3, #127	@ 0x7f
+ 8036888:	2b00      	cmp	r3, #0
+ 803688a:	d109      	bne.n	80368a0 <HAL_FDCAN_GetRxMessage+0x70>
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY;
+ 803688c:	68fb      	ldr	r3, [r7, #12]
+ 803688e:	f8d3 309c 	ldr.w	r3, [r3, #156]	@ 0x9c
+ 8036892:	f443 7280 	orr.w	r2, r3, #256	@ 0x100
+ 8036896:	68fb      	ldr	r3, [r7, #12]
+ 8036898:	f8c3 209c 	str.w	r2, [r3, #156]	@ 0x9c
+
+        return HAL_ERROR;
+ 803689c:	2301      	movs	r3, #1
+ 803689e:	e12a      	b.n	8036af6 <HAL_FDCAN_GetRxMessage+0x2c6>
+      }
+      else
+      {
+        /* Check that the Rx FIFO 0 is full & overwrite mode is on */
+        if (((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0F) >> FDCAN_RXF0S_F0F_Pos) == 1U)
+ 80368a0:	68fb      	ldr	r3, [r7, #12]
+ 80368a2:	681b      	ldr	r3, [r3, #0]
+ 80368a4:	f8d3 30a4 	ldr.w	r3, [r3, #164]	@ 0xa4
+ 80368a8:	0e1b      	lsrs	r3, r3, #24
+ 80368aa:	f003 0301 	and.w	r3, r3, #1
+ 80368ae:	2b01      	cmp	r3, #1
+ 80368b0:	d10a      	bne.n	80368c8 <HAL_FDCAN_GetRxMessage+0x98>
+        {
+          if (((hfdcan->Instance->RXF0C & FDCAN_RXF0C_F0OM) >> FDCAN_RXF0C_F0OM_Pos) == FDCAN_RX_FIFO_OVERWRITE)
+ 80368b2:	68fb      	ldr	r3, [r7, #12]
+ 80368b4:	681b      	ldr	r3, [r3, #0]
+ 80368b6:	f8d3 30a0 	ldr.w	r3, [r3, #160]	@ 0xa0
+ 80368ba:	0fdb      	lsrs	r3, r3, #31
+ 80368bc:	f003 0301 	and.w	r3, r3, #1
+ 80368c0:	2b01      	cmp	r3, #1
+ 80368c2:	d101      	bne.n	80368c8 <HAL_FDCAN_GetRxMessage+0x98>
+          {
+            /* When overwrite status is on discard first message in FIFO */
+            GetIndex = 1U;
+ 80368c4:	2301      	movs	r3, #1
+ 80368c6:	61fb      	str	r3, [r7, #28]
+          }
+        }
+
+        /* Calculate Rx FIFO 0 element index */
+        GetIndex += ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0GI) >> FDCAN_RXF0S_F0GI_Pos);
+ 80368c8:	68fb      	ldr	r3, [r7, #12]
+ 80368ca:	681b      	ldr	r3, [r3, #0]
+ 80368cc:	f8d3 30a4 	ldr.w	r3, [r3, #164]	@ 0xa4
+ 80368d0:	0a1b      	lsrs	r3, r3, #8
+ 80368d2:	f003 033f 	and.w	r3, r3, #63	@ 0x3f
+ 80368d6:	69fa      	ldr	r2, [r7, #28]
+ 80368d8:	4413      	add	r3, r2
+ 80368da:	61fb      	str	r3, [r7, #28]
+
+        /* Calculate Rx FIFO 0 element address */
+        RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO0SA + (GetIndex * hfdcan->Init.RxFifo0ElmtSize * 4U));
+ 80368dc:	68fb      	ldr	r3, [r7, #12]
+ 80368de:	6f5a      	ldr	r2, [r3, #116]	@ 0x74
+ 80368e0:	68fb      	ldr	r3, [r7, #12]
+ 80368e2:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
+ 80368e4:	69f9      	ldr	r1, [r7, #28]
+ 80368e6:	fb01 f303 	mul.w	r3, r1, r3
+ 80368ea:	009b      	lsls	r3, r3, #2
+ 80368ec:	4413      	add	r3, r2
+ 80368ee:	627b      	str	r3, [r7, #36]	@ 0x24
+ 80368f0:	e068      	b.n	80369c4 <HAL_FDCAN_GetRxMessage+0x194>
+      }
+    }
+    else if (RxLocation == FDCAN_RX_FIFO1) /* Rx element is assigned to the Rx FIFO 1 */
+ 80368f2:	68bb      	ldr	r3, [r7, #8]
+ 80368f4:	2b41      	cmp	r3, #65	@ 0x41
+ 80368f6:	d14c      	bne.n	8036992 <HAL_FDCAN_GetRxMessage+0x162>
+    {
+      /* Check that the Rx FIFO 1 has an allocated area into the RAM */
+      if ((hfdcan->Instance->RXF1C & FDCAN_RXF1C_F1S) == 0U)
+ 80368f8:	68fb      	ldr	r3, [r7, #12]
+ 80368fa:	681b      	ldr	r3, [r3, #0]
+ 80368fc:	f8d3 30b0 	ldr.w	r3, [r3, #176]	@ 0xb0
+ 8036900:	f403 03fe 	and.w	r3, r3, #8323072	@ 0x7f0000
+ 8036904:	2b00      	cmp	r3, #0
+ 8036906:	d109      	bne.n	803691c <HAL_FDCAN_GetRxMessage+0xec>
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+ 8036908:	68fb      	ldr	r3, [r7, #12]
+ 803690a:	f8d3 309c 	ldr.w	r3, [r3, #156]	@ 0x9c
+ 803690e:	f043 0220 	orr.w	r2, r3, #32
+ 8036912:	68fb      	ldr	r3, [r7, #12]
+ 8036914:	f8c3 209c 	str.w	r2, [r3, #156]	@ 0x9c
+
+        return HAL_ERROR;
+ 8036918:	2301      	movs	r3, #1
+ 803691a:	e0ec      	b.n	8036af6 <HAL_FDCAN_GetRxMessage+0x2c6>
+      }
+
+      /* Check that the Rx FIFO 1 is not empty */
+      if ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1FL) == 0U)
+ 803691c:	68fb      	ldr	r3, [r7, #12]
+ 803691e:	681b      	ldr	r3, [r3, #0]
+ 8036920:	f8d3 30b4 	ldr.w	r3, [r3, #180]	@ 0xb4
+ 8036924:	f003 037f 	and.w	r3, r3, #127	@ 0x7f
+ 8036928:	2b00      	cmp	r3, #0
+ 803692a:	d109      	bne.n	8036940 <HAL_FDCAN_GetRxMessage+0x110>
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY;
+ 803692c:	68fb      	ldr	r3, [r7, #12]
+ 803692e:	f8d3 309c 	ldr.w	r3, [r3, #156]	@ 0x9c
+ 8036932:	f443 7280 	orr.w	r2, r3, #256	@ 0x100
+ 8036936:	68fb      	ldr	r3, [r7, #12]
+ 8036938:	f8c3 209c 	str.w	r2, [r3, #156]	@ 0x9c
+
+        return HAL_ERROR;
+ 803693c:	2301      	movs	r3, #1
+ 803693e:	e0da      	b.n	8036af6 <HAL_FDCAN_GetRxMessage+0x2c6>
+      }
+      else
+      {
+        /* Check that the Rx FIFO 1 is full & overwrite mode is on */
+        if (((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1F) >> FDCAN_RXF1S_F1F_Pos) == 1U)
+ 8036940:	68fb      	ldr	r3, [r7, #12]
+ 8036942:	681b      	ldr	r3, [r3, #0]
+ 8036944:	f8d3 30b4 	ldr.w	r3, [r3, #180]	@ 0xb4
+ 8036948:	0e1b      	lsrs	r3, r3, #24
+ 803694a:	f003 0301 	and.w	r3, r3, #1
+ 803694e:	2b01      	cmp	r3, #1
+ 8036950:	d10a      	bne.n	8036968 <HAL_FDCAN_GetRxMessage+0x138>
+        {
+          if (((hfdcan->Instance->RXF1C & FDCAN_RXF1C_F1OM) >> FDCAN_RXF1C_F1OM_Pos) == FDCAN_RX_FIFO_OVERWRITE)
+ 8036952:	68fb      	ldr	r3, [r7, #12]
+ 8036954:	681b      	ldr	r3, [r3, #0]
+ 8036956:	f8d3 30b0 	ldr.w	r3, [r3, #176]	@ 0xb0
+ 803695a:	0fdb      	lsrs	r3, r3, #31
+ 803695c:	f003 0301 	and.w	r3, r3, #1
+ 8036960:	2b01      	cmp	r3, #1
+ 8036962:	d101      	bne.n	8036968 <HAL_FDCAN_GetRxMessage+0x138>
+          {
+            /* When overwrite status is on discard first message in FIFO */
+            GetIndex = 1U;
+ 8036964:	2301      	movs	r3, #1
+ 8036966:	61fb      	str	r3, [r7, #28]
+          }
+        }
+
+        /* Calculate Rx FIFO 1 element index */
+        GetIndex += ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1GI) >> FDCAN_RXF1S_F1GI_Pos);
+ 8036968:	68fb      	ldr	r3, [r7, #12]
+ 803696a:	681b      	ldr	r3, [r3, #0]
+ 803696c:	f8d3 30b4 	ldr.w	r3, [r3, #180]	@ 0xb4
+ 8036970:	0a1b      	lsrs	r3, r3, #8
+ 8036972:	f003 033f 	and.w	r3, r3, #63	@ 0x3f
+ 8036976:	69fa      	ldr	r2, [r7, #28]
+ 8036978:	4413      	add	r3, r2
+ 803697a:	61fb      	str	r3, [r7, #28]
+
+        /* Calculate Rx FIFO 1 element address */
+        RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO1SA + (GetIndex * hfdcan->Init.RxFifo1ElmtSize * 4U));
+ 803697c:	68fb      	ldr	r3, [r7, #12]
+ 803697e:	6f9a      	ldr	r2, [r3, #120]	@ 0x78
+ 8036980:	68fb      	ldr	r3, [r7, #12]
+ 8036982:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
+ 8036984:	69f9      	ldr	r1, [r7, #28]
+ 8036986:	fb01 f303 	mul.w	r3, r1, r3
+ 803698a:	009b      	lsls	r3, r3, #2
+ 803698c:	4413      	add	r3, r2
+ 803698e:	627b      	str	r3, [r7, #36]	@ 0x24
+ 8036990:	e018      	b.n	80369c4 <HAL_FDCAN_GetRxMessage+0x194>
+      }
+    }
+    else /* Rx element is assigned to a dedicated Rx buffer */
+    {
+      /* Check that the selected buffer has an allocated area into the RAM */
+      if (RxLocation >= hfdcan->Init.RxBuffersNbr)
+ 8036992:	68fb      	ldr	r3, [r7, #12]
+ 8036994:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
+ 8036996:	68ba      	ldr	r2, [r7, #8]
+ 8036998:	429a      	cmp	r2, r3
+ 803699a:	d309      	bcc.n	80369b0 <HAL_FDCAN_GetRxMessage+0x180>
+      {
+        /* Update error code */
+        hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+ 803699c:	68fb      	ldr	r3, [r7, #12]
+ 803699e:	f8d3 309c 	ldr.w	r3, [r3, #156]	@ 0x9c
+ 80369a2:	f043 0220 	orr.w	r2, r3, #32
+ 80369a6:	68fb      	ldr	r3, [r7, #12]
+ 80369a8:	f8c3 209c 	str.w	r2, [r3, #156]	@ 0x9c
+
+        return HAL_ERROR;
+ 80369ac:	2301      	movs	r3, #1
+ 80369ae:	e0a2      	b.n	8036af6 <HAL_FDCAN_GetRxMessage+0x2c6>
+      }
+      else
+      {
+        /* Calculate Rx buffer address */
+        RxAddress = (uint32_t *)(hfdcan->msgRam.RxBufferSA + (RxLocation * hfdcan->Init.RxBufferSize * 4U));
+ 80369b0:	68fb      	ldr	r3, [r7, #12]
+ 80369b2:	6fda      	ldr	r2, [r3, #124]	@ 0x7c
+ 80369b4:	68fb      	ldr	r3, [r7, #12]
+ 80369b6:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
+ 80369b8:	68b9      	ldr	r1, [r7, #8]
+ 80369ba:	fb01 f303 	mul.w	r3, r1, r3
+ 80369be:	009b      	lsls	r3, r3, #2
+ 80369c0:	4413      	add	r3, r2
+ 80369c2:	627b      	str	r3, [r7, #36]	@ 0x24
+      }
+    }
+
+    /* Retrieve IdType */
+    pRxHeader->IdType = *RxAddress & FDCAN_ELEMENT_MASK_XTD;
+ 80369c4:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 80369c6:	681b      	ldr	r3, [r3, #0]
+ 80369c8:	f003 4280 	and.w	r2, r3, #1073741824	@ 0x40000000
+ 80369cc:	687b      	ldr	r3, [r7, #4]
+ 80369ce:	605a      	str	r2, [r3, #4]
+
+    /* Retrieve Identifier */
+    if (pRxHeader->IdType == FDCAN_STANDARD_ID) /* Standard ID element */
+ 80369d0:	687b      	ldr	r3, [r7, #4]
+ 80369d2:	685b      	ldr	r3, [r3, #4]
+ 80369d4:	2b00      	cmp	r3, #0
+ 80369d6:	d107      	bne.n	80369e8 <HAL_FDCAN_GetRxMessage+0x1b8>
+    {
+      pRxHeader->Identifier = ((*RxAddress & FDCAN_ELEMENT_MASK_STDID) >> 18U);
+ 80369d8:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 80369da:	681b      	ldr	r3, [r3, #0]
+ 80369dc:	0c9b      	lsrs	r3, r3, #18
+ 80369de:	f3c3 020a 	ubfx	r2, r3, #0, #11
+ 80369e2:	687b      	ldr	r3, [r7, #4]
+ 80369e4:	601a      	str	r2, [r3, #0]
+ 80369e6:	e005      	b.n	80369f4 <HAL_FDCAN_GetRxMessage+0x1c4>
+    }
+    else /* Extended ID element */
+    {
+      pRxHeader->Identifier = (*RxAddress & FDCAN_ELEMENT_MASK_EXTID);
+ 80369e8:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 80369ea:	681b      	ldr	r3, [r3, #0]
+ 80369ec:	f023 4260 	bic.w	r2, r3, #3758096384	@ 0xe0000000
+ 80369f0:	687b      	ldr	r3, [r7, #4]
+ 80369f2:	601a      	str	r2, [r3, #0]
+    }
+
+    /* Retrieve RxFrameType */
+    pRxHeader->RxFrameType = (*RxAddress & FDCAN_ELEMENT_MASK_RTR);
+ 80369f4:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 80369f6:	681b      	ldr	r3, [r3, #0]
+ 80369f8:	f003 5200 	and.w	r2, r3, #536870912	@ 0x20000000
+ 80369fc:	687b      	ldr	r3, [r7, #4]
+ 80369fe:	609a      	str	r2, [r3, #8]
+
+    /* Retrieve ErrorStateIndicator */
+    pRxHeader->ErrorStateIndicator = (*RxAddress & FDCAN_ELEMENT_MASK_ESI);
+ 8036a00:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 8036a02:	681b      	ldr	r3, [r3, #0]
+ 8036a04:	f003 4200 	and.w	r2, r3, #2147483648	@ 0x80000000
+ 8036a08:	687b      	ldr	r3, [r7, #4]
+ 8036a0a:	611a      	str	r2, [r3, #16]
+
+    /* Increment RxAddress pointer to second word of Rx FIFO element */
+    RxAddress++;
+ 8036a0c:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 8036a0e:	3304      	adds	r3, #4
+ 8036a10:	627b      	str	r3, [r7, #36]	@ 0x24
+
+    /* Retrieve RxTimestamp */
+    pRxHeader->RxTimestamp = (*RxAddress & FDCAN_ELEMENT_MASK_TS);
+ 8036a12:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 8036a14:	681b      	ldr	r3, [r3, #0]
+ 8036a16:	b29a      	uxth	r2, r3
+ 8036a18:	687b      	ldr	r3, [r7, #4]
+ 8036a1a:	61da      	str	r2, [r3, #28]
+
+    /* Retrieve DataLength */
+    pRxHeader->DataLength = ((*RxAddress & FDCAN_ELEMENT_MASK_DLC) >> 16U);
+ 8036a1c:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 8036a1e:	681b      	ldr	r3, [r3, #0]
+ 8036a20:	0c1b      	lsrs	r3, r3, #16
+ 8036a22:	f003 020f 	and.w	r2, r3, #15
+ 8036a26:	687b      	ldr	r3, [r7, #4]
+ 8036a28:	60da      	str	r2, [r3, #12]
+
+    /* Retrieve BitRateSwitch */
+    pRxHeader->BitRateSwitch = (*RxAddress & FDCAN_ELEMENT_MASK_BRS);
+ 8036a2a:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 8036a2c:	681b      	ldr	r3, [r3, #0]
+ 8036a2e:	f403 1280 	and.w	r2, r3, #1048576	@ 0x100000
+ 8036a32:	687b      	ldr	r3, [r7, #4]
+ 8036a34:	615a      	str	r2, [r3, #20]
+
+    /* Retrieve FDFormat */
+    pRxHeader->FDFormat = (*RxAddress & FDCAN_ELEMENT_MASK_FDF);
+ 8036a36:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 8036a38:	681b      	ldr	r3, [r3, #0]
+ 8036a3a:	f403 1200 	and.w	r2, r3, #2097152	@ 0x200000
+ 8036a3e:	687b      	ldr	r3, [r7, #4]
+ 8036a40:	619a      	str	r2, [r3, #24]
+
+    /* Retrieve FilterIndex */
+    pRxHeader->FilterIndex = ((*RxAddress & FDCAN_ELEMENT_MASK_FIDX) >> 24U);
+ 8036a42:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 8036a44:	681b      	ldr	r3, [r3, #0]
+ 8036a46:	0e1b      	lsrs	r3, r3, #24
+ 8036a48:	f003 027f 	and.w	r2, r3, #127	@ 0x7f
+ 8036a4c:	687b      	ldr	r3, [r7, #4]
+ 8036a4e:	621a      	str	r2, [r3, #32]
+
+    /* Retrieve NonMatchingFrame */
+    pRxHeader->IsFilterMatchingFrame = ((*RxAddress & FDCAN_ELEMENT_MASK_ANMF) >> 31U);
+ 8036a50:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 8036a52:	681b      	ldr	r3, [r3, #0]
+ 8036a54:	0fda      	lsrs	r2, r3, #31
+ 8036a56:	687b      	ldr	r3, [r7, #4]
+ 8036a58:	625a      	str	r2, [r3, #36]	@ 0x24
+
+    /* Increment RxAddress pointer to payload of Rx FIFO element */
+    RxAddress++;
+ 8036a5a:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 8036a5c:	3304      	adds	r3, #4
+ 8036a5e:	627b      	str	r3, [r7, #36]	@ 0x24
+
+    /* Retrieve Rx payload */
+    pData = (uint8_t *)RxAddress;
+ 8036a60:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 8036a62:	617b      	str	r3, [r7, #20]
+    for (ByteCounter = 0; ByteCounter < DLCtoBytes[pRxHeader->DataLength]; ByteCounter++)
+ 8036a64:	2300      	movs	r3, #0
+ 8036a66:	623b      	str	r3, [r7, #32]
+ 8036a68:	e00a      	b.n	8036a80 <HAL_FDCAN_GetRxMessage+0x250>
+    {
+      pRxData[ByteCounter] = pData[ByteCounter];
+ 8036a6a:	697a      	ldr	r2, [r7, #20]
+ 8036a6c:	6a3b      	ldr	r3, [r7, #32]
+ 8036a6e:	441a      	add	r2, r3
+ 8036a70:	6839      	ldr	r1, [r7, #0]
+ 8036a72:	6a3b      	ldr	r3, [r7, #32]
+ 8036a74:	440b      	add	r3, r1
+ 8036a76:	7812      	ldrb	r2, [r2, #0]
+ 8036a78:	701a      	strb	r2, [r3, #0]
+    for (ByteCounter = 0; ByteCounter < DLCtoBytes[pRxHeader->DataLength]; ByteCounter++)
+ 8036a7a:	6a3b      	ldr	r3, [r7, #32]
+ 8036a7c:	3301      	adds	r3, #1
+ 8036a7e:	623b      	str	r3, [r7, #32]
+ 8036a80:	687b      	ldr	r3, [r7, #4]
+ 8036a82:	68db      	ldr	r3, [r3, #12]
+ 8036a84:	4a1f      	ldr	r2, [pc, #124]	@ (8036b04 <HAL_FDCAN_GetRxMessage+0x2d4>)
+ 8036a86:	5cd3      	ldrb	r3, [r2, r3]
+ 8036a88:	461a      	mov	r2, r3
+ 8036a8a:	6a3b      	ldr	r3, [r7, #32]
+ 8036a8c:	4293      	cmp	r3, r2
+ 8036a8e:	d3ec      	bcc.n	8036a6a <HAL_FDCAN_GetRxMessage+0x23a>
+    }
+
+    if (RxLocation == FDCAN_RX_FIFO0) /* Rx element is assigned to the Rx FIFO 0 */
+ 8036a90:	68bb      	ldr	r3, [r7, #8]
+ 8036a92:	2b40      	cmp	r3, #64	@ 0x40
+ 8036a94:	d105      	bne.n	8036aa2 <HAL_FDCAN_GetRxMessage+0x272>
+    {
+      /* Acknowledge the Rx FIFO 0 that the oldest element is read so that it increments the GetIndex */
+      hfdcan->Instance->RXF0A = GetIndex;
+ 8036a96:	68fb      	ldr	r3, [r7, #12]
+ 8036a98:	681b      	ldr	r3, [r3, #0]
+ 8036a9a:	69fa      	ldr	r2, [r7, #28]
+ 8036a9c:	f8c3 20a8 	str.w	r2, [r3, #168]	@ 0xa8
+ 8036aa0:	e01e      	b.n	8036ae0 <HAL_FDCAN_GetRxMessage+0x2b0>
+    }
+    else if (RxLocation == FDCAN_RX_FIFO1) /* Rx element is assigned to the Rx FIFO 1 */
+ 8036aa2:	68bb      	ldr	r3, [r7, #8]
+ 8036aa4:	2b41      	cmp	r3, #65	@ 0x41
+ 8036aa6:	d105      	bne.n	8036ab4 <HAL_FDCAN_GetRxMessage+0x284>
+    {
+      /* Acknowledge the Rx FIFO 1 that the oldest element is read so that it increments the GetIndex */
+      hfdcan->Instance->RXF1A = GetIndex;
+ 8036aa8:	68fb      	ldr	r3, [r7, #12]
+ 8036aaa:	681b      	ldr	r3, [r3, #0]
+ 8036aac:	69fa      	ldr	r2, [r7, #28]
+ 8036aae:	f8c3 20b8 	str.w	r2, [r3, #184]	@ 0xb8
+ 8036ab2:	e015      	b.n	8036ae0 <HAL_FDCAN_GetRxMessage+0x2b0>
+    }
+    else /* Rx element is assigned to a dedicated Rx buffer */
+    {
+      /* Clear the New Data flag of the current Rx buffer */
+      if (RxLocation < FDCAN_RX_BUFFER32)
+ 8036ab4:	68bb      	ldr	r3, [r7, #8]
+ 8036ab6:	2b1f      	cmp	r3, #31
+ 8036ab8:	d808      	bhi.n	8036acc <HAL_FDCAN_GetRxMessage+0x29c>
+      {
+        hfdcan->Instance->NDAT1 = ((uint32_t)1U << RxLocation);
+ 8036aba:	68fb      	ldr	r3, [r7, #12]
+ 8036abc:	681b      	ldr	r3, [r3, #0]
+ 8036abe:	2101      	movs	r1, #1
+ 8036ac0:	68ba      	ldr	r2, [r7, #8]
+ 8036ac2:	fa01 f202 	lsl.w	r2, r1, r2
+ 8036ac6:	f8c3 2098 	str.w	r2, [r3, #152]	@ 0x98
+ 8036aca:	e009      	b.n	8036ae0 <HAL_FDCAN_GetRxMessage+0x2b0>
+      }
+      else /* FDCAN_RX_BUFFER32 <= RxLocation <= FDCAN_RX_BUFFER63 */
+      {
+        hfdcan->Instance->NDAT2 = ((uint32_t)1U << (RxLocation & 0x1FU));
+ 8036acc:	68bb      	ldr	r3, [r7, #8]
+ 8036ace:	f003 021f 	and.w	r2, r3, #31
+ 8036ad2:	68fb      	ldr	r3, [r7, #12]
+ 8036ad4:	681b      	ldr	r3, [r3, #0]
+ 8036ad6:	2101      	movs	r1, #1
+ 8036ad8:	fa01 f202 	lsl.w	r2, r1, r2
+ 8036adc:	f8c3 209c 	str.w	r2, [r3, #156]	@ 0x9c
+      }
+    }
+
+    /* Return function status */
+    return HAL_OK;
+ 8036ae0:	2300      	movs	r3, #0
+ 8036ae2:	e008      	b.n	8036af6 <HAL_FDCAN_GetRxMessage+0x2c6>
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;
+ 8036ae4:	68fb      	ldr	r3, [r7, #12]
+ 8036ae6:	f8d3 309c 	ldr.w	r3, [r3, #156]	@ 0x9c
+ 8036aea:	f043 0208 	orr.w	r2, r3, #8
+ 8036aee:	68fb      	ldr	r3, [r7, #12]
+ 8036af0:	f8c3 209c 	str.w	r2, [r3, #156]	@ 0x9c
+
+    return HAL_ERROR;
+ 8036af4:	2301      	movs	r3, #1
+  }
+}
+ 8036af6:	4618      	mov	r0, r3
+ 8036af8:	372c      	adds	r7, #44	@ 0x2c
+ 8036afa:	46bd      	mov	sp, r7
+ 8036afc:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8036b00:	4770      	bx	lr
+ 8036b02:	bf00      	nop
+ 8036b04:	08041c70 	.word	0x08041c70
+
+08036b08 <HAL_FDCAN_ActivateNotification>:
+  *           - FDCAN_IT_TX_ABORT_COMPLETE
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs,
+                                                 uint32_t BufferIndexes)
+{
+ 8036b08:	b480      	push	{r7}
+ 8036b0a:	b087      	sub	sp, #28
+ 8036b0c:	af00      	add	r7, sp, #0
+ 8036b0e:	60f8      	str	r0, [r7, #12]
+ 8036b10:	60b9      	str	r1, [r7, #8]
+ 8036b12:	607a      	str	r2, [r7, #4]
+  HAL_FDCAN_StateTypeDef state = hfdcan->State;
+ 8036b14:	68fb      	ldr	r3, [r7, #12]
+ 8036b16:	f893 3098 	ldrb.w	r3, [r3, #152]	@ 0x98
+ 8036b1a:	75fb      	strb	r3, [r7, #23]
+
+  /* Check function parameters */
+  assert_param(IS_FDCAN_IT(ActiveITs));
+
+  if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY))
+ 8036b1c:	7dfb      	ldrb	r3, [r7, #23]
+ 8036b1e:	2b01      	cmp	r3, #1
+ 8036b20:	d002      	beq.n	8036b28 <HAL_FDCAN_ActivateNotification+0x20>
+ 8036b22:	7dfb      	ldrb	r3, [r7, #23]
+ 8036b24:	2b02      	cmp	r3, #2
+ 8036b26:	d155      	bne.n	8036bd4 <HAL_FDCAN_ActivateNotification+0xcc>
+  {
+    /* Enable Interrupt lines */
+    if ((ActiveITs & hfdcan->Instance->ILS) == 0U)
+ 8036b28:	68fb      	ldr	r3, [r7, #12]
+ 8036b2a:	681b      	ldr	r3, [r3, #0]
+ 8036b2c:	6d9a      	ldr	r2, [r3, #88]	@ 0x58
+ 8036b2e:	68bb      	ldr	r3, [r7, #8]
+ 8036b30:	4013      	ands	r3, r2
+ 8036b32:	2b00      	cmp	r3, #0
+ 8036b34:	d108      	bne.n	8036b48 <HAL_FDCAN_ActivateNotification+0x40>
+    {
+      /* Enable Interrupt line 0 */
+      SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0);
+ 8036b36:	68fb      	ldr	r3, [r7, #12]
+ 8036b38:	681b      	ldr	r3, [r3, #0]
+ 8036b3a:	6dda      	ldr	r2, [r3, #92]	@ 0x5c
+ 8036b3c:	68fb      	ldr	r3, [r7, #12]
+ 8036b3e:	681b      	ldr	r3, [r3, #0]
+ 8036b40:	f042 0201 	orr.w	r2, r2, #1
+ 8036b44:	65da      	str	r2, [r3, #92]	@ 0x5c
+ 8036b46:	e014      	b.n	8036b72 <HAL_FDCAN_ActivateNotification+0x6a>
+    }
+    else if ((ActiveITs & hfdcan->Instance->ILS) == ActiveITs)
+ 8036b48:	68fb      	ldr	r3, [r7, #12]
+ 8036b4a:	681b      	ldr	r3, [r3, #0]
+ 8036b4c:	6d9a      	ldr	r2, [r3, #88]	@ 0x58
+ 8036b4e:	68bb      	ldr	r3, [r7, #8]
+ 8036b50:	4013      	ands	r3, r2
+ 8036b52:	68ba      	ldr	r2, [r7, #8]
+ 8036b54:	429a      	cmp	r2, r3
+ 8036b56:	d108      	bne.n	8036b6a <HAL_FDCAN_ActivateNotification+0x62>
+    {
+      /* Enable Interrupt line 1 */
+      SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1);
+ 8036b58:	68fb      	ldr	r3, [r7, #12]
+ 8036b5a:	681b      	ldr	r3, [r3, #0]
+ 8036b5c:	6dda      	ldr	r2, [r3, #92]	@ 0x5c
+ 8036b5e:	68fb      	ldr	r3, [r7, #12]
+ 8036b60:	681b      	ldr	r3, [r3, #0]
+ 8036b62:	f042 0202 	orr.w	r2, r2, #2
+ 8036b66:	65da      	str	r2, [r3, #92]	@ 0x5c
+ 8036b68:	e003      	b.n	8036b72 <HAL_FDCAN_ActivateNotification+0x6a>
+    }
+    else
+    {
+      /* Enable Interrupt lines 0 and 1 */
+      hfdcan->Instance->ILE = (FDCAN_INTERRUPT_LINE0 | FDCAN_INTERRUPT_LINE1);
+ 8036b6a:	68fb      	ldr	r3, [r7, #12]
+ 8036b6c:	681b      	ldr	r3, [r3, #0]
+ 8036b6e:	2203      	movs	r2, #3
+ 8036b70:	65da      	str	r2, [r3, #92]	@ 0x5c
+    }
+
+    if ((ActiveITs & FDCAN_IT_TX_COMPLETE) != 0U)
+ 8036b72:	68bb      	ldr	r3, [r7, #8]
+ 8036b74:	f403 7300 	and.w	r3, r3, #512	@ 0x200
+ 8036b78:	2b00      	cmp	r3, #0
+ 8036b7a:	d009      	beq.n	8036b90 <HAL_FDCAN_ActivateNotification+0x88>
+    {
+      /* Enable Tx Buffer Transmission Interrupt to set TC flag in IR register,
+         but interrupt will only occur if TC is enabled in IE register */
+      SET_BIT(hfdcan->Instance->TXBTIE, BufferIndexes);
+ 8036b7c:	68fb      	ldr	r3, [r7, #12]
+ 8036b7e:	681b      	ldr	r3, [r3, #0]
+ 8036b80:	f8d3 10e0 	ldr.w	r1, [r3, #224]	@ 0xe0
+ 8036b84:	68fb      	ldr	r3, [r7, #12]
+ 8036b86:	681b      	ldr	r3, [r3, #0]
+ 8036b88:	687a      	ldr	r2, [r7, #4]
+ 8036b8a:	430a      	orrs	r2, r1
+ 8036b8c:	f8c3 20e0 	str.w	r2, [r3, #224]	@ 0xe0
+    }
+
+    if ((ActiveITs & FDCAN_IT_TX_ABORT_COMPLETE) != 0U)
+ 8036b90:	68bb      	ldr	r3, [r7, #8]
+ 8036b92:	f403 6380 	and.w	r3, r3, #1024	@ 0x400
+ 8036b96:	2b00      	cmp	r3, #0
+ 8036b98:	d009      	beq.n	8036bae <HAL_FDCAN_ActivateNotification+0xa6>
+    {
+      /* Enable Tx Buffer Cancellation Finished Interrupt to set TCF flag in IR register,
+         but interrupt will only occur if TCF is enabled in IE register */
+      SET_BIT(hfdcan->Instance->TXBCIE, BufferIndexes);
+ 8036b9a:	68fb      	ldr	r3, [r7, #12]
+ 8036b9c:	681b      	ldr	r3, [r3, #0]
+ 8036b9e:	f8d3 10e4 	ldr.w	r1, [r3, #228]	@ 0xe4
+ 8036ba2:	68fb      	ldr	r3, [r7, #12]
+ 8036ba4:	681b      	ldr	r3, [r3, #0]
+ 8036ba6:	687a      	ldr	r2, [r7, #4]
+ 8036ba8:	430a      	orrs	r2, r1
+ 8036baa:	f8c3 20e4 	str.w	r2, [r3, #228]	@ 0xe4
+    }
+
+    /* Enable the selected interrupts */
+    __HAL_FDCAN_ENABLE_IT(hfdcan, ActiveITs);
+ 8036bae:	68fb      	ldr	r3, [r7, #12]
+ 8036bb0:	681b      	ldr	r3, [r3, #0]
+ 8036bb2:	6d59      	ldr	r1, [r3, #84]	@ 0x54
+ 8036bb4:	68ba      	ldr	r2, [r7, #8]
+ 8036bb6:	4b0f      	ldr	r3, [pc, #60]	@ (8036bf4 <HAL_FDCAN_ActivateNotification+0xec>)
+ 8036bb8:	4013      	ands	r3, r2
+ 8036bba:	68fa      	ldr	r2, [r7, #12]
+ 8036bbc:	6812      	ldr	r2, [r2, #0]
+ 8036bbe:	430b      	orrs	r3, r1
+ 8036bc0:	6553      	str	r3, [r2, #84]	@ 0x54
+ 8036bc2:	4b0d      	ldr	r3, [pc, #52]	@ (8036bf8 <HAL_FDCAN_ActivateNotification+0xf0>)
+ 8036bc4:	695a      	ldr	r2, [r3, #20]
+ 8036bc6:	68bb      	ldr	r3, [r7, #8]
+ 8036bc8:	0f9b      	lsrs	r3, r3, #30
+ 8036bca:	490b      	ldr	r1, [pc, #44]	@ (8036bf8 <HAL_FDCAN_ActivateNotification+0xf0>)
+ 8036bcc:	4313      	orrs	r3, r2
+ 8036bce:	614b      	str	r3, [r1, #20]
+
+    /* Return function status */
+    return HAL_OK;
+ 8036bd0:	2300      	movs	r3, #0
+ 8036bd2:	e008      	b.n	8036be6 <HAL_FDCAN_ActivateNotification+0xde>
+  }
+  else
+  {
+    /* Update error code */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED;
+ 8036bd4:	68fb      	ldr	r3, [r7, #12]
+ 8036bd6:	f8d3 309c 	ldr.w	r3, [r3, #156]	@ 0x9c
+ 8036bda:	f043 0202 	orr.w	r2, r3, #2
+ 8036bde:	68fb      	ldr	r3, [r7, #12]
+ 8036be0:	f8c3 209c 	str.w	r2, [r3, #156]	@ 0x9c
+
+    return HAL_ERROR;
+ 8036be4:	2301      	movs	r3, #1
+  }
+}
+ 8036be6:	4618      	mov	r0, r3
+ 8036be8:	371c      	adds	r7, #28
+ 8036bea:	46bd      	mov	sp, r7
+ 8036bec:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8036bf0:	4770      	bx	lr
+ 8036bf2:	bf00      	nop
+ 8036bf4:	3fcfffff 	.word	0x3fcfffff
+ 8036bf8:	4000a800 	.word	0x4000a800
+
+08036bfc <HAL_FDCAN_IRQHandler>:
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+  */
+void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan)
+{
+ 8036bfc:	b580      	push	{r7, lr}
+ 8036bfe:	b096      	sub	sp, #88	@ 0x58
+ 8036c00:	af00      	add	r7, sp, #0
+ 8036c02:	6078      	str	r0, [r7, #4]
+  uint32_t itsourceIE;
+  uint32_t itsourceTTIE;
+  uint32_t itflagIR;
+  uint32_t itflagTTIR;
+
+  ClkCalibrationITs = (FDCAN_CCU->IR << 30);
+ 8036c04:	4b95      	ldr	r3, [pc, #596]	@ (8036e5c <HAL_FDCAN_IRQHandler+0x260>)
+ 8036c06:	691b      	ldr	r3, [r3, #16]
+ 8036c08:	079b      	lsls	r3, r3, #30
+ 8036c0a:	657b      	str	r3, [r7, #84]	@ 0x54
+  ClkCalibrationITs &= (FDCAN_CCU->IE << 30);
+ 8036c0c:	4b93      	ldr	r3, [pc, #588]	@ (8036e5c <HAL_FDCAN_IRQHandler+0x260>)
+ 8036c0e:	695b      	ldr	r3, [r3, #20]
+ 8036c10:	079b      	lsls	r3, r3, #30
+ 8036c12:	6d7a      	ldr	r2, [r7, #84]	@ 0x54
+ 8036c14:	4013      	ands	r3, r2
+ 8036c16:	657b      	str	r3, [r7, #84]	@ 0x54
+  TxEventFifoITs = hfdcan->Instance->IR & FDCAN_TX_EVENT_FIFO_MASK;
+ 8036c18:	687b      	ldr	r3, [r7, #4]
+ 8036c1a:	681b      	ldr	r3, [r3, #0]
+ 8036c1c:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
+ 8036c1e:	f403 4370 	and.w	r3, r3, #61440	@ 0xf000
+ 8036c22:	653b      	str	r3, [r7, #80]	@ 0x50
+  TxEventFifoITs &= hfdcan->Instance->IE;
+ 8036c24:	687b      	ldr	r3, [r7, #4]
+ 8036c26:	681b      	ldr	r3, [r3, #0]
+ 8036c28:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
+ 8036c2a:	6d3a      	ldr	r2, [r7, #80]	@ 0x50
+ 8036c2c:	4013      	ands	r3, r2
+ 8036c2e:	653b      	str	r3, [r7, #80]	@ 0x50
+  RxFifo0ITs = hfdcan->Instance->IR & FDCAN_RX_FIFO0_MASK;
+ 8036c30:	687b      	ldr	r3, [r7, #4]
+ 8036c32:	681b      	ldr	r3, [r3, #0]
+ 8036c34:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
+ 8036c36:	f003 030f 	and.w	r3, r3, #15
+ 8036c3a:	64fb      	str	r3, [r7, #76]	@ 0x4c
+  RxFifo0ITs &= hfdcan->Instance->IE;
+ 8036c3c:	687b      	ldr	r3, [r7, #4]
+ 8036c3e:	681b      	ldr	r3, [r3, #0]
+ 8036c40:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
+ 8036c42:	6cfa      	ldr	r2, [r7, #76]	@ 0x4c
+ 8036c44:	4013      	ands	r3, r2
+ 8036c46:	64fb      	str	r3, [r7, #76]	@ 0x4c
+  RxFifo1ITs = hfdcan->Instance->IR & FDCAN_RX_FIFO1_MASK;
+ 8036c48:	687b      	ldr	r3, [r7, #4]
+ 8036c4a:	681b      	ldr	r3, [r3, #0]
+ 8036c4c:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
+ 8036c4e:	f003 03f0 	and.w	r3, r3, #240	@ 0xf0
+ 8036c52:	64bb      	str	r3, [r7, #72]	@ 0x48
+  RxFifo1ITs &= hfdcan->Instance->IE;
+ 8036c54:	687b      	ldr	r3, [r7, #4]
+ 8036c56:	681b      	ldr	r3, [r3, #0]
+ 8036c58:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
+ 8036c5a:	6cba      	ldr	r2, [r7, #72]	@ 0x48
+ 8036c5c:	4013      	ands	r3, r2
+ 8036c5e:	64bb      	str	r3, [r7, #72]	@ 0x48
+  Errors = hfdcan->Instance->IR & FDCAN_ERROR_MASK;
+ 8036c60:	687b      	ldr	r3, [r7, #4]
+ 8036c62:	681b      	ldr	r3, [r3, #0]
+ 8036c64:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
+ 8036c66:	f003 5371 	and.w	r3, r3, #1010827264	@ 0x3c400000
+ 8036c6a:	647b      	str	r3, [r7, #68]	@ 0x44
+  Errors &= hfdcan->Instance->IE;
+ 8036c6c:	687b      	ldr	r3, [r7, #4]
+ 8036c6e:	681b      	ldr	r3, [r3, #0]
+ 8036c70:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
+ 8036c72:	6c7a      	ldr	r2, [r7, #68]	@ 0x44
+ 8036c74:	4013      	ands	r3, r2
+ 8036c76:	647b      	str	r3, [r7, #68]	@ 0x44
+  ErrorStatusITs = hfdcan->Instance->IR & FDCAN_ERROR_STATUS_MASK;
+ 8036c78:	687b      	ldr	r3, [r7, #4]
+ 8036c7a:	681b      	ldr	r3, [r3, #0]
+ 8036c7c:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
+ 8036c7e:	f003 7360 	and.w	r3, r3, #58720256	@ 0x3800000
+ 8036c82:	643b      	str	r3, [r7, #64]	@ 0x40
+  ErrorStatusITs &= hfdcan->Instance->IE;
+ 8036c84:	687b      	ldr	r3, [r7, #4]
+ 8036c86:	681b      	ldr	r3, [r3, #0]
+ 8036c88:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
+ 8036c8a:	6c3a      	ldr	r2, [r7, #64]	@ 0x40
+ 8036c8c:	4013      	ands	r3, r2
+ 8036c8e:	643b      	str	r3, [r7, #64]	@ 0x40
+  itsourceIE = hfdcan->Instance->IE;
+ 8036c90:	687b      	ldr	r3, [r7, #4]
+ 8036c92:	681b      	ldr	r3, [r3, #0]
+ 8036c94:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
+ 8036c96:	63fb      	str	r3, [r7, #60]	@ 0x3c
+  itflagIR = hfdcan->Instance->IR;
+ 8036c98:	687b      	ldr	r3, [r7, #4]
+ 8036c9a:	681b      	ldr	r3, [r3, #0]
+ 8036c9c:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
+ 8036c9e:	63bb      	str	r3, [r7, #56]	@ 0x38
+
+  /* High Priority Message interrupt management *******************************/
+  if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_RX_HIGH_PRIORITY_MSG) != RESET)
+ 8036ca0:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
+ 8036ca2:	f403 7380 	and.w	r3, r3, #256	@ 0x100
+ 8036ca6:	2b00      	cmp	r3, #0
+ 8036ca8:	d00f      	beq.n	8036cca <HAL_FDCAN_IRQHandler+0xce>
+  {
+    if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG) != RESET)
+ 8036caa:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 8036cac:	f403 7380 	and.w	r3, r3, #256	@ 0x100
+ 8036cb0:	2b00      	cmp	r3, #0
+ 8036cb2:	d00a      	beq.n	8036cca <HAL_FDCAN_IRQHandler+0xce>
+    {
+      /* Clear the High Priority Message flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG);
+ 8036cb4:	687b      	ldr	r3, [r7, #4]
+ 8036cb6:	681b      	ldr	r3, [r3, #0]
+ 8036cb8:	f44f 7280 	mov.w	r2, #256	@ 0x100
+ 8036cbc:	651a      	str	r2, [r3, #80]	@ 0x50
+ 8036cbe:	4b67      	ldr	r3, [pc, #412]	@ (8036e5c <HAL_FDCAN_IRQHandler+0x260>)
+ 8036cc0:	2200      	movs	r2, #0
+ 8036cc2:	611a      	str	r2, [r3, #16]
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hfdcan->HighPriorityMessageCallback(hfdcan);
+#else
+      /* High Priority Message Callback */
+      HAL_FDCAN_HighPriorityMessageCallback(hfdcan);
+ 8036cc4:	6878      	ldr	r0, [r7, #4]
+ 8036cc6:	f000 fa44 	bl	8037152 <HAL_FDCAN_HighPriorityMessageCallback>
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Transmission Abort interrupt management **********************************/
+  if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_TX_ABORT_COMPLETE) != RESET)
+ 8036cca:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
+ 8036ccc:	f403 6380 	and.w	r3, r3, #1024	@ 0x400
+ 8036cd0:	2b00      	cmp	r3, #0
+ 8036cd2:	d01c      	beq.n	8036d0e <HAL_FDCAN_IRQHandler+0x112>
+  {
+    if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_TX_ABORT_COMPLETE) != RESET)
+ 8036cd4:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 8036cd6:	f403 6380 	and.w	r3, r3, #1024	@ 0x400
+ 8036cda:	2b00      	cmp	r3, #0
+ 8036cdc:	d017      	beq.n	8036d0e <HAL_FDCAN_IRQHandler+0x112>
+    {
+      /* List of aborted monitored buffers */
+      AbortedBuffers = hfdcan->Instance->TXBCF;
+ 8036cde:	687b      	ldr	r3, [r7, #4]
+ 8036ce0:	681b      	ldr	r3, [r3, #0]
+ 8036ce2:	f8d3 30dc 	ldr.w	r3, [r3, #220]	@ 0xdc
+ 8036ce6:	637b      	str	r3, [r7, #52]	@ 0x34
+      AbortedBuffers &= hfdcan->Instance->TXBCIE;
+ 8036ce8:	687b      	ldr	r3, [r7, #4]
+ 8036cea:	681b      	ldr	r3, [r3, #0]
+ 8036cec:	f8d3 30e4 	ldr.w	r3, [r3, #228]	@ 0xe4
+ 8036cf0:	6b7a      	ldr	r2, [r7, #52]	@ 0x34
+ 8036cf2:	4013      	ands	r3, r2
+ 8036cf4:	637b      	str	r3, [r7, #52]	@ 0x34
+
+      /* Clear the Transmission Cancellation flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_ABORT_COMPLETE);
+ 8036cf6:	687b      	ldr	r3, [r7, #4]
+ 8036cf8:	681b      	ldr	r3, [r3, #0]
+ 8036cfa:	f44f 6280 	mov.w	r2, #1024	@ 0x400
+ 8036cfe:	651a      	str	r2, [r3, #80]	@ 0x50
+ 8036d00:	4b56      	ldr	r3, [pc, #344]	@ (8036e5c <HAL_FDCAN_IRQHandler+0x260>)
+ 8036d02:	2200      	movs	r2, #0
+ 8036d04:	611a      	str	r2, [r3, #16]
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hfdcan->TxBufferAbortCallback(hfdcan, AbortedBuffers);
+#else
+      /* Transmission Cancellation Callback */
+      HAL_FDCAN_TxBufferAbortCallback(hfdcan, AbortedBuffers);
+ 8036d06:	6b79      	ldr	r1, [r7, #52]	@ 0x34
+ 8036d08:	6878      	ldr	r0, [r7, #4]
+ 8036d0a:	f000 f9f9 	bl	8037100 <HAL_FDCAN_TxBufferAbortCallback>
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Clock calibration unit interrupts management *****************************/
+  if (ClkCalibrationITs != 0U)
+ 8036d0e:	6d7b      	ldr	r3, [r7, #84]	@ 0x54
+ 8036d10:	2b00      	cmp	r3, #0
+ 8036d12:	d00d      	beq.n	8036d30 <HAL_FDCAN_IRQHandler+0x134>
+  {
+    /* Clear the Clock Calibration flags */
+    __HAL_FDCAN_CLEAR_FLAG(hfdcan, ClkCalibrationITs);
+ 8036d14:	687b      	ldr	r3, [r7, #4]
+ 8036d16:	681a      	ldr	r2, [r3, #0]
+ 8036d18:	6d79      	ldr	r1, [r7, #84]	@ 0x54
+ 8036d1a:	4b51      	ldr	r3, [pc, #324]	@ (8036e60 <HAL_FDCAN_IRQHandler+0x264>)
+ 8036d1c:	400b      	ands	r3, r1
+ 8036d1e:	6513      	str	r3, [r2, #80]	@ 0x50
+ 8036d20:	4a4e      	ldr	r2, [pc, #312]	@ (8036e5c <HAL_FDCAN_IRQHandler+0x260>)
+ 8036d22:	6d7b      	ldr	r3, [r7, #84]	@ 0x54
+ 8036d24:	0f9b      	lsrs	r3, r3, #30
+ 8036d26:	6113      	str	r3, [r2, #16]
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+    /* Call registered callback*/
+    hfdcan->ClockCalibrationCallback(hfdcan, ClkCalibrationITs);
+#else
+    /* Clock Calibration Callback */
+    HAL_FDCAN_ClockCalibrationCallback(hfdcan, ClkCalibrationITs);
+ 8036d28:	6d79      	ldr	r1, [r7, #84]	@ 0x54
+ 8036d2a:	6878      	ldr	r0, [r7, #4]
+ 8036d2c:	f000 f9b2 	bl	8037094 <HAL_FDCAN_ClockCalibrationCallback>
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+  }
+
+  /* Tx event FIFO interrupts management **************************************/
+  if (TxEventFifoITs != 0U)
+ 8036d30:	6d3b      	ldr	r3, [r7, #80]	@ 0x50
+ 8036d32:	2b00      	cmp	r3, #0
+ 8036d34:	d00d      	beq.n	8036d52 <HAL_FDCAN_IRQHandler+0x156>
+  {
+    /* Clear the Tx Event FIFO flags */
+    __HAL_FDCAN_CLEAR_FLAG(hfdcan, TxEventFifoITs);
+ 8036d36:	687b      	ldr	r3, [r7, #4]
+ 8036d38:	681a      	ldr	r2, [r3, #0]
+ 8036d3a:	6d39      	ldr	r1, [r7, #80]	@ 0x50
+ 8036d3c:	4b48      	ldr	r3, [pc, #288]	@ (8036e60 <HAL_FDCAN_IRQHandler+0x264>)
+ 8036d3e:	400b      	ands	r3, r1
+ 8036d40:	6513      	str	r3, [r2, #80]	@ 0x50
+ 8036d42:	4a46      	ldr	r2, [pc, #280]	@ (8036e5c <HAL_FDCAN_IRQHandler+0x260>)
+ 8036d44:	6d3b      	ldr	r3, [r7, #80]	@ 0x50
+ 8036d46:	0f9b      	lsrs	r3, r3, #30
+ 8036d48:	6113      	str	r3, [r2, #16]
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+    /* Call registered callback*/
+    hfdcan->TxEventFifoCallback(hfdcan, TxEventFifoITs);
+#else
+    /* Tx Event FIFO Callback */
+    HAL_FDCAN_TxEventFifoCallback(hfdcan, TxEventFifoITs);
+ 8036d4a:	6d39      	ldr	r1, [r7, #80]	@ 0x50
+ 8036d4c:	6878      	ldr	r0, [r7, #4]
+ 8036d4e:	f000 f9ac 	bl	80370aa <HAL_FDCAN_TxEventFifoCallback>
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+  }
+
+  /* Rx FIFO 0 interrupts management ******************************************/
+  if (RxFifo0ITs != 0U)
+ 8036d52:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
+ 8036d54:	2b00      	cmp	r3, #0
+ 8036d56:	d00d      	beq.n	8036d74 <HAL_FDCAN_IRQHandler+0x178>
+  {
+    /* Clear the Rx FIFO 0 flags */
+    __HAL_FDCAN_CLEAR_FLAG(hfdcan, RxFifo0ITs);
+ 8036d58:	687b      	ldr	r3, [r7, #4]
+ 8036d5a:	681a      	ldr	r2, [r3, #0]
+ 8036d5c:	6cf9      	ldr	r1, [r7, #76]	@ 0x4c
+ 8036d5e:	4b40      	ldr	r3, [pc, #256]	@ (8036e60 <HAL_FDCAN_IRQHandler+0x264>)
+ 8036d60:	400b      	ands	r3, r1
+ 8036d62:	6513      	str	r3, [r2, #80]	@ 0x50
+ 8036d64:	4a3d      	ldr	r2, [pc, #244]	@ (8036e5c <HAL_FDCAN_IRQHandler+0x260>)
+ 8036d66:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
+ 8036d68:	0f9b      	lsrs	r3, r3, #30
+ 8036d6a:	6113      	str	r3, [r2, #16]
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+    /* Call registered callback*/
+    hfdcan->RxFifo0Callback(hfdcan, RxFifo0ITs);
+#else
+    /* Rx FIFO 0 Callback */
+    HAL_FDCAN_RxFifo0Callback(hfdcan, RxFifo0ITs);
+ 8036d6c:	6cf9      	ldr	r1, [r7, #76]	@ 0x4c
+ 8036d6e:	6878      	ldr	r0, [r7, #4]
+ 8036d70:	f7ea f81c 	bl	8020dac <HAL_FDCAN_RxFifo0Callback>
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+  }
+
+  /* Rx FIFO 1 interrupts management ******************************************/
+  if (RxFifo1ITs != 0U)
+ 8036d74:	6cbb      	ldr	r3, [r7, #72]	@ 0x48
+ 8036d76:	2b00      	cmp	r3, #0
+ 8036d78:	d00d      	beq.n	8036d96 <HAL_FDCAN_IRQHandler+0x19a>
+  {
+    /* Clear the Rx FIFO 1 flags */
+    __HAL_FDCAN_CLEAR_FLAG(hfdcan, RxFifo1ITs);
+ 8036d7a:	687b      	ldr	r3, [r7, #4]
+ 8036d7c:	681a      	ldr	r2, [r3, #0]
+ 8036d7e:	6cb9      	ldr	r1, [r7, #72]	@ 0x48
+ 8036d80:	4b37      	ldr	r3, [pc, #220]	@ (8036e60 <HAL_FDCAN_IRQHandler+0x264>)
+ 8036d82:	400b      	ands	r3, r1
+ 8036d84:	6513      	str	r3, [r2, #80]	@ 0x50
+ 8036d86:	4a35      	ldr	r2, [pc, #212]	@ (8036e5c <HAL_FDCAN_IRQHandler+0x260>)
+ 8036d88:	6cbb      	ldr	r3, [r7, #72]	@ 0x48
+ 8036d8a:	0f9b      	lsrs	r3, r3, #30
+ 8036d8c:	6113      	str	r3, [r2, #16]
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+    /* Call registered callback*/
+    hfdcan->RxFifo1Callback(hfdcan, RxFifo1ITs);
+#else
+    /* Rx FIFO 1 Callback */
+    HAL_FDCAN_RxFifo1Callback(hfdcan, RxFifo1ITs);
+ 8036d8e:	6cb9      	ldr	r1, [r7, #72]	@ 0x48
+ 8036d90:	6878      	ldr	r0, [r7, #4]
+ 8036d92:	f000 f995 	bl	80370c0 <HAL_FDCAN_RxFifo1Callback>
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+  }
+
+  /* Tx FIFO empty interrupt management ***************************************/
+  if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_TX_FIFO_EMPTY) != RESET)
+ 8036d96:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
+ 8036d98:	f403 6300 	and.w	r3, r3, #2048	@ 0x800
+ 8036d9c:	2b00      	cmp	r3, #0
+ 8036d9e:	d00f      	beq.n	8036dc0 <HAL_FDCAN_IRQHandler+0x1c4>
+  {
+    if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_TX_FIFO_EMPTY) != RESET)
+ 8036da0:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 8036da2:	f403 6300 	and.w	r3, r3, #2048	@ 0x800
+ 8036da6:	2b00      	cmp	r3, #0
+ 8036da8:	d00a      	beq.n	8036dc0 <HAL_FDCAN_IRQHandler+0x1c4>
+    {
+      /* Clear the Tx FIFO empty flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_FIFO_EMPTY);
+ 8036daa:	687b      	ldr	r3, [r7, #4]
+ 8036dac:	681b      	ldr	r3, [r3, #0]
+ 8036dae:	f44f 6200 	mov.w	r2, #2048	@ 0x800
+ 8036db2:	651a      	str	r2, [r3, #80]	@ 0x50
+ 8036db4:	4b29      	ldr	r3, [pc, #164]	@ (8036e5c <HAL_FDCAN_IRQHandler+0x260>)
+ 8036db6:	2200      	movs	r2, #0
+ 8036db8:	611a      	str	r2, [r3, #16]
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hfdcan->TxFifoEmptyCallback(hfdcan);
+#else
+      /* Tx FIFO empty Callback */
+      HAL_FDCAN_TxFifoEmptyCallback(hfdcan);
+ 8036dba:	6878      	ldr	r0, [r7, #4]
+ 8036dbc:	f000 f98b 	bl	80370d6 <HAL_FDCAN_TxFifoEmptyCallback>
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Transmission Complete interrupt management *******************************/
+  if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_TX_COMPLETE) != RESET)
+ 8036dc0:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
+ 8036dc2:	f403 7300 	and.w	r3, r3, #512	@ 0x200
+ 8036dc6:	2b00      	cmp	r3, #0
+ 8036dc8:	d01c      	beq.n	8036e04 <HAL_FDCAN_IRQHandler+0x208>
+  {
+    if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_TX_COMPLETE) != RESET)
+ 8036dca:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 8036dcc:	f403 7300 	and.w	r3, r3, #512	@ 0x200
+ 8036dd0:	2b00      	cmp	r3, #0
+ 8036dd2:	d017      	beq.n	8036e04 <HAL_FDCAN_IRQHandler+0x208>
+    {
+      /* List of transmitted monitored buffers */
+      TransmittedBuffers = hfdcan->Instance->TXBTO;
+ 8036dd4:	687b      	ldr	r3, [r7, #4]
+ 8036dd6:	681b      	ldr	r3, [r3, #0]
+ 8036dd8:	f8d3 30d8 	ldr.w	r3, [r3, #216]	@ 0xd8
+ 8036ddc:	633b      	str	r3, [r7, #48]	@ 0x30
+      TransmittedBuffers &= hfdcan->Instance->TXBTIE;
+ 8036dde:	687b      	ldr	r3, [r7, #4]
+ 8036de0:	681b      	ldr	r3, [r3, #0]
+ 8036de2:	f8d3 30e0 	ldr.w	r3, [r3, #224]	@ 0xe0
+ 8036de6:	6b3a      	ldr	r2, [r7, #48]	@ 0x30
+ 8036de8:	4013      	ands	r3, r2
+ 8036dea:	633b      	str	r3, [r7, #48]	@ 0x30
+
+      /* Clear the Transmission Complete flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_COMPLETE);
+ 8036dec:	687b      	ldr	r3, [r7, #4]
+ 8036dee:	681b      	ldr	r3, [r3, #0]
+ 8036df0:	f44f 7200 	mov.w	r2, #512	@ 0x200
+ 8036df4:	651a      	str	r2, [r3, #80]	@ 0x50
+ 8036df6:	4b19      	ldr	r3, [pc, #100]	@ (8036e5c <HAL_FDCAN_IRQHandler+0x260>)
+ 8036df8:	2200      	movs	r2, #0
+ 8036dfa:	611a      	str	r2, [r3, #16]
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hfdcan->TxBufferCompleteCallback(hfdcan, TransmittedBuffers);
+#else
+      /* Transmission Complete Callback */
+      HAL_FDCAN_TxBufferCompleteCallback(hfdcan, TransmittedBuffers);
+ 8036dfc:	6b39      	ldr	r1, [r7, #48]	@ 0x30
+ 8036dfe:	6878      	ldr	r0, [r7, #4]
+ 8036e00:	f000 f973 	bl	80370ea <HAL_FDCAN_TxBufferCompleteCallback>
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Rx Buffer New Message interrupt management *******************************/
+  if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_RX_BUFFER_NEW_MESSAGE) != RESET)
+ 8036e04:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
+ 8036e06:	f403 2300 	and.w	r3, r3, #524288	@ 0x80000
+ 8036e0a:	2b00      	cmp	r3, #0
+ 8036e0c:	d00f      	beq.n	8036e2e <HAL_FDCAN_IRQHandler+0x232>
+  {
+    if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE) != RESET)
+ 8036e0e:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 8036e10:	f403 2300 	and.w	r3, r3, #524288	@ 0x80000
+ 8036e14:	2b00      	cmp	r3, #0
+ 8036e16:	d00a      	beq.n	8036e2e <HAL_FDCAN_IRQHandler+0x232>
+    {
+      /* Clear the Rx Buffer New Message flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE);
+ 8036e18:	687b      	ldr	r3, [r7, #4]
+ 8036e1a:	681b      	ldr	r3, [r3, #0]
+ 8036e1c:	f44f 2200 	mov.w	r2, #524288	@ 0x80000
+ 8036e20:	651a      	str	r2, [r3, #80]	@ 0x50
+ 8036e22:	4b0e      	ldr	r3, [pc, #56]	@ (8036e5c <HAL_FDCAN_IRQHandler+0x260>)
+ 8036e24:	2200      	movs	r2, #0
+ 8036e26:	611a      	str	r2, [r3, #16]
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hfdcan->RxBufferNewMessageCallback(hfdcan);
+#else
+      /* Rx Buffer New Message Callback */
+      HAL_FDCAN_RxBufferNewMessageCallback(hfdcan);
+ 8036e28:	6878      	ldr	r0, [r7, #4]
+ 8036e2a:	f000 f974 	bl	8037116 <HAL_FDCAN_RxBufferNewMessageCallback>
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Timestamp Wraparound interrupt management ********************************/
+  if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_TIMESTAMP_WRAPAROUND) != RESET)
+ 8036e2e:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
+ 8036e30:	f403 3380 	and.w	r3, r3, #65536	@ 0x10000
+ 8036e34:	2b00      	cmp	r3, #0
+ 8036e36:	d015      	beq.n	8036e64 <HAL_FDCAN_IRQHandler+0x268>
+  {
+    if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_TIMESTAMP_WRAPAROUND) != RESET)
+ 8036e38:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 8036e3a:	f403 3380 	and.w	r3, r3, #65536	@ 0x10000
+ 8036e3e:	2b00      	cmp	r3, #0
+ 8036e40:	d010      	beq.n	8036e64 <HAL_FDCAN_IRQHandler+0x268>
+    {
+      /* Clear the Timestamp Wraparound flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMESTAMP_WRAPAROUND);
+ 8036e42:	687b      	ldr	r3, [r7, #4]
+ 8036e44:	681b      	ldr	r3, [r3, #0]
+ 8036e46:	f44f 3280 	mov.w	r2, #65536	@ 0x10000
+ 8036e4a:	651a      	str	r2, [r3, #80]	@ 0x50
+ 8036e4c:	4b03      	ldr	r3, [pc, #12]	@ (8036e5c <HAL_FDCAN_IRQHandler+0x260>)
+ 8036e4e:	2200      	movs	r2, #0
+ 8036e50:	611a      	str	r2, [r3, #16]
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hfdcan->TimestampWraparoundCallback(hfdcan);
+#else
+      /* Timestamp Wraparound Callback */
+      HAL_FDCAN_TimestampWraparoundCallback(hfdcan);
+ 8036e52:	6878      	ldr	r0, [r7, #4]
+ 8036e54:	f000 f969 	bl	803712a <HAL_FDCAN_TimestampWraparoundCallback>
+ 8036e58:	e004      	b.n	8036e64 <HAL_FDCAN_IRQHandler+0x268>
+ 8036e5a:	bf00      	nop
+ 8036e5c:	4000a800 	.word	0x4000a800
+ 8036e60:	3fcfffff 	.word	0x3fcfffff
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Timeout Occurred interrupt management ************************************/
+  if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_TIMEOUT_OCCURRED) != RESET)
+ 8036e64:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
+ 8036e66:	f403 2380 	and.w	r3, r3, #262144	@ 0x40000
+ 8036e6a:	2b00      	cmp	r3, #0
+ 8036e6c:	d00f      	beq.n	8036e8e <HAL_FDCAN_IRQHandler+0x292>
+  {
+    if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_TIMEOUT_OCCURRED) != RESET)
+ 8036e6e:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 8036e70:	f403 2380 	and.w	r3, r3, #262144	@ 0x40000
+ 8036e74:	2b00      	cmp	r3, #0
+ 8036e76:	d00a      	beq.n	8036e8e <HAL_FDCAN_IRQHandler+0x292>
+    {
+      /* Clear the Timeout Occurred flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMEOUT_OCCURRED);
+ 8036e78:	687b      	ldr	r3, [r7, #4]
+ 8036e7a:	681b      	ldr	r3, [r3, #0]
+ 8036e7c:	f44f 2280 	mov.w	r2, #262144	@ 0x40000
+ 8036e80:	651a      	str	r2, [r3, #80]	@ 0x50
+ 8036e82:	4b81      	ldr	r3, [pc, #516]	@ (8037088 <HAL_FDCAN_IRQHandler+0x48c>)
+ 8036e84:	2200      	movs	r2, #0
+ 8036e86:	611a      	str	r2, [r3, #16]
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hfdcan->TimeoutOccurredCallback(hfdcan);
+#else
+      /* Timeout Occurred Callback */
+      HAL_FDCAN_TimeoutOccurredCallback(hfdcan);
+ 8036e88:	6878      	ldr	r0, [r7, #4]
+ 8036e8a:	f000 f958 	bl	803713e <HAL_FDCAN_TimeoutOccurredCallback>
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Message RAM access failure interrupt management **************************/
+  if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_RAM_ACCESS_FAILURE) != RESET)
+ 8036e8e:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
+ 8036e90:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
+ 8036e94:	2b00      	cmp	r3, #0
+ 8036e96:	d014      	beq.n	8036ec2 <HAL_FDCAN_IRQHandler+0x2c6>
+  {
+    if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_RAM_ACCESS_FAILURE) != RESET)
+ 8036e98:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 8036e9a:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
+ 8036e9e:	2b00      	cmp	r3, #0
+ 8036ea0:	d00f      	beq.n	8036ec2 <HAL_FDCAN_IRQHandler+0x2c6>
+    {
+      /* Clear the Message RAM access failure flag */
+      __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RAM_ACCESS_FAILURE);
+ 8036ea2:	687b      	ldr	r3, [r7, #4]
+ 8036ea4:	681b      	ldr	r3, [r3, #0]
+ 8036ea6:	f44f 3200 	mov.w	r2, #131072	@ 0x20000
+ 8036eaa:	651a      	str	r2, [r3, #80]	@ 0x50
+ 8036eac:	4b76      	ldr	r3, [pc, #472]	@ (8037088 <HAL_FDCAN_IRQHandler+0x48c>)
+ 8036eae:	2200      	movs	r2, #0
+ 8036eb0:	611a      	str	r2, [r3, #16]
+
+      /* Update error code */
+      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_RAM_ACCESS;
+ 8036eb2:	687b      	ldr	r3, [r7, #4]
+ 8036eb4:	f8d3 309c 	ldr.w	r3, [r3, #156]	@ 0x9c
+ 8036eb8:	f043 0280 	orr.w	r2, r3, #128	@ 0x80
+ 8036ebc:	687b      	ldr	r3, [r7, #4]
+ 8036ebe:	f8c3 209c 	str.w	r2, [r3, #156]	@ 0x9c
+    }
+  }
+
+  /* Error Status interrupts management ***************************************/
+  if (ErrorStatusITs != 0U)
+ 8036ec2:	6c3b      	ldr	r3, [r7, #64]	@ 0x40
+ 8036ec4:	2b00      	cmp	r3, #0
+ 8036ec6:	d00d      	beq.n	8036ee4 <HAL_FDCAN_IRQHandler+0x2e8>
+  {
+    /* Clear the Error flags */
+    __HAL_FDCAN_CLEAR_FLAG(hfdcan, ErrorStatusITs);
+ 8036ec8:	687b      	ldr	r3, [r7, #4]
+ 8036eca:	681a      	ldr	r2, [r3, #0]
+ 8036ecc:	6c39      	ldr	r1, [r7, #64]	@ 0x40
+ 8036ece:	4b6f      	ldr	r3, [pc, #444]	@ (803708c <HAL_FDCAN_IRQHandler+0x490>)
+ 8036ed0:	400b      	ands	r3, r1
+ 8036ed2:	6513      	str	r3, [r2, #80]	@ 0x50
+ 8036ed4:	4a6c      	ldr	r2, [pc, #432]	@ (8037088 <HAL_FDCAN_IRQHandler+0x48c>)
+ 8036ed6:	6c3b      	ldr	r3, [r7, #64]	@ 0x40
+ 8036ed8:	0f9b      	lsrs	r3, r3, #30
+ 8036eda:	6113      	str	r3, [r2, #16]
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+    /* Call registered callback*/
+    hfdcan->ErrorStatusCallback(hfdcan, ErrorStatusITs);
+#else
+    /* Error Status Callback */
+    HAL_FDCAN_ErrorStatusCallback(hfdcan, ErrorStatusITs);
+ 8036edc:	6c39      	ldr	r1, [r7, #64]	@ 0x40
+ 8036ede:	6878      	ldr	r0, [r7, #4]
+ 8036ee0:	f7e9 ff48 	bl	8020d74 <HAL_FDCAN_ErrorStatusCallback>
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+  }
+
+  /* Error interrupts management **********************************************/
+  if (Errors != 0U)
+ 8036ee4:	6c7b      	ldr	r3, [r7, #68]	@ 0x44
+ 8036ee6:	2b00      	cmp	r3, #0
+ 8036ee8:	d011      	beq.n	8036f0e <HAL_FDCAN_IRQHandler+0x312>
+  {
+    /* Clear the Error flags */
+    __HAL_FDCAN_CLEAR_FLAG(hfdcan, Errors);
+ 8036eea:	687b      	ldr	r3, [r7, #4]
+ 8036eec:	681a      	ldr	r2, [r3, #0]
+ 8036eee:	6c79      	ldr	r1, [r7, #68]	@ 0x44
+ 8036ef0:	4b66      	ldr	r3, [pc, #408]	@ (803708c <HAL_FDCAN_IRQHandler+0x490>)
+ 8036ef2:	400b      	ands	r3, r1
+ 8036ef4:	6513      	str	r3, [r2, #80]	@ 0x50
+ 8036ef6:	4a64      	ldr	r2, [pc, #400]	@ (8037088 <HAL_FDCAN_IRQHandler+0x48c>)
+ 8036ef8:	6c7b      	ldr	r3, [r7, #68]	@ 0x44
+ 8036efa:	0f9b      	lsrs	r3, r3, #30
+ 8036efc:	6113      	str	r3, [r2, #16]
+
+    /* Update error code */
+    hfdcan->ErrorCode |= Errors;
+ 8036efe:	687b      	ldr	r3, [r7, #4]
+ 8036f00:	f8d3 209c 	ldr.w	r2, [r3, #156]	@ 0x9c
+ 8036f04:	6c7b      	ldr	r3, [r7, #68]	@ 0x44
+ 8036f06:	431a      	orrs	r2, r3
+ 8036f08:	687b      	ldr	r3, [r7, #4]
+ 8036f0a:	f8c3 209c 	str.w	r2, [r3, #156]	@ 0x9c
+  }
+
+  if (hfdcan->Instance == FDCAN1)
+ 8036f0e:	687b      	ldr	r3, [r7, #4]
+ 8036f10:	681b      	ldr	r3, [r3, #0]
+ 8036f12:	4a5f      	ldr	r2, [pc, #380]	@ (8037090 <HAL_FDCAN_IRQHandler+0x494>)
+ 8036f14:	4293      	cmp	r3, r2
+ 8036f16:	f040 80aa 	bne.w	803706e <HAL_FDCAN_IRQHandler+0x472>
+  {
+    if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != 0U)
+ 8036f1a:	687b      	ldr	r3, [r7, #4]
+ 8036f1c:	685b      	ldr	r3, [r3, #4]
+ 8036f1e:	689b      	ldr	r3, [r3, #8]
+ 8036f20:	f003 0303 	and.w	r3, r3, #3
+ 8036f24:	2b00      	cmp	r3, #0
+ 8036f26:	f000 80a2 	beq.w	803706e <HAL_FDCAN_IRQHandler+0x472>
+    {
+      TTSchedSyncITs = hfdcan->ttcan->TTIR & FDCAN_TT_SCHEDULE_SYNC_MASK;
+ 8036f2a:	687b      	ldr	r3, [r7, #4]
+ 8036f2c:	685b      	ldr	r3, [r3, #4]
+ 8036f2e:	6a1b      	ldr	r3, [r3, #32]
+ 8036f30:	f003 030f 	and.w	r3, r3, #15
+ 8036f34:	62fb      	str	r3, [r7, #44]	@ 0x2c
+      TTSchedSyncITs &= hfdcan->ttcan->TTIE;
+ 8036f36:	687b      	ldr	r3, [r7, #4]
+ 8036f38:	685b      	ldr	r3, [r3, #4]
+ 8036f3a:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 8036f3c:	6afa      	ldr	r2, [r7, #44]	@ 0x2c
+ 8036f3e:	4013      	ands	r3, r2
+ 8036f40:	62fb      	str	r3, [r7, #44]	@ 0x2c
+      TTTimeMarkITs = hfdcan->ttcan->TTIR & FDCAN_TT_TIME_MARK_MASK;
+ 8036f42:	687b      	ldr	r3, [r7, #4]
+ 8036f44:	685b      	ldr	r3, [r3, #4]
+ 8036f46:	6a1b      	ldr	r3, [r3, #32]
+ 8036f48:	f003 0330 	and.w	r3, r3, #48	@ 0x30
+ 8036f4c:	62bb      	str	r3, [r7, #40]	@ 0x28
+      TTTimeMarkITs &= hfdcan->ttcan->TTIE;
+ 8036f4e:	687b      	ldr	r3, [r7, #4]
+ 8036f50:	685b      	ldr	r3, [r3, #4]
+ 8036f52:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 8036f54:	6aba      	ldr	r2, [r7, #40]	@ 0x28
+ 8036f56:	4013      	ands	r3, r2
+ 8036f58:	62bb      	str	r3, [r7, #40]	@ 0x28
+      TTGlobTimeITs = hfdcan->ttcan->TTIR & FDCAN_TT_GLOBAL_TIME_MASK;
+ 8036f5a:	687b      	ldr	r3, [r7, #4]
+ 8036f5c:	685b      	ldr	r3, [r3, #4]
+ 8036f5e:	6a1b      	ldr	r3, [r3, #32]
+ 8036f60:	f403 73c0 	and.w	r3, r3, #384	@ 0x180
+ 8036f64:	627b      	str	r3, [r7, #36]	@ 0x24
+      TTGlobTimeITs &= hfdcan->ttcan->TTIE;
+ 8036f66:	687b      	ldr	r3, [r7, #4]
+ 8036f68:	685b      	ldr	r3, [r3, #4]
+ 8036f6a:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 8036f6c:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
+ 8036f6e:	4013      	ands	r3, r2
+ 8036f70:	627b      	str	r3, [r7, #36]	@ 0x24
+      TTDistErrors = hfdcan->ttcan->TTIR & FDCAN_TT_DISTURBING_ERROR_MASK;
+ 8036f72:	687b      	ldr	r3, [r7, #4]
+ 8036f74:	685b      	ldr	r3, [r3, #4]
+ 8036f76:	6a1b      	ldr	r3, [r3, #32]
+ 8036f78:	f403 43fc 	and.w	r3, r3, #32256	@ 0x7e00
+ 8036f7c:	623b      	str	r3, [r7, #32]
+      TTDistErrors &= hfdcan->ttcan->TTIE;
+ 8036f7e:	687b      	ldr	r3, [r7, #4]
+ 8036f80:	685b      	ldr	r3, [r3, #4]
+ 8036f82:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 8036f84:	6a3a      	ldr	r2, [r7, #32]
+ 8036f86:	4013      	ands	r3, r2
+ 8036f88:	623b      	str	r3, [r7, #32]
+      TTFatalErrors = hfdcan->ttcan->TTIR & FDCAN_TT_FATAL_ERROR_MASK;
+ 8036f8a:	687b      	ldr	r3, [r7, #4]
+ 8036f8c:	685b      	ldr	r3, [r3, #4]
+ 8036f8e:	6a1b      	ldr	r3, [r3, #32]
+ 8036f90:	f403 23f0 	and.w	r3, r3, #491520	@ 0x78000
+ 8036f94:	61fb      	str	r3, [r7, #28]
+      TTFatalErrors &= hfdcan->ttcan->TTIE;
+ 8036f96:	687b      	ldr	r3, [r7, #4]
+ 8036f98:	685b      	ldr	r3, [r3, #4]
+ 8036f9a:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 8036f9c:	69fa      	ldr	r2, [r7, #28]
+ 8036f9e:	4013      	ands	r3, r2
+ 8036fa0:	61fb      	str	r3, [r7, #28]
+      itsourceTTIE = hfdcan->ttcan->TTIE;
+ 8036fa2:	687b      	ldr	r3, [r7, #4]
+ 8036fa4:	685b      	ldr	r3, [r3, #4]
+ 8036fa6:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 8036fa8:	61bb      	str	r3, [r7, #24]
+      itflagTTIR = hfdcan->ttcan->TTIR;
+ 8036faa:	687b      	ldr	r3, [r7, #4]
+ 8036fac:	685b      	ldr	r3, [r3, #4]
+ 8036fae:	6a1b      	ldr	r3, [r3, #32]
+ 8036fb0:	617b      	str	r3, [r7, #20]
+
+      /* TT Schedule Synchronization interrupts management **********************/
+      if (TTSchedSyncITs != 0U)
+ 8036fb2:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
+ 8036fb4:	2b00      	cmp	r3, #0
+ 8036fb6:	d007      	beq.n	8036fc8 <HAL_FDCAN_IRQHandler+0x3cc>
+      {
+        /* Clear the TT Schedule Synchronization flags */
+        __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTSchedSyncITs);
+ 8036fb8:	687b      	ldr	r3, [r7, #4]
+ 8036fba:	685b      	ldr	r3, [r3, #4]
+ 8036fbc:	6afa      	ldr	r2, [r7, #44]	@ 0x2c
+ 8036fbe:	621a      	str	r2, [r3, #32]
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+        /* Call registered callback*/
+        hfdcan->TT_ScheduleSyncCallback(hfdcan, TTSchedSyncITs);
+#else
+        /* TT Schedule Synchronization Callback */
+        HAL_FDCAN_TT_ScheduleSyncCallback(hfdcan, TTSchedSyncITs);
+ 8036fc0:	6af9      	ldr	r1, [r7, #44]	@ 0x2c
+ 8036fc2:	6878      	ldr	r0, [r7, #4]
+ 8036fc4:	f000 f8d9 	bl	803717a <HAL_FDCAN_TT_ScheduleSyncCallback>
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+      }
+
+      /* TT Time Mark interrupts management *************************************/
+      if (TTTimeMarkITs != 0U)
+ 8036fc8:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 8036fca:	2b00      	cmp	r3, #0
+ 8036fcc:	d007      	beq.n	8036fde <HAL_FDCAN_IRQHandler+0x3e2>
+      {
+        /* Clear the TT Time Mark flags */
+        __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTTimeMarkITs);
+ 8036fce:	687b      	ldr	r3, [r7, #4]
+ 8036fd0:	685b      	ldr	r3, [r3, #4]
+ 8036fd2:	6aba      	ldr	r2, [r7, #40]	@ 0x28
+ 8036fd4:	621a      	str	r2, [r3, #32]
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+        /* Call registered callback*/
+        hfdcan->TT_TimeMarkCallback(hfdcan, TTTimeMarkITs);
+#else
+        /* TT Time Mark Callback */
+        HAL_FDCAN_TT_TimeMarkCallback(hfdcan, TTTimeMarkITs);
+ 8036fd6:	6ab9      	ldr	r1, [r7, #40]	@ 0x28
+ 8036fd8:	6878      	ldr	r0, [r7, #4]
+ 8036fda:	f000 f8d9 	bl	8037190 <HAL_FDCAN_TT_TimeMarkCallback>
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+      }
+
+      /* TT Stop Watch interrupt management *************************************/
+      if (FDCAN_CHECK_IT_SOURCE(itsourceTTIE, FDCAN_TT_IT_STOP_WATCH) != RESET)
+ 8036fde:	69bb      	ldr	r3, [r7, #24]
+ 8036fe0:	f003 0340 	and.w	r3, r3, #64	@ 0x40
+ 8036fe4:	2b00      	cmp	r3, #0
+ 8036fe6:	d019      	beq.n	803701c <HAL_FDCAN_IRQHandler+0x420>
+      {
+        if (FDCAN_CHECK_FLAG(itflagTTIR, FDCAN_TT_FLAG_STOP_WATCH) != RESET)
+ 8036fe8:	697b      	ldr	r3, [r7, #20]
+ 8036fea:	f003 0340 	and.w	r3, r3, #64	@ 0x40
+ 8036fee:	2b00      	cmp	r3, #0
+ 8036ff0:	d014      	beq.n	803701c <HAL_FDCAN_IRQHandler+0x420>
+        {
+          /* Retrieve Stop watch Time and Cycle count */
+          SWTime = ((hfdcan->ttcan->TTCPT & FDCAN_TTCPT_SWV) >> FDCAN_TTCPT_SWV_Pos);
+ 8036ff2:	687b      	ldr	r3, [r7, #4]
+ 8036ff4:	685b      	ldr	r3, [r3, #4]
+ 8036ff6:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 8036ff8:	0c1b      	lsrs	r3, r3, #16
+ 8036ffa:	b29b      	uxth	r3, r3
+ 8036ffc:	613b      	str	r3, [r7, #16]
+          SWCycleCount = ((hfdcan->ttcan->TTCPT & FDCAN_TTCPT_CCV) >> FDCAN_TTCPT_CCV_Pos);
+ 8036ffe:	687b      	ldr	r3, [r7, #4]
+ 8037000:	685b      	ldr	r3, [r3, #4]
+ 8037002:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 8037004:	f003 033f 	and.w	r3, r3, #63	@ 0x3f
+ 8037008:	60fb      	str	r3, [r7, #12]
+
+          /* Clear the TT Stop Watch flag */
+          __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, FDCAN_TT_FLAG_STOP_WATCH);
+ 803700a:	687b      	ldr	r3, [r7, #4]
+ 803700c:	685b      	ldr	r3, [r3, #4]
+ 803700e:	2240      	movs	r2, #64	@ 0x40
+ 8037010:	621a      	str	r2, [r3, #32]
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+          /* Call registered callback*/
+          hfdcan->TT_StopWatchCallback(hfdcan, SWTime, SWCycleCount);
+#else
+          /* TT Stop Watch Callback */
+          HAL_FDCAN_TT_StopWatchCallback(hfdcan, SWTime, SWCycleCount);
+ 8037012:	68fa      	ldr	r2, [r7, #12]
+ 8037014:	6939      	ldr	r1, [r7, #16]
+ 8037016:	6878      	ldr	r0, [r7, #4]
+ 8037018:	f000 f8c5 	bl	80371a6 <HAL_FDCAN_TT_StopWatchCallback>
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+        }
+      }
+
+      /* TT Global Time interrupts management ***********************************/
+      if (TTGlobTimeITs != 0U)
+ 803701c:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 803701e:	2b00      	cmp	r3, #0
+ 8037020:	d007      	beq.n	8037032 <HAL_FDCAN_IRQHandler+0x436>
+      {
+        /* Clear the TT Global Time flags */
+        __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTGlobTimeITs);
+ 8037022:	687b      	ldr	r3, [r7, #4]
+ 8037024:	685b      	ldr	r3, [r3, #4]
+ 8037026:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
+ 8037028:	621a      	str	r2, [r3, #32]
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+        /* Call registered callback*/
+        hfdcan->TT_GlobalTimeCallback(hfdcan, TTGlobTimeITs);
+#else
+        /* TT Global Time Callback */
+        HAL_FDCAN_TT_GlobalTimeCallback(hfdcan, TTGlobTimeITs);
+ 803702a:	6a79      	ldr	r1, [r7, #36]	@ 0x24
+ 803702c:	6878      	ldr	r0, [r7, #4]
+ 803702e:	f000 f8c6 	bl	80371be <HAL_FDCAN_TT_GlobalTimeCallback>
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+      }
+
+      /* TT Disturbing Error interrupts management ******************************/
+      if (TTDistErrors != 0U)
+ 8037032:	6a3b      	ldr	r3, [r7, #32]
+ 8037034:	2b00      	cmp	r3, #0
+ 8037036:	d00b      	beq.n	8037050 <HAL_FDCAN_IRQHandler+0x454>
+      {
+        /* Clear the TT Disturbing Error flags */
+        __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTDistErrors);
+ 8037038:	687b      	ldr	r3, [r7, #4]
+ 803703a:	685b      	ldr	r3, [r3, #4]
+ 803703c:	6a3a      	ldr	r2, [r7, #32]
+ 803703e:	621a      	str	r2, [r3, #32]
+
+        /* Update error code */
+        hfdcan->ErrorCode |= TTDistErrors;
+ 8037040:	687b      	ldr	r3, [r7, #4]
+ 8037042:	f8d3 209c 	ldr.w	r2, [r3, #156]	@ 0x9c
+ 8037046:	6a3b      	ldr	r3, [r7, #32]
+ 8037048:	431a      	orrs	r2, r3
+ 803704a:	687b      	ldr	r3, [r7, #4]
+ 803704c:	f8c3 209c 	str.w	r2, [r3, #156]	@ 0x9c
+      }
+
+      /* TT Fatal Error interrupts management ***********************************/
+      if (TTFatalErrors != 0U)
+ 8037050:	69fb      	ldr	r3, [r7, #28]
+ 8037052:	2b00      	cmp	r3, #0
+ 8037054:	d00b      	beq.n	803706e <HAL_FDCAN_IRQHandler+0x472>
+      {
+        /* Clear the TT Fatal Error flags */
+        __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTFatalErrors);
+ 8037056:	687b      	ldr	r3, [r7, #4]
+ 8037058:	685b      	ldr	r3, [r3, #4]
+ 803705a:	69fa      	ldr	r2, [r7, #28]
+ 803705c:	621a      	str	r2, [r3, #32]
+
+        /* Update error code */
+        hfdcan->ErrorCode |= TTFatalErrors;
+ 803705e:	687b      	ldr	r3, [r7, #4]
+ 8037060:	f8d3 209c 	ldr.w	r2, [r3, #156]	@ 0x9c
+ 8037064:	69fb      	ldr	r3, [r7, #28]
+ 8037066:	431a      	orrs	r2, r3
+ 8037068:	687b      	ldr	r3, [r7, #4]
+ 803706a:	f8c3 209c 	str.w	r2, [r3, #156]	@ 0x9c
+      }
+    }
+  }
+
+  if (hfdcan->ErrorCode != HAL_FDCAN_ERROR_NONE)
+ 803706e:	687b      	ldr	r3, [r7, #4]
+ 8037070:	f8d3 309c 	ldr.w	r3, [r3, #156]	@ 0x9c
+ 8037074:	2b00      	cmp	r3, #0
+ 8037076:	d002      	beq.n	803707e <HAL_FDCAN_IRQHandler+0x482>
+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
+    /* Call registered callback*/
+    hfdcan->ErrorCallback(hfdcan);
+#else
+    /* Error Callback */
+    HAL_FDCAN_ErrorCallback(hfdcan);
+ 8037078:	6878      	ldr	r0, [r7, #4]
+ 803707a:	f000 f874 	bl	8037166 <HAL_FDCAN_ErrorCallback>
+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
+  }
+}
+ 803707e:	bf00      	nop
+ 8037080:	3758      	adds	r7, #88	@ 0x58
+ 8037082:	46bd      	mov	sp, r7
+ 8037084:	bd80      	pop	{r7, pc}
+ 8037086:	bf00      	nop
+ 8037088:	4000a800 	.word	0x4000a800
+ 803708c:	3fcfffff 	.word	0x3fcfffff
+ 8037090:	4000a000 	.word	0x4000a000
+
+08037094 <HAL_FDCAN_ClockCalibrationCallback>:
+  * @param  ClkCalibrationITs indicates which Clock Calibration interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_Clock_Calibration_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_ClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs)
+{
+ 8037094:	b480      	push	{r7}
+ 8037096:	b083      	sub	sp, #12
+ 8037098:	af00      	add	r7, sp, #0
+ 803709a:	6078      	str	r0, [r7, #4]
+ 803709c:	6039      	str	r1, [r7, #0]
+  UNUSED(ClkCalibrationITs);
+
+  /* NOTE: This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_ClockCalibrationCallback could be implemented in the user file
+   */
+}
+ 803709e:	bf00      	nop
+ 80370a0:	370c      	adds	r7, #12
+ 80370a2:	46bd      	mov	sp, r7
+ 80370a4:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80370a8:	4770      	bx	lr
+
+080370aa <HAL_FDCAN_TxEventFifoCallback>:
+  * @param  TxEventFifoITs indicates which Tx Event FIFO interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_Tx_Event_Fifo_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs)
+{
+ 80370aa:	b480      	push	{r7}
+ 80370ac:	b083      	sub	sp, #12
+ 80370ae:	af00      	add	r7, sp, #0
+ 80370b0:	6078      	str	r0, [r7, #4]
+ 80370b2:	6039      	str	r1, [r7, #0]
+  UNUSED(TxEventFifoITs);
+
+  /* NOTE: This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TxEventFifoCallback could be implemented in the user file
+   */
+}
+ 80370b4:	bf00      	nop
+ 80370b6:	370c      	adds	r7, #12
+ 80370b8:	46bd      	mov	sp, r7
+ 80370ba:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80370be:	4770      	bx	lr
+
+080370c0 <HAL_FDCAN_RxFifo1Callback>:
+  * @param  RxFifo1ITs indicates which Rx FIFO 1 interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_Rx_Fifo1_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs)
+{
+ 80370c0:	b480      	push	{r7}
+ 80370c2:	b083      	sub	sp, #12
+ 80370c4:	af00      	add	r7, sp, #0
+ 80370c6:	6078      	str	r0, [r7, #4]
+ 80370c8:	6039      	str	r1, [r7, #0]
+  UNUSED(RxFifo1ITs);
+
+  /* NOTE: This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_RxFifo1Callback could be implemented in the user file
+   */
+}
+ 80370ca:	bf00      	nop
+ 80370cc:	370c      	adds	r7, #12
+ 80370ce:	46bd      	mov	sp, r7
+ 80370d0:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80370d4:	4770      	bx	lr
+
+080370d6 <HAL_FDCAN_TxFifoEmptyCallback>:
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+ 80370d6:	b480      	push	{r7}
+ 80370d8:	b083      	sub	sp, #12
+ 80370da:	af00      	add	r7, sp, #0
+ 80370dc:	6078      	str	r0, [r7, #4]
+  UNUSED(hfdcan);
+
+  /* NOTE: This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TxFifoEmptyCallback could be implemented in the user file
+   */
+}
+ 80370de:	bf00      	nop
+ 80370e0:	370c      	adds	r7, #12
+ 80370e2:	46bd      	mov	sp, r7
+ 80370e4:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80370e8:	4770      	bx	lr
+
+080370ea <HAL_FDCAN_TxBufferCompleteCallback>:
+  * @param  BufferIndexes Indexes of the transmitted buffers.
+  *         This parameter can be any combination of @arg FDCAN_Tx_location.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
+{
+ 80370ea:	b480      	push	{r7}
+ 80370ec:	b083      	sub	sp, #12
+ 80370ee:	af00      	add	r7, sp, #0
+ 80370f0:	6078      	str	r0, [r7, #4]
+ 80370f2:	6039      	str	r1, [r7, #0]
+  UNUSED(BufferIndexes);
+
+  /* NOTE: This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TxBufferCompleteCallback could be implemented in the user file
+   */
+}
+ 80370f4:	bf00      	nop
+ 80370f6:	370c      	adds	r7, #12
+ 80370f8:	46bd      	mov	sp, r7
+ 80370fa:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80370fe:	4770      	bx	lr
+
+08037100 <HAL_FDCAN_TxBufferAbortCallback>:
+  * @param  BufferIndexes Indexes of the aborted buffers.
+  *         This parameter can be any combination of @arg FDCAN_Tx_location.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
+{
+ 8037100:	b480      	push	{r7}
+ 8037102:	b083      	sub	sp, #12
+ 8037104:	af00      	add	r7, sp, #0
+ 8037106:	6078      	str	r0, [r7, #4]
+ 8037108:	6039      	str	r1, [r7, #0]
+  UNUSED(BufferIndexes);
+
+  /* NOTE: This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TxBufferAbortCallback could be implemented in the user file
+   */
+}
+ 803710a:	bf00      	nop
+ 803710c:	370c      	adds	r7, #12
+ 803710e:	46bd      	mov	sp, r7
+ 8037110:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8037114:	4770      	bx	lr
+
+08037116 <HAL_FDCAN_RxBufferNewMessageCallback>:
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval None
+  */
+__weak void HAL_FDCAN_RxBufferNewMessageCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+ 8037116:	b480      	push	{r7}
+ 8037118:	b083      	sub	sp, #12
+ 803711a:	af00      	add	r7, sp, #0
+ 803711c:	6078      	str	r0, [r7, #4]
+  UNUSED(hfdcan);
+
+  /* NOTE: This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_RxBufferNewMessageCallback could be implemented in the user file
+   */
+}
+ 803711e:	bf00      	nop
+ 8037120:	370c      	adds	r7, #12
+ 8037122:	46bd      	mov	sp, r7
+ 8037124:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8037128:	4770      	bx	lr
+
+0803712a <HAL_FDCAN_TimestampWraparoundCallback>:
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+ 803712a:	b480      	push	{r7}
+ 803712c:	b083      	sub	sp, #12
+ 803712e:	af00      	add	r7, sp, #0
+ 8037130:	6078      	str	r0, [r7, #4]
+  UNUSED(hfdcan);
+
+  /* NOTE: This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TimestampWraparoundCallback could be implemented in the user file
+   */
+}
+ 8037132:	bf00      	nop
+ 8037134:	370c      	adds	r7, #12
+ 8037136:	46bd      	mov	sp, r7
+ 8037138:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 803713c:	4770      	bx	lr
+
+0803713e <HAL_FDCAN_TimeoutOccurredCallback>:
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+ 803713e:	b480      	push	{r7}
+ 8037140:	b083      	sub	sp, #12
+ 8037142:	af00      	add	r7, sp, #0
+ 8037144:	6078      	str	r0, [r7, #4]
+  UNUSED(hfdcan);
+
+  /* NOTE: This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TimeoutOccurredCallback could be implemented in the user file
+   */
+}
+ 8037146:	bf00      	nop
+ 8037148:	370c      	adds	r7, #12
+ 803714a:	46bd      	mov	sp, r7
+ 803714c:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8037150:	4770      	bx	lr
+
+08037152 <HAL_FDCAN_HighPriorityMessageCallback>:
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval None
+  */
+__weak void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+ 8037152:	b480      	push	{r7}
+ 8037154:	b083      	sub	sp, #12
+ 8037156:	af00      	add	r7, sp, #0
+ 8037158:	6078      	str	r0, [r7, #4]
+  UNUSED(hfdcan);
+
+  /* NOTE: This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_HighPriorityMessageCallback could be implemented in the user file
+   */
+}
+ 803715a:	bf00      	nop
+ 803715c:	370c      	adds	r7, #12
+ 803715e:	46bd      	mov	sp, r7
+ 8037160:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8037164:	4770      	bx	lr
+
+08037166 <HAL_FDCAN_ErrorCallback>:
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval None
+  */
+__weak void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+ 8037166:	b480      	push	{r7}
+ 8037168:	b083      	sub	sp, #12
+ 803716a:	af00      	add	r7, sp, #0
+ 803716c:	6078      	str	r0, [r7, #4]
+  UNUSED(hfdcan);
+
+  /* NOTE: This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_ErrorCallback could be implemented in the user file
+   */
+}
+ 803716e:	bf00      	nop
+ 8037170:	370c      	adds	r7, #12
+ 8037172:	46bd      	mov	sp, r7
+ 8037174:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8037178:	4770      	bx	lr
+
+0803717a <HAL_FDCAN_TT_ScheduleSyncCallback>:
+  * @param  TTSchedSyncITs indicates which TT Schedule Synchronization interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_TTScheduleSynchronization_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TT_ScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs)
+{
+ 803717a:	b480      	push	{r7}
+ 803717c:	b083      	sub	sp, #12
+ 803717e:	af00      	add	r7, sp, #0
+ 8037180:	6078      	str	r0, [r7, #4]
+ 8037182:	6039      	str	r1, [r7, #0]
+  UNUSED(TTSchedSyncITs);
+
+  /* NOTE: This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TT_ScheduleSyncCallback could be implemented in the user file
+   */
+}
+ 8037184:	bf00      	nop
+ 8037186:	370c      	adds	r7, #12
+ 8037188:	46bd      	mov	sp, r7
+ 803718a:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 803718e:	4770      	bx	lr
+
+08037190 <HAL_FDCAN_TT_TimeMarkCallback>:
+  * @param  TTTimeMarkITs indicates which TT Schedule Synchronization interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_TTTimeMark_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TT_TimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs)
+{
+ 8037190:	b480      	push	{r7}
+ 8037192:	b083      	sub	sp, #12
+ 8037194:	af00      	add	r7, sp, #0
+ 8037196:	6078      	str	r0, [r7, #4]
+ 8037198:	6039      	str	r1, [r7, #0]
+  UNUSED(TTTimeMarkITs);
+
+  /* NOTE: This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TT_TimeMarkCallback could be implemented in the user file
+   */
+}
+ 803719a:	bf00      	nop
+ 803719c:	370c      	adds	r7, #12
+ 803719e:	46bd      	mov	sp, r7
+ 80371a0:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80371a4:	4770      	bx	lr
+
+080371a6 <HAL_FDCAN_TT_StopWatchCallback>:
+  * @param  SWCycleCount Cycle count value captured together with SWTime.
+  *         This parameter is a number between 0 and 0x3F.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TT_StopWatchCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount)
+{
+ 80371a6:	b480      	push	{r7}
+ 80371a8:	b085      	sub	sp, #20
+ 80371aa:	af00      	add	r7, sp, #0
+ 80371ac:	60f8      	str	r0, [r7, #12]
+ 80371ae:	60b9      	str	r1, [r7, #8]
+ 80371b0:	607a      	str	r2, [r7, #4]
+  UNUSED(SWCycleCount);
+
+  /* NOTE: This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TT_StopWatchCallback could be implemented in the user file
+   */
+}
+ 80371b2:	bf00      	nop
+ 80371b4:	3714      	adds	r7, #20
+ 80371b6:	46bd      	mov	sp, r7
+ 80371b8:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80371bc:	4770      	bx	lr
+
+080371be <HAL_FDCAN_TT_GlobalTimeCallback>:
+  * @param  TTGlobTimeITs indicates which TT Global Time interrupts are signaled.
+  *         This parameter can be any combination of @arg FDCAN_TTGlobalTime_Interrupts.
+  * @retval None
+  */
+__weak void HAL_FDCAN_TT_GlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs)
+{
+ 80371be:	b480      	push	{r7}
+ 80371c0:	b083      	sub	sp, #12
+ 80371c2:	af00      	add	r7, sp, #0
+ 80371c4:	6078      	str	r0, [r7, #4]
+ 80371c6:	6039      	str	r1, [r7, #0]
+  UNUSED(TTGlobTimeITs);
+
+  /* NOTE: This function Should not be modified, when the callback is needed,
+            the HAL_FDCAN_TT_GlobalTimeCallback could be implemented in the user file
+   */
+}
+ 80371c8:	bf00      	nop
+ 80371ca:	370c      	adds	r7, #12
+ 80371cc:	46bd      	mov	sp, r7
+ 80371ce:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80371d2:	4770      	bx	lr
+
+080371d4 <FDCAN_CalcultateRamBlockAddresses>:
+  * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified FDCAN.
+  * @retval HAL status
+ */
+static HAL_StatusTypeDef FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan)
+{
+ 80371d4:	b480      	push	{r7}
+ 80371d6:	b085      	sub	sp, #20
+ 80371d8:	af00      	add	r7, sp, #0
+ 80371da:	6078      	str	r0, [r7, #4]
+  uint32_t RAMcounter;
+  uint32_t StartAddress;
+
+  StartAddress = hfdcan->Init.MessageRAMOffset;
+ 80371dc:	687b      	ldr	r3, [r7, #4]
+ 80371de:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
+ 80371e0:	60bb      	str	r3, [r7, #8]
+
+  /* Standard filter list start address */
+  MODIFY_REG(hfdcan->Instance->SIDFC, FDCAN_SIDFC_FLSSA, (StartAddress << FDCAN_SIDFC_FLSSA_Pos));
+ 80371e2:	687b      	ldr	r3, [r7, #4]
+ 80371e4:	681b      	ldr	r3, [r3, #0]
+ 80371e6:	f8d3 2084 	ldr.w	r2, [r3, #132]	@ 0x84
+ 80371ea:	4ba7      	ldr	r3, [pc, #668]	@ (8037488 <FDCAN_CalcultateRamBlockAddresses+0x2b4>)
+ 80371ec:	4013      	ands	r3, r2
+ 80371ee:	68ba      	ldr	r2, [r7, #8]
+ 80371f0:	0091      	lsls	r1, r2, #2
+ 80371f2:	687a      	ldr	r2, [r7, #4]
+ 80371f4:	6812      	ldr	r2, [r2, #0]
+ 80371f6:	430b      	orrs	r3, r1
+ 80371f8:	f8c2 3084 	str.w	r3, [r2, #132]	@ 0x84
+
+  /* Standard filter elements number */
+  MODIFY_REG(hfdcan->Instance->SIDFC, FDCAN_SIDFC_LSS, (hfdcan->Init.StdFiltersNbr << FDCAN_SIDFC_LSS_Pos));
+ 80371fc:	687b      	ldr	r3, [r7, #4]
+ 80371fe:	681b      	ldr	r3, [r3, #0]
+ 8037200:	f8d3 3084 	ldr.w	r3, [r3, #132]	@ 0x84
+ 8037204:	f423 017f 	bic.w	r1, r3, #16711680	@ 0xff0000
+ 8037208:	687b      	ldr	r3, [r7, #4]
+ 803720a:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
+ 803720c:	041a      	lsls	r2, r3, #16
+ 803720e:	687b      	ldr	r3, [r7, #4]
+ 8037210:	681b      	ldr	r3, [r3, #0]
+ 8037212:	430a      	orrs	r2, r1
+ 8037214:	f8c3 2084 	str.w	r2, [r3, #132]	@ 0x84
+
+  /* Extended filter list start address */
+  StartAddress += hfdcan->Init.StdFiltersNbr;
+ 8037218:	687b      	ldr	r3, [r7, #4]
+ 803721a:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
+ 803721c:	68ba      	ldr	r2, [r7, #8]
+ 803721e:	4413      	add	r3, r2
+ 8037220:	60bb      	str	r3, [r7, #8]
+  MODIFY_REG(hfdcan->Instance->XIDFC, FDCAN_XIDFC_FLESA, (StartAddress << FDCAN_XIDFC_FLESA_Pos));
+ 8037222:	687b      	ldr	r3, [r7, #4]
+ 8037224:	681b      	ldr	r3, [r3, #0]
+ 8037226:	f8d3 2088 	ldr.w	r2, [r3, #136]	@ 0x88
+ 803722a:	4b97      	ldr	r3, [pc, #604]	@ (8037488 <FDCAN_CalcultateRamBlockAddresses+0x2b4>)
+ 803722c:	4013      	ands	r3, r2
+ 803722e:	68ba      	ldr	r2, [r7, #8]
+ 8037230:	0091      	lsls	r1, r2, #2
+ 8037232:	687a      	ldr	r2, [r7, #4]
+ 8037234:	6812      	ldr	r2, [r2, #0]
+ 8037236:	430b      	orrs	r3, r1
+ 8037238:	f8c2 3088 	str.w	r3, [r2, #136]	@ 0x88
+
+  /* Extended filter elements number */
+  MODIFY_REG(hfdcan->Instance->XIDFC, FDCAN_XIDFC_LSE, (hfdcan->Init.ExtFiltersNbr << FDCAN_XIDFC_LSE_Pos));
+ 803723c:	687b      	ldr	r3, [r7, #4]
+ 803723e:	681b      	ldr	r3, [r3, #0]
+ 8037240:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
+ 8037244:	f423 01fe 	bic.w	r1, r3, #8323072	@ 0x7f0000
+ 8037248:	687b      	ldr	r3, [r7, #4]
+ 803724a:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 803724c:	041a      	lsls	r2, r3, #16
+ 803724e:	687b      	ldr	r3, [r7, #4]
+ 8037250:	681b      	ldr	r3, [r3, #0]
+ 8037252:	430a      	orrs	r2, r1
+ 8037254:	f8c3 2088 	str.w	r2, [r3, #136]	@ 0x88
+
+  /* Rx FIFO 0 start address */
+  StartAddress += (hfdcan->Init.ExtFiltersNbr * 2U);
+ 8037258:	687b      	ldr	r3, [r7, #4]
+ 803725a:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 803725c:	005b      	lsls	r3, r3, #1
+ 803725e:	68ba      	ldr	r2, [r7, #8]
+ 8037260:	4413      	add	r3, r2
+ 8037262:	60bb      	str	r3, [r7, #8]
+  MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0SA, (StartAddress << FDCAN_RXF0C_F0SA_Pos));
+ 8037264:	687b      	ldr	r3, [r7, #4]
+ 8037266:	681b      	ldr	r3, [r3, #0]
+ 8037268:	f8d3 20a0 	ldr.w	r2, [r3, #160]	@ 0xa0
+ 803726c:	4b86      	ldr	r3, [pc, #536]	@ (8037488 <FDCAN_CalcultateRamBlockAddresses+0x2b4>)
+ 803726e:	4013      	ands	r3, r2
+ 8037270:	68ba      	ldr	r2, [r7, #8]
+ 8037272:	0091      	lsls	r1, r2, #2
+ 8037274:	687a      	ldr	r2, [r7, #4]
+ 8037276:	6812      	ldr	r2, [r2, #0]
+ 8037278:	430b      	orrs	r3, r1
+ 803727a:	f8c2 30a0 	str.w	r3, [r2, #160]	@ 0xa0
+
+  /* Rx FIFO 0 elements number */
+  MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0S, (hfdcan->Init.RxFifo0ElmtsNbr << FDCAN_RXF0C_F0S_Pos));
+ 803727e:	687b      	ldr	r3, [r7, #4]
+ 8037280:	681b      	ldr	r3, [r3, #0]
+ 8037282:	f8d3 30a0 	ldr.w	r3, [r3, #160]	@ 0xa0
+ 8037286:	f423 01fe 	bic.w	r1, r3, #8323072	@ 0x7f0000
+ 803728a:	687b      	ldr	r3, [r7, #4]
+ 803728c:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
+ 803728e:	041a      	lsls	r2, r3, #16
+ 8037290:	687b      	ldr	r3, [r7, #4]
+ 8037292:	681b      	ldr	r3, [r3, #0]
+ 8037294:	430a      	orrs	r2, r1
+ 8037296:	f8c3 20a0 	str.w	r2, [r3, #160]	@ 0xa0
+
+  /* Rx FIFO 1 start address */
+  StartAddress += (hfdcan->Init.RxFifo0ElmtsNbr * hfdcan->Init.RxFifo0ElmtSize);
+ 803729a:	687b      	ldr	r3, [r7, #4]
+ 803729c:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
+ 803729e:	687a      	ldr	r2, [r7, #4]
+ 80372a0:	6c52      	ldr	r2, [r2, #68]	@ 0x44
+ 80372a2:	fb02 f303 	mul.w	r3, r2, r3
+ 80372a6:	68ba      	ldr	r2, [r7, #8]
+ 80372a8:	4413      	add	r3, r2
+ 80372aa:	60bb      	str	r3, [r7, #8]
+  MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1SA, (StartAddress << FDCAN_RXF1C_F1SA_Pos));
+ 80372ac:	687b      	ldr	r3, [r7, #4]
+ 80372ae:	681b      	ldr	r3, [r3, #0]
+ 80372b0:	f8d3 20b0 	ldr.w	r2, [r3, #176]	@ 0xb0
+ 80372b4:	4b74      	ldr	r3, [pc, #464]	@ (8037488 <FDCAN_CalcultateRamBlockAddresses+0x2b4>)
+ 80372b6:	4013      	ands	r3, r2
+ 80372b8:	68ba      	ldr	r2, [r7, #8]
+ 80372ba:	0091      	lsls	r1, r2, #2
+ 80372bc:	687a      	ldr	r2, [r7, #4]
+ 80372be:	6812      	ldr	r2, [r2, #0]
+ 80372c0:	430b      	orrs	r3, r1
+ 80372c2:	f8c2 30b0 	str.w	r3, [r2, #176]	@ 0xb0
+
+  /* Rx FIFO 1 elements number */
+  MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1S, (hfdcan->Init.RxFifo1ElmtsNbr << FDCAN_RXF1C_F1S_Pos));
+ 80372c6:	687b      	ldr	r3, [r7, #4]
+ 80372c8:	681b      	ldr	r3, [r3, #0]
+ 80372ca:	f8d3 30b0 	ldr.w	r3, [r3, #176]	@ 0xb0
+ 80372ce:	f423 01fe 	bic.w	r1, r3, #8323072	@ 0x7f0000
+ 80372d2:	687b      	ldr	r3, [r7, #4]
+ 80372d4:	6c9b      	ldr	r3, [r3, #72]	@ 0x48
+ 80372d6:	041a      	lsls	r2, r3, #16
+ 80372d8:	687b      	ldr	r3, [r7, #4]
+ 80372da:	681b      	ldr	r3, [r3, #0]
+ 80372dc:	430a      	orrs	r2, r1
+ 80372de:	f8c3 20b0 	str.w	r2, [r3, #176]	@ 0xb0
+
+  /* Rx buffer list start address */
+  StartAddress += (hfdcan->Init.RxFifo1ElmtsNbr * hfdcan->Init.RxFifo1ElmtSize);
+ 80372e2:	687b      	ldr	r3, [r7, #4]
+ 80372e4:	6c9b      	ldr	r3, [r3, #72]	@ 0x48
+ 80372e6:	687a      	ldr	r2, [r7, #4]
+ 80372e8:	6cd2      	ldr	r2, [r2, #76]	@ 0x4c
+ 80372ea:	fb02 f303 	mul.w	r3, r2, r3
+ 80372ee:	68ba      	ldr	r2, [r7, #8]
+ 80372f0:	4413      	add	r3, r2
+ 80372f2:	60bb      	str	r3, [r7, #8]
+  MODIFY_REG(hfdcan->Instance->RXBC, FDCAN_RXBC_RBSA, (StartAddress << FDCAN_RXBC_RBSA_Pos));
+ 80372f4:	687b      	ldr	r3, [r7, #4]
+ 80372f6:	681b      	ldr	r3, [r3, #0]
+ 80372f8:	f8d3 20ac 	ldr.w	r2, [r3, #172]	@ 0xac
+ 80372fc:	4b62      	ldr	r3, [pc, #392]	@ (8037488 <FDCAN_CalcultateRamBlockAddresses+0x2b4>)
+ 80372fe:	4013      	ands	r3, r2
+ 8037300:	68ba      	ldr	r2, [r7, #8]
+ 8037302:	0091      	lsls	r1, r2, #2
+ 8037304:	687a      	ldr	r2, [r7, #4]
+ 8037306:	6812      	ldr	r2, [r2, #0]
+ 8037308:	430b      	orrs	r3, r1
+ 803730a:	f8c2 30ac 	str.w	r3, [r2, #172]	@ 0xac
+
+  /* Tx event FIFO start address */
+  StartAddress += (hfdcan->Init.RxBuffersNbr * hfdcan->Init.RxBufferSize);
+ 803730e:	687b      	ldr	r3, [r7, #4]
+ 8037310:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
+ 8037312:	687a      	ldr	r2, [r7, #4]
+ 8037314:	6d52      	ldr	r2, [r2, #84]	@ 0x54
+ 8037316:	fb02 f303 	mul.w	r3, r2, r3
+ 803731a:	68ba      	ldr	r2, [r7, #8]
+ 803731c:	4413      	add	r3, r2
+ 803731e:	60bb      	str	r3, [r7, #8]
+  MODIFY_REG(hfdcan->Instance->TXEFC, FDCAN_TXEFC_EFSA, (StartAddress << FDCAN_TXEFC_EFSA_Pos));
+ 8037320:	687b      	ldr	r3, [r7, #4]
+ 8037322:	681b      	ldr	r3, [r3, #0]
+ 8037324:	f8d3 20f0 	ldr.w	r2, [r3, #240]	@ 0xf0
+ 8037328:	4b57      	ldr	r3, [pc, #348]	@ (8037488 <FDCAN_CalcultateRamBlockAddresses+0x2b4>)
+ 803732a:	4013      	ands	r3, r2
+ 803732c:	68ba      	ldr	r2, [r7, #8]
+ 803732e:	0091      	lsls	r1, r2, #2
+ 8037330:	687a      	ldr	r2, [r7, #4]
+ 8037332:	6812      	ldr	r2, [r2, #0]
+ 8037334:	430b      	orrs	r3, r1
+ 8037336:	f8c2 30f0 	str.w	r3, [r2, #240]	@ 0xf0
+
+  /* Tx event FIFO elements number */
+  MODIFY_REG(hfdcan->Instance->TXEFC, FDCAN_TXEFC_EFS, (hfdcan->Init.TxEventsNbr << FDCAN_TXEFC_EFS_Pos));
+ 803733a:	687b      	ldr	r3, [r7, #4]
+ 803733c:	681b      	ldr	r3, [r3, #0]
+ 803733e:	f8d3 30f0 	ldr.w	r3, [r3, #240]	@ 0xf0
+ 8037342:	f423 117c 	bic.w	r1, r3, #4128768	@ 0x3f0000
+ 8037346:	687b      	ldr	r3, [r7, #4]
+ 8037348:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
+ 803734a:	041a      	lsls	r2, r3, #16
+ 803734c:	687b      	ldr	r3, [r7, #4]
+ 803734e:	681b      	ldr	r3, [r3, #0]
+ 8037350:	430a      	orrs	r2, r1
+ 8037352:	f8c3 20f0 	str.w	r2, [r3, #240]	@ 0xf0
+
+  /* Tx buffer list start address */
+  StartAddress += (hfdcan->Init.TxEventsNbr * 2U);
+ 8037356:	687b      	ldr	r3, [r7, #4]
+ 8037358:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
+ 803735a:	005b      	lsls	r3, r3, #1
+ 803735c:	68ba      	ldr	r2, [r7, #8]
+ 803735e:	4413      	add	r3, r2
+ 8037360:	60bb      	str	r3, [r7, #8]
+  MODIFY_REG(hfdcan->Instance->TXBC, FDCAN_TXBC_TBSA, (StartAddress << FDCAN_TXBC_TBSA_Pos));
+ 8037362:	687b      	ldr	r3, [r7, #4]
+ 8037364:	681b      	ldr	r3, [r3, #0]
+ 8037366:	f8d3 20c0 	ldr.w	r2, [r3, #192]	@ 0xc0
+ 803736a:	4b47      	ldr	r3, [pc, #284]	@ (8037488 <FDCAN_CalcultateRamBlockAddresses+0x2b4>)
+ 803736c:	4013      	ands	r3, r2
+ 803736e:	68ba      	ldr	r2, [r7, #8]
+ 8037370:	0091      	lsls	r1, r2, #2
+ 8037372:	687a      	ldr	r2, [r7, #4]
+ 8037374:	6812      	ldr	r2, [r2, #0]
+ 8037376:	430b      	orrs	r3, r1
+ 8037378:	f8c2 30c0 	str.w	r3, [r2, #192]	@ 0xc0
+
+  /* Dedicated Tx buffers number */
+  MODIFY_REG(hfdcan->Instance->TXBC, FDCAN_TXBC_NDTB, (hfdcan->Init.TxBuffersNbr << FDCAN_TXBC_NDTB_Pos));
+ 803737c:	687b      	ldr	r3, [r7, #4]
+ 803737e:	681b      	ldr	r3, [r3, #0]
+ 8037380:	f8d3 30c0 	ldr.w	r3, [r3, #192]	@ 0xc0
+ 8037384:	f423 117c 	bic.w	r1, r3, #4128768	@ 0x3f0000
+ 8037388:	687b      	ldr	r3, [r7, #4]
+ 803738a:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
+ 803738c:	041a      	lsls	r2, r3, #16
+ 803738e:	687b      	ldr	r3, [r7, #4]
+ 8037390:	681b      	ldr	r3, [r3, #0]
+ 8037392:	430a      	orrs	r2, r1
+ 8037394:	f8c3 20c0 	str.w	r2, [r3, #192]	@ 0xc0
+
+  /* Tx FIFO/queue elements number */
+  MODIFY_REG(hfdcan->Instance->TXBC, FDCAN_TXBC_TFQS, (hfdcan->Init.TxFifoQueueElmtsNbr << FDCAN_TXBC_TFQS_Pos));
+ 8037398:	687b      	ldr	r3, [r7, #4]
+ 803739a:	681b      	ldr	r3, [r3, #0]
+ 803739c:	f8d3 30c0 	ldr.w	r3, [r3, #192]	@ 0xc0
+ 80373a0:	f023 517c 	bic.w	r1, r3, #1056964608	@ 0x3f000000
+ 80373a4:	687b      	ldr	r3, [r7, #4]
+ 80373a6:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
+ 80373a8:	061a      	lsls	r2, r3, #24
+ 80373aa:	687b      	ldr	r3, [r7, #4]
+ 80373ac:	681b      	ldr	r3, [r3, #0]
+ 80373ae:	430a      	orrs	r2, r1
+ 80373b0:	f8c3 20c0 	str.w	r2, [r3, #192]	@ 0xc0
+
+  hfdcan->msgRam.StandardFilterSA = SRAMCAN_BASE + (hfdcan->Init.MessageRAMOffset * 4U);
+ 80373b4:	687b      	ldr	r3, [r7, #4]
+ 80373b6:	6b5a      	ldr	r2, [r3, #52]	@ 0x34
+ 80373b8:	4b34      	ldr	r3, [pc, #208]	@ (803748c <FDCAN_CalcultateRamBlockAddresses+0x2b8>)
+ 80373ba:	4413      	add	r3, r2
+ 80373bc:	009a      	lsls	r2, r3, #2
+ 80373be:	687b      	ldr	r3, [r7, #4]
+ 80373c0:	66da      	str	r2, [r3, #108]	@ 0x6c
+  hfdcan->msgRam.ExtendedFilterSA = hfdcan->msgRam.StandardFilterSA + (hfdcan->Init.StdFiltersNbr * 4U);
+ 80373c2:	687b      	ldr	r3, [r7, #4]
+ 80373c4:	6eda      	ldr	r2, [r3, #108]	@ 0x6c
+ 80373c6:	687b      	ldr	r3, [r7, #4]
+ 80373c8:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
+ 80373ca:	009b      	lsls	r3, r3, #2
+ 80373cc:	441a      	add	r2, r3
+ 80373ce:	687b      	ldr	r3, [r7, #4]
+ 80373d0:	671a      	str	r2, [r3, #112]	@ 0x70
+  hfdcan->msgRam.RxFIFO0SA = hfdcan->msgRam.ExtendedFilterSA + (hfdcan->Init.ExtFiltersNbr * 2U * 4U);
+ 80373d2:	687b      	ldr	r3, [r7, #4]
+ 80373d4:	6f1a      	ldr	r2, [r3, #112]	@ 0x70
+ 80373d6:	687b      	ldr	r3, [r7, #4]
+ 80373d8:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 80373da:	00db      	lsls	r3, r3, #3
+ 80373dc:	441a      	add	r2, r3
+ 80373de:	687b      	ldr	r3, [r7, #4]
+ 80373e0:	675a      	str	r2, [r3, #116]	@ 0x74
+  hfdcan->msgRam.RxFIFO1SA = hfdcan->msgRam.RxFIFO0SA +
+ 80373e2:	687b      	ldr	r3, [r7, #4]
+ 80373e4:	6f5a      	ldr	r2, [r3, #116]	@ 0x74
+                             (hfdcan->Init.RxFifo0ElmtsNbr * hfdcan->Init.RxFifo0ElmtSize * 4U);
+ 80373e6:	687b      	ldr	r3, [r7, #4]
+ 80373e8:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
+ 80373ea:	6879      	ldr	r1, [r7, #4]
+ 80373ec:	6c49      	ldr	r1, [r1, #68]	@ 0x44
+ 80373ee:	fb01 f303 	mul.w	r3, r1, r3
+ 80373f2:	009b      	lsls	r3, r3, #2
+  hfdcan->msgRam.RxFIFO1SA = hfdcan->msgRam.RxFIFO0SA +
+ 80373f4:	441a      	add	r2, r3
+ 80373f6:	687b      	ldr	r3, [r7, #4]
+ 80373f8:	679a      	str	r2, [r3, #120]	@ 0x78
+  hfdcan->msgRam.RxBufferSA = hfdcan->msgRam.RxFIFO1SA +
+ 80373fa:	687b      	ldr	r3, [r7, #4]
+ 80373fc:	6f9a      	ldr	r2, [r3, #120]	@ 0x78
+                              (hfdcan->Init.RxFifo1ElmtsNbr * hfdcan->Init.RxFifo1ElmtSize * 4U);
+ 80373fe:	687b      	ldr	r3, [r7, #4]
+ 8037400:	6c9b      	ldr	r3, [r3, #72]	@ 0x48
+ 8037402:	6879      	ldr	r1, [r7, #4]
+ 8037404:	6cc9      	ldr	r1, [r1, #76]	@ 0x4c
+ 8037406:	fb01 f303 	mul.w	r3, r1, r3
+ 803740a:	009b      	lsls	r3, r3, #2
+  hfdcan->msgRam.RxBufferSA = hfdcan->msgRam.RxFIFO1SA +
+ 803740c:	441a      	add	r2, r3
+ 803740e:	687b      	ldr	r3, [r7, #4]
+ 8037410:	67da      	str	r2, [r3, #124]	@ 0x7c
+  hfdcan->msgRam.TxEventFIFOSA = hfdcan->msgRam.RxBufferSA +
+ 8037412:	687b      	ldr	r3, [r7, #4]
+ 8037414:	6fda      	ldr	r2, [r3, #124]	@ 0x7c
+                                 (hfdcan->Init.RxBuffersNbr * hfdcan->Init.RxBufferSize * 4U);
+ 8037416:	687b      	ldr	r3, [r7, #4]
+ 8037418:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
+ 803741a:	6879      	ldr	r1, [r7, #4]
+ 803741c:	6d49      	ldr	r1, [r1, #84]	@ 0x54
+ 803741e:	fb01 f303 	mul.w	r3, r1, r3
+ 8037422:	009b      	lsls	r3, r3, #2
+  hfdcan->msgRam.TxEventFIFOSA = hfdcan->msgRam.RxBufferSA +
+ 8037424:	441a      	add	r2, r3
+ 8037426:	687b      	ldr	r3, [r7, #4]
+ 8037428:	f8c3 2080 	str.w	r2, [r3, #128]	@ 0x80
+  hfdcan->msgRam.TxBufferSA = hfdcan->msgRam.TxEventFIFOSA + (hfdcan->Init.TxEventsNbr * 2U * 4U);
+ 803742c:	687b      	ldr	r3, [r7, #4]
+ 803742e:	f8d3 2080 	ldr.w	r2, [r3, #128]	@ 0x80
+ 8037432:	687b      	ldr	r3, [r7, #4]
+ 8037434:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
+ 8037436:	00db      	lsls	r3, r3, #3
+ 8037438:	441a      	add	r2, r3
+ 803743a:	687b      	ldr	r3, [r7, #4]
+ 803743c:	f8c3 2084 	str.w	r2, [r3, #132]	@ 0x84
+  hfdcan->msgRam.TxFIFOQSA = hfdcan->msgRam.TxBufferSA + (hfdcan->Init.TxBuffersNbr * hfdcan->Init.TxElmtSize * 4U);
+ 8037440:	687b      	ldr	r3, [r7, #4]
+ 8037442:	f8d3 2084 	ldr.w	r2, [r3, #132]	@ 0x84
+ 8037446:	687b      	ldr	r3, [r7, #4]
+ 8037448:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
+ 803744a:	6879      	ldr	r1, [r7, #4]
+ 803744c:	6e89      	ldr	r1, [r1, #104]	@ 0x68
+ 803744e:	fb01 f303 	mul.w	r3, r1, r3
+ 8037452:	009b      	lsls	r3, r3, #2
+ 8037454:	441a      	add	r2, r3
+ 8037456:	687b      	ldr	r3, [r7, #4]
+ 8037458:	f8c3 2088 	str.w	r2, [r3, #136]	@ 0x88
+
+  hfdcan->msgRam.EndAddress = hfdcan->msgRam.TxFIFOQSA +
+ 803745c:	687b      	ldr	r3, [r7, #4]
+ 803745e:	f8d3 2088 	ldr.w	r2, [r3, #136]	@ 0x88
+                              (hfdcan->Init.TxFifoQueueElmtsNbr * hfdcan->Init.TxElmtSize * 4U);
+ 8037462:	687b      	ldr	r3, [r7, #4]
+ 8037464:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
+ 8037466:	6879      	ldr	r1, [r7, #4]
+ 8037468:	6e89      	ldr	r1, [r1, #104]	@ 0x68
+ 803746a:	fb01 f303 	mul.w	r3, r1, r3
+ 803746e:	009b      	lsls	r3, r3, #2
+  hfdcan->msgRam.EndAddress = hfdcan->msgRam.TxFIFOQSA +
+ 8037470:	441a      	add	r2, r3
+ 8037472:	687b      	ldr	r3, [r7, #4]
+ 8037474:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90
+
+  if (hfdcan->msgRam.EndAddress > FDCAN_MESSAGE_RAM_END_ADDRESS) /* Last address of the Message RAM */
+ 8037478:	687b      	ldr	r3, [r7, #4]
+ 803747a:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
+ 803747e:	4a04      	ldr	r2, [pc, #16]	@ (8037490 <FDCAN_CalcultateRamBlockAddresses+0x2bc>)
+ 8037480:	4293      	cmp	r3, r2
+ 8037482:	d915      	bls.n	80374b0 <FDCAN_CalcultateRamBlockAddresses+0x2dc>
+ 8037484:	e006      	b.n	8037494 <FDCAN_CalcultateRamBlockAddresses+0x2c0>
+ 8037486:	bf00      	nop
+ 8037488:	ffff0003 	.word	0xffff0003
+ 803748c:	10002b00 	.word	0x10002b00
+ 8037490:	4000d3fc 	.word	0x4000d3fc
+  {
+    /* Update error code.
+       Message RAM overflow */
+    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
+ 8037494:	687b      	ldr	r3, [r7, #4]
+ 8037496:	f8d3 309c 	ldr.w	r3, [r3, #156]	@ 0x9c
+ 803749a:	f043 0220 	orr.w	r2, r3, #32
+ 803749e:	687b      	ldr	r3, [r7, #4]
+ 80374a0:	f8c3 209c 	str.w	r2, [r3, #156]	@ 0x9c
+
+    /* Change FDCAN state */
+    hfdcan->State = HAL_FDCAN_STATE_ERROR;
+ 80374a4:	687b      	ldr	r3, [r7, #4]
+ 80374a6:	2203      	movs	r2, #3
+ 80374a8:	f883 2098 	strb.w	r2, [r3, #152]	@ 0x98
+
+    return HAL_ERROR;
+ 80374ac:	2301      	movs	r3, #1
+ 80374ae:	e010      	b.n	80374d2 <FDCAN_CalcultateRamBlockAddresses+0x2fe>
+  }
+  else
+  {
+    /* Flush the allocated Message RAM area */
+    for (RAMcounter = hfdcan->msgRam.StandardFilterSA; RAMcounter < hfdcan->msgRam.EndAddress; RAMcounter += 4U)
+ 80374b0:	687b      	ldr	r3, [r7, #4]
+ 80374b2:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
+ 80374b4:	60fb      	str	r3, [r7, #12]
+ 80374b6:	e005      	b.n	80374c4 <FDCAN_CalcultateRamBlockAddresses+0x2f0>
+    {
+      *(uint32_t *)(RAMcounter) = 0x00000000;
+ 80374b8:	68fb      	ldr	r3, [r7, #12]
+ 80374ba:	2200      	movs	r2, #0
+ 80374bc:	601a      	str	r2, [r3, #0]
+    for (RAMcounter = hfdcan->msgRam.StandardFilterSA; RAMcounter < hfdcan->msgRam.EndAddress; RAMcounter += 4U)
+ 80374be:	68fb      	ldr	r3, [r7, #12]
+ 80374c0:	3304      	adds	r3, #4
+ 80374c2:	60fb      	str	r3, [r7, #12]
+ 80374c4:	687b      	ldr	r3, [r7, #4]
+ 80374c6:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
+ 80374ca:	68fa      	ldr	r2, [r7, #12]
+ 80374cc:	429a      	cmp	r2, r3
+ 80374ce:	d3f3      	bcc.n	80374b8 <FDCAN_CalcultateRamBlockAddresses+0x2e4>
+    }
+  }
+
+  /* Return function status */
+  return HAL_OK;
+ 80374d0:	2300      	movs	r3, #0
+}
+ 80374d2:	4618      	mov	r0, r3
+ 80374d4:	3714      	adds	r7, #20
+ 80374d6:	46bd      	mov	sp, r7
+ 80374d8:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80374dc:	4770      	bx	lr
+ 80374de:	bf00      	nop
+
+080374e0 <FDCAN_CopyMessageToRAM>:
+  * @param  BufferIndex index of the buffer to be configured.
+  * @retval none
+ */
+static void FDCAN_CopyMessageToRAM(const FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader,
+                                   const uint8_t *pTxData, uint32_t BufferIndex)
+{
+ 80374e0:	b480      	push	{r7}
+ 80374e2:	b089      	sub	sp, #36	@ 0x24
+ 80374e4:	af00      	add	r7, sp, #0
+ 80374e6:	60f8      	str	r0, [r7, #12]
+ 80374e8:	60b9      	str	r1, [r7, #8]
+ 80374ea:	607a      	str	r2, [r7, #4]
+ 80374ec:	603b      	str	r3, [r7, #0]
+  uint32_t TxElementW2;
+  uint32_t *TxAddress;
+  uint32_t ByteCounter;
+
+  /* Build first word of Tx header element */
+  if (pTxHeader->IdType == FDCAN_STANDARD_ID)
+ 80374ee:	68bb      	ldr	r3, [r7, #8]
+ 80374f0:	685b      	ldr	r3, [r3, #4]
+ 80374f2:	2b00      	cmp	r3, #0
+ 80374f4:	d10a      	bne.n	803750c <FDCAN_CopyMessageToRAM+0x2c>
+  {
+    TxElementW1 = (pTxHeader->ErrorStateIndicator |
+ 80374f6:	68bb      	ldr	r3, [r7, #8]
+ 80374f8:	691a      	ldr	r2, [r3, #16]
+                   FDCAN_STANDARD_ID |
+                   pTxHeader->TxFrameType |
+ 80374fa:	68bb      	ldr	r3, [r7, #8]
+ 80374fc:	689b      	ldr	r3, [r3, #8]
+                   FDCAN_STANDARD_ID |
+ 80374fe:	431a      	orrs	r2, r3
+                   (pTxHeader->Identifier << 18U));
+ 8037500:	68bb      	ldr	r3, [r7, #8]
+ 8037502:	681b      	ldr	r3, [r3, #0]
+ 8037504:	049b      	lsls	r3, r3, #18
+    TxElementW1 = (pTxHeader->ErrorStateIndicator |
+ 8037506:	4313      	orrs	r3, r2
+ 8037508:	61fb      	str	r3, [r7, #28]
+ 803750a:	e00a      	b.n	8037522 <FDCAN_CopyMessageToRAM+0x42>
+  }
+  else /* pTxHeader->IdType == FDCAN_EXTENDED_ID */
+  {
+    TxElementW1 = (pTxHeader->ErrorStateIndicator |
+ 803750c:	68bb      	ldr	r3, [r7, #8]
+ 803750e:	691a      	ldr	r2, [r3, #16]
+                   FDCAN_EXTENDED_ID |
+                   pTxHeader->TxFrameType |
+ 8037510:	68bb      	ldr	r3, [r7, #8]
+ 8037512:	689b      	ldr	r3, [r3, #8]
+                   FDCAN_EXTENDED_ID |
+ 8037514:	431a      	orrs	r2, r3
+                   pTxHeader->Identifier);
+ 8037516:	68bb      	ldr	r3, [r7, #8]
+ 8037518:	681b      	ldr	r3, [r3, #0]
+                   pTxHeader->TxFrameType |
+ 803751a:	4313      	orrs	r3, r2
+    TxElementW1 = (pTxHeader->ErrorStateIndicator |
+ 803751c:	f043 4380 	orr.w	r3, r3, #1073741824	@ 0x40000000
+ 8037520:	61fb      	str	r3, [r7, #28]
+  }
+
+  /* Build second word of Tx header element */
+  TxElementW2 = ((pTxHeader->MessageMarker << 24U) |
+ 8037522:	68bb      	ldr	r3, [r7, #8]
+ 8037524:	6a1b      	ldr	r3, [r3, #32]
+ 8037526:	061a      	lsls	r2, r3, #24
+                 pTxHeader->TxEventFifoControl |
+ 8037528:	68bb      	ldr	r3, [r7, #8]
+ 803752a:	69db      	ldr	r3, [r3, #28]
+  TxElementW2 = ((pTxHeader->MessageMarker << 24U) |
+ 803752c:	431a      	orrs	r2, r3
+                 pTxHeader->FDFormat |
+ 803752e:	68bb      	ldr	r3, [r7, #8]
+ 8037530:	699b      	ldr	r3, [r3, #24]
+                 pTxHeader->TxEventFifoControl |
+ 8037532:	431a      	orrs	r2, r3
+                 pTxHeader->BitRateSwitch |
+ 8037534:	68bb      	ldr	r3, [r7, #8]
+ 8037536:	695b      	ldr	r3, [r3, #20]
+                 pTxHeader->FDFormat |
+ 8037538:	431a      	orrs	r2, r3
+                 (pTxHeader->DataLength << 16U));
+ 803753a:	68bb      	ldr	r3, [r7, #8]
+ 803753c:	68db      	ldr	r3, [r3, #12]
+ 803753e:	041b      	lsls	r3, r3, #16
+  TxElementW2 = ((pTxHeader->MessageMarker << 24U) |
+ 8037540:	4313      	orrs	r3, r2
+ 8037542:	613b      	str	r3, [r7, #16]
+
+  /* Calculate Tx element address */
+  TxAddress = (uint32_t *)(hfdcan->msgRam.TxBufferSA + (BufferIndex * hfdcan->Init.TxElmtSize * 4U));
+ 8037544:	68fb      	ldr	r3, [r7, #12]
+ 8037546:	f8d3 2084 	ldr.w	r2, [r3, #132]	@ 0x84
+ 803754a:	68fb      	ldr	r3, [r7, #12]
+ 803754c:	6e9b      	ldr	r3, [r3, #104]	@ 0x68
+ 803754e:	6839      	ldr	r1, [r7, #0]
+ 8037550:	fb01 f303 	mul.w	r3, r1, r3
+ 8037554:	009b      	lsls	r3, r3, #2
+ 8037556:	4413      	add	r3, r2
+ 8037558:	61bb      	str	r3, [r7, #24]
+
+  /* Write Tx element header to the message RAM */
+  *TxAddress = TxElementW1;
+ 803755a:	69bb      	ldr	r3, [r7, #24]
+ 803755c:	69fa      	ldr	r2, [r7, #28]
+ 803755e:	601a      	str	r2, [r3, #0]
+  TxAddress++;
+ 8037560:	69bb      	ldr	r3, [r7, #24]
+ 8037562:	3304      	adds	r3, #4
+ 8037564:	61bb      	str	r3, [r7, #24]
+  *TxAddress = TxElementW2;
+ 8037566:	69bb      	ldr	r3, [r7, #24]
+ 8037568:	693a      	ldr	r2, [r7, #16]
+ 803756a:	601a      	str	r2, [r3, #0]
+  TxAddress++;
+ 803756c:	69bb      	ldr	r3, [r7, #24]
+ 803756e:	3304      	adds	r3, #4
+ 8037570:	61bb      	str	r3, [r7, #24]
+
+  /* Write Tx payload to the message RAM */
+  for (ByteCounter = 0; ByteCounter < DLCtoBytes[pTxHeader->DataLength]; ByteCounter += 4U)
+ 8037572:	2300      	movs	r3, #0
+ 8037574:	617b      	str	r3, [r7, #20]
+ 8037576:	e020      	b.n	80375ba <FDCAN_CopyMessageToRAM+0xda>
+  {
+    *TxAddress = (((uint32_t)pTxData[ByteCounter + 3U] << 24U) |
+ 8037578:	697b      	ldr	r3, [r7, #20]
+ 803757a:	3303      	adds	r3, #3
+ 803757c:	687a      	ldr	r2, [r7, #4]
+ 803757e:	4413      	add	r3, r2
+ 8037580:	781b      	ldrb	r3, [r3, #0]
+ 8037582:	061a      	lsls	r2, r3, #24
+                  ((uint32_t)pTxData[ByteCounter + 2U] << 16U) |
+ 8037584:	697b      	ldr	r3, [r7, #20]
+ 8037586:	3302      	adds	r3, #2
+ 8037588:	6879      	ldr	r1, [r7, #4]
+ 803758a:	440b      	add	r3, r1
+ 803758c:	781b      	ldrb	r3, [r3, #0]
+ 803758e:	041b      	lsls	r3, r3, #16
+    *TxAddress = (((uint32_t)pTxData[ByteCounter + 3U] << 24U) |
+ 8037590:	431a      	orrs	r2, r3
+                  ((uint32_t)pTxData[ByteCounter + 1U] << 8U)  |
+ 8037592:	697b      	ldr	r3, [r7, #20]
+ 8037594:	3301      	adds	r3, #1
+ 8037596:	6879      	ldr	r1, [r7, #4]
+ 8037598:	440b      	add	r3, r1
+ 803759a:	781b      	ldrb	r3, [r3, #0]
+ 803759c:	021b      	lsls	r3, r3, #8
+                  ((uint32_t)pTxData[ByteCounter + 2U] << 16U) |
+ 803759e:	4313      	orrs	r3, r2
+                  (uint32_t)pTxData[ByteCounter]);
+ 80375a0:	6879      	ldr	r1, [r7, #4]
+ 80375a2:	697a      	ldr	r2, [r7, #20]
+ 80375a4:	440a      	add	r2, r1
+ 80375a6:	7812      	ldrb	r2, [r2, #0]
+                  ((uint32_t)pTxData[ByteCounter + 1U] << 8U)  |
+ 80375a8:	431a      	orrs	r2, r3
+    *TxAddress = (((uint32_t)pTxData[ByteCounter + 3U] << 24U) |
+ 80375aa:	69bb      	ldr	r3, [r7, #24]
+ 80375ac:	601a      	str	r2, [r3, #0]
+    TxAddress++;
+ 80375ae:	69bb      	ldr	r3, [r7, #24]
+ 80375b0:	3304      	adds	r3, #4
+ 80375b2:	61bb      	str	r3, [r7, #24]
+  for (ByteCounter = 0; ByteCounter < DLCtoBytes[pTxHeader->DataLength]; ByteCounter += 4U)
+ 80375b4:	697b      	ldr	r3, [r7, #20]
+ 80375b6:	3304      	adds	r3, #4
+ 80375b8:	617b      	str	r3, [r7, #20]
+ 80375ba:	68bb      	ldr	r3, [r7, #8]
+ 80375bc:	68db      	ldr	r3, [r3, #12]
+ 80375be:	4a06      	ldr	r2, [pc, #24]	@ (80375d8 <FDCAN_CopyMessageToRAM+0xf8>)
+ 80375c0:	5cd3      	ldrb	r3, [r2, r3]
+ 80375c2:	461a      	mov	r2, r3
+ 80375c4:	697b      	ldr	r3, [r7, #20]
+ 80375c6:	4293      	cmp	r3, r2
+ 80375c8:	d3d6      	bcc.n	8037578 <FDCAN_CopyMessageToRAM+0x98>
+  }
+}
+ 80375ca:	bf00      	nop
+ 80375cc:	bf00      	nop
+ 80375ce:	3724      	adds	r7, #36	@ 0x24
+ 80375d0:	46bd      	mov	sp, r7
+ 80375d2:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80375d6:	4770      	bx	lr
+ 80375d8:	08041c70 	.word	0x08041c70
+
+080375dc <HAL_GPIO_Init>:
+  * @param  GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
+  *         the configuration information for the specified GPIO peripheral.
+  * @retval None
+  */
+void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
+{
+ 80375dc:	b480      	push	{r7}
+ 80375de:	b089      	sub	sp, #36	@ 0x24
+ 80375e0:	af00      	add	r7, sp, #0
+ 80375e2:	6078      	str	r0, [r7, #4]
+ 80375e4:	6039      	str	r1, [r7, #0]
+  uint32_t position = 0x00U;
+ 80375e6:	2300      	movs	r3, #0
+ 80375e8:	61fb      	str	r3, [r7, #28]
+  EXTI_Core_TypeDef *EXTI_CurrentCPU;
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+  EXTI_CurrentCPU = EXTI_D2; /* EXTI for CM4 CPU */
+#else
+  EXTI_CurrentCPU = EXTI_D1; /* EXTI for CM7 CPU */
+ 80375ea:	4b89      	ldr	r3, [pc, #548]	@ (8037810 <HAL_GPIO_Init+0x234>)
+ 80375ec:	617b      	str	r3, [r7, #20]
+  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
+  assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
+
+  /* Configure the port pins */
+  while (((GPIO_Init->Pin) >> position) != 0x00U)
+ 80375ee:	e194      	b.n	803791a <HAL_GPIO_Init+0x33e>
+  {
+    /* Get current io position */
+    iocurrent = (GPIO_Init->Pin) & (1UL << position);
+ 80375f0:	683b      	ldr	r3, [r7, #0]
+ 80375f2:	681a      	ldr	r2, [r3, #0]
+ 80375f4:	2101      	movs	r1, #1
+ 80375f6:	69fb      	ldr	r3, [r7, #28]
+ 80375f8:	fa01 f303 	lsl.w	r3, r1, r3
+ 80375fc:	4013      	ands	r3, r2
+ 80375fe:	613b      	str	r3, [r7, #16]
+
+    if (iocurrent != 0x00U)
+ 8037600:	693b      	ldr	r3, [r7, #16]
+ 8037602:	2b00      	cmp	r3, #0
+ 8037604:	f000 8186 	beq.w	8037914 <HAL_GPIO_Init+0x338>
+    {
+      /*--------------------- GPIO Mode Configuration ------------------------*/
+      /* In case of Output or Alternate function mode selection */
+      if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
+ 8037608:	683b      	ldr	r3, [r7, #0]
+ 803760a:	685b      	ldr	r3, [r3, #4]
+ 803760c:	f003 0303 	and.w	r3, r3, #3
+ 8037610:	2b01      	cmp	r3, #1
+ 8037612:	d005      	beq.n	8037620 <HAL_GPIO_Init+0x44>
+ 8037614:	683b      	ldr	r3, [r7, #0]
+ 8037616:	685b      	ldr	r3, [r3, #4]
+ 8037618:	f003 0303 	and.w	r3, r3, #3
+ 803761c:	2b02      	cmp	r3, #2
+ 803761e:	d130      	bne.n	8037682 <HAL_GPIO_Init+0xa6>
+      {
+        /* Check the Speed parameter */
+        assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
+
+        /* Configure the IO Speed */
+        temp = GPIOx->OSPEEDR;
+ 8037620:	687b      	ldr	r3, [r7, #4]
+ 8037622:	689b      	ldr	r3, [r3, #8]
+ 8037624:	61bb      	str	r3, [r7, #24]
+        temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
+ 8037626:	69fb      	ldr	r3, [r7, #28]
+ 8037628:	005b      	lsls	r3, r3, #1
+ 803762a:	2203      	movs	r2, #3
+ 803762c:	fa02 f303 	lsl.w	r3, r2, r3
+ 8037630:	43db      	mvns	r3, r3
+ 8037632:	69ba      	ldr	r2, [r7, #24]
+ 8037634:	4013      	ands	r3, r2
+ 8037636:	61bb      	str	r3, [r7, #24]
+        temp |= (GPIO_Init->Speed << (position * 2U));
+ 8037638:	683b      	ldr	r3, [r7, #0]
+ 803763a:	68da      	ldr	r2, [r3, #12]
+ 803763c:	69fb      	ldr	r3, [r7, #28]
+ 803763e:	005b      	lsls	r3, r3, #1
+ 8037640:	fa02 f303 	lsl.w	r3, r2, r3
+ 8037644:	69ba      	ldr	r2, [r7, #24]
+ 8037646:	4313      	orrs	r3, r2
+ 8037648:	61bb      	str	r3, [r7, #24]
+        GPIOx->OSPEEDR = temp;
+ 803764a:	687b      	ldr	r3, [r7, #4]
+ 803764c:	69ba      	ldr	r2, [r7, #24]
+ 803764e:	609a      	str	r2, [r3, #8]
+
+        /* Configure the IO Output Type */
+        temp = GPIOx->OTYPER;
+ 8037650:	687b      	ldr	r3, [r7, #4]
+ 8037652:	685b      	ldr	r3, [r3, #4]
+ 8037654:	61bb      	str	r3, [r7, #24]
+        temp &= ~(GPIO_OTYPER_OT0 << position) ;
+ 8037656:	2201      	movs	r2, #1
+ 8037658:	69fb      	ldr	r3, [r7, #28]
+ 803765a:	fa02 f303 	lsl.w	r3, r2, r3
+ 803765e:	43db      	mvns	r3, r3
+ 8037660:	69ba      	ldr	r2, [r7, #24]
+ 8037662:	4013      	ands	r3, r2
+ 8037664:	61bb      	str	r3, [r7, #24]
+        temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
+ 8037666:	683b      	ldr	r3, [r7, #0]
+ 8037668:	685b      	ldr	r3, [r3, #4]
+ 803766a:	091b      	lsrs	r3, r3, #4
+ 803766c:	f003 0201 	and.w	r2, r3, #1
+ 8037670:	69fb      	ldr	r3, [r7, #28]
+ 8037672:	fa02 f303 	lsl.w	r3, r2, r3
+ 8037676:	69ba      	ldr	r2, [r7, #24]
+ 8037678:	4313      	orrs	r3, r2
+ 803767a:	61bb      	str	r3, [r7, #24]
+        GPIOx->OTYPER = temp;
+ 803767c:	687b      	ldr	r3, [r7, #4]
+ 803767e:	69ba      	ldr	r2, [r7, #24]
+ 8037680:	605a      	str	r2, [r3, #4]
+      }
+
+      if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
+ 8037682:	683b      	ldr	r3, [r7, #0]
+ 8037684:	685b      	ldr	r3, [r3, #4]
+ 8037686:	f003 0303 	and.w	r3, r3, #3
+ 803768a:	2b03      	cmp	r3, #3
+ 803768c:	d017      	beq.n	80376be <HAL_GPIO_Init+0xe2>
+      {
+       /* Check the Pull parameter */
+       assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
+
+      /* Activate the Pull-up or Pull down resistor for the current IO */
+      temp = GPIOx->PUPDR;
+ 803768e:	687b      	ldr	r3, [r7, #4]
+ 8037690:	68db      	ldr	r3, [r3, #12]
+ 8037692:	61bb      	str	r3, [r7, #24]
+      temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
+ 8037694:	69fb      	ldr	r3, [r7, #28]
+ 8037696:	005b      	lsls	r3, r3, #1
+ 8037698:	2203      	movs	r2, #3
+ 803769a:	fa02 f303 	lsl.w	r3, r2, r3
+ 803769e:	43db      	mvns	r3, r3
+ 80376a0:	69ba      	ldr	r2, [r7, #24]
+ 80376a2:	4013      	ands	r3, r2
+ 80376a4:	61bb      	str	r3, [r7, #24]
+      temp |= ((GPIO_Init->Pull) << (position * 2U));
+ 80376a6:	683b      	ldr	r3, [r7, #0]
+ 80376a8:	689a      	ldr	r2, [r3, #8]
+ 80376aa:	69fb      	ldr	r3, [r7, #28]
+ 80376ac:	005b      	lsls	r3, r3, #1
+ 80376ae:	fa02 f303 	lsl.w	r3, r2, r3
+ 80376b2:	69ba      	ldr	r2, [r7, #24]
+ 80376b4:	4313      	orrs	r3, r2
+ 80376b6:	61bb      	str	r3, [r7, #24]
+      GPIOx->PUPDR = temp;
+ 80376b8:	687b      	ldr	r3, [r7, #4]
+ 80376ba:	69ba      	ldr	r2, [r7, #24]
+ 80376bc:	60da      	str	r2, [r3, #12]
+      }
+
+      /* In case of Alternate function mode selection */
+      if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
+ 80376be:	683b      	ldr	r3, [r7, #0]
+ 80376c0:	685b      	ldr	r3, [r3, #4]
+ 80376c2:	f003 0303 	and.w	r3, r3, #3
+ 80376c6:	2b02      	cmp	r3, #2
+ 80376c8:	d123      	bne.n	8037712 <HAL_GPIO_Init+0x136>
+        /* Check the Alternate function parameters */
+        assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
+        assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
+
+        /* Configure Alternate function mapped with the current IO */
+        temp = GPIOx->AFR[position >> 3U];
+ 80376ca:	69fb      	ldr	r3, [r7, #28]
+ 80376cc:	08da      	lsrs	r2, r3, #3
+ 80376ce:	687b      	ldr	r3, [r7, #4]
+ 80376d0:	3208      	adds	r2, #8
+ 80376d2:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
+ 80376d6:	61bb      	str	r3, [r7, #24]
+        temp &= ~(0xFU << ((position & 0x07U) * 4U));
+ 80376d8:	69fb      	ldr	r3, [r7, #28]
+ 80376da:	f003 0307 	and.w	r3, r3, #7
+ 80376de:	009b      	lsls	r3, r3, #2
+ 80376e0:	220f      	movs	r2, #15
+ 80376e2:	fa02 f303 	lsl.w	r3, r2, r3
+ 80376e6:	43db      	mvns	r3, r3
+ 80376e8:	69ba      	ldr	r2, [r7, #24]
+ 80376ea:	4013      	ands	r3, r2
+ 80376ec:	61bb      	str	r3, [r7, #24]
+        temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
+ 80376ee:	683b      	ldr	r3, [r7, #0]
+ 80376f0:	691a      	ldr	r2, [r3, #16]
+ 80376f2:	69fb      	ldr	r3, [r7, #28]
+ 80376f4:	f003 0307 	and.w	r3, r3, #7
+ 80376f8:	009b      	lsls	r3, r3, #2
+ 80376fa:	fa02 f303 	lsl.w	r3, r2, r3
+ 80376fe:	69ba      	ldr	r2, [r7, #24]
+ 8037700:	4313      	orrs	r3, r2
+ 8037702:	61bb      	str	r3, [r7, #24]
+        GPIOx->AFR[position >> 3U] = temp;
+ 8037704:	69fb      	ldr	r3, [r7, #28]
+ 8037706:	08da      	lsrs	r2, r3, #3
+ 8037708:	687b      	ldr	r3, [r7, #4]
+ 803770a:	3208      	adds	r2, #8
+ 803770c:	69b9      	ldr	r1, [r7, #24]
+ 803770e:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
+      }
+
+      /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
+      temp = GPIOx->MODER;
+ 8037712:	687b      	ldr	r3, [r7, #4]
+ 8037714:	681b      	ldr	r3, [r3, #0]
+ 8037716:	61bb      	str	r3, [r7, #24]
+      temp &= ~(GPIO_MODER_MODE0 << (position * 2U));
+ 8037718:	69fb      	ldr	r3, [r7, #28]
+ 803771a:	005b      	lsls	r3, r3, #1
+ 803771c:	2203      	movs	r2, #3
+ 803771e:	fa02 f303 	lsl.w	r3, r2, r3
+ 8037722:	43db      	mvns	r3, r3
+ 8037724:	69ba      	ldr	r2, [r7, #24]
+ 8037726:	4013      	ands	r3, r2
+ 8037728:	61bb      	str	r3, [r7, #24]
+      temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
+ 803772a:	683b      	ldr	r3, [r7, #0]
+ 803772c:	685b      	ldr	r3, [r3, #4]
+ 803772e:	f003 0203 	and.w	r2, r3, #3
+ 8037732:	69fb      	ldr	r3, [r7, #28]
+ 8037734:	005b      	lsls	r3, r3, #1
+ 8037736:	fa02 f303 	lsl.w	r3, r2, r3
+ 803773a:	69ba      	ldr	r2, [r7, #24]
+ 803773c:	4313      	orrs	r3, r2
+ 803773e:	61bb      	str	r3, [r7, #24]
+      GPIOx->MODER = temp;
+ 8037740:	687b      	ldr	r3, [r7, #4]
+ 8037742:	69ba      	ldr	r2, [r7, #24]
+ 8037744:	601a      	str	r2, [r3, #0]
+
+      /*--------------------- EXTI Mode Configuration ------------------------*/
+      /* Configure the External Interrupt or event for the current IO */
+      if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
+ 8037746:	683b      	ldr	r3, [r7, #0]
+ 8037748:	685b      	ldr	r3, [r3, #4]
+ 803774a:	f403 3340 	and.w	r3, r3, #196608	@ 0x30000
+ 803774e:	2b00      	cmp	r3, #0
+ 8037750:	f000 80e0 	beq.w	8037914 <HAL_GPIO_Init+0x338>
+      {
+        /* Enable SYSCFG Clock */
+        __HAL_RCC_SYSCFG_CLK_ENABLE();
+ 8037754:	4b2f      	ldr	r3, [pc, #188]	@ (8037814 <HAL_GPIO_Init+0x238>)
+ 8037756:	f8d3 30f4 	ldr.w	r3, [r3, #244]	@ 0xf4
+ 803775a:	4a2e      	ldr	r2, [pc, #184]	@ (8037814 <HAL_GPIO_Init+0x238>)
+ 803775c:	f043 0302 	orr.w	r3, r3, #2
+ 8037760:	f8c2 30f4 	str.w	r3, [r2, #244]	@ 0xf4
+ 8037764:	4b2b      	ldr	r3, [pc, #172]	@ (8037814 <HAL_GPIO_Init+0x238>)
+ 8037766:	f8d3 30f4 	ldr.w	r3, [r3, #244]	@ 0xf4
+ 803776a:	f003 0302 	and.w	r3, r3, #2
+ 803776e:	60fb      	str	r3, [r7, #12]
+ 8037770:	68fb      	ldr	r3, [r7, #12]
+
+        temp = SYSCFG->EXTICR[position >> 2U];
+ 8037772:	4a29      	ldr	r2, [pc, #164]	@ (8037818 <HAL_GPIO_Init+0x23c>)
+ 8037774:	69fb      	ldr	r3, [r7, #28]
+ 8037776:	089b      	lsrs	r3, r3, #2
+ 8037778:	3302      	adds	r3, #2
+ 803777a:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
+ 803777e:	61bb      	str	r3, [r7, #24]
+        temp &= ~(0x0FUL << (4U * (position & 0x03U)));
+ 8037780:	69fb      	ldr	r3, [r7, #28]
+ 8037782:	f003 0303 	and.w	r3, r3, #3
+ 8037786:	009b      	lsls	r3, r3, #2
+ 8037788:	220f      	movs	r2, #15
+ 803778a:	fa02 f303 	lsl.w	r3, r2, r3
+ 803778e:	43db      	mvns	r3, r3
+ 8037790:	69ba      	ldr	r2, [r7, #24]
+ 8037792:	4013      	ands	r3, r2
+ 8037794:	61bb      	str	r3, [r7, #24]
+        temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
+ 8037796:	687b      	ldr	r3, [r7, #4]
+ 8037798:	4a20      	ldr	r2, [pc, #128]	@ (803781c <HAL_GPIO_Init+0x240>)
+ 803779a:	4293      	cmp	r3, r2
+ 803779c:	d052      	beq.n	8037844 <HAL_GPIO_Init+0x268>
+ 803779e:	687b      	ldr	r3, [r7, #4]
+ 80377a0:	4a1f      	ldr	r2, [pc, #124]	@ (8037820 <HAL_GPIO_Init+0x244>)
+ 80377a2:	4293      	cmp	r3, r2
+ 80377a4:	d031      	beq.n	803780a <HAL_GPIO_Init+0x22e>
+ 80377a6:	687b      	ldr	r3, [r7, #4]
+ 80377a8:	4a1e      	ldr	r2, [pc, #120]	@ (8037824 <HAL_GPIO_Init+0x248>)
+ 80377aa:	4293      	cmp	r3, r2
+ 80377ac:	d02b      	beq.n	8037806 <HAL_GPIO_Init+0x22a>
+ 80377ae:	687b      	ldr	r3, [r7, #4]
+ 80377b0:	4a1d      	ldr	r2, [pc, #116]	@ (8037828 <HAL_GPIO_Init+0x24c>)
+ 80377b2:	4293      	cmp	r3, r2
+ 80377b4:	d025      	beq.n	8037802 <HAL_GPIO_Init+0x226>
+ 80377b6:	687b      	ldr	r3, [r7, #4]
+ 80377b8:	4a1c      	ldr	r2, [pc, #112]	@ (803782c <HAL_GPIO_Init+0x250>)
+ 80377ba:	4293      	cmp	r3, r2
+ 80377bc:	d01f      	beq.n	80377fe <HAL_GPIO_Init+0x222>
+ 80377be:	687b      	ldr	r3, [r7, #4]
+ 80377c0:	4a1b      	ldr	r2, [pc, #108]	@ (8037830 <HAL_GPIO_Init+0x254>)
+ 80377c2:	4293      	cmp	r3, r2
+ 80377c4:	d019      	beq.n	80377fa <HAL_GPIO_Init+0x21e>
+ 80377c6:	687b      	ldr	r3, [r7, #4]
+ 80377c8:	4a1a      	ldr	r2, [pc, #104]	@ (8037834 <HAL_GPIO_Init+0x258>)
+ 80377ca:	4293      	cmp	r3, r2
+ 80377cc:	d013      	beq.n	80377f6 <HAL_GPIO_Init+0x21a>
+ 80377ce:	687b      	ldr	r3, [r7, #4]
+ 80377d0:	4a19      	ldr	r2, [pc, #100]	@ (8037838 <HAL_GPIO_Init+0x25c>)
+ 80377d2:	4293      	cmp	r3, r2
+ 80377d4:	d00d      	beq.n	80377f2 <HAL_GPIO_Init+0x216>
+ 80377d6:	687b      	ldr	r3, [r7, #4]
+ 80377d8:	4a18      	ldr	r2, [pc, #96]	@ (803783c <HAL_GPIO_Init+0x260>)
+ 80377da:	4293      	cmp	r3, r2
+ 80377dc:	d007      	beq.n	80377ee <HAL_GPIO_Init+0x212>
+ 80377de:	687b      	ldr	r3, [r7, #4]
+ 80377e0:	4a17      	ldr	r2, [pc, #92]	@ (8037840 <HAL_GPIO_Init+0x264>)
+ 80377e2:	4293      	cmp	r3, r2
+ 80377e4:	d101      	bne.n	80377ea <HAL_GPIO_Init+0x20e>
+ 80377e6:	2309      	movs	r3, #9
+ 80377e8:	e02d      	b.n	8037846 <HAL_GPIO_Init+0x26a>
+ 80377ea:	230a      	movs	r3, #10
+ 80377ec:	e02b      	b.n	8037846 <HAL_GPIO_Init+0x26a>
+ 80377ee:	2308      	movs	r3, #8
+ 80377f0:	e029      	b.n	8037846 <HAL_GPIO_Init+0x26a>
+ 80377f2:	2307      	movs	r3, #7
+ 80377f4:	e027      	b.n	8037846 <HAL_GPIO_Init+0x26a>
+ 80377f6:	2306      	movs	r3, #6
+ 80377f8:	e025      	b.n	8037846 <HAL_GPIO_Init+0x26a>
+ 80377fa:	2305      	movs	r3, #5
+ 80377fc:	e023      	b.n	8037846 <HAL_GPIO_Init+0x26a>
+ 80377fe:	2304      	movs	r3, #4
+ 8037800:	e021      	b.n	8037846 <HAL_GPIO_Init+0x26a>
+ 8037802:	2303      	movs	r3, #3
+ 8037804:	e01f      	b.n	8037846 <HAL_GPIO_Init+0x26a>
+ 8037806:	2302      	movs	r3, #2
+ 8037808:	e01d      	b.n	8037846 <HAL_GPIO_Init+0x26a>
+ 803780a:	2301      	movs	r3, #1
+ 803780c:	e01b      	b.n	8037846 <HAL_GPIO_Init+0x26a>
+ 803780e:	bf00      	nop
+ 8037810:	58000080 	.word	0x58000080
+ 8037814:	58024400 	.word	0x58024400
+ 8037818:	58000400 	.word	0x58000400
+ 803781c:	58020000 	.word	0x58020000
+ 8037820:	58020400 	.word	0x58020400
+ 8037824:	58020800 	.word	0x58020800
+ 8037828:	58020c00 	.word	0x58020c00
+ 803782c:	58021000 	.word	0x58021000
+ 8037830:	58021400 	.word	0x58021400
+ 8037834:	58021800 	.word	0x58021800
+ 8037838:	58021c00 	.word	0x58021c00
+ 803783c:	58022000 	.word	0x58022000
+ 8037840:	58022400 	.word	0x58022400
+ 8037844:	2300      	movs	r3, #0
+ 8037846:	69fa      	ldr	r2, [r7, #28]
+ 8037848:	f002 0203 	and.w	r2, r2, #3
+ 803784c:	0092      	lsls	r2, r2, #2
+ 803784e:	4093      	lsls	r3, r2
+ 8037850:	69ba      	ldr	r2, [r7, #24]
+ 8037852:	4313      	orrs	r3, r2
+ 8037854:	61bb      	str	r3, [r7, #24]
+        SYSCFG->EXTICR[position >> 2U] = temp;
+ 8037856:	4938      	ldr	r1, [pc, #224]	@ (8037938 <HAL_GPIO_Init+0x35c>)
+ 8037858:	69fb      	ldr	r3, [r7, #28]
+ 803785a:	089b      	lsrs	r3, r3, #2
+ 803785c:	3302      	adds	r3, #2
+ 803785e:	69ba      	ldr	r2, [r7, #24]
+ 8037860:	f841 2023 	str.w	r2, [r1, r3, lsl #2]
+
+        /* Clear Rising Falling edge configuration */
+        temp = EXTI->RTSR1;
+ 8037864:	f04f 43b0 	mov.w	r3, #1476395008	@ 0x58000000
+ 8037868:	681b      	ldr	r3, [r3, #0]
+ 803786a:	61bb      	str	r3, [r7, #24]
+        temp &= ~(iocurrent);
+ 803786c:	693b      	ldr	r3, [r7, #16]
+ 803786e:	43db      	mvns	r3, r3
+ 8037870:	69ba      	ldr	r2, [r7, #24]
+ 8037872:	4013      	ands	r3, r2
+ 8037874:	61bb      	str	r3, [r7, #24]
+        if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
+ 8037876:	683b      	ldr	r3, [r7, #0]
+ 8037878:	685b      	ldr	r3, [r3, #4]
+ 803787a:	f403 1380 	and.w	r3, r3, #1048576	@ 0x100000
+ 803787e:	2b00      	cmp	r3, #0
+ 8037880:	d003      	beq.n	803788a <HAL_GPIO_Init+0x2ae>
+        {
+          temp |= iocurrent;
+ 8037882:	69ba      	ldr	r2, [r7, #24]
+ 8037884:	693b      	ldr	r3, [r7, #16]
+ 8037886:	4313      	orrs	r3, r2
+ 8037888:	61bb      	str	r3, [r7, #24]
+        }
+        EXTI->RTSR1 = temp;
+ 803788a:	f04f 42b0 	mov.w	r2, #1476395008	@ 0x58000000
+ 803788e:	69bb      	ldr	r3, [r7, #24]
+ 8037890:	6013      	str	r3, [r2, #0]
+
+        temp = EXTI->FTSR1;
+ 8037892:	f04f 43b0 	mov.w	r3, #1476395008	@ 0x58000000
+ 8037896:	685b      	ldr	r3, [r3, #4]
+ 8037898:	61bb      	str	r3, [r7, #24]
+        temp &= ~(iocurrent);
+ 803789a:	693b      	ldr	r3, [r7, #16]
+ 803789c:	43db      	mvns	r3, r3
+ 803789e:	69ba      	ldr	r2, [r7, #24]
+ 80378a0:	4013      	ands	r3, r2
+ 80378a2:	61bb      	str	r3, [r7, #24]
+        if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
+ 80378a4:	683b      	ldr	r3, [r7, #0]
+ 80378a6:	685b      	ldr	r3, [r3, #4]
+ 80378a8:	f403 1300 	and.w	r3, r3, #2097152	@ 0x200000
+ 80378ac:	2b00      	cmp	r3, #0
+ 80378ae:	d003      	beq.n	80378b8 <HAL_GPIO_Init+0x2dc>
+        {
+          temp |= iocurrent;
+ 80378b0:	69ba      	ldr	r2, [r7, #24]
+ 80378b2:	693b      	ldr	r3, [r7, #16]
+ 80378b4:	4313      	orrs	r3, r2
+ 80378b6:	61bb      	str	r3, [r7, #24]
+        }
+        EXTI->FTSR1 = temp;
+ 80378b8:	f04f 42b0 	mov.w	r2, #1476395008	@ 0x58000000
+ 80378bc:	69bb      	ldr	r3, [r7, #24]
+ 80378be:	6053      	str	r3, [r2, #4]
+
+        temp = EXTI_CurrentCPU->EMR1;
+ 80378c0:	697b      	ldr	r3, [r7, #20]
+ 80378c2:	685b      	ldr	r3, [r3, #4]
+ 80378c4:	61bb      	str	r3, [r7, #24]
+        temp &= ~(iocurrent);
+ 80378c6:	693b      	ldr	r3, [r7, #16]
+ 80378c8:	43db      	mvns	r3, r3
+ 80378ca:	69ba      	ldr	r2, [r7, #24]
+ 80378cc:	4013      	ands	r3, r2
+ 80378ce:	61bb      	str	r3, [r7, #24]
+        if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
+ 80378d0:	683b      	ldr	r3, [r7, #0]
+ 80378d2:	685b      	ldr	r3, [r3, #4]
+ 80378d4:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
+ 80378d8:	2b00      	cmp	r3, #0
+ 80378da:	d003      	beq.n	80378e4 <HAL_GPIO_Init+0x308>
+        {
+          temp |= iocurrent;
+ 80378dc:	69ba      	ldr	r2, [r7, #24]
+ 80378de:	693b      	ldr	r3, [r7, #16]
+ 80378e0:	4313      	orrs	r3, r2
+ 80378e2:	61bb      	str	r3, [r7, #24]
+        }
+        EXTI_CurrentCPU->EMR1 = temp;
+ 80378e4:	697b      	ldr	r3, [r7, #20]
+ 80378e6:	69ba      	ldr	r2, [r7, #24]
+ 80378e8:	605a      	str	r2, [r3, #4]
+
+        /* Clear EXTI line configuration */
+        temp = EXTI_CurrentCPU->IMR1;
+ 80378ea:	697b      	ldr	r3, [r7, #20]
+ 80378ec:	681b      	ldr	r3, [r3, #0]
+ 80378ee:	61bb      	str	r3, [r7, #24]
+        temp &= ~(iocurrent);
+ 80378f0:	693b      	ldr	r3, [r7, #16]
+ 80378f2:	43db      	mvns	r3, r3
+ 80378f4:	69ba      	ldr	r2, [r7, #24]
+ 80378f6:	4013      	ands	r3, r2
+ 80378f8:	61bb      	str	r3, [r7, #24]
+        if ((GPIO_Init->Mode & EXTI_IT) != 0x00U)
+ 80378fa:	683b      	ldr	r3, [r7, #0]
+ 80378fc:	685b      	ldr	r3, [r3, #4]
+ 80378fe:	f403 3380 	and.w	r3, r3, #65536	@ 0x10000
+ 8037902:	2b00      	cmp	r3, #0
+ 8037904:	d003      	beq.n	803790e <HAL_GPIO_Init+0x332>
+        {
+          temp |= iocurrent;
+ 8037906:	69ba      	ldr	r2, [r7, #24]
+ 8037908:	693b      	ldr	r3, [r7, #16]
+ 803790a:	4313      	orrs	r3, r2
+ 803790c:	61bb      	str	r3, [r7, #24]
+        }
+        EXTI_CurrentCPU->IMR1 = temp;
+ 803790e:	697b      	ldr	r3, [r7, #20]
+ 8037910:	69ba      	ldr	r2, [r7, #24]
+ 8037912:	601a      	str	r2, [r3, #0]
+      }
+    }
+
+    position++;
+ 8037914:	69fb      	ldr	r3, [r7, #28]
+ 8037916:	3301      	adds	r3, #1
+ 8037918:	61fb      	str	r3, [r7, #28]
+  while (((GPIO_Init->Pin) >> position) != 0x00U)
+ 803791a:	683b      	ldr	r3, [r7, #0]
+ 803791c:	681a      	ldr	r2, [r3, #0]
+ 803791e:	69fb      	ldr	r3, [r7, #28]
+ 8037920:	fa22 f303 	lsr.w	r3, r2, r3
+ 8037924:	2b00      	cmp	r3, #0
+ 8037926:	f47f ae63 	bne.w	80375f0 <HAL_GPIO_Init+0x14>
+  }
+}
+ 803792a:	bf00      	nop
+ 803792c:	bf00      	nop
+ 803792e:	3724      	adds	r7, #36	@ 0x24
+ 8037930:	46bd      	mov	sp, r7
+ 8037932:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8037936:	4770      	bx	lr
+ 8037938:	58000400 	.word	0x58000400
+
+0803793c <HAL_GPIO_WritePin>:
+  *            @arg GPIO_PIN_RESET: to clear the port pin
+  *            @arg GPIO_PIN_SET: to set the port pin
+  * @retval None
+  */
+void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
+{
+ 803793c:	b480      	push	{r7}
+ 803793e:	b083      	sub	sp, #12
+ 8037940:	af00      	add	r7, sp, #0
+ 8037942:	6078      	str	r0, [r7, #4]
+ 8037944:	460b      	mov	r3, r1
+ 8037946:	807b      	strh	r3, [r7, #2]
+ 8037948:	4613      	mov	r3, r2
+ 803794a:	707b      	strb	r3, [r7, #1]
+  /* Check the parameters */
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+  assert_param(IS_GPIO_PIN_ACTION(PinState));
+
+  if (PinState != GPIO_PIN_RESET)
+ 803794c:	787b      	ldrb	r3, [r7, #1]
+ 803794e:	2b00      	cmp	r3, #0
+ 8037950:	d003      	beq.n	803795a <HAL_GPIO_WritePin+0x1e>
+  {
+    GPIOx->BSRR = GPIO_Pin;
+ 8037952:	887a      	ldrh	r2, [r7, #2]
+ 8037954:	687b      	ldr	r3, [r7, #4]
+ 8037956:	619a      	str	r2, [r3, #24]
+  }
+  else
+  {
+    GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER;
+  }
+}
+ 8037958:	e003      	b.n	8037962 <HAL_GPIO_WritePin+0x26>
+    GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER;
+ 803795a:	887b      	ldrh	r3, [r7, #2]
+ 803795c:	041a      	lsls	r2, r3, #16
+ 803795e:	687b      	ldr	r3, [r7, #4]
+ 8037960:	619a      	str	r2, [r3, #24]
+}
+ 8037962:	bf00      	nop
+ 8037964:	370c      	adds	r7, #12
+ 8037966:	46bd      	mov	sp, r7
+ 8037968:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 803796c:	4770      	bx	lr
+	...
+
+08037970 <HAL_I2C_Init>:
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
+{
+ 8037970:	b580      	push	{r7, lr}
+ 8037972:	b082      	sub	sp, #8
+ 8037974:	af00      	add	r7, sp, #0
+ 8037976:	6078      	str	r0, [r7, #4]
+  /* Check the I2C handle allocation */
+  if (hi2c == NULL)
+ 8037978:	687b      	ldr	r3, [r7, #4]
+ 803797a:	2b00      	cmp	r3, #0
+ 803797c:	d101      	bne.n	8037982 <HAL_I2C_Init+0x12>
+  {
+    return HAL_ERROR;
+ 803797e:	2301      	movs	r3, #1
+ 8037980:	e08b      	b.n	8037a9a <HAL_I2C_Init+0x12a>
+  assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
+  assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
+  assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
+  assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
+
+  if (hi2c->State == HAL_I2C_STATE_RESET)
+ 8037982:	687b      	ldr	r3, [r7, #4]
+ 8037984:	f893 3041 	ldrb.w	r3, [r3, #65]	@ 0x41
+ 8037988:	b2db      	uxtb	r3, r3
+ 803798a:	2b00      	cmp	r3, #0
+ 803798c:	d106      	bne.n	803799c <HAL_I2C_Init+0x2c>
+  {
+    /* Allocate lock resource and initialize it */
+    hi2c->Lock = HAL_UNLOCKED;
+ 803798e:	687b      	ldr	r3, [r7, #4]
+ 8037990:	2200      	movs	r2, #0
+ 8037992:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40
+
+    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+    hi2c->MspInitCallback(hi2c);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+    HAL_I2C_MspInit(hi2c);
+ 8037996:	6878      	ldr	r0, [r7, #4]
+ 8037998:	f7f7 fd68 	bl	802f46c <HAL_I2C_MspInit>
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+
+  hi2c->State = HAL_I2C_STATE_BUSY;
+ 803799c:	687b      	ldr	r3, [r7, #4]
+ 803799e:	2224      	movs	r2, #36	@ 0x24
+ 80379a0:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
+
+  /* Disable the selected I2C peripheral */
+  __HAL_I2C_DISABLE(hi2c);
+ 80379a4:	687b      	ldr	r3, [r7, #4]
+ 80379a6:	681b      	ldr	r3, [r3, #0]
+ 80379a8:	681a      	ldr	r2, [r3, #0]
+ 80379aa:	687b      	ldr	r3, [r7, #4]
+ 80379ac:	681b      	ldr	r3, [r3, #0]
+ 80379ae:	f022 0201 	bic.w	r2, r2, #1
+ 80379b2:	601a      	str	r2, [r3, #0]
+
+  /*---------------------------- I2Cx TIMINGR Configuration ------------------*/
+  /* Configure I2Cx: Frequency range */
+  hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
+ 80379b4:	687b      	ldr	r3, [r7, #4]
+ 80379b6:	685a      	ldr	r2, [r3, #4]
+ 80379b8:	687b      	ldr	r3, [r7, #4]
+ 80379ba:	681b      	ldr	r3, [r3, #0]
+ 80379bc:	f022 6270 	bic.w	r2, r2, #251658240	@ 0xf000000
+ 80379c0:	611a      	str	r2, [r3, #16]
+
+  /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
+  /* Disable Own Address1 before set the Own Address1 configuration */
+  hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
+ 80379c2:	687b      	ldr	r3, [r7, #4]
+ 80379c4:	681b      	ldr	r3, [r3, #0]
+ 80379c6:	689a      	ldr	r2, [r3, #8]
+ 80379c8:	687b      	ldr	r3, [r7, #4]
+ 80379ca:	681b      	ldr	r3, [r3, #0]
+ 80379cc:	f422 4200 	bic.w	r2, r2, #32768	@ 0x8000
+ 80379d0:	609a      	str	r2, [r3, #8]
+
+  /* Configure I2Cx: Own Address1 and ack own address1 mode */
+  if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
+ 80379d2:	687b      	ldr	r3, [r7, #4]
+ 80379d4:	68db      	ldr	r3, [r3, #12]
+ 80379d6:	2b01      	cmp	r3, #1
+ 80379d8:	d107      	bne.n	80379ea <HAL_I2C_Init+0x7a>
+  {
+    hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
+ 80379da:	687b      	ldr	r3, [r7, #4]
+ 80379dc:	689a      	ldr	r2, [r3, #8]
+ 80379de:	687b      	ldr	r3, [r7, #4]
+ 80379e0:	681b      	ldr	r3, [r3, #0]
+ 80379e2:	f442 4200 	orr.w	r2, r2, #32768	@ 0x8000
+ 80379e6:	609a      	str	r2, [r3, #8]
+ 80379e8:	e006      	b.n	80379f8 <HAL_I2C_Init+0x88>
+  }
+  else /* I2C_ADDRESSINGMODE_10BIT */
+  {
+    hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
+ 80379ea:	687b      	ldr	r3, [r7, #4]
+ 80379ec:	689a      	ldr	r2, [r3, #8]
+ 80379ee:	687b      	ldr	r3, [r7, #4]
+ 80379f0:	681b      	ldr	r3, [r3, #0]
+ 80379f2:	f442 4204 	orr.w	r2, r2, #33792	@ 0x8400
+ 80379f6:	609a      	str	r2, [r3, #8]
+  }
+
+  /*---------------------------- I2Cx CR2 Configuration ----------------------*/
+  /* Configure I2Cx: Addressing Master mode */
+  if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+ 80379f8:	687b      	ldr	r3, [r7, #4]
+ 80379fa:	68db      	ldr	r3, [r3, #12]
+ 80379fc:	2b02      	cmp	r3, #2
+ 80379fe:	d108      	bne.n	8037a12 <HAL_I2C_Init+0xa2>
+  {
+    SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
+ 8037a00:	687b      	ldr	r3, [r7, #4]
+ 8037a02:	681b      	ldr	r3, [r3, #0]
+ 8037a04:	685a      	ldr	r2, [r3, #4]
+ 8037a06:	687b      	ldr	r3, [r7, #4]
+ 8037a08:	681b      	ldr	r3, [r3, #0]
+ 8037a0a:	f442 6200 	orr.w	r2, r2, #2048	@ 0x800
+ 8037a0e:	605a      	str	r2, [r3, #4]
+ 8037a10:	e007      	b.n	8037a22 <HAL_I2C_Init+0xb2>
+  }
+  else
+  {
+    /* Clear the I2C ADD10 bit */
+    CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
+ 8037a12:	687b      	ldr	r3, [r7, #4]
+ 8037a14:	681b      	ldr	r3, [r3, #0]
+ 8037a16:	685a      	ldr	r2, [r3, #4]
+ 8037a18:	687b      	ldr	r3, [r7, #4]
+ 8037a1a:	681b      	ldr	r3, [r3, #0]
+ 8037a1c:	f422 6200 	bic.w	r2, r2, #2048	@ 0x800
+ 8037a20:	605a      	str	r2, [r3, #4]
+  }
+  /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
+  hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
+ 8037a22:	687b      	ldr	r3, [r7, #4]
+ 8037a24:	681b      	ldr	r3, [r3, #0]
+ 8037a26:	6859      	ldr	r1, [r3, #4]
+ 8037a28:	687b      	ldr	r3, [r7, #4]
+ 8037a2a:	681a      	ldr	r2, [r3, #0]
+ 8037a2c:	4b1d      	ldr	r3, [pc, #116]	@ (8037aa4 <HAL_I2C_Init+0x134>)
+ 8037a2e:	430b      	orrs	r3, r1
+ 8037a30:	6053      	str	r3, [r2, #4]
+
+  /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
+  /* Disable Own Address2 before set the Own Address2 configuration */
+  hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
+ 8037a32:	687b      	ldr	r3, [r7, #4]
+ 8037a34:	681b      	ldr	r3, [r3, #0]
+ 8037a36:	68da      	ldr	r2, [r3, #12]
+ 8037a38:	687b      	ldr	r3, [r7, #4]
+ 8037a3a:	681b      	ldr	r3, [r3, #0]
+ 8037a3c:	f422 4200 	bic.w	r2, r2, #32768	@ 0x8000
+ 8037a40:	60da      	str	r2, [r3, #12]
+
+  /* Configure I2Cx: Dual mode and Own Address2 */
+  hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
+ 8037a42:	687b      	ldr	r3, [r7, #4]
+ 8037a44:	691a      	ldr	r2, [r3, #16]
+ 8037a46:	687b      	ldr	r3, [r7, #4]
+ 8037a48:	695b      	ldr	r3, [r3, #20]
+ 8037a4a:	ea42 0103 	orr.w	r1, r2, r3
+                          (hi2c->Init.OwnAddress2Masks << 8));
+ 8037a4e:	687b      	ldr	r3, [r7, #4]
+ 8037a50:	699b      	ldr	r3, [r3, #24]
+ 8037a52:	021a      	lsls	r2, r3, #8
+  hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
+ 8037a54:	687b      	ldr	r3, [r7, #4]
+ 8037a56:	681b      	ldr	r3, [r3, #0]
+ 8037a58:	430a      	orrs	r2, r1
+ 8037a5a:	60da      	str	r2, [r3, #12]
+
+  /*---------------------------- I2Cx CR1 Configuration ----------------------*/
+  /* Configure I2Cx: Generalcall and NoStretch mode */
+  hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
+ 8037a5c:	687b      	ldr	r3, [r7, #4]
+ 8037a5e:	69d9      	ldr	r1, [r3, #28]
+ 8037a60:	687b      	ldr	r3, [r7, #4]
+ 8037a62:	6a1a      	ldr	r2, [r3, #32]
+ 8037a64:	687b      	ldr	r3, [r7, #4]
+ 8037a66:	681b      	ldr	r3, [r3, #0]
+ 8037a68:	430a      	orrs	r2, r1
+ 8037a6a:	601a      	str	r2, [r3, #0]
+
+  /* Enable the selected I2C peripheral */
+  __HAL_I2C_ENABLE(hi2c);
+ 8037a6c:	687b      	ldr	r3, [r7, #4]
+ 8037a6e:	681b      	ldr	r3, [r3, #0]
+ 8037a70:	681a      	ldr	r2, [r3, #0]
+ 8037a72:	687b      	ldr	r3, [r7, #4]
+ 8037a74:	681b      	ldr	r3, [r3, #0]
+ 8037a76:	f042 0201 	orr.w	r2, r2, #1
+ 8037a7a:	601a      	str	r2, [r3, #0]
+
+  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 8037a7c:	687b      	ldr	r3, [r7, #4]
+ 8037a7e:	2200      	movs	r2, #0
+ 8037a80:	645a      	str	r2, [r3, #68]	@ 0x44
+  hi2c->State = HAL_I2C_STATE_READY;
+ 8037a82:	687b      	ldr	r3, [r7, #4]
+ 8037a84:	2220      	movs	r2, #32
+ 8037a86:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
+  hi2c->PreviousState = I2C_STATE_NONE;
+ 8037a8a:	687b      	ldr	r3, [r7, #4]
+ 8037a8c:	2200      	movs	r2, #0
+ 8037a8e:	631a      	str	r2, [r3, #48]	@ 0x30
+  hi2c->Mode = HAL_I2C_MODE_NONE;
+ 8037a90:	687b      	ldr	r3, [r7, #4]
+ 8037a92:	2200      	movs	r2, #0
+ 8037a94:	f883 2042 	strb.w	r2, [r3, #66]	@ 0x42
+
+  return HAL_OK;
+ 8037a98:	2300      	movs	r3, #0
+}
+ 8037a9a:	4618      	mov	r0, r3
+ 8037a9c:	3708      	adds	r7, #8
+ 8037a9e:	46bd      	mov	sp, r7
+ 8037aa0:	bd80      	pop	{r7, pc}
+ 8037aa2:	bf00      	nop
+ 8037aa4:	02008000 	.word	0x02008000
+
+08037aa8 <HAL_I2C_EV_IRQHandler>:
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) /* Derogation MISRAC2012-Rule-8.13 */
+{
+ 8037aa8:	b580      	push	{r7, lr}
+ 8037aaa:	b084      	sub	sp, #16
+ 8037aac:	af00      	add	r7, sp, #0
+ 8037aae:	6078      	str	r0, [r7, #4]
+  /* Get current IT Flags and IT sources value */
+  uint32_t itflags   = READ_REG(hi2c->Instance->ISR);
+ 8037ab0:	687b      	ldr	r3, [r7, #4]
+ 8037ab2:	681b      	ldr	r3, [r3, #0]
+ 8037ab4:	699b      	ldr	r3, [r3, #24]
+ 8037ab6:	60fb      	str	r3, [r7, #12]
+  uint32_t itsources = READ_REG(hi2c->Instance->CR1);
+ 8037ab8:	687b      	ldr	r3, [r7, #4]
+ 8037aba:	681b      	ldr	r3, [r3, #0]
+ 8037abc:	681b      	ldr	r3, [r3, #0]
+ 8037abe:	60bb      	str	r3, [r7, #8]
+
+  /* I2C events treatment -------------------------------------*/
+  if (hi2c->XferISR != NULL)
+ 8037ac0:	687b      	ldr	r3, [r7, #4]
+ 8037ac2:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
+ 8037ac4:	2b00      	cmp	r3, #0
+ 8037ac6:	d005      	beq.n	8037ad4 <HAL_I2C_EV_IRQHandler+0x2c>
+  {
+    hi2c->XferISR(hi2c, itflags, itsources);
+ 8037ac8:	687b      	ldr	r3, [r7, #4]
+ 8037aca:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
+ 8037acc:	68ba      	ldr	r2, [r7, #8]
+ 8037ace:	68f9      	ldr	r1, [r7, #12]
+ 8037ad0:	6878      	ldr	r0, [r7, #4]
+ 8037ad2:	4798      	blx	r3
+  }
+}
+ 8037ad4:	bf00      	nop
+ 8037ad6:	3710      	adds	r7, #16
+ 8037ad8:	46bd      	mov	sp, r7
+ 8037ada:	bd80      	pop	{r7, pc}
+
+08037adc <HAL_I2C_ER_IRQHandler>:
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
+{
+ 8037adc:	b580      	push	{r7, lr}
+ 8037ade:	b086      	sub	sp, #24
+ 8037ae0:	af00      	add	r7, sp, #0
+ 8037ae2:	6078      	str	r0, [r7, #4]
+  uint32_t itflags   = READ_REG(hi2c->Instance->ISR);
+ 8037ae4:	687b      	ldr	r3, [r7, #4]
+ 8037ae6:	681b      	ldr	r3, [r3, #0]
+ 8037ae8:	699b      	ldr	r3, [r3, #24]
+ 8037aea:	617b      	str	r3, [r7, #20]
+  uint32_t itsources = READ_REG(hi2c->Instance->CR1);
+ 8037aec:	687b      	ldr	r3, [r7, #4]
+ 8037aee:	681b      	ldr	r3, [r3, #0]
+ 8037af0:	681b      	ldr	r3, [r3, #0]
+ 8037af2:	613b      	str	r3, [r7, #16]
+  uint32_t tmperror;
+
+  /* I2C Bus error interrupt occurred ------------------------------------*/
+  if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \
+ 8037af4:	697b      	ldr	r3, [r7, #20]
+ 8037af6:	f403 7380 	and.w	r3, r3, #256	@ 0x100
+ 8037afa:	2b00      	cmp	r3, #0
+ 8037afc:	d00f      	beq.n	8037b1e <HAL_I2C_ER_IRQHandler+0x42>
+      (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+ 8037afe:	693b      	ldr	r3, [r7, #16]
+ 8037b00:	f003 0380 	and.w	r3, r3, #128	@ 0x80
+  if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \
+ 8037b04:	2b00      	cmp	r3, #0
+ 8037b06:	d00a      	beq.n	8037b1e <HAL_I2C_ER_IRQHandler+0x42>
+  {
+    hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
+ 8037b08:	687b      	ldr	r3, [r7, #4]
+ 8037b0a:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
+ 8037b0c:	f043 0201 	orr.w	r2, r3, #1
+ 8037b10:	687b      	ldr	r3, [r7, #4]
+ 8037b12:	645a      	str	r2, [r3, #68]	@ 0x44
+
+    /* Clear BERR flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
+ 8037b14:	687b      	ldr	r3, [r7, #4]
+ 8037b16:	681b      	ldr	r3, [r3, #0]
+ 8037b18:	f44f 7280 	mov.w	r2, #256	@ 0x100
+ 8037b1c:	61da      	str	r2, [r3, #28]
+  }
+
+  /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
+  if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \
+ 8037b1e:	697b      	ldr	r3, [r7, #20]
+ 8037b20:	f403 6380 	and.w	r3, r3, #1024	@ 0x400
+ 8037b24:	2b00      	cmp	r3, #0
+ 8037b26:	d00f      	beq.n	8037b48 <HAL_I2C_ER_IRQHandler+0x6c>
+      (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+ 8037b28:	693b      	ldr	r3, [r7, #16]
+ 8037b2a:	f003 0380 	and.w	r3, r3, #128	@ 0x80
+  if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \
+ 8037b2e:	2b00      	cmp	r3, #0
+ 8037b30:	d00a      	beq.n	8037b48 <HAL_I2C_ER_IRQHandler+0x6c>
+  {
+    hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
+ 8037b32:	687b      	ldr	r3, [r7, #4]
+ 8037b34:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
+ 8037b36:	f043 0208 	orr.w	r2, r3, #8
+ 8037b3a:	687b      	ldr	r3, [r7, #4]
+ 8037b3c:	645a      	str	r2, [r3, #68]	@ 0x44
+
+    /* Clear OVR flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
+ 8037b3e:	687b      	ldr	r3, [r7, #4]
+ 8037b40:	681b      	ldr	r3, [r3, #0]
+ 8037b42:	f44f 6280 	mov.w	r2, #1024	@ 0x400
+ 8037b46:	61da      	str	r2, [r3, #28]
+  }
+
+  /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
+  if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \
+ 8037b48:	697b      	ldr	r3, [r7, #20]
+ 8037b4a:	f403 7300 	and.w	r3, r3, #512	@ 0x200
+ 8037b4e:	2b00      	cmp	r3, #0
+ 8037b50:	d00f      	beq.n	8037b72 <HAL_I2C_ER_IRQHandler+0x96>
+      (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+ 8037b52:	693b      	ldr	r3, [r7, #16]
+ 8037b54:	f003 0380 	and.w	r3, r3, #128	@ 0x80
+  if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \
+ 8037b58:	2b00      	cmp	r3, #0
+ 8037b5a:	d00a      	beq.n	8037b72 <HAL_I2C_ER_IRQHandler+0x96>
+  {
+    hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
+ 8037b5c:	687b      	ldr	r3, [r7, #4]
+ 8037b5e:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
+ 8037b60:	f043 0202 	orr.w	r2, r3, #2
+ 8037b64:	687b      	ldr	r3, [r7, #4]
+ 8037b66:	645a      	str	r2, [r3, #68]	@ 0x44
+
+    /* Clear ARLO flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
+ 8037b68:	687b      	ldr	r3, [r7, #4]
+ 8037b6a:	681b      	ldr	r3, [r3, #0]
+ 8037b6c:	f44f 7200 	mov.w	r2, #512	@ 0x200
+ 8037b70:	61da      	str	r2, [r3, #28]
+  }
+
+  /* Store current volatile hi2c->ErrorCode, misra rule */
+  tmperror = hi2c->ErrorCode;
+ 8037b72:	687b      	ldr	r3, [r7, #4]
+ 8037b74:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
+ 8037b76:	60fb      	str	r3, [r7, #12]
+
+  /* Call the Error Callback in case of Error detected */
+  if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) !=  HAL_I2C_ERROR_NONE)
+ 8037b78:	68fb      	ldr	r3, [r7, #12]
+ 8037b7a:	f003 030b 	and.w	r3, r3, #11
+ 8037b7e:	2b00      	cmp	r3, #0
+ 8037b80:	d003      	beq.n	8037b8a <HAL_I2C_ER_IRQHandler+0xae>
+  {
+    I2C_ITError(hi2c, tmperror);
+ 8037b82:	68f9      	ldr	r1, [r7, #12]
+ 8037b84:	6878      	ldr	r0, [r7, #4]
+ 8037b86:	f000 fcc5 	bl	8038514 <I2C_ITError>
+  }
+}
+ 8037b8a:	bf00      	nop
+ 8037b8c:	3718      	adds	r7, #24
+ 8037b8e:	46bd      	mov	sp, r7
+ 8037b90:	bd80      	pop	{r7, pc}
+
+08037b92 <HAL_I2C_SlaveTxCpltCallback>:
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ 8037b92:	b480      	push	{r7}
+ 8037b94:	b083      	sub	sp, #12
+ 8037b96:	af00      	add	r7, sp, #0
+ 8037b98:	6078      	str	r0, [r7, #4]
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
+   */
+}
+ 8037b9a:	bf00      	nop
+ 8037b9c:	370c      	adds	r7, #12
+ 8037b9e:	46bd      	mov	sp, r7
+ 8037ba0:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8037ba4:	4770      	bx	lr
+
+08037ba6 <HAL_I2C_SlaveRxCpltCallback>:
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ 8037ba6:	b480      	push	{r7}
+ 8037ba8:	b083      	sub	sp, #12
+ 8037baa:	af00      	add	r7, sp, #0
+ 8037bac:	6078      	str	r0, [r7, #4]
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
+   */
+}
+ 8037bae:	bf00      	nop
+ 8037bb0:	370c      	adds	r7, #12
+ 8037bb2:	46bd      	mov	sp, r7
+ 8037bb4:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8037bb8:	4770      	bx	lr
+
+08037bba <HAL_I2C_AddrCallback>:
+  * @param  TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION
+  * @param  AddrMatchCode Address Match Code
+  * @retval None
+  */
+__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
+{
+ 8037bba:	b480      	push	{r7}
+ 8037bbc:	b083      	sub	sp, #12
+ 8037bbe:	af00      	add	r7, sp, #0
+ 8037bc0:	6078      	str	r0, [r7, #4]
+ 8037bc2:	460b      	mov	r3, r1
+ 8037bc4:	70fb      	strb	r3, [r7, #3]
+ 8037bc6:	4613      	mov	r3, r2
+ 8037bc8:	803b      	strh	r3, [r7, #0]
+  UNUSED(AddrMatchCode);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_AddrCallback() could be implemented in the user file
+   */
+}
+ 8037bca:	bf00      	nop
+ 8037bcc:	370c      	adds	r7, #12
+ 8037bce:	46bd      	mov	sp, r7
+ 8037bd0:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8037bd4:	4770      	bx	lr
+
+08037bd6 <HAL_I2C_ListenCpltCallback>:
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ 8037bd6:	b480      	push	{r7}
+ 8037bd8:	b083      	sub	sp, #12
+ 8037bda:	af00      	add	r7, sp, #0
+ 8037bdc:	6078      	str	r0, [r7, #4]
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_ListenCpltCallback() could be implemented in the user file
+   */
+}
+ 8037bde:	bf00      	nop
+ 8037be0:	370c      	adds	r7, #12
+ 8037be2:	46bd      	mov	sp, r7
+ 8037be4:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8037be8:	4770      	bx	lr
+
+08037bea <HAL_I2C_ErrorCallback>:
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
+{
+ 8037bea:	b480      	push	{r7}
+ 8037bec:	b083      	sub	sp, #12
+ 8037bee:	af00      	add	r7, sp, #0
+ 8037bf0:	6078      	str	r0, [r7, #4]
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_ErrorCallback could be implemented in the user file
+   */
+}
+ 8037bf2:	bf00      	nop
+ 8037bf4:	370c      	adds	r7, #12
+ 8037bf6:	46bd      	mov	sp, r7
+ 8037bf8:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8037bfc:	4770      	bx	lr
+
+08037bfe <HAL_I2C_AbortCpltCallback>:
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @retval None
+  */
+__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ 8037bfe:	b480      	push	{r7}
+ 8037c00:	b083      	sub	sp, #12
+ 8037c02:	af00      	add	r7, sp, #0
+ 8037c04:	6078      	str	r0, [r7, #4]
+  UNUSED(hi2c);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_I2C_AbortCpltCallback could be implemented in the user file
+   */
+}
+ 8037c06:	bf00      	nop
+ 8037c08:	370c      	adds	r7, #12
+ 8037c0a:	46bd      	mov	sp, r7
+ 8037c0c:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8037c10:	4770      	bx	lr
+
+08037c12 <I2C_Slave_ISR_IT>:
+  * @param  ITSources Interrupt sources enabled.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+                                          uint32_t ITSources)
+{
+ 8037c12:	b580      	push	{r7, lr}
+ 8037c14:	b086      	sub	sp, #24
+ 8037c16:	af00      	add	r7, sp, #0
+ 8037c18:	60f8      	str	r0, [r7, #12]
+ 8037c1a:	60b9      	str	r1, [r7, #8]
+ 8037c1c:	607a      	str	r2, [r7, #4]
+  uint32_t tmpoptions = hi2c->XferOptions;
+ 8037c1e:	68fb      	ldr	r3, [r7, #12]
+ 8037c20:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 8037c22:	617b      	str	r3, [r7, #20]
+  uint32_t tmpITFlags = ITFlags;
+ 8037c24:	68bb      	ldr	r3, [r7, #8]
+ 8037c26:	613b      	str	r3, [r7, #16]
+
+  /* Process locked */
+  __HAL_LOCK(hi2c);
+ 8037c28:	68fb      	ldr	r3, [r7, #12]
+ 8037c2a:	f893 3040 	ldrb.w	r3, [r3, #64]	@ 0x40
+ 8037c2e:	2b01      	cmp	r3, #1
+ 8037c30:	d101      	bne.n	8037c36 <I2C_Slave_ISR_IT+0x24>
+ 8037c32:	2302      	movs	r3, #2
+ 8037c34:	e0e2      	b.n	8037dfc <I2C_Slave_ISR_IT+0x1ea>
+ 8037c36:	68fb      	ldr	r3, [r7, #12]
+ 8037c38:	2201      	movs	r2, #1
+ 8037c3a:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40
+
+  /* Check if STOPF is set */
+  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
+ 8037c3e:	693b      	ldr	r3, [r7, #16]
+ 8037c40:	f003 0320 	and.w	r3, r3, #32
+ 8037c44:	2b00      	cmp	r3, #0
+ 8037c46:	d009      	beq.n	8037c5c <I2C_Slave_ISR_IT+0x4a>
+      (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ 8037c48:	687b      	ldr	r3, [r7, #4]
+ 8037c4a:	f003 0320 	and.w	r3, r3, #32
+  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
+ 8037c4e:	2b00      	cmp	r3, #0
+ 8037c50:	d004      	beq.n	8037c5c <I2C_Slave_ISR_IT+0x4a>
+  {
+    /* Call I2C Slave complete process */
+    I2C_ITSlaveCplt(hi2c, tmpITFlags);
+ 8037c52:	6939      	ldr	r1, [r7, #16]
+ 8037c54:	68f8      	ldr	r0, [r7, #12]
+ 8037c56:	f000 f9b5 	bl	8037fc4 <I2C_ITSlaveCplt>
+ 8037c5a:	e0ca      	b.n	8037df2 <I2C_Slave_ISR_IT+0x1e0>
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
+ 8037c5c:	693b      	ldr	r3, [r7, #16]
+ 8037c5e:	f003 0310 	and.w	r3, r3, #16
+ 8037c62:	2b00      	cmp	r3, #0
+ 8037c64:	d04b      	beq.n	8037cfe <I2C_Slave_ISR_IT+0xec>
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ 8037c66:	687b      	ldr	r3, [r7, #4]
+ 8037c68:	f003 0310 	and.w	r3, r3, #16
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
+ 8037c6c:	2b00      	cmp	r3, #0
+ 8037c6e:	d046      	beq.n	8037cfe <I2C_Slave_ISR_IT+0xec>
+  {
+    /* Check that I2C transfer finished */
+    /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
+    /* Mean XferCount == 0*/
+    /* So clear Flag NACKF only */
+    if (hi2c->XferCount == 0U)
+ 8037c70:	68fb      	ldr	r3, [r7, #12]
+ 8037c72:	8d5b      	ldrh	r3, [r3, #42]	@ 0x2a
+ 8037c74:	b29b      	uxth	r3, r3
+ 8037c76:	2b00      	cmp	r3, #0
+ 8037c78:	d128      	bne.n	8037ccc <I2C_Slave_ISR_IT+0xba>
+    {
+      if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
+ 8037c7a:	68fb      	ldr	r3, [r7, #12]
+ 8037c7c:	f893 3041 	ldrb.w	r3, [r3, #65]	@ 0x41
+ 8037c80:	b2db      	uxtb	r3, r3
+ 8037c82:	2b28      	cmp	r3, #40	@ 0x28
+ 8037c84:	d108      	bne.n	8037c98 <I2C_Slave_ISR_IT+0x86>
+ 8037c86:	697b      	ldr	r3, [r7, #20]
+ 8037c88:	f1b3 7f00 	cmp.w	r3, #33554432	@ 0x2000000
+ 8037c8c:	d104      	bne.n	8037c98 <I2C_Slave_ISR_IT+0x86>
+        /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
+           Warning[Pa134]: left and right operands are identical */
+      {
+        /* Call I2C Listen complete process */
+        I2C_ITListenCplt(hi2c, tmpITFlags);
+ 8037c8e:	6939      	ldr	r1, [r7, #16]
+ 8037c90:	68f8      	ldr	r0, [r7, #12]
+ 8037c92:	f000 fbeb 	bl	803846c <I2C_ITListenCplt>
+ 8037c96:	e031      	b.n	8037cfc <I2C_Slave_ISR_IT+0xea>
+      }
+      else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
+ 8037c98:	68fb      	ldr	r3, [r7, #12]
+ 8037c9a:	f893 3041 	ldrb.w	r3, [r3, #65]	@ 0x41
+ 8037c9e:	b2db      	uxtb	r3, r3
+ 8037ca0:	2b29      	cmp	r3, #41	@ 0x29
+ 8037ca2:	d10e      	bne.n	8037cc2 <I2C_Slave_ISR_IT+0xb0>
+ 8037ca4:	697b      	ldr	r3, [r7, #20]
+ 8037ca6:	f513 3f80 	cmn.w	r3, #65536	@ 0x10000
+ 8037caa:	d00a      	beq.n	8037cc2 <I2C_Slave_ISR_IT+0xb0>
+      {
+        /* Clear NACK Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+ 8037cac:	68fb      	ldr	r3, [r7, #12]
+ 8037cae:	681b      	ldr	r3, [r3, #0]
+ 8037cb0:	2210      	movs	r2, #16
+ 8037cb2:	61da      	str	r2, [r3, #28]
+
+        /* Flush TX register */
+        I2C_Flush_TXDR(hi2c);
+ 8037cb4:	68f8      	ldr	r0, [r7, #12]
+ 8037cb6:	f000 fd44 	bl	8038742 <I2C_Flush_TXDR>
+
+        /* Last Byte is Transmitted */
+        /* Call I2C Slave Sequential complete process */
+        I2C_ITSlaveSeqCplt(hi2c);
+ 8037cba:	68f8      	ldr	r0, [r7, #12]
+ 8037cbc:	f000 f926 	bl	8037f0c <I2C_ITSlaveSeqCplt>
+ 8037cc0:	e01c      	b.n	8037cfc <I2C_Slave_ISR_IT+0xea>
+      }
+      else
+      {
+        /* Clear NACK Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+ 8037cc2:	68fb      	ldr	r3, [r7, #12]
+ 8037cc4:	681b      	ldr	r3, [r3, #0]
+ 8037cc6:	2210      	movs	r2, #16
+ 8037cc8:	61da      	str	r2, [r3, #28]
+    if (hi2c->XferCount == 0U)
+ 8037cca:	e08f      	b.n	8037dec <I2C_Slave_ISR_IT+0x1da>
+    }
+    else
+    {
+      /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
+      /* Clear NACK Flag */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+ 8037ccc:	68fb      	ldr	r3, [r7, #12]
+ 8037cce:	681b      	ldr	r3, [r3, #0]
+ 8037cd0:	2210      	movs	r2, #16
+ 8037cd2:	61da      	str	r2, [r3, #28]
+
+      /* Set ErrorCode corresponding to a Non-Acknowledge */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ 8037cd4:	68fb      	ldr	r3, [r7, #12]
+ 8037cd6:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
+ 8037cd8:	f043 0204 	orr.w	r2, r3, #4
+ 8037cdc:	68fb      	ldr	r3, [r7, #12]
+ 8037cde:	645a      	str	r2, [r3, #68]	@ 0x44
+
+      if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
+ 8037ce0:	697b      	ldr	r3, [r7, #20]
+ 8037ce2:	2b00      	cmp	r3, #0
+ 8037ce4:	d003      	beq.n	8037cee <I2C_Slave_ISR_IT+0xdc>
+ 8037ce6:	697b      	ldr	r3, [r7, #20]
+ 8037ce8:	f1b3 7f80 	cmp.w	r3, #16777216	@ 0x1000000
+ 8037cec:	d17e      	bne.n	8037dec <I2C_Slave_ISR_IT+0x1da>
+      {
+        /* Call the corresponding callback to inform upper layer of End of Transfer */
+        I2C_ITError(hi2c, hi2c->ErrorCode);
+ 8037cee:	68fb      	ldr	r3, [r7, #12]
+ 8037cf0:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
+ 8037cf2:	4619      	mov	r1, r3
+ 8037cf4:	68f8      	ldr	r0, [r7, #12]
+ 8037cf6:	f000 fc0d 	bl	8038514 <I2C_ITError>
+    if (hi2c->XferCount == 0U)
+ 8037cfa:	e077      	b.n	8037dec <I2C_Slave_ISR_IT+0x1da>
+ 8037cfc:	e076      	b.n	8037dec <I2C_Slave_ISR_IT+0x1da>
+      }
+    }
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
+ 8037cfe:	693b      	ldr	r3, [r7, #16]
+ 8037d00:	f003 0304 	and.w	r3, r3, #4
+ 8037d04:	2b00      	cmp	r3, #0
+ 8037d06:	d02f      	beq.n	8037d68 <I2C_Slave_ISR_IT+0x156>
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
+ 8037d08:	687b      	ldr	r3, [r7, #4]
+ 8037d0a:	f003 0304 	and.w	r3, r3, #4
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
+ 8037d0e:	2b00      	cmp	r3, #0
+ 8037d10:	d02a      	beq.n	8037d68 <I2C_Slave_ISR_IT+0x156>
+  {
+    if (hi2c->XferCount > 0U)
+ 8037d12:	68fb      	ldr	r3, [r7, #12]
+ 8037d14:	8d5b      	ldrh	r3, [r3, #42]	@ 0x2a
+ 8037d16:	b29b      	uxth	r3, r3
+ 8037d18:	2b00      	cmp	r3, #0
+ 8037d1a:	d018      	beq.n	8037d4e <I2C_Slave_ISR_IT+0x13c>
+    {
+      /* Read data from RXDR */
+      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+ 8037d1c:	68fb      	ldr	r3, [r7, #12]
+ 8037d1e:	681b      	ldr	r3, [r3, #0]
+ 8037d20:	6a5a      	ldr	r2, [r3, #36]	@ 0x24
+ 8037d22:	68fb      	ldr	r3, [r7, #12]
+ 8037d24:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 8037d26:	b2d2      	uxtb	r2, r2
+ 8037d28:	701a      	strb	r2, [r3, #0]
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+ 8037d2a:	68fb      	ldr	r3, [r7, #12]
+ 8037d2c:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 8037d2e:	1c5a      	adds	r2, r3, #1
+ 8037d30:	68fb      	ldr	r3, [r7, #12]
+ 8037d32:	625a      	str	r2, [r3, #36]	@ 0x24
+
+      hi2c->XferSize--;
+ 8037d34:	68fb      	ldr	r3, [r7, #12]
+ 8037d36:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
+ 8037d38:	3b01      	subs	r3, #1
+ 8037d3a:	b29a      	uxth	r2, r3
+ 8037d3c:	68fb      	ldr	r3, [r7, #12]
+ 8037d3e:	851a      	strh	r2, [r3, #40]	@ 0x28
+      hi2c->XferCount--;
+ 8037d40:	68fb      	ldr	r3, [r7, #12]
+ 8037d42:	8d5b      	ldrh	r3, [r3, #42]	@ 0x2a
+ 8037d44:	b29b      	uxth	r3, r3
+ 8037d46:	3b01      	subs	r3, #1
+ 8037d48:	b29a      	uxth	r2, r3
+ 8037d4a:	68fb      	ldr	r3, [r7, #12]
+ 8037d4c:	855a      	strh	r2, [r3, #42]	@ 0x2a
+    }
+
+    if ((hi2c->XferCount == 0U) && \
+ 8037d4e:	68fb      	ldr	r3, [r7, #12]
+ 8037d50:	8d5b      	ldrh	r3, [r3, #42]	@ 0x2a
+ 8037d52:	b29b      	uxth	r3, r3
+ 8037d54:	2b00      	cmp	r3, #0
+ 8037d56:	d14b      	bne.n	8037df0 <I2C_Slave_ISR_IT+0x1de>
+ 8037d58:	697b      	ldr	r3, [r7, #20]
+ 8037d5a:	f513 3f80 	cmn.w	r3, #65536	@ 0x10000
+ 8037d5e:	d047      	beq.n	8037df0 <I2C_Slave_ISR_IT+0x1de>
+        (tmpoptions != I2C_NO_OPTION_FRAME))
+    {
+      /* Call I2C Slave Sequential complete process */
+      I2C_ITSlaveSeqCplt(hi2c);
+ 8037d60:	68f8      	ldr	r0, [r7, #12]
+ 8037d62:	f000 f8d3 	bl	8037f0c <I2C_ITSlaveSeqCplt>
+    if ((hi2c->XferCount == 0U) && \
+ 8037d66:	e043      	b.n	8037df0 <I2C_Slave_ISR_IT+0x1de>
+    }
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \
+ 8037d68:	693b      	ldr	r3, [r7, #16]
+ 8037d6a:	f003 0308 	and.w	r3, r3, #8
+ 8037d6e:	2b00      	cmp	r3, #0
+ 8037d70:	d009      	beq.n	8037d86 <I2C_Slave_ISR_IT+0x174>
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
+ 8037d72:	687b      	ldr	r3, [r7, #4]
+ 8037d74:	f003 0308 	and.w	r3, r3, #8
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \
+ 8037d78:	2b00      	cmp	r3, #0
+ 8037d7a:	d004      	beq.n	8037d86 <I2C_Slave_ISR_IT+0x174>
+  {
+    I2C_ITAddrCplt(hi2c, tmpITFlags);
+ 8037d7c:	6939      	ldr	r1, [r7, #16]
+ 8037d7e:	68f8      	ldr	r0, [r7, #12]
+ 8037d80:	f000 f840 	bl	8037e04 <I2C_ITAddrCplt>
+ 8037d84:	e035      	b.n	8037df2 <I2C_Slave_ISR_IT+0x1e0>
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
+ 8037d86:	693b      	ldr	r3, [r7, #16]
+ 8037d88:	f003 0302 	and.w	r3, r3, #2
+ 8037d8c:	2b00      	cmp	r3, #0
+ 8037d8e:	d030      	beq.n	8037df2 <I2C_Slave_ISR_IT+0x1e0>
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
+ 8037d90:	687b      	ldr	r3, [r7, #4]
+ 8037d92:	f003 0302 	and.w	r3, r3, #2
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
+ 8037d96:	2b00      	cmp	r3, #0
+ 8037d98:	d02b      	beq.n	8037df2 <I2C_Slave_ISR_IT+0x1e0>
+  {
+    /* Write data to TXDR only if XferCount not reach "0" */
+    /* A TXIS flag can be set, during STOP treatment      */
+    /* Check if all Data have already been sent */
+    /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
+    if (hi2c->XferCount > 0U)
+ 8037d9a:	68fb      	ldr	r3, [r7, #12]
+ 8037d9c:	8d5b      	ldrh	r3, [r3, #42]	@ 0x2a
+ 8037d9e:	b29b      	uxth	r3, r3
+ 8037da0:	2b00      	cmp	r3, #0
+ 8037da2:	d018      	beq.n	8037dd6 <I2C_Slave_ISR_IT+0x1c4>
+    {
+      /* Write data to TXDR */
+      hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+ 8037da4:	68fb      	ldr	r3, [r7, #12]
+ 8037da6:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 8037da8:	781a      	ldrb	r2, [r3, #0]
+ 8037daa:	68fb      	ldr	r3, [r7, #12]
+ 8037dac:	681b      	ldr	r3, [r3, #0]
+ 8037dae:	629a      	str	r2, [r3, #40]	@ 0x28
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+ 8037db0:	68fb      	ldr	r3, [r7, #12]
+ 8037db2:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 8037db4:	1c5a      	adds	r2, r3, #1
+ 8037db6:	68fb      	ldr	r3, [r7, #12]
+ 8037db8:	625a      	str	r2, [r3, #36]	@ 0x24
+
+      hi2c->XferCount--;
+ 8037dba:	68fb      	ldr	r3, [r7, #12]
+ 8037dbc:	8d5b      	ldrh	r3, [r3, #42]	@ 0x2a
+ 8037dbe:	b29b      	uxth	r3, r3
+ 8037dc0:	3b01      	subs	r3, #1
+ 8037dc2:	b29a      	uxth	r2, r3
+ 8037dc4:	68fb      	ldr	r3, [r7, #12]
+ 8037dc6:	855a      	strh	r2, [r3, #42]	@ 0x2a
+      hi2c->XferSize--;
+ 8037dc8:	68fb      	ldr	r3, [r7, #12]
+ 8037dca:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
+ 8037dcc:	3b01      	subs	r3, #1
+ 8037dce:	b29a      	uxth	r2, r3
+ 8037dd0:	68fb      	ldr	r3, [r7, #12]
+ 8037dd2:	851a      	strh	r2, [r3, #40]	@ 0x28
+ 8037dd4:	e00d      	b.n	8037df2 <I2C_Slave_ISR_IT+0x1e0>
+    }
+    else
+    {
+      if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
+ 8037dd6:	697b      	ldr	r3, [r7, #20]
+ 8037dd8:	f1b3 7f80 	cmp.w	r3, #16777216	@ 0x1000000
+ 8037ddc:	d002      	beq.n	8037de4 <I2C_Slave_ISR_IT+0x1d2>
+ 8037dde:	697b      	ldr	r3, [r7, #20]
+ 8037de0:	2b00      	cmp	r3, #0
+ 8037de2:	d106      	bne.n	8037df2 <I2C_Slave_ISR_IT+0x1e0>
+      {
+        /* Last Byte is Transmitted */
+        /* Call I2C Slave Sequential complete process */
+        I2C_ITSlaveSeqCplt(hi2c);
+ 8037de4:	68f8      	ldr	r0, [r7, #12]
+ 8037de6:	f000 f891 	bl	8037f0c <I2C_ITSlaveSeqCplt>
+ 8037dea:	e002      	b.n	8037df2 <I2C_Slave_ISR_IT+0x1e0>
+    if (hi2c->XferCount == 0U)
+ 8037dec:	bf00      	nop
+ 8037dee:	e000      	b.n	8037df2 <I2C_Slave_ISR_IT+0x1e0>
+    if ((hi2c->XferCount == 0U) && \
+ 8037df0:	bf00      	nop
+  {
+    /* Nothing to do */
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2c);
+ 8037df2:	68fb      	ldr	r3, [r7, #12]
+ 8037df4:	2200      	movs	r2, #0
+ 8037df6:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40
+
+  return HAL_OK;
+ 8037dfa:	2300      	movs	r3, #0
+}
+ 8037dfc:	4618      	mov	r0, r3
+ 8037dfe:	3718      	adds	r7, #24
+ 8037e00:	46bd      	mov	sp, r7
+ 8037e02:	bd80      	pop	{r7, pc}
+
+08037e04 <I2C_ITAddrCplt>:
+  * @param  hi2c I2C handle.
+  * @param  ITFlags Interrupt flags to handle.
+  * @retval None
+  */
+static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
+{
+ 8037e04:	b580      	push	{r7, lr}
+ 8037e06:	b084      	sub	sp, #16
+ 8037e08:	af00      	add	r7, sp, #0
+ 8037e0a:	6078      	str	r0, [r7, #4]
+ 8037e0c:	6039      	str	r1, [r7, #0]
+
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(ITFlags);
+
+  /* In case of Listen state, need to inform upper layer of address match code event */
+  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+ 8037e0e:	687b      	ldr	r3, [r7, #4]
+ 8037e10:	f893 3041 	ldrb.w	r3, [r3, #65]	@ 0x41
+ 8037e14:	b2db      	uxtb	r3, r3
+ 8037e16:	f003 0328 	and.w	r3, r3, #40	@ 0x28
+ 8037e1a:	2b28      	cmp	r3, #40	@ 0x28
+ 8037e1c:	d16a      	bne.n	8037ef4 <I2C_ITAddrCplt+0xf0>
+  {
+    transferdirection = I2C_GET_DIR(hi2c);
+ 8037e1e:	687b      	ldr	r3, [r7, #4]
+ 8037e20:	681b      	ldr	r3, [r3, #0]
+ 8037e22:	699b      	ldr	r3, [r3, #24]
+ 8037e24:	0c1b      	lsrs	r3, r3, #16
+ 8037e26:	b2db      	uxtb	r3, r3
+ 8037e28:	f003 0301 	and.w	r3, r3, #1
+ 8037e2c:	73fb      	strb	r3, [r7, #15]
+    slaveaddrcode     = I2C_GET_ADDR_MATCH(hi2c);
+ 8037e2e:	687b      	ldr	r3, [r7, #4]
+ 8037e30:	681b      	ldr	r3, [r3, #0]
+ 8037e32:	699b      	ldr	r3, [r3, #24]
+ 8037e34:	0c1b      	lsrs	r3, r3, #16
+ 8037e36:	b29b      	uxth	r3, r3
+ 8037e38:	f003 03fe 	and.w	r3, r3, #254	@ 0xfe
+ 8037e3c:	81bb      	strh	r3, [r7, #12]
+    ownadd1code       = I2C_GET_OWN_ADDRESS1(hi2c);
+ 8037e3e:	687b      	ldr	r3, [r7, #4]
+ 8037e40:	681b      	ldr	r3, [r3, #0]
+ 8037e42:	689b      	ldr	r3, [r3, #8]
+ 8037e44:	b29b      	uxth	r3, r3
+ 8037e46:	f3c3 0309 	ubfx	r3, r3, #0, #10
+ 8037e4a:	817b      	strh	r3, [r7, #10]
+    ownadd2code       = I2C_GET_OWN_ADDRESS2(hi2c);
+ 8037e4c:	687b      	ldr	r3, [r7, #4]
+ 8037e4e:	681b      	ldr	r3, [r3, #0]
+ 8037e50:	68db      	ldr	r3, [r3, #12]
+ 8037e52:	b29b      	uxth	r3, r3
+ 8037e54:	f003 03fe 	and.w	r3, r3, #254	@ 0xfe
+ 8037e58:	813b      	strh	r3, [r7, #8]
+
+    /* If 10bits addressing mode is selected */
+    if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+ 8037e5a:	687b      	ldr	r3, [r7, #4]
+ 8037e5c:	68db      	ldr	r3, [r3, #12]
+ 8037e5e:	2b02      	cmp	r3, #2
+ 8037e60:	d138      	bne.n	8037ed4 <I2C_ITAddrCplt+0xd0>
+    {
+      if ((slaveaddrcode & SLAVE_ADDR_MSK) == ((ownadd1code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK))
+ 8037e62:	897b      	ldrh	r3, [r7, #10]
+ 8037e64:	09db      	lsrs	r3, r3, #7
+ 8037e66:	b29a      	uxth	r2, r3
+ 8037e68:	89bb      	ldrh	r3, [r7, #12]
+ 8037e6a:	4053      	eors	r3, r2
+ 8037e6c:	b29b      	uxth	r3, r3
+ 8037e6e:	f003 0306 	and.w	r3, r3, #6
+ 8037e72:	2b00      	cmp	r3, #0
+ 8037e74:	d11c      	bne.n	8037eb0 <I2C_ITAddrCplt+0xac>
+      {
+        slaveaddrcode = ownadd1code;
+ 8037e76:	897b      	ldrh	r3, [r7, #10]
+ 8037e78:	81bb      	strh	r3, [r7, #12]
+        hi2c->AddrEventCount++;
+ 8037e7a:	687b      	ldr	r3, [r7, #4]
+ 8037e7c:	6c9b      	ldr	r3, [r3, #72]	@ 0x48
+ 8037e7e:	1c5a      	adds	r2, r3, #1
+ 8037e80:	687b      	ldr	r3, [r7, #4]
+ 8037e82:	649a      	str	r2, [r3, #72]	@ 0x48
+        if (hi2c->AddrEventCount == 2U)
+ 8037e84:	687b      	ldr	r3, [r7, #4]
+ 8037e86:	6c9b      	ldr	r3, [r3, #72]	@ 0x48
+ 8037e88:	2b02      	cmp	r3, #2
+ 8037e8a:	d13b      	bne.n	8037f04 <I2C_ITAddrCplt+0x100>
+        {
+          /* Reset Address Event counter */
+          hi2c->AddrEventCount = 0U;
+ 8037e8c:	687b      	ldr	r3, [r7, #4]
+ 8037e8e:	2200      	movs	r2, #0
+ 8037e90:	649a      	str	r2, [r3, #72]	@ 0x48
+
+          /* Clear ADDR flag */
+          __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+ 8037e92:	687b      	ldr	r3, [r7, #4]
+ 8037e94:	681b      	ldr	r3, [r3, #0]
+ 8037e96:	2208      	movs	r2, #8
+ 8037e98:	61da      	str	r2, [r3, #28]
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hi2c);
+ 8037e9a:	687b      	ldr	r3, [r7, #4]
+ 8037e9c:	2200      	movs	r2, #0
+ 8037e9e:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40
+
+          /* Call Slave Addr callback */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+          hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#else
+          HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
+ 8037ea2:	89ba      	ldrh	r2, [r7, #12]
+ 8037ea4:	7bfb      	ldrb	r3, [r7, #15]
+ 8037ea6:	4619      	mov	r1, r3
+ 8037ea8:	6878      	ldr	r0, [r7, #4]
+ 8037eaa:	f7ff fe86 	bl	8037bba <HAL_I2C_AddrCallback>
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+  }
+}
+ 8037eae:	e029      	b.n	8037f04 <I2C_ITAddrCplt+0x100>
+        slaveaddrcode = ownadd2code;
+ 8037eb0:	893b      	ldrh	r3, [r7, #8]
+ 8037eb2:	81bb      	strh	r3, [r7, #12]
+        I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+ 8037eb4:	f44f 4100 	mov.w	r1, #32768	@ 0x8000
+ 8037eb8:	6878      	ldr	r0, [r7, #4]
+ 8037eba:	f000 fc84 	bl	80387c6 <I2C_Disable_IRQ>
+        __HAL_UNLOCK(hi2c);
+ 8037ebe:	687b      	ldr	r3, [r7, #4]
+ 8037ec0:	2200      	movs	r2, #0
+ 8037ec2:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40
+        HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
+ 8037ec6:	89ba      	ldrh	r2, [r7, #12]
+ 8037ec8:	7bfb      	ldrb	r3, [r7, #15]
+ 8037eca:	4619      	mov	r1, r3
+ 8037ecc:	6878      	ldr	r0, [r7, #4]
+ 8037ece:	f7ff fe74 	bl	8037bba <HAL_I2C_AddrCallback>
+}
+ 8037ed2:	e017      	b.n	8037f04 <I2C_ITAddrCplt+0x100>
+      I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+ 8037ed4:	f44f 4100 	mov.w	r1, #32768	@ 0x8000
+ 8037ed8:	6878      	ldr	r0, [r7, #4]
+ 8037eda:	f000 fc74 	bl	80387c6 <I2C_Disable_IRQ>
+      __HAL_UNLOCK(hi2c);
+ 8037ede:	687b      	ldr	r3, [r7, #4]
+ 8037ee0:	2200      	movs	r2, #0
+ 8037ee2:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40
+      HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
+ 8037ee6:	89ba      	ldrh	r2, [r7, #12]
+ 8037ee8:	7bfb      	ldrb	r3, [r7, #15]
+ 8037eea:	4619      	mov	r1, r3
+ 8037eec:	6878      	ldr	r0, [r7, #4]
+ 8037eee:	f7ff fe64 	bl	8037bba <HAL_I2C_AddrCallback>
+}
+ 8037ef2:	e007      	b.n	8037f04 <I2C_ITAddrCplt+0x100>
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+ 8037ef4:	687b      	ldr	r3, [r7, #4]
+ 8037ef6:	681b      	ldr	r3, [r3, #0]
+ 8037ef8:	2208      	movs	r2, #8
+ 8037efa:	61da      	str	r2, [r3, #28]
+    __HAL_UNLOCK(hi2c);
+ 8037efc:	687b      	ldr	r3, [r7, #4]
+ 8037efe:	2200      	movs	r2, #0
+ 8037f00:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40
+}
+ 8037f04:	bf00      	nop
+ 8037f06:	3710      	adds	r7, #16
+ 8037f08:	46bd      	mov	sp, r7
+ 8037f0a:	bd80      	pop	{r7, pc}
+
+08037f0c <I2C_ITSlaveSeqCplt>:
+  * @brief  I2C Slave sequential complete process.
+  * @param  hi2c I2C handle.
+  * @retval None
+  */
+static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c)
+{
+ 8037f0c:	b580      	push	{r7, lr}
+ 8037f0e:	b084      	sub	sp, #16
+ 8037f10:	af00      	add	r7, sp, #0
+ 8037f12:	6078      	str	r0, [r7, #4]
+  uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
+ 8037f14:	687b      	ldr	r3, [r7, #4]
+ 8037f16:	681b      	ldr	r3, [r3, #0]
+ 8037f18:	681b      	ldr	r3, [r3, #0]
+ 8037f1a:	60fb      	str	r3, [r7, #12]
+
+  /* Reset I2C handle mode */
+  hi2c->Mode = HAL_I2C_MODE_NONE;
+ 8037f1c:	687b      	ldr	r3, [r7, #4]
+ 8037f1e:	2200      	movs	r2, #0
+ 8037f20:	f883 2042 	strb.w	r2, [r3, #66]	@ 0x42
+
+  /* If a DMA is ongoing, Update handle size context */
+  if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
+ 8037f24:	68fb      	ldr	r3, [r7, #12]
+ 8037f26:	f403 4380 	and.w	r3, r3, #16384	@ 0x4000
+ 8037f2a:	2b00      	cmp	r3, #0
+ 8037f2c:	d008      	beq.n	8037f40 <I2C_ITSlaveSeqCplt+0x34>
+  {
+    /* Disable DMA Request */
+    hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+ 8037f2e:	687b      	ldr	r3, [r7, #4]
+ 8037f30:	681b      	ldr	r3, [r3, #0]
+ 8037f32:	681a      	ldr	r2, [r3, #0]
+ 8037f34:	687b      	ldr	r3, [r7, #4]
+ 8037f36:	681b      	ldr	r3, [r3, #0]
+ 8037f38:	f422 4280 	bic.w	r2, r2, #16384	@ 0x4000
+ 8037f3c:	601a      	str	r2, [r3, #0]
+ 8037f3e:	e00c      	b.n	8037f5a <I2C_ITSlaveSeqCplt+0x4e>
+  }
+  else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
+ 8037f40:	68fb      	ldr	r3, [r7, #12]
+ 8037f42:	f403 4300 	and.w	r3, r3, #32768	@ 0x8000
+ 8037f46:	2b00      	cmp	r3, #0
+ 8037f48:	d007      	beq.n	8037f5a <I2C_ITSlaveSeqCplt+0x4e>
+  {
+    /* Disable DMA Request */
+    hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+ 8037f4a:	687b      	ldr	r3, [r7, #4]
+ 8037f4c:	681b      	ldr	r3, [r3, #0]
+ 8037f4e:	681a      	ldr	r2, [r3, #0]
+ 8037f50:	687b      	ldr	r3, [r7, #4]
+ 8037f52:	681b      	ldr	r3, [r3, #0]
+ 8037f54:	f422 4200 	bic.w	r2, r2, #32768	@ 0x8000
+ 8037f58:	601a      	str	r2, [r3, #0]
+  else
+  {
+    /* Do nothing */
+  }
+
+  if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+ 8037f5a:	687b      	ldr	r3, [r7, #4]
+ 8037f5c:	f893 3041 	ldrb.w	r3, [r3, #65]	@ 0x41
+ 8037f60:	b2db      	uxtb	r3, r3
+ 8037f62:	2b29      	cmp	r3, #41	@ 0x29
+ 8037f64:	d112      	bne.n	8037f8c <I2C_ITSlaveSeqCplt+0x80>
+  {
+    /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
+    hi2c->State         = HAL_I2C_STATE_LISTEN;
+ 8037f66:	687b      	ldr	r3, [r7, #4]
+ 8037f68:	2228      	movs	r2, #40	@ 0x28
+ 8037f6a:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
+    hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+ 8037f6e:	687b      	ldr	r3, [r7, #4]
+ 8037f70:	2221      	movs	r2, #33	@ 0x21
+ 8037f72:	631a      	str	r2, [r3, #48]	@ 0x30
+
+    /* Disable Interrupts */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+ 8037f74:	2101      	movs	r1, #1
+ 8037f76:	6878      	ldr	r0, [r7, #4]
+ 8037f78:	f000 fc25 	bl	80387c6 <I2C_Disable_IRQ>
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+ 8037f7c:	687b      	ldr	r3, [r7, #4]
+ 8037f7e:	2200      	movs	r2, #0
+ 8037f80:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->SlaveTxCpltCallback(hi2c);
+#else
+    HAL_I2C_SlaveTxCpltCallback(hi2c);
+ 8037f84:	6878      	ldr	r0, [r7, #4]
+ 8037f86:	f7ff fe04 	bl	8037b92 <HAL_I2C_SlaveTxCpltCallback>
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+}
+ 8037f8a:	e017      	b.n	8037fbc <I2C_ITSlaveSeqCplt+0xb0>
+  else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+ 8037f8c:	687b      	ldr	r3, [r7, #4]
+ 8037f8e:	f893 3041 	ldrb.w	r3, [r3, #65]	@ 0x41
+ 8037f92:	b2db      	uxtb	r3, r3
+ 8037f94:	2b2a      	cmp	r3, #42	@ 0x2a
+ 8037f96:	d111      	bne.n	8037fbc <I2C_ITSlaveSeqCplt+0xb0>
+    hi2c->State         = HAL_I2C_STATE_LISTEN;
+ 8037f98:	687b      	ldr	r3, [r7, #4]
+ 8037f9a:	2228      	movs	r2, #40	@ 0x28
+ 8037f9c:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
+    hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+ 8037fa0:	687b      	ldr	r3, [r7, #4]
+ 8037fa2:	2222      	movs	r2, #34	@ 0x22
+ 8037fa4:	631a      	str	r2, [r3, #48]	@ 0x30
+    I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+ 8037fa6:	2102      	movs	r1, #2
+ 8037fa8:	6878      	ldr	r0, [r7, #4]
+ 8037faa:	f000 fc0c 	bl	80387c6 <I2C_Disable_IRQ>
+    __HAL_UNLOCK(hi2c);
+ 8037fae:	687b      	ldr	r3, [r7, #4]
+ 8037fb0:	2200      	movs	r2, #0
+ 8037fb2:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40
+    HAL_I2C_SlaveRxCpltCallback(hi2c);
+ 8037fb6:	6878      	ldr	r0, [r7, #4]
+ 8037fb8:	f7ff fdf5 	bl	8037ba6 <HAL_I2C_SlaveRxCpltCallback>
+}
+ 8037fbc:	bf00      	nop
+ 8037fbe:	3710      	adds	r7, #16
+ 8037fc0:	46bd      	mov	sp, r7
+ 8037fc2:	bd80      	pop	{r7, pc}
+
+08037fc4 <I2C_ITSlaveCplt>:
+  * @param  hi2c I2C handle.
+  * @param  ITFlags Interrupt flags to handle.
+  * @retval None
+  */
+static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
+{
+ 8037fc4:	b580      	push	{r7, lr}
+ 8037fc6:	b086      	sub	sp, #24
+ 8037fc8:	af00      	add	r7, sp, #0
+ 8037fca:	6078      	str	r0, [r7, #4]
+ 8037fcc:	6039      	str	r1, [r7, #0]
+  uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
+ 8037fce:	687b      	ldr	r3, [r7, #4]
+ 8037fd0:	681b      	ldr	r3, [r3, #0]
+ 8037fd2:	681b      	ldr	r3, [r3, #0]
+ 8037fd4:	613b      	str	r3, [r7, #16]
+  uint32_t tmpITFlags = ITFlags;
+ 8037fd6:	683b      	ldr	r3, [r7, #0]
+ 8037fd8:	617b      	str	r3, [r7, #20]
+  uint32_t tmpoptions = hi2c->XferOptions;
+ 8037fda:	687b      	ldr	r3, [r7, #4]
+ 8037fdc:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 8037fde:	60fb      	str	r3, [r7, #12]
+  HAL_I2C_StateTypeDef tmpstate = hi2c->State;
+ 8037fe0:	687b      	ldr	r3, [r7, #4]
+ 8037fe2:	f893 3041 	ldrb.w	r3, [r3, #65]	@ 0x41
+ 8037fe6:	72fb      	strb	r3, [r7, #11]
+
+  /* Clear STOP Flag */
+  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+ 8037fe8:	687b      	ldr	r3, [r7, #4]
+ 8037fea:	681b      	ldr	r3, [r3, #0]
+ 8037fec:	2220      	movs	r2, #32
+ 8037fee:	61da      	str	r2, [r3, #28]
+
+  /* Disable Interrupts and Store Previous state */
+  if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
+ 8037ff0:	7afb      	ldrb	r3, [r7, #11]
+ 8037ff2:	2b21      	cmp	r3, #33	@ 0x21
+ 8037ff4:	d002      	beq.n	8037ffc <I2C_ITSlaveCplt+0x38>
+ 8037ff6:	7afb      	ldrb	r3, [r7, #11]
+ 8037ff8:	2b29      	cmp	r3, #41	@ 0x29
+ 8037ffa:	d108      	bne.n	803800e <I2C_ITSlaveCplt+0x4a>
+  {
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
+ 8037ffc:	f248 0101 	movw	r1, #32769	@ 0x8001
+ 8038000:	6878      	ldr	r0, [r7, #4]
+ 8038002:	f000 fbe0 	bl	80387c6 <I2C_Disable_IRQ>
+    hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+ 8038006:	687b      	ldr	r3, [r7, #4]
+ 8038008:	2221      	movs	r2, #33	@ 0x21
+ 803800a:	631a      	str	r2, [r3, #48]	@ 0x30
+ 803800c:	e019      	b.n	8038042 <I2C_ITSlaveCplt+0x7e>
+  }
+  else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
+ 803800e:	7afb      	ldrb	r3, [r7, #11]
+ 8038010:	2b22      	cmp	r3, #34	@ 0x22
+ 8038012:	d002      	beq.n	803801a <I2C_ITSlaveCplt+0x56>
+ 8038014:	7afb      	ldrb	r3, [r7, #11]
+ 8038016:	2b2a      	cmp	r3, #42	@ 0x2a
+ 8038018:	d108      	bne.n	803802c <I2C_ITSlaveCplt+0x68>
+  {
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
+ 803801a:	f248 0102 	movw	r1, #32770	@ 0x8002
+ 803801e:	6878      	ldr	r0, [r7, #4]
+ 8038020:	f000 fbd1 	bl	80387c6 <I2C_Disable_IRQ>
+    hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+ 8038024:	687b      	ldr	r3, [r7, #4]
+ 8038026:	2222      	movs	r2, #34	@ 0x22
+ 8038028:	631a      	str	r2, [r3, #48]	@ 0x30
+ 803802a:	e00a      	b.n	8038042 <I2C_ITSlaveCplt+0x7e>
+  }
+  else if (tmpstate == HAL_I2C_STATE_LISTEN)
+ 803802c:	7afb      	ldrb	r3, [r7, #11]
+ 803802e:	2b28      	cmp	r3, #40	@ 0x28
+ 8038030:	d107      	bne.n	8038042 <I2C_ITSlaveCplt+0x7e>
+  {
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT);
+ 8038032:	f248 0103 	movw	r1, #32771	@ 0x8003
+ 8038036:	6878      	ldr	r0, [r7, #4]
+ 8038038:	f000 fbc5 	bl	80387c6 <I2C_Disable_IRQ>
+    hi2c->PreviousState = I2C_STATE_NONE;
+ 803803c:	687b      	ldr	r3, [r7, #4]
+ 803803e:	2200      	movs	r2, #0
+ 8038040:	631a      	str	r2, [r3, #48]	@ 0x30
+  {
+    /* Do nothing */
+  }
+
+  /* Disable Address Acknowledge */
+  hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ 8038042:	687b      	ldr	r3, [r7, #4]
+ 8038044:	681b      	ldr	r3, [r3, #0]
+ 8038046:	685a      	ldr	r2, [r3, #4]
+ 8038048:	687b      	ldr	r3, [r7, #4]
+ 803804a:	681b      	ldr	r3, [r3, #0]
+ 803804c:	f442 4200 	orr.w	r2, r2, #32768	@ 0x8000
+ 8038050:	605a      	str	r2, [r3, #4]
+
+  /* Clear Configuration Register 2 */
+  I2C_RESET_CR2(hi2c);
+ 8038052:	687b      	ldr	r3, [r7, #4]
+ 8038054:	681b      	ldr	r3, [r3, #0]
+ 8038056:	6859      	ldr	r1, [r3, #4]
+ 8038058:	687b      	ldr	r3, [r7, #4]
+ 803805a:	681a      	ldr	r2, [r3, #0]
+ 803805c:	4b7f      	ldr	r3, [pc, #508]	@ (803825c <I2C_ITSlaveCplt+0x298>)
+ 803805e:	400b      	ands	r3, r1
+ 8038060:	6053      	str	r3, [r2, #4]
+
+  /* Flush TX register */
+  I2C_Flush_TXDR(hi2c);
+ 8038062:	6878      	ldr	r0, [r7, #4]
+ 8038064:	f000 fb6d 	bl	8038742 <I2C_Flush_TXDR>
+
+  /* If a DMA is ongoing, Update handle size context */
+  if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
+ 8038068:	693b      	ldr	r3, [r7, #16]
+ 803806a:	f403 4380 	and.w	r3, r3, #16384	@ 0x4000
+ 803806e:	2b00      	cmp	r3, #0
+ 8038070:	d07a      	beq.n	8038168 <I2C_ITSlaveCplt+0x1a4>
+  {
+    /* Disable DMA Request */
+    hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+ 8038072:	687b      	ldr	r3, [r7, #4]
+ 8038074:	681b      	ldr	r3, [r3, #0]
+ 8038076:	681a      	ldr	r2, [r3, #0]
+ 8038078:	687b      	ldr	r3, [r7, #4]
+ 803807a:	681b      	ldr	r3, [r3, #0]
+ 803807c:	f422 4280 	bic.w	r2, r2, #16384	@ 0x4000
+ 8038080:	601a      	str	r2, [r3, #0]
+
+    if (hi2c->hdmatx != NULL)
+ 8038082:	687b      	ldr	r3, [r7, #4]
+ 8038084:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
+ 8038086:	2b00      	cmp	r3, #0
+ 8038088:	f000 8111 	beq.w	80382ae <I2C_ITSlaveCplt+0x2ea>
+    {
+      hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx);
+ 803808c:	687b      	ldr	r3, [r7, #4]
+ 803808e:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
+ 8038090:	681b      	ldr	r3, [r3, #0]
+ 8038092:	4a73      	ldr	r2, [pc, #460]	@ (8038260 <I2C_ITSlaveCplt+0x29c>)
+ 8038094:	4293      	cmp	r3, r2
+ 8038096:	d059      	beq.n	803814c <I2C_ITSlaveCplt+0x188>
+ 8038098:	687b      	ldr	r3, [r7, #4]
+ 803809a:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
+ 803809c:	681b      	ldr	r3, [r3, #0]
+ 803809e:	4a71      	ldr	r2, [pc, #452]	@ (8038264 <I2C_ITSlaveCplt+0x2a0>)
+ 80380a0:	4293      	cmp	r3, r2
+ 80380a2:	d053      	beq.n	803814c <I2C_ITSlaveCplt+0x188>
+ 80380a4:	687b      	ldr	r3, [r7, #4]
+ 80380a6:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
+ 80380a8:	681b      	ldr	r3, [r3, #0]
+ 80380aa:	4a6f      	ldr	r2, [pc, #444]	@ (8038268 <I2C_ITSlaveCplt+0x2a4>)
+ 80380ac:	4293      	cmp	r3, r2
+ 80380ae:	d04d      	beq.n	803814c <I2C_ITSlaveCplt+0x188>
+ 80380b0:	687b      	ldr	r3, [r7, #4]
+ 80380b2:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
+ 80380b4:	681b      	ldr	r3, [r3, #0]
+ 80380b6:	4a6d      	ldr	r2, [pc, #436]	@ (803826c <I2C_ITSlaveCplt+0x2a8>)
+ 80380b8:	4293      	cmp	r3, r2
+ 80380ba:	d047      	beq.n	803814c <I2C_ITSlaveCplt+0x188>
+ 80380bc:	687b      	ldr	r3, [r7, #4]
+ 80380be:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
+ 80380c0:	681b      	ldr	r3, [r3, #0]
+ 80380c2:	4a6b      	ldr	r2, [pc, #428]	@ (8038270 <I2C_ITSlaveCplt+0x2ac>)
+ 80380c4:	4293      	cmp	r3, r2
+ 80380c6:	d041      	beq.n	803814c <I2C_ITSlaveCplt+0x188>
+ 80380c8:	687b      	ldr	r3, [r7, #4]
+ 80380ca:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
+ 80380cc:	681b      	ldr	r3, [r3, #0]
+ 80380ce:	4a69      	ldr	r2, [pc, #420]	@ (8038274 <I2C_ITSlaveCplt+0x2b0>)
+ 80380d0:	4293      	cmp	r3, r2
+ 80380d2:	d03b      	beq.n	803814c <I2C_ITSlaveCplt+0x188>
+ 80380d4:	687b      	ldr	r3, [r7, #4]
+ 80380d6:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
+ 80380d8:	681b      	ldr	r3, [r3, #0]
+ 80380da:	4a67      	ldr	r2, [pc, #412]	@ (8038278 <I2C_ITSlaveCplt+0x2b4>)
+ 80380dc:	4293      	cmp	r3, r2
+ 80380de:	d035      	beq.n	803814c <I2C_ITSlaveCplt+0x188>
+ 80380e0:	687b      	ldr	r3, [r7, #4]
+ 80380e2:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
+ 80380e4:	681b      	ldr	r3, [r3, #0]
+ 80380e6:	4a65      	ldr	r2, [pc, #404]	@ (803827c <I2C_ITSlaveCplt+0x2b8>)
+ 80380e8:	4293      	cmp	r3, r2
+ 80380ea:	d02f      	beq.n	803814c <I2C_ITSlaveCplt+0x188>
+ 80380ec:	687b      	ldr	r3, [r7, #4]
+ 80380ee:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
+ 80380f0:	681b      	ldr	r3, [r3, #0]
+ 80380f2:	4a63      	ldr	r2, [pc, #396]	@ (8038280 <I2C_ITSlaveCplt+0x2bc>)
+ 80380f4:	4293      	cmp	r3, r2
+ 80380f6:	d029      	beq.n	803814c <I2C_ITSlaveCplt+0x188>
+ 80380f8:	687b      	ldr	r3, [r7, #4]
+ 80380fa:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
+ 80380fc:	681b      	ldr	r3, [r3, #0]
+ 80380fe:	4a61      	ldr	r2, [pc, #388]	@ (8038284 <I2C_ITSlaveCplt+0x2c0>)
+ 8038100:	4293      	cmp	r3, r2
+ 8038102:	d023      	beq.n	803814c <I2C_ITSlaveCplt+0x188>
+ 8038104:	687b      	ldr	r3, [r7, #4]
+ 8038106:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
+ 8038108:	681b      	ldr	r3, [r3, #0]
+ 803810a:	4a5f      	ldr	r2, [pc, #380]	@ (8038288 <I2C_ITSlaveCplt+0x2c4>)
+ 803810c:	4293      	cmp	r3, r2
+ 803810e:	d01d      	beq.n	803814c <I2C_ITSlaveCplt+0x188>
+ 8038110:	687b      	ldr	r3, [r7, #4]
+ 8038112:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
+ 8038114:	681b      	ldr	r3, [r3, #0]
+ 8038116:	4a5d      	ldr	r2, [pc, #372]	@ (803828c <I2C_ITSlaveCplt+0x2c8>)
+ 8038118:	4293      	cmp	r3, r2
+ 803811a:	d017      	beq.n	803814c <I2C_ITSlaveCplt+0x188>
+ 803811c:	687b      	ldr	r3, [r7, #4]
+ 803811e:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
+ 8038120:	681b      	ldr	r3, [r3, #0]
+ 8038122:	4a5b      	ldr	r2, [pc, #364]	@ (8038290 <I2C_ITSlaveCplt+0x2cc>)
+ 8038124:	4293      	cmp	r3, r2
+ 8038126:	d011      	beq.n	803814c <I2C_ITSlaveCplt+0x188>
+ 8038128:	687b      	ldr	r3, [r7, #4]
+ 803812a:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
+ 803812c:	681b      	ldr	r3, [r3, #0]
+ 803812e:	4a59      	ldr	r2, [pc, #356]	@ (8038294 <I2C_ITSlaveCplt+0x2d0>)
+ 8038130:	4293      	cmp	r3, r2
+ 8038132:	d00b      	beq.n	803814c <I2C_ITSlaveCplt+0x188>
+ 8038134:	687b      	ldr	r3, [r7, #4]
+ 8038136:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
+ 8038138:	681b      	ldr	r3, [r3, #0]
+ 803813a:	4a57      	ldr	r2, [pc, #348]	@ (8038298 <I2C_ITSlaveCplt+0x2d4>)
+ 803813c:	4293      	cmp	r3, r2
+ 803813e:	d005      	beq.n	803814c <I2C_ITSlaveCplt+0x188>
+ 8038140:	687b      	ldr	r3, [r7, #4]
+ 8038142:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
+ 8038144:	681b      	ldr	r3, [r3, #0]
+ 8038146:	4a55      	ldr	r2, [pc, #340]	@ (803829c <I2C_ITSlaveCplt+0x2d8>)
+ 8038148:	4293      	cmp	r3, r2
+ 803814a:	d105      	bne.n	8038158 <I2C_ITSlaveCplt+0x194>
+ 803814c:	687b      	ldr	r3, [r7, #4]
+ 803814e:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
+ 8038150:	681b      	ldr	r3, [r3, #0]
+ 8038152:	685b      	ldr	r3, [r3, #4]
+ 8038154:	b29b      	uxth	r3, r3
+ 8038156:	e004      	b.n	8038162 <I2C_ITSlaveCplt+0x19e>
+ 8038158:	687b      	ldr	r3, [r7, #4]
+ 803815a:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
+ 803815c:	681b      	ldr	r3, [r3, #0]
+ 803815e:	685b      	ldr	r3, [r3, #4]
+ 8038160:	b29b      	uxth	r3, r3
+ 8038162:	687a      	ldr	r2, [r7, #4]
+ 8038164:	8553      	strh	r3, [r2, #42]	@ 0x2a
+ 8038166:	e0a2      	b.n	80382ae <I2C_ITSlaveCplt+0x2ea>
+    }
+  }
+  else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
+ 8038168:	693b      	ldr	r3, [r7, #16]
+ 803816a:	f403 4300 	and.w	r3, r3, #32768	@ 0x8000
+ 803816e:	2b00      	cmp	r3, #0
+ 8038170:	f000 809d 	beq.w	80382ae <I2C_ITSlaveCplt+0x2ea>
+  {
+    /* Disable DMA Request */
+    hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+ 8038174:	687b      	ldr	r3, [r7, #4]
+ 8038176:	681b      	ldr	r3, [r3, #0]
+ 8038178:	681a      	ldr	r2, [r3, #0]
+ 803817a:	687b      	ldr	r3, [r7, #4]
+ 803817c:	681b      	ldr	r3, [r3, #0]
+ 803817e:	f422 4200 	bic.w	r2, r2, #32768	@ 0x8000
+ 8038182:	601a      	str	r2, [r3, #0]
+
+    if (hi2c->hdmarx != NULL)
+ 8038184:	687b      	ldr	r3, [r7, #4]
+ 8038186:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 8038188:	2b00      	cmp	r3, #0
+ 803818a:	f000 8090 	beq.w	80382ae <I2C_ITSlaveCplt+0x2ea>
+    {
+      hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx);
+ 803818e:	687b      	ldr	r3, [r7, #4]
+ 8038190:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 8038192:	681b      	ldr	r3, [r3, #0]
+ 8038194:	4a32      	ldr	r2, [pc, #200]	@ (8038260 <I2C_ITSlaveCplt+0x29c>)
+ 8038196:	4293      	cmp	r3, r2
+ 8038198:	d059      	beq.n	803824e <I2C_ITSlaveCplt+0x28a>
+ 803819a:	687b      	ldr	r3, [r7, #4]
+ 803819c:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 803819e:	681b      	ldr	r3, [r3, #0]
+ 80381a0:	4a30      	ldr	r2, [pc, #192]	@ (8038264 <I2C_ITSlaveCplt+0x2a0>)
+ 80381a2:	4293      	cmp	r3, r2
+ 80381a4:	d053      	beq.n	803824e <I2C_ITSlaveCplt+0x28a>
+ 80381a6:	687b      	ldr	r3, [r7, #4]
+ 80381a8:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 80381aa:	681b      	ldr	r3, [r3, #0]
+ 80381ac:	4a2e      	ldr	r2, [pc, #184]	@ (8038268 <I2C_ITSlaveCplt+0x2a4>)
+ 80381ae:	4293      	cmp	r3, r2
+ 80381b0:	d04d      	beq.n	803824e <I2C_ITSlaveCplt+0x28a>
+ 80381b2:	687b      	ldr	r3, [r7, #4]
+ 80381b4:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 80381b6:	681b      	ldr	r3, [r3, #0]
+ 80381b8:	4a2c      	ldr	r2, [pc, #176]	@ (803826c <I2C_ITSlaveCplt+0x2a8>)
+ 80381ba:	4293      	cmp	r3, r2
+ 80381bc:	d047      	beq.n	803824e <I2C_ITSlaveCplt+0x28a>
+ 80381be:	687b      	ldr	r3, [r7, #4]
+ 80381c0:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 80381c2:	681b      	ldr	r3, [r3, #0]
+ 80381c4:	4a2a      	ldr	r2, [pc, #168]	@ (8038270 <I2C_ITSlaveCplt+0x2ac>)
+ 80381c6:	4293      	cmp	r3, r2
+ 80381c8:	d041      	beq.n	803824e <I2C_ITSlaveCplt+0x28a>
+ 80381ca:	687b      	ldr	r3, [r7, #4]
+ 80381cc:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 80381ce:	681b      	ldr	r3, [r3, #0]
+ 80381d0:	4a28      	ldr	r2, [pc, #160]	@ (8038274 <I2C_ITSlaveCplt+0x2b0>)
+ 80381d2:	4293      	cmp	r3, r2
+ 80381d4:	d03b      	beq.n	803824e <I2C_ITSlaveCplt+0x28a>
+ 80381d6:	687b      	ldr	r3, [r7, #4]
+ 80381d8:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 80381da:	681b      	ldr	r3, [r3, #0]
+ 80381dc:	4a26      	ldr	r2, [pc, #152]	@ (8038278 <I2C_ITSlaveCplt+0x2b4>)
+ 80381de:	4293      	cmp	r3, r2
+ 80381e0:	d035      	beq.n	803824e <I2C_ITSlaveCplt+0x28a>
+ 80381e2:	687b      	ldr	r3, [r7, #4]
+ 80381e4:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 80381e6:	681b      	ldr	r3, [r3, #0]
+ 80381e8:	4a24      	ldr	r2, [pc, #144]	@ (803827c <I2C_ITSlaveCplt+0x2b8>)
+ 80381ea:	4293      	cmp	r3, r2
+ 80381ec:	d02f      	beq.n	803824e <I2C_ITSlaveCplt+0x28a>
+ 80381ee:	687b      	ldr	r3, [r7, #4]
+ 80381f0:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 80381f2:	681b      	ldr	r3, [r3, #0]
+ 80381f4:	4a22      	ldr	r2, [pc, #136]	@ (8038280 <I2C_ITSlaveCplt+0x2bc>)
+ 80381f6:	4293      	cmp	r3, r2
+ 80381f8:	d029      	beq.n	803824e <I2C_ITSlaveCplt+0x28a>
+ 80381fa:	687b      	ldr	r3, [r7, #4]
+ 80381fc:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 80381fe:	681b      	ldr	r3, [r3, #0]
+ 8038200:	4a20      	ldr	r2, [pc, #128]	@ (8038284 <I2C_ITSlaveCplt+0x2c0>)
+ 8038202:	4293      	cmp	r3, r2
+ 8038204:	d023      	beq.n	803824e <I2C_ITSlaveCplt+0x28a>
+ 8038206:	687b      	ldr	r3, [r7, #4]
+ 8038208:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 803820a:	681b      	ldr	r3, [r3, #0]
+ 803820c:	4a1e      	ldr	r2, [pc, #120]	@ (8038288 <I2C_ITSlaveCplt+0x2c4>)
+ 803820e:	4293      	cmp	r3, r2
+ 8038210:	d01d      	beq.n	803824e <I2C_ITSlaveCplt+0x28a>
+ 8038212:	687b      	ldr	r3, [r7, #4]
+ 8038214:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 8038216:	681b      	ldr	r3, [r3, #0]
+ 8038218:	4a1c      	ldr	r2, [pc, #112]	@ (803828c <I2C_ITSlaveCplt+0x2c8>)
+ 803821a:	4293      	cmp	r3, r2
+ 803821c:	d017      	beq.n	803824e <I2C_ITSlaveCplt+0x28a>
+ 803821e:	687b      	ldr	r3, [r7, #4]
+ 8038220:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 8038222:	681b      	ldr	r3, [r3, #0]
+ 8038224:	4a1a      	ldr	r2, [pc, #104]	@ (8038290 <I2C_ITSlaveCplt+0x2cc>)
+ 8038226:	4293      	cmp	r3, r2
+ 8038228:	d011      	beq.n	803824e <I2C_ITSlaveCplt+0x28a>
+ 803822a:	687b      	ldr	r3, [r7, #4]
+ 803822c:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 803822e:	681b      	ldr	r3, [r3, #0]
+ 8038230:	4a18      	ldr	r2, [pc, #96]	@ (8038294 <I2C_ITSlaveCplt+0x2d0>)
+ 8038232:	4293      	cmp	r3, r2
+ 8038234:	d00b      	beq.n	803824e <I2C_ITSlaveCplt+0x28a>
+ 8038236:	687b      	ldr	r3, [r7, #4]
+ 8038238:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 803823a:	681b      	ldr	r3, [r3, #0]
+ 803823c:	4a16      	ldr	r2, [pc, #88]	@ (8038298 <I2C_ITSlaveCplt+0x2d4>)
+ 803823e:	4293      	cmp	r3, r2
+ 8038240:	d005      	beq.n	803824e <I2C_ITSlaveCplt+0x28a>
+ 8038242:	687b      	ldr	r3, [r7, #4]
+ 8038244:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 8038246:	681b      	ldr	r3, [r3, #0]
+ 8038248:	4a14      	ldr	r2, [pc, #80]	@ (803829c <I2C_ITSlaveCplt+0x2d8>)
+ 803824a:	4293      	cmp	r3, r2
+ 803824c:	d128      	bne.n	80382a0 <I2C_ITSlaveCplt+0x2dc>
+ 803824e:	687b      	ldr	r3, [r7, #4]
+ 8038250:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 8038252:	681b      	ldr	r3, [r3, #0]
+ 8038254:	685b      	ldr	r3, [r3, #4]
+ 8038256:	b29b      	uxth	r3, r3
+ 8038258:	e027      	b.n	80382aa <I2C_ITSlaveCplt+0x2e6>
+ 803825a:	bf00      	nop
+ 803825c:	fe00e800 	.word	0xfe00e800
+ 8038260:	40020010 	.word	0x40020010
+ 8038264:	40020028 	.word	0x40020028
+ 8038268:	40020040 	.word	0x40020040
+ 803826c:	40020058 	.word	0x40020058
+ 8038270:	40020070 	.word	0x40020070
+ 8038274:	40020088 	.word	0x40020088
+ 8038278:	400200a0 	.word	0x400200a0
+ 803827c:	400200b8 	.word	0x400200b8
+ 8038280:	40020410 	.word	0x40020410
+ 8038284:	40020428 	.word	0x40020428
+ 8038288:	40020440 	.word	0x40020440
+ 803828c:	40020458 	.word	0x40020458
+ 8038290:	40020470 	.word	0x40020470
+ 8038294:	40020488 	.word	0x40020488
+ 8038298:	400204a0 	.word	0x400204a0
+ 803829c:	400204b8 	.word	0x400204b8
+ 80382a0:	687b      	ldr	r3, [r7, #4]
+ 80382a2:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 80382a4:	681b      	ldr	r3, [r3, #0]
+ 80382a6:	685b      	ldr	r3, [r3, #4]
+ 80382a8:	b29b      	uxth	r3, r3
+ 80382aa:	687a      	ldr	r2, [r7, #4]
+ 80382ac:	8553      	strh	r3, [r2, #42]	@ 0x2a
+  {
+    /* Do nothing */
+  }
+
+  /* Store Last receive data if any */
+  if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)
+ 80382ae:	697b      	ldr	r3, [r7, #20]
+ 80382b0:	f003 0304 	and.w	r3, r3, #4
+ 80382b4:	2b00      	cmp	r3, #0
+ 80382b6:	d020      	beq.n	80382fa <I2C_ITSlaveCplt+0x336>
+  {
+    /* Remove RXNE flag on temporary variable as read done */
+    tmpITFlags &= ~I2C_FLAG_RXNE;
+ 80382b8:	697b      	ldr	r3, [r7, #20]
+ 80382ba:	f023 0304 	bic.w	r3, r3, #4
+ 80382be:	617b      	str	r3, [r7, #20]
+
+    /* Read data from RXDR */
+    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+ 80382c0:	687b      	ldr	r3, [r7, #4]
+ 80382c2:	681b      	ldr	r3, [r3, #0]
+ 80382c4:	6a5a      	ldr	r2, [r3, #36]	@ 0x24
+ 80382c6:	687b      	ldr	r3, [r7, #4]
+ 80382c8:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 80382ca:	b2d2      	uxtb	r2, r2
+ 80382cc:	701a      	strb	r2, [r3, #0]
+
+    /* Increment Buffer pointer */
+    hi2c->pBuffPtr++;
+ 80382ce:	687b      	ldr	r3, [r7, #4]
+ 80382d0:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 80382d2:	1c5a      	adds	r2, r3, #1
+ 80382d4:	687b      	ldr	r3, [r7, #4]
+ 80382d6:	625a      	str	r2, [r3, #36]	@ 0x24
+
+    if ((hi2c->XferSize > 0U))
+ 80382d8:	687b      	ldr	r3, [r7, #4]
+ 80382da:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
+ 80382dc:	2b00      	cmp	r3, #0
+ 80382de:	d00c      	beq.n	80382fa <I2C_ITSlaveCplt+0x336>
+    {
+      hi2c->XferSize--;
+ 80382e0:	687b      	ldr	r3, [r7, #4]
+ 80382e2:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
+ 80382e4:	3b01      	subs	r3, #1
+ 80382e6:	b29a      	uxth	r2, r3
+ 80382e8:	687b      	ldr	r3, [r7, #4]
+ 80382ea:	851a      	strh	r2, [r3, #40]	@ 0x28
+      hi2c->XferCount--;
+ 80382ec:	687b      	ldr	r3, [r7, #4]
+ 80382ee:	8d5b      	ldrh	r3, [r3, #42]	@ 0x2a
+ 80382f0:	b29b      	uxth	r3, r3
+ 80382f2:	3b01      	subs	r3, #1
+ 80382f4:	b29a      	uxth	r2, r3
+ 80382f6:	687b      	ldr	r3, [r7, #4]
+ 80382f8:	855a      	strh	r2, [r3, #42]	@ 0x2a
+    }
+  }
+
+  /* All data are not transferred, so set error code accordingly */
+  if (hi2c->XferCount != 0U)
+ 80382fa:	687b      	ldr	r3, [r7, #4]
+ 80382fc:	8d5b      	ldrh	r3, [r3, #42]	@ 0x2a
+ 80382fe:	b29b      	uxth	r3, r3
+ 8038300:	2b00      	cmp	r3, #0
+ 8038302:	d005      	beq.n	8038310 <I2C_ITSlaveCplt+0x34c>
+  {
+    /* Set ErrorCode corresponding to a Non-Acknowledge */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ 8038304:	687b      	ldr	r3, [r7, #4]
+ 8038306:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
+ 8038308:	f043 0204 	orr.w	r2, r3, #4
+ 803830c:	687b      	ldr	r3, [r7, #4]
+ 803830e:	645a      	str	r2, [r3, #68]	@ 0x44
+  }
+
+  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
+ 8038310:	697b      	ldr	r3, [r7, #20]
+ 8038312:	f003 0310 	and.w	r3, r3, #16
+ 8038316:	2b00      	cmp	r3, #0
+ 8038318:	d049      	beq.n	80383ae <I2C_ITSlaveCplt+0x3ea>
+      (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_IT_NACKI) != RESET))
+ 803831a:	693b      	ldr	r3, [r7, #16]
+ 803831c:	f003 0310 	and.w	r3, r3, #16
+  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
+ 8038320:	2b00      	cmp	r3, #0
+ 8038322:	d044      	beq.n	80383ae <I2C_ITSlaveCplt+0x3ea>
+  {
+    /* Check that I2C transfer finished */
+    /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
+    /* Mean XferCount == 0*/
+    /* So clear Flag NACKF only */
+    if (hi2c->XferCount == 0U)
+ 8038324:	687b      	ldr	r3, [r7, #4]
+ 8038326:	8d5b      	ldrh	r3, [r3, #42]	@ 0x2a
+ 8038328:	b29b      	uxth	r3, r3
+ 803832a:	2b00      	cmp	r3, #0
+ 803832c:	d128      	bne.n	8038380 <I2C_ITSlaveCplt+0x3bc>
+    {
+      if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
+ 803832e:	687b      	ldr	r3, [r7, #4]
+ 8038330:	f893 3041 	ldrb.w	r3, [r3, #65]	@ 0x41
+ 8038334:	b2db      	uxtb	r3, r3
+ 8038336:	2b28      	cmp	r3, #40	@ 0x28
+ 8038338:	d108      	bne.n	803834c <I2C_ITSlaveCplt+0x388>
+ 803833a:	68fb      	ldr	r3, [r7, #12]
+ 803833c:	f1b3 7f00 	cmp.w	r3, #33554432	@ 0x2000000
+ 8038340:	d104      	bne.n	803834c <I2C_ITSlaveCplt+0x388>
+        /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
+           Warning[Pa134]: left and right operands are identical */
+      {
+        /* Call I2C Listen complete process */
+        I2C_ITListenCplt(hi2c, tmpITFlags);
+ 8038342:	6979      	ldr	r1, [r7, #20]
+ 8038344:	6878      	ldr	r0, [r7, #4]
+ 8038346:	f000 f891 	bl	803846c <I2C_ITListenCplt>
+ 803834a:	e030      	b.n	80383ae <I2C_ITSlaveCplt+0x3ea>
+      }
+      else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
+ 803834c:	687b      	ldr	r3, [r7, #4]
+ 803834e:	f893 3041 	ldrb.w	r3, [r3, #65]	@ 0x41
+ 8038352:	b2db      	uxtb	r3, r3
+ 8038354:	2b29      	cmp	r3, #41	@ 0x29
+ 8038356:	d10e      	bne.n	8038376 <I2C_ITSlaveCplt+0x3b2>
+ 8038358:	68fb      	ldr	r3, [r7, #12]
+ 803835a:	f513 3f80 	cmn.w	r3, #65536	@ 0x10000
+ 803835e:	d00a      	beq.n	8038376 <I2C_ITSlaveCplt+0x3b2>
+      {
+        /* Clear NACK Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+ 8038360:	687b      	ldr	r3, [r7, #4]
+ 8038362:	681b      	ldr	r3, [r3, #0]
+ 8038364:	2210      	movs	r2, #16
+ 8038366:	61da      	str	r2, [r3, #28]
+
+        /* Flush TX register */
+        I2C_Flush_TXDR(hi2c);
+ 8038368:	6878      	ldr	r0, [r7, #4]
+ 803836a:	f000 f9ea 	bl	8038742 <I2C_Flush_TXDR>
+
+        /* Last Byte is Transmitted */
+        /* Call I2C Slave Sequential complete process */
+        I2C_ITSlaveSeqCplt(hi2c);
+ 803836e:	6878      	ldr	r0, [r7, #4]
+ 8038370:	f7ff fdcc 	bl	8037f0c <I2C_ITSlaveSeqCplt>
+ 8038374:	e01b      	b.n	80383ae <I2C_ITSlaveCplt+0x3ea>
+      }
+      else
+      {
+        /* Clear NACK Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+ 8038376:	687b      	ldr	r3, [r7, #4]
+ 8038378:	681b      	ldr	r3, [r3, #0]
+ 803837a:	2210      	movs	r2, #16
+ 803837c:	61da      	str	r2, [r3, #28]
+ 803837e:	e016      	b.n	80383ae <I2C_ITSlaveCplt+0x3ea>
+    }
+    else
+    {
+      /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
+      /* Clear NACK Flag */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+ 8038380:	687b      	ldr	r3, [r7, #4]
+ 8038382:	681b      	ldr	r3, [r3, #0]
+ 8038384:	2210      	movs	r2, #16
+ 8038386:	61da      	str	r2, [r3, #28]
+
+      /* Set ErrorCode corresponding to a Non-Acknowledge */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ 8038388:	687b      	ldr	r3, [r7, #4]
+ 803838a:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
+ 803838c:	f043 0204 	orr.w	r2, r3, #4
+ 8038390:	687b      	ldr	r3, [r7, #4]
+ 8038392:	645a      	str	r2, [r3, #68]	@ 0x44
+
+      if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
+ 8038394:	68fb      	ldr	r3, [r7, #12]
+ 8038396:	2b00      	cmp	r3, #0
+ 8038398:	d003      	beq.n	80383a2 <I2C_ITSlaveCplt+0x3de>
+ 803839a:	68fb      	ldr	r3, [r7, #12]
+ 803839c:	f1b3 7f80 	cmp.w	r3, #16777216	@ 0x1000000
+ 80383a0:	d105      	bne.n	80383ae <I2C_ITSlaveCplt+0x3ea>
+      {
+        /* Call the corresponding callback to inform upper layer of End of Transfer */
+        I2C_ITError(hi2c, hi2c->ErrorCode);
+ 80383a2:	687b      	ldr	r3, [r7, #4]
+ 80383a4:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
+ 80383a6:	4619      	mov	r1, r3
+ 80383a8:	6878      	ldr	r0, [r7, #4]
+ 80383aa:	f000 f8b3 	bl	8038514 <I2C_ITError>
+      }
+    }
+  }
+
+  hi2c->Mode = HAL_I2C_MODE_NONE;
+ 80383ae:	687b      	ldr	r3, [r7, #4]
+ 80383b0:	2200      	movs	r2, #0
+ 80383b2:	f883 2042 	strb.w	r2, [r3, #66]	@ 0x42
+  hi2c->XferISR = NULL;
+ 80383b6:	687b      	ldr	r3, [r7, #4]
+ 80383b8:	2200      	movs	r2, #0
+ 80383ba:	635a      	str	r2, [r3, #52]	@ 0x34
+
+  if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+ 80383bc:	687b      	ldr	r3, [r7, #4]
+ 80383be:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
+ 80383c0:	2b00      	cmp	r3, #0
+ 80383c2:	d010      	beq.n	80383e6 <I2C_ITSlaveCplt+0x422>
+  {
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+    I2C_ITError(hi2c, hi2c->ErrorCode);
+ 80383c4:	687b      	ldr	r3, [r7, #4]
+ 80383c6:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
+ 80383c8:	4619      	mov	r1, r3
+ 80383ca:	6878      	ldr	r0, [r7, #4]
+ 80383cc:	f000 f8a2 	bl	8038514 <I2C_ITError>
+
+    /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+    if (hi2c->State == HAL_I2C_STATE_LISTEN)
+ 80383d0:	687b      	ldr	r3, [r7, #4]
+ 80383d2:	f893 3041 	ldrb.w	r3, [r3, #65]	@ 0x41
+ 80383d6:	b2db      	uxtb	r3, r3
+ 80383d8:	2b28      	cmp	r3, #40	@ 0x28
+ 80383da:	d141      	bne.n	8038460 <I2C_ITSlaveCplt+0x49c>
+    {
+      /* Call I2C Listen complete process */
+      I2C_ITListenCplt(hi2c, tmpITFlags);
+ 80383dc:	6979      	ldr	r1, [r7, #20]
+ 80383de:	6878      	ldr	r0, [r7, #4]
+ 80383e0:	f000 f844 	bl	803846c <I2C_ITListenCplt>
+    hi2c->SlaveTxCpltCallback(hi2c);
+#else
+    HAL_I2C_SlaveTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+}
+ 80383e4:	e03c      	b.n	8038460 <I2C_ITSlaveCplt+0x49c>
+  else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+ 80383e6:	687b      	ldr	r3, [r7, #4]
+ 80383e8:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 80383ea:	f513 3f80 	cmn.w	r3, #65536	@ 0x10000
+ 80383ee:	d014      	beq.n	803841a <I2C_ITSlaveCplt+0x456>
+    I2C_ITSlaveSeqCplt(hi2c);
+ 80383f0:	6878      	ldr	r0, [r7, #4]
+ 80383f2:	f7ff fd8b 	bl	8037f0c <I2C_ITSlaveSeqCplt>
+    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ 80383f6:	687b      	ldr	r3, [r7, #4]
+ 80383f8:	4a1b      	ldr	r2, [pc, #108]	@ (8038468 <I2C_ITSlaveCplt+0x4a4>)
+ 80383fa:	62da      	str	r2, [r3, #44]	@ 0x2c
+    hi2c->State = HAL_I2C_STATE_READY;
+ 80383fc:	687b      	ldr	r3, [r7, #4]
+ 80383fe:	2220      	movs	r2, #32
+ 8038400:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
+    hi2c->PreviousState = I2C_STATE_NONE;
+ 8038404:	687b      	ldr	r3, [r7, #4]
+ 8038406:	2200      	movs	r2, #0
+ 8038408:	631a      	str	r2, [r3, #48]	@ 0x30
+    __HAL_UNLOCK(hi2c);
+ 803840a:	687b      	ldr	r3, [r7, #4]
+ 803840c:	2200      	movs	r2, #0
+ 803840e:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40
+    HAL_I2C_ListenCpltCallback(hi2c);
+ 8038412:	6878      	ldr	r0, [r7, #4]
+ 8038414:	f7ff fbdf 	bl	8037bd6 <HAL_I2C_ListenCpltCallback>
+}
+ 8038418:	e022      	b.n	8038460 <I2C_ITSlaveCplt+0x49c>
+  else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+ 803841a:	687b      	ldr	r3, [r7, #4]
+ 803841c:	f893 3041 	ldrb.w	r3, [r3, #65]	@ 0x41
+ 8038420:	b2db      	uxtb	r3, r3
+ 8038422:	2b22      	cmp	r3, #34	@ 0x22
+ 8038424:	d10e      	bne.n	8038444 <I2C_ITSlaveCplt+0x480>
+    hi2c->State = HAL_I2C_STATE_READY;
+ 8038426:	687b      	ldr	r3, [r7, #4]
+ 8038428:	2220      	movs	r2, #32
+ 803842a:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
+    hi2c->PreviousState = I2C_STATE_NONE;
+ 803842e:	687b      	ldr	r3, [r7, #4]
+ 8038430:	2200      	movs	r2, #0
+ 8038432:	631a      	str	r2, [r3, #48]	@ 0x30
+    __HAL_UNLOCK(hi2c);
+ 8038434:	687b      	ldr	r3, [r7, #4]
+ 8038436:	2200      	movs	r2, #0
+ 8038438:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40
+    HAL_I2C_SlaveRxCpltCallback(hi2c);
+ 803843c:	6878      	ldr	r0, [r7, #4]
+ 803843e:	f7ff fbb2 	bl	8037ba6 <HAL_I2C_SlaveRxCpltCallback>
+}
+ 8038442:	e00d      	b.n	8038460 <I2C_ITSlaveCplt+0x49c>
+    hi2c->State = HAL_I2C_STATE_READY;
+ 8038444:	687b      	ldr	r3, [r7, #4]
+ 8038446:	2220      	movs	r2, #32
+ 8038448:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
+    hi2c->PreviousState = I2C_STATE_NONE;
+ 803844c:	687b      	ldr	r3, [r7, #4]
+ 803844e:	2200      	movs	r2, #0
+ 8038450:	631a      	str	r2, [r3, #48]	@ 0x30
+    __HAL_UNLOCK(hi2c);
+ 8038452:	687b      	ldr	r3, [r7, #4]
+ 8038454:	2200      	movs	r2, #0
+ 8038456:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40
+    HAL_I2C_SlaveTxCpltCallback(hi2c);
+ 803845a:	6878      	ldr	r0, [r7, #4]
+ 803845c:	f7ff fb99 	bl	8037b92 <HAL_I2C_SlaveTxCpltCallback>
+}
+ 8038460:	bf00      	nop
+ 8038462:	3718      	adds	r7, #24
+ 8038464:	46bd      	mov	sp, r7
+ 8038466:	bd80      	pop	{r7, pc}
+ 8038468:	ffff0000 	.word	0xffff0000
+
+0803846c <I2C_ITListenCplt>:
+  * @param  hi2c I2C handle.
+  * @param  ITFlags Interrupt flags to handle.
+  * @retval None
+  */
+static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
+{
+ 803846c:	b580      	push	{r7, lr}
+ 803846e:	b082      	sub	sp, #8
+ 8038470:	af00      	add	r7, sp, #0
+ 8038472:	6078      	str	r0, [r7, #4]
+ 8038474:	6039      	str	r1, [r7, #0]
+  /* Reset handle parameters */
+  hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ 8038476:	687b      	ldr	r3, [r7, #4]
+ 8038478:	4a25      	ldr	r2, [pc, #148]	@ (8038510 <I2C_ITListenCplt+0xa4>)
+ 803847a:	62da      	str	r2, [r3, #44]	@ 0x2c
+  hi2c->PreviousState = I2C_STATE_NONE;
+ 803847c:	687b      	ldr	r3, [r7, #4]
+ 803847e:	2200      	movs	r2, #0
+ 8038480:	631a      	str	r2, [r3, #48]	@ 0x30
+  hi2c->State = HAL_I2C_STATE_READY;
+ 8038482:	687b      	ldr	r3, [r7, #4]
+ 8038484:	2220      	movs	r2, #32
+ 8038486:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
+  hi2c->Mode = HAL_I2C_MODE_NONE;
+ 803848a:	687b      	ldr	r3, [r7, #4]
+ 803848c:	2200      	movs	r2, #0
+ 803848e:	f883 2042 	strb.w	r2, [r3, #66]	@ 0x42
+  hi2c->XferISR = NULL;
+ 8038492:	687b      	ldr	r3, [r7, #4]
+ 8038494:	2200      	movs	r2, #0
+ 8038496:	635a      	str	r2, [r3, #52]	@ 0x34
+
+  /* Store Last receive data if any */
+  if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET)
+ 8038498:	683b      	ldr	r3, [r7, #0]
+ 803849a:	f003 0304 	and.w	r3, r3, #4
+ 803849e:	2b00      	cmp	r3, #0
+ 80384a0:	d022      	beq.n	80384e8 <I2C_ITListenCplt+0x7c>
+  {
+    /* Read data from RXDR */
+    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+ 80384a2:	687b      	ldr	r3, [r7, #4]
+ 80384a4:	681b      	ldr	r3, [r3, #0]
+ 80384a6:	6a5a      	ldr	r2, [r3, #36]	@ 0x24
+ 80384a8:	687b      	ldr	r3, [r7, #4]
+ 80384aa:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 80384ac:	b2d2      	uxtb	r2, r2
+ 80384ae:	701a      	strb	r2, [r3, #0]
+
+    /* Increment Buffer pointer */
+    hi2c->pBuffPtr++;
+ 80384b0:	687b      	ldr	r3, [r7, #4]
+ 80384b2:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 80384b4:	1c5a      	adds	r2, r3, #1
+ 80384b6:	687b      	ldr	r3, [r7, #4]
+ 80384b8:	625a      	str	r2, [r3, #36]	@ 0x24
+
+    if ((hi2c->XferSize > 0U))
+ 80384ba:	687b      	ldr	r3, [r7, #4]
+ 80384bc:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
+ 80384be:	2b00      	cmp	r3, #0
+ 80384c0:	d012      	beq.n	80384e8 <I2C_ITListenCplt+0x7c>
+    {
+      hi2c->XferSize--;
+ 80384c2:	687b      	ldr	r3, [r7, #4]
+ 80384c4:	8d1b      	ldrh	r3, [r3, #40]	@ 0x28
+ 80384c6:	3b01      	subs	r3, #1
+ 80384c8:	b29a      	uxth	r2, r3
+ 80384ca:	687b      	ldr	r3, [r7, #4]
+ 80384cc:	851a      	strh	r2, [r3, #40]	@ 0x28
+      hi2c->XferCount--;
+ 80384ce:	687b      	ldr	r3, [r7, #4]
+ 80384d0:	8d5b      	ldrh	r3, [r3, #42]	@ 0x2a
+ 80384d2:	b29b      	uxth	r3, r3
+ 80384d4:	3b01      	subs	r3, #1
+ 80384d6:	b29a      	uxth	r2, r3
+ 80384d8:	687b      	ldr	r3, [r7, #4]
+ 80384da:	855a      	strh	r2, [r3, #42]	@ 0x2a
+
+      /* Set ErrorCode corresponding to a Non-Acknowledge */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ 80384dc:	687b      	ldr	r3, [r7, #4]
+ 80384de:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
+ 80384e0:	f043 0204 	orr.w	r2, r3, #4
+ 80384e4:	687b      	ldr	r3, [r7, #4]
+ 80384e6:	645a      	str	r2, [r3, #68]	@ 0x44
+    }
+  }
+
+  /* Disable all Interrupts*/
+  I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
+ 80384e8:	f248 0103 	movw	r1, #32771	@ 0x8003
+ 80384ec:	6878      	ldr	r0, [r7, #4]
+ 80384ee:	f000 f96a 	bl	80387c6 <I2C_Disable_IRQ>
+
+  /* Clear NACK Flag */
+  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+ 80384f2:	687b      	ldr	r3, [r7, #4]
+ 80384f4:	681b      	ldr	r3, [r3, #0]
+ 80384f6:	2210      	movs	r2, #16
+ 80384f8:	61da      	str	r2, [r3, #28]
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2c);
+ 80384fa:	687b      	ldr	r3, [r7, #4]
+ 80384fc:	2200      	movs	r2, #0
+ 80384fe:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40
+
+  /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+  hi2c->ListenCpltCallback(hi2c);
+#else
+  HAL_I2C_ListenCpltCallback(hi2c);
+ 8038502:	6878      	ldr	r0, [r7, #4]
+ 8038504:	f7ff fb67 	bl	8037bd6 <HAL_I2C_ListenCpltCallback>
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+}
+ 8038508:	bf00      	nop
+ 803850a:	3708      	adds	r7, #8
+ 803850c:	46bd      	mov	sp, r7
+ 803850e:	bd80      	pop	{r7, pc}
+ 8038510:	ffff0000 	.word	0xffff0000
+
+08038514 <I2C_ITError>:
+  * @param  hi2c I2C handle.
+  * @param  ErrorCode Error code to handle.
+  * @retval None
+  */
+static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
+{
+ 8038514:	b580      	push	{r7, lr}
+ 8038516:	b084      	sub	sp, #16
+ 8038518:	af00      	add	r7, sp, #0
+ 803851a:	6078      	str	r0, [r7, #4]
+ 803851c:	6039      	str	r1, [r7, #0]
+  HAL_I2C_StateTypeDef tmpstate = hi2c->State;
+ 803851e:	687b      	ldr	r3, [r7, #4]
+ 8038520:	f893 3041 	ldrb.w	r3, [r3, #65]	@ 0x41
+ 8038524:	73fb      	strb	r3, [r7, #15]
+
+  uint32_t tmppreviousstate;
+
+  /* Reset handle parameters */
+  hi2c->Mode          = HAL_I2C_MODE_NONE;
+ 8038526:	687b      	ldr	r3, [r7, #4]
+ 8038528:	2200      	movs	r2, #0
+ 803852a:	f883 2042 	strb.w	r2, [r3, #66]	@ 0x42
+  hi2c->XferOptions   = I2C_NO_OPTION_FRAME;
+ 803852e:	687b      	ldr	r3, [r7, #4]
+ 8038530:	4a6d      	ldr	r2, [pc, #436]	@ (80386e8 <I2C_ITError+0x1d4>)
+ 8038532:	62da      	str	r2, [r3, #44]	@ 0x2c
+  hi2c->XferCount     = 0U;
+ 8038534:	687b      	ldr	r3, [r7, #4]
+ 8038536:	2200      	movs	r2, #0
+ 8038538:	855a      	strh	r2, [r3, #42]	@ 0x2a
+
+  /* Set new error code */
+  hi2c->ErrorCode |= ErrorCode;
+ 803853a:	687b      	ldr	r3, [r7, #4]
+ 803853c:	6c5a      	ldr	r2, [r3, #68]	@ 0x44
+ 803853e:	683b      	ldr	r3, [r7, #0]
+ 8038540:	431a      	orrs	r2, r3
+ 8038542:	687b      	ldr	r3, [r7, #4]
+ 8038544:	645a      	str	r2, [r3, #68]	@ 0x44
+
+  /* Disable Interrupts */
+  if ((tmpstate == HAL_I2C_STATE_LISTEN)         ||
+ 8038546:	7bfb      	ldrb	r3, [r7, #15]
+ 8038548:	2b28      	cmp	r3, #40	@ 0x28
+ 803854a:	d005      	beq.n	8038558 <I2C_ITError+0x44>
+ 803854c:	7bfb      	ldrb	r3, [r7, #15]
+ 803854e:	2b29      	cmp	r3, #41	@ 0x29
+ 8038550:	d002      	beq.n	8038558 <I2C_ITError+0x44>
+      (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
+ 8038552:	7bfb      	ldrb	r3, [r7, #15]
+ 8038554:	2b2a      	cmp	r3, #42	@ 0x2a
+ 8038556:	d10b      	bne.n	8038570 <I2C_ITError+0x5c>
+      (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
+  {
+    /* Disable all interrupts, except interrupts related to LISTEN state */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);
+ 8038558:	2103      	movs	r1, #3
+ 803855a:	6878      	ldr	r0, [r7, #4]
+ 803855c:	f000 f933 	bl	80387c6 <I2C_Disable_IRQ>
+
+    /* keep HAL_I2C_STATE_LISTEN if set */
+    hi2c->State         = HAL_I2C_STATE_LISTEN;
+ 8038560:	687b      	ldr	r3, [r7, #4]
+ 8038562:	2228      	movs	r2, #40	@ 0x28
+ 8038564:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
+    hi2c->XferISR       = I2C_Slave_ISR_IT;
+ 8038568:	687b      	ldr	r3, [r7, #4]
+ 803856a:	4a60      	ldr	r2, [pc, #384]	@ (80386ec <I2C_ITError+0x1d8>)
+ 803856c:	635a      	str	r2, [r3, #52]	@ 0x34
+ 803856e:	e030      	b.n	80385d2 <I2C_ITError+0xbe>
+  }
+  else
+  {
+    /* Disable all interrupts */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
+ 8038570:	f248 0103 	movw	r1, #32771	@ 0x8003
+ 8038574:	6878      	ldr	r0, [r7, #4]
+ 8038576:	f000 f926 	bl	80387c6 <I2C_Disable_IRQ>
+
+    /* Flush TX register */
+    I2C_Flush_TXDR(hi2c);
+ 803857a:	6878      	ldr	r0, [r7, #4]
+ 803857c:	f000 f8e1 	bl	8038742 <I2C_Flush_TXDR>
+
+    /* If state is an abort treatment on going, don't change state */
+    /* This change will be do later */
+    if (hi2c->State != HAL_I2C_STATE_ABORT)
+ 8038580:	687b      	ldr	r3, [r7, #4]
+ 8038582:	f893 3041 	ldrb.w	r3, [r3, #65]	@ 0x41
+ 8038586:	b2db      	uxtb	r3, r3
+ 8038588:	2b60      	cmp	r3, #96	@ 0x60
+ 803858a:	d01f      	beq.n	80385cc <I2C_ITError+0xb8>
+    {
+      /* Set HAL_I2C_STATE_READY */
+      hi2c->State         = HAL_I2C_STATE_READY;
+ 803858c:	687b      	ldr	r3, [r7, #4]
+ 803858e:	2220      	movs	r2, #32
+ 8038590:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
+
+      /* Check if a STOPF is detected */
+      if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
+ 8038594:	687b      	ldr	r3, [r7, #4]
+ 8038596:	681b      	ldr	r3, [r3, #0]
+ 8038598:	699b      	ldr	r3, [r3, #24]
+ 803859a:	f003 0320 	and.w	r3, r3, #32
+ 803859e:	2b20      	cmp	r3, #32
+ 80385a0:	d114      	bne.n	80385cc <I2C_ITError+0xb8>
+      {
+        if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
+ 80385a2:	687b      	ldr	r3, [r7, #4]
+ 80385a4:	681b      	ldr	r3, [r3, #0]
+ 80385a6:	699b      	ldr	r3, [r3, #24]
+ 80385a8:	f003 0310 	and.w	r3, r3, #16
+ 80385ac:	2b10      	cmp	r3, #16
+ 80385ae:	d109      	bne.n	80385c4 <I2C_ITError+0xb0>
+        {
+          __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+ 80385b0:	687b      	ldr	r3, [r7, #4]
+ 80385b2:	681b      	ldr	r3, [r3, #0]
+ 80385b4:	2210      	movs	r2, #16
+ 80385b6:	61da      	str	r2, [r3, #28]
+          hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ 80385b8:	687b      	ldr	r3, [r7, #4]
+ 80385ba:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
+ 80385bc:	f043 0204 	orr.w	r2, r3, #4
+ 80385c0:	687b      	ldr	r3, [r7, #4]
+ 80385c2:	645a      	str	r2, [r3, #68]	@ 0x44
+        }
+
+        /* Clear STOP Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+ 80385c4:	687b      	ldr	r3, [r7, #4]
+ 80385c6:	681b      	ldr	r3, [r3, #0]
+ 80385c8:	2220      	movs	r2, #32
+ 80385ca:	61da      	str	r2, [r3, #28]
+      }
+
+    }
+    hi2c->XferISR       = NULL;
+ 80385cc:	687b      	ldr	r3, [r7, #4]
+ 80385ce:	2200      	movs	r2, #0
+ 80385d0:	635a      	str	r2, [r3, #52]	@ 0x34
+  }
+
+  /* Abort DMA TX transfer if any */
+  tmppreviousstate = hi2c->PreviousState;
+ 80385d2:	687b      	ldr	r3, [r7, #4]
+ 80385d4:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
+ 80385d6:	60bb      	str	r3, [r7, #8]
+
+  if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \
+ 80385d8:	687b      	ldr	r3, [r7, #4]
+ 80385da:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
+ 80385dc:	2b00      	cmp	r3, #0
+ 80385de:	d039      	beq.n	8038654 <I2C_ITError+0x140>
+ 80385e0:	68bb      	ldr	r3, [r7, #8]
+ 80385e2:	2b11      	cmp	r3, #17
+ 80385e4:	d002      	beq.n	80385ec <I2C_ITError+0xd8>
+ 80385e6:	68bb      	ldr	r3, [r7, #8]
+ 80385e8:	2b21      	cmp	r3, #33	@ 0x21
+ 80385ea:	d133      	bne.n	8038654 <I2C_ITError+0x140>
+                                 (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
+  {
+    if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+ 80385ec:	687b      	ldr	r3, [r7, #4]
+ 80385ee:	681b      	ldr	r3, [r3, #0]
+ 80385f0:	681b      	ldr	r3, [r3, #0]
+ 80385f2:	f403 4380 	and.w	r3, r3, #16384	@ 0x4000
+ 80385f6:	f5b3 4f80 	cmp.w	r3, #16384	@ 0x4000
+ 80385fa:	d107      	bne.n	803860c <I2C_ITError+0xf8>
+    {
+      hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+ 80385fc:	687b      	ldr	r3, [r7, #4]
+ 80385fe:	681b      	ldr	r3, [r3, #0]
+ 8038600:	681a      	ldr	r2, [r3, #0]
+ 8038602:	687b      	ldr	r3, [r7, #4]
+ 8038604:	681b      	ldr	r3, [r3, #0]
+ 8038606:	f422 4280 	bic.w	r2, r2, #16384	@ 0x4000
+ 803860a:	601a      	str	r2, [r3, #0]
+    }
+
+    if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
+ 803860c:	687b      	ldr	r3, [r7, #4]
+ 803860e:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
+ 8038610:	4618      	mov	r0, r3
+ 8038612:	f7fc fd4f 	bl	80350b4 <HAL_DMA_GetState>
+ 8038616:	4603      	mov	r3, r0
+ 8038618:	2b01      	cmp	r3, #1
+ 803861a:	d017      	beq.n	803864c <I2C_ITError+0x138>
+    {
+      /* Set the I2C DMA Abort callback :
+       will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+      hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+ 803861c:	687b      	ldr	r3, [r7, #4]
+ 803861e:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
+ 8038620:	4a33      	ldr	r2, [pc, #204]	@ (80386f0 <I2C_ITError+0x1dc>)
+ 8038622:	651a      	str	r2, [r3, #80]	@ 0x50
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+ 8038624:	687b      	ldr	r3, [r7, #4]
+ 8038626:	2200      	movs	r2, #0
+ 8038628:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40
+
+      /* Abort DMA TX */
+      if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+ 803862c:	687b      	ldr	r3, [r7, #4]
+ 803862e:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
+ 8038630:	4618      	mov	r0, r3
+ 8038632:	f7fb fbcf 	bl	8033dd4 <HAL_DMA_Abort_IT>
+ 8038636:	4603      	mov	r3, r0
+ 8038638:	2b00      	cmp	r3, #0
+ 803863a:	d04d      	beq.n	80386d8 <I2C_ITError+0x1c4>
+      {
+        /* Call Directly XferAbortCallback function in case of error */
+        hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+ 803863c:	687b      	ldr	r3, [r7, #4]
+ 803863e:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
+ 8038640:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
+ 8038642:	687a      	ldr	r2, [r7, #4]
+ 8038644:	6b92      	ldr	r2, [r2, #56]	@ 0x38
+ 8038646:	4610      	mov	r0, r2
+ 8038648:	4798      	blx	r3
+    if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
+ 803864a:	e045      	b.n	80386d8 <I2C_ITError+0x1c4>
+      }
+    }
+    else
+    {
+      I2C_TreatErrorCallback(hi2c);
+ 803864c:	6878      	ldr	r0, [r7, #4]
+ 803864e:	f000 f851 	bl	80386f4 <I2C_TreatErrorCallback>
+    if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
+ 8038652:	e041      	b.n	80386d8 <I2C_ITError+0x1c4>
+    }
+  }
+  /* Abort DMA RX transfer if any */
+  else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || \
+ 8038654:	687b      	ldr	r3, [r7, #4]
+ 8038656:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 8038658:	2b00      	cmp	r3, #0
+ 803865a:	d039      	beq.n	80386d0 <I2C_ITError+0x1bc>
+ 803865c:	68bb      	ldr	r3, [r7, #8]
+ 803865e:	2b12      	cmp	r3, #18
+ 8038660:	d002      	beq.n	8038668 <I2C_ITError+0x154>
+ 8038662:	68bb      	ldr	r3, [r7, #8]
+ 8038664:	2b22      	cmp	r3, #34	@ 0x22
+ 8038666:	d133      	bne.n	80386d0 <I2C_ITError+0x1bc>
+                                      (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX)))
+  {
+    if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+ 8038668:	687b      	ldr	r3, [r7, #4]
+ 803866a:	681b      	ldr	r3, [r3, #0]
+ 803866c:	681b      	ldr	r3, [r3, #0]
+ 803866e:	f403 4300 	and.w	r3, r3, #32768	@ 0x8000
+ 8038672:	f5b3 4f00 	cmp.w	r3, #32768	@ 0x8000
+ 8038676:	d107      	bne.n	8038688 <I2C_ITError+0x174>
+    {
+      hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+ 8038678:	687b      	ldr	r3, [r7, #4]
+ 803867a:	681b      	ldr	r3, [r3, #0]
+ 803867c:	681a      	ldr	r2, [r3, #0]
+ 803867e:	687b      	ldr	r3, [r7, #4]
+ 8038680:	681b      	ldr	r3, [r3, #0]
+ 8038682:	f422 4200 	bic.w	r2, r2, #32768	@ 0x8000
+ 8038686:	601a      	str	r2, [r3, #0]
+    }
+
+    if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
+ 8038688:	687b      	ldr	r3, [r7, #4]
+ 803868a:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 803868c:	4618      	mov	r0, r3
+ 803868e:	f7fc fd11 	bl	80350b4 <HAL_DMA_GetState>
+ 8038692:	4603      	mov	r3, r0
+ 8038694:	2b01      	cmp	r3, #1
+ 8038696:	d017      	beq.n	80386c8 <I2C_ITError+0x1b4>
+    {
+      /* Set the I2C DMA Abort callback :
+        will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+      hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+ 8038698:	687b      	ldr	r3, [r7, #4]
+ 803869a:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 803869c:	4a14      	ldr	r2, [pc, #80]	@ (80386f0 <I2C_ITError+0x1dc>)
+ 803869e:	651a      	str	r2, [r3, #80]	@ 0x50
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hi2c);
+ 80386a0:	687b      	ldr	r3, [r7, #4]
+ 80386a2:	2200      	movs	r2, #0
+ 80386a4:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40
+
+      /* Abort DMA RX */
+      if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+ 80386a8:	687b      	ldr	r3, [r7, #4]
+ 80386aa:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 80386ac:	4618      	mov	r0, r3
+ 80386ae:	f7fb fb91 	bl	8033dd4 <HAL_DMA_Abort_IT>
+ 80386b2:	4603      	mov	r3, r0
+ 80386b4:	2b00      	cmp	r3, #0
+ 80386b6:	d011      	beq.n	80386dc <I2C_ITError+0x1c8>
+      {
+        /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
+        hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+ 80386b8:	687b      	ldr	r3, [r7, #4]
+ 80386ba:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 80386bc:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
+ 80386be:	687a      	ldr	r2, [r7, #4]
+ 80386c0:	6bd2      	ldr	r2, [r2, #60]	@ 0x3c
+ 80386c2:	4610      	mov	r0, r2
+ 80386c4:	4798      	blx	r3
+    if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
+ 80386c6:	e009      	b.n	80386dc <I2C_ITError+0x1c8>
+      }
+    }
+    else
+    {
+      I2C_TreatErrorCallback(hi2c);
+ 80386c8:	6878      	ldr	r0, [r7, #4]
+ 80386ca:	f000 f813 	bl	80386f4 <I2C_TreatErrorCallback>
+    if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
+ 80386ce:	e005      	b.n	80386dc <I2C_ITError+0x1c8>
+    }
+  }
+  else
+  {
+    I2C_TreatErrorCallback(hi2c);
+ 80386d0:	6878      	ldr	r0, [r7, #4]
+ 80386d2:	f000 f80f 	bl	80386f4 <I2C_TreatErrorCallback>
+  }
+}
+ 80386d6:	e002      	b.n	80386de <I2C_ITError+0x1ca>
+    if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
+ 80386d8:	bf00      	nop
+ 80386da:	e000      	b.n	80386de <I2C_ITError+0x1ca>
+    if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
+ 80386dc:	bf00      	nop
+}
+ 80386de:	bf00      	nop
+ 80386e0:	3710      	adds	r7, #16
+ 80386e2:	46bd      	mov	sp, r7
+ 80386e4:	bd80      	pop	{r7, pc}
+ 80386e6:	bf00      	nop
+ 80386e8:	ffff0000 	.word	0xffff0000
+ 80386ec:	08037c13 	.word	0x08037c13
+ 80386f0:	0803878b 	.word	0x0803878b
+
+080386f4 <I2C_TreatErrorCallback>:
+  * @brief  I2C Error callback treatment.
+  * @param  hi2c I2C handle.
+  * @retval None
+  */
+static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c)
+{
+ 80386f4:	b580      	push	{r7, lr}
+ 80386f6:	b082      	sub	sp, #8
+ 80386f8:	af00      	add	r7, sp, #0
+ 80386fa:	6078      	str	r0, [r7, #4]
+  if (hi2c->State == HAL_I2C_STATE_ABORT)
+ 80386fc:	687b      	ldr	r3, [r7, #4]
+ 80386fe:	f893 3041 	ldrb.w	r3, [r3, #65]	@ 0x41
+ 8038702:	b2db      	uxtb	r3, r3
+ 8038704:	2b60      	cmp	r3, #96	@ 0x60
+ 8038706:	d10e      	bne.n	8038726 <I2C_TreatErrorCallback+0x32>
+  {
+    hi2c->State = HAL_I2C_STATE_READY;
+ 8038708:	687b      	ldr	r3, [r7, #4]
+ 803870a:	2220      	movs	r2, #32
+ 803870c:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
+    hi2c->PreviousState = I2C_STATE_NONE;
+ 8038710:	687b      	ldr	r3, [r7, #4]
+ 8038712:	2200      	movs	r2, #0
+ 8038714:	631a      	str	r2, [r3, #48]	@ 0x30
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+ 8038716:	687b      	ldr	r3, [r7, #4]
+ 8038718:	2200      	movs	r2, #0
+ 803871a:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40
+
+    /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+    hi2c->AbortCpltCallback(hi2c);
+#else
+    HAL_I2C_AbortCpltCallback(hi2c);
+ 803871e:	6878      	ldr	r0, [r7, #4]
+ 8038720:	f7ff fa6d 	bl	8037bfe <HAL_I2C_AbortCpltCallback>
+    hi2c->ErrorCallback(hi2c);
+#else
+    HAL_I2C_ErrorCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+  }
+}
+ 8038724:	e009      	b.n	803873a <I2C_TreatErrorCallback+0x46>
+    hi2c->PreviousState = I2C_STATE_NONE;
+ 8038726:	687b      	ldr	r3, [r7, #4]
+ 8038728:	2200      	movs	r2, #0
+ 803872a:	631a      	str	r2, [r3, #48]	@ 0x30
+    __HAL_UNLOCK(hi2c);
+ 803872c:	687b      	ldr	r3, [r7, #4]
+ 803872e:	2200      	movs	r2, #0
+ 8038730:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40
+    HAL_I2C_ErrorCallback(hi2c);
+ 8038734:	6878      	ldr	r0, [r7, #4]
+ 8038736:	f7ff fa58 	bl	8037bea <HAL_I2C_ErrorCallback>
+}
+ 803873a:	bf00      	nop
+ 803873c:	3708      	adds	r7, #8
+ 803873e:	46bd      	mov	sp, r7
+ 8038740:	bd80      	pop	{r7, pc}
+
+08038742 <I2C_Flush_TXDR>:
+  * @brief  I2C Tx data register flush process.
+  * @param  hi2c I2C handle.
+  * @retval None
+  */
+static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
+{
+ 8038742:	b480      	push	{r7}
+ 8038744:	b083      	sub	sp, #12
+ 8038746:	af00      	add	r7, sp, #0
+ 8038748:	6078      	str	r0, [r7, #4]
+  /* If a pending TXIS flag is set */
+  /* Write a dummy data in TXDR to clear it */
+  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
+ 803874a:	687b      	ldr	r3, [r7, #4]
+ 803874c:	681b      	ldr	r3, [r3, #0]
+ 803874e:	699b      	ldr	r3, [r3, #24]
+ 8038750:	f003 0302 	and.w	r3, r3, #2
+ 8038754:	2b02      	cmp	r3, #2
+ 8038756:	d103      	bne.n	8038760 <I2C_Flush_TXDR+0x1e>
+  {
+    hi2c->Instance->TXDR = 0x00U;
+ 8038758:	687b      	ldr	r3, [r7, #4]
+ 803875a:	681b      	ldr	r3, [r3, #0]
+ 803875c:	2200      	movs	r2, #0
+ 803875e:	629a      	str	r2, [r3, #40]	@ 0x28
+  }
+
+  /* Flush TX register if not empty */
+  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
+ 8038760:	687b      	ldr	r3, [r7, #4]
+ 8038762:	681b      	ldr	r3, [r3, #0]
+ 8038764:	699b      	ldr	r3, [r3, #24]
+ 8038766:	f003 0301 	and.w	r3, r3, #1
+ 803876a:	2b01      	cmp	r3, #1
+ 803876c:	d007      	beq.n	803877e <I2C_Flush_TXDR+0x3c>
+  {
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
+ 803876e:	687b      	ldr	r3, [r7, #4]
+ 8038770:	681b      	ldr	r3, [r3, #0]
+ 8038772:	699a      	ldr	r2, [r3, #24]
+ 8038774:	687b      	ldr	r3, [r7, #4]
+ 8038776:	681b      	ldr	r3, [r3, #0]
+ 8038778:	f042 0201 	orr.w	r2, r2, #1
+ 803877c:	619a      	str	r2, [r3, #24]
+  }
+}
+ 803877e:	bf00      	nop
+ 8038780:	370c      	adds	r7, #12
+ 8038782:	46bd      	mov	sp, r7
+ 8038784:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8038788:	4770      	bx	lr
+
+0803878a <I2C_DMAAbort>:
+  *        (To be called at end of DMA Abort procedure).
+  * @param hdma DMA handle.
+  * @retval None
+  */
+static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
+{
+ 803878a:	b580      	push	{r7, lr}
+ 803878c:	b084      	sub	sp, #16
+ 803878e:	af00      	add	r7, sp, #0
+ 8038790:	6078      	str	r0, [r7, #4]
+  /* Derogation MISRAC2012-Rule-11.5 */
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
+ 8038792:	687b      	ldr	r3, [r7, #4]
+ 8038794:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
+ 8038796:	60fb      	str	r3, [r7, #12]
+
+  /* Reset AbortCpltCallback */
+  if (hi2c->hdmatx != NULL)
+ 8038798:	68fb      	ldr	r3, [r7, #12]
+ 803879a:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
+ 803879c:	2b00      	cmp	r3, #0
+ 803879e:	d003      	beq.n	80387a8 <I2C_DMAAbort+0x1e>
+  {
+    hi2c->hdmatx->XferAbortCallback = NULL;
+ 80387a0:	68fb      	ldr	r3, [r7, #12]
+ 80387a2:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
+ 80387a4:	2200      	movs	r2, #0
+ 80387a6:	651a      	str	r2, [r3, #80]	@ 0x50
+  }
+  if (hi2c->hdmarx != NULL)
+ 80387a8:	68fb      	ldr	r3, [r7, #12]
+ 80387aa:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 80387ac:	2b00      	cmp	r3, #0
+ 80387ae:	d003      	beq.n	80387b8 <I2C_DMAAbort+0x2e>
+  {
+    hi2c->hdmarx->XferAbortCallback = NULL;
+ 80387b0:	68fb      	ldr	r3, [r7, #12]
+ 80387b2:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 80387b4:	2200      	movs	r2, #0
+ 80387b6:	651a      	str	r2, [r3, #80]	@ 0x50
+  }
+
+  I2C_TreatErrorCallback(hi2c);
+ 80387b8:	68f8      	ldr	r0, [r7, #12]
+ 80387ba:	f7ff ff9b 	bl	80386f4 <I2C_TreatErrorCallback>
+}
+ 80387be:	bf00      	nop
+ 80387c0:	3710      	adds	r7, #16
+ 80387c2:	46bd      	mov	sp, r7
+ 80387c4:	bd80      	pop	{r7, pc}
+
+080387c6 <I2C_Disable_IRQ>:
+  *                the configuration information for the specified I2C.
+  * @param  InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
+  * @retval None
+  */
+static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
+{
+ 80387c6:	b480      	push	{r7}
+ 80387c8:	b085      	sub	sp, #20
+ 80387ca:	af00      	add	r7, sp, #0
+ 80387cc:	6078      	str	r0, [r7, #4]
+ 80387ce:	460b      	mov	r3, r1
+ 80387d0:	807b      	strh	r3, [r7, #2]
+  uint32_t tmpisr = 0U;
+ 80387d2:	2300      	movs	r3, #0
+ 80387d4:	60fb      	str	r3, [r7, #12]
+
+  if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
+ 80387d6:	887b      	ldrh	r3, [r7, #2]
+ 80387d8:	f003 0301 	and.w	r3, r3, #1
+ 80387dc:	2b00      	cmp	r3, #0
+ 80387de:	d00f      	beq.n	8038800 <I2C_Disable_IRQ+0x3a>
+  {
+    /* Disable TC and TXI interrupts */
+    tmpisr |= I2C_IT_TCI | I2C_IT_TXI;
+ 80387e0:	68fb      	ldr	r3, [r7, #12]
+ 80387e2:	f043 0342 	orr.w	r3, r3, #66	@ 0x42
+ 80387e6:	60fb      	str	r3, [r7, #12]
+
+    if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
+ 80387e8:	687b      	ldr	r3, [r7, #4]
+ 80387ea:	f893 3041 	ldrb.w	r3, [r3, #65]	@ 0x41
+ 80387ee:	b2db      	uxtb	r3, r3
+ 80387f0:	f003 0328 	and.w	r3, r3, #40	@ 0x28
+ 80387f4:	2b28      	cmp	r3, #40	@ 0x28
+ 80387f6:	d003      	beq.n	8038800 <I2C_Disable_IRQ+0x3a>
+    {
+      /* Disable NACK and STOP interrupts */
+      tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+ 80387f8:	68fb      	ldr	r3, [r7, #12]
+ 80387fa:	f043 03b0 	orr.w	r3, r3, #176	@ 0xb0
+ 80387fe:	60fb      	str	r3, [r7, #12]
+    }
+  }
+
+  if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
+ 8038800:	887b      	ldrh	r3, [r7, #2]
+ 8038802:	f003 0302 	and.w	r3, r3, #2
+ 8038806:	2b00      	cmp	r3, #0
+ 8038808:	d00f      	beq.n	803882a <I2C_Disable_IRQ+0x64>
+  {
+    /* Disable TC and RXI interrupts */
+    tmpisr |= I2C_IT_TCI | I2C_IT_RXI;
+ 803880a:	68fb      	ldr	r3, [r7, #12]
+ 803880c:	f043 0344 	orr.w	r3, r3, #68	@ 0x44
+ 8038810:	60fb      	str	r3, [r7, #12]
+
+    if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
+ 8038812:	687b      	ldr	r3, [r7, #4]
+ 8038814:	f893 3041 	ldrb.w	r3, [r3, #65]	@ 0x41
+ 8038818:	b2db      	uxtb	r3, r3
+ 803881a:	f003 0328 	and.w	r3, r3, #40	@ 0x28
+ 803881e:	2b28      	cmp	r3, #40	@ 0x28
+ 8038820:	d003      	beq.n	803882a <I2C_Disable_IRQ+0x64>
+    {
+      /* Disable NACK and STOP interrupts */
+      tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+ 8038822:	68fb      	ldr	r3, [r7, #12]
+ 8038824:	f043 03b0 	orr.w	r3, r3, #176	@ 0xb0
+ 8038828:	60fb      	str	r3, [r7, #12]
+    }
+  }
+
+  if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
+ 803882a:	f9b7 3002 	ldrsh.w	r3, [r7, #2]
+ 803882e:	2b00      	cmp	r3, #0
+ 8038830:	da03      	bge.n	803883a <I2C_Disable_IRQ+0x74>
+  {
+    /* Disable ADDR, NACK and STOP interrupts */
+    tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+ 8038832:	68fb      	ldr	r3, [r7, #12]
+ 8038834:	f043 03b8 	orr.w	r3, r3, #184	@ 0xb8
+ 8038838:	60fb      	str	r3, [r7, #12]
+  }
+
+  if (InterruptRequest == I2C_XFER_ERROR_IT)
+ 803883a:	887b      	ldrh	r3, [r7, #2]
+ 803883c:	2b10      	cmp	r3, #16
+ 803883e:	d103      	bne.n	8038848 <I2C_Disable_IRQ+0x82>
+  {
+    /* Enable ERR and NACK interrupts */
+    tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
+ 8038840:	68fb      	ldr	r3, [r7, #12]
+ 8038842:	f043 0390 	orr.w	r3, r3, #144	@ 0x90
+ 8038846:	60fb      	str	r3, [r7, #12]
+  }
+
+  if (InterruptRequest == I2C_XFER_CPLT_IT)
+ 8038848:	887b      	ldrh	r3, [r7, #2]
+ 803884a:	2b20      	cmp	r3, #32
+ 803884c:	d103      	bne.n	8038856 <I2C_Disable_IRQ+0x90>
+  {
+    /* Enable STOP interrupts */
+    tmpisr |= I2C_IT_STOPI;
+ 803884e:	68fb      	ldr	r3, [r7, #12]
+ 8038850:	f043 0320 	orr.w	r3, r3, #32
+ 8038854:	60fb      	str	r3, [r7, #12]
+  }
+
+  if (InterruptRequest == I2C_XFER_RELOAD_IT)
+ 8038856:	887b      	ldrh	r3, [r7, #2]
+ 8038858:	2b40      	cmp	r3, #64	@ 0x40
+ 803885a:	d103      	bne.n	8038864 <I2C_Disable_IRQ+0x9e>
+  {
+    /* Enable TC interrupts */
+    tmpisr |= I2C_IT_TCI;
+ 803885c:	68fb      	ldr	r3, [r7, #12]
+ 803885e:	f043 0340 	orr.w	r3, r3, #64	@ 0x40
+ 8038862:	60fb      	str	r3, [r7, #12]
+  }
+
+  /* Disable interrupts only at the end */
+  /* to avoid a breaking situation like at "t" time */
+  /* all disable interrupts request are not done */
+  __HAL_I2C_DISABLE_IT(hi2c, tmpisr);
+ 8038864:	687b      	ldr	r3, [r7, #4]
+ 8038866:	681b      	ldr	r3, [r3, #0]
+ 8038868:	6819      	ldr	r1, [r3, #0]
+ 803886a:	68fb      	ldr	r3, [r7, #12]
+ 803886c:	43da      	mvns	r2, r3
+ 803886e:	687b      	ldr	r3, [r7, #4]
+ 8038870:	681b      	ldr	r3, [r3, #0]
+ 8038872:	400a      	ands	r2, r1
+ 8038874:	601a      	str	r2, [r3, #0]
+}
+ 8038876:	bf00      	nop
+ 8038878:	3714      	adds	r7, #20
+ 803887a:	46bd      	mov	sp, r7
+ 803887c:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8038880:	4770      	bx	lr
+
+08038882 <HAL_I2CEx_ConfigAnalogFilter>:
+  *                the configuration information for the specified I2Cx peripheral.
+  * @param  AnalogFilter New state of the Analog filter.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
+{
+ 8038882:	b480      	push	{r7}
+ 8038884:	b083      	sub	sp, #12
+ 8038886:	af00      	add	r7, sp, #0
+ 8038888:	6078      	str	r0, [r7, #4]
+ 803888a:	6039      	str	r1, [r7, #0]
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+  assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+ 803888c:	687b      	ldr	r3, [r7, #4]
+ 803888e:	f893 3041 	ldrb.w	r3, [r3, #65]	@ 0x41
+ 8038892:	b2db      	uxtb	r3, r3
+ 8038894:	2b20      	cmp	r3, #32
+ 8038896:	d138      	bne.n	803890a <HAL_I2CEx_ConfigAnalogFilter+0x88>
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+ 8038898:	687b      	ldr	r3, [r7, #4]
+ 803889a:	f893 3040 	ldrb.w	r3, [r3, #64]	@ 0x40
+ 803889e:	2b01      	cmp	r3, #1
+ 80388a0:	d101      	bne.n	80388a6 <HAL_I2CEx_ConfigAnalogFilter+0x24>
+ 80388a2:	2302      	movs	r3, #2
+ 80388a4:	e032      	b.n	803890c <HAL_I2CEx_ConfigAnalogFilter+0x8a>
+ 80388a6:	687b      	ldr	r3, [r7, #4]
+ 80388a8:	2201      	movs	r2, #1
+ 80388aa:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40
+
+    hi2c->State = HAL_I2C_STATE_BUSY;
+ 80388ae:	687b      	ldr	r3, [r7, #4]
+ 80388b0:	2224      	movs	r2, #36	@ 0x24
+ 80388b2:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
+
+    /* Disable the selected I2C peripheral */
+    __HAL_I2C_DISABLE(hi2c);
+ 80388b6:	687b      	ldr	r3, [r7, #4]
+ 80388b8:	681b      	ldr	r3, [r3, #0]
+ 80388ba:	681a      	ldr	r2, [r3, #0]
+ 80388bc:	687b      	ldr	r3, [r7, #4]
+ 80388be:	681b      	ldr	r3, [r3, #0]
+ 80388c0:	f022 0201 	bic.w	r2, r2, #1
+ 80388c4:	601a      	str	r2, [r3, #0]
+
+    /* Reset I2Cx ANOFF bit */
+    hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
+ 80388c6:	687b      	ldr	r3, [r7, #4]
+ 80388c8:	681b      	ldr	r3, [r3, #0]
+ 80388ca:	681a      	ldr	r2, [r3, #0]
+ 80388cc:	687b      	ldr	r3, [r7, #4]
+ 80388ce:	681b      	ldr	r3, [r3, #0]
+ 80388d0:	f422 5280 	bic.w	r2, r2, #4096	@ 0x1000
+ 80388d4:	601a      	str	r2, [r3, #0]
+
+    /* Set analog filter bit*/
+    hi2c->Instance->CR1 |= AnalogFilter;
+ 80388d6:	687b      	ldr	r3, [r7, #4]
+ 80388d8:	681b      	ldr	r3, [r3, #0]
+ 80388da:	6819      	ldr	r1, [r3, #0]
+ 80388dc:	687b      	ldr	r3, [r7, #4]
+ 80388de:	681b      	ldr	r3, [r3, #0]
+ 80388e0:	683a      	ldr	r2, [r7, #0]
+ 80388e2:	430a      	orrs	r2, r1
+ 80388e4:	601a      	str	r2, [r3, #0]
+
+    __HAL_I2C_ENABLE(hi2c);
+ 80388e6:	687b      	ldr	r3, [r7, #4]
+ 80388e8:	681b      	ldr	r3, [r3, #0]
+ 80388ea:	681a      	ldr	r2, [r3, #0]
+ 80388ec:	687b      	ldr	r3, [r7, #4]
+ 80388ee:	681b      	ldr	r3, [r3, #0]
+ 80388f0:	f042 0201 	orr.w	r2, r2, #1
+ 80388f4:	601a      	str	r2, [r3, #0]
+
+    hi2c->State = HAL_I2C_STATE_READY;
+ 80388f6:	687b      	ldr	r3, [r7, #4]
+ 80388f8:	2220      	movs	r2, #32
+ 80388fa:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+ 80388fe:	687b      	ldr	r3, [r7, #4]
+ 8038900:	2200      	movs	r2, #0
+ 8038902:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40
+
+    return HAL_OK;
+ 8038906:	2300      	movs	r3, #0
+ 8038908:	e000      	b.n	803890c <HAL_I2CEx_ConfigAnalogFilter+0x8a>
+  }
+  else
+  {
+    return HAL_BUSY;
+ 803890a:	2302      	movs	r3, #2
+  }
+}
+ 803890c:	4618      	mov	r0, r3
+ 803890e:	370c      	adds	r7, #12
+ 8038910:	46bd      	mov	sp, r7
+ 8038912:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8038916:	4770      	bx	lr
+
+08038918 <HAL_I2CEx_ConfigDigitalFilter>:
+  *                the configuration information for the specified I2Cx peripheral.
+  * @param  DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
+{
+ 8038918:	b480      	push	{r7}
+ 803891a:	b085      	sub	sp, #20
+ 803891c:	af00      	add	r7, sp, #0
+ 803891e:	6078      	str	r0, [r7, #4]
+ 8038920:	6039      	str	r1, [r7, #0]
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+  assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
+
+  if (hi2c->State == HAL_I2C_STATE_READY)
+ 8038922:	687b      	ldr	r3, [r7, #4]
+ 8038924:	f893 3041 	ldrb.w	r3, [r3, #65]	@ 0x41
+ 8038928:	b2db      	uxtb	r3, r3
+ 803892a:	2b20      	cmp	r3, #32
+ 803892c:	d139      	bne.n	80389a2 <HAL_I2CEx_ConfigDigitalFilter+0x8a>
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+ 803892e:	687b      	ldr	r3, [r7, #4]
+ 8038930:	f893 3040 	ldrb.w	r3, [r3, #64]	@ 0x40
+ 8038934:	2b01      	cmp	r3, #1
+ 8038936:	d101      	bne.n	803893c <HAL_I2CEx_ConfigDigitalFilter+0x24>
+ 8038938:	2302      	movs	r3, #2
+ 803893a:	e033      	b.n	80389a4 <HAL_I2CEx_ConfigDigitalFilter+0x8c>
+ 803893c:	687b      	ldr	r3, [r7, #4]
+ 803893e:	2201      	movs	r2, #1
+ 8038940:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40
+
+    hi2c->State = HAL_I2C_STATE_BUSY;
+ 8038944:	687b      	ldr	r3, [r7, #4]
+ 8038946:	2224      	movs	r2, #36	@ 0x24
+ 8038948:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
+
+    /* Disable the selected I2C peripheral */
+    __HAL_I2C_DISABLE(hi2c);
+ 803894c:	687b      	ldr	r3, [r7, #4]
+ 803894e:	681b      	ldr	r3, [r3, #0]
+ 8038950:	681a      	ldr	r2, [r3, #0]
+ 8038952:	687b      	ldr	r3, [r7, #4]
+ 8038954:	681b      	ldr	r3, [r3, #0]
+ 8038956:	f022 0201 	bic.w	r2, r2, #1
+ 803895a:	601a      	str	r2, [r3, #0]
+
+    /* Get the old register value */
+    tmpreg = hi2c->Instance->CR1;
+ 803895c:	687b      	ldr	r3, [r7, #4]
+ 803895e:	681b      	ldr	r3, [r3, #0]
+ 8038960:	681b      	ldr	r3, [r3, #0]
+ 8038962:	60fb      	str	r3, [r7, #12]
+
+    /* Reset I2Cx DNF bits [11:8] */
+    tmpreg &= ~(I2C_CR1_DNF);
+ 8038964:	68fb      	ldr	r3, [r7, #12]
+ 8038966:	f423 6370 	bic.w	r3, r3, #3840	@ 0xf00
+ 803896a:	60fb      	str	r3, [r7, #12]
+
+    /* Set I2Cx DNF coefficient */
+    tmpreg |= DigitalFilter << 8U;
+ 803896c:	683b      	ldr	r3, [r7, #0]
+ 803896e:	021b      	lsls	r3, r3, #8
+ 8038970:	68fa      	ldr	r2, [r7, #12]
+ 8038972:	4313      	orrs	r3, r2
+ 8038974:	60fb      	str	r3, [r7, #12]
+
+    /* Store the new register value */
+    hi2c->Instance->CR1 = tmpreg;
+ 8038976:	687b      	ldr	r3, [r7, #4]
+ 8038978:	681b      	ldr	r3, [r3, #0]
+ 803897a:	68fa      	ldr	r2, [r7, #12]
+ 803897c:	601a      	str	r2, [r3, #0]
+
+    __HAL_I2C_ENABLE(hi2c);
+ 803897e:	687b      	ldr	r3, [r7, #4]
+ 8038980:	681b      	ldr	r3, [r3, #0]
+ 8038982:	681a      	ldr	r2, [r3, #0]
+ 8038984:	687b      	ldr	r3, [r7, #4]
+ 8038986:	681b      	ldr	r3, [r3, #0]
+ 8038988:	f042 0201 	orr.w	r2, r2, #1
+ 803898c:	601a      	str	r2, [r3, #0]
+
+    hi2c->State = HAL_I2C_STATE_READY;
+ 803898e:	687b      	ldr	r3, [r7, #4]
+ 8038990:	2220      	movs	r2, #32
+ 8038992:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+ 8038996:	687b      	ldr	r3, [r7, #4]
+ 8038998:	2200      	movs	r2, #0
+ 803899a:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40
+
+    return HAL_OK;
+ 803899e:	2300      	movs	r3, #0
+ 80389a0:	e000      	b.n	80389a4 <HAL_I2CEx_ConfigDigitalFilter+0x8c>
+  }
+  else
+  {
+    return HAL_BUSY;
+ 80389a2:	2302      	movs	r3, #2
+  }
+}
+ 80389a4:	4618      	mov	r0, r3
+ 80389a6:	3714      	adds	r7, #20
+ 80389a8:	46bd      	mov	sp, r7
+ 80389aa:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80389ae:	4770      	bx	lr
+
+080389b0 <HAL_MDMA_Abort_IT>:
+  * @param  hmdma  : pointer to a MDMA_HandleTypeDef structure that contains
+  *                 the configuration information for the specified MDMA Channel.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MDMA_Abort_IT(MDMA_HandleTypeDef *hmdma)
+{
+ 80389b0:	b480      	push	{r7}
+ 80389b2:	b083      	sub	sp, #12
+ 80389b4:	af00      	add	r7, sp, #0
+ 80389b6:	6078      	str	r0, [r7, #4]
+  /* Check the MDMA peripheral handle */
+  if(hmdma == NULL)
+ 80389b8:	687b      	ldr	r3, [r7, #4]
+ 80389ba:	2b00      	cmp	r3, #0
+ 80389bc:	d101      	bne.n	80389c2 <HAL_MDMA_Abort_IT+0x12>
+  {
+    return HAL_ERROR;
+ 80389be:	2301      	movs	r3, #1
+ 80389c0:	e017      	b.n	80389f2 <HAL_MDMA_Abort_IT+0x42>
+  }
+
+  if(HAL_MDMA_STATE_BUSY != hmdma->State)
+ 80389c2:	687b      	ldr	r3, [r7, #4]
+ 80389c4:	f893 303d 	ldrb.w	r3, [r3, #61]	@ 0x3d
+ 80389c8:	b2db      	uxtb	r3, r3
+ 80389ca:	2b02      	cmp	r3, #2
+ 80389cc:	d004      	beq.n	80389d8 <HAL_MDMA_Abort_IT+0x28>
+  {
+    /* No transfer ongoing */
+    hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER;
+ 80389ce:	687b      	ldr	r3, [r7, #4]
+ 80389d0:	2280      	movs	r2, #128	@ 0x80
+ 80389d2:	669a      	str	r2, [r3, #104]	@ 0x68
+
+    return HAL_ERROR;
+ 80389d4:	2301      	movs	r3, #1
+ 80389d6:	e00c      	b.n	80389f2 <HAL_MDMA_Abort_IT+0x42>
+  }
+  else
+  {
+    /* Set Abort State  */
+    hmdma->State = HAL_MDMA_STATE_ABORT;
+ 80389d8:	687b      	ldr	r3, [r7, #4]
+ 80389da:	2204      	movs	r2, #4
+ 80389dc:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d
+
+    /* Disable the stream */
+    __HAL_MDMA_DISABLE(hmdma);
+ 80389e0:	687b      	ldr	r3, [r7, #4]
+ 80389e2:	681b      	ldr	r3, [r3, #0]
+ 80389e4:	68da      	ldr	r2, [r3, #12]
+ 80389e6:	687b      	ldr	r3, [r7, #4]
+ 80389e8:	681b      	ldr	r3, [r3, #0]
+ 80389ea:	f022 0201 	bic.w	r2, r2, #1
+ 80389ee:	60da      	str	r2, [r3, #12]
+  }
+
+  return HAL_OK;
+ 80389f0:	2300      	movs	r3, #0
+}
+ 80389f2:	4618      	mov	r0, r3
+ 80389f4:	370c      	adds	r7, #12
+ 80389f6:	46bd      	mov	sp, r7
+ 80389f8:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 80389fc:	4770      	bx	lr
+	...
+
+08038a00 <HAL_PWREx_ConfigSupply>:
+  *         PWR_SMPS_2V5_SUPPLIES_EXT are used only for lines that supports SMPS
+  *         regulator.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_PWREx_ConfigSupply (uint32_t SupplySource)
+{
+ 8038a00:	b580      	push	{r7, lr}
+ 8038a02:	b084      	sub	sp, #16
+ 8038a04:	af00      	add	r7, sp, #0
+ 8038a06:	6078      	str	r0, [r7, #4]
+  /* Check the parameters */
+  assert_param (IS_PWR_SUPPLY (SupplySource));
+
+  /* Check if supply source was configured */
+#if defined (PWR_FLAG_SCUEN)
+  if (__HAL_PWR_GET_FLAG (PWR_FLAG_SCUEN) == 0U)
+ 8038a08:	4b19      	ldr	r3, [pc, #100]	@ (8038a70 <HAL_PWREx_ConfigSupply+0x70>)
+ 8038a0a:	68db      	ldr	r3, [r3, #12]
+ 8038a0c:	f003 0304 	and.w	r3, r3, #4
+ 8038a10:	2b04      	cmp	r3, #4
+ 8038a12:	d00a      	beq.n	8038a2a <HAL_PWREx_ConfigSupply+0x2a>
+#else
+  if ((PWR->CR3 & (PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)) != (PWR_CR3_SMPSEN | PWR_CR3_LDOEN))
+#endif /* defined (PWR_FLAG_SCUEN) */
+  {
+    /* Check supply configuration */
+    if ((PWR->CR3 & PWR_SUPPLY_CONFIG_MASK) != SupplySource)
+ 8038a14:	4b16      	ldr	r3, [pc, #88]	@ (8038a70 <HAL_PWREx_ConfigSupply+0x70>)
+ 8038a16:	68db      	ldr	r3, [r3, #12]
+ 8038a18:	f003 0307 	and.w	r3, r3, #7
+ 8038a1c:	687a      	ldr	r2, [r7, #4]
+ 8038a1e:	429a      	cmp	r2, r3
+ 8038a20:	d001      	beq.n	8038a26 <HAL_PWREx_ConfigSupply+0x26>
+    {
+      /* Supply configuration update locked, can't apply a new supply config */
+      return HAL_ERROR;
+ 8038a22:	2301      	movs	r3, #1
+ 8038a24:	e01f      	b.n	8038a66 <HAL_PWREx_ConfigSupply+0x66>
+    else
+    {
+      /* Supply configuration update locked, but new supply configuration
+         matches with old supply configuration : nothing to do
+      */
+      return HAL_OK;
+ 8038a26:	2300      	movs	r3, #0
+ 8038a28:	e01d      	b.n	8038a66 <HAL_PWREx_ConfigSupply+0x66>
+    }
+  }
+
+  /* Set the power supply configuration */
+  MODIFY_REG (PWR->CR3, PWR_SUPPLY_CONFIG_MASK, SupplySource);
+ 8038a2a:	4b11      	ldr	r3, [pc, #68]	@ (8038a70 <HAL_PWREx_ConfigSupply+0x70>)
+ 8038a2c:	68db      	ldr	r3, [r3, #12]
+ 8038a2e:	f023 0207 	bic.w	r2, r3, #7
+ 8038a32:	490f      	ldr	r1, [pc, #60]	@ (8038a70 <HAL_PWREx_ConfigSupply+0x70>)
+ 8038a34:	687b      	ldr	r3, [r7, #4]
+ 8038a36:	4313      	orrs	r3, r2
+ 8038a38:	60cb      	str	r3, [r1, #12]
+
+  /* Get tick */
+  tickstart = HAL_GetTick ();
+ 8038a3a:	f7f8 ff79 	bl	8031930 <HAL_GetTick>
+ 8038a3e:	60f8      	str	r0, [r7, #12]
+
+  /* Wait till voltage level flag is set */
+  while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U)
+ 8038a40:	e009      	b.n	8038a56 <HAL_PWREx_ConfigSupply+0x56>
+  {
+    if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY)
+ 8038a42:	f7f8 ff75 	bl	8031930 <HAL_GetTick>
+ 8038a46:	4602      	mov	r2, r0
+ 8038a48:	68fb      	ldr	r3, [r7, #12]
+ 8038a4a:	1ad3      	subs	r3, r2, r3
+ 8038a4c:	f5b3 7f7a 	cmp.w	r3, #1000	@ 0x3e8
+ 8038a50:	d901      	bls.n	8038a56 <HAL_PWREx_ConfigSupply+0x56>
+    {
+      return HAL_ERROR;
+ 8038a52:	2301      	movs	r3, #1
+ 8038a54:	e007      	b.n	8038a66 <HAL_PWREx_ConfigSupply+0x66>
+  while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U)
+ 8038a56:	4b06      	ldr	r3, [pc, #24]	@ (8038a70 <HAL_PWREx_ConfigSupply+0x70>)
+ 8038a58:	685b      	ldr	r3, [r3, #4]
+ 8038a5a:	f403 5300 	and.w	r3, r3, #8192	@ 0x2000
+ 8038a5e:	f5b3 5f00 	cmp.w	r3, #8192	@ 0x2000
+ 8038a62:	d1ee      	bne.n	8038a42 <HAL_PWREx_ConfigSupply+0x42>
+      }
+    }
+  }
+#endif /* defined (SMPS) */
+
+  return HAL_OK;
+ 8038a64:	2300      	movs	r3, #0
+}
+ 8038a66:	4618      	mov	r0, r3
+ 8038a68:	3710      	adds	r7, #16
+ 8038a6a:	46bd      	mov	sp, r7
+ 8038a6c:	bd80      	pop	{r7, pc}
+ 8038a6e:	bf00      	nop
+ 8038a70:	58024800 	.word	0x58024800
+
+08038a74 <HAL_QSPI_Init>:
+  *        in the QSPI_InitTypeDef and initialize the associated handle.
+  * @param hqspi QSPI handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
+{
+ 8038a74:	b580      	push	{r7, lr}
+ 8038a76:	b086      	sub	sp, #24
+ 8038a78:	af02      	add	r7, sp, #8
+ 8038a7a:	6078      	str	r0, [r7, #4]
+  HAL_StatusTypeDef status;
+  uint32_t tickstart = HAL_GetTick();
+ 8038a7c:	f7f8 ff58 	bl	8031930 <HAL_GetTick>
+ 8038a80:	60f8      	str	r0, [r7, #12]
+
+  /* Check the QSPI handle allocation */
+  if(hqspi == NULL)
+ 8038a82:	687b      	ldr	r3, [r7, #4]
+ 8038a84:	2b00      	cmp	r3, #0
+ 8038a86:	d101      	bne.n	8038a8c <HAL_QSPI_Init+0x18>
+  {
+    return HAL_ERROR;
+ 8038a88:	2301      	movs	r3, #1
+ 8038a8a:	e05f      	b.n	8038b4c <HAL_QSPI_Init+0xd8>
+  if (hqspi->Init.DualFlash != QSPI_DUALFLASH_ENABLE )
+  {
+    assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID));
+  }
+
+  if(hqspi->State == HAL_QSPI_STATE_RESET)
+ 8038a8c:	687b      	ldr	r3, [r7, #4]
+ 8038a8e:	f893 3041 	ldrb.w	r3, [r3, #65]	@ 0x41
+ 8038a92:	b2db      	uxtb	r3, r3
+ 8038a94:	2b00      	cmp	r3, #0
+ 8038a96:	d107      	bne.n	8038aa8 <HAL_QSPI_Init+0x34>
+
+    /* Init the low level hardware */
+    hqspi->MspInitCallback(hqspi);
+#else
+    /* Init the low level hardware : GPIO, CLOCK */
+    HAL_QSPI_MspInit(hqspi);
+ 8038a98:	6878      	ldr	r0, [r7, #4]
+ 8038a9a:	f7f7 fa77 	bl	802ff8c <HAL_QSPI_MspInit>
+#endif
+
+    /* Configure the default timeout for the QSPI memory access */
+    HAL_QSPI_SetTimeout(hqspi, HAL_QSPI_TIMEOUT_DEFAULT_VALUE);
+ 8038a9e:	f241 3188 	movw	r1, #5000	@ 0x1388
+ 8038aa2:	6878      	ldr	r0, [r7, #4]
+ 8038aa4:	f000 fa64 	bl	8038f70 <HAL_QSPI_SetTimeout>
+  }
+
+  /* Configure QSPI FIFO Threshold */
+  MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES,
+ 8038aa8:	687b      	ldr	r3, [r7, #4]
+ 8038aaa:	681b      	ldr	r3, [r3, #0]
+ 8038aac:	681b      	ldr	r3, [r3, #0]
+ 8038aae:	f423 51f8 	bic.w	r1, r3, #7936	@ 0x1f00
+ 8038ab2:	687b      	ldr	r3, [r7, #4]
+ 8038ab4:	689b      	ldr	r3, [r3, #8]
+ 8038ab6:	3b01      	subs	r3, #1
+ 8038ab8:	021a      	lsls	r2, r3, #8
+ 8038aba:	687b      	ldr	r3, [r7, #4]
+ 8038abc:	681b      	ldr	r3, [r3, #0]
+ 8038abe:	430a      	orrs	r2, r1
+ 8038ac0:	601a      	str	r2, [r3, #0]
+             ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos));
+
+  /* Wait till BUSY flag reset */
+  status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
+ 8038ac2:	687b      	ldr	r3, [r7, #4]
+ 8038ac4:	6c9b      	ldr	r3, [r3, #72]	@ 0x48
+ 8038ac6:	9300      	str	r3, [sp, #0]
+ 8038ac8:	68fb      	ldr	r3, [r7, #12]
+ 8038aca:	2200      	movs	r2, #0
+ 8038acc:	2120      	movs	r1, #32
+ 8038ace:	6878      	ldr	r0, [r7, #4]
+ 8038ad0:	f000 fa8f 	bl	8038ff2 <QSPI_WaitFlagStateUntilTimeout>
+ 8038ad4:	4603      	mov	r3, r0
+ 8038ad6:	72fb      	strb	r3, [r7, #11]
+
+  if(status == HAL_OK)
+ 8038ad8:	7afb      	ldrb	r3, [r7, #11]
+ 8038ada:	2b00      	cmp	r3, #0
+ 8038adc:	d135      	bne.n	8038b4a <HAL_QSPI_Init+0xd6>
+  {
+    /* Configure QSPI Clock Prescaler and Sample Shift */
+    MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUADSPI_CR_DFM),
+ 8038ade:	687b      	ldr	r3, [r7, #4]
+ 8038ae0:	681b      	ldr	r3, [r3, #0]
+ 8038ae2:	681a      	ldr	r2, [r3, #0]
+ 8038ae4:	4b1b      	ldr	r3, [pc, #108]	@ (8038b54 <HAL_QSPI_Init+0xe0>)
+ 8038ae6:	4013      	ands	r3, r2
+ 8038ae8:	687a      	ldr	r2, [r7, #4]
+ 8038aea:	6852      	ldr	r2, [r2, #4]
+ 8038aec:	0611      	lsls	r1, r2, #24
+ 8038aee:	687a      	ldr	r2, [r7, #4]
+ 8038af0:	68d2      	ldr	r2, [r2, #12]
+ 8038af2:	4311      	orrs	r1, r2
+ 8038af4:	687a      	ldr	r2, [r7, #4]
+ 8038af6:	69d2      	ldr	r2, [r2, #28]
+ 8038af8:	4311      	orrs	r1, r2
+ 8038afa:	687a      	ldr	r2, [r7, #4]
+ 8038afc:	6a12      	ldr	r2, [r2, #32]
+ 8038afe:	4311      	orrs	r1, r2
+ 8038b00:	687a      	ldr	r2, [r7, #4]
+ 8038b02:	6812      	ldr	r2, [r2, #0]
+ 8038b04:	430b      	orrs	r3, r1
+ 8038b06:	6013      	str	r3, [r2, #0]
+               ((hqspi->Init.ClockPrescaler << QUADSPI_CR_PRESCALER_Pos) |
+                hqspi->Init.SampleShifting  | hqspi->Init.FlashID | hqspi->Init.DualFlash));
+
+    /* Configure QSPI Flash Size, CS High Time and Clock Mode */
+    MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE),
+ 8038b08:	687b      	ldr	r3, [r7, #4]
+ 8038b0a:	681b      	ldr	r3, [r3, #0]
+ 8038b0c:	685a      	ldr	r2, [r3, #4]
+ 8038b0e:	4b12      	ldr	r3, [pc, #72]	@ (8038b58 <HAL_QSPI_Init+0xe4>)
+ 8038b10:	4013      	ands	r3, r2
+ 8038b12:	687a      	ldr	r2, [r7, #4]
+ 8038b14:	6912      	ldr	r2, [r2, #16]
+ 8038b16:	0411      	lsls	r1, r2, #16
+ 8038b18:	687a      	ldr	r2, [r7, #4]
+ 8038b1a:	6952      	ldr	r2, [r2, #20]
+ 8038b1c:	4311      	orrs	r1, r2
+ 8038b1e:	687a      	ldr	r2, [r7, #4]
+ 8038b20:	6992      	ldr	r2, [r2, #24]
+ 8038b22:	4311      	orrs	r1, r2
+ 8038b24:	687a      	ldr	r2, [r7, #4]
+ 8038b26:	6812      	ldr	r2, [r2, #0]
+ 8038b28:	430b      	orrs	r3, r1
+ 8038b2a:	6053      	str	r3, [r2, #4]
+               ((hqspi->Init.FlashSize << QUADSPI_DCR_FSIZE_Pos) |
+                hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode));
+
+    /* Enable the QSPI peripheral */
+    __HAL_QSPI_ENABLE(hqspi);
+ 8038b2c:	687b      	ldr	r3, [r7, #4]
+ 8038b2e:	681b      	ldr	r3, [r3, #0]
+ 8038b30:	681a      	ldr	r2, [r3, #0]
+ 8038b32:	687b      	ldr	r3, [r7, #4]
+ 8038b34:	681b      	ldr	r3, [r3, #0]
+ 8038b36:	f042 0201 	orr.w	r2, r2, #1
+ 8038b3a:	601a      	str	r2, [r3, #0]
+
+    /* Set QSPI error code to none */
+    hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
+ 8038b3c:	687b      	ldr	r3, [r7, #4]
+ 8038b3e:	2200      	movs	r2, #0
+ 8038b40:	645a      	str	r2, [r3, #68]	@ 0x44
+
+    /* Initialize the QSPI state */
+    hqspi->State = HAL_QSPI_STATE_READY;
+ 8038b42:	687b      	ldr	r3, [r7, #4]
+ 8038b44:	2201      	movs	r2, #1
+ 8038b46:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
+  }
+
+  /* Return function status */
+  return status;
+ 8038b4a:	7afb      	ldrb	r3, [r7, #11]
+}
+ 8038b4c:	4618      	mov	r0, r3
+ 8038b4e:	3710      	adds	r7, #16
+ 8038b50:	46bd      	mov	sp, r7
+ 8038b52:	bd80      	pop	{r7, pc}
+ 8038b54:	00ffff2f 	.word	0x00ffff2f
+ 8038b58:	ffe0f8fe 	.word	0xffe0f8fe
+
+08038b5c <HAL_QSPI_IRQHandler>:
+  * @brief Handle QSPI interrupt request.
+  * @param hqspi QSPI handle
+  * @retval None
+  */
+void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
+{
+ 8038b5c:	b580      	push	{r7, lr}
+ 8038b5e:	b086      	sub	sp, #24
+ 8038b60:	af00      	add	r7, sp, #0
+ 8038b62:	6078      	str	r0, [r7, #4]
+  __IO uint32_t *data_reg;
+  uint32_t flag = READ_REG(hqspi->Instance->SR);
+ 8038b64:	687b      	ldr	r3, [r7, #4]
+ 8038b66:	681b      	ldr	r3, [r3, #0]
+ 8038b68:	689b      	ldr	r3, [r3, #8]
+ 8038b6a:	617b      	str	r3, [r7, #20]
+  uint32_t itsource = READ_REG(hqspi->Instance->CR);
+ 8038b6c:	687b      	ldr	r3, [r7, #4]
+ 8038b6e:	681b      	ldr	r3, [r3, #0]
+ 8038b70:	681b      	ldr	r3, [r3, #0]
+ 8038b72:	613b      	str	r3, [r7, #16]
+
+  /* QSPI Fifo Threshold interrupt occurred ----------------------------------*/
+  if(((flag & QSPI_FLAG_FT) != 0U) && ((itsource & QSPI_IT_FT) != 0U))
+ 8038b74:	697b      	ldr	r3, [r7, #20]
+ 8038b76:	f003 0304 	and.w	r3, r3, #4
+ 8038b7a:	2b00      	cmp	r3, #0
+ 8038b7c:	d064      	beq.n	8038c48 <HAL_QSPI_IRQHandler+0xec>
+ 8038b7e:	693b      	ldr	r3, [r7, #16]
+ 8038b80:	f403 2380 	and.w	r3, r3, #262144	@ 0x40000
+ 8038b84:	2b00      	cmp	r3, #0
+ 8038b86:	d05f      	beq.n	8038c48 <HAL_QSPI_IRQHandler+0xec>
+  {
+    data_reg = &hqspi->Instance->DR;
+ 8038b88:	687b      	ldr	r3, [r7, #4]
+ 8038b8a:	681b      	ldr	r3, [r3, #0]
+ 8038b8c:	3320      	adds	r3, #32
+ 8038b8e:	60fb      	str	r3, [r7, #12]
+
+    if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
+ 8038b90:	687b      	ldr	r3, [r7, #4]
+ 8038b92:	f893 3041 	ldrb.w	r3, [r3, #65]	@ 0x41
+ 8038b96:	b2db      	uxtb	r3, r3
+ 8038b98:	2b12      	cmp	r3, #18
+ 8038b9a:	d125      	bne.n	8038be8 <HAL_QSPI_IRQHandler+0x8c>
+    {
+      /* Transmission process */
+      while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != RESET)
+ 8038b9c:	e01c      	b.n	8038bd8 <HAL_QSPI_IRQHandler+0x7c>
+      {
+        if (hqspi->TxXferCount > 0U)
+ 8038b9e:	687b      	ldr	r3, [r7, #4]
+ 8038ba0:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 8038ba2:	2b00      	cmp	r3, #0
+ 8038ba4:	d00f      	beq.n	8038bc6 <HAL_QSPI_IRQHandler+0x6a>
+        {
+          /* Fill the FIFO until the threshold is reached */
+          *((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr;
+ 8038ba6:	687b      	ldr	r3, [r7, #4]
+ 8038ba8:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 8038baa:	781a      	ldrb	r2, [r3, #0]
+ 8038bac:	68fb      	ldr	r3, [r7, #12]
+ 8038bae:	701a      	strb	r2, [r3, #0]
+          hqspi->pTxBuffPtr++;
+ 8038bb0:	687b      	ldr	r3, [r7, #4]
+ 8038bb2:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 8038bb4:	1c5a      	adds	r2, r3, #1
+ 8038bb6:	687b      	ldr	r3, [r7, #4]
+ 8038bb8:	625a      	str	r2, [r3, #36]	@ 0x24
+          hqspi->TxXferCount--;
+ 8038bba:	687b      	ldr	r3, [r7, #4]
+ 8038bbc:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 8038bbe:	1e5a      	subs	r2, r3, #1
+ 8038bc0:	687b      	ldr	r3, [r7, #4]
+ 8038bc2:	62da      	str	r2, [r3, #44]	@ 0x2c
+ 8038bc4:	e008      	b.n	8038bd8 <HAL_QSPI_IRQHandler+0x7c>
+        }
+        else
+        {
+          /* No more data available for the transfer */
+          /* Disable the QSPI FIFO Threshold Interrupt */
+          __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);
+ 8038bc6:	687b      	ldr	r3, [r7, #4]
+ 8038bc8:	681b      	ldr	r3, [r3, #0]
+ 8038bca:	681a      	ldr	r2, [r3, #0]
+ 8038bcc:	687b      	ldr	r3, [r7, #4]
+ 8038bce:	681b      	ldr	r3, [r3, #0]
+ 8038bd0:	f422 2280 	bic.w	r2, r2, #262144	@ 0x40000
+ 8038bd4:	601a      	str	r2, [r3, #0]
+          break;
+ 8038bd6:	e033      	b.n	8038c40 <HAL_QSPI_IRQHandler+0xe4>
+      while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != RESET)
+ 8038bd8:	687b      	ldr	r3, [r7, #4]
+ 8038bda:	681b      	ldr	r3, [r3, #0]
+ 8038bdc:	689b      	ldr	r3, [r3, #8]
+ 8038bde:	f003 0304 	and.w	r3, r3, #4
+ 8038be2:	2b00      	cmp	r3, #0
+ 8038be4:	d1db      	bne.n	8038b9e <HAL_QSPI_IRQHandler+0x42>
+ 8038be6:	e02b      	b.n	8038c40 <HAL_QSPI_IRQHandler+0xe4>
+        }
+      }
+    }
+    else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
+ 8038be8:	687b      	ldr	r3, [r7, #4]
+ 8038bea:	f893 3041 	ldrb.w	r3, [r3, #65]	@ 0x41
+ 8038bee:	b2db      	uxtb	r3, r3
+ 8038bf0:	2b22      	cmp	r3, #34	@ 0x22
+ 8038bf2:	d125      	bne.n	8038c40 <HAL_QSPI_IRQHandler+0xe4>
+    {
+      /* Receiving Process */
+      while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != RESET)
+ 8038bf4:	e01d      	b.n	8038c32 <HAL_QSPI_IRQHandler+0xd6>
+      {
+        if (hqspi->RxXferCount > 0U)
+ 8038bf6:	687b      	ldr	r3, [r7, #4]
+ 8038bf8:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
+ 8038bfa:	2b00      	cmp	r3, #0
+ 8038bfc:	d010      	beq.n	8038c20 <HAL_QSPI_IRQHandler+0xc4>
+        {
+          /* Read the FIFO until the threshold is reached */
+          *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg);
+ 8038bfe:	687b      	ldr	r3, [r7, #4]
+ 8038c00:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
+ 8038c02:	68fa      	ldr	r2, [r7, #12]
+ 8038c04:	7812      	ldrb	r2, [r2, #0]
+ 8038c06:	b2d2      	uxtb	r2, r2
+ 8038c08:	701a      	strb	r2, [r3, #0]
+          hqspi->pRxBuffPtr++;
+ 8038c0a:	687b      	ldr	r3, [r7, #4]
+ 8038c0c:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
+ 8038c0e:	1c5a      	adds	r2, r3, #1
+ 8038c10:	687b      	ldr	r3, [r7, #4]
+ 8038c12:	631a      	str	r2, [r3, #48]	@ 0x30
+          hqspi->RxXferCount--;
+ 8038c14:	687b      	ldr	r3, [r7, #4]
+ 8038c16:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
+ 8038c18:	1e5a      	subs	r2, r3, #1
+ 8038c1a:	687b      	ldr	r3, [r7, #4]
+ 8038c1c:	639a      	str	r2, [r3, #56]	@ 0x38
+ 8038c1e:	e008      	b.n	8038c32 <HAL_QSPI_IRQHandler+0xd6>
+        }
+        else
+        {
+          /* All data have been received for the transfer */
+          /* Disable the QSPI FIFO Threshold Interrupt */
+          __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);
+ 8038c20:	687b      	ldr	r3, [r7, #4]
+ 8038c22:	681b      	ldr	r3, [r3, #0]
+ 8038c24:	681a      	ldr	r2, [r3, #0]
+ 8038c26:	687b      	ldr	r3, [r7, #4]
+ 8038c28:	681b      	ldr	r3, [r3, #0]
+ 8038c2a:	f422 2280 	bic.w	r2, r2, #262144	@ 0x40000
+ 8038c2e:	601a      	str	r2, [r3, #0]
+          break;
+ 8038c30:	e006      	b.n	8038c40 <HAL_QSPI_IRQHandler+0xe4>
+      while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != RESET)
+ 8038c32:	687b      	ldr	r3, [r7, #4]
+ 8038c34:	681b      	ldr	r3, [r3, #0]
+ 8038c36:	689b      	ldr	r3, [r3, #8]
+ 8038c38:	f003 0304 	and.w	r3, r3, #4
+ 8038c3c:	2b00      	cmp	r3, #0
+ 8038c3e:	d1da      	bne.n	8038bf6 <HAL_QSPI_IRQHandler+0x9a>
+
+    /* FIFO Threshold callback */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+    hqspi->FifoThresholdCallback(hqspi);
+#else
+    HAL_QSPI_FifoThresholdCallback(hqspi);
+ 8038c40:	6878      	ldr	r0, [r7, #4]
+ 8038c42:	f000 f977 	bl	8038f34 <HAL_QSPI_FifoThresholdCallback>
+ 8038c46:	e13c      	b.n	8038ec2 <HAL_QSPI_IRQHandler+0x366>
+#endif
+  }
+
+  /* QSPI Transfer Complete interrupt occurred -------------------------------*/
+  else if(((flag & QSPI_FLAG_TC) != 0U) && ((itsource & QSPI_IT_TC) != 0U))
+ 8038c48:	697b      	ldr	r3, [r7, #20]
+ 8038c4a:	f003 0302 	and.w	r3, r3, #2
+ 8038c4e:	2b00      	cmp	r3, #0
+ 8038c50:	f000 80b0 	beq.w	8038db4 <HAL_QSPI_IRQHandler+0x258>
+ 8038c54:	693b      	ldr	r3, [r7, #16]
+ 8038c56:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
+ 8038c5a:	2b00      	cmp	r3, #0
+ 8038c5c:	f000 80aa 	beq.w	8038db4 <HAL_QSPI_IRQHandler+0x258>
+  {
+    /* Clear interrupt */
+    WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TC);
+ 8038c60:	687b      	ldr	r3, [r7, #4]
+ 8038c62:	681b      	ldr	r3, [r3, #0]
+ 8038c64:	2202      	movs	r2, #2
+ 8038c66:	60da      	str	r2, [r3, #12]
+
+    /* Disable the QSPI FIFO Threshold, Transfer Error and Transfer complete Interrupts */
+    __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
+ 8038c68:	687b      	ldr	r3, [r7, #4]
+ 8038c6a:	681b      	ldr	r3, [r3, #0]
+ 8038c6c:	681a      	ldr	r2, [r3, #0]
+ 8038c6e:	687b      	ldr	r3, [r7, #4]
+ 8038c70:	681b      	ldr	r3, [r3, #0]
+ 8038c72:	f422 22e0 	bic.w	r2, r2, #458752	@ 0x70000
+ 8038c76:	601a      	str	r2, [r3, #0]
+
+    /* Transfer complete callback */
+    if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
+ 8038c78:	687b      	ldr	r3, [r7, #4]
+ 8038c7a:	f893 3041 	ldrb.w	r3, [r3, #65]	@ 0x41
+ 8038c7e:	b2db      	uxtb	r3, r3
+ 8038c80:	2b12      	cmp	r3, #18
+ 8038c82:	d120      	bne.n	8038cc6 <HAL_QSPI_IRQHandler+0x16a>
+    {
+      if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
+ 8038c84:	687b      	ldr	r3, [r7, #4]
+ 8038c86:	681b      	ldr	r3, [r3, #0]
+ 8038c88:	681b      	ldr	r3, [r3, #0]
+ 8038c8a:	f003 0304 	and.w	r3, r3, #4
+ 8038c8e:	2b00      	cmp	r3, #0
+ 8038c90:	d011      	beq.n	8038cb6 <HAL_QSPI_IRQHandler+0x15a>
+      {
+        /* Disable using MDMA by clearing DMAEN, note that DMAEN bit is "reserved"
+           but no impact on H7 HW and it minimize the cost in the footprint */
+        CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+ 8038c92:	687b      	ldr	r3, [r7, #4]
+ 8038c94:	681b      	ldr	r3, [r3, #0]
+ 8038c96:	681a      	ldr	r2, [r3, #0]
+ 8038c98:	687b      	ldr	r3, [r7, #4]
+ 8038c9a:	681b      	ldr	r3, [r3, #0]
+ 8038c9c:	f022 0204 	bic.w	r2, r2, #4
+ 8038ca0:	601a      	str	r2, [r3, #0]
+
+        /* Disable the MDMA channel */
+        __HAL_MDMA_DISABLE(hqspi->hmdma);
+ 8038ca2:	687b      	ldr	r3, [r7, #4]
+ 8038ca4:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 8038ca6:	681b      	ldr	r3, [r3, #0]
+ 8038ca8:	68da      	ldr	r2, [r3, #12]
+ 8038caa:	687b      	ldr	r3, [r7, #4]
+ 8038cac:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 8038cae:	681b      	ldr	r3, [r3, #0]
+ 8038cb0:	f022 0201 	bic.w	r2, r2, #1
+ 8038cb4:	60da      	str	r2, [r3, #12]
+      }
+
+
+      /* Change state of QSPI */
+      hqspi->State = HAL_QSPI_STATE_READY;
+ 8038cb6:	687b      	ldr	r3, [r7, #4]
+ 8038cb8:	2201      	movs	r2, #1
+ 8038cba:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
+
+      /* TX Complete callback */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+      hqspi->TxCpltCallback(hqspi);
+#else
+      HAL_QSPI_TxCpltCallback(hqspi);
+ 8038cbe:	6878      	ldr	r0, [r7, #4]
+ 8038cc0:	f000 f92e 	bl	8038f20 <HAL_QSPI_TxCpltCallback>
+    if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
+ 8038cc4:	e0fa      	b.n	8038ebc <HAL_QSPI_IRQHandler+0x360>
+#endif
+    }
+    else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
+ 8038cc6:	687b      	ldr	r3, [r7, #4]
+ 8038cc8:	f893 3041 	ldrb.w	r3, [r3, #65]	@ 0x41
+ 8038ccc:	b2db      	uxtb	r3, r3
+ 8038cce:	2b22      	cmp	r3, #34	@ 0x22
+ 8038cd0:	d143      	bne.n	8038d5a <HAL_QSPI_IRQHandler+0x1fe>
+    {
+      if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
+ 8038cd2:	687b      	ldr	r3, [r7, #4]
+ 8038cd4:	681b      	ldr	r3, [r3, #0]
+ 8038cd6:	681b      	ldr	r3, [r3, #0]
+ 8038cd8:	f003 0304 	and.w	r3, r3, #4
+ 8038cdc:	2b00      	cmp	r3, #0
+ 8038cde:	d012      	beq.n	8038d06 <HAL_QSPI_IRQHandler+0x1aa>
+      {
+        /* Disable using MDMA by clearing DMAEN, note that DMAEN bit is "reserved"
+           but no impact on H7 HW and it minimize the cost in the footprint */
+        CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+ 8038ce0:	687b      	ldr	r3, [r7, #4]
+ 8038ce2:	681b      	ldr	r3, [r3, #0]
+ 8038ce4:	681a      	ldr	r2, [r3, #0]
+ 8038ce6:	687b      	ldr	r3, [r7, #4]
+ 8038ce8:	681b      	ldr	r3, [r3, #0]
+ 8038cea:	f022 0204 	bic.w	r2, r2, #4
+ 8038cee:	601a      	str	r2, [r3, #0]
+
+        /* Disable the MDMA channel */
+        __HAL_MDMA_DISABLE(hqspi->hmdma);
+ 8038cf0:	687b      	ldr	r3, [r7, #4]
+ 8038cf2:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 8038cf4:	681b      	ldr	r3, [r3, #0]
+ 8038cf6:	68da      	ldr	r2, [r3, #12]
+ 8038cf8:	687b      	ldr	r3, [r7, #4]
+ 8038cfa:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 8038cfc:	681b      	ldr	r3, [r3, #0]
+ 8038cfe:	f022 0201 	bic.w	r2, r2, #1
+ 8038d02:	60da      	str	r2, [r3, #12]
+ 8038d04:	e021      	b.n	8038d4a <HAL_QSPI_IRQHandler+0x1ee>
+      }
+      else
+      {
+        data_reg = &hqspi->Instance->DR;
+ 8038d06:	687b      	ldr	r3, [r7, #4]
+ 8038d08:	681b      	ldr	r3, [r3, #0]
+ 8038d0a:	3320      	adds	r3, #32
+ 8038d0c:	60fb      	str	r3, [r7, #12]
+        while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0U)
+ 8038d0e:	e013      	b.n	8038d38 <HAL_QSPI_IRQHandler+0x1dc>
+        {
+          if (hqspi->RxXferCount > 0U)
+ 8038d10:	687b      	ldr	r3, [r7, #4]
+ 8038d12:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
+ 8038d14:	2b00      	cmp	r3, #0
+ 8038d16:	d017      	beq.n	8038d48 <HAL_QSPI_IRQHandler+0x1ec>
+          {
+            /* Read the last data received in the FIFO until it is empty */
+            *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg);
+ 8038d18:	687b      	ldr	r3, [r7, #4]
+ 8038d1a:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
+ 8038d1c:	68fa      	ldr	r2, [r7, #12]
+ 8038d1e:	7812      	ldrb	r2, [r2, #0]
+ 8038d20:	b2d2      	uxtb	r2, r2
+ 8038d22:	701a      	strb	r2, [r3, #0]
+            hqspi->pRxBuffPtr++;
+ 8038d24:	687b      	ldr	r3, [r7, #4]
+ 8038d26:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
+ 8038d28:	1c5a      	adds	r2, r3, #1
+ 8038d2a:	687b      	ldr	r3, [r7, #4]
+ 8038d2c:	631a      	str	r2, [r3, #48]	@ 0x30
+            hqspi->RxXferCount--;
+ 8038d2e:	687b      	ldr	r3, [r7, #4]
+ 8038d30:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
+ 8038d32:	1e5a      	subs	r2, r3, #1
+ 8038d34:	687b      	ldr	r3, [r7, #4]
+ 8038d36:	639a      	str	r2, [r3, #56]	@ 0x38
+        while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0U)
+ 8038d38:	687b      	ldr	r3, [r7, #4]
+ 8038d3a:	681b      	ldr	r3, [r3, #0]
+ 8038d3c:	689b      	ldr	r3, [r3, #8]
+ 8038d3e:	f403 537c 	and.w	r3, r3, #16128	@ 0x3f00
+ 8038d42:	2b00      	cmp	r3, #0
+ 8038d44:	d1e4      	bne.n	8038d10 <HAL_QSPI_IRQHandler+0x1b4>
+ 8038d46:	e000      	b.n	8038d4a <HAL_QSPI_IRQHandler+0x1ee>
+          }
+          else
+          {
+            /* All data have been received for the transfer */
+            break;
+ 8038d48:	bf00      	nop
+        }
+      }
+
+
+      /* Change state of QSPI */
+      hqspi->State = HAL_QSPI_STATE_READY;
+ 8038d4a:	687b      	ldr	r3, [r7, #4]
+ 8038d4c:	2201      	movs	r2, #1
+ 8038d4e:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
+
+      /* RX Complete callback */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+      hqspi->RxCpltCallback(hqspi);
+#else
+      HAL_QSPI_RxCpltCallback(hqspi);
+ 8038d52:	6878      	ldr	r0, [r7, #4]
+ 8038d54:	f000 f8da 	bl	8038f0c <HAL_QSPI_RxCpltCallback>
+    if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
+ 8038d58:	e0b0      	b.n	8038ebc <HAL_QSPI_IRQHandler+0x360>
+#endif
+    }
+    else if(hqspi->State == HAL_QSPI_STATE_BUSY)
+ 8038d5a:	687b      	ldr	r3, [r7, #4]
+ 8038d5c:	f893 3041 	ldrb.w	r3, [r3, #65]	@ 0x41
+ 8038d60:	b2db      	uxtb	r3, r3
+ 8038d62:	2b02      	cmp	r3, #2
+ 8038d64:	d107      	bne.n	8038d76 <HAL_QSPI_IRQHandler+0x21a>
+    {
+      /* Change state of QSPI */
+      hqspi->State = HAL_QSPI_STATE_READY;
+ 8038d66:	687b      	ldr	r3, [r7, #4]
+ 8038d68:	2201      	movs	r2, #1
+ 8038d6a:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
+
+      /* Command Complete callback */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+      hqspi->CmdCpltCallback(hqspi);
+#else
+      HAL_QSPI_CmdCpltCallback(hqspi);
+ 8038d6e:	6878      	ldr	r0, [r7, #4]
+ 8038d70:	f000 f8c2 	bl	8038ef8 <HAL_QSPI_CmdCpltCallback>
+    if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
+ 8038d74:	e0a2      	b.n	8038ebc <HAL_QSPI_IRQHandler+0x360>
+#endif
+    }
+    else if(hqspi->State == HAL_QSPI_STATE_ABORT)
+ 8038d76:	687b      	ldr	r3, [r7, #4]
+ 8038d78:	f893 3041 	ldrb.w	r3, [r3, #65]	@ 0x41
+ 8038d7c:	b2db      	uxtb	r3, r3
+ 8038d7e:	2b08      	cmp	r3, #8
+ 8038d80:	f040 809c 	bne.w	8038ebc <HAL_QSPI_IRQHandler+0x360>
+    {
+      /* Reset functional mode configuration to indirect write mode by default */
+      CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE);
+ 8038d84:	687b      	ldr	r3, [r7, #4]
+ 8038d86:	681b      	ldr	r3, [r3, #0]
+ 8038d88:	695a      	ldr	r2, [r3, #20]
+ 8038d8a:	687b      	ldr	r3, [r7, #4]
+ 8038d8c:	681b      	ldr	r3, [r3, #0]
+ 8038d8e:	f022 6240 	bic.w	r2, r2, #201326592	@ 0xc000000
+ 8038d92:	615a      	str	r2, [r3, #20]
+
+      /* Change state of QSPI */
+      hqspi->State = HAL_QSPI_STATE_READY;
+ 8038d94:	687b      	ldr	r3, [r7, #4]
+ 8038d96:	2201      	movs	r2, #1
+ 8038d98:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
+
+      if (hqspi->ErrorCode == HAL_QSPI_ERROR_NONE)
+ 8038d9c:	687b      	ldr	r3, [r7, #4]
+ 8038d9e:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
+ 8038da0:	2b00      	cmp	r3, #0
+ 8038da2:	d103      	bne.n	8038dac <HAL_QSPI_IRQHandler+0x250>
+
+        /* Abort Complete callback */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+        hqspi->AbortCpltCallback(hqspi);
+#else
+        HAL_QSPI_AbortCpltCallback(hqspi);
+ 8038da4:	6878      	ldr	r0, [r7, #4]
+ 8038da6:	f000 f89d 	bl	8038ee4 <HAL_QSPI_AbortCpltCallback>
+    if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
+ 8038daa:	e087      	b.n	8038ebc <HAL_QSPI_IRQHandler+0x360>
+
+        /* Error callback */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+        hqspi->ErrorCallback(hqspi);
+#else
+        HAL_QSPI_ErrorCallback(hqspi);
+ 8038dac:	6878      	ldr	r0, [r7, #4]
+ 8038dae:	f000 f88f 	bl	8038ed0 <HAL_QSPI_ErrorCallback>
+    if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
+ 8038db2:	e083      	b.n	8038ebc <HAL_QSPI_IRQHandler+0x360>
+     /* Nothing to do */
+    }
+  }
+
+  /* QSPI Status Match interrupt occurred ------------------------------------*/
+  else if(((flag & QSPI_FLAG_SM) != 0U) && ((itsource & QSPI_IT_SM) != 0U))
+ 8038db4:	697b      	ldr	r3, [r7, #20]
+ 8038db6:	f003 0308 	and.w	r3, r3, #8
+ 8038dba:	2b00      	cmp	r3, #0
+ 8038dbc:	d01f      	beq.n	8038dfe <HAL_QSPI_IRQHandler+0x2a2>
+ 8038dbe:	693b      	ldr	r3, [r7, #16]
+ 8038dc0:	f403 2300 	and.w	r3, r3, #524288	@ 0x80000
+ 8038dc4:	2b00      	cmp	r3, #0
+ 8038dc6:	d01a      	beq.n	8038dfe <HAL_QSPI_IRQHandler+0x2a2>
+  {
+    /* Clear interrupt */
+    WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_SM);
+ 8038dc8:	687b      	ldr	r3, [r7, #4]
+ 8038dca:	681b      	ldr	r3, [r3, #0]
+ 8038dcc:	2208      	movs	r2, #8
+ 8038dce:	60da      	str	r2, [r3, #12]
+
+    /* Check if the automatic poll mode stop is activated */
+    if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0U)
+ 8038dd0:	687b      	ldr	r3, [r7, #4]
+ 8038dd2:	681b      	ldr	r3, [r3, #0]
+ 8038dd4:	681b      	ldr	r3, [r3, #0]
+ 8038dd6:	f403 0380 	and.w	r3, r3, #4194304	@ 0x400000
+ 8038dda:	2b00      	cmp	r3, #0
+ 8038ddc:	d00b      	beq.n	8038df6 <HAL_QSPI_IRQHandler+0x29a>
+    {
+      /* Disable the QSPI Transfer Error and Status Match Interrupts */
+      __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));
+ 8038dde:	687b      	ldr	r3, [r7, #4]
+ 8038de0:	681b      	ldr	r3, [r3, #0]
+ 8038de2:	681a      	ldr	r2, [r3, #0]
+ 8038de4:	687b      	ldr	r3, [r7, #4]
+ 8038de6:	681b      	ldr	r3, [r3, #0]
+ 8038de8:	f422 2210 	bic.w	r2, r2, #589824	@ 0x90000
+ 8038dec:	601a      	str	r2, [r3, #0]
+
+      /* Change state of QSPI */
+      hqspi->State = HAL_QSPI_STATE_READY;
+ 8038dee:	687b      	ldr	r3, [r7, #4]
+ 8038df0:	2201      	movs	r2, #1
+ 8038df2:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
+
+    /* Status match callback */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+    hqspi->StatusMatchCallback(hqspi);
+#else
+    HAL_QSPI_StatusMatchCallback(hqspi);
+ 8038df6:	6878      	ldr	r0, [r7, #4]
+ 8038df8:	f000 f8a6 	bl	8038f48 <HAL_QSPI_StatusMatchCallback>
+ 8038dfc:	e061      	b.n	8038ec2 <HAL_QSPI_IRQHandler+0x366>
+#endif
+  }
+
+  /* QSPI Transfer Error interrupt occurred ----------------------------------*/
+  else if(((flag & QSPI_FLAG_TE) != 0U) && ((itsource & QSPI_IT_TE) != 0U))
+ 8038dfe:	697b      	ldr	r3, [r7, #20]
+ 8038e00:	f003 0301 	and.w	r3, r3, #1
+ 8038e04:	2b00      	cmp	r3, #0
+ 8038e06:	d047      	beq.n	8038e98 <HAL_QSPI_IRQHandler+0x33c>
+ 8038e08:	693b      	ldr	r3, [r7, #16]
+ 8038e0a:	f403 3380 	and.w	r3, r3, #65536	@ 0x10000
+ 8038e0e:	2b00      	cmp	r3, #0
+ 8038e10:	d042      	beq.n	8038e98 <HAL_QSPI_IRQHandler+0x33c>
+  {
+    /* Clear interrupt */
+    WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TE);
+ 8038e12:	687b      	ldr	r3, [r7, #4]
+ 8038e14:	681b      	ldr	r3, [r3, #0]
+ 8038e16:	2201      	movs	r2, #1
+ 8038e18:	60da      	str	r2, [r3, #12]
+
+    /* Disable all the QSPI Interrupts */
+    __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
+ 8038e1a:	687b      	ldr	r3, [r7, #4]
+ 8038e1c:	681b      	ldr	r3, [r3, #0]
+ 8038e1e:	681a      	ldr	r2, [r3, #0]
+ 8038e20:	687b      	ldr	r3, [r7, #4]
+ 8038e22:	681b      	ldr	r3, [r3, #0]
+ 8038e24:	f422 2270 	bic.w	r2, r2, #983040	@ 0xf0000
+ 8038e28:	601a      	str	r2, [r3, #0]
+
+    /* Set error code */
+    hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER;
+ 8038e2a:	687b      	ldr	r3, [r7, #4]
+ 8038e2c:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
+ 8038e2e:	f043 0202 	orr.w	r2, r3, #2
+ 8038e32:	687b      	ldr	r3, [r7, #4]
+ 8038e34:	645a      	str	r2, [r3, #68]	@ 0x44
+
+    if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
+ 8038e36:	687b      	ldr	r3, [r7, #4]
+ 8038e38:	681b      	ldr	r3, [r3, #0]
+ 8038e3a:	681b      	ldr	r3, [r3, #0]
+ 8038e3c:	f003 0304 	and.w	r3, r3, #4
+ 8038e40:	2b00      	cmp	r3, #0
+ 8038e42:	d021      	beq.n	8038e88 <HAL_QSPI_IRQHandler+0x32c>
+    {
+      /* Disable using MDMA by clearing DMAEN, note that DMAEN bit is "reserved"
+         but no impact on H7 HW and it minimize the cost in the footprint */
+      CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
+ 8038e44:	687b      	ldr	r3, [r7, #4]
+ 8038e46:	681b      	ldr	r3, [r3, #0]
+ 8038e48:	681a      	ldr	r2, [r3, #0]
+ 8038e4a:	687b      	ldr	r3, [r7, #4]
+ 8038e4c:	681b      	ldr	r3, [r3, #0]
+ 8038e4e:	f022 0204 	bic.w	r2, r2, #4
+ 8038e52:	601a      	str	r2, [r3, #0]
+
+      /* Disable the MDMA channel */
+      hqspi->hmdma->XferAbortCallback = QSPI_DMAAbortCplt;
+ 8038e54:	687b      	ldr	r3, [r7, #4]
+ 8038e56:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 8038e58:	4a1c      	ldr	r2, [pc, #112]	@ (8038ecc <HAL_QSPI_IRQHandler+0x370>)
+ 8038e5a:	659a      	str	r2, [r3, #88]	@ 0x58
+      if (HAL_MDMA_Abort_IT(hqspi->hmdma) != HAL_OK)
+ 8038e5c:	687b      	ldr	r3, [r7, #4]
+ 8038e5e:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 8038e60:	4618      	mov	r0, r3
+ 8038e62:	f7ff fda5 	bl	80389b0 <HAL_MDMA_Abort_IT>
+ 8038e66:	4603      	mov	r3, r0
+ 8038e68:	2b00      	cmp	r3, #0
+ 8038e6a:	d029      	beq.n	8038ec0 <HAL_QSPI_IRQHandler+0x364>
+      {
+        /* Set error code to DMA */
+        hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
+ 8038e6c:	687b      	ldr	r3, [r7, #4]
+ 8038e6e:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
+ 8038e70:	f043 0204 	orr.w	r2, r3, #4
+ 8038e74:	687b      	ldr	r3, [r7, #4]
+ 8038e76:	645a      	str	r2, [r3, #68]	@ 0x44
+
+        /* Change state of QSPI */
+        hqspi->State = HAL_QSPI_STATE_READY;
+ 8038e78:	687b      	ldr	r3, [r7, #4]
+ 8038e7a:	2201      	movs	r2, #1
+ 8038e7c:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
+
+        /* Error callback */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+        hqspi->ErrorCallback(hqspi);
+#else
+        HAL_QSPI_ErrorCallback(hqspi);
+ 8038e80:	6878      	ldr	r0, [r7, #4]
+ 8038e82:	f000 f825 	bl	8038ed0 <HAL_QSPI_ErrorCallback>
+    if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
+ 8038e86:	e01b      	b.n	8038ec0 <HAL_QSPI_IRQHandler+0x364>
+      }
+    }
+    else
+    {
+      /* Change state of QSPI */
+      hqspi->State = HAL_QSPI_STATE_READY;
+ 8038e88:	687b      	ldr	r3, [r7, #4]
+ 8038e8a:	2201      	movs	r2, #1
+ 8038e8c:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
+
+      /* Error callback */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+      hqspi->ErrorCallback(hqspi);
+#else
+      HAL_QSPI_ErrorCallback(hqspi);
+ 8038e90:	6878      	ldr	r0, [r7, #4]
+ 8038e92:	f000 f81d 	bl	8038ed0 <HAL_QSPI_ErrorCallback>
+    if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
+ 8038e96:	e013      	b.n	8038ec0 <HAL_QSPI_IRQHandler+0x364>
+#endif
+    }
+  }
+
+  /* QSPI Timeout interrupt occurred -----------------------------------------*/
+  else if(((flag & QSPI_FLAG_TO) != 0U) && ((itsource & QSPI_IT_TO) != 0U))
+ 8038e98:	697b      	ldr	r3, [r7, #20]
+ 8038e9a:	f003 0310 	and.w	r3, r3, #16
+ 8038e9e:	2b00      	cmp	r3, #0
+ 8038ea0:	d00f      	beq.n	8038ec2 <HAL_QSPI_IRQHandler+0x366>
+ 8038ea2:	693b      	ldr	r3, [r7, #16]
+ 8038ea4:	f403 1380 	and.w	r3, r3, #1048576	@ 0x100000
+ 8038ea8:	2b00      	cmp	r3, #0
+ 8038eaa:	d00a      	beq.n	8038ec2 <HAL_QSPI_IRQHandler+0x366>
+  {
+    /* Clear interrupt */
+    WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TO);
+ 8038eac:	687b      	ldr	r3, [r7, #4]
+ 8038eae:	681b      	ldr	r3, [r3, #0]
+ 8038eb0:	2210      	movs	r2, #16
+ 8038eb2:	60da      	str	r2, [r3, #12]
+
+    /* Timeout callback */
+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
+    hqspi->TimeOutCallback(hqspi);
+#else
+    HAL_QSPI_TimeOutCallback(hqspi);
+ 8038eb4:	6878      	ldr	r0, [r7, #4]
+ 8038eb6:	f000 f851 	bl	8038f5c <HAL_QSPI_TimeOutCallback>
+
+   else
+  {
+   /* Nothing to do */
+  }
+}
+ 8038eba:	e002      	b.n	8038ec2 <HAL_QSPI_IRQHandler+0x366>
+    if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
+ 8038ebc:	bf00      	nop
+ 8038ebe:	e000      	b.n	8038ec2 <HAL_QSPI_IRQHandler+0x366>
+    if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U)
+ 8038ec0:	bf00      	nop
+}
+ 8038ec2:	bf00      	nop
+ 8038ec4:	3718      	adds	r7, #24
+ 8038ec6:	46bd      	mov	sp, r7
+ 8038ec8:	bd80      	pop	{r7, pc}
+ 8038eca:	bf00      	nop
+ 8038ecc:	08038f8d 	.word	0x08038f8d
+
+08038ed0 <HAL_QSPI_ErrorCallback>:
+  * @brief  Transfer Error callback.
+  * @param  hqspi QSPI handle
+  * @retval None
+  */
+__weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)
+{
+ 8038ed0:	b480      	push	{r7}
+ 8038ed2:	b083      	sub	sp, #12
+ 8038ed4:	af00      	add	r7, sp, #0
+ 8038ed6:	6078      	str	r0, [r7, #4]
+  UNUSED(hqspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_QSPI_ErrorCallback could be implemented in the user file
+   */
+}
+ 8038ed8:	bf00      	nop
+ 8038eda:	370c      	adds	r7, #12
+ 8038edc:	46bd      	mov	sp, r7
+ 8038ede:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8038ee2:	4770      	bx	lr
+
+08038ee4 <HAL_QSPI_AbortCpltCallback>:
+  * @brief  Abort completed callback.
+  * @param  hqspi QSPI handle
+  * @retval None
+  */
+__weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi)
+{
+ 8038ee4:	b480      	push	{r7}
+ 8038ee6:	b083      	sub	sp, #12
+ 8038ee8:	af00      	add	r7, sp, #0
+ 8038eea:	6078      	str	r0, [r7, #4]
+  UNUSED(hqspi);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_QSPI_AbortCpltCallback could be implemented in the user file
+   */
+}
+ 8038eec:	bf00      	nop
+ 8038eee:	370c      	adds	r7, #12
+ 8038ef0:	46bd      	mov	sp, r7
+ 8038ef2:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8038ef6:	4770      	bx	lr
+
+08038ef8 <HAL_QSPI_CmdCpltCallback>:
+  * @brief  Command completed callback.
+  * @param  hqspi QSPI handle
+  * @retval None
+  */
+__weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)
+{
+ 8038ef8:	b480      	push	{r7}
+ 8038efa:	b083      	sub	sp, #12
+ 8038efc:	af00      	add	r7, sp, #0
+ 8038efe:	6078      	str	r0, [r7, #4]
+  UNUSED(hqspi);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_QSPI_CmdCpltCallback could be implemented in the user file
+   */
+}
+ 8038f00:	bf00      	nop
+ 8038f02:	370c      	adds	r7, #12
+ 8038f04:	46bd      	mov	sp, r7
+ 8038f06:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8038f0a:	4770      	bx	lr
+
+08038f0c <HAL_QSPI_RxCpltCallback>:
+  * @brief  Rx Transfer completed callback.
+  * @param  hqspi QSPI handle
+  * @retval None
+  */
+__weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
+{
+ 8038f0c:	b480      	push	{r7}
+ 8038f0e:	b083      	sub	sp, #12
+ 8038f10:	af00      	add	r7, sp, #0
+ 8038f12:	6078      	str	r0, [r7, #4]
+  UNUSED(hqspi);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_QSPI_RxCpltCallback could be implemented in the user file
+   */
+}
+ 8038f14:	bf00      	nop
+ 8038f16:	370c      	adds	r7, #12
+ 8038f18:	46bd      	mov	sp, r7
+ 8038f1a:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8038f1e:	4770      	bx	lr
+
+08038f20 <HAL_QSPI_TxCpltCallback>:
+  * @brief  Tx Transfer completed callback.
+  * @param  hqspi QSPI handle
+  * @retval None
+  */
+__weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
+{
+ 8038f20:	b480      	push	{r7}
+ 8038f22:	b083      	sub	sp, #12
+ 8038f24:	af00      	add	r7, sp, #0
+ 8038f26:	6078      	str	r0, [r7, #4]
+  UNUSED(hqspi);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_QSPI_TxCpltCallback could be implemented in the user file
+   */
+}
+ 8038f28:	bf00      	nop
+ 8038f2a:	370c      	adds	r7, #12
+ 8038f2c:	46bd      	mov	sp, r7
+ 8038f2e:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8038f32:	4770      	bx	lr
+
+08038f34 <HAL_QSPI_FifoThresholdCallback>:
+  * @brief  FIFO Threshold callback.
+  * @param  hqspi QSPI handle
+  * @retval None
+  */
+__weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)
+{
+ 8038f34:	b480      	push	{r7}
+ 8038f36:	b083      	sub	sp, #12
+ 8038f38:	af00      	add	r7, sp, #0
+ 8038f3a:	6078      	str	r0, [r7, #4]
+  UNUSED(hqspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_QSPI_FIFOThresholdCallback could be implemented in the user file
+   */
+}
+ 8038f3c:	bf00      	nop
+ 8038f3e:	370c      	adds	r7, #12
+ 8038f40:	46bd      	mov	sp, r7
+ 8038f42:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8038f46:	4770      	bx	lr
+
+08038f48 <HAL_QSPI_StatusMatchCallback>:
+  * @brief  Status Match callback.
+  * @param  hqspi QSPI handle
+  * @retval None
+  */
+__weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)
+{
+ 8038f48:	b480      	push	{r7}
+ 8038f4a:	b083      	sub	sp, #12
+ 8038f4c:	af00      	add	r7, sp, #0
+ 8038f4e:	6078      	str	r0, [r7, #4]
+  UNUSED(hqspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_QSPI_StatusMatchCallback could be implemented in the user file
+   */
+}
+ 8038f50:	bf00      	nop
+ 8038f52:	370c      	adds	r7, #12
+ 8038f54:	46bd      	mov	sp, r7
+ 8038f56:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8038f5a:	4770      	bx	lr
+
+08038f5c <HAL_QSPI_TimeOutCallback>:
+  * @brief  Timeout callback.
+  * @param  hqspi QSPI handle
+  * @retval None
+  */
+__weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)
+{
+ 8038f5c:	b480      	push	{r7}
+ 8038f5e:	b083      	sub	sp, #12
+ 8038f60:	af00      	add	r7, sp, #0
+ 8038f62:	6078      	str	r0, [r7, #4]
+  UNUSED(hqspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_QSPI_TimeOutCallback could be implemented in the user file
+   */
+}
+ 8038f64:	bf00      	nop
+ 8038f66:	370c      	adds	r7, #12
+ 8038f68:	46bd      	mov	sp, r7
+ 8038f6a:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8038f6e:	4770      	bx	lr
+
+08038f70 <HAL_QSPI_SetTimeout>:
+  * @param  hqspi QSPI handle.
+  * @param  Timeout Timeout for the QSPI memory access.
+  * @retval None
+  */
+void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
+{
+ 8038f70:	b480      	push	{r7}
+ 8038f72:	b083      	sub	sp, #12
+ 8038f74:	af00      	add	r7, sp, #0
+ 8038f76:	6078      	str	r0, [r7, #4]
+ 8038f78:	6039      	str	r1, [r7, #0]
+  hqspi->Timeout = Timeout;
+ 8038f7a:	687b      	ldr	r3, [r7, #4]
+ 8038f7c:	683a      	ldr	r2, [r7, #0]
+ 8038f7e:	649a      	str	r2, [r3, #72]	@ 0x48
+}
+ 8038f80:	bf00      	nop
+ 8038f82:	370c      	adds	r7, #12
+ 8038f84:	46bd      	mov	sp, r7
+ 8038f86:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8038f8a:	4770      	bx	lr
+
+08038f8c <QSPI_DMAAbortCplt>:
+  * @brief  MDMA QSPI abort complete callback.
+  * @param  hmdma MDMA handle
+  * @retval None
+  */
+static void QSPI_DMAAbortCplt(MDMA_HandleTypeDef *hmdma)
+{
+ 8038f8c:	b580      	push	{r7, lr}
+ 8038f8e:	b084      	sub	sp, #16
+ 8038f90:	af00      	add	r7, sp, #0
+ 8038f92:	6078      	str	r0, [r7, #4]
+  QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hmdma->Parent);
+ 8038f94:	687b      	ldr	r3, [r7, #4]
+ 8038f96:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
+ 8038f98:	60fb      	str	r3, [r7, #12]
+
+  hqspi->RxXferCount = 0U;
+ 8038f9a:	68fb      	ldr	r3, [r7, #12]
+ 8038f9c:	2200      	movs	r2, #0
+ 8038f9e:	639a      	str	r2, [r3, #56]	@ 0x38
+  hqspi->TxXferCount = 0U;
+ 8038fa0:	68fb      	ldr	r3, [r7, #12]
+ 8038fa2:	2200      	movs	r2, #0
+ 8038fa4:	62da      	str	r2, [r3, #44]	@ 0x2c
+
+  if(hqspi->State == HAL_QSPI_STATE_ABORT)
+ 8038fa6:	68fb      	ldr	r3, [r7, #12]
+ 8038fa8:	f893 3041 	ldrb.w	r3, [r3, #65]	@ 0x41
+ 8038fac:	b2db      	uxtb	r3, r3
+ 8038fae:	2b08      	cmp	r3, #8
+ 8038fb0:	d114      	bne.n	8038fdc <QSPI_DMAAbortCplt+0x50>
+  {
+    /* MDMA Abort called by QSPI abort */
+    /* Clear interrupt */
+    __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
+ 8038fb2:	68fb      	ldr	r3, [r7, #12]
+ 8038fb4:	681b      	ldr	r3, [r3, #0]
+ 8038fb6:	2202      	movs	r2, #2
+ 8038fb8:	60da      	str	r2, [r3, #12]
+
+    /* Enable the QSPI Transfer Complete Interrupt */
+    __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
+ 8038fba:	68fb      	ldr	r3, [r7, #12]
+ 8038fbc:	681b      	ldr	r3, [r3, #0]
+ 8038fbe:	681a      	ldr	r2, [r3, #0]
+ 8038fc0:	68fb      	ldr	r3, [r7, #12]
+ 8038fc2:	681b      	ldr	r3, [r3, #0]
+ 8038fc4:	f442 3200 	orr.w	r2, r2, #131072	@ 0x20000
+ 8038fc8:	601a      	str	r2, [r3, #0]
+
+    /* Configure QSPI: CR register with Abort request */
+    SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
+ 8038fca:	68fb      	ldr	r3, [r7, #12]
+ 8038fcc:	681b      	ldr	r3, [r3, #0]
+ 8038fce:	681a      	ldr	r2, [r3, #0]
+ 8038fd0:	68fb      	ldr	r3, [r7, #12]
+ 8038fd2:	681b      	ldr	r3, [r3, #0]
+ 8038fd4:	f042 0202 	orr.w	r2, r2, #2
+ 8038fd8:	601a      	str	r2, [r3, #0]
+    hqspi->ErrorCallback(hqspi);
+#else
+    HAL_QSPI_ErrorCallback(hqspi);
+#endif
+  }
+}
+ 8038fda:	e006      	b.n	8038fea <QSPI_DMAAbortCplt+0x5e>
+    hqspi->State = HAL_QSPI_STATE_READY;
+ 8038fdc:	68fb      	ldr	r3, [r7, #12]
+ 8038fde:	2201      	movs	r2, #1
+ 8038fe0:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
+    HAL_QSPI_ErrorCallback(hqspi);
+ 8038fe4:	68f8      	ldr	r0, [r7, #12]
+ 8038fe6:	f7ff ff73 	bl	8038ed0 <HAL_QSPI_ErrorCallback>
+}
+ 8038fea:	bf00      	nop
+ 8038fec:	3710      	adds	r7, #16
+ 8038fee:	46bd      	mov	sp, r7
+ 8038ff0:	bd80      	pop	{r7, pc}
+
+08038ff2 <QSPI_WaitFlagStateUntilTimeout>:
+  * @param  Timeout Duration of the timeout
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,
+                                                        FlagStatus State, uint32_t Tickstart, uint32_t Timeout)
+{
+ 8038ff2:	b580      	push	{r7, lr}
+ 8038ff4:	b084      	sub	sp, #16
+ 8038ff6:	af00      	add	r7, sp, #0
+ 8038ff8:	60f8      	str	r0, [r7, #12]
+ 8038ffa:	60b9      	str	r1, [r7, #8]
+ 8038ffc:	603b      	str	r3, [r7, #0]
+ 8038ffe:	4613      	mov	r3, r2
+ 8039000:	71fb      	strb	r3, [r7, #7]
+  /* Wait until flag is in expected state */
+  while((__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)
+ 8039002:	e01a      	b.n	803903a <QSPI_WaitFlagStateUntilTimeout+0x48>
+  {
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
+ 8039004:	69bb      	ldr	r3, [r7, #24]
+ 8039006:	f1b3 3fff 	cmp.w	r3, #4294967295
+ 803900a:	d016      	beq.n	803903a <QSPI_WaitFlagStateUntilTimeout+0x48>
+    {
+      if(((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+ 803900c:	f7f8 fc90 	bl	8031930 <HAL_GetTick>
+ 8039010:	4602      	mov	r2, r0
+ 8039012:	683b      	ldr	r3, [r7, #0]
+ 8039014:	1ad3      	subs	r3, r2, r3
+ 8039016:	69ba      	ldr	r2, [r7, #24]
+ 8039018:	429a      	cmp	r2, r3
+ 803901a:	d302      	bcc.n	8039022 <QSPI_WaitFlagStateUntilTimeout+0x30>
+ 803901c:	69bb      	ldr	r3, [r7, #24]
+ 803901e:	2b00      	cmp	r3, #0
+ 8039020:	d10b      	bne.n	803903a <QSPI_WaitFlagStateUntilTimeout+0x48>
+      {
+        hqspi->State     = HAL_QSPI_STATE_ERROR;
+ 8039022:	68fb      	ldr	r3, [r7, #12]
+ 8039024:	2204      	movs	r2, #4
+ 8039026:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
+        hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT;
+ 803902a:	68fb      	ldr	r3, [r7, #12]
+ 803902c:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
+ 803902e:	f043 0201 	orr.w	r2, r3, #1
+ 8039032:	68fb      	ldr	r3, [r7, #12]
+ 8039034:	645a      	str	r2, [r3, #68]	@ 0x44
+
+        return HAL_ERROR;
+ 8039036:	2301      	movs	r3, #1
+ 8039038:	e00e      	b.n	8039058 <QSPI_WaitFlagStateUntilTimeout+0x66>
+  while((__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)
+ 803903a:	68fb      	ldr	r3, [r7, #12]
+ 803903c:	681b      	ldr	r3, [r3, #0]
+ 803903e:	689a      	ldr	r2, [r3, #8]
+ 8039040:	68bb      	ldr	r3, [r7, #8]
+ 8039042:	4013      	ands	r3, r2
+ 8039044:	2b00      	cmp	r3, #0
+ 8039046:	bf14      	ite	ne
+ 8039048:	2301      	movne	r3, #1
+ 803904a:	2300      	moveq	r3, #0
+ 803904c:	b2db      	uxtb	r3, r3
+ 803904e:	461a      	mov	r2, r3
+ 8039050:	79fb      	ldrb	r3, [r7, #7]
+ 8039052:	429a      	cmp	r2, r3
+ 8039054:	d1d6      	bne.n	8039004 <QSPI_WaitFlagStateUntilTimeout+0x12>
+      }
+    }
+  }
+  return HAL_OK;
+ 8039056:	2300      	movs	r3, #0
+}
+ 8039058:	4618      	mov	r0, r3
+ 803905a:	3710      	adds	r7, #16
+ 803905c:	46bd      	mov	sp, r7
+ 803905e:	bd80      	pop	{r7, pc}
+
+08039060 <HAL_RCC_OscConfig>:
+  *         supported by this function. User should request a transition to HSE Off
+  *         first and then HSE On or HSE Bypass.
+  * @retval HAL status
+  */
+__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
+{
+ 8039060:	b580      	push	{r7, lr}
+ 8039062:	b08c      	sub	sp, #48	@ 0x30
+ 8039064:	af00      	add	r7, sp, #0
+ 8039066:	6078      	str	r0, [r7, #4]
+  uint32_t tickstart;
+  uint32_t temp1_pllckcfg, temp2_pllckcfg;
+
+  /* Check Null pointer */
+  if (RCC_OscInitStruct == NULL)
+ 8039068:	687b      	ldr	r3, [r7, #4]
+ 803906a:	2b00      	cmp	r3, #0
+ 803906c:	d102      	bne.n	8039074 <HAL_RCC_OscConfig+0x14>
+  {
+    return HAL_ERROR;
+ 803906e:	2301      	movs	r3, #1
+ 8039070:	f000 bc48 	b.w	8039904 <HAL_RCC_OscConfig+0x8a4>
+  }
+
+  /* Check the parameters */
+  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
+  /*------------------------------- HSE Configuration ------------------------*/
+  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
+ 8039074:	687b      	ldr	r3, [r7, #4]
+ 8039076:	681b      	ldr	r3, [r3, #0]
+ 8039078:	f003 0301 	and.w	r3, r3, #1
+ 803907c:	2b00      	cmp	r3, #0
+ 803907e:	f000 8088 	beq.w	8039192 <HAL_RCC_OscConfig+0x132>
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
+
+    const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
+ 8039082:	4b99      	ldr	r3, [pc, #612]	@ (80392e8 <HAL_RCC_OscConfig+0x288>)
+ 8039084:	691b      	ldr	r3, [r3, #16]
+ 8039086:	f003 0338 	and.w	r3, r3, #56	@ 0x38
+ 803908a:	62fb      	str	r3, [r7, #44]	@ 0x2c
+    const uint32_t temp_pllckselr = RCC->PLLCKSELR;
+ 803908c:	4b96      	ldr	r3, [pc, #600]	@ (80392e8 <HAL_RCC_OscConfig+0x288>)
+ 803908e:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 8039090:	62bb      	str	r3, [r7, #40]	@ 0x28
+    /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
+    if ((temp_sysclksrc == RCC_CFGR_SWS_HSE) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSE)))
+ 8039092:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
+ 8039094:	2b10      	cmp	r3, #16
+ 8039096:	d007      	beq.n	80390a8 <HAL_RCC_OscConfig+0x48>
+ 8039098:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
+ 803909a:	2b18      	cmp	r3, #24
+ 803909c:	d111      	bne.n	80390c2 <HAL_RCC_OscConfig+0x62>
+ 803909e:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 80390a0:	f003 0303 	and.w	r3, r3, #3
+ 80390a4:	2b02      	cmp	r3, #2
+ 80390a6:	d10c      	bne.n	80390c2 <HAL_RCC_OscConfig+0x62>
+    {
+      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
+ 80390a8:	4b8f      	ldr	r3, [pc, #572]	@ (80392e8 <HAL_RCC_OscConfig+0x288>)
+ 80390aa:	681b      	ldr	r3, [r3, #0]
+ 80390ac:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
+ 80390b0:	2b00      	cmp	r3, #0
+ 80390b2:	d06d      	beq.n	8039190 <HAL_RCC_OscConfig+0x130>
+ 80390b4:	687b      	ldr	r3, [r7, #4]
+ 80390b6:	685b      	ldr	r3, [r3, #4]
+ 80390b8:	2b00      	cmp	r3, #0
+ 80390ba:	d169      	bne.n	8039190 <HAL_RCC_OscConfig+0x130>
+      {
+        return HAL_ERROR;
+ 80390bc:	2301      	movs	r3, #1
+ 80390be:	f000 bc21 	b.w	8039904 <HAL_RCC_OscConfig+0x8a4>
+      }
+    }
+    else
+    {
+      /* Set the new HSE configuration ---------------------------------------*/
+      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
+ 80390c2:	687b      	ldr	r3, [r7, #4]
+ 80390c4:	685b      	ldr	r3, [r3, #4]
+ 80390c6:	f5b3 3f80 	cmp.w	r3, #65536	@ 0x10000
+ 80390ca:	d106      	bne.n	80390da <HAL_RCC_OscConfig+0x7a>
+ 80390cc:	4b86      	ldr	r3, [pc, #536]	@ (80392e8 <HAL_RCC_OscConfig+0x288>)
+ 80390ce:	681b      	ldr	r3, [r3, #0]
+ 80390d0:	4a85      	ldr	r2, [pc, #532]	@ (80392e8 <HAL_RCC_OscConfig+0x288>)
+ 80390d2:	f443 3380 	orr.w	r3, r3, #65536	@ 0x10000
+ 80390d6:	6013      	str	r3, [r2, #0]
+ 80390d8:	e02e      	b.n	8039138 <HAL_RCC_OscConfig+0xd8>
+ 80390da:	687b      	ldr	r3, [r7, #4]
+ 80390dc:	685b      	ldr	r3, [r3, #4]
+ 80390de:	2b00      	cmp	r3, #0
+ 80390e0:	d10c      	bne.n	80390fc <HAL_RCC_OscConfig+0x9c>
+ 80390e2:	4b81      	ldr	r3, [pc, #516]	@ (80392e8 <HAL_RCC_OscConfig+0x288>)
+ 80390e4:	681b      	ldr	r3, [r3, #0]
+ 80390e6:	4a80      	ldr	r2, [pc, #512]	@ (80392e8 <HAL_RCC_OscConfig+0x288>)
+ 80390e8:	f423 3380 	bic.w	r3, r3, #65536	@ 0x10000
+ 80390ec:	6013      	str	r3, [r2, #0]
+ 80390ee:	4b7e      	ldr	r3, [pc, #504]	@ (80392e8 <HAL_RCC_OscConfig+0x288>)
+ 80390f0:	681b      	ldr	r3, [r3, #0]
+ 80390f2:	4a7d      	ldr	r2, [pc, #500]	@ (80392e8 <HAL_RCC_OscConfig+0x288>)
+ 80390f4:	f423 2380 	bic.w	r3, r3, #262144	@ 0x40000
+ 80390f8:	6013      	str	r3, [r2, #0]
+ 80390fa:	e01d      	b.n	8039138 <HAL_RCC_OscConfig+0xd8>
+ 80390fc:	687b      	ldr	r3, [r7, #4]
+ 80390fe:	685b      	ldr	r3, [r3, #4]
+ 8039100:	f5b3 2fa0 	cmp.w	r3, #327680	@ 0x50000
+ 8039104:	d10c      	bne.n	8039120 <HAL_RCC_OscConfig+0xc0>
+ 8039106:	4b78      	ldr	r3, [pc, #480]	@ (80392e8 <HAL_RCC_OscConfig+0x288>)
+ 8039108:	681b      	ldr	r3, [r3, #0]
+ 803910a:	4a77      	ldr	r2, [pc, #476]	@ (80392e8 <HAL_RCC_OscConfig+0x288>)
+ 803910c:	f443 2380 	orr.w	r3, r3, #262144	@ 0x40000
+ 8039110:	6013      	str	r3, [r2, #0]
+ 8039112:	4b75      	ldr	r3, [pc, #468]	@ (80392e8 <HAL_RCC_OscConfig+0x288>)
+ 8039114:	681b      	ldr	r3, [r3, #0]
+ 8039116:	4a74      	ldr	r2, [pc, #464]	@ (80392e8 <HAL_RCC_OscConfig+0x288>)
+ 8039118:	f443 3380 	orr.w	r3, r3, #65536	@ 0x10000
+ 803911c:	6013      	str	r3, [r2, #0]
+ 803911e:	e00b      	b.n	8039138 <HAL_RCC_OscConfig+0xd8>
+ 8039120:	4b71      	ldr	r3, [pc, #452]	@ (80392e8 <HAL_RCC_OscConfig+0x288>)
+ 8039122:	681b      	ldr	r3, [r3, #0]
+ 8039124:	4a70      	ldr	r2, [pc, #448]	@ (80392e8 <HAL_RCC_OscConfig+0x288>)
+ 8039126:	f423 3380 	bic.w	r3, r3, #65536	@ 0x10000
+ 803912a:	6013      	str	r3, [r2, #0]
+ 803912c:	4b6e      	ldr	r3, [pc, #440]	@ (80392e8 <HAL_RCC_OscConfig+0x288>)
+ 803912e:	681b      	ldr	r3, [r3, #0]
+ 8039130:	4a6d      	ldr	r2, [pc, #436]	@ (80392e8 <HAL_RCC_OscConfig+0x288>)
+ 8039132:	f423 2380 	bic.w	r3, r3, #262144	@ 0x40000
+ 8039136:	6013      	str	r3, [r2, #0]
+
+      /* Check the HSE State */
+      if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
+ 8039138:	687b      	ldr	r3, [r7, #4]
+ 803913a:	685b      	ldr	r3, [r3, #4]
+ 803913c:	2b00      	cmp	r3, #0
+ 803913e:	d013      	beq.n	8039168 <HAL_RCC_OscConfig+0x108>
+      {
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+ 8039140:	f7f8 fbf6 	bl	8031930 <HAL_GetTick>
+ 8039144:	6278      	str	r0, [r7, #36]	@ 0x24
+
+        /* Wait till HSE is ready */
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
+ 8039146:	e008      	b.n	803915a <HAL_RCC_OscConfig+0xfa>
+        {
+          if ((uint32_t)(HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
+ 8039148:	f7f8 fbf2 	bl	8031930 <HAL_GetTick>
+ 803914c:	4602      	mov	r2, r0
+ 803914e:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 8039150:	1ad3      	subs	r3, r2, r3
+ 8039152:	2b64      	cmp	r3, #100	@ 0x64
+ 8039154:	d901      	bls.n	803915a <HAL_RCC_OscConfig+0xfa>
+          {
+            return HAL_TIMEOUT;
+ 8039156:	2303      	movs	r3, #3
+ 8039158:	e3d4      	b.n	8039904 <HAL_RCC_OscConfig+0x8a4>
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
+ 803915a:	4b63      	ldr	r3, [pc, #396]	@ (80392e8 <HAL_RCC_OscConfig+0x288>)
+ 803915c:	681b      	ldr	r3, [r3, #0]
+ 803915e:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
+ 8039162:	2b00      	cmp	r3, #0
+ 8039164:	d0f0      	beq.n	8039148 <HAL_RCC_OscConfig+0xe8>
+ 8039166:	e014      	b.n	8039192 <HAL_RCC_OscConfig+0x132>
+        }
+      }
+      else
+      {
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+ 8039168:	f7f8 fbe2 	bl	8031930 <HAL_GetTick>
+ 803916c:	6278      	str	r0, [r7, #36]	@ 0x24
+
+        /* Wait till HSE is disabled */
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)
+ 803916e:	e008      	b.n	8039182 <HAL_RCC_OscConfig+0x122>
+        {
+          if ((uint32_t)(HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
+ 8039170:	f7f8 fbde 	bl	8031930 <HAL_GetTick>
+ 8039174:	4602      	mov	r2, r0
+ 8039176:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 8039178:	1ad3      	subs	r3, r2, r3
+ 803917a:	2b64      	cmp	r3, #100	@ 0x64
+ 803917c:	d901      	bls.n	8039182 <HAL_RCC_OscConfig+0x122>
+          {
+            return HAL_TIMEOUT;
+ 803917e:	2303      	movs	r3, #3
+ 8039180:	e3c0      	b.n	8039904 <HAL_RCC_OscConfig+0x8a4>
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)
+ 8039182:	4b59      	ldr	r3, [pc, #356]	@ (80392e8 <HAL_RCC_OscConfig+0x288>)
+ 8039184:	681b      	ldr	r3, [r3, #0]
+ 8039186:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
+ 803918a:	2b00      	cmp	r3, #0
+ 803918c:	d1f0      	bne.n	8039170 <HAL_RCC_OscConfig+0x110>
+ 803918e:	e000      	b.n	8039192 <HAL_RCC_OscConfig+0x132>
+      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
+ 8039190:	bf00      	nop
+        }
+      }
+    }
+  }
+  /*----------------------------- HSI Configuration --------------------------*/
+  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
+ 8039192:	687b      	ldr	r3, [r7, #4]
+ 8039194:	681b      	ldr	r3, [r3, #0]
+ 8039196:	f003 0302 	and.w	r3, r3, #2
+ 803919a:	2b00      	cmp	r3, #0
+ 803919c:	f000 80ca 	beq.w	8039334 <HAL_RCC_OscConfig+0x2d4>
+    /* Check the parameters */
+    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
+    assert_param(IS_RCC_HSICALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
+
+    /* When the HSI is used as system clock it will not be disabled */
+    const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
+ 80391a0:	4b51      	ldr	r3, [pc, #324]	@ (80392e8 <HAL_RCC_OscConfig+0x288>)
+ 80391a2:	691b      	ldr	r3, [r3, #16]
+ 80391a4:	f003 0338 	and.w	r3, r3, #56	@ 0x38
+ 80391a8:	623b      	str	r3, [r7, #32]
+    const uint32_t temp_pllckselr = RCC->PLLCKSELR;
+ 80391aa:	4b4f      	ldr	r3, [pc, #316]	@ (80392e8 <HAL_RCC_OscConfig+0x288>)
+ 80391ac:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 80391ae:	61fb      	str	r3, [r7, #28]
+    if ((temp_sysclksrc == RCC_CFGR_SWS_HSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSI)))
+ 80391b0:	6a3b      	ldr	r3, [r7, #32]
+ 80391b2:	2b00      	cmp	r3, #0
+ 80391b4:	d007      	beq.n	80391c6 <HAL_RCC_OscConfig+0x166>
+ 80391b6:	6a3b      	ldr	r3, [r7, #32]
+ 80391b8:	2b18      	cmp	r3, #24
+ 80391ba:	d156      	bne.n	803926a <HAL_RCC_OscConfig+0x20a>
+ 80391bc:	69fb      	ldr	r3, [r7, #28]
+ 80391be:	f003 0303 	and.w	r3, r3, #3
+ 80391c2:	2b00      	cmp	r3, #0
+ 80391c4:	d151      	bne.n	803926a <HAL_RCC_OscConfig+0x20a>
+    {
+      /* When HSI is used as system clock it will not be disabled */
+      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
+ 80391c6:	4b48      	ldr	r3, [pc, #288]	@ (80392e8 <HAL_RCC_OscConfig+0x288>)
+ 80391c8:	681b      	ldr	r3, [r3, #0]
+ 80391ca:	f003 0304 	and.w	r3, r3, #4
+ 80391ce:	2b00      	cmp	r3, #0
+ 80391d0:	d005      	beq.n	80391de <HAL_RCC_OscConfig+0x17e>
+ 80391d2:	687b      	ldr	r3, [r7, #4]
+ 80391d4:	68db      	ldr	r3, [r3, #12]
+ 80391d6:	2b00      	cmp	r3, #0
+ 80391d8:	d101      	bne.n	80391de <HAL_RCC_OscConfig+0x17e>
+      {
+        return HAL_ERROR;
+ 80391da:	2301      	movs	r3, #1
+ 80391dc:	e392      	b.n	8039904 <HAL_RCC_OscConfig+0x8a4>
+      }
+      /* Otherwise, only HSI division and calibration are allowed */
+      else
+      {
+        /* Enable the Internal High Speed oscillator (HSI, HSIDIV2, HSIDIV4, or HSIDIV8) */
+        __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState);
+ 80391de:	4b42      	ldr	r3, [pc, #264]	@ (80392e8 <HAL_RCC_OscConfig+0x288>)
+ 80391e0:	681b      	ldr	r3, [r3, #0]
+ 80391e2:	f023 0219 	bic.w	r2, r3, #25
+ 80391e6:	687b      	ldr	r3, [r7, #4]
+ 80391e8:	68db      	ldr	r3, [r3, #12]
+ 80391ea:	493f      	ldr	r1, [pc, #252]	@ (80392e8 <HAL_RCC_OscConfig+0x288>)
+ 80391ec:	4313      	orrs	r3, r2
+ 80391ee:	600b      	str	r3, [r1, #0]
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+ 80391f0:	f7f8 fb9e 	bl	8031930 <HAL_GetTick>
+ 80391f4:	6278      	str	r0, [r7, #36]	@ 0x24
+
+        /* Wait till HSI is ready */
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
+ 80391f6:	e008      	b.n	803920a <HAL_RCC_OscConfig+0x1aa>
+        {
+          if ((uint32_t)(HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
+ 80391f8:	f7f8 fb9a 	bl	8031930 <HAL_GetTick>
+ 80391fc:	4602      	mov	r2, r0
+ 80391fe:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 8039200:	1ad3      	subs	r3, r2, r3
+ 8039202:	2b02      	cmp	r3, #2
+ 8039204:	d901      	bls.n	803920a <HAL_RCC_OscConfig+0x1aa>
+          {
+            return HAL_TIMEOUT;
+ 8039206:	2303      	movs	r3, #3
+ 8039208:	e37c      	b.n	8039904 <HAL_RCC_OscConfig+0x8a4>
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
+ 803920a:	4b37      	ldr	r3, [pc, #220]	@ (80392e8 <HAL_RCC_OscConfig+0x288>)
+ 803920c:	681b      	ldr	r3, [r3, #0]
+ 803920e:	f003 0304 	and.w	r3, r3, #4
+ 8039212:	2b00      	cmp	r3, #0
+ 8039214:	d0f0      	beq.n	80391f8 <HAL_RCC_OscConfig+0x198>
+          }
+        }
+        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+ 8039216:	f7f8 fbbb 	bl	8031990 <HAL_GetREVID>
+ 803921a:	4603      	mov	r3, r0
+ 803921c:	f241 0203 	movw	r2, #4099	@ 0x1003
+ 8039220:	4293      	cmp	r3, r2
+ 8039222:	d817      	bhi.n	8039254 <HAL_RCC_OscConfig+0x1f4>
+ 8039224:	687b      	ldr	r3, [r7, #4]
+ 8039226:	691b      	ldr	r3, [r3, #16]
+ 8039228:	2b40      	cmp	r3, #64	@ 0x40
+ 803922a:	d108      	bne.n	803923e <HAL_RCC_OscConfig+0x1de>
+ 803922c:	4b2e      	ldr	r3, [pc, #184]	@ (80392e8 <HAL_RCC_OscConfig+0x288>)
+ 803922e:	685b      	ldr	r3, [r3, #4]
+ 8039230:	f423 337c 	bic.w	r3, r3, #258048	@ 0x3f000
+ 8039234:	4a2c      	ldr	r2, [pc, #176]	@ (80392e8 <HAL_RCC_OscConfig+0x288>)
+ 8039236:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
+ 803923a:	6053      	str	r3, [r2, #4]
+      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
+ 803923c:	e07a      	b.n	8039334 <HAL_RCC_OscConfig+0x2d4>
+        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+ 803923e:	4b2a      	ldr	r3, [pc, #168]	@ (80392e8 <HAL_RCC_OscConfig+0x288>)
+ 8039240:	685b      	ldr	r3, [r3, #4]
+ 8039242:	f423 327c 	bic.w	r2, r3, #258048	@ 0x3f000
+ 8039246:	687b      	ldr	r3, [r7, #4]
+ 8039248:	691b      	ldr	r3, [r3, #16]
+ 803924a:	031b      	lsls	r3, r3, #12
+ 803924c:	4926      	ldr	r1, [pc, #152]	@ (80392e8 <HAL_RCC_OscConfig+0x288>)
+ 803924e:	4313      	orrs	r3, r2
+ 8039250:	604b      	str	r3, [r1, #4]
+      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
+ 8039252:	e06f      	b.n	8039334 <HAL_RCC_OscConfig+0x2d4>
+        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+ 8039254:	4b24      	ldr	r3, [pc, #144]	@ (80392e8 <HAL_RCC_OscConfig+0x288>)
+ 8039256:	685b      	ldr	r3, [r3, #4]
+ 8039258:	f023 42fe 	bic.w	r2, r3, #2130706432	@ 0x7f000000
+ 803925c:	687b      	ldr	r3, [r7, #4]
+ 803925e:	691b      	ldr	r3, [r3, #16]
+ 8039260:	061b      	lsls	r3, r3, #24
+ 8039262:	4921      	ldr	r1, [pc, #132]	@ (80392e8 <HAL_RCC_OscConfig+0x288>)
+ 8039264:	4313      	orrs	r3, r2
+ 8039266:	604b      	str	r3, [r1, #4]
+      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
+ 8039268:	e064      	b.n	8039334 <HAL_RCC_OscConfig+0x2d4>
+    }
+
+    else
+    {
+      /* Check the HSI State */
+      if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF)
+ 803926a:	687b      	ldr	r3, [r7, #4]
+ 803926c:	68db      	ldr	r3, [r3, #12]
+ 803926e:	2b00      	cmp	r3, #0
+ 8039270:	d047      	beq.n	8039302 <HAL_RCC_OscConfig+0x2a2>
+      {
+        /* Enable the Internal High Speed oscillator (HSI, HSIDIV2,HSIDIV4, or HSIDIV8) */
+        __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState);
+ 8039272:	4b1d      	ldr	r3, [pc, #116]	@ (80392e8 <HAL_RCC_OscConfig+0x288>)
+ 8039274:	681b      	ldr	r3, [r3, #0]
+ 8039276:	f023 0219 	bic.w	r2, r3, #25
+ 803927a:	687b      	ldr	r3, [r7, #4]
+ 803927c:	68db      	ldr	r3, [r3, #12]
+ 803927e:	491a      	ldr	r1, [pc, #104]	@ (80392e8 <HAL_RCC_OscConfig+0x288>)
+ 8039280:	4313      	orrs	r3, r2
+ 8039282:	600b      	str	r3, [r1, #0]
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+ 8039284:	f7f8 fb54 	bl	8031930 <HAL_GetTick>
+ 8039288:	6278      	str	r0, [r7, #36]	@ 0x24
+
+        /* Wait till HSI is ready */
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
+ 803928a:	e008      	b.n	803929e <HAL_RCC_OscConfig+0x23e>
+        {
+          if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
+ 803928c:	f7f8 fb50 	bl	8031930 <HAL_GetTick>
+ 8039290:	4602      	mov	r2, r0
+ 8039292:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 8039294:	1ad3      	subs	r3, r2, r3
+ 8039296:	2b02      	cmp	r3, #2
+ 8039298:	d901      	bls.n	803929e <HAL_RCC_OscConfig+0x23e>
+          {
+            return HAL_TIMEOUT;
+ 803929a:	2303      	movs	r3, #3
+ 803929c:	e332      	b.n	8039904 <HAL_RCC_OscConfig+0x8a4>
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
+ 803929e:	4b12      	ldr	r3, [pc, #72]	@ (80392e8 <HAL_RCC_OscConfig+0x288>)
+ 80392a0:	681b      	ldr	r3, [r3, #0]
+ 80392a2:	f003 0304 	and.w	r3, r3, #4
+ 80392a6:	2b00      	cmp	r3, #0
+ 80392a8:	d0f0      	beq.n	803928c <HAL_RCC_OscConfig+0x22c>
+          }
+        }
+
+        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+ 80392aa:	f7f8 fb71 	bl	8031990 <HAL_GetREVID>
+ 80392ae:	4603      	mov	r3, r0
+ 80392b0:	f241 0203 	movw	r2, #4099	@ 0x1003
+ 80392b4:	4293      	cmp	r3, r2
+ 80392b6:	d819      	bhi.n	80392ec <HAL_RCC_OscConfig+0x28c>
+ 80392b8:	687b      	ldr	r3, [r7, #4]
+ 80392ba:	691b      	ldr	r3, [r3, #16]
+ 80392bc:	2b40      	cmp	r3, #64	@ 0x40
+ 80392be:	d108      	bne.n	80392d2 <HAL_RCC_OscConfig+0x272>
+ 80392c0:	4b09      	ldr	r3, [pc, #36]	@ (80392e8 <HAL_RCC_OscConfig+0x288>)
+ 80392c2:	685b      	ldr	r3, [r3, #4]
+ 80392c4:	f423 337c 	bic.w	r3, r3, #258048	@ 0x3f000
+ 80392c8:	4a07      	ldr	r2, [pc, #28]	@ (80392e8 <HAL_RCC_OscConfig+0x288>)
+ 80392ca:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
+ 80392ce:	6053      	str	r3, [r2, #4]
+ 80392d0:	e030      	b.n	8039334 <HAL_RCC_OscConfig+0x2d4>
+ 80392d2:	4b05      	ldr	r3, [pc, #20]	@ (80392e8 <HAL_RCC_OscConfig+0x288>)
+ 80392d4:	685b      	ldr	r3, [r3, #4]
+ 80392d6:	f423 327c 	bic.w	r2, r3, #258048	@ 0x3f000
+ 80392da:	687b      	ldr	r3, [r7, #4]
+ 80392dc:	691b      	ldr	r3, [r3, #16]
+ 80392de:	031b      	lsls	r3, r3, #12
+ 80392e0:	4901      	ldr	r1, [pc, #4]	@ (80392e8 <HAL_RCC_OscConfig+0x288>)
+ 80392e2:	4313      	orrs	r3, r2
+ 80392e4:	604b      	str	r3, [r1, #4]
+ 80392e6:	e025      	b.n	8039334 <HAL_RCC_OscConfig+0x2d4>
+ 80392e8:	58024400 	.word	0x58024400
+ 80392ec:	4b9a      	ldr	r3, [pc, #616]	@ (8039558 <HAL_RCC_OscConfig+0x4f8>)
+ 80392ee:	685b      	ldr	r3, [r3, #4]
+ 80392f0:	f023 42fe 	bic.w	r2, r3, #2130706432	@ 0x7f000000
+ 80392f4:	687b      	ldr	r3, [r7, #4]
+ 80392f6:	691b      	ldr	r3, [r3, #16]
+ 80392f8:	061b      	lsls	r3, r3, #24
+ 80392fa:	4997      	ldr	r1, [pc, #604]	@ (8039558 <HAL_RCC_OscConfig+0x4f8>)
+ 80392fc:	4313      	orrs	r3, r2
+ 80392fe:	604b      	str	r3, [r1, #4]
+ 8039300:	e018      	b.n	8039334 <HAL_RCC_OscConfig+0x2d4>
+      }
+      else
+      {
+        /* Disable the Internal High Speed oscillator (HSI). */
+        __HAL_RCC_HSI_DISABLE();
+ 8039302:	4b95      	ldr	r3, [pc, #596]	@ (8039558 <HAL_RCC_OscConfig+0x4f8>)
+ 8039304:	681b      	ldr	r3, [r3, #0]
+ 8039306:	4a94      	ldr	r2, [pc, #592]	@ (8039558 <HAL_RCC_OscConfig+0x4f8>)
+ 8039308:	f023 0301 	bic.w	r3, r3, #1
+ 803930c:	6013      	str	r3, [r2, #0]
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+ 803930e:	f7f8 fb0f 	bl	8031930 <HAL_GetTick>
+ 8039312:	6278      	str	r0, [r7, #36]	@ 0x24
+
+        /* Wait till HSI is disabled */
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)
+ 8039314:	e008      	b.n	8039328 <HAL_RCC_OscConfig+0x2c8>
+        {
+          if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
+ 8039316:	f7f8 fb0b 	bl	8031930 <HAL_GetTick>
+ 803931a:	4602      	mov	r2, r0
+ 803931c:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 803931e:	1ad3      	subs	r3, r2, r3
+ 8039320:	2b02      	cmp	r3, #2
+ 8039322:	d901      	bls.n	8039328 <HAL_RCC_OscConfig+0x2c8>
+          {
+            return HAL_TIMEOUT;
+ 8039324:	2303      	movs	r3, #3
+ 8039326:	e2ed      	b.n	8039904 <HAL_RCC_OscConfig+0x8a4>
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)
+ 8039328:	4b8b      	ldr	r3, [pc, #556]	@ (8039558 <HAL_RCC_OscConfig+0x4f8>)
+ 803932a:	681b      	ldr	r3, [r3, #0]
+ 803932c:	f003 0304 	and.w	r3, r3, #4
+ 8039330:	2b00      	cmp	r3, #0
+ 8039332:	d1f0      	bne.n	8039316 <HAL_RCC_OscConfig+0x2b6>
+        }
+      }
+    }
+  }
+  /*----------------------------- CSI Configuration --------------------------*/
+  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI)
+ 8039334:	687b      	ldr	r3, [r7, #4]
+ 8039336:	681b      	ldr	r3, [r3, #0]
+ 8039338:	f003 0310 	and.w	r3, r3, #16
+ 803933c:	2b00      	cmp	r3, #0
+ 803933e:	f000 80a9 	beq.w	8039494 <HAL_RCC_OscConfig+0x434>
+    /* Check the parameters */
+    assert_param(IS_RCC_CSI(RCC_OscInitStruct->CSIState));
+    assert_param(IS_RCC_CSICALIBRATION_VALUE(RCC_OscInitStruct->CSICalibrationValue));
+
+    /* When the CSI is used as system clock it will not disabled */
+    const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
+ 8039342:	4b85      	ldr	r3, [pc, #532]	@ (8039558 <HAL_RCC_OscConfig+0x4f8>)
+ 8039344:	691b      	ldr	r3, [r3, #16]
+ 8039346:	f003 0338 	and.w	r3, r3, #56	@ 0x38
+ 803934a:	61bb      	str	r3, [r7, #24]
+    const uint32_t temp_pllckselr = RCC->PLLCKSELR;
+ 803934c:	4b82      	ldr	r3, [pc, #520]	@ (8039558 <HAL_RCC_OscConfig+0x4f8>)
+ 803934e:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 8039350:	617b      	str	r3, [r7, #20]
+    if ((temp_sysclksrc == RCC_CFGR_SWS_CSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_CSI)))
+ 8039352:	69bb      	ldr	r3, [r7, #24]
+ 8039354:	2b08      	cmp	r3, #8
+ 8039356:	d007      	beq.n	8039368 <HAL_RCC_OscConfig+0x308>
+ 8039358:	69bb      	ldr	r3, [r7, #24]
+ 803935a:	2b18      	cmp	r3, #24
+ 803935c:	d13a      	bne.n	80393d4 <HAL_RCC_OscConfig+0x374>
+ 803935e:	697b      	ldr	r3, [r7, #20]
+ 8039360:	f003 0303 	and.w	r3, r3, #3
+ 8039364:	2b01      	cmp	r3, #1
+ 8039366:	d135      	bne.n	80393d4 <HAL_RCC_OscConfig+0x374>
+    {
+      /* When CSI is used as system clock it will not disabled */
+      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON))
+ 8039368:	4b7b      	ldr	r3, [pc, #492]	@ (8039558 <HAL_RCC_OscConfig+0x4f8>)
+ 803936a:	681b      	ldr	r3, [r3, #0]
+ 803936c:	f403 7380 	and.w	r3, r3, #256	@ 0x100
+ 8039370:	2b00      	cmp	r3, #0
+ 8039372:	d005      	beq.n	8039380 <HAL_RCC_OscConfig+0x320>
+ 8039374:	687b      	ldr	r3, [r7, #4]
+ 8039376:	69db      	ldr	r3, [r3, #28]
+ 8039378:	2b80      	cmp	r3, #128	@ 0x80
+ 803937a:	d001      	beq.n	8039380 <HAL_RCC_OscConfig+0x320>
+      {
+        return HAL_ERROR;
+ 803937c:	2301      	movs	r3, #1
+ 803937e:	e2c1      	b.n	8039904 <HAL_RCC_OscConfig+0x8a4>
+      }
+      /* Otherwise, just the calibration is allowed */
+      else
+      {
+        /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/
+        __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue);
+ 8039380:	f7f8 fb06 	bl	8031990 <HAL_GetREVID>
+ 8039384:	4603      	mov	r3, r0
+ 8039386:	f241 0203 	movw	r2, #4099	@ 0x1003
+ 803938a:	4293      	cmp	r3, r2
+ 803938c:	d817      	bhi.n	80393be <HAL_RCC_OscConfig+0x35e>
+ 803938e:	687b      	ldr	r3, [r7, #4]
+ 8039390:	6a1b      	ldr	r3, [r3, #32]
+ 8039392:	2b20      	cmp	r3, #32
+ 8039394:	d108      	bne.n	80393a8 <HAL_RCC_OscConfig+0x348>
+ 8039396:	4b70      	ldr	r3, [pc, #448]	@ (8039558 <HAL_RCC_OscConfig+0x4f8>)
+ 8039398:	685b      	ldr	r3, [r3, #4]
+ 803939a:	f023 43f8 	bic.w	r3, r3, #2080374784	@ 0x7c000000
+ 803939e:	4a6e      	ldr	r2, [pc, #440]	@ (8039558 <HAL_RCC_OscConfig+0x4f8>)
+ 80393a0:	f043 4380 	orr.w	r3, r3, #1073741824	@ 0x40000000
+ 80393a4:	6053      	str	r3, [r2, #4]
+      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON))
+ 80393a6:	e075      	b.n	8039494 <HAL_RCC_OscConfig+0x434>
+        __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue);
+ 80393a8:	4b6b      	ldr	r3, [pc, #428]	@ (8039558 <HAL_RCC_OscConfig+0x4f8>)
+ 80393aa:	685b      	ldr	r3, [r3, #4]
+ 80393ac:	f023 42f8 	bic.w	r2, r3, #2080374784	@ 0x7c000000
+ 80393b0:	687b      	ldr	r3, [r7, #4]
+ 80393b2:	6a1b      	ldr	r3, [r3, #32]
+ 80393b4:	069b      	lsls	r3, r3, #26
+ 80393b6:	4968      	ldr	r1, [pc, #416]	@ (8039558 <HAL_RCC_OscConfig+0x4f8>)
+ 80393b8:	4313      	orrs	r3, r2
+ 80393ba:	604b      	str	r3, [r1, #4]
+      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON))
+ 80393bc:	e06a      	b.n	8039494 <HAL_RCC_OscConfig+0x434>
+        __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue);
+ 80393be:	4b66      	ldr	r3, [pc, #408]	@ (8039558 <HAL_RCC_OscConfig+0x4f8>)
+ 80393c0:	68db      	ldr	r3, [r3, #12]
+ 80393c2:	f023 527c 	bic.w	r2, r3, #1056964608	@ 0x3f000000
+ 80393c6:	687b      	ldr	r3, [r7, #4]
+ 80393c8:	6a1b      	ldr	r3, [r3, #32]
+ 80393ca:	061b      	lsls	r3, r3, #24
+ 80393cc:	4962      	ldr	r1, [pc, #392]	@ (8039558 <HAL_RCC_OscConfig+0x4f8>)
+ 80393ce:	4313      	orrs	r3, r2
+ 80393d0:	60cb      	str	r3, [r1, #12]
+      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON))
+ 80393d2:	e05f      	b.n	8039494 <HAL_RCC_OscConfig+0x434>
+      }
+    }
+    else
+    {
+      /* Check the CSI State */
+      if ((RCC_OscInitStruct->CSIState) != RCC_CSI_OFF)
+ 80393d4:	687b      	ldr	r3, [r7, #4]
+ 80393d6:	69db      	ldr	r3, [r3, #28]
+ 80393d8:	2b00      	cmp	r3, #0
+ 80393da:	d042      	beq.n	8039462 <HAL_RCC_OscConfig+0x402>
+      {
+        /* Enable the Internal High Speed oscillator (CSI). */
+        __HAL_RCC_CSI_ENABLE();
+ 80393dc:	4b5e      	ldr	r3, [pc, #376]	@ (8039558 <HAL_RCC_OscConfig+0x4f8>)
+ 80393de:	681b      	ldr	r3, [r3, #0]
+ 80393e0:	4a5d      	ldr	r2, [pc, #372]	@ (8039558 <HAL_RCC_OscConfig+0x4f8>)
+ 80393e2:	f043 0380 	orr.w	r3, r3, #128	@ 0x80
+ 80393e6:	6013      	str	r3, [r2, #0]
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+ 80393e8:	f7f8 faa2 	bl	8031930 <HAL_GetTick>
+ 80393ec:	6278      	str	r0, [r7, #36]	@ 0x24
+
+        /* Wait till CSI is ready */
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U)
+ 80393ee:	e008      	b.n	8039402 <HAL_RCC_OscConfig+0x3a2>
+        {
+          if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE)
+ 80393f0:	f7f8 fa9e 	bl	8031930 <HAL_GetTick>
+ 80393f4:	4602      	mov	r2, r0
+ 80393f6:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 80393f8:	1ad3      	subs	r3, r2, r3
+ 80393fa:	2b02      	cmp	r3, #2
+ 80393fc:	d901      	bls.n	8039402 <HAL_RCC_OscConfig+0x3a2>
+          {
+            return HAL_TIMEOUT;
+ 80393fe:	2303      	movs	r3, #3
+ 8039400:	e280      	b.n	8039904 <HAL_RCC_OscConfig+0x8a4>
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U)
+ 8039402:	4b55      	ldr	r3, [pc, #340]	@ (8039558 <HAL_RCC_OscConfig+0x4f8>)
+ 8039404:	681b      	ldr	r3, [r3, #0]
+ 8039406:	f403 7380 	and.w	r3, r3, #256	@ 0x100
+ 803940a:	2b00      	cmp	r3, #0
+ 803940c:	d0f0      	beq.n	80393f0 <HAL_RCC_OscConfig+0x390>
+          }
+        }
+
+        /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/
+        __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue);
+ 803940e:	f7f8 fabf 	bl	8031990 <HAL_GetREVID>
+ 8039412:	4603      	mov	r3, r0
+ 8039414:	f241 0203 	movw	r2, #4099	@ 0x1003
+ 8039418:	4293      	cmp	r3, r2
+ 803941a:	d817      	bhi.n	803944c <HAL_RCC_OscConfig+0x3ec>
+ 803941c:	687b      	ldr	r3, [r7, #4]
+ 803941e:	6a1b      	ldr	r3, [r3, #32]
+ 8039420:	2b20      	cmp	r3, #32
+ 8039422:	d108      	bne.n	8039436 <HAL_RCC_OscConfig+0x3d6>
+ 8039424:	4b4c      	ldr	r3, [pc, #304]	@ (8039558 <HAL_RCC_OscConfig+0x4f8>)
+ 8039426:	685b      	ldr	r3, [r3, #4]
+ 8039428:	f023 43f8 	bic.w	r3, r3, #2080374784	@ 0x7c000000
+ 803942c:	4a4a      	ldr	r2, [pc, #296]	@ (8039558 <HAL_RCC_OscConfig+0x4f8>)
+ 803942e:	f043 4380 	orr.w	r3, r3, #1073741824	@ 0x40000000
+ 8039432:	6053      	str	r3, [r2, #4]
+ 8039434:	e02e      	b.n	8039494 <HAL_RCC_OscConfig+0x434>
+ 8039436:	4b48      	ldr	r3, [pc, #288]	@ (8039558 <HAL_RCC_OscConfig+0x4f8>)
+ 8039438:	685b      	ldr	r3, [r3, #4]
+ 803943a:	f023 42f8 	bic.w	r2, r3, #2080374784	@ 0x7c000000
+ 803943e:	687b      	ldr	r3, [r7, #4]
+ 8039440:	6a1b      	ldr	r3, [r3, #32]
+ 8039442:	069b      	lsls	r3, r3, #26
+ 8039444:	4944      	ldr	r1, [pc, #272]	@ (8039558 <HAL_RCC_OscConfig+0x4f8>)
+ 8039446:	4313      	orrs	r3, r2
+ 8039448:	604b      	str	r3, [r1, #4]
+ 803944a:	e023      	b.n	8039494 <HAL_RCC_OscConfig+0x434>
+ 803944c:	4b42      	ldr	r3, [pc, #264]	@ (8039558 <HAL_RCC_OscConfig+0x4f8>)
+ 803944e:	68db      	ldr	r3, [r3, #12]
+ 8039450:	f023 527c 	bic.w	r2, r3, #1056964608	@ 0x3f000000
+ 8039454:	687b      	ldr	r3, [r7, #4]
+ 8039456:	6a1b      	ldr	r3, [r3, #32]
+ 8039458:	061b      	lsls	r3, r3, #24
+ 803945a:	493f      	ldr	r1, [pc, #252]	@ (8039558 <HAL_RCC_OscConfig+0x4f8>)
+ 803945c:	4313      	orrs	r3, r2
+ 803945e:	60cb      	str	r3, [r1, #12]
+ 8039460:	e018      	b.n	8039494 <HAL_RCC_OscConfig+0x434>
+      }
+      else
+      {
+        /* Disable the Internal High Speed oscillator (CSI). */
+        __HAL_RCC_CSI_DISABLE();
+ 8039462:	4b3d      	ldr	r3, [pc, #244]	@ (8039558 <HAL_RCC_OscConfig+0x4f8>)
+ 8039464:	681b      	ldr	r3, [r3, #0]
+ 8039466:	4a3c      	ldr	r2, [pc, #240]	@ (8039558 <HAL_RCC_OscConfig+0x4f8>)
+ 8039468:	f023 0380 	bic.w	r3, r3, #128	@ 0x80
+ 803946c:	6013      	str	r3, [r2, #0]
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+ 803946e:	f7f8 fa5f 	bl	8031930 <HAL_GetTick>
+ 8039472:	6278      	str	r0, [r7, #36]	@ 0x24
+
+        /* Wait till CSI is disabled */
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U)
+ 8039474:	e008      	b.n	8039488 <HAL_RCC_OscConfig+0x428>
+        {
+          if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE)
+ 8039476:	f7f8 fa5b 	bl	8031930 <HAL_GetTick>
+ 803947a:	4602      	mov	r2, r0
+ 803947c:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 803947e:	1ad3      	subs	r3, r2, r3
+ 8039480:	2b02      	cmp	r3, #2
+ 8039482:	d901      	bls.n	8039488 <HAL_RCC_OscConfig+0x428>
+          {
+            return HAL_TIMEOUT;
+ 8039484:	2303      	movs	r3, #3
+ 8039486:	e23d      	b.n	8039904 <HAL_RCC_OscConfig+0x8a4>
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U)
+ 8039488:	4b33      	ldr	r3, [pc, #204]	@ (8039558 <HAL_RCC_OscConfig+0x4f8>)
+ 803948a:	681b      	ldr	r3, [r3, #0]
+ 803948c:	f403 7380 	and.w	r3, r3, #256	@ 0x100
+ 8039490:	2b00      	cmp	r3, #0
+ 8039492:	d1f0      	bne.n	8039476 <HAL_RCC_OscConfig+0x416>
+        }
+      }
+    }
+  }
+  /*------------------------------ LSI Configuration -------------------------*/
+  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
+ 8039494:	687b      	ldr	r3, [r7, #4]
+ 8039496:	681b      	ldr	r3, [r3, #0]
+ 8039498:	f003 0308 	and.w	r3, r3, #8
+ 803949c:	2b00      	cmp	r3, #0
+ 803949e:	d036      	beq.n	803950e <HAL_RCC_OscConfig+0x4ae>
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
+
+    /* Check the LSI State */
+    if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF)
+ 80394a0:	687b      	ldr	r3, [r7, #4]
+ 80394a2:	695b      	ldr	r3, [r3, #20]
+ 80394a4:	2b00      	cmp	r3, #0
+ 80394a6:	d019      	beq.n	80394dc <HAL_RCC_OscConfig+0x47c>
+    {
+      /* Enable the Internal Low Speed oscillator (LSI). */
+      __HAL_RCC_LSI_ENABLE();
+ 80394a8:	4b2b      	ldr	r3, [pc, #172]	@ (8039558 <HAL_RCC_OscConfig+0x4f8>)
+ 80394aa:	6f5b      	ldr	r3, [r3, #116]	@ 0x74
+ 80394ac:	4a2a      	ldr	r2, [pc, #168]	@ (8039558 <HAL_RCC_OscConfig+0x4f8>)
+ 80394ae:	f043 0301 	orr.w	r3, r3, #1
+ 80394b2:	6753      	str	r3, [r2, #116]	@ 0x74
+
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+ 80394b4:	f7f8 fa3c 	bl	8031930 <HAL_GetTick>
+ 80394b8:	6278      	str	r0, [r7, #36]	@ 0x24
+
+      /* Wait till LSI is ready */
+      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)
+ 80394ba:	e008      	b.n	80394ce <HAL_RCC_OscConfig+0x46e>
+      {
+        if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
+ 80394bc:	f7f8 fa38 	bl	8031930 <HAL_GetTick>
+ 80394c0:	4602      	mov	r2, r0
+ 80394c2:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 80394c4:	1ad3      	subs	r3, r2, r3
+ 80394c6:	2b02      	cmp	r3, #2
+ 80394c8:	d901      	bls.n	80394ce <HAL_RCC_OscConfig+0x46e>
+        {
+          return HAL_TIMEOUT;
+ 80394ca:	2303      	movs	r3, #3
+ 80394cc:	e21a      	b.n	8039904 <HAL_RCC_OscConfig+0x8a4>
+      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)
+ 80394ce:	4b22      	ldr	r3, [pc, #136]	@ (8039558 <HAL_RCC_OscConfig+0x4f8>)
+ 80394d0:	6f5b      	ldr	r3, [r3, #116]	@ 0x74
+ 80394d2:	f003 0302 	and.w	r3, r3, #2
+ 80394d6:	2b00      	cmp	r3, #0
+ 80394d8:	d0f0      	beq.n	80394bc <HAL_RCC_OscConfig+0x45c>
+ 80394da:	e018      	b.n	803950e <HAL_RCC_OscConfig+0x4ae>
+      }
+    }
+    else
+    {
+      /* Disable the Internal Low Speed oscillator (LSI). */
+      __HAL_RCC_LSI_DISABLE();
+ 80394dc:	4b1e      	ldr	r3, [pc, #120]	@ (8039558 <HAL_RCC_OscConfig+0x4f8>)
+ 80394de:	6f5b      	ldr	r3, [r3, #116]	@ 0x74
+ 80394e0:	4a1d      	ldr	r2, [pc, #116]	@ (8039558 <HAL_RCC_OscConfig+0x4f8>)
+ 80394e2:	f023 0301 	bic.w	r3, r3, #1
+ 80394e6:	6753      	str	r3, [r2, #116]	@ 0x74
+
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+ 80394e8:	f7f8 fa22 	bl	8031930 <HAL_GetTick>
+ 80394ec:	6278      	str	r0, [r7, #36]	@ 0x24
+
+      /* Wait till LSI is ready */
+      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)
+ 80394ee:	e008      	b.n	8039502 <HAL_RCC_OscConfig+0x4a2>
+      {
+        if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
+ 80394f0:	f7f8 fa1e 	bl	8031930 <HAL_GetTick>
+ 80394f4:	4602      	mov	r2, r0
+ 80394f6:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 80394f8:	1ad3      	subs	r3, r2, r3
+ 80394fa:	2b02      	cmp	r3, #2
+ 80394fc:	d901      	bls.n	8039502 <HAL_RCC_OscConfig+0x4a2>
+        {
+          return HAL_TIMEOUT;
+ 80394fe:	2303      	movs	r3, #3
+ 8039500:	e200      	b.n	8039904 <HAL_RCC_OscConfig+0x8a4>
+      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)
+ 8039502:	4b15      	ldr	r3, [pc, #84]	@ (8039558 <HAL_RCC_OscConfig+0x4f8>)
+ 8039504:	6f5b      	ldr	r3, [r3, #116]	@ 0x74
+ 8039506:	f003 0302 	and.w	r3, r3, #2
+ 803950a:	2b00      	cmp	r3, #0
+ 803950c:	d1f0      	bne.n	80394f0 <HAL_RCC_OscConfig+0x490>
+      }
+    }
+  }
+
+  /*------------------------------ HSI48 Configuration -------------------------*/
+  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
+ 803950e:	687b      	ldr	r3, [r7, #4]
+ 8039510:	681b      	ldr	r3, [r3, #0]
+ 8039512:	f003 0320 	and.w	r3, r3, #32
+ 8039516:	2b00      	cmp	r3, #0
+ 8039518:	d039      	beq.n	803958e <HAL_RCC_OscConfig+0x52e>
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));
+
+    /* Check the HSI48 State */
+    if ((RCC_OscInitStruct->HSI48State) != RCC_HSI48_OFF)
+ 803951a:	687b      	ldr	r3, [r7, #4]
+ 803951c:	699b      	ldr	r3, [r3, #24]
+ 803951e:	2b00      	cmp	r3, #0
+ 8039520:	d01c      	beq.n	803955c <HAL_RCC_OscConfig+0x4fc>
+    {
+      /* Enable the Internal Low Speed oscillator (HSI48). */
+      __HAL_RCC_HSI48_ENABLE();
+ 8039522:	4b0d      	ldr	r3, [pc, #52]	@ (8039558 <HAL_RCC_OscConfig+0x4f8>)
+ 8039524:	681b      	ldr	r3, [r3, #0]
+ 8039526:	4a0c      	ldr	r2, [pc, #48]	@ (8039558 <HAL_RCC_OscConfig+0x4f8>)
+ 8039528:	f443 5380 	orr.w	r3, r3, #4096	@ 0x1000
+ 803952c:	6013      	str	r3, [r2, #0]
+
+      /* Get time-out */
+      tickstart = HAL_GetTick();
+ 803952e:	f7f8 f9ff 	bl	8031930 <HAL_GetTick>
+ 8039532:	6278      	str	r0, [r7, #36]	@ 0x24
+
+      /* Wait till HSI48 is ready */
+      while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U)
+ 8039534:	e008      	b.n	8039548 <HAL_RCC_OscConfig+0x4e8>
+      {
+        if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
+ 8039536:	f7f8 f9fb 	bl	8031930 <HAL_GetTick>
+ 803953a:	4602      	mov	r2, r0
+ 803953c:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 803953e:	1ad3      	subs	r3, r2, r3
+ 8039540:	2b02      	cmp	r3, #2
+ 8039542:	d901      	bls.n	8039548 <HAL_RCC_OscConfig+0x4e8>
+        {
+          return HAL_TIMEOUT;
+ 8039544:	2303      	movs	r3, #3
+ 8039546:	e1dd      	b.n	8039904 <HAL_RCC_OscConfig+0x8a4>
+      while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U)
+ 8039548:	4b03      	ldr	r3, [pc, #12]	@ (8039558 <HAL_RCC_OscConfig+0x4f8>)
+ 803954a:	681b      	ldr	r3, [r3, #0]
+ 803954c:	f403 5300 	and.w	r3, r3, #8192	@ 0x2000
+ 8039550:	2b00      	cmp	r3, #0
+ 8039552:	d0f0      	beq.n	8039536 <HAL_RCC_OscConfig+0x4d6>
+ 8039554:	e01b      	b.n	803958e <HAL_RCC_OscConfig+0x52e>
+ 8039556:	bf00      	nop
+ 8039558:	58024400 	.word	0x58024400
+      }
+    }
+    else
+    {
+      /* Disable the Internal Low Speed oscillator (HSI48). */
+      __HAL_RCC_HSI48_DISABLE();
+ 803955c:	4b9b      	ldr	r3, [pc, #620]	@ (80397cc <HAL_RCC_OscConfig+0x76c>)
+ 803955e:	681b      	ldr	r3, [r3, #0]
+ 8039560:	4a9a      	ldr	r2, [pc, #616]	@ (80397cc <HAL_RCC_OscConfig+0x76c>)
+ 8039562:	f423 5380 	bic.w	r3, r3, #4096	@ 0x1000
+ 8039566:	6013      	str	r3, [r2, #0]
+
+      /* Get time-out */
+      tickstart = HAL_GetTick();
+ 8039568:	f7f8 f9e2 	bl	8031930 <HAL_GetTick>
+ 803956c:	6278      	str	r0, [r7, #36]	@ 0x24
+
+      /* Wait till HSI48 is ready */
+      while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U)
+ 803956e:	e008      	b.n	8039582 <HAL_RCC_OscConfig+0x522>
+      {
+        if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
+ 8039570:	f7f8 f9de 	bl	8031930 <HAL_GetTick>
+ 8039574:	4602      	mov	r2, r0
+ 8039576:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 8039578:	1ad3      	subs	r3, r2, r3
+ 803957a:	2b02      	cmp	r3, #2
+ 803957c:	d901      	bls.n	8039582 <HAL_RCC_OscConfig+0x522>
+        {
+          return HAL_TIMEOUT;
+ 803957e:	2303      	movs	r3, #3
+ 8039580:	e1c0      	b.n	8039904 <HAL_RCC_OscConfig+0x8a4>
+      while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U)
+ 8039582:	4b92      	ldr	r3, [pc, #584]	@ (80397cc <HAL_RCC_OscConfig+0x76c>)
+ 8039584:	681b      	ldr	r3, [r3, #0]
+ 8039586:	f403 5300 	and.w	r3, r3, #8192	@ 0x2000
+ 803958a:	2b00      	cmp	r3, #0
+ 803958c:	d1f0      	bne.n	8039570 <HAL_RCC_OscConfig+0x510>
+        }
+      }
+    }
+  }
+  /*------------------------------ LSE Configuration -------------------------*/
+  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
+ 803958e:	687b      	ldr	r3, [r7, #4]
+ 8039590:	681b      	ldr	r3, [r3, #0]
+ 8039592:	f003 0304 	and.w	r3, r3, #4
+ 8039596:	2b00      	cmp	r3, #0
+ 8039598:	f000 8081 	beq.w	803969e <HAL_RCC_OscConfig+0x63e>
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
+
+    /* Enable write access to Backup domain */
+    PWR->CR1 |= PWR_CR1_DBP;
+ 803959c:	4b8c      	ldr	r3, [pc, #560]	@ (80397d0 <HAL_RCC_OscConfig+0x770>)
+ 803959e:	681b      	ldr	r3, [r3, #0]
+ 80395a0:	4a8b      	ldr	r2, [pc, #556]	@ (80397d0 <HAL_RCC_OscConfig+0x770>)
+ 80395a2:	f443 7380 	orr.w	r3, r3, #256	@ 0x100
+ 80395a6:	6013      	str	r3, [r2, #0]
+
+    /* Wait for Backup domain Write protection disable */
+    tickstart = HAL_GetTick();
+ 80395a8:	f7f8 f9c2 	bl	8031930 <HAL_GetTick>
+ 80395ac:	6278      	str	r0, [r7, #36]	@ 0x24
+
+    while ((PWR->CR1 & PWR_CR1_DBP) == 0U)
+ 80395ae:	e008      	b.n	80395c2 <HAL_RCC_OscConfig+0x562>
+    {
+      if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
+ 80395b0:	f7f8 f9be 	bl	8031930 <HAL_GetTick>
+ 80395b4:	4602      	mov	r2, r0
+ 80395b6:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 80395b8:	1ad3      	subs	r3, r2, r3
+ 80395ba:	2b64      	cmp	r3, #100	@ 0x64
+ 80395bc:	d901      	bls.n	80395c2 <HAL_RCC_OscConfig+0x562>
+      {
+        return HAL_TIMEOUT;
+ 80395be:	2303      	movs	r3, #3
+ 80395c0:	e1a0      	b.n	8039904 <HAL_RCC_OscConfig+0x8a4>
+    while ((PWR->CR1 & PWR_CR1_DBP) == 0U)
+ 80395c2:	4b83      	ldr	r3, [pc, #524]	@ (80397d0 <HAL_RCC_OscConfig+0x770>)
+ 80395c4:	681b      	ldr	r3, [r3, #0]
+ 80395c6:	f403 7380 	and.w	r3, r3, #256	@ 0x100
+ 80395ca:	2b00      	cmp	r3, #0
+ 80395cc:	d0f0      	beq.n	80395b0 <HAL_RCC_OscConfig+0x550>
+      }
+    }
+
+    /* Set the new LSE configuration -----------------------------------------*/
+    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
+ 80395ce:	687b      	ldr	r3, [r7, #4]
+ 80395d0:	689b      	ldr	r3, [r3, #8]
+ 80395d2:	2b01      	cmp	r3, #1
+ 80395d4:	d106      	bne.n	80395e4 <HAL_RCC_OscConfig+0x584>
+ 80395d6:	4b7d      	ldr	r3, [pc, #500]	@ (80397cc <HAL_RCC_OscConfig+0x76c>)
+ 80395d8:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
+ 80395da:	4a7c      	ldr	r2, [pc, #496]	@ (80397cc <HAL_RCC_OscConfig+0x76c>)
+ 80395dc:	f043 0301 	orr.w	r3, r3, #1
+ 80395e0:	6713      	str	r3, [r2, #112]	@ 0x70
+ 80395e2:	e02d      	b.n	8039640 <HAL_RCC_OscConfig+0x5e0>
+ 80395e4:	687b      	ldr	r3, [r7, #4]
+ 80395e6:	689b      	ldr	r3, [r3, #8]
+ 80395e8:	2b00      	cmp	r3, #0
+ 80395ea:	d10c      	bne.n	8039606 <HAL_RCC_OscConfig+0x5a6>
+ 80395ec:	4b77      	ldr	r3, [pc, #476]	@ (80397cc <HAL_RCC_OscConfig+0x76c>)
+ 80395ee:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
+ 80395f0:	4a76      	ldr	r2, [pc, #472]	@ (80397cc <HAL_RCC_OscConfig+0x76c>)
+ 80395f2:	f023 0301 	bic.w	r3, r3, #1
+ 80395f6:	6713      	str	r3, [r2, #112]	@ 0x70
+ 80395f8:	4b74      	ldr	r3, [pc, #464]	@ (80397cc <HAL_RCC_OscConfig+0x76c>)
+ 80395fa:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
+ 80395fc:	4a73      	ldr	r2, [pc, #460]	@ (80397cc <HAL_RCC_OscConfig+0x76c>)
+ 80395fe:	f023 0304 	bic.w	r3, r3, #4
+ 8039602:	6713      	str	r3, [r2, #112]	@ 0x70
+ 8039604:	e01c      	b.n	8039640 <HAL_RCC_OscConfig+0x5e0>
+ 8039606:	687b      	ldr	r3, [r7, #4]
+ 8039608:	689b      	ldr	r3, [r3, #8]
+ 803960a:	2b05      	cmp	r3, #5
+ 803960c:	d10c      	bne.n	8039628 <HAL_RCC_OscConfig+0x5c8>
+ 803960e:	4b6f      	ldr	r3, [pc, #444]	@ (80397cc <HAL_RCC_OscConfig+0x76c>)
+ 8039610:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
+ 8039612:	4a6e      	ldr	r2, [pc, #440]	@ (80397cc <HAL_RCC_OscConfig+0x76c>)
+ 8039614:	f043 0304 	orr.w	r3, r3, #4
+ 8039618:	6713      	str	r3, [r2, #112]	@ 0x70
+ 803961a:	4b6c      	ldr	r3, [pc, #432]	@ (80397cc <HAL_RCC_OscConfig+0x76c>)
+ 803961c:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
+ 803961e:	4a6b      	ldr	r2, [pc, #428]	@ (80397cc <HAL_RCC_OscConfig+0x76c>)
+ 8039620:	f043 0301 	orr.w	r3, r3, #1
+ 8039624:	6713      	str	r3, [r2, #112]	@ 0x70
+ 8039626:	e00b      	b.n	8039640 <HAL_RCC_OscConfig+0x5e0>
+ 8039628:	4b68      	ldr	r3, [pc, #416]	@ (80397cc <HAL_RCC_OscConfig+0x76c>)
+ 803962a:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
+ 803962c:	4a67      	ldr	r2, [pc, #412]	@ (80397cc <HAL_RCC_OscConfig+0x76c>)
+ 803962e:	f023 0301 	bic.w	r3, r3, #1
+ 8039632:	6713      	str	r3, [r2, #112]	@ 0x70
+ 8039634:	4b65      	ldr	r3, [pc, #404]	@ (80397cc <HAL_RCC_OscConfig+0x76c>)
+ 8039636:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
+ 8039638:	4a64      	ldr	r2, [pc, #400]	@ (80397cc <HAL_RCC_OscConfig+0x76c>)
+ 803963a:	f023 0304 	bic.w	r3, r3, #4
+ 803963e:	6713      	str	r3, [r2, #112]	@ 0x70
+    /* Check the LSE State */
+    if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
+ 8039640:	687b      	ldr	r3, [r7, #4]
+ 8039642:	689b      	ldr	r3, [r3, #8]
+ 8039644:	2b00      	cmp	r3, #0
+ 8039646:	d015      	beq.n	8039674 <HAL_RCC_OscConfig+0x614>
+    {
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+ 8039648:	f7f8 f972 	bl	8031930 <HAL_GetTick>
+ 803964c:	6278      	str	r0, [r7, #36]	@ 0x24
+
+      /* Wait till LSE is ready */
+      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
+ 803964e:	e00a      	b.n	8039666 <HAL_RCC_OscConfig+0x606>
+      {
+        if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
+ 8039650:	f7f8 f96e 	bl	8031930 <HAL_GetTick>
+ 8039654:	4602      	mov	r2, r0
+ 8039656:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 8039658:	1ad3      	subs	r3, r2, r3
+ 803965a:	f241 3288 	movw	r2, #5000	@ 0x1388
+ 803965e:	4293      	cmp	r3, r2
+ 8039660:	d901      	bls.n	8039666 <HAL_RCC_OscConfig+0x606>
+        {
+          return HAL_TIMEOUT;
+ 8039662:	2303      	movs	r3, #3
+ 8039664:	e14e      	b.n	8039904 <HAL_RCC_OscConfig+0x8a4>
+      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
+ 8039666:	4b59      	ldr	r3, [pc, #356]	@ (80397cc <HAL_RCC_OscConfig+0x76c>)
+ 8039668:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
+ 803966a:	f003 0302 	and.w	r3, r3, #2
+ 803966e:	2b00      	cmp	r3, #0
+ 8039670:	d0ee      	beq.n	8039650 <HAL_RCC_OscConfig+0x5f0>
+ 8039672:	e014      	b.n	803969e <HAL_RCC_OscConfig+0x63e>
+      }
+    }
+    else
+    {
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+ 8039674:	f7f8 f95c 	bl	8031930 <HAL_GetTick>
+ 8039678:	6278      	str	r0, [r7, #36]	@ 0x24
+
+      /* Wait till LSE is disabled */
+      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
+ 803967a:	e00a      	b.n	8039692 <HAL_RCC_OscConfig+0x632>
+      {
+        if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
+ 803967c:	f7f8 f958 	bl	8031930 <HAL_GetTick>
+ 8039680:	4602      	mov	r2, r0
+ 8039682:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 8039684:	1ad3      	subs	r3, r2, r3
+ 8039686:	f241 3288 	movw	r2, #5000	@ 0x1388
+ 803968a:	4293      	cmp	r3, r2
+ 803968c:	d901      	bls.n	8039692 <HAL_RCC_OscConfig+0x632>
+        {
+          return HAL_TIMEOUT;
+ 803968e:	2303      	movs	r3, #3
+ 8039690:	e138      	b.n	8039904 <HAL_RCC_OscConfig+0x8a4>
+      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
+ 8039692:	4b4e      	ldr	r3, [pc, #312]	@ (80397cc <HAL_RCC_OscConfig+0x76c>)
+ 8039694:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
+ 8039696:	f003 0302 	and.w	r3, r3, #2
+ 803969a:	2b00      	cmp	r3, #0
+ 803969c:	d1ee      	bne.n	803967c <HAL_RCC_OscConfig+0x61c>
+    }
+  }
+  /*-------------------------------- PLL Configuration -----------------------*/
+  /* Check the parameters */
+  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
+  if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
+ 803969e:	687b      	ldr	r3, [r7, #4]
+ 80396a0:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 80396a2:	2b00      	cmp	r3, #0
+ 80396a4:	f000 812d 	beq.w	8039902 <HAL_RCC_OscConfig+0x8a2>
+  {
+    /* Check if the PLL is used as system clock or not */
+    if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL1)
+ 80396a8:	4b48      	ldr	r3, [pc, #288]	@ (80397cc <HAL_RCC_OscConfig+0x76c>)
+ 80396aa:	691b      	ldr	r3, [r3, #16]
+ 80396ac:	f003 0338 	and.w	r3, r3, #56	@ 0x38
+ 80396b0:	2b18      	cmp	r3, #24
+ 80396b2:	f000 80bd 	beq.w	8039830 <HAL_RCC_OscConfig+0x7d0>
+    {
+      if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
+ 80396b6:	687b      	ldr	r3, [r7, #4]
+ 80396b8:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 80396ba:	2b02      	cmp	r3, #2
+ 80396bc:	f040 809e 	bne.w	80397fc <HAL_RCC_OscConfig+0x79c>
+        assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
+        assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
+        assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN));
+
+        /* Disable the main PLL. */
+        __HAL_RCC_PLL_DISABLE();
+ 80396c0:	4b42      	ldr	r3, [pc, #264]	@ (80397cc <HAL_RCC_OscConfig+0x76c>)
+ 80396c2:	681b      	ldr	r3, [r3, #0]
+ 80396c4:	4a41      	ldr	r2, [pc, #260]	@ (80397cc <HAL_RCC_OscConfig+0x76c>)
+ 80396c6:	f023 7380 	bic.w	r3, r3, #16777216	@ 0x1000000
+ 80396ca:	6013      	str	r3, [r2, #0]
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+ 80396cc:	f7f8 f930 	bl	8031930 <HAL_GetTick>
+ 80396d0:	6278      	str	r0, [r7, #36]	@ 0x24
+
+        /* Wait till PLL is disabled */
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
+ 80396d2:	e008      	b.n	80396e6 <HAL_RCC_OscConfig+0x686>
+        {
+          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+ 80396d4:	f7f8 f92c 	bl	8031930 <HAL_GetTick>
+ 80396d8:	4602      	mov	r2, r0
+ 80396da:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 80396dc:	1ad3      	subs	r3, r2, r3
+ 80396de:	2b02      	cmp	r3, #2
+ 80396e0:	d901      	bls.n	80396e6 <HAL_RCC_OscConfig+0x686>
+          {
+            return HAL_TIMEOUT;
+ 80396e2:	2303      	movs	r3, #3
+ 80396e4:	e10e      	b.n	8039904 <HAL_RCC_OscConfig+0x8a4>
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
+ 80396e6:	4b39      	ldr	r3, [pc, #228]	@ (80397cc <HAL_RCC_OscConfig+0x76c>)
+ 80396e8:	681b      	ldr	r3, [r3, #0]
+ 80396ea:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
+ 80396ee:	2b00      	cmp	r3, #0
+ 80396f0:	d1f0      	bne.n	80396d4 <HAL_RCC_OscConfig+0x674>
+          }
+        }
+
+        /* Configure the main PLL clock source, multiplication and division factors. */
+        __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
+ 80396f2:	4b36      	ldr	r3, [pc, #216]	@ (80397cc <HAL_RCC_OscConfig+0x76c>)
+ 80396f4:	6a9a      	ldr	r2, [r3, #40]	@ 0x28
+ 80396f6:	4b37      	ldr	r3, [pc, #220]	@ (80397d4 <HAL_RCC_OscConfig+0x774>)
+ 80396f8:	4013      	ands	r3, r2
+ 80396fa:	687a      	ldr	r2, [r7, #4]
+ 80396fc:	6a91      	ldr	r1, [r2, #40]	@ 0x28
+ 80396fe:	687a      	ldr	r2, [r7, #4]
+ 8039700:	6ad2      	ldr	r2, [r2, #44]	@ 0x2c
+ 8039702:	0112      	lsls	r2, r2, #4
+ 8039704:	430a      	orrs	r2, r1
+ 8039706:	4931      	ldr	r1, [pc, #196]	@ (80397cc <HAL_RCC_OscConfig+0x76c>)
+ 8039708:	4313      	orrs	r3, r2
+ 803970a:	628b      	str	r3, [r1, #40]	@ 0x28
+ 803970c:	687b      	ldr	r3, [r7, #4]
+ 803970e:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
+ 8039710:	3b01      	subs	r3, #1
+ 8039712:	f3c3 0208 	ubfx	r2, r3, #0, #9
+ 8039716:	687b      	ldr	r3, [r7, #4]
+ 8039718:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
+ 803971a:	3b01      	subs	r3, #1
+ 803971c:	025b      	lsls	r3, r3, #9
+ 803971e:	b29b      	uxth	r3, r3
+ 8039720:	431a      	orrs	r2, r3
+ 8039722:	687b      	ldr	r3, [r7, #4]
+ 8039724:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
+ 8039726:	3b01      	subs	r3, #1
+ 8039728:	041b      	lsls	r3, r3, #16
+ 803972a:	f403 03fe 	and.w	r3, r3, #8323072	@ 0x7f0000
+ 803972e:	431a      	orrs	r2, r3
+ 8039730:	687b      	ldr	r3, [r7, #4]
+ 8039732:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 8039734:	3b01      	subs	r3, #1
+ 8039736:	061b      	lsls	r3, r3, #24
+ 8039738:	f003 43fe 	and.w	r3, r3, #2130706432	@ 0x7f000000
+ 803973c:	4923      	ldr	r1, [pc, #140]	@ (80397cc <HAL_RCC_OscConfig+0x76c>)
+ 803973e:	4313      	orrs	r3, r2
+ 8039740:	630b      	str	r3, [r1, #48]	@ 0x30
+                             RCC_OscInitStruct->PLL.PLLP,
+                             RCC_OscInitStruct->PLL.PLLQ,
+                             RCC_OscInitStruct->PLL.PLLR);
+
+        /* Disable PLLFRACN . */
+        __HAL_RCC_PLLFRACN_DISABLE();
+ 8039742:	4b22      	ldr	r3, [pc, #136]	@ (80397cc <HAL_RCC_OscConfig+0x76c>)
+ 8039744:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 8039746:	4a21      	ldr	r2, [pc, #132]	@ (80397cc <HAL_RCC_OscConfig+0x76c>)
+ 8039748:	f023 0301 	bic.w	r3, r3, #1
+ 803974c:	62d3      	str	r3, [r2, #44]	@ 0x2c
+
+        /* Configure PLL PLL1FRACN */
+        __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN);
+ 803974e:	4b1f      	ldr	r3, [pc, #124]	@ (80397cc <HAL_RCC_OscConfig+0x76c>)
+ 8039750:	6b5a      	ldr	r2, [r3, #52]	@ 0x34
+ 8039752:	4b21      	ldr	r3, [pc, #132]	@ (80397d8 <HAL_RCC_OscConfig+0x778>)
+ 8039754:	4013      	ands	r3, r2
+ 8039756:	687a      	ldr	r2, [r7, #4]
+ 8039758:	6c92      	ldr	r2, [r2, #72]	@ 0x48
+ 803975a:	00d2      	lsls	r2, r2, #3
+ 803975c:	491b      	ldr	r1, [pc, #108]	@ (80397cc <HAL_RCC_OscConfig+0x76c>)
+ 803975e:	4313      	orrs	r3, r2
+ 8039760:	634b      	str	r3, [r1, #52]	@ 0x34
+
+        /* Select PLL1 input reference frequency range: VCI */
+        __HAL_RCC_PLL_VCIRANGE(RCC_OscInitStruct->PLL.PLLRGE) ;
+ 8039762:	4b1a      	ldr	r3, [pc, #104]	@ (80397cc <HAL_RCC_OscConfig+0x76c>)
+ 8039764:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 8039766:	f023 020c 	bic.w	r2, r3, #12
+ 803976a:	687b      	ldr	r3, [r7, #4]
+ 803976c:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
+ 803976e:	4917      	ldr	r1, [pc, #92]	@ (80397cc <HAL_RCC_OscConfig+0x76c>)
+ 8039770:	4313      	orrs	r3, r2
+ 8039772:	62cb      	str	r3, [r1, #44]	@ 0x2c
+
+        /* Select PLL1 output frequency range : VCO */
+        __HAL_RCC_PLL_VCORANGE(RCC_OscInitStruct->PLL.PLLVCOSEL) ;
+ 8039774:	4b15      	ldr	r3, [pc, #84]	@ (80397cc <HAL_RCC_OscConfig+0x76c>)
+ 8039776:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 8039778:	f023 0202 	bic.w	r2, r3, #2
+ 803977c:	687b      	ldr	r3, [r7, #4]
+ 803977e:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
+ 8039780:	4912      	ldr	r1, [pc, #72]	@ (80397cc <HAL_RCC_OscConfig+0x76c>)
+ 8039782:	4313      	orrs	r3, r2
+ 8039784:	62cb      	str	r3, [r1, #44]	@ 0x2c
+
+        /* Enable PLL System Clock output. */
+        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP);
+ 8039786:	4b11      	ldr	r3, [pc, #68]	@ (80397cc <HAL_RCC_OscConfig+0x76c>)
+ 8039788:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 803978a:	4a10      	ldr	r2, [pc, #64]	@ (80397cc <HAL_RCC_OscConfig+0x76c>)
+ 803978c:	f443 3380 	orr.w	r3, r3, #65536	@ 0x10000
+ 8039790:	62d3      	str	r3, [r2, #44]	@ 0x2c
+
+        /* Enable PLL1Q Clock output. */
+        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+ 8039792:	4b0e      	ldr	r3, [pc, #56]	@ (80397cc <HAL_RCC_OscConfig+0x76c>)
+ 8039794:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 8039796:	4a0d      	ldr	r2, [pc, #52]	@ (80397cc <HAL_RCC_OscConfig+0x76c>)
+ 8039798:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
+ 803979c:	62d3      	str	r3, [r2, #44]	@ 0x2c
+
+        /* Enable PLL1R  Clock output. */
+        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR);
+ 803979e:	4b0b      	ldr	r3, [pc, #44]	@ (80397cc <HAL_RCC_OscConfig+0x76c>)
+ 80397a0:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 80397a2:	4a0a      	ldr	r2, [pc, #40]	@ (80397cc <HAL_RCC_OscConfig+0x76c>)
+ 80397a4:	f443 2380 	orr.w	r3, r3, #262144	@ 0x40000
+ 80397a8:	62d3      	str	r3, [r2, #44]	@ 0x2c
+
+        /* Enable PLL1FRACN . */
+        __HAL_RCC_PLLFRACN_ENABLE();
+ 80397aa:	4b08      	ldr	r3, [pc, #32]	@ (80397cc <HAL_RCC_OscConfig+0x76c>)
+ 80397ac:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 80397ae:	4a07      	ldr	r2, [pc, #28]	@ (80397cc <HAL_RCC_OscConfig+0x76c>)
+ 80397b0:	f043 0301 	orr.w	r3, r3, #1
+ 80397b4:	62d3      	str	r3, [r2, #44]	@ 0x2c
+
+        /* Enable the main PLL. */
+        __HAL_RCC_PLL_ENABLE();
+ 80397b6:	4b05      	ldr	r3, [pc, #20]	@ (80397cc <HAL_RCC_OscConfig+0x76c>)
+ 80397b8:	681b      	ldr	r3, [r3, #0]
+ 80397ba:	4a04      	ldr	r2, [pc, #16]	@ (80397cc <HAL_RCC_OscConfig+0x76c>)
+ 80397bc:	f043 7380 	orr.w	r3, r3, #16777216	@ 0x1000000
+ 80397c0:	6013      	str	r3, [r2, #0]
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+ 80397c2:	f7f8 f8b5 	bl	8031930 <HAL_GetTick>
+ 80397c6:	6278      	str	r0, [r7, #36]	@ 0x24
+
+        /* Wait till PLL is ready */
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
+ 80397c8:	e011      	b.n	80397ee <HAL_RCC_OscConfig+0x78e>
+ 80397ca:	bf00      	nop
+ 80397cc:	58024400 	.word	0x58024400
+ 80397d0:	58024800 	.word	0x58024800
+ 80397d4:	fffffc0c 	.word	0xfffffc0c
+ 80397d8:	ffff0007 	.word	0xffff0007
+        {
+          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+ 80397dc:	f7f8 f8a8 	bl	8031930 <HAL_GetTick>
+ 80397e0:	4602      	mov	r2, r0
+ 80397e2:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 80397e4:	1ad3      	subs	r3, r2, r3
+ 80397e6:	2b02      	cmp	r3, #2
+ 80397e8:	d901      	bls.n	80397ee <HAL_RCC_OscConfig+0x78e>
+          {
+            return HAL_TIMEOUT;
+ 80397ea:	2303      	movs	r3, #3
+ 80397ec:	e08a      	b.n	8039904 <HAL_RCC_OscConfig+0x8a4>
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
+ 80397ee:	4b47      	ldr	r3, [pc, #284]	@ (803990c <HAL_RCC_OscConfig+0x8ac>)
+ 80397f0:	681b      	ldr	r3, [r3, #0]
+ 80397f2:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
+ 80397f6:	2b00      	cmp	r3, #0
+ 80397f8:	d0f0      	beq.n	80397dc <HAL_RCC_OscConfig+0x77c>
+ 80397fa:	e082      	b.n	8039902 <HAL_RCC_OscConfig+0x8a2>
+        }
+      }
+      else
+      {
+        /* Disable the main PLL. */
+        __HAL_RCC_PLL_DISABLE();
+ 80397fc:	4b43      	ldr	r3, [pc, #268]	@ (803990c <HAL_RCC_OscConfig+0x8ac>)
+ 80397fe:	681b      	ldr	r3, [r3, #0]
+ 8039800:	4a42      	ldr	r2, [pc, #264]	@ (803990c <HAL_RCC_OscConfig+0x8ac>)
+ 8039802:	f023 7380 	bic.w	r3, r3, #16777216	@ 0x1000000
+ 8039806:	6013      	str	r3, [r2, #0]
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+ 8039808:	f7f8 f892 	bl	8031930 <HAL_GetTick>
+ 803980c:	6278      	str	r0, [r7, #36]	@ 0x24
+
+        /* Wait till PLL is disabled */
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
+ 803980e:	e008      	b.n	8039822 <HAL_RCC_OscConfig+0x7c2>
+        {
+          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+ 8039810:	f7f8 f88e 	bl	8031930 <HAL_GetTick>
+ 8039814:	4602      	mov	r2, r0
+ 8039816:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 8039818:	1ad3      	subs	r3, r2, r3
+ 803981a:	2b02      	cmp	r3, #2
+ 803981c:	d901      	bls.n	8039822 <HAL_RCC_OscConfig+0x7c2>
+          {
+            return HAL_TIMEOUT;
+ 803981e:	2303      	movs	r3, #3
+ 8039820:	e070      	b.n	8039904 <HAL_RCC_OscConfig+0x8a4>
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
+ 8039822:	4b3a      	ldr	r3, [pc, #232]	@ (803990c <HAL_RCC_OscConfig+0x8ac>)
+ 8039824:	681b      	ldr	r3, [r3, #0]
+ 8039826:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
+ 803982a:	2b00      	cmp	r3, #0
+ 803982c:	d1f0      	bne.n	8039810 <HAL_RCC_OscConfig+0x7b0>
+ 803982e:	e068      	b.n	8039902 <HAL_RCC_OscConfig+0x8a2>
+      }
+    }
+    else
+    {
+      /* Do not return HAL_ERROR if request repeats the current configuration */
+      temp1_pllckcfg = RCC->PLLCKSELR;
+ 8039830:	4b36      	ldr	r3, [pc, #216]	@ (803990c <HAL_RCC_OscConfig+0x8ac>)
+ 8039832:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 8039834:	613b      	str	r3, [r7, #16]
+      temp2_pllckcfg = RCC->PLL1DIVR;
+ 8039836:	4b35      	ldr	r3, [pc, #212]	@ (803990c <HAL_RCC_OscConfig+0x8ac>)
+ 8039838:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
+ 803983a:	60fb      	str	r3, [r7, #12]
+      if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
+ 803983c:	687b      	ldr	r3, [r7, #4]
+ 803983e:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 8039840:	2b01      	cmp	r3, #1
+ 8039842:	d031      	beq.n	80398a8 <HAL_RCC_OscConfig+0x848>
+          (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
+ 8039844:	693b      	ldr	r3, [r7, #16]
+ 8039846:	f003 0203 	and.w	r2, r3, #3
+ 803984a:	687b      	ldr	r3, [r7, #4]
+ 803984c:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+      if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
+ 803984e:	429a      	cmp	r2, r3
+ 8039850:	d12a      	bne.n	80398a8 <HAL_RCC_OscConfig+0x848>
+          ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) ||
+ 8039852:	693b      	ldr	r3, [r7, #16]
+ 8039854:	091b      	lsrs	r3, r3, #4
+ 8039856:	f003 023f 	and.w	r2, r3, #63	@ 0x3f
+ 803985a:	687b      	ldr	r3, [r7, #4]
+ 803985c:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+          (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
+ 803985e:	429a      	cmp	r2, r3
+ 8039860:	d122      	bne.n	80398a8 <HAL_RCC_OscConfig+0x848>
+          (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) ||
+ 8039862:	68fb      	ldr	r3, [r7, #12]
+ 8039864:	f3c3 0208 	ubfx	r2, r3, #0, #9
+ 8039868:	687b      	ldr	r3, [r7, #4]
+ 803986a:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
+ 803986c:	3b01      	subs	r3, #1
+          ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) ||
+ 803986e:	429a      	cmp	r2, r3
+ 8039870:	d11a      	bne.n	80398a8 <HAL_RCC_OscConfig+0x848>
+          ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) ||
+ 8039872:	68fb      	ldr	r3, [r7, #12]
+ 8039874:	0a5b      	lsrs	r3, r3, #9
+ 8039876:	f003 027f 	and.w	r2, r3, #127	@ 0x7f
+ 803987a:	687b      	ldr	r3, [r7, #4]
+ 803987c:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
+ 803987e:	3b01      	subs	r3, #1
+          (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) ||
+ 8039880:	429a      	cmp	r2, r3
+ 8039882:	d111      	bne.n	80398a8 <HAL_RCC_OscConfig+0x848>
+          ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) ||
+ 8039884:	68fb      	ldr	r3, [r7, #12]
+ 8039886:	0c1b      	lsrs	r3, r3, #16
+ 8039888:	f003 027f 	and.w	r2, r3, #127	@ 0x7f
+ 803988c:	687b      	ldr	r3, [r7, #4]
+ 803988e:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
+ 8039890:	3b01      	subs	r3, #1
+          ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) ||
+ 8039892:	429a      	cmp	r2, r3
+ 8039894:	d108      	bne.n	80398a8 <HAL_RCC_OscConfig+0x848>
+          ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) != (RCC_OscInitStruct->PLL.PLLR - 1U)))
+ 8039896:	68fb      	ldr	r3, [r7, #12]
+ 8039898:	0e1b      	lsrs	r3, r3, #24
+ 803989a:	f003 027f 	and.w	r2, r3, #127	@ 0x7f
+ 803989e:	687b      	ldr	r3, [r7, #4]
+ 80398a0:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 80398a2:	3b01      	subs	r3, #1
+          ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) ||
+ 80398a4:	429a      	cmp	r2, r3
+ 80398a6:	d001      	beq.n	80398ac <HAL_RCC_OscConfig+0x84c>
+      {
+        return HAL_ERROR;
+ 80398a8:	2301      	movs	r3, #1
+ 80398aa:	e02b      	b.n	8039904 <HAL_RCC_OscConfig+0x8a4>
+      }
+      else
+      {
+        /* Check if only fractional part needs to be updated  */
+        temp1_pllckcfg = ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> RCC_PLL1FRACR_FRACN1_Pos);
+ 80398ac:	4b17      	ldr	r3, [pc, #92]	@ (803990c <HAL_RCC_OscConfig+0x8ac>)
+ 80398ae:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
+ 80398b0:	08db      	lsrs	r3, r3, #3
+ 80398b2:	f3c3 030c 	ubfx	r3, r3, #0, #13
+ 80398b6:	613b      	str	r3, [r7, #16]
+        if (RCC_OscInitStruct->PLL.PLLFRACN != temp1_pllckcfg)
+ 80398b8:	687b      	ldr	r3, [r7, #4]
+ 80398ba:	6c9b      	ldr	r3, [r3, #72]	@ 0x48
+ 80398bc:	693a      	ldr	r2, [r7, #16]
+ 80398be:	429a      	cmp	r2, r3
+ 80398c0:	d01f      	beq.n	8039902 <HAL_RCC_OscConfig+0x8a2>
+        {
+          assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN));
+          /* Disable PLL1FRACEN */
+          __HAL_RCC_PLLFRACN_DISABLE();
+ 80398c2:	4b12      	ldr	r3, [pc, #72]	@ (803990c <HAL_RCC_OscConfig+0x8ac>)
+ 80398c4:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 80398c6:	4a11      	ldr	r2, [pc, #68]	@ (803990c <HAL_RCC_OscConfig+0x8ac>)
+ 80398c8:	f023 0301 	bic.w	r3, r3, #1
+ 80398cc:	62d3      	str	r3, [r2, #44]	@ 0x2c
+          /* Get Start Tick*/
+          tickstart = HAL_GetTick();
+ 80398ce:	f7f8 f82f 	bl	8031930 <HAL_GetTick>
+ 80398d2:	6278      	str	r0, [r7, #36]	@ 0x24
+          /* Wait at least 2 CK_REF (PLL input source divided by M) period to make sure next latched value will be taken into account. */
+          while ((HAL_GetTick() - tickstart) < PLL_FRAC_TIMEOUT_VALUE)
+ 80398d4:	bf00      	nop
+ 80398d6:	f7f8 f82b 	bl	8031930 <HAL_GetTick>
+ 80398da:	4602      	mov	r2, r0
+ 80398dc:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 80398de:	4293      	cmp	r3, r2
+ 80398e0:	d0f9      	beq.n	80398d6 <HAL_RCC_OscConfig+0x876>
+          {
+          }
+          /* Configure PLL1 PLL1FRACN */
+          __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN);
+ 80398e2:	4b0a      	ldr	r3, [pc, #40]	@ (803990c <HAL_RCC_OscConfig+0x8ac>)
+ 80398e4:	6b5a      	ldr	r2, [r3, #52]	@ 0x34
+ 80398e6:	4b0a      	ldr	r3, [pc, #40]	@ (8039910 <HAL_RCC_OscConfig+0x8b0>)
+ 80398e8:	4013      	ands	r3, r2
+ 80398ea:	687a      	ldr	r2, [r7, #4]
+ 80398ec:	6c92      	ldr	r2, [r2, #72]	@ 0x48
+ 80398ee:	00d2      	lsls	r2, r2, #3
+ 80398f0:	4906      	ldr	r1, [pc, #24]	@ (803990c <HAL_RCC_OscConfig+0x8ac>)
+ 80398f2:	4313      	orrs	r3, r2
+ 80398f4:	634b      	str	r3, [r1, #52]	@ 0x34
+          /* Enable PLL1FRACEN to latch new value. */
+          __HAL_RCC_PLLFRACN_ENABLE();
+ 80398f6:	4b05      	ldr	r3, [pc, #20]	@ (803990c <HAL_RCC_OscConfig+0x8ac>)
+ 80398f8:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 80398fa:	4a04      	ldr	r2, [pc, #16]	@ (803990c <HAL_RCC_OscConfig+0x8ac>)
+ 80398fc:	f043 0301 	orr.w	r3, r3, #1
+ 8039900:	62d3      	str	r3, [r2, #44]	@ 0x2c
+        }
+      }
+    }
+  }
+  return HAL_OK;
+ 8039902:	2300      	movs	r3, #0
+}
+ 8039904:	4618      	mov	r0, r3
+ 8039906:	3730      	adds	r7, #48	@ 0x30
+ 8039908:	46bd      	mov	sp, r7
+ 803990a:	bd80      	pop	{r7, pc}
+ 803990c:	58024400 	.word	0x58024400
+ 8039910:	ffff0007 	.word	0xffff0007
+
+08039914 <HAL_RCC_ClockConfig>:
+  *         D1CPRE[3:0] bits to ensure that  Domain1 core clock not exceed the maximum allowed frequency
+  *         (for more details refer to section above "Initialization/de-initialization functions")
+  * @retval None
+  */
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
+{
+ 8039914:	b580      	push	{r7, lr}
+ 8039916:	b086      	sub	sp, #24
+ 8039918:	af00      	add	r7, sp, #0
+ 803991a:	6078      	str	r0, [r7, #4]
+ 803991c:	6039      	str	r1, [r7, #0]
+  HAL_StatusTypeDef halstatus;
+  uint32_t tickstart;
+  uint32_t common_system_clock;
+
+  /* Check Null pointer */
+  if (RCC_ClkInitStruct == NULL)
+ 803991e:	687b      	ldr	r3, [r7, #4]
+ 8039920:	2b00      	cmp	r3, #0
+ 8039922:	d101      	bne.n	8039928 <HAL_RCC_ClockConfig+0x14>
+  {
+    return HAL_ERROR;
+ 8039924:	2301      	movs	r3, #1
+ 8039926:	e19c      	b.n	8039c62 <HAL_RCC_ClockConfig+0x34e>
+  /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
+    must be correctly programmed according to the frequency of the CPU clock
+    (HCLK) and the supply voltage of the device. */
+
+  /* Increasing the CPU frequency */
+  if (FLatency > __HAL_FLASH_GET_LATENCY())
+ 8039928:	4b8a      	ldr	r3, [pc, #552]	@ (8039b54 <HAL_RCC_ClockConfig+0x240>)
+ 803992a:	681b      	ldr	r3, [r3, #0]
+ 803992c:	f003 030f 	and.w	r3, r3, #15
+ 8039930:	683a      	ldr	r2, [r7, #0]
+ 8039932:	429a      	cmp	r2, r3
+ 8039934:	d910      	bls.n	8039958 <HAL_RCC_ClockConfig+0x44>
+  {
+    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+    __HAL_FLASH_SET_LATENCY(FLatency);
+ 8039936:	4b87      	ldr	r3, [pc, #540]	@ (8039b54 <HAL_RCC_ClockConfig+0x240>)
+ 8039938:	681b      	ldr	r3, [r3, #0]
+ 803993a:	f023 020f 	bic.w	r2, r3, #15
+ 803993e:	4985      	ldr	r1, [pc, #532]	@ (8039b54 <HAL_RCC_ClockConfig+0x240>)
+ 8039940:	683b      	ldr	r3, [r7, #0]
+ 8039942:	4313      	orrs	r3, r2
+ 8039944:	600b      	str	r3, [r1, #0]
+
+    /* Check that the new number of wait states is taken into account to access the Flash
+    memory by reading the FLASH_ACR register */
+    if (__HAL_FLASH_GET_LATENCY() != FLatency)
+ 8039946:	4b83      	ldr	r3, [pc, #524]	@ (8039b54 <HAL_RCC_ClockConfig+0x240>)
+ 8039948:	681b      	ldr	r3, [r3, #0]
+ 803994a:	f003 030f 	and.w	r3, r3, #15
+ 803994e:	683a      	ldr	r2, [r7, #0]
+ 8039950:	429a      	cmp	r2, r3
+ 8039952:	d001      	beq.n	8039958 <HAL_RCC_ClockConfig+0x44>
+    {
+      return HAL_ERROR;
+ 8039954:	2301      	movs	r3, #1
+ 8039956:	e184      	b.n	8039c62 <HAL_RCC_ClockConfig+0x34e>
+
+  }
+
+  /* Increasing the BUS frequency divider */
+  /*-------------------------- D1PCLK1/CDPCLK1 Configuration ---------------------------*/
+  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1)
+ 8039958:	687b      	ldr	r3, [r7, #4]
+ 803995a:	681b      	ldr	r3, [r3, #0]
+ 803995c:	f003 0304 	and.w	r3, r3, #4
+ 8039960:	2b00      	cmp	r3, #0
+ 8039962:	d010      	beq.n	8039986 <HAL_RCC_ClockConfig+0x72>
+  {
+#if defined (RCC_D1CFGR_D1PPRE)
+    if ((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_D1PPRE))
+ 8039964:	687b      	ldr	r3, [r7, #4]
+ 8039966:	691a      	ldr	r2, [r3, #16]
+ 8039968:	4b7b      	ldr	r3, [pc, #492]	@ (8039b58 <HAL_RCC_ClockConfig+0x244>)
+ 803996a:	699b      	ldr	r3, [r3, #24]
+ 803996c:	f003 0370 	and.w	r3, r3, #112	@ 0x70
+ 8039970:	429a      	cmp	r2, r3
+ 8039972:	d908      	bls.n	8039986 <HAL_RCC_ClockConfig+0x72>
+    {
+      assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider));
+      MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider);
+ 8039974:	4b78      	ldr	r3, [pc, #480]	@ (8039b58 <HAL_RCC_ClockConfig+0x244>)
+ 8039976:	699b      	ldr	r3, [r3, #24]
+ 8039978:	f023 0270 	bic.w	r2, r3, #112	@ 0x70
+ 803997c:	687b      	ldr	r3, [r7, #4]
+ 803997e:	691b      	ldr	r3, [r3, #16]
+ 8039980:	4975      	ldr	r1, [pc, #468]	@ (8039b58 <HAL_RCC_ClockConfig+0x244>)
+ 8039982:	4313      	orrs	r3, r2
+ 8039984:	618b      	str	r3, [r1, #24]
+    }
+#endif
+  }
+
+  /*-------------------------- PCLK1 Configuration ---------------------------*/
+  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+ 8039986:	687b      	ldr	r3, [r7, #4]
+ 8039988:	681b      	ldr	r3, [r3, #0]
+ 803998a:	f003 0308 	and.w	r3, r3, #8
+ 803998e:	2b00      	cmp	r3, #0
+ 8039990:	d010      	beq.n	80399b4 <HAL_RCC_ClockConfig+0xa0>
+  {
+#if defined (RCC_D2CFGR_D2PPRE1)
+    if ((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1))
+ 8039992:	687b      	ldr	r3, [r7, #4]
+ 8039994:	695a      	ldr	r2, [r3, #20]
+ 8039996:	4b70      	ldr	r3, [pc, #448]	@ (8039b58 <HAL_RCC_ClockConfig+0x244>)
+ 8039998:	69db      	ldr	r3, [r3, #28]
+ 803999a:	f003 0370 	and.w	r3, r3, #112	@ 0x70
+ 803999e:	429a      	cmp	r2, r3
+ 80399a0:	d908      	bls.n	80399b4 <HAL_RCC_ClockConfig+0xa0>
+    {
+      assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider));
+      MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
+ 80399a2:	4b6d      	ldr	r3, [pc, #436]	@ (8039b58 <HAL_RCC_ClockConfig+0x244>)
+ 80399a4:	69db      	ldr	r3, [r3, #28]
+ 80399a6:	f023 0270 	bic.w	r2, r3, #112	@ 0x70
+ 80399aa:	687b      	ldr	r3, [r7, #4]
+ 80399ac:	695b      	ldr	r3, [r3, #20]
+ 80399ae:	496a      	ldr	r1, [pc, #424]	@ (8039b58 <HAL_RCC_ClockConfig+0x244>)
+ 80399b0:	4313      	orrs	r3, r2
+ 80399b2:	61cb      	str	r3, [r1, #28]
+      MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
+    }
+#endif
+  }
+  /*-------------------------- PCLK2 Configuration ---------------------------*/
+  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
+ 80399b4:	687b      	ldr	r3, [r7, #4]
+ 80399b6:	681b      	ldr	r3, [r3, #0]
+ 80399b8:	f003 0310 	and.w	r3, r3, #16
+ 80399bc:	2b00      	cmp	r3, #0
+ 80399be:	d010      	beq.n	80399e2 <HAL_RCC_ClockConfig+0xce>
+  {
+#if defined(RCC_D2CFGR_D2PPRE2)
+    if ((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2))
+ 80399c0:	687b      	ldr	r3, [r7, #4]
+ 80399c2:	699a      	ldr	r2, [r3, #24]
+ 80399c4:	4b64      	ldr	r3, [pc, #400]	@ (8039b58 <HAL_RCC_ClockConfig+0x244>)
+ 80399c6:	69db      	ldr	r3, [r3, #28]
+ 80399c8:	f403 63e0 	and.w	r3, r3, #1792	@ 0x700
+ 80399cc:	429a      	cmp	r2, r3
+ 80399ce:	d908      	bls.n	80399e2 <HAL_RCC_ClockConfig+0xce>
+    {
+      assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider));
+      MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider));
+ 80399d0:	4b61      	ldr	r3, [pc, #388]	@ (8039b58 <HAL_RCC_ClockConfig+0x244>)
+ 80399d2:	69db      	ldr	r3, [r3, #28]
+ 80399d4:	f423 62e0 	bic.w	r2, r3, #1792	@ 0x700
+ 80399d8:	687b      	ldr	r3, [r7, #4]
+ 80399da:	699b      	ldr	r3, [r3, #24]
+ 80399dc:	495e      	ldr	r1, [pc, #376]	@ (8039b58 <HAL_RCC_ClockConfig+0x244>)
+ 80399de:	4313      	orrs	r3, r2
+ 80399e0:	61cb      	str	r3, [r1, #28]
+    }
+#endif
+  }
+
+  /*-------------------------- D3PCLK1 Configuration ---------------------------*/
+  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1)
+ 80399e2:	687b      	ldr	r3, [r7, #4]
+ 80399e4:	681b      	ldr	r3, [r3, #0]
+ 80399e6:	f003 0320 	and.w	r3, r3, #32
+ 80399ea:	2b00      	cmp	r3, #0
+ 80399ec:	d010      	beq.n	8039a10 <HAL_RCC_ClockConfig+0xfc>
+  {
+#if defined(RCC_D3CFGR_D3PPRE)
+    if ((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->D3CFGR & RCC_D3CFGR_D3PPRE))
+ 80399ee:	687b      	ldr	r3, [r7, #4]
+ 80399f0:	69da      	ldr	r2, [r3, #28]
+ 80399f2:	4b59      	ldr	r3, [pc, #356]	@ (8039b58 <HAL_RCC_ClockConfig+0x244>)
+ 80399f4:	6a1b      	ldr	r3, [r3, #32]
+ 80399f6:	f003 0370 	and.w	r3, r3, #112	@ 0x70
+ 80399fa:	429a      	cmp	r2, r3
+ 80399fc:	d908      	bls.n	8039a10 <HAL_RCC_ClockConfig+0xfc>
+    {
+      assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider));
+      MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider));
+ 80399fe:	4b56      	ldr	r3, [pc, #344]	@ (8039b58 <HAL_RCC_ClockConfig+0x244>)
+ 8039a00:	6a1b      	ldr	r3, [r3, #32]
+ 8039a02:	f023 0270 	bic.w	r2, r3, #112	@ 0x70
+ 8039a06:	687b      	ldr	r3, [r7, #4]
+ 8039a08:	69db      	ldr	r3, [r3, #28]
+ 8039a0a:	4953      	ldr	r1, [pc, #332]	@ (8039b58 <HAL_RCC_ClockConfig+0x244>)
+ 8039a0c:	4313      	orrs	r3, r2
+ 8039a0e:	620b      	str	r3, [r1, #32]
+    }
+#endif
+  }
+
+  /*-------------------------- HCLK Configuration --------------------------*/
+  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
+ 8039a10:	687b      	ldr	r3, [r7, #4]
+ 8039a12:	681b      	ldr	r3, [r3, #0]
+ 8039a14:	f003 0302 	and.w	r3, r3, #2
+ 8039a18:	2b00      	cmp	r3, #0
+ 8039a1a:	d010      	beq.n	8039a3e <HAL_RCC_ClockConfig+0x12a>
+  {
+#if defined (RCC_D1CFGR_HPRE)
+    if ((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_HPRE))
+ 8039a1c:	687b      	ldr	r3, [r7, #4]
+ 8039a1e:	68da      	ldr	r2, [r3, #12]
+ 8039a20:	4b4d      	ldr	r3, [pc, #308]	@ (8039b58 <HAL_RCC_ClockConfig+0x244>)
+ 8039a22:	699b      	ldr	r3, [r3, #24]
+ 8039a24:	f003 030f 	and.w	r3, r3, #15
+ 8039a28:	429a      	cmp	r2, r3
+ 8039a2a:	d908      	bls.n	8039a3e <HAL_RCC_ClockConfig+0x12a>
+    {
+      /* Set the new HCLK clock divider */
+      assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
+      MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
+ 8039a2c:	4b4a      	ldr	r3, [pc, #296]	@ (8039b58 <HAL_RCC_ClockConfig+0x244>)
+ 8039a2e:	699b      	ldr	r3, [r3, #24]
+ 8039a30:	f023 020f 	bic.w	r2, r3, #15
+ 8039a34:	687b      	ldr	r3, [r7, #4]
+ 8039a36:	68db      	ldr	r3, [r3, #12]
+ 8039a38:	4947      	ldr	r1, [pc, #284]	@ (8039b58 <HAL_RCC_ClockConfig+0x244>)
+ 8039a3a:	4313      	orrs	r3, r2
+ 8039a3c:	618b      	str	r3, [r1, #24]
+    }
+#endif
+  }
+
+  /*------------------------- SYSCLK Configuration -------------------------*/
+  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
+ 8039a3e:	687b      	ldr	r3, [r7, #4]
+ 8039a40:	681b      	ldr	r3, [r3, #0]
+ 8039a42:	f003 0301 	and.w	r3, r3, #1
+ 8039a46:	2b00      	cmp	r3, #0
+ 8039a48:	d055      	beq.n	8039af6 <HAL_RCC_ClockConfig+0x1e2>
+  {
+    assert_param(IS_RCC_SYSCLK(RCC_ClkInitStruct->SYSCLKDivider));
+    assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
+#if defined(RCC_D1CFGR_D1CPRE)
+    MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, RCC_ClkInitStruct->SYSCLKDivider);
+ 8039a4a:	4b43      	ldr	r3, [pc, #268]	@ (8039b58 <HAL_RCC_ClockConfig+0x244>)
+ 8039a4c:	699b      	ldr	r3, [r3, #24]
+ 8039a4e:	f423 6270 	bic.w	r2, r3, #3840	@ 0xf00
+ 8039a52:	687b      	ldr	r3, [r7, #4]
+ 8039a54:	689b      	ldr	r3, [r3, #8]
+ 8039a56:	4940      	ldr	r1, [pc, #256]	@ (8039b58 <HAL_RCC_ClockConfig+0x244>)
+ 8039a58:	4313      	orrs	r3, r2
+ 8039a5a:	618b      	str	r3, [r1, #24]
+#else
+    MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE, RCC_ClkInitStruct->SYSCLKDivider);
+#endif
+    /* HSE is selected as System Clock Source */
+    if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+ 8039a5c:	687b      	ldr	r3, [r7, #4]
+ 8039a5e:	685b      	ldr	r3, [r3, #4]
+ 8039a60:	2b02      	cmp	r3, #2
+ 8039a62:	d107      	bne.n	8039a74 <HAL_RCC_ClockConfig+0x160>
+    {
+      /* Check the HSE ready flag */
+      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
+ 8039a64:	4b3c      	ldr	r3, [pc, #240]	@ (8039b58 <HAL_RCC_ClockConfig+0x244>)
+ 8039a66:	681b      	ldr	r3, [r3, #0]
+ 8039a68:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
+ 8039a6c:	2b00      	cmp	r3, #0
+ 8039a6e:	d121      	bne.n	8039ab4 <HAL_RCC_ClockConfig+0x1a0>
+      {
+        return HAL_ERROR;
+ 8039a70:	2301      	movs	r3, #1
+ 8039a72:	e0f6      	b.n	8039c62 <HAL_RCC_ClockConfig+0x34e>
+      }
+    }
+    /* PLL is selected as System Clock Source */
+    else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+ 8039a74:	687b      	ldr	r3, [r7, #4]
+ 8039a76:	685b      	ldr	r3, [r3, #4]
+ 8039a78:	2b03      	cmp	r3, #3
+ 8039a7a:	d107      	bne.n	8039a8c <HAL_RCC_ClockConfig+0x178>
+    {
+      /* Check the PLL ready flag */
+      if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
+ 8039a7c:	4b36      	ldr	r3, [pc, #216]	@ (8039b58 <HAL_RCC_ClockConfig+0x244>)
+ 8039a7e:	681b      	ldr	r3, [r3, #0]
+ 8039a80:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
+ 8039a84:	2b00      	cmp	r3, #0
+ 8039a86:	d115      	bne.n	8039ab4 <HAL_RCC_ClockConfig+0x1a0>
+      {
+        return HAL_ERROR;
+ 8039a88:	2301      	movs	r3, #1
+ 8039a8a:	e0ea      	b.n	8039c62 <HAL_RCC_ClockConfig+0x34e>
+      }
+    }
+    /* CSI is selected as System Clock Source */
+    else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_CSI)
+ 8039a8c:	687b      	ldr	r3, [r7, #4]
+ 8039a8e:	685b      	ldr	r3, [r3, #4]
+ 8039a90:	2b01      	cmp	r3, #1
+ 8039a92:	d107      	bne.n	8039aa4 <HAL_RCC_ClockConfig+0x190>
+    {
+      /* Check the PLL ready flag */
+      if (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U)
+ 8039a94:	4b30      	ldr	r3, [pc, #192]	@ (8039b58 <HAL_RCC_ClockConfig+0x244>)
+ 8039a96:	681b      	ldr	r3, [r3, #0]
+ 8039a98:	f403 7380 	and.w	r3, r3, #256	@ 0x100
+ 8039a9c:	2b00      	cmp	r3, #0
+ 8039a9e:	d109      	bne.n	8039ab4 <HAL_RCC_ClockConfig+0x1a0>
+      {
+        return HAL_ERROR;
+ 8039aa0:	2301      	movs	r3, #1
+ 8039aa2:	e0de      	b.n	8039c62 <HAL_RCC_ClockConfig+0x34e>
+    }
+    /* HSI is selected as System Clock Source */
+    else
+    {
+      /* Check the HSI ready flag */
+      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
+ 8039aa4:	4b2c      	ldr	r3, [pc, #176]	@ (8039b58 <HAL_RCC_ClockConfig+0x244>)
+ 8039aa6:	681b      	ldr	r3, [r3, #0]
+ 8039aa8:	f003 0304 	and.w	r3, r3, #4
+ 8039aac:	2b00      	cmp	r3, #0
+ 8039aae:	d101      	bne.n	8039ab4 <HAL_RCC_ClockConfig+0x1a0>
+      {
+        return HAL_ERROR;
+ 8039ab0:	2301      	movs	r3, #1
+ 8039ab2:	e0d6      	b.n	8039c62 <HAL_RCC_ClockConfig+0x34e>
+      }
+    }
+    MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
+ 8039ab4:	4b28      	ldr	r3, [pc, #160]	@ (8039b58 <HAL_RCC_ClockConfig+0x244>)
+ 8039ab6:	691b      	ldr	r3, [r3, #16]
+ 8039ab8:	f023 0207 	bic.w	r2, r3, #7
+ 8039abc:	687b      	ldr	r3, [r7, #4]
+ 8039abe:	685b      	ldr	r3, [r3, #4]
+ 8039ac0:	4925      	ldr	r1, [pc, #148]	@ (8039b58 <HAL_RCC_ClockConfig+0x244>)
+ 8039ac2:	4313      	orrs	r3, r2
+ 8039ac4:	610b      	str	r3, [r1, #16]
+
+    /* Get Start Tick*/
+    tickstart = HAL_GetTick();
+ 8039ac6:	f7f7 ff33 	bl	8031930 <HAL_GetTick>
+ 8039aca:	6178      	str	r0, [r7, #20]
+
+    while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
+ 8039acc:	e00a      	b.n	8039ae4 <HAL_RCC_ClockConfig+0x1d0>
+    {
+      if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+ 8039ace:	f7f7 ff2f 	bl	8031930 <HAL_GetTick>
+ 8039ad2:	4602      	mov	r2, r0
+ 8039ad4:	697b      	ldr	r3, [r7, #20]
+ 8039ad6:	1ad3      	subs	r3, r2, r3
+ 8039ad8:	f241 3288 	movw	r2, #5000	@ 0x1388
+ 8039adc:	4293      	cmp	r3, r2
+ 8039ade:	d901      	bls.n	8039ae4 <HAL_RCC_ClockConfig+0x1d0>
+      {
+        return HAL_TIMEOUT;
+ 8039ae0:	2303      	movs	r3, #3
+ 8039ae2:	e0be      	b.n	8039c62 <HAL_RCC_ClockConfig+0x34e>
+    while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
+ 8039ae4:	4b1c      	ldr	r3, [pc, #112]	@ (8039b58 <HAL_RCC_ClockConfig+0x244>)
+ 8039ae6:	691b      	ldr	r3, [r3, #16]
+ 8039ae8:	f003 0238 	and.w	r2, r3, #56	@ 0x38
+ 8039aec:	687b      	ldr	r3, [r7, #4]
+ 8039aee:	685b      	ldr	r3, [r3, #4]
+ 8039af0:	00db      	lsls	r3, r3, #3
+ 8039af2:	429a      	cmp	r2, r3
+ 8039af4:	d1eb      	bne.n	8039ace <HAL_RCC_ClockConfig+0x1ba>
+
+  }
+
+  /* Decreasing the BUS frequency divider */
+  /*-------------------------- HCLK Configuration --------------------------*/
+  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
+ 8039af6:	687b      	ldr	r3, [r7, #4]
+ 8039af8:	681b      	ldr	r3, [r3, #0]
+ 8039afa:	f003 0302 	and.w	r3, r3, #2
+ 8039afe:	2b00      	cmp	r3, #0
+ 8039b00:	d010      	beq.n	8039b24 <HAL_RCC_ClockConfig+0x210>
+  {
+#if defined(RCC_D1CFGR_HPRE)
+    if ((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_HPRE))
+ 8039b02:	687b      	ldr	r3, [r7, #4]
+ 8039b04:	68da      	ldr	r2, [r3, #12]
+ 8039b06:	4b14      	ldr	r3, [pc, #80]	@ (8039b58 <HAL_RCC_ClockConfig+0x244>)
+ 8039b08:	699b      	ldr	r3, [r3, #24]
+ 8039b0a:	f003 030f 	and.w	r3, r3, #15
+ 8039b0e:	429a      	cmp	r2, r3
+ 8039b10:	d208      	bcs.n	8039b24 <HAL_RCC_ClockConfig+0x210>
+    {
+      /* Set the new HCLK clock divider */
+      assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
+      MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
+ 8039b12:	4b11      	ldr	r3, [pc, #68]	@ (8039b58 <HAL_RCC_ClockConfig+0x244>)
+ 8039b14:	699b      	ldr	r3, [r3, #24]
+ 8039b16:	f023 020f 	bic.w	r2, r3, #15
+ 8039b1a:	687b      	ldr	r3, [r7, #4]
+ 8039b1c:	68db      	ldr	r3, [r3, #12]
+ 8039b1e:	490e      	ldr	r1, [pc, #56]	@ (8039b58 <HAL_RCC_ClockConfig+0x244>)
+ 8039b20:	4313      	orrs	r3, r2
+ 8039b22:	618b      	str	r3, [r1, #24]
+    }
+#endif
+  }
+
+  /* Decreasing the number of wait states because of lower CPU frequency */
+  if (FLatency < __HAL_FLASH_GET_LATENCY())
+ 8039b24:	4b0b      	ldr	r3, [pc, #44]	@ (8039b54 <HAL_RCC_ClockConfig+0x240>)
+ 8039b26:	681b      	ldr	r3, [r3, #0]
+ 8039b28:	f003 030f 	and.w	r3, r3, #15
+ 8039b2c:	683a      	ldr	r2, [r7, #0]
+ 8039b2e:	429a      	cmp	r2, r3
+ 8039b30:	d214      	bcs.n	8039b5c <HAL_RCC_ClockConfig+0x248>
+  {
+    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+    __HAL_FLASH_SET_LATENCY(FLatency);
+ 8039b32:	4b08      	ldr	r3, [pc, #32]	@ (8039b54 <HAL_RCC_ClockConfig+0x240>)
+ 8039b34:	681b      	ldr	r3, [r3, #0]
+ 8039b36:	f023 020f 	bic.w	r2, r3, #15
+ 8039b3a:	4906      	ldr	r1, [pc, #24]	@ (8039b54 <HAL_RCC_ClockConfig+0x240>)
+ 8039b3c:	683b      	ldr	r3, [r7, #0]
+ 8039b3e:	4313      	orrs	r3, r2
+ 8039b40:	600b      	str	r3, [r1, #0]
+
+    /* Check that the new number of wait states is taken into account to access the Flash
+    memory by reading the FLASH_ACR register */
+    if (__HAL_FLASH_GET_LATENCY() != FLatency)
+ 8039b42:	4b04      	ldr	r3, [pc, #16]	@ (8039b54 <HAL_RCC_ClockConfig+0x240>)
+ 8039b44:	681b      	ldr	r3, [r3, #0]
+ 8039b46:	f003 030f 	and.w	r3, r3, #15
+ 8039b4a:	683a      	ldr	r2, [r7, #0]
+ 8039b4c:	429a      	cmp	r2, r3
+ 8039b4e:	d005      	beq.n	8039b5c <HAL_RCC_ClockConfig+0x248>
+    {
+      return HAL_ERROR;
+ 8039b50:	2301      	movs	r3, #1
+ 8039b52:	e086      	b.n	8039c62 <HAL_RCC_ClockConfig+0x34e>
+ 8039b54:	52002000 	.word	0x52002000
+ 8039b58:	58024400 	.word	0x58024400
+    }
+  }
+
+  /*-------------------------- D1PCLK1/CDPCLK Configuration ---------------------------*/
+  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1)
+ 8039b5c:	687b      	ldr	r3, [r7, #4]
+ 8039b5e:	681b      	ldr	r3, [r3, #0]
+ 8039b60:	f003 0304 	and.w	r3, r3, #4
+ 8039b64:	2b00      	cmp	r3, #0
+ 8039b66:	d010      	beq.n	8039b8a <HAL_RCC_ClockConfig+0x276>
+  {
+#if defined(RCC_D1CFGR_D1PPRE)
+    if ((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_D1PPRE))
+ 8039b68:	687b      	ldr	r3, [r7, #4]
+ 8039b6a:	691a      	ldr	r2, [r3, #16]
+ 8039b6c:	4b3f      	ldr	r3, [pc, #252]	@ (8039c6c <HAL_RCC_ClockConfig+0x358>)
+ 8039b6e:	699b      	ldr	r3, [r3, #24]
+ 8039b70:	f003 0370 	and.w	r3, r3, #112	@ 0x70
+ 8039b74:	429a      	cmp	r2, r3
+ 8039b76:	d208      	bcs.n	8039b8a <HAL_RCC_ClockConfig+0x276>
+    {
+      assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider));
+      MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider);
+ 8039b78:	4b3c      	ldr	r3, [pc, #240]	@ (8039c6c <HAL_RCC_ClockConfig+0x358>)
+ 8039b7a:	699b      	ldr	r3, [r3, #24]
+ 8039b7c:	f023 0270 	bic.w	r2, r3, #112	@ 0x70
+ 8039b80:	687b      	ldr	r3, [r7, #4]
+ 8039b82:	691b      	ldr	r3, [r3, #16]
+ 8039b84:	4939      	ldr	r1, [pc, #228]	@ (8039c6c <HAL_RCC_ClockConfig+0x358>)
+ 8039b86:	4313      	orrs	r3, r2
+ 8039b88:	618b      	str	r3, [r1, #24]
+    }
+#endif
+  }
+
+  /*-------------------------- PCLK1 Configuration ---------------------------*/
+  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+ 8039b8a:	687b      	ldr	r3, [r7, #4]
+ 8039b8c:	681b      	ldr	r3, [r3, #0]
+ 8039b8e:	f003 0308 	and.w	r3, r3, #8
+ 8039b92:	2b00      	cmp	r3, #0
+ 8039b94:	d010      	beq.n	8039bb8 <HAL_RCC_ClockConfig+0x2a4>
+  {
+#if defined(RCC_D2CFGR_D2PPRE1)
+    if ((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1))
+ 8039b96:	687b      	ldr	r3, [r7, #4]
+ 8039b98:	695a      	ldr	r2, [r3, #20]
+ 8039b9a:	4b34      	ldr	r3, [pc, #208]	@ (8039c6c <HAL_RCC_ClockConfig+0x358>)
+ 8039b9c:	69db      	ldr	r3, [r3, #28]
+ 8039b9e:	f003 0370 	and.w	r3, r3, #112	@ 0x70
+ 8039ba2:	429a      	cmp	r2, r3
+ 8039ba4:	d208      	bcs.n	8039bb8 <HAL_RCC_ClockConfig+0x2a4>
+    {
+      assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider));
+      MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
+ 8039ba6:	4b31      	ldr	r3, [pc, #196]	@ (8039c6c <HAL_RCC_ClockConfig+0x358>)
+ 8039ba8:	69db      	ldr	r3, [r3, #28]
+ 8039baa:	f023 0270 	bic.w	r2, r3, #112	@ 0x70
+ 8039bae:	687b      	ldr	r3, [r7, #4]
+ 8039bb0:	695b      	ldr	r3, [r3, #20]
+ 8039bb2:	492e      	ldr	r1, [pc, #184]	@ (8039c6c <HAL_RCC_ClockConfig+0x358>)
+ 8039bb4:	4313      	orrs	r3, r2
+ 8039bb6:	61cb      	str	r3, [r1, #28]
+    }
+#endif
+  }
+
+  /*-------------------------- PCLK2 Configuration ---------------------------*/
+  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
+ 8039bb8:	687b      	ldr	r3, [r7, #4]
+ 8039bba:	681b      	ldr	r3, [r3, #0]
+ 8039bbc:	f003 0310 	and.w	r3, r3, #16
+ 8039bc0:	2b00      	cmp	r3, #0
+ 8039bc2:	d010      	beq.n	8039be6 <HAL_RCC_ClockConfig+0x2d2>
+  {
+#if defined (RCC_D2CFGR_D2PPRE2)
+    if ((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2))
+ 8039bc4:	687b      	ldr	r3, [r7, #4]
+ 8039bc6:	699a      	ldr	r2, [r3, #24]
+ 8039bc8:	4b28      	ldr	r3, [pc, #160]	@ (8039c6c <HAL_RCC_ClockConfig+0x358>)
+ 8039bca:	69db      	ldr	r3, [r3, #28]
+ 8039bcc:	f403 63e0 	and.w	r3, r3, #1792	@ 0x700
+ 8039bd0:	429a      	cmp	r2, r3
+ 8039bd2:	d208      	bcs.n	8039be6 <HAL_RCC_ClockConfig+0x2d2>
+    {
+      assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider));
+      MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider));
+ 8039bd4:	4b25      	ldr	r3, [pc, #148]	@ (8039c6c <HAL_RCC_ClockConfig+0x358>)
+ 8039bd6:	69db      	ldr	r3, [r3, #28]
+ 8039bd8:	f423 62e0 	bic.w	r2, r3, #1792	@ 0x700
+ 8039bdc:	687b      	ldr	r3, [r7, #4]
+ 8039bde:	699b      	ldr	r3, [r3, #24]
+ 8039be0:	4922      	ldr	r1, [pc, #136]	@ (8039c6c <HAL_RCC_ClockConfig+0x358>)
+ 8039be2:	4313      	orrs	r3, r2
+ 8039be4:	61cb      	str	r3, [r1, #28]
+    }
+#endif
+  }
+
+  /*-------------------------- D3PCLK1/SRDPCLK1 Configuration ---------------------------*/
+  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1)
+ 8039be6:	687b      	ldr	r3, [r7, #4]
+ 8039be8:	681b      	ldr	r3, [r3, #0]
+ 8039bea:	f003 0320 	and.w	r3, r3, #32
+ 8039bee:	2b00      	cmp	r3, #0
+ 8039bf0:	d010      	beq.n	8039c14 <HAL_RCC_ClockConfig+0x300>
+  {
+#if defined(RCC_D3CFGR_D3PPRE)
+    if ((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->D3CFGR & RCC_D3CFGR_D3PPRE))
+ 8039bf2:	687b      	ldr	r3, [r7, #4]
+ 8039bf4:	69da      	ldr	r2, [r3, #28]
+ 8039bf6:	4b1d      	ldr	r3, [pc, #116]	@ (8039c6c <HAL_RCC_ClockConfig+0x358>)
+ 8039bf8:	6a1b      	ldr	r3, [r3, #32]
+ 8039bfa:	f003 0370 	and.w	r3, r3, #112	@ 0x70
+ 8039bfe:	429a      	cmp	r2, r3
+ 8039c00:	d208      	bcs.n	8039c14 <HAL_RCC_ClockConfig+0x300>
+    {
+      assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider));
+      MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider));
+ 8039c02:	4b1a      	ldr	r3, [pc, #104]	@ (8039c6c <HAL_RCC_ClockConfig+0x358>)
+ 8039c04:	6a1b      	ldr	r3, [r3, #32]
+ 8039c06:	f023 0270 	bic.w	r2, r3, #112	@ 0x70
+ 8039c0a:	687b      	ldr	r3, [r7, #4]
+ 8039c0c:	69db      	ldr	r3, [r3, #28]
+ 8039c0e:	4917      	ldr	r1, [pc, #92]	@ (8039c6c <HAL_RCC_ClockConfig+0x358>)
+ 8039c10:	4313      	orrs	r3, r2
+ 8039c12:	620b      	str	r3, [r1, #32]
+#endif
+  }
+
+  /* Update the SystemCoreClock global variable */
+#if defined(RCC_D1CFGR_D1CPRE)
+  common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
+ 8039c14:	f000 f844 	bl	8039ca0 <HAL_RCC_GetSysClockFreq>
+ 8039c18:	4602      	mov	r2, r0
+ 8039c1a:	4b14      	ldr	r3, [pc, #80]	@ (8039c6c <HAL_RCC_ClockConfig+0x358>)
+ 8039c1c:	699b      	ldr	r3, [r3, #24]
+ 8039c1e:	0a1b      	lsrs	r3, r3, #8
+ 8039c20:	f003 030f 	and.w	r3, r3, #15
+ 8039c24:	4912      	ldr	r1, [pc, #72]	@ (8039c70 <HAL_RCC_ClockConfig+0x35c>)
+ 8039c26:	5ccb      	ldrb	r3, [r1, r3]
+ 8039c28:	f003 031f 	and.w	r3, r3, #31
+ 8039c2c:	fa22 f303 	lsr.w	r3, r2, r3
+ 8039c30:	613b      	str	r3, [r7, #16]
+#else
+  common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU);
+#endif
+
+#if defined(RCC_D1CFGR_HPRE)
+  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
+ 8039c32:	4b0e      	ldr	r3, [pc, #56]	@ (8039c6c <HAL_RCC_ClockConfig+0x358>)
+ 8039c34:	699b      	ldr	r3, [r3, #24]
+ 8039c36:	f003 030f 	and.w	r3, r3, #15
+ 8039c3a:	4a0d      	ldr	r2, [pc, #52]	@ (8039c70 <HAL_RCC_ClockConfig+0x35c>)
+ 8039c3c:	5cd3      	ldrb	r3, [r2, r3]
+ 8039c3e:	f003 031f 	and.w	r3, r3, #31
+ 8039c42:	693a      	ldr	r2, [r7, #16]
+ 8039c44:	fa22 f303 	lsr.w	r3, r2, r3
+ 8039c48:	4a0a      	ldr	r2, [pc, #40]	@ (8039c74 <HAL_RCC_ClockConfig+0x360>)
+ 8039c4a:	6013      	str	r3, [r2, #0]
+#endif
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+  SystemCoreClock = SystemD2Clock;
+#else
+  SystemCoreClock = common_system_clock;
+ 8039c4c:	4a0a      	ldr	r2, [pc, #40]	@ (8039c78 <HAL_RCC_ClockConfig+0x364>)
+ 8039c4e:	693b      	ldr	r3, [r7, #16]
+ 8039c50:	6013      	str	r3, [r2, #0]
+#endif /* DUAL_CORE && CORE_CM4 */
+
+  /* Configure the source of time base considering new system clocks settings*/
+  halstatus = HAL_InitTick(uwTickPrio);
+ 8039c52:	4b0a      	ldr	r3, [pc, #40]	@ (8039c7c <HAL_RCC_ClockConfig+0x368>)
+ 8039c54:	681b      	ldr	r3, [r3, #0]
+ 8039c56:	4618      	mov	r0, r3
+ 8039c58:	f7f7 fe20 	bl	803189c <HAL_InitTick>
+ 8039c5c:	4603      	mov	r3, r0
+ 8039c5e:	73fb      	strb	r3, [r7, #15]
+
+  return halstatus;
+ 8039c60:	7bfb      	ldrb	r3, [r7, #15]
+}
+ 8039c62:	4618      	mov	r0, r3
+ 8039c64:	3718      	adds	r7, #24
+ 8039c66:	46bd      	mov	sp, r7
+ 8039c68:	bd80      	pop	{r7, pc}
+ 8039c6a:	bf00      	nop
+ 8039c6c:	58024400 	.word	0x58024400
+ 8039c70:	08041c58 	.word	0x08041c58
+ 8039c74:	24000130 	.word	0x24000130
+ 8039c78:	2400012c 	.word	0x2400012c
+ 8039c7c:	24000134 	.word	0x24000134
+
+08039c80 <HAL_RCC_EnableCSS>:
+  *         allowing the MCU to perform rescue operations. The CSSI is linked to
+  *         the Cortex-M NMI (Non-Mask-able Interrupt) exception vector.
+  * @retval None
+  */
+void HAL_RCC_EnableCSS(void)
+{
+ 8039c80:	b480      	push	{r7}
+ 8039c82:	af00      	add	r7, sp, #0
+  SET_BIT(RCC->CR, RCC_CR_CSSHSEON) ;
+ 8039c84:	4b05      	ldr	r3, [pc, #20]	@ (8039c9c <HAL_RCC_EnableCSS+0x1c>)
+ 8039c86:	681b      	ldr	r3, [r3, #0]
+ 8039c88:	4a04      	ldr	r2, [pc, #16]	@ (8039c9c <HAL_RCC_EnableCSS+0x1c>)
+ 8039c8a:	f443 2300 	orr.w	r3, r3, #524288	@ 0x80000
+ 8039c8e:	6013      	str	r3, [r2, #0]
+}
+ 8039c90:	bf00      	nop
+ 8039c92:	46bd      	mov	sp, r7
+ 8039c94:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8039c98:	4770      	bx	lr
+ 8039c9a:	bf00      	nop
+ 8039c9c:	58024400 	.word	0x58024400
+
+08039ca0 <HAL_RCC_GetSysClockFreq>:
+  *
+  *
+  * @retval SYSCLK frequency
+  */
+uint32_t HAL_RCC_GetSysClockFreq(void)
+{
+ 8039ca0:	b480      	push	{r7}
+ 8039ca2:	b089      	sub	sp, #36	@ 0x24
+ 8039ca4:	af00      	add	r7, sp, #0
+  float_t fracn1, pllvco;
+  uint32_t sysclockfreq;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+ 8039ca6:	4bb3      	ldr	r3, [pc, #716]	@ (8039f74 <HAL_RCC_GetSysClockFreq+0x2d4>)
+ 8039ca8:	691b      	ldr	r3, [r3, #16]
+ 8039caa:	f003 0338 	and.w	r3, r3, #56	@ 0x38
+ 8039cae:	2b18      	cmp	r3, #24
+ 8039cb0:	f200 8155 	bhi.w	8039f5e <HAL_RCC_GetSysClockFreq+0x2be>
+ 8039cb4:	a201      	add	r2, pc, #4	@ (adr r2, 8039cbc <HAL_RCC_GetSysClockFreq+0x1c>)
+ 8039cb6:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 8039cba:	bf00      	nop
+ 8039cbc:	08039d21 	.word	0x08039d21
+ 8039cc0:	08039f5f 	.word	0x08039f5f
+ 8039cc4:	08039f5f 	.word	0x08039f5f
+ 8039cc8:	08039f5f 	.word	0x08039f5f
+ 8039ccc:	08039f5f 	.word	0x08039f5f
+ 8039cd0:	08039f5f 	.word	0x08039f5f
+ 8039cd4:	08039f5f 	.word	0x08039f5f
+ 8039cd8:	08039f5f 	.word	0x08039f5f
+ 8039cdc:	08039d47 	.word	0x08039d47
+ 8039ce0:	08039f5f 	.word	0x08039f5f
+ 8039ce4:	08039f5f 	.word	0x08039f5f
+ 8039ce8:	08039f5f 	.word	0x08039f5f
+ 8039cec:	08039f5f 	.word	0x08039f5f
+ 8039cf0:	08039f5f 	.word	0x08039f5f
+ 8039cf4:	08039f5f 	.word	0x08039f5f
+ 8039cf8:	08039f5f 	.word	0x08039f5f
+ 8039cfc:	08039d4d 	.word	0x08039d4d
+ 8039d00:	08039f5f 	.word	0x08039f5f
+ 8039d04:	08039f5f 	.word	0x08039f5f
+ 8039d08:	08039f5f 	.word	0x08039f5f
+ 8039d0c:	08039f5f 	.word	0x08039f5f
+ 8039d10:	08039f5f 	.word	0x08039f5f
+ 8039d14:	08039f5f 	.word	0x08039f5f
+ 8039d18:	08039f5f 	.word	0x08039f5f
+ 8039d1c:	08039d53 	.word	0x08039d53
+  {
+    case RCC_CFGR_SWS_HSI:  /* HSI used as system clock source */
+
+      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
+ 8039d20:	4b94      	ldr	r3, [pc, #592]	@ (8039f74 <HAL_RCC_GetSysClockFreq+0x2d4>)
+ 8039d22:	681b      	ldr	r3, [r3, #0]
+ 8039d24:	f003 0320 	and.w	r3, r3, #32
+ 8039d28:	2b00      	cmp	r3, #0
+ 8039d2a:	d009      	beq.n	8039d40 <HAL_RCC_GetSysClockFreq+0xa0>
+      {
+        sysclockfreq = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
+ 8039d2c:	4b91      	ldr	r3, [pc, #580]	@ (8039f74 <HAL_RCC_GetSysClockFreq+0x2d4>)
+ 8039d2e:	681b      	ldr	r3, [r3, #0]
+ 8039d30:	08db      	lsrs	r3, r3, #3
+ 8039d32:	f003 0303 	and.w	r3, r3, #3
+ 8039d36:	4a90      	ldr	r2, [pc, #576]	@ (8039f78 <HAL_RCC_GetSysClockFreq+0x2d8>)
+ 8039d38:	fa22 f303 	lsr.w	r3, r2, r3
+ 8039d3c:	61bb      	str	r3, [r7, #24]
+      else
+      {
+        sysclockfreq = (uint32_t) HSI_VALUE;
+      }
+
+      break;
+ 8039d3e:	e111      	b.n	8039f64 <HAL_RCC_GetSysClockFreq+0x2c4>
+        sysclockfreq = (uint32_t) HSI_VALUE;
+ 8039d40:	4b8d      	ldr	r3, [pc, #564]	@ (8039f78 <HAL_RCC_GetSysClockFreq+0x2d8>)
+ 8039d42:	61bb      	str	r3, [r7, #24]
+      break;
+ 8039d44:	e10e      	b.n	8039f64 <HAL_RCC_GetSysClockFreq+0x2c4>
+
+    case RCC_CFGR_SWS_CSI:  /* CSI used as system clock  source */
+      sysclockfreq = CSI_VALUE;
+ 8039d46:	4b8d      	ldr	r3, [pc, #564]	@ (8039f7c <HAL_RCC_GetSysClockFreq+0x2dc>)
+ 8039d48:	61bb      	str	r3, [r7, #24]
+      break;
+ 8039d4a:	e10b      	b.n	8039f64 <HAL_RCC_GetSysClockFreq+0x2c4>
+
+    case RCC_CFGR_SWS_HSE:  /* HSE used as system clock  source */
+      sysclockfreq = HSE_VALUE;
+ 8039d4c:	4b8c      	ldr	r3, [pc, #560]	@ (8039f80 <HAL_RCC_GetSysClockFreq+0x2e0>)
+ 8039d4e:	61bb      	str	r3, [r7, #24]
+      break;
+ 8039d50:	e108      	b.n	8039f64 <HAL_RCC_GetSysClockFreq+0x2c4>
+    case RCC_CFGR_SWS_PLL1:  /* PLL1 used as system clock  source */
+
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
+      SYSCLK = PLL_VCO / PLLR
+      */
+      pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
+ 8039d52:	4b88      	ldr	r3, [pc, #544]	@ (8039f74 <HAL_RCC_GetSysClockFreq+0x2d4>)
+ 8039d54:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 8039d56:	f003 0303 	and.w	r3, r3, #3
+ 8039d5a:	617b      	str	r3, [r7, #20]
+      pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4)  ;
+ 8039d5c:	4b85      	ldr	r3, [pc, #532]	@ (8039f74 <HAL_RCC_GetSysClockFreq+0x2d4>)
+ 8039d5e:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 8039d60:	091b      	lsrs	r3, r3, #4
+ 8039d62:	f003 033f 	and.w	r3, r3, #63	@ 0x3f
+ 8039d66:	613b      	str	r3, [r7, #16]
+      pllfracen = ((RCC-> PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) >> RCC_PLLCFGR_PLL1FRACEN_Pos);
+ 8039d68:	4b82      	ldr	r3, [pc, #520]	@ (8039f74 <HAL_RCC_GetSysClockFreq+0x2d4>)
+ 8039d6a:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 8039d6c:	f003 0301 	and.w	r3, r3, #1
+ 8039d70:	60fb      	str	r3, [r7, #12]
+      fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3));
+ 8039d72:	4b80      	ldr	r3, [pc, #512]	@ (8039f74 <HAL_RCC_GetSysClockFreq+0x2d4>)
+ 8039d74:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
+ 8039d76:	08db      	lsrs	r3, r3, #3
+ 8039d78:	f3c3 030c 	ubfx	r3, r3, #0, #13
+ 8039d7c:	68fa      	ldr	r2, [r7, #12]
+ 8039d7e:	fb02 f303 	mul.w	r3, r2, r3
+ 8039d82:	ee07 3a90 	vmov	s15, r3
+ 8039d86:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 8039d8a:	edc7 7a02 	vstr	s15, [r7, #8]
+
+      if (pllm != 0U)
+ 8039d8e:	693b      	ldr	r3, [r7, #16]
+ 8039d90:	2b00      	cmp	r3, #0
+ 8039d92:	f000 80e1 	beq.w	8039f58 <HAL_RCC_GetSysClockFreq+0x2b8>
+ 8039d96:	697b      	ldr	r3, [r7, #20]
+ 8039d98:	2b02      	cmp	r3, #2
+ 8039d9a:	f000 8083 	beq.w	8039ea4 <HAL_RCC_GetSysClockFreq+0x204>
+ 8039d9e:	697b      	ldr	r3, [r7, #20]
+ 8039da0:	2b02      	cmp	r3, #2
+ 8039da2:	f200 80a1 	bhi.w	8039ee8 <HAL_RCC_GetSysClockFreq+0x248>
+ 8039da6:	697b      	ldr	r3, [r7, #20]
+ 8039da8:	2b00      	cmp	r3, #0
+ 8039daa:	d003      	beq.n	8039db4 <HAL_RCC_GetSysClockFreq+0x114>
+ 8039dac:	697b      	ldr	r3, [r7, #20]
+ 8039dae:	2b01      	cmp	r3, #1
+ 8039db0:	d056      	beq.n	8039e60 <HAL_RCC_GetSysClockFreq+0x1c0>
+ 8039db2:	e099      	b.n	8039ee8 <HAL_RCC_GetSysClockFreq+0x248>
+      {
+        switch (pllsource)
+        {
+          case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
+
+            if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
+ 8039db4:	4b6f      	ldr	r3, [pc, #444]	@ (8039f74 <HAL_RCC_GetSysClockFreq+0x2d4>)
+ 8039db6:	681b      	ldr	r3, [r3, #0]
+ 8039db8:	f003 0320 	and.w	r3, r3, #32
+ 8039dbc:	2b00      	cmp	r3, #0
+ 8039dbe:	d02d      	beq.n	8039e1c <HAL_RCC_GetSysClockFreq+0x17c>
+            {
+              hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
+ 8039dc0:	4b6c      	ldr	r3, [pc, #432]	@ (8039f74 <HAL_RCC_GetSysClockFreq+0x2d4>)
+ 8039dc2:	681b      	ldr	r3, [r3, #0]
+ 8039dc4:	08db      	lsrs	r3, r3, #3
+ 8039dc6:	f003 0303 	and.w	r3, r3, #3
+ 8039dca:	4a6b      	ldr	r2, [pc, #428]	@ (8039f78 <HAL_RCC_GetSysClockFreq+0x2d8>)
+ 8039dcc:	fa22 f303 	lsr.w	r3, r2, r3
+ 8039dd0:	607b      	str	r3, [r7, #4]
+              pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
+ 8039dd2:	687b      	ldr	r3, [r7, #4]
+ 8039dd4:	ee07 3a90 	vmov	s15, r3
+ 8039dd8:	eef8 6a67 	vcvt.f32.u32	s13, s15
+ 8039ddc:	693b      	ldr	r3, [r7, #16]
+ 8039dde:	ee07 3a90 	vmov	s15, r3
+ 8039de2:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 8039de6:	ee86 7aa7 	vdiv.f32	s14, s13, s15
+ 8039dea:	4b62      	ldr	r3, [pc, #392]	@ (8039f74 <HAL_RCC_GetSysClockFreq+0x2d4>)
+ 8039dec:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
+ 8039dee:	f3c3 0308 	ubfx	r3, r3, #0, #9
+ 8039df2:	ee07 3a90 	vmov	s15, r3
+ 8039df6:	eef8 6a67 	vcvt.f32.u32	s13, s15
+ 8039dfa:	ed97 6a02 	vldr	s12, [r7, #8]
+ 8039dfe:	eddf 5a61 	vldr	s11, [pc, #388]	@ 8039f84 <HAL_RCC_GetSysClockFreq+0x2e4>
+ 8039e02:	eec6 7a25 	vdiv.f32	s15, s12, s11
+ 8039e06:	ee76 7aa7 	vadd.f32	s15, s13, s15
+ 8039e0a:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
+ 8039e0e:	ee77 7aa6 	vadd.f32	s15, s15, s13
+ 8039e12:	ee67 7a27 	vmul.f32	s15, s14, s15
+ 8039e16:	edc7 7a07 	vstr	s15, [r7, #28]
+            }
+            else
+            {
+              pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
+            }
+            break;
+ 8039e1a:	e087      	b.n	8039f2c <HAL_RCC_GetSysClockFreq+0x28c>
+              pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
+ 8039e1c:	693b      	ldr	r3, [r7, #16]
+ 8039e1e:	ee07 3a90 	vmov	s15, r3
+ 8039e22:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 8039e26:	eddf 6a58 	vldr	s13, [pc, #352]	@ 8039f88 <HAL_RCC_GetSysClockFreq+0x2e8>
+ 8039e2a:	ee86 7aa7 	vdiv.f32	s14, s13, s15
+ 8039e2e:	4b51      	ldr	r3, [pc, #324]	@ (8039f74 <HAL_RCC_GetSysClockFreq+0x2d4>)
+ 8039e30:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
+ 8039e32:	f3c3 0308 	ubfx	r3, r3, #0, #9
+ 8039e36:	ee07 3a90 	vmov	s15, r3
+ 8039e3a:	eef8 6a67 	vcvt.f32.u32	s13, s15
+ 8039e3e:	ed97 6a02 	vldr	s12, [r7, #8]
+ 8039e42:	eddf 5a50 	vldr	s11, [pc, #320]	@ 8039f84 <HAL_RCC_GetSysClockFreq+0x2e4>
+ 8039e46:	eec6 7a25 	vdiv.f32	s15, s12, s11
+ 8039e4a:	ee76 7aa7 	vadd.f32	s15, s13, s15
+ 8039e4e:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
+ 8039e52:	ee77 7aa6 	vadd.f32	s15, s15, s13
+ 8039e56:	ee67 7a27 	vmul.f32	s15, s14, s15
+ 8039e5a:	edc7 7a07 	vstr	s15, [r7, #28]
+            break;
+ 8039e5e:	e065      	b.n	8039f2c <HAL_RCC_GetSysClockFreq+0x28c>
+
+          case RCC_PLLSOURCE_CSI:  /* CSI used as PLL clock source */
+            pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
+ 8039e60:	693b      	ldr	r3, [r7, #16]
+ 8039e62:	ee07 3a90 	vmov	s15, r3
+ 8039e66:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 8039e6a:	eddf 6a48 	vldr	s13, [pc, #288]	@ 8039f8c <HAL_RCC_GetSysClockFreq+0x2ec>
+ 8039e6e:	ee86 7aa7 	vdiv.f32	s14, s13, s15
+ 8039e72:	4b40      	ldr	r3, [pc, #256]	@ (8039f74 <HAL_RCC_GetSysClockFreq+0x2d4>)
+ 8039e74:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
+ 8039e76:	f3c3 0308 	ubfx	r3, r3, #0, #9
+ 8039e7a:	ee07 3a90 	vmov	s15, r3
+ 8039e7e:	eef8 6a67 	vcvt.f32.u32	s13, s15
+ 8039e82:	ed97 6a02 	vldr	s12, [r7, #8]
+ 8039e86:	eddf 5a3f 	vldr	s11, [pc, #252]	@ 8039f84 <HAL_RCC_GetSysClockFreq+0x2e4>
+ 8039e8a:	eec6 7a25 	vdiv.f32	s15, s12, s11
+ 8039e8e:	ee76 7aa7 	vadd.f32	s15, s13, s15
+ 8039e92:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
+ 8039e96:	ee77 7aa6 	vadd.f32	s15, s15, s13
+ 8039e9a:	ee67 7a27 	vmul.f32	s15, s14, s15
+ 8039e9e:	edc7 7a07 	vstr	s15, [r7, #28]
+            break;
+ 8039ea2:	e043      	b.n	8039f2c <HAL_RCC_GetSysClockFreq+0x28c>
+
+          case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
+            pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
+ 8039ea4:	693b      	ldr	r3, [r7, #16]
+ 8039ea6:	ee07 3a90 	vmov	s15, r3
+ 8039eaa:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 8039eae:	eddf 6a38 	vldr	s13, [pc, #224]	@ 8039f90 <HAL_RCC_GetSysClockFreq+0x2f0>
+ 8039eb2:	ee86 7aa7 	vdiv.f32	s14, s13, s15
+ 8039eb6:	4b2f      	ldr	r3, [pc, #188]	@ (8039f74 <HAL_RCC_GetSysClockFreq+0x2d4>)
+ 8039eb8:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
+ 8039eba:	f3c3 0308 	ubfx	r3, r3, #0, #9
+ 8039ebe:	ee07 3a90 	vmov	s15, r3
+ 8039ec2:	eef8 6a67 	vcvt.f32.u32	s13, s15
+ 8039ec6:	ed97 6a02 	vldr	s12, [r7, #8]
+ 8039eca:	eddf 5a2e 	vldr	s11, [pc, #184]	@ 8039f84 <HAL_RCC_GetSysClockFreq+0x2e4>
+ 8039ece:	eec6 7a25 	vdiv.f32	s15, s12, s11
+ 8039ed2:	ee76 7aa7 	vadd.f32	s15, s13, s15
+ 8039ed6:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
+ 8039eda:	ee77 7aa6 	vadd.f32	s15, s15, s13
+ 8039ede:	ee67 7a27 	vmul.f32	s15, s14, s15
+ 8039ee2:	edc7 7a07 	vstr	s15, [r7, #28]
+            break;
+ 8039ee6:	e021      	b.n	8039f2c <HAL_RCC_GetSysClockFreq+0x28c>
+
+          default:
+            pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
+ 8039ee8:	693b      	ldr	r3, [r7, #16]
+ 8039eea:	ee07 3a90 	vmov	s15, r3
+ 8039eee:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 8039ef2:	eddf 6a26 	vldr	s13, [pc, #152]	@ 8039f8c <HAL_RCC_GetSysClockFreq+0x2ec>
+ 8039ef6:	ee86 7aa7 	vdiv.f32	s14, s13, s15
+ 8039efa:	4b1e      	ldr	r3, [pc, #120]	@ (8039f74 <HAL_RCC_GetSysClockFreq+0x2d4>)
+ 8039efc:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
+ 8039efe:	f3c3 0308 	ubfx	r3, r3, #0, #9
+ 8039f02:	ee07 3a90 	vmov	s15, r3
+ 8039f06:	eef8 6a67 	vcvt.f32.u32	s13, s15
+ 8039f0a:	ed97 6a02 	vldr	s12, [r7, #8]
+ 8039f0e:	eddf 5a1d 	vldr	s11, [pc, #116]	@ 8039f84 <HAL_RCC_GetSysClockFreq+0x2e4>
+ 8039f12:	eec6 7a25 	vdiv.f32	s15, s12, s11
+ 8039f16:	ee76 7aa7 	vadd.f32	s15, s13, s15
+ 8039f1a:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
+ 8039f1e:	ee77 7aa6 	vadd.f32	s15, s15, s13
+ 8039f22:	ee67 7a27 	vmul.f32	s15, s14, s15
+ 8039f26:	edc7 7a07 	vstr	s15, [r7, #28]
+            break;
+ 8039f2a:	bf00      	nop
+        }
+        pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + 1U) ;
+ 8039f2c:	4b11      	ldr	r3, [pc, #68]	@ (8039f74 <HAL_RCC_GetSysClockFreq+0x2d4>)
+ 8039f2e:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
+ 8039f30:	0a5b      	lsrs	r3, r3, #9
+ 8039f32:	f003 037f 	and.w	r3, r3, #127	@ 0x7f
+ 8039f36:	3301      	adds	r3, #1
+ 8039f38:	603b      	str	r3, [r7, #0]
+        sysclockfreq = (uint32_t)(float_t)(pllvco / (float_t)pllp);
+ 8039f3a:	683b      	ldr	r3, [r7, #0]
+ 8039f3c:	ee07 3a90 	vmov	s15, r3
+ 8039f40:	eeb8 7a67 	vcvt.f32.u32	s14, s15
+ 8039f44:	edd7 6a07 	vldr	s13, [r7, #28]
+ 8039f48:	eec6 7a87 	vdiv.f32	s15, s13, s14
+ 8039f4c:	eefc 7ae7 	vcvt.u32.f32	s15, s15
+ 8039f50:	ee17 3a90 	vmov	r3, s15
+ 8039f54:	61bb      	str	r3, [r7, #24]
+      }
+      else
+      {
+        sysclockfreq = 0U;
+      }
+      break;
+ 8039f56:	e005      	b.n	8039f64 <HAL_RCC_GetSysClockFreq+0x2c4>
+        sysclockfreq = 0U;
+ 8039f58:	2300      	movs	r3, #0
+ 8039f5a:	61bb      	str	r3, [r7, #24]
+      break;
+ 8039f5c:	e002      	b.n	8039f64 <HAL_RCC_GetSysClockFreq+0x2c4>
+
+    default:
+      sysclockfreq = CSI_VALUE;
+ 8039f5e:	4b07      	ldr	r3, [pc, #28]	@ (8039f7c <HAL_RCC_GetSysClockFreq+0x2dc>)
+ 8039f60:	61bb      	str	r3, [r7, #24]
+      break;
+ 8039f62:	bf00      	nop
+  }
+
+  return sysclockfreq;
+ 8039f64:	69bb      	ldr	r3, [r7, #24]
+}
+ 8039f66:	4618      	mov	r0, r3
+ 8039f68:	3724      	adds	r7, #36	@ 0x24
+ 8039f6a:	46bd      	mov	sp, r7
+ 8039f6c:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 8039f70:	4770      	bx	lr
+ 8039f72:	bf00      	nop
+ 8039f74:	58024400 	.word	0x58024400
+ 8039f78:	03d09000 	.word	0x03d09000
+ 8039f7c:	003d0900 	.word	0x003d0900
+ 8039f80:	017d7840 	.word	0x017d7840
+ 8039f84:	46000000 	.word	0x46000000
+ 8039f88:	4c742400 	.word	0x4c742400
+ 8039f8c:	4a742400 	.word	0x4a742400
+ 8039f90:	4bbebc20 	.word	0x4bbebc20
+
+08039f94 <HAL_RCC_GetHCLKFreq>:
+  * @note   The SystemD2Clock CMSIS variable is used to store System domain2 Clock Frequency
+  *         and updated within this function
+  * @retval HCLK frequency
+  */
+uint32_t HAL_RCC_GetHCLKFreq(void)
+{
+ 8039f94:	b580      	push	{r7, lr}
+ 8039f96:	b082      	sub	sp, #8
+ 8039f98:	af00      	add	r7, sp, #0
+  uint32_t common_system_clock;
+
+#if defined(RCC_D1CFGR_D1CPRE)
+  common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
+ 8039f9a:	f7ff fe81 	bl	8039ca0 <HAL_RCC_GetSysClockFreq>
+ 8039f9e:	4602      	mov	r2, r0
+ 8039fa0:	4b10      	ldr	r3, [pc, #64]	@ (8039fe4 <HAL_RCC_GetHCLKFreq+0x50>)
+ 8039fa2:	699b      	ldr	r3, [r3, #24]
+ 8039fa4:	0a1b      	lsrs	r3, r3, #8
+ 8039fa6:	f003 030f 	and.w	r3, r3, #15
+ 8039faa:	490f      	ldr	r1, [pc, #60]	@ (8039fe8 <HAL_RCC_GetHCLKFreq+0x54>)
+ 8039fac:	5ccb      	ldrb	r3, [r1, r3]
+ 8039fae:	f003 031f 	and.w	r3, r3, #31
+ 8039fb2:	fa22 f303 	lsr.w	r3, r2, r3
+ 8039fb6:	607b      	str	r3, [r7, #4]
+#else
+  common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU);
+#endif
+
+#if defined(RCC_D1CFGR_HPRE)
+  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
+ 8039fb8:	4b0a      	ldr	r3, [pc, #40]	@ (8039fe4 <HAL_RCC_GetHCLKFreq+0x50>)
+ 8039fba:	699b      	ldr	r3, [r3, #24]
+ 8039fbc:	f003 030f 	and.w	r3, r3, #15
+ 8039fc0:	4a09      	ldr	r2, [pc, #36]	@ (8039fe8 <HAL_RCC_GetHCLKFreq+0x54>)
+ 8039fc2:	5cd3      	ldrb	r3, [r2, r3]
+ 8039fc4:	f003 031f 	and.w	r3, r3, #31
+ 8039fc8:	687a      	ldr	r2, [r7, #4]
+ 8039fca:	fa22 f303 	lsr.w	r3, r2, r3
+ 8039fce:	4a07      	ldr	r2, [pc, #28]	@ (8039fec <HAL_RCC_GetHCLKFreq+0x58>)
+ 8039fd0:	6013      	str	r3, [r2, #0]
+#endif
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+  SystemCoreClock = SystemD2Clock;
+#else
+  SystemCoreClock = common_system_clock;
+ 8039fd2:	4a07      	ldr	r2, [pc, #28]	@ (8039ff0 <HAL_RCC_GetHCLKFreq+0x5c>)
+ 8039fd4:	687b      	ldr	r3, [r7, #4]
+ 8039fd6:	6013      	str	r3, [r2, #0]
+#endif /* DUAL_CORE && CORE_CM4 */
+
+  return SystemD2Clock;
+ 8039fd8:	4b04      	ldr	r3, [pc, #16]	@ (8039fec <HAL_RCC_GetHCLKFreq+0x58>)
+ 8039fda:	681b      	ldr	r3, [r3, #0]
+}
+ 8039fdc:	4618      	mov	r0, r3
+ 8039fde:	3708      	adds	r7, #8
+ 8039fe0:	46bd      	mov	sp, r7
+ 8039fe2:	bd80      	pop	{r7, pc}
+ 8039fe4:	58024400 	.word	0x58024400
+ 8039fe8:	08041c58 	.word	0x08041c58
+ 8039fec:	24000130 	.word	0x24000130
+ 8039ff0:	2400012c 	.word	0x2400012c
+
+08039ff4 <HAL_RCC_GetPCLK1Freq>:
+  * @note   Each time PCLK1 changes, this function must be called to update the
+  *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
+  * @retval PCLK1 frequency
+  */
+uint32_t HAL_RCC_GetPCLK1Freq(void)
+{
+ 8039ff4:	b580      	push	{r7, lr}
+ 8039ff6:	af00      	add	r7, sp, #0
+#if defined (RCC_D2CFGR_D2PPRE1)
+  /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
+  return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1) >> RCC_D2CFGR_D2PPRE1_Pos]) & 0x1FU));
+ 8039ff8:	f7ff ffcc 	bl	8039f94 <HAL_RCC_GetHCLKFreq>
+ 8039ffc:	4602      	mov	r2, r0
+ 8039ffe:	4b06      	ldr	r3, [pc, #24]	@ (803a018 <HAL_RCC_GetPCLK1Freq+0x24>)
+ 803a000:	69db      	ldr	r3, [r3, #28]
+ 803a002:	091b      	lsrs	r3, r3, #4
+ 803a004:	f003 0307 	and.w	r3, r3, #7
+ 803a008:	4904      	ldr	r1, [pc, #16]	@ (803a01c <HAL_RCC_GetPCLK1Freq+0x28>)
+ 803a00a:	5ccb      	ldrb	r3, [r1, r3]
+ 803a00c:	f003 031f 	and.w	r3, r3, #31
+ 803a010:	fa22 f303 	lsr.w	r3, r2, r3
+#else
+  /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
+  return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1) >> RCC_CDCFGR2_CDPPRE1_Pos]) & 0x1FU));
+#endif
+}
+ 803a014:	4618      	mov	r0, r3
+ 803a016:	bd80      	pop	{r7, pc}
+ 803a018:	58024400 	.word	0x58024400
+ 803a01c:	08041c58 	.word	0x08041c58
+
+0803a020 <HAL_RCC_GetPCLK2Freq>:
+  * @note   Each time PCLK2 changes, this function must be called to update the
+  *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
+  * @retval PCLK1 frequency
+  */
+uint32_t HAL_RCC_GetPCLK2Freq(void)
+{
+ 803a020:	b580      	push	{r7, lr}
+ 803a022:	af00      	add	r7, sp, #0
+  /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
+#if defined(RCC_D2CFGR_D2PPRE2)
+  return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2) >> RCC_D2CFGR_D2PPRE2_Pos]) & 0x1FU));
+ 803a024:	f7ff ffb6 	bl	8039f94 <HAL_RCC_GetHCLKFreq>
+ 803a028:	4602      	mov	r2, r0
+ 803a02a:	4b06      	ldr	r3, [pc, #24]	@ (803a044 <HAL_RCC_GetPCLK2Freq+0x24>)
+ 803a02c:	69db      	ldr	r3, [r3, #28]
+ 803a02e:	0a1b      	lsrs	r3, r3, #8
+ 803a030:	f003 0307 	and.w	r3, r3, #7
+ 803a034:	4904      	ldr	r1, [pc, #16]	@ (803a048 <HAL_RCC_GetPCLK2Freq+0x28>)
+ 803a036:	5ccb      	ldrb	r3, [r1, r3]
+ 803a038:	f003 031f 	and.w	r3, r3, #31
+ 803a03c:	fa22 f303 	lsr.w	r3, r2, r3
+#else
+  return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2) >> RCC_CDCFGR2_CDPPRE2_Pos]) & 0x1FU));
+#endif
+}
+ 803a040:	4618      	mov	r0, r3
+ 803a042:	bd80      	pop	{r7, pc}
+ 803a044:	58024400 	.word	0x58024400
+ 803a048:	08041c58 	.word	0x08041c58
+
+0803a04c <HAL_RCC_NMI_IRQHandler>:
+  * @brief This function handles the RCC CSS interrupt request.
+  * @note This API should be called under the NMI_Handler().
+  * @retval None
+  */
+void HAL_RCC_NMI_IRQHandler(void)
+{
+ 803a04c:	b580      	push	{r7, lr}
+ 803a04e:	af00      	add	r7, sp, #0
+  /* Check RCC CSSF flag  */
+  if (__HAL_RCC_GET_IT(RCC_IT_CSS))
+ 803a050:	4b07      	ldr	r3, [pc, #28]	@ (803a070 <HAL_RCC_NMI_IRQHandler+0x24>)
+ 803a052:	6e5b      	ldr	r3, [r3, #100]	@ 0x64
+ 803a054:	f403 6380 	and.w	r3, r3, #1024	@ 0x400
+ 803a058:	f5b3 6f80 	cmp.w	r3, #1024	@ 0x400
+ 803a05c:	d105      	bne.n	803a06a <HAL_RCC_NMI_IRQHandler+0x1e>
+  {
+    /* RCC Clock Security System interrupt user callback */
+    HAL_RCC_CSSCallback();
+ 803a05e:	f000 f809 	bl	803a074 <HAL_RCC_CSSCallback>
+
+    /* Clear RCC CSS pending bit */
+    __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
+ 803a062:	4b03      	ldr	r3, [pc, #12]	@ (803a070 <HAL_RCC_NMI_IRQHandler+0x24>)
+ 803a064:	f44f 6280 	mov.w	r2, #1024	@ 0x400
+ 803a068:	669a      	str	r2, [r3, #104]	@ 0x68
+  }
+}
+ 803a06a:	bf00      	nop
+ 803a06c:	bd80      	pop	{r7, pc}
+ 803a06e:	bf00      	nop
+ 803a070:	58024400 	.word	0x58024400
+
+0803a074 <HAL_RCC_CSSCallback>:
+/**
+  * @brief  RCC Clock Security System interrupt callback
+  * @retval none
+  */
+__weak void HAL_RCC_CSSCallback(void)
+{
+ 803a074:	b480      	push	{r7}
+ 803a076:	af00      	add	r7, sp, #0
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_RCC_CSSCallback could be implemented in the user file
+   */
+}
+ 803a078:	bf00      	nop
+ 803a07a:	46bd      	mov	sp, r7
+ 803a07c:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 803a080:	4770      	bx	lr
+	...
+
+0803a084 <HAL_RCCEx_PeriphCLKConfig>:
+  * (*) : Available on some STM32H7 lines only.
+  *
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+{
+ 803a084:	e92d 4fb0 	stmdb	sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
+ 803a088:	b0ca      	sub	sp, #296	@ 0x128
+ 803a08a:	af00      	add	r7, sp, #0
+ 803a08c:	f8c7 0114 	str.w	r0, [r7, #276]	@ 0x114
+  uint32_t tmpreg;
+  uint32_t tickstart;
+  HAL_StatusTypeDef ret = HAL_OK;      /* Intermediate status */
+ 803a090:	2300      	movs	r3, #0
+ 803a092:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+  HAL_StatusTypeDef status = HAL_OK;   /* Final status */
+ 803a096:	2300      	movs	r3, #0
+ 803a098:	f887 3126 	strb.w	r3, [r7, #294]	@ 0x126
+
+  /*---------------------------- SPDIFRX configuration -------------------------------*/
+
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
+ 803a09c:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803a0a0:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 803a0a4:	f002 6400 	and.w	r4, r2, #134217728	@ 0x8000000
+ 803a0a8:	2500      	movs	r5, #0
+ 803a0aa:	ea54 0305 	orrs.w	r3, r4, r5
+ 803a0ae:	d049      	beq.n	803a144 <HAL_RCCEx_PeriphCLKConfig+0xc0>
+  {
+
+    switch (PeriphClkInit->SpdifrxClockSelection)
+ 803a0b0:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803a0b4:	6e9b      	ldr	r3, [r3, #104]	@ 0x68
+ 803a0b6:	f5b3 1f40 	cmp.w	r3, #3145728	@ 0x300000
+ 803a0ba:	d02f      	beq.n	803a11c <HAL_RCCEx_PeriphCLKConfig+0x98>
+ 803a0bc:	f5b3 1f40 	cmp.w	r3, #3145728	@ 0x300000
+ 803a0c0:	d828      	bhi.n	803a114 <HAL_RCCEx_PeriphCLKConfig+0x90>
+ 803a0c2:	f5b3 1f00 	cmp.w	r3, #2097152	@ 0x200000
+ 803a0c6:	d01a      	beq.n	803a0fe <HAL_RCCEx_PeriphCLKConfig+0x7a>
+ 803a0c8:	f5b3 1f00 	cmp.w	r3, #2097152	@ 0x200000
+ 803a0cc:	d822      	bhi.n	803a114 <HAL_RCCEx_PeriphCLKConfig+0x90>
+ 803a0ce:	2b00      	cmp	r3, #0
+ 803a0d0:	d003      	beq.n	803a0da <HAL_RCCEx_PeriphCLKConfig+0x56>
+ 803a0d2:	f5b3 1f80 	cmp.w	r3, #1048576	@ 0x100000
+ 803a0d6:	d007      	beq.n	803a0e8 <HAL_RCCEx_PeriphCLKConfig+0x64>
+ 803a0d8:	e01c      	b.n	803a114 <HAL_RCCEx_PeriphCLKConfig+0x90>
+    {
+      case RCC_SPDIFRXCLKSOURCE_PLL:      /* PLL is used as clock source for SPDIFRX*/
+        /* Enable PLL1Q Clock output generated form System PLL . */
+        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+ 803a0da:	4bb8      	ldr	r3, [pc, #736]	@ (803a3bc <HAL_RCCEx_PeriphCLKConfig+0x338>)
+ 803a0dc:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 803a0de:	4ab7      	ldr	r2, [pc, #732]	@ (803a3bc <HAL_RCCEx_PeriphCLKConfig+0x338>)
+ 803a0e0:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
+ 803a0e4:	62d3      	str	r3, [r2, #44]	@ 0x2c
+
+        /* SPDIFRX clock source configuration done later after clock selection check */
+        break;
+ 803a0e6:	e01a      	b.n	803a11e <HAL_RCCEx_PeriphCLKConfig+0x9a>
+
+      case RCC_SPDIFRXCLKSOURCE_PLL2: /* PLL2 is used as clock source for SPDIFRX*/
+
+        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE);
+ 803a0e8:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803a0ec:	3308      	adds	r3, #8
+ 803a0ee:	2102      	movs	r1, #2
+ 803a0f0:	4618      	mov	r0, r3
+ 803a0f2:	f002 fb61 	bl	803c7b8 <RCCEx_PLL2_Config>
+ 803a0f6:	4603      	mov	r3, r0
+ 803a0f8:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+
+        /* SPDIFRX clock source configuration done later after clock selection check */
+        break;
+ 803a0fc:	e00f      	b.n	803a11e <HAL_RCCEx_PeriphCLKConfig+0x9a>
+
+      case RCC_SPDIFRXCLKSOURCE_PLL3:  /* PLL3 is used as clock source for SPDIFRX*/
+        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE);
+ 803a0fe:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803a102:	3328      	adds	r3, #40	@ 0x28
+ 803a104:	2102      	movs	r1, #2
+ 803a106:	4618      	mov	r0, r3
+ 803a108:	f002 fc08 	bl	803c91c <RCCEx_PLL3_Config>
+ 803a10c:	4603      	mov	r3, r0
+ 803a10e:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+
+        /* SPDIFRX clock source configuration done later after clock selection check */
+        break;
+ 803a112:	e004      	b.n	803a11e <HAL_RCCEx_PeriphCLKConfig+0x9a>
+        /* Internal OSC clock is used as source of SPDIFRX clock*/
+        /* SPDIFRX clock source configuration done later after clock selection check */
+        break;
+
+      default:
+        ret = HAL_ERROR;
+ 803a114:	2301      	movs	r3, #1
+ 803a116:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+        break;
+ 803a11a:	e000      	b.n	803a11e <HAL_RCCEx_PeriphCLKConfig+0x9a>
+        break;
+ 803a11c:	bf00      	nop
+    }
+
+    if (ret == HAL_OK)
+ 803a11e:	f897 3127 	ldrb.w	r3, [r7, #295]	@ 0x127
+ 803a122:	2b00      	cmp	r3, #0
+ 803a124:	d10a      	bne.n	803a13c <HAL_RCCEx_PeriphCLKConfig+0xb8>
+    {
+      /* Set the source of SPDIFRX clock*/
+      __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifrxClockSelection);
+ 803a126:	4ba5      	ldr	r3, [pc, #660]	@ (803a3bc <HAL_RCCEx_PeriphCLKConfig+0x338>)
+ 803a128:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
+ 803a12a:	f423 1140 	bic.w	r1, r3, #3145728	@ 0x300000
+ 803a12e:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803a132:	6e9b      	ldr	r3, [r3, #104]	@ 0x68
+ 803a134:	4aa1      	ldr	r2, [pc, #644]	@ (803a3bc <HAL_RCCEx_PeriphCLKConfig+0x338>)
+ 803a136:	430b      	orrs	r3, r1
+ 803a138:	6513      	str	r3, [r2, #80]	@ 0x50
+ 803a13a:	e003      	b.n	803a144 <HAL_RCCEx_PeriphCLKConfig+0xc0>
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+ 803a13c:	f897 3127 	ldrb.w	r3, [r7, #295]	@ 0x127
+ 803a140:	f887 3126 	strb.w	r3, [r7, #294]	@ 0x126
+    }
+  }
+
+  /*---------------------------- SAI1 configuration -------------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)
+ 803a144:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803a148:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 803a14c:	f402 7880 	and.w	r8, r2, #256	@ 0x100
+ 803a150:	f04f 0900 	mov.w	r9, #0
+ 803a154:	ea58 0309 	orrs.w	r3, r8, r9
+ 803a158:	d047      	beq.n	803a1ea <HAL_RCCEx_PeriphCLKConfig+0x166>
+  {
+    switch (PeriphClkInit->Sai1ClockSelection)
+ 803a15a:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803a15e:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
+ 803a160:	2b04      	cmp	r3, #4
+ 803a162:	d82a      	bhi.n	803a1ba <HAL_RCCEx_PeriphCLKConfig+0x136>
+ 803a164:	a201      	add	r2, pc, #4	@ (adr r2, 803a16c <HAL_RCCEx_PeriphCLKConfig+0xe8>)
+ 803a166:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 803a16a:	bf00      	nop
+ 803a16c:	0803a181 	.word	0x0803a181
+ 803a170:	0803a18f 	.word	0x0803a18f
+ 803a174:	0803a1a5 	.word	0x0803a1a5
+ 803a178:	0803a1c3 	.word	0x0803a1c3
+ 803a17c:	0803a1c3 	.word	0x0803a1c3
+    {
+      case RCC_SAI1CLKSOURCE_PLL:      /* PLL is used as clock source for SAI1*/
+        /* Enable SAI Clock output generated form System PLL . */
+        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+ 803a180:	4b8e      	ldr	r3, [pc, #568]	@ (803a3bc <HAL_RCCEx_PeriphCLKConfig+0x338>)
+ 803a182:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 803a184:	4a8d      	ldr	r2, [pc, #564]	@ (803a3bc <HAL_RCCEx_PeriphCLKConfig+0x338>)
+ 803a186:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
+ 803a18a:	62d3      	str	r3, [r2, #44]	@ 0x2c
+
+        /* SAI1 clock source configuration done later after clock selection check */
+        break;
+ 803a18c:	e01a      	b.n	803a1c4 <HAL_RCCEx_PeriphCLKConfig+0x140>
+
+      case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI1*/
+
+        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
+ 803a18e:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803a192:	3308      	adds	r3, #8
+ 803a194:	2100      	movs	r1, #0
+ 803a196:	4618      	mov	r0, r3
+ 803a198:	f002 fb0e 	bl	803c7b8 <RCCEx_PLL2_Config>
+ 803a19c:	4603      	mov	r3, r0
+ 803a19e:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+
+        /* SAI1 clock source configuration done later after clock selection check */
+        break;
+ 803a1a2:	e00f      	b.n	803a1c4 <HAL_RCCEx_PeriphCLKConfig+0x140>
+
+      case RCC_SAI1CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI1*/
+        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
+ 803a1a4:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803a1a8:	3328      	adds	r3, #40	@ 0x28
+ 803a1aa:	2100      	movs	r1, #0
+ 803a1ac:	4618      	mov	r0, r3
+ 803a1ae:	f002 fbb5 	bl	803c91c <RCCEx_PLL3_Config>
+ 803a1b2:	4603      	mov	r3, r0
+ 803a1b4:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+
+        /* SAI1 clock source configuration done later after clock selection check */
+        break;
+ 803a1b8:	e004      	b.n	803a1c4 <HAL_RCCEx_PeriphCLKConfig+0x140>
+        /* HSI, HSE, or CSI oscillator is used as source of SAI1 clock */
+        /* SAI1 clock source configuration done later after clock selection check */
+        break;
+
+      default:
+        ret = HAL_ERROR;
+ 803a1ba:	2301      	movs	r3, #1
+ 803a1bc:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+        break;
+ 803a1c0:	e000      	b.n	803a1c4 <HAL_RCCEx_PeriphCLKConfig+0x140>
+        break;
+ 803a1c2:	bf00      	nop
+    }
+
+    if (ret == HAL_OK)
+ 803a1c4:	f897 3127 	ldrb.w	r3, [r7, #295]	@ 0x127
+ 803a1c8:	2b00      	cmp	r3, #0
+ 803a1ca:	d10a      	bne.n	803a1e2 <HAL_RCCEx_PeriphCLKConfig+0x15e>
+    {
+      /* Set the source of SAI1 clock*/
+      __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
+ 803a1cc:	4b7b      	ldr	r3, [pc, #492]	@ (803a3bc <HAL_RCCEx_PeriphCLKConfig+0x338>)
+ 803a1ce:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
+ 803a1d0:	f023 0107 	bic.w	r1, r3, #7
+ 803a1d4:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803a1d8:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
+ 803a1da:	4a78      	ldr	r2, [pc, #480]	@ (803a3bc <HAL_RCCEx_PeriphCLKConfig+0x338>)
+ 803a1dc:	430b      	orrs	r3, r1
+ 803a1de:	6513      	str	r3, [r2, #80]	@ 0x50
+ 803a1e0:	e003      	b.n	803a1ea <HAL_RCCEx_PeriphCLKConfig+0x166>
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+ 803a1e2:	f897 3127 	ldrb.w	r3, [r7, #295]	@ 0x127
+ 803a1e6:	f887 3126 	strb.w	r3, [r7, #294]	@ 0x126
+    }
+  }
+
+#if defined(SAI3)
+  /*---------------------------- SAI2/3 configuration -------------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI23) == RCC_PERIPHCLK_SAI23)
+ 803a1ea:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803a1ee:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 803a1f2:	f402 7a00 	and.w	sl, r2, #512	@ 0x200
+ 803a1f6:	f04f 0b00 	mov.w	fp, #0
+ 803a1fa:	ea5a 030b 	orrs.w	r3, sl, fp
+ 803a1fe:	d04c      	beq.n	803a29a <HAL_RCCEx_PeriphCLKConfig+0x216>
+  {
+    switch (PeriphClkInit->Sai23ClockSelection)
+ 803a200:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803a204:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
+ 803a206:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
+ 803a20a:	d030      	beq.n	803a26e <HAL_RCCEx_PeriphCLKConfig+0x1ea>
+ 803a20c:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
+ 803a210:	d829      	bhi.n	803a266 <HAL_RCCEx_PeriphCLKConfig+0x1e2>
+ 803a212:	2bc0      	cmp	r3, #192	@ 0xc0
+ 803a214:	d02d      	beq.n	803a272 <HAL_RCCEx_PeriphCLKConfig+0x1ee>
+ 803a216:	2bc0      	cmp	r3, #192	@ 0xc0
+ 803a218:	d825      	bhi.n	803a266 <HAL_RCCEx_PeriphCLKConfig+0x1e2>
+ 803a21a:	2b80      	cmp	r3, #128	@ 0x80
+ 803a21c:	d018      	beq.n	803a250 <HAL_RCCEx_PeriphCLKConfig+0x1cc>
+ 803a21e:	2b80      	cmp	r3, #128	@ 0x80
+ 803a220:	d821      	bhi.n	803a266 <HAL_RCCEx_PeriphCLKConfig+0x1e2>
+ 803a222:	2b00      	cmp	r3, #0
+ 803a224:	d002      	beq.n	803a22c <HAL_RCCEx_PeriphCLKConfig+0x1a8>
+ 803a226:	2b40      	cmp	r3, #64	@ 0x40
+ 803a228:	d007      	beq.n	803a23a <HAL_RCCEx_PeriphCLKConfig+0x1b6>
+ 803a22a:	e01c      	b.n	803a266 <HAL_RCCEx_PeriphCLKConfig+0x1e2>
+    {
+      case RCC_SAI23CLKSOURCE_PLL:      /* PLL is used as clock source for SAI2/3 */
+        /* Enable SAI Clock output generated form System PLL . */
+        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+ 803a22c:	4b63      	ldr	r3, [pc, #396]	@ (803a3bc <HAL_RCCEx_PeriphCLKConfig+0x338>)
+ 803a22e:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 803a230:	4a62      	ldr	r2, [pc, #392]	@ (803a3bc <HAL_RCCEx_PeriphCLKConfig+0x338>)
+ 803a232:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
+ 803a236:	62d3      	str	r3, [r2, #44]	@ 0x2c
+
+        /* SAI2/3 clock source configuration done later after clock selection check */
+        break;
+ 803a238:	e01c      	b.n	803a274 <HAL_RCCEx_PeriphCLKConfig+0x1f0>
+
+      case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2/3 */
+
+        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
+ 803a23a:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803a23e:	3308      	adds	r3, #8
+ 803a240:	2100      	movs	r1, #0
+ 803a242:	4618      	mov	r0, r3
+ 803a244:	f002 fab8 	bl	803c7b8 <RCCEx_PLL2_Config>
+ 803a248:	4603      	mov	r3, r0
+ 803a24a:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+
+        /* SAI2/3 clock source configuration done later after clock selection check */
+        break;
+ 803a24e:	e011      	b.n	803a274 <HAL_RCCEx_PeriphCLKConfig+0x1f0>
+
+      case RCC_SAI23CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI2/3 */
+        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
+ 803a250:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803a254:	3328      	adds	r3, #40	@ 0x28
+ 803a256:	2100      	movs	r1, #0
+ 803a258:	4618      	mov	r0, r3
+ 803a25a:	f002 fb5f 	bl	803c91c <RCCEx_PLL3_Config>
+ 803a25e:	4603      	mov	r3, r0
+ 803a260:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+
+        /* SAI2/3 clock source configuration done later after clock selection check */
+        break;
+ 803a264:	e006      	b.n	803a274 <HAL_RCCEx_PeriphCLKConfig+0x1f0>
+        /* HSI, HSE, or CSI oscillator is used as source of SAI2/3 clock */
+        /* SAI2/3 clock source configuration done later after clock selection check */
+        break;
+
+      default:
+        ret = HAL_ERROR;
+ 803a266:	2301      	movs	r3, #1
+ 803a268:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+        break;
+ 803a26c:	e002      	b.n	803a274 <HAL_RCCEx_PeriphCLKConfig+0x1f0>
+        break;
+ 803a26e:	bf00      	nop
+ 803a270:	e000      	b.n	803a274 <HAL_RCCEx_PeriphCLKConfig+0x1f0>
+        break;
+ 803a272:	bf00      	nop
+    }
+
+    if (ret == HAL_OK)
+ 803a274:	f897 3127 	ldrb.w	r3, [r7, #295]	@ 0x127
+ 803a278:	2b00      	cmp	r3, #0
+ 803a27a:	d10a      	bne.n	803a292 <HAL_RCCEx_PeriphCLKConfig+0x20e>
+    {
+      /* Set the source of SAI2/3 clock*/
+      __HAL_RCC_SAI23_CONFIG(PeriphClkInit->Sai23ClockSelection);
+ 803a27c:	4b4f      	ldr	r3, [pc, #316]	@ (803a3bc <HAL_RCCEx_PeriphCLKConfig+0x338>)
+ 803a27e:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
+ 803a280:	f423 71e0 	bic.w	r1, r3, #448	@ 0x1c0
+ 803a284:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803a288:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
+ 803a28a:	4a4c      	ldr	r2, [pc, #304]	@ (803a3bc <HAL_RCCEx_PeriphCLKConfig+0x338>)
+ 803a28c:	430b      	orrs	r3, r1
+ 803a28e:	6513      	str	r3, [r2, #80]	@ 0x50
+ 803a290:	e003      	b.n	803a29a <HAL_RCCEx_PeriphCLKConfig+0x216>
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+ 803a292:	f897 3127 	ldrb.w	r3, [r7, #295]	@ 0x127
+ 803a296:	f887 3126 	strb.w	r3, [r7, #294]	@ 0x126
+  }
+#endif  /*SAI2B*/
+
+#if defined(SAI4)
+  /*---------------------------- SAI4A configuration -------------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4A) == RCC_PERIPHCLK_SAI4A)
+ 803a29a:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803a29e:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 803a2a2:	f402 6380 	and.w	r3, r2, #1024	@ 0x400
+ 803a2a6:	f8c7 3108 	str.w	r3, [r7, #264]	@ 0x108
+ 803a2aa:	2300      	movs	r3, #0
+ 803a2ac:	f8c7 310c 	str.w	r3, [r7, #268]	@ 0x10c
+ 803a2b0:	e9d7 1242 	ldrd	r1, r2, [r7, #264]	@ 0x108
+ 803a2b4:	460b      	mov	r3, r1
+ 803a2b6:	4313      	orrs	r3, r2
+ 803a2b8:	d053      	beq.n	803a362 <HAL_RCCEx_PeriphCLKConfig+0x2de>
+  {
+    switch (PeriphClkInit->Sai4AClockSelection)
+ 803a2ba:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803a2be:	f8d3 30a8 	ldr.w	r3, [r3, #168]	@ 0xa8
+ 803a2c2:	f5b3 0f00 	cmp.w	r3, #8388608	@ 0x800000
+ 803a2c6:	d035      	beq.n	803a334 <HAL_RCCEx_PeriphCLKConfig+0x2b0>
+ 803a2c8:	f5b3 0f00 	cmp.w	r3, #8388608	@ 0x800000
+ 803a2cc:	d82e      	bhi.n	803a32c <HAL_RCCEx_PeriphCLKConfig+0x2a8>
+ 803a2ce:	f5b3 0fc0 	cmp.w	r3, #6291456	@ 0x600000
+ 803a2d2:	d031      	beq.n	803a338 <HAL_RCCEx_PeriphCLKConfig+0x2b4>
+ 803a2d4:	f5b3 0fc0 	cmp.w	r3, #6291456	@ 0x600000
+ 803a2d8:	d828      	bhi.n	803a32c <HAL_RCCEx_PeriphCLKConfig+0x2a8>
+ 803a2da:	f5b3 0f80 	cmp.w	r3, #4194304	@ 0x400000
+ 803a2de:	d01a      	beq.n	803a316 <HAL_RCCEx_PeriphCLKConfig+0x292>
+ 803a2e0:	f5b3 0f80 	cmp.w	r3, #4194304	@ 0x400000
+ 803a2e4:	d822      	bhi.n	803a32c <HAL_RCCEx_PeriphCLKConfig+0x2a8>
+ 803a2e6:	2b00      	cmp	r3, #0
+ 803a2e8:	d003      	beq.n	803a2f2 <HAL_RCCEx_PeriphCLKConfig+0x26e>
+ 803a2ea:	f5b3 1f00 	cmp.w	r3, #2097152	@ 0x200000
+ 803a2ee:	d007      	beq.n	803a300 <HAL_RCCEx_PeriphCLKConfig+0x27c>
+ 803a2f0:	e01c      	b.n	803a32c <HAL_RCCEx_PeriphCLKConfig+0x2a8>
+    {
+      case RCC_SAI4ACLKSOURCE_PLL:      /* PLL is used as clock source for SAI2*/
+        /* Enable SAI Clock output generated form System PLL . */
+        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+ 803a2f2:	4b32      	ldr	r3, [pc, #200]	@ (803a3bc <HAL_RCCEx_PeriphCLKConfig+0x338>)
+ 803a2f4:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 803a2f6:	4a31      	ldr	r2, [pc, #196]	@ (803a3bc <HAL_RCCEx_PeriphCLKConfig+0x338>)
+ 803a2f8:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
+ 803a2fc:	62d3      	str	r3, [r2, #44]	@ 0x2c
+
+        /* SAI1 clock source configuration done later after clock selection check */
+        break;
+ 803a2fe:	e01c      	b.n	803a33a <HAL_RCCEx_PeriphCLKConfig+0x2b6>
+
+      case RCC_SAI4ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/
+
+        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
+ 803a300:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803a304:	3308      	adds	r3, #8
+ 803a306:	2100      	movs	r1, #0
+ 803a308:	4618      	mov	r0, r3
+ 803a30a:	f002 fa55 	bl	803c7b8 <RCCEx_PLL2_Config>
+ 803a30e:	4603      	mov	r3, r0
+ 803a310:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+
+        /* SAI2 clock source configuration done later after clock selection check */
+        break;
+ 803a314:	e011      	b.n	803a33a <HAL_RCCEx_PeriphCLKConfig+0x2b6>
+
+      case RCC_SAI4ACLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI2*/
+        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
+ 803a316:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803a31a:	3328      	adds	r3, #40	@ 0x28
+ 803a31c:	2100      	movs	r1, #0
+ 803a31e:	4618      	mov	r0, r3
+ 803a320:	f002 fafc 	bl	803c91c <RCCEx_PLL3_Config>
+ 803a324:	4603      	mov	r3, r0
+ 803a326:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+
+        /* SAI1 clock source configuration done later after clock selection check */
+        break;
+ 803a32a:	e006      	b.n	803a33a <HAL_RCCEx_PeriphCLKConfig+0x2b6>
+        /* SAI4A clock source configuration done later after clock selection check */
+        break;
+#endif /* RCC_VER_3_0 */
+
+      default:
+        ret = HAL_ERROR;
+ 803a32c:	2301      	movs	r3, #1
+ 803a32e:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+        break;
+ 803a332:	e002      	b.n	803a33a <HAL_RCCEx_PeriphCLKConfig+0x2b6>
+        break;
+ 803a334:	bf00      	nop
+ 803a336:	e000      	b.n	803a33a <HAL_RCCEx_PeriphCLKConfig+0x2b6>
+        break;
+ 803a338:	bf00      	nop
+    }
+
+    if (ret == HAL_OK)
+ 803a33a:	f897 3127 	ldrb.w	r3, [r7, #295]	@ 0x127
+ 803a33e:	2b00      	cmp	r3, #0
+ 803a340:	d10b      	bne.n	803a35a <HAL_RCCEx_PeriphCLKConfig+0x2d6>
+    {
+      /* Set the source of SAI4A clock*/
+      __HAL_RCC_SAI4A_CONFIG(PeriphClkInit->Sai4AClockSelection);
+ 803a342:	4b1e      	ldr	r3, [pc, #120]	@ (803a3bc <HAL_RCCEx_PeriphCLKConfig+0x338>)
+ 803a344:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
+ 803a346:	f423 0160 	bic.w	r1, r3, #14680064	@ 0xe00000
+ 803a34a:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803a34e:	f8d3 30a8 	ldr.w	r3, [r3, #168]	@ 0xa8
+ 803a352:	4a1a      	ldr	r2, [pc, #104]	@ (803a3bc <HAL_RCCEx_PeriphCLKConfig+0x338>)
+ 803a354:	430b      	orrs	r3, r1
+ 803a356:	6593      	str	r3, [r2, #88]	@ 0x58
+ 803a358:	e003      	b.n	803a362 <HAL_RCCEx_PeriphCLKConfig+0x2de>
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+ 803a35a:	f897 3127 	ldrb.w	r3, [r7, #295]	@ 0x127
+ 803a35e:	f887 3126 	strb.w	r3, [r7, #294]	@ 0x126
+    }
+  }
+  /*---------------------------- SAI4B configuration -------------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4B) == RCC_PERIPHCLK_SAI4B)
+ 803a362:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803a366:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 803a36a:	f402 6300 	and.w	r3, r2, #2048	@ 0x800
+ 803a36e:	f8c7 3100 	str.w	r3, [r7, #256]	@ 0x100
+ 803a372:	2300      	movs	r3, #0
+ 803a374:	f8c7 3104 	str.w	r3, [r7, #260]	@ 0x104
+ 803a378:	e9d7 1240 	ldrd	r1, r2, [r7, #256]	@ 0x100
+ 803a37c:	460b      	mov	r3, r1
+ 803a37e:	4313      	orrs	r3, r2
+ 803a380:	d056      	beq.n	803a430 <HAL_RCCEx_PeriphCLKConfig+0x3ac>
+  {
+    switch (PeriphClkInit->Sai4BClockSelection)
+ 803a382:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803a386:	f8d3 30ac 	ldr.w	r3, [r3, #172]	@ 0xac
+ 803a38a:	f1b3 6f80 	cmp.w	r3, #67108864	@ 0x4000000
+ 803a38e:	d038      	beq.n	803a402 <HAL_RCCEx_PeriphCLKConfig+0x37e>
+ 803a390:	f1b3 6f80 	cmp.w	r3, #67108864	@ 0x4000000
+ 803a394:	d831      	bhi.n	803a3fa <HAL_RCCEx_PeriphCLKConfig+0x376>
+ 803a396:	f1b3 7f40 	cmp.w	r3, #50331648	@ 0x3000000
+ 803a39a:	d034      	beq.n	803a406 <HAL_RCCEx_PeriphCLKConfig+0x382>
+ 803a39c:	f1b3 7f40 	cmp.w	r3, #50331648	@ 0x3000000
+ 803a3a0:	d82b      	bhi.n	803a3fa <HAL_RCCEx_PeriphCLKConfig+0x376>
+ 803a3a2:	f1b3 7f00 	cmp.w	r3, #33554432	@ 0x2000000
+ 803a3a6:	d01d      	beq.n	803a3e4 <HAL_RCCEx_PeriphCLKConfig+0x360>
+ 803a3a8:	f1b3 7f00 	cmp.w	r3, #33554432	@ 0x2000000
+ 803a3ac:	d825      	bhi.n	803a3fa <HAL_RCCEx_PeriphCLKConfig+0x376>
+ 803a3ae:	2b00      	cmp	r3, #0
+ 803a3b0:	d006      	beq.n	803a3c0 <HAL_RCCEx_PeriphCLKConfig+0x33c>
+ 803a3b2:	f1b3 7f80 	cmp.w	r3, #16777216	@ 0x1000000
+ 803a3b6:	d00a      	beq.n	803a3ce <HAL_RCCEx_PeriphCLKConfig+0x34a>
+ 803a3b8:	e01f      	b.n	803a3fa <HAL_RCCEx_PeriphCLKConfig+0x376>
+ 803a3ba:	bf00      	nop
+ 803a3bc:	58024400 	.word	0x58024400
+    {
+      case RCC_SAI4BCLKSOURCE_PLL:      /* PLL is used as clock source for SAI2*/
+        /* Enable SAI Clock output generated form System PLL . */
+        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+ 803a3c0:	4ba2      	ldr	r3, [pc, #648]	@ (803a64c <HAL_RCCEx_PeriphCLKConfig+0x5c8>)
+ 803a3c2:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 803a3c4:	4aa1      	ldr	r2, [pc, #644]	@ (803a64c <HAL_RCCEx_PeriphCLKConfig+0x5c8>)
+ 803a3c6:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
+ 803a3ca:	62d3      	str	r3, [r2, #44]	@ 0x2c
+
+        /* SAI1 clock source configuration done later after clock selection check */
+        break;
+ 803a3cc:	e01c      	b.n	803a408 <HAL_RCCEx_PeriphCLKConfig+0x384>
+
+      case RCC_SAI4BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/
+
+        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
+ 803a3ce:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803a3d2:	3308      	adds	r3, #8
+ 803a3d4:	2100      	movs	r1, #0
+ 803a3d6:	4618      	mov	r0, r3
+ 803a3d8:	f002 f9ee 	bl	803c7b8 <RCCEx_PLL2_Config>
+ 803a3dc:	4603      	mov	r3, r0
+ 803a3de:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+
+        /* SAI2 clock source configuration done later after clock selection check */
+        break;
+ 803a3e2:	e011      	b.n	803a408 <HAL_RCCEx_PeriphCLKConfig+0x384>
+
+      case RCC_SAI4BCLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI2*/
+        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
+ 803a3e4:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803a3e8:	3328      	adds	r3, #40	@ 0x28
+ 803a3ea:	2100      	movs	r1, #0
+ 803a3ec:	4618      	mov	r0, r3
+ 803a3ee:	f002 fa95 	bl	803c91c <RCCEx_PLL3_Config>
+ 803a3f2:	4603      	mov	r3, r0
+ 803a3f4:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+
+        /* SAI1 clock source configuration done later after clock selection check */
+        break;
+ 803a3f8:	e006      	b.n	803a408 <HAL_RCCEx_PeriphCLKConfig+0x384>
+        /* SAI4B clock source configuration done later after clock selection check */
+        break;
+#endif /* RCC_VER_3_0 */
+
+      default:
+        ret = HAL_ERROR;
+ 803a3fa:	2301      	movs	r3, #1
+ 803a3fc:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+        break;
+ 803a400:	e002      	b.n	803a408 <HAL_RCCEx_PeriphCLKConfig+0x384>
+        break;
+ 803a402:	bf00      	nop
+ 803a404:	e000      	b.n	803a408 <HAL_RCCEx_PeriphCLKConfig+0x384>
+        break;
+ 803a406:	bf00      	nop
+    }
+
+    if (ret == HAL_OK)
+ 803a408:	f897 3127 	ldrb.w	r3, [r7, #295]	@ 0x127
+ 803a40c:	2b00      	cmp	r3, #0
+ 803a40e:	d10b      	bne.n	803a428 <HAL_RCCEx_PeriphCLKConfig+0x3a4>
+    {
+      /* Set the source of SAI4B clock*/
+      __HAL_RCC_SAI4B_CONFIG(PeriphClkInit->Sai4BClockSelection);
+ 803a410:	4b8e      	ldr	r3, [pc, #568]	@ (803a64c <HAL_RCCEx_PeriphCLKConfig+0x5c8>)
+ 803a412:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
+ 803a414:	f023 61e0 	bic.w	r1, r3, #117440512	@ 0x7000000
+ 803a418:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803a41c:	f8d3 30ac 	ldr.w	r3, [r3, #172]	@ 0xac
+ 803a420:	4a8a      	ldr	r2, [pc, #552]	@ (803a64c <HAL_RCCEx_PeriphCLKConfig+0x5c8>)
+ 803a422:	430b      	orrs	r3, r1
+ 803a424:	6593      	str	r3, [r2, #88]	@ 0x58
+ 803a426:	e003      	b.n	803a430 <HAL_RCCEx_PeriphCLKConfig+0x3ac>
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+ 803a428:	f897 3127 	ldrb.w	r3, [r7, #295]	@ 0x127
+ 803a42c:	f887 3126 	strb.w	r3, [r7, #294]	@ 0x126
+  }
+#endif  /*SAI4*/
+
+#if defined(QUADSPI)
+  /*---------------------------- QSPI configuration -------------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI)
+ 803a430:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803a434:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 803a438:	f002 7300 	and.w	r3, r2, #33554432	@ 0x2000000
+ 803a43c:	f8c7 30f8 	str.w	r3, [r7, #248]	@ 0xf8
+ 803a440:	2300      	movs	r3, #0
+ 803a442:	f8c7 30fc 	str.w	r3, [r7, #252]	@ 0xfc
+ 803a446:	e9d7 123e 	ldrd	r1, r2, [r7, #248]	@ 0xf8
+ 803a44a:	460b      	mov	r3, r1
+ 803a44c:	4313      	orrs	r3, r2
+ 803a44e:	d03a      	beq.n	803a4c6 <HAL_RCCEx_PeriphCLKConfig+0x442>
+  {
+    switch (PeriphClkInit->QspiClockSelection)
+ 803a450:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803a454:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
+ 803a456:	2b30      	cmp	r3, #48	@ 0x30
+ 803a458:	d01f      	beq.n	803a49a <HAL_RCCEx_PeriphCLKConfig+0x416>
+ 803a45a:	2b30      	cmp	r3, #48	@ 0x30
+ 803a45c:	d819      	bhi.n	803a492 <HAL_RCCEx_PeriphCLKConfig+0x40e>
+ 803a45e:	2b20      	cmp	r3, #32
+ 803a460:	d00c      	beq.n	803a47c <HAL_RCCEx_PeriphCLKConfig+0x3f8>
+ 803a462:	2b20      	cmp	r3, #32
+ 803a464:	d815      	bhi.n	803a492 <HAL_RCCEx_PeriphCLKConfig+0x40e>
+ 803a466:	2b00      	cmp	r3, #0
+ 803a468:	d019      	beq.n	803a49e <HAL_RCCEx_PeriphCLKConfig+0x41a>
+ 803a46a:	2b10      	cmp	r3, #16
+ 803a46c:	d111      	bne.n	803a492 <HAL_RCCEx_PeriphCLKConfig+0x40e>
+    {
+      case RCC_QSPICLKSOURCE_PLL:      /* PLL is used as clock source for QSPI*/
+        /* Enable QSPI Clock output generated form System PLL . */
+        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+ 803a46e:	4b77      	ldr	r3, [pc, #476]	@ (803a64c <HAL_RCCEx_PeriphCLKConfig+0x5c8>)
+ 803a470:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 803a472:	4a76      	ldr	r2, [pc, #472]	@ (803a64c <HAL_RCCEx_PeriphCLKConfig+0x5c8>)
+ 803a474:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
+ 803a478:	62d3      	str	r3, [r2, #44]	@ 0x2c
+
+        /* QSPI clock source configuration done later after clock selection check */
+        break;
+ 803a47a:	e011      	b.n	803a4a0 <HAL_RCCEx_PeriphCLKConfig+0x41c>
+
+      case RCC_QSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for QSPI*/
+
+        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE);
+ 803a47c:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803a480:	3308      	adds	r3, #8
+ 803a482:	2102      	movs	r1, #2
+ 803a484:	4618      	mov	r0, r3
+ 803a486:	f002 f997 	bl	803c7b8 <RCCEx_PLL2_Config>
+ 803a48a:	4603      	mov	r3, r0
+ 803a48c:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+
+        /* QSPI clock source configuration done later after clock selection check */
+        break;
+ 803a490:	e006      	b.n	803a4a0 <HAL_RCCEx_PeriphCLKConfig+0x41c>
+      case RCC_QSPICLKSOURCE_D1HCLK:
+        /* Domain1 HCLK  clock selected as QSPI kernel peripheral clock */
+        break;
+
+      default:
+        ret = HAL_ERROR;
+ 803a492:	2301      	movs	r3, #1
+ 803a494:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+        break;
+ 803a498:	e002      	b.n	803a4a0 <HAL_RCCEx_PeriphCLKConfig+0x41c>
+        break;
+ 803a49a:	bf00      	nop
+ 803a49c:	e000      	b.n	803a4a0 <HAL_RCCEx_PeriphCLKConfig+0x41c>
+        break;
+ 803a49e:	bf00      	nop
+    }
+
+    if (ret == HAL_OK)
+ 803a4a0:	f897 3127 	ldrb.w	r3, [r7, #295]	@ 0x127
+ 803a4a4:	2b00      	cmp	r3, #0
+ 803a4a6:	d10a      	bne.n	803a4be <HAL_RCCEx_PeriphCLKConfig+0x43a>
+    {
+      /* Set the source of QSPI clock*/
+      __HAL_RCC_QSPI_CONFIG(PeriphClkInit->QspiClockSelection);
+ 803a4a8:	4b68      	ldr	r3, [pc, #416]	@ (803a64c <HAL_RCCEx_PeriphCLKConfig+0x5c8>)
+ 803a4aa:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
+ 803a4ac:	f023 0130 	bic.w	r1, r3, #48	@ 0x30
+ 803a4b0:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803a4b4:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
+ 803a4b6:	4a65      	ldr	r2, [pc, #404]	@ (803a64c <HAL_RCCEx_PeriphCLKConfig+0x5c8>)
+ 803a4b8:	430b      	orrs	r3, r1
+ 803a4ba:	64d3      	str	r3, [r2, #76]	@ 0x4c
+ 803a4bc:	e003      	b.n	803a4c6 <HAL_RCCEx_PeriphCLKConfig+0x442>
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+ 803a4be:	f897 3127 	ldrb.w	r3, [r7, #295]	@ 0x127
+ 803a4c2:	f887 3126 	strb.w	r3, [r7, #294]	@ 0x126
+    }
+  }
+#endif  /*OCTOSPI*/
+
+  /*---------------------------- SPI1/2/3 configuration -------------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI123) == RCC_PERIPHCLK_SPI123)
+ 803a4c6:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803a4ca:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 803a4ce:	f402 5380 	and.w	r3, r2, #4096	@ 0x1000
+ 803a4d2:	f8c7 30f0 	str.w	r3, [r7, #240]	@ 0xf0
+ 803a4d6:	2300      	movs	r3, #0
+ 803a4d8:	f8c7 30f4 	str.w	r3, [r7, #244]	@ 0xf4
+ 803a4dc:	e9d7 123c 	ldrd	r1, r2, [r7, #240]	@ 0xf0
+ 803a4e0:	460b      	mov	r3, r1
+ 803a4e2:	4313      	orrs	r3, r2
+ 803a4e4:	d051      	beq.n	803a58a <HAL_RCCEx_PeriphCLKConfig+0x506>
+  {
+    switch (PeriphClkInit->Spi123ClockSelection)
+ 803a4e6:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803a4ea:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
+ 803a4ec:	f5b3 4f80 	cmp.w	r3, #16384	@ 0x4000
+ 803a4f0:	d035      	beq.n	803a55e <HAL_RCCEx_PeriphCLKConfig+0x4da>
+ 803a4f2:	f5b3 4f80 	cmp.w	r3, #16384	@ 0x4000
+ 803a4f6:	d82e      	bhi.n	803a556 <HAL_RCCEx_PeriphCLKConfig+0x4d2>
+ 803a4f8:	f5b3 5f40 	cmp.w	r3, #12288	@ 0x3000
+ 803a4fc:	d031      	beq.n	803a562 <HAL_RCCEx_PeriphCLKConfig+0x4de>
+ 803a4fe:	f5b3 5f40 	cmp.w	r3, #12288	@ 0x3000
+ 803a502:	d828      	bhi.n	803a556 <HAL_RCCEx_PeriphCLKConfig+0x4d2>
+ 803a504:	f5b3 5f00 	cmp.w	r3, #8192	@ 0x2000
+ 803a508:	d01a      	beq.n	803a540 <HAL_RCCEx_PeriphCLKConfig+0x4bc>
+ 803a50a:	f5b3 5f00 	cmp.w	r3, #8192	@ 0x2000
+ 803a50e:	d822      	bhi.n	803a556 <HAL_RCCEx_PeriphCLKConfig+0x4d2>
+ 803a510:	2b00      	cmp	r3, #0
+ 803a512:	d003      	beq.n	803a51c <HAL_RCCEx_PeriphCLKConfig+0x498>
+ 803a514:	f5b3 5f80 	cmp.w	r3, #4096	@ 0x1000
+ 803a518:	d007      	beq.n	803a52a <HAL_RCCEx_PeriphCLKConfig+0x4a6>
+ 803a51a:	e01c      	b.n	803a556 <HAL_RCCEx_PeriphCLKConfig+0x4d2>
+    {
+      case RCC_SPI123CLKSOURCE_PLL:      /* PLL is used as clock source for SPI1/2/3 */
+        /* Enable SPI Clock output generated form System PLL . */
+        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+ 803a51c:	4b4b      	ldr	r3, [pc, #300]	@ (803a64c <HAL_RCCEx_PeriphCLKConfig+0x5c8>)
+ 803a51e:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 803a520:	4a4a      	ldr	r2, [pc, #296]	@ (803a64c <HAL_RCCEx_PeriphCLKConfig+0x5c8>)
+ 803a522:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
+ 803a526:	62d3      	str	r3, [r2, #44]	@ 0x2c
+
+        /* SPI1/2/3 clock source configuration done later after clock selection check */
+        break;
+ 803a528:	e01c      	b.n	803a564 <HAL_RCCEx_PeriphCLKConfig+0x4e0>
+
+      case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI1/2/3 */
+        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
+ 803a52a:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803a52e:	3308      	adds	r3, #8
+ 803a530:	2100      	movs	r1, #0
+ 803a532:	4618      	mov	r0, r3
+ 803a534:	f002 f940 	bl	803c7b8 <RCCEx_PLL2_Config>
+ 803a538:	4603      	mov	r3, r0
+ 803a53a:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+
+        /* SPI1/2/3 clock source configuration done later after clock selection check */
+        break;
+ 803a53e:	e011      	b.n	803a564 <HAL_RCCEx_PeriphCLKConfig+0x4e0>
+
+      case RCC_SPI123CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SPI1/2/3 */
+        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
+ 803a540:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803a544:	3328      	adds	r3, #40	@ 0x28
+ 803a546:	2100      	movs	r1, #0
+ 803a548:	4618      	mov	r0, r3
+ 803a54a:	f002 f9e7 	bl	803c91c <RCCEx_PLL3_Config>
+ 803a54e:	4603      	mov	r3, r0
+ 803a550:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+
+        /* SPI1/2/3 clock source configuration done later after clock selection check */
+        break;
+ 803a554:	e006      	b.n	803a564 <HAL_RCCEx_PeriphCLKConfig+0x4e0>
+        /* HSI, HSE, or CSI oscillator is used as source of SPI1/2/3 clock */
+        /* SPI1/2/3 clock source configuration done later after clock selection check */
+        break;
+
+      default:
+        ret = HAL_ERROR;
+ 803a556:	2301      	movs	r3, #1
+ 803a558:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+        break;
+ 803a55c:	e002      	b.n	803a564 <HAL_RCCEx_PeriphCLKConfig+0x4e0>
+        break;
+ 803a55e:	bf00      	nop
+ 803a560:	e000      	b.n	803a564 <HAL_RCCEx_PeriphCLKConfig+0x4e0>
+        break;
+ 803a562:	bf00      	nop
+    }
+
+    if (ret == HAL_OK)
+ 803a564:	f897 3127 	ldrb.w	r3, [r7, #295]	@ 0x127
+ 803a568:	2b00      	cmp	r3, #0
+ 803a56a:	d10a      	bne.n	803a582 <HAL_RCCEx_PeriphCLKConfig+0x4fe>
+    {
+      /* Set the source of SPI1/2/3 clock*/
+      __HAL_RCC_SPI123_CONFIG(PeriphClkInit->Spi123ClockSelection);
+ 803a56c:	4b37      	ldr	r3, [pc, #220]	@ (803a64c <HAL_RCCEx_PeriphCLKConfig+0x5c8>)
+ 803a56e:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
+ 803a570:	f423 41e0 	bic.w	r1, r3, #28672	@ 0x7000
+ 803a574:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803a578:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
+ 803a57a:	4a34      	ldr	r2, [pc, #208]	@ (803a64c <HAL_RCCEx_PeriphCLKConfig+0x5c8>)
+ 803a57c:	430b      	orrs	r3, r1
+ 803a57e:	6513      	str	r3, [r2, #80]	@ 0x50
+ 803a580:	e003      	b.n	803a58a <HAL_RCCEx_PeriphCLKConfig+0x506>
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+ 803a582:	f897 3127 	ldrb.w	r3, [r7, #295]	@ 0x127
+ 803a586:	f887 3126 	strb.w	r3, [r7, #294]	@ 0x126
+    }
+  }
+
+  /*---------------------------- SPI4/5 configuration -------------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45)
+ 803a58a:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803a58e:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 803a592:	f402 5300 	and.w	r3, r2, #8192	@ 0x2000
+ 803a596:	f8c7 30e8 	str.w	r3, [r7, #232]	@ 0xe8
+ 803a59a:	2300      	movs	r3, #0
+ 803a59c:	f8c7 30ec 	str.w	r3, [r7, #236]	@ 0xec
+ 803a5a0:	e9d7 123a 	ldrd	r1, r2, [r7, #232]	@ 0xe8
+ 803a5a4:	460b      	mov	r3, r1
+ 803a5a6:	4313      	orrs	r3, r2
+ 803a5a8:	d056      	beq.n	803a658 <HAL_RCCEx_PeriphCLKConfig+0x5d4>
+  {
+    switch (PeriphClkInit->Spi45ClockSelection)
+ 803a5aa:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803a5ae:	6e5b      	ldr	r3, [r3, #100]	@ 0x64
+ 803a5b0:	f5b3 2fa0 	cmp.w	r3, #327680	@ 0x50000
+ 803a5b4:	d033      	beq.n	803a61e <HAL_RCCEx_PeriphCLKConfig+0x59a>
+ 803a5b6:	f5b3 2fa0 	cmp.w	r3, #327680	@ 0x50000
+ 803a5ba:	d82c      	bhi.n	803a616 <HAL_RCCEx_PeriphCLKConfig+0x592>
+ 803a5bc:	f5b3 2f80 	cmp.w	r3, #262144	@ 0x40000
+ 803a5c0:	d02f      	beq.n	803a622 <HAL_RCCEx_PeriphCLKConfig+0x59e>
+ 803a5c2:	f5b3 2f80 	cmp.w	r3, #262144	@ 0x40000
+ 803a5c6:	d826      	bhi.n	803a616 <HAL_RCCEx_PeriphCLKConfig+0x592>
+ 803a5c8:	f5b3 3f40 	cmp.w	r3, #196608	@ 0x30000
+ 803a5cc:	d02b      	beq.n	803a626 <HAL_RCCEx_PeriphCLKConfig+0x5a2>
+ 803a5ce:	f5b3 3f40 	cmp.w	r3, #196608	@ 0x30000
+ 803a5d2:	d820      	bhi.n	803a616 <HAL_RCCEx_PeriphCLKConfig+0x592>
+ 803a5d4:	f5b3 3f00 	cmp.w	r3, #131072	@ 0x20000
+ 803a5d8:	d012      	beq.n	803a600 <HAL_RCCEx_PeriphCLKConfig+0x57c>
+ 803a5da:	f5b3 3f00 	cmp.w	r3, #131072	@ 0x20000
+ 803a5de:	d81a      	bhi.n	803a616 <HAL_RCCEx_PeriphCLKConfig+0x592>
+ 803a5e0:	2b00      	cmp	r3, #0
+ 803a5e2:	d022      	beq.n	803a62a <HAL_RCCEx_PeriphCLKConfig+0x5a6>
+ 803a5e4:	f5b3 3f80 	cmp.w	r3, #65536	@ 0x10000
+ 803a5e8:	d115      	bne.n	803a616 <HAL_RCCEx_PeriphCLKConfig+0x592>
+        /* SPI4/5 clock source configuration done later after clock selection check */
+        break;
+
+      case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI4/5 */
+
+        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
+ 803a5ea:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803a5ee:	3308      	adds	r3, #8
+ 803a5f0:	2101      	movs	r1, #1
+ 803a5f2:	4618      	mov	r0, r3
+ 803a5f4:	f002 f8e0 	bl	803c7b8 <RCCEx_PLL2_Config>
+ 803a5f8:	4603      	mov	r3, r0
+ 803a5fa:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+
+        /* SPI4/5 clock source configuration done later after clock selection check */
+        break;
+ 803a5fe:	e015      	b.n	803a62c <HAL_RCCEx_PeriphCLKConfig+0x5a8>
+      case RCC_SPI45CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SPI4/5 */
+        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE);
+ 803a600:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803a604:	3328      	adds	r3, #40	@ 0x28
+ 803a606:	2101      	movs	r1, #1
+ 803a608:	4618      	mov	r0, r3
+ 803a60a:	f002 f987 	bl	803c91c <RCCEx_PLL3_Config>
+ 803a60e:	4603      	mov	r3, r0
+ 803a610:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+        /* SPI4/5 clock source configuration done later after clock selection check */
+        break;
+ 803a614:	e00a      	b.n	803a62c <HAL_RCCEx_PeriphCLKConfig+0x5a8>
+        /* HSE,  oscillator is used as source of SPI4/5 clock */
+        /* SPI4/5 clock source configuration done later after clock selection check */
+        break;
+
+      default:
+        ret = HAL_ERROR;
+ 803a616:	2301      	movs	r3, #1
+ 803a618:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+        break;
+ 803a61c:	e006      	b.n	803a62c <HAL_RCCEx_PeriphCLKConfig+0x5a8>
+        break;
+ 803a61e:	bf00      	nop
+ 803a620:	e004      	b.n	803a62c <HAL_RCCEx_PeriphCLKConfig+0x5a8>
+        break;
+ 803a622:	bf00      	nop
+ 803a624:	e002      	b.n	803a62c <HAL_RCCEx_PeriphCLKConfig+0x5a8>
+        break;
+ 803a626:	bf00      	nop
+ 803a628:	e000      	b.n	803a62c <HAL_RCCEx_PeriphCLKConfig+0x5a8>
+        break;
+ 803a62a:	bf00      	nop
+    }
+
+    if (ret == HAL_OK)
+ 803a62c:	f897 3127 	ldrb.w	r3, [r7, #295]	@ 0x127
+ 803a630:	2b00      	cmp	r3, #0
+ 803a632:	d10d      	bne.n	803a650 <HAL_RCCEx_PeriphCLKConfig+0x5cc>
+    {
+      /* Set the source of SPI4/5 clock*/
+      __HAL_RCC_SPI45_CONFIG(PeriphClkInit->Spi45ClockSelection);
+ 803a634:	4b05      	ldr	r3, [pc, #20]	@ (803a64c <HAL_RCCEx_PeriphCLKConfig+0x5c8>)
+ 803a636:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
+ 803a638:	f423 21e0 	bic.w	r1, r3, #458752	@ 0x70000
+ 803a63c:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803a640:	6e5b      	ldr	r3, [r3, #100]	@ 0x64
+ 803a642:	4a02      	ldr	r2, [pc, #8]	@ (803a64c <HAL_RCCEx_PeriphCLKConfig+0x5c8>)
+ 803a644:	430b      	orrs	r3, r1
+ 803a646:	6513      	str	r3, [r2, #80]	@ 0x50
+ 803a648:	e006      	b.n	803a658 <HAL_RCCEx_PeriphCLKConfig+0x5d4>
+ 803a64a:	bf00      	nop
+ 803a64c:	58024400 	.word	0x58024400
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+ 803a650:	f897 3127 	ldrb.w	r3, [r7, #295]	@ 0x127
+ 803a654:	f887 3126 	strb.w	r3, [r7, #294]	@ 0x126
+    }
+  }
+
+  /*---------------------------- SPI6 configuration -------------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6)
+ 803a658:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803a65c:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 803a660:	f402 4380 	and.w	r3, r2, #16384	@ 0x4000
+ 803a664:	f8c7 30e0 	str.w	r3, [r7, #224]	@ 0xe0
+ 803a668:	2300      	movs	r3, #0
+ 803a66a:	f8c7 30e4 	str.w	r3, [r7, #228]	@ 0xe4
+ 803a66e:	e9d7 1238 	ldrd	r1, r2, [r7, #224]	@ 0xe0
+ 803a672:	460b      	mov	r3, r1
+ 803a674:	4313      	orrs	r3, r2
+ 803a676:	d055      	beq.n	803a724 <HAL_RCCEx_PeriphCLKConfig+0x6a0>
+  {
+    switch (PeriphClkInit->Spi6ClockSelection)
+ 803a678:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803a67c:	f8d3 30b0 	ldr.w	r3, [r3, #176]	@ 0xb0
+ 803a680:	f1b3 4fa0 	cmp.w	r3, #1342177280	@ 0x50000000
+ 803a684:	d033      	beq.n	803a6ee <HAL_RCCEx_PeriphCLKConfig+0x66a>
+ 803a686:	f1b3 4fa0 	cmp.w	r3, #1342177280	@ 0x50000000
+ 803a68a:	d82c      	bhi.n	803a6e6 <HAL_RCCEx_PeriphCLKConfig+0x662>
+ 803a68c:	f1b3 4f80 	cmp.w	r3, #1073741824	@ 0x40000000
+ 803a690:	d02f      	beq.n	803a6f2 <HAL_RCCEx_PeriphCLKConfig+0x66e>
+ 803a692:	f1b3 4f80 	cmp.w	r3, #1073741824	@ 0x40000000
+ 803a696:	d826      	bhi.n	803a6e6 <HAL_RCCEx_PeriphCLKConfig+0x662>
+ 803a698:	f1b3 5f40 	cmp.w	r3, #805306368	@ 0x30000000
+ 803a69c:	d02b      	beq.n	803a6f6 <HAL_RCCEx_PeriphCLKConfig+0x672>
+ 803a69e:	f1b3 5f40 	cmp.w	r3, #805306368	@ 0x30000000
+ 803a6a2:	d820      	bhi.n	803a6e6 <HAL_RCCEx_PeriphCLKConfig+0x662>
+ 803a6a4:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
+ 803a6a8:	d012      	beq.n	803a6d0 <HAL_RCCEx_PeriphCLKConfig+0x64c>
+ 803a6aa:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
+ 803a6ae:	d81a      	bhi.n	803a6e6 <HAL_RCCEx_PeriphCLKConfig+0x662>
+ 803a6b0:	2b00      	cmp	r3, #0
+ 803a6b2:	d022      	beq.n	803a6fa <HAL_RCCEx_PeriphCLKConfig+0x676>
+ 803a6b4:	f1b3 5f80 	cmp.w	r3, #268435456	@ 0x10000000
+ 803a6b8:	d115      	bne.n	803a6e6 <HAL_RCCEx_PeriphCLKConfig+0x662>
+        /* SPI6 clock source configuration done later after clock selection check */
+        break;
+
+      case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI6*/
+
+        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
+ 803a6ba:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803a6be:	3308      	adds	r3, #8
+ 803a6c0:	2101      	movs	r1, #1
+ 803a6c2:	4618      	mov	r0, r3
+ 803a6c4:	f002 f878 	bl	803c7b8 <RCCEx_PLL2_Config>
+ 803a6c8:	4603      	mov	r3, r0
+ 803a6ca:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+
+        /* SPI6 clock source configuration done later after clock selection check */
+        break;
+ 803a6ce:	e015      	b.n	803a6fc <HAL_RCCEx_PeriphCLKConfig+0x678>
+      case RCC_SPI6CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SPI6*/
+        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE);
+ 803a6d0:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803a6d4:	3328      	adds	r3, #40	@ 0x28
+ 803a6d6:	2101      	movs	r1, #1
+ 803a6d8:	4618      	mov	r0, r3
+ 803a6da:	f002 f91f 	bl	803c91c <RCCEx_PLL3_Config>
+ 803a6de:	4603      	mov	r3, r0
+ 803a6e0:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+        /* SPI6 clock source configuration done later after clock selection check */
+        break;
+ 803a6e4:	e00a      	b.n	803a6fc <HAL_RCCEx_PeriphCLKConfig+0x678>
+        /* SPI6 clock source configuration done later after clock selection check */
+        break;
+#endif
+
+      default:
+        ret = HAL_ERROR;
+ 803a6e6:	2301      	movs	r3, #1
+ 803a6e8:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+        break;
+ 803a6ec:	e006      	b.n	803a6fc <HAL_RCCEx_PeriphCLKConfig+0x678>
+        break;
+ 803a6ee:	bf00      	nop
+ 803a6f0:	e004      	b.n	803a6fc <HAL_RCCEx_PeriphCLKConfig+0x678>
+        break;
+ 803a6f2:	bf00      	nop
+ 803a6f4:	e002      	b.n	803a6fc <HAL_RCCEx_PeriphCLKConfig+0x678>
+        break;
+ 803a6f6:	bf00      	nop
+ 803a6f8:	e000      	b.n	803a6fc <HAL_RCCEx_PeriphCLKConfig+0x678>
+        break;
+ 803a6fa:	bf00      	nop
+    }
+
+    if (ret == HAL_OK)
+ 803a6fc:	f897 3127 	ldrb.w	r3, [r7, #295]	@ 0x127
+ 803a700:	2b00      	cmp	r3, #0
+ 803a702:	d10b      	bne.n	803a71c <HAL_RCCEx_PeriphCLKConfig+0x698>
+    {
+      /* Set the source of SPI6 clock*/
+      __HAL_RCC_SPI6_CONFIG(PeriphClkInit->Spi6ClockSelection);
+ 803a704:	4ba3      	ldr	r3, [pc, #652]	@ (803a994 <HAL_RCCEx_PeriphCLKConfig+0x910>)
+ 803a706:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
+ 803a708:	f023 41e0 	bic.w	r1, r3, #1879048192	@ 0x70000000
+ 803a70c:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803a710:	f8d3 30b0 	ldr.w	r3, [r3, #176]	@ 0xb0
+ 803a714:	4a9f      	ldr	r2, [pc, #636]	@ (803a994 <HAL_RCCEx_PeriphCLKConfig+0x910>)
+ 803a716:	430b      	orrs	r3, r1
+ 803a718:	6593      	str	r3, [r2, #88]	@ 0x58
+ 803a71a:	e003      	b.n	803a724 <HAL_RCCEx_PeriphCLKConfig+0x6a0>
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+ 803a71c:	f897 3127 	ldrb.w	r3, [r7, #295]	@ 0x127
+ 803a720:	f887 3126 	strb.w	r3, [r7, #294]	@ 0x126
+  }
+#endif /*DSI*/
+
+#if defined(FDCAN1) || defined(FDCAN2)
+  /*---------------------------- FDCAN configuration -------------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN)
+ 803a724:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803a728:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 803a72c:	f402 4300 	and.w	r3, r2, #32768	@ 0x8000
+ 803a730:	f8c7 30d8 	str.w	r3, [r7, #216]	@ 0xd8
+ 803a734:	2300      	movs	r3, #0
+ 803a736:	f8c7 30dc 	str.w	r3, [r7, #220]	@ 0xdc
+ 803a73a:	e9d7 1236 	ldrd	r1, r2, [r7, #216]	@ 0xd8
+ 803a73e:	460b      	mov	r3, r1
+ 803a740:	4313      	orrs	r3, r2
+ 803a742:	d037      	beq.n	803a7b4 <HAL_RCCEx_PeriphCLKConfig+0x730>
+  {
+    switch (PeriphClkInit->FdcanClockSelection)
+ 803a744:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803a748:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
+ 803a74a:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
+ 803a74e:	d00e      	beq.n	803a76e <HAL_RCCEx_PeriphCLKConfig+0x6ea>
+ 803a750:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
+ 803a754:	d816      	bhi.n	803a784 <HAL_RCCEx_PeriphCLKConfig+0x700>
+ 803a756:	2b00      	cmp	r3, #0
+ 803a758:	d018      	beq.n	803a78c <HAL_RCCEx_PeriphCLKConfig+0x708>
+ 803a75a:	f1b3 5f80 	cmp.w	r3, #268435456	@ 0x10000000
+ 803a75e:	d111      	bne.n	803a784 <HAL_RCCEx_PeriphCLKConfig+0x700>
+    {
+      case RCC_FDCANCLKSOURCE_PLL:      /* PLL is used as clock source for FDCAN*/
+        /* Enable FDCAN Clock output generated form System PLL . */
+        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+ 803a760:	4b8c      	ldr	r3, [pc, #560]	@ (803a994 <HAL_RCCEx_PeriphCLKConfig+0x910>)
+ 803a762:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 803a764:	4a8b      	ldr	r2, [pc, #556]	@ (803a994 <HAL_RCCEx_PeriphCLKConfig+0x910>)
+ 803a766:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
+ 803a76a:	62d3      	str	r3, [r2, #44]	@ 0x2c
+
+        /* FDCAN clock source configuration done later after clock selection check */
+        break;
+ 803a76c:	e00f      	b.n	803a78e <HAL_RCCEx_PeriphCLKConfig+0x70a>
+
+      case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is used as clock source for FDCAN*/
+
+        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
+ 803a76e:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803a772:	3308      	adds	r3, #8
+ 803a774:	2101      	movs	r1, #1
+ 803a776:	4618      	mov	r0, r3
+ 803a778:	f002 f81e 	bl	803c7b8 <RCCEx_PLL2_Config>
+ 803a77c:	4603      	mov	r3, r0
+ 803a77e:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+
+        /* FDCAN clock source configuration done later after clock selection check */
+        break;
+ 803a782:	e004      	b.n	803a78e <HAL_RCCEx_PeriphCLKConfig+0x70a>
+        /* HSE is used as clock source for FDCAN*/
+        /* FDCAN clock source configuration done later after clock selection check */
+        break;
+
+      default:
+        ret = HAL_ERROR;
+ 803a784:	2301      	movs	r3, #1
+ 803a786:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+        break;
+ 803a78a:	e000      	b.n	803a78e <HAL_RCCEx_PeriphCLKConfig+0x70a>
+        break;
+ 803a78c:	bf00      	nop
+    }
+
+    if (ret == HAL_OK)
+ 803a78e:	f897 3127 	ldrb.w	r3, [r7, #295]	@ 0x127
+ 803a792:	2b00      	cmp	r3, #0
+ 803a794:	d10a      	bne.n	803a7ac <HAL_RCCEx_PeriphCLKConfig+0x728>
+    {
+      /* Set the source of FDCAN clock*/
+      __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection);
+ 803a796:	4b7f      	ldr	r3, [pc, #508]	@ (803a994 <HAL_RCCEx_PeriphCLKConfig+0x910>)
+ 803a798:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
+ 803a79a:	f023 5140 	bic.w	r1, r3, #805306368	@ 0x30000000
+ 803a79e:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803a7a2:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
+ 803a7a4:	4a7b      	ldr	r2, [pc, #492]	@ (803a994 <HAL_RCCEx_PeriphCLKConfig+0x910>)
+ 803a7a6:	430b      	orrs	r3, r1
+ 803a7a8:	6513      	str	r3, [r2, #80]	@ 0x50
+ 803a7aa:	e003      	b.n	803a7b4 <HAL_RCCEx_PeriphCLKConfig+0x730>
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+ 803a7ac:	f897 3127 	ldrb.w	r3, [r7, #295]	@ 0x127
+ 803a7b0:	f887 3126 	strb.w	r3, [r7, #294]	@ 0x126
+    }
+  }
+#endif /*FDCAN1 || FDCAN2*/
+
+  /*---------------------------- FMC configuration -------------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC)
+ 803a7b4:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803a7b8:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 803a7bc:	f002 7380 	and.w	r3, r2, #16777216	@ 0x1000000
+ 803a7c0:	f8c7 30d0 	str.w	r3, [r7, #208]	@ 0xd0
+ 803a7c4:	2300      	movs	r3, #0
+ 803a7c6:	f8c7 30d4 	str.w	r3, [r7, #212]	@ 0xd4
+ 803a7ca:	e9d7 1234 	ldrd	r1, r2, [r7, #208]	@ 0xd0
+ 803a7ce:	460b      	mov	r3, r1
+ 803a7d0:	4313      	orrs	r3, r2
+ 803a7d2:	d039      	beq.n	803a848 <HAL_RCCEx_PeriphCLKConfig+0x7c4>
+  {
+    switch (PeriphClkInit->FmcClockSelection)
+ 803a7d4:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803a7d8:	6c9b      	ldr	r3, [r3, #72]	@ 0x48
+ 803a7da:	2b03      	cmp	r3, #3
+ 803a7dc:	d81c      	bhi.n	803a818 <HAL_RCCEx_PeriphCLKConfig+0x794>
+ 803a7de:	a201      	add	r2, pc, #4	@ (adr r2, 803a7e4 <HAL_RCCEx_PeriphCLKConfig+0x760>)
+ 803a7e0:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 803a7e4:	0803a821 	.word	0x0803a821
+ 803a7e8:	0803a7f5 	.word	0x0803a7f5
+ 803a7ec:	0803a803 	.word	0x0803a803
+ 803a7f0:	0803a821 	.word	0x0803a821
+    {
+      case RCC_FMCCLKSOURCE_PLL:      /* PLL is used as clock source for FMC*/
+        /* Enable FMC Clock output generated form System PLL . */
+        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+ 803a7f4:	4b67      	ldr	r3, [pc, #412]	@ (803a994 <HAL_RCCEx_PeriphCLKConfig+0x910>)
+ 803a7f6:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 803a7f8:	4a66      	ldr	r2, [pc, #408]	@ (803a994 <HAL_RCCEx_PeriphCLKConfig+0x910>)
+ 803a7fa:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
+ 803a7fe:	62d3      	str	r3, [r2, #44]	@ 0x2c
+
+        /* FMC clock source configuration done later after clock selection check */
+        break;
+ 803a800:	e00f      	b.n	803a822 <HAL_RCCEx_PeriphCLKConfig+0x79e>
+
+      case RCC_FMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for FMC*/
+
+        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE);
+ 803a802:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803a806:	3308      	adds	r3, #8
+ 803a808:	2102      	movs	r1, #2
+ 803a80a:	4618      	mov	r0, r3
+ 803a80c:	f001 ffd4 	bl	803c7b8 <RCCEx_PLL2_Config>
+ 803a810:	4603      	mov	r3, r0
+ 803a812:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+
+        /* FMC clock source configuration done later after clock selection check */
+        break;
+ 803a816:	e004      	b.n	803a822 <HAL_RCCEx_PeriphCLKConfig+0x79e>
+      case RCC_FMCCLKSOURCE_HCLK:
+        /* D1/CD HCLK  clock selected as FMC kernel peripheral clock */
+        break;
+
+      default:
+        ret = HAL_ERROR;
+ 803a818:	2301      	movs	r3, #1
+ 803a81a:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+        break;
+ 803a81e:	e000      	b.n	803a822 <HAL_RCCEx_PeriphCLKConfig+0x79e>
+        break;
+ 803a820:	bf00      	nop
+    }
+
+    if (ret == HAL_OK)
+ 803a822:	f897 3127 	ldrb.w	r3, [r7, #295]	@ 0x127
+ 803a826:	2b00      	cmp	r3, #0
+ 803a828:	d10a      	bne.n	803a840 <HAL_RCCEx_PeriphCLKConfig+0x7bc>
+    {
+      /* Set the source of FMC clock*/
+      __HAL_RCC_FMC_CONFIG(PeriphClkInit->FmcClockSelection);
+ 803a82a:	4b5a      	ldr	r3, [pc, #360]	@ (803a994 <HAL_RCCEx_PeriphCLKConfig+0x910>)
+ 803a82c:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
+ 803a82e:	f023 0103 	bic.w	r1, r3, #3
+ 803a832:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803a836:	6c9b      	ldr	r3, [r3, #72]	@ 0x48
+ 803a838:	4a56      	ldr	r2, [pc, #344]	@ (803a994 <HAL_RCCEx_PeriphCLKConfig+0x910>)
+ 803a83a:	430b      	orrs	r3, r1
+ 803a83c:	64d3      	str	r3, [r2, #76]	@ 0x4c
+ 803a83e:	e003      	b.n	803a848 <HAL_RCCEx_PeriphCLKConfig+0x7c4>
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+ 803a840:	f897 3127 	ldrb.w	r3, [r7, #295]	@ 0x127
+ 803a844:	f887 3126 	strb.w	r3, [r7, #294]	@ 0x126
+    }
+  }
+
+  /*---------------------------- RTC configuration -------------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
+ 803a848:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803a84c:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 803a850:	f402 0380 	and.w	r3, r2, #4194304	@ 0x400000
+ 803a854:	f8c7 30c8 	str.w	r3, [r7, #200]	@ 0xc8
+ 803a858:	2300      	movs	r3, #0
+ 803a85a:	f8c7 30cc 	str.w	r3, [r7, #204]	@ 0xcc
+ 803a85e:	e9d7 1232 	ldrd	r1, r2, [r7, #200]	@ 0xc8
+ 803a862:	460b      	mov	r3, r1
+ 803a864:	4313      	orrs	r3, r2
+ 803a866:	f000 809f 	beq.w	803a9a8 <HAL_RCCEx_PeriphCLKConfig+0x924>
+  {
+    /* check for RTC Parameters used to output RTCCLK */
+    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
+
+    /* Enable write access to Backup domain */
+    SET_BIT(PWR->CR1, PWR_CR1_DBP);
+ 803a86a:	4b4b      	ldr	r3, [pc, #300]	@ (803a998 <HAL_RCCEx_PeriphCLKConfig+0x914>)
+ 803a86c:	681b      	ldr	r3, [r3, #0]
+ 803a86e:	4a4a      	ldr	r2, [pc, #296]	@ (803a998 <HAL_RCCEx_PeriphCLKConfig+0x914>)
+ 803a870:	f443 7380 	orr.w	r3, r3, #256	@ 0x100
+ 803a874:	6013      	str	r3, [r2, #0]
+
+    /* Wait for Backup domain Write protection disable */
+    tickstart = HAL_GetTick();
+ 803a876:	f7f7 f85b 	bl	8031930 <HAL_GetTick>
+ 803a87a:	f8c7 0120 	str.w	r0, [r7, #288]	@ 0x120
+
+    while ((PWR->CR1 & PWR_CR1_DBP) == 0U)
+ 803a87e:	e00b      	b.n	803a898 <HAL_RCCEx_PeriphCLKConfig+0x814>
+    {
+      if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
+ 803a880:	f7f7 f856 	bl	8031930 <HAL_GetTick>
+ 803a884:	4602      	mov	r2, r0
+ 803a886:	f8d7 3120 	ldr.w	r3, [r7, #288]	@ 0x120
+ 803a88a:	1ad3      	subs	r3, r2, r3
+ 803a88c:	2b64      	cmp	r3, #100	@ 0x64
+ 803a88e:	d903      	bls.n	803a898 <HAL_RCCEx_PeriphCLKConfig+0x814>
+      {
+        ret = HAL_TIMEOUT;
+ 803a890:	2303      	movs	r3, #3
+ 803a892:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+        break;
+ 803a896:	e005      	b.n	803a8a4 <HAL_RCCEx_PeriphCLKConfig+0x820>
+    while ((PWR->CR1 & PWR_CR1_DBP) == 0U)
+ 803a898:	4b3f      	ldr	r3, [pc, #252]	@ (803a998 <HAL_RCCEx_PeriphCLKConfig+0x914>)
+ 803a89a:	681b      	ldr	r3, [r3, #0]
+ 803a89c:	f403 7380 	and.w	r3, r3, #256	@ 0x100
+ 803a8a0:	2b00      	cmp	r3, #0
+ 803a8a2:	d0ed      	beq.n	803a880 <HAL_RCCEx_PeriphCLKConfig+0x7fc>
+      }
+    }
+
+    if (ret == HAL_OK)
+ 803a8a4:	f897 3127 	ldrb.w	r3, [r7, #295]	@ 0x127
+ 803a8a8:	2b00      	cmp	r3, #0
+ 803a8aa:	d179      	bne.n	803a9a0 <HAL_RCCEx_PeriphCLKConfig+0x91c>
+    {
+      /* Reset the Backup domain only if the RTC Clock source selection is modified */
+      if ((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
+ 803a8ac:	4b39      	ldr	r3, [pc, #228]	@ (803a994 <HAL_RCCEx_PeriphCLKConfig+0x910>)
+ 803a8ae:	6f1a      	ldr	r2, [r3, #112]	@ 0x70
+ 803a8b0:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803a8b4:	f8d3 30b4 	ldr.w	r3, [r3, #180]	@ 0xb4
+ 803a8b8:	4053      	eors	r3, r2
+ 803a8ba:	f403 7340 	and.w	r3, r3, #768	@ 0x300
+ 803a8be:	2b00      	cmp	r3, #0
+ 803a8c0:	d015      	beq.n	803a8ee <HAL_RCCEx_PeriphCLKConfig+0x86a>
+      {
+        /* Store the content of BDCR register before the reset of Backup Domain */
+        tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
+ 803a8c2:	4b34      	ldr	r3, [pc, #208]	@ (803a994 <HAL_RCCEx_PeriphCLKConfig+0x910>)
+ 803a8c4:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
+ 803a8c6:	f423 7340 	bic.w	r3, r3, #768	@ 0x300
+ 803a8ca:	f8c7 311c 	str.w	r3, [r7, #284]	@ 0x11c
+        /* RTC Clock selection can be changed only if the Backup Domain is reset */
+        __HAL_RCC_BACKUPRESET_FORCE();
+ 803a8ce:	4b31      	ldr	r3, [pc, #196]	@ (803a994 <HAL_RCCEx_PeriphCLKConfig+0x910>)
+ 803a8d0:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
+ 803a8d2:	4a30      	ldr	r2, [pc, #192]	@ (803a994 <HAL_RCCEx_PeriphCLKConfig+0x910>)
+ 803a8d4:	f443 3380 	orr.w	r3, r3, #65536	@ 0x10000
+ 803a8d8:	6713      	str	r3, [r2, #112]	@ 0x70
+        __HAL_RCC_BACKUPRESET_RELEASE();
+ 803a8da:	4b2e      	ldr	r3, [pc, #184]	@ (803a994 <HAL_RCCEx_PeriphCLKConfig+0x910>)
+ 803a8dc:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
+ 803a8de:	4a2d      	ldr	r2, [pc, #180]	@ (803a994 <HAL_RCCEx_PeriphCLKConfig+0x910>)
+ 803a8e0:	f423 3380 	bic.w	r3, r3, #65536	@ 0x10000
+ 803a8e4:	6713      	str	r3, [r2, #112]	@ 0x70
+        /* Restore the Content of BDCR register */
+        RCC->BDCR = tmpreg;
+ 803a8e6:	4a2b      	ldr	r2, [pc, #172]	@ (803a994 <HAL_RCCEx_PeriphCLKConfig+0x910>)
+ 803a8e8:	f8d7 311c 	ldr.w	r3, [r7, #284]	@ 0x11c
+ 803a8ec:	6713      	str	r3, [r2, #112]	@ 0x70
+      }
+
+      /* If LSE is selected as RTC clock source (and enabled prior to Backup Domain reset), wait for LSE reactivation */
+      if (PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)
+ 803a8ee:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803a8f2:	f8d3 30b4 	ldr.w	r3, [r3, #180]	@ 0xb4
+ 803a8f6:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
+ 803a8fa:	d118      	bne.n	803a92e <HAL_RCCEx_PeriphCLKConfig+0x8aa>
+      {
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+ 803a8fc:	f7f7 f818 	bl	8031930 <HAL_GetTick>
+ 803a900:	f8c7 0120 	str.w	r0, [r7, #288]	@ 0x120
+
+        /* Wait till LSE is ready */
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
+ 803a904:	e00d      	b.n	803a922 <HAL_RCCEx_PeriphCLKConfig+0x89e>
+        {
+          if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
+ 803a906:	f7f7 f813 	bl	8031930 <HAL_GetTick>
+ 803a90a:	4602      	mov	r2, r0
+ 803a90c:	f8d7 3120 	ldr.w	r3, [r7, #288]	@ 0x120
+ 803a910:	1ad2      	subs	r2, r2, r3
+ 803a912:	f241 3388 	movw	r3, #5000	@ 0x1388
+ 803a916:	429a      	cmp	r2, r3
+ 803a918:	d903      	bls.n	803a922 <HAL_RCCEx_PeriphCLKConfig+0x89e>
+          {
+            ret = HAL_TIMEOUT;
+ 803a91a:	2303      	movs	r3, #3
+ 803a91c:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+            break;
+ 803a920:	e005      	b.n	803a92e <HAL_RCCEx_PeriphCLKConfig+0x8aa>
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
+ 803a922:	4b1c      	ldr	r3, [pc, #112]	@ (803a994 <HAL_RCCEx_PeriphCLKConfig+0x910>)
+ 803a924:	6f1b      	ldr	r3, [r3, #112]	@ 0x70
+ 803a926:	f003 0302 	and.w	r3, r3, #2
+ 803a92a:	2b00      	cmp	r3, #0
+ 803a92c:	d0eb      	beq.n	803a906 <HAL_RCCEx_PeriphCLKConfig+0x882>
+          }
+        }
+      }
+
+      if (ret == HAL_OK)
+ 803a92e:	f897 3127 	ldrb.w	r3, [r7, #295]	@ 0x127
+ 803a932:	2b00      	cmp	r3, #0
+ 803a934:	d129      	bne.n	803a98a <HAL_RCCEx_PeriphCLKConfig+0x906>
+      {
+        __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
+ 803a936:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803a93a:	f8d3 30b4 	ldr.w	r3, [r3, #180]	@ 0xb4
+ 803a93e:	f403 7340 	and.w	r3, r3, #768	@ 0x300
+ 803a942:	f5b3 7f40 	cmp.w	r3, #768	@ 0x300
+ 803a946:	d10e      	bne.n	803a966 <HAL_RCCEx_PeriphCLKConfig+0x8e2>
+ 803a948:	4b12      	ldr	r3, [pc, #72]	@ (803a994 <HAL_RCCEx_PeriphCLKConfig+0x910>)
+ 803a94a:	691b      	ldr	r3, [r3, #16]
+ 803a94c:	f423 517c 	bic.w	r1, r3, #16128	@ 0x3f00
+ 803a950:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803a954:	f8d3 30b4 	ldr.w	r3, [r3, #180]	@ 0xb4
+ 803a958:	091a      	lsrs	r2, r3, #4
+ 803a95a:	4b10      	ldr	r3, [pc, #64]	@ (803a99c <HAL_RCCEx_PeriphCLKConfig+0x918>)
+ 803a95c:	4013      	ands	r3, r2
+ 803a95e:	4a0d      	ldr	r2, [pc, #52]	@ (803a994 <HAL_RCCEx_PeriphCLKConfig+0x910>)
+ 803a960:	430b      	orrs	r3, r1
+ 803a962:	6113      	str	r3, [r2, #16]
+ 803a964:	e005      	b.n	803a972 <HAL_RCCEx_PeriphCLKConfig+0x8ee>
+ 803a966:	4b0b      	ldr	r3, [pc, #44]	@ (803a994 <HAL_RCCEx_PeriphCLKConfig+0x910>)
+ 803a968:	691b      	ldr	r3, [r3, #16]
+ 803a96a:	4a0a      	ldr	r2, [pc, #40]	@ (803a994 <HAL_RCCEx_PeriphCLKConfig+0x910>)
+ 803a96c:	f423 537c 	bic.w	r3, r3, #16128	@ 0x3f00
+ 803a970:	6113      	str	r3, [r2, #16]
+ 803a972:	4b08      	ldr	r3, [pc, #32]	@ (803a994 <HAL_RCCEx_PeriphCLKConfig+0x910>)
+ 803a974:	6f19      	ldr	r1, [r3, #112]	@ 0x70
+ 803a976:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803a97a:	f8d3 30b4 	ldr.w	r3, [r3, #180]	@ 0xb4
+ 803a97e:	f3c3 030b 	ubfx	r3, r3, #0, #12
+ 803a982:	4a04      	ldr	r2, [pc, #16]	@ (803a994 <HAL_RCCEx_PeriphCLKConfig+0x910>)
+ 803a984:	430b      	orrs	r3, r1
+ 803a986:	6713      	str	r3, [r2, #112]	@ 0x70
+ 803a988:	e00e      	b.n	803a9a8 <HAL_RCCEx_PeriphCLKConfig+0x924>
+      }
+      else
+      {
+        /* set overall return value */
+        status = ret;
+ 803a98a:	f897 3127 	ldrb.w	r3, [r7, #295]	@ 0x127
+ 803a98e:	f887 3126 	strb.w	r3, [r7, #294]	@ 0x126
+ 803a992:	e009      	b.n	803a9a8 <HAL_RCCEx_PeriphCLKConfig+0x924>
+ 803a994:	58024400 	.word	0x58024400
+ 803a998:	58024800 	.word	0x58024800
+ 803a99c:	00ffffcf 	.word	0x00ffffcf
+      }
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+ 803a9a0:	f897 3127 	ldrb.w	r3, [r7, #295]	@ 0x127
+ 803a9a4:	f887 3126 	strb.w	r3, [r7, #294]	@ 0x126
+    }
+  }
+
+
+  /*-------------------------- USART1/6 configuration --------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART16) == RCC_PERIPHCLK_USART16)
+ 803a9a8:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803a9ac:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 803a9b0:	f002 0301 	and.w	r3, r2, #1
+ 803a9b4:	f8c7 30c0 	str.w	r3, [r7, #192]	@ 0xc0
+ 803a9b8:	2300      	movs	r3, #0
+ 803a9ba:	f8c7 30c4 	str.w	r3, [r7, #196]	@ 0xc4
+ 803a9be:	e9d7 1230 	ldrd	r1, r2, [r7, #192]	@ 0xc0
+ 803a9c2:	460b      	mov	r3, r1
+ 803a9c4:	4313      	orrs	r3, r2
+ 803a9c6:	f000 8089 	beq.w	803aadc <HAL_RCCEx_PeriphCLKConfig+0xa58>
+  {
+    switch (PeriphClkInit->Usart16ClockSelection)
+ 803a9ca:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803a9ce:	6fdb      	ldr	r3, [r3, #124]	@ 0x7c
+ 803a9d0:	2b28      	cmp	r3, #40	@ 0x28
+ 803a9d2:	d86b      	bhi.n	803aaac <HAL_RCCEx_PeriphCLKConfig+0xa28>
+ 803a9d4:	a201      	add	r2, pc, #4	@ (adr r2, 803a9dc <HAL_RCCEx_PeriphCLKConfig+0x958>)
+ 803a9d6:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 803a9da:	bf00      	nop
+ 803a9dc:	0803aab5 	.word	0x0803aab5
+ 803a9e0:	0803aaad 	.word	0x0803aaad
+ 803a9e4:	0803aaad 	.word	0x0803aaad
+ 803a9e8:	0803aaad 	.word	0x0803aaad
+ 803a9ec:	0803aaad 	.word	0x0803aaad
+ 803a9f0:	0803aaad 	.word	0x0803aaad
+ 803a9f4:	0803aaad 	.word	0x0803aaad
+ 803a9f8:	0803aaad 	.word	0x0803aaad
+ 803a9fc:	0803aa81 	.word	0x0803aa81
+ 803aa00:	0803aaad 	.word	0x0803aaad
+ 803aa04:	0803aaad 	.word	0x0803aaad
+ 803aa08:	0803aaad 	.word	0x0803aaad
+ 803aa0c:	0803aaad 	.word	0x0803aaad
+ 803aa10:	0803aaad 	.word	0x0803aaad
+ 803aa14:	0803aaad 	.word	0x0803aaad
+ 803aa18:	0803aaad 	.word	0x0803aaad
+ 803aa1c:	0803aa97 	.word	0x0803aa97
+ 803aa20:	0803aaad 	.word	0x0803aaad
+ 803aa24:	0803aaad 	.word	0x0803aaad
+ 803aa28:	0803aaad 	.word	0x0803aaad
+ 803aa2c:	0803aaad 	.word	0x0803aaad
+ 803aa30:	0803aaad 	.word	0x0803aaad
+ 803aa34:	0803aaad 	.word	0x0803aaad
+ 803aa38:	0803aaad 	.word	0x0803aaad
+ 803aa3c:	0803aab5 	.word	0x0803aab5
+ 803aa40:	0803aaad 	.word	0x0803aaad
+ 803aa44:	0803aaad 	.word	0x0803aaad
+ 803aa48:	0803aaad 	.word	0x0803aaad
+ 803aa4c:	0803aaad 	.word	0x0803aaad
+ 803aa50:	0803aaad 	.word	0x0803aaad
+ 803aa54:	0803aaad 	.word	0x0803aaad
+ 803aa58:	0803aaad 	.word	0x0803aaad
+ 803aa5c:	0803aab5 	.word	0x0803aab5
+ 803aa60:	0803aaad 	.word	0x0803aaad
+ 803aa64:	0803aaad 	.word	0x0803aaad
+ 803aa68:	0803aaad 	.word	0x0803aaad
+ 803aa6c:	0803aaad 	.word	0x0803aaad
+ 803aa70:	0803aaad 	.word	0x0803aaad
+ 803aa74:	0803aaad 	.word	0x0803aaad
+ 803aa78:	0803aaad 	.word	0x0803aaad
+ 803aa7c:	0803aab5 	.word	0x0803aab5
+      case RCC_USART16CLKSOURCE_PCLK2: /* CD/D2 PCLK2 as clock source for USART1/6 */
+        /* USART1/6 clock source configuration done later after clock selection check */
+        break;
+
+      case RCC_USART16CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART1/6 */
+        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
+ 803aa80:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803aa84:	3308      	adds	r3, #8
+ 803aa86:	2101      	movs	r1, #1
+ 803aa88:	4618      	mov	r0, r3
+ 803aa8a:	f001 fe95 	bl	803c7b8 <RCCEx_PLL2_Config>
+ 803aa8e:	4603      	mov	r3, r0
+ 803aa90:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+        /* USART1/6 clock source configuration done later after clock selection check */
+        break;
+ 803aa94:	e00f      	b.n	803aab6 <HAL_RCCEx_PeriphCLKConfig+0xa32>
+
+      case RCC_USART16CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART1/6 */
+        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE);
+ 803aa96:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803aa9a:	3328      	adds	r3, #40	@ 0x28
+ 803aa9c:	2101      	movs	r1, #1
+ 803aa9e:	4618      	mov	r0, r3
+ 803aaa0:	f001 ff3c 	bl	803c91c <RCCEx_PLL3_Config>
+ 803aaa4:	4603      	mov	r3, r0
+ 803aaa6:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+        /* USART1/6 clock source configuration done later after clock selection check */
+        break;
+ 803aaaa:	e004      	b.n	803aab6 <HAL_RCCEx_PeriphCLKConfig+0xa32>
+        /* LSE,  oscillator is used as source of USART1/6 clock */
+        /* USART1/6 clock source configuration done later after clock selection check */
+        break;
+
+      default:
+        ret = HAL_ERROR;
+ 803aaac:	2301      	movs	r3, #1
+ 803aaae:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+        break;
+ 803aab2:	e000      	b.n	803aab6 <HAL_RCCEx_PeriphCLKConfig+0xa32>
+        break;
+ 803aab4:	bf00      	nop
+    }
+
+    if (ret == HAL_OK)
+ 803aab6:	f897 3127 	ldrb.w	r3, [r7, #295]	@ 0x127
+ 803aaba:	2b00      	cmp	r3, #0
+ 803aabc:	d10a      	bne.n	803aad4 <HAL_RCCEx_PeriphCLKConfig+0xa50>
+    {
+      /* Set the source of USART1/6 clock */
+      __HAL_RCC_USART16_CONFIG(PeriphClkInit->Usart16ClockSelection);
+ 803aabe:	4bbf      	ldr	r3, [pc, #764]	@ (803adbc <HAL_RCCEx_PeriphCLKConfig+0xd38>)
+ 803aac0:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
+ 803aac2:	f023 0138 	bic.w	r1, r3, #56	@ 0x38
+ 803aac6:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803aaca:	6fdb      	ldr	r3, [r3, #124]	@ 0x7c
+ 803aacc:	4abb      	ldr	r2, [pc, #748]	@ (803adbc <HAL_RCCEx_PeriphCLKConfig+0xd38>)
+ 803aace:	430b      	orrs	r3, r1
+ 803aad0:	6553      	str	r3, [r2, #84]	@ 0x54
+ 803aad2:	e003      	b.n	803aadc <HAL_RCCEx_PeriphCLKConfig+0xa58>
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+ 803aad4:	f897 3127 	ldrb.w	r3, [r7, #295]	@ 0x127
+ 803aad8:	f887 3126 	strb.w	r3, [r7, #294]	@ 0x126
+    }
+  }
+
+  /*-------------------------- USART2/3/4/5/7/8 Configuration --------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART234578) == RCC_PERIPHCLK_USART234578)
+ 803aadc:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803aae0:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 803aae4:	f002 0302 	and.w	r3, r2, #2
+ 803aae8:	f8c7 30b8 	str.w	r3, [r7, #184]	@ 0xb8
+ 803aaec:	2300      	movs	r3, #0
+ 803aaee:	f8c7 30bc 	str.w	r3, [r7, #188]	@ 0xbc
+ 803aaf2:	e9d7 122e 	ldrd	r1, r2, [r7, #184]	@ 0xb8
+ 803aaf6:	460b      	mov	r3, r1
+ 803aaf8:	4313      	orrs	r3, r2
+ 803aafa:	d041      	beq.n	803ab80 <HAL_RCCEx_PeriphCLKConfig+0xafc>
+  {
+    switch (PeriphClkInit->Usart234578ClockSelection)
+ 803aafc:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803ab00:	6f9b      	ldr	r3, [r3, #120]	@ 0x78
+ 803ab02:	2b05      	cmp	r3, #5
+ 803ab04:	d824      	bhi.n	803ab50 <HAL_RCCEx_PeriphCLKConfig+0xacc>
+ 803ab06:	a201      	add	r2, pc, #4	@ (adr r2, 803ab0c <HAL_RCCEx_PeriphCLKConfig+0xa88>)
+ 803ab08:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 803ab0c:	0803ab59 	.word	0x0803ab59
+ 803ab10:	0803ab25 	.word	0x0803ab25
+ 803ab14:	0803ab3b 	.word	0x0803ab3b
+ 803ab18:	0803ab59 	.word	0x0803ab59
+ 803ab1c:	0803ab59 	.word	0x0803ab59
+ 803ab20:	0803ab59 	.word	0x0803ab59
+      case RCC_USART234578CLKSOURCE_PCLK1: /* CD/D2 PCLK1 as clock source for USART2/3/4/5/7/8 */
+        /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
+        break;
+
+      case RCC_USART234578CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART2/3/4/5/7/8 */
+        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
+ 803ab24:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803ab28:	3308      	adds	r3, #8
+ 803ab2a:	2101      	movs	r1, #1
+ 803ab2c:	4618      	mov	r0, r3
+ 803ab2e:	f001 fe43 	bl	803c7b8 <RCCEx_PLL2_Config>
+ 803ab32:	4603      	mov	r3, r0
+ 803ab34:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+        /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
+        break;
+ 803ab38:	e00f      	b.n	803ab5a <HAL_RCCEx_PeriphCLKConfig+0xad6>
+
+      case RCC_USART234578CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART2/3/4/5/7/8 */
+        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE);
+ 803ab3a:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803ab3e:	3328      	adds	r3, #40	@ 0x28
+ 803ab40:	2101      	movs	r1, #1
+ 803ab42:	4618      	mov	r0, r3
+ 803ab44:	f001 feea 	bl	803c91c <RCCEx_PLL3_Config>
+ 803ab48:	4603      	mov	r3, r0
+ 803ab4a:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+        /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
+        break;
+ 803ab4e:	e004      	b.n	803ab5a <HAL_RCCEx_PeriphCLKConfig+0xad6>
+        /* LSE,  oscillator is used as source of USART2/3/4/5/7/8 clock */
+        /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
+        break;
+
+      default:
+        ret = HAL_ERROR;
+ 803ab50:	2301      	movs	r3, #1
+ 803ab52:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+        break;
+ 803ab56:	e000      	b.n	803ab5a <HAL_RCCEx_PeriphCLKConfig+0xad6>
+        break;
+ 803ab58:	bf00      	nop
+    }
+
+    if (ret == HAL_OK)
+ 803ab5a:	f897 3127 	ldrb.w	r3, [r7, #295]	@ 0x127
+ 803ab5e:	2b00      	cmp	r3, #0
+ 803ab60:	d10a      	bne.n	803ab78 <HAL_RCCEx_PeriphCLKConfig+0xaf4>
+    {
+      /* Set the source of USART2/3/4/5/7/8 clock */
+      __HAL_RCC_USART234578_CONFIG(PeriphClkInit->Usart234578ClockSelection);
+ 803ab62:	4b96      	ldr	r3, [pc, #600]	@ (803adbc <HAL_RCCEx_PeriphCLKConfig+0xd38>)
+ 803ab64:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
+ 803ab66:	f023 0107 	bic.w	r1, r3, #7
+ 803ab6a:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803ab6e:	6f9b      	ldr	r3, [r3, #120]	@ 0x78
+ 803ab70:	4a92      	ldr	r2, [pc, #584]	@ (803adbc <HAL_RCCEx_PeriphCLKConfig+0xd38>)
+ 803ab72:	430b      	orrs	r3, r1
+ 803ab74:	6553      	str	r3, [r2, #84]	@ 0x54
+ 803ab76:	e003      	b.n	803ab80 <HAL_RCCEx_PeriphCLKConfig+0xafc>
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+ 803ab78:	f897 3127 	ldrb.w	r3, [r7, #295]	@ 0x127
+ 803ab7c:	f887 3126 	strb.w	r3, [r7, #294]	@ 0x126
+    }
+  }
+
+  /*-------------------------- LPUART1 Configuration -------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
+ 803ab80:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803ab84:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 803ab88:	f002 0304 	and.w	r3, r2, #4
+ 803ab8c:	f8c7 30b0 	str.w	r3, [r7, #176]	@ 0xb0
+ 803ab90:	2300      	movs	r3, #0
+ 803ab92:	f8c7 30b4 	str.w	r3, [r7, #180]	@ 0xb4
+ 803ab96:	e9d7 122c 	ldrd	r1, r2, [r7, #176]	@ 0xb0
+ 803ab9a:	460b      	mov	r3, r1
+ 803ab9c:	4313      	orrs	r3, r2
+ 803ab9e:	d044      	beq.n	803ac2a <HAL_RCCEx_PeriphCLKConfig+0xba6>
+  {
+    switch (PeriphClkInit->Lpuart1ClockSelection)
+ 803aba0:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803aba4:	f8d3 3094 	ldr.w	r3, [r3, #148]	@ 0x94
+ 803aba8:	2b05      	cmp	r3, #5
+ 803abaa:	d825      	bhi.n	803abf8 <HAL_RCCEx_PeriphCLKConfig+0xb74>
+ 803abac:	a201      	add	r2, pc, #4	@ (adr r2, 803abb4 <HAL_RCCEx_PeriphCLKConfig+0xb30>)
+ 803abae:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 803abb2:	bf00      	nop
+ 803abb4:	0803ac01 	.word	0x0803ac01
+ 803abb8:	0803abcd 	.word	0x0803abcd
+ 803abbc:	0803abe3 	.word	0x0803abe3
+ 803abc0:	0803ac01 	.word	0x0803ac01
+ 803abc4:	0803ac01 	.word	0x0803ac01
+ 803abc8:	0803ac01 	.word	0x0803ac01
+      case RCC_LPUART1CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPUART1 */
+        /* LPUART1 clock source configuration done later after clock selection check */
+        break;
+
+      case RCC_LPUART1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPUART1 */
+        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
+ 803abcc:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803abd0:	3308      	adds	r3, #8
+ 803abd2:	2101      	movs	r1, #1
+ 803abd4:	4618      	mov	r0, r3
+ 803abd6:	f001 fdef 	bl	803c7b8 <RCCEx_PLL2_Config>
+ 803abda:	4603      	mov	r3, r0
+ 803abdc:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+        /* LPUART1 clock source configuration done later after clock selection check */
+        break;
+ 803abe0:	e00f      	b.n	803ac02 <HAL_RCCEx_PeriphCLKConfig+0xb7e>
+
+      case RCC_LPUART1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPUART1 */
+        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE);
+ 803abe2:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803abe6:	3328      	adds	r3, #40	@ 0x28
+ 803abe8:	2101      	movs	r1, #1
+ 803abea:	4618      	mov	r0, r3
+ 803abec:	f001 fe96 	bl	803c91c <RCCEx_PLL3_Config>
+ 803abf0:	4603      	mov	r3, r0
+ 803abf2:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+        /* LPUART1 clock source configuration done later after clock selection check */
+        break;
+ 803abf6:	e004      	b.n	803ac02 <HAL_RCCEx_PeriphCLKConfig+0xb7e>
+        /* LSE,  oscillator is used as source of LPUART1 clock */
+        /* LPUART1 clock source configuration done later after clock selection check */
+        break;
+
+      default:
+        ret = HAL_ERROR;
+ 803abf8:	2301      	movs	r3, #1
+ 803abfa:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+        break;
+ 803abfe:	e000      	b.n	803ac02 <HAL_RCCEx_PeriphCLKConfig+0xb7e>
+        break;
+ 803ac00:	bf00      	nop
+    }
+
+    if (ret == HAL_OK)
+ 803ac02:	f897 3127 	ldrb.w	r3, [r7, #295]	@ 0x127
+ 803ac06:	2b00      	cmp	r3, #0
+ 803ac08:	d10b      	bne.n	803ac22 <HAL_RCCEx_PeriphCLKConfig+0xb9e>
+    {
+      /* Set the source of LPUART1 clock */
+      __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
+ 803ac0a:	4b6c      	ldr	r3, [pc, #432]	@ (803adbc <HAL_RCCEx_PeriphCLKConfig+0xd38>)
+ 803ac0c:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
+ 803ac0e:	f023 0107 	bic.w	r1, r3, #7
+ 803ac12:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803ac16:	f8d3 3094 	ldr.w	r3, [r3, #148]	@ 0x94
+ 803ac1a:	4a68      	ldr	r2, [pc, #416]	@ (803adbc <HAL_RCCEx_PeriphCLKConfig+0xd38>)
+ 803ac1c:	430b      	orrs	r3, r1
+ 803ac1e:	6593      	str	r3, [r2, #88]	@ 0x58
+ 803ac20:	e003      	b.n	803ac2a <HAL_RCCEx_PeriphCLKConfig+0xba6>
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+ 803ac22:	f897 3127 	ldrb.w	r3, [r7, #295]	@ 0x127
+ 803ac26:	f887 3126 	strb.w	r3, [r7, #294]	@ 0x126
+    }
+  }
+
+  /*---------------------------- LPTIM1 configuration -------------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
+ 803ac2a:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803ac2e:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 803ac32:	f002 0320 	and.w	r3, r2, #32
+ 803ac36:	f8c7 30a8 	str.w	r3, [r7, #168]	@ 0xa8
+ 803ac3a:	2300      	movs	r3, #0
+ 803ac3c:	f8c7 30ac 	str.w	r3, [r7, #172]	@ 0xac
+ 803ac40:	e9d7 122a 	ldrd	r1, r2, [r7, #168]	@ 0xa8
+ 803ac44:	460b      	mov	r3, r1
+ 803ac46:	4313      	orrs	r3, r2
+ 803ac48:	d055      	beq.n	803acf6 <HAL_RCCEx_PeriphCLKConfig+0xc72>
+  {
+    switch (PeriphClkInit->Lptim1ClockSelection)
+ 803ac4a:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803ac4e:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
+ 803ac52:	f1b3 4fa0 	cmp.w	r3, #1342177280	@ 0x50000000
+ 803ac56:	d033      	beq.n	803acc0 <HAL_RCCEx_PeriphCLKConfig+0xc3c>
+ 803ac58:	f1b3 4fa0 	cmp.w	r3, #1342177280	@ 0x50000000
+ 803ac5c:	d82c      	bhi.n	803acb8 <HAL_RCCEx_PeriphCLKConfig+0xc34>
+ 803ac5e:	f1b3 4f80 	cmp.w	r3, #1073741824	@ 0x40000000
+ 803ac62:	d02f      	beq.n	803acc4 <HAL_RCCEx_PeriphCLKConfig+0xc40>
+ 803ac64:	f1b3 4f80 	cmp.w	r3, #1073741824	@ 0x40000000
+ 803ac68:	d826      	bhi.n	803acb8 <HAL_RCCEx_PeriphCLKConfig+0xc34>
+ 803ac6a:	f1b3 5f40 	cmp.w	r3, #805306368	@ 0x30000000
+ 803ac6e:	d02b      	beq.n	803acc8 <HAL_RCCEx_PeriphCLKConfig+0xc44>
+ 803ac70:	f1b3 5f40 	cmp.w	r3, #805306368	@ 0x30000000
+ 803ac74:	d820      	bhi.n	803acb8 <HAL_RCCEx_PeriphCLKConfig+0xc34>
+ 803ac76:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
+ 803ac7a:	d012      	beq.n	803aca2 <HAL_RCCEx_PeriphCLKConfig+0xc1e>
+ 803ac7c:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
+ 803ac80:	d81a      	bhi.n	803acb8 <HAL_RCCEx_PeriphCLKConfig+0xc34>
+ 803ac82:	2b00      	cmp	r3, #0
+ 803ac84:	d022      	beq.n	803accc <HAL_RCCEx_PeriphCLKConfig+0xc48>
+ 803ac86:	f1b3 5f80 	cmp.w	r3, #268435456	@ 0x10000000
+ 803ac8a:	d115      	bne.n	803acb8 <HAL_RCCEx_PeriphCLKConfig+0xc34>
+        /* LPTIM1 clock source configuration done later after clock selection check */
+        break;
+
+      case RCC_LPTIM1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM1*/
+
+        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
+ 803ac8c:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803ac90:	3308      	adds	r3, #8
+ 803ac92:	2100      	movs	r1, #0
+ 803ac94:	4618      	mov	r0, r3
+ 803ac96:	f001 fd8f 	bl	803c7b8 <RCCEx_PLL2_Config>
+ 803ac9a:	4603      	mov	r3, r0
+ 803ac9c:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+
+        /* LPTIM1 clock source configuration done later after clock selection check */
+        break;
+ 803aca0:	e015      	b.n	803acce <HAL_RCCEx_PeriphCLKConfig+0xc4a>
+
+      case RCC_LPTIM1CLKSOURCE_PLL3:  /* PLL3 is used as clock source for LPTIM1*/
+        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE);
+ 803aca2:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803aca6:	3328      	adds	r3, #40	@ 0x28
+ 803aca8:	2102      	movs	r1, #2
+ 803acaa:	4618      	mov	r0, r3
+ 803acac:	f001 fe36 	bl	803c91c <RCCEx_PLL3_Config>
+ 803acb0:	4603      	mov	r3, r0
+ 803acb2:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+
+        /* LPTIM1 clock source configuration done later after clock selection check */
+        break;
+ 803acb6:	e00a      	b.n	803acce <HAL_RCCEx_PeriphCLKConfig+0xc4a>
+        /* HSI, HSE, or CSI oscillator is used as source of LPTIM1 clock */
+        /* LPTIM1 clock source configuration done later after clock selection check */
+        break;
+
+      default:
+        ret = HAL_ERROR;
+ 803acb8:	2301      	movs	r3, #1
+ 803acba:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+        break;
+ 803acbe:	e006      	b.n	803acce <HAL_RCCEx_PeriphCLKConfig+0xc4a>
+        break;
+ 803acc0:	bf00      	nop
+ 803acc2:	e004      	b.n	803acce <HAL_RCCEx_PeriphCLKConfig+0xc4a>
+        break;
+ 803acc4:	bf00      	nop
+ 803acc6:	e002      	b.n	803acce <HAL_RCCEx_PeriphCLKConfig+0xc4a>
+        break;
+ 803acc8:	bf00      	nop
+ 803acca:	e000      	b.n	803acce <HAL_RCCEx_PeriphCLKConfig+0xc4a>
+        break;
+ 803accc:	bf00      	nop
+    }
+
+    if (ret == HAL_OK)
+ 803acce:	f897 3127 	ldrb.w	r3, [r7, #295]	@ 0x127
+ 803acd2:	2b00      	cmp	r3, #0
+ 803acd4:	d10b      	bne.n	803acee <HAL_RCCEx_PeriphCLKConfig+0xc6a>
+    {
+      /* Set the source of LPTIM1 clock*/
+      __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
+ 803acd6:	4b39      	ldr	r3, [pc, #228]	@ (803adbc <HAL_RCCEx_PeriphCLKConfig+0xd38>)
+ 803acd8:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
+ 803acda:	f023 41e0 	bic.w	r1, r3, #1879048192	@ 0x70000000
+ 803acde:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803ace2:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
+ 803ace6:	4a35      	ldr	r2, [pc, #212]	@ (803adbc <HAL_RCCEx_PeriphCLKConfig+0xd38>)
+ 803ace8:	430b      	orrs	r3, r1
+ 803acea:	6553      	str	r3, [r2, #84]	@ 0x54
+ 803acec:	e003      	b.n	803acf6 <HAL_RCCEx_PeriphCLKConfig+0xc72>
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+ 803acee:	f897 3127 	ldrb.w	r3, [r7, #295]	@ 0x127
+ 803acf2:	f887 3126 	strb.w	r3, [r7, #294]	@ 0x126
+    }
+  }
+
+  /*---------------------------- LPTIM2 configuration -------------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2)
+ 803acf6:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803acfa:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 803acfe:	f002 0340 	and.w	r3, r2, #64	@ 0x40
+ 803ad02:	f8c7 30a0 	str.w	r3, [r7, #160]	@ 0xa0
+ 803ad06:	2300      	movs	r3, #0
+ 803ad08:	f8c7 30a4 	str.w	r3, [r7, #164]	@ 0xa4
+ 803ad0c:	e9d7 1228 	ldrd	r1, r2, [r7, #160]	@ 0xa0
+ 803ad10:	460b      	mov	r3, r1
+ 803ad12:	4313      	orrs	r3, r2
+ 803ad14:	d058      	beq.n	803adc8 <HAL_RCCEx_PeriphCLKConfig+0xd44>
+  {
+    switch (PeriphClkInit->Lptim2ClockSelection)
+ 803ad16:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803ad1a:	f8d3 309c 	ldr.w	r3, [r3, #156]	@ 0x9c
+ 803ad1e:	f5b3 5fa0 	cmp.w	r3, #5120	@ 0x1400
+ 803ad22:	d033      	beq.n	803ad8c <HAL_RCCEx_PeriphCLKConfig+0xd08>
+ 803ad24:	f5b3 5fa0 	cmp.w	r3, #5120	@ 0x1400
+ 803ad28:	d82c      	bhi.n	803ad84 <HAL_RCCEx_PeriphCLKConfig+0xd00>
+ 803ad2a:	f5b3 5f80 	cmp.w	r3, #4096	@ 0x1000
+ 803ad2e:	d02f      	beq.n	803ad90 <HAL_RCCEx_PeriphCLKConfig+0xd0c>
+ 803ad30:	f5b3 5f80 	cmp.w	r3, #4096	@ 0x1000
+ 803ad34:	d826      	bhi.n	803ad84 <HAL_RCCEx_PeriphCLKConfig+0xd00>
+ 803ad36:	f5b3 6f40 	cmp.w	r3, #3072	@ 0xc00
+ 803ad3a:	d02b      	beq.n	803ad94 <HAL_RCCEx_PeriphCLKConfig+0xd10>
+ 803ad3c:	f5b3 6f40 	cmp.w	r3, #3072	@ 0xc00
+ 803ad40:	d820      	bhi.n	803ad84 <HAL_RCCEx_PeriphCLKConfig+0xd00>
+ 803ad42:	f5b3 6f00 	cmp.w	r3, #2048	@ 0x800
+ 803ad46:	d012      	beq.n	803ad6e <HAL_RCCEx_PeriphCLKConfig+0xcea>
+ 803ad48:	f5b3 6f00 	cmp.w	r3, #2048	@ 0x800
+ 803ad4c:	d81a      	bhi.n	803ad84 <HAL_RCCEx_PeriphCLKConfig+0xd00>
+ 803ad4e:	2b00      	cmp	r3, #0
+ 803ad50:	d022      	beq.n	803ad98 <HAL_RCCEx_PeriphCLKConfig+0xd14>
+ 803ad52:	f5b3 6f80 	cmp.w	r3, #1024	@ 0x400
+ 803ad56:	d115      	bne.n	803ad84 <HAL_RCCEx_PeriphCLKConfig+0xd00>
+        /* LPTIM2 clock source configuration done later after clock selection check */
+        break;
+
+      case RCC_LPTIM2CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM2*/
+
+        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
+ 803ad58:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803ad5c:	3308      	adds	r3, #8
+ 803ad5e:	2100      	movs	r1, #0
+ 803ad60:	4618      	mov	r0, r3
+ 803ad62:	f001 fd29 	bl	803c7b8 <RCCEx_PLL2_Config>
+ 803ad66:	4603      	mov	r3, r0
+ 803ad68:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+
+        /* LPTIM2 clock source configuration done later after clock selection check */
+        break;
+ 803ad6c:	e015      	b.n	803ad9a <HAL_RCCEx_PeriphCLKConfig+0xd16>
+
+      case RCC_LPTIM2CLKSOURCE_PLL3:  /* PLL3 is used as clock source for LPTIM2*/
+        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE);
+ 803ad6e:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803ad72:	3328      	adds	r3, #40	@ 0x28
+ 803ad74:	2102      	movs	r1, #2
+ 803ad76:	4618      	mov	r0, r3
+ 803ad78:	f001 fdd0 	bl	803c91c <RCCEx_PLL3_Config>
+ 803ad7c:	4603      	mov	r3, r0
+ 803ad7e:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+
+        /* LPTIM2 clock source configuration done later after clock selection check */
+        break;
+ 803ad82:	e00a      	b.n	803ad9a <HAL_RCCEx_PeriphCLKConfig+0xd16>
+        /* HSI, HSE, or CSI oscillator is used as source of LPTIM2 clock */
+        /* LPTIM2 clock source configuration done later after clock selection check */
+        break;
+
+      default:
+        ret = HAL_ERROR;
+ 803ad84:	2301      	movs	r3, #1
+ 803ad86:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+        break;
+ 803ad8a:	e006      	b.n	803ad9a <HAL_RCCEx_PeriphCLKConfig+0xd16>
+        break;
+ 803ad8c:	bf00      	nop
+ 803ad8e:	e004      	b.n	803ad9a <HAL_RCCEx_PeriphCLKConfig+0xd16>
+        break;
+ 803ad90:	bf00      	nop
+ 803ad92:	e002      	b.n	803ad9a <HAL_RCCEx_PeriphCLKConfig+0xd16>
+        break;
+ 803ad94:	bf00      	nop
+ 803ad96:	e000      	b.n	803ad9a <HAL_RCCEx_PeriphCLKConfig+0xd16>
+        break;
+ 803ad98:	bf00      	nop
+    }
+
+    if (ret == HAL_OK)
+ 803ad9a:	f897 3127 	ldrb.w	r3, [r7, #295]	@ 0x127
+ 803ad9e:	2b00      	cmp	r3, #0
+ 803ada0:	d10e      	bne.n	803adc0 <HAL_RCCEx_PeriphCLKConfig+0xd3c>
+    {
+      /* Set the source of LPTIM2 clock*/
+      __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);
+ 803ada2:	4b06      	ldr	r3, [pc, #24]	@ (803adbc <HAL_RCCEx_PeriphCLKConfig+0xd38>)
+ 803ada4:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
+ 803ada6:	f423 51e0 	bic.w	r1, r3, #7168	@ 0x1c00
+ 803adaa:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803adae:	f8d3 309c 	ldr.w	r3, [r3, #156]	@ 0x9c
+ 803adb2:	4a02      	ldr	r2, [pc, #8]	@ (803adbc <HAL_RCCEx_PeriphCLKConfig+0xd38>)
+ 803adb4:	430b      	orrs	r3, r1
+ 803adb6:	6593      	str	r3, [r2, #88]	@ 0x58
+ 803adb8:	e006      	b.n	803adc8 <HAL_RCCEx_PeriphCLKConfig+0xd44>
+ 803adba:	bf00      	nop
+ 803adbc:	58024400 	.word	0x58024400
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+ 803adc0:	f897 3127 	ldrb.w	r3, [r7, #295]	@ 0x127
+ 803adc4:	f887 3126 	strb.w	r3, [r7, #294]	@ 0x126
+    }
+  }
+
+  /*---------------------------- LPTIM345 configuration -------------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM345) == RCC_PERIPHCLK_LPTIM345)
+ 803adc8:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803adcc:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 803add0:	f002 0380 	and.w	r3, r2, #128	@ 0x80
+ 803add4:	f8c7 3098 	str.w	r3, [r7, #152]	@ 0x98
+ 803add8:	2300      	movs	r3, #0
+ 803adda:	f8c7 309c 	str.w	r3, [r7, #156]	@ 0x9c
+ 803adde:	e9d7 1226 	ldrd	r1, r2, [r7, #152]	@ 0x98
+ 803ade2:	460b      	mov	r3, r1
+ 803ade4:	4313      	orrs	r3, r2
+ 803ade6:	d055      	beq.n	803ae94 <HAL_RCCEx_PeriphCLKConfig+0xe10>
+  {
+    switch (PeriphClkInit->Lptim345ClockSelection)
+ 803ade8:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803adec:	f8d3 30a0 	ldr.w	r3, [r3, #160]	@ 0xa0
+ 803adf0:	f5b3 4f20 	cmp.w	r3, #40960	@ 0xa000
+ 803adf4:	d033      	beq.n	803ae5e <HAL_RCCEx_PeriphCLKConfig+0xdda>
+ 803adf6:	f5b3 4f20 	cmp.w	r3, #40960	@ 0xa000
+ 803adfa:	d82c      	bhi.n	803ae56 <HAL_RCCEx_PeriphCLKConfig+0xdd2>
+ 803adfc:	f5b3 4f00 	cmp.w	r3, #32768	@ 0x8000
+ 803ae00:	d02f      	beq.n	803ae62 <HAL_RCCEx_PeriphCLKConfig+0xdde>
+ 803ae02:	f5b3 4f00 	cmp.w	r3, #32768	@ 0x8000
+ 803ae06:	d826      	bhi.n	803ae56 <HAL_RCCEx_PeriphCLKConfig+0xdd2>
+ 803ae08:	f5b3 4fc0 	cmp.w	r3, #24576	@ 0x6000
+ 803ae0c:	d02b      	beq.n	803ae66 <HAL_RCCEx_PeriphCLKConfig+0xde2>
+ 803ae0e:	f5b3 4fc0 	cmp.w	r3, #24576	@ 0x6000
+ 803ae12:	d820      	bhi.n	803ae56 <HAL_RCCEx_PeriphCLKConfig+0xdd2>
+ 803ae14:	f5b3 4f80 	cmp.w	r3, #16384	@ 0x4000
+ 803ae18:	d012      	beq.n	803ae40 <HAL_RCCEx_PeriphCLKConfig+0xdbc>
+ 803ae1a:	f5b3 4f80 	cmp.w	r3, #16384	@ 0x4000
+ 803ae1e:	d81a      	bhi.n	803ae56 <HAL_RCCEx_PeriphCLKConfig+0xdd2>
+ 803ae20:	2b00      	cmp	r3, #0
+ 803ae22:	d022      	beq.n	803ae6a <HAL_RCCEx_PeriphCLKConfig+0xde6>
+ 803ae24:	f5b3 5f00 	cmp.w	r3, #8192	@ 0x2000
+ 803ae28:	d115      	bne.n	803ae56 <HAL_RCCEx_PeriphCLKConfig+0xdd2>
+      case RCC_LPTIM345CLKSOURCE_PCLK4:      /* SRD/D3 PCLK1 (PCLK4) as clock source for LPTIM3/4/5 */
+        /* LPTIM3/4/5 clock source configuration done later after clock selection check */
+        break;
+
+      case RCC_LPTIM345CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM3/4/5 */
+        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
+ 803ae2a:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803ae2e:	3308      	adds	r3, #8
+ 803ae30:	2100      	movs	r1, #0
+ 803ae32:	4618      	mov	r0, r3
+ 803ae34:	f001 fcc0 	bl	803c7b8 <RCCEx_PLL2_Config>
+ 803ae38:	4603      	mov	r3, r0
+ 803ae3a:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+
+        /* LPTIM3/4/5 clock source configuration done later after clock selection check */
+        break;
+ 803ae3e:	e015      	b.n	803ae6c <HAL_RCCEx_PeriphCLKConfig+0xde8>
+
+      case RCC_LPTIM345CLKSOURCE_PLL3:  /* PLL3 is used as clock source for LPTIM3/4/5 */
+        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE);
+ 803ae40:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803ae44:	3328      	adds	r3, #40	@ 0x28
+ 803ae46:	2102      	movs	r1, #2
+ 803ae48:	4618      	mov	r0, r3
+ 803ae4a:	f001 fd67 	bl	803c91c <RCCEx_PLL3_Config>
+ 803ae4e:	4603      	mov	r3, r0
+ 803ae50:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+
+        /* LPTIM3/4/5 clock source configuration done later after clock selection check */
+        break;
+ 803ae54:	e00a      	b.n	803ae6c <HAL_RCCEx_PeriphCLKConfig+0xde8>
+        /* HSI, HSE, or CSI oscillator is used as source of LPTIM3/4/5 clock */
+        /* LPTIM3/4/5 clock source configuration done later after clock selection check */
+        break;
+
+      default:
+        ret = HAL_ERROR;
+ 803ae56:	2301      	movs	r3, #1
+ 803ae58:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+        break;
+ 803ae5c:	e006      	b.n	803ae6c <HAL_RCCEx_PeriphCLKConfig+0xde8>
+        break;
+ 803ae5e:	bf00      	nop
+ 803ae60:	e004      	b.n	803ae6c <HAL_RCCEx_PeriphCLKConfig+0xde8>
+        break;
+ 803ae62:	bf00      	nop
+ 803ae64:	e002      	b.n	803ae6c <HAL_RCCEx_PeriphCLKConfig+0xde8>
+        break;
+ 803ae66:	bf00      	nop
+ 803ae68:	e000      	b.n	803ae6c <HAL_RCCEx_PeriphCLKConfig+0xde8>
+        break;
+ 803ae6a:	bf00      	nop
+    }
+
+    if (ret == HAL_OK)
+ 803ae6c:	f897 3127 	ldrb.w	r3, [r7, #295]	@ 0x127
+ 803ae70:	2b00      	cmp	r3, #0
+ 803ae72:	d10b      	bne.n	803ae8c <HAL_RCCEx_PeriphCLKConfig+0xe08>
+    {
+      /* Set the source of LPTIM3/4/5 clock */
+      __HAL_RCC_LPTIM345_CONFIG(PeriphClkInit->Lptim345ClockSelection);
+ 803ae74:	4ba1      	ldr	r3, [pc, #644]	@ (803b0fc <HAL_RCCEx_PeriphCLKConfig+0x1078>)
+ 803ae76:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
+ 803ae78:	f423 4160 	bic.w	r1, r3, #57344	@ 0xe000
+ 803ae7c:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803ae80:	f8d3 30a0 	ldr.w	r3, [r3, #160]	@ 0xa0
+ 803ae84:	4a9d      	ldr	r2, [pc, #628]	@ (803b0fc <HAL_RCCEx_PeriphCLKConfig+0x1078>)
+ 803ae86:	430b      	orrs	r3, r1
+ 803ae88:	6593      	str	r3, [r2, #88]	@ 0x58
+ 803ae8a:	e003      	b.n	803ae94 <HAL_RCCEx_PeriphCLKConfig+0xe10>
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+ 803ae8c:	f897 3127 	ldrb.w	r3, [r7, #295]	@ 0x127
+ 803ae90:	f887 3126 	strb.w	r3, [r7, #294]	@ 0x126
+
+    __HAL_RCC_I2C1235_CONFIG(PeriphClkInit->I2c1235ClockSelection);
+
+  }
+#else
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C123) == RCC_PERIPHCLK_I2C123)
+ 803ae94:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803ae98:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 803ae9c:	f002 0308 	and.w	r3, r2, #8
+ 803aea0:	f8c7 3090 	str.w	r3, [r7, #144]	@ 0x90
+ 803aea4:	2300      	movs	r3, #0
+ 803aea6:	f8c7 3094 	str.w	r3, [r7, #148]	@ 0x94
+ 803aeaa:	e9d7 1224 	ldrd	r1, r2, [r7, #144]	@ 0x90
+ 803aeae:	460b      	mov	r3, r1
+ 803aeb0:	4313      	orrs	r3, r2
+ 803aeb2:	d01e      	beq.n	803aef2 <HAL_RCCEx_PeriphCLKConfig+0xe6e>
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_I2C123CLKSOURCE(PeriphClkInit->I2c123ClockSelection));
+
+    if ((PeriphClkInit->I2c123ClockSelection) == RCC_I2C123CLKSOURCE_PLL3)
+ 803aeb4:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803aeb8:	f8d3 3084 	ldr.w	r3, [r3, #132]	@ 0x84
+ 803aebc:	f5b3 5f80 	cmp.w	r3, #4096	@ 0x1000
+ 803aec0:	d10c      	bne.n	803aedc <HAL_RCCEx_PeriphCLKConfig+0xe58>
+    {
+      if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK)
+ 803aec2:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803aec6:	3328      	adds	r3, #40	@ 0x28
+ 803aec8:	2102      	movs	r1, #2
+ 803aeca:	4618      	mov	r0, r3
+ 803aecc:	f001 fd26 	bl	803c91c <RCCEx_PLL3_Config>
+ 803aed0:	4603      	mov	r3, r0
+ 803aed2:	2b00      	cmp	r3, #0
+ 803aed4:	d002      	beq.n	803aedc <HAL_RCCEx_PeriphCLKConfig+0xe58>
+      {
+        status = HAL_ERROR;
+ 803aed6:	2301      	movs	r3, #1
+ 803aed8:	f887 3126 	strb.w	r3, [r7, #294]	@ 0x126
+      }
+    }
+
+    __HAL_RCC_I2C123_CONFIG(PeriphClkInit->I2c123ClockSelection);
+ 803aedc:	4b87      	ldr	r3, [pc, #540]	@ (803b0fc <HAL_RCCEx_PeriphCLKConfig+0x1078>)
+ 803aede:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
+ 803aee0:	f423 5140 	bic.w	r1, r3, #12288	@ 0x3000
+ 803aee4:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803aee8:	f8d3 3084 	ldr.w	r3, [r3, #132]	@ 0x84
+ 803aeec:	4a83      	ldr	r2, [pc, #524]	@ (803b0fc <HAL_RCCEx_PeriphCLKConfig+0x1078>)
+ 803aeee:	430b      	orrs	r3, r1
+ 803aef0:	6553      	str	r3, [r2, #84]	@ 0x54
+
+  }
+#endif /* I2C5 */
+
+  /*------------------------------ I2C4 Configuration ------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
+ 803aef2:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803aef6:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 803aefa:	f002 0310 	and.w	r3, r2, #16
+ 803aefe:	f8c7 3088 	str.w	r3, [r7, #136]	@ 0x88
+ 803af02:	2300      	movs	r3, #0
+ 803af04:	f8c7 308c 	str.w	r3, [r7, #140]	@ 0x8c
+ 803af08:	e9d7 1222 	ldrd	r1, r2, [r7, #136]	@ 0x88
+ 803af0c:	460b      	mov	r3, r1
+ 803af0e:	4313      	orrs	r3, r2
+ 803af10:	d01e      	beq.n	803af50 <HAL_RCCEx_PeriphCLKConfig+0xecc>
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));
+
+    if ((PeriphClkInit->I2c4ClockSelection) == RCC_I2C4CLKSOURCE_PLL3)
+ 803af12:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803af16:	f8d3 3098 	ldr.w	r3, [r3, #152]	@ 0x98
+ 803af1a:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
+ 803af1e:	d10c      	bne.n	803af3a <HAL_RCCEx_PeriphCLKConfig+0xeb6>
+    {
+      if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK)
+ 803af20:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803af24:	3328      	adds	r3, #40	@ 0x28
+ 803af26:	2102      	movs	r1, #2
+ 803af28:	4618      	mov	r0, r3
+ 803af2a:	f001 fcf7 	bl	803c91c <RCCEx_PLL3_Config>
+ 803af2e:	4603      	mov	r3, r0
+ 803af30:	2b00      	cmp	r3, #0
+ 803af32:	d002      	beq.n	803af3a <HAL_RCCEx_PeriphCLKConfig+0xeb6>
+      {
+        status = HAL_ERROR;
+ 803af34:	2301      	movs	r3, #1
+ 803af36:	f887 3126 	strb.w	r3, [r7, #294]	@ 0x126
+      }
+    }
+
+    __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
+ 803af3a:	4b70      	ldr	r3, [pc, #448]	@ (803b0fc <HAL_RCCEx_PeriphCLKConfig+0x1078>)
+ 803af3c:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
+ 803af3e:	f423 7140 	bic.w	r1, r3, #768	@ 0x300
+ 803af42:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803af46:	f8d3 3098 	ldr.w	r3, [r3, #152]	@ 0x98
+ 803af4a:	4a6c      	ldr	r2, [pc, #432]	@ (803b0fc <HAL_RCCEx_PeriphCLKConfig+0x1078>)
+ 803af4c:	430b      	orrs	r3, r1
+ 803af4e:	6593      	str	r3, [r2, #88]	@ 0x58
+
+  }
+
+  /*---------------------------- ADC configuration -------------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
+ 803af50:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803af54:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 803af58:	f402 2300 	and.w	r3, r2, #524288	@ 0x80000
+ 803af5c:	f8c7 3080 	str.w	r3, [r7, #128]	@ 0x80
+ 803af60:	2300      	movs	r3, #0
+ 803af62:	f8c7 3084 	str.w	r3, [r7, #132]	@ 0x84
+ 803af66:	e9d7 1220 	ldrd	r1, r2, [r7, #128]	@ 0x80
+ 803af6a:	460b      	mov	r3, r1
+ 803af6c:	4313      	orrs	r3, r2
+ 803af6e:	d03e      	beq.n	803afee <HAL_RCCEx_PeriphCLKConfig+0xf6a>
+  {
+    switch (PeriphClkInit->AdcClockSelection)
+ 803af70:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803af74:	f8d3 30a4 	ldr.w	r3, [r3, #164]	@ 0xa4
+ 803af78:	f5b3 3f00 	cmp.w	r3, #131072	@ 0x20000
+ 803af7c:	d022      	beq.n	803afc4 <HAL_RCCEx_PeriphCLKConfig+0xf40>
+ 803af7e:	f5b3 3f00 	cmp.w	r3, #131072	@ 0x20000
+ 803af82:	d81b      	bhi.n	803afbc <HAL_RCCEx_PeriphCLKConfig+0xf38>
+ 803af84:	2b00      	cmp	r3, #0
+ 803af86:	d003      	beq.n	803af90 <HAL_RCCEx_PeriphCLKConfig+0xf0c>
+ 803af88:	f5b3 3f80 	cmp.w	r3, #65536	@ 0x10000
+ 803af8c:	d00b      	beq.n	803afa6 <HAL_RCCEx_PeriphCLKConfig+0xf22>
+ 803af8e:	e015      	b.n	803afbc <HAL_RCCEx_PeriphCLKConfig+0xf38>
+    {
+
+      case RCC_ADCCLKSOURCE_PLL2: /* PLL2 is used as clock source for ADC*/
+
+        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
+ 803af90:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803af94:	3308      	adds	r3, #8
+ 803af96:	2100      	movs	r1, #0
+ 803af98:	4618      	mov	r0, r3
+ 803af9a:	f001 fc0d 	bl	803c7b8 <RCCEx_PLL2_Config>
+ 803af9e:	4603      	mov	r3, r0
+ 803afa0:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+
+        /* ADC clock source configuration done later after clock selection check */
+        break;
+ 803afa4:	e00f      	b.n	803afc6 <HAL_RCCEx_PeriphCLKConfig+0xf42>
+
+      case RCC_ADCCLKSOURCE_PLL3:  /* PLL3 is used as clock source for ADC*/
+        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE);
+ 803afa6:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803afaa:	3328      	adds	r3, #40	@ 0x28
+ 803afac:	2102      	movs	r1, #2
+ 803afae:	4618      	mov	r0, r3
+ 803afb0:	f001 fcb4 	bl	803c91c <RCCEx_PLL3_Config>
+ 803afb4:	4603      	mov	r3, r0
+ 803afb6:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+
+        /* ADC clock source configuration done later after clock selection check */
+        break;
+ 803afba:	e004      	b.n	803afc6 <HAL_RCCEx_PeriphCLKConfig+0xf42>
+        /* HSI, HSE, or CSI oscillator is used as source of ADC clock */
+        /* ADC clock source configuration done later after clock selection check */
+        break;
+
+      default:
+        ret = HAL_ERROR;
+ 803afbc:	2301      	movs	r3, #1
+ 803afbe:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+        break;
+ 803afc2:	e000      	b.n	803afc6 <HAL_RCCEx_PeriphCLKConfig+0xf42>
+        break;
+ 803afc4:	bf00      	nop
+    }
+
+    if (ret == HAL_OK)
+ 803afc6:	f897 3127 	ldrb.w	r3, [r7, #295]	@ 0x127
+ 803afca:	2b00      	cmp	r3, #0
+ 803afcc:	d10b      	bne.n	803afe6 <HAL_RCCEx_PeriphCLKConfig+0xf62>
+    {
+      /* Set the source of ADC clock*/
+      __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
+ 803afce:	4b4b      	ldr	r3, [pc, #300]	@ (803b0fc <HAL_RCCEx_PeriphCLKConfig+0x1078>)
+ 803afd0:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
+ 803afd2:	f423 3140 	bic.w	r1, r3, #196608	@ 0x30000
+ 803afd6:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803afda:	f8d3 30a4 	ldr.w	r3, [r3, #164]	@ 0xa4
+ 803afde:	4a47      	ldr	r2, [pc, #284]	@ (803b0fc <HAL_RCCEx_PeriphCLKConfig+0x1078>)
+ 803afe0:	430b      	orrs	r3, r1
+ 803afe2:	6593      	str	r3, [r2, #88]	@ 0x58
+ 803afe4:	e003      	b.n	803afee <HAL_RCCEx_PeriphCLKConfig+0xf6a>
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+ 803afe6:	f897 3127 	ldrb.w	r3, [r7, #295]	@ 0x127
+ 803afea:	f887 3126 	strb.w	r3, [r7, #294]	@ 0x126
+    }
+  }
+
+  /*------------------------------ USB Configuration -------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
+ 803afee:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803aff2:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 803aff6:	f402 2380 	and.w	r3, r2, #262144	@ 0x40000
+ 803affa:	67bb      	str	r3, [r7, #120]	@ 0x78
+ 803affc:	2300      	movs	r3, #0
+ 803affe:	67fb      	str	r3, [r7, #124]	@ 0x7c
+ 803b000:	e9d7 121e 	ldrd	r1, r2, [r7, #120]	@ 0x78
+ 803b004:	460b      	mov	r3, r1
+ 803b006:	4313      	orrs	r3, r2
+ 803b008:	d03b      	beq.n	803b082 <HAL_RCCEx_PeriphCLKConfig+0xffe>
+  {
+
+    switch (PeriphClkInit->UsbClockSelection)
+ 803b00a:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803b00e:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
+ 803b012:	f5b3 1f40 	cmp.w	r3, #3145728	@ 0x300000
+ 803b016:	d01f      	beq.n	803b058 <HAL_RCCEx_PeriphCLKConfig+0xfd4>
+ 803b018:	f5b3 1f40 	cmp.w	r3, #3145728	@ 0x300000
+ 803b01c:	d818      	bhi.n	803b050 <HAL_RCCEx_PeriphCLKConfig+0xfcc>
+ 803b01e:	f5b3 1f80 	cmp.w	r3, #1048576	@ 0x100000
+ 803b022:	d003      	beq.n	803b02c <HAL_RCCEx_PeriphCLKConfig+0xfa8>
+ 803b024:	f5b3 1f00 	cmp.w	r3, #2097152	@ 0x200000
+ 803b028:	d007      	beq.n	803b03a <HAL_RCCEx_PeriphCLKConfig+0xfb6>
+ 803b02a:	e011      	b.n	803b050 <HAL_RCCEx_PeriphCLKConfig+0xfcc>
+    {
+      case RCC_USBCLKSOURCE_PLL:      /* PLL is used as clock source for USB*/
+        /* Enable USB Clock output generated form System USB . */
+        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+ 803b02c:	4b33      	ldr	r3, [pc, #204]	@ (803b0fc <HAL_RCCEx_PeriphCLKConfig+0x1078>)
+ 803b02e:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 803b030:	4a32      	ldr	r2, [pc, #200]	@ (803b0fc <HAL_RCCEx_PeriphCLKConfig+0x1078>)
+ 803b032:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
+ 803b036:	62d3      	str	r3, [r2, #44]	@ 0x2c
+
+        /* USB clock source configuration done later after clock selection check */
+        break;
+ 803b038:	e00f      	b.n	803b05a <HAL_RCCEx_PeriphCLKConfig+0xfd6>
+
+      case RCC_USBCLKSOURCE_PLL3: /* PLL3 is used as clock source for USB*/
+
+        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE);
+ 803b03a:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803b03e:	3328      	adds	r3, #40	@ 0x28
+ 803b040:	2101      	movs	r1, #1
+ 803b042:	4618      	mov	r0, r3
+ 803b044:	f001 fc6a 	bl	803c91c <RCCEx_PLL3_Config>
+ 803b048:	4603      	mov	r3, r0
+ 803b04a:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+
+        /* USB clock source configuration done later after clock selection check */
+        break;
+ 803b04e:	e004      	b.n	803b05a <HAL_RCCEx_PeriphCLKConfig+0xfd6>
+        /* HSI48 oscillator is used as source of USB clock */
+        /* USB clock source configuration done later after clock selection check */
+        break;
+
+      default:
+        ret = HAL_ERROR;
+ 803b050:	2301      	movs	r3, #1
+ 803b052:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+        break;
+ 803b056:	e000      	b.n	803b05a <HAL_RCCEx_PeriphCLKConfig+0xfd6>
+        break;
+ 803b058:	bf00      	nop
+    }
+
+    if (ret == HAL_OK)
+ 803b05a:	f897 3127 	ldrb.w	r3, [r7, #295]	@ 0x127
+ 803b05e:	2b00      	cmp	r3, #0
+ 803b060:	d10b      	bne.n	803b07a <HAL_RCCEx_PeriphCLKConfig+0xff6>
+    {
+      /* Set the source of USB clock*/
+      __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
+ 803b062:	4b26      	ldr	r3, [pc, #152]	@ (803b0fc <HAL_RCCEx_PeriphCLKConfig+0x1078>)
+ 803b064:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
+ 803b066:	f423 1140 	bic.w	r1, r3, #3145728	@ 0x300000
+ 803b06a:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803b06e:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
+ 803b072:	4a22      	ldr	r2, [pc, #136]	@ (803b0fc <HAL_RCCEx_PeriphCLKConfig+0x1078>)
+ 803b074:	430b      	orrs	r3, r1
+ 803b076:	6553      	str	r3, [r2, #84]	@ 0x54
+ 803b078:	e003      	b.n	803b082 <HAL_RCCEx_PeriphCLKConfig+0xffe>
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+ 803b07a:	f897 3127 	ldrb.w	r3, [r7, #295]	@ 0x127
+ 803b07e:	f887 3126 	strb.w	r3, [r7, #294]	@ 0x126
+    }
+
+  }
+
+  /*------------------------------------- SDMMC Configuration ------------------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC) == RCC_PERIPHCLK_SDMMC)
+ 803b082:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803b086:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 803b08a:	f402 3380 	and.w	r3, r2, #65536	@ 0x10000
+ 803b08e:	673b      	str	r3, [r7, #112]	@ 0x70
+ 803b090:	2300      	movs	r3, #0
+ 803b092:	677b      	str	r3, [r7, #116]	@ 0x74
+ 803b094:	e9d7 121c 	ldrd	r1, r2, [r7, #112]	@ 0x70
+ 803b098:	460b      	mov	r3, r1
+ 803b09a:	4313      	orrs	r3, r2
+ 803b09c:	d034      	beq.n	803b108 <HAL_RCCEx_PeriphCLKConfig+0x1084>
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_SDMMC(PeriphClkInit->SdmmcClockSelection));
+
+    switch (PeriphClkInit->SdmmcClockSelection)
+ 803b09e:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803b0a2:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
+ 803b0a4:	2b00      	cmp	r3, #0
+ 803b0a6:	d003      	beq.n	803b0b0 <HAL_RCCEx_PeriphCLKConfig+0x102c>
+ 803b0a8:	f5b3 3f80 	cmp.w	r3, #65536	@ 0x10000
+ 803b0ac:	d007      	beq.n	803b0be <HAL_RCCEx_PeriphCLKConfig+0x103a>
+ 803b0ae:	e011      	b.n	803b0d4 <HAL_RCCEx_PeriphCLKConfig+0x1050>
+    {
+      case RCC_SDMMCCLKSOURCE_PLL:      /* PLL is used as clock source for SDMMC*/
+        /* Enable SDMMC Clock output generated form System PLL . */
+        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+ 803b0b0:	4b12      	ldr	r3, [pc, #72]	@ (803b0fc <HAL_RCCEx_PeriphCLKConfig+0x1078>)
+ 803b0b2:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 803b0b4:	4a11      	ldr	r2, [pc, #68]	@ (803b0fc <HAL_RCCEx_PeriphCLKConfig+0x1078>)
+ 803b0b6:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
+ 803b0ba:	62d3      	str	r3, [r2, #44]	@ 0x2c
+
+        /* SDMMC clock source configuration done later after clock selection check */
+        break;
+ 803b0bc:	e00e      	b.n	803b0dc <HAL_RCCEx_PeriphCLKConfig+0x1058>
+
+      case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for SDMMC*/
+
+        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE);
+ 803b0be:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803b0c2:	3308      	adds	r3, #8
+ 803b0c4:	2102      	movs	r1, #2
+ 803b0c6:	4618      	mov	r0, r3
+ 803b0c8:	f001 fb76 	bl	803c7b8 <RCCEx_PLL2_Config>
+ 803b0cc:	4603      	mov	r3, r0
+ 803b0ce:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+
+        /* SDMMC clock source configuration done later after clock selection check */
+        break;
+ 803b0d2:	e003      	b.n	803b0dc <HAL_RCCEx_PeriphCLKConfig+0x1058>
+
+      default:
+        ret = HAL_ERROR;
+ 803b0d4:	2301      	movs	r3, #1
+ 803b0d6:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+        break;
+ 803b0da:	bf00      	nop
+    }
+
+    if (ret == HAL_OK)
+ 803b0dc:	f897 3127 	ldrb.w	r3, [r7, #295]	@ 0x127
+ 803b0e0:	2b00      	cmp	r3, #0
+ 803b0e2:	d10d      	bne.n	803b100 <HAL_RCCEx_PeriphCLKConfig+0x107c>
+    {
+      /* Set the source of SDMMC clock*/
+      __HAL_RCC_SDMMC_CONFIG(PeriphClkInit->SdmmcClockSelection);
+ 803b0e4:	4b05      	ldr	r3, [pc, #20]	@ (803b0fc <HAL_RCCEx_PeriphCLKConfig+0x1078>)
+ 803b0e6:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
+ 803b0e8:	f423 3180 	bic.w	r1, r3, #65536	@ 0x10000
+ 803b0ec:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803b0f0:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
+ 803b0f2:	4a02      	ldr	r2, [pc, #8]	@ (803b0fc <HAL_RCCEx_PeriphCLKConfig+0x1078>)
+ 803b0f4:	430b      	orrs	r3, r1
+ 803b0f6:	64d3      	str	r3, [r2, #76]	@ 0x4c
+ 803b0f8:	e006      	b.n	803b108 <HAL_RCCEx_PeriphCLKConfig+0x1084>
+ 803b0fa:	bf00      	nop
+ 803b0fc:	58024400 	.word	0x58024400
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+ 803b100:	f897 3127 	ldrb.w	r3, [r7, #295]	@ 0x127
+ 803b104:	f887 3126 	strb.w	r3, [r7, #294]	@ 0x126
+    }
+  }
+
+#if defined(LTDC)
+  /*-------------------------------------- LTDC Configuration -----------------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)
+ 803b108:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803b10c:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 803b110:	f002 5300 	and.w	r3, r2, #536870912	@ 0x20000000
+ 803b114:	66bb      	str	r3, [r7, #104]	@ 0x68
+ 803b116:	2300      	movs	r3, #0
+ 803b118:	66fb      	str	r3, [r7, #108]	@ 0x6c
+ 803b11a:	e9d7 121a 	ldrd	r1, r2, [r7, #104]	@ 0x68
+ 803b11e:	460b      	mov	r3, r1
+ 803b120:	4313      	orrs	r3, r2
+ 803b122:	d00c      	beq.n	803b13e <HAL_RCCEx_PeriphCLKConfig+0x10ba>
+  {
+    if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK)
+ 803b124:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803b128:	3328      	adds	r3, #40	@ 0x28
+ 803b12a:	2102      	movs	r1, #2
+ 803b12c:	4618      	mov	r0, r3
+ 803b12e:	f001 fbf5 	bl	803c91c <RCCEx_PLL3_Config>
+ 803b132:	4603      	mov	r3, r0
+ 803b134:	2b00      	cmp	r3, #0
+ 803b136:	d002      	beq.n	803b13e <HAL_RCCEx_PeriphCLKConfig+0x10ba>
+    {
+      status = HAL_ERROR;
+ 803b138:	2301      	movs	r3, #1
+ 803b13a:	f887 3126 	strb.w	r3, [r7, #294]	@ 0x126
+    }
+  }
+#endif /* LTDC */
+
+  /*------------------------------ RNG Configuration -------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG)
+ 803b13e:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803b142:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 803b146:	f402 3300 	and.w	r3, r2, #131072	@ 0x20000
+ 803b14a:	663b      	str	r3, [r7, #96]	@ 0x60
+ 803b14c:	2300      	movs	r3, #0
+ 803b14e:	667b      	str	r3, [r7, #100]	@ 0x64
+ 803b150:	e9d7 1218 	ldrd	r1, r2, [r7, #96]	@ 0x60
+ 803b154:	460b      	mov	r3, r1
+ 803b156:	4313      	orrs	r3, r2
+ 803b158:	d038      	beq.n	803b1cc <HAL_RCCEx_PeriphCLKConfig+0x1148>
+  {
+
+    switch (PeriphClkInit->RngClockSelection)
+ 803b15a:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803b15e:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
+ 803b162:	f5b3 7f40 	cmp.w	r3, #768	@ 0x300
+ 803b166:	d018      	beq.n	803b19a <HAL_RCCEx_PeriphCLKConfig+0x1116>
+ 803b168:	f5b3 7f40 	cmp.w	r3, #768	@ 0x300
+ 803b16c:	d811      	bhi.n	803b192 <HAL_RCCEx_PeriphCLKConfig+0x110e>
+ 803b16e:	f5b3 7f00 	cmp.w	r3, #512	@ 0x200
+ 803b172:	d014      	beq.n	803b19e <HAL_RCCEx_PeriphCLKConfig+0x111a>
+ 803b174:	f5b3 7f00 	cmp.w	r3, #512	@ 0x200
+ 803b178:	d80b      	bhi.n	803b192 <HAL_RCCEx_PeriphCLKConfig+0x110e>
+ 803b17a:	2b00      	cmp	r3, #0
+ 803b17c:	d011      	beq.n	803b1a2 <HAL_RCCEx_PeriphCLKConfig+0x111e>
+ 803b17e:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
+ 803b182:	d106      	bne.n	803b192 <HAL_RCCEx_PeriphCLKConfig+0x110e>
+    {
+      case RCC_RNGCLKSOURCE_PLL:     /* PLL is used as clock source for RNG*/
+        /* Enable RNG Clock output generated form System RNG . */
+        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+ 803b184:	4bc3      	ldr	r3, [pc, #780]	@ (803b494 <HAL_RCCEx_PeriphCLKConfig+0x1410>)
+ 803b186:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 803b188:	4ac2      	ldr	r2, [pc, #776]	@ (803b494 <HAL_RCCEx_PeriphCLKConfig+0x1410>)
+ 803b18a:	f443 3300 	orr.w	r3, r3, #131072	@ 0x20000
+ 803b18e:	62d3      	str	r3, [r2, #44]	@ 0x2c
+
+        /* RNG clock source configuration done later after clock selection check */
+        break;
+ 803b190:	e008      	b.n	803b1a4 <HAL_RCCEx_PeriphCLKConfig+0x1120>
+        /* HSI48 oscillator is used as source of RNG clock */
+        /* RNG clock source configuration done later after clock selection check */
+        break;
+
+      default:
+        ret = HAL_ERROR;
+ 803b192:	2301      	movs	r3, #1
+ 803b194:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+        break;
+ 803b198:	e004      	b.n	803b1a4 <HAL_RCCEx_PeriphCLKConfig+0x1120>
+        break;
+ 803b19a:	bf00      	nop
+ 803b19c:	e002      	b.n	803b1a4 <HAL_RCCEx_PeriphCLKConfig+0x1120>
+        break;
+ 803b19e:	bf00      	nop
+ 803b1a0:	e000      	b.n	803b1a4 <HAL_RCCEx_PeriphCLKConfig+0x1120>
+        break;
+ 803b1a2:	bf00      	nop
+    }
+
+    if (ret == HAL_OK)
+ 803b1a4:	f897 3127 	ldrb.w	r3, [r7, #295]	@ 0x127
+ 803b1a8:	2b00      	cmp	r3, #0
+ 803b1aa:	d10b      	bne.n	803b1c4 <HAL_RCCEx_PeriphCLKConfig+0x1140>
+    {
+      /* Set the source of RNG clock*/
+      __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
+ 803b1ac:	4bb9      	ldr	r3, [pc, #740]	@ (803b494 <HAL_RCCEx_PeriphCLKConfig+0x1410>)
+ 803b1ae:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
+ 803b1b0:	f423 7140 	bic.w	r1, r3, #768	@ 0x300
+ 803b1b4:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803b1b8:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
+ 803b1bc:	4ab5      	ldr	r2, [pc, #724]	@ (803b494 <HAL_RCCEx_PeriphCLKConfig+0x1410>)
+ 803b1be:	430b      	orrs	r3, r1
+ 803b1c0:	6553      	str	r3, [r2, #84]	@ 0x54
+ 803b1c2:	e003      	b.n	803b1cc <HAL_RCCEx_PeriphCLKConfig+0x1148>
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+ 803b1c4:	f897 3127 	ldrb.w	r3, [r7, #295]	@ 0x127
+ 803b1c8:	f887 3126 	strb.w	r3, [r7, #294]	@ 0x126
+    }
+
+  }
+
+  /*------------------------------ SWPMI1 Configuration ------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1)
+ 803b1cc:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803b1d0:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 803b1d4:	f402 1380 	and.w	r3, r2, #1048576	@ 0x100000
+ 803b1d8:	65bb      	str	r3, [r7, #88]	@ 0x58
+ 803b1da:	2300      	movs	r3, #0
+ 803b1dc:	65fb      	str	r3, [r7, #92]	@ 0x5c
+ 803b1de:	e9d7 1216 	ldrd	r1, r2, [r7, #88]	@ 0x58
+ 803b1e2:	460b      	mov	r3, r1
+ 803b1e4:	4313      	orrs	r3, r2
+ 803b1e6:	d009      	beq.n	803b1fc <HAL_RCCEx_PeriphCLKConfig+0x1178>
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection));
+
+    /* Configure the SWPMI1 interface clock source */
+    __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection);
+ 803b1e8:	4baa      	ldr	r3, [pc, #680]	@ (803b494 <HAL_RCCEx_PeriphCLKConfig+0x1410>)
+ 803b1ea:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
+ 803b1ec:	f023 4100 	bic.w	r1, r3, #2147483648	@ 0x80000000
+ 803b1f0:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803b1f4:	6f5b      	ldr	r3, [r3, #116]	@ 0x74
+ 803b1f6:	4aa7      	ldr	r2, [pc, #668]	@ (803b494 <HAL_RCCEx_PeriphCLKConfig+0x1410>)
+ 803b1f8:	430b      	orrs	r3, r1
+ 803b1fa:	6513      	str	r3, [r2, #80]	@ 0x50
+  }
+#if defined(HRTIM1)
+  /*------------------------------ HRTIM1 clock Configuration ----------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HRTIM1) == RCC_PERIPHCLK_HRTIM1)
+ 803b1fc:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803b200:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 803b204:	f002 5380 	and.w	r3, r2, #268435456	@ 0x10000000
+ 803b208:	653b      	str	r3, [r7, #80]	@ 0x50
+ 803b20a:	2300      	movs	r3, #0
+ 803b20c:	657b      	str	r3, [r7, #84]	@ 0x54
+ 803b20e:	e9d7 1214 	ldrd	r1, r2, [r7, #80]	@ 0x50
+ 803b212:	460b      	mov	r3, r1
+ 803b214:	4313      	orrs	r3, r2
+ 803b216:	d00a      	beq.n	803b22e <HAL_RCCEx_PeriphCLKConfig+0x11aa>
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_HRTIM1CLKSOURCE(PeriphClkInit->Hrtim1ClockSelection));
+
+    /* Configure the HRTIM1 clock source */
+    __HAL_RCC_HRTIM1_CONFIG(PeriphClkInit->Hrtim1ClockSelection);
+ 803b218:	4b9e      	ldr	r3, [pc, #632]	@ (803b494 <HAL_RCCEx_PeriphCLKConfig+0x1410>)
+ 803b21a:	691b      	ldr	r3, [r3, #16]
+ 803b21c:	f423 4180 	bic.w	r1, r3, #16384	@ 0x4000
+ 803b220:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803b224:	f8d3 30b8 	ldr.w	r3, [r3, #184]	@ 0xb8
+ 803b228:	4a9a      	ldr	r2, [pc, #616]	@ (803b494 <HAL_RCCEx_PeriphCLKConfig+0x1410>)
+ 803b22a:	430b      	orrs	r3, r1
+ 803b22c:	6113      	str	r3, [r2, #16]
+  }
+#endif  /*HRTIM1*/
+  /*------------------------------ DFSDM1 Configuration ------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
+ 803b22e:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803b232:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 803b236:	f402 1300 	and.w	r3, r2, #2097152	@ 0x200000
+ 803b23a:	64bb      	str	r3, [r7, #72]	@ 0x48
+ 803b23c:	2300      	movs	r3, #0
+ 803b23e:	64fb      	str	r3, [r7, #76]	@ 0x4c
+ 803b240:	e9d7 1212 	ldrd	r1, r2, [r7, #72]	@ 0x48
+ 803b244:	460b      	mov	r3, r1
+ 803b246:	4313      	orrs	r3, r2
+ 803b248:	d009      	beq.n	803b25e <HAL_RCCEx_PeriphCLKConfig+0x11da>
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));
+
+    /* Configure the DFSDM1 interface clock source */
+    __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
+ 803b24a:	4b92      	ldr	r3, [pc, #584]	@ (803b494 <HAL_RCCEx_PeriphCLKConfig+0x1410>)
+ 803b24c:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
+ 803b24e:	f023 7180 	bic.w	r1, r3, #16777216	@ 0x1000000
+ 803b252:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803b256:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
+ 803b258:	4a8e      	ldr	r2, [pc, #568]	@ (803b494 <HAL_RCCEx_PeriphCLKConfig+0x1410>)
+ 803b25a:	430b      	orrs	r3, r1
+ 803b25c:	6513      	str	r3, [r2, #80]	@ 0x50
+    __HAL_RCC_DFSDM2_CONFIG(PeriphClkInit->Dfsdm2ClockSelection);
+  }
+#endif  /* DFSDM2 */
+
+  /*------------------------------------ TIM configuration --------------------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM)
+ 803b25e:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803b262:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 803b266:	f002 4380 	and.w	r3, r2, #1073741824	@ 0x40000000
+ 803b26a:	643b      	str	r3, [r7, #64]	@ 0x40
+ 803b26c:	2300      	movs	r3, #0
+ 803b26e:	647b      	str	r3, [r7, #68]	@ 0x44
+ 803b270:	e9d7 1210 	ldrd	r1, r2, [r7, #64]	@ 0x40
+ 803b274:	460b      	mov	r3, r1
+ 803b276:	4313      	orrs	r3, r2
+ 803b278:	d00e      	beq.n	803b298 <HAL_RCCEx_PeriphCLKConfig+0x1214>
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));
+
+    /* Configure Timer Prescaler */
+    __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
+ 803b27a:	4b86      	ldr	r3, [pc, #536]	@ (803b494 <HAL_RCCEx_PeriphCLKConfig+0x1410>)
+ 803b27c:	691b      	ldr	r3, [r3, #16]
+ 803b27e:	4a85      	ldr	r2, [pc, #532]	@ (803b494 <HAL_RCCEx_PeriphCLKConfig+0x1410>)
+ 803b280:	f423 4300 	bic.w	r3, r3, #32768	@ 0x8000
+ 803b284:	6113      	str	r3, [r2, #16]
+ 803b286:	4b83      	ldr	r3, [pc, #524]	@ (803b494 <HAL_RCCEx_PeriphCLKConfig+0x1410>)
+ 803b288:	6919      	ldr	r1, [r3, #16]
+ 803b28a:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803b28e:	f8d3 30bc 	ldr.w	r3, [r3, #188]	@ 0xbc
+ 803b292:	4a80      	ldr	r2, [pc, #512]	@ (803b494 <HAL_RCCEx_PeriphCLKConfig+0x1410>)
+ 803b294:	430b      	orrs	r3, r1
+ 803b296:	6113      	str	r3, [r2, #16]
+  }
+
+  /*------------------------------------ CKPER configuration --------------------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER)
+ 803b298:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803b29c:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 803b2a0:	f002 4300 	and.w	r3, r2, #2147483648	@ 0x80000000
+ 803b2a4:	63bb      	str	r3, [r7, #56]	@ 0x38
+ 803b2a6:	2300      	movs	r3, #0
+ 803b2a8:	63fb      	str	r3, [r7, #60]	@ 0x3c
+ 803b2aa:	e9d7 120e 	ldrd	r1, r2, [r7, #56]	@ 0x38
+ 803b2ae:	460b      	mov	r3, r1
+ 803b2b0:	4313      	orrs	r3, r2
+ 803b2b2:	d009      	beq.n	803b2c8 <HAL_RCCEx_PeriphCLKConfig+0x1244>
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_CLKPSOURCE(PeriphClkInit->CkperClockSelection));
+
+    /* Configure the CKPER clock source */
+    __HAL_RCC_CLKP_CONFIG(PeriphClkInit->CkperClockSelection);
+ 803b2b4:	4b77      	ldr	r3, [pc, #476]	@ (803b494 <HAL_RCCEx_PeriphCLKConfig+0x1410>)
+ 803b2b6:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
+ 803b2b8:	f023 5140 	bic.w	r1, r3, #805306368	@ 0x30000000
+ 803b2bc:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803b2c0:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
+ 803b2c2:	4a74      	ldr	r2, [pc, #464]	@ (803b494 <HAL_RCCEx_PeriphCLKConfig+0x1410>)
+ 803b2c4:	430b      	orrs	r3, r1
+ 803b2c6:	64d3      	str	r3, [r2, #76]	@ 0x4c
+  }
+
+  /*------------------------------ CEC Configuration ------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
+ 803b2c8:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803b2cc:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 803b2d0:	f402 0300 	and.w	r3, r2, #8388608	@ 0x800000
+ 803b2d4:	633b      	str	r3, [r7, #48]	@ 0x30
+ 803b2d6:	2300      	movs	r3, #0
+ 803b2d8:	637b      	str	r3, [r7, #52]	@ 0x34
+ 803b2da:	e9d7 120c 	ldrd	r1, r2, [r7, #48]	@ 0x30
+ 803b2de:	460b      	mov	r3, r1
+ 803b2e0:	4313      	orrs	r3, r2
+ 803b2e2:	d00a      	beq.n	803b2fa <HAL_RCCEx_PeriphCLKConfig+0x1276>
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
+
+    /* Configure the CEC interface clock source */
+    __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
+ 803b2e4:	4b6b      	ldr	r3, [pc, #428]	@ (803b494 <HAL_RCCEx_PeriphCLKConfig+0x1410>)
+ 803b2e6:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
+ 803b2e8:	f423 0140 	bic.w	r1, r3, #12582912	@ 0xc00000
+ 803b2ec:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803b2f0:	f8d3 308c 	ldr.w	r3, [r3, #140]	@ 0x8c
+ 803b2f4:	4a67      	ldr	r2, [pc, #412]	@ (803b494 <HAL_RCCEx_PeriphCLKConfig+0x1410>)
+ 803b2f6:	430b      	orrs	r3, r1
+ 803b2f8:	6553      	str	r3, [r2, #84]	@ 0x54
+  }
+
+  /*---------------------------- PLL2 configuration -------------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVP) == RCC_PERIPHCLK_PLL2_DIVP)
+ 803b2fa:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803b2fe:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 803b302:	2100      	movs	r1, #0
+ 803b304:	62b9      	str	r1, [r7, #40]	@ 0x28
+ 803b306:	f003 0301 	and.w	r3, r3, #1
+ 803b30a:	62fb      	str	r3, [r7, #44]	@ 0x2c
+ 803b30c:	e9d7 120a 	ldrd	r1, r2, [r7, #40]	@ 0x28
+ 803b310:	460b      	mov	r3, r1
+ 803b312:	4313      	orrs	r3, r2
+ 803b314:	d011      	beq.n	803b33a <HAL_RCCEx_PeriphCLKConfig+0x12b6>
+  {
+    ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
+ 803b316:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803b31a:	3308      	adds	r3, #8
+ 803b31c:	2100      	movs	r1, #0
+ 803b31e:	4618      	mov	r0, r3
+ 803b320:	f001 fa4a 	bl	803c7b8 <RCCEx_PLL2_Config>
+ 803b324:	4603      	mov	r3, r0
+ 803b326:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+    
+    if (ret == HAL_OK)
+ 803b32a:	f897 3127 	ldrb.w	r3, [r7, #295]	@ 0x127
+ 803b32e:	2b00      	cmp	r3, #0
+ 803b330:	d003      	beq.n	803b33a <HAL_RCCEx_PeriphCLKConfig+0x12b6>
+      /*Nothing to do*/
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+ 803b332:	f897 3127 	ldrb.w	r3, [r7, #295]	@ 0x127
+ 803b336:	f887 3126 	strb.w	r3, [r7, #294]	@ 0x126
+    } 
+  }
+  
+  
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVQ) == RCC_PERIPHCLK_PLL2_DIVQ)
+ 803b33a:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803b33e:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 803b342:	2100      	movs	r1, #0
+ 803b344:	6239      	str	r1, [r7, #32]
+ 803b346:	f003 0302 	and.w	r3, r3, #2
+ 803b34a:	627b      	str	r3, [r7, #36]	@ 0x24
+ 803b34c:	e9d7 1208 	ldrd	r1, r2, [r7, #32]
+ 803b350:	460b      	mov	r3, r1
+ 803b352:	4313      	orrs	r3, r2
+ 803b354:	d011      	beq.n	803b37a <HAL_RCCEx_PeriphCLKConfig+0x12f6>
+  {
+    ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
+ 803b356:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803b35a:	3308      	adds	r3, #8
+ 803b35c:	2101      	movs	r1, #1
+ 803b35e:	4618      	mov	r0, r3
+ 803b360:	f001 fa2a 	bl	803c7b8 <RCCEx_PLL2_Config>
+ 803b364:	4603      	mov	r3, r0
+ 803b366:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+    
+    if (ret == HAL_OK)
+ 803b36a:	f897 3127 	ldrb.w	r3, [r7, #295]	@ 0x127
+ 803b36e:	2b00      	cmp	r3, #0
+ 803b370:	d003      	beq.n	803b37a <HAL_RCCEx_PeriphCLKConfig+0x12f6>
+      /*Nothing to do*/
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+ 803b372:	f897 3127 	ldrb.w	r3, [r7, #295]	@ 0x127
+ 803b376:	f887 3126 	strb.w	r3, [r7, #294]	@ 0x126
+    }
+  }
+  
+  
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVR) == RCC_PERIPHCLK_PLL2_DIVR)
+ 803b37a:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803b37e:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 803b382:	2100      	movs	r1, #0
+ 803b384:	61b9      	str	r1, [r7, #24]
+ 803b386:	f003 0304 	and.w	r3, r3, #4
+ 803b38a:	61fb      	str	r3, [r7, #28]
+ 803b38c:	e9d7 1206 	ldrd	r1, r2, [r7, #24]
+ 803b390:	460b      	mov	r3, r1
+ 803b392:	4313      	orrs	r3, r2
+ 803b394:	d011      	beq.n	803b3ba <HAL_RCCEx_PeriphCLKConfig+0x1336>
+  {
+    ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE);
+ 803b396:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803b39a:	3308      	adds	r3, #8
+ 803b39c:	2102      	movs	r1, #2
+ 803b39e:	4618      	mov	r0, r3
+ 803b3a0:	f001 fa0a 	bl	803c7b8 <RCCEx_PLL2_Config>
+ 803b3a4:	4603      	mov	r3, r0
+ 803b3a6:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+    
+    if (ret == HAL_OK)
+ 803b3aa:	f897 3127 	ldrb.w	r3, [r7, #295]	@ 0x127
+ 803b3ae:	2b00      	cmp	r3, #0
+ 803b3b0:	d003      	beq.n	803b3ba <HAL_RCCEx_PeriphCLKConfig+0x1336>
+      /*Nothing to do*/
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+ 803b3b2:	f897 3127 	ldrb.w	r3, [r7, #295]	@ 0x127
+ 803b3b6:	f887 3126 	strb.w	r3, [r7, #294]	@ 0x126
+    }
+  }
+  
+
+  /*---------------------------- PLL3 configuration -------------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVP) == RCC_PERIPHCLK_PLL3_DIVP)
+ 803b3ba:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803b3be:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 803b3c2:	2100      	movs	r1, #0
+ 803b3c4:	6139      	str	r1, [r7, #16]
+ 803b3c6:	f003 0308 	and.w	r3, r3, #8
+ 803b3ca:	617b      	str	r3, [r7, #20]
+ 803b3cc:	e9d7 1204 	ldrd	r1, r2, [r7, #16]
+ 803b3d0:	460b      	mov	r3, r1
+ 803b3d2:	4313      	orrs	r3, r2
+ 803b3d4:	d011      	beq.n	803b3fa <HAL_RCCEx_PeriphCLKConfig+0x1376>
+  {
+    ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
+ 803b3d6:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803b3da:	3328      	adds	r3, #40	@ 0x28
+ 803b3dc:	2100      	movs	r1, #0
+ 803b3de:	4618      	mov	r0, r3
+ 803b3e0:	f001 fa9c 	bl	803c91c <RCCEx_PLL3_Config>
+ 803b3e4:	4603      	mov	r3, r0
+ 803b3e6:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+  
+    if (ret == HAL_OK)
+ 803b3ea:	f897 3127 	ldrb.w	r3, [r7, #295]	@ 0x127
+ 803b3ee:	2b00      	cmp	r3, #0
+ 803b3f0:	d003      	beq.n	803b3fa <HAL_RCCEx_PeriphCLKConfig+0x1376>
+      /*Nothing to do*/
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+ 803b3f2:	f897 3127 	ldrb.w	r3, [r7, #295]	@ 0x127
+ 803b3f6:	f887 3126 	strb.w	r3, [r7, #294]	@ 0x126
+    }
+  }
+  
+  
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVQ) == RCC_PERIPHCLK_PLL3_DIVQ)
+ 803b3fa:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803b3fe:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 803b402:	2100      	movs	r1, #0
+ 803b404:	60b9      	str	r1, [r7, #8]
+ 803b406:	f003 0310 	and.w	r3, r3, #16
+ 803b40a:	60fb      	str	r3, [r7, #12]
+ 803b40c:	e9d7 1202 	ldrd	r1, r2, [r7, #8]
+ 803b410:	460b      	mov	r3, r1
+ 803b412:	4313      	orrs	r3, r2
+ 803b414:	d011      	beq.n	803b43a <HAL_RCCEx_PeriphCLKConfig+0x13b6>
+  {
+    ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE);
+ 803b416:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803b41a:	3328      	adds	r3, #40	@ 0x28
+ 803b41c:	2101      	movs	r1, #1
+ 803b41e:	4618      	mov	r0, r3
+ 803b420:	f001 fa7c 	bl	803c91c <RCCEx_PLL3_Config>
+ 803b424:	4603      	mov	r3, r0
+ 803b426:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+    
+    if (ret == HAL_OK)
+ 803b42a:	f897 3127 	ldrb.w	r3, [r7, #295]	@ 0x127
+ 803b42e:	2b00      	cmp	r3, #0
+ 803b430:	d003      	beq.n	803b43a <HAL_RCCEx_PeriphCLKConfig+0x13b6>
+      /*Nothing to do*/
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+ 803b432:	f897 3127 	ldrb.w	r3, [r7, #295]	@ 0x127
+ 803b436:	f887 3126 	strb.w	r3, [r7, #294]	@ 0x126
+    }
+  }
+  
+  
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVR) == RCC_PERIPHCLK_PLL3_DIVR)
+ 803b43a:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803b43e:	e9d3 2300 	ldrd	r2, r3, [r3]
+ 803b442:	2100      	movs	r1, #0
+ 803b444:	6039      	str	r1, [r7, #0]
+ 803b446:	f003 0320 	and.w	r3, r3, #32
+ 803b44a:	607b      	str	r3, [r7, #4]
+ 803b44c:	e9d7 1200 	ldrd	r1, r2, [r7]
+ 803b450:	460b      	mov	r3, r1
+ 803b452:	4313      	orrs	r3, r2
+ 803b454:	d011      	beq.n	803b47a <HAL_RCCEx_PeriphCLKConfig+0x13f6>
+  {
+    ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE);
+ 803b456:	f8d7 3114 	ldr.w	r3, [r7, #276]	@ 0x114
+ 803b45a:	3328      	adds	r3, #40	@ 0x28
+ 803b45c:	2102      	movs	r1, #2
+ 803b45e:	4618      	mov	r0, r3
+ 803b460:	f001 fa5c 	bl	803c91c <RCCEx_PLL3_Config>
+ 803b464:	4603      	mov	r3, r0
+ 803b466:	f887 3127 	strb.w	r3, [r7, #295]	@ 0x127
+    
+    if (ret == HAL_OK)
+ 803b46a:	f897 3127 	ldrb.w	r3, [r7, #295]	@ 0x127
+ 803b46e:	2b00      	cmp	r3, #0
+ 803b470:	d003      	beq.n	803b47a <HAL_RCCEx_PeriphCLKConfig+0x13f6>
+      /*Nothing to do*/
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+ 803b472:	f897 3127 	ldrb.w	r3, [r7, #295]	@ 0x127
+ 803b476:	f887 3126 	strb.w	r3, [r7, #294]	@ 0x126
+    } 
+  }
+
+  if (status == HAL_OK)
+ 803b47a:	f897 3126 	ldrb.w	r3, [r7, #294]	@ 0x126
+ 803b47e:	2b00      	cmp	r3, #0
+ 803b480:	d101      	bne.n	803b486 <HAL_RCCEx_PeriphCLKConfig+0x1402>
+  {
+    return HAL_OK;
+ 803b482:	2300      	movs	r3, #0
+ 803b484:	e000      	b.n	803b488 <HAL_RCCEx_PeriphCLKConfig+0x1404>
+  }
+  return HAL_ERROR;
+ 803b486:	2301      	movs	r3, #1
+}
+ 803b488:	4618      	mov	r0, r3
+ 803b48a:	f507 7794 	add.w	r7, r7, #296	@ 0x128
+ 803b48e:	46bd      	mov	sp, r7
+ 803b490:	e8bd 8fb0 	ldmia.w	sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
+ 803b494:	58024400 	.word	0x58024400
+
+0803b498 <HAL_RCCEx_GetPeriphCLKFreq>:
+  * @retval Frequency in KHz
+  *
+  *  (*) : Available on some STM32H7 lines only.
+  */
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk)
+{
+ 803b498:	b580      	push	{r7, lr}
+ 803b49a:	b090      	sub	sp, #64	@ 0x40
+ 803b49c:	af00      	add	r7, sp, #0
+ 803b49e:	e9c7 0100 	strd	r0, r1, [r7]
+  /* This variable is used to store the SAI and CKP clock source */
+  uint32_t saiclocksource;
+  uint32_t ckpclocksource;
+  uint32_t srcclk;
+
+  if (PeriphClk == RCC_PERIPHCLK_SAI1)
+ 803b4a2:	e9d7 2300 	ldrd	r2, r3, [r7]
+ 803b4a6:	f5a2 7180 	sub.w	r1, r2, #256	@ 0x100
+ 803b4aa:	430b      	orrs	r3, r1
+ 803b4ac:	f040 8094 	bne.w	803b5d8 <HAL_RCCEx_GetPeriphCLKFreq+0x140>
+  {
+
+    saiclocksource = __HAL_RCC_GET_SAI1_SOURCE();
+ 803b4b0:	4b9e      	ldr	r3, [pc, #632]	@ (803b72c <HAL_RCCEx_GetPeriphCLKFreq+0x294>)
+ 803b4b2:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
+ 803b4b4:	f003 0307 	and.w	r3, r3, #7
+ 803b4b8:	633b      	str	r3, [r7, #48]	@ 0x30
+
+    switch (saiclocksource)
+ 803b4ba:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
+ 803b4bc:	2b04      	cmp	r3, #4
+ 803b4be:	f200 8087 	bhi.w	803b5d0 <HAL_RCCEx_GetPeriphCLKFreq+0x138>
+ 803b4c2:	a201      	add	r2, pc, #4	@ (adr r2, 803b4c8 <HAL_RCCEx_GetPeriphCLKFreq+0x30>)
+ 803b4c4:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 803b4c8:	0803b4dd 	.word	0x0803b4dd
+ 803b4cc:	0803b505 	.word	0x0803b505
+ 803b4d0:	0803b52d 	.word	0x0803b52d
+ 803b4d4:	0803b5c9 	.word	0x0803b5c9
+ 803b4d8:	0803b555 	.word	0x0803b555
+    {
+      case RCC_SAI1CLKSOURCE_PLL: /* PLL1 is the clock source for SAI1 */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
+ 803b4dc:	4b93      	ldr	r3, [pc, #588]	@ (803b72c <HAL_RCCEx_GetPeriphCLKFreq+0x294>)
+ 803b4de:	681b      	ldr	r3, [r3, #0]
+ 803b4e0:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
+ 803b4e4:	f1b3 7f00 	cmp.w	r3, #33554432	@ 0x2000000
+ 803b4e8:	d108      	bne.n	803b4fc <HAL_RCCEx_GetPeriphCLKFreq+0x64>
+        {
+          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+ 803b4ea:	f107 0324 	add.w	r3, r7, #36	@ 0x24
+ 803b4ee:	4618      	mov	r0, r3
+ 803b4f0:	f001 f810 	bl	803c514 <HAL_RCCEx_GetPLL1ClockFreq>
+          frequency = pll1_clocks.PLL1_Q_Frequency;
+ 803b4f4:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 803b4f6:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 803b4f8:	f000 bd45 	b.w	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+          frequency = 0;
+ 803b4fc:	2300      	movs	r3, #0
+ 803b4fe:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803b500:	f000 bd41 	b.w	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+      }
+      case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI1 */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
+ 803b504:	4b89      	ldr	r3, [pc, #548]	@ (803b72c <HAL_RCCEx_GetPeriphCLKFreq+0x294>)
+ 803b506:	681b      	ldr	r3, [r3, #0]
+ 803b508:	f003 6300 	and.w	r3, r3, #134217728	@ 0x8000000
+ 803b50c:	f1b3 6f00 	cmp.w	r3, #134217728	@ 0x8000000
+ 803b510:	d108      	bne.n	803b524 <HAL_RCCEx_GetPeriphCLKFreq+0x8c>
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+ 803b512:	f107 0318 	add.w	r3, r7, #24
+ 803b516:	4618      	mov	r0, r3
+ 803b518:	f000 fd54 	bl	803bfc4 <HAL_RCCEx_GetPLL2ClockFreq>
+          frequency = pll2_clocks.PLL2_P_Frequency;
+ 803b51c:	69bb      	ldr	r3, [r7, #24]
+ 803b51e:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 803b520:	f000 bd31 	b.w	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+          frequency = 0;
+ 803b524:	2300      	movs	r3, #0
+ 803b526:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803b528:	f000 bd2d 	b.w	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+      }
+
+      case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI1 */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
+ 803b52c:	4b7f      	ldr	r3, [pc, #508]	@ (803b72c <HAL_RCCEx_GetPeriphCLKFreq+0x294>)
+ 803b52e:	681b      	ldr	r3, [r3, #0]
+ 803b530:	f003 5300 	and.w	r3, r3, #536870912	@ 0x20000000
+ 803b534:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
+ 803b538:	d108      	bne.n	803b54c <HAL_RCCEx_GetPeriphCLKFreq+0xb4>
+        {
+          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+ 803b53a:	f107 030c 	add.w	r3, r7, #12
+ 803b53e:	4618      	mov	r0, r3
+ 803b540:	f000 fe94 	bl	803c26c <HAL_RCCEx_GetPLL3ClockFreq>
+          frequency = pll3_clocks.PLL3_P_Frequency;
+ 803b544:	68fb      	ldr	r3, [r7, #12]
+ 803b546:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 803b548:	f000 bd1d 	b.w	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+          frequency = 0;
+ 803b54c:	2300      	movs	r3, #0
+ 803b54e:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803b550:	f000 bd19 	b.w	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+      }
+
+      case RCC_SAI1CLKSOURCE_CLKP: /* CKPER is the clock source for SAI1*/
+      {
+
+        ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
+ 803b554:	4b75      	ldr	r3, [pc, #468]	@ (803b72c <HAL_RCCEx_GetPeriphCLKFreq+0x294>)
+ 803b556:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
+ 803b558:	f003 5340 	and.w	r3, r3, #805306368	@ 0x30000000
+ 803b55c:	637b      	str	r3, [r7, #52]	@ 0x34
+
+        if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
+ 803b55e:	4b73      	ldr	r3, [pc, #460]	@ (803b72c <HAL_RCCEx_GetPeriphCLKFreq+0x294>)
+ 803b560:	681b      	ldr	r3, [r3, #0]
+ 803b562:	f003 0304 	and.w	r3, r3, #4
+ 803b566:	2b04      	cmp	r3, #4
+ 803b568:	d10c      	bne.n	803b584 <HAL_RCCEx_GetPeriphCLKFreq+0xec>
+ 803b56a:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
+ 803b56c:	2b00      	cmp	r3, #0
+ 803b56e:	d109      	bne.n	803b584 <HAL_RCCEx_GetPeriphCLKFreq+0xec>
+        {
+          /* In Case the CKPER Source is HSI */
+          frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
+ 803b570:	4b6e      	ldr	r3, [pc, #440]	@ (803b72c <HAL_RCCEx_GetPeriphCLKFreq+0x294>)
+ 803b572:	681b      	ldr	r3, [r3, #0]
+ 803b574:	08db      	lsrs	r3, r3, #3
+ 803b576:	f003 0303 	and.w	r3, r3, #3
+ 803b57a:	4a6d      	ldr	r2, [pc, #436]	@ (803b730 <HAL_RCCEx_GetPeriphCLKFreq+0x298>)
+ 803b57c:	fa22 f303 	lsr.w	r3, r2, r3
+ 803b580:	63fb      	str	r3, [r7, #60]	@ 0x3c
+ 803b582:	e01f      	b.n	803b5c4 <HAL_RCCEx_GetPeriphCLKFreq+0x12c>
+        }
+
+        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
+ 803b584:	4b69      	ldr	r3, [pc, #420]	@ (803b72c <HAL_RCCEx_GetPeriphCLKFreq+0x294>)
+ 803b586:	681b      	ldr	r3, [r3, #0]
+ 803b588:	f403 7380 	and.w	r3, r3, #256	@ 0x100
+ 803b58c:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
+ 803b590:	d106      	bne.n	803b5a0 <HAL_RCCEx_GetPeriphCLKFreq+0x108>
+ 803b592:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
+ 803b594:	f1b3 5f80 	cmp.w	r3, #268435456	@ 0x10000000
+ 803b598:	d102      	bne.n	803b5a0 <HAL_RCCEx_GetPeriphCLKFreq+0x108>
+        {
+          /* In Case the CKPER Source is CSI */
+          frequency = CSI_VALUE;
+ 803b59a:	4b66      	ldr	r3, [pc, #408]	@ (803b734 <HAL_RCCEx_GetPeriphCLKFreq+0x29c>)
+ 803b59c:	63fb      	str	r3, [r7, #60]	@ 0x3c
+ 803b59e:	e011      	b.n	803b5c4 <HAL_RCCEx_GetPeriphCLKFreq+0x12c>
+        }
+
+        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
+ 803b5a0:	4b62      	ldr	r3, [pc, #392]	@ (803b72c <HAL_RCCEx_GetPeriphCLKFreq+0x294>)
+ 803b5a2:	681b      	ldr	r3, [r3, #0]
+ 803b5a4:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
+ 803b5a8:	f5b3 3f00 	cmp.w	r3, #131072	@ 0x20000
+ 803b5ac:	d106      	bne.n	803b5bc <HAL_RCCEx_GetPeriphCLKFreq+0x124>
+ 803b5ae:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
+ 803b5b0:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
+ 803b5b4:	d102      	bne.n	803b5bc <HAL_RCCEx_GetPeriphCLKFreq+0x124>
+        {
+          /* In Case the CKPER Source is HSE */
+          frequency = HSE_VALUE;
+ 803b5b6:	4b60      	ldr	r3, [pc, #384]	@ (803b738 <HAL_RCCEx_GetPeriphCLKFreq+0x2a0>)
+ 803b5b8:	63fb      	str	r3, [r7, #60]	@ 0x3c
+ 803b5ba:	e003      	b.n	803b5c4 <HAL_RCCEx_GetPeriphCLKFreq+0x12c>
+        }
+
+        else
+        {
+          /* In Case the CKPER is disabled*/
+          frequency = 0;
+ 803b5bc:	2300      	movs	r3, #0
+ 803b5be:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        }
+
+        break;
+ 803b5c0:	f000 bce1 	b.w	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+ 803b5c4:	f000 bcdf 	b.w	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+      }
+
+      case (RCC_SAI1CLKSOURCE_PIN): /* External clock is the clock source for SAI1 */
+      {
+        frequency = EXTERNAL_CLOCK_VALUE;
+ 803b5c8:	4b5c      	ldr	r3, [pc, #368]	@ (803b73c <HAL_RCCEx_GetPeriphCLKFreq+0x2a4>)
+ 803b5ca:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803b5cc:	f000 bcdb 	b.w	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+      }
+      default :
+      {
+        frequency = 0;
+ 803b5d0:	2300      	movs	r3, #0
+ 803b5d2:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803b5d4:	f000 bcd7 	b.w	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+      }
+    }
+  }
+
+#if defined(SAI3)
+  else if (PeriphClk == RCC_PERIPHCLK_SAI23)
+ 803b5d8:	e9d7 2300 	ldrd	r2, r3, [r7]
+ 803b5dc:	f5a2 7100 	sub.w	r1, r2, #512	@ 0x200
+ 803b5e0:	430b      	orrs	r3, r1
+ 803b5e2:	f040 80ad 	bne.w	803b740 <HAL_RCCEx_GetPeriphCLKFreq+0x2a8>
+  {
+
+    saiclocksource = __HAL_RCC_GET_SAI23_SOURCE();
+ 803b5e6:	4b51      	ldr	r3, [pc, #324]	@ (803b72c <HAL_RCCEx_GetPeriphCLKFreq+0x294>)
+ 803b5e8:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
+ 803b5ea:	f403 73e0 	and.w	r3, r3, #448	@ 0x1c0
+ 803b5ee:	633b      	str	r3, [r7, #48]	@ 0x30
+
+    switch (saiclocksource)
+ 803b5f0:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
+ 803b5f2:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
+ 803b5f6:	d056      	beq.n	803b6a6 <HAL_RCCEx_GetPeriphCLKFreq+0x20e>
+ 803b5f8:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
+ 803b5fa:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
+ 803b5fe:	f200 8090 	bhi.w	803b722 <HAL_RCCEx_GetPeriphCLKFreq+0x28a>
+ 803b602:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
+ 803b604:	2bc0      	cmp	r3, #192	@ 0xc0
+ 803b606:	f000 8088 	beq.w	803b71a <HAL_RCCEx_GetPeriphCLKFreq+0x282>
+ 803b60a:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
+ 803b60c:	2bc0      	cmp	r3, #192	@ 0xc0
+ 803b60e:	f200 8088 	bhi.w	803b722 <HAL_RCCEx_GetPeriphCLKFreq+0x28a>
+ 803b612:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
+ 803b614:	2b80      	cmp	r3, #128	@ 0x80
+ 803b616:	d032      	beq.n	803b67e <HAL_RCCEx_GetPeriphCLKFreq+0x1e6>
+ 803b618:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
+ 803b61a:	2b80      	cmp	r3, #128	@ 0x80
+ 803b61c:	f200 8081 	bhi.w	803b722 <HAL_RCCEx_GetPeriphCLKFreq+0x28a>
+ 803b620:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
+ 803b622:	2b00      	cmp	r3, #0
+ 803b624:	d003      	beq.n	803b62e <HAL_RCCEx_GetPeriphCLKFreq+0x196>
+ 803b626:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
+ 803b628:	2b40      	cmp	r3, #64	@ 0x40
+ 803b62a:	d014      	beq.n	803b656 <HAL_RCCEx_GetPeriphCLKFreq+0x1be>
+ 803b62c:	e079      	b.n	803b722 <HAL_RCCEx_GetPeriphCLKFreq+0x28a>
+    {
+      case RCC_SAI23CLKSOURCE_PLL: /* PLL1 is the clock source for SAI2/3 */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
+ 803b62e:	4b3f      	ldr	r3, [pc, #252]	@ (803b72c <HAL_RCCEx_GetPeriphCLKFreq+0x294>)
+ 803b630:	681b      	ldr	r3, [r3, #0]
+ 803b632:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
+ 803b636:	f1b3 7f00 	cmp.w	r3, #33554432	@ 0x2000000
+ 803b63a:	d108      	bne.n	803b64e <HAL_RCCEx_GetPeriphCLKFreq+0x1b6>
+        {
+          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+ 803b63c:	f107 0324 	add.w	r3, r7, #36	@ 0x24
+ 803b640:	4618      	mov	r0, r3
+ 803b642:	f000 ff67 	bl	803c514 <HAL_RCCEx_GetPLL1ClockFreq>
+          frequency = pll1_clocks.PLL1_Q_Frequency;
+ 803b646:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 803b648:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 803b64a:	f000 bc9c 	b.w	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+          frequency = 0;
+ 803b64e:	2300      	movs	r3, #0
+ 803b650:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803b652:	f000 bc98 	b.w	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+      }
+      case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI2/3 */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
+ 803b656:	4b35      	ldr	r3, [pc, #212]	@ (803b72c <HAL_RCCEx_GetPeriphCLKFreq+0x294>)
+ 803b658:	681b      	ldr	r3, [r3, #0]
+ 803b65a:	f003 6300 	and.w	r3, r3, #134217728	@ 0x8000000
+ 803b65e:	f1b3 6f00 	cmp.w	r3, #134217728	@ 0x8000000
+ 803b662:	d108      	bne.n	803b676 <HAL_RCCEx_GetPeriphCLKFreq+0x1de>
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+ 803b664:	f107 0318 	add.w	r3, r7, #24
+ 803b668:	4618      	mov	r0, r3
+ 803b66a:	f000 fcab 	bl	803bfc4 <HAL_RCCEx_GetPLL2ClockFreq>
+          frequency = pll2_clocks.PLL2_P_Frequency;
+ 803b66e:	69bb      	ldr	r3, [r7, #24]
+ 803b670:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 803b672:	f000 bc88 	b.w	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+          frequency = 0;
+ 803b676:	2300      	movs	r3, #0
+ 803b678:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803b67a:	f000 bc84 	b.w	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+      }
+
+      case RCC_SAI23CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI2/3 */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
+ 803b67e:	4b2b      	ldr	r3, [pc, #172]	@ (803b72c <HAL_RCCEx_GetPeriphCLKFreq+0x294>)
+ 803b680:	681b      	ldr	r3, [r3, #0]
+ 803b682:	f003 5300 	and.w	r3, r3, #536870912	@ 0x20000000
+ 803b686:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
+ 803b68a:	d108      	bne.n	803b69e <HAL_RCCEx_GetPeriphCLKFreq+0x206>
+        {
+          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+ 803b68c:	f107 030c 	add.w	r3, r7, #12
+ 803b690:	4618      	mov	r0, r3
+ 803b692:	f000 fdeb 	bl	803c26c <HAL_RCCEx_GetPLL3ClockFreq>
+          frequency = pll3_clocks.PLL3_P_Frequency;
+ 803b696:	68fb      	ldr	r3, [r7, #12]
+ 803b698:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 803b69a:	f000 bc74 	b.w	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+          frequency = 0;
+ 803b69e:	2300      	movs	r3, #0
+ 803b6a0:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803b6a2:	f000 bc70 	b.w	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+      }
+
+      case RCC_SAI23CLKSOURCE_CLKP: /* CKPER is the clock source for SAI2/3 */
+      {
+
+        ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
+ 803b6a6:	4b21      	ldr	r3, [pc, #132]	@ (803b72c <HAL_RCCEx_GetPeriphCLKFreq+0x294>)
+ 803b6a8:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
+ 803b6aa:	f003 5340 	and.w	r3, r3, #805306368	@ 0x30000000
+ 803b6ae:	637b      	str	r3, [r7, #52]	@ 0x34
+
+        if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
+ 803b6b0:	4b1e      	ldr	r3, [pc, #120]	@ (803b72c <HAL_RCCEx_GetPeriphCLKFreq+0x294>)
+ 803b6b2:	681b      	ldr	r3, [r3, #0]
+ 803b6b4:	f003 0304 	and.w	r3, r3, #4
+ 803b6b8:	2b04      	cmp	r3, #4
+ 803b6ba:	d10c      	bne.n	803b6d6 <HAL_RCCEx_GetPeriphCLKFreq+0x23e>
+ 803b6bc:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
+ 803b6be:	2b00      	cmp	r3, #0
+ 803b6c0:	d109      	bne.n	803b6d6 <HAL_RCCEx_GetPeriphCLKFreq+0x23e>
+        {
+          /* In Case the CKPER Source is HSI */
+          frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
+ 803b6c2:	4b1a      	ldr	r3, [pc, #104]	@ (803b72c <HAL_RCCEx_GetPeriphCLKFreq+0x294>)
+ 803b6c4:	681b      	ldr	r3, [r3, #0]
+ 803b6c6:	08db      	lsrs	r3, r3, #3
+ 803b6c8:	f003 0303 	and.w	r3, r3, #3
+ 803b6cc:	4a18      	ldr	r2, [pc, #96]	@ (803b730 <HAL_RCCEx_GetPeriphCLKFreq+0x298>)
+ 803b6ce:	fa22 f303 	lsr.w	r3, r2, r3
+ 803b6d2:	63fb      	str	r3, [r7, #60]	@ 0x3c
+ 803b6d4:	e01f      	b.n	803b716 <HAL_RCCEx_GetPeriphCLKFreq+0x27e>
+        }
+
+        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
+ 803b6d6:	4b15      	ldr	r3, [pc, #84]	@ (803b72c <HAL_RCCEx_GetPeriphCLKFreq+0x294>)
+ 803b6d8:	681b      	ldr	r3, [r3, #0]
+ 803b6da:	f403 7380 	and.w	r3, r3, #256	@ 0x100
+ 803b6de:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
+ 803b6e2:	d106      	bne.n	803b6f2 <HAL_RCCEx_GetPeriphCLKFreq+0x25a>
+ 803b6e4:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
+ 803b6e6:	f1b3 5f80 	cmp.w	r3, #268435456	@ 0x10000000
+ 803b6ea:	d102      	bne.n	803b6f2 <HAL_RCCEx_GetPeriphCLKFreq+0x25a>
+        {
+          /* In Case the CKPER Source is CSI */
+          frequency = CSI_VALUE;
+ 803b6ec:	4b11      	ldr	r3, [pc, #68]	@ (803b734 <HAL_RCCEx_GetPeriphCLKFreq+0x29c>)
+ 803b6ee:	63fb      	str	r3, [r7, #60]	@ 0x3c
+ 803b6f0:	e011      	b.n	803b716 <HAL_RCCEx_GetPeriphCLKFreq+0x27e>
+        }
+
+        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
+ 803b6f2:	4b0e      	ldr	r3, [pc, #56]	@ (803b72c <HAL_RCCEx_GetPeriphCLKFreq+0x294>)
+ 803b6f4:	681b      	ldr	r3, [r3, #0]
+ 803b6f6:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
+ 803b6fa:	f5b3 3f00 	cmp.w	r3, #131072	@ 0x20000
+ 803b6fe:	d106      	bne.n	803b70e <HAL_RCCEx_GetPeriphCLKFreq+0x276>
+ 803b700:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
+ 803b702:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
+ 803b706:	d102      	bne.n	803b70e <HAL_RCCEx_GetPeriphCLKFreq+0x276>
+        {
+          /* In Case the CKPER Source is HSE */
+          frequency = HSE_VALUE;
+ 803b708:	4b0b      	ldr	r3, [pc, #44]	@ (803b738 <HAL_RCCEx_GetPeriphCLKFreq+0x2a0>)
+ 803b70a:	63fb      	str	r3, [r7, #60]	@ 0x3c
+ 803b70c:	e003      	b.n	803b716 <HAL_RCCEx_GetPeriphCLKFreq+0x27e>
+        }
+
+        else
+        {
+          /* In Case the CKPER is disabled*/
+          frequency = 0;
+ 803b70e:	2300      	movs	r3, #0
+ 803b710:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        }
+
+        break;
+ 803b712:	f000 bc38 	b.w	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+ 803b716:	f000 bc36 	b.w	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+      }
+
+      case (RCC_SAI23CLKSOURCE_PIN): /* External clock is the clock source for SAI2/3 */
+      {
+        frequency = EXTERNAL_CLOCK_VALUE;
+ 803b71a:	4b08      	ldr	r3, [pc, #32]	@ (803b73c <HAL_RCCEx_GetPeriphCLKFreq+0x2a4>)
+ 803b71c:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803b71e:	f000 bc32 	b.w	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+      }
+      default :
+      {
+        frequency = 0;
+ 803b722:	2300      	movs	r3, #0
+ 803b724:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803b726:	f000 bc2e 	b.w	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+ 803b72a:	bf00      	nop
+ 803b72c:	58024400 	.word	0x58024400
+ 803b730:	03d09000 	.word	0x03d09000
+ 803b734:	003d0900 	.word	0x003d0900
+ 803b738:	017d7840 	.word	0x017d7840
+ 803b73c:	00bb8000 	.word	0x00bb8000
+    }
+  }
+#endif
+
+#if defined(SAI4)
+  else if (PeriphClk == RCC_PERIPHCLK_SAI4A)
+ 803b740:	e9d7 2300 	ldrd	r2, r3, [r7]
+ 803b744:	f5a2 6180 	sub.w	r1, r2, #1024	@ 0x400
+ 803b748:	430b      	orrs	r3, r1
+ 803b74a:	f040 809c 	bne.w	803b886 <HAL_RCCEx_GetPeriphCLKFreq+0x3ee>
+  {
+
+    saiclocksource = __HAL_RCC_GET_SAI4A_SOURCE();
+ 803b74e:	4b9e      	ldr	r3, [pc, #632]	@ (803b9c8 <HAL_RCCEx_GetPeriphCLKFreq+0x530>)
+ 803b750:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
+ 803b752:	f403 0360 	and.w	r3, r3, #14680064	@ 0xe00000
+ 803b756:	633b      	str	r3, [r7, #48]	@ 0x30
+
+    switch (saiclocksource)
+ 803b758:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
+ 803b75a:	f5b3 0f00 	cmp.w	r3, #8388608	@ 0x800000
+ 803b75e:	d054      	beq.n	803b80a <HAL_RCCEx_GetPeriphCLKFreq+0x372>
+ 803b760:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
+ 803b762:	f5b3 0f00 	cmp.w	r3, #8388608	@ 0x800000
+ 803b766:	f200 808b 	bhi.w	803b880 <HAL_RCCEx_GetPeriphCLKFreq+0x3e8>
+ 803b76a:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
+ 803b76c:	f5b3 0fc0 	cmp.w	r3, #6291456	@ 0x600000
+ 803b770:	f000 8083 	beq.w	803b87a <HAL_RCCEx_GetPeriphCLKFreq+0x3e2>
+ 803b774:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
+ 803b776:	f5b3 0fc0 	cmp.w	r3, #6291456	@ 0x600000
+ 803b77a:	f200 8081 	bhi.w	803b880 <HAL_RCCEx_GetPeriphCLKFreq+0x3e8>
+ 803b77e:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
+ 803b780:	f5b3 0f80 	cmp.w	r3, #4194304	@ 0x400000
+ 803b784:	d02f      	beq.n	803b7e6 <HAL_RCCEx_GetPeriphCLKFreq+0x34e>
+ 803b786:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
+ 803b788:	f5b3 0f80 	cmp.w	r3, #4194304	@ 0x400000
+ 803b78c:	d878      	bhi.n	803b880 <HAL_RCCEx_GetPeriphCLKFreq+0x3e8>
+ 803b78e:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
+ 803b790:	2b00      	cmp	r3, #0
+ 803b792:	d004      	beq.n	803b79e <HAL_RCCEx_GetPeriphCLKFreq+0x306>
+ 803b794:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
+ 803b796:	f5b3 1f00 	cmp.w	r3, #2097152	@ 0x200000
+ 803b79a:	d012      	beq.n	803b7c2 <HAL_RCCEx_GetPeriphCLKFreq+0x32a>
+ 803b79c:	e070      	b.n	803b880 <HAL_RCCEx_GetPeriphCLKFreq+0x3e8>
+    {
+      case RCC_SAI4ACLKSOURCE_PLL: /* PLL1 is the clock source for SAI4A */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
+ 803b79e:	4b8a      	ldr	r3, [pc, #552]	@ (803b9c8 <HAL_RCCEx_GetPeriphCLKFreq+0x530>)
+ 803b7a0:	681b      	ldr	r3, [r3, #0]
+ 803b7a2:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
+ 803b7a6:	f1b3 7f00 	cmp.w	r3, #33554432	@ 0x2000000
+ 803b7aa:	d107      	bne.n	803b7bc <HAL_RCCEx_GetPeriphCLKFreq+0x324>
+        {
+          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+ 803b7ac:	f107 0324 	add.w	r3, r7, #36	@ 0x24
+ 803b7b0:	4618      	mov	r0, r3
+ 803b7b2:	f000 feaf 	bl	803c514 <HAL_RCCEx_GetPLL1ClockFreq>
+          frequency = pll1_clocks.PLL1_Q_Frequency;
+ 803b7b6:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 803b7b8:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 803b7ba:	e3e4      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+          frequency = 0;
+ 803b7bc:	2300      	movs	r3, #0
+ 803b7be:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803b7c0:	e3e1      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+      }
+      case RCC_SAI4ACLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI4A */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
+ 803b7c2:	4b81      	ldr	r3, [pc, #516]	@ (803b9c8 <HAL_RCCEx_GetPeriphCLKFreq+0x530>)
+ 803b7c4:	681b      	ldr	r3, [r3, #0]
+ 803b7c6:	f003 6300 	and.w	r3, r3, #134217728	@ 0x8000000
+ 803b7ca:	f1b3 6f00 	cmp.w	r3, #134217728	@ 0x8000000
+ 803b7ce:	d107      	bne.n	803b7e0 <HAL_RCCEx_GetPeriphCLKFreq+0x348>
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+ 803b7d0:	f107 0318 	add.w	r3, r7, #24
+ 803b7d4:	4618      	mov	r0, r3
+ 803b7d6:	f000 fbf5 	bl	803bfc4 <HAL_RCCEx_GetPLL2ClockFreq>
+          frequency = pll2_clocks.PLL2_P_Frequency;
+ 803b7da:	69bb      	ldr	r3, [r7, #24]
+ 803b7dc:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 803b7de:	e3d2      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+          frequency = 0;
+ 803b7e0:	2300      	movs	r3, #0
+ 803b7e2:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803b7e4:	e3cf      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+      }
+
+      case RCC_SAI4ACLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI4A */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
+ 803b7e6:	4b78      	ldr	r3, [pc, #480]	@ (803b9c8 <HAL_RCCEx_GetPeriphCLKFreq+0x530>)
+ 803b7e8:	681b      	ldr	r3, [r3, #0]
+ 803b7ea:	f003 5300 	and.w	r3, r3, #536870912	@ 0x20000000
+ 803b7ee:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
+ 803b7f2:	d107      	bne.n	803b804 <HAL_RCCEx_GetPeriphCLKFreq+0x36c>
+        {
+          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+ 803b7f4:	f107 030c 	add.w	r3, r7, #12
+ 803b7f8:	4618      	mov	r0, r3
+ 803b7fa:	f000 fd37 	bl	803c26c <HAL_RCCEx_GetPLL3ClockFreq>
+          frequency = pll3_clocks.PLL3_P_Frequency;
+ 803b7fe:	68fb      	ldr	r3, [r7, #12]
+ 803b800:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 803b802:	e3c0      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+          frequency = 0;
+ 803b804:	2300      	movs	r3, #0
+ 803b806:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803b808:	e3bd      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+      }
+
+      case RCC_SAI4ACLKSOURCE_CLKP: /* CKPER is the clock source for SAI4A*/
+      {
+
+        ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
+ 803b80a:	4b6f      	ldr	r3, [pc, #444]	@ (803b9c8 <HAL_RCCEx_GetPeriphCLKFreq+0x530>)
+ 803b80c:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
+ 803b80e:	f003 5340 	and.w	r3, r3, #805306368	@ 0x30000000
+ 803b812:	637b      	str	r3, [r7, #52]	@ 0x34
+
+        if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
+ 803b814:	4b6c      	ldr	r3, [pc, #432]	@ (803b9c8 <HAL_RCCEx_GetPeriphCLKFreq+0x530>)
+ 803b816:	681b      	ldr	r3, [r3, #0]
+ 803b818:	f003 0304 	and.w	r3, r3, #4
+ 803b81c:	2b04      	cmp	r3, #4
+ 803b81e:	d10c      	bne.n	803b83a <HAL_RCCEx_GetPeriphCLKFreq+0x3a2>
+ 803b820:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
+ 803b822:	2b00      	cmp	r3, #0
+ 803b824:	d109      	bne.n	803b83a <HAL_RCCEx_GetPeriphCLKFreq+0x3a2>
+        {
+          /* In Case the CKPER Source is HSI */
+          frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
+ 803b826:	4b68      	ldr	r3, [pc, #416]	@ (803b9c8 <HAL_RCCEx_GetPeriphCLKFreq+0x530>)
+ 803b828:	681b      	ldr	r3, [r3, #0]
+ 803b82a:	08db      	lsrs	r3, r3, #3
+ 803b82c:	f003 0303 	and.w	r3, r3, #3
+ 803b830:	4a66      	ldr	r2, [pc, #408]	@ (803b9cc <HAL_RCCEx_GetPeriphCLKFreq+0x534>)
+ 803b832:	fa22 f303 	lsr.w	r3, r2, r3
+ 803b836:	63fb      	str	r3, [r7, #60]	@ 0x3c
+ 803b838:	e01e      	b.n	803b878 <HAL_RCCEx_GetPeriphCLKFreq+0x3e0>
+        }
+
+        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
+ 803b83a:	4b63      	ldr	r3, [pc, #396]	@ (803b9c8 <HAL_RCCEx_GetPeriphCLKFreq+0x530>)
+ 803b83c:	681b      	ldr	r3, [r3, #0]
+ 803b83e:	f403 7380 	and.w	r3, r3, #256	@ 0x100
+ 803b842:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
+ 803b846:	d106      	bne.n	803b856 <HAL_RCCEx_GetPeriphCLKFreq+0x3be>
+ 803b848:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
+ 803b84a:	f1b3 5f80 	cmp.w	r3, #268435456	@ 0x10000000
+ 803b84e:	d102      	bne.n	803b856 <HAL_RCCEx_GetPeriphCLKFreq+0x3be>
+        {
+          /* In Case the CKPER Source is CSI */
+          frequency = CSI_VALUE;
+ 803b850:	4b5f      	ldr	r3, [pc, #380]	@ (803b9d0 <HAL_RCCEx_GetPeriphCLKFreq+0x538>)
+ 803b852:	63fb      	str	r3, [r7, #60]	@ 0x3c
+ 803b854:	e010      	b.n	803b878 <HAL_RCCEx_GetPeriphCLKFreq+0x3e0>
+        }
+
+        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
+ 803b856:	4b5c      	ldr	r3, [pc, #368]	@ (803b9c8 <HAL_RCCEx_GetPeriphCLKFreq+0x530>)
+ 803b858:	681b      	ldr	r3, [r3, #0]
+ 803b85a:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
+ 803b85e:	f5b3 3f00 	cmp.w	r3, #131072	@ 0x20000
+ 803b862:	d106      	bne.n	803b872 <HAL_RCCEx_GetPeriphCLKFreq+0x3da>
+ 803b864:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
+ 803b866:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
+ 803b86a:	d102      	bne.n	803b872 <HAL_RCCEx_GetPeriphCLKFreq+0x3da>
+        {
+          /* In Case the CKPER Source is HSE */
+          frequency = HSE_VALUE;
+ 803b86c:	4b59      	ldr	r3, [pc, #356]	@ (803b9d4 <HAL_RCCEx_GetPeriphCLKFreq+0x53c>)
+ 803b86e:	63fb      	str	r3, [r7, #60]	@ 0x3c
+ 803b870:	e002      	b.n	803b878 <HAL_RCCEx_GetPeriphCLKFreq+0x3e0>
+        }
+
+        else
+        {
+          /* In Case the CKPER is disabled*/
+          frequency = 0;
+ 803b872:	2300      	movs	r3, #0
+ 803b874:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        }
+
+        break;
+ 803b876:	e386      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+ 803b878:	e385      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+      }
+
+      case RCC_SAI4ACLKSOURCE_PIN: /* External clock is the clock source for SAI4A */
+      {
+        frequency = EXTERNAL_CLOCK_VALUE;
+ 803b87a:	4b57      	ldr	r3, [pc, #348]	@ (803b9d8 <HAL_RCCEx_GetPeriphCLKFreq+0x540>)
+ 803b87c:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803b87e:	e382      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+      }
+
+      default :
+      {
+        frequency = 0;
+ 803b880:	2300      	movs	r3, #0
+ 803b882:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803b884:	e37f      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+      }
+    }
+  }
+
+  else if (PeriphClk == RCC_PERIPHCLK_SAI4B)
+ 803b886:	e9d7 2300 	ldrd	r2, r3, [r7]
+ 803b88a:	f5a2 6100 	sub.w	r1, r2, #2048	@ 0x800
+ 803b88e:	430b      	orrs	r3, r1
+ 803b890:	f040 80a7 	bne.w	803b9e2 <HAL_RCCEx_GetPeriphCLKFreq+0x54a>
+  {
+
+    saiclocksource = __HAL_RCC_GET_SAI4B_SOURCE();
+ 803b894:	4b4c      	ldr	r3, [pc, #304]	@ (803b9c8 <HAL_RCCEx_GetPeriphCLKFreq+0x530>)
+ 803b896:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
+ 803b898:	f003 63e0 	and.w	r3, r3, #117440512	@ 0x7000000
+ 803b89c:	633b      	str	r3, [r7, #48]	@ 0x30
+
+    switch (saiclocksource)
+ 803b89e:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
+ 803b8a0:	f1b3 6f80 	cmp.w	r3, #67108864	@ 0x4000000
+ 803b8a4:	d055      	beq.n	803b952 <HAL_RCCEx_GetPeriphCLKFreq+0x4ba>
+ 803b8a6:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
+ 803b8a8:	f1b3 6f80 	cmp.w	r3, #67108864	@ 0x4000000
+ 803b8ac:	f200 8096 	bhi.w	803b9dc <HAL_RCCEx_GetPeriphCLKFreq+0x544>
+ 803b8b0:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
+ 803b8b2:	f1b3 7f40 	cmp.w	r3, #50331648	@ 0x3000000
+ 803b8b6:	f000 8084 	beq.w	803b9c2 <HAL_RCCEx_GetPeriphCLKFreq+0x52a>
+ 803b8ba:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
+ 803b8bc:	f1b3 7f40 	cmp.w	r3, #50331648	@ 0x3000000
+ 803b8c0:	f200 808c 	bhi.w	803b9dc <HAL_RCCEx_GetPeriphCLKFreq+0x544>
+ 803b8c4:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
+ 803b8c6:	f1b3 7f00 	cmp.w	r3, #33554432	@ 0x2000000
+ 803b8ca:	d030      	beq.n	803b92e <HAL_RCCEx_GetPeriphCLKFreq+0x496>
+ 803b8cc:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
+ 803b8ce:	f1b3 7f00 	cmp.w	r3, #33554432	@ 0x2000000
+ 803b8d2:	f200 8083 	bhi.w	803b9dc <HAL_RCCEx_GetPeriphCLKFreq+0x544>
+ 803b8d6:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
+ 803b8d8:	2b00      	cmp	r3, #0
+ 803b8da:	d004      	beq.n	803b8e6 <HAL_RCCEx_GetPeriphCLKFreq+0x44e>
+ 803b8dc:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
+ 803b8de:	f1b3 7f80 	cmp.w	r3, #16777216	@ 0x1000000
+ 803b8e2:	d012      	beq.n	803b90a <HAL_RCCEx_GetPeriphCLKFreq+0x472>
+ 803b8e4:	e07a      	b.n	803b9dc <HAL_RCCEx_GetPeriphCLKFreq+0x544>
+    {
+      case RCC_SAI4BCLKSOURCE_PLL: /* PLL1 is the clock source for SAI4B */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
+ 803b8e6:	4b38      	ldr	r3, [pc, #224]	@ (803b9c8 <HAL_RCCEx_GetPeriphCLKFreq+0x530>)
+ 803b8e8:	681b      	ldr	r3, [r3, #0]
+ 803b8ea:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
+ 803b8ee:	f1b3 7f00 	cmp.w	r3, #33554432	@ 0x2000000
+ 803b8f2:	d107      	bne.n	803b904 <HAL_RCCEx_GetPeriphCLKFreq+0x46c>
+        {
+          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+ 803b8f4:	f107 0324 	add.w	r3, r7, #36	@ 0x24
+ 803b8f8:	4618      	mov	r0, r3
+ 803b8fa:	f000 fe0b 	bl	803c514 <HAL_RCCEx_GetPLL1ClockFreq>
+          frequency = pll1_clocks.PLL1_Q_Frequency;
+ 803b8fe:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 803b900:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 803b902:	e340      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+          frequency = 0;
+ 803b904:	2300      	movs	r3, #0
+ 803b906:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803b908:	e33d      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+      }
+      case RCC_SAI4BCLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI4B */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
+ 803b90a:	4b2f      	ldr	r3, [pc, #188]	@ (803b9c8 <HAL_RCCEx_GetPeriphCLKFreq+0x530>)
+ 803b90c:	681b      	ldr	r3, [r3, #0]
+ 803b90e:	f003 6300 	and.w	r3, r3, #134217728	@ 0x8000000
+ 803b912:	f1b3 6f00 	cmp.w	r3, #134217728	@ 0x8000000
+ 803b916:	d107      	bne.n	803b928 <HAL_RCCEx_GetPeriphCLKFreq+0x490>
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+ 803b918:	f107 0318 	add.w	r3, r7, #24
+ 803b91c:	4618      	mov	r0, r3
+ 803b91e:	f000 fb51 	bl	803bfc4 <HAL_RCCEx_GetPLL2ClockFreq>
+          frequency = pll2_clocks.PLL2_P_Frequency;
+ 803b922:	69bb      	ldr	r3, [r7, #24]
+ 803b924:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 803b926:	e32e      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+          frequency = 0;
+ 803b928:	2300      	movs	r3, #0
+ 803b92a:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803b92c:	e32b      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+      }
+
+      case RCC_SAI4BCLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI4B */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
+ 803b92e:	4b26      	ldr	r3, [pc, #152]	@ (803b9c8 <HAL_RCCEx_GetPeriphCLKFreq+0x530>)
+ 803b930:	681b      	ldr	r3, [r3, #0]
+ 803b932:	f003 5300 	and.w	r3, r3, #536870912	@ 0x20000000
+ 803b936:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
+ 803b93a:	d107      	bne.n	803b94c <HAL_RCCEx_GetPeriphCLKFreq+0x4b4>
+        {
+          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+ 803b93c:	f107 030c 	add.w	r3, r7, #12
+ 803b940:	4618      	mov	r0, r3
+ 803b942:	f000 fc93 	bl	803c26c <HAL_RCCEx_GetPLL3ClockFreq>
+          frequency = pll3_clocks.PLL3_P_Frequency;
+ 803b946:	68fb      	ldr	r3, [r7, #12]
+ 803b948:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 803b94a:	e31c      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+          frequency = 0;
+ 803b94c:	2300      	movs	r3, #0
+ 803b94e:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803b950:	e319      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+      }
+
+      case RCC_SAI4BCLKSOURCE_CLKP: /* CKPER is the clock source for SAI4B*/
+      {
+
+        ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
+ 803b952:	4b1d      	ldr	r3, [pc, #116]	@ (803b9c8 <HAL_RCCEx_GetPeriphCLKFreq+0x530>)
+ 803b954:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
+ 803b956:	f003 5340 	and.w	r3, r3, #805306368	@ 0x30000000
+ 803b95a:	637b      	str	r3, [r7, #52]	@ 0x34
+
+        if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
+ 803b95c:	4b1a      	ldr	r3, [pc, #104]	@ (803b9c8 <HAL_RCCEx_GetPeriphCLKFreq+0x530>)
+ 803b95e:	681b      	ldr	r3, [r3, #0]
+ 803b960:	f003 0304 	and.w	r3, r3, #4
+ 803b964:	2b04      	cmp	r3, #4
+ 803b966:	d10c      	bne.n	803b982 <HAL_RCCEx_GetPeriphCLKFreq+0x4ea>
+ 803b968:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
+ 803b96a:	2b00      	cmp	r3, #0
+ 803b96c:	d109      	bne.n	803b982 <HAL_RCCEx_GetPeriphCLKFreq+0x4ea>
+        {
+          /* In Case the CKPER Source is HSI */
+          frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
+ 803b96e:	4b16      	ldr	r3, [pc, #88]	@ (803b9c8 <HAL_RCCEx_GetPeriphCLKFreq+0x530>)
+ 803b970:	681b      	ldr	r3, [r3, #0]
+ 803b972:	08db      	lsrs	r3, r3, #3
+ 803b974:	f003 0303 	and.w	r3, r3, #3
+ 803b978:	4a14      	ldr	r2, [pc, #80]	@ (803b9cc <HAL_RCCEx_GetPeriphCLKFreq+0x534>)
+ 803b97a:	fa22 f303 	lsr.w	r3, r2, r3
+ 803b97e:	63fb      	str	r3, [r7, #60]	@ 0x3c
+ 803b980:	e01e      	b.n	803b9c0 <HAL_RCCEx_GetPeriphCLKFreq+0x528>
+        }
+
+        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
+ 803b982:	4b11      	ldr	r3, [pc, #68]	@ (803b9c8 <HAL_RCCEx_GetPeriphCLKFreq+0x530>)
+ 803b984:	681b      	ldr	r3, [r3, #0]
+ 803b986:	f403 7380 	and.w	r3, r3, #256	@ 0x100
+ 803b98a:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
+ 803b98e:	d106      	bne.n	803b99e <HAL_RCCEx_GetPeriphCLKFreq+0x506>
+ 803b990:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
+ 803b992:	f1b3 5f80 	cmp.w	r3, #268435456	@ 0x10000000
+ 803b996:	d102      	bne.n	803b99e <HAL_RCCEx_GetPeriphCLKFreq+0x506>
+        {
+          /* In Case the CKPER Source is CSI */
+          frequency = CSI_VALUE;
+ 803b998:	4b0d      	ldr	r3, [pc, #52]	@ (803b9d0 <HAL_RCCEx_GetPeriphCLKFreq+0x538>)
+ 803b99a:	63fb      	str	r3, [r7, #60]	@ 0x3c
+ 803b99c:	e010      	b.n	803b9c0 <HAL_RCCEx_GetPeriphCLKFreq+0x528>
+        }
+
+        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
+ 803b99e:	4b0a      	ldr	r3, [pc, #40]	@ (803b9c8 <HAL_RCCEx_GetPeriphCLKFreq+0x530>)
+ 803b9a0:	681b      	ldr	r3, [r3, #0]
+ 803b9a2:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
+ 803b9a6:	f5b3 3f00 	cmp.w	r3, #131072	@ 0x20000
+ 803b9aa:	d106      	bne.n	803b9ba <HAL_RCCEx_GetPeriphCLKFreq+0x522>
+ 803b9ac:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
+ 803b9ae:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
+ 803b9b2:	d102      	bne.n	803b9ba <HAL_RCCEx_GetPeriphCLKFreq+0x522>
+        {
+          /* In Case the CKPER Source is HSE */
+          frequency = HSE_VALUE;
+ 803b9b4:	4b07      	ldr	r3, [pc, #28]	@ (803b9d4 <HAL_RCCEx_GetPeriphCLKFreq+0x53c>)
+ 803b9b6:	63fb      	str	r3, [r7, #60]	@ 0x3c
+ 803b9b8:	e002      	b.n	803b9c0 <HAL_RCCEx_GetPeriphCLKFreq+0x528>
+        }
+
+        else
+        {
+          /* In Case the CKPER is disabled*/
+          frequency = 0;
+ 803b9ba:	2300      	movs	r3, #0
+ 803b9bc:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        }
+
+        break;
+ 803b9be:	e2e2      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+ 803b9c0:	e2e1      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+      }
+
+      case RCC_SAI4BCLKSOURCE_PIN: /* External clock is the clock source for SAI4B */
+      {
+        frequency = EXTERNAL_CLOCK_VALUE;
+ 803b9c2:	4b05      	ldr	r3, [pc, #20]	@ (803b9d8 <HAL_RCCEx_GetPeriphCLKFreq+0x540>)
+ 803b9c4:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803b9c6:	e2de      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+ 803b9c8:	58024400 	.word	0x58024400
+ 803b9cc:	03d09000 	.word	0x03d09000
+ 803b9d0:	003d0900 	.word	0x003d0900
+ 803b9d4:	017d7840 	.word	0x017d7840
+ 803b9d8:	00bb8000 	.word	0x00bb8000
+      }
+
+      default :
+      {
+        frequency = 0;
+ 803b9dc:	2300      	movs	r3, #0
+ 803b9de:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803b9e0:	e2d1      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+      }
+    }
+  }
+#endif /*SAI4*/
+  else if (PeriphClk == RCC_PERIPHCLK_SPI123)
+ 803b9e2:	e9d7 2300 	ldrd	r2, r3, [r7]
+ 803b9e6:	f5a2 5180 	sub.w	r1, r2, #4096	@ 0x1000
+ 803b9ea:	430b      	orrs	r3, r1
+ 803b9ec:	f040 809c 	bne.w	803bb28 <HAL_RCCEx_GetPeriphCLKFreq+0x690>
+  {
+    /* Get SPI1/2/3 clock source */
+    srcclk = __HAL_RCC_GET_SPI123_SOURCE();
+ 803b9f0:	4b93      	ldr	r3, [pc, #588]	@ (803bc40 <HAL_RCCEx_GetPeriphCLKFreq+0x7a8>)
+ 803b9f2:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
+ 803b9f4:	f403 43e0 	and.w	r3, r3, #28672	@ 0x7000
+ 803b9f8:	63bb      	str	r3, [r7, #56]	@ 0x38
+
+    switch (srcclk)
+ 803b9fa:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 803b9fc:	f5b3 4f80 	cmp.w	r3, #16384	@ 0x4000
+ 803ba00:	d054      	beq.n	803baac <HAL_RCCEx_GetPeriphCLKFreq+0x614>
+ 803ba02:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 803ba04:	f5b3 4f80 	cmp.w	r3, #16384	@ 0x4000
+ 803ba08:	f200 808b 	bhi.w	803bb22 <HAL_RCCEx_GetPeriphCLKFreq+0x68a>
+ 803ba0c:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 803ba0e:	f5b3 5f40 	cmp.w	r3, #12288	@ 0x3000
+ 803ba12:	f000 8083 	beq.w	803bb1c <HAL_RCCEx_GetPeriphCLKFreq+0x684>
+ 803ba16:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 803ba18:	f5b3 5f40 	cmp.w	r3, #12288	@ 0x3000
+ 803ba1c:	f200 8081 	bhi.w	803bb22 <HAL_RCCEx_GetPeriphCLKFreq+0x68a>
+ 803ba20:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 803ba22:	f5b3 5f00 	cmp.w	r3, #8192	@ 0x2000
+ 803ba26:	d02f      	beq.n	803ba88 <HAL_RCCEx_GetPeriphCLKFreq+0x5f0>
+ 803ba28:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 803ba2a:	f5b3 5f00 	cmp.w	r3, #8192	@ 0x2000
+ 803ba2e:	d878      	bhi.n	803bb22 <HAL_RCCEx_GetPeriphCLKFreq+0x68a>
+ 803ba30:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 803ba32:	2b00      	cmp	r3, #0
+ 803ba34:	d004      	beq.n	803ba40 <HAL_RCCEx_GetPeriphCLKFreq+0x5a8>
+ 803ba36:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 803ba38:	f5b3 5f80 	cmp.w	r3, #4096	@ 0x1000
+ 803ba3c:	d012      	beq.n	803ba64 <HAL_RCCEx_GetPeriphCLKFreq+0x5cc>
+ 803ba3e:	e070      	b.n	803bb22 <HAL_RCCEx_GetPeriphCLKFreq+0x68a>
+    {
+      case RCC_SPI123CLKSOURCE_PLL: /* PLL1 is the clock source for SPI123 */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
+ 803ba40:	4b7f      	ldr	r3, [pc, #508]	@ (803bc40 <HAL_RCCEx_GetPeriphCLKFreq+0x7a8>)
+ 803ba42:	681b      	ldr	r3, [r3, #0]
+ 803ba44:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
+ 803ba48:	f1b3 7f00 	cmp.w	r3, #33554432	@ 0x2000000
+ 803ba4c:	d107      	bne.n	803ba5e <HAL_RCCEx_GetPeriphCLKFreq+0x5c6>
+        {
+          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+ 803ba4e:	f107 0324 	add.w	r3, r7, #36	@ 0x24
+ 803ba52:	4618      	mov	r0, r3
+ 803ba54:	f000 fd5e 	bl	803c514 <HAL_RCCEx_GetPLL1ClockFreq>
+          frequency = pll1_clocks.PLL1_Q_Frequency;
+ 803ba58:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 803ba5a:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 803ba5c:	e293      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+          frequency = 0;
+ 803ba5e:	2300      	movs	r3, #0
+ 803ba60:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803ba62:	e290      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+      }
+      case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI123 */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
+ 803ba64:	4b76      	ldr	r3, [pc, #472]	@ (803bc40 <HAL_RCCEx_GetPeriphCLKFreq+0x7a8>)
+ 803ba66:	681b      	ldr	r3, [r3, #0]
+ 803ba68:	f003 6300 	and.w	r3, r3, #134217728	@ 0x8000000
+ 803ba6c:	f1b3 6f00 	cmp.w	r3, #134217728	@ 0x8000000
+ 803ba70:	d107      	bne.n	803ba82 <HAL_RCCEx_GetPeriphCLKFreq+0x5ea>
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+ 803ba72:	f107 0318 	add.w	r3, r7, #24
+ 803ba76:	4618      	mov	r0, r3
+ 803ba78:	f000 faa4 	bl	803bfc4 <HAL_RCCEx_GetPLL2ClockFreq>
+          frequency = pll2_clocks.PLL2_P_Frequency;
+ 803ba7c:	69bb      	ldr	r3, [r7, #24]
+ 803ba7e:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 803ba80:	e281      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+          frequency = 0;
+ 803ba82:	2300      	movs	r3, #0
+ 803ba84:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803ba86:	e27e      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+      }
+
+      case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI123 */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
+ 803ba88:	4b6d      	ldr	r3, [pc, #436]	@ (803bc40 <HAL_RCCEx_GetPeriphCLKFreq+0x7a8>)
+ 803ba8a:	681b      	ldr	r3, [r3, #0]
+ 803ba8c:	f003 5300 	and.w	r3, r3, #536870912	@ 0x20000000
+ 803ba90:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
+ 803ba94:	d107      	bne.n	803baa6 <HAL_RCCEx_GetPeriphCLKFreq+0x60e>
+        {
+          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+ 803ba96:	f107 030c 	add.w	r3, r7, #12
+ 803ba9a:	4618      	mov	r0, r3
+ 803ba9c:	f000 fbe6 	bl	803c26c <HAL_RCCEx_GetPLL3ClockFreq>
+          frequency = pll3_clocks.PLL3_P_Frequency;
+ 803baa0:	68fb      	ldr	r3, [r7, #12]
+ 803baa2:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 803baa4:	e26f      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+          frequency = 0;
+ 803baa6:	2300      	movs	r3, #0
+ 803baa8:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803baaa:	e26c      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+      }
+
+      case RCC_SPI123CLKSOURCE_CLKP: /* CKPER is the clock source for SPI123 */
+      {
+
+        ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
+ 803baac:	4b64      	ldr	r3, [pc, #400]	@ (803bc40 <HAL_RCCEx_GetPeriphCLKFreq+0x7a8>)
+ 803baae:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
+ 803bab0:	f003 5340 	and.w	r3, r3, #805306368	@ 0x30000000
+ 803bab4:	637b      	str	r3, [r7, #52]	@ 0x34
+
+        if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
+ 803bab6:	4b62      	ldr	r3, [pc, #392]	@ (803bc40 <HAL_RCCEx_GetPeriphCLKFreq+0x7a8>)
+ 803bab8:	681b      	ldr	r3, [r3, #0]
+ 803baba:	f003 0304 	and.w	r3, r3, #4
+ 803babe:	2b04      	cmp	r3, #4
+ 803bac0:	d10c      	bne.n	803badc <HAL_RCCEx_GetPeriphCLKFreq+0x644>
+ 803bac2:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
+ 803bac4:	2b00      	cmp	r3, #0
+ 803bac6:	d109      	bne.n	803badc <HAL_RCCEx_GetPeriphCLKFreq+0x644>
+        {
+          /* In Case the CKPER Source is HSI */
+          frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
+ 803bac8:	4b5d      	ldr	r3, [pc, #372]	@ (803bc40 <HAL_RCCEx_GetPeriphCLKFreq+0x7a8>)
+ 803baca:	681b      	ldr	r3, [r3, #0]
+ 803bacc:	08db      	lsrs	r3, r3, #3
+ 803bace:	f003 0303 	and.w	r3, r3, #3
+ 803bad2:	4a5c      	ldr	r2, [pc, #368]	@ (803bc44 <HAL_RCCEx_GetPeriphCLKFreq+0x7ac>)
+ 803bad4:	fa22 f303 	lsr.w	r3, r2, r3
+ 803bad8:	63fb      	str	r3, [r7, #60]	@ 0x3c
+ 803bada:	e01e      	b.n	803bb1a <HAL_RCCEx_GetPeriphCLKFreq+0x682>
+        }
+
+        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
+ 803badc:	4b58      	ldr	r3, [pc, #352]	@ (803bc40 <HAL_RCCEx_GetPeriphCLKFreq+0x7a8>)
+ 803bade:	681b      	ldr	r3, [r3, #0]
+ 803bae0:	f403 7380 	and.w	r3, r3, #256	@ 0x100
+ 803bae4:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
+ 803bae8:	d106      	bne.n	803baf8 <HAL_RCCEx_GetPeriphCLKFreq+0x660>
+ 803baea:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
+ 803baec:	f1b3 5f80 	cmp.w	r3, #268435456	@ 0x10000000
+ 803baf0:	d102      	bne.n	803baf8 <HAL_RCCEx_GetPeriphCLKFreq+0x660>
+        {
+          /* In Case the CKPER Source is CSI */
+          frequency = CSI_VALUE;
+ 803baf2:	4b55      	ldr	r3, [pc, #340]	@ (803bc48 <HAL_RCCEx_GetPeriphCLKFreq+0x7b0>)
+ 803baf4:	63fb      	str	r3, [r7, #60]	@ 0x3c
+ 803baf6:	e010      	b.n	803bb1a <HAL_RCCEx_GetPeriphCLKFreq+0x682>
+        }
+
+        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
+ 803baf8:	4b51      	ldr	r3, [pc, #324]	@ (803bc40 <HAL_RCCEx_GetPeriphCLKFreq+0x7a8>)
+ 803bafa:	681b      	ldr	r3, [r3, #0]
+ 803bafc:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
+ 803bb00:	f5b3 3f00 	cmp.w	r3, #131072	@ 0x20000
+ 803bb04:	d106      	bne.n	803bb14 <HAL_RCCEx_GetPeriphCLKFreq+0x67c>
+ 803bb06:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
+ 803bb08:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
+ 803bb0c:	d102      	bne.n	803bb14 <HAL_RCCEx_GetPeriphCLKFreq+0x67c>
+        {
+          /* In Case the CKPER Source is HSE */
+          frequency = HSE_VALUE;
+ 803bb0e:	4b4f      	ldr	r3, [pc, #316]	@ (803bc4c <HAL_RCCEx_GetPeriphCLKFreq+0x7b4>)
+ 803bb10:	63fb      	str	r3, [r7, #60]	@ 0x3c
+ 803bb12:	e002      	b.n	803bb1a <HAL_RCCEx_GetPeriphCLKFreq+0x682>
+        }
+
+        else
+        {
+          /* In Case the CKPER is disabled*/
+          frequency = 0;
+ 803bb14:	2300      	movs	r3, #0
+ 803bb16:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        }
+
+        break;
+ 803bb18:	e235      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+ 803bb1a:	e234      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+      }
+
+      case (RCC_SPI123CLKSOURCE_PIN): /* External clock is the clock source for I2S */
+      {
+        frequency = EXTERNAL_CLOCK_VALUE;
+ 803bb1c:	4b4c      	ldr	r3, [pc, #304]	@ (803bc50 <HAL_RCCEx_GetPeriphCLKFreq+0x7b8>)
+ 803bb1e:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803bb20:	e231      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+      }
+      default :
+      {
+        frequency = 0;
+ 803bb22:	2300      	movs	r3, #0
+ 803bb24:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803bb26:	e22e      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+      }
+    }
+  }
+  else if (PeriphClk == RCC_PERIPHCLK_SPI45)
+ 803bb28:	e9d7 2300 	ldrd	r2, r3, [r7]
+ 803bb2c:	f5a2 5100 	sub.w	r1, r2, #8192	@ 0x2000
+ 803bb30:	430b      	orrs	r3, r1
+ 803bb32:	f040 808f 	bne.w	803bc54 <HAL_RCCEx_GetPeriphCLKFreq+0x7bc>
+  {
+    /* Get SPI45 clock source */
+    srcclk = __HAL_RCC_GET_SPI45_SOURCE();
+ 803bb36:	4b42      	ldr	r3, [pc, #264]	@ (803bc40 <HAL_RCCEx_GetPeriphCLKFreq+0x7a8>)
+ 803bb38:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
+ 803bb3a:	f403 23e0 	and.w	r3, r3, #458752	@ 0x70000
+ 803bb3e:	63bb      	str	r3, [r7, #56]	@ 0x38
+    switch (srcclk)
+ 803bb40:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 803bb42:	f5b3 2fa0 	cmp.w	r3, #327680	@ 0x50000
+ 803bb46:	d06b      	beq.n	803bc20 <HAL_RCCEx_GetPeriphCLKFreq+0x788>
+ 803bb48:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 803bb4a:	f5b3 2fa0 	cmp.w	r3, #327680	@ 0x50000
+ 803bb4e:	d874      	bhi.n	803bc3a <HAL_RCCEx_GetPeriphCLKFreq+0x7a2>
+ 803bb50:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 803bb52:	f5b3 2f80 	cmp.w	r3, #262144	@ 0x40000
+ 803bb56:	d056      	beq.n	803bc06 <HAL_RCCEx_GetPeriphCLKFreq+0x76e>
+ 803bb58:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 803bb5a:	f5b3 2f80 	cmp.w	r3, #262144	@ 0x40000
+ 803bb5e:	d86c      	bhi.n	803bc3a <HAL_RCCEx_GetPeriphCLKFreq+0x7a2>
+ 803bb60:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 803bb62:	f5b3 3f40 	cmp.w	r3, #196608	@ 0x30000
+ 803bb66:	d03b      	beq.n	803bbe0 <HAL_RCCEx_GetPeriphCLKFreq+0x748>
+ 803bb68:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 803bb6a:	f5b3 3f40 	cmp.w	r3, #196608	@ 0x30000
+ 803bb6e:	d864      	bhi.n	803bc3a <HAL_RCCEx_GetPeriphCLKFreq+0x7a2>
+ 803bb70:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 803bb72:	f5b3 3f00 	cmp.w	r3, #131072	@ 0x20000
+ 803bb76:	d021      	beq.n	803bbbc <HAL_RCCEx_GetPeriphCLKFreq+0x724>
+ 803bb78:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 803bb7a:	f5b3 3f00 	cmp.w	r3, #131072	@ 0x20000
+ 803bb7e:	d85c      	bhi.n	803bc3a <HAL_RCCEx_GetPeriphCLKFreq+0x7a2>
+ 803bb80:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 803bb82:	2b00      	cmp	r3, #0
+ 803bb84:	d004      	beq.n	803bb90 <HAL_RCCEx_GetPeriphCLKFreq+0x6f8>
+ 803bb86:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 803bb88:	f5b3 3f80 	cmp.w	r3, #65536	@ 0x10000
+ 803bb8c:	d004      	beq.n	803bb98 <HAL_RCCEx_GetPeriphCLKFreq+0x700>
+ 803bb8e:	e054      	b.n	803bc3a <HAL_RCCEx_GetPeriphCLKFreq+0x7a2>
+    {
+      case RCC_SPI45CLKSOURCE_PCLK2: /* CD/D2 PCLK2 is the clock source for SPI4/5 */
+      {
+        frequency = HAL_RCC_GetPCLK1Freq();
+ 803bb90:	f7fe fa30 	bl	8039ff4 <HAL_RCC_GetPCLK1Freq>
+ 803bb94:	63f8      	str	r0, [r7, #60]	@ 0x3c
+        break;
+ 803bb96:	e1f6      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+      }
+      case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI45 */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
+ 803bb98:	4b29      	ldr	r3, [pc, #164]	@ (803bc40 <HAL_RCCEx_GetPeriphCLKFreq+0x7a8>)
+ 803bb9a:	681b      	ldr	r3, [r3, #0]
+ 803bb9c:	f003 6300 	and.w	r3, r3, #134217728	@ 0x8000000
+ 803bba0:	f1b3 6f00 	cmp.w	r3, #134217728	@ 0x8000000
+ 803bba4:	d107      	bne.n	803bbb6 <HAL_RCCEx_GetPeriphCLKFreq+0x71e>
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+ 803bba6:	f107 0318 	add.w	r3, r7, #24
+ 803bbaa:	4618      	mov	r0, r3
+ 803bbac:	f000 fa0a 	bl	803bfc4 <HAL_RCCEx_GetPLL2ClockFreq>
+          frequency = pll2_clocks.PLL2_Q_Frequency;
+ 803bbb0:	69fb      	ldr	r3, [r7, #28]
+ 803bbb2:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 803bbb4:	e1e7      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+          frequency = 0;
+ 803bbb6:	2300      	movs	r3, #0
+ 803bbb8:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803bbba:	e1e4      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+      }
+      case RCC_SPI45CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI45 */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
+ 803bbbc:	4b20      	ldr	r3, [pc, #128]	@ (803bc40 <HAL_RCCEx_GetPeriphCLKFreq+0x7a8>)
+ 803bbbe:	681b      	ldr	r3, [r3, #0]
+ 803bbc0:	f003 5300 	and.w	r3, r3, #536870912	@ 0x20000000
+ 803bbc4:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
+ 803bbc8:	d107      	bne.n	803bbda <HAL_RCCEx_GetPeriphCLKFreq+0x742>
+        {
+          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+ 803bbca:	f107 030c 	add.w	r3, r7, #12
+ 803bbce:	4618      	mov	r0, r3
+ 803bbd0:	f000 fb4c 	bl	803c26c <HAL_RCCEx_GetPLL3ClockFreq>
+          frequency = pll3_clocks.PLL3_Q_Frequency;
+ 803bbd4:	693b      	ldr	r3, [r7, #16]
+ 803bbd6:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 803bbd8:	e1d5      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+          frequency = 0;
+ 803bbda:	2300      	movs	r3, #0
+ 803bbdc:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803bbde:	e1d2      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+      }
+      case RCC_SPI45CLKSOURCE_HSI: /* HSI is the clock source for SPI45 */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
+ 803bbe0:	4b17      	ldr	r3, [pc, #92]	@ (803bc40 <HAL_RCCEx_GetPeriphCLKFreq+0x7a8>)
+ 803bbe2:	681b      	ldr	r3, [r3, #0]
+ 803bbe4:	f003 0304 	and.w	r3, r3, #4
+ 803bbe8:	2b04      	cmp	r3, #4
+ 803bbea:	d109      	bne.n	803bc00 <HAL_RCCEx_GetPeriphCLKFreq+0x768>
+        {
+          frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
+ 803bbec:	4b14      	ldr	r3, [pc, #80]	@ (803bc40 <HAL_RCCEx_GetPeriphCLKFreq+0x7a8>)
+ 803bbee:	681b      	ldr	r3, [r3, #0]
+ 803bbf0:	08db      	lsrs	r3, r3, #3
+ 803bbf2:	f003 0303 	and.w	r3, r3, #3
+ 803bbf6:	4a13      	ldr	r2, [pc, #76]	@ (803bc44 <HAL_RCCEx_GetPeriphCLKFreq+0x7ac>)
+ 803bbf8:	fa22 f303 	lsr.w	r3, r2, r3
+ 803bbfc:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 803bbfe:	e1c2      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+          frequency = 0;
+ 803bc00:	2300      	movs	r3, #0
+ 803bc02:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803bc04:	e1bf      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+      }
+      case RCC_SPI45CLKSOURCE_CSI: /* CSI is the clock source for SPI45 */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY))
+ 803bc06:	4b0e      	ldr	r3, [pc, #56]	@ (803bc40 <HAL_RCCEx_GetPeriphCLKFreq+0x7a8>)
+ 803bc08:	681b      	ldr	r3, [r3, #0]
+ 803bc0a:	f403 7380 	and.w	r3, r3, #256	@ 0x100
+ 803bc0e:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
+ 803bc12:	d102      	bne.n	803bc1a <HAL_RCCEx_GetPeriphCLKFreq+0x782>
+        {
+          frequency = CSI_VALUE;
+ 803bc14:	4b0c      	ldr	r3, [pc, #48]	@ (803bc48 <HAL_RCCEx_GetPeriphCLKFreq+0x7b0>)
+ 803bc16:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 803bc18:	e1b5      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+          frequency = 0;
+ 803bc1a:	2300      	movs	r3, #0
+ 803bc1c:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803bc1e:	e1b2      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+      }
+      case RCC_SPI45CLKSOURCE_HSE: /* HSE is the clock source for SPI45 */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
+ 803bc20:	4b07      	ldr	r3, [pc, #28]	@ (803bc40 <HAL_RCCEx_GetPeriphCLKFreq+0x7a8>)
+ 803bc22:	681b      	ldr	r3, [r3, #0]
+ 803bc24:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
+ 803bc28:	f5b3 3f00 	cmp.w	r3, #131072	@ 0x20000
+ 803bc2c:	d102      	bne.n	803bc34 <HAL_RCCEx_GetPeriphCLKFreq+0x79c>
+        {
+          frequency = HSE_VALUE;
+ 803bc2e:	4b07      	ldr	r3, [pc, #28]	@ (803bc4c <HAL_RCCEx_GetPeriphCLKFreq+0x7b4>)
+ 803bc30:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 803bc32:	e1a8      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+          frequency = 0;
+ 803bc34:	2300      	movs	r3, #0
+ 803bc36:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803bc38:	e1a5      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+      }
+      default :
+      {
+        frequency = 0;
+ 803bc3a:	2300      	movs	r3, #0
+ 803bc3c:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803bc3e:	e1a2      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+ 803bc40:	58024400 	.word	0x58024400
+ 803bc44:	03d09000 	.word	0x03d09000
+ 803bc48:	003d0900 	.word	0x003d0900
+ 803bc4c:	017d7840 	.word	0x017d7840
+ 803bc50:	00bb8000 	.word	0x00bb8000
+      }
+    }
+  }
+  else if (PeriphClk == RCC_PERIPHCLK_ADC)
+ 803bc54:	e9d7 2300 	ldrd	r2, r3, [r7]
+ 803bc58:	f5a2 2100 	sub.w	r1, r2, #524288	@ 0x80000
+ 803bc5c:	430b      	orrs	r3, r1
+ 803bc5e:	d173      	bne.n	803bd48 <HAL_RCCEx_GetPeriphCLKFreq+0x8b0>
+  {
+    /* Get ADC clock source */
+    srcclk = __HAL_RCC_GET_ADC_SOURCE();
+ 803bc60:	4b9c      	ldr	r3, [pc, #624]	@ (803bed4 <HAL_RCCEx_GetPeriphCLKFreq+0xa3c>)
+ 803bc62:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
+ 803bc64:	f403 3340 	and.w	r3, r3, #196608	@ 0x30000
+ 803bc68:	63bb      	str	r3, [r7, #56]	@ 0x38
+
+    switch (srcclk)
+ 803bc6a:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 803bc6c:	f5b3 3f00 	cmp.w	r3, #131072	@ 0x20000
+ 803bc70:	d02f      	beq.n	803bcd2 <HAL_RCCEx_GetPeriphCLKFreq+0x83a>
+ 803bc72:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 803bc74:	f5b3 3f00 	cmp.w	r3, #131072	@ 0x20000
+ 803bc78:	d863      	bhi.n	803bd42 <HAL_RCCEx_GetPeriphCLKFreq+0x8aa>
+ 803bc7a:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 803bc7c:	2b00      	cmp	r3, #0
+ 803bc7e:	d004      	beq.n	803bc8a <HAL_RCCEx_GetPeriphCLKFreq+0x7f2>
+ 803bc80:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 803bc82:	f5b3 3f80 	cmp.w	r3, #65536	@ 0x10000
+ 803bc86:	d012      	beq.n	803bcae <HAL_RCCEx_GetPeriphCLKFreq+0x816>
+ 803bc88:	e05b      	b.n	803bd42 <HAL_RCCEx_GetPeriphCLKFreq+0x8aa>
+    {
+      case RCC_ADCCLKSOURCE_PLL2:
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
+ 803bc8a:	4b92      	ldr	r3, [pc, #584]	@ (803bed4 <HAL_RCCEx_GetPeriphCLKFreq+0xa3c>)
+ 803bc8c:	681b      	ldr	r3, [r3, #0]
+ 803bc8e:	f003 6300 	and.w	r3, r3, #134217728	@ 0x8000000
+ 803bc92:	f1b3 6f00 	cmp.w	r3, #134217728	@ 0x8000000
+ 803bc96:	d107      	bne.n	803bca8 <HAL_RCCEx_GetPeriphCLKFreq+0x810>
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+ 803bc98:	f107 0318 	add.w	r3, r7, #24
+ 803bc9c:	4618      	mov	r0, r3
+ 803bc9e:	f000 f991 	bl	803bfc4 <HAL_RCCEx_GetPLL2ClockFreq>
+          frequency = pll2_clocks.PLL2_P_Frequency;
+ 803bca2:	69bb      	ldr	r3, [r7, #24]
+ 803bca4:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 803bca6:	e16e      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+          frequency = 0;
+ 803bca8:	2300      	movs	r3, #0
+ 803bcaa:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803bcac:	e16b      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+      }
+      case RCC_ADCCLKSOURCE_PLL3:
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
+ 803bcae:	4b89      	ldr	r3, [pc, #548]	@ (803bed4 <HAL_RCCEx_GetPeriphCLKFreq+0xa3c>)
+ 803bcb0:	681b      	ldr	r3, [r3, #0]
+ 803bcb2:	f003 5300 	and.w	r3, r3, #536870912	@ 0x20000000
+ 803bcb6:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
+ 803bcba:	d107      	bne.n	803bccc <HAL_RCCEx_GetPeriphCLKFreq+0x834>
+        {
+          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+ 803bcbc:	f107 030c 	add.w	r3, r7, #12
+ 803bcc0:	4618      	mov	r0, r3
+ 803bcc2:	f000 fad3 	bl	803c26c <HAL_RCCEx_GetPLL3ClockFreq>
+          frequency = pll3_clocks.PLL3_R_Frequency;
+ 803bcc6:	697b      	ldr	r3, [r7, #20]
+ 803bcc8:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 803bcca:	e15c      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+          frequency = 0;
+ 803bccc:	2300      	movs	r3, #0
+ 803bcce:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803bcd0:	e159      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+      }
+
+      case RCC_ADCCLKSOURCE_CLKP:
+      {
+
+        ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
+ 803bcd2:	4b80      	ldr	r3, [pc, #512]	@ (803bed4 <HAL_RCCEx_GetPeriphCLKFreq+0xa3c>)
+ 803bcd4:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
+ 803bcd6:	f003 5340 	and.w	r3, r3, #805306368	@ 0x30000000
+ 803bcda:	637b      	str	r3, [r7, #52]	@ 0x34
+
+        if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
+ 803bcdc:	4b7d      	ldr	r3, [pc, #500]	@ (803bed4 <HAL_RCCEx_GetPeriphCLKFreq+0xa3c>)
+ 803bcde:	681b      	ldr	r3, [r3, #0]
+ 803bce0:	f003 0304 	and.w	r3, r3, #4
+ 803bce4:	2b04      	cmp	r3, #4
+ 803bce6:	d10c      	bne.n	803bd02 <HAL_RCCEx_GetPeriphCLKFreq+0x86a>
+ 803bce8:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
+ 803bcea:	2b00      	cmp	r3, #0
+ 803bcec:	d109      	bne.n	803bd02 <HAL_RCCEx_GetPeriphCLKFreq+0x86a>
+        {
+          /* In Case the CKPER Source is HSI */
+          frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
+ 803bcee:	4b79      	ldr	r3, [pc, #484]	@ (803bed4 <HAL_RCCEx_GetPeriphCLKFreq+0xa3c>)
+ 803bcf0:	681b      	ldr	r3, [r3, #0]
+ 803bcf2:	08db      	lsrs	r3, r3, #3
+ 803bcf4:	f003 0303 	and.w	r3, r3, #3
+ 803bcf8:	4a77      	ldr	r2, [pc, #476]	@ (803bed8 <HAL_RCCEx_GetPeriphCLKFreq+0xa40>)
+ 803bcfa:	fa22 f303 	lsr.w	r3, r2, r3
+ 803bcfe:	63fb      	str	r3, [r7, #60]	@ 0x3c
+ 803bd00:	e01e      	b.n	803bd40 <HAL_RCCEx_GetPeriphCLKFreq+0x8a8>
+        }
+
+        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
+ 803bd02:	4b74      	ldr	r3, [pc, #464]	@ (803bed4 <HAL_RCCEx_GetPeriphCLKFreq+0xa3c>)
+ 803bd04:	681b      	ldr	r3, [r3, #0]
+ 803bd06:	f403 7380 	and.w	r3, r3, #256	@ 0x100
+ 803bd0a:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
+ 803bd0e:	d106      	bne.n	803bd1e <HAL_RCCEx_GetPeriphCLKFreq+0x886>
+ 803bd10:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
+ 803bd12:	f1b3 5f80 	cmp.w	r3, #268435456	@ 0x10000000
+ 803bd16:	d102      	bne.n	803bd1e <HAL_RCCEx_GetPeriphCLKFreq+0x886>
+        {
+          /* In Case the CKPER Source is CSI */
+          frequency = CSI_VALUE;
+ 803bd18:	4b70      	ldr	r3, [pc, #448]	@ (803bedc <HAL_RCCEx_GetPeriphCLKFreq+0xa44>)
+ 803bd1a:	63fb      	str	r3, [r7, #60]	@ 0x3c
+ 803bd1c:	e010      	b.n	803bd40 <HAL_RCCEx_GetPeriphCLKFreq+0x8a8>
+        }
+
+        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
+ 803bd1e:	4b6d      	ldr	r3, [pc, #436]	@ (803bed4 <HAL_RCCEx_GetPeriphCLKFreq+0xa3c>)
+ 803bd20:	681b      	ldr	r3, [r3, #0]
+ 803bd22:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
+ 803bd26:	f5b3 3f00 	cmp.w	r3, #131072	@ 0x20000
+ 803bd2a:	d106      	bne.n	803bd3a <HAL_RCCEx_GetPeriphCLKFreq+0x8a2>
+ 803bd2c:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
+ 803bd2e:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
+ 803bd32:	d102      	bne.n	803bd3a <HAL_RCCEx_GetPeriphCLKFreq+0x8a2>
+        {
+          /* In Case the CKPER Source is HSE */
+          frequency = HSE_VALUE;
+ 803bd34:	4b6a      	ldr	r3, [pc, #424]	@ (803bee0 <HAL_RCCEx_GetPeriphCLKFreq+0xa48>)
+ 803bd36:	63fb      	str	r3, [r7, #60]	@ 0x3c
+ 803bd38:	e002      	b.n	803bd40 <HAL_RCCEx_GetPeriphCLKFreq+0x8a8>
+        }
+
+        else
+        {
+          /* In Case the CKPER is disabled*/
+          frequency = 0;
+ 803bd3a:	2300      	movs	r3, #0
+ 803bd3c:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        }
+
+        break;
+ 803bd3e:	e122      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+ 803bd40:	e121      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+      }
+
+      default :
+      {
+        frequency = 0;
+ 803bd42:	2300      	movs	r3, #0
+ 803bd44:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803bd46:	e11e      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+      }
+    }
+  }
+  else if (PeriphClk == RCC_PERIPHCLK_SDMMC)
+ 803bd48:	e9d7 2300 	ldrd	r2, r3, [r7]
+ 803bd4c:	f5a2 3180 	sub.w	r1, r2, #65536	@ 0x10000
+ 803bd50:	430b      	orrs	r3, r1
+ 803bd52:	d133      	bne.n	803bdbc <HAL_RCCEx_GetPeriphCLKFreq+0x924>
+  {
+    /* Get SDMMC clock source */
+    srcclk = __HAL_RCC_GET_SDMMC_SOURCE();
+ 803bd54:	4b5f      	ldr	r3, [pc, #380]	@ (803bed4 <HAL_RCCEx_GetPeriphCLKFreq+0xa3c>)
+ 803bd56:	6cdb      	ldr	r3, [r3, #76]	@ 0x4c
+ 803bd58:	f403 3380 	and.w	r3, r3, #65536	@ 0x10000
+ 803bd5c:	63bb      	str	r3, [r7, #56]	@ 0x38
+
+    switch (srcclk)
+ 803bd5e:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 803bd60:	2b00      	cmp	r3, #0
+ 803bd62:	d004      	beq.n	803bd6e <HAL_RCCEx_GetPeriphCLKFreq+0x8d6>
+ 803bd64:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 803bd66:	f5b3 3f80 	cmp.w	r3, #65536	@ 0x10000
+ 803bd6a:	d012      	beq.n	803bd92 <HAL_RCCEx_GetPeriphCLKFreq+0x8fa>
+ 803bd6c:	e023      	b.n	803bdb6 <HAL_RCCEx_GetPeriphCLKFreq+0x91e>
+    {
+      case RCC_SDMMCCLKSOURCE_PLL: /* PLL1 is the clock source for SDMMC */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
+ 803bd6e:	4b59      	ldr	r3, [pc, #356]	@ (803bed4 <HAL_RCCEx_GetPeriphCLKFreq+0xa3c>)
+ 803bd70:	681b      	ldr	r3, [r3, #0]
+ 803bd72:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
+ 803bd76:	f1b3 7f00 	cmp.w	r3, #33554432	@ 0x2000000
+ 803bd7a:	d107      	bne.n	803bd8c <HAL_RCCEx_GetPeriphCLKFreq+0x8f4>
+        {
+          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+ 803bd7c:	f107 0324 	add.w	r3, r7, #36	@ 0x24
+ 803bd80:	4618      	mov	r0, r3
+ 803bd82:	f000 fbc7 	bl	803c514 <HAL_RCCEx_GetPLL1ClockFreq>
+          frequency = pll1_clocks.PLL1_Q_Frequency;
+ 803bd86:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 803bd88:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 803bd8a:	e0fc      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+          frequency = 0;
+ 803bd8c:	2300      	movs	r3, #0
+ 803bd8e:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803bd90:	e0f9      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+      }
+      case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is the clock source for SDMMC */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
+ 803bd92:	4b50      	ldr	r3, [pc, #320]	@ (803bed4 <HAL_RCCEx_GetPeriphCLKFreq+0xa3c>)
+ 803bd94:	681b      	ldr	r3, [r3, #0]
+ 803bd96:	f003 6300 	and.w	r3, r3, #134217728	@ 0x8000000
+ 803bd9a:	f1b3 6f00 	cmp.w	r3, #134217728	@ 0x8000000
+ 803bd9e:	d107      	bne.n	803bdb0 <HAL_RCCEx_GetPeriphCLKFreq+0x918>
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+ 803bda0:	f107 0318 	add.w	r3, r7, #24
+ 803bda4:	4618      	mov	r0, r3
+ 803bda6:	f000 f90d 	bl	803bfc4 <HAL_RCCEx_GetPLL2ClockFreq>
+          frequency = pll2_clocks.PLL2_R_Frequency;
+ 803bdaa:	6a3b      	ldr	r3, [r7, #32]
+ 803bdac:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 803bdae:	e0ea      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+          frequency = 0;
+ 803bdb0:	2300      	movs	r3, #0
+ 803bdb2:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803bdb4:	e0e7      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+      }
+
+      default :
+      {
+        frequency = 0;
+ 803bdb6:	2300      	movs	r3, #0
+ 803bdb8:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803bdba:	e0e4      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+      }
+    }
+  }
+  else if (PeriphClk == RCC_PERIPHCLK_SPI6)
+ 803bdbc:	e9d7 2300 	ldrd	r2, r3, [r7]
+ 803bdc0:	f5a2 4180 	sub.w	r1, r2, #16384	@ 0x4000
+ 803bdc4:	430b      	orrs	r3, r1
+ 803bdc6:	f040 808d 	bne.w	803bee4 <HAL_RCCEx_GetPeriphCLKFreq+0xa4c>
+  {
+    /* Get SPI6 clock source */
+    srcclk = __HAL_RCC_GET_SPI6_SOURCE();
+ 803bdca:	4b42      	ldr	r3, [pc, #264]	@ (803bed4 <HAL_RCCEx_GetPeriphCLKFreq+0xa3c>)
+ 803bdcc:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
+ 803bdce:	f003 43e0 	and.w	r3, r3, #1879048192	@ 0x70000000
+ 803bdd2:	63bb      	str	r3, [r7, #56]	@ 0x38
+
+    switch (srcclk)
+ 803bdd4:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 803bdd6:	f1b3 4fa0 	cmp.w	r3, #1342177280	@ 0x50000000
+ 803bdda:	d06b      	beq.n	803beb4 <HAL_RCCEx_GetPeriphCLKFreq+0xa1c>
+ 803bddc:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 803bdde:	f1b3 4fa0 	cmp.w	r3, #1342177280	@ 0x50000000
+ 803bde2:	d874      	bhi.n	803bece <HAL_RCCEx_GetPeriphCLKFreq+0xa36>
+ 803bde4:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 803bde6:	f1b3 4f80 	cmp.w	r3, #1073741824	@ 0x40000000
+ 803bdea:	d056      	beq.n	803be9a <HAL_RCCEx_GetPeriphCLKFreq+0xa02>
+ 803bdec:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 803bdee:	f1b3 4f80 	cmp.w	r3, #1073741824	@ 0x40000000
+ 803bdf2:	d86c      	bhi.n	803bece <HAL_RCCEx_GetPeriphCLKFreq+0xa36>
+ 803bdf4:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 803bdf6:	f1b3 5f40 	cmp.w	r3, #805306368	@ 0x30000000
+ 803bdfa:	d03b      	beq.n	803be74 <HAL_RCCEx_GetPeriphCLKFreq+0x9dc>
+ 803bdfc:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 803bdfe:	f1b3 5f40 	cmp.w	r3, #805306368	@ 0x30000000
+ 803be02:	d864      	bhi.n	803bece <HAL_RCCEx_GetPeriphCLKFreq+0xa36>
+ 803be04:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 803be06:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
+ 803be0a:	d021      	beq.n	803be50 <HAL_RCCEx_GetPeriphCLKFreq+0x9b8>
+ 803be0c:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 803be0e:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
+ 803be12:	d85c      	bhi.n	803bece <HAL_RCCEx_GetPeriphCLKFreq+0xa36>
+ 803be14:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 803be16:	2b00      	cmp	r3, #0
+ 803be18:	d004      	beq.n	803be24 <HAL_RCCEx_GetPeriphCLKFreq+0x98c>
+ 803be1a:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 803be1c:	f1b3 5f80 	cmp.w	r3, #268435456	@ 0x10000000
+ 803be20:	d004      	beq.n	803be2c <HAL_RCCEx_GetPeriphCLKFreq+0x994>
+ 803be22:	e054      	b.n	803bece <HAL_RCCEx_GetPeriphCLKFreq+0xa36>
+    {
+      case RCC_SPI6CLKSOURCE_D3PCLK1: /* D3PCLK1 (PCLK4) is the clock source for SPI6 */
+      {
+        frequency = HAL_RCCEx_GetD3PCLK1Freq();
+ 803be24:	f000 f8b8 	bl	803bf98 <HAL_RCCEx_GetD3PCLK1Freq>
+ 803be28:	63f8      	str	r0, [r7, #60]	@ 0x3c
+        break;
+ 803be2a:	e0ac      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+      }
+      case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI6 */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
+ 803be2c:	4b29      	ldr	r3, [pc, #164]	@ (803bed4 <HAL_RCCEx_GetPeriphCLKFreq+0xa3c>)
+ 803be2e:	681b      	ldr	r3, [r3, #0]
+ 803be30:	f003 6300 	and.w	r3, r3, #134217728	@ 0x8000000
+ 803be34:	f1b3 6f00 	cmp.w	r3, #134217728	@ 0x8000000
+ 803be38:	d107      	bne.n	803be4a <HAL_RCCEx_GetPeriphCLKFreq+0x9b2>
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+ 803be3a:	f107 0318 	add.w	r3, r7, #24
+ 803be3e:	4618      	mov	r0, r3
+ 803be40:	f000 f8c0 	bl	803bfc4 <HAL_RCCEx_GetPLL2ClockFreq>
+          frequency = pll2_clocks.PLL2_Q_Frequency;
+ 803be44:	69fb      	ldr	r3, [r7, #28]
+ 803be46:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 803be48:	e09d      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+          frequency = 0;
+ 803be4a:	2300      	movs	r3, #0
+ 803be4c:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803be4e:	e09a      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+      }
+      case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI6 */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
+ 803be50:	4b20      	ldr	r3, [pc, #128]	@ (803bed4 <HAL_RCCEx_GetPeriphCLKFreq+0xa3c>)
+ 803be52:	681b      	ldr	r3, [r3, #0]
+ 803be54:	f003 5300 	and.w	r3, r3, #536870912	@ 0x20000000
+ 803be58:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
+ 803be5c:	d107      	bne.n	803be6e <HAL_RCCEx_GetPeriphCLKFreq+0x9d6>
+        {
+          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+ 803be5e:	f107 030c 	add.w	r3, r7, #12
+ 803be62:	4618      	mov	r0, r3
+ 803be64:	f000 fa02 	bl	803c26c <HAL_RCCEx_GetPLL3ClockFreq>
+          frequency = pll3_clocks.PLL3_Q_Frequency;
+ 803be68:	693b      	ldr	r3, [r7, #16]
+ 803be6a:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 803be6c:	e08b      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+          frequency = 0;
+ 803be6e:	2300      	movs	r3, #0
+ 803be70:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803be72:	e088      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+      }
+      case RCC_SPI6CLKSOURCE_HSI: /* HSI is the clock source for SPI6 */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
+ 803be74:	4b17      	ldr	r3, [pc, #92]	@ (803bed4 <HAL_RCCEx_GetPeriphCLKFreq+0xa3c>)
+ 803be76:	681b      	ldr	r3, [r3, #0]
+ 803be78:	f003 0304 	and.w	r3, r3, #4
+ 803be7c:	2b04      	cmp	r3, #4
+ 803be7e:	d109      	bne.n	803be94 <HAL_RCCEx_GetPeriphCLKFreq+0x9fc>
+        {
+          frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
+ 803be80:	4b14      	ldr	r3, [pc, #80]	@ (803bed4 <HAL_RCCEx_GetPeriphCLKFreq+0xa3c>)
+ 803be82:	681b      	ldr	r3, [r3, #0]
+ 803be84:	08db      	lsrs	r3, r3, #3
+ 803be86:	f003 0303 	and.w	r3, r3, #3
+ 803be8a:	4a13      	ldr	r2, [pc, #76]	@ (803bed8 <HAL_RCCEx_GetPeriphCLKFreq+0xa40>)
+ 803be8c:	fa22 f303 	lsr.w	r3, r2, r3
+ 803be90:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 803be92:	e078      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+          frequency = 0;
+ 803be94:	2300      	movs	r3, #0
+ 803be96:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803be98:	e075      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+      }
+      case RCC_SPI6CLKSOURCE_CSI: /* CSI is the clock source for SPI6 */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY))
+ 803be9a:	4b0e      	ldr	r3, [pc, #56]	@ (803bed4 <HAL_RCCEx_GetPeriphCLKFreq+0xa3c>)
+ 803be9c:	681b      	ldr	r3, [r3, #0]
+ 803be9e:	f403 7380 	and.w	r3, r3, #256	@ 0x100
+ 803bea2:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
+ 803bea6:	d102      	bne.n	803beae <HAL_RCCEx_GetPeriphCLKFreq+0xa16>
+        {
+          frequency = CSI_VALUE;
+ 803bea8:	4b0c      	ldr	r3, [pc, #48]	@ (803bedc <HAL_RCCEx_GetPeriphCLKFreq+0xa44>)
+ 803beaa:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 803beac:	e06b      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+          frequency = 0;
+ 803beae:	2300      	movs	r3, #0
+ 803beb0:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803beb2:	e068      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+      }
+      case RCC_SPI6CLKSOURCE_HSE: /* HSE is the clock source for SPI6 */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
+ 803beb4:	4b07      	ldr	r3, [pc, #28]	@ (803bed4 <HAL_RCCEx_GetPeriphCLKFreq+0xa3c>)
+ 803beb6:	681b      	ldr	r3, [r3, #0]
+ 803beb8:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
+ 803bebc:	f5b3 3f00 	cmp.w	r3, #131072	@ 0x20000
+ 803bec0:	d102      	bne.n	803bec8 <HAL_RCCEx_GetPeriphCLKFreq+0xa30>
+        {
+          frequency = HSE_VALUE;
+ 803bec2:	4b07      	ldr	r3, [pc, #28]	@ (803bee0 <HAL_RCCEx_GetPeriphCLKFreq+0xa48>)
+ 803bec4:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 803bec6:	e05e      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+          frequency = 0;
+ 803bec8:	2300      	movs	r3, #0
+ 803beca:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803becc:	e05b      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+        break;
+      }
+#endif /* RCC_SPI6CLKSOURCE_PIN */
+      default :
+      {
+        frequency = 0;
+ 803bece:	2300      	movs	r3, #0
+ 803bed0:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803bed2:	e058      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+ 803bed4:	58024400 	.word	0x58024400
+ 803bed8:	03d09000 	.word	0x03d09000
+ 803bedc:	003d0900 	.word	0x003d0900
+ 803bee0:	017d7840 	.word	0x017d7840
+      }
+    }
+  }
+  else if (PeriphClk == RCC_PERIPHCLK_FDCAN)
+ 803bee4:	e9d7 2300 	ldrd	r2, r3, [r7]
+ 803bee8:	f5a2 4100 	sub.w	r1, r2, #32768	@ 0x8000
+ 803beec:	430b      	orrs	r3, r1
+ 803beee:	d148      	bne.n	803bf82 <HAL_RCCEx_GetPeriphCLKFreq+0xaea>
+  {
+    /* Get FDCAN clock source */
+    srcclk = __HAL_RCC_GET_FDCAN_SOURCE();
+ 803bef0:	4b27      	ldr	r3, [pc, #156]	@ (803bf90 <HAL_RCCEx_GetPeriphCLKFreq+0xaf8>)
+ 803bef2:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
+ 803bef4:	f003 5340 	and.w	r3, r3, #805306368	@ 0x30000000
+ 803bef8:	63bb      	str	r3, [r7, #56]	@ 0x38
+
+    switch (srcclk)
+ 803befa:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 803befc:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
+ 803bf00:	d02a      	beq.n	803bf58 <HAL_RCCEx_GetPeriphCLKFreq+0xac0>
+ 803bf02:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 803bf04:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
+ 803bf08:	d838      	bhi.n	803bf7c <HAL_RCCEx_GetPeriphCLKFreq+0xae4>
+ 803bf0a:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 803bf0c:	2b00      	cmp	r3, #0
+ 803bf0e:	d004      	beq.n	803bf1a <HAL_RCCEx_GetPeriphCLKFreq+0xa82>
+ 803bf10:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 803bf12:	f1b3 5f80 	cmp.w	r3, #268435456	@ 0x10000000
+ 803bf16:	d00d      	beq.n	803bf34 <HAL_RCCEx_GetPeriphCLKFreq+0xa9c>
+ 803bf18:	e030      	b.n	803bf7c <HAL_RCCEx_GetPeriphCLKFreq+0xae4>
+    {
+      case RCC_FDCANCLKSOURCE_HSE: /* HSE is the clock source for FDCAN */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
+ 803bf1a:	4b1d      	ldr	r3, [pc, #116]	@ (803bf90 <HAL_RCCEx_GetPeriphCLKFreq+0xaf8>)
+ 803bf1c:	681b      	ldr	r3, [r3, #0]
+ 803bf1e:	f403 3300 	and.w	r3, r3, #131072	@ 0x20000
+ 803bf22:	f5b3 3f00 	cmp.w	r3, #131072	@ 0x20000
+ 803bf26:	d102      	bne.n	803bf2e <HAL_RCCEx_GetPeriphCLKFreq+0xa96>
+        {
+          frequency = HSE_VALUE;
+ 803bf28:	4b1a      	ldr	r3, [pc, #104]	@ (803bf94 <HAL_RCCEx_GetPeriphCLKFreq+0xafc>)
+ 803bf2a:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 803bf2c:	e02b      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+          frequency = 0;
+ 803bf2e:	2300      	movs	r3, #0
+ 803bf30:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803bf32:	e028      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+      }
+      case RCC_FDCANCLKSOURCE_PLL: /* PLL is the clock source for FDCAN */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
+ 803bf34:	4b16      	ldr	r3, [pc, #88]	@ (803bf90 <HAL_RCCEx_GetPeriphCLKFreq+0xaf8>)
+ 803bf36:	681b      	ldr	r3, [r3, #0]
+ 803bf38:	f003 7300 	and.w	r3, r3, #33554432	@ 0x2000000
+ 803bf3c:	f1b3 7f00 	cmp.w	r3, #33554432	@ 0x2000000
+ 803bf40:	d107      	bne.n	803bf52 <HAL_RCCEx_GetPeriphCLKFreq+0xaba>
+        {
+          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+ 803bf42:	f107 0324 	add.w	r3, r7, #36	@ 0x24
+ 803bf46:	4618      	mov	r0, r3
+ 803bf48:	f000 fae4 	bl	803c514 <HAL_RCCEx_GetPLL1ClockFreq>
+          frequency = pll1_clocks.PLL1_Q_Frequency;
+ 803bf4c:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 803bf4e:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 803bf50:	e019      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+          frequency = 0;
+ 803bf52:	2300      	movs	r3, #0
+ 803bf54:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803bf56:	e016      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+      }
+      case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is the clock source for FDCAN */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
+ 803bf58:	4b0d      	ldr	r3, [pc, #52]	@ (803bf90 <HAL_RCCEx_GetPeriphCLKFreq+0xaf8>)
+ 803bf5a:	681b      	ldr	r3, [r3, #0]
+ 803bf5c:	f003 6300 	and.w	r3, r3, #134217728	@ 0x8000000
+ 803bf60:	f1b3 6f00 	cmp.w	r3, #134217728	@ 0x8000000
+ 803bf64:	d107      	bne.n	803bf76 <HAL_RCCEx_GetPeriphCLKFreq+0xade>
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+ 803bf66:	f107 0318 	add.w	r3, r7, #24
+ 803bf6a:	4618      	mov	r0, r3
+ 803bf6c:	f000 f82a 	bl	803bfc4 <HAL_RCCEx_GetPLL2ClockFreq>
+          frequency = pll2_clocks.PLL2_Q_Frequency;
+ 803bf70:	69fb      	ldr	r3, [r7, #28]
+ 803bf72:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+ 803bf74:	e007      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+          frequency = 0;
+ 803bf76:	2300      	movs	r3, #0
+ 803bf78:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803bf7a:	e004      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+      }
+      default :
+      {
+        frequency = 0;
+ 803bf7c:	2300      	movs	r3, #0
+ 803bf7e:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803bf80:	e001      	b.n	803bf86 <HAL_RCCEx_GetPeriphCLKFreq+0xaee>
+      }
+    }
+  }
+  else
+  {
+    frequency = 0;
+ 803bf82:	2300      	movs	r3, #0
+ 803bf84:	63fb      	str	r3, [r7, #60]	@ 0x3c
+  }
+
+  return frequency;
+ 803bf86:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
+}
+ 803bf88:	4618      	mov	r0, r3
+ 803bf8a:	3740      	adds	r7, #64	@ 0x40
+ 803bf8c:	46bd      	mov	sp, r7
+ 803bf8e:	bd80      	pop	{r7, pc}
+ 803bf90:	58024400 	.word	0x58024400
+ 803bf94:	017d7840 	.word	0x017d7840
+
+0803bf98 <HAL_RCCEx_GetD3PCLK1Freq>:
+  * @note   Each time D3PCLK1 changes, this function must be called to update the
+  *         right D3PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
+  * @retval D3PCLK1 frequency
+  */
+uint32_t HAL_RCCEx_GetD3PCLK1Freq(void)
+{
+ 803bf98:	b580      	push	{r7, lr}
+ 803bf9a:	af00      	add	r7, sp, #0
+#if defined(RCC_D3CFGR_D3PPRE)
+  /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/
+  return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D3CFGR & RCC_D3CFGR_D3PPRE) >> RCC_D3CFGR_D3PPRE_Pos] & 0x1FU));
+ 803bf9c:	f7fd fffa 	bl	8039f94 <HAL_RCC_GetHCLKFreq>
+ 803bfa0:	4602      	mov	r2, r0
+ 803bfa2:	4b06      	ldr	r3, [pc, #24]	@ (803bfbc <HAL_RCCEx_GetD3PCLK1Freq+0x24>)
+ 803bfa4:	6a1b      	ldr	r3, [r3, #32]
+ 803bfa6:	091b      	lsrs	r3, r3, #4
+ 803bfa8:	f003 0307 	and.w	r3, r3, #7
+ 803bfac:	4904      	ldr	r1, [pc, #16]	@ (803bfc0 <HAL_RCCEx_GetD3PCLK1Freq+0x28>)
+ 803bfae:	5ccb      	ldrb	r3, [r1, r3]
+ 803bfb0:	f003 031f 	and.w	r3, r3, #31
+ 803bfb4:	fa22 f303 	lsr.w	r3, r2, r3
+#else
+  /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/
+  return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE) >> RCC_SRDCFGR_SRDPPRE_Pos] & 0x1FU));
+#endif
+}
+ 803bfb8:	4618      	mov	r0, r3
+ 803bfba:	bd80      	pop	{r7, pc}
+ 803bfbc:	58024400 	.word	0x58024400
+ 803bfc0:	08041c58 	.word	0x08041c58
+
+0803bfc4 <HAL_RCCEx_GetPLL2ClockFreq>:
+  *         right PLL2CLK value. Otherwise, any configuration based on this function will be incorrect.
+  * @param  PLL2_Clocks structure.
+  * @retval None
+  */
+void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks)
+{
+ 803bfc4:	b480      	push	{r7}
+ 803bfc6:	b089      	sub	sp, #36	@ 0x24
+ 803bfc8:	af00      	add	r7, sp, #0
+ 803bfca:	6078      	str	r0, [r7, #4]
+  float_t fracn2, pll2vco;
+
+  /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL2M) * PLL2N
+     PLL2xCLK = PLL2_VCO / PLL2x
+  */
+  pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
+ 803bfcc:	4ba1      	ldr	r3, [pc, #644]	@ (803c254 <HAL_RCCEx_GetPLL2ClockFreq+0x290>)
+ 803bfce:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 803bfd0:	f003 0303 	and.w	r3, r3, #3
+ 803bfd4:	61bb      	str	r3, [r7, #24]
+  pll2m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2) >> 12);
+ 803bfd6:	4b9f      	ldr	r3, [pc, #636]	@ (803c254 <HAL_RCCEx_GetPLL2ClockFreq+0x290>)
+ 803bfd8:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 803bfda:	0b1b      	lsrs	r3, r3, #12
+ 803bfdc:	f003 033f 	and.w	r3, r3, #63	@ 0x3f
+ 803bfe0:	617b      	str	r3, [r7, #20]
+  pll2fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL2FRACEN) >> RCC_PLLCFGR_PLL2FRACEN_Pos;
+ 803bfe2:	4b9c      	ldr	r3, [pc, #624]	@ (803c254 <HAL_RCCEx_GetPLL2ClockFreq+0x290>)
+ 803bfe4:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 803bfe6:	091b      	lsrs	r3, r3, #4
+ 803bfe8:	f003 0301 	and.w	r3, r3, #1
+ 803bfec:	613b      	str	r3, [r7, #16]
+  fracn2 = (float_t)(uint32_t)(pll2fracen * ((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACN2) >> 3));
+ 803bfee:	4b99      	ldr	r3, [pc, #612]	@ (803c254 <HAL_RCCEx_GetPLL2ClockFreq+0x290>)
+ 803bff0:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 803bff2:	08db      	lsrs	r3, r3, #3
+ 803bff4:	f3c3 030c 	ubfx	r3, r3, #0, #13
+ 803bff8:	693a      	ldr	r2, [r7, #16]
+ 803bffa:	fb02 f303 	mul.w	r3, r2, r3
+ 803bffe:	ee07 3a90 	vmov	s15, r3
+ 803c002:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 803c006:	edc7 7a03 	vstr	s15, [r7, #12]
+
+  if (pll2m != 0U)
+ 803c00a:	697b      	ldr	r3, [r7, #20]
+ 803c00c:	2b00      	cmp	r3, #0
+ 803c00e:	f000 8111 	beq.w	803c234 <HAL_RCCEx_GetPLL2ClockFreq+0x270>
+  {
+    switch (pllsource)
+ 803c012:	69bb      	ldr	r3, [r7, #24]
+ 803c014:	2b02      	cmp	r3, #2
+ 803c016:	f000 8083 	beq.w	803c120 <HAL_RCCEx_GetPLL2ClockFreq+0x15c>
+ 803c01a:	69bb      	ldr	r3, [r7, #24]
+ 803c01c:	2b02      	cmp	r3, #2
+ 803c01e:	f200 80a1 	bhi.w	803c164 <HAL_RCCEx_GetPLL2ClockFreq+0x1a0>
+ 803c022:	69bb      	ldr	r3, [r7, #24]
+ 803c024:	2b00      	cmp	r3, #0
+ 803c026:	d003      	beq.n	803c030 <HAL_RCCEx_GetPLL2ClockFreq+0x6c>
+ 803c028:	69bb      	ldr	r3, [r7, #24]
+ 803c02a:	2b01      	cmp	r3, #1
+ 803c02c:	d056      	beq.n	803c0dc <HAL_RCCEx_GetPLL2ClockFreq+0x118>
+ 803c02e:	e099      	b.n	803c164 <HAL_RCCEx_GetPLL2ClockFreq+0x1a0>
+    {
+
+      case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
+
+        if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
+ 803c030:	4b88      	ldr	r3, [pc, #544]	@ (803c254 <HAL_RCCEx_GetPLL2ClockFreq+0x290>)
+ 803c032:	681b      	ldr	r3, [r3, #0]
+ 803c034:	f003 0320 	and.w	r3, r3, #32
+ 803c038:	2b00      	cmp	r3, #0
+ 803c03a:	d02d      	beq.n	803c098 <HAL_RCCEx_GetPLL2ClockFreq+0xd4>
+        {
+          hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
+ 803c03c:	4b85      	ldr	r3, [pc, #532]	@ (803c254 <HAL_RCCEx_GetPLL2ClockFreq+0x290>)
+ 803c03e:	681b      	ldr	r3, [r3, #0]
+ 803c040:	08db      	lsrs	r3, r3, #3
+ 803c042:	f003 0303 	and.w	r3, r3, #3
+ 803c046:	4a84      	ldr	r2, [pc, #528]	@ (803c258 <HAL_RCCEx_GetPLL2ClockFreq+0x294>)
+ 803c048:	fa22 f303 	lsr.w	r3, r2, r3
+ 803c04c:	60bb      	str	r3, [r7, #8]
+          pll2vco = ((float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1);
+ 803c04e:	68bb      	ldr	r3, [r7, #8]
+ 803c050:	ee07 3a90 	vmov	s15, r3
+ 803c054:	eef8 6a67 	vcvt.f32.u32	s13, s15
+ 803c058:	697b      	ldr	r3, [r7, #20]
+ 803c05a:	ee07 3a90 	vmov	s15, r3
+ 803c05e:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 803c062:	ee86 7aa7 	vdiv.f32	s14, s13, s15
+ 803c066:	4b7b      	ldr	r3, [pc, #492]	@ (803c254 <HAL_RCCEx_GetPLL2ClockFreq+0x290>)
+ 803c068:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
+ 803c06a:	f3c3 0308 	ubfx	r3, r3, #0, #9
+ 803c06e:	ee07 3a90 	vmov	s15, r3
+ 803c072:	eef8 6a67 	vcvt.f32.u32	s13, s15
+ 803c076:	ed97 6a03 	vldr	s12, [r7, #12]
+ 803c07a:	eddf 5a78 	vldr	s11, [pc, #480]	@ 803c25c <HAL_RCCEx_GetPLL2ClockFreq+0x298>
+ 803c07e:	eec6 7a25 	vdiv.f32	s15, s12, s11
+ 803c082:	ee76 7aa7 	vadd.f32	s15, s13, s15
+ 803c086:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
+ 803c08a:	ee77 7aa6 	vadd.f32	s15, s15, s13
+ 803c08e:	ee67 7a27 	vmul.f32	s15, s14, s15
+ 803c092:	edc7 7a07 	vstr	s15, [r7, #28]
+        }
+        else
+        {
+          pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1);
+        }
+        break;
+ 803c096:	e087      	b.n	803c1a8 <HAL_RCCEx_GetPLL2ClockFreq+0x1e4>
+          pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1);
+ 803c098:	697b      	ldr	r3, [r7, #20]
+ 803c09a:	ee07 3a90 	vmov	s15, r3
+ 803c09e:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 803c0a2:	eddf 6a6f 	vldr	s13, [pc, #444]	@ 803c260 <HAL_RCCEx_GetPLL2ClockFreq+0x29c>
+ 803c0a6:	ee86 7aa7 	vdiv.f32	s14, s13, s15
+ 803c0aa:	4b6a      	ldr	r3, [pc, #424]	@ (803c254 <HAL_RCCEx_GetPLL2ClockFreq+0x290>)
+ 803c0ac:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
+ 803c0ae:	f3c3 0308 	ubfx	r3, r3, #0, #9
+ 803c0b2:	ee07 3a90 	vmov	s15, r3
+ 803c0b6:	eef8 6a67 	vcvt.f32.u32	s13, s15
+ 803c0ba:	ed97 6a03 	vldr	s12, [r7, #12]
+ 803c0be:	eddf 5a67 	vldr	s11, [pc, #412]	@ 803c25c <HAL_RCCEx_GetPLL2ClockFreq+0x298>
+ 803c0c2:	eec6 7a25 	vdiv.f32	s15, s12, s11
+ 803c0c6:	ee76 7aa7 	vadd.f32	s15, s13, s15
+ 803c0ca:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
+ 803c0ce:	ee77 7aa6 	vadd.f32	s15, s15, s13
+ 803c0d2:	ee67 7a27 	vmul.f32	s15, s14, s15
+ 803c0d6:	edc7 7a07 	vstr	s15, [r7, #28]
+        break;
+ 803c0da:	e065      	b.n	803c1a8 <HAL_RCCEx_GetPLL2ClockFreq+0x1e4>
+
+      case RCC_PLLSOURCE_CSI:  /* CSI used as PLL clock source */
+        pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1);
+ 803c0dc:	697b      	ldr	r3, [r7, #20]
+ 803c0de:	ee07 3a90 	vmov	s15, r3
+ 803c0e2:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 803c0e6:	eddf 6a5f 	vldr	s13, [pc, #380]	@ 803c264 <HAL_RCCEx_GetPLL2ClockFreq+0x2a0>
+ 803c0ea:	ee86 7aa7 	vdiv.f32	s14, s13, s15
+ 803c0ee:	4b59      	ldr	r3, [pc, #356]	@ (803c254 <HAL_RCCEx_GetPLL2ClockFreq+0x290>)
+ 803c0f0:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
+ 803c0f2:	f3c3 0308 	ubfx	r3, r3, #0, #9
+ 803c0f6:	ee07 3a90 	vmov	s15, r3
+ 803c0fa:	eef8 6a67 	vcvt.f32.u32	s13, s15
+ 803c0fe:	ed97 6a03 	vldr	s12, [r7, #12]
+ 803c102:	eddf 5a56 	vldr	s11, [pc, #344]	@ 803c25c <HAL_RCCEx_GetPLL2ClockFreq+0x298>
+ 803c106:	eec6 7a25 	vdiv.f32	s15, s12, s11
+ 803c10a:	ee76 7aa7 	vadd.f32	s15, s13, s15
+ 803c10e:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
+ 803c112:	ee77 7aa6 	vadd.f32	s15, s15, s13
+ 803c116:	ee67 7a27 	vmul.f32	s15, s14, s15
+ 803c11a:	edc7 7a07 	vstr	s15, [r7, #28]
+        break;
+ 803c11e:	e043      	b.n	803c1a8 <HAL_RCCEx_GetPLL2ClockFreq+0x1e4>
+
+      case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
+        pll2vco = ((float_t)HSE_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1);
+ 803c120:	697b      	ldr	r3, [r7, #20]
+ 803c122:	ee07 3a90 	vmov	s15, r3
+ 803c126:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 803c12a:	eddf 6a4f 	vldr	s13, [pc, #316]	@ 803c268 <HAL_RCCEx_GetPLL2ClockFreq+0x2a4>
+ 803c12e:	ee86 7aa7 	vdiv.f32	s14, s13, s15
+ 803c132:	4b48      	ldr	r3, [pc, #288]	@ (803c254 <HAL_RCCEx_GetPLL2ClockFreq+0x290>)
+ 803c134:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
+ 803c136:	f3c3 0308 	ubfx	r3, r3, #0, #9
+ 803c13a:	ee07 3a90 	vmov	s15, r3
+ 803c13e:	eef8 6a67 	vcvt.f32.u32	s13, s15
+ 803c142:	ed97 6a03 	vldr	s12, [r7, #12]
+ 803c146:	eddf 5a45 	vldr	s11, [pc, #276]	@ 803c25c <HAL_RCCEx_GetPLL2ClockFreq+0x298>
+ 803c14a:	eec6 7a25 	vdiv.f32	s15, s12, s11
+ 803c14e:	ee76 7aa7 	vadd.f32	s15, s13, s15
+ 803c152:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
+ 803c156:	ee77 7aa6 	vadd.f32	s15, s15, s13
+ 803c15a:	ee67 7a27 	vmul.f32	s15, s14, s15
+ 803c15e:	edc7 7a07 	vstr	s15, [r7, #28]
+        break;
+ 803c162:	e021      	b.n	803c1a8 <HAL_RCCEx_GetPLL2ClockFreq+0x1e4>
+
+      default:
+        pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1);
+ 803c164:	697b      	ldr	r3, [r7, #20]
+ 803c166:	ee07 3a90 	vmov	s15, r3
+ 803c16a:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 803c16e:	eddf 6a3d 	vldr	s13, [pc, #244]	@ 803c264 <HAL_RCCEx_GetPLL2ClockFreq+0x2a0>
+ 803c172:	ee86 7aa7 	vdiv.f32	s14, s13, s15
+ 803c176:	4b37      	ldr	r3, [pc, #220]	@ (803c254 <HAL_RCCEx_GetPLL2ClockFreq+0x290>)
+ 803c178:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
+ 803c17a:	f3c3 0308 	ubfx	r3, r3, #0, #9
+ 803c17e:	ee07 3a90 	vmov	s15, r3
+ 803c182:	eef8 6a67 	vcvt.f32.u32	s13, s15
+ 803c186:	ed97 6a03 	vldr	s12, [r7, #12]
+ 803c18a:	eddf 5a34 	vldr	s11, [pc, #208]	@ 803c25c <HAL_RCCEx_GetPLL2ClockFreq+0x298>
+ 803c18e:	eec6 7a25 	vdiv.f32	s15, s12, s11
+ 803c192:	ee76 7aa7 	vadd.f32	s15, s13, s15
+ 803c196:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
+ 803c19a:	ee77 7aa6 	vadd.f32	s15, s15, s13
+ 803c19e:	ee67 7a27 	vmul.f32	s15, s14, s15
+ 803c1a2:	edc7 7a07 	vstr	s15, [r7, #28]
+        break;
+ 803c1a6:	bf00      	nop
+    }
+    PLL2_Clocks->PLL2_P_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >> 9)  + (float_t)1)) ;
+ 803c1a8:	4b2a      	ldr	r3, [pc, #168]	@ (803c254 <HAL_RCCEx_GetPLL2ClockFreq+0x290>)
+ 803c1aa:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
+ 803c1ac:	0a5b      	lsrs	r3, r3, #9
+ 803c1ae:	f003 037f 	and.w	r3, r3, #127	@ 0x7f
+ 803c1b2:	ee07 3a90 	vmov	s15, r3
+ 803c1b6:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 803c1ba:	eeb7 7a00 	vmov.f32	s14, #112	@ 0x3f800000  1.0
+ 803c1be:	ee37 7a87 	vadd.f32	s14, s15, s14
+ 803c1c2:	edd7 6a07 	vldr	s13, [r7, #28]
+ 803c1c6:	eec6 7a87 	vdiv.f32	s15, s13, s14
+ 803c1ca:	eefc 7ae7 	vcvt.u32.f32	s15, s15
+ 803c1ce:	ee17 2a90 	vmov	r2, s15
+ 803c1d2:	687b      	ldr	r3, [r7, #4]
+ 803c1d4:	601a      	str	r2, [r3, #0]
+    PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >> 16) + (float_t)1)) ;
+ 803c1d6:	4b1f      	ldr	r3, [pc, #124]	@ (803c254 <HAL_RCCEx_GetPLL2ClockFreq+0x290>)
+ 803c1d8:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
+ 803c1da:	0c1b      	lsrs	r3, r3, #16
+ 803c1dc:	f003 037f 	and.w	r3, r3, #127	@ 0x7f
+ 803c1e0:	ee07 3a90 	vmov	s15, r3
+ 803c1e4:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 803c1e8:	eeb7 7a00 	vmov.f32	s14, #112	@ 0x3f800000  1.0
+ 803c1ec:	ee37 7a87 	vadd.f32	s14, s15, s14
+ 803c1f0:	edd7 6a07 	vldr	s13, [r7, #28]
+ 803c1f4:	eec6 7a87 	vdiv.f32	s15, s13, s14
+ 803c1f8:	eefc 7ae7 	vcvt.u32.f32	s15, s15
+ 803c1fc:	ee17 2a90 	vmov	r2, s15
+ 803c200:	687b      	ldr	r3, [r7, #4]
+ 803c202:	605a      	str	r2, [r3, #4]
+    PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >> 24) + (float_t)1)) ;
+ 803c204:	4b13      	ldr	r3, [pc, #76]	@ (803c254 <HAL_RCCEx_GetPLL2ClockFreq+0x290>)
+ 803c206:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
+ 803c208:	0e1b      	lsrs	r3, r3, #24
+ 803c20a:	f003 037f 	and.w	r3, r3, #127	@ 0x7f
+ 803c20e:	ee07 3a90 	vmov	s15, r3
+ 803c212:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 803c216:	eeb7 7a00 	vmov.f32	s14, #112	@ 0x3f800000  1.0
+ 803c21a:	ee37 7a87 	vadd.f32	s14, s15, s14
+ 803c21e:	edd7 6a07 	vldr	s13, [r7, #28]
+ 803c222:	eec6 7a87 	vdiv.f32	s15, s13, s14
+ 803c226:	eefc 7ae7 	vcvt.u32.f32	s15, s15
+ 803c22a:	ee17 2a90 	vmov	r2, s15
+ 803c22e:	687b      	ldr	r3, [r7, #4]
+ 803c230:	609a      	str	r2, [r3, #8]
+  {
+    PLL2_Clocks->PLL2_P_Frequency = 0U;
+    PLL2_Clocks->PLL2_Q_Frequency = 0U;
+    PLL2_Clocks->PLL2_R_Frequency = 0U;
+  }
+}
+ 803c232:	e008      	b.n	803c246 <HAL_RCCEx_GetPLL2ClockFreq+0x282>
+    PLL2_Clocks->PLL2_P_Frequency = 0U;
+ 803c234:	687b      	ldr	r3, [r7, #4]
+ 803c236:	2200      	movs	r2, #0
+ 803c238:	601a      	str	r2, [r3, #0]
+    PLL2_Clocks->PLL2_Q_Frequency = 0U;
+ 803c23a:	687b      	ldr	r3, [r7, #4]
+ 803c23c:	2200      	movs	r2, #0
+ 803c23e:	605a      	str	r2, [r3, #4]
+    PLL2_Clocks->PLL2_R_Frequency = 0U;
+ 803c240:	687b      	ldr	r3, [r7, #4]
+ 803c242:	2200      	movs	r2, #0
+ 803c244:	609a      	str	r2, [r3, #8]
+}
+ 803c246:	bf00      	nop
+ 803c248:	3724      	adds	r7, #36	@ 0x24
+ 803c24a:	46bd      	mov	sp, r7
+ 803c24c:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 803c250:	4770      	bx	lr
+ 803c252:	bf00      	nop
+ 803c254:	58024400 	.word	0x58024400
+ 803c258:	03d09000 	.word	0x03d09000
+ 803c25c:	46000000 	.word	0x46000000
+ 803c260:	4c742400 	.word	0x4c742400
+ 803c264:	4a742400 	.word	0x4a742400
+ 803c268:	4bbebc20 	.word	0x4bbebc20
+
+0803c26c <HAL_RCCEx_GetPLL3ClockFreq>:
+  *         right PLL3CLK value. Otherwise, any configuration based on this function will be incorrect.
+  * @param  PLL3_Clocks structure.
+  * @retval None
+  */
+void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks)
+{
+ 803c26c:	b480      	push	{r7}
+ 803c26e:	b089      	sub	sp, #36	@ 0x24
+ 803c270:	af00      	add	r7, sp, #0
+ 803c272:	6078      	str	r0, [r7, #4]
+  float_t fracn3, pll3vco;
+
+  /* PLL3_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL3M) * PLL3N
+     PLL3xCLK = PLL3_VCO / PLLxR
+  */
+  pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
+ 803c274:	4ba1      	ldr	r3, [pc, #644]	@ (803c4fc <HAL_RCCEx_GetPLL3ClockFreq+0x290>)
+ 803c276:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 803c278:	f003 0303 	and.w	r3, r3, #3
+ 803c27c:	61bb      	str	r3, [r7, #24]
+  pll3m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3) >> 20)  ;
+ 803c27e:	4b9f      	ldr	r3, [pc, #636]	@ (803c4fc <HAL_RCCEx_GetPLL3ClockFreq+0x290>)
+ 803c280:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 803c282:	0d1b      	lsrs	r3, r3, #20
+ 803c284:	f003 033f 	and.w	r3, r3, #63	@ 0x3f
+ 803c288:	617b      	str	r3, [r7, #20]
+  pll3fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL3FRACEN) >> RCC_PLLCFGR_PLL3FRACEN_Pos;
+ 803c28a:	4b9c      	ldr	r3, [pc, #624]	@ (803c4fc <HAL_RCCEx_GetPLL3ClockFreq+0x290>)
+ 803c28c:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 803c28e:	0a1b      	lsrs	r3, r3, #8
+ 803c290:	f003 0301 	and.w	r3, r3, #1
+ 803c294:	613b      	str	r3, [r7, #16]
+  fracn3 = (float_t)(uint32_t)(pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACN3) >> 3));
+ 803c296:	4b99      	ldr	r3, [pc, #612]	@ (803c4fc <HAL_RCCEx_GetPLL3ClockFreq+0x290>)
+ 803c298:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
+ 803c29a:	08db      	lsrs	r3, r3, #3
+ 803c29c:	f3c3 030c 	ubfx	r3, r3, #0, #13
+ 803c2a0:	693a      	ldr	r2, [r7, #16]
+ 803c2a2:	fb02 f303 	mul.w	r3, r2, r3
+ 803c2a6:	ee07 3a90 	vmov	s15, r3
+ 803c2aa:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 803c2ae:	edc7 7a03 	vstr	s15, [r7, #12]
+
+  if (pll3m != 0U)
+ 803c2b2:	697b      	ldr	r3, [r7, #20]
+ 803c2b4:	2b00      	cmp	r3, #0
+ 803c2b6:	f000 8111 	beq.w	803c4dc <HAL_RCCEx_GetPLL3ClockFreq+0x270>
+  {
+    switch (pllsource)
+ 803c2ba:	69bb      	ldr	r3, [r7, #24]
+ 803c2bc:	2b02      	cmp	r3, #2
+ 803c2be:	f000 8083 	beq.w	803c3c8 <HAL_RCCEx_GetPLL3ClockFreq+0x15c>
+ 803c2c2:	69bb      	ldr	r3, [r7, #24]
+ 803c2c4:	2b02      	cmp	r3, #2
+ 803c2c6:	f200 80a1 	bhi.w	803c40c <HAL_RCCEx_GetPLL3ClockFreq+0x1a0>
+ 803c2ca:	69bb      	ldr	r3, [r7, #24]
+ 803c2cc:	2b00      	cmp	r3, #0
+ 803c2ce:	d003      	beq.n	803c2d8 <HAL_RCCEx_GetPLL3ClockFreq+0x6c>
+ 803c2d0:	69bb      	ldr	r3, [r7, #24]
+ 803c2d2:	2b01      	cmp	r3, #1
+ 803c2d4:	d056      	beq.n	803c384 <HAL_RCCEx_GetPLL3ClockFreq+0x118>
+ 803c2d6:	e099      	b.n	803c40c <HAL_RCCEx_GetPLL3ClockFreq+0x1a0>
+    {
+      case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
+
+        if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
+ 803c2d8:	4b88      	ldr	r3, [pc, #544]	@ (803c4fc <HAL_RCCEx_GetPLL3ClockFreq+0x290>)
+ 803c2da:	681b      	ldr	r3, [r3, #0]
+ 803c2dc:	f003 0320 	and.w	r3, r3, #32
+ 803c2e0:	2b00      	cmp	r3, #0
+ 803c2e2:	d02d      	beq.n	803c340 <HAL_RCCEx_GetPLL3ClockFreq+0xd4>
+        {
+          hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
+ 803c2e4:	4b85      	ldr	r3, [pc, #532]	@ (803c4fc <HAL_RCCEx_GetPLL3ClockFreq+0x290>)
+ 803c2e6:	681b      	ldr	r3, [r3, #0]
+ 803c2e8:	08db      	lsrs	r3, r3, #3
+ 803c2ea:	f003 0303 	and.w	r3, r3, #3
+ 803c2ee:	4a84      	ldr	r2, [pc, #528]	@ (803c500 <HAL_RCCEx_GetPLL3ClockFreq+0x294>)
+ 803c2f0:	fa22 f303 	lsr.w	r3, r2, r3
+ 803c2f4:	60bb      	str	r3, [r7, #8]
+          pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1);
+ 803c2f6:	68bb      	ldr	r3, [r7, #8]
+ 803c2f8:	ee07 3a90 	vmov	s15, r3
+ 803c2fc:	eef8 6a67 	vcvt.f32.u32	s13, s15
+ 803c300:	697b      	ldr	r3, [r7, #20]
+ 803c302:	ee07 3a90 	vmov	s15, r3
+ 803c306:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 803c30a:	ee86 7aa7 	vdiv.f32	s14, s13, s15
+ 803c30e:	4b7b      	ldr	r3, [pc, #492]	@ (803c4fc <HAL_RCCEx_GetPLL3ClockFreq+0x290>)
+ 803c310:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
+ 803c312:	f3c3 0308 	ubfx	r3, r3, #0, #9
+ 803c316:	ee07 3a90 	vmov	s15, r3
+ 803c31a:	eef8 6a67 	vcvt.f32.u32	s13, s15
+ 803c31e:	ed97 6a03 	vldr	s12, [r7, #12]
+ 803c322:	eddf 5a78 	vldr	s11, [pc, #480]	@ 803c504 <HAL_RCCEx_GetPLL3ClockFreq+0x298>
+ 803c326:	eec6 7a25 	vdiv.f32	s15, s12, s11
+ 803c32a:	ee76 7aa7 	vadd.f32	s15, s13, s15
+ 803c32e:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
+ 803c332:	ee77 7aa6 	vadd.f32	s15, s15, s13
+ 803c336:	ee67 7a27 	vmul.f32	s15, s14, s15
+ 803c33a:	edc7 7a07 	vstr	s15, [r7, #28]
+        }
+        else
+        {
+          pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1);
+        }
+        break;
+ 803c33e:	e087      	b.n	803c450 <HAL_RCCEx_GetPLL3ClockFreq+0x1e4>
+          pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1);
+ 803c340:	697b      	ldr	r3, [r7, #20]
+ 803c342:	ee07 3a90 	vmov	s15, r3
+ 803c346:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 803c34a:	eddf 6a6f 	vldr	s13, [pc, #444]	@ 803c508 <HAL_RCCEx_GetPLL3ClockFreq+0x29c>
+ 803c34e:	ee86 7aa7 	vdiv.f32	s14, s13, s15
+ 803c352:	4b6a      	ldr	r3, [pc, #424]	@ (803c4fc <HAL_RCCEx_GetPLL3ClockFreq+0x290>)
+ 803c354:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
+ 803c356:	f3c3 0308 	ubfx	r3, r3, #0, #9
+ 803c35a:	ee07 3a90 	vmov	s15, r3
+ 803c35e:	eef8 6a67 	vcvt.f32.u32	s13, s15
+ 803c362:	ed97 6a03 	vldr	s12, [r7, #12]
+ 803c366:	eddf 5a67 	vldr	s11, [pc, #412]	@ 803c504 <HAL_RCCEx_GetPLL3ClockFreq+0x298>
+ 803c36a:	eec6 7a25 	vdiv.f32	s15, s12, s11
+ 803c36e:	ee76 7aa7 	vadd.f32	s15, s13, s15
+ 803c372:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
+ 803c376:	ee77 7aa6 	vadd.f32	s15, s15, s13
+ 803c37a:	ee67 7a27 	vmul.f32	s15, s14, s15
+ 803c37e:	edc7 7a07 	vstr	s15, [r7, #28]
+        break;
+ 803c382:	e065      	b.n	803c450 <HAL_RCCEx_GetPLL3ClockFreq+0x1e4>
+      case RCC_PLLSOURCE_CSI:  /* CSI used as PLL clock source */
+        pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1);
+ 803c384:	697b      	ldr	r3, [r7, #20]
+ 803c386:	ee07 3a90 	vmov	s15, r3
+ 803c38a:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 803c38e:	eddf 6a5f 	vldr	s13, [pc, #380]	@ 803c50c <HAL_RCCEx_GetPLL3ClockFreq+0x2a0>
+ 803c392:	ee86 7aa7 	vdiv.f32	s14, s13, s15
+ 803c396:	4b59      	ldr	r3, [pc, #356]	@ (803c4fc <HAL_RCCEx_GetPLL3ClockFreq+0x290>)
+ 803c398:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
+ 803c39a:	f3c3 0308 	ubfx	r3, r3, #0, #9
+ 803c39e:	ee07 3a90 	vmov	s15, r3
+ 803c3a2:	eef8 6a67 	vcvt.f32.u32	s13, s15
+ 803c3a6:	ed97 6a03 	vldr	s12, [r7, #12]
+ 803c3aa:	eddf 5a56 	vldr	s11, [pc, #344]	@ 803c504 <HAL_RCCEx_GetPLL3ClockFreq+0x298>
+ 803c3ae:	eec6 7a25 	vdiv.f32	s15, s12, s11
+ 803c3b2:	ee76 7aa7 	vadd.f32	s15, s13, s15
+ 803c3b6:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
+ 803c3ba:	ee77 7aa6 	vadd.f32	s15, s15, s13
+ 803c3be:	ee67 7a27 	vmul.f32	s15, s14, s15
+ 803c3c2:	edc7 7a07 	vstr	s15, [r7, #28]
+        break;
+ 803c3c6:	e043      	b.n	803c450 <HAL_RCCEx_GetPLL3ClockFreq+0x1e4>
+
+      case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
+        pll3vco = ((float_t)HSE_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1);
+ 803c3c8:	697b      	ldr	r3, [r7, #20]
+ 803c3ca:	ee07 3a90 	vmov	s15, r3
+ 803c3ce:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 803c3d2:	eddf 6a4f 	vldr	s13, [pc, #316]	@ 803c510 <HAL_RCCEx_GetPLL3ClockFreq+0x2a4>
+ 803c3d6:	ee86 7aa7 	vdiv.f32	s14, s13, s15
+ 803c3da:	4b48      	ldr	r3, [pc, #288]	@ (803c4fc <HAL_RCCEx_GetPLL3ClockFreq+0x290>)
+ 803c3dc:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
+ 803c3de:	f3c3 0308 	ubfx	r3, r3, #0, #9
+ 803c3e2:	ee07 3a90 	vmov	s15, r3
+ 803c3e6:	eef8 6a67 	vcvt.f32.u32	s13, s15
+ 803c3ea:	ed97 6a03 	vldr	s12, [r7, #12]
+ 803c3ee:	eddf 5a45 	vldr	s11, [pc, #276]	@ 803c504 <HAL_RCCEx_GetPLL3ClockFreq+0x298>
+ 803c3f2:	eec6 7a25 	vdiv.f32	s15, s12, s11
+ 803c3f6:	ee76 7aa7 	vadd.f32	s15, s13, s15
+ 803c3fa:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
+ 803c3fe:	ee77 7aa6 	vadd.f32	s15, s15, s13
+ 803c402:	ee67 7a27 	vmul.f32	s15, s14, s15
+ 803c406:	edc7 7a07 	vstr	s15, [r7, #28]
+        break;
+ 803c40a:	e021      	b.n	803c450 <HAL_RCCEx_GetPLL3ClockFreq+0x1e4>
+
+      default:
+        pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1);
+ 803c40c:	697b      	ldr	r3, [r7, #20]
+ 803c40e:	ee07 3a90 	vmov	s15, r3
+ 803c412:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 803c416:	eddf 6a3d 	vldr	s13, [pc, #244]	@ 803c50c <HAL_RCCEx_GetPLL3ClockFreq+0x2a0>
+ 803c41a:	ee86 7aa7 	vdiv.f32	s14, s13, s15
+ 803c41e:	4b37      	ldr	r3, [pc, #220]	@ (803c4fc <HAL_RCCEx_GetPLL3ClockFreq+0x290>)
+ 803c420:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
+ 803c422:	f3c3 0308 	ubfx	r3, r3, #0, #9
+ 803c426:	ee07 3a90 	vmov	s15, r3
+ 803c42a:	eef8 6a67 	vcvt.f32.u32	s13, s15
+ 803c42e:	ed97 6a03 	vldr	s12, [r7, #12]
+ 803c432:	eddf 5a34 	vldr	s11, [pc, #208]	@ 803c504 <HAL_RCCEx_GetPLL3ClockFreq+0x298>
+ 803c436:	eec6 7a25 	vdiv.f32	s15, s12, s11
+ 803c43a:	ee76 7aa7 	vadd.f32	s15, s13, s15
+ 803c43e:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
+ 803c442:	ee77 7aa6 	vadd.f32	s15, s15, s13
+ 803c446:	ee67 7a27 	vmul.f32	s15, s14, s15
+ 803c44a:	edc7 7a07 	vstr	s15, [r7, #28]
+        break;
+ 803c44e:	bf00      	nop
+    }
+    PLL3_Clocks->PLL3_P_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >> 9)  + (float_t)1)) ;
+ 803c450:	4b2a      	ldr	r3, [pc, #168]	@ (803c4fc <HAL_RCCEx_GetPLL3ClockFreq+0x290>)
+ 803c452:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
+ 803c454:	0a5b      	lsrs	r3, r3, #9
+ 803c456:	f003 037f 	and.w	r3, r3, #127	@ 0x7f
+ 803c45a:	ee07 3a90 	vmov	s15, r3
+ 803c45e:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 803c462:	eeb7 7a00 	vmov.f32	s14, #112	@ 0x3f800000  1.0
+ 803c466:	ee37 7a87 	vadd.f32	s14, s15, s14
+ 803c46a:	edd7 6a07 	vldr	s13, [r7, #28]
+ 803c46e:	eec6 7a87 	vdiv.f32	s15, s13, s14
+ 803c472:	eefc 7ae7 	vcvt.u32.f32	s15, s15
+ 803c476:	ee17 2a90 	vmov	r2, s15
+ 803c47a:	687b      	ldr	r3, [r7, #4]
+ 803c47c:	601a      	str	r2, [r3, #0]
+    PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >> 16) + (float_t)1)) ;
+ 803c47e:	4b1f      	ldr	r3, [pc, #124]	@ (803c4fc <HAL_RCCEx_GetPLL3ClockFreq+0x290>)
+ 803c480:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
+ 803c482:	0c1b      	lsrs	r3, r3, #16
+ 803c484:	f003 037f 	and.w	r3, r3, #127	@ 0x7f
+ 803c488:	ee07 3a90 	vmov	s15, r3
+ 803c48c:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 803c490:	eeb7 7a00 	vmov.f32	s14, #112	@ 0x3f800000  1.0
+ 803c494:	ee37 7a87 	vadd.f32	s14, s15, s14
+ 803c498:	edd7 6a07 	vldr	s13, [r7, #28]
+ 803c49c:	eec6 7a87 	vdiv.f32	s15, s13, s14
+ 803c4a0:	eefc 7ae7 	vcvt.u32.f32	s15, s15
+ 803c4a4:	ee17 2a90 	vmov	r2, s15
+ 803c4a8:	687b      	ldr	r3, [r7, #4]
+ 803c4aa:	605a      	str	r2, [r3, #4]
+    PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >> 24) + (float_t)1)) ;
+ 803c4ac:	4b13      	ldr	r3, [pc, #76]	@ (803c4fc <HAL_RCCEx_GetPLL3ClockFreq+0x290>)
+ 803c4ae:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
+ 803c4b0:	0e1b      	lsrs	r3, r3, #24
+ 803c4b2:	f003 037f 	and.w	r3, r3, #127	@ 0x7f
+ 803c4b6:	ee07 3a90 	vmov	s15, r3
+ 803c4ba:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 803c4be:	eeb7 7a00 	vmov.f32	s14, #112	@ 0x3f800000  1.0
+ 803c4c2:	ee37 7a87 	vadd.f32	s14, s15, s14
+ 803c4c6:	edd7 6a07 	vldr	s13, [r7, #28]
+ 803c4ca:	eec6 7a87 	vdiv.f32	s15, s13, s14
+ 803c4ce:	eefc 7ae7 	vcvt.u32.f32	s15, s15
+ 803c4d2:	ee17 2a90 	vmov	r2, s15
+ 803c4d6:	687b      	ldr	r3, [r7, #4]
+ 803c4d8:	609a      	str	r2, [r3, #8]
+    PLL3_Clocks->PLL3_P_Frequency = 0U;
+    PLL3_Clocks->PLL3_Q_Frequency = 0U;
+    PLL3_Clocks->PLL3_R_Frequency = 0U;
+  }
+
+}
+ 803c4da:	e008      	b.n	803c4ee <HAL_RCCEx_GetPLL3ClockFreq+0x282>
+    PLL3_Clocks->PLL3_P_Frequency = 0U;
+ 803c4dc:	687b      	ldr	r3, [r7, #4]
+ 803c4de:	2200      	movs	r2, #0
+ 803c4e0:	601a      	str	r2, [r3, #0]
+    PLL3_Clocks->PLL3_Q_Frequency = 0U;
+ 803c4e2:	687b      	ldr	r3, [r7, #4]
+ 803c4e4:	2200      	movs	r2, #0
+ 803c4e6:	605a      	str	r2, [r3, #4]
+    PLL3_Clocks->PLL3_R_Frequency = 0U;
+ 803c4e8:	687b      	ldr	r3, [r7, #4]
+ 803c4ea:	2200      	movs	r2, #0
+ 803c4ec:	609a      	str	r2, [r3, #8]
+}
+ 803c4ee:	bf00      	nop
+ 803c4f0:	3724      	adds	r7, #36	@ 0x24
+ 803c4f2:	46bd      	mov	sp, r7
+ 803c4f4:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 803c4f8:	4770      	bx	lr
+ 803c4fa:	bf00      	nop
+ 803c4fc:	58024400 	.word	0x58024400
+ 803c500:	03d09000 	.word	0x03d09000
+ 803c504:	46000000 	.word	0x46000000
+ 803c508:	4c742400 	.word	0x4c742400
+ 803c50c:	4a742400 	.word	0x4a742400
+ 803c510:	4bbebc20 	.word	0x4bbebc20
+
+0803c514 <HAL_RCCEx_GetPLL1ClockFreq>:
+  *         right PLL1CLK value. Otherwise, any configuration based on this function will be incorrect.
+  * @param  PLL1_Clocks structure.
+  * @retval None
+  */
+void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks)
+{
+ 803c514:	b480      	push	{r7}
+ 803c516:	b089      	sub	sp, #36	@ 0x24
+ 803c518:	af00      	add	r7, sp, #0
+ 803c51a:	6078      	str	r0, [r7, #4]
+  uint32_t pllsource, pll1m, pll1fracen, hsivalue;
+  float_t fracn1, pll1vco;
+
+  pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
+ 803c51c:	4ba0      	ldr	r3, [pc, #640]	@ (803c7a0 <HAL_RCCEx_GetPLL1ClockFreq+0x28c>)
+ 803c51e:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 803c520:	f003 0303 	and.w	r3, r3, #3
+ 803c524:	61bb      	str	r3, [r7, #24]
+  pll1m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4);
+ 803c526:	4b9e      	ldr	r3, [pc, #632]	@ (803c7a0 <HAL_RCCEx_GetPLL1ClockFreq+0x28c>)
+ 803c528:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 803c52a:	091b      	lsrs	r3, r3, #4
+ 803c52c:	f003 033f 	and.w	r3, r3, #63	@ 0x3f
+ 803c530:	617b      	str	r3, [r7, #20]
+  pll1fracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN;
+ 803c532:	4b9b      	ldr	r3, [pc, #620]	@ (803c7a0 <HAL_RCCEx_GetPLL1ClockFreq+0x28c>)
+ 803c534:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 803c536:	f003 0301 	and.w	r3, r3, #1
+ 803c53a:	613b      	str	r3, [r7, #16]
+  fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3));
+ 803c53c:	4b98      	ldr	r3, [pc, #608]	@ (803c7a0 <HAL_RCCEx_GetPLL1ClockFreq+0x28c>)
+ 803c53e:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
+ 803c540:	08db      	lsrs	r3, r3, #3
+ 803c542:	f3c3 030c 	ubfx	r3, r3, #0, #13
+ 803c546:	693a      	ldr	r2, [r7, #16]
+ 803c548:	fb02 f303 	mul.w	r3, r2, r3
+ 803c54c:	ee07 3a90 	vmov	s15, r3
+ 803c550:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 803c554:	edc7 7a03 	vstr	s15, [r7, #12]
+
+  if (pll1m != 0U)
+ 803c558:	697b      	ldr	r3, [r7, #20]
+ 803c55a:	2b00      	cmp	r3, #0
+ 803c55c:	f000 8111 	beq.w	803c782 <HAL_RCCEx_GetPLL1ClockFreq+0x26e>
+  {
+    switch (pllsource)
+ 803c560:	69bb      	ldr	r3, [r7, #24]
+ 803c562:	2b02      	cmp	r3, #2
+ 803c564:	f000 8083 	beq.w	803c66e <HAL_RCCEx_GetPLL1ClockFreq+0x15a>
+ 803c568:	69bb      	ldr	r3, [r7, #24]
+ 803c56a:	2b02      	cmp	r3, #2
+ 803c56c:	f200 80a1 	bhi.w	803c6b2 <HAL_RCCEx_GetPLL1ClockFreq+0x19e>
+ 803c570:	69bb      	ldr	r3, [r7, #24]
+ 803c572:	2b00      	cmp	r3, #0
+ 803c574:	d003      	beq.n	803c57e <HAL_RCCEx_GetPLL1ClockFreq+0x6a>
+ 803c576:	69bb      	ldr	r3, [r7, #24]
+ 803c578:	2b01      	cmp	r3, #1
+ 803c57a:	d056      	beq.n	803c62a <HAL_RCCEx_GetPLL1ClockFreq+0x116>
+ 803c57c:	e099      	b.n	803c6b2 <HAL_RCCEx_GetPLL1ClockFreq+0x19e>
+    {
+
+      case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
+
+        if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
+ 803c57e:	4b88      	ldr	r3, [pc, #544]	@ (803c7a0 <HAL_RCCEx_GetPLL1ClockFreq+0x28c>)
+ 803c580:	681b      	ldr	r3, [r3, #0]
+ 803c582:	f003 0320 	and.w	r3, r3, #32
+ 803c586:	2b00      	cmp	r3, #0
+ 803c588:	d02d      	beq.n	803c5e6 <HAL_RCCEx_GetPLL1ClockFreq+0xd2>
+        {
+          hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
+ 803c58a:	4b85      	ldr	r3, [pc, #532]	@ (803c7a0 <HAL_RCCEx_GetPLL1ClockFreq+0x28c>)
+ 803c58c:	681b      	ldr	r3, [r3, #0]
+ 803c58e:	08db      	lsrs	r3, r3, #3
+ 803c590:	f003 0303 	and.w	r3, r3, #3
+ 803c594:	4a83      	ldr	r2, [pc, #524]	@ (803c7a4 <HAL_RCCEx_GetPLL1ClockFreq+0x290>)
+ 803c596:	fa22 f303 	lsr.w	r3, r2, r3
+ 803c59a:	60bb      	str	r3, [r7, #8]
+          pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
+ 803c59c:	68bb      	ldr	r3, [r7, #8]
+ 803c59e:	ee07 3a90 	vmov	s15, r3
+ 803c5a2:	eef8 6a67 	vcvt.f32.u32	s13, s15
+ 803c5a6:	697b      	ldr	r3, [r7, #20]
+ 803c5a8:	ee07 3a90 	vmov	s15, r3
+ 803c5ac:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 803c5b0:	ee86 7aa7 	vdiv.f32	s14, s13, s15
+ 803c5b4:	4b7a      	ldr	r3, [pc, #488]	@ (803c7a0 <HAL_RCCEx_GetPLL1ClockFreq+0x28c>)
+ 803c5b6:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
+ 803c5b8:	f3c3 0308 	ubfx	r3, r3, #0, #9
+ 803c5bc:	ee07 3a90 	vmov	s15, r3
+ 803c5c0:	eef8 6a67 	vcvt.f32.u32	s13, s15
+ 803c5c4:	ed97 6a03 	vldr	s12, [r7, #12]
+ 803c5c8:	eddf 5a77 	vldr	s11, [pc, #476]	@ 803c7a8 <HAL_RCCEx_GetPLL1ClockFreq+0x294>
+ 803c5cc:	eec6 7a25 	vdiv.f32	s15, s12, s11
+ 803c5d0:	ee76 7aa7 	vadd.f32	s15, s13, s15
+ 803c5d4:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
+ 803c5d8:	ee77 7aa6 	vadd.f32	s15, s15, s13
+ 803c5dc:	ee67 7a27 	vmul.f32	s15, s14, s15
+ 803c5e0:	edc7 7a07 	vstr	s15, [r7, #28]
+        }
+        else
+        {
+          pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
+        }
+        break;
+ 803c5e4:	e087      	b.n	803c6f6 <HAL_RCCEx_GetPLL1ClockFreq+0x1e2>
+          pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
+ 803c5e6:	697b      	ldr	r3, [r7, #20]
+ 803c5e8:	ee07 3a90 	vmov	s15, r3
+ 803c5ec:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 803c5f0:	eddf 6a6e 	vldr	s13, [pc, #440]	@ 803c7ac <HAL_RCCEx_GetPLL1ClockFreq+0x298>
+ 803c5f4:	ee86 7aa7 	vdiv.f32	s14, s13, s15
+ 803c5f8:	4b69      	ldr	r3, [pc, #420]	@ (803c7a0 <HAL_RCCEx_GetPLL1ClockFreq+0x28c>)
+ 803c5fa:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
+ 803c5fc:	f3c3 0308 	ubfx	r3, r3, #0, #9
+ 803c600:	ee07 3a90 	vmov	s15, r3
+ 803c604:	eef8 6a67 	vcvt.f32.u32	s13, s15
+ 803c608:	ed97 6a03 	vldr	s12, [r7, #12]
+ 803c60c:	eddf 5a66 	vldr	s11, [pc, #408]	@ 803c7a8 <HAL_RCCEx_GetPLL1ClockFreq+0x294>
+ 803c610:	eec6 7a25 	vdiv.f32	s15, s12, s11
+ 803c614:	ee76 7aa7 	vadd.f32	s15, s13, s15
+ 803c618:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
+ 803c61c:	ee77 7aa6 	vadd.f32	s15, s15, s13
+ 803c620:	ee67 7a27 	vmul.f32	s15, s14, s15
+ 803c624:	edc7 7a07 	vstr	s15, [r7, #28]
+        break;
+ 803c628:	e065      	b.n	803c6f6 <HAL_RCCEx_GetPLL1ClockFreq+0x1e2>
+      case RCC_PLLSOURCE_CSI:  /* CSI used as PLL clock source */
+        pll1vco = ((float_t)CSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
+ 803c62a:	697b      	ldr	r3, [r7, #20]
+ 803c62c:	ee07 3a90 	vmov	s15, r3
+ 803c630:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 803c634:	eddf 6a5e 	vldr	s13, [pc, #376]	@ 803c7b0 <HAL_RCCEx_GetPLL1ClockFreq+0x29c>
+ 803c638:	ee86 7aa7 	vdiv.f32	s14, s13, s15
+ 803c63c:	4b58      	ldr	r3, [pc, #352]	@ (803c7a0 <HAL_RCCEx_GetPLL1ClockFreq+0x28c>)
+ 803c63e:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
+ 803c640:	f3c3 0308 	ubfx	r3, r3, #0, #9
+ 803c644:	ee07 3a90 	vmov	s15, r3
+ 803c648:	eef8 6a67 	vcvt.f32.u32	s13, s15
+ 803c64c:	ed97 6a03 	vldr	s12, [r7, #12]
+ 803c650:	eddf 5a55 	vldr	s11, [pc, #340]	@ 803c7a8 <HAL_RCCEx_GetPLL1ClockFreq+0x294>
+ 803c654:	eec6 7a25 	vdiv.f32	s15, s12, s11
+ 803c658:	ee76 7aa7 	vadd.f32	s15, s13, s15
+ 803c65c:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
+ 803c660:	ee77 7aa6 	vadd.f32	s15, s15, s13
+ 803c664:	ee67 7a27 	vmul.f32	s15, s14, s15
+ 803c668:	edc7 7a07 	vstr	s15, [r7, #28]
+        break;
+ 803c66c:	e043      	b.n	803c6f6 <HAL_RCCEx_GetPLL1ClockFreq+0x1e2>
+
+      case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
+        pll1vco = ((float_t)HSE_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
+ 803c66e:	697b      	ldr	r3, [r7, #20]
+ 803c670:	ee07 3a90 	vmov	s15, r3
+ 803c674:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 803c678:	eddf 6a4e 	vldr	s13, [pc, #312]	@ 803c7b4 <HAL_RCCEx_GetPLL1ClockFreq+0x2a0>
+ 803c67c:	ee86 7aa7 	vdiv.f32	s14, s13, s15
+ 803c680:	4b47      	ldr	r3, [pc, #284]	@ (803c7a0 <HAL_RCCEx_GetPLL1ClockFreq+0x28c>)
+ 803c682:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
+ 803c684:	f3c3 0308 	ubfx	r3, r3, #0, #9
+ 803c688:	ee07 3a90 	vmov	s15, r3
+ 803c68c:	eef8 6a67 	vcvt.f32.u32	s13, s15
+ 803c690:	ed97 6a03 	vldr	s12, [r7, #12]
+ 803c694:	eddf 5a44 	vldr	s11, [pc, #272]	@ 803c7a8 <HAL_RCCEx_GetPLL1ClockFreq+0x294>
+ 803c698:	eec6 7a25 	vdiv.f32	s15, s12, s11
+ 803c69c:	ee76 7aa7 	vadd.f32	s15, s13, s15
+ 803c6a0:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
+ 803c6a4:	ee77 7aa6 	vadd.f32	s15, s15, s13
+ 803c6a8:	ee67 7a27 	vmul.f32	s15, s14, s15
+ 803c6ac:	edc7 7a07 	vstr	s15, [r7, #28]
+        break;
+ 803c6b0:	e021      	b.n	803c6f6 <HAL_RCCEx_GetPLL1ClockFreq+0x1e2>
+
+      default:
+        pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
+ 803c6b2:	697b      	ldr	r3, [r7, #20]
+ 803c6b4:	ee07 3a90 	vmov	s15, r3
+ 803c6b8:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 803c6bc:	eddf 6a3b 	vldr	s13, [pc, #236]	@ 803c7ac <HAL_RCCEx_GetPLL1ClockFreq+0x298>
+ 803c6c0:	ee86 7aa7 	vdiv.f32	s14, s13, s15
+ 803c6c4:	4b36      	ldr	r3, [pc, #216]	@ (803c7a0 <HAL_RCCEx_GetPLL1ClockFreq+0x28c>)
+ 803c6c6:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
+ 803c6c8:	f3c3 0308 	ubfx	r3, r3, #0, #9
+ 803c6cc:	ee07 3a90 	vmov	s15, r3
+ 803c6d0:	eef8 6a67 	vcvt.f32.u32	s13, s15
+ 803c6d4:	ed97 6a03 	vldr	s12, [r7, #12]
+ 803c6d8:	eddf 5a33 	vldr	s11, [pc, #204]	@ 803c7a8 <HAL_RCCEx_GetPLL1ClockFreq+0x294>
+ 803c6dc:	eec6 7a25 	vdiv.f32	s15, s12, s11
+ 803c6e0:	ee76 7aa7 	vadd.f32	s15, s13, s15
+ 803c6e4:	eef7 6a00 	vmov.f32	s13, #112	@ 0x3f800000  1.0
+ 803c6e8:	ee77 7aa6 	vadd.f32	s15, s15, s13
+ 803c6ec:	ee67 7a27 	vmul.f32	s15, s14, s15
+ 803c6f0:	edc7 7a07 	vstr	s15, [r7, #28]
+        break;
+ 803c6f4:	bf00      	nop
+    }
+
+    PLL1_Clocks->PLL1_P_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9)  + (float_t)1)) ;
+ 803c6f6:	4b2a      	ldr	r3, [pc, #168]	@ (803c7a0 <HAL_RCCEx_GetPLL1ClockFreq+0x28c>)
+ 803c6f8:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
+ 803c6fa:	0a5b      	lsrs	r3, r3, #9
+ 803c6fc:	f003 037f 	and.w	r3, r3, #127	@ 0x7f
+ 803c700:	ee07 3a90 	vmov	s15, r3
+ 803c704:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 803c708:	eeb7 7a00 	vmov.f32	s14, #112	@ 0x3f800000  1.0
+ 803c70c:	ee37 7a87 	vadd.f32	s14, s15, s14
+ 803c710:	edd7 6a07 	vldr	s13, [r7, #28]
+ 803c714:	eec6 7a87 	vdiv.f32	s15, s13, s14
+ 803c718:	eefc 7ae7 	vcvt.u32.f32	s15, s15
+ 803c71c:	ee17 2a90 	vmov	r2, s15
+ 803c720:	687b      	ldr	r3, [r7, #4]
+ 803c722:	601a      	str	r2, [r3, #0]
+    PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_Q1) >> 16) + (float_t)1)) ;
+ 803c724:	4b1e      	ldr	r3, [pc, #120]	@ (803c7a0 <HAL_RCCEx_GetPLL1ClockFreq+0x28c>)
+ 803c726:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
+ 803c728:	0c1b      	lsrs	r3, r3, #16
+ 803c72a:	f003 037f 	and.w	r3, r3, #127	@ 0x7f
+ 803c72e:	ee07 3a90 	vmov	s15, r3
+ 803c732:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 803c736:	eeb7 7a00 	vmov.f32	s14, #112	@ 0x3f800000  1.0
+ 803c73a:	ee37 7a87 	vadd.f32	s14, s15, s14
+ 803c73e:	edd7 6a07 	vldr	s13, [r7, #28]
+ 803c742:	eec6 7a87 	vdiv.f32	s15, s13, s14
+ 803c746:	eefc 7ae7 	vcvt.u32.f32	s15, s15
+ 803c74a:	ee17 2a90 	vmov	r2, s15
+ 803c74e:	687b      	ldr	r3, [r7, #4]
+ 803c750:	605a      	str	r2, [r3, #4]
+    PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >> 24) + (float_t)1)) ;
+ 803c752:	4b13      	ldr	r3, [pc, #76]	@ (803c7a0 <HAL_RCCEx_GetPLL1ClockFreq+0x28c>)
+ 803c754:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
+ 803c756:	0e1b      	lsrs	r3, r3, #24
+ 803c758:	f003 037f 	and.w	r3, r3, #127	@ 0x7f
+ 803c75c:	ee07 3a90 	vmov	s15, r3
+ 803c760:	eef8 7a67 	vcvt.f32.u32	s15, s15
+ 803c764:	eeb7 7a00 	vmov.f32	s14, #112	@ 0x3f800000  1.0
+ 803c768:	ee37 7a87 	vadd.f32	s14, s15, s14
+ 803c76c:	edd7 6a07 	vldr	s13, [r7, #28]
+ 803c770:	eec6 7a87 	vdiv.f32	s15, s13, s14
+ 803c774:	eefc 7ae7 	vcvt.u32.f32	s15, s15
+ 803c778:	ee17 2a90 	vmov	r2, s15
+ 803c77c:	687b      	ldr	r3, [r7, #4]
+ 803c77e:	609a      	str	r2, [r3, #8]
+    PLL1_Clocks->PLL1_P_Frequency = 0U;
+    PLL1_Clocks->PLL1_Q_Frequency = 0U;
+    PLL1_Clocks->PLL1_R_Frequency = 0U;
+  }
+
+}
+ 803c780:	e008      	b.n	803c794 <HAL_RCCEx_GetPLL1ClockFreq+0x280>
+    PLL1_Clocks->PLL1_P_Frequency = 0U;
+ 803c782:	687b      	ldr	r3, [r7, #4]
+ 803c784:	2200      	movs	r2, #0
+ 803c786:	601a      	str	r2, [r3, #0]
+    PLL1_Clocks->PLL1_Q_Frequency = 0U;
+ 803c788:	687b      	ldr	r3, [r7, #4]
+ 803c78a:	2200      	movs	r2, #0
+ 803c78c:	605a      	str	r2, [r3, #4]
+    PLL1_Clocks->PLL1_R_Frequency = 0U;
+ 803c78e:	687b      	ldr	r3, [r7, #4]
+ 803c790:	2200      	movs	r2, #0
+ 803c792:	609a      	str	r2, [r3, #8]
+}
+ 803c794:	bf00      	nop
+ 803c796:	3724      	adds	r7, #36	@ 0x24
+ 803c798:	46bd      	mov	sp, r7
+ 803c79a:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 803c79e:	4770      	bx	lr
+ 803c7a0:	58024400 	.word	0x58024400
+ 803c7a4:	03d09000 	.word	0x03d09000
+ 803c7a8:	46000000 	.word	0x46000000
+ 803c7ac:	4c742400 	.word	0x4c742400
+ 803c7b0:	4a742400 	.word	0x4a742400
+ 803c7b4:	4bbebc20 	.word	0x4bbebc20
+
+0803c7b8 <RCCEx_PLL2_Config>:
+  * @note   PLL2 is temporary disabled to apply new parameters
+  *
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider)
+{
+ 803c7b8:	b580      	push	{r7, lr}
+ 803c7ba:	b084      	sub	sp, #16
+ 803c7bc:	af00      	add	r7, sp, #0
+ 803c7be:	6078      	str	r0, [r7, #4]
+ 803c7c0:	6039      	str	r1, [r7, #0]
+
+  uint32_t tickstart;
+  HAL_StatusTypeDef status = HAL_OK;
+ 803c7c2:	2300      	movs	r3, #0
+ 803c7c4:	73fb      	strb	r3, [r7, #15]
+  assert_param(IS_RCC_PLL2RGE_VALUE(pll2->PLL2RGE));
+  assert_param(IS_RCC_PLL2VCO_VALUE(pll2->PLL2VCOSEL));
+  assert_param(IS_RCC_PLLFRACN_VALUE(pll2->PLL2FRACN));
+
+  /* Check that PLL2 OSC clock source is already set */
+  if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
+ 803c7c6:	4b53      	ldr	r3, [pc, #332]	@ (803c914 <RCCEx_PLL2_Config+0x15c>)
+ 803c7c8:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 803c7ca:	f003 0303 	and.w	r3, r3, #3
+ 803c7ce:	2b03      	cmp	r3, #3
+ 803c7d0:	d101      	bne.n	803c7d6 <RCCEx_PLL2_Config+0x1e>
+  {
+    return HAL_ERROR;
+ 803c7d2:	2301      	movs	r3, #1
+ 803c7d4:	e099      	b.n	803c90a <RCCEx_PLL2_Config+0x152>
+
+
+  else
+  {
+    /* Disable  PLL2. */
+    __HAL_RCC_PLL2_DISABLE();
+ 803c7d6:	4b4f      	ldr	r3, [pc, #316]	@ (803c914 <RCCEx_PLL2_Config+0x15c>)
+ 803c7d8:	681b      	ldr	r3, [r3, #0]
+ 803c7da:	4a4e      	ldr	r2, [pc, #312]	@ (803c914 <RCCEx_PLL2_Config+0x15c>)
+ 803c7dc:	f023 6380 	bic.w	r3, r3, #67108864	@ 0x4000000
+ 803c7e0:	6013      	str	r3, [r2, #0]
+
+    /* Get Start Tick*/
+    tickstart = HAL_GetTick();
+ 803c7e2:	f7f5 f8a5 	bl	8031930 <HAL_GetTick>
+ 803c7e6:	60b8      	str	r0, [r7, #8]
+
+    /* Wait till PLL is disabled */
+    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U)
+ 803c7e8:	e008      	b.n	803c7fc <RCCEx_PLL2_Config+0x44>
+    {
+      if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
+ 803c7ea:	f7f5 f8a1 	bl	8031930 <HAL_GetTick>
+ 803c7ee:	4602      	mov	r2, r0
+ 803c7f0:	68bb      	ldr	r3, [r7, #8]
+ 803c7f2:	1ad3      	subs	r3, r2, r3
+ 803c7f4:	2b02      	cmp	r3, #2
+ 803c7f6:	d901      	bls.n	803c7fc <RCCEx_PLL2_Config+0x44>
+      {
+        return HAL_TIMEOUT;
+ 803c7f8:	2303      	movs	r3, #3
+ 803c7fa:	e086      	b.n	803c90a <RCCEx_PLL2_Config+0x152>
+    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U)
+ 803c7fc:	4b45      	ldr	r3, [pc, #276]	@ (803c914 <RCCEx_PLL2_Config+0x15c>)
+ 803c7fe:	681b      	ldr	r3, [r3, #0]
+ 803c800:	f003 6300 	and.w	r3, r3, #134217728	@ 0x8000000
+ 803c804:	2b00      	cmp	r3, #0
+ 803c806:	d1f0      	bne.n	803c7ea <RCCEx_PLL2_Config+0x32>
+      }
+    }
+
+    /* Configure PLL2 multiplication and division factors. */
+    __HAL_RCC_PLL2_CONFIG(pll2->PLL2M,
+ 803c808:	4b42      	ldr	r3, [pc, #264]	@ (803c914 <RCCEx_PLL2_Config+0x15c>)
+ 803c80a:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 803c80c:	f423 327c 	bic.w	r2, r3, #258048	@ 0x3f000
+ 803c810:	687b      	ldr	r3, [r7, #4]
+ 803c812:	681b      	ldr	r3, [r3, #0]
+ 803c814:	031b      	lsls	r3, r3, #12
+ 803c816:	493f      	ldr	r1, [pc, #252]	@ (803c914 <RCCEx_PLL2_Config+0x15c>)
+ 803c818:	4313      	orrs	r3, r2
+ 803c81a:	628b      	str	r3, [r1, #40]	@ 0x28
+ 803c81c:	687b      	ldr	r3, [r7, #4]
+ 803c81e:	685b      	ldr	r3, [r3, #4]
+ 803c820:	3b01      	subs	r3, #1
+ 803c822:	f3c3 0208 	ubfx	r2, r3, #0, #9
+ 803c826:	687b      	ldr	r3, [r7, #4]
+ 803c828:	689b      	ldr	r3, [r3, #8]
+ 803c82a:	3b01      	subs	r3, #1
+ 803c82c:	025b      	lsls	r3, r3, #9
+ 803c82e:	b29b      	uxth	r3, r3
+ 803c830:	431a      	orrs	r2, r3
+ 803c832:	687b      	ldr	r3, [r7, #4]
+ 803c834:	68db      	ldr	r3, [r3, #12]
+ 803c836:	3b01      	subs	r3, #1
+ 803c838:	041b      	lsls	r3, r3, #16
+ 803c83a:	f403 03fe 	and.w	r3, r3, #8323072	@ 0x7f0000
+ 803c83e:	431a      	orrs	r2, r3
+ 803c840:	687b      	ldr	r3, [r7, #4]
+ 803c842:	691b      	ldr	r3, [r3, #16]
+ 803c844:	3b01      	subs	r3, #1
+ 803c846:	061b      	lsls	r3, r3, #24
+ 803c848:	f003 43fe 	and.w	r3, r3, #2130706432	@ 0x7f000000
+ 803c84c:	4931      	ldr	r1, [pc, #196]	@ (803c914 <RCCEx_PLL2_Config+0x15c>)
+ 803c84e:	4313      	orrs	r3, r2
+ 803c850:	638b      	str	r3, [r1, #56]	@ 0x38
+                          pll2->PLL2P,
+                          pll2->PLL2Q,
+                          pll2->PLL2R);
+
+    /* Select PLL2 input reference frequency range: VCI */
+    __HAL_RCC_PLL2_VCIRANGE(pll2->PLL2RGE) ;
+ 803c852:	4b30      	ldr	r3, [pc, #192]	@ (803c914 <RCCEx_PLL2_Config+0x15c>)
+ 803c854:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 803c856:	f023 02c0 	bic.w	r2, r3, #192	@ 0xc0
+ 803c85a:	687b      	ldr	r3, [r7, #4]
+ 803c85c:	695b      	ldr	r3, [r3, #20]
+ 803c85e:	492d      	ldr	r1, [pc, #180]	@ (803c914 <RCCEx_PLL2_Config+0x15c>)
+ 803c860:	4313      	orrs	r3, r2
+ 803c862:	62cb      	str	r3, [r1, #44]	@ 0x2c
+
+    /* Select PLL2 output frequency range : VCO */
+    __HAL_RCC_PLL2_VCORANGE(pll2->PLL2VCOSEL) ;
+ 803c864:	4b2b      	ldr	r3, [pc, #172]	@ (803c914 <RCCEx_PLL2_Config+0x15c>)
+ 803c866:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 803c868:	f023 0220 	bic.w	r2, r3, #32
+ 803c86c:	687b      	ldr	r3, [r7, #4]
+ 803c86e:	699b      	ldr	r3, [r3, #24]
+ 803c870:	4928      	ldr	r1, [pc, #160]	@ (803c914 <RCCEx_PLL2_Config+0x15c>)
+ 803c872:	4313      	orrs	r3, r2
+ 803c874:	62cb      	str	r3, [r1, #44]	@ 0x2c
+
+    /* Disable PLL2FRACN . */
+    __HAL_RCC_PLL2FRACN_DISABLE();
+ 803c876:	4b27      	ldr	r3, [pc, #156]	@ (803c914 <RCCEx_PLL2_Config+0x15c>)
+ 803c878:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 803c87a:	4a26      	ldr	r2, [pc, #152]	@ (803c914 <RCCEx_PLL2_Config+0x15c>)
+ 803c87c:	f023 0310 	bic.w	r3, r3, #16
+ 803c880:	62d3      	str	r3, [r2, #44]	@ 0x2c
+
+    /* Configures PLL2 clock Fractional Part Of The Multiplication Factor */
+    __HAL_RCC_PLL2FRACN_CONFIG(pll2->PLL2FRACN);
+ 803c882:	4b24      	ldr	r3, [pc, #144]	@ (803c914 <RCCEx_PLL2_Config+0x15c>)
+ 803c884:	6bda      	ldr	r2, [r3, #60]	@ 0x3c
+ 803c886:	4b24      	ldr	r3, [pc, #144]	@ (803c918 <RCCEx_PLL2_Config+0x160>)
+ 803c888:	4013      	ands	r3, r2
+ 803c88a:	687a      	ldr	r2, [r7, #4]
+ 803c88c:	69d2      	ldr	r2, [r2, #28]
+ 803c88e:	00d2      	lsls	r2, r2, #3
+ 803c890:	4920      	ldr	r1, [pc, #128]	@ (803c914 <RCCEx_PLL2_Config+0x15c>)
+ 803c892:	4313      	orrs	r3, r2
+ 803c894:	63cb      	str	r3, [r1, #60]	@ 0x3c
+
+    /* Enable PLL2FRACN . */
+    __HAL_RCC_PLL2FRACN_ENABLE();
+ 803c896:	4b1f      	ldr	r3, [pc, #124]	@ (803c914 <RCCEx_PLL2_Config+0x15c>)
+ 803c898:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 803c89a:	4a1e      	ldr	r2, [pc, #120]	@ (803c914 <RCCEx_PLL2_Config+0x15c>)
+ 803c89c:	f043 0310 	orr.w	r3, r3, #16
+ 803c8a0:	62d3      	str	r3, [r2, #44]	@ 0x2c
+
+    /* Enable the PLL2 clock output */
+    if (Divider == DIVIDER_P_UPDATE)
+ 803c8a2:	683b      	ldr	r3, [r7, #0]
+ 803c8a4:	2b00      	cmp	r3, #0
+ 803c8a6:	d106      	bne.n	803c8b6 <RCCEx_PLL2_Config+0xfe>
+    {
+      __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP);
+ 803c8a8:	4b1a      	ldr	r3, [pc, #104]	@ (803c914 <RCCEx_PLL2_Config+0x15c>)
+ 803c8aa:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 803c8ac:	4a19      	ldr	r2, [pc, #100]	@ (803c914 <RCCEx_PLL2_Config+0x15c>)
+ 803c8ae:	f443 2300 	orr.w	r3, r3, #524288	@ 0x80000
+ 803c8b2:	62d3      	str	r3, [r2, #44]	@ 0x2c
+ 803c8b4:	e00f      	b.n	803c8d6 <RCCEx_PLL2_Config+0x11e>
+    }
+    else if (Divider == DIVIDER_Q_UPDATE)
+ 803c8b6:	683b      	ldr	r3, [r7, #0]
+ 803c8b8:	2b01      	cmp	r3, #1
+ 803c8ba:	d106      	bne.n	803c8ca <RCCEx_PLL2_Config+0x112>
+    {
+      __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ);
+ 803c8bc:	4b15      	ldr	r3, [pc, #84]	@ (803c914 <RCCEx_PLL2_Config+0x15c>)
+ 803c8be:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 803c8c0:	4a14      	ldr	r2, [pc, #80]	@ (803c914 <RCCEx_PLL2_Config+0x15c>)
+ 803c8c2:	f443 1380 	orr.w	r3, r3, #1048576	@ 0x100000
+ 803c8c6:	62d3      	str	r3, [r2, #44]	@ 0x2c
+ 803c8c8:	e005      	b.n	803c8d6 <RCCEx_PLL2_Config+0x11e>
+    }
+    else
+    {
+      __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVR);
+ 803c8ca:	4b12      	ldr	r3, [pc, #72]	@ (803c914 <RCCEx_PLL2_Config+0x15c>)
+ 803c8cc:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 803c8ce:	4a11      	ldr	r2, [pc, #68]	@ (803c914 <RCCEx_PLL2_Config+0x15c>)
+ 803c8d0:	f443 1300 	orr.w	r3, r3, #2097152	@ 0x200000
+ 803c8d4:	62d3      	str	r3, [r2, #44]	@ 0x2c
+    }
+
+    /* Enable  PLL2. */
+    __HAL_RCC_PLL2_ENABLE();
+ 803c8d6:	4b0f      	ldr	r3, [pc, #60]	@ (803c914 <RCCEx_PLL2_Config+0x15c>)
+ 803c8d8:	681b      	ldr	r3, [r3, #0]
+ 803c8da:	4a0e      	ldr	r2, [pc, #56]	@ (803c914 <RCCEx_PLL2_Config+0x15c>)
+ 803c8dc:	f043 6380 	orr.w	r3, r3, #67108864	@ 0x4000000
+ 803c8e0:	6013      	str	r3, [r2, #0]
+
+    /* Get Start Tick*/
+    tickstart = HAL_GetTick();
+ 803c8e2:	f7f5 f825 	bl	8031930 <HAL_GetTick>
+ 803c8e6:	60b8      	str	r0, [r7, #8]
+
+    /* Wait till PLL2 is ready */
+    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U)
+ 803c8e8:	e008      	b.n	803c8fc <RCCEx_PLL2_Config+0x144>
+    {
+      if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
+ 803c8ea:	f7f5 f821 	bl	8031930 <HAL_GetTick>
+ 803c8ee:	4602      	mov	r2, r0
+ 803c8f0:	68bb      	ldr	r3, [r7, #8]
+ 803c8f2:	1ad3      	subs	r3, r2, r3
+ 803c8f4:	2b02      	cmp	r3, #2
+ 803c8f6:	d901      	bls.n	803c8fc <RCCEx_PLL2_Config+0x144>
+      {
+        return HAL_TIMEOUT;
+ 803c8f8:	2303      	movs	r3, #3
+ 803c8fa:	e006      	b.n	803c90a <RCCEx_PLL2_Config+0x152>
+    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U)
+ 803c8fc:	4b05      	ldr	r3, [pc, #20]	@ (803c914 <RCCEx_PLL2_Config+0x15c>)
+ 803c8fe:	681b      	ldr	r3, [r3, #0]
+ 803c900:	f003 6300 	and.w	r3, r3, #134217728	@ 0x8000000
+ 803c904:	2b00      	cmp	r3, #0
+ 803c906:	d0f0      	beq.n	803c8ea <RCCEx_PLL2_Config+0x132>
+    }
+
+  }
+
+
+  return status;
+ 803c908:	7bfb      	ldrb	r3, [r7, #15]
+}
+ 803c90a:	4618      	mov	r0, r3
+ 803c90c:	3710      	adds	r7, #16
+ 803c90e:	46bd      	mov	sp, r7
+ 803c910:	bd80      	pop	{r7, pc}
+ 803c912:	bf00      	nop
+ 803c914:	58024400 	.word	0x58024400
+ 803c918:	ffff0007 	.word	0xffff0007
+
+0803c91c <RCCEx_PLL3_Config>:
+  * @note   PLL3 is temporary disabled to apply new parameters
+  *
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider)
+{
+ 803c91c:	b580      	push	{r7, lr}
+ 803c91e:	b084      	sub	sp, #16
+ 803c920:	af00      	add	r7, sp, #0
+ 803c922:	6078      	str	r0, [r7, #4]
+ 803c924:	6039      	str	r1, [r7, #0]
+  uint32_t tickstart;
+  HAL_StatusTypeDef status = HAL_OK;
+ 803c926:	2300      	movs	r3, #0
+ 803c928:	73fb      	strb	r3, [r7, #15]
+  assert_param(IS_RCC_PLL3RGE_VALUE(pll3->PLL3RGE));
+  assert_param(IS_RCC_PLL3VCO_VALUE(pll3->PLL3VCOSEL));
+  assert_param(IS_RCC_PLLFRACN_VALUE(pll3->PLL3FRACN));
+
+  /* Check that PLL3 OSC clock source is already set */
+  if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
+ 803c92a:	4b53      	ldr	r3, [pc, #332]	@ (803ca78 <RCCEx_PLL3_Config+0x15c>)
+ 803c92c:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 803c92e:	f003 0303 	and.w	r3, r3, #3
+ 803c932:	2b03      	cmp	r3, #3
+ 803c934:	d101      	bne.n	803c93a <RCCEx_PLL3_Config+0x1e>
+  {
+    return HAL_ERROR;
+ 803c936:	2301      	movs	r3, #1
+ 803c938:	e099      	b.n	803ca6e <RCCEx_PLL3_Config+0x152>
+
+
+  else
+  {
+    /* Disable  PLL3. */
+    __HAL_RCC_PLL3_DISABLE();
+ 803c93a:	4b4f      	ldr	r3, [pc, #316]	@ (803ca78 <RCCEx_PLL3_Config+0x15c>)
+ 803c93c:	681b      	ldr	r3, [r3, #0]
+ 803c93e:	4a4e      	ldr	r2, [pc, #312]	@ (803ca78 <RCCEx_PLL3_Config+0x15c>)
+ 803c940:	f023 5380 	bic.w	r3, r3, #268435456	@ 0x10000000
+ 803c944:	6013      	str	r3, [r2, #0]
+
+    /* Get Start Tick*/
+    tickstart = HAL_GetTick();
+ 803c946:	f7f4 fff3 	bl	8031930 <HAL_GetTick>
+ 803c94a:	60b8      	str	r0, [r7, #8]
+    /* Wait till PLL3 is ready */
+    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U)
+ 803c94c:	e008      	b.n	803c960 <RCCEx_PLL3_Config+0x44>
+    {
+      if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE)
+ 803c94e:	f7f4 ffef 	bl	8031930 <HAL_GetTick>
+ 803c952:	4602      	mov	r2, r0
+ 803c954:	68bb      	ldr	r3, [r7, #8]
+ 803c956:	1ad3      	subs	r3, r2, r3
+ 803c958:	2b02      	cmp	r3, #2
+ 803c95a:	d901      	bls.n	803c960 <RCCEx_PLL3_Config+0x44>
+      {
+        return HAL_TIMEOUT;
+ 803c95c:	2303      	movs	r3, #3
+ 803c95e:	e086      	b.n	803ca6e <RCCEx_PLL3_Config+0x152>
+    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U)
+ 803c960:	4b45      	ldr	r3, [pc, #276]	@ (803ca78 <RCCEx_PLL3_Config+0x15c>)
+ 803c962:	681b      	ldr	r3, [r3, #0]
+ 803c964:	f003 5300 	and.w	r3, r3, #536870912	@ 0x20000000
+ 803c968:	2b00      	cmp	r3, #0
+ 803c96a:	d1f0      	bne.n	803c94e <RCCEx_PLL3_Config+0x32>
+      }
+    }
+
+    /* Configure the PLL3  multiplication and division factors. */
+    __HAL_RCC_PLL3_CONFIG(pll3->PLL3M,
+ 803c96c:	4b42      	ldr	r3, [pc, #264]	@ (803ca78 <RCCEx_PLL3_Config+0x15c>)
+ 803c96e:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 803c970:	f023 727c 	bic.w	r2, r3, #66060288	@ 0x3f00000
+ 803c974:	687b      	ldr	r3, [r7, #4]
+ 803c976:	681b      	ldr	r3, [r3, #0]
+ 803c978:	051b      	lsls	r3, r3, #20
+ 803c97a:	493f      	ldr	r1, [pc, #252]	@ (803ca78 <RCCEx_PLL3_Config+0x15c>)
+ 803c97c:	4313      	orrs	r3, r2
+ 803c97e:	628b      	str	r3, [r1, #40]	@ 0x28
+ 803c980:	687b      	ldr	r3, [r7, #4]
+ 803c982:	685b      	ldr	r3, [r3, #4]
+ 803c984:	3b01      	subs	r3, #1
+ 803c986:	f3c3 0208 	ubfx	r2, r3, #0, #9
+ 803c98a:	687b      	ldr	r3, [r7, #4]
+ 803c98c:	689b      	ldr	r3, [r3, #8]
+ 803c98e:	3b01      	subs	r3, #1
+ 803c990:	025b      	lsls	r3, r3, #9
+ 803c992:	b29b      	uxth	r3, r3
+ 803c994:	431a      	orrs	r2, r3
+ 803c996:	687b      	ldr	r3, [r7, #4]
+ 803c998:	68db      	ldr	r3, [r3, #12]
+ 803c99a:	3b01      	subs	r3, #1
+ 803c99c:	041b      	lsls	r3, r3, #16
+ 803c99e:	f403 03fe 	and.w	r3, r3, #8323072	@ 0x7f0000
+ 803c9a2:	431a      	orrs	r2, r3
+ 803c9a4:	687b      	ldr	r3, [r7, #4]
+ 803c9a6:	691b      	ldr	r3, [r3, #16]
+ 803c9a8:	3b01      	subs	r3, #1
+ 803c9aa:	061b      	lsls	r3, r3, #24
+ 803c9ac:	f003 43fe 	and.w	r3, r3, #2130706432	@ 0x7f000000
+ 803c9b0:	4931      	ldr	r1, [pc, #196]	@ (803ca78 <RCCEx_PLL3_Config+0x15c>)
+ 803c9b2:	4313      	orrs	r3, r2
+ 803c9b4:	640b      	str	r3, [r1, #64]	@ 0x40
+                          pll3->PLL3P,
+                          pll3->PLL3Q,
+                          pll3->PLL3R);
+
+    /* Select PLL3 input reference frequency range: VCI */
+    __HAL_RCC_PLL3_VCIRANGE(pll3->PLL3RGE) ;
+ 803c9b6:	4b30      	ldr	r3, [pc, #192]	@ (803ca78 <RCCEx_PLL3_Config+0x15c>)
+ 803c9b8:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 803c9ba:	f423 6240 	bic.w	r2, r3, #3072	@ 0xc00
+ 803c9be:	687b      	ldr	r3, [r7, #4]
+ 803c9c0:	695b      	ldr	r3, [r3, #20]
+ 803c9c2:	492d      	ldr	r1, [pc, #180]	@ (803ca78 <RCCEx_PLL3_Config+0x15c>)
+ 803c9c4:	4313      	orrs	r3, r2
+ 803c9c6:	62cb      	str	r3, [r1, #44]	@ 0x2c
+
+    /* Select PLL3 output frequency range : VCO */
+    __HAL_RCC_PLL3_VCORANGE(pll3->PLL3VCOSEL) ;
+ 803c9c8:	4b2b      	ldr	r3, [pc, #172]	@ (803ca78 <RCCEx_PLL3_Config+0x15c>)
+ 803c9ca:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 803c9cc:	f423 7200 	bic.w	r2, r3, #512	@ 0x200
+ 803c9d0:	687b      	ldr	r3, [r7, #4]
+ 803c9d2:	699b      	ldr	r3, [r3, #24]
+ 803c9d4:	4928      	ldr	r1, [pc, #160]	@ (803ca78 <RCCEx_PLL3_Config+0x15c>)
+ 803c9d6:	4313      	orrs	r3, r2
+ 803c9d8:	62cb      	str	r3, [r1, #44]	@ 0x2c
+
+    /* Disable PLL3FRACN . */
+    __HAL_RCC_PLL3FRACN_DISABLE();
+ 803c9da:	4b27      	ldr	r3, [pc, #156]	@ (803ca78 <RCCEx_PLL3_Config+0x15c>)
+ 803c9dc:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 803c9de:	4a26      	ldr	r2, [pc, #152]	@ (803ca78 <RCCEx_PLL3_Config+0x15c>)
+ 803c9e0:	f423 7380 	bic.w	r3, r3, #256	@ 0x100
+ 803c9e4:	62d3      	str	r3, [r2, #44]	@ 0x2c
+
+    /* Configures PLL3 clock Fractional Part Of The Multiplication Factor */
+    __HAL_RCC_PLL3FRACN_CONFIG(pll3->PLL3FRACN);
+ 803c9e6:	4b24      	ldr	r3, [pc, #144]	@ (803ca78 <RCCEx_PLL3_Config+0x15c>)
+ 803c9e8:	6c5a      	ldr	r2, [r3, #68]	@ 0x44
+ 803c9ea:	4b24      	ldr	r3, [pc, #144]	@ (803ca7c <RCCEx_PLL3_Config+0x160>)
+ 803c9ec:	4013      	ands	r3, r2
+ 803c9ee:	687a      	ldr	r2, [r7, #4]
+ 803c9f0:	69d2      	ldr	r2, [r2, #28]
+ 803c9f2:	00d2      	lsls	r2, r2, #3
+ 803c9f4:	4920      	ldr	r1, [pc, #128]	@ (803ca78 <RCCEx_PLL3_Config+0x15c>)
+ 803c9f6:	4313      	orrs	r3, r2
+ 803c9f8:	644b      	str	r3, [r1, #68]	@ 0x44
+
+    /* Enable PLL3FRACN . */
+    __HAL_RCC_PLL3FRACN_ENABLE();
+ 803c9fa:	4b1f      	ldr	r3, [pc, #124]	@ (803ca78 <RCCEx_PLL3_Config+0x15c>)
+ 803c9fc:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 803c9fe:	4a1e      	ldr	r2, [pc, #120]	@ (803ca78 <RCCEx_PLL3_Config+0x15c>)
+ 803ca00:	f443 7380 	orr.w	r3, r3, #256	@ 0x100
+ 803ca04:	62d3      	str	r3, [r2, #44]	@ 0x2c
+
+    /* Enable the PLL3 clock output */
+    if (Divider == DIVIDER_P_UPDATE)
+ 803ca06:	683b      	ldr	r3, [r7, #0]
+ 803ca08:	2b00      	cmp	r3, #0
+ 803ca0a:	d106      	bne.n	803ca1a <RCCEx_PLL3_Config+0xfe>
+    {
+      __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP);
+ 803ca0c:	4b1a      	ldr	r3, [pc, #104]	@ (803ca78 <RCCEx_PLL3_Config+0x15c>)
+ 803ca0e:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 803ca10:	4a19      	ldr	r2, [pc, #100]	@ (803ca78 <RCCEx_PLL3_Config+0x15c>)
+ 803ca12:	f443 0380 	orr.w	r3, r3, #4194304	@ 0x400000
+ 803ca16:	62d3      	str	r3, [r2, #44]	@ 0x2c
+ 803ca18:	e00f      	b.n	803ca3a <RCCEx_PLL3_Config+0x11e>
+    }
+    else if (Divider == DIVIDER_Q_UPDATE)
+ 803ca1a:	683b      	ldr	r3, [r7, #0]
+ 803ca1c:	2b01      	cmp	r3, #1
+ 803ca1e:	d106      	bne.n	803ca2e <RCCEx_PLL3_Config+0x112>
+    {
+      __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
+ 803ca20:	4b15      	ldr	r3, [pc, #84]	@ (803ca78 <RCCEx_PLL3_Config+0x15c>)
+ 803ca22:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 803ca24:	4a14      	ldr	r2, [pc, #80]	@ (803ca78 <RCCEx_PLL3_Config+0x15c>)
+ 803ca26:	f443 0300 	orr.w	r3, r3, #8388608	@ 0x800000
+ 803ca2a:	62d3      	str	r3, [r2, #44]	@ 0x2c
+ 803ca2c:	e005      	b.n	803ca3a <RCCEx_PLL3_Config+0x11e>
+    }
+    else
+    {
+      __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);
+ 803ca2e:	4b12      	ldr	r3, [pc, #72]	@ (803ca78 <RCCEx_PLL3_Config+0x15c>)
+ 803ca30:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 803ca32:	4a11      	ldr	r2, [pc, #68]	@ (803ca78 <RCCEx_PLL3_Config+0x15c>)
+ 803ca34:	f043 7380 	orr.w	r3, r3, #16777216	@ 0x1000000
+ 803ca38:	62d3      	str	r3, [r2, #44]	@ 0x2c
+    }
+
+    /* Enable  PLL3. */
+    __HAL_RCC_PLL3_ENABLE();
+ 803ca3a:	4b0f      	ldr	r3, [pc, #60]	@ (803ca78 <RCCEx_PLL3_Config+0x15c>)
+ 803ca3c:	681b      	ldr	r3, [r3, #0]
+ 803ca3e:	4a0e      	ldr	r2, [pc, #56]	@ (803ca78 <RCCEx_PLL3_Config+0x15c>)
+ 803ca40:	f043 5380 	orr.w	r3, r3, #268435456	@ 0x10000000
+ 803ca44:	6013      	str	r3, [r2, #0]
+
+    /* Get Start Tick*/
+    tickstart = HAL_GetTick();
+ 803ca46:	f7f4 ff73 	bl	8031930 <HAL_GetTick>
+ 803ca4a:	60b8      	str	r0, [r7, #8]
+
+    /* Wait till PLL3 is ready */
+    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U)
+ 803ca4c:	e008      	b.n	803ca60 <RCCEx_PLL3_Config+0x144>
+    {
+      if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE)
+ 803ca4e:	f7f4 ff6f 	bl	8031930 <HAL_GetTick>
+ 803ca52:	4602      	mov	r2, r0
+ 803ca54:	68bb      	ldr	r3, [r7, #8]
+ 803ca56:	1ad3      	subs	r3, r2, r3
+ 803ca58:	2b02      	cmp	r3, #2
+ 803ca5a:	d901      	bls.n	803ca60 <RCCEx_PLL3_Config+0x144>
+      {
+        return HAL_TIMEOUT;
+ 803ca5c:	2303      	movs	r3, #3
+ 803ca5e:	e006      	b.n	803ca6e <RCCEx_PLL3_Config+0x152>
+    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U)
+ 803ca60:	4b05      	ldr	r3, [pc, #20]	@ (803ca78 <RCCEx_PLL3_Config+0x15c>)
+ 803ca62:	681b      	ldr	r3, [r3, #0]
+ 803ca64:	f003 5300 	and.w	r3, r3, #536870912	@ 0x20000000
+ 803ca68:	2b00      	cmp	r3, #0
+ 803ca6a:	d0f0      	beq.n	803ca4e <RCCEx_PLL3_Config+0x132>
+    }
+
+  }
+
+
+  return status;
+ 803ca6c:	7bfb      	ldrb	r3, [r7, #15]
+}
+ 803ca6e:	4618      	mov	r0, r3
+ 803ca70:	3710      	adds	r7, #16
+ 803ca72:	46bd      	mov	sp, r7
+ 803ca74:	bd80      	pop	{r7, pc}
+ 803ca76:	bf00      	nop
+ 803ca78:	58024400 	.word	0x58024400
+ 803ca7c:	ffff0007 	.word	0xffff0007
+
+0803ca80 <HAL_TIM_Base_Init>:
+  *         Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
+{
+ 803ca80:	b580      	push	{r7, lr}
+ 803ca82:	b082      	sub	sp, #8
+ 803ca84:	af00      	add	r7, sp, #0
+ 803ca86:	6078      	str	r0, [r7, #4]
+  /* Check the TIM handle allocation */
+  if (htim == NULL)
+ 803ca88:	687b      	ldr	r3, [r7, #4]
+ 803ca8a:	2b00      	cmp	r3, #0
+ 803ca8c:	d101      	bne.n	803ca92 <HAL_TIM_Base_Init+0x12>
+  {
+    return HAL_ERROR;
+ 803ca8e:	2301      	movs	r3, #1
+ 803ca90:	e049      	b.n	803cb26 <HAL_TIM_Base_Init+0xa6>
+  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
+  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+
+  if (htim->State == HAL_TIM_STATE_RESET)
+ 803ca92:	687b      	ldr	r3, [r7, #4]
+ 803ca94:	f893 303d 	ldrb.w	r3, [r3, #61]	@ 0x3d
+ 803ca98:	b2db      	uxtb	r3, r3
+ 803ca9a:	2b00      	cmp	r3, #0
+ 803ca9c:	d106      	bne.n	803caac <HAL_TIM_Base_Init+0x2c>
+  {
+    /* Allocate lock resource and initialize it */
+    htim->Lock = HAL_UNLOCKED;
+ 803ca9e:	687b      	ldr	r3, [r7, #4]
+ 803caa0:	2200      	movs	r2, #0
+ 803caa2:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c
+    }
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    htim->Base_MspInitCallback(htim);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    HAL_TIM_Base_MspInit(htim);
+ 803caa6:	6878      	ldr	r0, [r7, #4]
+ 803caa8:	f7f3 fe16 	bl	80306d8 <HAL_TIM_Base_MspInit>
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+ 803caac:	687b      	ldr	r3, [r7, #4]
+ 803caae:	2202      	movs	r2, #2
+ 803cab0:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d
+
+  /* Set the Time Base configuration */
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+ 803cab4:	687b      	ldr	r3, [r7, #4]
+ 803cab6:	681a      	ldr	r2, [r3, #0]
+ 803cab8:	687b      	ldr	r3, [r7, #4]
+ 803caba:	3304      	adds	r3, #4
+ 803cabc:	4619      	mov	r1, r3
+ 803cabe:	4610      	mov	r0, r2
+ 803cac0:	f000 fad6 	bl	803d070 <TIM_Base_SetConfig>
+
+  /* Initialize the DMA burst operation state */
+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+ 803cac4:	687b      	ldr	r3, [r7, #4]
+ 803cac6:	2201      	movs	r2, #1
+ 803cac8:	f883 2048 	strb.w	r2, [r3, #72]	@ 0x48
+
+  /* Initialize the TIM channels state */
+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 803cacc:	687b      	ldr	r3, [r7, #4]
+ 803cace:	2201      	movs	r2, #1
+ 803cad0:	f883 203e 	strb.w	r2, [r3, #62]	@ 0x3e
+ 803cad4:	687b      	ldr	r3, [r7, #4]
+ 803cad6:	2201      	movs	r2, #1
+ 803cad8:	f883 203f 	strb.w	r2, [r3, #63]	@ 0x3f
+ 803cadc:	687b      	ldr	r3, [r7, #4]
+ 803cade:	2201      	movs	r2, #1
+ 803cae0:	f883 2040 	strb.w	r2, [r3, #64]	@ 0x40
+ 803cae4:	687b      	ldr	r3, [r7, #4]
+ 803cae6:	2201      	movs	r2, #1
+ 803cae8:	f883 2041 	strb.w	r2, [r3, #65]	@ 0x41
+ 803caec:	687b      	ldr	r3, [r7, #4]
+ 803caee:	2201      	movs	r2, #1
+ 803caf0:	f883 2042 	strb.w	r2, [r3, #66]	@ 0x42
+ 803caf4:	687b      	ldr	r3, [r7, #4]
+ 803caf6:	2201      	movs	r2, #1
+ 803caf8:	f883 2043 	strb.w	r2, [r3, #67]	@ 0x43
+  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 803cafc:	687b      	ldr	r3, [r7, #4]
+ 803cafe:	2201      	movs	r2, #1
+ 803cb00:	f883 2044 	strb.w	r2, [r3, #68]	@ 0x44
+ 803cb04:	687b      	ldr	r3, [r7, #4]
+ 803cb06:	2201      	movs	r2, #1
+ 803cb08:	f883 2045 	strb.w	r2, [r3, #69]	@ 0x45
+ 803cb0c:	687b      	ldr	r3, [r7, #4]
+ 803cb0e:	2201      	movs	r2, #1
+ 803cb10:	f883 2046 	strb.w	r2, [r3, #70]	@ 0x46
+ 803cb14:	687b      	ldr	r3, [r7, #4]
+ 803cb16:	2201      	movs	r2, #1
+ 803cb18:	f883 2047 	strb.w	r2, [r3, #71]	@ 0x47
+
+  /* Initialize the TIM state*/
+  htim->State = HAL_TIM_STATE_READY;
+ 803cb1c:	687b      	ldr	r3, [r7, #4]
+ 803cb1e:	2201      	movs	r2, #1
+ 803cb20:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d
+
+  return HAL_OK;
+ 803cb24:	2300      	movs	r3, #0
+}
+ 803cb26:	4618      	mov	r0, r3
+ 803cb28:	3708      	adds	r7, #8
+ 803cb2a:	46bd      	mov	sp, r7
+ 803cb2c:	bd80      	pop	{r7, pc}
+	...
+
+0803cb30 <HAL_TIM_Base_Start_IT>:
+  * @brief  Starts the TIM Base generation in interrupt mode.
+  * @param  htim TIM Base handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
+{
+ 803cb30:	b480      	push	{r7}
+ 803cb32:	b085      	sub	sp, #20
+ 803cb34:	af00      	add	r7, sp, #0
+ 803cb36:	6078      	str	r0, [r7, #4]
+
+  /* Check the parameters */
+  assert_param(IS_TIM_INSTANCE(htim->Instance));
+
+  /* Check the TIM state */
+  if (htim->State != HAL_TIM_STATE_READY)
+ 803cb38:	687b      	ldr	r3, [r7, #4]
+ 803cb3a:	f893 303d 	ldrb.w	r3, [r3, #61]	@ 0x3d
+ 803cb3e:	b2db      	uxtb	r3, r3
+ 803cb40:	2b01      	cmp	r3, #1
+ 803cb42:	d001      	beq.n	803cb48 <HAL_TIM_Base_Start_IT+0x18>
+  {
+    return HAL_ERROR;
+ 803cb44:	2301      	movs	r3, #1
+ 803cb46:	e054      	b.n	803cbf2 <HAL_TIM_Base_Start_IT+0xc2>
+  }
+
+  /* Set the TIM state */
+  htim->State = HAL_TIM_STATE_BUSY;
+ 803cb48:	687b      	ldr	r3, [r7, #4]
+ 803cb4a:	2202      	movs	r2, #2
+ 803cb4c:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d
+
+  /* Enable the TIM Update interrupt */
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
+ 803cb50:	687b      	ldr	r3, [r7, #4]
+ 803cb52:	681b      	ldr	r3, [r3, #0]
+ 803cb54:	68da      	ldr	r2, [r3, #12]
+ 803cb56:	687b      	ldr	r3, [r7, #4]
+ 803cb58:	681b      	ldr	r3, [r3, #0]
+ 803cb5a:	f042 0201 	orr.w	r2, r2, #1
+ 803cb5e:	60da      	str	r2, [r3, #12]
+
+  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ 803cb60:	687b      	ldr	r3, [r7, #4]
+ 803cb62:	681b      	ldr	r3, [r3, #0]
+ 803cb64:	4a26      	ldr	r2, [pc, #152]	@ (803cc00 <HAL_TIM_Base_Start_IT+0xd0>)
+ 803cb66:	4293      	cmp	r3, r2
+ 803cb68:	d022      	beq.n	803cbb0 <HAL_TIM_Base_Start_IT+0x80>
+ 803cb6a:	687b      	ldr	r3, [r7, #4]
+ 803cb6c:	681b      	ldr	r3, [r3, #0]
+ 803cb6e:	f1b3 4f80 	cmp.w	r3, #1073741824	@ 0x40000000
+ 803cb72:	d01d      	beq.n	803cbb0 <HAL_TIM_Base_Start_IT+0x80>
+ 803cb74:	687b      	ldr	r3, [r7, #4]
+ 803cb76:	681b      	ldr	r3, [r3, #0]
+ 803cb78:	4a22      	ldr	r2, [pc, #136]	@ (803cc04 <HAL_TIM_Base_Start_IT+0xd4>)
+ 803cb7a:	4293      	cmp	r3, r2
+ 803cb7c:	d018      	beq.n	803cbb0 <HAL_TIM_Base_Start_IT+0x80>
+ 803cb7e:	687b      	ldr	r3, [r7, #4]
+ 803cb80:	681b      	ldr	r3, [r3, #0]
+ 803cb82:	4a21      	ldr	r2, [pc, #132]	@ (803cc08 <HAL_TIM_Base_Start_IT+0xd8>)
+ 803cb84:	4293      	cmp	r3, r2
+ 803cb86:	d013      	beq.n	803cbb0 <HAL_TIM_Base_Start_IT+0x80>
+ 803cb88:	687b      	ldr	r3, [r7, #4]
+ 803cb8a:	681b      	ldr	r3, [r3, #0]
+ 803cb8c:	4a1f      	ldr	r2, [pc, #124]	@ (803cc0c <HAL_TIM_Base_Start_IT+0xdc>)
+ 803cb8e:	4293      	cmp	r3, r2
+ 803cb90:	d00e      	beq.n	803cbb0 <HAL_TIM_Base_Start_IT+0x80>
+ 803cb92:	687b      	ldr	r3, [r7, #4]
+ 803cb94:	681b      	ldr	r3, [r3, #0]
+ 803cb96:	4a1e      	ldr	r2, [pc, #120]	@ (803cc10 <HAL_TIM_Base_Start_IT+0xe0>)
+ 803cb98:	4293      	cmp	r3, r2
+ 803cb9a:	d009      	beq.n	803cbb0 <HAL_TIM_Base_Start_IT+0x80>
+ 803cb9c:	687b      	ldr	r3, [r7, #4]
+ 803cb9e:	681b      	ldr	r3, [r3, #0]
+ 803cba0:	4a1c      	ldr	r2, [pc, #112]	@ (803cc14 <HAL_TIM_Base_Start_IT+0xe4>)
+ 803cba2:	4293      	cmp	r3, r2
+ 803cba4:	d004      	beq.n	803cbb0 <HAL_TIM_Base_Start_IT+0x80>
+ 803cba6:	687b      	ldr	r3, [r7, #4]
+ 803cba8:	681b      	ldr	r3, [r3, #0]
+ 803cbaa:	4a1b      	ldr	r2, [pc, #108]	@ (803cc18 <HAL_TIM_Base_Start_IT+0xe8>)
+ 803cbac:	4293      	cmp	r3, r2
+ 803cbae:	d115      	bne.n	803cbdc <HAL_TIM_Base_Start_IT+0xac>
+  {
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ 803cbb0:	687b      	ldr	r3, [r7, #4]
+ 803cbb2:	681b      	ldr	r3, [r3, #0]
+ 803cbb4:	689a      	ldr	r2, [r3, #8]
+ 803cbb6:	4b19      	ldr	r3, [pc, #100]	@ (803cc1c <HAL_TIM_Base_Start_IT+0xec>)
+ 803cbb8:	4013      	ands	r3, r2
+ 803cbba:	60fb      	str	r3, [r7, #12]
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 803cbbc:	68fb      	ldr	r3, [r7, #12]
+ 803cbbe:	2b06      	cmp	r3, #6
+ 803cbc0:	d015      	beq.n	803cbee <HAL_TIM_Base_Start_IT+0xbe>
+ 803cbc2:	68fb      	ldr	r3, [r7, #12]
+ 803cbc4:	f5b3 3f80 	cmp.w	r3, #65536	@ 0x10000
+ 803cbc8:	d011      	beq.n	803cbee <HAL_TIM_Base_Start_IT+0xbe>
+    {
+      __HAL_TIM_ENABLE(htim);
+ 803cbca:	687b      	ldr	r3, [r7, #4]
+ 803cbcc:	681b      	ldr	r3, [r3, #0]
+ 803cbce:	681a      	ldr	r2, [r3, #0]
+ 803cbd0:	687b      	ldr	r3, [r7, #4]
+ 803cbd2:	681b      	ldr	r3, [r3, #0]
+ 803cbd4:	f042 0201 	orr.w	r2, r2, #1
+ 803cbd8:	601a      	str	r2, [r3, #0]
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 803cbda:	e008      	b.n	803cbee <HAL_TIM_Base_Start_IT+0xbe>
+    }
+  }
+  else
+  {
+    __HAL_TIM_ENABLE(htim);
+ 803cbdc:	687b      	ldr	r3, [r7, #4]
+ 803cbde:	681b      	ldr	r3, [r3, #0]
+ 803cbe0:	681a      	ldr	r2, [r3, #0]
+ 803cbe2:	687b      	ldr	r3, [r7, #4]
+ 803cbe4:	681b      	ldr	r3, [r3, #0]
+ 803cbe6:	f042 0201 	orr.w	r2, r2, #1
+ 803cbea:	601a      	str	r2, [r3, #0]
+ 803cbec:	e000      	b.n	803cbf0 <HAL_TIM_Base_Start_IT+0xc0>
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 803cbee:	bf00      	nop
+  }
+
+  /* Return function status */
+  return HAL_OK;
+ 803cbf0:	2300      	movs	r3, #0
+}
+ 803cbf2:	4618      	mov	r0, r3
+ 803cbf4:	3714      	adds	r7, #20
+ 803cbf6:	46bd      	mov	sp, r7
+ 803cbf8:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 803cbfc:	4770      	bx	lr
+ 803cbfe:	bf00      	nop
+ 803cc00:	40010000 	.word	0x40010000
+ 803cc04:	40000400 	.word	0x40000400
+ 803cc08:	40000800 	.word	0x40000800
+ 803cc0c:	40000c00 	.word	0x40000c00
+ 803cc10:	40010400 	.word	0x40010400
+ 803cc14:	40001800 	.word	0x40001800
+ 803cc18:	40014000 	.word	0x40014000
+ 803cc1c:	00010007 	.word	0x00010007
+
+0803cc20 <HAL_TIM_IRQHandler>:
+  * @brief  This function handles TIM interrupts requests.
+  * @param  htim TIM  handle
+  * @retval None
+  */
+void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
+{
+ 803cc20:	b580      	push	{r7, lr}
+ 803cc22:	b084      	sub	sp, #16
+ 803cc24:	af00      	add	r7, sp, #0
+ 803cc26:	6078      	str	r0, [r7, #4]
+  uint32_t itsource = htim->Instance->DIER;
+ 803cc28:	687b      	ldr	r3, [r7, #4]
+ 803cc2a:	681b      	ldr	r3, [r3, #0]
+ 803cc2c:	68db      	ldr	r3, [r3, #12]
+ 803cc2e:	60fb      	str	r3, [r7, #12]
+  uint32_t itflag   = htim->Instance->SR;
+ 803cc30:	687b      	ldr	r3, [r7, #4]
+ 803cc32:	681b      	ldr	r3, [r3, #0]
+ 803cc34:	691b      	ldr	r3, [r3, #16]
+ 803cc36:	60bb      	str	r3, [r7, #8]
+
+  /* Capture compare 1 event */
+  if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
+ 803cc38:	68bb      	ldr	r3, [r7, #8]
+ 803cc3a:	f003 0302 	and.w	r3, r3, #2
+ 803cc3e:	2b00      	cmp	r3, #0
+ 803cc40:	d020      	beq.n	803cc84 <HAL_TIM_IRQHandler+0x64>
+  {
+    if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
+ 803cc42:	68fb      	ldr	r3, [r7, #12]
+ 803cc44:	f003 0302 	and.w	r3, r3, #2
+ 803cc48:	2b00      	cmp	r3, #0
+ 803cc4a:	d01b      	beq.n	803cc84 <HAL_TIM_IRQHandler+0x64>
+    {
+      {
+        __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
+ 803cc4c:	687b      	ldr	r3, [r7, #4]
+ 803cc4e:	681b      	ldr	r3, [r3, #0]
+ 803cc50:	f06f 0202 	mvn.w	r2, #2
+ 803cc54:	611a      	str	r2, [r3, #16]
+        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+ 803cc56:	687b      	ldr	r3, [r7, #4]
+ 803cc58:	2201      	movs	r2, #1
+ 803cc5a:	771a      	strb	r2, [r3, #28]
+
+        /* Input capture event */
+        if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
+ 803cc5c:	687b      	ldr	r3, [r7, #4]
+ 803cc5e:	681b      	ldr	r3, [r3, #0]
+ 803cc60:	699b      	ldr	r3, [r3, #24]
+ 803cc62:	f003 0303 	and.w	r3, r3, #3
+ 803cc66:	2b00      	cmp	r3, #0
+ 803cc68:	d003      	beq.n	803cc72 <HAL_TIM_IRQHandler+0x52>
+        {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+          htim->IC_CaptureCallback(htim);
+#else
+          HAL_TIM_IC_CaptureCallback(htim);
+ 803cc6a:	6878      	ldr	r0, [r7, #4]
+ 803cc6c:	f000 f9e2 	bl	803d034 <HAL_TIM_IC_CaptureCallback>
+ 803cc70:	e005      	b.n	803cc7e <HAL_TIM_IRQHandler+0x5e>
+        {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+          htim->OC_DelayElapsedCallback(htim);
+          htim->PWM_PulseFinishedCallback(htim);
+#else
+          HAL_TIM_OC_DelayElapsedCallback(htim);
+ 803cc72:	6878      	ldr	r0, [r7, #4]
+ 803cc74:	f000 f9d4 	bl	803d020 <HAL_TIM_OC_DelayElapsedCallback>
+          HAL_TIM_PWM_PulseFinishedCallback(htim);
+ 803cc78:	6878      	ldr	r0, [r7, #4]
+ 803cc7a:	f000 f9e5 	bl	803d048 <HAL_TIM_PWM_PulseFinishedCallback>
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+        }
+        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ 803cc7e:	687b      	ldr	r3, [r7, #4]
+ 803cc80:	2200      	movs	r2, #0
+ 803cc82:	771a      	strb	r2, [r3, #28]
+      }
+    }
+  }
+  /* Capture compare 2 event */
+  if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
+ 803cc84:	68bb      	ldr	r3, [r7, #8]
+ 803cc86:	f003 0304 	and.w	r3, r3, #4
+ 803cc8a:	2b00      	cmp	r3, #0
+ 803cc8c:	d020      	beq.n	803ccd0 <HAL_TIM_IRQHandler+0xb0>
+  {
+    if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
+ 803cc8e:	68fb      	ldr	r3, [r7, #12]
+ 803cc90:	f003 0304 	and.w	r3, r3, #4
+ 803cc94:	2b00      	cmp	r3, #0
+ 803cc96:	d01b      	beq.n	803ccd0 <HAL_TIM_IRQHandler+0xb0>
+    {
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
+ 803cc98:	687b      	ldr	r3, [r7, #4]
+ 803cc9a:	681b      	ldr	r3, [r3, #0]
+ 803cc9c:	f06f 0204 	mvn.w	r2, #4
+ 803cca0:	611a      	str	r2, [r3, #16]
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ 803cca2:	687b      	ldr	r3, [r7, #4]
+ 803cca4:	2202      	movs	r2, #2
+ 803cca6:	771a      	strb	r2, [r3, #28]
+      /* Input capture event */
+      if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
+ 803cca8:	687b      	ldr	r3, [r7, #4]
+ 803ccaa:	681b      	ldr	r3, [r3, #0]
+ 803ccac:	699b      	ldr	r3, [r3, #24]
+ 803ccae:	f403 7340 	and.w	r3, r3, #768	@ 0x300
+ 803ccb2:	2b00      	cmp	r3, #0
+ 803ccb4:	d003      	beq.n	803ccbe <HAL_TIM_IRQHandler+0x9e>
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->IC_CaptureCallback(htim);
+#else
+        HAL_TIM_IC_CaptureCallback(htim);
+ 803ccb6:	6878      	ldr	r0, [r7, #4]
+ 803ccb8:	f000 f9bc 	bl	803d034 <HAL_TIM_IC_CaptureCallback>
+ 803ccbc:	e005      	b.n	803ccca <HAL_TIM_IRQHandler+0xaa>
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->OC_DelayElapsedCallback(htim);
+        htim->PWM_PulseFinishedCallback(htim);
+#else
+        HAL_TIM_OC_DelayElapsedCallback(htim);
+ 803ccbe:	6878      	ldr	r0, [r7, #4]
+ 803ccc0:	f000 f9ae 	bl	803d020 <HAL_TIM_OC_DelayElapsedCallback>
+        HAL_TIM_PWM_PulseFinishedCallback(htim);
+ 803ccc4:	6878      	ldr	r0, [r7, #4]
+ 803ccc6:	f000 f9bf 	bl	803d048 <HAL_TIM_PWM_PulseFinishedCallback>
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ 803ccca:	687b      	ldr	r3, [r7, #4]
+ 803cccc:	2200      	movs	r2, #0
+ 803ccce:	771a      	strb	r2, [r3, #28]
+    }
+  }
+  /* Capture compare 3 event */
+  if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
+ 803ccd0:	68bb      	ldr	r3, [r7, #8]
+ 803ccd2:	f003 0308 	and.w	r3, r3, #8
+ 803ccd6:	2b00      	cmp	r3, #0
+ 803ccd8:	d020      	beq.n	803cd1c <HAL_TIM_IRQHandler+0xfc>
+  {
+    if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
+ 803ccda:	68fb      	ldr	r3, [r7, #12]
+ 803ccdc:	f003 0308 	and.w	r3, r3, #8
+ 803cce0:	2b00      	cmp	r3, #0
+ 803cce2:	d01b      	beq.n	803cd1c <HAL_TIM_IRQHandler+0xfc>
+    {
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
+ 803cce4:	687b      	ldr	r3, [r7, #4]
+ 803cce6:	681b      	ldr	r3, [r3, #0]
+ 803cce8:	f06f 0208 	mvn.w	r2, #8
+ 803ccec:	611a      	str	r2, [r3, #16]
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ 803ccee:	687b      	ldr	r3, [r7, #4]
+ 803ccf0:	2204      	movs	r2, #4
+ 803ccf2:	771a      	strb	r2, [r3, #28]
+      /* Input capture event */
+      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
+ 803ccf4:	687b      	ldr	r3, [r7, #4]
+ 803ccf6:	681b      	ldr	r3, [r3, #0]
+ 803ccf8:	69db      	ldr	r3, [r3, #28]
+ 803ccfa:	f003 0303 	and.w	r3, r3, #3
+ 803ccfe:	2b00      	cmp	r3, #0
+ 803cd00:	d003      	beq.n	803cd0a <HAL_TIM_IRQHandler+0xea>
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->IC_CaptureCallback(htim);
+#else
+        HAL_TIM_IC_CaptureCallback(htim);
+ 803cd02:	6878      	ldr	r0, [r7, #4]
+ 803cd04:	f000 f996 	bl	803d034 <HAL_TIM_IC_CaptureCallback>
+ 803cd08:	e005      	b.n	803cd16 <HAL_TIM_IRQHandler+0xf6>
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->OC_DelayElapsedCallback(htim);
+        htim->PWM_PulseFinishedCallback(htim);
+#else
+        HAL_TIM_OC_DelayElapsedCallback(htim);
+ 803cd0a:	6878      	ldr	r0, [r7, #4]
+ 803cd0c:	f000 f988 	bl	803d020 <HAL_TIM_OC_DelayElapsedCallback>
+        HAL_TIM_PWM_PulseFinishedCallback(htim);
+ 803cd10:	6878      	ldr	r0, [r7, #4]
+ 803cd12:	f000 f999 	bl	803d048 <HAL_TIM_PWM_PulseFinishedCallback>
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ 803cd16:	687b      	ldr	r3, [r7, #4]
+ 803cd18:	2200      	movs	r2, #0
+ 803cd1a:	771a      	strb	r2, [r3, #28]
+    }
+  }
+  /* Capture compare 4 event */
+  if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
+ 803cd1c:	68bb      	ldr	r3, [r7, #8]
+ 803cd1e:	f003 0310 	and.w	r3, r3, #16
+ 803cd22:	2b00      	cmp	r3, #0
+ 803cd24:	d020      	beq.n	803cd68 <HAL_TIM_IRQHandler+0x148>
+  {
+    if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
+ 803cd26:	68fb      	ldr	r3, [r7, #12]
+ 803cd28:	f003 0310 	and.w	r3, r3, #16
+ 803cd2c:	2b00      	cmp	r3, #0
+ 803cd2e:	d01b      	beq.n	803cd68 <HAL_TIM_IRQHandler+0x148>
+    {
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
+ 803cd30:	687b      	ldr	r3, [r7, #4]
+ 803cd32:	681b      	ldr	r3, [r3, #0]
+ 803cd34:	f06f 0210 	mvn.w	r2, #16
+ 803cd38:	611a      	str	r2, [r3, #16]
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+ 803cd3a:	687b      	ldr	r3, [r7, #4]
+ 803cd3c:	2208      	movs	r2, #8
+ 803cd3e:	771a      	strb	r2, [r3, #28]
+      /* Input capture event */
+      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
+ 803cd40:	687b      	ldr	r3, [r7, #4]
+ 803cd42:	681b      	ldr	r3, [r3, #0]
+ 803cd44:	69db      	ldr	r3, [r3, #28]
+ 803cd46:	f403 7340 	and.w	r3, r3, #768	@ 0x300
+ 803cd4a:	2b00      	cmp	r3, #0
+ 803cd4c:	d003      	beq.n	803cd56 <HAL_TIM_IRQHandler+0x136>
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->IC_CaptureCallback(htim);
+#else
+        HAL_TIM_IC_CaptureCallback(htim);
+ 803cd4e:	6878      	ldr	r0, [r7, #4]
+ 803cd50:	f000 f970 	bl	803d034 <HAL_TIM_IC_CaptureCallback>
+ 803cd54:	e005      	b.n	803cd62 <HAL_TIM_IRQHandler+0x142>
+      {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+        htim->OC_DelayElapsedCallback(htim);
+        htim->PWM_PulseFinishedCallback(htim);
+#else
+        HAL_TIM_OC_DelayElapsedCallback(htim);
+ 803cd56:	6878      	ldr	r0, [r7, #4]
+ 803cd58:	f000 f962 	bl	803d020 <HAL_TIM_OC_DelayElapsedCallback>
+        HAL_TIM_PWM_PulseFinishedCallback(htim);
+ 803cd5c:	6878      	ldr	r0, [r7, #4]
+ 803cd5e:	f000 f973 	bl	803d048 <HAL_TIM_PWM_PulseFinishedCallback>
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+      }
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ 803cd62:	687b      	ldr	r3, [r7, #4]
+ 803cd64:	2200      	movs	r2, #0
+ 803cd66:	771a      	strb	r2, [r3, #28]
+    }
+  }
+  /* TIM Update event */
+  if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
+ 803cd68:	68bb      	ldr	r3, [r7, #8]
+ 803cd6a:	f003 0301 	and.w	r3, r3, #1
+ 803cd6e:	2b00      	cmp	r3, #0
+ 803cd70:	d00c      	beq.n	803cd8c <HAL_TIM_IRQHandler+0x16c>
+  {
+    if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
+ 803cd72:	68fb      	ldr	r3, [r7, #12]
+ 803cd74:	f003 0301 	and.w	r3, r3, #1
+ 803cd78:	2b00      	cmp	r3, #0
+ 803cd7a:	d007      	beq.n	803cd8c <HAL_TIM_IRQHandler+0x16c>
+    {
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
+ 803cd7c:	687b      	ldr	r3, [r7, #4]
+ 803cd7e:	681b      	ldr	r3, [r3, #0]
+ 803cd80:	f06f 0201 	mvn.w	r2, #1
+ 803cd84:	611a      	str	r2, [r3, #16]
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->PeriodElapsedCallback(htim);
+#else
+      HAL_TIM_PeriodElapsedCallback(htim);
+ 803cd86:	6878      	ldr	r0, [r7, #4]
+ 803cd88:	f7e4 fb68 	bl	802145c <HAL_TIM_PeriodElapsedCallback>
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+  /* TIM Break input event */
+  if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
+ 803cd8c:	68bb      	ldr	r3, [r7, #8]
+ 803cd8e:	f003 0380 	and.w	r3, r3, #128	@ 0x80
+ 803cd92:	2b00      	cmp	r3, #0
+ 803cd94:	d104      	bne.n	803cda0 <HAL_TIM_IRQHandler+0x180>
+      ((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK)))
+ 803cd96:	68bb      	ldr	r3, [r7, #8]
+ 803cd98:	f403 5300 	and.w	r3, r3, #8192	@ 0x2000
+  if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
+ 803cd9c:	2b00      	cmp	r3, #0
+ 803cd9e:	d00c      	beq.n	803cdba <HAL_TIM_IRQHandler+0x19a>
+  {
+    if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
+ 803cda0:	68fb      	ldr	r3, [r7, #12]
+ 803cda2:	f003 0380 	and.w	r3, r3, #128	@ 0x80
+ 803cda6:	2b00      	cmp	r3, #0
+ 803cda8:	d007      	beq.n	803cdba <HAL_TIM_IRQHandler+0x19a>
+    {
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK);
+ 803cdaa:	687b      	ldr	r3, [r7, #4]
+ 803cdac:	681b      	ldr	r3, [r3, #0]
+ 803cdae:	f46f 5202 	mvn.w	r2, #8320	@ 0x2080
+ 803cdb2:	611a      	str	r2, [r3, #16]
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->BreakCallback(htim);
+#else
+      HAL_TIMEx_BreakCallback(htim);
+ 803cdb4:	6878      	ldr	r0, [r7, #4]
+ 803cdb6:	f000 fb37 	bl	803d428 <HAL_TIMEx_BreakCallback>
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+  /* TIM Break2 input event */
+  if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2))
+ 803cdba:	68bb      	ldr	r3, [r7, #8]
+ 803cdbc:	f403 7380 	and.w	r3, r3, #256	@ 0x100
+ 803cdc0:	2b00      	cmp	r3, #0
+ 803cdc2:	d00c      	beq.n	803cdde <HAL_TIM_IRQHandler+0x1be>
+  {
+    if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
+ 803cdc4:	68fb      	ldr	r3, [r7, #12]
+ 803cdc6:	f003 0380 	and.w	r3, r3, #128	@ 0x80
+ 803cdca:	2b00      	cmp	r3, #0
+ 803cdcc:	d007      	beq.n	803cdde <HAL_TIM_IRQHandler+0x1be>
+    {
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
+ 803cdce:	687b      	ldr	r3, [r7, #4]
+ 803cdd0:	681b      	ldr	r3, [r3, #0]
+ 803cdd2:	f46f 7280 	mvn.w	r2, #256	@ 0x100
+ 803cdd6:	611a      	str	r2, [r3, #16]
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->Break2Callback(htim);
+#else
+      HAL_TIMEx_Break2Callback(htim);
+ 803cdd8:	6878      	ldr	r0, [r7, #4]
+ 803cdda:	f000 fb2f 	bl	803d43c <HAL_TIMEx_Break2Callback>
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+  /* TIM Trigger detection event */
+  if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
+ 803cdde:	68bb      	ldr	r3, [r7, #8]
+ 803cde0:	f003 0340 	and.w	r3, r3, #64	@ 0x40
+ 803cde4:	2b00      	cmp	r3, #0
+ 803cde6:	d00c      	beq.n	803ce02 <HAL_TIM_IRQHandler+0x1e2>
+  {
+    if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
+ 803cde8:	68fb      	ldr	r3, [r7, #12]
+ 803cdea:	f003 0340 	and.w	r3, r3, #64	@ 0x40
+ 803cdee:	2b00      	cmp	r3, #0
+ 803cdf0:	d007      	beq.n	803ce02 <HAL_TIM_IRQHandler+0x1e2>
+    {
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
+ 803cdf2:	687b      	ldr	r3, [r7, #4]
+ 803cdf4:	681b      	ldr	r3, [r3, #0]
+ 803cdf6:	f06f 0240 	mvn.w	r2, #64	@ 0x40
+ 803cdfa:	611a      	str	r2, [r3, #16]
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->TriggerCallback(htim);
+#else
+      HAL_TIM_TriggerCallback(htim);
+ 803cdfc:	6878      	ldr	r0, [r7, #4]
+ 803cdfe:	f000 f92d 	bl	803d05c <HAL_TIM_TriggerCallback>
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+  /* TIM commutation event */
+  if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM))
+ 803ce02:	68bb      	ldr	r3, [r7, #8]
+ 803ce04:	f003 0320 	and.w	r3, r3, #32
+ 803ce08:	2b00      	cmp	r3, #0
+ 803ce0a:	d00c      	beq.n	803ce26 <HAL_TIM_IRQHandler+0x206>
+  {
+    if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
+ 803ce0c:	68fb      	ldr	r3, [r7, #12]
+ 803ce0e:	f003 0320 	and.w	r3, r3, #32
+ 803ce12:	2b00      	cmp	r3, #0
+ 803ce14:	d007      	beq.n	803ce26 <HAL_TIM_IRQHandler+0x206>
+    {
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
+ 803ce16:	687b      	ldr	r3, [r7, #4]
+ 803ce18:	681b      	ldr	r3, [r3, #0]
+ 803ce1a:	f06f 0220 	mvn.w	r2, #32
+ 803ce1e:	611a      	str	r2, [r3, #16]
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+      htim->CommutationCallback(htim);
+#else
+      HAL_TIMEx_CommutCallback(htim);
+ 803ce20:	6878      	ldr	r0, [r7, #4]
+ 803ce22:	f000 faf7 	bl	803d414 <HAL_TIMEx_CommutCallback>
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+    }
+  }
+}
+ 803ce26:	bf00      	nop
+ 803ce28:	3710      	adds	r7, #16
+ 803ce2a:	46bd      	mov	sp, r7
+ 803ce2c:	bd80      	pop	{r7, pc}
+	...
+
+0803ce30 <HAL_TIM_ConfigClockSource>:
+  * @param  sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
+  *         contains the clock source information for the TIM peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
+{
+ 803ce30:	b580      	push	{r7, lr}
+ 803ce32:	b084      	sub	sp, #16
+ 803ce34:	af00      	add	r7, sp, #0
+ 803ce36:	6078      	str	r0, [r7, #4]
+ 803ce38:	6039      	str	r1, [r7, #0]
+  HAL_StatusTypeDef status = HAL_OK;
+ 803ce3a:	2300      	movs	r3, #0
+ 803ce3c:	73fb      	strb	r3, [r7, #15]
+  uint32_t tmpsmcr;
+
+  /* Process Locked */
+  __HAL_LOCK(htim);
+ 803ce3e:	687b      	ldr	r3, [r7, #4]
+ 803ce40:	f893 303c 	ldrb.w	r3, [r3, #60]	@ 0x3c
+ 803ce44:	2b01      	cmp	r3, #1
+ 803ce46:	d101      	bne.n	803ce4c <HAL_TIM_ConfigClockSource+0x1c>
+ 803ce48:	2302      	movs	r3, #2
+ 803ce4a:	e0dc      	b.n	803d006 <HAL_TIM_ConfigClockSource+0x1d6>
+ 803ce4c:	687b      	ldr	r3, [r7, #4]
+ 803ce4e:	2201      	movs	r2, #1
+ 803ce50:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c
+
+  htim->State = HAL_TIM_STATE_BUSY;
+ 803ce54:	687b      	ldr	r3, [r7, #4]
+ 803ce56:	2202      	movs	r2, #2
+ 803ce58:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d
+
+  /* Check the parameters */
+  assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
+
+  /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
+  tmpsmcr = htim->Instance->SMCR;
+ 803ce5c:	687b      	ldr	r3, [r7, #4]
+ 803ce5e:	681b      	ldr	r3, [r3, #0]
+ 803ce60:	689b      	ldr	r3, [r3, #8]
+ 803ce62:	60bb      	str	r3, [r7, #8]
+  tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
+ 803ce64:	68ba      	ldr	r2, [r7, #8]
+ 803ce66:	4b6a      	ldr	r3, [pc, #424]	@ (803d010 <HAL_TIM_ConfigClockSource+0x1e0>)
+ 803ce68:	4013      	ands	r3, r2
+ 803ce6a:	60bb      	str	r3, [r7, #8]
+  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+ 803ce6c:	68bb      	ldr	r3, [r7, #8]
+ 803ce6e:	f423 437f 	bic.w	r3, r3, #65280	@ 0xff00
+ 803ce72:	60bb      	str	r3, [r7, #8]
+  htim->Instance->SMCR = tmpsmcr;
+ 803ce74:	687b      	ldr	r3, [r7, #4]
+ 803ce76:	681b      	ldr	r3, [r3, #0]
+ 803ce78:	68ba      	ldr	r2, [r7, #8]
+ 803ce7a:	609a      	str	r2, [r3, #8]
+
+  switch (sClockSourceConfig->ClockSource)
+ 803ce7c:	683b      	ldr	r3, [r7, #0]
+ 803ce7e:	681b      	ldr	r3, [r3, #0]
+ 803ce80:	4a64      	ldr	r2, [pc, #400]	@ (803d014 <HAL_TIM_ConfigClockSource+0x1e4>)
+ 803ce82:	4293      	cmp	r3, r2
+ 803ce84:	f000 80a9 	beq.w	803cfda <HAL_TIM_ConfigClockSource+0x1aa>
+ 803ce88:	4a62      	ldr	r2, [pc, #392]	@ (803d014 <HAL_TIM_ConfigClockSource+0x1e4>)
+ 803ce8a:	4293      	cmp	r3, r2
+ 803ce8c:	f200 80ae 	bhi.w	803cfec <HAL_TIM_ConfigClockSource+0x1bc>
+ 803ce90:	4a61      	ldr	r2, [pc, #388]	@ (803d018 <HAL_TIM_ConfigClockSource+0x1e8>)
+ 803ce92:	4293      	cmp	r3, r2
+ 803ce94:	f000 80a1 	beq.w	803cfda <HAL_TIM_ConfigClockSource+0x1aa>
+ 803ce98:	4a5f      	ldr	r2, [pc, #380]	@ (803d018 <HAL_TIM_ConfigClockSource+0x1e8>)
+ 803ce9a:	4293      	cmp	r3, r2
+ 803ce9c:	f200 80a6 	bhi.w	803cfec <HAL_TIM_ConfigClockSource+0x1bc>
+ 803cea0:	4a5e      	ldr	r2, [pc, #376]	@ (803d01c <HAL_TIM_ConfigClockSource+0x1ec>)
+ 803cea2:	4293      	cmp	r3, r2
+ 803cea4:	f000 8099 	beq.w	803cfda <HAL_TIM_ConfigClockSource+0x1aa>
+ 803cea8:	4a5c      	ldr	r2, [pc, #368]	@ (803d01c <HAL_TIM_ConfigClockSource+0x1ec>)
+ 803ceaa:	4293      	cmp	r3, r2
+ 803ceac:	f200 809e 	bhi.w	803cfec <HAL_TIM_ConfigClockSource+0x1bc>
+ 803ceb0:	f1b3 1f10 	cmp.w	r3, #1048592	@ 0x100010
+ 803ceb4:	f000 8091 	beq.w	803cfda <HAL_TIM_ConfigClockSource+0x1aa>
+ 803ceb8:	f1b3 1f10 	cmp.w	r3, #1048592	@ 0x100010
+ 803cebc:	f200 8096 	bhi.w	803cfec <HAL_TIM_ConfigClockSource+0x1bc>
+ 803cec0:	f5b3 1f80 	cmp.w	r3, #1048576	@ 0x100000
+ 803cec4:	f000 8089 	beq.w	803cfda <HAL_TIM_ConfigClockSource+0x1aa>
+ 803cec8:	f5b3 1f80 	cmp.w	r3, #1048576	@ 0x100000
+ 803cecc:	f200 808e 	bhi.w	803cfec <HAL_TIM_ConfigClockSource+0x1bc>
+ 803ced0:	f5b3 5f00 	cmp.w	r3, #8192	@ 0x2000
+ 803ced4:	d03e      	beq.n	803cf54 <HAL_TIM_ConfigClockSource+0x124>
+ 803ced6:	f5b3 5f00 	cmp.w	r3, #8192	@ 0x2000
+ 803ceda:	f200 8087 	bhi.w	803cfec <HAL_TIM_ConfigClockSource+0x1bc>
+ 803cede:	f5b3 5f80 	cmp.w	r3, #4096	@ 0x1000
+ 803cee2:	f000 8086 	beq.w	803cff2 <HAL_TIM_ConfigClockSource+0x1c2>
+ 803cee6:	f5b3 5f80 	cmp.w	r3, #4096	@ 0x1000
+ 803ceea:	d87f      	bhi.n	803cfec <HAL_TIM_ConfigClockSource+0x1bc>
+ 803ceec:	2b70      	cmp	r3, #112	@ 0x70
+ 803ceee:	d01a      	beq.n	803cf26 <HAL_TIM_ConfigClockSource+0xf6>
+ 803cef0:	2b70      	cmp	r3, #112	@ 0x70
+ 803cef2:	d87b      	bhi.n	803cfec <HAL_TIM_ConfigClockSource+0x1bc>
+ 803cef4:	2b60      	cmp	r3, #96	@ 0x60
+ 803cef6:	d050      	beq.n	803cf9a <HAL_TIM_ConfigClockSource+0x16a>
+ 803cef8:	2b60      	cmp	r3, #96	@ 0x60
+ 803cefa:	d877      	bhi.n	803cfec <HAL_TIM_ConfigClockSource+0x1bc>
+ 803cefc:	2b50      	cmp	r3, #80	@ 0x50
+ 803cefe:	d03c      	beq.n	803cf7a <HAL_TIM_ConfigClockSource+0x14a>
+ 803cf00:	2b50      	cmp	r3, #80	@ 0x50
+ 803cf02:	d873      	bhi.n	803cfec <HAL_TIM_ConfigClockSource+0x1bc>
+ 803cf04:	2b40      	cmp	r3, #64	@ 0x40
+ 803cf06:	d058      	beq.n	803cfba <HAL_TIM_ConfigClockSource+0x18a>
+ 803cf08:	2b40      	cmp	r3, #64	@ 0x40
+ 803cf0a:	d86f      	bhi.n	803cfec <HAL_TIM_ConfigClockSource+0x1bc>
+ 803cf0c:	2b30      	cmp	r3, #48	@ 0x30
+ 803cf0e:	d064      	beq.n	803cfda <HAL_TIM_ConfigClockSource+0x1aa>
+ 803cf10:	2b30      	cmp	r3, #48	@ 0x30
+ 803cf12:	d86b      	bhi.n	803cfec <HAL_TIM_ConfigClockSource+0x1bc>
+ 803cf14:	2b20      	cmp	r3, #32
+ 803cf16:	d060      	beq.n	803cfda <HAL_TIM_ConfigClockSource+0x1aa>
+ 803cf18:	2b20      	cmp	r3, #32
+ 803cf1a:	d867      	bhi.n	803cfec <HAL_TIM_ConfigClockSource+0x1bc>
+ 803cf1c:	2b00      	cmp	r3, #0
+ 803cf1e:	d05c      	beq.n	803cfda <HAL_TIM_ConfigClockSource+0x1aa>
+ 803cf20:	2b10      	cmp	r3, #16
+ 803cf22:	d05a      	beq.n	803cfda <HAL_TIM_ConfigClockSource+0x1aa>
+ 803cf24:	e062      	b.n	803cfec <HAL_TIM_ConfigClockSource+0x1bc>
+      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      /* Configure the ETR Clock source */
+      TIM_ETR_SetConfig(htim->Instance,
+ 803cf26:	687b      	ldr	r3, [r7, #4]
+ 803cf28:	6818      	ldr	r0, [r3, #0]
+                        sClockSourceConfig->ClockPrescaler,
+ 803cf2a:	683b      	ldr	r3, [r7, #0]
+ 803cf2c:	6899      	ldr	r1, [r3, #8]
+                        sClockSourceConfig->ClockPolarity,
+ 803cf2e:	683b      	ldr	r3, [r7, #0]
+ 803cf30:	685a      	ldr	r2, [r3, #4]
+                        sClockSourceConfig->ClockFilter);
+ 803cf32:	683b      	ldr	r3, [r7, #0]
+ 803cf34:	68db      	ldr	r3, [r3, #12]
+      TIM_ETR_SetConfig(htim->Instance,
+ 803cf36:	f000 f9bf 	bl	803d2b8 <TIM_ETR_SetConfig>
+
+      /* Select the External clock mode1 and the ETRF trigger */
+      tmpsmcr = htim->Instance->SMCR;
+ 803cf3a:	687b      	ldr	r3, [r7, #4]
+ 803cf3c:	681b      	ldr	r3, [r3, #0]
+ 803cf3e:	689b      	ldr	r3, [r3, #8]
+ 803cf40:	60bb      	str	r3, [r7, #8]
+      tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
+ 803cf42:	68bb      	ldr	r3, [r7, #8]
+ 803cf44:	f043 0377 	orr.w	r3, r3, #119	@ 0x77
+ 803cf48:	60bb      	str	r3, [r7, #8]
+      /* Write to TIMx SMCR */
+      htim->Instance->SMCR = tmpsmcr;
+ 803cf4a:	687b      	ldr	r3, [r7, #4]
+ 803cf4c:	681b      	ldr	r3, [r3, #0]
+ 803cf4e:	68ba      	ldr	r2, [r7, #8]
+ 803cf50:	609a      	str	r2, [r3, #8]
+      break;
+ 803cf52:	e04f      	b.n	803cff4 <HAL_TIM_ConfigClockSource+0x1c4>
+      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      /* Configure the ETR Clock source */
+      TIM_ETR_SetConfig(htim->Instance,
+ 803cf54:	687b      	ldr	r3, [r7, #4]
+ 803cf56:	6818      	ldr	r0, [r3, #0]
+                        sClockSourceConfig->ClockPrescaler,
+ 803cf58:	683b      	ldr	r3, [r7, #0]
+ 803cf5a:	6899      	ldr	r1, [r3, #8]
+                        sClockSourceConfig->ClockPolarity,
+ 803cf5c:	683b      	ldr	r3, [r7, #0]
+ 803cf5e:	685a      	ldr	r2, [r3, #4]
+                        sClockSourceConfig->ClockFilter);
+ 803cf60:	683b      	ldr	r3, [r7, #0]
+ 803cf62:	68db      	ldr	r3, [r3, #12]
+      TIM_ETR_SetConfig(htim->Instance,
+ 803cf64:	f000 f9a8 	bl	803d2b8 <TIM_ETR_SetConfig>
+      /* Enable the External clock mode2 */
+      htim->Instance->SMCR |= TIM_SMCR_ECE;
+ 803cf68:	687b      	ldr	r3, [r7, #4]
+ 803cf6a:	681b      	ldr	r3, [r3, #0]
+ 803cf6c:	689a      	ldr	r2, [r3, #8]
+ 803cf6e:	687b      	ldr	r3, [r7, #4]
+ 803cf70:	681b      	ldr	r3, [r3, #0]
+ 803cf72:	f442 4280 	orr.w	r2, r2, #16384	@ 0x4000
+ 803cf76:	609a      	str	r2, [r3, #8]
+      break;
+ 803cf78:	e03c      	b.n	803cff4 <HAL_TIM_ConfigClockSource+0x1c4>
+
+      /* Check TI1 input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      TIM_TI1_ConfigInputStage(htim->Instance,
+ 803cf7a:	687b      	ldr	r3, [r7, #4]
+ 803cf7c:	6818      	ldr	r0, [r3, #0]
+                               sClockSourceConfig->ClockPolarity,
+ 803cf7e:	683b      	ldr	r3, [r7, #0]
+ 803cf80:	6859      	ldr	r1, [r3, #4]
+                               sClockSourceConfig->ClockFilter);
+ 803cf82:	683b      	ldr	r3, [r7, #0]
+ 803cf84:	68db      	ldr	r3, [r3, #12]
+      TIM_TI1_ConfigInputStage(htim->Instance,
+ 803cf86:	461a      	mov	r2, r3
+ 803cf88:	f000 f918 	bl	803d1bc <TIM_TI1_ConfigInputStage>
+      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
+ 803cf8c:	687b      	ldr	r3, [r7, #4]
+ 803cf8e:	681b      	ldr	r3, [r3, #0]
+ 803cf90:	2150      	movs	r1, #80	@ 0x50
+ 803cf92:	4618      	mov	r0, r3
+ 803cf94:	f000 f972 	bl	803d27c <TIM_ITRx_SetConfig>
+      break;
+ 803cf98:	e02c      	b.n	803cff4 <HAL_TIM_ConfigClockSource+0x1c4>
+
+      /* Check TI2 input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      TIM_TI2_ConfigInputStage(htim->Instance,
+ 803cf9a:	687b      	ldr	r3, [r7, #4]
+ 803cf9c:	6818      	ldr	r0, [r3, #0]
+                               sClockSourceConfig->ClockPolarity,
+ 803cf9e:	683b      	ldr	r3, [r7, #0]
+ 803cfa0:	6859      	ldr	r1, [r3, #4]
+                               sClockSourceConfig->ClockFilter);
+ 803cfa2:	683b      	ldr	r3, [r7, #0]
+ 803cfa4:	68db      	ldr	r3, [r3, #12]
+      TIM_TI2_ConfigInputStage(htim->Instance,
+ 803cfa6:	461a      	mov	r2, r3
+ 803cfa8:	f000 f937 	bl	803d21a <TIM_TI2_ConfigInputStage>
+      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
+ 803cfac:	687b      	ldr	r3, [r7, #4]
+ 803cfae:	681b      	ldr	r3, [r3, #0]
+ 803cfb0:	2160      	movs	r1, #96	@ 0x60
+ 803cfb2:	4618      	mov	r0, r3
+ 803cfb4:	f000 f962 	bl	803d27c <TIM_ITRx_SetConfig>
+      break;
+ 803cfb8:	e01c      	b.n	803cff4 <HAL_TIM_ConfigClockSource+0x1c4>
+
+      /* Check TI1 input conditioning related parameters */
+      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
+      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
+
+      TIM_TI1_ConfigInputStage(htim->Instance,
+ 803cfba:	687b      	ldr	r3, [r7, #4]
+ 803cfbc:	6818      	ldr	r0, [r3, #0]
+                               sClockSourceConfig->ClockPolarity,
+ 803cfbe:	683b      	ldr	r3, [r7, #0]
+ 803cfc0:	6859      	ldr	r1, [r3, #4]
+                               sClockSourceConfig->ClockFilter);
+ 803cfc2:	683b      	ldr	r3, [r7, #0]
+ 803cfc4:	68db      	ldr	r3, [r3, #12]
+      TIM_TI1_ConfigInputStage(htim->Instance,
+ 803cfc6:	461a      	mov	r2, r3
+ 803cfc8:	f000 f8f8 	bl	803d1bc <TIM_TI1_ConfigInputStage>
+      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
+ 803cfcc:	687b      	ldr	r3, [r7, #4]
+ 803cfce:	681b      	ldr	r3, [r3, #0]
+ 803cfd0:	2140      	movs	r1, #64	@ 0x40
+ 803cfd2:	4618      	mov	r0, r3
+ 803cfd4:	f000 f952 	bl	803d27c <TIM_ITRx_SetConfig>
+      break;
+ 803cfd8:	e00c      	b.n	803cff4 <HAL_TIM_ConfigClockSource+0x1c4>
+    case TIM_CLOCKSOURCE_ITR8:
+    {
+      /* Check whether or not the timer instance supports internal trigger input */
+      assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
+
+      TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
+ 803cfda:	687b      	ldr	r3, [r7, #4]
+ 803cfdc:	681a      	ldr	r2, [r3, #0]
+ 803cfde:	683b      	ldr	r3, [r7, #0]
+ 803cfe0:	681b      	ldr	r3, [r3, #0]
+ 803cfe2:	4619      	mov	r1, r3
+ 803cfe4:	4610      	mov	r0, r2
+ 803cfe6:	f000 f949 	bl	803d27c <TIM_ITRx_SetConfig>
+      break;
+ 803cfea:	e003      	b.n	803cff4 <HAL_TIM_ConfigClockSource+0x1c4>
+    }
+
+    default:
+      status = HAL_ERROR;
+ 803cfec:	2301      	movs	r3, #1
+ 803cfee:	73fb      	strb	r3, [r7, #15]
+      break;
+ 803cff0:	e000      	b.n	803cff4 <HAL_TIM_ConfigClockSource+0x1c4>
+      break;
+ 803cff2:	bf00      	nop
+  }
+  htim->State = HAL_TIM_STATE_READY;
+ 803cff4:	687b      	ldr	r3, [r7, #4]
+ 803cff6:	2201      	movs	r2, #1
+ 803cff8:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d
+
+  __HAL_UNLOCK(htim);
+ 803cffc:	687b      	ldr	r3, [r7, #4]
+ 803cffe:	2200      	movs	r2, #0
+ 803d000:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c
+
+  return status;
+ 803d004:	7bfb      	ldrb	r3, [r7, #15]
+}
+ 803d006:	4618      	mov	r0, r3
+ 803d008:	3710      	adds	r7, #16
+ 803d00a:	46bd      	mov	sp, r7
+ 803d00c:	bd80      	pop	{r7, pc}
+ 803d00e:	bf00      	nop
+ 803d010:	ffceff88 	.word	0xffceff88
+ 803d014:	00100040 	.word	0x00100040
+ 803d018:	00100030 	.word	0x00100030
+ 803d01c:	00100020 	.word	0x00100020
+
+0803d020 <HAL_TIM_OC_DelayElapsedCallback>:
+  * @brief  Output Compare callback in non-blocking mode
+  * @param  htim TIM OC handle
+  * @retval None
+  */
+__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
+{
+ 803d020:	b480      	push	{r7}
+ 803d022:	b083      	sub	sp, #12
+ 803d024:	af00      	add	r7, sp, #0
+ 803d026:	6078      	str	r0, [r7, #4]
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
+   */
+}
+ 803d028:	bf00      	nop
+ 803d02a:	370c      	adds	r7, #12
+ 803d02c:	46bd      	mov	sp, r7
+ 803d02e:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 803d032:	4770      	bx	lr
+
+0803d034 <HAL_TIM_IC_CaptureCallback>:
+  * @brief  Input Capture callback in non-blocking mode
+  * @param  htim TIM IC handle
+  * @retval None
+  */
+__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
+{
+ 803d034:	b480      	push	{r7}
+ 803d036:	b083      	sub	sp, #12
+ 803d038:	af00      	add	r7, sp, #0
+ 803d03a:	6078      	str	r0, [r7, #4]
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_IC_CaptureCallback could be implemented in the user file
+   */
+}
+ 803d03c:	bf00      	nop
+ 803d03e:	370c      	adds	r7, #12
+ 803d040:	46bd      	mov	sp, r7
+ 803d042:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 803d046:	4770      	bx	lr
+
+0803d048 <HAL_TIM_PWM_PulseFinishedCallback>:
+  * @brief  PWM Pulse finished callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
+{
+ 803d048:	b480      	push	{r7}
+ 803d04a:	b083      	sub	sp, #12
+ 803d04c:	af00      	add	r7, sp, #0
+ 803d04e:	6078      	str	r0, [r7, #4]
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
+   */
+}
+ 803d050:	bf00      	nop
+ 803d052:	370c      	adds	r7, #12
+ 803d054:	46bd      	mov	sp, r7
+ 803d056:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 803d05a:	4770      	bx	lr
+
+0803d05c <HAL_TIM_TriggerCallback>:
+  * @brief  Hall Trigger detection callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
+{
+ 803d05c:	b480      	push	{r7}
+ 803d05e:	b083      	sub	sp, #12
+ 803d060:	af00      	add	r7, sp, #0
+ 803d062:	6078      	str	r0, [r7, #4]
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIM_TriggerCallback could be implemented in the user file
+   */
+}
+ 803d064:	bf00      	nop
+ 803d066:	370c      	adds	r7, #12
+ 803d068:	46bd      	mov	sp, r7
+ 803d06a:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 803d06e:	4770      	bx	lr
+
+0803d070 <TIM_Base_SetConfig>:
+  * @param  TIMx TIM peripheral
+  * @param  Structure TIM Base configuration structure
+  * @retval None
+  */
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
+{
+ 803d070:	b480      	push	{r7}
+ 803d072:	b085      	sub	sp, #20
+ 803d074:	af00      	add	r7, sp, #0
+ 803d076:	6078      	str	r0, [r7, #4]
+ 803d078:	6039      	str	r1, [r7, #0]
+  uint32_t tmpcr1;
+  tmpcr1 = TIMx->CR1;
+ 803d07a:	687b      	ldr	r3, [r7, #4]
+ 803d07c:	681b      	ldr	r3, [r3, #0]
+ 803d07e:	60fb      	str	r3, [r7, #12]
+
+  /* Set TIM Time Base Unit parameters ---------------------------------------*/
+  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
+ 803d080:	687b      	ldr	r3, [r7, #4]
+ 803d082:	4a46      	ldr	r2, [pc, #280]	@ (803d19c <TIM_Base_SetConfig+0x12c>)
+ 803d084:	4293      	cmp	r3, r2
+ 803d086:	d013      	beq.n	803d0b0 <TIM_Base_SetConfig+0x40>
+ 803d088:	687b      	ldr	r3, [r7, #4]
+ 803d08a:	f1b3 4f80 	cmp.w	r3, #1073741824	@ 0x40000000
+ 803d08e:	d00f      	beq.n	803d0b0 <TIM_Base_SetConfig+0x40>
+ 803d090:	687b      	ldr	r3, [r7, #4]
+ 803d092:	4a43      	ldr	r2, [pc, #268]	@ (803d1a0 <TIM_Base_SetConfig+0x130>)
+ 803d094:	4293      	cmp	r3, r2
+ 803d096:	d00b      	beq.n	803d0b0 <TIM_Base_SetConfig+0x40>
+ 803d098:	687b      	ldr	r3, [r7, #4]
+ 803d09a:	4a42      	ldr	r2, [pc, #264]	@ (803d1a4 <TIM_Base_SetConfig+0x134>)
+ 803d09c:	4293      	cmp	r3, r2
+ 803d09e:	d007      	beq.n	803d0b0 <TIM_Base_SetConfig+0x40>
+ 803d0a0:	687b      	ldr	r3, [r7, #4]
+ 803d0a2:	4a41      	ldr	r2, [pc, #260]	@ (803d1a8 <TIM_Base_SetConfig+0x138>)
+ 803d0a4:	4293      	cmp	r3, r2
+ 803d0a6:	d003      	beq.n	803d0b0 <TIM_Base_SetConfig+0x40>
+ 803d0a8:	687b      	ldr	r3, [r7, #4]
+ 803d0aa:	4a40      	ldr	r2, [pc, #256]	@ (803d1ac <TIM_Base_SetConfig+0x13c>)
+ 803d0ac:	4293      	cmp	r3, r2
+ 803d0ae:	d108      	bne.n	803d0c2 <TIM_Base_SetConfig+0x52>
+  {
+    /* Select the Counter Mode */
+    tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
+ 803d0b0:	68fb      	ldr	r3, [r7, #12]
+ 803d0b2:	f023 0370 	bic.w	r3, r3, #112	@ 0x70
+ 803d0b6:	60fb      	str	r3, [r7, #12]
+    tmpcr1 |= Structure->CounterMode;
+ 803d0b8:	683b      	ldr	r3, [r7, #0]
+ 803d0ba:	685b      	ldr	r3, [r3, #4]
+ 803d0bc:	68fa      	ldr	r2, [r7, #12]
+ 803d0be:	4313      	orrs	r3, r2
+ 803d0c0:	60fb      	str	r3, [r7, #12]
+  }
+
+  if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
+ 803d0c2:	687b      	ldr	r3, [r7, #4]
+ 803d0c4:	4a35      	ldr	r2, [pc, #212]	@ (803d19c <TIM_Base_SetConfig+0x12c>)
+ 803d0c6:	4293      	cmp	r3, r2
+ 803d0c8:	d01f      	beq.n	803d10a <TIM_Base_SetConfig+0x9a>
+ 803d0ca:	687b      	ldr	r3, [r7, #4]
+ 803d0cc:	f1b3 4f80 	cmp.w	r3, #1073741824	@ 0x40000000
+ 803d0d0:	d01b      	beq.n	803d10a <TIM_Base_SetConfig+0x9a>
+ 803d0d2:	687b      	ldr	r3, [r7, #4]
+ 803d0d4:	4a32      	ldr	r2, [pc, #200]	@ (803d1a0 <TIM_Base_SetConfig+0x130>)
+ 803d0d6:	4293      	cmp	r3, r2
+ 803d0d8:	d017      	beq.n	803d10a <TIM_Base_SetConfig+0x9a>
+ 803d0da:	687b      	ldr	r3, [r7, #4]
+ 803d0dc:	4a31      	ldr	r2, [pc, #196]	@ (803d1a4 <TIM_Base_SetConfig+0x134>)
+ 803d0de:	4293      	cmp	r3, r2
+ 803d0e0:	d013      	beq.n	803d10a <TIM_Base_SetConfig+0x9a>
+ 803d0e2:	687b      	ldr	r3, [r7, #4]
+ 803d0e4:	4a30      	ldr	r2, [pc, #192]	@ (803d1a8 <TIM_Base_SetConfig+0x138>)
+ 803d0e6:	4293      	cmp	r3, r2
+ 803d0e8:	d00f      	beq.n	803d10a <TIM_Base_SetConfig+0x9a>
+ 803d0ea:	687b      	ldr	r3, [r7, #4]
+ 803d0ec:	4a2f      	ldr	r2, [pc, #188]	@ (803d1ac <TIM_Base_SetConfig+0x13c>)
+ 803d0ee:	4293      	cmp	r3, r2
+ 803d0f0:	d00b      	beq.n	803d10a <TIM_Base_SetConfig+0x9a>
+ 803d0f2:	687b      	ldr	r3, [r7, #4]
+ 803d0f4:	4a2e      	ldr	r2, [pc, #184]	@ (803d1b0 <TIM_Base_SetConfig+0x140>)
+ 803d0f6:	4293      	cmp	r3, r2
+ 803d0f8:	d007      	beq.n	803d10a <TIM_Base_SetConfig+0x9a>
+ 803d0fa:	687b      	ldr	r3, [r7, #4]
+ 803d0fc:	4a2d      	ldr	r2, [pc, #180]	@ (803d1b4 <TIM_Base_SetConfig+0x144>)
+ 803d0fe:	4293      	cmp	r3, r2
+ 803d100:	d003      	beq.n	803d10a <TIM_Base_SetConfig+0x9a>
+ 803d102:	687b      	ldr	r3, [r7, #4]
+ 803d104:	4a2c      	ldr	r2, [pc, #176]	@ (803d1b8 <TIM_Base_SetConfig+0x148>)
+ 803d106:	4293      	cmp	r3, r2
+ 803d108:	d108      	bne.n	803d11c <TIM_Base_SetConfig+0xac>
+  {
+    /* Set the clock division */
+    tmpcr1 &= ~TIM_CR1_CKD;
+ 803d10a:	68fb      	ldr	r3, [r7, #12]
+ 803d10c:	f423 7340 	bic.w	r3, r3, #768	@ 0x300
+ 803d110:	60fb      	str	r3, [r7, #12]
+    tmpcr1 |= (uint32_t)Structure->ClockDivision;
+ 803d112:	683b      	ldr	r3, [r7, #0]
+ 803d114:	68db      	ldr	r3, [r3, #12]
+ 803d116:	68fa      	ldr	r2, [r7, #12]
+ 803d118:	4313      	orrs	r3, r2
+ 803d11a:	60fb      	str	r3, [r7, #12]
+  }
+
+  /* Set the auto-reload preload */
+  MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
+ 803d11c:	68fb      	ldr	r3, [r7, #12]
+ 803d11e:	f023 0280 	bic.w	r2, r3, #128	@ 0x80
+ 803d122:	683b      	ldr	r3, [r7, #0]
+ 803d124:	695b      	ldr	r3, [r3, #20]
+ 803d126:	4313      	orrs	r3, r2
+ 803d128:	60fb      	str	r3, [r7, #12]
+
+  TIMx->CR1 = tmpcr1;
+ 803d12a:	687b      	ldr	r3, [r7, #4]
+ 803d12c:	68fa      	ldr	r2, [r7, #12]
+ 803d12e:	601a      	str	r2, [r3, #0]
+
+  /* Set the Autoreload value */
+  TIMx->ARR = (uint32_t)Structure->Period ;
+ 803d130:	683b      	ldr	r3, [r7, #0]
+ 803d132:	689a      	ldr	r2, [r3, #8]
+ 803d134:	687b      	ldr	r3, [r7, #4]
+ 803d136:	62da      	str	r2, [r3, #44]	@ 0x2c
+
+  /* Set the Prescaler value */
+  TIMx->PSC = Structure->Prescaler;
+ 803d138:	683b      	ldr	r3, [r7, #0]
+ 803d13a:	681a      	ldr	r2, [r3, #0]
+ 803d13c:	687b      	ldr	r3, [r7, #4]
+ 803d13e:	629a      	str	r2, [r3, #40]	@ 0x28
+
+  if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
+ 803d140:	687b      	ldr	r3, [r7, #4]
+ 803d142:	4a16      	ldr	r2, [pc, #88]	@ (803d19c <TIM_Base_SetConfig+0x12c>)
+ 803d144:	4293      	cmp	r3, r2
+ 803d146:	d00f      	beq.n	803d168 <TIM_Base_SetConfig+0xf8>
+ 803d148:	687b      	ldr	r3, [r7, #4]
+ 803d14a:	4a18      	ldr	r2, [pc, #96]	@ (803d1ac <TIM_Base_SetConfig+0x13c>)
+ 803d14c:	4293      	cmp	r3, r2
+ 803d14e:	d00b      	beq.n	803d168 <TIM_Base_SetConfig+0xf8>
+ 803d150:	687b      	ldr	r3, [r7, #4]
+ 803d152:	4a17      	ldr	r2, [pc, #92]	@ (803d1b0 <TIM_Base_SetConfig+0x140>)
+ 803d154:	4293      	cmp	r3, r2
+ 803d156:	d007      	beq.n	803d168 <TIM_Base_SetConfig+0xf8>
+ 803d158:	687b      	ldr	r3, [r7, #4]
+ 803d15a:	4a16      	ldr	r2, [pc, #88]	@ (803d1b4 <TIM_Base_SetConfig+0x144>)
+ 803d15c:	4293      	cmp	r3, r2
+ 803d15e:	d003      	beq.n	803d168 <TIM_Base_SetConfig+0xf8>
+ 803d160:	687b      	ldr	r3, [r7, #4]
+ 803d162:	4a15      	ldr	r2, [pc, #84]	@ (803d1b8 <TIM_Base_SetConfig+0x148>)
+ 803d164:	4293      	cmp	r3, r2
+ 803d166:	d103      	bne.n	803d170 <TIM_Base_SetConfig+0x100>
+  {
+    /* Set the Repetition Counter value */
+    TIMx->RCR = Structure->RepetitionCounter;
+ 803d168:	683b      	ldr	r3, [r7, #0]
+ 803d16a:	691a      	ldr	r2, [r3, #16]
+ 803d16c:	687b      	ldr	r3, [r7, #4]
+ 803d16e:	631a      	str	r2, [r3, #48]	@ 0x30
+  }
+
+  /* Generate an update event to reload the Prescaler
+     and the repetition counter (only for advanced timer) value immediately */
+  TIMx->EGR = TIM_EGR_UG;
+ 803d170:	687b      	ldr	r3, [r7, #4]
+ 803d172:	2201      	movs	r2, #1
+ 803d174:	615a      	str	r2, [r3, #20]
+
+  /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */
+  if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE))
+ 803d176:	687b      	ldr	r3, [r7, #4]
+ 803d178:	691b      	ldr	r3, [r3, #16]
+ 803d17a:	f003 0301 	and.w	r3, r3, #1
+ 803d17e:	2b01      	cmp	r3, #1
+ 803d180:	d105      	bne.n	803d18e <TIM_Base_SetConfig+0x11e>
+  {
+    /* Clear the update flag */
+    CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE);
+ 803d182:	687b      	ldr	r3, [r7, #4]
+ 803d184:	691b      	ldr	r3, [r3, #16]
+ 803d186:	f023 0201 	bic.w	r2, r3, #1
+ 803d18a:	687b      	ldr	r3, [r7, #4]
+ 803d18c:	611a      	str	r2, [r3, #16]
+  }
+}
+ 803d18e:	bf00      	nop
+ 803d190:	3714      	adds	r7, #20
+ 803d192:	46bd      	mov	sp, r7
+ 803d194:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 803d198:	4770      	bx	lr
+ 803d19a:	bf00      	nop
+ 803d19c:	40010000 	.word	0x40010000
+ 803d1a0:	40000400 	.word	0x40000400
+ 803d1a4:	40000800 	.word	0x40000800
+ 803d1a8:	40000c00 	.word	0x40000c00
+ 803d1ac:	40010400 	.word	0x40010400
+ 803d1b0:	40014000 	.word	0x40014000
+ 803d1b4:	40014400 	.word	0x40014400
+ 803d1b8:	40014800 	.word	0x40014800
+
+0803d1bc <TIM_TI1_ConfigInputStage>:
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
+{
+ 803d1bc:	b480      	push	{r7}
+ 803d1be:	b087      	sub	sp, #28
+ 803d1c0:	af00      	add	r7, sp, #0
+ 803d1c2:	60f8      	str	r0, [r7, #12]
+ 803d1c4:	60b9      	str	r1, [r7, #8]
+ 803d1c6:	607a      	str	r2, [r7, #4]
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 1: Reset the CC1E Bit */
+  tmpccer = TIMx->CCER;
+ 803d1c8:	68fb      	ldr	r3, [r7, #12]
+ 803d1ca:	6a1b      	ldr	r3, [r3, #32]
+ 803d1cc:	617b      	str	r3, [r7, #20]
+  TIMx->CCER &= ~TIM_CCER_CC1E;
+ 803d1ce:	68fb      	ldr	r3, [r7, #12]
+ 803d1d0:	6a1b      	ldr	r3, [r3, #32]
+ 803d1d2:	f023 0201 	bic.w	r2, r3, #1
+ 803d1d6:	68fb      	ldr	r3, [r7, #12]
+ 803d1d8:	621a      	str	r2, [r3, #32]
+  tmpccmr1 = TIMx->CCMR1;
+ 803d1da:	68fb      	ldr	r3, [r7, #12]
+ 803d1dc:	699b      	ldr	r3, [r3, #24]
+ 803d1de:	613b      	str	r3, [r7, #16]
+
+  /* Set the filter */
+  tmpccmr1 &= ~TIM_CCMR1_IC1F;
+ 803d1e0:	693b      	ldr	r3, [r7, #16]
+ 803d1e2:	f023 03f0 	bic.w	r3, r3, #240	@ 0xf0
+ 803d1e6:	613b      	str	r3, [r7, #16]
+  tmpccmr1 |= (TIM_ICFilter << 4U);
+ 803d1e8:	687b      	ldr	r3, [r7, #4]
+ 803d1ea:	011b      	lsls	r3, r3, #4
+ 803d1ec:	693a      	ldr	r2, [r7, #16]
+ 803d1ee:	4313      	orrs	r3, r2
+ 803d1f0:	613b      	str	r3, [r7, #16]
+
+  /* Select the Polarity and set the CC1E Bit */
+  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
+ 803d1f2:	697b      	ldr	r3, [r7, #20]
+ 803d1f4:	f023 030a 	bic.w	r3, r3, #10
+ 803d1f8:	617b      	str	r3, [r7, #20]
+  tmpccer |= TIM_ICPolarity;
+ 803d1fa:	697a      	ldr	r2, [r7, #20]
+ 803d1fc:	68bb      	ldr	r3, [r7, #8]
+ 803d1fe:	4313      	orrs	r3, r2
+ 803d200:	617b      	str	r3, [r7, #20]
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1;
+ 803d202:	68fb      	ldr	r3, [r7, #12]
+ 803d204:	693a      	ldr	r2, [r7, #16]
+ 803d206:	619a      	str	r2, [r3, #24]
+  TIMx->CCER = tmpccer;
+ 803d208:	68fb      	ldr	r3, [r7, #12]
+ 803d20a:	697a      	ldr	r2, [r7, #20]
+ 803d20c:	621a      	str	r2, [r3, #32]
+}
+ 803d20e:	bf00      	nop
+ 803d210:	371c      	adds	r7, #28
+ 803d212:	46bd      	mov	sp, r7
+ 803d214:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 803d218:	4770      	bx	lr
+
+0803d21a <TIM_TI2_ConfigInputStage>:
+  * @param  TIM_ICFilter Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
+{
+ 803d21a:	b480      	push	{r7}
+ 803d21c:	b087      	sub	sp, #28
+ 803d21e:	af00      	add	r7, sp, #0
+ 803d220:	60f8      	str	r0, [r7, #12]
+ 803d222:	60b9      	str	r1, [r7, #8]
+ 803d224:	607a      	str	r2, [r7, #4]
+  uint32_t tmpccmr1;
+  uint32_t tmpccer;
+
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  tmpccer = TIMx->CCER;
+ 803d226:	68fb      	ldr	r3, [r7, #12]
+ 803d228:	6a1b      	ldr	r3, [r3, #32]
+ 803d22a:	617b      	str	r3, [r7, #20]
+  TIMx->CCER &= ~TIM_CCER_CC2E;
+ 803d22c:	68fb      	ldr	r3, [r7, #12]
+ 803d22e:	6a1b      	ldr	r3, [r3, #32]
+ 803d230:	f023 0210 	bic.w	r2, r3, #16
+ 803d234:	68fb      	ldr	r3, [r7, #12]
+ 803d236:	621a      	str	r2, [r3, #32]
+  tmpccmr1 = TIMx->CCMR1;
+ 803d238:	68fb      	ldr	r3, [r7, #12]
+ 803d23a:	699b      	ldr	r3, [r3, #24]
+ 803d23c:	613b      	str	r3, [r7, #16]
+
+  /* Set the filter */
+  tmpccmr1 &= ~TIM_CCMR1_IC2F;
+ 803d23e:	693b      	ldr	r3, [r7, #16]
+ 803d240:	f423 4370 	bic.w	r3, r3, #61440	@ 0xf000
+ 803d244:	613b      	str	r3, [r7, #16]
+  tmpccmr1 |= (TIM_ICFilter << 12U);
+ 803d246:	687b      	ldr	r3, [r7, #4]
+ 803d248:	031b      	lsls	r3, r3, #12
+ 803d24a:	693a      	ldr	r2, [r7, #16]
+ 803d24c:	4313      	orrs	r3, r2
+ 803d24e:	613b      	str	r3, [r7, #16]
+
+  /* Select the Polarity and set the CC2E Bit */
+  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
+ 803d250:	697b      	ldr	r3, [r7, #20]
+ 803d252:	f023 03a0 	bic.w	r3, r3, #160	@ 0xa0
+ 803d256:	617b      	str	r3, [r7, #20]
+  tmpccer |= (TIM_ICPolarity << 4U);
+ 803d258:	68bb      	ldr	r3, [r7, #8]
+ 803d25a:	011b      	lsls	r3, r3, #4
+ 803d25c:	697a      	ldr	r2, [r7, #20]
+ 803d25e:	4313      	orrs	r3, r2
+ 803d260:	617b      	str	r3, [r7, #20]
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1 ;
+ 803d262:	68fb      	ldr	r3, [r7, #12]
+ 803d264:	693a      	ldr	r2, [r7, #16]
+ 803d266:	619a      	str	r2, [r3, #24]
+  TIMx->CCER = tmpccer;
+ 803d268:	68fb      	ldr	r3, [r7, #12]
+ 803d26a:	697a      	ldr	r2, [r7, #20]
+ 803d26c:	621a      	str	r2, [r3, #32]
+}
+ 803d26e:	bf00      	nop
+ 803d270:	371c      	adds	r7, #28
+ 803d272:	46bd      	mov	sp, r7
+ 803d274:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 803d278:	4770      	bx	lr
+	...
+
+0803d27c <TIM_ITRx_SetConfig>:
+  *       (*)  Value not defined in all devices.
+  *
+  * @retval None
+  */
+static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
+{
+ 803d27c:	b480      	push	{r7}
+ 803d27e:	b085      	sub	sp, #20
+ 803d280:	af00      	add	r7, sp, #0
+ 803d282:	6078      	str	r0, [r7, #4]
+ 803d284:	6039      	str	r1, [r7, #0]
+  uint32_t tmpsmcr;
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = TIMx->SMCR;
+ 803d286:	687b      	ldr	r3, [r7, #4]
+ 803d288:	689b      	ldr	r3, [r3, #8]
+ 803d28a:	60fb      	str	r3, [r7, #12]
+  /* Reset the TS Bits */
+  tmpsmcr &= ~TIM_SMCR_TS;
+ 803d28c:	68fa      	ldr	r2, [r7, #12]
+ 803d28e:	4b09      	ldr	r3, [pc, #36]	@ (803d2b4 <TIM_ITRx_SetConfig+0x38>)
+ 803d290:	4013      	ands	r3, r2
+ 803d292:	60fb      	str	r3, [r7, #12]
+  /* Set the Input Trigger source and the slave mode*/
+  tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
+ 803d294:	683a      	ldr	r2, [r7, #0]
+ 803d296:	68fb      	ldr	r3, [r7, #12]
+ 803d298:	4313      	orrs	r3, r2
+ 803d29a:	f043 0307 	orr.w	r3, r3, #7
+ 803d29e:	60fb      	str	r3, [r7, #12]
+  /* Write to TIMx SMCR */
+  TIMx->SMCR = tmpsmcr;
+ 803d2a0:	687b      	ldr	r3, [r7, #4]
+ 803d2a2:	68fa      	ldr	r2, [r7, #12]
+ 803d2a4:	609a      	str	r2, [r3, #8]
+}
+ 803d2a6:	bf00      	nop
+ 803d2a8:	3714      	adds	r7, #20
+ 803d2aa:	46bd      	mov	sp, r7
+ 803d2ac:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 803d2b0:	4770      	bx	lr
+ 803d2b2:	bf00      	nop
+ 803d2b4:	ffcfff8f 	.word	0xffcfff8f
+
+0803d2b8 <TIM_ETR_SetConfig>:
+  *          This parameter must be a value between 0x00 and 0x0F
+  * @retval None
+  */
+void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
+                       uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
+{
+ 803d2b8:	b480      	push	{r7}
+ 803d2ba:	b087      	sub	sp, #28
+ 803d2bc:	af00      	add	r7, sp, #0
+ 803d2be:	60f8      	str	r0, [r7, #12]
+ 803d2c0:	60b9      	str	r1, [r7, #8]
+ 803d2c2:	607a      	str	r2, [r7, #4]
+ 803d2c4:	603b      	str	r3, [r7, #0]
+  uint32_t tmpsmcr;
+
+  tmpsmcr = TIMx->SMCR;
+ 803d2c6:	68fb      	ldr	r3, [r7, #12]
+ 803d2c8:	689b      	ldr	r3, [r3, #8]
+ 803d2ca:	617b      	str	r3, [r7, #20]
+
+  /* Reset the ETR Bits */
+  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+ 803d2cc:	697b      	ldr	r3, [r7, #20]
+ 803d2ce:	f423 437f 	bic.w	r3, r3, #65280	@ 0xff00
+ 803d2d2:	617b      	str	r3, [r7, #20]
+
+  /* Set the Prescaler, the Filter value and the Polarity */
+  tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
+ 803d2d4:	683b      	ldr	r3, [r7, #0]
+ 803d2d6:	021a      	lsls	r2, r3, #8
+ 803d2d8:	687b      	ldr	r3, [r7, #4]
+ 803d2da:	431a      	orrs	r2, r3
+ 803d2dc:	68bb      	ldr	r3, [r7, #8]
+ 803d2de:	4313      	orrs	r3, r2
+ 803d2e0:	697a      	ldr	r2, [r7, #20]
+ 803d2e2:	4313      	orrs	r3, r2
+ 803d2e4:	617b      	str	r3, [r7, #20]
+
+  /* Write to TIMx SMCR */
+  TIMx->SMCR = tmpsmcr;
+ 803d2e6:	68fb      	ldr	r3, [r7, #12]
+ 803d2e8:	697a      	ldr	r2, [r7, #20]
+ 803d2ea:	609a      	str	r2, [r3, #8]
+}
+ 803d2ec:	bf00      	nop
+ 803d2ee:	371c      	adds	r7, #28
+ 803d2f0:	46bd      	mov	sp, r7
+ 803d2f2:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 803d2f6:	4770      	bx	lr
+
+0803d2f8 <HAL_TIMEx_MasterConfigSynchronization>:
+  *         mode.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
+                                                        const TIM_MasterConfigTypeDef *sMasterConfig)
+{
+ 803d2f8:	b480      	push	{r7}
+ 803d2fa:	b085      	sub	sp, #20
+ 803d2fc:	af00      	add	r7, sp, #0
+ 803d2fe:	6078      	str	r0, [r7, #4]
+ 803d300:	6039      	str	r1, [r7, #0]
+  assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
+  assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
+
+  /* Check input state */
+  __HAL_LOCK(htim);
+ 803d302:	687b      	ldr	r3, [r7, #4]
+ 803d304:	f893 303c 	ldrb.w	r3, [r3, #60]	@ 0x3c
+ 803d308:	2b01      	cmp	r3, #1
+ 803d30a:	d101      	bne.n	803d310 <HAL_TIMEx_MasterConfigSynchronization+0x18>
+ 803d30c:	2302      	movs	r3, #2
+ 803d30e:	e06d      	b.n	803d3ec <HAL_TIMEx_MasterConfigSynchronization+0xf4>
+ 803d310:	687b      	ldr	r3, [r7, #4]
+ 803d312:	2201      	movs	r2, #1
+ 803d314:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c
+
+  /* Change the handler state */
+  htim->State = HAL_TIM_STATE_BUSY;
+ 803d318:	687b      	ldr	r3, [r7, #4]
+ 803d31a:	2202      	movs	r2, #2
+ 803d31c:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d
+
+  /* Get the TIMx CR2 register value */
+  tmpcr2 = htim->Instance->CR2;
+ 803d320:	687b      	ldr	r3, [r7, #4]
+ 803d322:	681b      	ldr	r3, [r3, #0]
+ 803d324:	685b      	ldr	r3, [r3, #4]
+ 803d326:	60fb      	str	r3, [r7, #12]
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = htim->Instance->SMCR;
+ 803d328:	687b      	ldr	r3, [r7, #4]
+ 803d32a:	681b      	ldr	r3, [r3, #0]
+ 803d32c:	689b      	ldr	r3, [r3, #8]
+ 803d32e:	60bb      	str	r3, [r7, #8]
+
+  /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
+  if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
+ 803d330:	687b      	ldr	r3, [r7, #4]
+ 803d332:	681b      	ldr	r3, [r3, #0]
+ 803d334:	4a30      	ldr	r2, [pc, #192]	@ (803d3f8 <HAL_TIMEx_MasterConfigSynchronization+0x100>)
+ 803d336:	4293      	cmp	r3, r2
+ 803d338:	d004      	beq.n	803d344 <HAL_TIMEx_MasterConfigSynchronization+0x4c>
+ 803d33a:	687b      	ldr	r3, [r7, #4]
+ 803d33c:	681b      	ldr	r3, [r3, #0]
+ 803d33e:	4a2f      	ldr	r2, [pc, #188]	@ (803d3fc <HAL_TIMEx_MasterConfigSynchronization+0x104>)
+ 803d340:	4293      	cmp	r3, r2
+ 803d342:	d108      	bne.n	803d356 <HAL_TIMEx_MasterConfigSynchronization+0x5e>
+  {
+    /* Check the parameters */
+    assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
+
+    /* Clear the MMS2 bits */
+    tmpcr2 &= ~TIM_CR2_MMS2;
+ 803d344:	68fb      	ldr	r3, [r7, #12]
+ 803d346:	f423 0370 	bic.w	r3, r3, #15728640	@ 0xf00000
+ 803d34a:	60fb      	str	r3, [r7, #12]
+    /* Select the TRGO2 source*/
+    tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
+ 803d34c:	683b      	ldr	r3, [r7, #0]
+ 803d34e:	685b      	ldr	r3, [r3, #4]
+ 803d350:	68fa      	ldr	r2, [r7, #12]
+ 803d352:	4313      	orrs	r3, r2
+ 803d354:	60fb      	str	r3, [r7, #12]
+  }
+
+  /* Reset the MMS Bits */
+  tmpcr2 &= ~TIM_CR2_MMS;
+ 803d356:	68fb      	ldr	r3, [r7, #12]
+ 803d358:	f023 0370 	bic.w	r3, r3, #112	@ 0x70
+ 803d35c:	60fb      	str	r3, [r7, #12]
+  /* Select the TRGO source */
+  tmpcr2 |=  sMasterConfig->MasterOutputTrigger;
+ 803d35e:	683b      	ldr	r3, [r7, #0]
+ 803d360:	681b      	ldr	r3, [r3, #0]
+ 803d362:	68fa      	ldr	r2, [r7, #12]
+ 803d364:	4313      	orrs	r3, r2
+ 803d366:	60fb      	str	r3, [r7, #12]
+
+  /* Update TIMx CR2 */
+  htim->Instance->CR2 = tmpcr2;
+ 803d368:	687b      	ldr	r3, [r7, #4]
+ 803d36a:	681b      	ldr	r3, [r3, #0]
+ 803d36c:	68fa      	ldr	r2, [r7, #12]
+ 803d36e:	605a      	str	r2, [r3, #4]
+
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ 803d370:	687b      	ldr	r3, [r7, #4]
+ 803d372:	681b      	ldr	r3, [r3, #0]
+ 803d374:	4a20      	ldr	r2, [pc, #128]	@ (803d3f8 <HAL_TIMEx_MasterConfigSynchronization+0x100>)
+ 803d376:	4293      	cmp	r3, r2
+ 803d378:	d022      	beq.n	803d3c0 <HAL_TIMEx_MasterConfigSynchronization+0xc8>
+ 803d37a:	687b      	ldr	r3, [r7, #4]
+ 803d37c:	681b      	ldr	r3, [r3, #0]
+ 803d37e:	f1b3 4f80 	cmp.w	r3, #1073741824	@ 0x40000000
+ 803d382:	d01d      	beq.n	803d3c0 <HAL_TIMEx_MasterConfigSynchronization+0xc8>
+ 803d384:	687b      	ldr	r3, [r7, #4]
+ 803d386:	681b      	ldr	r3, [r3, #0]
+ 803d388:	4a1d      	ldr	r2, [pc, #116]	@ (803d400 <HAL_TIMEx_MasterConfigSynchronization+0x108>)
+ 803d38a:	4293      	cmp	r3, r2
+ 803d38c:	d018      	beq.n	803d3c0 <HAL_TIMEx_MasterConfigSynchronization+0xc8>
+ 803d38e:	687b      	ldr	r3, [r7, #4]
+ 803d390:	681b      	ldr	r3, [r3, #0]
+ 803d392:	4a1c      	ldr	r2, [pc, #112]	@ (803d404 <HAL_TIMEx_MasterConfigSynchronization+0x10c>)
+ 803d394:	4293      	cmp	r3, r2
+ 803d396:	d013      	beq.n	803d3c0 <HAL_TIMEx_MasterConfigSynchronization+0xc8>
+ 803d398:	687b      	ldr	r3, [r7, #4]
+ 803d39a:	681b      	ldr	r3, [r3, #0]
+ 803d39c:	4a1a      	ldr	r2, [pc, #104]	@ (803d408 <HAL_TIMEx_MasterConfigSynchronization+0x110>)
+ 803d39e:	4293      	cmp	r3, r2
+ 803d3a0:	d00e      	beq.n	803d3c0 <HAL_TIMEx_MasterConfigSynchronization+0xc8>
+ 803d3a2:	687b      	ldr	r3, [r7, #4]
+ 803d3a4:	681b      	ldr	r3, [r3, #0]
+ 803d3a6:	4a15      	ldr	r2, [pc, #84]	@ (803d3fc <HAL_TIMEx_MasterConfigSynchronization+0x104>)
+ 803d3a8:	4293      	cmp	r3, r2
+ 803d3aa:	d009      	beq.n	803d3c0 <HAL_TIMEx_MasterConfigSynchronization+0xc8>
+ 803d3ac:	687b      	ldr	r3, [r7, #4]
+ 803d3ae:	681b      	ldr	r3, [r3, #0]
+ 803d3b0:	4a16      	ldr	r2, [pc, #88]	@ (803d40c <HAL_TIMEx_MasterConfigSynchronization+0x114>)
+ 803d3b2:	4293      	cmp	r3, r2
+ 803d3b4:	d004      	beq.n	803d3c0 <HAL_TIMEx_MasterConfigSynchronization+0xc8>
+ 803d3b6:	687b      	ldr	r3, [r7, #4]
+ 803d3b8:	681b      	ldr	r3, [r3, #0]
+ 803d3ba:	4a15      	ldr	r2, [pc, #84]	@ (803d410 <HAL_TIMEx_MasterConfigSynchronization+0x118>)
+ 803d3bc:	4293      	cmp	r3, r2
+ 803d3be:	d10c      	bne.n	803d3da <HAL_TIMEx_MasterConfigSynchronization+0xe2>
+  {
+    /* Reset the MSM Bit */
+    tmpsmcr &= ~TIM_SMCR_MSM;
+ 803d3c0:	68bb      	ldr	r3, [r7, #8]
+ 803d3c2:	f023 0380 	bic.w	r3, r3, #128	@ 0x80
+ 803d3c6:	60bb      	str	r3, [r7, #8]
+    /* Set master mode */
+    tmpsmcr |= sMasterConfig->MasterSlaveMode;
+ 803d3c8:	683b      	ldr	r3, [r7, #0]
+ 803d3ca:	689b      	ldr	r3, [r3, #8]
+ 803d3cc:	68ba      	ldr	r2, [r7, #8]
+ 803d3ce:	4313      	orrs	r3, r2
+ 803d3d0:	60bb      	str	r3, [r7, #8]
+
+    /* Update TIMx SMCR */
+    htim->Instance->SMCR = tmpsmcr;
+ 803d3d2:	687b      	ldr	r3, [r7, #4]
+ 803d3d4:	681b      	ldr	r3, [r3, #0]
+ 803d3d6:	68ba      	ldr	r2, [r7, #8]
+ 803d3d8:	609a      	str	r2, [r3, #8]
+  }
+
+  /* Change the htim state */
+  htim->State = HAL_TIM_STATE_READY;
+ 803d3da:	687b      	ldr	r3, [r7, #4]
+ 803d3dc:	2201      	movs	r2, #1
+ 803d3de:	f883 203d 	strb.w	r2, [r3, #61]	@ 0x3d
+
+  __HAL_UNLOCK(htim);
+ 803d3e2:	687b      	ldr	r3, [r7, #4]
+ 803d3e4:	2200      	movs	r2, #0
+ 803d3e6:	f883 203c 	strb.w	r2, [r3, #60]	@ 0x3c
+
+  return HAL_OK;
+ 803d3ea:	2300      	movs	r3, #0
+}
+ 803d3ec:	4618      	mov	r0, r3
+ 803d3ee:	3714      	adds	r7, #20
+ 803d3f0:	46bd      	mov	sp, r7
+ 803d3f2:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 803d3f6:	4770      	bx	lr
+ 803d3f8:	40010000 	.word	0x40010000
+ 803d3fc:	40010400 	.word	0x40010400
+ 803d400:	40000400 	.word	0x40000400
+ 803d404:	40000800 	.word	0x40000800
+ 803d408:	40000c00 	.word	0x40000c00
+ 803d40c:	40001800 	.word	0x40001800
+ 803d410:	40014000 	.word	0x40014000
+
+0803d414 <HAL_TIMEx_CommutCallback>:
+  * @brief  Commutation callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
+{
+ 803d414:	b480      	push	{r7}
+ 803d416:	b083      	sub	sp, #12
+ 803d418:	af00      	add	r7, sp, #0
+ 803d41a:	6078      	str	r0, [r7, #4]
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_CommutCallback could be implemented in the user file
+   */
+}
+ 803d41c:	bf00      	nop
+ 803d41e:	370c      	adds	r7, #12
+ 803d420:	46bd      	mov	sp, r7
+ 803d422:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 803d426:	4770      	bx	lr
+
+0803d428 <HAL_TIMEx_BreakCallback>:
+  * @brief  Break detection callback in non-blocking mode
+  * @param  htim TIM handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
+{
+ 803d428:	b480      	push	{r7}
+ 803d42a:	b083      	sub	sp, #12
+ 803d42c:	af00      	add	r7, sp, #0
+ 803d42e:	6078      	str	r0, [r7, #4]
+  UNUSED(htim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_TIMEx_BreakCallback could be implemented in the user file
+   */
+}
+ 803d430:	bf00      	nop
+ 803d432:	370c      	adds	r7, #12
+ 803d434:	46bd      	mov	sp, r7
+ 803d436:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 803d43a:	4770      	bx	lr
+
+0803d43c <HAL_TIMEx_Break2Callback>:
+  * @brief  Break2 detection callback in non blocking mode
+  * @param  htim: TIM handle
+  * @retval None
+  */
+__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
+{
+ 803d43c:	b480      	push	{r7}
+ 803d43e:	b083      	sub	sp, #12
+ 803d440:	af00      	add	r7, sp, #0
+ 803d442:	6078      	str	r0, [r7, #4]
+  UNUSED(htim);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_TIMEx_Break2Callback could be implemented in the user file
+   */
+}
+ 803d444:	bf00      	nop
+ 803d446:	370c      	adds	r7, #12
+ 803d448:	46bd      	mov	sp, r7
+ 803d44a:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 803d44e:	4770      	bx	lr
+
+0803d450 <HAL_UART_Init>:
+  *        parameters in the UART_InitTypeDef and initialize the associated handle.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
+{
+ 803d450:	b580      	push	{r7, lr}
+ 803d452:	b082      	sub	sp, #8
+ 803d454:	af00      	add	r7, sp, #0
+ 803d456:	6078      	str	r0, [r7, #4]
+  /* Check the UART handle allocation */
+  if (huart == NULL)
+ 803d458:	687b      	ldr	r3, [r7, #4]
+ 803d45a:	2b00      	cmp	r3, #0
+ 803d45c:	d101      	bne.n	803d462 <HAL_UART_Init+0x12>
+  {
+    return HAL_ERROR;
+ 803d45e:	2301      	movs	r3, #1
+ 803d460:	e042      	b.n	803d4e8 <HAL_UART_Init+0x98>
+  {
+    /* Check the parameters */
+    assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
+  }
+
+  if (huart->gState == HAL_UART_STATE_RESET)
+ 803d462:	687b      	ldr	r3, [r7, #4]
+ 803d464:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
+ 803d468:	2b00      	cmp	r3, #0
+ 803d46a:	d106      	bne.n	803d47a <HAL_UART_Init+0x2a>
+  {
+    /* Allocate lock resource and initialize it */
+    huart->Lock = HAL_UNLOCKED;
+ 803d46c:	687b      	ldr	r3, [r7, #4]
+ 803d46e:	2200      	movs	r2, #0
+ 803d470:	f883 2084 	strb.w	r2, [r3, #132]	@ 0x84
+
+    /* Init the low level hardware */
+    huart->MspInitCallback(huart);
+#else
+    /* Init the low level hardware : GPIO, CLOCK */
+    HAL_UART_MspInit(huart);
+ 803d474:	6878      	ldr	r0, [r7, #4]
+ 803d476:	f7f3 fc11 	bl	8030c9c <HAL_UART_MspInit>
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+  }
+
+  huart->gState = HAL_UART_STATE_BUSY;
+ 803d47a:	687b      	ldr	r3, [r7, #4]
+ 803d47c:	2224      	movs	r2, #36	@ 0x24
+ 803d47e:	f8c3 2088 	str.w	r2, [r3, #136]	@ 0x88
+
+  __HAL_UART_DISABLE(huart);
+ 803d482:	687b      	ldr	r3, [r7, #4]
+ 803d484:	681b      	ldr	r3, [r3, #0]
+ 803d486:	681a      	ldr	r2, [r3, #0]
+ 803d488:	687b      	ldr	r3, [r7, #4]
+ 803d48a:	681b      	ldr	r3, [r3, #0]
+ 803d48c:	f022 0201 	bic.w	r2, r2, #1
+ 803d490:	601a      	str	r2, [r3, #0]
+
+  /* Perform advanced settings configuration */
+  /* For some items, configuration requires to be done prior TE and RE bits are set */
+  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+ 803d492:	687b      	ldr	r3, [r7, #4]
+ 803d494:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 803d496:	2b00      	cmp	r3, #0
+ 803d498:	d002      	beq.n	803d4a0 <HAL_UART_Init+0x50>
+  {
+    UART_AdvFeatureConfig(huart);
+ 803d49a:	6878      	ldr	r0, [r7, #4]
+ 803d49c:	f001 fac4 	bl	803ea28 <UART_AdvFeatureConfig>
+  }
+
+  /* Set the UART Communication parameters */
+  if (UART_SetConfig(huart) == HAL_ERROR)
+ 803d4a0:	6878      	ldr	r0, [r7, #4]
+ 803d4a2:	f000 fd59 	bl	803df58 <UART_SetConfig>
+ 803d4a6:	4603      	mov	r3, r0
+ 803d4a8:	2b01      	cmp	r3, #1
+ 803d4aa:	d101      	bne.n	803d4b0 <HAL_UART_Init+0x60>
+  {
+    return HAL_ERROR;
+ 803d4ac:	2301      	movs	r3, #1
+ 803d4ae:	e01b      	b.n	803d4e8 <HAL_UART_Init+0x98>
+  }
+
+  /* In asynchronous mode, the following bits must be kept cleared:
+  - LINEN and CLKEN bits in the USART_CR2 register,
+  - SCEN, HDSEL and IREN  bits in the USART_CR3 register.*/
+  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ 803d4b0:	687b      	ldr	r3, [r7, #4]
+ 803d4b2:	681b      	ldr	r3, [r3, #0]
+ 803d4b4:	685a      	ldr	r2, [r3, #4]
+ 803d4b6:	687b      	ldr	r3, [r7, #4]
+ 803d4b8:	681b      	ldr	r3, [r3, #0]
+ 803d4ba:	f422 4290 	bic.w	r2, r2, #18432	@ 0x4800
+ 803d4be:	605a      	str	r2, [r3, #4]
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+ 803d4c0:	687b      	ldr	r3, [r7, #4]
+ 803d4c2:	681b      	ldr	r3, [r3, #0]
+ 803d4c4:	689a      	ldr	r2, [r3, #8]
+ 803d4c6:	687b      	ldr	r3, [r7, #4]
+ 803d4c8:	681b      	ldr	r3, [r3, #0]
+ 803d4ca:	f022 022a 	bic.w	r2, r2, #42	@ 0x2a
+ 803d4ce:	609a      	str	r2, [r3, #8]
+
+  __HAL_UART_ENABLE(huart);
+ 803d4d0:	687b      	ldr	r3, [r7, #4]
+ 803d4d2:	681b      	ldr	r3, [r3, #0]
+ 803d4d4:	681a      	ldr	r2, [r3, #0]
+ 803d4d6:	687b      	ldr	r3, [r7, #4]
+ 803d4d8:	681b      	ldr	r3, [r3, #0]
+ 803d4da:	f042 0201 	orr.w	r2, r2, #1
+ 803d4de:	601a      	str	r2, [r3, #0]
+
+  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+  return (UART_CheckIdleState(huart));
+ 803d4e0:	6878      	ldr	r0, [r7, #4]
+ 803d4e2:	f001 fb43 	bl	803eb6c <UART_CheckIdleState>
+ 803d4e6:	4603      	mov	r3, r0
+}
+ 803d4e8:	4618      	mov	r0, r3
+ 803d4ea:	3708      	adds	r7, #8
+ 803d4ec:	46bd      	mov	sp, r7
+ 803d4ee:	bd80      	pop	{r7, pc}
+
+0803d4f0 <HAL_UART_Transmit>:
+  * @param Size    Amount of data elements (u8 or u16) to be sent.
+  * @param Timeout Timeout duration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+ 803d4f0:	b580      	push	{r7, lr}
+ 803d4f2:	b08a      	sub	sp, #40	@ 0x28
+ 803d4f4:	af02      	add	r7, sp, #8
+ 803d4f6:	60f8      	str	r0, [r7, #12]
+ 803d4f8:	60b9      	str	r1, [r7, #8]
+ 803d4fa:	603b      	str	r3, [r7, #0]
+ 803d4fc:	4613      	mov	r3, r2
+ 803d4fe:	80fb      	strh	r3, [r7, #6]
+  const uint8_t  *pdata8bits;
+  const uint16_t *pdata16bits;
+  uint32_t tickstart;
+
+  /* Check that a Tx process is not already ongoing */
+  if (huart->gState == HAL_UART_STATE_READY)
+ 803d500:	68fb      	ldr	r3, [r7, #12]
+ 803d502:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
+ 803d506:	2b20      	cmp	r3, #32
+ 803d508:	d17b      	bne.n	803d602 <HAL_UART_Transmit+0x112>
+  {
+    if ((pData == NULL) || (Size == 0U))
+ 803d50a:	68bb      	ldr	r3, [r7, #8]
+ 803d50c:	2b00      	cmp	r3, #0
+ 803d50e:	d002      	beq.n	803d516 <HAL_UART_Transmit+0x26>
+ 803d510:	88fb      	ldrh	r3, [r7, #6]
+ 803d512:	2b00      	cmp	r3, #0
+ 803d514:	d101      	bne.n	803d51a <HAL_UART_Transmit+0x2a>
+    {
+      return  HAL_ERROR;
+ 803d516:	2301      	movs	r3, #1
+ 803d518:	e074      	b.n	803d604 <HAL_UART_Transmit+0x114>
+    }
+
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+ 803d51a:	68fb      	ldr	r3, [r7, #12]
+ 803d51c:	2200      	movs	r2, #0
+ 803d51e:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90
+    huart->gState = HAL_UART_STATE_BUSY_TX;
+ 803d522:	68fb      	ldr	r3, [r7, #12]
+ 803d524:	2221      	movs	r2, #33	@ 0x21
+ 803d526:	f8c3 2088 	str.w	r2, [r3, #136]	@ 0x88
+
+    /* Init tickstart for timeout management */
+    tickstart = HAL_GetTick();
+ 803d52a:	f7f4 fa01 	bl	8031930 <HAL_GetTick>
+ 803d52e:	6178      	str	r0, [r7, #20]
+
+    huart->TxXferSize  = Size;
+ 803d530:	68fb      	ldr	r3, [r7, #12]
+ 803d532:	88fa      	ldrh	r2, [r7, #6]
+ 803d534:	f8a3 2054 	strh.w	r2, [r3, #84]	@ 0x54
+    huart->TxXferCount = Size;
+ 803d538:	68fb      	ldr	r3, [r7, #12]
+ 803d53a:	88fa      	ldrh	r2, [r7, #6]
+ 803d53c:	f8a3 2056 	strh.w	r2, [r3, #86]	@ 0x56
+
+    /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
+    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ 803d540:	68fb      	ldr	r3, [r7, #12]
+ 803d542:	689b      	ldr	r3, [r3, #8]
+ 803d544:	f5b3 5f80 	cmp.w	r3, #4096	@ 0x1000
+ 803d548:	d108      	bne.n	803d55c <HAL_UART_Transmit+0x6c>
+ 803d54a:	68fb      	ldr	r3, [r7, #12]
+ 803d54c:	691b      	ldr	r3, [r3, #16]
+ 803d54e:	2b00      	cmp	r3, #0
+ 803d550:	d104      	bne.n	803d55c <HAL_UART_Transmit+0x6c>
+    {
+      pdata8bits  = NULL;
+ 803d552:	2300      	movs	r3, #0
+ 803d554:	61fb      	str	r3, [r7, #28]
+      pdata16bits = (const uint16_t *) pData;
+ 803d556:	68bb      	ldr	r3, [r7, #8]
+ 803d558:	61bb      	str	r3, [r7, #24]
+ 803d55a:	e003      	b.n	803d564 <HAL_UART_Transmit+0x74>
+    }
+    else
+    {
+      pdata8bits  = pData;
+ 803d55c:	68bb      	ldr	r3, [r7, #8]
+ 803d55e:	61fb      	str	r3, [r7, #28]
+      pdata16bits = NULL;
+ 803d560:	2300      	movs	r3, #0
+ 803d562:	61bb      	str	r3, [r7, #24]
+    }
+
+    while (huart->TxXferCount > 0U)
+ 803d564:	e030      	b.n	803d5c8 <HAL_UART_Transmit+0xd8>
+    {
+      if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ 803d566:	683b      	ldr	r3, [r7, #0]
+ 803d568:	9300      	str	r3, [sp, #0]
+ 803d56a:	697b      	ldr	r3, [r7, #20]
+ 803d56c:	2200      	movs	r2, #0
+ 803d56e:	2180      	movs	r1, #128	@ 0x80
+ 803d570:	68f8      	ldr	r0, [r7, #12]
+ 803d572:	f001 fba5 	bl	803ecc0 <UART_WaitOnFlagUntilTimeout>
+ 803d576:	4603      	mov	r3, r0
+ 803d578:	2b00      	cmp	r3, #0
+ 803d57a:	d005      	beq.n	803d588 <HAL_UART_Transmit+0x98>
+      {
+
+        huart->gState = HAL_UART_STATE_READY;
+ 803d57c:	68fb      	ldr	r3, [r7, #12]
+ 803d57e:	2220      	movs	r2, #32
+ 803d580:	f8c3 2088 	str.w	r2, [r3, #136]	@ 0x88
+
+        return HAL_TIMEOUT;
+ 803d584:	2303      	movs	r3, #3
+ 803d586:	e03d      	b.n	803d604 <HAL_UART_Transmit+0x114>
+      }
+      if (pdata8bits == NULL)
+ 803d588:	69fb      	ldr	r3, [r7, #28]
+ 803d58a:	2b00      	cmp	r3, #0
+ 803d58c:	d10b      	bne.n	803d5a6 <HAL_UART_Transmit+0xb6>
+      {
+        huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
+ 803d58e:	69bb      	ldr	r3, [r7, #24]
+ 803d590:	881b      	ldrh	r3, [r3, #0]
+ 803d592:	461a      	mov	r2, r3
+ 803d594:	68fb      	ldr	r3, [r7, #12]
+ 803d596:	681b      	ldr	r3, [r3, #0]
+ 803d598:	f3c2 0208 	ubfx	r2, r2, #0, #9
+ 803d59c:	629a      	str	r2, [r3, #40]	@ 0x28
+        pdata16bits++;
+ 803d59e:	69bb      	ldr	r3, [r7, #24]
+ 803d5a0:	3302      	adds	r3, #2
+ 803d5a2:	61bb      	str	r3, [r7, #24]
+ 803d5a4:	e007      	b.n	803d5b6 <HAL_UART_Transmit+0xc6>
+      }
+      else
+      {
+        huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
+ 803d5a6:	69fb      	ldr	r3, [r7, #28]
+ 803d5a8:	781a      	ldrb	r2, [r3, #0]
+ 803d5aa:	68fb      	ldr	r3, [r7, #12]
+ 803d5ac:	681b      	ldr	r3, [r3, #0]
+ 803d5ae:	629a      	str	r2, [r3, #40]	@ 0x28
+        pdata8bits++;
+ 803d5b0:	69fb      	ldr	r3, [r7, #28]
+ 803d5b2:	3301      	adds	r3, #1
+ 803d5b4:	61fb      	str	r3, [r7, #28]
+      }
+      huart->TxXferCount--;
+ 803d5b6:	68fb      	ldr	r3, [r7, #12]
+ 803d5b8:	f8b3 3056 	ldrh.w	r3, [r3, #86]	@ 0x56
+ 803d5bc:	b29b      	uxth	r3, r3
+ 803d5be:	3b01      	subs	r3, #1
+ 803d5c0:	b29a      	uxth	r2, r3
+ 803d5c2:	68fb      	ldr	r3, [r7, #12]
+ 803d5c4:	f8a3 2056 	strh.w	r2, [r3, #86]	@ 0x56
+    while (huart->TxXferCount > 0U)
+ 803d5c8:	68fb      	ldr	r3, [r7, #12]
+ 803d5ca:	f8b3 3056 	ldrh.w	r3, [r3, #86]	@ 0x56
+ 803d5ce:	b29b      	uxth	r3, r3
+ 803d5d0:	2b00      	cmp	r3, #0
+ 803d5d2:	d1c8      	bne.n	803d566 <HAL_UART_Transmit+0x76>
+    }
+
+    if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+ 803d5d4:	683b      	ldr	r3, [r7, #0]
+ 803d5d6:	9300      	str	r3, [sp, #0]
+ 803d5d8:	697b      	ldr	r3, [r7, #20]
+ 803d5da:	2200      	movs	r2, #0
+ 803d5dc:	2140      	movs	r1, #64	@ 0x40
+ 803d5de:	68f8      	ldr	r0, [r7, #12]
+ 803d5e0:	f001 fb6e 	bl	803ecc0 <UART_WaitOnFlagUntilTimeout>
+ 803d5e4:	4603      	mov	r3, r0
+ 803d5e6:	2b00      	cmp	r3, #0
+ 803d5e8:	d005      	beq.n	803d5f6 <HAL_UART_Transmit+0x106>
+    {
+      huart->gState = HAL_UART_STATE_READY;
+ 803d5ea:	68fb      	ldr	r3, [r7, #12]
+ 803d5ec:	2220      	movs	r2, #32
+ 803d5ee:	f8c3 2088 	str.w	r2, [r3, #136]	@ 0x88
+
+      return HAL_TIMEOUT;
+ 803d5f2:	2303      	movs	r3, #3
+ 803d5f4:	e006      	b.n	803d604 <HAL_UART_Transmit+0x114>
+    }
+
+    /* At end of Tx process, restore huart->gState to Ready */
+    huart->gState = HAL_UART_STATE_READY;
+ 803d5f6:	68fb      	ldr	r3, [r7, #12]
+ 803d5f8:	2220      	movs	r2, #32
+ 803d5fa:	f8c3 2088 	str.w	r2, [r3, #136]	@ 0x88
+
+    return HAL_OK;
+ 803d5fe:	2300      	movs	r3, #0
+ 803d600:	e000      	b.n	803d604 <HAL_UART_Transmit+0x114>
+  }
+  else
+  {
+    return HAL_BUSY;
+ 803d602:	2302      	movs	r3, #2
+  }
+}
+ 803d604:	4618      	mov	r0, r3
+ 803d606:	3720      	adds	r7, #32
+ 803d608:	46bd      	mov	sp, r7
+ 803d60a:	bd80      	pop	{r7, pc}
+
+0803d60c <HAL_UART_Receive_IT>:
+  * @param pData Pointer to data buffer (u8 or u16 data elements).
+  * @param Size  Amount of data elements (u8 or u16) to be received.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+ 803d60c:	b580      	push	{r7, lr}
+ 803d60e:	b08a      	sub	sp, #40	@ 0x28
+ 803d610:	af00      	add	r7, sp, #0
+ 803d612:	60f8      	str	r0, [r7, #12]
+ 803d614:	60b9      	str	r1, [r7, #8]
+ 803d616:	4613      	mov	r3, r2
+ 803d618:	80fb      	strh	r3, [r7, #6]
+  /* Check that a Rx process is not already ongoing */
+  if (huart->RxState == HAL_UART_STATE_READY)
+ 803d61a:	68fb      	ldr	r3, [r7, #12]
+ 803d61c:	f8d3 308c 	ldr.w	r3, [r3, #140]	@ 0x8c
+ 803d620:	2b20      	cmp	r3, #32
+ 803d622:	d137      	bne.n	803d694 <HAL_UART_Receive_IT+0x88>
+  {
+    if ((pData == NULL) || (Size == 0U))
+ 803d624:	68bb      	ldr	r3, [r7, #8]
+ 803d626:	2b00      	cmp	r3, #0
+ 803d628:	d002      	beq.n	803d630 <HAL_UART_Receive_IT+0x24>
+ 803d62a:	88fb      	ldrh	r3, [r7, #6]
+ 803d62c:	2b00      	cmp	r3, #0
+ 803d62e:	d101      	bne.n	803d634 <HAL_UART_Receive_IT+0x28>
+    {
+      return HAL_ERROR;
+ 803d630:	2301      	movs	r3, #1
+ 803d632:	e030      	b.n	803d696 <HAL_UART_Receive_IT+0x8a>
+    }
+
+    /* Set Reception type to Standard reception */
+    huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ 803d634:	68fb      	ldr	r3, [r7, #12]
+ 803d636:	2200      	movs	r2, #0
+ 803d638:	66da      	str	r2, [r3, #108]	@ 0x6c
+
+    if (!(IS_LPUART_INSTANCE(huart->Instance)))
+ 803d63a:	68fb      	ldr	r3, [r7, #12]
+ 803d63c:	681b      	ldr	r3, [r3, #0]
+ 803d63e:	4a18      	ldr	r2, [pc, #96]	@ (803d6a0 <HAL_UART_Receive_IT+0x94>)
+ 803d640:	4293      	cmp	r3, r2
+ 803d642:	d01f      	beq.n	803d684 <HAL_UART_Receive_IT+0x78>
+    {
+      /* Check that USART RTOEN bit is set */
+      if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+ 803d644:	68fb      	ldr	r3, [r7, #12]
+ 803d646:	681b      	ldr	r3, [r3, #0]
+ 803d648:	685b      	ldr	r3, [r3, #4]
+ 803d64a:	f403 0300 	and.w	r3, r3, #8388608	@ 0x800000
+ 803d64e:	2b00      	cmp	r3, #0
+ 803d650:	d018      	beq.n	803d684 <HAL_UART_Receive_IT+0x78>
+      {
+        /* Enable the UART Receiver Timeout Interrupt */
+        ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+ 803d652:	68fb      	ldr	r3, [r7, #12]
+ 803d654:	681b      	ldr	r3, [r3, #0]
+ 803d656:	617b      	str	r3, [r7, #20]
+ */
+__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ 803d658:	697b      	ldr	r3, [r7, #20]
+ 803d65a:	e853 3f00 	ldrex	r3, [r3]
+ 803d65e:	613b      	str	r3, [r7, #16]
+   return(result);
+ 803d660:	693b      	ldr	r3, [r7, #16]
+ 803d662:	f043 6380 	orr.w	r3, r3, #67108864	@ 0x4000000
+ 803d666:	627b      	str	r3, [r7, #36]	@ 0x24
+ 803d668:	68fb      	ldr	r3, [r7, #12]
+ 803d66a:	681b      	ldr	r3, [r3, #0]
+ 803d66c:	461a      	mov	r2, r3
+ 803d66e:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 803d670:	623b      	str	r3, [r7, #32]
+ 803d672:	61fa      	str	r2, [r7, #28]
+ */
+__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ 803d674:	69f9      	ldr	r1, [r7, #28]
+ 803d676:	6a3a      	ldr	r2, [r7, #32]
+ 803d678:	e841 2300 	strex	r3, r2, [r1]
+ 803d67c:	61bb      	str	r3, [r7, #24]
+   return(result);
+ 803d67e:	69bb      	ldr	r3, [r7, #24]
+ 803d680:	2b00      	cmp	r3, #0
+ 803d682:	d1e6      	bne.n	803d652 <HAL_UART_Receive_IT+0x46>
+      }
+    }
+
+    return (UART_Start_Receive_IT(huart, pData, Size));
+ 803d684:	88fb      	ldrh	r3, [r7, #6]
+ 803d686:	461a      	mov	r2, r3
+ 803d688:	68b9      	ldr	r1, [r7, #8]
+ 803d68a:	68f8      	ldr	r0, [r7, #12]
+ 803d68c:	f001 fb86 	bl	803ed9c <UART_Start_Receive_IT>
+ 803d690:	4603      	mov	r3, r0
+ 803d692:	e000      	b.n	803d696 <HAL_UART_Receive_IT+0x8a>
+  }
+  else
+  {
+    return HAL_BUSY;
+ 803d694:	2302      	movs	r3, #2
+  }
+}
+ 803d696:	4618      	mov	r0, r3
+ 803d698:	3728      	adds	r7, #40	@ 0x28
+ 803d69a:	46bd      	mov	sp, r7
+ 803d69c:	bd80      	pop	{r7, pc}
+ 803d69e:	bf00      	nop
+ 803d6a0:	58000c00 	.word	0x58000c00
+
+0803d6a4 <HAL_UART_Transmit_DMA>:
+  * @param pData Pointer to data buffer (u8 or u16 data elements).
+  * @param Size  Amount of data elements (u8 or u16) to be sent.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size)
+{
+ 803d6a4:	b580      	push	{r7, lr}
+ 803d6a6:	b08a      	sub	sp, #40	@ 0x28
+ 803d6a8:	af00      	add	r7, sp, #0
+ 803d6aa:	60f8      	str	r0, [r7, #12]
+ 803d6ac:	60b9      	str	r1, [r7, #8]
+ 803d6ae:	4613      	mov	r3, r2
+ 803d6b0:	80fb      	strh	r3, [r7, #6]
+  /* Check that a Tx process is not already ongoing */
+  if (huart->gState == HAL_UART_STATE_READY)
+ 803d6b2:	68fb      	ldr	r3, [r7, #12]
+ 803d6b4:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
+ 803d6b8:	2b20      	cmp	r3, #32
+ 803d6ba:	d167      	bne.n	803d78c <HAL_UART_Transmit_DMA+0xe8>
+  {
+    if ((pData == NULL) || (Size == 0U))
+ 803d6bc:	68bb      	ldr	r3, [r7, #8]
+ 803d6be:	2b00      	cmp	r3, #0
+ 803d6c0:	d002      	beq.n	803d6c8 <HAL_UART_Transmit_DMA+0x24>
+ 803d6c2:	88fb      	ldrh	r3, [r7, #6]
+ 803d6c4:	2b00      	cmp	r3, #0
+ 803d6c6:	d101      	bne.n	803d6cc <HAL_UART_Transmit_DMA+0x28>
+    {
+      return HAL_ERROR;
+ 803d6c8:	2301      	movs	r3, #1
+ 803d6ca:	e060      	b.n	803d78e <HAL_UART_Transmit_DMA+0xea>
+    }
+
+    huart->pTxBuffPtr  = pData;
+ 803d6cc:	68fb      	ldr	r3, [r7, #12]
+ 803d6ce:	68ba      	ldr	r2, [r7, #8]
+ 803d6d0:	651a      	str	r2, [r3, #80]	@ 0x50
+    huart->TxXferSize  = Size;
+ 803d6d2:	68fb      	ldr	r3, [r7, #12]
+ 803d6d4:	88fa      	ldrh	r2, [r7, #6]
+ 803d6d6:	f8a3 2054 	strh.w	r2, [r3, #84]	@ 0x54
+    huart->TxXferCount = Size;
+ 803d6da:	68fb      	ldr	r3, [r7, #12]
+ 803d6dc:	88fa      	ldrh	r2, [r7, #6]
+ 803d6de:	f8a3 2056 	strh.w	r2, [r3, #86]	@ 0x56
+
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+ 803d6e2:	68fb      	ldr	r3, [r7, #12]
+ 803d6e4:	2200      	movs	r2, #0
+ 803d6e6:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90
+    huart->gState = HAL_UART_STATE_BUSY_TX;
+ 803d6ea:	68fb      	ldr	r3, [r7, #12]
+ 803d6ec:	2221      	movs	r2, #33	@ 0x21
+ 803d6ee:	f8c3 2088 	str.w	r2, [r3, #136]	@ 0x88
+
+    if (huart->hdmatx != NULL)
+ 803d6f2:	68fb      	ldr	r3, [r7, #12]
+ 803d6f4:	6fdb      	ldr	r3, [r3, #124]	@ 0x7c
+ 803d6f6:	2b00      	cmp	r3, #0
+ 803d6f8:	d028      	beq.n	803d74c <HAL_UART_Transmit_DMA+0xa8>
+    {
+      /* Set the UART DMA transfer complete callback */
+      huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
+ 803d6fa:	68fb      	ldr	r3, [r7, #12]
+ 803d6fc:	6fdb      	ldr	r3, [r3, #124]	@ 0x7c
+ 803d6fe:	4a26      	ldr	r2, [pc, #152]	@ (803d798 <HAL_UART_Transmit_DMA+0xf4>)
+ 803d700:	63da      	str	r2, [r3, #60]	@ 0x3c
+
+      /* Set the UART DMA Half transfer complete callback */
+      huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
+ 803d702:	68fb      	ldr	r3, [r7, #12]
+ 803d704:	6fdb      	ldr	r3, [r3, #124]	@ 0x7c
+ 803d706:	4a25      	ldr	r2, [pc, #148]	@ (803d79c <HAL_UART_Transmit_DMA+0xf8>)
+ 803d708:	641a      	str	r2, [r3, #64]	@ 0x40
+
+      /* Set the DMA error callback */
+      huart->hdmatx->XferErrorCallback = UART_DMAError;
+ 803d70a:	68fb      	ldr	r3, [r7, #12]
+ 803d70c:	6fdb      	ldr	r3, [r3, #124]	@ 0x7c
+ 803d70e:	4a24      	ldr	r2, [pc, #144]	@ (803d7a0 <HAL_UART_Transmit_DMA+0xfc>)
+ 803d710:	64da      	str	r2, [r3, #76]	@ 0x4c
+
+      /* Set the DMA abort callback */
+      huart->hdmatx->XferAbortCallback = NULL;
+ 803d712:	68fb      	ldr	r3, [r7, #12]
+ 803d714:	6fdb      	ldr	r3, [r3, #124]	@ 0x7c
+ 803d716:	2200      	movs	r2, #0
+ 803d718:	651a      	str	r2, [r3, #80]	@ 0x50
+
+      /* Enable the UART transmit DMA channel */
+      if (HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, Size) != HAL_OK)
+ 803d71a:	68fb      	ldr	r3, [r7, #12]
+ 803d71c:	6fd8      	ldr	r0, [r3, #124]	@ 0x7c
+ 803d71e:	68fb      	ldr	r3, [r7, #12]
+ 803d720:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
+ 803d722:	4619      	mov	r1, r3
+ 803d724:	68fb      	ldr	r3, [r7, #12]
+ 803d726:	681b      	ldr	r3, [r3, #0]
+ 803d728:	3328      	adds	r3, #40	@ 0x28
+ 803d72a:	461a      	mov	r2, r3
+ 803d72c:	88fb      	ldrh	r3, [r7, #6]
+ 803d72e:	f7f5 fdc9 	bl	80332c4 <HAL_DMA_Start_IT>
+ 803d732:	4603      	mov	r3, r0
+ 803d734:	2b00      	cmp	r3, #0
+ 803d736:	d009      	beq.n	803d74c <HAL_UART_Transmit_DMA+0xa8>
+      {
+        /* Set error code to DMA */
+        huart->ErrorCode = HAL_UART_ERROR_DMA;
+ 803d738:	68fb      	ldr	r3, [r7, #12]
+ 803d73a:	2210      	movs	r2, #16
+ 803d73c:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90
+
+        /* Restore huart->gState to ready */
+        huart->gState = HAL_UART_STATE_READY;
+ 803d740:	68fb      	ldr	r3, [r7, #12]
+ 803d742:	2220      	movs	r2, #32
+ 803d744:	f8c3 2088 	str.w	r2, [r3, #136]	@ 0x88
+
+        return HAL_ERROR;
+ 803d748:	2301      	movs	r3, #1
+ 803d74a:	e020      	b.n	803d78e <HAL_UART_Transmit_DMA+0xea>
+      }
+    }
+    /* Clear the TC flag in the ICR register */
+    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
+ 803d74c:	68fb      	ldr	r3, [r7, #12]
+ 803d74e:	681b      	ldr	r3, [r3, #0]
+ 803d750:	2240      	movs	r2, #64	@ 0x40
+ 803d752:	621a      	str	r2, [r3, #32]
+
+    /* Enable the DMA transfer for transmit request by setting the DMAT bit
+    in the UART CR3 register */
+    ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+ 803d754:	68fb      	ldr	r3, [r7, #12]
+ 803d756:	681b      	ldr	r3, [r3, #0]
+ 803d758:	3308      	adds	r3, #8
+ 803d75a:	617b      	str	r3, [r7, #20]
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ 803d75c:	697b      	ldr	r3, [r7, #20]
+ 803d75e:	e853 3f00 	ldrex	r3, [r3]
+ 803d762:	613b      	str	r3, [r7, #16]
+   return(result);
+ 803d764:	693b      	ldr	r3, [r7, #16]
+ 803d766:	f043 0380 	orr.w	r3, r3, #128	@ 0x80
+ 803d76a:	627b      	str	r3, [r7, #36]	@ 0x24
+ 803d76c:	68fb      	ldr	r3, [r7, #12]
+ 803d76e:	681b      	ldr	r3, [r3, #0]
+ 803d770:	3308      	adds	r3, #8
+ 803d772:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
+ 803d774:	623a      	str	r2, [r7, #32]
+ 803d776:	61fb      	str	r3, [r7, #28]
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ 803d778:	69f9      	ldr	r1, [r7, #28]
+ 803d77a:	6a3a      	ldr	r2, [r7, #32]
+ 803d77c:	e841 2300 	strex	r3, r2, [r1]
+ 803d780:	61bb      	str	r3, [r7, #24]
+   return(result);
+ 803d782:	69bb      	ldr	r3, [r7, #24]
+ 803d784:	2b00      	cmp	r3, #0
+ 803d786:	d1e5      	bne.n	803d754 <HAL_UART_Transmit_DMA+0xb0>
+
+    return HAL_OK;
+ 803d788:	2300      	movs	r3, #0
+ 803d78a:	e000      	b.n	803d78e <HAL_UART_Transmit_DMA+0xea>
+  }
+  else
+  {
+    return HAL_BUSY;
+ 803d78c:	2302      	movs	r3, #2
+  }
+}
+ 803d78e:	4618      	mov	r0, r3
+ 803d790:	3728      	adds	r7, #40	@ 0x28
+ 803d792:	46bd      	mov	sp, r7
+ 803d794:	bd80      	pop	{r7, pc}
+ 803d796:	bf00      	nop
+ 803d798:	0803f131 	.word	0x0803f131
+ 803d79c:	0803f1c7 	.word	0x0803f1c7
+ 803d7a0:	0803f1e3 	.word	0x0803f1e3
+
+0803d7a4 <HAL_UART_IRQHandler>:
+  * @brief Handle UART interrupt request.
+  * @param huart UART handle.
+  * @retval None
+  */
+void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
+{
+ 803d7a4:	b580      	push	{r7, lr}
+ 803d7a6:	b0ba      	sub	sp, #232	@ 0xe8
+ 803d7a8:	af00      	add	r7, sp, #0
+ 803d7aa:	6078      	str	r0, [r7, #4]
+  uint32_t isrflags   = READ_REG(huart->Instance->ISR);
+ 803d7ac:	687b      	ldr	r3, [r7, #4]
+ 803d7ae:	681b      	ldr	r3, [r3, #0]
+ 803d7b0:	69db      	ldr	r3, [r3, #28]
+ 803d7b2:	f8c7 30e4 	str.w	r3, [r7, #228]	@ 0xe4
+  uint32_t cr1its     = READ_REG(huart->Instance->CR1);
+ 803d7b6:	687b      	ldr	r3, [r7, #4]
+ 803d7b8:	681b      	ldr	r3, [r3, #0]
+ 803d7ba:	681b      	ldr	r3, [r3, #0]
+ 803d7bc:	f8c7 30e0 	str.w	r3, [r7, #224]	@ 0xe0
+  uint32_t cr3its     = READ_REG(huart->Instance->CR3);
+ 803d7c0:	687b      	ldr	r3, [r7, #4]
+ 803d7c2:	681b      	ldr	r3, [r3, #0]
+ 803d7c4:	689b      	ldr	r3, [r3, #8]
+ 803d7c6:	f8c7 30dc 	str.w	r3, [r7, #220]	@ 0xdc
+
+  uint32_t errorflags;
+  uint32_t errorcode;
+
+  /* If no error occurs */
+  errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
+ 803d7ca:	f8d7 20e4 	ldr.w	r2, [r7, #228]	@ 0xe4
+ 803d7ce:	f640 030f 	movw	r3, #2063	@ 0x80f
+ 803d7d2:	4013      	ands	r3, r2
+ 803d7d4:	f8c7 30d8 	str.w	r3, [r7, #216]	@ 0xd8
+  if (errorflags == 0U)
+ 803d7d8:	f8d7 30d8 	ldr.w	r3, [r7, #216]	@ 0xd8
+ 803d7dc:	2b00      	cmp	r3, #0
+ 803d7de:	d11b      	bne.n	803d818 <HAL_UART_IRQHandler+0x74>
+  {
+    /* UART in mode Receiver ---------------------------------------------------*/
+    if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
+ 803d7e0:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
+ 803d7e4:	f003 0320 	and.w	r3, r3, #32
+ 803d7e8:	2b00      	cmp	r3, #0
+ 803d7ea:	d015      	beq.n	803d818 <HAL_UART_IRQHandler+0x74>
+        && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
+ 803d7ec:	f8d7 30e0 	ldr.w	r3, [r7, #224]	@ 0xe0
+ 803d7f0:	f003 0320 	and.w	r3, r3, #32
+ 803d7f4:	2b00      	cmp	r3, #0
+ 803d7f6:	d105      	bne.n	803d804 <HAL_UART_IRQHandler+0x60>
+            || ((cr3its & USART_CR3_RXFTIE) != 0U)))
+ 803d7f8:	f8d7 30dc 	ldr.w	r3, [r7, #220]	@ 0xdc
+ 803d7fc:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
+ 803d800:	2b00      	cmp	r3, #0
+ 803d802:	d009      	beq.n	803d818 <HAL_UART_IRQHandler+0x74>
+    {
+      if (huart->RxISR != NULL)
+ 803d804:	687b      	ldr	r3, [r7, #4]
+ 803d806:	6f5b      	ldr	r3, [r3, #116]	@ 0x74
+ 803d808:	2b00      	cmp	r3, #0
+ 803d80a:	f000 8377 	beq.w	803defc <HAL_UART_IRQHandler+0x758>
+      {
+        huart->RxISR(huart);
+ 803d80e:	687b      	ldr	r3, [r7, #4]
+ 803d810:	6f5b      	ldr	r3, [r3, #116]	@ 0x74
+ 803d812:	6878      	ldr	r0, [r7, #4]
+ 803d814:	4798      	blx	r3
+      }
+      return;
+ 803d816:	e371      	b.n	803defc <HAL_UART_IRQHandler+0x758>
+    }
+  }
+
+  /* If some errors occur */
+  if ((errorflags != 0U)
+ 803d818:	f8d7 30d8 	ldr.w	r3, [r7, #216]	@ 0xd8
+ 803d81c:	2b00      	cmp	r3, #0
+ 803d81e:	f000 8123 	beq.w	803da68 <HAL_UART_IRQHandler+0x2c4>
+      && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)
+ 803d822:	f8d7 20dc 	ldr.w	r2, [r7, #220]	@ 0xdc
+ 803d826:	4b8d      	ldr	r3, [pc, #564]	@ (803da5c <HAL_UART_IRQHandler+0x2b8>)
+ 803d828:	4013      	ands	r3, r2
+ 803d82a:	2b00      	cmp	r3, #0
+ 803d82c:	d106      	bne.n	803d83c <HAL_UART_IRQHandler+0x98>
+           || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U))))
+ 803d82e:	f8d7 20e0 	ldr.w	r2, [r7, #224]	@ 0xe0
+ 803d832:	4b8b      	ldr	r3, [pc, #556]	@ (803da60 <HAL_UART_IRQHandler+0x2bc>)
+ 803d834:	4013      	ands	r3, r2
+ 803d836:	2b00      	cmp	r3, #0
+ 803d838:	f000 8116 	beq.w	803da68 <HAL_UART_IRQHandler+0x2c4>
+  {
+    /* UART parity error interrupt occurred -------------------------------------*/
+    if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
+ 803d83c:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
+ 803d840:	f003 0301 	and.w	r3, r3, #1
+ 803d844:	2b00      	cmp	r3, #0
+ 803d846:	d011      	beq.n	803d86c <HAL_UART_IRQHandler+0xc8>
+ 803d848:	f8d7 30e0 	ldr.w	r3, [r7, #224]	@ 0xe0
+ 803d84c:	f403 7380 	and.w	r3, r3, #256	@ 0x100
+ 803d850:	2b00      	cmp	r3, #0
+ 803d852:	d00b      	beq.n	803d86c <HAL_UART_IRQHandler+0xc8>
+    {
+      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
+ 803d854:	687b      	ldr	r3, [r7, #4]
+ 803d856:	681b      	ldr	r3, [r3, #0]
+ 803d858:	2201      	movs	r2, #1
+ 803d85a:	621a      	str	r2, [r3, #32]
+
+      huart->ErrorCode |= HAL_UART_ERROR_PE;
+ 803d85c:	687b      	ldr	r3, [r7, #4]
+ 803d85e:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
+ 803d862:	f043 0201 	orr.w	r2, r3, #1
+ 803d866:	687b      	ldr	r3, [r7, #4]
+ 803d868:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90
+    }
+
+    /* UART frame error interrupt occurred --------------------------------------*/
+    if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+ 803d86c:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
+ 803d870:	f003 0302 	and.w	r3, r3, #2
+ 803d874:	2b00      	cmp	r3, #0
+ 803d876:	d011      	beq.n	803d89c <HAL_UART_IRQHandler+0xf8>
+ 803d878:	f8d7 30dc 	ldr.w	r3, [r7, #220]	@ 0xdc
+ 803d87c:	f003 0301 	and.w	r3, r3, #1
+ 803d880:	2b00      	cmp	r3, #0
+ 803d882:	d00b      	beq.n	803d89c <HAL_UART_IRQHandler+0xf8>
+    {
+      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
+ 803d884:	687b      	ldr	r3, [r7, #4]
+ 803d886:	681b      	ldr	r3, [r3, #0]
+ 803d888:	2202      	movs	r2, #2
+ 803d88a:	621a      	str	r2, [r3, #32]
+
+      huart->ErrorCode |= HAL_UART_ERROR_FE;
+ 803d88c:	687b      	ldr	r3, [r7, #4]
+ 803d88e:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
+ 803d892:	f043 0204 	orr.w	r2, r3, #4
+ 803d896:	687b      	ldr	r3, [r7, #4]
+ 803d898:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90
+    }
+
+    /* UART noise error interrupt occurred --------------------------------------*/
+    if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+ 803d89c:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
+ 803d8a0:	f003 0304 	and.w	r3, r3, #4
+ 803d8a4:	2b00      	cmp	r3, #0
+ 803d8a6:	d011      	beq.n	803d8cc <HAL_UART_IRQHandler+0x128>
+ 803d8a8:	f8d7 30dc 	ldr.w	r3, [r7, #220]	@ 0xdc
+ 803d8ac:	f003 0301 	and.w	r3, r3, #1
+ 803d8b0:	2b00      	cmp	r3, #0
+ 803d8b2:	d00b      	beq.n	803d8cc <HAL_UART_IRQHandler+0x128>
+    {
+      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
+ 803d8b4:	687b      	ldr	r3, [r7, #4]
+ 803d8b6:	681b      	ldr	r3, [r3, #0]
+ 803d8b8:	2204      	movs	r2, #4
+ 803d8ba:	621a      	str	r2, [r3, #32]
+
+      huart->ErrorCode |= HAL_UART_ERROR_NE;
+ 803d8bc:	687b      	ldr	r3, [r7, #4]
+ 803d8be:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
+ 803d8c2:	f043 0202 	orr.w	r2, r3, #2
+ 803d8c6:	687b      	ldr	r3, [r7, #4]
+ 803d8c8:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90
+    }
+
+    /* UART Over-Run interrupt occurred -----------------------------------------*/
+    if (((isrflags & USART_ISR_ORE) != 0U)
+ 803d8cc:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
+ 803d8d0:	f003 0308 	and.w	r3, r3, #8
+ 803d8d4:	2b00      	cmp	r3, #0
+ 803d8d6:	d017      	beq.n	803d908 <HAL_UART_IRQHandler+0x164>
+        && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
+ 803d8d8:	f8d7 30e0 	ldr.w	r3, [r7, #224]	@ 0xe0
+ 803d8dc:	f003 0320 	and.w	r3, r3, #32
+ 803d8e0:	2b00      	cmp	r3, #0
+ 803d8e2:	d105      	bne.n	803d8f0 <HAL_UART_IRQHandler+0x14c>
+            ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)))
+ 803d8e4:	f8d7 20dc 	ldr.w	r2, [r7, #220]	@ 0xdc
+ 803d8e8:	4b5c      	ldr	r3, [pc, #368]	@ (803da5c <HAL_UART_IRQHandler+0x2b8>)
+ 803d8ea:	4013      	ands	r3, r2
+        && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
+ 803d8ec:	2b00      	cmp	r3, #0
+ 803d8ee:	d00b      	beq.n	803d908 <HAL_UART_IRQHandler+0x164>
+    {
+      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
+ 803d8f0:	687b      	ldr	r3, [r7, #4]
+ 803d8f2:	681b      	ldr	r3, [r3, #0]
+ 803d8f4:	2208      	movs	r2, #8
+ 803d8f6:	621a      	str	r2, [r3, #32]
+
+      huart->ErrorCode |= HAL_UART_ERROR_ORE;
+ 803d8f8:	687b      	ldr	r3, [r7, #4]
+ 803d8fa:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
+ 803d8fe:	f043 0208 	orr.w	r2, r3, #8
+ 803d902:	687b      	ldr	r3, [r7, #4]
+ 803d904:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90
+    }
+
+    /* UART Receiver Timeout interrupt occurred ---------------------------------*/
+    if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
+ 803d908:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
+ 803d90c:	f403 6300 	and.w	r3, r3, #2048	@ 0x800
+ 803d910:	2b00      	cmp	r3, #0
+ 803d912:	d012      	beq.n	803d93a <HAL_UART_IRQHandler+0x196>
+ 803d914:	f8d7 30e0 	ldr.w	r3, [r7, #224]	@ 0xe0
+ 803d918:	f003 6380 	and.w	r3, r3, #67108864	@ 0x4000000
+ 803d91c:	2b00      	cmp	r3, #0
+ 803d91e:	d00c      	beq.n	803d93a <HAL_UART_IRQHandler+0x196>
+    {
+      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
+ 803d920:	687b      	ldr	r3, [r7, #4]
+ 803d922:	681b      	ldr	r3, [r3, #0]
+ 803d924:	f44f 6200 	mov.w	r2, #2048	@ 0x800
+ 803d928:	621a      	str	r2, [r3, #32]
+
+      huart->ErrorCode |= HAL_UART_ERROR_RTO;
+ 803d92a:	687b      	ldr	r3, [r7, #4]
+ 803d92c:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
+ 803d930:	f043 0220 	orr.w	r2, r3, #32
+ 803d934:	687b      	ldr	r3, [r7, #4]
+ 803d936:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90
+    }
+
+    /* Call UART Error Call back function if need be ----------------------------*/
+    if (huart->ErrorCode != HAL_UART_ERROR_NONE)
+ 803d93a:	687b      	ldr	r3, [r7, #4]
+ 803d93c:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
+ 803d940:	2b00      	cmp	r3, #0
+ 803d942:	f000 82dd 	beq.w	803df00 <HAL_UART_IRQHandler+0x75c>
+    {
+      /* UART in mode Receiver --------------------------------------------------*/
+      if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
+ 803d946:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
+ 803d94a:	f003 0320 	and.w	r3, r3, #32
+ 803d94e:	2b00      	cmp	r3, #0
+ 803d950:	d013      	beq.n	803d97a <HAL_UART_IRQHandler+0x1d6>
+          && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
+ 803d952:	f8d7 30e0 	ldr.w	r3, [r7, #224]	@ 0xe0
+ 803d956:	f003 0320 	and.w	r3, r3, #32
+ 803d95a:	2b00      	cmp	r3, #0
+ 803d95c:	d105      	bne.n	803d96a <HAL_UART_IRQHandler+0x1c6>
+              || ((cr3its & USART_CR3_RXFTIE) != 0U)))
+ 803d95e:	f8d7 30dc 	ldr.w	r3, [r7, #220]	@ 0xdc
+ 803d962:	f003 5380 	and.w	r3, r3, #268435456	@ 0x10000000
+ 803d966:	2b00      	cmp	r3, #0
+ 803d968:	d007      	beq.n	803d97a <HAL_UART_IRQHandler+0x1d6>
+      {
+        if (huart->RxISR != NULL)
+ 803d96a:	687b      	ldr	r3, [r7, #4]
+ 803d96c:	6f5b      	ldr	r3, [r3, #116]	@ 0x74
+ 803d96e:	2b00      	cmp	r3, #0
+ 803d970:	d003      	beq.n	803d97a <HAL_UART_IRQHandler+0x1d6>
+        {
+          huart->RxISR(huart);
+ 803d972:	687b      	ldr	r3, [r7, #4]
+ 803d974:	6f5b      	ldr	r3, [r3, #116]	@ 0x74
+ 803d976:	6878      	ldr	r0, [r7, #4]
+ 803d978:	4798      	blx	r3
+      /* If Error is to be considered as blocking :
+          - Receiver Timeout error in Reception
+          - Overrun error in Reception
+          - any error occurs in DMA mode reception
+      */
+      errorcode = huart->ErrorCode;
+ 803d97a:	687b      	ldr	r3, [r7, #4]
+ 803d97c:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
+ 803d980:	f8c7 30d4 	str.w	r3, [r7, #212]	@ 0xd4
+      if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
+ 803d984:	687b      	ldr	r3, [r7, #4]
+ 803d986:	681b      	ldr	r3, [r3, #0]
+ 803d988:	689b      	ldr	r3, [r3, #8]
+ 803d98a:	f003 0340 	and.w	r3, r3, #64	@ 0x40
+ 803d98e:	2b40      	cmp	r3, #64	@ 0x40
+ 803d990:	d005      	beq.n	803d99e <HAL_UART_IRQHandler+0x1fa>
+          ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U))
+ 803d992:	f8d7 30d4 	ldr.w	r3, [r7, #212]	@ 0xd4
+ 803d996:	f003 0328 	and.w	r3, r3, #40	@ 0x28
+      if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
+ 803d99a:	2b00      	cmp	r3, #0
+ 803d99c:	d054      	beq.n	803da48 <HAL_UART_IRQHandler+0x2a4>
+      {
+        /* Blocking error : transfer is aborted
+           Set the UART state ready to be able to start again the process,
+           Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
+        UART_EndRxTransfer(huart);
+ 803d99e:	6878      	ldr	r0, [r7, #4]
+ 803d9a0:	f001 fb60 	bl	803f064 <UART_EndRxTransfer>
+
+        /* Abort the UART DMA Rx channel if enabled */
+        if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ 803d9a4:	687b      	ldr	r3, [r7, #4]
+ 803d9a6:	681b      	ldr	r3, [r3, #0]
+ 803d9a8:	689b      	ldr	r3, [r3, #8]
+ 803d9aa:	f003 0340 	and.w	r3, r3, #64	@ 0x40
+ 803d9ae:	2b40      	cmp	r3, #64	@ 0x40
+ 803d9b0:	d146      	bne.n	803da40 <HAL_UART_IRQHandler+0x29c>
+        {
+          /* Disable the UART DMA Rx request if enabled */
+          ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+ 803d9b2:	687b      	ldr	r3, [r7, #4]
+ 803d9b4:	681b      	ldr	r3, [r3, #0]
+ 803d9b6:	3308      	adds	r3, #8
+ 803d9b8:	f8c7 309c 	str.w	r3, [r7, #156]	@ 0x9c
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ 803d9bc:	f8d7 309c 	ldr.w	r3, [r7, #156]	@ 0x9c
+ 803d9c0:	e853 3f00 	ldrex	r3, [r3]
+ 803d9c4:	f8c7 3098 	str.w	r3, [r7, #152]	@ 0x98
+   return(result);
+ 803d9c8:	f8d7 3098 	ldr.w	r3, [r7, #152]	@ 0x98
+ 803d9cc:	f023 0340 	bic.w	r3, r3, #64	@ 0x40
+ 803d9d0:	f8c7 30d0 	str.w	r3, [r7, #208]	@ 0xd0
+ 803d9d4:	687b      	ldr	r3, [r7, #4]
+ 803d9d6:	681b      	ldr	r3, [r3, #0]
+ 803d9d8:	3308      	adds	r3, #8
+ 803d9da:	f8d7 20d0 	ldr.w	r2, [r7, #208]	@ 0xd0
+ 803d9de:	f8c7 20a8 	str.w	r2, [r7, #168]	@ 0xa8
+ 803d9e2:	f8c7 30a4 	str.w	r3, [r7, #164]	@ 0xa4
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ 803d9e6:	f8d7 10a4 	ldr.w	r1, [r7, #164]	@ 0xa4
+ 803d9ea:	f8d7 20a8 	ldr.w	r2, [r7, #168]	@ 0xa8
+ 803d9ee:	e841 2300 	strex	r3, r2, [r1]
+ 803d9f2:	f8c7 30a0 	str.w	r3, [r7, #160]	@ 0xa0
+   return(result);
+ 803d9f6:	f8d7 30a0 	ldr.w	r3, [r7, #160]	@ 0xa0
+ 803d9fa:	2b00      	cmp	r3, #0
+ 803d9fc:	d1d9      	bne.n	803d9b2 <HAL_UART_IRQHandler+0x20e>
+
+          /* Abort the UART DMA Rx channel */
+          if (huart->hdmarx != NULL)
+ 803d9fe:	687b      	ldr	r3, [r7, #4]
+ 803da00:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
+ 803da04:	2b00      	cmp	r3, #0
+ 803da06:	d017      	beq.n	803da38 <HAL_UART_IRQHandler+0x294>
+          {
+            /* Set the UART DMA Abort callback :
+               will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
+            huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
+ 803da08:	687b      	ldr	r3, [r7, #4]
+ 803da0a:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
+ 803da0e:	4a15      	ldr	r2, [pc, #84]	@ (803da64 <HAL_UART_IRQHandler+0x2c0>)
+ 803da10:	651a      	str	r2, [r3, #80]	@ 0x50
+
+            /* Abort DMA RX */
+            if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+ 803da12:	687b      	ldr	r3, [r7, #4]
+ 803da14:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
+ 803da18:	4618      	mov	r0, r3
+ 803da1a:	f7f6 f9db 	bl	8033dd4 <HAL_DMA_Abort_IT>
+ 803da1e:	4603      	mov	r3, r0
+ 803da20:	2b00      	cmp	r3, #0
+ 803da22:	d019      	beq.n	803da58 <HAL_UART_IRQHandler+0x2b4>
+            {
+              /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
+              huart->hdmarx->XferAbortCallback(huart->hdmarx);
+ 803da24:	687b      	ldr	r3, [r7, #4]
+ 803da26:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
+ 803da2a:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
+ 803da2c:	687a      	ldr	r2, [r7, #4]
+ 803da2e:	f8d2 2080 	ldr.w	r2, [r2, #128]	@ 0x80
+ 803da32:	4610      	mov	r0, r2
+ 803da34:	4798      	blx	r3
+        if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ 803da36:	e00f      	b.n	803da58 <HAL_UART_IRQHandler+0x2b4>
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+            /*Call registered error callback*/
+            huart->ErrorCallback(huart);
+#else
+            /*Call legacy weak error callback*/
+            HAL_UART_ErrorCallback(huart);
+ 803da38:	6878      	ldr	r0, [r7, #4]
+ 803da3a:	f000 fa77 	bl	803df2c <HAL_UART_ErrorCallback>
+        if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ 803da3e:	e00b      	b.n	803da58 <HAL_UART_IRQHandler+0x2b4>
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+          /*Call registered error callback*/
+          huart->ErrorCallback(huart);
+#else
+          /*Call legacy weak error callback*/
+          HAL_UART_ErrorCallback(huart);
+ 803da40:	6878      	ldr	r0, [r7, #4]
+ 803da42:	f000 fa73 	bl	803df2c <HAL_UART_ErrorCallback>
+        if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ 803da46:	e007      	b.n	803da58 <HAL_UART_IRQHandler+0x2b4>
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+        /*Call registered error callback*/
+        huart->ErrorCallback(huart);
+#else
+        /*Call legacy weak error callback*/
+        HAL_UART_ErrorCallback(huart);
+ 803da48:	6878      	ldr	r0, [r7, #4]
+ 803da4a:	f000 fa6f 	bl	803df2c <HAL_UART_ErrorCallback>
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+        huart->ErrorCode = HAL_UART_ERROR_NONE;
+ 803da4e:	687b      	ldr	r3, [r7, #4]
+ 803da50:	2200      	movs	r2, #0
+ 803da52:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90
+      }
+    }
+    return;
+ 803da56:	e253      	b.n	803df00 <HAL_UART_IRQHandler+0x75c>
+        if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ 803da58:	bf00      	nop
+    return;
+ 803da5a:	e251      	b.n	803df00 <HAL_UART_IRQHandler+0x75c>
+ 803da5c:	10000001 	.word	0x10000001
+ 803da60:	04000120 	.word	0x04000120
+ 803da64:	0803f263 	.word	0x0803f263
+
+  } /* End if some error occurs */
+
+  /* Check current reception Mode :
+     If Reception till IDLE event has been selected : */
+  if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ 803da68:	687b      	ldr	r3, [r7, #4]
+ 803da6a:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
+ 803da6c:	2b01      	cmp	r3, #1
+ 803da6e:	f040 81e7 	bne.w	803de40 <HAL_UART_IRQHandler+0x69c>
+      && ((isrflags & USART_ISR_IDLE) != 0U)
+ 803da72:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
+ 803da76:	f003 0310 	and.w	r3, r3, #16
+ 803da7a:	2b00      	cmp	r3, #0
+ 803da7c:	f000 81e0 	beq.w	803de40 <HAL_UART_IRQHandler+0x69c>
+      && ((cr1its & USART_ISR_IDLE) != 0U))
+ 803da80:	f8d7 30e0 	ldr.w	r3, [r7, #224]	@ 0xe0
+ 803da84:	f003 0310 	and.w	r3, r3, #16
+ 803da88:	2b00      	cmp	r3, #0
+ 803da8a:	f000 81d9 	beq.w	803de40 <HAL_UART_IRQHandler+0x69c>
+  {
+    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+ 803da8e:	687b      	ldr	r3, [r7, #4]
+ 803da90:	681b      	ldr	r3, [r3, #0]
+ 803da92:	2210      	movs	r2, #16
+ 803da94:	621a      	str	r2, [r3, #32]
+
+    /* Check if DMA mode is enabled in UART */
+    if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ 803da96:	687b      	ldr	r3, [r7, #4]
+ 803da98:	681b      	ldr	r3, [r3, #0]
+ 803da9a:	689b      	ldr	r3, [r3, #8]
+ 803da9c:	f003 0340 	and.w	r3, r3, #64	@ 0x40
+ 803daa0:	2b40      	cmp	r3, #64	@ 0x40
+ 803daa2:	f040 8151 	bne.w	803dd48 <HAL_UART_IRQHandler+0x5a4>
+    {
+      /* DMA mode enabled */
+      /* Check received length : If all expected data are received, do nothing,
+         (DMA cplt callback will be called).
+         Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
+      uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx);
+ 803daa6:	687b      	ldr	r3, [r7, #4]
+ 803daa8:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
+ 803daac:	681b      	ldr	r3, [r3, #0]
+ 803daae:	4a96      	ldr	r2, [pc, #600]	@ (803dd08 <HAL_UART_IRQHandler+0x564>)
+ 803dab0:	4293      	cmp	r3, r2
+ 803dab2:	d068      	beq.n	803db86 <HAL_UART_IRQHandler+0x3e2>
+ 803dab4:	687b      	ldr	r3, [r7, #4]
+ 803dab6:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
+ 803daba:	681b      	ldr	r3, [r3, #0]
+ 803dabc:	4a93      	ldr	r2, [pc, #588]	@ (803dd0c <HAL_UART_IRQHandler+0x568>)
+ 803dabe:	4293      	cmp	r3, r2
+ 803dac0:	d061      	beq.n	803db86 <HAL_UART_IRQHandler+0x3e2>
+ 803dac2:	687b      	ldr	r3, [r7, #4]
+ 803dac4:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
+ 803dac8:	681b      	ldr	r3, [r3, #0]
+ 803daca:	4a91      	ldr	r2, [pc, #580]	@ (803dd10 <HAL_UART_IRQHandler+0x56c>)
+ 803dacc:	4293      	cmp	r3, r2
+ 803dace:	d05a      	beq.n	803db86 <HAL_UART_IRQHandler+0x3e2>
+ 803dad0:	687b      	ldr	r3, [r7, #4]
+ 803dad2:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
+ 803dad6:	681b      	ldr	r3, [r3, #0]
+ 803dad8:	4a8e      	ldr	r2, [pc, #568]	@ (803dd14 <HAL_UART_IRQHandler+0x570>)
+ 803dada:	4293      	cmp	r3, r2
+ 803dadc:	d053      	beq.n	803db86 <HAL_UART_IRQHandler+0x3e2>
+ 803dade:	687b      	ldr	r3, [r7, #4]
+ 803dae0:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
+ 803dae4:	681b      	ldr	r3, [r3, #0]
+ 803dae6:	4a8c      	ldr	r2, [pc, #560]	@ (803dd18 <HAL_UART_IRQHandler+0x574>)
+ 803dae8:	4293      	cmp	r3, r2
+ 803daea:	d04c      	beq.n	803db86 <HAL_UART_IRQHandler+0x3e2>
+ 803daec:	687b      	ldr	r3, [r7, #4]
+ 803daee:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
+ 803daf2:	681b      	ldr	r3, [r3, #0]
+ 803daf4:	4a89      	ldr	r2, [pc, #548]	@ (803dd1c <HAL_UART_IRQHandler+0x578>)
+ 803daf6:	4293      	cmp	r3, r2
+ 803daf8:	d045      	beq.n	803db86 <HAL_UART_IRQHandler+0x3e2>
+ 803dafa:	687b      	ldr	r3, [r7, #4]
+ 803dafc:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
+ 803db00:	681b      	ldr	r3, [r3, #0]
+ 803db02:	4a87      	ldr	r2, [pc, #540]	@ (803dd20 <HAL_UART_IRQHandler+0x57c>)
+ 803db04:	4293      	cmp	r3, r2
+ 803db06:	d03e      	beq.n	803db86 <HAL_UART_IRQHandler+0x3e2>
+ 803db08:	687b      	ldr	r3, [r7, #4]
+ 803db0a:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
+ 803db0e:	681b      	ldr	r3, [r3, #0]
+ 803db10:	4a84      	ldr	r2, [pc, #528]	@ (803dd24 <HAL_UART_IRQHandler+0x580>)
+ 803db12:	4293      	cmp	r3, r2
+ 803db14:	d037      	beq.n	803db86 <HAL_UART_IRQHandler+0x3e2>
+ 803db16:	687b      	ldr	r3, [r7, #4]
+ 803db18:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
+ 803db1c:	681b      	ldr	r3, [r3, #0]
+ 803db1e:	4a82      	ldr	r2, [pc, #520]	@ (803dd28 <HAL_UART_IRQHandler+0x584>)
+ 803db20:	4293      	cmp	r3, r2
+ 803db22:	d030      	beq.n	803db86 <HAL_UART_IRQHandler+0x3e2>
+ 803db24:	687b      	ldr	r3, [r7, #4]
+ 803db26:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
+ 803db2a:	681b      	ldr	r3, [r3, #0]
+ 803db2c:	4a7f      	ldr	r2, [pc, #508]	@ (803dd2c <HAL_UART_IRQHandler+0x588>)
+ 803db2e:	4293      	cmp	r3, r2
+ 803db30:	d029      	beq.n	803db86 <HAL_UART_IRQHandler+0x3e2>
+ 803db32:	687b      	ldr	r3, [r7, #4]
+ 803db34:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
+ 803db38:	681b      	ldr	r3, [r3, #0]
+ 803db3a:	4a7d      	ldr	r2, [pc, #500]	@ (803dd30 <HAL_UART_IRQHandler+0x58c>)
+ 803db3c:	4293      	cmp	r3, r2
+ 803db3e:	d022      	beq.n	803db86 <HAL_UART_IRQHandler+0x3e2>
+ 803db40:	687b      	ldr	r3, [r7, #4]
+ 803db42:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
+ 803db46:	681b      	ldr	r3, [r3, #0]
+ 803db48:	4a7a      	ldr	r2, [pc, #488]	@ (803dd34 <HAL_UART_IRQHandler+0x590>)
+ 803db4a:	4293      	cmp	r3, r2
+ 803db4c:	d01b      	beq.n	803db86 <HAL_UART_IRQHandler+0x3e2>
+ 803db4e:	687b      	ldr	r3, [r7, #4]
+ 803db50:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
+ 803db54:	681b      	ldr	r3, [r3, #0]
+ 803db56:	4a78      	ldr	r2, [pc, #480]	@ (803dd38 <HAL_UART_IRQHandler+0x594>)
+ 803db58:	4293      	cmp	r3, r2
+ 803db5a:	d014      	beq.n	803db86 <HAL_UART_IRQHandler+0x3e2>
+ 803db5c:	687b      	ldr	r3, [r7, #4]
+ 803db5e:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
+ 803db62:	681b      	ldr	r3, [r3, #0]
+ 803db64:	4a75      	ldr	r2, [pc, #468]	@ (803dd3c <HAL_UART_IRQHandler+0x598>)
+ 803db66:	4293      	cmp	r3, r2
+ 803db68:	d00d      	beq.n	803db86 <HAL_UART_IRQHandler+0x3e2>
+ 803db6a:	687b      	ldr	r3, [r7, #4]
+ 803db6c:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
+ 803db70:	681b      	ldr	r3, [r3, #0]
+ 803db72:	4a73      	ldr	r2, [pc, #460]	@ (803dd40 <HAL_UART_IRQHandler+0x59c>)
+ 803db74:	4293      	cmp	r3, r2
+ 803db76:	d006      	beq.n	803db86 <HAL_UART_IRQHandler+0x3e2>
+ 803db78:	687b      	ldr	r3, [r7, #4]
+ 803db7a:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
+ 803db7e:	681b      	ldr	r3, [r3, #0]
+ 803db80:	4a70      	ldr	r2, [pc, #448]	@ (803dd44 <HAL_UART_IRQHandler+0x5a0>)
+ 803db82:	4293      	cmp	r3, r2
+ 803db84:	d106      	bne.n	803db94 <HAL_UART_IRQHandler+0x3f0>
+ 803db86:	687b      	ldr	r3, [r7, #4]
+ 803db88:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
+ 803db8c:	681b      	ldr	r3, [r3, #0]
+ 803db8e:	685b      	ldr	r3, [r3, #4]
+ 803db90:	b29b      	uxth	r3, r3
+ 803db92:	e005      	b.n	803dba0 <HAL_UART_IRQHandler+0x3fc>
+ 803db94:	687b      	ldr	r3, [r7, #4]
+ 803db96:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
+ 803db9a:	681b      	ldr	r3, [r3, #0]
+ 803db9c:	685b      	ldr	r3, [r3, #4]
+ 803db9e:	b29b      	uxth	r3, r3
+ 803dba0:	f8a7 30be 	strh.w	r3, [r7, #190]	@ 0xbe
+      if ((nb_remaining_rx_data > 0U)
+ 803dba4:	f8b7 30be 	ldrh.w	r3, [r7, #190]	@ 0xbe
+ 803dba8:	2b00      	cmp	r3, #0
+ 803dbaa:	f000 81ab 	beq.w	803df04 <HAL_UART_IRQHandler+0x760>
+          && (nb_remaining_rx_data < huart->RxXferSize))
+ 803dbae:	687b      	ldr	r3, [r7, #4]
+ 803dbb0:	f8b3 305c 	ldrh.w	r3, [r3, #92]	@ 0x5c
+ 803dbb4:	f8b7 20be 	ldrh.w	r2, [r7, #190]	@ 0xbe
+ 803dbb8:	429a      	cmp	r2, r3
+ 803dbba:	f080 81a3 	bcs.w	803df04 <HAL_UART_IRQHandler+0x760>
+      {
+        /* Reception is not complete */
+        huart->RxXferCount = nb_remaining_rx_data;
+ 803dbbe:	687b      	ldr	r3, [r7, #4]
+ 803dbc0:	f8b7 20be 	ldrh.w	r2, [r7, #190]	@ 0xbe
+ 803dbc4:	f8a3 205e 	strh.w	r2, [r3, #94]	@ 0x5e
+
+        /* In Normal mode, end DMA xfer and HAL UART Rx process*/
+        if (huart->hdmarx->Init.Mode != DMA_CIRCULAR)
+ 803dbc8:	687b      	ldr	r3, [r7, #4]
+ 803dbca:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
+ 803dbce:	69db      	ldr	r3, [r3, #28]
+ 803dbd0:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
+ 803dbd4:	f000 8087 	beq.w	803dce6 <HAL_UART_IRQHandler+0x542>
+        {
+          /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ 803dbd8:	687b      	ldr	r3, [r7, #4]
+ 803dbda:	681b      	ldr	r3, [r3, #0]
+ 803dbdc:	f8c7 3088 	str.w	r3, [r7, #136]	@ 0x88
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ 803dbe0:	f8d7 3088 	ldr.w	r3, [r7, #136]	@ 0x88
+ 803dbe4:	e853 3f00 	ldrex	r3, [r3]
+ 803dbe8:	f8c7 3084 	str.w	r3, [r7, #132]	@ 0x84
+   return(result);
+ 803dbec:	f8d7 3084 	ldr.w	r3, [r7, #132]	@ 0x84
+ 803dbf0:	f423 7380 	bic.w	r3, r3, #256	@ 0x100
+ 803dbf4:	f8c7 30b8 	str.w	r3, [r7, #184]	@ 0xb8
+ 803dbf8:	687b      	ldr	r3, [r7, #4]
+ 803dbfa:	681b      	ldr	r3, [r3, #0]
+ 803dbfc:	461a      	mov	r2, r3
+ 803dbfe:	f8d7 30b8 	ldr.w	r3, [r7, #184]	@ 0xb8
+ 803dc02:	f8c7 3094 	str.w	r3, [r7, #148]	@ 0x94
+ 803dc06:	f8c7 2090 	str.w	r2, [r7, #144]	@ 0x90
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ 803dc0a:	f8d7 1090 	ldr.w	r1, [r7, #144]	@ 0x90
+ 803dc0e:	f8d7 2094 	ldr.w	r2, [r7, #148]	@ 0x94
+ 803dc12:	e841 2300 	strex	r3, r2, [r1]
+ 803dc16:	f8c7 308c 	str.w	r3, [r7, #140]	@ 0x8c
+   return(result);
+ 803dc1a:	f8d7 308c 	ldr.w	r3, [r7, #140]	@ 0x8c
+ 803dc1e:	2b00      	cmp	r3, #0
+ 803dc20:	d1da      	bne.n	803dbd8 <HAL_UART_IRQHandler+0x434>
+          ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ 803dc22:	687b      	ldr	r3, [r7, #4]
+ 803dc24:	681b      	ldr	r3, [r3, #0]
+ 803dc26:	3308      	adds	r3, #8
+ 803dc28:	677b      	str	r3, [r7, #116]	@ 0x74
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ 803dc2a:	6f7b      	ldr	r3, [r7, #116]	@ 0x74
+ 803dc2c:	e853 3f00 	ldrex	r3, [r3]
+ 803dc30:	673b      	str	r3, [r7, #112]	@ 0x70
+   return(result);
+ 803dc32:	6f3b      	ldr	r3, [r7, #112]	@ 0x70
+ 803dc34:	f023 0301 	bic.w	r3, r3, #1
+ 803dc38:	f8c7 30b4 	str.w	r3, [r7, #180]	@ 0xb4
+ 803dc3c:	687b      	ldr	r3, [r7, #4]
+ 803dc3e:	681b      	ldr	r3, [r3, #0]
+ 803dc40:	3308      	adds	r3, #8
+ 803dc42:	f8d7 20b4 	ldr.w	r2, [r7, #180]	@ 0xb4
+ 803dc46:	f8c7 2080 	str.w	r2, [r7, #128]	@ 0x80
+ 803dc4a:	67fb      	str	r3, [r7, #124]	@ 0x7c
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ 803dc4c:	6ff9      	ldr	r1, [r7, #124]	@ 0x7c
+ 803dc4e:	f8d7 2080 	ldr.w	r2, [r7, #128]	@ 0x80
+ 803dc52:	e841 2300 	strex	r3, r2, [r1]
+ 803dc56:	67bb      	str	r3, [r7, #120]	@ 0x78
+   return(result);
+ 803dc58:	6fbb      	ldr	r3, [r7, #120]	@ 0x78
+ 803dc5a:	2b00      	cmp	r3, #0
+ 803dc5c:	d1e1      	bne.n	803dc22 <HAL_UART_IRQHandler+0x47e>
+
+          /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
+             in the UART CR3 register */
+          ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+ 803dc5e:	687b      	ldr	r3, [r7, #4]
+ 803dc60:	681b      	ldr	r3, [r3, #0]
+ 803dc62:	3308      	adds	r3, #8
+ 803dc64:	663b      	str	r3, [r7, #96]	@ 0x60
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ 803dc66:	6e3b      	ldr	r3, [r7, #96]	@ 0x60
+ 803dc68:	e853 3f00 	ldrex	r3, [r3]
+ 803dc6c:	65fb      	str	r3, [r7, #92]	@ 0x5c
+   return(result);
+ 803dc6e:	6dfb      	ldr	r3, [r7, #92]	@ 0x5c
+ 803dc70:	f023 0340 	bic.w	r3, r3, #64	@ 0x40
+ 803dc74:	f8c7 30b0 	str.w	r3, [r7, #176]	@ 0xb0
+ 803dc78:	687b      	ldr	r3, [r7, #4]
+ 803dc7a:	681b      	ldr	r3, [r3, #0]
+ 803dc7c:	3308      	adds	r3, #8
+ 803dc7e:	f8d7 20b0 	ldr.w	r2, [r7, #176]	@ 0xb0
+ 803dc82:	66fa      	str	r2, [r7, #108]	@ 0x6c
+ 803dc84:	66bb      	str	r3, [r7, #104]	@ 0x68
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ 803dc86:	6eb9      	ldr	r1, [r7, #104]	@ 0x68
+ 803dc88:	6efa      	ldr	r2, [r7, #108]	@ 0x6c
+ 803dc8a:	e841 2300 	strex	r3, r2, [r1]
+ 803dc8e:	667b      	str	r3, [r7, #100]	@ 0x64
+   return(result);
+ 803dc90:	6e7b      	ldr	r3, [r7, #100]	@ 0x64
+ 803dc92:	2b00      	cmp	r3, #0
+ 803dc94:	d1e3      	bne.n	803dc5e <HAL_UART_IRQHandler+0x4ba>
+
+          /* At end of Rx process, restore huart->RxState to Ready */
+          huart->RxState = HAL_UART_STATE_READY;
+ 803dc96:	687b      	ldr	r3, [r7, #4]
+ 803dc98:	2220      	movs	r2, #32
+ 803dc9a:	f8c3 208c 	str.w	r2, [r3, #140]	@ 0x8c
+          huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ 803dc9e:	687b      	ldr	r3, [r7, #4]
+ 803dca0:	2200      	movs	r2, #0
+ 803dca2:	66da      	str	r2, [r3, #108]	@ 0x6c
+
+          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ 803dca4:	687b      	ldr	r3, [r7, #4]
+ 803dca6:	681b      	ldr	r3, [r3, #0]
+ 803dca8:	64fb      	str	r3, [r7, #76]	@ 0x4c
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ 803dcaa:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
+ 803dcac:	e853 3f00 	ldrex	r3, [r3]
+ 803dcb0:	64bb      	str	r3, [r7, #72]	@ 0x48
+   return(result);
+ 803dcb2:	6cbb      	ldr	r3, [r7, #72]	@ 0x48
+ 803dcb4:	f023 0310 	bic.w	r3, r3, #16
+ 803dcb8:	f8c7 30ac 	str.w	r3, [r7, #172]	@ 0xac
+ 803dcbc:	687b      	ldr	r3, [r7, #4]
+ 803dcbe:	681b      	ldr	r3, [r3, #0]
+ 803dcc0:	461a      	mov	r2, r3
+ 803dcc2:	f8d7 30ac 	ldr.w	r3, [r7, #172]	@ 0xac
+ 803dcc6:	65bb      	str	r3, [r7, #88]	@ 0x58
+ 803dcc8:	657a      	str	r2, [r7, #84]	@ 0x54
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ 803dcca:	6d79      	ldr	r1, [r7, #84]	@ 0x54
+ 803dccc:	6dba      	ldr	r2, [r7, #88]	@ 0x58
+ 803dcce:	e841 2300 	strex	r3, r2, [r1]
+ 803dcd2:	653b      	str	r3, [r7, #80]	@ 0x50
+   return(result);
+ 803dcd4:	6d3b      	ldr	r3, [r7, #80]	@ 0x50
+ 803dcd6:	2b00      	cmp	r3, #0
+ 803dcd8:	d1e4      	bne.n	803dca4 <HAL_UART_IRQHandler+0x500>
+
+          /* Last bytes received, so no need as the abort is immediate */
+          (void)HAL_DMA_Abort(huart->hdmarx);
+ 803dcda:	687b      	ldr	r3, [r7, #4]
+ 803dcdc:	f8d3 3080 	ldr.w	r3, [r3, #128]	@ 0x80
+ 803dce0:	4618      	mov	r0, r3
+ 803dce2:	f7f5 fd59 	bl	8033798 <HAL_DMA_Abort>
+        }
+
+        /* Initialize type of RxEvent that correspond to RxEvent callback execution;
+           In this case, Rx Event type is Idle Event */
+        huart->RxEventType = HAL_UART_RXEVENT_IDLE;
+ 803dce6:	687b      	ldr	r3, [r7, #4]
+ 803dce8:	2202      	movs	r2, #2
+ 803dcea:	671a      	str	r2, [r3, #112]	@ 0x70
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+        /*Call registered Rx Event callback*/
+        huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
+#else
+        /*Call legacy weak Rx Event callback*/
+        HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
+ 803dcec:	687b      	ldr	r3, [r7, #4]
+ 803dcee:	f8b3 205c 	ldrh.w	r2, [r3, #92]	@ 0x5c
+ 803dcf2:	687b      	ldr	r3, [r7, #4]
+ 803dcf4:	f8b3 305e 	ldrh.w	r3, [r3, #94]	@ 0x5e
+ 803dcf8:	b29b      	uxth	r3, r3
+ 803dcfa:	1ad3      	subs	r3, r2, r3
+ 803dcfc:	b29b      	uxth	r3, r3
+ 803dcfe:	4619      	mov	r1, r3
+ 803dd00:	6878      	ldr	r0, [r7, #4]
+ 803dd02:	f000 f91d 	bl	803df40 <HAL_UARTEx_RxEventCallback>
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+      }
+      return;
+ 803dd06:	e0fd      	b.n	803df04 <HAL_UART_IRQHandler+0x760>
+ 803dd08:	40020010 	.word	0x40020010
+ 803dd0c:	40020028 	.word	0x40020028
+ 803dd10:	40020040 	.word	0x40020040
+ 803dd14:	40020058 	.word	0x40020058
+ 803dd18:	40020070 	.word	0x40020070
+ 803dd1c:	40020088 	.word	0x40020088
+ 803dd20:	400200a0 	.word	0x400200a0
+ 803dd24:	400200b8 	.word	0x400200b8
+ 803dd28:	40020410 	.word	0x40020410
+ 803dd2c:	40020428 	.word	0x40020428
+ 803dd30:	40020440 	.word	0x40020440
+ 803dd34:	40020458 	.word	0x40020458
+ 803dd38:	40020470 	.word	0x40020470
+ 803dd3c:	40020488 	.word	0x40020488
+ 803dd40:	400204a0 	.word	0x400204a0
+ 803dd44:	400204b8 	.word	0x400204b8
+    else
+    {
+      /* DMA mode not enabled */
+      /* Check received length : If all expected data are received, do nothing.
+         Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
+      uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
+ 803dd48:	687b      	ldr	r3, [r7, #4]
+ 803dd4a:	f8b3 205c 	ldrh.w	r2, [r3, #92]	@ 0x5c
+ 803dd4e:	687b      	ldr	r3, [r7, #4]
+ 803dd50:	f8b3 305e 	ldrh.w	r3, [r3, #94]	@ 0x5e
+ 803dd54:	b29b      	uxth	r3, r3
+ 803dd56:	1ad3      	subs	r3, r2, r3
+ 803dd58:	f8a7 30ce 	strh.w	r3, [r7, #206]	@ 0xce
+      if ((huart->RxXferCount > 0U)
+ 803dd5c:	687b      	ldr	r3, [r7, #4]
+ 803dd5e:	f8b3 305e 	ldrh.w	r3, [r3, #94]	@ 0x5e
+ 803dd62:	b29b      	uxth	r3, r3
+ 803dd64:	2b00      	cmp	r3, #0
+ 803dd66:	f000 80cf 	beq.w	803df08 <HAL_UART_IRQHandler+0x764>
+          && (nb_rx_data > 0U))
+ 803dd6a:	f8b7 30ce 	ldrh.w	r3, [r7, #206]	@ 0xce
+ 803dd6e:	2b00      	cmp	r3, #0
+ 803dd70:	f000 80ca 	beq.w	803df08 <HAL_UART_IRQHandler+0x764>
+      {
+        /* Disable the UART Parity Error Interrupt and RXNE interrupts */
+        ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+ 803dd74:	687b      	ldr	r3, [r7, #4]
+ 803dd76:	681b      	ldr	r3, [r3, #0]
+ 803dd78:	63bb      	str	r3, [r7, #56]	@ 0x38
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ 803dd7a:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 803dd7c:	e853 3f00 	ldrex	r3, [r3]
+ 803dd80:	637b      	str	r3, [r7, #52]	@ 0x34
+   return(result);
+ 803dd82:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
+ 803dd84:	f423 7390 	bic.w	r3, r3, #288	@ 0x120
+ 803dd88:	f8c7 30c8 	str.w	r3, [r7, #200]	@ 0xc8
+ 803dd8c:	687b      	ldr	r3, [r7, #4]
+ 803dd8e:	681b      	ldr	r3, [r3, #0]
+ 803dd90:	461a      	mov	r2, r3
+ 803dd92:	f8d7 30c8 	ldr.w	r3, [r7, #200]	@ 0xc8
+ 803dd96:	647b      	str	r3, [r7, #68]	@ 0x44
+ 803dd98:	643a      	str	r2, [r7, #64]	@ 0x40
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ 803dd9a:	6c39      	ldr	r1, [r7, #64]	@ 0x40
+ 803dd9c:	6c7a      	ldr	r2, [r7, #68]	@ 0x44
+ 803dd9e:	e841 2300 	strex	r3, r2, [r1]
+ 803dda2:	63fb      	str	r3, [r7, #60]	@ 0x3c
+   return(result);
+ 803dda4:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
+ 803dda6:	2b00      	cmp	r3, #0
+ 803dda8:	d1e4      	bne.n	803dd74 <HAL_UART_IRQHandler+0x5d0>
+
+        /* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */
+        ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+ 803ddaa:	687b      	ldr	r3, [r7, #4]
+ 803ddac:	681b      	ldr	r3, [r3, #0]
+ 803ddae:	3308      	adds	r3, #8
+ 803ddb0:	627b      	str	r3, [r7, #36]	@ 0x24
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ 803ddb2:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 803ddb4:	e853 3f00 	ldrex	r3, [r3]
+ 803ddb8:	623b      	str	r3, [r7, #32]
+   return(result);
+ 803ddba:	6a3a      	ldr	r2, [r7, #32]
+ 803ddbc:	4b55      	ldr	r3, [pc, #340]	@ (803df14 <HAL_UART_IRQHandler+0x770>)
+ 803ddbe:	4013      	ands	r3, r2
+ 803ddc0:	f8c7 30c4 	str.w	r3, [r7, #196]	@ 0xc4
+ 803ddc4:	687b      	ldr	r3, [r7, #4]
+ 803ddc6:	681b      	ldr	r3, [r3, #0]
+ 803ddc8:	3308      	adds	r3, #8
+ 803ddca:	f8d7 20c4 	ldr.w	r2, [r7, #196]	@ 0xc4
+ 803ddce:	633a      	str	r2, [r7, #48]	@ 0x30
+ 803ddd0:	62fb      	str	r3, [r7, #44]	@ 0x2c
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ 803ddd2:	6af9      	ldr	r1, [r7, #44]	@ 0x2c
+ 803ddd4:	6b3a      	ldr	r2, [r7, #48]	@ 0x30
+ 803ddd6:	e841 2300 	strex	r3, r2, [r1]
+ 803ddda:	62bb      	str	r3, [r7, #40]	@ 0x28
+   return(result);
+ 803dddc:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 803ddde:	2b00      	cmp	r3, #0
+ 803dde0:	d1e3      	bne.n	803ddaa <HAL_UART_IRQHandler+0x606>
+
+        /* Rx process is completed, restore huart->RxState to Ready */
+        huart->RxState = HAL_UART_STATE_READY;
+ 803dde2:	687b      	ldr	r3, [r7, #4]
+ 803dde4:	2220      	movs	r2, #32
+ 803dde6:	f8c3 208c 	str.w	r2, [r3, #140]	@ 0x8c
+        huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ 803ddea:	687b      	ldr	r3, [r7, #4]
+ 803ddec:	2200      	movs	r2, #0
+ 803ddee:	66da      	str	r2, [r3, #108]	@ 0x6c
+
+        /* Clear RxISR function pointer */
+        huart->RxISR = NULL;
+ 803ddf0:	687b      	ldr	r3, [r7, #4]
+ 803ddf2:	2200      	movs	r2, #0
+ 803ddf4:	675a      	str	r2, [r3, #116]	@ 0x74
+
+        ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ 803ddf6:	687b      	ldr	r3, [r7, #4]
+ 803ddf8:	681b      	ldr	r3, [r3, #0]
+ 803ddfa:	613b      	str	r3, [r7, #16]
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ 803ddfc:	693b      	ldr	r3, [r7, #16]
+ 803ddfe:	e853 3f00 	ldrex	r3, [r3]
+ 803de02:	60fb      	str	r3, [r7, #12]
+   return(result);
+ 803de04:	68fb      	ldr	r3, [r7, #12]
+ 803de06:	f023 0310 	bic.w	r3, r3, #16
+ 803de0a:	f8c7 30c0 	str.w	r3, [r7, #192]	@ 0xc0
+ 803de0e:	687b      	ldr	r3, [r7, #4]
+ 803de10:	681b      	ldr	r3, [r3, #0]
+ 803de12:	461a      	mov	r2, r3
+ 803de14:	f8d7 30c0 	ldr.w	r3, [r7, #192]	@ 0xc0
+ 803de18:	61fb      	str	r3, [r7, #28]
+ 803de1a:	61ba      	str	r2, [r7, #24]
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ 803de1c:	69b9      	ldr	r1, [r7, #24]
+ 803de1e:	69fa      	ldr	r2, [r7, #28]
+ 803de20:	e841 2300 	strex	r3, r2, [r1]
+ 803de24:	617b      	str	r3, [r7, #20]
+   return(result);
+ 803de26:	697b      	ldr	r3, [r7, #20]
+ 803de28:	2b00      	cmp	r3, #0
+ 803de2a:	d1e4      	bne.n	803ddf6 <HAL_UART_IRQHandler+0x652>
+
+        /* Initialize type of RxEvent that correspond to RxEvent callback execution;
+           In this case, Rx Event type is Idle Event */
+        huart->RxEventType = HAL_UART_RXEVENT_IDLE;
+ 803de2c:	687b      	ldr	r3, [r7, #4]
+ 803de2e:	2202      	movs	r2, #2
+ 803de30:	671a      	str	r2, [r3, #112]	@ 0x70
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+        /*Call registered Rx complete callback*/
+        huart->RxEventCallback(huart, nb_rx_data);
+#else
+        /*Call legacy weak Rx Event callback*/
+        HAL_UARTEx_RxEventCallback(huart, nb_rx_data);
+ 803de32:	f8b7 30ce 	ldrh.w	r3, [r7, #206]	@ 0xce
+ 803de36:	4619      	mov	r1, r3
+ 803de38:	6878      	ldr	r0, [r7, #4]
+ 803de3a:	f000 f881 	bl	803df40 <HAL_UARTEx_RxEventCallback>
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+      }
+      return;
+ 803de3e:	e063      	b.n	803df08 <HAL_UART_IRQHandler+0x764>
+    }
+  }
+
+  /* UART wakeup from Stop mode interrupt occurred ---------------------------*/
+  if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U))
+ 803de40:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
+ 803de44:	f403 1380 	and.w	r3, r3, #1048576	@ 0x100000
+ 803de48:	2b00      	cmp	r3, #0
+ 803de4a:	d00e      	beq.n	803de6a <HAL_UART_IRQHandler+0x6c6>
+ 803de4c:	f8d7 30dc 	ldr.w	r3, [r7, #220]	@ 0xdc
+ 803de50:	f403 0380 	and.w	r3, r3, #4194304	@ 0x400000
+ 803de54:	2b00      	cmp	r3, #0
+ 803de56:	d008      	beq.n	803de6a <HAL_UART_IRQHandler+0x6c6>
+  {
+    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF);
+ 803de58:	687b      	ldr	r3, [r7, #4]
+ 803de5a:	681b      	ldr	r3, [r3, #0]
+ 803de5c:	f44f 1280 	mov.w	r2, #1048576	@ 0x100000
+ 803de60:	621a      	str	r2, [r3, #32]
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /* Call registered Wakeup Callback */
+    huart->WakeupCallback(huart);
+#else
+    /* Call legacy weak Wakeup Callback */
+    HAL_UARTEx_WakeupCallback(huart);
+ 803de62:	6878      	ldr	r0, [r7, #4]
+ 803de64:	f001 ff5a 	bl	803fd1c <HAL_UARTEx_WakeupCallback>
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+    return;
+ 803de68:	e051      	b.n	803df0e <HAL_UART_IRQHandler+0x76a>
+  }
+
+  /* UART in mode Transmitter ------------------------------------------------*/
+  if (((isrflags & USART_ISR_TXE_TXFNF) != 0U)
+ 803de6a:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
+ 803de6e:	f003 0380 	and.w	r3, r3, #128	@ 0x80
+ 803de72:	2b00      	cmp	r3, #0
+ 803de74:	d014      	beq.n	803dea0 <HAL_UART_IRQHandler+0x6fc>
+      && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)
+ 803de76:	f8d7 30e0 	ldr.w	r3, [r7, #224]	@ 0xe0
+ 803de7a:	f003 0380 	and.w	r3, r3, #128	@ 0x80
+ 803de7e:	2b00      	cmp	r3, #0
+ 803de80:	d105      	bne.n	803de8e <HAL_UART_IRQHandler+0x6ea>
+          || ((cr3its & USART_CR3_TXFTIE) != 0U)))
+ 803de82:	f8d7 30dc 	ldr.w	r3, [r7, #220]	@ 0xdc
+ 803de86:	f403 0300 	and.w	r3, r3, #8388608	@ 0x800000
+ 803de8a:	2b00      	cmp	r3, #0
+ 803de8c:	d008      	beq.n	803dea0 <HAL_UART_IRQHandler+0x6fc>
+  {
+    if (huart->TxISR != NULL)
+ 803de8e:	687b      	ldr	r3, [r7, #4]
+ 803de90:	6f9b      	ldr	r3, [r3, #120]	@ 0x78
+ 803de92:	2b00      	cmp	r3, #0
+ 803de94:	d03a      	beq.n	803df0c <HAL_UART_IRQHandler+0x768>
+    {
+      huart->TxISR(huart);
+ 803de96:	687b      	ldr	r3, [r7, #4]
+ 803de98:	6f9b      	ldr	r3, [r3, #120]	@ 0x78
+ 803de9a:	6878      	ldr	r0, [r7, #4]
+ 803de9c:	4798      	blx	r3
+    }
+    return;
+ 803de9e:	e035      	b.n	803df0c <HAL_UART_IRQHandler+0x768>
+  }
+
+  /* UART in mode Transmitter (transmission end) -----------------------------*/
+  if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
+ 803dea0:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
+ 803dea4:	f003 0340 	and.w	r3, r3, #64	@ 0x40
+ 803dea8:	2b00      	cmp	r3, #0
+ 803deaa:	d009      	beq.n	803dec0 <HAL_UART_IRQHandler+0x71c>
+ 803deac:	f8d7 30e0 	ldr.w	r3, [r7, #224]	@ 0xe0
+ 803deb0:	f003 0340 	and.w	r3, r3, #64	@ 0x40
+ 803deb4:	2b00      	cmp	r3, #0
+ 803deb6:	d003      	beq.n	803dec0 <HAL_UART_IRQHandler+0x71c>
+  {
+    UART_EndTransmit_IT(huart);
+ 803deb8:	6878      	ldr	r0, [r7, #4]
+ 803deba:	f001 f9e8 	bl	803f28e <UART_EndTransmit_IT>
+    return;
+ 803debe:	e026      	b.n	803df0e <HAL_UART_IRQHandler+0x76a>
+  }
+
+  /* UART TX Fifo Empty occurred ----------------------------------------------*/
+  if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U))
+ 803dec0:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
+ 803dec4:	f403 0300 	and.w	r3, r3, #8388608	@ 0x800000
+ 803dec8:	2b00      	cmp	r3, #0
+ 803deca:	d009      	beq.n	803dee0 <HAL_UART_IRQHandler+0x73c>
+ 803decc:	f8d7 30e0 	ldr.w	r3, [r7, #224]	@ 0xe0
+ 803ded0:	f003 4380 	and.w	r3, r3, #1073741824	@ 0x40000000
+ 803ded4:	2b00      	cmp	r3, #0
+ 803ded6:	d003      	beq.n	803dee0 <HAL_UART_IRQHandler+0x73c>
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /* Call registered Tx Fifo Empty Callback */
+    huart->TxFifoEmptyCallback(huart);
+#else
+    /* Call legacy weak Tx Fifo Empty Callback */
+    HAL_UARTEx_TxFifoEmptyCallback(huart);
+ 803ded8:	6878      	ldr	r0, [r7, #4]
+ 803deda:	f001 ff33 	bl	803fd44 <HAL_UARTEx_TxFifoEmptyCallback>
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+    return;
+ 803dede:	e016      	b.n	803df0e <HAL_UART_IRQHandler+0x76a>
+  }
+
+  /* UART RX Fifo Full occurred ----------------------------------------------*/
+  if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U))
+ 803dee0:	f8d7 30e4 	ldr.w	r3, [r7, #228]	@ 0xe4
+ 803dee4:	f003 7380 	and.w	r3, r3, #16777216	@ 0x1000000
+ 803dee8:	2b00      	cmp	r3, #0
+ 803deea:	d010      	beq.n	803df0e <HAL_UART_IRQHandler+0x76a>
+ 803deec:	f8d7 30e0 	ldr.w	r3, [r7, #224]	@ 0xe0
+ 803def0:	2b00      	cmp	r3, #0
+ 803def2:	da0c      	bge.n	803df0e <HAL_UART_IRQHandler+0x76a>
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /* Call registered Rx Fifo Full Callback */
+    huart->RxFifoFullCallback(huart);
+#else
+    /* Call legacy weak Rx Fifo Full Callback */
+    HAL_UARTEx_RxFifoFullCallback(huart);
+ 803def4:	6878      	ldr	r0, [r7, #4]
+ 803def6:	f001 ff1b 	bl	803fd30 <HAL_UARTEx_RxFifoFullCallback>
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+    return;
+ 803defa:	e008      	b.n	803df0e <HAL_UART_IRQHandler+0x76a>
+      return;
+ 803defc:	bf00      	nop
+ 803defe:	e006      	b.n	803df0e <HAL_UART_IRQHandler+0x76a>
+    return;
+ 803df00:	bf00      	nop
+ 803df02:	e004      	b.n	803df0e <HAL_UART_IRQHandler+0x76a>
+      return;
+ 803df04:	bf00      	nop
+ 803df06:	e002      	b.n	803df0e <HAL_UART_IRQHandler+0x76a>
+      return;
+ 803df08:	bf00      	nop
+ 803df0a:	e000      	b.n	803df0e <HAL_UART_IRQHandler+0x76a>
+    return;
+ 803df0c:	bf00      	nop
+  }
+}
+ 803df0e:	37e8      	adds	r7, #232	@ 0xe8
+ 803df10:	46bd      	mov	sp, r7
+ 803df12:	bd80      	pop	{r7, pc}
+ 803df14:	effffffe 	.word	0xeffffffe
+
+0803df18 <HAL_UART_TxHalfCpltCallback>:
+  * @brief  Tx Half Transfer completed callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
+{
+ 803df18:	b480      	push	{r7}
+ 803df1a:	b083      	sub	sp, #12
+ 803df1c:	af00      	add	r7, sp, #0
+ 803df1e:	6078      	str	r0, [r7, #4]
+  UNUSED(huart);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_UART_TxHalfCpltCallback can be implemented in the user file.
+   */
+}
+ 803df20:	bf00      	nop
+ 803df22:	370c      	adds	r7, #12
+ 803df24:	46bd      	mov	sp, r7
+ 803df26:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 803df2a:	4770      	bx	lr
+
+0803df2c <HAL_UART_ErrorCallback>:
+  * @brief  UART error callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
+{
+ 803df2c:	b480      	push	{r7}
+ 803df2e:	b083      	sub	sp, #12
+ 803df30:	af00      	add	r7, sp, #0
+ 803df32:	6078      	str	r0, [r7, #4]
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_ErrorCallback can be implemented in the user file.
+   */
+}
+ 803df34:	bf00      	nop
+ 803df36:	370c      	adds	r7, #12
+ 803df38:	46bd      	mov	sp, r7
+ 803df3a:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 803df3e:	4770      	bx	lr
+
+0803df40 <HAL_UARTEx_RxEventCallback>:
+  * @param  Size  Number of data available in application reception buffer (indicates a position in
+  *               reception buffer until which, data are available)
+  * @retval None
+  */
+__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size)
+{
+ 803df40:	b480      	push	{r7}
+ 803df42:	b083      	sub	sp, #12
+ 803df44:	af00      	add	r7, sp, #0
+ 803df46:	6078      	str	r0, [r7, #4]
+ 803df48:	460b      	mov	r3, r1
+ 803df4a:	807b      	strh	r3, [r7, #2]
+  UNUSED(Size);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UARTEx_RxEventCallback can be implemented in the user file.
+   */
+}
+ 803df4c:	bf00      	nop
+ 803df4e:	370c      	adds	r7, #12
+ 803df50:	46bd      	mov	sp, r7
+ 803df52:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 803df56:	4770      	bx	lr
+
+0803df58 <UART_SetConfig>:
+  * @brief Configure the UART peripheral.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
+{
+ 803df58:	e92d 4fb0 	stmdb	sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
+ 803df5c:	b092      	sub	sp, #72	@ 0x48
+ 803df5e:	af00      	add	r7, sp, #0
+ 803df60:	6178      	str	r0, [r7, #20]
+  uint32_t tmpreg;
+  uint16_t brrtemp;
+  UART_ClockSourceTypeDef clocksource;
+  uint32_t usartdiv;
+  HAL_StatusTypeDef ret               = HAL_OK;
+ 803df62:	2300      	movs	r3, #0
+ 803df64:	f887 3042 	strb.w	r3, [r7, #66]	@ 0x42
+  *  the UART Word Length, Parity, Mode and oversampling:
+  *  set the M bits according to huart->Init.WordLength value
+  *  set PCE and PS bits according to huart->Init.Parity value
+  *  set TE and RE bits according to huart->Init.Mode value
+  *  set OVER8 bit according to huart->Init.OverSampling value */
+  tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
+ 803df68:	697b      	ldr	r3, [r7, #20]
+ 803df6a:	689a      	ldr	r2, [r3, #8]
+ 803df6c:	697b      	ldr	r3, [r7, #20]
+ 803df6e:	691b      	ldr	r3, [r3, #16]
+ 803df70:	431a      	orrs	r2, r3
+ 803df72:	697b      	ldr	r3, [r7, #20]
+ 803df74:	695b      	ldr	r3, [r3, #20]
+ 803df76:	431a      	orrs	r2, r3
+ 803df78:	697b      	ldr	r3, [r7, #20]
+ 803df7a:	69db      	ldr	r3, [r3, #28]
+ 803df7c:	4313      	orrs	r3, r2
+ 803df7e:	647b      	str	r3, [r7, #68]	@ 0x44
+  MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
+ 803df80:	697b      	ldr	r3, [r7, #20]
+ 803df82:	681b      	ldr	r3, [r3, #0]
+ 803df84:	681a      	ldr	r2, [r3, #0]
+ 803df86:	4bbe      	ldr	r3, [pc, #760]	@ (803e280 <UART_SetConfig+0x328>)
+ 803df88:	4013      	ands	r3, r2
+ 803df8a:	697a      	ldr	r2, [r7, #20]
+ 803df8c:	6812      	ldr	r2, [r2, #0]
+ 803df8e:	6c79      	ldr	r1, [r7, #68]	@ 0x44
+ 803df90:	430b      	orrs	r3, r1
+ 803df92:	6013      	str	r3, [r2, #0]
+
+  /*-------------------------- USART CR2 Configuration -----------------------*/
+  /* Configure the UART Stop Bits: Set STOP[13:12] bits according
+  * to huart->Init.StopBits value */
+  MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
+ 803df94:	697b      	ldr	r3, [r7, #20]
+ 803df96:	681b      	ldr	r3, [r3, #0]
+ 803df98:	685b      	ldr	r3, [r3, #4]
+ 803df9a:	f423 5140 	bic.w	r1, r3, #12288	@ 0x3000
+ 803df9e:	697b      	ldr	r3, [r7, #20]
+ 803dfa0:	68da      	ldr	r2, [r3, #12]
+ 803dfa2:	697b      	ldr	r3, [r7, #20]
+ 803dfa4:	681b      	ldr	r3, [r3, #0]
+ 803dfa6:	430a      	orrs	r2, r1
+ 803dfa8:	605a      	str	r2, [r3, #4]
+  /* Configure
+  * - UART HardWare Flow Control: set CTSE and RTSE bits according
+  *   to huart->Init.HwFlowCtl value
+  * - one-bit sampling method versus three samples' majority rule according
+  *   to huart->Init.OneBitSampling (not applicable to LPUART) */
+  tmpreg = (uint32_t)huart->Init.HwFlowCtl;
+ 803dfaa:	697b      	ldr	r3, [r7, #20]
+ 803dfac:	699b      	ldr	r3, [r3, #24]
+ 803dfae:	647b      	str	r3, [r7, #68]	@ 0x44
+
+  if (!(UART_INSTANCE_LOWPOWER(huart)))
+ 803dfb0:	697b      	ldr	r3, [r7, #20]
+ 803dfb2:	681b      	ldr	r3, [r3, #0]
+ 803dfb4:	4ab3      	ldr	r2, [pc, #716]	@ (803e284 <UART_SetConfig+0x32c>)
+ 803dfb6:	4293      	cmp	r3, r2
+ 803dfb8:	d004      	beq.n	803dfc4 <UART_SetConfig+0x6c>
+  {
+    tmpreg |= huart->Init.OneBitSampling;
+ 803dfba:	697b      	ldr	r3, [r7, #20]
+ 803dfbc:	6a1b      	ldr	r3, [r3, #32]
+ 803dfbe:	6c7a      	ldr	r2, [r7, #68]	@ 0x44
+ 803dfc0:	4313      	orrs	r3, r2
+ 803dfc2:	647b      	str	r3, [r7, #68]	@ 0x44
+  }
+  MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
+ 803dfc4:	697b      	ldr	r3, [r7, #20]
+ 803dfc6:	681b      	ldr	r3, [r3, #0]
+ 803dfc8:	689a      	ldr	r2, [r3, #8]
+ 803dfca:	4baf      	ldr	r3, [pc, #700]	@ (803e288 <UART_SetConfig+0x330>)
+ 803dfcc:	4013      	ands	r3, r2
+ 803dfce:	697a      	ldr	r2, [r7, #20]
+ 803dfd0:	6812      	ldr	r2, [r2, #0]
+ 803dfd2:	6c79      	ldr	r1, [r7, #68]	@ 0x44
+ 803dfd4:	430b      	orrs	r3, r1
+ 803dfd6:	6093      	str	r3, [r2, #8]
+
+  /*-------------------------- USART PRESC Configuration -----------------------*/
+  /* Configure
+  * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */
+  MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
+ 803dfd8:	697b      	ldr	r3, [r7, #20]
+ 803dfda:	681b      	ldr	r3, [r3, #0]
+ 803dfdc:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
+ 803dfde:	f023 010f 	bic.w	r1, r3, #15
+ 803dfe2:	697b      	ldr	r3, [r7, #20]
+ 803dfe4:	6a5a      	ldr	r2, [r3, #36]	@ 0x24
+ 803dfe6:	697b      	ldr	r3, [r7, #20]
+ 803dfe8:	681b      	ldr	r3, [r3, #0]
+ 803dfea:	430a      	orrs	r2, r1
+ 803dfec:	62da      	str	r2, [r3, #44]	@ 0x2c
+
+  /*-------------------------- USART BRR Configuration -----------------------*/
+  UART_GETCLOCKSOURCE(huart, clocksource);
+ 803dfee:	697b      	ldr	r3, [r7, #20]
+ 803dff0:	681b      	ldr	r3, [r3, #0]
+ 803dff2:	4aa6      	ldr	r2, [pc, #664]	@ (803e28c <UART_SetConfig+0x334>)
+ 803dff4:	4293      	cmp	r3, r2
+ 803dff6:	d177      	bne.n	803e0e8 <UART_SetConfig+0x190>
+ 803dff8:	4ba5      	ldr	r3, [pc, #660]	@ (803e290 <UART_SetConfig+0x338>)
+ 803dffa:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
+ 803dffc:	f003 0338 	and.w	r3, r3, #56	@ 0x38
+ 803e000:	2b28      	cmp	r3, #40	@ 0x28
+ 803e002:	d86d      	bhi.n	803e0e0 <UART_SetConfig+0x188>
+ 803e004:	a201      	add	r2, pc, #4	@ (adr r2, 803e00c <UART_SetConfig+0xb4>)
+ 803e006:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 803e00a:	bf00      	nop
+ 803e00c:	0803e0b1 	.word	0x0803e0b1
+ 803e010:	0803e0e1 	.word	0x0803e0e1
+ 803e014:	0803e0e1 	.word	0x0803e0e1
+ 803e018:	0803e0e1 	.word	0x0803e0e1
+ 803e01c:	0803e0e1 	.word	0x0803e0e1
+ 803e020:	0803e0e1 	.word	0x0803e0e1
+ 803e024:	0803e0e1 	.word	0x0803e0e1
+ 803e028:	0803e0e1 	.word	0x0803e0e1
+ 803e02c:	0803e0b9 	.word	0x0803e0b9
+ 803e030:	0803e0e1 	.word	0x0803e0e1
+ 803e034:	0803e0e1 	.word	0x0803e0e1
+ 803e038:	0803e0e1 	.word	0x0803e0e1
+ 803e03c:	0803e0e1 	.word	0x0803e0e1
+ 803e040:	0803e0e1 	.word	0x0803e0e1
+ 803e044:	0803e0e1 	.word	0x0803e0e1
+ 803e048:	0803e0e1 	.word	0x0803e0e1
+ 803e04c:	0803e0c1 	.word	0x0803e0c1
+ 803e050:	0803e0e1 	.word	0x0803e0e1
+ 803e054:	0803e0e1 	.word	0x0803e0e1
+ 803e058:	0803e0e1 	.word	0x0803e0e1
+ 803e05c:	0803e0e1 	.word	0x0803e0e1
+ 803e060:	0803e0e1 	.word	0x0803e0e1
+ 803e064:	0803e0e1 	.word	0x0803e0e1
+ 803e068:	0803e0e1 	.word	0x0803e0e1
+ 803e06c:	0803e0c9 	.word	0x0803e0c9
+ 803e070:	0803e0e1 	.word	0x0803e0e1
+ 803e074:	0803e0e1 	.word	0x0803e0e1
+ 803e078:	0803e0e1 	.word	0x0803e0e1
+ 803e07c:	0803e0e1 	.word	0x0803e0e1
+ 803e080:	0803e0e1 	.word	0x0803e0e1
+ 803e084:	0803e0e1 	.word	0x0803e0e1
+ 803e088:	0803e0e1 	.word	0x0803e0e1
+ 803e08c:	0803e0d1 	.word	0x0803e0d1
+ 803e090:	0803e0e1 	.word	0x0803e0e1
+ 803e094:	0803e0e1 	.word	0x0803e0e1
+ 803e098:	0803e0e1 	.word	0x0803e0e1
+ 803e09c:	0803e0e1 	.word	0x0803e0e1
+ 803e0a0:	0803e0e1 	.word	0x0803e0e1
+ 803e0a4:	0803e0e1 	.word	0x0803e0e1
+ 803e0a8:	0803e0e1 	.word	0x0803e0e1
+ 803e0ac:	0803e0d9 	.word	0x0803e0d9
+ 803e0b0:	2301      	movs	r3, #1
+ 803e0b2:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e0b6:	e222      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e0b8:	2304      	movs	r3, #4
+ 803e0ba:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e0be:	e21e      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e0c0:	2308      	movs	r3, #8
+ 803e0c2:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e0c6:	e21a      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e0c8:	2310      	movs	r3, #16
+ 803e0ca:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e0ce:	e216      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e0d0:	2320      	movs	r3, #32
+ 803e0d2:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e0d6:	e212      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e0d8:	2340      	movs	r3, #64	@ 0x40
+ 803e0da:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e0de:	e20e      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e0e0:	2380      	movs	r3, #128	@ 0x80
+ 803e0e2:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e0e6:	e20a      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e0e8:	697b      	ldr	r3, [r7, #20]
+ 803e0ea:	681b      	ldr	r3, [r3, #0]
+ 803e0ec:	4a69      	ldr	r2, [pc, #420]	@ (803e294 <UART_SetConfig+0x33c>)
+ 803e0ee:	4293      	cmp	r3, r2
+ 803e0f0:	d130      	bne.n	803e154 <UART_SetConfig+0x1fc>
+ 803e0f2:	4b67      	ldr	r3, [pc, #412]	@ (803e290 <UART_SetConfig+0x338>)
+ 803e0f4:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
+ 803e0f6:	f003 0307 	and.w	r3, r3, #7
+ 803e0fa:	2b05      	cmp	r3, #5
+ 803e0fc:	d826      	bhi.n	803e14c <UART_SetConfig+0x1f4>
+ 803e0fe:	a201      	add	r2, pc, #4	@ (adr r2, 803e104 <UART_SetConfig+0x1ac>)
+ 803e100:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 803e104:	0803e11d 	.word	0x0803e11d
+ 803e108:	0803e125 	.word	0x0803e125
+ 803e10c:	0803e12d 	.word	0x0803e12d
+ 803e110:	0803e135 	.word	0x0803e135
+ 803e114:	0803e13d 	.word	0x0803e13d
+ 803e118:	0803e145 	.word	0x0803e145
+ 803e11c:	2300      	movs	r3, #0
+ 803e11e:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e122:	e1ec      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e124:	2304      	movs	r3, #4
+ 803e126:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e12a:	e1e8      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e12c:	2308      	movs	r3, #8
+ 803e12e:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e132:	e1e4      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e134:	2310      	movs	r3, #16
+ 803e136:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e13a:	e1e0      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e13c:	2320      	movs	r3, #32
+ 803e13e:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e142:	e1dc      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e144:	2340      	movs	r3, #64	@ 0x40
+ 803e146:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e14a:	e1d8      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e14c:	2380      	movs	r3, #128	@ 0x80
+ 803e14e:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e152:	e1d4      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e154:	697b      	ldr	r3, [r7, #20]
+ 803e156:	681b      	ldr	r3, [r3, #0]
+ 803e158:	4a4f      	ldr	r2, [pc, #316]	@ (803e298 <UART_SetConfig+0x340>)
+ 803e15a:	4293      	cmp	r3, r2
+ 803e15c:	d130      	bne.n	803e1c0 <UART_SetConfig+0x268>
+ 803e15e:	4b4c      	ldr	r3, [pc, #304]	@ (803e290 <UART_SetConfig+0x338>)
+ 803e160:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
+ 803e162:	f003 0307 	and.w	r3, r3, #7
+ 803e166:	2b05      	cmp	r3, #5
+ 803e168:	d826      	bhi.n	803e1b8 <UART_SetConfig+0x260>
+ 803e16a:	a201      	add	r2, pc, #4	@ (adr r2, 803e170 <UART_SetConfig+0x218>)
+ 803e16c:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 803e170:	0803e189 	.word	0x0803e189
+ 803e174:	0803e191 	.word	0x0803e191
+ 803e178:	0803e199 	.word	0x0803e199
+ 803e17c:	0803e1a1 	.word	0x0803e1a1
+ 803e180:	0803e1a9 	.word	0x0803e1a9
+ 803e184:	0803e1b1 	.word	0x0803e1b1
+ 803e188:	2300      	movs	r3, #0
+ 803e18a:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e18e:	e1b6      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e190:	2304      	movs	r3, #4
+ 803e192:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e196:	e1b2      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e198:	2308      	movs	r3, #8
+ 803e19a:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e19e:	e1ae      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e1a0:	2310      	movs	r3, #16
+ 803e1a2:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e1a6:	e1aa      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e1a8:	2320      	movs	r3, #32
+ 803e1aa:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e1ae:	e1a6      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e1b0:	2340      	movs	r3, #64	@ 0x40
+ 803e1b2:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e1b6:	e1a2      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e1b8:	2380      	movs	r3, #128	@ 0x80
+ 803e1ba:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e1be:	e19e      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e1c0:	697b      	ldr	r3, [r7, #20]
+ 803e1c2:	681b      	ldr	r3, [r3, #0]
+ 803e1c4:	4a35      	ldr	r2, [pc, #212]	@ (803e29c <UART_SetConfig+0x344>)
+ 803e1c6:	4293      	cmp	r3, r2
+ 803e1c8:	d130      	bne.n	803e22c <UART_SetConfig+0x2d4>
+ 803e1ca:	4b31      	ldr	r3, [pc, #196]	@ (803e290 <UART_SetConfig+0x338>)
+ 803e1cc:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
+ 803e1ce:	f003 0307 	and.w	r3, r3, #7
+ 803e1d2:	2b05      	cmp	r3, #5
+ 803e1d4:	d826      	bhi.n	803e224 <UART_SetConfig+0x2cc>
+ 803e1d6:	a201      	add	r2, pc, #4	@ (adr r2, 803e1dc <UART_SetConfig+0x284>)
+ 803e1d8:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 803e1dc:	0803e1f5 	.word	0x0803e1f5
+ 803e1e0:	0803e1fd 	.word	0x0803e1fd
+ 803e1e4:	0803e205 	.word	0x0803e205
+ 803e1e8:	0803e20d 	.word	0x0803e20d
+ 803e1ec:	0803e215 	.word	0x0803e215
+ 803e1f0:	0803e21d 	.word	0x0803e21d
+ 803e1f4:	2300      	movs	r3, #0
+ 803e1f6:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e1fa:	e180      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e1fc:	2304      	movs	r3, #4
+ 803e1fe:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e202:	e17c      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e204:	2308      	movs	r3, #8
+ 803e206:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e20a:	e178      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e20c:	2310      	movs	r3, #16
+ 803e20e:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e212:	e174      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e214:	2320      	movs	r3, #32
+ 803e216:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e21a:	e170      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e21c:	2340      	movs	r3, #64	@ 0x40
+ 803e21e:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e222:	e16c      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e224:	2380      	movs	r3, #128	@ 0x80
+ 803e226:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e22a:	e168      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e22c:	697b      	ldr	r3, [r7, #20]
+ 803e22e:	681b      	ldr	r3, [r3, #0]
+ 803e230:	4a1b      	ldr	r2, [pc, #108]	@ (803e2a0 <UART_SetConfig+0x348>)
+ 803e232:	4293      	cmp	r3, r2
+ 803e234:	d142      	bne.n	803e2bc <UART_SetConfig+0x364>
+ 803e236:	4b16      	ldr	r3, [pc, #88]	@ (803e290 <UART_SetConfig+0x338>)
+ 803e238:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
+ 803e23a:	f003 0307 	and.w	r3, r3, #7
+ 803e23e:	2b05      	cmp	r3, #5
+ 803e240:	d838      	bhi.n	803e2b4 <UART_SetConfig+0x35c>
+ 803e242:	a201      	add	r2, pc, #4	@ (adr r2, 803e248 <UART_SetConfig+0x2f0>)
+ 803e244:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 803e248:	0803e261 	.word	0x0803e261
+ 803e24c:	0803e269 	.word	0x0803e269
+ 803e250:	0803e271 	.word	0x0803e271
+ 803e254:	0803e279 	.word	0x0803e279
+ 803e258:	0803e2a5 	.word	0x0803e2a5
+ 803e25c:	0803e2ad 	.word	0x0803e2ad
+ 803e260:	2300      	movs	r3, #0
+ 803e262:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e266:	e14a      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e268:	2304      	movs	r3, #4
+ 803e26a:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e26e:	e146      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e270:	2308      	movs	r3, #8
+ 803e272:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e276:	e142      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e278:	2310      	movs	r3, #16
+ 803e27a:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e27e:	e13e      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e280:	cfff69f3 	.word	0xcfff69f3
+ 803e284:	58000c00 	.word	0x58000c00
+ 803e288:	11fff4ff 	.word	0x11fff4ff
+ 803e28c:	40011000 	.word	0x40011000
+ 803e290:	58024400 	.word	0x58024400
+ 803e294:	40004400 	.word	0x40004400
+ 803e298:	40004800 	.word	0x40004800
+ 803e29c:	40004c00 	.word	0x40004c00
+ 803e2a0:	40005000 	.word	0x40005000
+ 803e2a4:	2320      	movs	r3, #32
+ 803e2a6:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e2aa:	e128      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e2ac:	2340      	movs	r3, #64	@ 0x40
+ 803e2ae:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e2b2:	e124      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e2b4:	2380      	movs	r3, #128	@ 0x80
+ 803e2b6:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e2ba:	e120      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e2bc:	697b      	ldr	r3, [r7, #20]
+ 803e2be:	681b      	ldr	r3, [r3, #0]
+ 803e2c0:	4acb      	ldr	r2, [pc, #812]	@ (803e5f0 <UART_SetConfig+0x698>)
+ 803e2c2:	4293      	cmp	r3, r2
+ 803e2c4:	d176      	bne.n	803e3b4 <UART_SetConfig+0x45c>
+ 803e2c6:	4bcb      	ldr	r3, [pc, #812]	@ (803e5f4 <UART_SetConfig+0x69c>)
+ 803e2c8:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
+ 803e2ca:	f003 0338 	and.w	r3, r3, #56	@ 0x38
+ 803e2ce:	2b28      	cmp	r3, #40	@ 0x28
+ 803e2d0:	d86c      	bhi.n	803e3ac <UART_SetConfig+0x454>
+ 803e2d2:	a201      	add	r2, pc, #4	@ (adr r2, 803e2d8 <UART_SetConfig+0x380>)
+ 803e2d4:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 803e2d8:	0803e37d 	.word	0x0803e37d
+ 803e2dc:	0803e3ad 	.word	0x0803e3ad
+ 803e2e0:	0803e3ad 	.word	0x0803e3ad
+ 803e2e4:	0803e3ad 	.word	0x0803e3ad
+ 803e2e8:	0803e3ad 	.word	0x0803e3ad
+ 803e2ec:	0803e3ad 	.word	0x0803e3ad
+ 803e2f0:	0803e3ad 	.word	0x0803e3ad
+ 803e2f4:	0803e3ad 	.word	0x0803e3ad
+ 803e2f8:	0803e385 	.word	0x0803e385
+ 803e2fc:	0803e3ad 	.word	0x0803e3ad
+ 803e300:	0803e3ad 	.word	0x0803e3ad
+ 803e304:	0803e3ad 	.word	0x0803e3ad
+ 803e308:	0803e3ad 	.word	0x0803e3ad
+ 803e30c:	0803e3ad 	.word	0x0803e3ad
+ 803e310:	0803e3ad 	.word	0x0803e3ad
+ 803e314:	0803e3ad 	.word	0x0803e3ad
+ 803e318:	0803e38d 	.word	0x0803e38d
+ 803e31c:	0803e3ad 	.word	0x0803e3ad
+ 803e320:	0803e3ad 	.word	0x0803e3ad
+ 803e324:	0803e3ad 	.word	0x0803e3ad
+ 803e328:	0803e3ad 	.word	0x0803e3ad
+ 803e32c:	0803e3ad 	.word	0x0803e3ad
+ 803e330:	0803e3ad 	.word	0x0803e3ad
+ 803e334:	0803e3ad 	.word	0x0803e3ad
+ 803e338:	0803e395 	.word	0x0803e395
+ 803e33c:	0803e3ad 	.word	0x0803e3ad
+ 803e340:	0803e3ad 	.word	0x0803e3ad
+ 803e344:	0803e3ad 	.word	0x0803e3ad
+ 803e348:	0803e3ad 	.word	0x0803e3ad
+ 803e34c:	0803e3ad 	.word	0x0803e3ad
+ 803e350:	0803e3ad 	.word	0x0803e3ad
+ 803e354:	0803e3ad 	.word	0x0803e3ad
+ 803e358:	0803e39d 	.word	0x0803e39d
+ 803e35c:	0803e3ad 	.word	0x0803e3ad
+ 803e360:	0803e3ad 	.word	0x0803e3ad
+ 803e364:	0803e3ad 	.word	0x0803e3ad
+ 803e368:	0803e3ad 	.word	0x0803e3ad
+ 803e36c:	0803e3ad 	.word	0x0803e3ad
+ 803e370:	0803e3ad 	.word	0x0803e3ad
+ 803e374:	0803e3ad 	.word	0x0803e3ad
+ 803e378:	0803e3a5 	.word	0x0803e3a5
+ 803e37c:	2301      	movs	r3, #1
+ 803e37e:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e382:	e0bc      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e384:	2304      	movs	r3, #4
+ 803e386:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e38a:	e0b8      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e38c:	2308      	movs	r3, #8
+ 803e38e:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e392:	e0b4      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e394:	2310      	movs	r3, #16
+ 803e396:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e39a:	e0b0      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e39c:	2320      	movs	r3, #32
+ 803e39e:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e3a2:	e0ac      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e3a4:	2340      	movs	r3, #64	@ 0x40
+ 803e3a6:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e3aa:	e0a8      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e3ac:	2380      	movs	r3, #128	@ 0x80
+ 803e3ae:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e3b2:	e0a4      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e3b4:	697b      	ldr	r3, [r7, #20]
+ 803e3b6:	681b      	ldr	r3, [r3, #0]
+ 803e3b8:	4a8f      	ldr	r2, [pc, #572]	@ (803e5f8 <UART_SetConfig+0x6a0>)
+ 803e3ba:	4293      	cmp	r3, r2
+ 803e3bc:	d130      	bne.n	803e420 <UART_SetConfig+0x4c8>
+ 803e3be:	4b8d      	ldr	r3, [pc, #564]	@ (803e5f4 <UART_SetConfig+0x69c>)
+ 803e3c0:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
+ 803e3c2:	f003 0307 	and.w	r3, r3, #7
+ 803e3c6:	2b05      	cmp	r3, #5
+ 803e3c8:	d826      	bhi.n	803e418 <UART_SetConfig+0x4c0>
+ 803e3ca:	a201      	add	r2, pc, #4	@ (adr r2, 803e3d0 <UART_SetConfig+0x478>)
+ 803e3cc:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 803e3d0:	0803e3e9 	.word	0x0803e3e9
+ 803e3d4:	0803e3f1 	.word	0x0803e3f1
+ 803e3d8:	0803e3f9 	.word	0x0803e3f9
+ 803e3dc:	0803e401 	.word	0x0803e401
+ 803e3e0:	0803e409 	.word	0x0803e409
+ 803e3e4:	0803e411 	.word	0x0803e411
+ 803e3e8:	2300      	movs	r3, #0
+ 803e3ea:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e3ee:	e086      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e3f0:	2304      	movs	r3, #4
+ 803e3f2:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e3f6:	e082      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e3f8:	2308      	movs	r3, #8
+ 803e3fa:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e3fe:	e07e      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e400:	2310      	movs	r3, #16
+ 803e402:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e406:	e07a      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e408:	2320      	movs	r3, #32
+ 803e40a:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e40e:	e076      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e410:	2340      	movs	r3, #64	@ 0x40
+ 803e412:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e416:	e072      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e418:	2380      	movs	r3, #128	@ 0x80
+ 803e41a:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e41e:	e06e      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e420:	697b      	ldr	r3, [r7, #20]
+ 803e422:	681b      	ldr	r3, [r3, #0]
+ 803e424:	4a75      	ldr	r2, [pc, #468]	@ (803e5fc <UART_SetConfig+0x6a4>)
+ 803e426:	4293      	cmp	r3, r2
+ 803e428:	d130      	bne.n	803e48c <UART_SetConfig+0x534>
+ 803e42a:	4b72      	ldr	r3, [pc, #456]	@ (803e5f4 <UART_SetConfig+0x69c>)
+ 803e42c:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
+ 803e42e:	f003 0307 	and.w	r3, r3, #7
+ 803e432:	2b05      	cmp	r3, #5
+ 803e434:	d826      	bhi.n	803e484 <UART_SetConfig+0x52c>
+ 803e436:	a201      	add	r2, pc, #4	@ (adr r2, 803e43c <UART_SetConfig+0x4e4>)
+ 803e438:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 803e43c:	0803e455 	.word	0x0803e455
+ 803e440:	0803e45d 	.word	0x0803e45d
+ 803e444:	0803e465 	.word	0x0803e465
+ 803e448:	0803e46d 	.word	0x0803e46d
+ 803e44c:	0803e475 	.word	0x0803e475
+ 803e450:	0803e47d 	.word	0x0803e47d
+ 803e454:	2300      	movs	r3, #0
+ 803e456:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e45a:	e050      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e45c:	2304      	movs	r3, #4
+ 803e45e:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e462:	e04c      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e464:	2308      	movs	r3, #8
+ 803e466:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e46a:	e048      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e46c:	2310      	movs	r3, #16
+ 803e46e:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e472:	e044      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e474:	2320      	movs	r3, #32
+ 803e476:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e47a:	e040      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e47c:	2340      	movs	r3, #64	@ 0x40
+ 803e47e:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e482:	e03c      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e484:	2380      	movs	r3, #128	@ 0x80
+ 803e486:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e48a:	e038      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e48c:	697b      	ldr	r3, [r7, #20]
+ 803e48e:	681b      	ldr	r3, [r3, #0]
+ 803e490:	4a5b      	ldr	r2, [pc, #364]	@ (803e600 <UART_SetConfig+0x6a8>)
+ 803e492:	4293      	cmp	r3, r2
+ 803e494:	d130      	bne.n	803e4f8 <UART_SetConfig+0x5a0>
+ 803e496:	4b57      	ldr	r3, [pc, #348]	@ (803e5f4 <UART_SetConfig+0x69c>)
+ 803e498:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
+ 803e49a:	f003 0307 	and.w	r3, r3, #7
+ 803e49e:	2b05      	cmp	r3, #5
+ 803e4a0:	d826      	bhi.n	803e4f0 <UART_SetConfig+0x598>
+ 803e4a2:	a201      	add	r2, pc, #4	@ (adr r2, 803e4a8 <UART_SetConfig+0x550>)
+ 803e4a4:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 803e4a8:	0803e4c1 	.word	0x0803e4c1
+ 803e4ac:	0803e4c9 	.word	0x0803e4c9
+ 803e4b0:	0803e4d1 	.word	0x0803e4d1
+ 803e4b4:	0803e4d9 	.word	0x0803e4d9
+ 803e4b8:	0803e4e1 	.word	0x0803e4e1
+ 803e4bc:	0803e4e9 	.word	0x0803e4e9
+ 803e4c0:	2302      	movs	r3, #2
+ 803e4c2:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e4c6:	e01a      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e4c8:	2304      	movs	r3, #4
+ 803e4ca:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e4ce:	e016      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e4d0:	2308      	movs	r3, #8
+ 803e4d2:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e4d6:	e012      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e4d8:	2310      	movs	r3, #16
+ 803e4da:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e4de:	e00e      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e4e0:	2320      	movs	r3, #32
+ 803e4e2:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e4e6:	e00a      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e4e8:	2340      	movs	r3, #64	@ 0x40
+ 803e4ea:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e4ee:	e006      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e4f0:	2380      	movs	r3, #128	@ 0x80
+ 803e4f2:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+ 803e4f6:	e002      	b.n	803e4fe <UART_SetConfig+0x5a6>
+ 803e4f8:	2380      	movs	r3, #128	@ 0x80
+ 803e4fa:	f887 3043 	strb.w	r3, [r7, #67]	@ 0x43
+
+  /* Check LPUART instance */
+  if (UART_INSTANCE_LOWPOWER(huart))
+ 803e4fe:	697b      	ldr	r3, [r7, #20]
+ 803e500:	681b      	ldr	r3, [r3, #0]
+ 803e502:	4a3f      	ldr	r2, [pc, #252]	@ (803e600 <UART_SetConfig+0x6a8>)
+ 803e504:	4293      	cmp	r3, r2
+ 803e506:	f040 80f8 	bne.w	803e6fa <UART_SetConfig+0x7a2>
+  {
+    /* Retrieve frequency clock */
+    switch (clocksource)
+ 803e50a:	f897 3043 	ldrb.w	r3, [r7, #67]	@ 0x43
+ 803e50e:	2b20      	cmp	r3, #32
+ 803e510:	dc46      	bgt.n	803e5a0 <UART_SetConfig+0x648>
+ 803e512:	2b02      	cmp	r3, #2
+ 803e514:	f2c0 8082 	blt.w	803e61c <UART_SetConfig+0x6c4>
+ 803e518:	3b02      	subs	r3, #2
+ 803e51a:	2b1e      	cmp	r3, #30
+ 803e51c:	d87e      	bhi.n	803e61c <UART_SetConfig+0x6c4>
+ 803e51e:	a201      	add	r2, pc, #4	@ (adr r2, 803e524 <UART_SetConfig+0x5cc>)
+ 803e520:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 803e524:	0803e5a7 	.word	0x0803e5a7
+ 803e528:	0803e61d 	.word	0x0803e61d
+ 803e52c:	0803e5af 	.word	0x0803e5af
+ 803e530:	0803e61d 	.word	0x0803e61d
+ 803e534:	0803e61d 	.word	0x0803e61d
+ 803e538:	0803e61d 	.word	0x0803e61d
+ 803e53c:	0803e5bf 	.word	0x0803e5bf
+ 803e540:	0803e61d 	.word	0x0803e61d
+ 803e544:	0803e61d 	.word	0x0803e61d
+ 803e548:	0803e61d 	.word	0x0803e61d
+ 803e54c:	0803e61d 	.word	0x0803e61d
+ 803e550:	0803e61d 	.word	0x0803e61d
+ 803e554:	0803e61d 	.word	0x0803e61d
+ 803e558:	0803e61d 	.word	0x0803e61d
+ 803e55c:	0803e5cf 	.word	0x0803e5cf
+ 803e560:	0803e61d 	.word	0x0803e61d
+ 803e564:	0803e61d 	.word	0x0803e61d
+ 803e568:	0803e61d 	.word	0x0803e61d
+ 803e56c:	0803e61d 	.word	0x0803e61d
+ 803e570:	0803e61d 	.word	0x0803e61d
+ 803e574:	0803e61d 	.word	0x0803e61d
+ 803e578:	0803e61d 	.word	0x0803e61d
+ 803e57c:	0803e61d 	.word	0x0803e61d
+ 803e580:	0803e61d 	.word	0x0803e61d
+ 803e584:	0803e61d 	.word	0x0803e61d
+ 803e588:	0803e61d 	.word	0x0803e61d
+ 803e58c:	0803e61d 	.word	0x0803e61d
+ 803e590:	0803e61d 	.word	0x0803e61d
+ 803e594:	0803e61d 	.word	0x0803e61d
+ 803e598:	0803e61d 	.word	0x0803e61d
+ 803e59c:	0803e60f 	.word	0x0803e60f
+ 803e5a0:	2b40      	cmp	r3, #64	@ 0x40
+ 803e5a2:	d037      	beq.n	803e614 <UART_SetConfig+0x6bc>
+ 803e5a4:	e03a      	b.n	803e61c <UART_SetConfig+0x6c4>
+    {
+      case UART_CLOCKSOURCE_D3PCLK1:
+        pclk = HAL_RCCEx_GetD3PCLK1Freq();
+ 803e5a6:	f7fd fcf7 	bl	803bf98 <HAL_RCCEx_GetD3PCLK1Freq>
+ 803e5aa:	63f8      	str	r0, [r7, #60]	@ 0x3c
+        break;
+ 803e5ac:	e03c      	b.n	803e628 <UART_SetConfig+0x6d0>
+      case UART_CLOCKSOURCE_PLL2:
+        HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+ 803e5ae:	f107 0324 	add.w	r3, r7, #36	@ 0x24
+ 803e5b2:	4618      	mov	r0, r3
+ 803e5b4:	f7fd fd06 	bl	803bfc4 <HAL_RCCEx_GetPLL2ClockFreq>
+        pclk = pll2_clocks.PLL2_Q_Frequency;
+ 803e5b8:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 803e5ba:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803e5bc:	e034      	b.n	803e628 <UART_SetConfig+0x6d0>
+      case UART_CLOCKSOURCE_PLL3:
+        HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+ 803e5be:	f107 0318 	add.w	r3, r7, #24
+ 803e5c2:	4618      	mov	r0, r3
+ 803e5c4:	f7fd fe52 	bl	803c26c <HAL_RCCEx_GetPLL3ClockFreq>
+        pclk = pll3_clocks.PLL3_Q_Frequency;
+ 803e5c8:	69fb      	ldr	r3, [r7, #28]
+ 803e5ca:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803e5cc:	e02c      	b.n	803e628 <UART_SetConfig+0x6d0>
+      case UART_CLOCKSOURCE_HSI:
+        if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
+ 803e5ce:	4b09      	ldr	r3, [pc, #36]	@ (803e5f4 <UART_SetConfig+0x69c>)
+ 803e5d0:	681b      	ldr	r3, [r3, #0]
+ 803e5d2:	f003 0320 	and.w	r3, r3, #32
+ 803e5d6:	2b00      	cmp	r3, #0
+ 803e5d8:	d016      	beq.n	803e608 <UART_SetConfig+0x6b0>
+        {
+          pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U));
+ 803e5da:	4b06      	ldr	r3, [pc, #24]	@ (803e5f4 <UART_SetConfig+0x69c>)
+ 803e5dc:	681b      	ldr	r3, [r3, #0]
+ 803e5de:	08db      	lsrs	r3, r3, #3
+ 803e5e0:	f003 0303 	and.w	r3, r3, #3
+ 803e5e4:	4a07      	ldr	r2, [pc, #28]	@ (803e604 <UART_SetConfig+0x6ac>)
+ 803e5e6:	fa22 f303 	lsr.w	r3, r2, r3
+ 803e5ea:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        }
+        else
+        {
+          pclk = (uint32_t) HSI_VALUE;
+        }
+        break;
+ 803e5ec:	e01c      	b.n	803e628 <UART_SetConfig+0x6d0>
+ 803e5ee:	bf00      	nop
+ 803e5f0:	40011400 	.word	0x40011400
+ 803e5f4:	58024400 	.word	0x58024400
+ 803e5f8:	40007800 	.word	0x40007800
+ 803e5fc:	40007c00 	.word	0x40007c00
+ 803e600:	58000c00 	.word	0x58000c00
+ 803e604:	03d09000 	.word	0x03d09000
+          pclk = (uint32_t) HSI_VALUE;
+ 803e608:	4b9d      	ldr	r3, [pc, #628]	@ (803e880 <UART_SetConfig+0x928>)
+ 803e60a:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803e60c:	e00c      	b.n	803e628 <UART_SetConfig+0x6d0>
+      case UART_CLOCKSOURCE_CSI:
+        pclk = (uint32_t) CSI_VALUE;
+ 803e60e:	4b9d      	ldr	r3, [pc, #628]	@ (803e884 <UART_SetConfig+0x92c>)
+ 803e610:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803e612:	e009      	b.n	803e628 <UART_SetConfig+0x6d0>
+      case UART_CLOCKSOURCE_LSE:
+        pclk = (uint32_t) LSE_VALUE;
+ 803e614:	f44f 4300 	mov.w	r3, #32768	@ 0x8000
+ 803e618:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803e61a:	e005      	b.n	803e628 <UART_SetConfig+0x6d0>
+      default:
+        pclk = 0U;
+ 803e61c:	2300      	movs	r3, #0
+ 803e61e:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        ret = HAL_ERROR;
+ 803e620:	2301      	movs	r3, #1
+ 803e622:	f887 3042 	strb.w	r3, [r7, #66]	@ 0x42
+        break;
+ 803e626:	bf00      	nop
+    }
+
+    /* If proper clock source reported */
+    if (pclk != 0U)
+ 803e628:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
+ 803e62a:	2b00      	cmp	r3, #0
+ 803e62c:	f000 81de 	beq.w	803e9ec <UART_SetConfig+0xa94>
+    {
+      /* Compute clock after Prescaler */
+      lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]);
+ 803e630:	697b      	ldr	r3, [r7, #20]
+ 803e632:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 803e634:	4a94      	ldr	r2, [pc, #592]	@ (803e888 <UART_SetConfig+0x930>)
+ 803e636:	f832 3013 	ldrh.w	r3, [r2, r3, lsl #1]
+ 803e63a:	461a      	mov	r2, r3
+ 803e63c:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
+ 803e63e:	fbb3 f3f2 	udiv	r3, r3, r2
+ 803e642:	633b      	str	r3, [r7, #48]	@ 0x30
+
+      /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */
+      if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) ||
+ 803e644:	697b      	ldr	r3, [r7, #20]
+ 803e646:	685a      	ldr	r2, [r3, #4]
+ 803e648:	4613      	mov	r3, r2
+ 803e64a:	005b      	lsls	r3, r3, #1
+ 803e64c:	4413      	add	r3, r2
+ 803e64e:	6b3a      	ldr	r2, [r7, #48]	@ 0x30
+ 803e650:	429a      	cmp	r2, r3
+ 803e652:	d305      	bcc.n	803e660 <UART_SetConfig+0x708>
+          (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate)))
+ 803e654:	697b      	ldr	r3, [r7, #20]
+ 803e656:	685b      	ldr	r3, [r3, #4]
+ 803e658:	031b      	lsls	r3, r3, #12
+      if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) ||
+ 803e65a:	6b3a      	ldr	r2, [r7, #48]	@ 0x30
+ 803e65c:	429a      	cmp	r2, r3
+ 803e65e:	d903      	bls.n	803e668 <UART_SetConfig+0x710>
+      {
+        ret = HAL_ERROR;
+ 803e660:	2301      	movs	r3, #1
+ 803e662:	f887 3042 	strb.w	r3, [r7, #66]	@ 0x42
+ 803e666:	e1c1      	b.n	803e9ec <UART_SetConfig+0xa94>
+      }
+      else
+      {
+        /* Check computed UsartDiv value is in allocated range
+           (it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */
+        usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ 803e668:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
+ 803e66a:	2200      	movs	r2, #0
+ 803e66c:	60bb      	str	r3, [r7, #8]
+ 803e66e:	60fa      	str	r2, [r7, #12]
+ 803e670:	697b      	ldr	r3, [r7, #20]
+ 803e672:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 803e674:	4a84      	ldr	r2, [pc, #528]	@ (803e888 <UART_SetConfig+0x930>)
+ 803e676:	f832 3013 	ldrh.w	r3, [r2, r3, lsl #1]
+ 803e67a:	b29b      	uxth	r3, r3
+ 803e67c:	2200      	movs	r2, #0
+ 803e67e:	603b      	str	r3, [r7, #0]
+ 803e680:	607a      	str	r2, [r7, #4]
+ 803e682:	e9d7 2300 	ldrd	r2, r3, [r7]
+ 803e686:	e9d7 0102 	ldrd	r0, r1, [r7, #8]
+ 803e68a:	f7e1 fe91 	bl	80203b0 <__aeabi_uldivmod>
+ 803e68e:	4602      	mov	r2, r0
+ 803e690:	460b      	mov	r3, r1
+ 803e692:	4610      	mov	r0, r2
+ 803e694:	4619      	mov	r1, r3
+ 803e696:	f04f 0200 	mov.w	r2, #0
+ 803e69a:	f04f 0300 	mov.w	r3, #0
+ 803e69e:	020b      	lsls	r3, r1, #8
+ 803e6a0:	ea43 6310 	orr.w	r3, r3, r0, lsr #24
+ 803e6a4:	0202      	lsls	r2, r0, #8
+ 803e6a6:	6979      	ldr	r1, [r7, #20]
+ 803e6a8:	6849      	ldr	r1, [r1, #4]
+ 803e6aa:	0849      	lsrs	r1, r1, #1
+ 803e6ac:	2000      	movs	r0, #0
+ 803e6ae:	460c      	mov	r4, r1
+ 803e6b0:	4605      	mov	r5, r0
+ 803e6b2:	eb12 0804 	adds.w	r8, r2, r4
+ 803e6b6:	eb43 0905 	adc.w	r9, r3, r5
+ 803e6ba:	697b      	ldr	r3, [r7, #20]
+ 803e6bc:	685b      	ldr	r3, [r3, #4]
+ 803e6be:	2200      	movs	r2, #0
+ 803e6c0:	469a      	mov	sl, r3
+ 803e6c2:	4693      	mov	fp, r2
+ 803e6c4:	4652      	mov	r2, sl
+ 803e6c6:	465b      	mov	r3, fp
+ 803e6c8:	4640      	mov	r0, r8
+ 803e6ca:	4649      	mov	r1, r9
+ 803e6cc:	f7e1 fe70 	bl	80203b0 <__aeabi_uldivmod>
+ 803e6d0:	4602      	mov	r2, r0
+ 803e6d2:	460b      	mov	r3, r1
+ 803e6d4:	4613      	mov	r3, r2
+ 803e6d6:	63bb      	str	r3, [r7, #56]	@ 0x38
+        if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))
+ 803e6d8:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 803e6da:	f5b3 7f40 	cmp.w	r3, #768	@ 0x300
+ 803e6de:	d308      	bcc.n	803e6f2 <UART_SetConfig+0x79a>
+ 803e6e0:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 803e6e2:	f5b3 1f80 	cmp.w	r3, #1048576	@ 0x100000
+ 803e6e6:	d204      	bcs.n	803e6f2 <UART_SetConfig+0x79a>
+        {
+          huart->Instance->BRR = usartdiv;
+ 803e6e8:	697b      	ldr	r3, [r7, #20]
+ 803e6ea:	681b      	ldr	r3, [r3, #0]
+ 803e6ec:	6bba      	ldr	r2, [r7, #56]	@ 0x38
+ 803e6ee:	60da      	str	r2, [r3, #12]
+ 803e6f0:	e17c      	b.n	803e9ec <UART_SetConfig+0xa94>
+        }
+        else
+        {
+          ret = HAL_ERROR;
+ 803e6f2:	2301      	movs	r3, #1
+ 803e6f4:	f887 3042 	strb.w	r3, [r7, #66]	@ 0x42
+ 803e6f8:	e178      	b.n	803e9ec <UART_SetConfig+0xa94>
+      } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) ||
+                (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */
+    } /* if (pclk != 0) */
+  }
+  /* Check UART Over Sampling to set Baud Rate Register */
+  else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
+ 803e6fa:	697b      	ldr	r3, [r7, #20]
+ 803e6fc:	69db      	ldr	r3, [r3, #28]
+ 803e6fe:	f5b3 4f00 	cmp.w	r3, #32768	@ 0x8000
+ 803e702:	f040 80c5 	bne.w	803e890 <UART_SetConfig+0x938>
+  {
+    switch (clocksource)
+ 803e706:	f897 3043 	ldrb.w	r3, [r7, #67]	@ 0x43
+ 803e70a:	2b20      	cmp	r3, #32
+ 803e70c:	dc48      	bgt.n	803e7a0 <UART_SetConfig+0x848>
+ 803e70e:	2b00      	cmp	r3, #0
+ 803e710:	db7b      	blt.n	803e80a <UART_SetConfig+0x8b2>
+ 803e712:	2b20      	cmp	r3, #32
+ 803e714:	d879      	bhi.n	803e80a <UART_SetConfig+0x8b2>
+ 803e716:	a201      	add	r2, pc, #4	@ (adr r2, 803e71c <UART_SetConfig+0x7c4>)
+ 803e718:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 803e71c:	0803e7a7 	.word	0x0803e7a7
+ 803e720:	0803e7af 	.word	0x0803e7af
+ 803e724:	0803e80b 	.word	0x0803e80b
+ 803e728:	0803e80b 	.word	0x0803e80b
+ 803e72c:	0803e7b7 	.word	0x0803e7b7
+ 803e730:	0803e80b 	.word	0x0803e80b
+ 803e734:	0803e80b 	.word	0x0803e80b
+ 803e738:	0803e80b 	.word	0x0803e80b
+ 803e73c:	0803e7c7 	.word	0x0803e7c7
+ 803e740:	0803e80b 	.word	0x0803e80b
+ 803e744:	0803e80b 	.word	0x0803e80b
+ 803e748:	0803e80b 	.word	0x0803e80b
+ 803e74c:	0803e80b 	.word	0x0803e80b
+ 803e750:	0803e80b 	.word	0x0803e80b
+ 803e754:	0803e80b 	.word	0x0803e80b
+ 803e758:	0803e80b 	.word	0x0803e80b
+ 803e75c:	0803e7d7 	.word	0x0803e7d7
+ 803e760:	0803e80b 	.word	0x0803e80b
+ 803e764:	0803e80b 	.word	0x0803e80b
+ 803e768:	0803e80b 	.word	0x0803e80b
+ 803e76c:	0803e80b 	.word	0x0803e80b
+ 803e770:	0803e80b 	.word	0x0803e80b
+ 803e774:	0803e80b 	.word	0x0803e80b
+ 803e778:	0803e80b 	.word	0x0803e80b
+ 803e77c:	0803e80b 	.word	0x0803e80b
+ 803e780:	0803e80b 	.word	0x0803e80b
+ 803e784:	0803e80b 	.word	0x0803e80b
+ 803e788:	0803e80b 	.word	0x0803e80b
+ 803e78c:	0803e80b 	.word	0x0803e80b
+ 803e790:	0803e80b 	.word	0x0803e80b
+ 803e794:	0803e80b 	.word	0x0803e80b
+ 803e798:	0803e80b 	.word	0x0803e80b
+ 803e79c:	0803e7fd 	.word	0x0803e7fd
+ 803e7a0:	2b40      	cmp	r3, #64	@ 0x40
+ 803e7a2:	d02e      	beq.n	803e802 <UART_SetConfig+0x8aa>
+ 803e7a4:	e031      	b.n	803e80a <UART_SetConfig+0x8b2>
+    {
+      case UART_CLOCKSOURCE_D2PCLK1:
+        pclk = HAL_RCC_GetPCLK1Freq();
+ 803e7a6:	f7fb fc25 	bl	8039ff4 <HAL_RCC_GetPCLK1Freq>
+ 803e7aa:	63f8      	str	r0, [r7, #60]	@ 0x3c
+        break;
+ 803e7ac:	e033      	b.n	803e816 <UART_SetConfig+0x8be>
+      case UART_CLOCKSOURCE_D2PCLK2:
+        pclk = HAL_RCC_GetPCLK2Freq();
+ 803e7ae:	f7fb fc37 	bl	803a020 <HAL_RCC_GetPCLK2Freq>
+ 803e7b2:	63f8      	str	r0, [r7, #60]	@ 0x3c
+        break;
+ 803e7b4:	e02f      	b.n	803e816 <UART_SetConfig+0x8be>
+      case UART_CLOCKSOURCE_PLL2:
+        HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+ 803e7b6:	f107 0324 	add.w	r3, r7, #36	@ 0x24
+ 803e7ba:	4618      	mov	r0, r3
+ 803e7bc:	f7fd fc02 	bl	803bfc4 <HAL_RCCEx_GetPLL2ClockFreq>
+        pclk = pll2_clocks.PLL2_Q_Frequency;
+ 803e7c0:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 803e7c2:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803e7c4:	e027      	b.n	803e816 <UART_SetConfig+0x8be>
+      case UART_CLOCKSOURCE_PLL3:
+        HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+ 803e7c6:	f107 0318 	add.w	r3, r7, #24
+ 803e7ca:	4618      	mov	r0, r3
+ 803e7cc:	f7fd fd4e 	bl	803c26c <HAL_RCCEx_GetPLL3ClockFreq>
+        pclk = pll3_clocks.PLL3_Q_Frequency;
+ 803e7d0:	69fb      	ldr	r3, [r7, #28]
+ 803e7d2:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803e7d4:	e01f      	b.n	803e816 <UART_SetConfig+0x8be>
+      case UART_CLOCKSOURCE_HSI:
+        if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
+ 803e7d6:	4b2d      	ldr	r3, [pc, #180]	@ (803e88c <UART_SetConfig+0x934>)
+ 803e7d8:	681b      	ldr	r3, [r3, #0]
+ 803e7da:	f003 0320 	and.w	r3, r3, #32
+ 803e7de:	2b00      	cmp	r3, #0
+ 803e7e0:	d009      	beq.n	803e7f6 <UART_SetConfig+0x89e>
+        {
+          pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U));
+ 803e7e2:	4b2a      	ldr	r3, [pc, #168]	@ (803e88c <UART_SetConfig+0x934>)
+ 803e7e4:	681b      	ldr	r3, [r3, #0]
+ 803e7e6:	08db      	lsrs	r3, r3, #3
+ 803e7e8:	f003 0303 	and.w	r3, r3, #3
+ 803e7ec:	4a24      	ldr	r2, [pc, #144]	@ (803e880 <UART_SetConfig+0x928>)
+ 803e7ee:	fa22 f303 	lsr.w	r3, r2, r3
+ 803e7f2:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        }
+        else
+        {
+          pclk = (uint32_t) HSI_VALUE;
+        }
+        break;
+ 803e7f4:	e00f      	b.n	803e816 <UART_SetConfig+0x8be>
+          pclk = (uint32_t) HSI_VALUE;
+ 803e7f6:	4b22      	ldr	r3, [pc, #136]	@ (803e880 <UART_SetConfig+0x928>)
+ 803e7f8:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803e7fa:	e00c      	b.n	803e816 <UART_SetConfig+0x8be>
+      case UART_CLOCKSOURCE_CSI:
+        pclk = (uint32_t) CSI_VALUE;
+ 803e7fc:	4b21      	ldr	r3, [pc, #132]	@ (803e884 <UART_SetConfig+0x92c>)
+ 803e7fe:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803e800:	e009      	b.n	803e816 <UART_SetConfig+0x8be>
+      case UART_CLOCKSOURCE_LSE:
+        pclk = (uint32_t) LSE_VALUE;
+ 803e802:	f44f 4300 	mov.w	r3, #32768	@ 0x8000
+ 803e806:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803e808:	e005      	b.n	803e816 <UART_SetConfig+0x8be>
+      default:
+        pclk = 0U;
+ 803e80a:	2300      	movs	r3, #0
+ 803e80c:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        ret = HAL_ERROR;
+ 803e80e:	2301      	movs	r3, #1
+ 803e810:	f887 3042 	strb.w	r3, [r7, #66]	@ 0x42
+        break;
+ 803e814:	bf00      	nop
+    }
+
+    /* USARTDIV must be greater than or equal to 0d16 */
+    if (pclk != 0U)
+ 803e816:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
+ 803e818:	2b00      	cmp	r3, #0
+ 803e81a:	f000 80e7 	beq.w	803e9ec <UART_SetConfig+0xa94>
+    {
+      usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ 803e81e:	697b      	ldr	r3, [r7, #20]
+ 803e820:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 803e822:	4a19      	ldr	r2, [pc, #100]	@ (803e888 <UART_SetConfig+0x930>)
+ 803e824:	f832 3013 	ldrh.w	r3, [r2, r3, lsl #1]
+ 803e828:	461a      	mov	r2, r3
+ 803e82a:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
+ 803e82c:	fbb3 f3f2 	udiv	r3, r3, r2
+ 803e830:	005a      	lsls	r2, r3, #1
+ 803e832:	697b      	ldr	r3, [r7, #20]
+ 803e834:	685b      	ldr	r3, [r3, #4]
+ 803e836:	085b      	lsrs	r3, r3, #1
+ 803e838:	441a      	add	r2, r3
+ 803e83a:	697b      	ldr	r3, [r7, #20]
+ 803e83c:	685b      	ldr	r3, [r3, #4]
+ 803e83e:	fbb2 f3f3 	udiv	r3, r2, r3
+ 803e842:	63bb      	str	r3, [r7, #56]	@ 0x38
+      if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
+ 803e844:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 803e846:	2b0f      	cmp	r3, #15
+ 803e848:	d916      	bls.n	803e878 <UART_SetConfig+0x920>
+ 803e84a:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 803e84c:	f5b3 3f80 	cmp.w	r3, #65536	@ 0x10000
+ 803e850:	d212      	bcs.n	803e878 <UART_SetConfig+0x920>
+      {
+        brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
+ 803e852:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 803e854:	b29b      	uxth	r3, r3
+ 803e856:	f023 030f 	bic.w	r3, r3, #15
+ 803e85a:	86fb      	strh	r3, [r7, #54]	@ 0x36
+        brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
+ 803e85c:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 803e85e:	085b      	lsrs	r3, r3, #1
+ 803e860:	b29b      	uxth	r3, r3
+ 803e862:	f003 0307 	and.w	r3, r3, #7
+ 803e866:	b29a      	uxth	r2, r3
+ 803e868:	8efb      	ldrh	r3, [r7, #54]	@ 0x36
+ 803e86a:	4313      	orrs	r3, r2
+ 803e86c:	86fb      	strh	r3, [r7, #54]	@ 0x36
+        huart->Instance->BRR = brrtemp;
+ 803e86e:	697b      	ldr	r3, [r7, #20]
+ 803e870:	681b      	ldr	r3, [r3, #0]
+ 803e872:	8efa      	ldrh	r2, [r7, #54]	@ 0x36
+ 803e874:	60da      	str	r2, [r3, #12]
+ 803e876:	e0b9      	b.n	803e9ec <UART_SetConfig+0xa94>
+      }
+      else
+      {
+        ret = HAL_ERROR;
+ 803e878:	2301      	movs	r3, #1
+ 803e87a:	f887 3042 	strb.w	r3, [r7, #66]	@ 0x42
+ 803e87e:	e0b5      	b.n	803e9ec <UART_SetConfig+0xa94>
+ 803e880:	03d09000 	.word	0x03d09000
+ 803e884:	003d0900 	.word	0x003d0900
+ 803e888:	08041c80 	.word	0x08041c80
+ 803e88c:	58024400 	.word	0x58024400
+      }
+    }
+  }
+  else
+  {
+    switch (clocksource)
+ 803e890:	f897 3043 	ldrb.w	r3, [r7, #67]	@ 0x43
+ 803e894:	2b20      	cmp	r3, #32
+ 803e896:	dc49      	bgt.n	803e92c <UART_SetConfig+0x9d4>
+ 803e898:	2b00      	cmp	r3, #0
+ 803e89a:	db7c      	blt.n	803e996 <UART_SetConfig+0xa3e>
+ 803e89c:	2b20      	cmp	r3, #32
+ 803e89e:	d87a      	bhi.n	803e996 <UART_SetConfig+0xa3e>
+ 803e8a0:	a201      	add	r2, pc, #4	@ (adr r2, 803e8a8 <UART_SetConfig+0x950>)
+ 803e8a2:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
+ 803e8a6:	bf00      	nop
+ 803e8a8:	0803e933 	.word	0x0803e933
+ 803e8ac:	0803e93b 	.word	0x0803e93b
+ 803e8b0:	0803e997 	.word	0x0803e997
+ 803e8b4:	0803e997 	.word	0x0803e997
+ 803e8b8:	0803e943 	.word	0x0803e943
+ 803e8bc:	0803e997 	.word	0x0803e997
+ 803e8c0:	0803e997 	.word	0x0803e997
+ 803e8c4:	0803e997 	.word	0x0803e997
+ 803e8c8:	0803e953 	.word	0x0803e953
+ 803e8cc:	0803e997 	.word	0x0803e997
+ 803e8d0:	0803e997 	.word	0x0803e997
+ 803e8d4:	0803e997 	.word	0x0803e997
+ 803e8d8:	0803e997 	.word	0x0803e997
+ 803e8dc:	0803e997 	.word	0x0803e997
+ 803e8e0:	0803e997 	.word	0x0803e997
+ 803e8e4:	0803e997 	.word	0x0803e997
+ 803e8e8:	0803e963 	.word	0x0803e963
+ 803e8ec:	0803e997 	.word	0x0803e997
+ 803e8f0:	0803e997 	.word	0x0803e997
+ 803e8f4:	0803e997 	.word	0x0803e997
+ 803e8f8:	0803e997 	.word	0x0803e997
+ 803e8fc:	0803e997 	.word	0x0803e997
+ 803e900:	0803e997 	.word	0x0803e997
+ 803e904:	0803e997 	.word	0x0803e997
+ 803e908:	0803e997 	.word	0x0803e997
+ 803e90c:	0803e997 	.word	0x0803e997
+ 803e910:	0803e997 	.word	0x0803e997
+ 803e914:	0803e997 	.word	0x0803e997
+ 803e918:	0803e997 	.word	0x0803e997
+ 803e91c:	0803e997 	.word	0x0803e997
+ 803e920:	0803e997 	.word	0x0803e997
+ 803e924:	0803e997 	.word	0x0803e997
+ 803e928:	0803e989 	.word	0x0803e989
+ 803e92c:	2b40      	cmp	r3, #64	@ 0x40
+ 803e92e:	d02e      	beq.n	803e98e <UART_SetConfig+0xa36>
+ 803e930:	e031      	b.n	803e996 <UART_SetConfig+0xa3e>
+    {
+      case UART_CLOCKSOURCE_D2PCLK1:
+        pclk = HAL_RCC_GetPCLK1Freq();
+ 803e932:	f7fb fb5f 	bl	8039ff4 <HAL_RCC_GetPCLK1Freq>
+ 803e936:	63f8      	str	r0, [r7, #60]	@ 0x3c
+        break;
+ 803e938:	e033      	b.n	803e9a2 <UART_SetConfig+0xa4a>
+      case UART_CLOCKSOURCE_D2PCLK2:
+        pclk = HAL_RCC_GetPCLK2Freq();
+ 803e93a:	f7fb fb71 	bl	803a020 <HAL_RCC_GetPCLK2Freq>
+ 803e93e:	63f8      	str	r0, [r7, #60]	@ 0x3c
+        break;
+ 803e940:	e02f      	b.n	803e9a2 <UART_SetConfig+0xa4a>
+      case UART_CLOCKSOURCE_PLL2:
+        HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+ 803e942:	f107 0324 	add.w	r3, r7, #36	@ 0x24
+ 803e946:	4618      	mov	r0, r3
+ 803e948:	f7fd fb3c 	bl	803bfc4 <HAL_RCCEx_GetPLL2ClockFreq>
+        pclk = pll2_clocks.PLL2_Q_Frequency;
+ 803e94c:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 803e94e:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803e950:	e027      	b.n	803e9a2 <UART_SetConfig+0xa4a>
+      case UART_CLOCKSOURCE_PLL3:
+        HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+ 803e952:	f107 0318 	add.w	r3, r7, #24
+ 803e956:	4618      	mov	r0, r3
+ 803e958:	f7fd fc88 	bl	803c26c <HAL_RCCEx_GetPLL3ClockFreq>
+        pclk = pll3_clocks.PLL3_Q_Frequency;
+ 803e95c:	69fb      	ldr	r3, [r7, #28]
+ 803e95e:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803e960:	e01f      	b.n	803e9a2 <UART_SetConfig+0xa4a>
+      case UART_CLOCKSOURCE_HSI:
+        if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
+ 803e962:	4b2d      	ldr	r3, [pc, #180]	@ (803ea18 <UART_SetConfig+0xac0>)
+ 803e964:	681b      	ldr	r3, [r3, #0]
+ 803e966:	f003 0320 	and.w	r3, r3, #32
+ 803e96a:	2b00      	cmp	r3, #0
+ 803e96c:	d009      	beq.n	803e982 <UART_SetConfig+0xa2a>
+        {
+          pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U));
+ 803e96e:	4b2a      	ldr	r3, [pc, #168]	@ (803ea18 <UART_SetConfig+0xac0>)
+ 803e970:	681b      	ldr	r3, [r3, #0]
+ 803e972:	08db      	lsrs	r3, r3, #3
+ 803e974:	f003 0303 	and.w	r3, r3, #3
+ 803e978:	4a28      	ldr	r2, [pc, #160]	@ (803ea1c <UART_SetConfig+0xac4>)
+ 803e97a:	fa22 f303 	lsr.w	r3, r2, r3
+ 803e97e:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        }
+        else
+        {
+          pclk = (uint32_t) HSI_VALUE;
+        }
+        break;
+ 803e980:	e00f      	b.n	803e9a2 <UART_SetConfig+0xa4a>
+          pclk = (uint32_t) HSI_VALUE;
+ 803e982:	4b26      	ldr	r3, [pc, #152]	@ (803ea1c <UART_SetConfig+0xac4>)
+ 803e984:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803e986:	e00c      	b.n	803e9a2 <UART_SetConfig+0xa4a>
+      case UART_CLOCKSOURCE_CSI:
+        pclk = (uint32_t) CSI_VALUE;
+ 803e988:	4b25      	ldr	r3, [pc, #148]	@ (803ea20 <UART_SetConfig+0xac8>)
+ 803e98a:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803e98c:	e009      	b.n	803e9a2 <UART_SetConfig+0xa4a>
+      case UART_CLOCKSOURCE_LSE:
+        pclk = (uint32_t) LSE_VALUE;
+ 803e98e:	f44f 4300 	mov.w	r3, #32768	@ 0x8000
+ 803e992:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        break;
+ 803e994:	e005      	b.n	803e9a2 <UART_SetConfig+0xa4a>
+      default:
+        pclk = 0U;
+ 803e996:	2300      	movs	r3, #0
+ 803e998:	63fb      	str	r3, [r7, #60]	@ 0x3c
+        ret = HAL_ERROR;
+ 803e99a:	2301      	movs	r3, #1
+ 803e99c:	f887 3042 	strb.w	r3, [r7, #66]	@ 0x42
+        break;
+ 803e9a0:	bf00      	nop
+    }
+
+    if (pclk != 0U)
+ 803e9a2:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
+ 803e9a4:	2b00      	cmp	r3, #0
+ 803e9a6:	d021      	beq.n	803e9ec <UART_SetConfig+0xa94>
+    {
+      /* USARTDIV must be greater than or equal to 0d16 */
+      usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ 803e9a8:	697b      	ldr	r3, [r7, #20]
+ 803e9aa:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 803e9ac:	4a1d      	ldr	r2, [pc, #116]	@ (803ea24 <UART_SetConfig+0xacc>)
+ 803e9ae:	f832 3013 	ldrh.w	r3, [r2, r3, lsl #1]
+ 803e9b2:	461a      	mov	r2, r3
+ 803e9b4:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
+ 803e9b6:	fbb3 f2f2 	udiv	r2, r3, r2
+ 803e9ba:	697b      	ldr	r3, [r7, #20]
+ 803e9bc:	685b      	ldr	r3, [r3, #4]
+ 803e9be:	085b      	lsrs	r3, r3, #1
+ 803e9c0:	441a      	add	r2, r3
+ 803e9c2:	697b      	ldr	r3, [r7, #20]
+ 803e9c4:	685b      	ldr	r3, [r3, #4]
+ 803e9c6:	fbb2 f3f3 	udiv	r3, r2, r3
+ 803e9ca:	63bb      	str	r3, [r7, #56]	@ 0x38
+      if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
+ 803e9cc:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 803e9ce:	2b0f      	cmp	r3, #15
+ 803e9d0:	d909      	bls.n	803e9e6 <UART_SetConfig+0xa8e>
+ 803e9d2:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 803e9d4:	f5b3 3f80 	cmp.w	r3, #65536	@ 0x10000
+ 803e9d8:	d205      	bcs.n	803e9e6 <UART_SetConfig+0xa8e>
+      {
+        huart->Instance->BRR = (uint16_t)usartdiv;
+ 803e9da:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 803e9dc:	b29a      	uxth	r2, r3
+ 803e9de:	697b      	ldr	r3, [r7, #20]
+ 803e9e0:	681b      	ldr	r3, [r3, #0]
+ 803e9e2:	60da      	str	r2, [r3, #12]
+ 803e9e4:	e002      	b.n	803e9ec <UART_SetConfig+0xa94>
+      }
+      else
+      {
+        ret = HAL_ERROR;
+ 803e9e6:	2301      	movs	r3, #1
+ 803e9e8:	f887 3042 	strb.w	r3, [r7, #66]	@ 0x42
+      }
+    }
+  }
+
+  /* Initialize the number of data to process during RX/TX ISR execution */
+  huart->NbTxDataToProcess = 1;
+ 803e9ec:	697b      	ldr	r3, [r7, #20]
+ 803e9ee:	2201      	movs	r2, #1
+ 803e9f0:	f8a3 206a 	strh.w	r2, [r3, #106]	@ 0x6a
+  huart->NbRxDataToProcess = 1;
+ 803e9f4:	697b      	ldr	r3, [r7, #20]
+ 803e9f6:	2201      	movs	r2, #1
+ 803e9f8:	f8a3 2068 	strh.w	r2, [r3, #104]	@ 0x68
+
+  /* Clear ISR function pointers */
+  huart->RxISR = NULL;
+ 803e9fc:	697b      	ldr	r3, [r7, #20]
+ 803e9fe:	2200      	movs	r2, #0
+ 803ea00:	675a      	str	r2, [r3, #116]	@ 0x74
+  huart->TxISR = NULL;
+ 803ea02:	697b      	ldr	r3, [r7, #20]
+ 803ea04:	2200      	movs	r2, #0
+ 803ea06:	679a      	str	r2, [r3, #120]	@ 0x78
+
+  return ret;
+ 803ea08:	f897 3042 	ldrb.w	r3, [r7, #66]	@ 0x42
+}
+ 803ea0c:	4618      	mov	r0, r3
+ 803ea0e:	3748      	adds	r7, #72	@ 0x48
+ 803ea10:	46bd      	mov	sp, r7
+ 803ea12:	e8bd 8fb0 	ldmia.w	sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
+ 803ea16:	bf00      	nop
+ 803ea18:	58024400 	.word	0x58024400
+ 803ea1c:	03d09000 	.word	0x03d09000
+ 803ea20:	003d0900 	.word	0x003d0900
+ 803ea24:	08041c80 	.word	0x08041c80
+
+0803ea28 <UART_AdvFeatureConfig>:
+  * @brief Configure the UART peripheral advanced features.
+  * @param huart UART handle.
+  * @retval None
+  */
+void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
+{
+ 803ea28:	b480      	push	{r7}
+ 803ea2a:	b083      	sub	sp, #12
+ 803ea2c:	af00      	add	r7, sp, #0
+ 803ea2e:	6078      	str	r0, [r7, #4]
+  /* Check whether the set of advanced features to configure is properly set */
+  assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
+
+  /* if required, configure RX/TX pins swap */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
+ 803ea30:	687b      	ldr	r3, [r7, #4]
+ 803ea32:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 803ea34:	f003 0308 	and.w	r3, r3, #8
+ 803ea38:	2b00      	cmp	r3, #0
+ 803ea3a:	d00a      	beq.n	803ea52 <UART_AdvFeatureConfig+0x2a>
+  {
+    assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
+ 803ea3c:	687b      	ldr	r3, [r7, #4]
+ 803ea3e:	681b      	ldr	r3, [r3, #0]
+ 803ea40:	685b      	ldr	r3, [r3, #4]
+ 803ea42:	f423 4100 	bic.w	r1, r3, #32768	@ 0x8000
+ 803ea46:	687b      	ldr	r3, [r7, #4]
+ 803ea48:	6b9a      	ldr	r2, [r3, #56]	@ 0x38
+ 803ea4a:	687b      	ldr	r3, [r7, #4]
+ 803ea4c:	681b      	ldr	r3, [r3, #0]
+ 803ea4e:	430a      	orrs	r2, r1
+ 803ea50:	605a      	str	r2, [r3, #4]
+  }
+
+  /* if required, configure TX pin active level inversion */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
+ 803ea52:	687b      	ldr	r3, [r7, #4]
+ 803ea54:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 803ea56:	f003 0301 	and.w	r3, r3, #1
+ 803ea5a:	2b00      	cmp	r3, #0
+ 803ea5c:	d00a      	beq.n	803ea74 <UART_AdvFeatureConfig+0x4c>
+  {
+    assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
+ 803ea5e:	687b      	ldr	r3, [r7, #4]
+ 803ea60:	681b      	ldr	r3, [r3, #0]
+ 803ea62:	685b      	ldr	r3, [r3, #4]
+ 803ea64:	f423 3100 	bic.w	r1, r3, #131072	@ 0x20000
+ 803ea68:	687b      	ldr	r3, [r7, #4]
+ 803ea6a:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
+ 803ea6c:	687b      	ldr	r3, [r7, #4]
+ 803ea6e:	681b      	ldr	r3, [r3, #0]
+ 803ea70:	430a      	orrs	r2, r1
+ 803ea72:	605a      	str	r2, [r3, #4]
+  }
+
+  /* if required, configure RX pin active level inversion */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
+ 803ea74:	687b      	ldr	r3, [r7, #4]
+ 803ea76:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 803ea78:	f003 0302 	and.w	r3, r3, #2
+ 803ea7c:	2b00      	cmp	r3, #0
+ 803ea7e:	d00a      	beq.n	803ea96 <UART_AdvFeatureConfig+0x6e>
+  {
+    assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
+ 803ea80:	687b      	ldr	r3, [r7, #4]
+ 803ea82:	681b      	ldr	r3, [r3, #0]
+ 803ea84:	685b      	ldr	r3, [r3, #4]
+ 803ea86:	f423 3180 	bic.w	r1, r3, #65536	@ 0x10000
+ 803ea8a:	687b      	ldr	r3, [r7, #4]
+ 803ea8c:	6b1a      	ldr	r2, [r3, #48]	@ 0x30
+ 803ea8e:	687b      	ldr	r3, [r7, #4]
+ 803ea90:	681b      	ldr	r3, [r3, #0]
+ 803ea92:	430a      	orrs	r2, r1
+ 803ea94:	605a      	str	r2, [r3, #4]
+  }
+
+  /* if required, configure data inversion */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
+ 803ea96:	687b      	ldr	r3, [r7, #4]
+ 803ea98:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 803ea9a:	f003 0304 	and.w	r3, r3, #4
+ 803ea9e:	2b00      	cmp	r3, #0
+ 803eaa0:	d00a      	beq.n	803eab8 <UART_AdvFeatureConfig+0x90>
+  {
+    assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
+ 803eaa2:	687b      	ldr	r3, [r7, #4]
+ 803eaa4:	681b      	ldr	r3, [r3, #0]
+ 803eaa6:	685b      	ldr	r3, [r3, #4]
+ 803eaa8:	f423 2180 	bic.w	r1, r3, #262144	@ 0x40000
+ 803eaac:	687b      	ldr	r3, [r7, #4]
+ 803eaae:	6b5a      	ldr	r2, [r3, #52]	@ 0x34
+ 803eab0:	687b      	ldr	r3, [r7, #4]
+ 803eab2:	681b      	ldr	r3, [r3, #0]
+ 803eab4:	430a      	orrs	r2, r1
+ 803eab6:	605a      	str	r2, [r3, #4]
+  }
+
+  /* if required, configure RX overrun detection disabling */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
+ 803eab8:	687b      	ldr	r3, [r7, #4]
+ 803eaba:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 803eabc:	f003 0310 	and.w	r3, r3, #16
+ 803eac0:	2b00      	cmp	r3, #0
+ 803eac2:	d00a      	beq.n	803eada <UART_AdvFeatureConfig+0xb2>
+  {
+    assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
+    MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
+ 803eac4:	687b      	ldr	r3, [r7, #4]
+ 803eac6:	681b      	ldr	r3, [r3, #0]
+ 803eac8:	689b      	ldr	r3, [r3, #8]
+ 803eaca:	f423 5180 	bic.w	r1, r3, #4096	@ 0x1000
+ 803eace:	687b      	ldr	r3, [r7, #4]
+ 803ead0:	6bda      	ldr	r2, [r3, #60]	@ 0x3c
+ 803ead2:	687b      	ldr	r3, [r7, #4]
+ 803ead4:	681b      	ldr	r3, [r3, #0]
+ 803ead6:	430a      	orrs	r2, r1
+ 803ead8:	609a      	str	r2, [r3, #8]
+  }
+
+  /* if required, configure DMA disabling on reception error */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
+ 803eada:	687b      	ldr	r3, [r7, #4]
+ 803eadc:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 803eade:	f003 0320 	and.w	r3, r3, #32
+ 803eae2:	2b00      	cmp	r3, #0
+ 803eae4:	d00a      	beq.n	803eafc <UART_AdvFeatureConfig+0xd4>
+  {
+    assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
+    MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
+ 803eae6:	687b      	ldr	r3, [r7, #4]
+ 803eae8:	681b      	ldr	r3, [r3, #0]
+ 803eaea:	689b      	ldr	r3, [r3, #8]
+ 803eaec:	f423 5100 	bic.w	r1, r3, #8192	@ 0x2000
+ 803eaf0:	687b      	ldr	r3, [r7, #4]
+ 803eaf2:	6c1a      	ldr	r2, [r3, #64]	@ 0x40
+ 803eaf4:	687b      	ldr	r3, [r7, #4]
+ 803eaf6:	681b      	ldr	r3, [r3, #0]
+ 803eaf8:	430a      	orrs	r2, r1
+ 803eafa:	609a      	str	r2, [r3, #8]
+  }
+
+  /* if required, configure auto Baud rate detection scheme */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
+ 803eafc:	687b      	ldr	r3, [r7, #4]
+ 803eafe:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 803eb00:	f003 0340 	and.w	r3, r3, #64	@ 0x40
+ 803eb04:	2b00      	cmp	r3, #0
+ 803eb06:	d01a      	beq.n	803eb3e <UART_AdvFeatureConfig+0x116>
+  {
+    assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
+    assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
+ 803eb08:	687b      	ldr	r3, [r7, #4]
+ 803eb0a:	681b      	ldr	r3, [r3, #0]
+ 803eb0c:	685b      	ldr	r3, [r3, #4]
+ 803eb0e:	f423 1180 	bic.w	r1, r3, #1048576	@ 0x100000
+ 803eb12:	687b      	ldr	r3, [r7, #4]
+ 803eb14:	6c5a      	ldr	r2, [r3, #68]	@ 0x44
+ 803eb16:	687b      	ldr	r3, [r7, #4]
+ 803eb18:	681b      	ldr	r3, [r3, #0]
+ 803eb1a:	430a      	orrs	r2, r1
+ 803eb1c:	605a      	str	r2, [r3, #4]
+    /* set auto Baudrate detection parameters if detection is enabled */
+    if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
+ 803eb1e:	687b      	ldr	r3, [r7, #4]
+ 803eb20:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
+ 803eb22:	f5b3 1f80 	cmp.w	r3, #1048576	@ 0x100000
+ 803eb26:	d10a      	bne.n	803eb3e <UART_AdvFeatureConfig+0x116>
+    {
+      assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
+      MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
+ 803eb28:	687b      	ldr	r3, [r7, #4]
+ 803eb2a:	681b      	ldr	r3, [r3, #0]
+ 803eb2c:	685b      	ldr	r3, [r3, #4]
+ 803eb2e:	f423 01c0 	bic.w	r1, r3, #6291456	@ 0x600000
+ 803eb32:	687b      	ldr	r3, [r7, #4]
+ 803eb34:	6c9a      	ldr	r2, [r3, #72]	@ 0x48
+ 803eb36:	687b      	ldr	r3, [r7, #4]
+ 803eb38:	681b      	ldr	r3, [r3, #0]
+ 803eb3a:	430a      	orrs	r2, r1
+ 803eb3c:	605a      	str	r2, [r3, #4]
+    }
+  }
+
+  /* if required, configure MSB first on communication line */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
+ 803eb3e:	687b      	ldr	r3, [r7, #4]
+ 803eb40:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
+ 803eb42:	f003 0380 	and.w	r3, r3, #128	@ 0x80
+ 803eb46:	2b00      	cmp	r3, #0
+ 803eb48:	d00a      	beq.n	803eb60 <UART_AdvFeatureConfig+0x138>
+  {
+    assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
+ 803eb4a:	687b      	ldr	r3, [r7, #4]
+ 803eb4c:	681b      	ldr	r3, [r3, #0]
+ 803eb4e:	685b      	ldr	r3, [r3, #4]
+ 803eb50:	f423 2100 	bic.w	r1, r3, #524288	@ 0x80000
+ 803eb54:	687b      	ldr	r3, [r7, #4]
+ 803eb56:	6cda      	ldr	r2, [r3, #76]	@ 0x4c
+ 803eb58:	687b      	ldr	r3, [r7, #4]
+ 803eb5a:	681b      	ldr	r3, [r3, #0]
+ 803eb5c:	430a      	orrs	r2, r1
+ 803eb5e:	605a      	str	r2, [r3, #4]
+  }
+}
+ 803eb60:	bf00      	nop
+ 803eb62:	370c      	adds	r7, #12
+ 803eb64:	46bd      	mov	sp, r7
+ 803eb66:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 803eb6a:	4770      	bx	lr
+
+0803eb6c <UART_CheckIdleState>:
+  * @brief Check the UART Idle State.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
+{
+ 803eb6c:	b580      	push	{r7, lr}
+ 803eb6e:	b098      	sub	sp, #96	@ 0x60
+ 803eb70:	af02      	add	r7, sp, #8
+ 803eb72:	6078      	str	r0, [r7, #4]
+  uint32_t tickstart;
+
+  /* Initialize the UART ErrorCode */
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+ 803eb74:	687b      	ldr	r3, [r7, #4]
+ 803eb76:	2200      	movs	r2, #0
+ 803eb78:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90
+
+  /* Init tickstart for timeout management */
+  tickstart = HAL_GetTick();
+ 803eb7c:	f7f2 fed8 	bl	8031930 <HAL_GetTick>
+ 803eb80:	6578      	str	r0, [r7, #84]	@ 0x54
+
+  /* Check if the Transmitter is enabled */
+  if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+ 803eb82:	687b      	ldr	r3, [r7, #4]
+ 803eb84:	681b      	ldr	r3, [r3, #0]
+ 803eb86:	681b      	ldr	r3, [r3, #0]
+ 803eb88:	f003 0308 	and.w	r3, r3, #8
+ 803eb8c:	2b08      	cmp	r3, #8
+ 803eb8e:	d12f      	bne.n	803ebf0 <UART_CheckIdleState+0x84>
+  {
+    /* Wait until TEACK flag is set */
+    if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
+ 803eb90:	f06f 437e 	mvn.w	r3, #4261412864	@ 0xfe000000
+ 803eb94:	9300      	str	r3, [sp, #0]
+ 803eb96:	6d7b      	ldr	r3, [r7, #84]	@ 0x54
+ 803eb98:	2200      	movs	r2, #0
+ 803eb9a:	f44f 1100 	mov.w	r1, #2097152	@ 0x200000
+ 803eb9e:	6878      	ldr	r0, [r7, #4]
+ 803eba0:	f000 f88e 	bl	803ecc0 <UART_WaitOnFlagUntilTimeout>
+ 803eba4:	4603      	mov	r3, r0
+ 803eba6:	2b00      	cmp	r3, #0
+ 803eba8:	d022      	beq.n	803ebf0 <UART_CheckIdleState+0x84>
+    {
+      /* Disable TXE interrupt for the interrupt process */
+      ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE));
+ 803ebaa:	687b      	ldr	r3, [r7, #4]
+ 803ebac:	681b      	ldr	r3, [r3, #0]
+ 803ebae:	63bb      	str	r3, [r7, #56]	@ 0x38
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ 803ebb0:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 803ebb2:	e853 3f00 	ldrex	r3, [r3]
+ 803ebb6:	637b      	str	r3, [r7, #52]	@ 0x34
+   return(result);
+ 803ebb8:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
+ 803ebba:	f023 0380 	bic.w	r3, r3, #128	@ 0x80
+ 803ebbe:	653b      	str	r3, [r7, #80]	@ 0x50
+ 803ebc0:	687b      	ldr	r3, [r7, #4]
+ 803ebc2:	681b      	ldr	r3, [r3, #0]
+ 803ebc4:	461a      	mov	r2, r3
+ 803ebc6:	6d3b      	ldr	r3, [r7, #80]	@ 0x50
+ 803ebc8:	647b      	str	r3, [r7, #68]	@ 0x44
+ 803ebca:	643a      	str	r2, [r7, #64]	@ 0x40
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ 803ebcc:	6c39      	ldr	r1, [r7, #64]	@ 0x40
+ 803ebce:	6c7a      	ldr	r2, [r7, #68]	@ 0x44
+ 803ebd0:	e841 2300 	strex	r3, r2, [r1]
+ 803ebd4:	63fb      	str	r3, [r7, #60]	@ 0x3c
+   return(result);
+ 803ebd6:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
+ 803ebd8:	2b00      	cmp	r3, #0
+ 803ebda:	d1e6      	bne.n	803ebaa <UART_CheckIdleState+0x3e>
+
+      huart->gState = HAL_UART_STATE_READY;
+ 803ebdc:	687b      	ldr	r3, [r7, #4]
+ 803ebde:	2220      	movs	r2, #32
+ 803ebe0:	f8c3 2088 	str.w	r2, [r3, #136]	@ 0x88
+
+      __HAL_UNLOCK(huart);
+ 803ebe4:	687b      	ldr	r3, [r7, #4]
+ 803ebe6:	2200      	movs	r2, #0
+ 803ebe8:	f883 2084 	strb.w	r2, [r3, #132]	@ 0x84
+
+      /* Timeout occurred */
+      return HAL_TIMEOUT;
+ 803ebec:	2303      	movs	r3, #3
+ 803ebee:	e063      	b.n	803ecb8 <UART_CheckIdleState+0x14c>
+    }
+  }
+
+  /* Check if the Receiver is enabled */
+  if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
+ 803ebf0:	687b      	ldr	r3, [r7, #4]
+ 803ebf2:	681b      	ldr	r3, [r3, #0]
+ 803ebf4:	681b      	ldr	r3, [r3, #0]
+ 803ebf6:	f003 0304 	and.w	r3, r3, #4
+ 803ebfa:	2b04      	cmp	r3, #4
+ 803ebfc:	d149      	bne.n	803ec92 <UART_CheckIdleState+0x126>
+  {
+    /* Wait until REACK flag is set */
+    if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
+ 803ebfe:	f06f 437e 	mvn.w	r3, #4261412864	@ 0xfe000000
+ 803ec02:	9300      	str	r3, [sp, #0]
+ 803ec04:	6d7b      	ldr	r3, [r7, #84]	@ 0x54
+ 803ec06:	2200      	movs	r2, #0
+ 803ec08:	f44f 0180 	mov.w	r1, #4194304	@ 0x400000
+ 803ec0c:	6878      	ldr	r0, [r7, #4]
+ 803ec0e:	f000 f857 	bl	803ecc0 <UART_WaitOnFlagUntilTimeout>
+ 803ec12:	4603      	mov	r3, r0
+ 803ec14:	2b00      	cmp	r3, #0
+ 803ec16:	d03c      	beq.n	803ec92 <UART_CheckIdleState+0x126>
+    {
+      /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error)
+      interrupts for the interrupt process */
+      ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+ 803ec18:	687b      	ldr	r3, [r7, #4]
+ 803ec1a:	681b      	ldr	r3, [r3, #0]
+ 803ec1c:	627b      	str	r3, [r7, #36]	@ 0x24
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ 803ec1e:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 803ec20:	e853 3f00 	ldrex	r3, [r3]
+ 803ec24:	623b      	str	r3, [r7, #32]
+   return(result);
+ 803ec26:	6a3b      	ldr	r3, [r7, #32]
+ 803ec28:	f423 7390 	bic.w	r3, r3, #288	@ 0x120
+ 803ec2c:	64fb      	str	r3, [r7, #76]	@ 0x4c
+ 803ec2e:	687b      	ldr	r3, [r7, #4]
+ 803ec30:	681b      	ldr	r3, [r3, #0]
+ 803ec32:	461a      	mov	r2, r3
+ 803ec34:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
+ 803ec36:	633b      	str	r3, [r7, #48]	@ 0x30
+ 803ec38:	62fa      	str	r2, [r7, #44]	@ 0x2c
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ 803ec3a:	6af9      	ldr	r1, [r7, #44]	@ 0x2c
+ 803ec3c:	6b3a      	ldr	r2, [r7, #48]	@ 0x30
+ 803ec3e:	e841 2300 	strex	r3, r2, [r1]
+ 803ec42:	62bb      	str	r3, [r7, #40]	@ 0x28
+   return(result);
+ 803ec44:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 803ec46:	2b00      	cmp	r3, #0
+ 803ec48:	d1e6      	bne.n	803ec18 <UART_CheckIdleState+0xac>
+      ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ 803ec4a:	687b      	ldr	r3, [r7, #4]
+ 803ec4c:	681b      	ldr	r3, [r3, #0]
+ 803ec4e:	3308      	adds	r3, #8
+ 803ec50:	613b      	str	r3, [r7, #16]
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ 803ec52:	693b      	ldr	r3, [r7, #16]
+ 803ec54:	e853 3f00 	ldrex	r3, [r3]
+ 803ec58:	60fb      	str	r3, [r7, #12]
+   return(result);
+ 803ec5a:	68fb      	ldr	r3, [r7, #12]
+ 803ec5c:	f023 0301 	bic.w	r3, r3, #1
+ 803ec60:	64bb      	str	r3, [r7, #72]	@ 0x48
+ 803ec62:	687b      	ldr	r3, [r7, #4]
+ 803ec64:	681b      	ldr	r3, [r3, #0]
+ 803ec66:	3308      	adds	r3, #8
+ 803ec68:	6cba      	ldr	r2, [r7, #72]	@ 0x48
+ 803ec6a:	61fa      	str	r2, [r7, #28]
+ 803ec6c:	61bb      	str	r3, [r7, #24]
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ 803ec6e:	69b9      	ldr	r1, [r7, #24]
+ 803ec70:	69fa      	ldr	r2, [r7, #28]
+ 803ec72:	e841 2300 	strex	r3, r2, [r1]
+ 803ec76:	617b      	str	r3, [r7, #20]
+   return(result);
+ 803ec78:	697b      	ldr	r3, [r7, #20]
+ 803ec7a:	2b00      	cmp	r3, #0
+ 803ec7c:	d1e5      	bne.n	803ec4a <UART_CheckIdleState+0xde>
+
+      huart->RxState = HAL_UART_STATE_READY;
+ 803ec7e:	687b      	ldr	r3, [r7, #4]
+ 803ec80:	2220      	movs	r2, #32
+ 803ec82:	f8c3 208c 	str.w	r2, [r3, #140]	@ 0x8c
+
+      __HAL_UNLOCK(huart);
+ 803ec86:	687b      	ldr	r3, [r7, #4]
+ 803ec88:	2200      	movs	r2, #0
+ 803ec8a:	f883 2084 	strb.w	r2, [r3, #132]	@ 0x84
+
+      /* Timeout occurred */
+      return HAL_TIMEOUT;
+ 803ec8e:	2303      	movs	r3, #3
+ 803ec90:	e012      	b.n	803ecb8 <UART_CheckIdleState+0x14c>
+    }
+  }
+
+  /* Initialize the UART State */
+  huart->gState = HAL_UART_STATE_READY;
+ 803ec92:	687b      	ldr	r3, [r7, #4]
+ 803ec94:	2220      	movs	r2, #32
+ 803ec96:	f8c3 2088 	str.w	r2, [r3, #136]	@ 0x88
+  huart->RxState = HAL_UART_STATE_READY;
+ 803ec9a:	687b      	ldr	r3, [r7, #4]
+ 803ec9c:	2220      	movs	r2, #32
+ 803ec9e:	f8c3 208c 	str.w	r2, [r3, #140]	@ 0x8c
+  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ 803eca2:	687b      	ldr	r3, [r7, #4]
+ 803eca4:	2200      	movs	r2, #0
+ 803eca6:	66da      	str	r2, [r3, #108]	@ 0x6c
+  huart->RxEventType = HAL_UART_RXEVENT_TC;
+ 803eca8:	687b      	ldr	r3, [r7, #4]
+ 803ecaa:	2200      	movs	r2, #0
+ 803ecac:	671a      	str	r2, [r3, #112]	@ 0x70
+
+  __HAL_UNLOCK(huart);
+ 803ecae:	687b      	ldr	r3, [r7, #4]
+ 803ecb0:	2200      	movs	r2, #0
+ 803ecb2:	f883 2084 	strb.w	r2, [r3, #132]	@ 0x84
+
+  return HAL_OK;
+ 803ecb6:	2300      	movs	r3, #0
+}
+ 803ecb8:	4618      	mov	r0, r3
+ 803ecba:	3758      	adds	r7, #88	@ 0x58
+ 803ecbc:	46bd      	mov	sp, r7
+ 803ecbe:	bd80      	pop	{r7, pc}
+
+0803ecc0 <UART_WaitOnFlagUntilTimeout>:
+  * @param Timeout   Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
+                                              uint32_t Tickstart, uint32_t Timeout)
+{
+ 803ecc0:	b580      	push	{r7, lr}
+ 803ecc2:	b084      	sub	sp, #16
+ 803ecc4:	af00      	add	r7, sp, #0
+ 803ecc6:	60f8      	str	r0, [r7, #12]
+ 803ecc8:	60b9      	str	r1, [r7, #8]
+ 803ecca:	603b      	str	r3, [r7, #0]
+ 803eccc:	4613      	mov	r3, r2
+ 803ecce:	71fb      	strb	r3, [r7, #7]
+  /* Wait until flag is set */
+  while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
+ 803ecd0:	e04f      	b.n	803ed72 <UART_WaitOnFlagUntilTimeout+0xb2>
+  {
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
+ 803ecd2:	69bb      	ldr	r3, [r7, #24]
+ 803ecd4:	f1b3 3fff 	cmp.w	r3, #4294967295
+ 803ecd8:	d04b      	beq.n	803ed72 <UART_WaitOnFlagUntilTimeout+0xb2>
+    {
+      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+ 803ecda:	f7f2 fe29 	bl	8031930 <HAL_GetTick>
+ 803ecde:	4602      	mov	r2, r0
+ 803ece0:	683b      	ldr	r3, [r7, #0]
+ 803ece2:	1ad3      	subs	r3, r2, r3
+ 803ece4:	69ba      	ldr	r2, [r7, #24]
+ 803ece6:	429a      	cmp	r2, r3
+ 803ece8:	d302      	bcc.n	803ecf0 <UART_WaitOnFlagUntilTimeout+0x30>
+ 803ecea:	69bb      	ldr	r3, [r7, #24]
+ 803ecec:	2b00      	cmp	r3, #0
+ 803ecee:	d101      	bne.n	803ecf4 <UART_WaitOnFlagUntilTimeout+0x34>
+      {
+
+        return HAL_TIMEOUT;
+ 803ecf0:	2303      	movs	r3, #3
+ 803ecf2:	e04e      	b.n	803ed92 <UART_WaitOnFlagUntilTimeout+0xd2>
+      }
+
+      if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
+ 803ecf4:	68fb      	ldr	r3, [r7, #12]
+ 803ecf6:	681b      	ldr	r3, [r3, #0]
+ 803ecf8:	681b      	ldr	r3, [r3, #0]
+ 803ecfa:	f003 0304 	and.w	r3, r3, #4
+ 803ecfe:	2b00      	cmp	r3, #0
+ 803ed00:	d037      	beq.n	803ed72 <UART_WaitOnFlagUntilTimeout+0xb2>
+ 803ed02:	68bb      	ldr	r3, [r7, #8]
+ 803ed04:	2b80      	cmp	r3, #128	@ 0x80
+ 803ed06:	d034      	beq.n	803ed72 <UART_WaitOnFlagUntilTimeout+0xb2>
+ 803ed08:	68bb      	ldr	r3, [r7, #8]
+ 803ed0a:	2b40      	cmp	r3, #64	@ 0x40
+ 803ed0c:	d031      	beq.n	803ed72 <UART_WaitOnFlagUntilTimeout+0xb2>
+      {
+        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
+ 803ed0e:	68fb      	ldr	r3, [r7, #12]
+ 803ed10:	681b      	ldr	r3, [r3, #0]
+ 803ed12:	69db      	ldr	r3, [r3, #28]
+ 803ed14:	f003 0308 	and.w	r3, r3, #8
+ 803ed18:	2b08      	cmp	r3, #8
+ 803ed1a:	d110      	bne.n	803ed3e <UART_WaitOnFlagUntilTimeout+0x7e>
+        {
+          /* Clear Overrun Error flag*/
+          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
+ 803ed1c:	68fb      	ldr	r3, [r7, #12]
+ 803ed1e:	681b      	ldr	r3, [r3, #0]
+ 803ed20:	2208      	movs	r2, #8
+ 803ed22:	621a      	str	r2, [r3, #32]
+
+          /* Blocking error : transfer is aborted
+          Set the UART state ready to be able to start again the process,
+          Disable Rx Interrupts if ongoing */
+          UART_EndRxTransfer(huart);
+ 803ed24:	68f8      	ldr	r0, [r7, #12]
+ 803ed26:	f000 f99d 	bl	803f064 <UART_EndRxTransfer>
+
+          huart->ErrorCode = HAL_UART_ERROR_ORE;
+ 803ed2a:	68fb      	ldr	r3, [r7, #12]
+ 803ed2c:	2208      	movs	r2, #8
+ 803ed2e:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(huart);
+ 803ed32:	68fb      	ldr	r3, [r7, #12]
+ 803ed34:	2200      	movs	r2, #0
+ 803ed36:	f883 2084 	strb.w	r2, [r3, #132]	@ 0x84
+
+          return HAL_ERROR;
+ 803ed3a:	2301      	movs	r3, #1
+ 803ed3c:	e029      	b.n	803ed92 <UART_WaitOnFlagUntilTimeout+0xd2>
+        }
+        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
+ 803ed3e:	68fb      	ldr	r3, [r7, #12]
+ 803ed40:	681b      	ldr	r3, [r3, #0]
+ 803ed42:	69db      	ldr	r3, [r3, #28]
+ 803ed44:	f403 6300 	and.w	r3, r3, #2048	@ 0x800
+ 803ed48:	f5b3 6f00 	cmp.w	r3, #2048	@ 0x800
+ 803ed4c:	d111      	bne.n	803ed72 <UART_WaitOnFlagUntilTimeout+0xb2>
+        {
+          /* Clear Receiver Timeout flag*/
+          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
+ 803ed4e:	68fb      	ldr	r3, [r7, #12]
+ 803ed50:	681b      	ldr	r3, [r3, #0]
+ 803ed52:	f44f 6200 	mov.w	r2, #2048	@ 0x800
+ 803ed56:	621a      	str	r2, [r3, #32]
+
+          /* Blocking error : transfer is aborted
+          Set the UART state ready to be able to start again the process,
+          Disable Rx Interrupts if ongoing */
+          UART_EndRxTransfer(huart);
+ 803ed58:	68f8      	ldr	r0, [r7, #12]
+ 803ed5a:	f000 f983 	bl	803f064 <UART_EndRxTransfer>
+
+          huart->ErrorCode = HAL_UART_ERROR_RTO;
+ 803ed5e:	68fb      	ldr	r3, [r7, #12]
+ 803ed60:	2220      	movs	r2, #32
+ 803ed62:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(huart);
+ 803ed66:	68fb      	ldr	r3, [r7, #12]
+ 803ed68:	2200      	movs	r2, #0
+ 803ed6a:	f883 2084 	strb.w	r2, [r3, #132]	@ 0x84
+
+          return HAL_TIMEOUT;
+ 803ed6e:	2303      	movs	r3, #3
+ 803ed70:	e00f      	b.n	803ed92 <UART_WaitOnFlagUntilTimeout+0xd2>
+  while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
+ 803ed72:	68fb      	ldr	r3, [r7, #12]
+ 803ed74:	681b      	ldr	r3, [r3, #0]
+ 803ed76:	69da      	ldr	r2, [r3, #28]
+ 803ed78:	68bb      	ldr	r3, [r7, #8]
+ 803ed7a:	4013      	ands	r3, r2
+ 803ed7c:	68ba      	ldr	r2, [r7, #8]
+ 803ed7e:	429a      	cmp	r2, r3
+ 803ed80:	bf0c      	ite	eq
+ 803ed82:	2301      	moveq	r3, #1
+ 803ed84:	2300      	movne	r3, #0
+ 803ed86:	b2db      	uxtb	r3, r3
+ 803ed88:	461a      	mov	r2, r3
+ 803ed8a:	79fb      	ldrb	r3, [r7, #7]
+ 803ed8c:	429a      	cmp	r2, r3
+ 803ed8e:	d0a0      	beq.n	803ecd2 <UART_WaitOnFlagUntilTimeout+0x12>
+        }
+      }
+    }
+  }
+  return HAL_OK;
+ 803ed90:	2300      	movs	r3, #0
+}
+ 803ed92:	4618      	mov	r0, r3
+ 803ed94:	3710      	adds	r7, #16
+ 803ed96:	46bd      	mov	sp, r7
+ 803ed98:	bd80      	pop	{r7, pc}
+	...
+
+0803ed9c <UART_Start_Receive_IT>:
+  * @param  pData Pointer to data buffer (u8 or u16 data elements).
+  * @param  Size  Amount of data elements (u8 or u16) to be received.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+ 803ed9c:	b480      	push	{r7}
+ 803ed9e:	b0a3      	sub	sp, #140	@ 0x8c
+ 803eda0:	af00      	add	r7, sp, #0
+ 803eda2:	60f8      	str	r0, [r7, #12]
+ 803eda4:	60b9      	str	r1, [r7, #8]
+ 803eda6:	4613      	mov	r3, r2
+ 803eda8:	80fb      	strh	r3, [r7, #6]
+  huart->pRxBuffPtr  = pData;
+ 803edaa:	68fb      	ldr	r3, [r7, #12]
+ 803edac:	68ba      	ldr	r2, [r7, #8]
+ 803edae:	659a      	str	r2, [r3, #88]	@ 0x58
+  huart->RxXferSize  = Size;
+ 803edb0:	68fb      	ldr	r3, [r7, #12]
+ 803edb2:	88fa      	ldrh	r2, [r7, #6]
+ 803edb4:	f8a3 205c 	strh.w	r2, [r3, #92]	@ 0x5c
+  huart->RxXferCount = Size;
+ 803edb8:	68fb      	ldr	r3, [r7, #12]
+ 803edba:	88fa      	ldrh	r2, [r7, #6]
+ 803edbc:	f8a3 205e 	strh.w	r2, [r3, #94]	@ 0x5e
+  huart->RxISR       = NULL;
+ 803edc0:	68fb      	ldr	r3, [r7, #12]
+ 803edc2:	2200      	movs	r2, #0
+ 803edc4:	675a      	str	r2, [r3, #116]	@ 0x74
+
+  /* Computation of UART mask to apply to RDR register */
+  UART_MASK_COMPUTATION(huart);
+ 803edc6:	68fb      	ldr	r3, [r7, #12]
+ 803edc8:	689b      	ldr	r3, [r3, #8]
+ 803edca:	f5b3 5f80 	cmp.w	r3, #4096	@ 0x1000
+ 803edce:	d10e      	bne.n	803edee <UART_Start_Receive_IT+0x52>
+ 803edd0:	68fb      	ldr	r3, [r7, #12]
+ 803edd2:	691b      	ldr	r3, [r3, #16]
+ 803edd4:	2b00      	cmp	r3, #0
+ 803edd6:	d105      	bne.n	803ede4 <UART_Start_Receive_IT+0x48>
+ 803edd8:	68fb      	ldr	r3, [r7, #12]
+ 803edda:	f240 12ff 	movw	r2, #511	@ 0x1ff
+ 803edde:	f8a3 2060 	strh.w	r2, [r3, #96]	@ 0x60
+ 803ede2:	e02d      	b.n	803ee40 <UART_Start_Receive_IT+0xa4>
+ 803ede4:	68fb      	ldr	r3, [r7, #12]
+ 803ede6:	22ff      	movs	r2, #255	@ 0xff
+ 803ede8:	f8a3 2060 	strh.w	r2, [r3, #96]	@ 0x60
+ 803edec:	e028      	b.n	803ee40 <UART_Start_Receive_IT+0xa4>
+ 803edee:	68fb      	ldr	r3, [r7, #12]
+ 803edf0:	689b      	ldr	r3, [r3, #8]
+ 803edf2:	2b00      	cmp	r3, #0
+ 803edf4:	d10d      	bne.n	803ee12 <UART_Start_Receive_IT+0x76>
+ 803edf6:	68fb      	ldr	r3, [r7, #12]
+ 803edf8:	691b      	ldr	r3, [r3, #16]
+ 803edfa:	2b00      	cmp	r3, #0
+ 803edfc:	d104      	bne.n	803ee08 <UART_Start_Receive_IT+0x6c>
+ 803edfe:	68fb      	ldr	r3, [r7, #12]
+ 803ee00:	22ff      	movs	r2, #255	@ 0xff
+ 803ee02:	f8a3 2060 	strh.w	r2, [r3, #96]	@ 0x60
+ 803ee06:	e01b      	b.n	803ee40 <UART_Start_Receive_IT+0xa4>
+ 803ee08:	68fb      	ldr	r3, [r7, #12]
+ 803ee0a:	227f      	movs	r2, #127	@ 0x7f
+ 803ee0c:	f8a3 2060 	strh.w	r2, [r3, #96]	@ 0x60
+ 803ee10:	e016      	b.n	803ee40 <UART_Start_Receive_IT+0xa4>
+ 803ee12:	68fb      	ldr	r3, [r7, #12]
+ 803ee14:	689b      	ldr	r3, [r3, #8]
+ 803ee16:	f1b3 5f80 	cmp.w	r3, #268435456	@ 0x10000000
+ 803ee1a:	d10d      	bne.n	803ee38 <UART_Start_Receive_IT+0x9c>
+ 803ee1c:	68fb      	ldr	r3, [r7, #12]
+ 803ee1e:	691b      	ldr	r3, [r3, #16]
+ 803ee20:	2b00      	cmp	r3, #0
+ 803ee22:	d104      	bne.n	803ee2e <UART_Start_Receive_IT+0x92>
+ 803ee24:	68fb      	ldr	r3, [r7, #12]
+ 803ee26:	227f      	movs	r2, #127	@ 0x7f
+ 803ee28:	f8a3 2060 	strh.w	r2, [r3, #96]	@ 0x60
+ 803ee2c:	e008      	b.n	803ee40 <UART_Start_Receive_IT+0xa4>
+ 803ee2e:	68fb      	ldr	r3, [r7, #12]
+ 803ee30:	223f      	movs	r2, #63	@ 0x3f
+ 803ee32:	f8a3 2060 	strh.w	r2, [r3, #96]	@ 0x60
+ 803ee36:	e003      	b.n	803ee40 <UART_Start_Receive_IT+0xa4>
+ 803ee38:	68fb      	ldr	r3, [r7, #12]
+ 803ee3a:	2200      	movs	r2, #0
+ 803ee3c:	f8a3 2060 	strh.w	r2, [r3, #96]	@ 0x60
+
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+ 803ee40:	68fb      	ldr	r3, [r7, #12]
+ 803ee42:	2200      	movs	r2, #0
+ 803ee44:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90
+  huart->RxState = HAL_UART_STATE_BUSY_RX;
+ 803ee48:	68fb      	ldr	r3, [r7, #12]
+ 803ee4a:	2222      	movs	r2, #34	@ 0x22
+ 803ee4c:	f8c3 208c 	str.w	r2, [r3, #140]	@ 0x8c
+
+  /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+  ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ 803ee50:	68fb      	ldr	r3, [r7, #12]
+ 803ee52:	681b      	ldr	r3, [r3, #0]
+ 803ee54:	3308      	adds	r3, #8
+ 803ee56:	667b      	str	r3, [r7, #100]	@ 0x64
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ 803ee58:	6e7b      	ldr	r3, [r7, #100]	@ 0x64
+ 803ee5a:	e853 3f00 	ldrex	r3, [r3]
+ 803ee5e:	663b      	str	r3, [r7, #96]	@ 0x60
+   return(result);
+ 803ee60:	6e3b      	ldr	r3, [r7, #96]	@ 0x60
+ 803ee62:	f043 0301 	orr.w	r3, r3, #1
+ 803ee66:	f8c7 3084 	str.w	r3, [r7, #132]	@ 0x84
+ 803ee6a:	68fb      	ldr	r3, [r7, #12]
+ 803ee6c:	681b      	ldr	r3, [r3, #0]
+ 803ee6e:	3308      	adds	r3, #8
+ 803ee70:	f8d7 2084 	ldr.w	r2, [r7, #132]	@ 0x84
+ 803ee74:	673a      	str	r2, [r7, #112]	@ 0x70
+ 803ee76:	66fb      	str	r3, [r7, #108]	@ 0x6c
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ 803ee78:	6ef9      	ldr	r1, [r7, #108]	@ 0x6c
+ 803ee7a:	6f3a      	ldr	r2, [r7, #112]	@ 0x70
+ 803ee7c:	e841 2300 	strex	r3, r2, [r1]
+ 803ee80:	66bb      	str	r3, [r7, #104]	@ 0x68
+   return(result);
+ 803ee82:	6ebb      	ldr	r3, [r7, #104]	@ 0x68
+ 803ee84:	2b00      	cmp	r3, #0
+ 803ee86:	d1e3      	bne.n	803ee50 <UART_Start_Receive_IT+0xb4>
+
+  /* Configure Rx interrupt processing */
+  if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess))
+ 803ee88:	68fb      	ldr	r3, [r7, #12]
+ 803ee8a:	6e5b      	ldr	r3, [r3, #100]	@ 0x64
+ 803ee8c:	f1b3 5f00 	cmp.w	r3, #536870912	@ 0x20000000
+ 803ee90:	d14f      	bne.n	803ef32 <UART_Start_Receive_IT+0x196>
+ 803ee92:	68fb      	ldr	r3, [r7, #12]
+ 803ee94:	f8b3 3068 	ldrh.w	r3, [r3, #104]	@ 0x68
+ 803ee98:	88fa      	ldrh	r2, [r7, #6]
+ 803ee9a:	429a      	cmp	r2, r3
+ 803ee9c:	d349      	bcc.n	803ef32 <UART_Start_Receive_IT+0x196>
+  {
+    /* Set the Rx ISR function pointer according to the data word length */
+    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ 803ee9e:	68fb      	ldr	r3, [r7, #12]
+ 803eea0:	689b      	ldr	r3, [r3, #8]
+ 803eea2:	f5b3 5f80 	cmp.w	r3, #4096	@ 0x1000
+ 803eea6:	d107      	bne.n	803eeb8 <UART_Start_Receive_IT+0x11c>
+ 803eea8:	68fb      	ldr	r3, [r7, #12]
+ 803eeaa:	691b      	ldr	r3, [r3, #16]
+ 803eeac:	2b00      	cmp	r3, #0
+ 803eeae:	d103      	bne.n	803eeb8 <UART_Start_Receive_IT+0x11c>
+    {
+      huart->RxISR = UART_RxISR_16BIT_FIFOEN;
+ 803eeb0:	68fb      	ldr	r3, [r7, #12]
+ 803eeb2:	4a47      	ldr	r2, [pc, #284]	@ (803efd0 <UART_Start_Receive_IT+0x234>)
+ 803eeb4:	675a      	str	r2, [r3, #116]	@ 0x74
+ 803eeb6:	e002      	b.n	803eebe <UART_Start_Receive_IT+0x122>
+    }
+    else
+    {
+      huart->RxISR = UART_RxISR_8BIT_FIFOEN;
+ 803eeb8:	68fb      	ldr	r3, [r7, #12]
+ 803eeba:	4a46      	ldr	r2, [pc, #280]	@ (803efd4 <UART_Start_Receive_IT+0x238>)
+ 803eebc:	675a      	str	r2, [r3, #116]	@ 0x74
+    }
+
+    /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */
+    if (huart->Init.Parity != UART_PARITY_NONE)
+ 803eebe:	68fb      	ldr	r3, [r7, #12]
+ 803eec0:	691b      	ldr	r3, [r3, #16]
+ 803eec2:	2b00      	cmp	r3, #0
+ 803eec4:	d01a      	beq.n	803eefc <UART_Start_Receive_IT+0x160>
+    {
+      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ 803eec6:	68fb      	ldr	r3, [r7, #12]
+ 803eec8:	681b      	ldr	r3, [r3, #0]
+ 803eeca:	653b      	str	r3, [r7, #80]	@ 0x50
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ 803eecc:	6d3b      	ldr	r3, [r7, #80]	@ 0x50
+ 803eece:	e853 3f00 	ldrex	r3, [r3]
+ 803eed2:	64fb      	str	r3, [r7, #76]	@ 0x4c
+   return(result);
+ 803eed4:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
+ 803eed6:	f443 7380 	orr.w	r3, r3, #256	@ 0x100
+ 803eeda:	f8c7 3080 	str.w	r3, [r7, #128]	@ 0x80
+ 803eede:	68fb      	ldr	r3, [r7, #12]
+ 803eee0:	681b      	ldr	r3, [r3, #0]
+ 803eee2:	461a      	mov	r2, r3
+ 803eee4:	f8d7 3080 	ldr.w	r3, [r7, #128]	@ 0x80
+ 803eee8:	65fb      	str	r3, [r7, #92]	@ 0x5c
+ 803eeea:	65ba      	str	r2, [r7, #88]	@ 0x58
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ 803eeec:	6db9      	ldr	r1, [r7, #88]	@ 0x58
+ 803eeee:	6dfa      	ldr	r2, [r7, #92]	@ 0x5c
+ 803eef0:	e841 2300 	strex	r3, r2, [r1]
+ 803eef4:	657b      	str	r3, [r7, #84]	@ 0x54
+   return(result);
+ 803eef6:	6d7b      	ldr	r3, [r7, #84]	@ 0x54
+ 803eef8:	2b00      	cmp	r3, #0
+ 803eefa:	d1e4      	bne.n	803eec6 <UART_Start_Receive_IT+0x12a>
+    }
+    ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
+ 803eefc:	68fb      	ldr	r3, [r7, #12]
+ 803eefe:	681b      	ldr	r3, [r3, #0]
+ 803ef00:	3308      	adds	r3, #8
+ 803ef02:	63fb      	str	r3, [r7, #60]	@ 0x3c
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ 803ef04:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
+ 803ef06:	e853 3f00 	ldrex	r3, [r3]
+ 803ef0a:	63bb      	str	r3, [r7, #56]	@ 0x38
+   return(result);
+ 803ef0c:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 803ef0e:	f043 5380 	orr.w	r3, r3, #268435456	@ 0x10000000
+ 803ef12:	67fb      	str	r3, [r7, #124]	@ 0x7c
+ 803ef14:	68fb      	ldr	r3, [r7, #12]
+ 803ef16:	681b      	ldr	r3, [r3, #0]
+ 803ef18:	3308      	adds	r3, #8
+ 803ef1a:	6ffa      	ldr	r2, [r7, #124]	@ 0x7c
+ 803ef1c:	64ba      	str	r2, [r7, #72]	@ 0x48
+ 803ef1e:	647b      	str	r3, [r7, #68]	@ 0x44
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ 803ef20:	6c79      	ldr	r1, [r7, #68]	@ 0x44
+ 803ef22:	6cba      	ldr	r2, [r7, #72]	@ 0x48
+ 803ef24:	e841 2300 	strex	r3, r2, [r1]
+ 803ef28:	643b      	str	r3, [r7, #64]	@ 0x40
+   return(result);
+ 803ef2a:	6c3b      	ldr	r3, [r7, #64]	@ 0x40
+ 803ef2c:	2b00      	cmp	r3, #0
+ 803ef2e:	d1e5      	bne.n	803eefc <UART_Start_Receive_IT+0x160>
+ 803ef30:	e046      	b.n	803efc0 <UART_Start_Receive_IT+0x224>
+  }
+  else
+  {
+    /* Set the Rx ISR function pointer according to the data word length */
+    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ 803ef32:	68fb      	ldr	r3, [r7, #12]
+ 803ef34:	689b      	ldr	r3, [r3, #8]
+ 803ef36:	f5b3 5f80 	cmp.w	r3, #4096	@ 0x1000
+ 803ef3a:	d107      	bne.n	803ef4c <UART_Start_Receive_IT+0x1b0>
+ 803ef3c:	68fb      	ldr	r3, [r7, #12]
+ 803ef3e:	691b      	ldr	r3, [r3, #16]
+ 803ef40:	2b00      	cmp	r3, #0
+ 803ef42:	d103      	bne.n	803ef4c <UART_Start_Receive_IT+0x1b0>
+    {
+      huart->RxISR = UART_RxISR_16BIT;
+ 803ef44:	68fb      	ldr	r3, [r7, #12]
+ 803ef46:	4a24      	ldr	r2, [pc, #144]	@ (803efd8 <UART_Start_Receive_IT+0x23c>)
+ 803ef48:	675a      	str	r2, [r3, #116]	@ 0x74
+ 803ef4a:	e002      	b.n	803ef52 <UART_Start_Receive_IT+0x1b6>
+    }
+    else
+    {
+      huart->RxISR = UART_RxISR_8BIT;
+ 803ef4c:	68fb      	ldr	r3, [r7, #12]
+ 803ef4e:	4a23      	ldr	r2, [pc, #140]	@ (803efdc <UART_Start_Receive_IT+0x240>)
+ 803ef50:	675a      	str	r2, [r3, #116]	@ 0x74
+    }
+
+    /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
+    if (huart->Init.Parity != UART_PARITY_NONE)
+ 803ef52:	68fb      	ldr	r3, [r7, #12]
+ 803ef54:	691b      	ldr	r3, [r3, #16]
+ 803ef56:	2b00      	cmp	r3, #0
+ 803ef58:	d019      	beq.n	803ef8e <UART_Start_Receive_IT+0x1f2>
+    {
+      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
+ 803ef5a:	68fb      	ldr	r3, [r7, #12]
+ 803ef5c:	681b      	ldr	r3, [r3, #0]
+ 803ef5e:	62bb      	str	r3, [r7, #40]	@ 0x28
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ 803ef60:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 803ef62:	e853 3f00 	ldrex	r3, [r3]
+ 803ef66:	627b      	str	r3, [r7, #36]	@ 0x24
+   return(result);
+ 803ef68:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 803ef6a:	f443 7390 	orr.w	r3, r3, #288	@ 0x120
+ 803ef6e:	677b      	str	r3, [r7, #116]	@ 0x74
+ 803ef70:	68fb      	ldr	r3, [r7, #12]
+ 803ef72:	681b      	ldr	r3, [r3, #0]
+ 803ef74:	461a      	mov	r2, r3
+ 803ef76:	6f7b      	ldr	r3, [r7, #116]	@ 0x74
+ 803ef78:	637b      	str	r3, [r7, #52]	@ 0x34
+ 803ef7a:	633a      	str	r2, [r7, #48]	@ 0x30
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ 803ef7c:	6b39      	ldr	r1, [r7, #48]	@ 0x30
+ 803ef7e:	6b7a      	ldr	r2, [r7, #52]	@ 0x34
+ 803ef80:	e841 2300 	strex	r3, r2, [r1]
+ 803ef84:	62fb      	str	r3, [r7, #44]	@ 0x2c
+   return(result);
+ 803ef86:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
+ 803ef88:	2b00      	cmp	r3, #0
+ 803ef8a:	d1e6      	bne.n	803ef5a <UART_Start_Receive_IT+0x1be>
+ 803ef8c:	e018      	b.n	803efc0 <UART_Start_Receive_IT+0x224>
+    }
+    else
+    {
+      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+ 803ef8e:	68fb      	ldr	r3, [r7, #12]
+ 803ef90:	681b      	ldr	r3, [r3, #0]
+ 803ef92:	617b      	str	r3, [r7, #20]
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ 803ef94:	697b      	ldr	r3, [r7, #20]
+ 803ef96:	e853 3f00 	ldrex	r3, [r3]
+ 803ef9a:	613b      	str	r3, [r7, #16]
+   return(result);
+ 803ef9c:	693b      	ldr	r3, [r7, #16]
+ 803ef9e:	f043 0320 	orr.w	r3, r3, #32
+ 803efa2:	67bb      	str	r3, [r7, #120]	@ 0x78
+ 803efa4:	68fb      	ldr	r3, [r7, #12]
+ 803efa6:	681b      	ldr	r3, [r3, #0]
+ 803efa8:	461a      	mov	r2, r3
+ 803efaa:	6fbb      	ldr	r3, [r7, #120]	@ 0x78
+ 803efac:	623b      	str	r3, [r7, #32]
+ 803efae:	61fa      	str	r2, [r7, #28]
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ 803efb0:	69f9      	ldr	r1, [r7, #28]
+ 803efb2:	6a3a      	ldr	r2, [r7, #32]
+ 803efb4:	e841 2300 	strex	r3, r2, [r1]
+ 803efb8:	61bb      	str	r3, [r7, #24]
+   return(result);
+ 803efba:	69bb      	ldr	r3, [r7, #24]
+ 803efbc:	2b00      	cmp	r3, #0
+ 803efbe:	d1e6      	bne.n	803ef8e <UART_Start_Receive_IT+0x1f2>
+    }
+  }
+  return HAL_OK;
+ 803efc0:	2300      	movs	r3, #0
+}
+ 803efc2:	4618      	mov	r0, r3
+ 803efc4:	378c      	adds	r7, #140	@ 0x8c
+ 803efc6:	46bd      	mov	sp, r7
+ 803efc8:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 803efcc:	4770      	bx	lr
+ 803efce:	bf00      	nop
+ 803efd0:	0803f9b5 	.word	0x0803f9b5
+ 803efd4:	0803f655 	.word	0x0803f655
+ 803efd8:	0803f49d 	.word	0x0803f49d
+ 803efdc:	0803f2e5 	.word	0x0803f2e5
+
+0803efe0 <UART_EndTxTransfer>:
+  * @brief  End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
+  * @param  huart UART handle.
+  * @retval None
+  */
+static void UART_EndTxTransfer(UART_HandleTypeDef *huart)
+{
+ 803efe0:	b480      	push	{r7}
+ 803efe2:	b08f      	sub	sp, #60	@ 0x3c
+ 803efe4:	af00      	add	r7, sp, #0
+ 803efe6:	6078      	str	r0, [r7, #4]
+  /* Disable TXEIE, TCIE, TXFT interrupts */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+ 803efe8:	687b      	ldr	r3, [r7, #4]
+ 803efea:	681b      	ldr	r3, [r3, #0]
+ 803efec:	623b      	str	r3, [r7, #32]
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ 803efee:	6a3b      	ldr	r3, [r7, #32]
+ 803eff0:	e853 3f00 	ldrex	r3, [r3]
+ 803eff4:	61fb      	str	r3, [r7, #28]
+   return(result);
+ 803eff6:	69fb      	ldr	r3, [r7, #28]
+ 803eff8:	f023 03c0 	bic.w	r3, r3, #192	@ 0xc0
+ 803effc:	637b      	str	r3, [r7, #52]	@ 0x34
+ 803effe:	687b      	ldr	r3, [r7, #4]
+ 803f000:	681b      	ldr	r3, [r3, #0]
+ 803f002:	461a      	mov	r2, r3
+ 803f004:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
+ 803f006:	62fb      	str	r3, [r7, #44]	@ 0x2c
+ 803f008:	62ba      	str	r2, [r7, #40]	@ 0x28
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ 803f00a:	6ab9      	ldr	r1, [r7, #40]	@ 0x28
+ 803f00c:	6afa      	ldr	r2, [r7, #44]	@ 0x2c
+ 803f00e:	e841 2300 	strex	r3, r2, [r1]
+ 803f012:	627b      	str	r3, [r7, #36]	@ 0x24
+   return(result);
+ 803f014:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 803f016:	2b00      	cmp	r3, #0
+ 803f018:	d1e6      	bne.n	803efe8 <UART_EndTxTransfer+0x8>
+  ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE));
+ 803f01a:	687b      	ldr	r3, [r7, #4]
+ 803f01c:	681b      	ldr	r3, [r3, #0]
+ 803f01e:	3308      	adds	r3, #8
+ 803f020:	60fb      	str	r3, [r7, #12]
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ 803f022:	68fb      	ldr	r3, [r7, #12]
+ 803f024:	e853 3f00 	ldrex	r3, [r3]
+ 803f028:	60bb      	str	r3, [r7, #8]
+   return(result);
+ 803f02a:	68bb      	ldr	r3, [r7, #8]
+ 803f02c:	f423 0300 	bic.w	r3, r3, #8388608	@ 0x800000
+ 803f030:	633b      	str	r3, [r7, #48]	@ 0x30
+ 803f032:	687b      	ldr	r3, [r7, #4]
+ 803f034:	681b      	ldr	r3, [r3, #0]
+ 803f036:	3308      	adds	r3, #8
+ 803f038:	6b3a      	ldr	r2, [r7, #48]	@ 0x30
+ 803f03a:	61ba      	str	r2, [r7, #24]
+ 803f03c:	617b      	str	r3, [r7, #20]
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ 803f03e:	6979      	ldr	r1, [r7, #20]
+ 803f040:	69ba      	ldr	r2, [r7, #24]
+ 803f042:	e841 2300 	strex	r3, r2, [r1]
+ 803f046:	613b      	str	r3, [r7, #16]
+   return(result);
+ 803f048:	693b      	ldr	r3, [r7, #16]
+ 803f04a:	2b00      	cmp	r3, #0
+ 803f04c:	d1e5      	bne.n	803f01a <UART_EndTxTransfer+0x3a>
+
+  /* At end of Tx process, restore huart->gState to Ready */
+  huart->gState = HAL_UART_STATE_READY;
+ 803f04e:	687b      	ldr	r3, [r7, #4]
+ 803f050:	2220      	movs	r2, #32
+ 803f052:	f8c3 2088 	str.w	r2, [r3, #136]	@ 0x88
+}
+ 803f056:	bf00      	nop
+ 803f058:	373c      	adds	r7, #60	@ 0x3c
+ 803f05a:	46bd      	mov	sp, r7
+ 803f05c:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 803f060:	4770      	bx	lr
+	...
+
+0803f064 <UART_EndRxTransfer>:
+  * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
+  * @param  huart UART handle.
+  * @retval None
+  */
+static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
+{
+ 803f064:	b480      	push	{r7}
+ 803f066:	b095      	sub	sp, #84	@ 0x54
+ 803f068:	af00      	add	r7, sp, #0
+ 803f06a:	6078      	str	r0, [r7, #4]
+  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+ 803f06c:	687b      	ldr	r3, [r7, #4]
+ 803f06e:	681b      	ldr	r3, [r3, #0]
+ 803f070:	637b      	str	r3, [r7, #52]	@ 0x34
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ 803f072:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
+ 803f074:	e853 3f00 	ldrex	r3, [r3]
+ 803f078:	633b      	str	r3, [r7, #48]	@ 0x30
+   return(result);
+ 803f07a:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
+ 803f07c:	f423 7390 	bic.w	r3, r3, #288	@ 0x120
+ 803f080:	64fb      	str	r3, [r7, #76]	@ 0x4c
+ 803f082:	687b      	ldr	r3, [r7, #4]
+ 803f084:	681b      	ldr	r3, [r3, #0]
+ 803f086:	461a      	mov	r2, r3
+ 803f088:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
+ 803f08a:	643b      	str	r3, [r7, #64]	@ 0x40
+ 803f08c:	63fa      	str	r2, [r7, #60]	@ 0x3c
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ 803f08e:	6bf9      	ldr	r1, [r7, #60]	@ 0x3c
+ 803f090:	6c3a      	ldr	r2, [r7, #64]	@ 0x40
+ 803f092:	e841 2300 	strex	r3, r2, [r1]
+ 803f096:	63bb      	str	r3, [r7, #56]	@ 0x38
+   return(result);
+ 803f098:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 803f09a:	2b00      	cmp	r3, #0
+ 803f09c:	d1e6      	bne.n	803f06c <UART_EndRxTransfer+0x8>
+  ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+ 803f09e:	687b      	ldr	r3, [r7, #4]
+ 803f0a0:	681b      	ldr	r3, [r3, #0]
+ 803f0a2:	3308      	adds	r3, #8
+ 803f0a4:	623b      	str	r3, [r7, #32]
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ 803f0a6:	6a3b      	ldr	r3, [r7, #32]
+ 803f0a8:	e853 3f00 	ldrex	r3, [r3]
+ 803f0ac:	61fb      	str	r3, [r7, #28]
+   return(result);
+ 803f0ae:	69fa      	ldr	r2, [r7, #28]
+ 803f0b0:	4b1e      	ldr	r3, [pc, #120]	@ (803f12c <UART_EndRxTransfer+0xc8>)
+ 803f0b2:	4013      	ands	r3, r2
+ 803f0b4:	64bb      	str	r3, [r7, #72]	@ 0x48
+ 803f0b6:	687b      	ldr	r3, [r7, #4]
+ 803f0b8:	681b      	ldr	r3, [r3, #0]
+ 803f0ba:	3308      	adds	r3, #8
+ 803f0bc:	6cba      	ldr	r2, [r7, #72]	@ 0x48
+ 803f0be:	62fa      	str	r2, [r7, #44]	@ 0x2c
+ 803f0c0:	62bb      	str	r3, [r7, #40]	@ 0x28
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ 803f0c2:	6ab9      	ldr	r1, [r7, #40]	@ 0x28
+ 803f0c4:	6afa      	ldr	r2, [r7, #44]	@ 0x2c
+ 803f0c6:	e841 2300 	strex	r3, r2, [r1]
+ 803f0ca:	627b      	str	r3, [r7, #36]	@ 0x24
+   return(result);
+ 803f0cc:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 803f0ce:	2b00      	cmp	r3, #0
+ 803f0d0:	d1e5      	bne.n	803f09e <UART_EndRxTransfer+0x3a>
+
+  /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
+  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ 803f0d2:	687b      	ldr	r3, [r7, #4]
+ 803f0d4:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
+ 803f0d6:	2b01      	cmp	r3, #1
+ 803f0d8:	d118      	bne.n	803f10c <UART_EndRxTransfer+0xa8>
+  {
+    ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ 803f0da:	687b      	ldr	r3, [r7, #4]
+ 803f0dc:	681b      	ldr	r3, [r3, #0]
+ 803f0de:	60fb      	str	r3, [r7, #12]
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ 803f0e0:	68fb      	ldr	r3, [r7, #12]
+ 803f0e2:	e853 3f00 	ldrex	r3, [r3]
+ 803f0e6:	60bb      	str	r3, [r7, #8]
+   return(result);
+ 803f0e8:	68bb      	ldr	r3, [r7, #8]
+ 803f0ea:	f023 0310 	bic.w	r3, r3, #16
+ 803f0ee:	647b      	str	r3, [r7, #68]	@ 0x44
+ 803f0f0:	687b      	ldr	r3, [r7, #4]
+ 803f0f2:	681b      	ldr	r3, [r3, #0]
+ 803f0f4:	461a      	mov	r2, r3
+ 803f0f6:	6c7b      	ldr	r3, [r7, #68]	@ 0x44
+ 803f0f8:	61bb      	str	r3, [r7, #24]
+ 803f0fa:	617a      	str	r2, [r7, #20]
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ 803f0fc:	6979      	ldr	r1, [r7, #20]
+ 803f0fe:	69ba      	ldr	r2, [r7, #24]
+ 803f100:	e841 2300 	strex	r3, r2, [r1]
+ 803f104:	613b      	str	r3, [r7, #16]
+   return(result);
+ 803f106:	693b      	ldr	r3, [r7, #16]
+ 803f108:	2b00      	cmp	r3, #0
+ 803f10a:	d1e6      	bne.n	803f0da <UART_EndRxTransfer+0x76>
+  }
+
+  /* At end of Rx process, restore huart->RxState to Ready */
+  huart->RxState = HAL_UART_STATE_READY;
+ 803f10c:	687b      	ldr	r3, [r7, #4]
+ 803f10e:	2220      	movs	r2, #32
+ 803f110:	f8c3 208c 	str.w	r2, [r3, #140]	@ 0x8c
+  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ 803f114:	687b      	ldr	r3, [r7, #4]
+ 803f116:	2200      	movs	r2, #0
+ 803f118:	66da      	str	r2, [r3, #108]	@ 0x6c
+
+  /* Reset RxIsr function pointer */
+  huart->RxISR = NULL;
+ 803f11a:	687b      	ldr	r3, [r7, #4]
+ 803f11c:	2200      	movs	r2, #0
+ 803f11e:	675a      	str	r2, [r3, #116]	@ 0x74
+}
+ 803f120:	bf00      	nop
+ 803f122:	3754      	adds	r7, #84	@ 0x54
+ 803f124:	46bd      	mov	sp, r7
+ 803f126:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 803f12a:	4770      	bx	lr
+ 803f12c:	effffffe 	.word	0xeffffffe
+
+0803f130 <UART_DMATransmitCplt>:
+  * @brief DMA UART transmit process complete callback.
+  * @param hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ 803f130:	b580      	push	{r7, lr}
+ 803f132:	b090      	sub	sp, #64	@ 0x40
+ 803f134:	af00      	add	r7, sp, #0
+ 803f136:	6078      	str	r0, [r7, #4]
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+ 803f138:	687b      	ldr	r3, [r7, #4]
+ 803f13a:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
+ 803f13c:	63fb      	str	r3, [r7, #60]	@ 0x3c
+
+  /* DMA Normal mode */
+  if (hdma->Init.Mode != DMA_CIRCULAR)
+ 803f13e:	687b      	ldr	r3, [r7, #4]
+ 803f140:	69db      	ldr	r3, [r3, #28]
+ 803f142:	f5b3 7f80 	cmp.w	r3, #256	@ 0x100
+ 803f146:	d037      	beq.n	803f1b8 <UART_DMATransmitCplt+0x88>
+  {
+    huart->TxXferCount = 0U;
+ 803f148:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
+ 803f14a:	2200      	movs	r2, #0
+ 803f14c:	f8a3 2056 	strh.w	r2, [r3, #86]	@ 0x56
+
+    /* Disable the DMA transfer for transmit request by resetting the DMAT bit
+       in the UART CR3 register */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+ 803f150:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
+ 803f152:	681b      	ldr	r3, [r3, #0]
+ 803f154:	3308      	adds	r3, #8
+ 803f156:	627b      	str	r3, [r7, #36]	@ 0x24
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ 803f158:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 803f15a:	e853 3f00 	ldrex	r3, [r3]
+ 803f15e:	623b      	str	r3, [r7, #32]
+   return(result);
+ 803f160:	6a3b      	ldr	r3, [r7, #32]
+ 803f162:	f023 0380 	bic.w	r3, r3, #128	@ 0x80
+ 803f166:	63bb      	str	r3, [r7, #56]	@ 0x38
+ 803f168:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
+ 803f16a:	681b      	ldr	r3, [r3, #0]
+ 803f16c:	3308      	adds	r3, #8
+ 803f16e:	6bba      	ldr	r2, [r7, #56]	@ 0x38
+ 803f170:	633a      	str	r2, [r7, #48]	@ 0x30
+ 803f172:	62fb      	str	r3, [r7, #44]	@ 0x2c
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ 803f174:	6af9      	ldr	r1, [r7, #44]	@ 0x2c
+ 803f176:	6b3a      	ldr	r2, [r7, #48]	@ 0x30
+ 803f178:	e841 2300 	strex	r3, r2, [r1]
+ 803f17c:	62bb      	str	r3, [r7, #40]	@ 0x28
+   return(result);
+ 803f17e:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 803f180:	2b00      	cmp	r3, #0
+ 803f182:	d1e5      	bne.n	803f150 <UART_DMATransmitCplt+0x20>
+
+    /* Enable the UART Transmit Complete Interrupt */
+    ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+ 803f184:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
+ 803f186:	681b      	ldr	r3, [r3, #0]
+ 803f188:	613b      	str	r3, [r7, #16]
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ 803f18a:	693b      	ldr	r3, [r7, #16]
+ 803f18c:	e853 3f00 	ldrex	r3, [r3]
+ 803f190:	60fb      	str	r3, [r7, #12]
+   return(result);
+ 803f192:	68fb      	ldr	r3, [r7, #12]
+ 803f194:	f043 0340 	orr.w	r3, r3, #64	@ 0x40
+ 803f198:	637b      	str	r3, [r7, #52]	@ 0x34
+ 803f19a:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
+ 803f19c:	681b      	ldr	r3, [r3, #0]
+ 803f19e:	461a      	mov	r2, r3
+ 803f1a0:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
+ 803f1a2:	61fb      	str	r3, [r7, #28]
+ 803f1a4:	61ba      	str	r2, [r7, #24]
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ 803f1a6:	69b9      	ldr	r1, [r7, #24]
+ 803f1a8:	69fa      	ldr	r2, [r7, #28]
+ 803f1aa:	e841 2300 	strex	r3, r2, [r1]
+ 803f1ae:	617b      	str	r3, [r7, #20]
+   return(result);
+ 803f1b0:	697b      	ldr	r3, [r7, #20]
+ 803f1b2:	2b00      	cmp	r3, #0
+ 803f1b4:	d1e6      	bne.n	803f184 <UART_DMATransmitCplt+0x54>
+#else
+    /*Call legacy weak Tx complete callback*/
+    HAL_UART_TxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+  }
+}
+ 803f1b6:	e002      	b.n	803f1be <UART_DMATransmitCplt+0x8e>
+    HAL_UART_TxCpltCallback(huart);
+ 803f1b8:	6bf8      	ldr	r0, [r7, #60]	@ 0x3c
+ 803f1ba:	f7e2 fd7b 	bl	8021cb4 <HAL_UART_TxCpltCallback>
+}
+ 803f1be:	bf00      	nop
+ 803f1c0:	3740      	adds	r7, #64	@ 0x40
+ 803f1c2:	46bd      	mov	sp, r7
+ 803f1c4:	bd80      	pop	{r7, pc}
+
+0803f1c6 <UART_DMATxHalfCplt>:
+  * @brief DMA UART transmit process half complete callback.
+  * @param hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ 803f1c6:	b580      	push	{r7, lr}
+ 803f1c8:	b084      	sub	sp, #16
+ 803f1ca:	af00      	add	r7, sp, #0
+ 803f1cc:	6078      	str	r0, [r7, #4]
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+ 803f1ce:	687b      	ldr	r3, [r7, #4]
+ 803f1d0:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
+ 803f1d2:	60fb      	str	r3, [r7, #12]
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /*Call registered Tx Half complete callback*/
+  huart->TxHalfCpltCallback(huart);
+#else
+  /*Call legacy weak Tx Half complete callback*/
+  HAL_UART_TxHalfCpltCallback(huart);
+ 803f1d4:	68f8      	ldr	r0, [r7, #12]
+ 803f1d6:	f7fe fe9f 	bl	803df18 <HAL_UART_TxHalfCpltCallback>
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+ 803f1da:	bf00      	nop
+ 803f1dc:	3710      	adds	r7, #16
+ 803f1de:	46bd      	mov	sp, r7
+ 803f1e0:	bd80      	pop	{r7, pc}
+
+0803f1e2 <UART_DMAError>:
+  * @brief DMA UART communication error callback.
+  * @param hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMAError(DMA_HandleTypeDef *hdma)
+{
+ 803f1e2:	b580      	push	{r7, lr}
+ 803f1e4:	b086      	sub	sp, #24
+ 803f1e6:	af00      	add	r7, sp, #0
+ 803f1e8:	6078      	str	r0, [r7, #4]
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+ 803f1ea:	687b      	ldr	r3, [r7, #4]
+ 803f1ec:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
+ 803f1ee:	617b      	str	r3, [r7, #20]
+
+  const HAL_UART_StateTypeDef gstate = huart->gState;
+ 803f1f0:	697b      	ldr	r3, [r7, #20]
+ 803f1f2:	f8d3 3088 	ldr.w	r3, [r3, #136]	@ 0x88
+ 803f1f6:	613b      	str	r3, [r7, #16]
+  const HAL_UART_StateTypeDef rxstate = huart->RxState;
+ 803f1f8:	697b      	ldr	r3, [r7, #20]
+ 803f1fa:	f8d3 308c 	ldr.w	r3, [r3, #140]	@ 0x8c
+ 803f1fe:	60fb      	str	r3, [r7, #12]
+
+  /* Stop UART DMA Tx request if ongoing */
+  if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
+ 803f200:	697b      	ldr	r3, [r7, #20]
+ 803f202:	681b      	ldr	r3, [r3, #0]
+ 803f204:	689b      	ldr	r3, [r3, #8]
+ 803f206:	f003 0380 	and.w	r3, r3, #128	@ 0x80
+ 803f20a:	2b80      	cmp	r3, #128	@ 0x80
+ 803f20c:	d109      	bne.n	803f222 <UART_DMAError+0x40>
+ 803f20e:	693b      	ldr	r3, [r7, #16]
+ 803f210:	2b21      	cmp	r3, #33	@ 0x21
+ 803f212:	d106      	bne.n	803f222 <UART_DMAError+0x40>
+      (gstate == HAL_UART_STATE_BUSY_TX))
+  {
+    huart->TxXferCount = 0U;
+ 803f214:	697b      	ldr	r3, [r7, #20]
+ 803f216:	2200      	movs	r2, #0
+ 803f218:	f8a3 2056 	strh.w	r2, [r3, #86]	@ 0x56
+    UART_EndTxTransfer(huart);
+ 803f21c:	6978      	ldr	r0, [r7, #20]
+ 803f21e:	f7ff fedf 	bl	803efe0 <UART_EndTxTransfer>
+  }
+
+  /* Stop UART DMA Rx request if ongoing */
+  if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
+ 803f222:	697b      	ldr	r3, [r7, #20]
+ 803f224:	681b      	ldr	r3, [r3, #0]
+ 803f226:	689b      	ldr	r3, [r3, #8]
+ 803f228:	f003 0340 	and.w	r3, r3, #64	@ 0x40
+ 803f22c:	2b40      	cmp	r3, #64	@ 0x40
+ 803f22e:	d109      	bne.n	803f244 <UART_DMAError+0x62>
+ 803f230:	68fb      	ldr	r3, [r7, #12]
+ 803f232:	2b22      	cmp	r3, #34	@ 0x22
+ 803f234:	d106      	bne.n	803f244 <UART_DMAError+0x62>
+      (rxstate == HAL_UART_STATE_BUSY_RX))
+  {
+    huart->RxXferCount = 0U;
+ 803f236:	697b      	ldr	r3, [r7, #20]
+ 803f238:	2200      	movs	r2, #0
+ 803f23a:	f8a3 205e 	strh.w	r2, [r3, #94]	@ 0x5e
+    UART_EndRxTransfer(huart);
+ 803f23e:	6978      	ldr	r0, [r7, #20]
+ 803f240:	f7ff ff10 	bl	803f064 <UART_EndRxTransfer>
+  }
+
+  huart->ErrorCode |= HAL_UART_ERROR_DMA;
+ 803f244:	697b      	ldr	r3, [r7, #20]
+ 803f246:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
+ 803f24a:	f043 0210 	orr.w	r2, r3, #16
+ 803f24e:	697b      	ldr	r3, [r7, #20]
+ 803f250:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /*Call registered error callback*/
+  huart->ErrorCallback(huart);
+#else
+  /*Call legacy weak error callback*/
+  HAL_UART_ErrorCallback(huart);
+ 803f254:	6978      	ldr	r0, [r7, #20]
+ 803f256:	f7fe fe69 	bl	803df2c <HAL_UART_ErrorCallback>
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+ 803f25a:	bf00      	nop
+ 803f25c:	3718      	adds	r7, #24
+ 803f25e:	46bd      	mov	sp, r7
+ 803f260:	bd80      	pop	{r7, pc}
+
+0803f262 <UART_DMAAbortOnError>:
+  *         (To be called at end of DMA Abort procedure following error occurrence).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+ 803f262:	b580      	push	{r7, lr}
+ 803f264:	b084      	sub	sp, #16
+ 803f266:	af00      	add	r7, sp, #0
+ 803f268:	6078      	str	r0, [r7, #4]
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+ 803f26a:	687b      	ldr	r3, [r7, #4]
+ 803f26c:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
+ 803f26e:	60fb      	str	r3, [r7, #12]
+  huart->RxXferCount = 0U;
+ 803f270:	68fb      	ldr	r3, [r7, #12]
+ 803f272:	2200      	movs	r2, #0
+ 803f274:	f8a3 205e 	strh.w	r2, [r3, #94]	@ 0x5e
+  huart->TxXferCount = 0U;
+ 803f278:	68fb      	ldr	r3, [r7, #12]
+ 803f27a:	2200      	movs	r2, #0
+ 803f27c:	f8a3 2056 	strh.w	r2, [r3, #86]	@ 0x56
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /*Call registered error callback*/
+  huart->ErrorCallback(huart);
+#else
+  /*Call legacy weak error callback*/
+  HAL_UART_ErrorCallback(huart);
+ 803f280:	68f8      	ldr	r0, [r7, #12]
+ 803f282:	f7fe fe53 	bl	803df2c <HAL_UART_ErrorCallback>
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+ 803f286:	bf00      	nop
+ 803f288:	3710      	adds	r7, #16
+ 803f28a:	46bd      	mov	sp, r7
+ 803f28c:	bd80      	pop	{r7, pc}
+
+0803f28e <UART_EndTransmit_IT>:
+  * @param  huart pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval None
+  */
+static void UART_EndTransmit_IT(UART_HandleTypeDef *huart)
+{
+ 803f28e:	b580      	push	{r7, lr}
+ 803f290:	b088      	sub	sp, #32
+ 803f292:	af00      	add	r7, sp, #0
+ 803f294:	6078      	str	r0, [r7, #4]
+  /* Disable the UART Transmit Complete Interrupt */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+ 803f296:	687b      	ldr	r3, [r7, #4]
+ 803f298:	681b      	ldr	r3, [r3, #0]
+ 803f29a:	60fb      	str	r3, [r7, #12]
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ 803f29c:	68fb      	ldr	r3, [r7, #12]
+ 803f29e:	e853 3f00 	ldrex	r3, [r3]
+ 803f2a2:	60bb      	str	r3, [r7, #8]
+   return(result);
+ 803f2a4:	68bb      	ldr	r3, [r7, #8]
+ 803f2a6:	f023 0340 	bic.w	r3, r3, #64	@ 0x40
+ 803f2aa:	61fb      	str	r3, [r7, #28]
+ 803f2ac:	687b      	ldr	r3, [r7, #4]
+ 803f2ae:	681b      	ldr	r3, [r3, #0]
+ 803f2b0:	461a      	mov	r2, r3
+ 803f2b2:	69fb      	ldr	r3, [r7, #28]
+ 803f2b4:	61bb      	str	r3, [r7, #24]
+ 803f2b6:	617a      	str	r2, [r7, #20]
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ 803f2b8:	6979      	ldr	r1, [r7, #20]
+ 803f2ba:	69ba      	ldr	r2, [r7, #24]
+ 803f2bc:	e841 2300 	strex	r3, r2, [r1]
+ 803f2c0:	613b      	str	r3, [r7, #16]
+   return(result);
+ 803f2c2:	693b      	ldr	r3, [r7, #16]
+ 803f2c4:	2b00      	cmp	r3, #0
+ 803f2c6:	d1e6      	bne.n	803f296 <UART_EndTransmit_IT+0x8>
+
+  /* Tx process is ended, restore huart->gState to Ready */
+  huart->gState = HAL_UART_STATE_READY;
+ 803f2c8:	687b      	ldr	r3, [r7, #4]
+ 803f2ca:	2220      	movs	r2, #32
+ 803f2cc:	f8c3 2088 	str.w	r2, [r3, #136]	@ 0x88
+
+  /* Cleat TxISR function pointer */
+  huart->TxISR = NULL;
+ 803f2d0:	687b      	ldr	r3, [r7, #4]
+ 803f2d2:	2200      	movs	r2, #0
+ 803f2d4:	679a      	str	r2, [r3, #120]	@ 0x78
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /*Call registered Tx complete callback*/
+  huart->TxCpltCallback(huart);
+#else
+  /*Call legacy weak Tx complete callback*/
+  HAL_UART_TxCpltCallback(huart);
+ 803f2d6:	6878      	ldr	r0, [r7, #4]
+ 803f2d8:	f7e2 fcec 	bl	8021cb4 <HAL_UART_TxCpltCallback>
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+ 803f2dc:	bf00      	nop
+ 803f2de:	3720      	adds	r7, #32
+ 803f2e0:	46bd      	mov	sp, r7
+ 803f2e2:	bd80      	pop	{r7, pc}
+
+0803f2e4 <UART_RxISR_8BIT>:
+  * @brief RX interrupt handler for 7 or 8 bits data word length .
+  * @param huart UART handle.
+  * @retval None
+  */
+static void UART_RxISR_8BIT(UART_HandleTypeDef *huart)
+{
+ 803f2e4:	b580      	push	{r7, lr}
+ 803f2e6:	b09c      	sub	sp, #112	@ 0x70
+ 803f2e8:	af00      	add	r7, sp, #0
+ 803f2ea:	6078      	str	r0, [r7, #4]
+  uint16_t uhMask = huart->Mask;
+ 803f2ec:	687b      	ldr	r3, [r7, #4]
+ 803f2ee:	f8b3 3060 	ldrh.w	r3, [r3, #96]	@ 0x60
+ 803f2f2:	f8a7 306e 	strh.w	r3, [r7, #110]	@ 0x6e
+  uint16_t  uhdata;
+
+  /* Check that a Rx process is ongoing */
+  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+ 803f2f6:	687b      	ldr	r3, [r7, #4]
+ 803f2f8:	f8d3 308c 	ldr.w	r3, [r3, #140]	@ 0x8c
+ 803f2fc:	2b22      	cmp	r3, #34	@ 0x22
+ 803f2fe:	f040 80be 	bne.w	803f47e <UART_RxISR_8BIT+0x19a>
+  {
+    uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
+ 803f302:	687b      	ldr	r3, [r7, #4]
+ 803f304:	681b      	ldr	r3, [r3, #0]
+ 803f306:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 803f308:	f8a7 306c 	strh.w	r3, [r7, #108]	@ 0x6c
+    *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
+ 803f30c:	f8b7 306c 	ldrh.w	r3, [r7, #108]	@ 0x6c
+ 803f310:	b2d9      	uxtb	r1, r3
+ 803f312:	f8b7 306e 	ldrh.w	r3, [r7, #110]	@ 0x6e
+ 803f316:	b2da      	uxtb	r2, r3
+ 803f318:	687b      	ldr	r3, [r7, #4]
+ 803f31a:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
+ 803f31c:	400a      	ands	r2, r1
+ 803f31e:	b2d2      	uxtb	r2, r2
+ 803f320:	701a      	strb	r2, [r3, #0]
+    huart->pRxBuffPtr++;
+ 803f322:	687b      	ldr	r3, [r7, #4]
+ 803f324:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
+ 803f326:	1c5a      	adds	r2, r3, #1
+ 803f328:	687b      	ldr	r3, [r7, #4]
+ 803f32a:	659a      	str	r2, [r3, #88]	@ 0x58
+    huart->RxXferCount--;
+ 803f32c:	687b      	ldr	r3, [r7, #4]
+ 803f32e:	f8b3 305e 	ldrh.w	r3, [r3, #94]	@ 0x5e
+ 803f332:	b29b      	uxth	r3, r3
+ 803f334:	3b01      	subs	r3, #1
+ 803f336:	b29a      	uxth	r2, r3
+ 803f338:	687b      	ldr	r3, [r7, #4]
+ 803f33a:	f8a3 205e 	strh.w	r2, [r3, #94]	@ 0x5e
+
+    if (huart->RxXferCount == 0U)
+ 803f33e:	687b      	ldr	r3, [r7, #4]
+ 803f340:	f8b3 305e 	ldrh.w	r3, [r3, #94]	@ 0x5e
+ 803f344:	b29b      	uxth	r3, r3
+ 803f346:	2b00      	cmp	r3, #0
+ 803f348:	f040 80a1 	bne.w	803f48e <UART_RxISR_8BIT+0x1aa>
+    {
+      /* Disable the UART Parity Error Interrupt and RXNE interrupts */
+      ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+ 803f34c:	687b      	ldr	r3, [r7, #4]
+ 803f34e:	681b      	ldr	r3, [r3, #0]
+ 803f350:	64fb      	str	r3, [r7, #76]	@ 0x4c
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ 803f352:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
+ 803f354:	e853 3f00 	ldrex	r3, [r3]
+ 803f358:	64bb      	str	r3, [r7, #72]	@ 0x48
+   return(result);
+ 803f35a:	6cbb      	ldr	r3, [r7, #72]	@ 0x48
+ 803f35c:	f423 7390 	bic.w	r3, r3, #288	@ 0x120
+ 803f360:	66bb      	str	r3, [r7, #104]	@ 0x68
+ 803f362:	687b      	ldr	r3, [r7, #4]
+ 803f364:	681b      	ldr	r3, [r3, #0]
+ 803f366:	461a      	mov	r2, r3
+ 803f368:	6ebb      	ldr	r3, [r7, #104]	@ 0x68
+ 803f36a:	65bb      	str	r3, [r7, #88]	@ 0x58
+ 803f36c:	657a      	str	r2, [r7, #84]	@ 0x54
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ 803f36e:	6d79      	ldr	r1, [r7, #84]	@ 0x54
+ 803f370:	6dba      	ldr	r2, [r7, #88]	@ 0x58
+ 803f372:	e841 2300 	strex	r3, r2, [r1]
+ 803f376:	653b      	str	r3, [r7, #80]	@ 0x50
+   return(result);
+ 803f378:	6d3b      	ldr	r3, [r7, #80]	@ 0x50
+ 803f37a:	2b00      	cmp	r3, #0
+ 803f37c:	d1e6      	bne.n	803f34c <UART_RxISR_8BIT+0x68>
+
+      /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+      ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ 803f37e:	687b      	ldr	r3, [r7, #4]
+ 803f380:	681b      	ldr	r3, [r3, #0]
+ 803f382:	3308      	adds	r3, #8
+ 803f384:	63bb      	str	r3, [r7, #56]	@ 0x38
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ 803f386:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 803f388:	e853 3f00 	ldrex	r3, [r3]
+ 803f38c:	637b      	str	r3, [r7, #52]	@ 0x34
+   return(result);
+ 803f38e:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
+ 803f390:	f023 0301 	bic.w	r3, r3, #1
+ 803f394:	667b      	str	r3, [r7, #100]	@ 0x64
+ 803f396:	687b      	ldr	r3, [r7, #4]
+ 803f398:	681b      	ldr	r3, [r3, #0]
+ 803f39a:	3308      	adds	r3, #8
+ 803f39c:	6e7a      	ldr	r2, [r7, #100]	@ 0x64
+ 803f39e:	647a      	str	r2, [r7, #68]	@ 0x44
+ 803f3a0:	643b      	str	r3, [r7, #64]	@ 0x40
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ 803f3a2:	6c39      	ldr	r1, [r7, #64]	@ 0x40
+ 803f3a4:	6c7a      	ldr	r2, [r7, #68]	@ 0x44
+ 803f3a6:	e841 2300 	strex	r3, r2, [r1]
+ 803f3aa:	63fb      	str	r3, [r7, #60]	@ 0x3c
+   return(result);
+ 803f3ac:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
+ 803f3ae:	2b00      	cmp	r3, #0
+ 803f3b0:	d1e5      	bne.n	803f37e <UART_RxISR_8BIT+0x9a>
+
+      /* Rx process is completed, restore huart->RxState to Ready */
+      huart->RxState = HAL_UART_STATE_READY;
+ 803f3b2:	687b      	ldr	r3, [r7, #4]
+ 803f3b4:	2220      	movs	r2, #32
+ 803f3b6:	f8c3 208c 	str.w	r2, [r3, #140]	@ 0x8c
+
+      /* Clear RxISR function pointer */
+      huart->RxISR = NULL;
+ 803f3ba:	687b      	ldr	r3, [r7, #4]
+ 803f3bc:	2200      	movs	r2, #0
+ 803f3be:	675a      	str	r2, [r3, #116]	@ 0x74
+
+      /* Initialize type of RxEvent to Transfer Complete */
+      huart->RxEventType = HAL_UART_RXEVENT_TC;
+ 803f3c0:	687b      	ldr	r3, [r7, #4]
+ 803f3c2:	2200      	movs	r2, #0
+ 803f3c4:	671a      	str	r2, [r3, #112]	@ 0x70
+
+      if (!(IS_LPUART_INSTANCE(huart->Instance)))
+ 803f3c6:	687b      	ldr	r3, [r7, #4]
+ 803f3c8:	681b      	ldr	r3, [r3, #0]
+ 803f3ca:	4a33      	ldr	r2, [pc, #204]	@ (803f498 <UART_RxISR_8BIT+0x1b4>)
+ 803f3cc:	4293      	cmp	r3, r2
+ 803f3ce:	d01f      	beq.n	803f410 <UART_RxISR_8BIT+0x12c>
+      {
+        /* Check that USART RTOEN bit is set */
+        if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+ 803f3d0:	687b      	ldr	r3, [r7, #4]
+ 803f3d2:	681b      	ldr	r3, [r3, #0]
+ 803f3d4:	685b      	ldr	r3, [r3, #4]
+ 803f3d6:	f403 0300 	and.w	r3, r3, #8388608	@ 0x800000
+ 803f3da:	2b00      	cmp	r3, #0
+ 803f3dc:	d018      	beq.n	803f410 <UART_RxISR_8BIT+0x12c>
+        {
+          /* Enable the UART Receiver Timeout Interrupt */
+          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+ 803f3de:	687b      	ldr	r3, [r7, #4]
+ 803f3e0:	681b      	ldr	r3, [r3, #0]
+ 803f3e2:	627b      	str	r3, [r7, #36]	@ 0x24
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ 803f3e4:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 803f3e6:	e853 3f00 	ldrex	r3, [r3]
+ 803f3ea:	623b      	str	r3, [r7, #32]
+   return(result);
+ 803f3ec:	6a3b      	ldr	r3, [r7, #32]
+ 803f3ee:	f023 6380 	bic.w	r3, r3, #67108864	@ 0x4000000
+ 803f3f2:	663b      	str	r3, [r7, #96]	@ 0x60
+ 803f3f4:	687b      	ldr	r3, [r7, #4]
+ 803f3f6:	681b      	ldr	r3, [r3, #0]
+ 803f3f8:	461a      	mov	r2, r3
+ 803f3fa:	6e3b      	ldr	r3, [r7, #96]	@ 0x60
+ 803f3fc:	633b      	str	r3, [r7, #48]	@ 0x30
+ 803f3fe:	62fa      	str	r2, [r7, #44]	@ 0x2c
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ 803f400:	6af9      	ldr	r1, [r7, #44]	@ 0x2c
+ 803f402:	6b3a      	ldr	r2, [r7, #48]	@ 0x30
+ 803f404:	e841 2300 	strex	r3, r2, [r1]
+ 803f408:	62bb      	str	r3, [r7, #40]	@ 0x28
+   return(result);
+ 803f40a:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 803f40c:	2b00      	cmp	r3, #0
+ 803f40e:	d1e6      	bne.n	803f3de <UART_RxISR_8BIT+0xfa>
+        }
+      }
+
+      /* Check current reception Mode :
+         If Reception till IDLE event has been selected : */
+      if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ 803f410:	687b      	ldr	r3, [r7, #4]
+ 803f412:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
+ 803f414:	2b01      	cmp	r3, #1
+ 803f416:	d12e      	bne.n	803f476 <UART_RxISR_8BIT+0x192>
+      {
+        /* Set reception type to Standard */
+        huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ 803f418:	687b      	ldr	r3, [r7, #4]
+ 803f41a:	2200      	movs	r2, #0
+ 803f41c:	66da      	str	r2, [r3, #108]	@ 0x6c
+
+        /* Disable IDLE interrupt */
+        ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ 803f41e:	687b      	ldr	r3, [r7, #4]
+ 803f420:	681b      	ldr	r3, [r3, #0]
+ 803f422:	613b      	str	r3, [r7, #16]
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ 803f424:	693b      	ldr	r3, [r7, #16]
+ 803f426:	e853 3f00 	ldrex	r3, [r3]
+ 803f42a:	60fb      	str	r3, [r7, #12]
+   return(result);
+ 803f42c:	68fb      	ldr	r3, [r7, #12]
+ 803f42e:	f023 0310 	bic.w	r3, r3, #16
+ 803f432:	65fb      	str	r3, [r7, #92]	@ 0x5c
+ 803f434:	687b      	ldr	r3, [r7, #4]
+ 803f436:	681b      	ldr	r3, [r3, #0]
+ 803f438:	461a      	mov	r2, r3
+ 803f43a:	6dfb      	ldr	r3, [r7, #92]	@ 0x5c
+ 803f43c:	61fb      	str	r3, [r7, #28]
+ 803f43e:	61ba      	str	r2, [r7, #24]
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ 803f440:	69b9      	ldr	r1, [r7, #24]
+ 803f442:	69fa      	ldr	r2, [r7, #28]
+ 803f444:	e841 2300 	strex	r3, r2, [r1]
+ 803f448:	617b      	str	r3, [r7, #20]
+   return(result);
+ 803f44a:	697b      	ldr	r3, [r7, #20]
+ 803f44c:	2b00      	cmp	r3, #0
+ 803f44e:	d1e6      	bne.n	803f41e <UART_RxISR_8BIT+0x13a>
+
+        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
+ 803f450:	687b      	ldr	r3, [r7, #4]
+ 803f452:	681b      	ldr	r3, [r3, #0]
+ 803f454:	69db      	ldr	r3, [r3, #28]
+ 803f456:	f003 0310 	and.w	r3, r3, #16
+ 803f45a:	2b10      	cmp	r3, #16
+ 803f45c:	d103      	bne.n	803f466 <UART_RxISR_8BIT+0x182>
+        {
+          /* Clear IDLE Flag */
+          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+ 803f45e:	687b      	ldr	r3, [r7, #4]
+ 803f460:	681b      	ldr	r3, [r3, #0]
+ 803f462:	2210      	movs	r2, #16
+ 803f464:	621a      	str	r2, [r3, #32]
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+        /*Call registered Rx Event callback*/
+        huart->RxEventCallback(huart, huart->RxXferSize);
+#else
+        /*Call legacy weak Rx Event callback*/
+        HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+ 803f466:	687b      	ldr	r3, [r7, #4]
+ 803f468:	f8b3 305c 	ldrh.w	r3, [r3, #92]	@ 0x5c
+ 803f46c:	4619      	mov	r1, r3
+ 803f46e:	6878      	ldr	r0, [r7, #4]
+ 803f470:	f7fe fd66 	bl	803df40 <HAL_UARTEx_RxEventCallback>
+  else
+  {
+    /* Clear RXNE interrupt flag */
+    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+  }
+}
+ 803f474:	e00b      	b.n	803f48e <UART_RxISR_8BIT+0x1aa>
+        HAL_UART_RxCpltCallback(huart);
+ 803f476:	6878      	ldr	r0, [r7, #4]
+ 803f478:	f7e2 fbae 	bl	8021bd8 <HAL_UART_RxCpltCallback>
+}
+ 803f47c:	e007      	b.n	803f48e <UART_RxISR_8BIT+0x1aa>
+    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+ 803f47e:	687b      	ldr	r3, [r7, #4]
+ 803f480:	681b      	ldr	r3, [r3, #0]
+ 803f482:	699a      	ldr	r2, [r3, #24]
+ 803f484:	687b      	ldr	r3, [r7, #4]
+ 803f486:	681b      	ldr	r3, [r3, #0]
+ 803f488:	f042 0208 	orr.w	r2, r2, #8
+ 803f48c:	619a      	str	r2, [r3, #24]
+}
+ 803f48e:	bf00      	nop
+ 803f490:	3770      	adds	r7, #112	@ 0x70
+ 803f492:	46bd      	mov	sp, r7
+ 803f494:	bd80      	pop	{r7, pc}
+ 803f496:	bf00      	nop
+ 803f498:	58000c00 	.word	0x58000c00
+
+0803f49c <UART_RxISR_16BIT>:
+  *         interruptions have been enabled by HAL_UART_Receive_IT()
+  * @param huart UART handle.
+  * @retval None
+  */
+static void UART_RxISR_16BIT(UART_HandleTypeDef *huart)
+{
+ 803f49c:	b580      	push	{r7, lr}
+ 803f49e:	b09c      	sub	sp, #112	@ 0x70
+ 803f4a0:	af00      	add	r7, sp, #0
+ 803f4a2:	6078      	str	r0, [r7, #4]
+  uint16_t *tmp;
+  uint16_t uhMask = huart->Mask;
+ 803f4a4:	687b      	ldr	r3, [r7, #4]
+ 803f4a6:	f8b3 3060 	ldrh.w	r3, [r3, #96]	@ 0x60
+ 803f4aa:	f8a7 306e 	strh.w	r3, [r7, #110]	@ 0x6e
+  uint16_t  uhdata;
+
+  /* Check that a Rx process is ongoing */
+  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+ 803f4ae:	687b      	ldr	r3, [r7, #4]
+ 803f4b0:	f8d3 308c 	ldr.w	r3, [r3, #140]	@ 0x8c
+ 803f4b4:	2b22      	cmp	r3, #34	@ 0x22
+ 803f4b6:	f040 80be 	bne.w	803f636 <UART_RxISR_16BIT+0x19a>
+  {
+    uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
+ 803f4ba:	687b      	ldr	r3, [r7, #4]
+ 803f4bc:	681b      	ldr	r3, [r3, #0]
+ 803f4be:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 803f4c0:	f8a7 306c 	strh.w	r3, [r7, #108]	@ 0x6c
+    tmp = (uint16_t *) huart->pRxBuffPtr ;
+ 803f4c4:	687b      	ldr	r3, [r7, #4]
+ 803f4c6:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
+ 803f4c8:	66bb      	str	r3, [r7, #104]	@ 0x68
+    *tmp = (uint16_t)(uhdata & uhMask);
+ 803f4ca:	f8b7 206c 	ldrh.w	r2, [r7, #108]	@ 0x6c
+ 803f4ce:	f8b7 306e 	ldrh.w	r3, [r7, #110]	@ 0x6e
+ 803f4d2:	4013      	ands	r3, r2
+ 803f4d4:	b29a      	uxth	r2, r3
+ 803f4d6:	6ebb      	ldr	r3, [r7, #104]	@ 0x68
+ 803f4d8:	801a      	strh	r2, [r3, #0]
+    huart->pRxBuffPtr += 2U;
+ 803f4da:	687b      	ldr	r3, [r7, #4]
+ 803f4dc:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
+ 803f4de:	1c9a      	adds	r2, r3, #2
+ 803f4e0:	687b      	ldr	r3, [r7, #4]
+ 803f4e2:	659a      	str	r2, [r3, #88]	@ 0x58
+    huart->RxXferCount--;
+ 803f4e4:	687b      	ldr	r3, [r7, #4]
+ 803f4e6:	f8b3 305e 	ldrh.w	r3, [r3, #94]	@ 0x5e
+ 803f4ea:	b29b      	uxth	r3, r3
+ 803f4ec:	3b01      	subs	r3, #1
+ 803f4ee:	b29a      	uxth	r2, r3
+ 803f4f0:	687b      	ldr	r3, [r7, #4]
+ 803f4f2:	f8a3 205e 	strh.w	r2, [r3, #94]	@ 0x5e
+
+    if (huart->RxXferCount == 0U)
+ 803f4f6:	687b      	ldr	r3, [r7, #4]
+ 803f4f8:	f8b3 305e 	ldrh.w	r3, [r3, #94]	@ 0x5e
+ 803f4fc:	b29b      	uxth	r3, r3
+ 803f4fe:	2b00      	cmp	r3, #0
+ 803f500:	f040 80a1 	bne.w	803f646 <UART_RxISR_16BIT+0x1aa>
+    {
+      /* Disable the UART Parity Error Interrupt and RXNE interrupt*/
+      ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+ 803f504:	687b      	ldr	r3, [r7, #4]
+ 803f506:	681b      	ldr	r3, [r3, #0]
+ 803f508:	64bb      	str	r3, [r7, #72]	@ 0x48
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ 803f50a:	6cbb      	ldr	r3, [r7, #72]	@ 0x48
+ 803f50c:	e853 3f00 	ldrex	r3, [r3]
+ 803f510:	647b      	str	r3, [r7, #68]	@ 0x44
+   return(result);
+ 803f512:	6c7b      	ldr	r3, [r7, #68]	@ 0x44
+ 803f514:	f423 7390 	bic.w	r3, r3, #288	@ 0x120
+ 803f518:	667b      	str	r3, [r7, #100]	@ 0x64
+ 803f51a:	687b      	ldr	r3, [r7, #4]
+ 803f51c:	681b      	ldr	r3, [r3, #0]
+ 803f51e:	461a      	mov	r2, r3
+ 803f520:	6e7b      	ldr	r3, [r7, #100]	@ 0x64
+ 803f522:	657b      	str	r3, [r7, #84]	@ 0x54
+ 803f524:	653a      	str	r2, [r7, #80]	@ 0x50
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ 803f526:	6d39      	ldr	r1, [r7, #80]	@ 0x50
+ 803f528:	6d7a      	ldr	r2, [r7, #84]	@ 0x54
+ 803f52a:	e841 2300 	strex	r3, r2, [r1]
+ 803f52e:	64fb      	str	r3, [r7, #76]	@ 0x4c
+   return(result);
+ 803f530:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
+ 803f532:	2b00      	cmp	r3, #0
+ 803f534:	d1e6      	bne.n	803f504 <UART_RxISR_16BIT+0x68>
+
+      /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+      ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ 803f536:	687b      	ldr	r3, [r7, #4]
+ 803f538:	681b      	ldr	r3, [r3, #0]
+ 803f53a:	3308      	adds	r3, #8
+ 803f53c:	637b      	str	r3, [r7, #52]	@ 0x34
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ 803f53e:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
+ 803f540:	e853 3f00 	ldrex	r3, [r3]
+ 803f544:	633b      	str	r3, [r7, #48]	@ 0x30
+   return(result);
+ 803f546:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
+ 803f548:	f023 0301 	bic.w	r3, r3, #1
+ 803f54c:	663b      	str	r3, [r7, #96]	@ 0x60
+ 803f54e:	687b      	ldr	r3, [r7, #4]
+ 803f550:	681b      	ldr	r3, [r3, #0]
+ 803f552:	3308      	adds	r3, #8
+ 803f554:	6e3a      	ldr	r2, [r7, #96]	@ 0x60
+ 803f556:	643a      	str	r2, [r7, #64]	@ 0x40
+ 803f558:	63fb      	str	r3, [r7, #60]	@ 0x3c
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ 803f55a:	6bf9      	ldr	r1, [r7, #60]	@ 0x3c
+ 803f55c:	6c3a      	ldr	r2, [r7, #64]	@ 0x40
+ 803f55e:	e841 2300 	strex	r3, r2, [r1]
+ 803f562:	63bb      	str	r3, [r7, #56]	@ 0x38
+   return(result);
+ 803f564:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 803f566:	2b00      	cmp	r3, #0
+ 803f568:	d1e5      	bne.n	803f536 <UART_RxISR_16BIT+0x9a>
+
+      /* Rx process is completed, restore huart->RxState to Ready */
+      huart->RxState = HAL_UART_STATE_READY;
+ 803f56a:	687b      	ldr	r3, [r7, #4]
+ 803f56c:	2220      	movs	r2, #32
+ 803f56e:	f8c3 208c 	str.w	r2, [r3, #140]	@ 0x8c
+
+      /* Clear RxISR function pointer */
+      huart->RxISR = NULL;
+ 803f572:	687b      	ldr	r3, [r7, #4]
+ 803f574:	2200      	movs	r2, #0
+ 803f576:	675a      	str	r2, [r3, #116]	@ 0x74
+
+      /* Initialize type of RxEvent to Transfer Complete */
+      huart->RxEventType = HAL_UART_RXEVENT_TC;
+ 803f578:	687b      	ldr	r3, [r7, #4]
+ 803f57a:	2200      	movs	r2, #0
+ 803f57c:	671a      	str	r2, [r3, #112]	@ 0x70
+
+      if (!(IS_LPUART_INSTANCE(huart->Instance)))
+ 803f57e:	687b      	ldr	r3, [r7, #4]
+ 803f580:	681b      	ldr	r3, [r3, #0]
+ 803f582:	4a33      	ldr	r2, [pc, #204]	@ (803f650 <UART_RxISR_16BIT+0x1b4>)
+ 803f584:	4293      	cmp	r3, r2
+ 803f586:	d01f      	beq.n	803f5c8 <UART_RxISR_16BIT+0x12c>
+      {
+        /* Check that USART RTOEN bit is set */
+        if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+ 803f588:	687b      	ldr	r3, [r7, #4]
+ 803f58a:	681b      	ldr	r3, [r3, #0]
+ 803f58c:	685b      	ldr	r3, [r3, #4]
+ 803f58e:	f403 0300 	and.w	r3, r3, #8388608	@ 0x800000
+ 803f592:	2b00      	cmp	r3, #0
+ 803f594:	d018      	beq.n	803f5c8 <UART_RxISR_16BIT+0x12c>
+        {
+          /* Enable the UART Receiver Timeout Interrupt */
+          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+ 803f596:	687b      	ldr	r3, [r7, #4]
+ 803f598:	681b      	ldr	r3, [r3, #0]
+ 803f59a:	623b      	str	r3, [r7, #32]
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ 803f59c:	6a3b      	ldr	r3, [r7, #32]
+ 803f59e:	e853 3f00 	ldrex	r3, [r3]
+ 803f5a2:	61fb      	str	r3, [r7, #28]
+   return(result);
+ 803f5a4:	69fb      	ldr	r3, [r7, #28]
+ 803f5a6:	f023 6380 	bic.w	r3, r3, #67108864	@ 0x4000000
+ 803f5aa:	65fb      	str	r3, [r7, #92]	@ 0x5c
+ 803f5ac:	687b      	ldr	r3, [r7, #4]
+ 803f5ae:	681b      	ldr	r3, [r3, #0]
+ 803f5b0:	461a      	mov	r2, r3
+ 803f5b2:	6dfb      	ldr	r3, [r7, #92]	@ 0x5c
+ 803f5b4:	62fb      	str	r3, [r7, #44]	@ 0x2c
+ 803f5b6:	62ba      	str	r2, [r7, #40]	@ 0x28
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ 803f5b8:	6ab9      	ldr	r1, [r7, #40]	@ 0x28
+ 803f5ba:	6afa      	ldr	r2, [r7, #44]	@ 0x2c
+ 803f5bc:	e841 2300 	strex	r3, r2, [r1]
+ 803f5c0:	627b      	str	r3, [r7, #36]	@ 0x24
+   return(result);
+ 803f5c2:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 803f5c4:	2b00      	cmp	r3, #0
+ 803f5c6:	d1e6      	bne.n	803f596 <UART_RxISR_16BIT+0xfa>
+        }
+      }
+
+      /* Check current reception Mode :
+         If Reception till IDLE event has been selected : */
+      if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ 803f5c8:	687b      	ldr	r3, [r7, #4]
+ 803f5ca:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
+ 803f5cc:	2b01      	cmp	r3, #1
+ 803f5ce:	d12e      	bne.n	803f62e <UART_RxISR_16BIT+0x192>
+      {
+        /* Set reception type to Standard */
+        huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ 803f5d0:	687b      	ldr	r3, [r7, #4]
+ 803f5d2:	2200      	movs	r2, #0
+ 803f5d4:	66da      	str	r2, [r3, #108]	@ 0x6c
+
+        /* Disable IDLE interrupt */
+        ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ 803f5d6:	687b      	ldr	r3, [r7, #4]
+ 803f5d8:	681b      	ldr	r3, [r3, #0]
+ 803f5da:	60fb      	str	r3, [r7, #12]
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ 803f5dc:	68fb      	ldr	r3, [r7, #12]
+ 803f5de:	e853 3f00 	ldrex	r3, [r3]
+ 803f5e2:	60bb      	str	r3, [r7, #8]
+   return(result);
+ 803f5e4:	68bb      	ldr	r3, [r7, #8]
+ 803f5e6:	f023 0310 	bic.w	r3, r3, #16
+ 803f5ea:	65bb      	str	r3, [r7, #88]	@ 0x58
+ 803f5ec:	687b      	ldr	r3, [r7, #4]
+ 803f5ee:	681b      	ldr	r3, [r3, #0]
+ 803f5f0:	461a      	mov	r2, r3
+ 803f5f2:	6dbb      	ldr	r3, [r7, #88]	@ 0x58
+ 803f5f4:	61bb      	str	r3, [r7, #24]
+ 803f5f6:	617a      	str	r2, [r7, #20]
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ 803f5f8:	6979      	ldr	r1, [r7, #20]
+ 803f5fa:	69ba      	ldr	r2, [r7, #24]
+ 803f5fc:	e841 2300 	strex	r3, r2, [r1]
+ 803f600:	613b      	str	r3, [r7, #16]
+   return(result);
+ 803f602:	693b      	ldr	r3, [r7, #16]
+ 803f604:	2b00      	cmp	r3, #0
+ 803f606:	d1e6      	bne.n	803f5d6 <UART_RxISR_16BIT+0x13a>
+
+        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
+ 803f608:	687b      	ldr	r3, [r7, #4]
+ 803f60a:	681b      	ldr	r3, [r3, #0]
+ 803f60c:	69db      	ldr	r3, [r3, #28]
+ 803f60e:	f003 0310 	and.w	r3, r3, #16
+ 803f612:	2b10      	cmp	r3, #16
+ 803f614:	d103      	bne.n	803f61e <UART_RxISR_16BIT+0x182>
+        {
+          /* Clear IDLE Flag */
+          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+ 803f616:	687b      	ldr	r3, [r7, #4]
+ 803f618:	681b      	ldr	r3, [r3, #0]
+ 803f61a:	2210      	movs	r2, #16
+ 803f61c:	621a      	str	r2, [r3, #32]
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+        /*Call registered Rx Event callback*/
+        huart->RxEventCallback(huart, huart->RxXferSize);
+#else
+        /*Call legacy weak Rx Event callback*/
+        HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+ 803f61e:	687b      	ldr	r3, [r7, #4]
+ 803f620:	f8b3 305c 	ldrh.w	r3, [r3, #92]	@ 0x5c
+ 803f624:	4619      	mov	r1, r3
+ 803f626:	6878      	ldr	r0, [r7, #4]
+ 803f628:	f7fe fc8a 	bl	803df40 <HAL_UARTEx_RxEventCallback>
+  else
+  {
+    /* Clear RXNE interrupt flag */
+    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+  }
+}
+ 803f62c:	e00b      	b.n	803f646 <UART_RxISR_16BIT+0x1aa>
+        HAL_UART_RxCpltCallback(huart);
+ 803f62e:	6878      	ldr	r0, [r7, #4]
+ 803f630:	f7e2 fad2 	bl	8021bd8 <HAL_UART_RxCpltCallback>
+}
+ 803f634:	e007      	b.n	803f646 <UART_RxISR_16BIT+0x1aa>
+    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+ 803f636:	687b      	ldr	r3, [r7, #4]
+ 803f638:	681b      	ldr	r3, [r3, #0]
+ 803f63a:	699a      	ldr	r2, [r3, #24]
+ 803f63c:	687b      	ldr	r3, [r7, #4]
+ 803f63e:	681b      	ldr	r3, [r3, #0]
+ 803f640:	f042 0208 	orr.w	r2, r2, #8
+ 803f644:	619a      	str	r2, [r3, #24]
+}
+ 803f646:	bf00      	nop
+ 803f648:	3770      	adds	r7, #112	@ 0x70
+ 803f64a:	46bd      	mov	sp, r7
+ 803f64c:	bd80      	pop	{r7, pc}
+ 803f64e:	bf00      	nop
+ 803f650:	58000c00 	.word	0x58000c00
+
+0803f654 <UART_RxISR_8BIT_FIFOEN>:
+  *         interruptions have been enabled by HAL_UART_Receive_IT()
+  * @param huart UART handle.
+  * @retval None
+  */
+static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)
+{
+ 803f654:	b580      	push	{r7, lr}
+ 803f656:	b0ac      	sub	sp, #176	@ 0xb0
+ 803f658:	af00      	add	r7, sp, #0
+ 803f65a:	6078      	str	r0, [r7, #4]
+  uint16_t  uhMask = huart->Mask;
+ 803f65c:	687b      	ldr	r3, [r7, #4]
+ 803f65e:	f8b3 3060 	ldrh.w	r3, [r3, #96]	@ 0x60
+ 803f662:	f8a7 30aa 	strh.w	r3, [r7, #170]	@ 0xaa
+  uint16_t  uhdata;
+  uint16_t  nb_rx_data;
+  uint16_t  rxdatacount;
+  uint32_t  isrflags = READ_REG(huart->Instance->ISR);
+ 803f666:	687b      	ldr	r3, [r7, #4]
+ 803f668:	681b      	ldr	r3, [r3, #0]
+ 803f66a:	69db      	ldr	r3, [r3, #28]
+ 803f66c:	f8c7 30ac 	str.w	r3, [r7, #172]	@ 0xac
+  uint32_t  cr1its   = READ_REG(huart->Instance->CR1);
+ 803f670:	687b      	ldr	r3, [r7, #4]
+ 803f672:	681b      	ldr	r3, [r3, #0]
+ 803f674:	681b      	ldr	r3, [r3, #0]
+ 803f676:	f8c7 30a4 	str.w	r3, [r7, #164]	@ 0xa4
+  uint32_t  cr3its   = READ_REG(huart->Instance->CR3);
+ 803f67a:	687b      	ldr	r3, [r7, #4]
+ 803f67c:	681b      	ldr	r3, [r3, #0]
+ 803f67e:	689b      	ldr	r3, [r3, #8]
+ 803f680:	f8c7 30a0 	str.w	r3, [r7, #160]	@ 0xa0
+
+  /* Check that a Rx process is ongoing */
+  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+ 803f684:	687b      	ldr	r3, [r7, #4]
+ 803f686:	f8d3 308c 	ldr.w	r3, [r3, #140]	@ 0x8c
+ 803f68a:	2b22      	cmp	r3, #34	@ 0x22
+ 803f68c:	f040 8180 	bne.w	803f990 <UART_RxISR_8BIT_FIFOEN+0x33c>
+  {
+    nb_rx_data = huart->NbRxDataToProcess;
+ 803f690:	687b      	ldr	r3, [r7, #4]
+ 803f692:	f8b3 3068 	ldrh.w	r3, [r3, #104]	@ 0x68
+ 803f696:	f8a7 309e 	strh.w	r3, [r7, #158]	@ 0x9e
+    while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
+ 803f69a:	e123      	b.n	803f8e4 <UART_RxISR_8BIT_FIFOEN+0x290>
+    {
+      uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
+ 803f69c:	687b      	ldr	r3, [r7, #4]
+ 803f69e:	681b      	ldr	r3, [r3, #0]
+ 803f6a0:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 803f6a2:	f8a7 309c 	strh.w	r3, [r7, #156]	@ 0x9c
+      *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
+ 803f6a6:	f8b7 309c 	ldrh.w	r3, [r7, #156]	@ 0x9c
+ 803f6aa:	b2d9      	uxtb	r1, r3
+ 803f6ac:	f8b7 30aa 	ldrh.w	r3, [r7, #170]	@ 0xaa
+ 803f6b0:	b2da      	uxtb	r2, r3
+ 803f6b2:	687b      	ldr	r3, [r7, #4]
+ 803f6b4:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
+ 803f6b6:	400a      	ands	r2, r1
+ 803f6b8:	b2d2      	uxtb	r2, r2
+ 803f6ba:	701a      	strb	r2, [r3, #0]
+      huart->pRxBuffPtr++;
+ 803f6bc:	687b      	ldr	r3, [r7, #4]
+ 803f6be:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
+ 803f6c0:	1c5a      	adds	r2, r3, #1
+ 803f6c2:	687b      	ldr	r3, [r7, #4]
+ 803f6c4:	659a      	str	r2, [r3, #88]	@ 0x58
+      huart->RxXferCount--;
+ 803f6c6:	687b      	ldr	r3, [r7, #4]
+ 803f6c8:	f8b3 305e 	ldrh.w	r3, [r3, #94]	@ 0x5e
+ 803f6cc:	b29b      	uxth	r3, r3
+ 803f6ce:	3b01      	subs	r3, #1
+ 803f6d0:	b29a      	uxth	r2, r3
+ 803f6d2:	687b      	ldr	r3, [r7, #4]
+ 803f6d4:	f8a3 205e 	strh.w	r2, [r3, #94]	@ 0x5e
+      isrflags = READ_REG(huart->Instance->ISR);
+ 803f6d8:	687b      	ldr	r3, [r7, #4]
+ 803f6da:	681b      	ldr	r3, [r3, #0]
+ 803f6dc:	69db      	ldr	r3, [r3, #28]
+ 803f6de:	f8c7 30ac 	str.w	r3, [r7, #172]	@ 0xac
+
+      /* If some non blocking errors occurred */
+      if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U)
+ 803f6e2:	f8d7 30ac 	ldr.w	r3, [r7, #172]	@ 0xac
+ 803f6e6:	f003 0307 	and.w	r3, r3, #7
+ 803f6ea:	2b00      	cmp	r3, #0
+ 803f6ec:	d053      	beq.n	803f796 <UART_RxISR_8BIT_FIFOEN+0x142>
+      {
+        /* UART parity error interrupt occurred -------------------------------------*/
+        if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
+ 803f6ee:	f8d7 30ac 	ldr.w	r3, [r7, #172]	@ 0xac
+ 803f6f2:	f003 0301 	and.w	r3, r3, #1
+ 803f6f6:	2b00      	cmp	r3, #0
+ 803f6f8:	d011      	beq.n	803f71e <UART_RxISR_8BIT_FIFOEN+0xca>
+ 803f6fa:	f8d7 30a4 	ldr.w	r3, [r7, #164]	@ 0xa4
+ 803f6fe:	f403 7380 	and.w	r3, r3, #256	@ 0x100
+ 803f702:	2b00      	cmp	r3, #0
+ 803f704:	d00b      	beq.n	803f71e <UART_RxISR_8BIT_FIFOEN+0xca>
+        {
+          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
+ 803f706:	687b      	ldr	r3, [r7, #4]
+ 803f708:	681b      	ldr	r3, [r3, #0]
+ 803f70a:	2201      	movs	r2, #1
+ 803f70c:	621a      	str	r2, [r3, #32]
+
+          huart->ErrorCode |= HAL_UART_ERROR_PE;
+ 803f70e:	687b      	ldr	r3, [r7, #4]
+ 803f710:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
+ 803f714:	f043 0201 	orr.w	r2, r3, #1
+ 803f718:	687b      	ldr	r3, [r7, #4]
+ 803f71a:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90
+        }
+
+        /* UART frame error interrupt occurred --------------------------------------*/
+        if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+ 803f71e:	f8d7 30ac 	ldr.w	r3, [r7, #172]	@ 0xac
+ 803f722:	f003 0302 	and.w	r3, r3, #2
+ 803f726:	2b00      	cmp	r3, #0
+ 803f728:	d011      	beq.n	803f74e <UART_RxISR_8BIT_FIFOEN+0xfa>
+ 803f72a:	f8d7 30a0 	ldr.w	r3, [r7, #160]	@ 0xa0
+ 803f72e:	f003 0301 	and.w	r3, r3, #1
+ 803f732:	2b00      	cmp	r3, #0
+ 803f734:	d00b      	beq.n	803f74e <UART_RxISR_8BIT_FIFOEN+0xfa>
+        {
+          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
+ 803f736:	687b      	ldr	r3, [r7, #4]
+ 803f738:	681b      	ldr	r3, [r3, #0]
+ 803f73a:	2202      	movs	r2, #2
+ 803f73c:	621a      	str	r2, [r3, #32]
+
+          huart->ErrorCode |= HAL_UART_ERROR_FE;
+ 803f73e:	687b      	ldr	r3, [r7, #4]
+ 803f740:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
+ 803f744:	f043 0204 	orr.w	r2, r3, #4
+ 803f748:	687b      	ldr	r3, [r7, #4]
+ 803f74a:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90
+        }
+
+        /* UART noise error interrupt occurred --------------------------------------*/
+        if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+ 803f74e:	f8d7 30ac 	ldr.w	r3, [r7, #172]	@ 0xac
+ 803f752:	f003 0304 	and.w	r3, r3, #4
+ 803f756:	2b00      	cmp	r3, #0
+ 803f758:	d011      	beq.n	803f77e <UART_RxISR_8BIT_FIFOEN+0x12a>
+ 803f75a:	f8d7 30a0 	ldr.w	r3, [r7, #160]	@ 0xa0
+ 803f75e:	f003 0301 	and.w	r3, r3, #1
+ 803f762:	2b00      	cmp	r3, #0
+ 803f764:	d00b      	beq.n	803f77e <UART_RxISR_8BIT_FIFOEN+0x12a>
+        {
+          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
+ 803f766:	687b      	ldr	r3, [r7, #4]
+ 803f768:	681b      	ldr	r3, [r3, #0]
+ 803f76a:	2204      	movs	r2, #4
+ 803f76c:	621a      	str	r2, [r3, #32]
+
+          huart->ErrorCode |= HAL_UART_ERROR_NE;
+ 803f76e:	687b      	ldr	r3, [r7, #4]
+ 803f770:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
+ 803f774:	f043 0202 	orr.w	r2, r3, #2
+ 803f778:	687b      	ldr	r3, [r7, #4]
+ 803f77a:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90
+        }
+
+        /* Call UART Error Call back function if need be ----------------------------*/
+        if (huart->ErrorCode != HAL_UART_ERROR_NONE)
+ 803f77e:	687b      	ldr	r3, [r7, #4]
+ 803f780:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
+ 803f784:	2b00      	cmp	r3, #0
+ 803f786:	d006      	beq.n	803f796 <UART_RxISR_8BIT_FIFOEN+0x142>
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+          /*Call registered error callback*/
+          huart->ErrorCallback(huart);
+#else
+          /*Call legacy weak error callback*/
+          HAL_UART_ErrorCallback(huart);
+ 803f788:	6878      	ldr	r0, [r7, #4]
+ 803f78a:	f7fe fbcf 	bl	803df2c <HAL_UART_ErrorCallback>
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+          huart->ErrorCode = HAL_UART_ERROR_NONE;
+ 803f78e:	687b      	ldr	r3, [r7, #4]
+ 803f790:	2200      	movs	r2, #0
+ 803f792:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90
+        }
+      }
+
+      if (huart->RxXferCount == 0U)
+ 803f796:	687b      	ldr	r3, [r7, #4]
+ 803f798:	f8b3 305e 	ldrh.w	r3, [r3, #94]	@ 0x5e
+ 803f79c:	b29b      	uxth	r3, r3
+ 803f79e:	2b00      	cmp	r3, #0
+ 803f7a0:	f040 80a0 	bne.w	803f8e4 <UART_RxISR_8BIT_FIFOEN+0x290>
+      {
+        /* Disable the UART Parity Error Interrupt and RXFT interrupt*/
+        ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ 803f7a4:	687b      	ldr	r3, [r7, #4]
+ 803f7a6:	681b      	ldr	r3, [r3, #0]
+ 803f7a8:	673b      	str	r3, [r7, #112]	@ 0x70
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ 803f7aa:	6f3b      	ldr	r3, [r7, #112]	@ 0x70
+ 803f7ac:	e853 3f00 	ldrex	r3, [r3]
+ 803f7b0:	66fb      	str	r3, [r7, #108]	@ 0x6c
+   return(result);
+ 803f7b2:	6efb      	ldr	r3, [r7, #108]	@ 0x6c
+ 803f7b4:	f423 7380 	bic.w	r3, r3, #256	@ 0x100
+ 803f7b8:	f8c7 3098 	str.w	r3, [r7, #152]	@ 0x98
+ 803f7bc:	687b      	ldr	r3, [r7, #4]
+ 803f7be:	681b      	ldr	r3, [r3, #0]
+ 803f7c0:	461a      	mov	r2, r3
+ 803f7c2:	f8d7 3098 	ldr.w	r3, [r7, #152]	@ 0x98
+ 803f7c6:	67fb      	str	r3, [r7, #124]	@ 0x7c
+ 803f7c8:	67ba      	str	r2, [r7, #120]	@ 0x78
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ 803f7ca:	6fb9      	ldr	r1, [r7, #120]	@ 0x78
+ 803f7cc:	6ffa      	ldr	r2, [r7, #124]	@ 0x7c
+ 803f7ce:	e841 2300 	strex	r3, r2, [r1]
+ 803f7d2:	677b      	str	r3, [r7, #116]	@ 0x74
+   return(result);
+ 803f7d4:	6f7b      	ldr	r3, [r7, #116]	@ 0x74
+ 803f7d6:	2b00      	cmp	r3, #0
+ 803f7d8:	d1e4      	bne.n	803f7a4 <UART_RxISR_8BIT_FIFOEN+0x150>
+
+        /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error)
+           and RX FIFO Threshold interrupt */
+        ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+ 803f7da:	687b      	ldr	r3, [r7, #4]
+ 803f7dc:	681b      	ldr	r3, [r3, #0]
+ 803f7de:	3308      	adds	r3, #8
+ 803f7e0:	65fb      	str	r3, [r7, #92]	@ 0x5c
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ 803f7e2:	6dfb      	ldr	r3, [r7, #92]	@ 0x5c
+ 803f7e4:	e853 3f00 	ldrex	r3, [r3]
+ 803f7e8:	65bb      	str	r3, [r7, #88]	@ 0x58
+   return(result);
+ 803f7ea:	6dba      	ldr	r2, [r7, #88]	@ 0x58
+ 803f7ec:	4b6e      	ldr	r3, [pc, #440]	@ (803f9a8 <UART_RxISR_8BIT_FIFOEN+0x354>)
+ 803f7ee:	4013      	ands	r3, r2
+ 803f7f0:	f8c7 3094 	str.w	r3, [r7, #148]	@ 0x94
+ 803f7f4:	687b      	ldr	r3, [r7, #4]
+ 803f7f6:	681b      	ldr	r3, [r3, #0]
+ 803f7f8:	3308      	adds	r3, #8
+ 803f7fa:	f8d7 2094 	ldr.w	r2, [r7, #148]	@ 0x94
+ 803f7fe:	66ba      	str	r2, [r7, #104]	@ 0x68
+ 803f800:	667b      	str	r3, [r7, #100]	@ 0x64
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ 803f802:	6e79      	ldr	r1, [r7, #100]	@ 0x64
+ 803f804:	6eba      	ldr	r2, [r7, #104]	@ 0x68
+ 803f806:	e841 2300 	strex	r3, r2, [r1]
+ 803f80a:	663b      	str	r3, [r7, #96]	@ 0x60
+   return(result);
+ 803f80c:	6e3b      	ldr	r3, [r7, #96]	@ 0x60
+ 803f80e:	2b00      	cmp	r3, #0
+ 803f810:	d1e3      	bne.n	803f7da <UART_RxISR_8BIT_FIFOEN+0x186>
+
+        /* Rx process is completed, restore huart->RxState to Ready */
+        huart->RxState = HAL_UART_STATE_READY;
+ 803f812:	687b      	ldr	r3, [r7, #4]
+ 803f814:	2220      	movs	r2, #32
+ 803f816:	f8c3 208c 	str.w	r2, [r3, #140]	@ 0x8c
+
+        /* Clear RxISR function pointer */
+        huart->RxISR = NULL;
+ 803f81a:	687b      	ldr	r3, [r7, #4]
+ 803f81c:	2200      	movs	r2, #0
+ 803f81e:	675a      	str	r2, [r3, #116]	@ 0x74
+
+        /* Initialize type of RxEvent to Transfer Complete */
+        huart->RxEventType = HAL_UART_RXEVENT_TC;
+ 803f820:	687b      	ldr	r3, [r7, #4]
+ 803f822:	2200      	movs	r2, #0
+ 803f824:	671a      	str	r2, [r3, #112]	@ 0x70
+
+        if (!(IS_LPUART_INSTANCE(huart->Instance)))
+ 803f826:	687b      	ldr	r3, [r7, #4]
+ 803f828:	681b      	ldr	r3, [r3, #0]
+ 803f82a:	4a60      	ldr	r2, [pc, #384]	@ (803f9ac <UART_RxISR_8BIT_FIFOEN+0x358>)
+ 803f82c:	4293      	cmp	r3, r2
+ 803f82e:	d021      	beq.n	803f874 <UART_RxISR_8BIT_FIFOEN+0x220>
+        {
+          /* Check that USART RTOEN bit is set */
+          if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+ 803f830:	687b      	ldr	r3, [r7, #4]
+ 803f832:	681b      	ldr	r3, [r3, #0]
+ 803f834:	685b      	ldr	r3, [r3, #4]
+ 803f836:	f403 0300 	and.w	r3, r3, #8388608	@ 0x800000
+ 803f83a:	2b00      	cmp	r3, #0
+ 803f83c:	d01a      	beq.n	803f874 <UART_RxISR_8BIT_FIFOEN+0x220>
+          {
+            /* Enable the UART Receiver Timeout Interrupt */
+            ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+ 803f83e:	687b      	ldr	r3, [r7, #4]
+ 803f840:	681b      	ldr	r3, [r3, #0]
+ 803f842:	64bb      	str	r3, [r7, #72]	@ 0x48
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ 803f844:	6cbb      	ldr	r3, [r7, #72]	@ 0x48
+ 803f846:	e853 3f00 	ldrex	r3, [r3]
+ 803f84a:	647b      	str	r3, [r7, #68]	@ 0x44
+   return(result);
+ 803f84c:	6c7b      	ldr	r3, [r7, #68]	@ 0x44
+ 803f84e:	f023 6380 	bic.w	r3, r3, #67108864	@ 0x4000000
+ 803f852:	f8c7 3090 	str.w	r3, [r7, #144]	@ 0x90
+ 803f856:	687b      	ldr	r3, [r7, #4]
+ 803f858:	681b      	ldr	r3, [r3, #0]
+ 803f85a:	461a      	mov	r2, r3
+ 803f85c:	f8d7 3090 	ldr.w	r3, [r7, #144]	@ 0x90
+ 803f860:	657b      	str	r3, [r7, #84]	@ 0x54
+ 803f862:	653a      	str	r2, [r7, #80]	@ 0x50
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ 803f864:	6d39      	ldr	r1, [r7, #80]	@ 0x50
+ 803f866:	6d7a      	ldr	r2, [r7, #84]	@ 0x54
+ 803f868:	e841 2300 	strex	r3, r2, [r1]
+ 803f86c:	64fb      	str	r3, [r7, #76]	@ 0x4c
+   return(result);
+ 803f86e:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
+ 803f870:	2b00      	cmp	r3, #0
+ 803f872:	d1e4      	bne.n	803f83e <UART_RxISR_8BIT_FIFOEN+0x1ea>
+          }
+        }
+
+        /* Check current reception Mode :
+           If Reception till IDLE event has been selected : */
+        if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ 803f874:	687b      	ldr	r3, [r7, #4]
+ 803f876:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
+ 803f878:	2b01      	cmp	r3, #1
+ 803f87a:	d130      	bne.n	803f8de <UART_RxISR_8BIT_FIFOEN+0x28a>
+        {
+          /* Set reception type to Standard */
+          huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ 803f87c:	687b      	ldr	r3, [r7, #4]
+ 803f87e:	2200      	movs	r2, #0
+ 803f880:	66da      	str	r2, [r3, #108]	@ 0x6c
+
+          /* Disable IDLE interrupt */
+          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ 803f882:	687b      	ldr	r3, [r7, #4]
+ 803f884:	681b      	ldr	r3, [r3, #0]
+ 803f886:	637b      	str	r3, [r7, #52]	@ 0x34
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ 803f888:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
+ 803f88a:	e853 3f00 	ldrex	r3, [r3]
+ 803f88e:	633b      	str	r3, [r7, #48]	@ 0x30
+   return(result);
+ 803f890:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
+ 803f892:	f023 0310 	bic.w	r3, r3, #16
+ 803f896:	f8c7 308c 	str.w	r3, [r7, #140]	@ 0x8c
+ 803f89a:	687b      	ldr	r3, [r7, #4]
+ 803f89c:	681b      	ldr	r3, [r3, #0]
+ 803f89e:	461a      	mov	r2, r3
+ 803f8a0:	f8d7 308c 	ldr.w	r3, [r7, #140]	@ 0x8c
+ 803f8a4:	643b      	str	r3, [r7, #64]	@ 0x40
+ 803f8a6:	63fa      	str	r2, [r7, #60]	@ 0x3c
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ 803f8a8:	6bf9      	ldr	r1, [r7, #60]	@ 0x3c
+ 803f8aa:	6c3a      	ldr	r2, [r7, #64]	@ 0x40
+ 803f8ac:	e841 2300 	strex	r3, r2, [r1]
+ 803f8b0:	63bb      	str	r3, [r7, #56]	@ 0x38
+   return(result);
+ 803f8b2:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 803f8b4:	2b00      	cmp	r3, #0
+ 803f8b6:	d1e4      	bne.n	803f882 <UART_RxISR_8BIT_FIFOEN+0x22e>
+
+          if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
+ 803f8b8:	687b      	ldr	r3, [r7, #4]
+ 803f8ba:	681b      	ldr	r3, [r3, #0]
+ 803f8bc:	69db      	ldr	r3, [r3, #28]
+ 803f8be:	f003 0310 	and.w	r3, r3, #16
+ 803f8c2:	2b10      	cmp	r3, #16
+ 803f8c4:	d103      	bne.n	803f8ce <UART_RxISR_8BIT_FIFOEN+0x27a>
+          {
+            /* Clear IDLE Flag */
+            __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+ 803f8c6:	687b      	ldr	r3, [r7, #4]
+ 803f8c8:	681b      	ldr	r3, [r3, #0]
+ 803f8ca:	2210      	movs	r2, #16
+ 803f8cc:	621a      	str	r2, [r3, #32]
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+          /*Call registered Rx Event callback*/
+          huart->RxEventCallback(huart, huart->RxXferSize);
+#else
+          /*Call legacy weak Rx Event callback*/
+          HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+ 803f8ce:	687b      	ldr	r3, [r7, #4]
+ 803f8d0:	f8b3 305c 	ldrh.w	r3, [r3, #92]	@ 0x5c
+ 803f8d4:	4619      	mov	r1, r3
+ 803f8d6:	6878      	ldr	r0, [r7, #4]
+ 803f8d8:	f7fe fb32 	bl	803df40 <HAL_UARTEx_RxEventCallback>
+ 803f8dc:	e002      	b.n	803f8e4 <UART_RxISR_8BIT_FIFOEN+0x290>
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+          /*Call registered Rx complete callback*/
+          huart->RxCpltCallback(huart);
+#else
+          /*Call legacy weak Rx complete callback*/
+          HAL_UART_RxCpltCallback(huart);
+ 803f8de:	6878      	ldr	r0, [r7, #4]
+ 803f8e0:	f7e2 f97a 	bl	8021bd8 <HAL_UART_RxCpltCallback>
+    while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
+ 803f8e4:	f8b7 309e 	ldrh.w	r3, [r7, #158]	@ 0x9e
+ 803f8e8:	2b00      	cmp	r3, #0
+ 803f8ea:	d006      	beq.n	803f8fa <UART_RxISR_8BIT_FIFOEN+0x2a6>
+ 803f8ec:	f8d7 30ac 	ldr.w	r3, [r7, #172]	@ 0xac
+ 803f8f0:	f003 0320 	and.w	r3, r3, #32
+ 803f8f4:	2b00      	cmp	r3, #0
+ 803f8f6:	f47f aed1 	bne.w	803f69c <UART_RxISR_8BIT_FIFOEN+0x48>
+
+    /* When remaining number of bytes to receive is less than the RX FIFO
+    threshold, next incoming frames are processed as if FIFO mode was
+    disabled (i.e. one interrupt per received frame).
+    */
+    rxdatacount = huart->RxXferCount;
+ 803f8fa:	687b      	ldr	r3, [r7, #4]
+ 803f8fc:	f8b3 305e 	ldrh.w	r3, [r3, #94]	@ 0x5e
+ 803f900:	f8a7 308a 	strh.w	r3, [r7, #138]	@ 0x8a
+    if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
+ 803f904:	f8b7 308a 	ldrh.w	r3, [r7, #138]	@ 0x8a
+ 803f908:	2b00      	cmp	r3, #0
+ 803f90a:	d049      	beq.n	803f9a0 <UART_RxISR_8BIT_FIFOEN+0x34c>
+ 803f90c:	687b      	ldr	r3, [r7, #4]
+ 803f90e:	f8b3 3068 	ldrh.w	r3, [r3, #104]	@ 0x68
+ 803f912:	f8b7 208a 	ldrh.w	r2, [r7, #138]	@ 0x8a
+ 803f916:	429a      	cmp	r2, r3
+ 803f918:	d242      	bcs.n	803f9a0 <UART_RxISR_8BIT_FIFOEN+0x34c>
+    {
+      /* Disable the UART RXFT interrupt*/
+      ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
+ 803f91a:	687b      	ldr	r3, [r7, #4]
+ 803f91c:	681b      	ldr	r3, [r3, #0]
+ 803f91e:	3308      	adds	r3, #8
+ 803f920:	623b      	str	r3, [r7, #32]
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ 803f922:	6a3b      	ldr	r3, [r7, #32]
+ 803f924:	e853 3f00 	ldrex	r3, [r3]
+ 803f928:	61fb      	str	r3, [r7, #28]
+   return(result);
+ 803f92a:	69fb      	ldr	r3, [r7, #28]
+ 803f92c:	f023 5380 	bic.w	r3, r3, #268435456	@ 0x10000000
+ 803f930:	f8c7 3084 	str.w	r3, [r7, #132]	@ 0x84
+ 803f934:	687b      	ldr	r3, [r7, #4]
+ 803f936:	681b      	ldr	r3, [r3, #0]
+ 803f938:	3308      	adds	r3, #8
+ 803f93a:	f8d7 2084 	ldr.w	r2, [r7, #132]	@ 0x84
+ 803f93e:	62fa      	str	r2, [r7, #44]	@ 0x2c
+ 803f940:	62bb      	str	r3, [r7, #40]	@ 0x28
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ 803f942:	6ab9      	ldr	r1, [r7, #40]	@ 0x28
+ 803f944:	6afa      	ldr	r2, [r7, #44]	@ 0x2c
+ 803f946:	e841 2300 	strex	r3, r2, [r1]
+ 803f94a:	627b      	str	r3, [r7, #36]	@ 0x24
+   return(result);
+ 803f94c:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 803f94e:	2b00      	cmp	r3, #0
+ 803f950:	d1e3      	bne.n	803f91a <UART_RxISR_8BIT_FIFOEN+0x2c6>
+
+      /* Update the RxISR function pointer */
+      huart->RxISR = UART_RxISR_8BIT;
+ 803f952:	687b      	ldr	r3, [r7, #4]
+ 803f954:	4a16      	ldr	r2, [pc, #88]	@ (803f9b0 <UART_RxISR_8BIT_FIFOEN+0x35c>)
+ 803f956:	675a      	str	r2, [r3, #116]	@ 0x74
+
+      /* Enable the UART Data Register Not Empty interrupt */
+      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+ 803f958:	687b      	ldr	r3, [r7, #4]
+ 803f95a:	681b      	ldr	r3, [r3, #0]
+ 803f95c:	60fb      	str	r3, [r7, #12]
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ 803f95e:	68fb      	ldr	r3, [r7, #12]
+ 803f960:	e853 3f00 	ldrex	r3, [r3]
+ 803f964:	60bb      	str	r3, [r7, #8]
+   return(result);
+ 803f966:	68bb      	ldr	r3, [r7, #8]
+ 803f968:	f043 0320 	orr.w	r3, r3, #32
+ 803f96c:	f8c7 3080 	str.w	r3, [r7, #128]	@ 0x80
+ 803f970:	687b      	ldr	r3, [r7, #4]
+ 803f972:	681b      	ldr	r3, [r3, #0]
+ 803f974:	461a      	mov	r2, r3
+ 803f976:	f8d7 3080 	ldr.w	r3, [r7, #128]	@ 0x80
+ 803f97a:	61bb      	str	r3, [r7, #24]
+ 803f97c:	617a      	str	r2, [r7, #20]
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ 803f97e:	6979      	ldr	r1, [r7, #20]
+ 803f980:	69ba      	ldr	r2, [r7, #24]
+ 803f982:	e841 2300 	strex	r3, r2, [r1]
+ 803f986:	613b      	str	r3, [r7, #16]
+   return(result);
+ 803f988:	693b      	ldr	r3, [r7, #16]
+ 803f98a:	2b00      	cmp	r3, #0
+ 803f98c:	d1e4      	bne.n	803f958 <UART_RxISR_8BIT_FIFOEN+0x304>
+  else
+  {
+    /* Clear RXNE interrupt flag */
+    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+  }
+}
+ 803f98e:	e007      	b.n	803f9a0 <UART_RxISR_8BIT_FIFOEN+0x34c>
+    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+ 803f990:	687b      	ldr	r3, [r7, #4]
+ 803f992:	681b      	ldr	r3, [r3, #0]
+ 803f994:	699a      	ldr	r2, [r3, #24]
+ 803f996:	687b      	ldr	r3, [r7, #4]
+ 803f998:	681b      	ldr	r3, [r3, #0]
+ 803f99a:	f042 0208 	orr.w	r2, r2, #8
+ 803f99e:	619a      	str	r2, [r3, #24]
+}
+ 803f9a0:	bf00      	nop
+ 803f9a2:	37b0      	adds	r7, #176	@ 0xb0
+ 803f9a4:	46bd      	mov	sp, r7
+ 803f9a6:	bd80      	pop	{r7, pc}
+ 803f9a8:	effffffe 	.word	0xeffffffe
+ 803f9ac:	58000c00 	.word	0x58000c00
+ 803f9b0:	0803f2e5 	.word	0x0803f2e5
+
+0803f9b4 <UART_RxISR_16BIT_FIFOEN>:
+  *         interruptions have been enabled by HAL_UART_Receive_IT()
+  * @param huart UART handle.
+  * @retval None
+  */
+static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
+{
+ 803f9b4:	b580      	push	{r7, lr}
+ 803f9b6:	b0ae      	sub	sp, #184	@ 0xb8
+ 803f9b8:	af00      	add	r7, sp, #0
+ 803f9ba:	6078      	str	r0, [r7, #4]
+  uint16_t *tmp;
+  uint16_t  uhMask = huart->Mask;
+ 803f9bc:	687b      	ldr	r3, [r7, #4]
+ 803f9be:	f8b3 3060 	ldrh.w	r3, [r3, #96]	@ 0x60
+ 803f9c2:	f8a7 30b2 	strh.w	r3, [r7, #178]	@ 0xb2
+  uint16_t  uhdata;
+  uint16_t  nb_rx_data;
+  uint16_t  rxdatacount;
+  uint32_t  isrflags = READ_REG(huart->Instance->ISR);
+ 803f9c6:	687b      	ldr	r3, [r7, #4]
+ 803f9c8:	681b      	ldr	r3, [r3, #0]
+ 803f9ca:	69db      	ldr	r3, [r3, #28]
+ 803f9cc:	f8c7 30b4 	str.w	r3, [r7, #180]	@ 0xb4
+  uint32_t  cr1its   = READ_REG(huart->Instance->CR1);
+ 803f9d0:	687b      	ldr	r3, [r7, #4]
+ 803f9d2:	681b      	ldr	r3, [r3, #0]
+ 803f9d4:	681b      	ldr	r3, [r3, #0]
+ 803f9d6:	f8c7 30ac 	str.w	r3, [r7, #172]	@ 0xac
+  uint32_t  cr3its   = READ_REG(huart->Instance->CR3);
+ 803f9da:	687b      	ldr	r3, [r7, #4]
+ 803f9dc:	681b      	ldr	r3, [r3, #0]
+ 803f9de:	689b      	ldr	r3, [r3, #8]
+ 803f9e0:	f8c7 30a8 	str.w	r3, [r7, #168]	@ 0xa8
+
+  /* Check that a Rx process is ongoing */
+  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+ 803f9e4:	687b      	ldr	r3, [r7, #4]
+ 803f9e6:	f8d3 308c 	ldr.w	r3, [r3, #140]	@ 0x8c
+ 803f9ea:	2b22      	cmp	r3, #34	@ 0x22
+ 803f9ec:	f040 8184 	bne.w	803fcf8 <UART_RxISR_16BIT_FIFOEN+0x344>
+  {
+    nb_rx_data = huart->NbRxDataToProcess;
+ 803f9f0:	687b      	ldr	r3, [r7, #4]
+ 803f9f2:	f8b3 3068 	ldrh.w	r3, [r3, #104]	@ 0x68
+ 803f9f6:	f8a7 30a6 	strh.w	r3, [r7, #166]	@ 0xa6
+    while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
+ 803f9fa:	e127      	b.n	803fc4c <UART_RxISR_16BIT_FIFOEN+0x298>
+    {
+      uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
+ 803f9fc:	687b      	ldr	r3, [r7, #4]
+ 803f9fe:	681b      	ldr	r3, [r3, #0]
+ 803fa00:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 803fa02:	f8a7 30a4 	strh.w	r3, [r7, #164]	@ 0xa4
+      tmp = (uint16_t *) huart->pRxBuffPtr ;
+ 803fa06:	687b      	ldr	r3, [r7, #4]
+ 803fa08:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
+ 803fa0a:	f8c7 30a0 	str.w	r3, [r7, #160]	@ 0xa0
+      *tmp = (uint16_t)(uhdata & uhMask);
+ 803fa0e:	f8b7 20a4 	ldrh.w	r2, [r7, #164]	@ 0xa4
+ 803fa12:	f8b7 30b2 	ldrh.w	r3, [r7, #178]	@ 0xb2
+ 803fa16:	4013      	ands	r3, r2
+ 803fa18:	b29a      	uxth	r2, r3
+ 803fa1a:	f8d7 30a0 	ldr.w	r3, [r7, #160]	@ 0xa0
+ 803fa1e:	801a      	strh	r2, [r3, #0]
+      huart->pRxBuffPtr += 2U;
+ 803fa20:	687b      	ldr	r3, [r7, #4]
+ 803fa22:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
+ 803fa24:	1c9a      	adds	r2, r3, #2
+ 803fa26:	687b      	ldr	r3, [r7, #4]
+ 803fa28:	659a      	str	r2, [r3, #88]	@ 0x58
+      huart->RxXferCount--;
+ 803fa2a:	687b      	ldr	r3, [r7, #4]
+ 803fa2c:	f8b3 305e 	ldrh.w	r3, [r3, #94]	@ 0x5e
+ 803fa30:	b29b      	uxth	r3, r3
+ 803fa32:	3b01      	subs	r3, #1
+ 803fa34:	b29a      	uxth	r2, r3
+ 803fa36:	687b      	ldr	r3, [r7, #4]
+ 803fa38:	f8a3 205e 	strh.w	r2, [r3, #94]	@ 0x5e
+      isrflags = READ_REG(huart->Instance->ISR);
+ 803fa3c:	687b      	ldr	r3, [r7, #4]
+ 803fa3e:	681b      	ldr	r3, [r3, #0]
+ 803fa40:	69db      	ldr	r3, [r3, #28]
+ 803fa42:	f8c7 30b4 	str.w	r3, [r7, #180]	@ 0xb4
+
+      /* If some non blocking errors occurred */
+      if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U)
+ 803fa46:	f8d7 30b4 	ldr.w	r3, [r7, #180]	@ 0xb4
+ 803fa4a:	f003 0307 	and.w	r3, r3, #7
+ 803fa4e:	2b00      	cmp	r3, #0
+ 803fa50:	d053      	beq.n	803fafa <UART_RxISR_16BIT_FIFOEN+0x146>
+      {
+        /* UART parity error interrupt occurred -------------------------------------*/
+        if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
+ 803fa52:	f8d7 30b4 	ldr.w	r3, [r7, #180]	@ 0xb4
+ 803fa56:	f003 0301 	and.w	r3, r3, #1
+ 803fa5a:	2b00      	cmp	r3, #0
+ 803fa5c:	d011      	beq.n	803fa82 <UART_RxISR_16BIT_FIFOEN+0xce>
+ 803fa5e:	f8d7 30ac 	ldr.w	r3, [r7, #172]	@ 0xac
+ 803fa62:	f403 7380 	and.w	r3, r3, #256	@ 0x100
+ 803fa66:	2b00      	cmp	r3, #0
+ 803fa68:	d00b      	beq.n	803fa82 <UART_RxISR_16BIT_FIFOEN+0xce>
+        {
+          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
+ 803fa6a:	687b      	ldr	r3, [r7, #4]
+ 803fa6c:	681b      	ldr	r3, [r3, #0]
+ 803fa6e:	2201      	movs	r2, #1
+ 803fa70:	621a      	str	r2, [r3, #32]
+
+          huart->ErrorCode |= HAL_UART_ERROR_PE;
+ 803fa72:	687b      	ldr	r3, [r7, #4]
+ 803fa74:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
+ 803fa78:	f043 0201 	orr.w	r2, r3, #1
+ 803fa7c:	687b      	ldr	r3, [r7, #4]
+ 803fa7e:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90
+        }
+
+        /* UART frame error interrupt occurred --------------------------------------*/
+        if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+ 803fa82:	f8d7 30b4 	ldr.w	r3, [r7, #180]	@ 0xb4
+ 803fa86:	f003 0302 	and.w	r3, r3, #2
+ 803fa8a:	2b00      	cmp	r3, #0
+ 803fa8c:	d011      	beq.n	803fab2 <UART_RxISR_16BIT_FIFOEN+0xfe>
+ 803fa8e:	f8d7 30a8 	ldr.w	r3, [r7, #168]	@ 0xa8
+ 803fa92:	f003 0301 	and.w	r3, r3, #1
+ 803fa96:	2b00      	cmp	r3, #0
+ 803fa98:	d00b      	beq.n	803fab2 <UART_RxISR_16BIT_FIFOEN+0xfe>
+        {
+          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
+ 803fa9a:	687b      	ldr	r3, [r7, #4]
+ 803fa9c:	681b      	ldr	r3, [r3, #0]
+ 803fa9e:	2202      	movs	r2, #2
+ 803faa0:	621a      	str	r2, [r3, #32]
+
+          huart->ErrorCode |= HAL_UART_ERROR_FE;
+ 803faa2:	687b      	ldr	r3, [r7, #4]
+ 803faa4:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
+ 803faa8:	f043 0204 	orr.w	r2, r3, #4
+ 803faac:	687b      	ldr	r3, [r7, #4]
+ 803faae:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90
+        }
+
+        /* UART noise error interrupt occurred --------------------------------------*/
+        if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+ 803fab2:	f8d7 30b4 	ldr.w	r3, [r7, #180]	@ 0xb4
+ 803fab6:	f003 0304 	and.w	r3, r3, #4
+ 803faba:	2b00      	cmp	r3, #0
+ 803fabc:	d011      	beq.n	803fae2 <UART_RxISR_16BIT_FIFOEN+0x12e>
+ 803fabe:	f8d7 30a8 	ldr.w	r3, [r7, #168]	@ 0xa8
+ 803fac2:	f003 0301 	and.w	r3, r3, #1
+ 803fac6:	2b00      	cmp	r3, #0
+ 803fac8:	d00b      	beq.n	803fae2 <UART_RxISR_16BIT_FIFOEN+0x12e>
+        {
+          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
+ 803faca:	687b      	ldr	r3, [r7, #4]
+ 803facc:	681b      	ldr	r3, [r3, #0]
+ 803face:	2204      	movs	r2, #4
+ 803fad0:	621a      	str	r2, [r3, #32]
+
+          huart->ErrorCode |= HAL_UART_ERROR_NE;
+ 803fad2:	687b      	ldr	r3, [r7, #4]
+ 803fad4:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
+ 803fad8:	f043 0202 	orr.w	r2, r3, #2
+ 803fadc:	687b      	ldr	r3, [r7, #4]
+ 803fade:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90
+        }
+
+        /* Call UART Error Call back function if need be ----------------------------*/
+        if (huart->ErrorCode != HAL_UART_ERROR_NONE)
+ 803fae2:	687b      	ldr	r3, [r7, #4]
+ 803fae4:	f8d3 3090 	ldr.w	r3, [r3, #144]	@ 0x90
+ 803fae8:	2b00      	cmp	r3, #0
+ 803faea:	d006      	beq.n	803fafa <UART_RxISR_16BIT_FIFOEN+0x146>
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+          /*Call registered error callback*/
+          huart->ErrorCallback(huart);
+#else
+          /*Call legacy weak error callback*/
+          HAL_UART_ErrorCallback(huart);
+ 803faec:	6878      	ldr	r0, [r7, #4]
+ 803faee:	f7fe fa1d 	bl	803df2c <HAL_UART_ErrorCallback>
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+          huart->ErrorCode = HAL_UART_ERROR_NONE;
+ 803faf2:	687b      	ldr	r3, [r7, #4]
+ 803faf4:	2200      	movs	r2, #0
+ 803faf6:	f8c3 2090 	str.w	r2, [r3, #144]	@ 0x90
+        }
+      }
+
+      if (huart->RxXferCount == 0U)
+ 803fafa:	687b      	ldr	r3, [r7, #4]
+ 803fafc:	f8b3 305e 	ldrh.w	r3, [r3, #94]	@ 0x5e
+ 803fb00:	b29b      	uxth	r3, r3
+ 803fb02:	2b00      	cmp	r3, #0
+ 803fb04:	f040 80a2 	bne.w	803fc4c <UART_RxISR_16BIT_FIFOEN+0x298>
+      {
+        /* Disable the UART Parity Error Interrupt and RXFT interrupt*/
+        ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ 803fb08:	687b      	ldr	r3, [r7, #4]
+ 803fb0a:	681b      	ldr	r3, [r3, #0]
+ 803fb0c:	677b      	str	r3, [r7, #116]	@ 0x74
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ 803fb0e:	6f7b      	ldr	r3, [r7, #116]	@ 0x74
+ 803fb10:	e853 3f00 	ldrex	r3, [r3]
+ 803fb14:	673b      	str	r3, [r7, #112]	@ 0x70
+   return(result);
+ 803fb16:	6f3b      	ldr	r3, [r7, #112]	@ 0x70
+ 803fb18:	f423 7380 	bic.w	r3, r3, #256	@ 0x100
+ 803fb1c:	f8c7 309c 	str.w	r3, [r7, #156]	@ 0x9c
+ 803fb20:	687b      	ldr	r3, [r7, #4]
+ 803fb22:	681b      	ldr	r3, [r3, #0]
+ 803fb24:	461a      	mov	r2, r3
+ 803fb26:	f8d7 309c 	ldr.w	r3, [r7, #156]	@ 0x9c
+ 803fb2a:	f8c7 3080 	str.w	r3, [r7, #128]	@ 0x80
+ 803fb2e:	67fa      	str	r2, [r7, #124]	@ 0x7c
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ 803fb30:	6ff9      	ldr	r1, [r7, #124]	@ 0x7c
+ 803fb32:	f8d7 2080 	ldr.w	r2, [r7, #128]	@ 0x80
+ 803fb36:	e841 2300 	strex	r3, r2, [r1]
+ 803fb3a:	67bb      	str	r3, [r7, #120]	@ 0x78
+   return(result);
+ 803fb3c:	6fbb      	ldr	r3, [r7, #120]	@ 0x78
+ 803fb3e:	2b00      	cmp	r3, #0
+ 803fb40:	d1e2      	bne.n	803fb08 <UART_RxISR_16BIT_FIFOEN+0x154>
+
+        /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error)
+           and RX FIFO Threshold interrupt */
+        ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+ 803fb42:	687b      	ldr	r3, [r7, #4]
+ 803fb44:	681b      	ldr	r3, [r3, #0]
+ 803fb46:	3308      	adds	r3, #8
+ 803fb48:	663b      	str	r3, [r7, #96]	@ 0x60
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ 803fb4a:	6e3b      	ldr	r3, [r7, #96]	@ 0x60
+ 803fb4c:	e853 3f00 	ldrex	r3, [r3]
+ 803fb50:	65fb      	str	r3, [r7, #92]	@ 0x5c
+   return(result);
+ 803fb52:	6dfa      	ldr	r2, [r7, #92]	@ 0x5c
+ 803fb54:	4b6e      	ldr	r3, [pc, #440]	@ (803fd10 <UART_RxISR_16BIT_FIFOEN+0x35c>)
+ 803fb56:	4013      	ands	r3, r2
+ 803fb58:	f8c7 3098 	str.w	r3, [r7, #152]	@ 0x98
+ 803fb5c:	687b      	ldr	r3, [r7, #4]
+ 803fb5e:	681b      	ldr	r3, [r3, #0]
+ 803fb60:	3308      	adds	r3, #8
+ 803fb62:	f8d7 2098 	ldr.w	r2, [r7, #152]	@ 0x98
+ 803fb66:	66fa      	str	r2, [r7, #108]	@ 0x6c
+ 803fb68:	66bb      	str	r3, [r7, #104]	@ 0x68
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ 803fb6a:	6eb9      	ldr	r1, [r7, #104]	@ 0x68
+ 803fb6c:	6efa      	ldr	r2, [r7, #108]	@ 0x6c
+ 803fb6e:	e841 2300 	strex	r3, r2, [r1]
+ 803fb72:	667b      	str	r3, [r7, #100]	@ 0x64
+   return(result);
+ 803fb74:	6e7b      	ldr	r3, [r7, #100]	@ 0x64
+ 803fb76:	2b00      	cmp	r3, #0
+ 803fb78:	d1e3      	bne.n	803fb42 <UART_RxISR_16BIT_FIFOEN+0x18e>
+
+        /* Rx process is completed, restore huart->RxState to Ready */
+        huart->RxState = HAL_UART_STATE_READY;
+ 803fb7a:	687b      	ldr	r3, [r7, #4]
+ 803fb7c:	2220      	movs	r2, #32
+ 803fb7e:	f8c3 208c 	str.w	r2, [r3, #140]	@ 0x8c
+
+        /* Clear RxISR function pointer */
+        huart->RxISR = NULL;
+ 803fb82:	687b      	ldr	r3, [r7, #4]
+ 803fb84:	2200      	movs	r2, #0
+ 803fb86:	675a      	str	r2, [r3, #116]	@ 0x74
+
+        /* Initialize type of RxEvent to Transfer Complete */
+        huart->RxEventType = HAL_UART_RXEVENT_TC;
+ 803fb88:	687b      	ldr	r3, [r7, #4]
+ 803fb8a:	2200      	movs	r2, #0
+ 803fb8c:	671a      	str	r2, [r3, #112]	@ 0x70
+
+        if (!(IS_LPUART_INSTANCE(huart->Instance)))
+ 803fb8e:	687b      	ldr	r3, [r7, #4]
+ 803fb90:	681b      	ldr	r3, [r3, #0]
+ 803fb92:	4a60      	ldr	r2, [pc, #384]	@ (803fd14 <UART_RxISR_16BIT_FIFOEN+0x360>)
+ 803fb94:	4293      	cmp	r3, r2
+ 803fb96:	d021      	beq.n	803fbdc <UART_RxISR_16BIT_FIFOEN+0x228>
+        {
+          /* Check that USART RTOEN bit is set */
+          if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+ 803fb98:	687b      	ldr	r3, [r7, #4]
+ 803fb9a:	681b      	ldr	r3, [r3, #0]
+ 803fb9c:	685b      	ldr	r3, [r3, #4]
+ 803fb9e:	f403 0300 	and.w	r3, r3, #8388608	@ 0x800000
+ 803fba2:	2b00      	cmp	r3, #0
+ 803fba4:	d01a      	beq.n	803fbdc <UART_RxISR_16BIT_FIFOEN+0x228>
+          {
+            /* Enable the UART Receiver Timeout Interrupt */
+            ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+ 803fba6:	687b      	ldr	r3, [r7, #4]
+ 803fba8:	681b      	ldr	r3, [r3, #0]
+ 803fbaa:	64fb      	str	r3, [r7, #76]	@ 0x4c
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ 803fbac:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
+ 803fbae:	e853 3f00 	ldrex	r3, [r3]
+ 803fbb2:	64bb      	str	r3, [r7, #72]	@ 0x48
+   return(result);
+ 803fbb4:	6cbb      	ldr	r3, [r7, #72]	@ 0x48
+ 803fbb6:	f023 6380 	bic.w	r3, r3, #67108864	@ 0x4000000
+ 803fbba:	f8c7 3094 	str.w	r3, [r7, #148]	@ 0x94
+ 803fbbe:	687b      	ldr	r3, [r7, #4]
+ 803fbc0:	681b      	ldr	r3, [r3, #0]
+ 803fbc2:	461a      	mov	r2, r3
+ 803fbc4:	f8d7 3094 	ldr.w	r3, [r7, #148]	@ 0x94
+ 803fbc8:	65bb      	str	r3, [r7, #88]	@ 0x58
+ 803fbca:	657a      	str	r2, [r7, #84]	@ 0x54
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ 803fbcc:	6d79      	ldr	r1, [r7, #84]	@ 0x54
+ 803fbce:	6dba      	ldr	r2, [r7, #88]	@ 0x58
+ 803fbd0:	e841 2300 	strex	r3, r2, [r1]
+ 803fbd4:	653b      	str	r3, [r7, #80]	@ 0x50
+   return(result);
+ 803fbd6:	6d3b      	ldr	r3, [r7, #80]	@ 0x50
+ 803fbd8:	2b00      	cmp	r3, #0
+ 803fbda:	d1e4      	bne.n	803fba6 <UART_RxISR_16BIT_FIFOEN+0x1f2>
+          }
+        }
+
+        /* Check current reception Mode :
+           If Reception till IDLE event has been selected : */
+        if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ 803fbdc:	687b      	ldr	r3, [r7, #4]
+ 803fbde:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
+ 803fbe0:	2b01      	cmp	r3, #1
+ 803fbe2:	d130      	bne.n	803fc46 <UART_RxISR_16BIT_FIFOEN+0x292>
+        {
+          /* Set reception type to Standard */
+          huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ 803fbe4:	687b      	ldr	r3, [r7, #4]
+ 803fbe6:	2200      	movs	r2, #0
+ 803fbe8:	66da      	str	r2, [r3, #108]	@ 0x6c
+
+          /* Disable IDLE interrupt */
+          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ 803fbea:	687b      	ldr	r3, [r7, #4]
+ 803fbec:	681b      	ldr	r3, [r3, #0]
+ 803fbee:	63bb      	str	r3, [r7, #56]	@ 0x38
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ 803fbf0:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
+ 803fbf2:	e853 3f00 	ldrex	r3, [r3]
+ 803fbf6:	637b      	str	r3, [r7, #52]	@ 0x34
+   return(result);
+ 803fbf8:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
+ 803fbfa:	f023 0310 	bic.w	r3, r3, #16
+ 803fbfe:	f8c7 3090 	str.w	r3, [r7, #144]	@ 0x90
+ 803fc02:	687b      	ldr	r3, [r7, #4]
+ 803fc04:	681b      	ldr	r3, [r3, #0]
+ 803fc06:	461a      	mov	r2, r3
+ 803fc08:	f8d7 3090 	ldr.w	r3, [r7, #144]	@ 0x90
+ 803fc0c:	647b      	str	r3, [r7, #68]	@ 0x44
+ 803fc0e:	643a      	str	r2, [r7, #64]	@ 0x40
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ 803fc10:	6c39      	ldr	r1, [r7, #64]	@ 0x40
+ 803fc12:	6c7a      	ldr	r2, [r7, #68]	@ 0x44
+ 803fc14:	e841 2300 	strex	r3, r2, [r1]
+ 803fc18:	63fb      	str	r3, [r7, #60]	@ 0x3c
+   return(result);
+ 803fc1a:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
+ 803fc1c:	2b00      	cmp	r3, #0
+ 803fc1e:	d1e4      	bne.n	803fbea <UART_RxISR_16BIT_FIFOEN+0x236>
+
+          if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
+ 803fc20:	687b      	ldr	r3, [r7, #4]
+ 803fc22:	681b      	ldr	r3, [r3, #0]
+ 803fc24:	69db      	ldr	r3, [r3, #28]
+ 803fc26:	f003 0310 	and.w	r3, r3, #16
+ 803fc2a:	2b10      	cmp	r3, #16
+ 803fc2c:	d103      	bne.n	803fc36 <UART_RxISR_16BIT_FIFOEN+0x282>
+          {
+            /* Clear IDLE Flag */
+            __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+ 803fc2e:	687b      	ldr	r3, [r7, #4]
+ 803fc30:	681b      	ldr	r3, [r3, #0]
+ 803fc32:	2210      	movs	r2, #16
+ 803fc34:	621a      	str	r2, [r3, #32]
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+          /*Call registered Rx Event callback*/
+          huart->RxEventCallback(huart, huart->RxXferSize);
+#else
+          /*Call legacy weak Rx Event callback*/
+          HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+ 803fc36:	687b      	ldr	r3, [r7, #4]
+ 803fc38:	f8b3 305c 	ldrh.w	r3, [r3, #92]	@ 0x5c
+ 803fc3c:	4619      	mov	r1, r3
+ 803fc3e:	6878      	ldr	r0, [r7, #4]
+ 803fc40:	f7fe f97e 	bl	803df40 <HAL_UARTEx_RxEventCallback>
+ 803fc44:	e002      	b.n	803fc4c <UART_RxISR_16BIT_FIFOEN+0x298>
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+          /*Call registered Rx complete callback*/
+          huart->RxCpltCallback(huart);
+#else
+          /*Call legacy weak Rx complete callback*/
+          HAL_UART_RxCpltCallback(huart);
+ 803fc46:	6878      	ldr	r0, [r7, #4]
+ 803fc48:	f7e1 ffc6 	bl	8021bd8 <HAL_UART_RxCpltCallback>
+    while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
+ 803fc4c:	f8b7 30a6 	ldrh.w	r3, [r7, #166]	@ 0xa6
+ 803fc50:	2b00      	cmp	r3, #0
+ 803fc52:	d006      	beq.n	803fc62 <UART_RxISR_16BIT_FIFOEN+0x2ae>
+ 803fc54:	f8d7 30b4 	ldr.w	r3, [r7, #180]	@ 0xb4
+ 803fc58:	f003 0320 	and.w	r3, r3, #32
+ 803fc5c:	2b00      	cmp	r3, #0
+ 803fc5e:	f47f aecd 	bne.w	803f9fc <UART_RxISR_16BIT_FIFOEN+0x48>
+
+    /* When remaining number of bytes to receive is less than the RX FIFO
+    threshold, next incoming frames are processed as if FIFO mode was
+    disabled (i.e. one interrupt per received frame).
+    */
+    rxdatacount = huart->RxXferCount;
+ 803fc62:	687b      	ldr	r3, [r7, #4]
+ 803fc64:	f8b3 305e 	ldrh.w	r3, [r3, #94]	@ 0x5e
+ 803fc68:	f8a7 308e 	strh.w	r3, [r7, #142]	@ 0x8e
+    if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
+ 803fc6c:	f8b7 308e 	ldrh.w	r3, [r7, #142]	@ 0x8e
+ 803fc70:	2b00      	cmp	r3, #0
+ 803fc72:	d049      	beq.n	803fd08 <UART_RxISR_16BIT_FIFOEN+0x354>
+ 803fc74:	687b      	ldr	r3, [r7, #4]
+ 803fc76:	f8b3 3068 	ldrh.w	r3, [r3, #104]	@ 0x68
+ 803fc7a:	f8b7 208e 	ldrh.w	r2, [r7, #142]	@ 0x8e
+ 803fc7e:	429a      	cmp	r2, r3
+ 803fc80:	d242      	bcs.n	803fd08 <UART_RxISR_16BIT_FIFOEN+0x354>
+    {
+      /* Disable the UART RXFT interrupt*/
+      ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
+ 803fc82:	687b      	ldr	r3, [r7, #4]
+ 803fc84:	681b      	ldr	r3, [r3, #0]
+ 803fc86:	3308      	adds	r3, #8
+ 803fc88:	627b      	str	r3, [r7, #36]	@ 0x24
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ 803fc8a:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
+ 803fc8c:	e853 3f00 	ldrex	r3, [r3]
+ 803fc90:	623b      	str	r3, [r7, #32]
+   return(result);
+ 803fc92:	6a3b      	ldr	r3, [r7, #32]
+ 803fc94:	f023 5380 	bic.w	r3, r3, #268435456	@ 0x10000000
+ 803fc98:	f8c7 3088 	str.w	r3, [r7, #136]	@ 0x88
+ 803fc9c:	687b      	ldr	r3, [r7, #4]
+ 803fc9e:	681b      	ldr	r3, [r3, #0]
+ 803fca0:	3308      	adds	r3, #8
+ 803fca2:	f8d7 2088 	ldr.w	r2, [r7, #136]	@ 0x88
+ 803fca6:	633a      	str	r2, [r7, #48]	@ 0x30
+ 803fca8:	62fb      	str	r3, [r7, #44]	@ 0x2c
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ 803fcaa:	6af9      	ldr	r1, [r7, #44]	@ 0x2c
+ 803fcac:	6b3a      	ldr	r2, [r7, #48]	@ 0x30
+ 803fcae:	e841 2300 	strex	r3, r2, [r1]
+ 803fcb2:	62bb      	str	r3, [r7, #40]	@ 0x28
+   return(result);
+ 803fcb4:	6abb      	ldr	r3, [r7, #40]	@ 0x28
+ 803fcb6:	2b00      	cmp	r3, #0
+ 803fcb8:	d1e3      	bne.n	803fc82 <UART_RxISR_16BIT_FIFOEN+0x2ce>
+
+      /* Update the RxISR function pointer */
+      huart->RxISR = UART_RxISR_16BIT;
+ 803fcba:	687b      	ldr	r3, [r7, #4]
+ 803fcbc:	4a16      	ldr	r2, [pc, #88]	@ (803fd18 <UART_RxISR_16BIT_FIFOEN+0x364>)
+ 803fcbe:	675a      	str	r2, [r3, #116]	@ 0x74
+
+      /* Enable the UART Data Register Not Empty interrupt */
+      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+ 803fcc0:	687b      	ldr	r3, [r7, #4]
+ 803fcc2:	681b      	ldr	r3, [r3, #0]
+ 803fcc4:	613b      	str	r3, [r7, #16]
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ 803fcc6:	693b      	ldr	r3, [r7, #16]
+ 803fcc8:	e853 3f00 	ldrex	r3, [r3]
+ 803fccc:	60fb      	str	r3, [r7, #12]
+   return(result);
+ 803fcce:	68fb      	ldr	r3, [r7, #12]
+ 803fcd0:	f043 0320 	orr.w	r3, r3, #32
+ 803fcd4:	f8c7 3084 	str.w	r3, [r7, #132]	@ 0x84
+ 803fcd8:	687b      	ldr	r3, [r7, #4]
+ 803fcda:	681b      	ldr	r3, [r3, #0]
+ 803fcdc:	461a      	mov	r2, r3
+ 803fcde:	f8d7 3084 	ldr.w	r3, [r7, #132]	@ 0x84
+ 803fce2:	61fb      	str	r3, [r7, #28]
+ 803fce4:	61ba      	str	r2, [r7, #24]
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ 803fce6:	69b9      	ldr	r1, [r7, #24]
+ 803fce8:	69fa      	ldr	r2, [r7, #28]
+ 803fcea:	e841 2300 	strex	r3, r2, [r1]
+ 803fcee:	617b      	str	r3, [r7, #20]
+   return(result);
+ 803fcf0:	697b      	ldr	r3, [r7, #20]
+ 803fcf2:	2b00      	cmp	r3, #0
+ 803fcf4:	d1e4      	bne.n	803fcc0 <UART_RxISR_16BIT_FIFOEN+0x30c>
+  else
+  {
+    /* Clear RXNE interrupt flag */
+    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+  }
+}
+ 803fcf6:	e007      	b.n	803fd08 <UART_RxISR_16BIT_FIFOEN+0x354>
+    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+ 803fcf8:	687b      	ldr	r3, [r7, #4]
+ 803fcfa:	681b      	ldr	r3, [r3, #0]
+ 803fcfc:	699a      	ldr	r2, [r3, #24]
+ 803fcfe:	687b      	ldr	r3, [r7, #4]
+ 803fd00:	681b      	ldr	r3, [r3, #0]
+ 803fd02:	f042 0208 	orr.w	r2, r2, #8
+ 803fd06:	619a      	str	r2, [r3, #24]
+}
+ 803fd08:	bf00      	nop
+ 803fd0a:	37b8      	adds	r7, #184	@ 0xb8
+ 803fd0c:	46bd      	mov	sp, r7
+ 803fd0e:	bd80      	pop	{r7, pc}
+ 803fd10:	effffffe 	.word	0xeffffffe
+ 803fd14:	58000c00 	.word	0x58000c00
+ 803fd18:	0803f49d 	.word	0x0803f49d
+
+0803fd1c <HAL_UARTEx_WakeupCallback>:
+  * @brief UART wakeup from Stop mode callback.
+  * @param huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
+{
+ 803fd1c:	b480      	push	{r7}
+ 803fd1e:	b083      	sub	sp, #12
+ 803fd20:	af00      	add	r7, sp, #0
+ 803fd22:	6078      	str	r0, [r7, #4]
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UARTEx_WakeupCallback can be implemented in the user file.
+   */
+}
+ 803fd24:	bf00      	nop
+ 803fd26:	370c      	adds	r7, #12
+ 803fd28:	46bd      	mov	sp, r7
+ 803fd2a:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 803fd2e:	4770      	bx	lr
+
+0803fd30 <HAL_UARTEx_RxFifoFullCallback>:
+  * @brief  UART RX Fifo full callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart)
+{
+ 803fd30:	b480      	push	{r7}
+ 803fd32:	b083      	sub	sp, #12
+ 803fd34:	af00      	add	r7, sp, #0
+ 803fd36:	6078      	str	r0, [r7, #4]
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file.
+   */
+}
+ 803fd38:	bf00      	nop
+ 803fd3a:	370c      	adds	r7, #12
+ 803fd3c:	46bd      	mov	sp, r7
+ 803fd3e:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 803fd42:	4770      	bx	lr
+
+0803fd44 <HAL_UARTEx_TxFifoEmptyCallback>:
+  * @brief  UART TX Fifo empty callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart)
+{
+ 803fd44:	b480      	push	{r7}
+ 803fd46:	b083      	sub	sp, #12
+ 803fd48:	af00      	add	r7, sp, #0
+ 803fd4a:	6078      	str	r0, [r7, #4]
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file.
+   */
+}
+ 803fd4c:	bf00      	nop
+ 803fd4e:	370c      	adds	r7, #12
+ 803fd50:	46bd      	mov	sp, r7
+ 803fd52:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 803fd56:	4770      	bx	lr
+
+0803fd58 <HAL_UARTEx_EnableFifoMode>:
+  * @brief  Enable the FIFO mode.
+  * @param huart      UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart)
+{
+ 803fd58:	b580      	push	{r7, lr}
+ 803fd5a:	b084      	sub	sp, #16
+ 803fd5c:	af00      	add	r7, sp, #0
+ 803fd5e:	6078      	str	r0, [r7, #4]
+
+  /* Check parameters */
+  assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
+
+  /* Process Locked */
+  __HAL_LOCK(huart);
+ 803fd60:	687b      	ldr	r3, [r7, #4]
+ 803fd62:	f893 3084 	ldrb.w	r3, [r3, #132]	@ 0x84
+ 803fd66:	2b01      	cmp	r3, #1
+ 803fd68:	d101      	bne.n	803fd6e <HAL_UARTEx_EnableFifoMode+0x16>
+ 803fd6a:	2302      	movs	r3, #2
+ 803fd6c:	e02b      	b.n	803fdc6 <HAL_UARTEx_EnableFifoMode+0x6e>
+ 803fd6e:	687b      	ldr	r3, [r7, #4]
+ 803fd70:	2201      	movs	r2, #1
+ 803fd72:	f883 2084 	strb.w	r2, [r3, #132]	@ 0x84
+
+  huart->gState = HAL_UART_STATE_BUSY;
+ 803fd76:	687b      	ldr	r3, [r7, #4]
+ 803fd78:	2224      	movs	r2, #36	@ 0x24
+ 803fd7a:	f8c3 2088 	str.w	r2, [r3, #136]	@ 0x88
+
+  /* Save actual UART configuration */
+  tmpcr1 = READ_REG(huart->Instance->CR1);
+ 803fd7e:	687b      	ldr	r3, [r7, #4]
+ 803fd80:	681b      	ldr	r3, [r3, #0]
+ 803fd82:	681b      	ldr	r3, [r3, #0]
+ 803fd84:	60fb      	str	r3, [r7, #12]
+
+  /* Disable UART */
+  __HAL_UART_DISABLE(huart);
+ 803fd86:	687b      	ldr	r3, [r7, #4]
+ 803fd88:	681b      	ldr	r3, [r3, #0]
+ 803fd8a:	681a      	ldr	r2, [r3, #0]
+ 803fd8c:	687b      	ldr	r3, [r7, #4]
+ 803fd8e:	681b      	ldr	r3, [r3, #0]
+ 803fd90:	f022 0201 	bic.w	r2, r2, #1
+ 803fd94:	601a      	str	r2, [r3, #0]
+
+  /* Enable FIFO mode */
+  SET_BIT(tmpcr1, USART_CR1_FIFOEN);
+ 803fd96:	68fb      	ldr	r3, [r7, #12]
+ 803fd98:	f043 5300 	orr.w	r3, r3, #536870912	@ 0x20000000
+ 803fd9c:	60fb      	str	r3, [r7, #12]
+  huart->FifoMode = UART_FIFOMODE_ENABLE;
+ 803fd9e:	687b      	ldr	r3, [r7, #4]
+ 803fda0:	f04f 5200 	mov.w	r2, #536870912	@ 0x20000000
+ 803fda4:	665a      	str	r2, [r3, #100]	@ 0x64
+
+  /* Restore UART configuration */
+  WRITE_REG(huart->Instance->CR1, tmpcr1);
+ 803fda6:	687b      	ldr	r3, [r7, #4]
+ 803fda8:	681b      	ldr	r3, [r3, #0]
+ 803fdaa:	68fa      	ldr	r2, [r7, #12]
+ 803fdac:	601a      	str	r2, [r3, #0]
+
+  /* Determine the number of data to process during RX/TX ISR execution */
+  UARTEx_SetNbDataToProcess(huart);
+ 803fdae:	6878      	ldr	r0, [r7, #4]
+ 803fdb0:	f000 f8c2 	bl	803ff38 <UARTEx_SetNbDataToProcess>
+
+  huart->gState = HAL_UART_STATE_READY;
+ 803fdb4:	687b      	ldr	r3, [r7, #4]
+ 803fdb6:	2220      	movs	r2, #32
+ 803fdb8:	f8c3 2088 	str.w	r2, [r3, #136]	@ 0x88
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+ 803fdbc:	687b      	ldr	r3, [r7, #4]
+ 803fdbe:	2200      	movs	r2, #0
+ 803fdc0:	f883 2084 	strb.w	r2, [r3, #132]	@ 0x84
+
+  return HAL_OK;
+ 803fdc4:	2300      	movs	r3, #0
+}
+ 803fdc6:	4618      	mov	r0, r3
+ 803fdc8:	3710      	adds	r7, #16
+ 803fdca:	46bd      	mov	sp, r7
+ 803fdcc:	bd80      	pop	{r7, pc}
+
+0803fdce <HAL_UARTEx_DisableFifoMode>:
+  * @brief  Disable the FIFO mode.
+  * @param huart      UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart)
+{
+ 803fdce:	b480      	push	{r7}
+ 803fdd0:	b085      	sub	sp, #20
+ 803fdd2:	af00      	add	r7, sp, #0
+ 803fdd4:	6078      	str	r0, [r7, #4]
+
+  /* Check parameters */
+  assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
+
+  /* Process Locked */
+  __HAL_LOCK(huart);
+ 803fdd6:	687b      	ldr	r3, [r7, #4]
+ 803fdd8:	f893 3084 	ldrb.w	r3, [r3, #132]	@ 0x84
+ 803fddc:	2b01      	cmp	r3, #1
+ 803fdde:	d101      	bne.n	803fde4 <HAL_UARTEx_DisableFifoMode+0x16>
+ 803fde0:	2302      	movs	r3, #2
+ 803fde2:	e027      	b.n	803fe34 <HAL_UARTEx_DisableFifoMode+0x66>
+ 803fde4:	687b      	ldr	r3, [r7, #4]
+ 803fde6:	2201      	movs	r2, #1
+ 803fde8:	f883 2084 	strb.w	r2, [r3, #132]	@ 0x84
+
+  huart->gState = HAL_UART_STATE_BUSY;
+ 803fdec:	687b      	ldr	r3, [r7, #4]
+ 803fdee:	2224      	movs	r2, #36	@ 0x24
+ 803fdf0:	f8c3 2088 	str.w	r2, [r3, #136]	@ 0x88
+
+  /* Save actual UART configuration */
+  tmpcr1 = READ_REG(huart->Instance->CR1);
+ 803fdf4:	687b      	ldr	r3, [r7, #4]
+ 803fdf6:	681b      	ldr	r3, [r3, #0]
+ 803fdf8:	681b      	ldr	r3, [r3, #0]
+ 803fdfa:	60fb      	str	r3, [r7, #12]
+
+  /* Disable UART */
+  __HAL_UART_DISABLE(huart);
+ 803fdfc:	687b      	ldr	r3, [r7, #4]
+ 803fdfe:	681b      	ldr	r3, [r3, #0]
+ 803fe00:	681a      	ldr	r2, [r3, #0]
+ 803fe02:	687b      	ldr	r3, [r7, #4]
+ 803fe04:	681b      	ldr	r3, [r3, #0]
+ 803fe06:	f022 0201 	bic.w	r2, r2, #1
+ 803fe0a:	601a      	str	r2, [r3, #0]
+
+  /* Enable FIFO mode */
+  CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
+ 803fe0c:	68fb      	ldr	r3, [r7, #12]
+ 803fe0e:	f023 5300 	bic.w	r3, r3, #536870912	@ 0x20000000
+ 803fe12:	60fb      	str	r3, [r7, #12]
+  huart->FifoMode = UART_FIFOMODE_DISABLE;
+ 803fe14:	687b      	ldr	r3, [r7, #4]
+ 803fe16:	2200      	movs	r2, #0
+ 803fe18:	665a      	str	r2, [r3, #100]	@ 0x64
+
+  /* Restore UART configuration */
+  WRITE_REG(huart->Instance->CR1, tmpcr1);
+ 803fe1a:	687b      	ldr	r3, [r7, #4]
+ 803fe1c:	681b      	ldr	r3, [r3, #0]
+ 803fe1e:	68fa      	ldr	r2, [r7, #12]
+ 803fe20:	601a      	str	r2, [r3, #0]
+
+  huart->gState = HAL_UART_STATE_READY;
+ 803fe22:	687b      	ldr	r3, [r7, #4]
+ 803fe24:	2220      	movs	r2, #32
+ 803fe26:	f8c3 2088 	str.w	r2, [r3, #136]	@ 0x88
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+ 803fe2a:	687b      	ldr	r3, [r7, #4]
+ 803fe2c:	2200      	movs	r2, #0
+ 803fe2e:	f883 2084 	strb.w	r2, [r3, #132]	@ 0x84
+
+  return HAL_OK;
+ 803fe32:	2300      	movs	r3, #0
+}
+ 803fe34:	4618      	mov	r0, r3
+ 803fe36:	3714      	adds	r7, #20
+ 803fe38:	46bd      	mov	sp, r7
+ 803fe3a:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 803fe3e:	4770      	bx	lr
+
+0803fe40 <HAL_UARTEx_SetTxFifoThreshold>:
+  *            @arg @ref UART_TXFIFO_THRESHOLD_7_8
+  *            @arg @ref UART_TXFIFO_THRESHOLD_8_8
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
+{
+ 803fe40:	b580      	push	{r7, lr}
+ 803fe42:	b084      	sub	sp, #16
+ 803fe44:	af00      	add	r7, sp, #0
+ 803fe46:	6078      	str	r0, [r7, #4]
+ 803fe48:	6039      	str	r1, [r7, #0]
+  /* Check parameters */
+  assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
+  assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold));
+
+  /* Process Locked */
+  __HAL_LOCK(huart);
+ 803fe4a:	687b      	ldr	r3, [r7, #4]
+ 803fe4c:	f893 3084 	ldrb.w	r3, [r3, #132]	@ 0x84
+ 803fe50:	2b01      	cmp	r3, #1
+ 803fe52:	d101      	bne.n	803fe58 <HAL_UARTEx_SetTxFifoThreshold+0x18>
+ 803fe54:	2302      	movs	r3, #2
+ 803fe56:	e02d      	b.n	803feb4 <HAL_UARTEx_SetTxFifoThreshold+0x74>
+ 803fe58:	687b      	ldr	r3, [r7, #4]
+ 803fe5a:	2201      	movs	r2, #1
+ 803fe5c:	f883 2084 	strb.w	r2, [r3, #132]	@ 0x84
+
+  huart->gState = HAL_UART_STATE_BUSY;
+ 803fe60:	687b      	ldr	r3, [r7, #4]
+ 803fe62:	2224      	movs	r2, #36	@ 0x24
+ 803fe64:	f8c3 2088 	str.w	r2, [r3, #136]	@ 0x88
+
+  /* Save actual UART configuration */
+  tmpcr1 = READ_REG(huart->Instance->CR1);
+ 803fe68:	687b      	ldr	r3, [r7, #4]
+ 803fe6a:	681b      	ldr	r3, [r3, #0]
+ 803fe6c:	681b      	ldr	r3, [r3, #0]
+ 803fe6e:	60fb      	str	r3, [r7, #12]
+
+  /* Disable UART */
+  __HAL_UART_DISABLE(huart);
+ 803fe70:	687b      	ldr	r3, [r7, #4]
+ 803fe72:	681b      	ldr	r3, [r3, #0]
+ 803fe74:	681a      	ldr	r2, [r3, #0]
+ 803fe76:	687b      	ldr	r3, [r7, #4]
+ 803fe78:	681b      	ldr	r3, [r3, #0]
+ 803fe7a:	f022 0201 	bic.w	r2, r2, #1
+ 803fe7e:	601a      	str	r2, [r3, #0]
+
+  /* Update TX threshold configuration */
+  MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
+ 803fe80:	687b      	ldr	r3, [r7, #4]
+ 803fe82:	681b      	ldr	r3, [r3, #0]
+ 803fe84:	689b      	ldr	r3, [r3, #8]
+ 803fe86:	f023 4160 	bic.w	r1, r3, #3758096384	@ 0xe0000000
+ 803fe8a:	687b      	ldr	r3, [r7, #4]
+ 803fe8c:	681b      	ldr	r3, [r3, #0]
+ 803fe8e:	683a      	ldr	r2, [r7, #0]
+ 803fe90:	430a      	orrs	r2, r1
+ 803fe92:	609a      	str	r2, [r3, #8]
+
+  /* Determine the number of data to process during RX/TX ISR execution */
+  UARTEx_SetNbDataToProcess(huart);
+ 803fe94:	6878      	ldr	r0, [r7, #4]
+ 803fe96:	f000 f84f 	bl	803ff38 <UARTEx_SetNbDataToProcess>
+
+  /* Restore UART configuration */
+  WRITE_REG(huart->Instance->CR1, tmpcr1);
+ 803fe9a:	687b      	ldr	r3, [r7, #4]
+ 803fe9c:	681b      	ldr	r3, [r3, #0]
+ 803fe9e:	68fa      	ldr	r2, [r7, #12]
+ 803fea0:	601a      	str	r2, [r3, #0]
+
+  huart->gState = HAL_UART_STATE_READY;
+ 803fea2:	687b      	ldr	r3, [r7, #4]
+ 803fea4:	2220      	movs	r2, #32
+ 803fea6:	f8c3 2088 	str.w	r2, [r3, #136]	@ 0x88
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+ 803feaa:	687b      	ldr	r3, [r7, #4]
+ 803feac:	2200      	movs	r2, #0
+ 803feae:	f883 2084 	strb.w	r2, [r3, #132]	@ 0x84
+
+  return HAL_OK;
+ 803feb2:	2300      	movs	r3, #0
+}
+ 803feb4:	4618      	mov	r0, r3
+ 803feb6:	3710      	adds	r7, #16
+ 803feb8:	46bd      	mov	sp, r7
+ 803feba:	bd80      	pop	{r7, pc}
+
+0803febc <HAL_UARTEx_SetRxFifoThreshold>:
+  *            @arg @ref UART_RXFIFO_THRESHOLD_7_8
+  *            @arg @ref UART_RXFIFO_THRESHOLD_8_8
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
+{
+ 803febc:	b580      	push	{r7, lr}
+ 803febe:	b084      	sub	sp, #16
+ 803fec0:	af00      	add	r7, sp, #0
+ 803fec2:	6078      	str	r0, [r7, #4]
+ 803fec4:	6039      	str	r1, [r7, #0]
+  /* Check the parameters */
+  assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
+  assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold));
+
+  /* Process Locked */
+  __HAL_LOCK(huart);
+ 803fec6:	687b      	ldr	r3, [r7, #4]
+ 803fec8:	f893 3084 	ldrb.w	r3, [r3, #132]	@ 0x84
+ 803fecc:	2b01      	cmp	r3, #1
+ 803fece:	d101      	bne.n	803fed4 <HAL_UARTEx_SetRxFifoThreshold+0x18>
+ 803fed0:	2302      	movs	r3, #2
+ 803fed2:	e02d      	b.n	803ff30 <HAL_UARTEx_SetRxFifoThreshold+0x74>
+ 803fed4:	687b      	ldr	r3, [r7, #4]
+ 803fed6:	2201      	movs	r2, #1
+ 803fed8:	f883 2084 	strb.w	r2, [r3, #132]	@ 0x84
+
+  huart->gState = HAL_UART_STATE_BUSY;
+ 803fedc:	687b      	ldr	r3, [r7, #4]
+ 803fede:	2224      	movs	r2, #36	@ 0x24
+ 803fee0:	f8c3 2088 	str.w	r2, [r3, #136]	@ 0x88
+
+  /* Save actual UART configuration */
+  tmpcr1 = READ_REG(huart->Instance->CR1);
+ 803fee4:	687b      	ldr	r3, [r7, #4]
+ 803fee6:	681b      	ldr	r3, [r3, #0]
+ 803fee8:	681b      	ldr	r3, [r3, #0]
+ 803feea:	60fb      	str	r3, [r7, #12]
+
+  /* Disable UART */
+  __HAL_UART_DISABLE(huart);
+ 803feec:	687b      	ldr	r3, [r7, #4]
+ 803feee:	681b      	ldr	r3, [r3, #0]
+ 803fef0:	681a      	ldr	r2, [r3, #0]
+ 803fef2:	687b      	ldr	r3, [r7, #4]
+ 803fef4:	681b      	ldr	r3, [r3, #0]
+ 803fef6:	f022 0201 	bic.w	r2, r2, #1
+ 803fefa:	601a      	str	r2, [r3, #0]
+
+  /* Update RX threshold configuration */
+  MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
+ 803fefc:	687b      	ldr	r3, [r7, #4]
+ 803fefe:	681b      	ldr	r3, [r3, #0]
+ 803ff00:	689b      	ldr	r3, [r3, #8]
+ 803ff02:	f023 6160 	bic.w	r1, r3, #234881024	@ 0xe000000
+ 803ff06:	687b      	ldr	r3, [r7, #4]
+ 803ff08:	681b      	ldr	r3, [r3, #0]
+ 803ff0a:	683a      	ldr	r2, [r7, #0]
+ 803ff0c:	430a      	orrs	r2, r1
+ 803ff0e:	609a      	str	r2, [r3, #8]
+
+  /* Determine the number of data to process during RX/TX ISR execution */
+  UARTEx_SetNbDataToProcess(huart);
+ 803ff10:	6878      	ldr	r0, [r7, #4]
+ 803ff12:	f000 f811 	bl	803ff38 <UARTEx_SetNbDataToProcess>
+
+  /* Restore UART configuration */
+  WRITE_REG(huart->Instance->CR1, tmpcr1);
+ 803ff16:	687b      	ldr	r3, [r7, #4]
+ 803ff18:	681b      	ldr	r3, [r3, #0]
+ 803ff1a:	68fa      	ldr	r2, [r7, #12]
+ 803ff1c:	601a      	str	r2, [r3, #0]
+
+  huart->gState = HAL_UART_STATE_READY;
+ 803ff1e:	687b      	ldr	r3, [r7, #4]
+ 803ff20:	2220      	movs	r2, #32
+ 803ff22:	f8c3 2088 	str.w	r2, [r3, #136]	@ 0x88
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+ 803ff26:	687b      	ldr	r3, [r7, #4]
+ 803ff28:	2200      	movs	r2, #0
+ 803ff2a:	f883 2084 	strb.w	r2, [r3, #132]	@ 0x84
+
+  return HAL_OK;
+ 803ff2e:	2300      	movs	r3, #0
+}
+ 803ff30:	4618      	mov	r0, r3
+ 803ff32:	3710      	adds	r7, #16
+ 803ff34:	46bd      	mov	sp, r7
+ 803ff36:	bd80      	pop	{r7, pc}
+
+0803ff38 <UARTEx_SetNbDataToProcess>:
+  *       the UART configuration registers.
+  * @param huart UART handle.
+  * @retval None
+  */
+static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart)
+{
+ 803ff38:	b480      	push	{r7}
+ 803ff3a:	b085      	sub	sp, #20
+ 803ff3c:	af00      	add	r7, sp, #0
+ 803ff3e:	6078      	str	r0, [r7, #4]
+  uint8_t rx_fifo_threshold;
+  uint8_t tx_fifo_threshold;
+  static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
+  static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
+
+  if (huart->FifoMode == UART_FIFOMODE_DISABLE)
+ 803ff40:	687b      	ldr	r3, [r7, #4]
+ 803ff42:	6e5b      	ldr	r3, [r3, #100]	@ 0x64
+ 803ff44:	2b00      	cmp	r3, #0
+ 803ff46:	d108      	bne.n	803ff5a <UARTEx_SetNbDataToProcess+0x22>
+  {
+    huart->NbTxDataToProcess = 1U;
+ 803ff48:	687b      	ldr	r3, [r7, #4]
+ 803ff4a:	2201      	movs	r2, #1
+ 803ff4c:	f8a3 206a 	strh.w	r2, [r3, #106]	@ 0x6a
+    huart->NbRxDataToProcess = 1U;
+ 803ff50:	687b      	ldr	r3, [r7, #4]
+ 803ff52:	2201      	movs	r2, #1
+ 803ff54:	f8a3 2068 	strh.w	r2, [r3, #104]	@ 0x68
+    huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
+                               (uint16_t)denominator[tx_fifo_threshold];
+    huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
+                               (uint16_t)denominator[rx_fifo_threshold];
+  }
+}
+ 803ff58:	e031      	b.n	803ffbe <UARTEx_SetNbDataToProcess+0x86>
+    rx_fifo_depth = RX_FIFO_DEPTH;
+ 803ff5a:	2310      	movs	r3, #16
+ 803ff5c:	73fb      	strb	r3, [r7, #15]
+    tx_fifo_depth = TX_FIFO_DEPTH;
+ 803ff5e:	2310      	movs	r3, #16
+ 803ff60:	73bb      	strb	r3, [r7, #14]
+    rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
+ 803ff62:	687b      	ldr	r3, [r7, #4]
+ 803ff64:	681b      	ldr	r3, [r3, #0]
+ 803ff66:	689b      	ldr	r3, [r3, #8]
+ 803ff68:	0e5b      	lsrs	r3, r3, #25
+ 803ff6a:	b2db      	uxtb	r3, r3
+ 803ff6c:	f003 0307 	and.w	r3, r3, #7
+ 803ff70:	737b      	strb	r3, [r7, #13]
+    tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
+ 803ff72:	687b      	ldr	r3, [r7, #4]
+ 803ff74:	681b      	ldr	r3, [r3, #0]
+ 803ff76:	689b      	ldr	r3, [r3, #8]
+ 803ff78:	0f5b      	lsrs	r3, r3, #29
+ 803ff7a:	b2db      	uxtb	r3, r3
+ 803ff7c:	f003 0307 	and.w	r3, r3, #7
+ 803ff80:	733b      	strb	r3, [r7, #12]
+    huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
+ 803ff82:	7bbb      	ldrb	r3, [r7, #14]
+ 803ff84:	7b3a      	ldrb	r2, [r7, #12]
+ 803ff86:	4911      	ldr	r1, [pc, #68]	@ (803ffcc <UARTEx_SetNbDataToProcess+0x94>)
+ 803ff88:	5c8a      	ldrb	r2, [r1, r2]
+ 803ff8a:	fb02 f303 	mul.w	r3, r2, r3
+                               (uint16_t)denominator[tx_fifo_threshold];
+ 803ff8e:	7b3a      	ldrb	r2, [r7, #12]
+ 803ff90:	490f      	ldr	r1, [pc, #60]	@ (803ffd0 <UARTEx_SetNbDataToProcess+0x98>)
+ 803ff92:	5c8a      	ldrb	r2, [r1, r2]
+    huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
+ 803ff94:	fb93 f3f2 	sdiv	r3, r3, r2
+ 803ff98:	b29a      	uxth	r2, r3
+ 803ff9a:	687b      	ldr	r3, [r7, #4]
+ 803ff9c:	f8a3 206a 	strh.w	r2, [r3, #106]	@ 0x6a
+    huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
+ 803ffa0:	7bfb      	ldrb	r3, [r7, #15]
+ 803ffa2:	7b7a      	ldrb	r2, [r7, #13]
+ 803ffa4:	4909      	ldr	r1, [pc, #36]	@ (803ffcc <UARTEx_SetNbDataToProcess+0x94>)
+ 803ffa6:	5c8a      	ldrb	r2, [r1, r2]
+ 803ffa8:	fb02 f303 	mul.w	r3, r2, r3
+                               (uint16_t)denominator[rx_fifo_threshold];
+ 803ffac:	7b7a      	ldrb	r2, [r7, #13]
+ 803ffae:	4908      	ldr	r1, [pc, #32]	@ (803ffd0 <UARTEx_SetNbDataToProcess+0x98>)
+ 803ffb0:	5c8a      	ldrb	r2, [r1, r2]
+    huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
+ 803ffb2:	fb93 f3f2 	sdiv	r3, r3, r2
+ 803ffb6:	b29a      	uxth	r2, r3
+ 803ffb8:	687b      	ldr	r3, [r7, #4]
+ 803ffba:	f8a3 2068 	strh.w	r2, [r3, #104]	@ 0x68
+}
+ 803ffbe:	bf00      	nop
+ 803ffc0:	3714      	adds	r7, #20
+ 803ffc2:	46bd      	mov	sp, r7
+ 803ffc4:	f85d 7b04 	ldr.w	r7, [sp], #4
+ 803ffc8:	4770      	bx	lr
+ 803ffca:	bf00      	nop
+ 803ffcc:	08041c98 	.word	0x08041c98
+ 803ffd0:	08041ca0 	.word	0x08041ca0
+
+0803ffd4 <malloc>:
+ 803ffd4:	4b02      	ldr	r3, [pc, #8]	@ (803ffe0 <malloc+0xc>)
+ 803ffd6:	4601      	mov	r1, r0
+ 803ffd8:	6818      	ldr	r0, [r3, #0]
+ 803ffda:	f000 b82d 	b.w	8040038 <_malloc_r>
+ 803ffde:	bf00      	nop
+ 803ffe0:	2400013c 	.word	0x2400013c
+
+0803ffe4 <free>:
+ 803ffe4:	4b02      	ldr	r3, [pc, #8]	@ (803fff0 <free+0xc>)
+ 803ffe6:	4601      	mov	r1, r0
+ 803ffe8:	6818      	ldr	r0, [r3, #0]
+ 803ffea:	f000 b9f5 	b.w	80403d8 <_free_r>
+ 803ffee:	bf00      	nop
+ 803fff0:	2400013c 	.word	0x2400013c
+
+0803fff4 <sbrk_aligned>:
+ 803fff4:	b570      	push	{r4, r5, r6, lr}
+ 803fff6:	4e0f      	ldr	r6, [pc, #60]	@ (8040034 <sbrk_aligned+0x40>)
+ 803fff8:	460c      	mov	r4, r1
+ 803fffa:	6831      	ldr	r1, [r6, #0]
+ 803fffc:	4605      	mov	r5, r0
+ 803fffe:	b911      	cbnz	r1, 8040006 <sbrk_aligned+0x12>
+ 8040000:	f000 f9a0 	bl	8040344 <_sbrk_r>
+ 8040004:	6030      	str	r0, [r6, #0]
+ 8040006:	4621      	mov	r1, r4
+ 8040008:	4628      	mov	r0, r5
+ 804000a:	f000 f99b 	bl	8040344 <_sbrk_r>
+ 804000e:	1c43      	adds	r3, r0, #1
+ 8040010:	d103      	bne.n	804001a <sbrk_aligned+0x26>
+ 8040012:	f04f 34ff 	mov.w	r4, #4294967295
+ 8040016:	4620      	mov	r0, r4
+ 8040018:	bd70      	pop	{r4, r5, r6, pc}
+ 804001a:	1cc4      	adds	r4, r0, #3
+ 804001c:	f024 0403 	bic.w	r4, r4, #3
+ 8040020:	42a0      	cmp	r0, r4
+ 8040022:	d0f8      	beq.n	8040016 <sbrk_aligned+0x22>
+ 8040024:	1a21      	subs	r1, r4, r0
+ 8040026:	4628      	mov	r0, r5
+ 8040028:	f000 f98c 	bl	8040344 <_sbrk_r>
+ 804002c:	3001      	adds	r0, #1
+ 804002e:	d1f2      	bne.n	8040016 <sbrk_aligned+0x22>
+ 8040030:	e7ef      	b.n	8040012 <sbrk_aligned+0x1e>
+ 8040032:	bf00      	nop
+ 8040034:	2400b27c 	.word	0x2400b27c
+
+08040038 <_malloc_r>:
+ 8040038:	e92d 43f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
+ 804003c:	1ccd      	adds	r5, r1, #3
+ 804003e:	f025 0503 	bic.w	r5, r5, #3
+ 8040042:	3508      	adds	r5, #8
+ 8040044:	2d0c      	cmp	r5, #12
+ 8040046:	bf38      	it	cc
+ 8040048:	250c      	movcc	r5, #12
+ 804004a:	2d00      	cmp	r5, #0
+ 804004c:	4606      	mov	r6, r0
+ 804004e:	db01      	blt.n	8040054 <_malloc_r+0x1c>
+ 8040050:	42a9      	cmp	r1, r5
+ 8040052:	d904      	bls.n	804005e <_malloc_r+0x26>
+ 8040054:	230c      	movs	r3, #12
+ 8040056:	6033      	str	r3, [r6, #0]
+ 8040058:	2000      	movs	r0, #0
+ 804005a:	e8bd 83f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
+ 804005e:	f8df 80d4 	ldr.w	r8, [pc, #212]	@ 8040134 <_malloc_r+0xfc>
+ 8040062:	f000 f869 	bl	8040138 <__malloc_lock>
+ 8040066:	f8d8 3000 	ldr.w	r3, [r8]
+ 804006a:	461c      	mov	r4, r3
+ 804006c:	bb44      	cbnz	r4, 80400c0 <_malloc_r+0x88>
+ 804006e:	4629      	mov	r1, r5
+ 8040070:	4630      	mov	r0, r6
+ 8040072:	f7ff ffbf 	bl	803fff4 <sbrk_aligned>
+ 8040076:	1c43      	adds	r3, r0, #1
+ 8040078:	4604      	mov	r4, r0
+ 804007a:	d158      	bne.n	804012e <_malloc_r+0xf6>
+ 804007c:	f8d8 4000 	ldr.w	r4, [r8]
+ 8040080:	4627      	mov	r7, r4
+ 8040082:	2f00      	cmp	r7, #0
+ 8040084:	d143      	bne.n	804010e <_malloc_r+0xd6>
+ 8040086:	2c00      	cmp	r4, #0
+ 8040088:	d04b      	beq.n	8040122 <_malloc_r+0xea>
+ 804008a:	6823      	ldr	r3, [r4, #0]
+ 804008c:	4639      	mov	r1, r7
+ 804008e:	4630      	mov	r0, r6
+ 8040090:	eb04 0903 	add.w	r9, r4, r3
+ 8040094:	f000 f956 	bl	8040344 <_sbrk_r>
+ 8040098:	4581      	cmp	r9, r0
+ 804009a:	d142      	bne.n	8040122 <_malloc_r+0xea>
+ 804009c:	6821      	ldr	r1, [r4, #0]
+ 804009e:	1a6d      	subs	r5, r5, r1
+ 80400a0:	4629      	mov	r1, r5
+ 80400a2:	4630      	mov	r0, r6
+ 80400a4:	f7ff ffa6 	bl	803fff4 <sbrk_aligned>
+ 80400a8:	3001      	adds	r0, #1
+ 80400aa:	d03a      	beq.n	8040122 <_malloc_r+0xea>
+ 80400ac:	6823      	ldr	r3, [r4, #0]
+ 80400ae:	442b      	add	r3, r5
+ 80400b0:	6023      	str	r3, [r4, #0]
+ 80400b2:	f8d8 3000 	ldr.w	r3, [r8]
+ 80400b6:	685a      	ldr	r2, [r3, #4]
+ 80400b8:	bb62      	cbnz	r2, 8040114 <_malloc_r+0xdc>
+ 80400ba:	f8c8 7000 	str.w	r7, [r8]
+ 80400be:	e00f      	b.n	80400e0 <_malloc_r+0xa8>
+ 80400c0:	6822      	ldr	r2, [r4, #0]
+ 80400c2:	1b52      	subs	r2, r2, r5
+ 80400c4:	d420      	bmi.n	8040108 <_malloc_r+0xd0>
+ 80400c6:	2a0b      	cmp	r2, #11
+ 80400c8:	d917      	bls.n	80400fa <_malloc_r+0xc2>
+ 80400ca:	1961      	adds	r1, r4, r5
+ 80400cc:	42a3      	cmp	r3, r4
+ 80400ce:	6025      	str	r5, [r4, #0]
+ 80400d0:	bf18      	it	ne
+ 80400d2:	6059      	strne	r1, [r3, #4]
+ 80400d4:	6863      	ldr	r3, [r4, #4]
+ 80400d6:	bf08      	it	eq
+ 80400d8:	f8c8 1000 	streq.w	r1, [r8]
+ 80400dc:	5162      	str	r2, [r4, r5]
+ 80400de:	604b      	str	r3, [r1, #4]
+ 80400e0:	4630      	mov	r0, r6
+ 80400e2:	f000 f82f 	bl	8040144 <__malloc_unlock>
+ 80400e6:	f104 000b 	add.w	r0, r4, #11
+ 80400ea:	1d23      	adds	r3, r4, #4
+ 80400ec:	f020 0007 	bic.w	r0, r0, #7
+ 80400f0:	1ac2      	subs	r2, r0, r3
+ 80400f2:	bf1c      	itt	ne
+ 80400f4:	1a1b      	subne	r3, r3, r0
+ 80400f6:	50a3      	strne	r3, [r4, r2]
+ 80400f8:	e7af      	b.n	804005a <_malloc_r+0x22>
+ 80400fa:	6862      	ldr	r2, [r4, #4]
+ 80400fc:	42a3      	cmp	r3, r4
+ 80400fe:	bf0c      	ite	eq
+ 8040100:	f8c8 2000 	streq.w	r2, [r8]
+ 8040104:	605a      	strne	r2, [r3, #4]
+ 8040106:	e7eb      	b.n	80400e0 <_malloc_r+0xa8>
+ 8040108:	4623      	mov	r3, r4
+ 804010a:	6864      	ldr	r4, [r4, #4]
+ 804010c:	e7ae      	b.n	804006c <_malloc_r+0x34>
+ 804010e:	463c      	mov	r4, r7
+ 8040110:	687f      	ldr	r7, [r7, #4]
+ 8040112:	e7b6      	b.n	8040082 <_malloc_r+0x4a>
+ 8040114:	461a      	mov	r2, r3
+ 8040116:	685b      	ldr	r3, [r3, #4]
+ 8040118:	42a3      	cmp	r3, r4
+ 804011a:	d1fb      	bne.n	8040114 <_malloc_r+0xdc>
+ 804011c:	2300      	movs	r3, #0
+ 804011e:	6053      	str	r3, [r2, #4]
+ 8040120:	e7de      	b.n	80400e0 <_malloc_r+0xa8>
+ 8040122:	230c      	movs	r3, #12
+ 8040124:	6033      	str	r3, [r6, #0]
+ 8040126:	4630      	mov	r0, r6
+ 8040128:	f000 f80c 	bl	8040144 <__malloc_unlock>
+ 804012c:	e794      	b.n	8040058 <_malloc_r+0x20>
+ 804012e:	6005      	str	r5, [r0, #0]
+ 8040130:	e7d6      	b.n	80400e0 <_malloc_r+0xa8>
+ 8040132:	bf00      	nop
+ 8040134:	2400b280 	.word	0x2400b280
+
+08040138 <__malloc_lock>:
+ 8040138:	4801      	ldr	r0, [pc, #4]	@ (8040140 <__malloc_lock+0x8>)
+ 804013a:	f000 b93d 	b.w	80403b8 <__retarget_lock_acquire_recursive>
+ 804013e:	bf00      	nop
+ 8040140:	2400b3c0 	.word	0x2400b3c0
+
+08040144 <__malloc_unlock>:
+ 8040144:	4801      	ldr	r0, [pc, #4]	@ (804014c <__malloc_unlock+0x8>)
+ 8040146:	f000 b938 	b.w	80403ba <__retarget_lock_release_recursive>
+ 804014a:	bf00      	nop
+ 804014c:	2400b3c0 	.word	0x2400b3c0
+
+08040150 <_strtoul_l.constprop.0>:
+ 8040150:	e92d 43f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, lr}
+ 8040154:	4e34      	ldr	r6, [pc, #208]	@ (8040228 <_strtoul_l.constprop.0+0xd8>)
+ 8040156:	4686      	mov	lr, r0
+ 8040158:	460d      	mov	r5, r1
+ 804015a:	4628      	mov	r0, r5
+ 804015c:	f815 4b01 	ldrb.w	r4, [r5], #1
+ 8040160:	5d37      	ldrb	r7, [r6, r4]
+ 8040162:	f017 0708 	ands.w	r7, r7, #8
+ 8040166:	d1f8      	bne.n	804015a <_strtoul_l.constprop.0+0xa>
+ 8040168:	2c2d      	cmp	r4, #45	@ 0x2d
+ 804016a:	d12f      	bne.n	80401cc <_strtoul_l.constprop.0+0x7c>
+ 804016c:	782c      	ldrb	r4, [r5, #0]
+ 804016e:	2701      	movs	r7, #1
+ 8040170:	1c85      	adds	r5, r0, #2
+ 8040172:	f033 0010 	bics.w	r0, r3, #16
+ 8040176:	d109      	bne.n	804018c <_strtoul_l.constprop.0+0x3c>
+ 8040178:	2c30      	cmp	r4, #48	@ 0x30
+ 804017a:	d12c      	bne.n	80401d6 <_strtoul_l.constprop.0+0x86>
+ 804017c:	7828      	ldrb	r0, [r5, #0]
+ 804017e:	f000 00df 	and.w	r0, r0, #223	@ 0xdf
+ 8040182:	2858      	cmp	r0, #88	@ 0x58
+ 8040184:	d127      	bne.n	80401d6 <_strtoul_l.constprop.0+0x86>
+ 8040186:	786c      	ldrb	r4, [r5, #1]
+ 8040188:	2310      	movs	r3, #16
+ 804018a:	3502      	adds	r5, #2
+ 804018c:	f04f 38ff 	mov.w	r8, #4294967295
+ 8040190:	2600      	movs	r6, #0
+ 8040192:	fbb8 f8f3 	udiv	r8, r8, r3
+ 8040196:	fb03 f908 	mul.w	r9, r3, r8
+ 804019a:	ea6f 0909 	mvn.w	r9, r9
+ 804019e:	4630      	mov	r0, r6
+ 80401a0:	f1a4 0c30 	sub.w	ip, r4, #48	@ 0x30
+ 80401a4:	f1bc 0f09 	cmp.w	ip, #9
+ 80401a8:	d81c      	bhi.n	80401e4 <_strtoul_l.constprop.0+0x94>
+ 80401aa:	4664      	mov	r4, ip
+ 80401ac:	42a3      	cmp	r3, r4
+ 80401ae:	dd2a      	ble.n	8040206 <_strtoul_l.constprop.0+0xb6>
+ 80401b0:	f1b6 3fff 	cmp.w	r6, #4294967295
+ 80401b4:	d007      	beq.n	80401c6 <_strtoul_l.constprop.0+0x76>
+ 80401b6:	4580      	cmp	r8, r0
+ 80401b8:	d322      	bcc.n	8040200 <_strtoul_l.constprop.0+0xb0>
+ 80401ba:	d101      	bne.n	80401c0 <_strtoul_l.constprop.0+0x70>
+ 80401bc:	45a1      	cmp	r9, r4
+ 80401be:	db1f      	blt.n	8040200 <_strtoul_l.constprop.0+0xb0>
+ 80401c0:	fb00 4003 	mla	r0, r0, r3, r4
+ 80401c4:	2601      	movs	r6, #1
+ 80401c6:	f815 4b01 	ldrb.w	r4, [r5], #1
+ 80401ca:	e7e9      	b.n	80401a0 <_strtoul_l.constprop.0+0x50>
+ 80401cc:	2c2b      	cmp	r4, #43	@ 0x2b
+ 80401ce:	bf04      	itt	eq
+ 80401d0:	782c      	ldrbeq	r4, [r5, #0]
+ 80401d2:	1c85      	addeq	r5, r0, #2
+ 80401d4:	e7cd      	b.n	8040172 <_strtoul_l.constprop.0+0x22>
+ 80401d6:	2b00      	cmp	r3, #0
+ 80401d8:	d1d8      	bne.n	804018c <_strtoul_l.constprop.0+0x3c>
+ 80401da:	2c30      	cmp	r4, #48	@ 0x30
+ 80401dc:	bf0c      	ite	eq
+ 80401de:	2308      	moveq	r3, #8
+ 80401e0:	230a      	movne	r3, #10
+ 80401e2:	e7d3      	b.n	804018c <_strtoul_l.constprop.0+0x3c>
+ 80401e4:	f1a4 0c41 	sub.w	ip, r4, #65	@ 0x41
+ 80401e8:	f1bc 0f19 	cmp.w	ip, #25
+ 80401ec:	d801      	bhi.n	80401f2 <_strtoul_l.constprop.0+0xa2>
+ 80401ee:	3c37      	subs	r4, #55	@ 0x37
+ 80401f0:	e7dc      	b.n	80401ac <_strtoul_l.constprop.0+0x5c>
+ 80401f2:	f1a4 0c61 	sub.w	ip, r4, #97	@ 0x61
+ 80401f6:	f1bc 0f19 	cmp.w	ip, #25
+ 80401fa:	d804      	bhi.n	8040206 <_strtoul_l.constprop.0+0xb6>
+ 80401fc:	3c57      	subs	r4, #87	@ 0x57
+ 80401fe:	e7d5      	b.n	80401ac <_strtoul_l.constprop.0+0x5c>
+ 8040200:	f04f 36ff 	mov.w	r6, #4294967295
+ 8040204:	e7df      	b.n	80401c6 <_strtoul_l.constprop.0+0x76>
+ 8040206:	1c73      	adds	r3, r6, #1
+ 8040208:	d106      	bne.n	8040218 <_strtoul_l.constprop.0+0xc8>
+ 804020a:	2322      	movs	r3, #34	@ 0x22
+ 804020c:	f8ce 3000 	str.w	r3, [lr]
+ 8040210:	4630      	mov	r0, r6
+ 8040212:	b932      	cbnz	r2, 8040222 <_strtoul_l.constprop.0+0xd2>
+ 8040214:	e8bd 83f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, pc}
+ 8040218:	b107      	cbz	r7, 804021c <_strtoul_l.constprop.0+0xcc>
+ 804021a:	4240      	negs	r0, r0
+ 804021c:	2a00      	cmp	r2, #0
+ 804021e:	d0f9      	beq.n	8040214 <_strtoul_l.constprop.0+0xc4>
+ 8040220:	b106      	cbz	r6, 8040224 <_strtoul_l.constprop.0+0xd4>
+ 8040222:	1e69      	subs	r1, r5, #1
+ 8040224:	6011      	str	r1, [r2, #0]
+ 8040226:	e7f5      	b.n	8040214 <_strtoul_l.constprop.0+0xc4>
+ 8040228:	08041ca9 	.word	0x08041ca9
+
+0804022c <strtoul>:
+ 804022c:	4613      	mov	r3, r2
+ 804022e:	460a      	mov	r2, r1
+ 8040230:	4601      	mov	r1, r0
+ 8040232:	4802      	ldr	r0, [pc, #8]	@ (804023c <strtoul+0x10>)
+ 8040234:	6800      	ldr	r0, [r0, #0]
+ 8040236:	f7ff bf8b 	b.w	8040150 <_strtoul_l.constprop.0>
+ 804023a:	bf00      	nop
+ 804023c:	2400013c 	.word	0x2400013c
+
+08040240 <sniprintf>:
+ 8040240:	b40c      	push	{r2, r3}
+ 8040242:	b530      	push	{r4, r5, lr}
+ 8040244:	4b17      	ldr	r3, [pc, #92]	@ (80402a4 <sniprintf+0x64>)
+ 8040246:	1e0c      	subs	r4, r1, #0
+ 8040248:	681d      	ldr	r5, [r3, #0]
+ 804024a:	b09d      	sub	sp, #116	@ 0x74
+ 804024c:	da08      	bge.n	8040260 <sniprintf+0x20>
+ 804024e:	238b      	movs	r3, #139	@ 0x8b
+ 8040250:	602b      	str	r3, [r5, #0]
+ 8040252:	f04f 30ff 	mov.w	r0, #4294967295
+ 8040256:	b01d      	add	sp, #116	@ 0x74
+ 8040258:	e8bd 4030 	ldmia.w	sp!, {r4, r5, lr}
+ 804025c:	b002      	add	sp, #8
+ 804025e:	4770      	bx	lr
+ 8040260:	f44f 7302 	mov.w	r3, #520	@ 0x208
+ 8040264:	f8ad 3014 	strh.w	r3, [sp, #20]
+ 8040268:	bf14      	ite	ne
+ 804026a:	f104 33ff 	addne.w	r3, r4, #4294967295
+ 804026e:	4623      	moveq	r3, r4
+ 8040270:	9304      	str	r3, [sp, #16]
+ 8040272:	9307      	str	r3, [sp, #28]
+ 8040274:	f64f 73ff 	movw	r3, #65535	@ 0xffff
+ 8040278:	9002      	str	r0, [sp, #8]
+ 804027a:	9006      	str	r0, [sp, #24]
+ 804027c:	f8ad 3016 	strh.w	r3, [sp, #22]
+ 8040280:	9a20      	ldr	r2, [sp, #128]	@ 0x80
+ 8040282:	ab21      	add	r3, sp, #132	@ 0x84
+ 8040284:	a902      	add	r1, sp, #8
+ 8040286:	4628      	mov	r0, r5
+ 8040288:	9301      	str	r3, [sp, #4]
+ 804028a:	f000 f94b 	bl	8040524 <_svfiprintf_r>
+ 804028e:	1c43      	adds	r3, r0, #1
+ 8040290:	bfbc      	itt	lt
+ 8040292:	238b      	movlt	r3, #139	@ 0x8b
+ 8040294:	602b      	strlt	r3, [r5, #0]
+ 8040296:	2c00      	cmp	r4, #0
+ 8040298:	d0dd      	beq.n	8040256 <sniprintf+0x16>
+ 804029a:	9b02      	ldr	r3, [sp, #8]
+ 804029c:	2200      	movs	r2, #0
+ 804029e:	701a      	strb	r2, [r3, #0]
+ 80402a0:	e7d9      	b.n	8040256 <sniprintf+0x16>
+ 80402a2:	bf00      	nop
+ 80402a4:	2400013c 	.word	0x2400013c
+
+080402a8 <_vsiprintf_r>:
+ 80402a8:	b500      	push	{lr}
+ 80402aa:	b09b      	sub	sp, #108	@ 0x6c
+ 80402ac:	9100      	str	r1, [sp, #0]
+ 80402ae:	9104      	str	r1, [sp, #16]
+ 80402b0:	f06f 4100 	mvn.w	r1, #2147483648	@ 0x80000000
+ 80402b4:	9105      	str	r1, [sp, #20]
+ 80402b6:	9102      	str	r1, [sp, #8]
+ 80402b8:	4905      	ldr	r1, [pc, #20]	@ (80402d0 <_vsiprintf_r+0x28>)
+ 80402ba:	9103      	str	r1, [sp, #12]
+ 80402bc:	4669      	mov	r1, sp
+ 80402be:	f000 f931 	bl	8040524 <_svfiprintf_r>
+ 80402c2:	9b00      	ldr	r3, [sp, #0]
+ 80402c4:	2200      	movs	r2, #0
+ 80402c6:	701a      	strb	r2, [r3, #0]
+ 80402c8:	b01b      	add	sp, #108	@ 0x6c
+ 80402ca:	f85d fb04 	ldr.w	pc, [sp], #4
+ 80402ce:	bf00      	nop
+ 80402d0:	ffff0208 	.word	0xffff0208
+
+080402d4 <vsiprintf>:
+ 80402d4:	4613      	mov	r3, r2
+ 80402d6:	460a      	mov	r2, r1
+ 80402d8:	4601      	mov	r1, r0
+ 80402da:	4802      	ldr	r0, [pc, #8]	@ (80402e4 <vsiprintf+0x10>)
+ 80402dc:	6800      	ldr	r0, [r0, #0]
+ 80402de:	f7ff bfe3 	b.w	80402a8 <_vsiprintf_r>
+ 80402e2:	bf00      	nop
+ 80402e4:	2400013c 	.word	0x2400013c
+
+080402e8 <memset>:
+ 80402e8:	4402      	add	r2, r0
+ 80402ea:	4603      	mov	r3, r0
+ 80402ec:	4293      	cmp	r3, r2
+ 80402ee:	d100      	bne.n	80402f2 <memset+0xa>
+ 80402f0:	4770      	bx	lr
+ 80402f2:	f803 1b01 	strb.w	r1, [r3], #1
+ 80402f6:	e7f9      	b.n	80402ec <memset+0x4>
+
+080402f8 <strncat>:
+ 80402f8:	b530      	push	{r4, r5, lr}
+ 80402fa:	4604      	mov	r4, r0
+ 80402fc:	7825      	ldrb	r5, [r4, #0]
+ 80402fe:	4623      	mov	r3, r4
+ 8040300:	3401      	adds	r4, #1
+ 8040302:	2d00      	cmp	r5, #0
+ 8040304:	d1fa      	bne.n	80402fc <strncat+0x4>
+ 8040306:	3a01      	subs	r2, #1
+ 8040308:	d304      	bcc.n	8040314 <strncat+0x1c>
+ 804030a:	f811 4b01 	ldrb.w	r4, [r1], #1
+ 804030e:	f803 4b01 	strb.w	r4, [r3], #1
+ 8040312:	b904      	cbnz	r4, 8040316 <strncat+0x1e>
+ 8040314:	bd30      	pop	{r4, r5, pc}
+ 8040316:	2a00      	cmp	r2, #0
+ 8040318:	d1f5      	bne.n	8040306 <strncat+0xe>
+ 804031a:	701a      	strb	r2, [r3, #0]
+ 804031c:	e7f3      	b.n	8040306 <strncat+0xe>
+
+0804031e <strncpy>:
+ 804031e:	b510      	push	{r4, lr}
+ 8040320:	3901      	subs	r1, #1
+ 8040322:	4603      	mov	r3, r0
+ 8040324:	b132      	cbz	r2, 8040334 <strncpy+0x16>
+ 8040326:	f811 4f01 	ldrb.w	r4, [r1, #1]!
+ 804032a:	f803 4b01 	strb.w	r4, [r3], #1
+ 804032e:	3a01      	subs	r2, #1
+ 8040330:	2c00      	cmp	r4, #0
+ 8040332:	d1f7      	bne.n	8040324 <strncpy+0x6>
+ 8040334:	441a      	add	r2, r3
+ 8040336:	2100      	movs	r1, #0
+ 8040338:	4293      	cmp	r3, r2
+ 804033a:	d100      	bne.n	804033e <strncpy+0x20>
+ 804033c:	bd10      	pop	{r4, pc}
+ 804033e:	f803 1b01 	strb.w	r1, [r3], #1
+ 8040342:	e7f9      	b.n	8040338 <strncpy+0x1a>
+
+08040344 <_sbrk_r>:
+ 8040344:	b538      	push	{r3, r4, r5, lr}
+ 8040346:	4d06      	ldr	r5, [pc, #24]	@ (8040360 <_sbrk_r+0x1c>)
+ 8040348:	2300      	movs	r3, #0
+ 804034a:	4604      	mov	r4, r0
+ 804034c:	4608      	mov	r0, r1
+ 804034e:	602b      	str	r3, [r5, #0]
+ 8040350:	f7f0 f856 	bl	8030400 <_sbrk>
+ 8040354:	1c43      	adds	r3, r0, #1
+ 8040356:	d102      	bne.n	804035e <_sbrk_r+0x1a>
+ 8040358:	682b      	ldr	r3, [r5, #0]
+ 804035a:	b103      	cbz	r3, 804035e <_sbrk_r+0x1a>
+ 804035c:	6023      	str	r3, [r4, #0]
+ 804035e:	bd38      	pop	{r3, r4, r5, pc}
+ 8040360:	2400b3bc 	.word	0x2400b3bc
+
+08040364 <__errno>:
+ 8040364:	4b01      	ldr	r3, [pc, #4]	@ (804036c <__errno+0x8>)
+ 8040366:	6818      	ldr	r0, [r3, #0]
+ 8040368:	4770      	bx	lr
+ 804036a:	bf00      	nop
+ 804036c:	2400013c 	.word	0x2400013c
+
+08040370 <__libc_init_array>:
+ 8040370:	b570      	push	{r4, r5, r6, lr}
+ 8040372:	4d0d      	ldr	r5, [pc, #52]	@ (80403a8 <__libc_init_array+0x38>)
+ 8040374:	4c0d      	ldr	r4, [pc, #52]	@ (80403ac <__libc_init_array+0x3c>)
+ 8040376:	1b64      	subs	r4, r4, r5
+ 8040378:	10a4      	asrs	r4, r4, #2
+ 804037a:	2600      	movs	r6, #0
+ 804037c:	42a6      	cmp	r6, r4
+ 804037e:	d109      	bne.n	8040394 <__libc_init_array+0x24>
+ 8040380:	4d0b      	ldr	r5, [pc, #44]	@ (80403b0 <__libc_init_array+0x40>)
+ 8040382:	4c0c      	ldr	r4, [pc, #48]	@ (80403b4 <__libc_init_array+0x44>)
+ 8040384:	f000 fd72 	bl	8040e6c <_init>
+ 8040388:	1b64      	subs	r4, r4, r5
+ 804038a:	10a4      	asrs	r4, r4, #2
+ 804038c:	2600      	movs	r6, #0
+ 804038e:	42a6      	cmp	r6, r4
+ 8040390:	d105      	bne.n	804039e <__libc_init_array+0x2e>
+ 8040392:	bd70      	pop	{r4, r5, r6, pc}
+ 8040394:	f855 3b04 	ldr.w	r3, [r5], #4
+ 8040398:	4798      	blx	r3
+ 804039a:	3601      	adds	r6, #1
+ 804039c:	e7ee      	b.n	804037c <__libc_init_array+0xc>
+ 804039e:	f855 3b04 	ldr.w	r3, [r5], #4
+ 80403a2:	4798      	blx	r3
+ 80403a4:	3601      	adds	r6, #1
+ 80403a6:	e7f2      	b.n	804038e <__libc_init_array+0x1e>
+ 80403a8:	08041e58 	.word	0x08041e58
+ 80403ac:	08041e58 	.word	0x08041e58
+ 80403b0:	08041e58 	.word	0x08041e58
+ 80403b4:	08041e5c 	.word	0x08041e5c
+
+080403b8 <__retarget_lock_acquire_recursive>:
+ 80403b8:	4770      	bx	lr
+
+080403ba <__retarget_lock_release_recursive>:
+ 80403ba:	4770      	bx	lr
+
+080403bc <memcpy>:
+ 80403bc:	440a      	add	r2, r1
+ 80403be:	4291      	cmp	r1, r2
+ 80403c0:	f100 33ff 	add.w	r3, r0, #4294967295
+ 80403c4:	d100      	bne.n	80403c8 <memcpy+0xc>
+ 80403c6:	4770      	bx	lr
+ 80403c8:	b510      	push	{r4, lr}
+ 80403ca:	f811 4b01 	ldrb.w	r4, [r1], #1
+ 80403ce:	f803 4f01 	strb.w	r4, [r3, #1]!
+ 80403d2:	4291      	cmp	r1, r2
+ 80403d4:	d1f9      	bne.n	80403ca <memcpy+0xe>
+ 80403d6:	bd10      	pop	{r4, pc}
+
+080403d8 <_free_r>:
+ 80403d8:	b538      	push	{r3, r4, r5, lr}
+ 80403da:	4605      	mov	r5, r0
+ 80403dc:	2900      	cmp	r1, #0
+ 80403de:	d041      	beq.n	8040464 <_free_r+0x8c>
+ 80403e0:	f851 3c04 	ldr.w	r3, [r1, #-4]
+ 80403e4:	1f0c      	subs	r4, r1, #4
+ 80403e6:	2b00      	cmp	r3, #0
+ 80403e8:	bfb8      	it	lt
+ 80403ea:	18e4      	addlt	r4, r4, r3
+ 80403ec:	f7ff fea4 	bl	8040138 <__malloc_lock>
+ 80403f0:	4a1d      	ldr	r2, [pc, #116]	@ (8040468 <_free_r+0x90>)
+ 80403f2:	6813      	ldr	r3, [r2, #0]
+ 80403f4:	b933      	cbnz	r3, 8040404 <_free_r+0x2c>
+ 80403f6:	6063      	str	r3, [r4, #4]
+ 80403f8:	6014      	str	r4, [r2, #0]
+ 80403fa:	4628      	mov	r0, r5
+ 80403fc:	e8bd 4038 	ldmia.w	sp!, {r3, r4, r5, lr}
+ 8040400:	f7ff bea0 	b.w	8040144 <__malloc_unlock>
+ 8040404:	42a3      	cmp	r3, r4
+ 8040406:	d908      	bls.n	804041a <_free_r+0x42>
+ 8040408:	6820      	ldr	r0, [r4, #0]
+ 804040a:	1821      	adds	r1, r4, r0
+ 804040c:	428b      	cmp	r3, r1
+ 804040e:	bf01      	itttt	eq
+ 8040410:	6819      	ldreq	r1, [r3, #0]
+ 8040412:	685b      	ldreq	r3, [r3, #4]
+ 8040414:	1809      	addeq	r1, r1, r0
+ 8040416:	6021      	streq	r1, [r4, #0]
+ 8040418:	e7ed      	b.n	80403f6 <_free_r+0x1e>
+ 804041a:	461a      	mov	r2, r3
+ 804041c:	685b      	ldr	r3, [r3, #4]
+ 804041e:	b10b      	cbz	r3, 8040424 <_free_r+0x4c>
+ 8040420:	42a3      	cmp	r3, r4
+ 8040422:	d9fa      	bls.n	804041a <_free_r+0x42>
+ 8040424:	6811      	ldr	r1, [r2, #0]
+ 8040426:	1850      	adds	r0, r2, r1
+ 8040428:	42a0      	cmp	r0, r4
+ 804042a:	d10b      	bne.n	8040444 <_free_r+0x6c>
+ 804042c:	6820      	ldr	r0, [r4, #0]
+ 804042e:	4401      	add	r1, r0
+ 8040430:	1850      	adds	r0, r2, r1
+ 8040432:	4283      	cmp	r3, r0
+ 8040434:	6011      	str	r1, [r2, #0]
+ 8040436:	d1e0      	bne.n	80403fa <_free_r+0x22>
+ 8040438:	6818      	ldr	r0, [r3, #0]
+ 804043a:	685b      	ldr	r3, [r3, #4]
+ 804043c:	6053      	str	r3, [r2, #4]
+ 804043e:	4408      	add	r0, r1
+ 8040440:	6010      	str	r0, [r2, #0]
+ 8040442:	e7da      	b.n	80403fa <_free_r+0x22>
+ 8040444:	d902      	bls.n	804044c <_free_r+0x74>
+ 8040446:	230c      	movs	r3, #12
+ 8040448:	602b      	str	r3, [r5, #0]
+ 804044a:	e7d6      	b.n	80403fa <_free_r+0x22>
+ 804044c:	6820      	ldr	r0, [r4, #0]
+ 804044e:	1821      	adds	r1, r4, r0
+ 8040450:	428b      	cmp	r3, r1
+ 8040452:	bf04      	itt	eq
+ 8040454:	6819      	ldreq	r1, [r3, #0]
+ 8040456:	685b      	ldreq	r3, [r3, #4]
+ 8040458:	6063      	str	r3, [r4, #4]
+ 804045a:	bf04      	itt	eq
+ 804045c:	1809      	addeq	r1, r1, r0
+ 804045e:	6021      	streq	r1, [r4, #0]
+ 8040460:	6054      	str	r4, [r2, #4]
+ 8040462:	e7ca      	b.n	80403fa <_free_r+0x22>
+ 8040464:	bd38      	pop	{r3, r4, r5, pc}
+ 8040466:	bf00      	nop
+ 8040468:	2400b280 	.word	0x2400b280
+
+0804046c <__ssputs_r>:
+ 804046c:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
+ 8040470:	688e      	ldr	r6, [r1, #8]
+ 8040472:	461f      	mov	r7, r3
+ 8040474:	42be      	cmp	r6, r7
+ 8040476:	680b      	ldr	r3, [r1, #0]
+ 8040478:	4682      	mov	sl, r0
+ 804047a:	460c      	mov	r4, r1
+ 804047c:	4690      	mov	r8, r2
+ 804047e:	d82d      	bhi.n	80404dc <__ssputs_r+0x70>
+ 8040480:	f9b1 200c 	ldrsh.w	r2, [r1, #12]
+ 8040484:	f412 6f90 	tst.w	r2, #1152	@ 0x480
+ 8040488:	d026      	beq.n	80404d8 <__ssputs_r+0x6c>
+ 804048a:	6965      	ldr	r5, [r4, #20]
+ 804048c:	6909      	ldr	r1, [r1, #16]
+ 804048e:	eb05 0545 	add.w	r5, r5, r5, lsl #1
+ 8040492:	eba3 0901 	sub.w	r9, r3, r1
+ 8040496:	eb05 75d5 	add.w	r5, r5, r5, lsr #31
+ 804049a:	1c7b      	adds	r3, r7, #1
+ 804049c:	444b      	add	r3, r9
+ 804049e:	106d      	asrs	r5, r5, #1
+ 80404a0:	429d      	cmp	r5, r3
+ 80404a2:	bf38      	it	cc
+ 80404a4:	461d      	movcc	r5, r3
+ 80404a6:	0553      	lsls	r3, r2, #21
+ 80404a8:	d527      	bpl.n	80404fa <__ssputs_r+0x8e>
+ 80404aa:	4629      	mov	r1, r5
+ 80404ac:	f7ff fdc4 	bl	8040038 <_malloc_r>
+ 80404b0:	4606      	mov	r6, r0
+ 80404b2:	b360      	cbz	r0, 804050e <__ssputs_r+0xa2>
+ 80404b4:	6921      	ldr	r1, [r4, #16]
+ 80404b6:	464a      	mov	r2, r9
+ 80404b8:	f7ff ff80 	bl	80403bc <memcpy>
+ 80404bc:	89a3      	ldrh	r3, [r4, #12]
+ 80404be:	f423 6390 	bic.w	r3, r3, #1152	@ 0x480
+ 80404c2:	f043 0380 	orr.w	r3, r3, #128	@ 0x80
+ 80404c6:	81a3      	strh	r3, [r4, #12]
+ 80404c8:	6126      	str	r6, [r4, #16]
+ 80404ca:	6165      	str	r5, [r4, #20]
+ 80404cc:	444e      	add	r6, r9
+ 80404ce:	eba5 0509 	sub.w	r5, r5, r9
+ 80404d2:	6026      	str	r6, [r4, #0]
+ 80404d4:	60a5      	str	r5, [r4, #8]
+ 80404d6:	463e      	mov	r6, r7
+ 80404d8:	42be      	cmp	r6, r7
+ 80404da:	d900      	bls.n	80404de <__ssputs_r+0x72>
+ 80404dc:	463e      	mov	r6, r7
+ 80404de:	6820      	ldr	r0, [r4, #0]
+ 80404e0:	4632      	mov	r2, r6
+ 80404e2:	4641      	mov	r1, r8
+ 80404e4:	f000 faa8 	bl	8040a38 <memmove>
+ 80404e8:	68a3      	ldr	r3, [r4, #8]
+ 80404ea:	1b9b      	subs	r3, r3, r6
+ 80404ec:	60a3      	str	r3, [r4, #8]
+ 80404ee:	6823      	ldr	r3, [r4, #0]
+ 80404f0:	4433      	add	r3, r6
+ 80404f2:	6023      	str	r3, [r4, #0]
+ 80404f4:	2000      	movs	r0, #0
+ 80404f6:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
+ 80404fa:	462a      	mov	r2, r5
+ 80404fc:	f000 fab6 	bl	8040a6c <_realloc_r>
+ 8040500:	4606      	mov	r6, r0
+ 8040502:	2800      	cmp	r0, #0
+ 8040504:	d1e0      	bne.n	80404c8 <__ssputs_r+0x5c>
+ 8040506:	6921      	ldr	r1, [r4, #16]
+ 8040508:	4650      	mov	r0, sl
+ 804050a:	f7ff ff65 	bl	80403d8 <_free_r>
+ 804050e:	230c      	movs	r3, #12
+ 8040510:	f8ca 3000 	str.w	r3, [sl]
+ 8040514:	89a3      	ldrh	r3, [r4, #12]
+ 8040516:	f043 0340 	orr.w	r3, r3, #64	@ 0x40
+ 804051a:	81a3      	strh	r3, [r4, #12]
+ 804051c:	f04f 30ff 	mov.w	r0, #4294967295
+ 8040520:	e7e9      	b.n	80404f6 <__ssputs_r+0x8a>
+	...
+
+08040524 <_svfiprintf_r>:
+ 8040524:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
+ 8040528:	4698      	mov	r8, r3
+ 804052a:	898b      	ldrh	r3, [r1, #12]
+ 804052c:	061b      	lsls	r3, r3, #24
+ 804052e:	b09d      	sub	sp, #116	@ 0x74
+ 8040530:	4607      	mov	r7, r0
+ 8040532:	460d      	mov	r5, r1
+ 8040534:	4614      	mov	r4, r2
+ 8040536:	d510      	bpl.n	804055a <_svfiprintf_r+0x36>
+ 8040538:	690b      	ldr	r3, [r1, #16]
+ 804053a:	b973      	cbnz	r3, 804055a <_svfiprintf_r+0x36>
+ 804053c:	2140      	movs	r1, #64	@ 0x40
+ 804053e:	f7ff fd7b 	bl	8040038 <_malloc_r>
+ 8040542:	6028      	str	r0, [r5, #0]
+ 8040544:	6128      	str	r0, [r5, #16]
+ 8040546:	b930      	cbnz	r0, 8040556 <_svfiprintf_r+0x32>
+ 8040548:	230c      	movs	r3, #12
+ 804054a:	603b      	str	r3, [r7, #0]
+ 804054c:	f04f 30ff 	mov.w	r0, #4294967295
+ 8040550:	b01d      	add	sp, #116	@ 0x74
+ 8040552:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
+ 8040556:	2340      	movs	r3, #64	@ 0x40
+ 8040558:	616b      	str	r3, [r5, #20]
+ 804055a:	2300      	movs	r3, #0
+ 804055c:	9309      	str	r3, [sp, #36]	@ 0x24
+ 804055e:	2320      	movs	r3, #32
+ 8040560:	f88d 3029 	strb.w	r3, [sp, #41]	@ 0x29
+ 8040564:	f8cd 800c 	str.w	r8, [sp, #12]
+ 8040568:	2330      	movs	r3, #48	@ 0x30
+ 804056a:	f8df 819c 	ldr.w	r8, [pc, #412]	@ 8040708 <_svfiprintf_r+0x1e4>
+ 804056e:	f88d 302a 	strb.w	r3, [sp, #42]	@ 0x2a
+ 8040572:	f04f 0901 	mov.w	r9, #1
+ 8040576:	4623      	mov	r3, r4
+ 8040578:	469a      	mov	sl, r3
+ 804057a:	f813 2b01 	ldrb.w	r2, [r3], #1
+ 804057e:	b10a      	cbz	r2, 8040584 <_svfiprintf_r+0x60>
+ 8040580:	2a25      	cmp	r2, #37	@ 0x25
+ 8040582:	d1f9      	bne.n	8040578 <_svfiprintf_r+0x54>
+ 8040584:	ebba 0b04 	subs.w	fp, sl, r4
+ 8040588:	d00b      	beq.n	80405a2 <_svfiprintf_r+0x7e>
+ 804058a:	465b      	mov	r3, fp
+ 804058c:	4622      	mov	r2, r4
+ 804058e:	4629      	mov	r1, r5
+ 8040590:	4638      	mov	r0, r7
+ 8040592:	f7ff ff6b 	bl	804046c <__ssputs_r>
+ 8040596:	3001      	adds	r0, #1
+ 8040598:	f000 80a7 	beq.w	80406ea <_svfiprintf_r+0x1c6>
+ 804059c:	9a09      	ldr	r2, [sp, #36]	@ 0x24
+ 804059e:	445a      	add	r2, fp
+ 80405a0:	9209      	str	r2, [sp, #36]	@ 0x24
+ 80405a2:	f89a 3000 	ldrb.w	r3, [sl]
+ 80405a6:	2b00      	cmp	r3, #0
+ 80405a8:	f000 809f 	beq.w	80406ea <_svfiprintf_r+0x1c6>
+ 80405ac:	2300      	movs	r3, #0
+ 80405ae:	f04f 32ff 	mov.w	r2, #4294967295
+ 80405b2:	e9cd 2305 	strd	r2, r3, [sp, #20]
+ 80405b6:	f10a 0a01 	add.w	sl, sl, #1
+ 80405ba:	9304      	str	r3, [sp, #16]
+ 80405bc:	9307      	str	r3, [sp, #28]
+ 80405be:	f88d 3053 	strb.w	r3, [sp, #83]	@ 0x53
+ 80405c2:	931a      	str	r3, [sp, #104]	@ 0x68
+ 80405c4:	4654      	mov	r4, sl
+ 80405c6:	2205      	movs	r2, #5
+ 80405c8:	f814 1b01 	ldrb.w	r1, [r4], #1
+ 80405cc:	484e      	ldr	r0, [pc, #312]	@ (8040708 <_svfiprintf_r+0x1e4>)
+ 80405ce:	f7df fe9f 	bl	8020310 <memchr>
+ 80405d2:	9a04      	ldr	r2, [sp, #16]
+ 80405d4:	b9d8      	cbnz	r0, 804060e <_svfiprintf_r+0xea>
+ 80405d6:	06d0      	lsls	r0, r2, #27
+ 80405d8:	bf44      	itt	mi
+ 80405da:	2320      	movmi	r3, #32
+ 80405dc:	f88d 3053 	strbmi.w	r3, [sp, #83]	@ 0x53
+ 80405e0:	0711      	lsls	r1, r2, #28
+ 80405e2:	bf44      	itt	mi
+ 80405e4:	232b      	movmi	r3, #43	@ 0x2b
+ 80405e6:	f88d 3053 	strbmi.w	r3, [sp, #83]	@ 0x53
+ 80405ea:	f89a 3000 	ldrb.w	r3, [sl]
+ 80405ee:	2b2a      	cmp	r3, #42	@ 0x2a
+ 80405f0:	d015      	beq.n	804061e <_svfiprintf_r+0xfa>
+ 80405f2:	9a07      	ldr	r2, [sp, #28]
+ 80405f4:	4654      	mov	r4, sl
+ 80405f6:	2000      	movs	r0, #0
+ 80405f8:	f04f 0c0a 	mov.w	ip, #10
+ 80405fc:	4621      	mov	r1, r4
+ 80405fe:	f811 3b01 	ldrb.w	r3, [r1], #1
+ 8040602:	3b30      	subs	r3, #48	@ 0x30
+ 8040604:	2b09      	cmp	r3, #9
+ 8040606:	d94b      	bls.n	80406a0 <_svfiprintf_r+0x17c>
+ 8040608:	b1b0      	cbz	r0, 8040638 <_svfiprintf_r+0x114>
+ 804060a:	9207      	str	r2, [sp, #28]
+ 804060c:	e014      	b.n	8040638 <_svfiprintf_r+0x114>
+ 804060e:	eba0 0308 	sub.w	r3, r0, r8
+ 8040612:	fa09 f303 	lsl.w	r3, r9, r3
+ 8040616:	4313      	orrs	r3, r2
+ 8040618:	9304      	str	r3, [sp, #16]
+ 804061a:	46a2      	mov	sl, r4
+ 804061c:	e7d2      	b.n	80405c4 <_svfiprintf_r+0xa0>
+ 804061e:	9b03      	ldr	r3, [sp, #12]
+ 8040620:	1d19      	adds	r1, r3, #4
+ 8040622:	681b      	ldr	r3, [r3, #0]
+ 8040624:	9103      	str	r1, [sp, #12]
+ 8040626:	2b00      	cmp	r3, #0
+ 8040628:	bfbb      	ittet	lt
+ 804062a:	425b      	neglt	r3, r3
+ 804062c:	f042 0202 	orrlt.w	r2, r2, #2
+ 8040630:	9307      	strge	r3, [sp, #28]
+ 8040632:	9307      	strlt	r3, [sp, #28]
+ 8040634:	bfb8      	it	lt
+ 8040636:	9204      	strlt	r2, [sp, #16]
+ 8040638:	7823      	ldrb	r3, [r4, #0]
+ 804063a:	2b2e      	cmp	r3, #46	@ 0x2e
+ 804063c:	d10a      	bne.n	8040654 <_svfiprintf_r+0x130>
+ 804063e:	7863      	ldrb	r3, [r4, #1]
+ 8040640:	2b2a      	cmp	r3, #42	@ 0x2a
+ 8040642:	d132      	bne.n	80406aa <_svfiprintf_r+0x186>
+ 8040644:	9b03      	ldr	r3, [sp, #12]
+ 8040646:	1d1a      	adds	r2, r3, #4
+ 8040648:	681b      	ldr	r3, [r3, #0]
+ 804064a:	9203      	str	r2, [sp, #12]
+ 804064c:	ea43 73e3 	orr.w	r3, r3, r3, asr #31
+ 8040650:	3402      	adds	r4, #2
+ 8040652:	9305      	str	r3, [sp, #20]
+ 8040654:	f8df a0c0 	ldr.w	sl, [pc, #192]	@ 8040718 <_svfiprintf_r+0x1f4>
+ 8040658:	7821      	ldrb	r1, [r4, #0]
+ 804065a:	2203      	movs	r2, #3
+ 804065c:	4650      	mov	r0, sl
+ 804065e:	f7df fe57 	bl	8020310 <memchr>
+ 8040662:	b138      	cbz	r0, 8040674 <_svfiprintf_r+0x150>
+ 8040664:	9b04      	ldr	r3, [sp, #16]
+ 8040666:	eba0 000a 	sub.w	r0, r0, sl
+ 804066a:	2240      	movs	r2, #64	@ 0x40
+ 804066c:	4082      	lsls	r2, r0
+ 804066e:	4313      	orrs	r3, r2
+ 8040670:	3401      	adds	r4, #1
+ 8040672:	9304      	str	r3, [sp, #16]
+ 8040674:	f814 1b01 	ldrb.w	r1, [r4], #1
+ 8040678:	4824      	ldr	r0, [pc, #144]	@ (804070c <_svfiprintf_r+0x1e8>)
+ 804067a:	f88d 1028 	strb.w	r1, [sp, #40]	@ 0x28
+ 804067e:	2206      	movs	r2, #6
+ 8040680:	f7df fe46 	bl	8020310 <memchr>
+ 8040684:	2800      	cmp	r0, #0
+ 8040686:	d036      	beq.n	80406f6 <_svfiprintf_r+0x1d2>
+ 8040688:	4b21      	ldr	r3, [pc, #132]	@ (8040710 <_svfiprintf_r+0x1ec>)
+ 804068a:	bb1b      	cbnz	r3, 80406d4 <_svfiprintf_r+0x1b0>
+ 804068c:	9b03      	ldr	r3, [sp, #12]
+ 804068e:	3307      	adds	r3, #7
+ 8040690:	f023 0307 	bic.w	r3, r3, #7
+ 8040694:	3308      	adds	r3, #8
+ 8040696:	9303      	str	r3, [sp, #12]
+ 8040698:	9b09      	ldr	r3, [sp, #36]	@ 0x24
+ 804069a:	4433      	add	r3, r6
+ 804069c:	9309      	str	r3, [sp, #36]	@ 0x24
+ 804069e:	e76a      	b.n	8040576 <_svfiprintf_r+0x52>
+ 80406a0:	fb0c 3202 	mla	r2, ip, r2, r3
+ 80406a4:	460c      	mov	r4, r1
+ 80406a6:	2001      	movs	r0, #1
+ 80406a8:	e7a8      	b.n	80405fc <_svfiprintf_r+0xd8>
+ 80406aa:	2300      	movs	r3, #0
+ 80406ac:	3401      	adds	r4, #1
+ 80406ae:	9305      	str	r3, [sp, #20]
+ 80406b0:	4619      	mov	r1, r3
+ 80406b2:	f04f 0c0a 	mov.w	ip, #10
+ 80406b6:	4620      	mov	r0, r4
+ 80406b8:	f810 2b01 	ldrb.w	r2, [r0], #1
+ 80406bc:	3a30      	subs	r2, #48	@ 0x30
+ 80406be:	2a09      	cmp	r2, #9
+ 80406c0:	d903      	bls.n	80406ca <_svfiprintf_r+0x1a6>
+ 80406c2:	2b00      	cmp	r3, #0
+ 80406c4:	d0c6      	beq.n	8040654 <_svfiprintf_r+0x130>
+ 80406c6:	9105      	str	r1, [sp, #20]
+ 80406c8:	e7c4      	b.n	8040654 <_svfiprintf_r+0x130>
+ 80406ca:	fb0c 2101 	mla	r1, ip, r1, r2
+ 80406ce:	4604      	mov	r4, r0
+ 80406d0:	2301      	movs	r3, #1
+ 80406d2:	e7f0      	b.n	80406b6 <_svfiprintf_r+0x192>
+ 80406d4:	ab03      	add	r3, sp, #12
+ 80406d6:	9300      	str	r3, [sp, #0]
+ 80406d8:	462a      	mov	r2, r5
+ 80406da:	4b0e      	ldr	r3, [pc, #56]	@ (8040714 <_svfiprintf_r+0x1f0>)
+ 80406dc:	a904      	add	r1, sp, #16
+ 80406de:	4638      	mov	r0, r7
+ 80406e0:	f3af 8000 	nop.w
+ 80406e4:	1c42      	adds	r2, r0, #1
+ 80406e6:	4606      	mov	r6, r0
+ 80406e8:	d1d6      	bne.n	8040698 <_svfiprintf_r+0x174>
+ 80406ea:	89ab      	ldrh	r3, [r5, #12]
+ 80406ec:	065b      	lsls	r3, r3, #25
+ 80406ee:	f53f af2d 	bmi.w	804054c <_svfiprintf_r+0x28>
+ 80406f2:	9809      	ldr	r0, [sp, #36]	@ 0x24
+ 80406f4:	e72c      	b.n	8040550 <_svfiprintf_r+0x2c>
+ 80406f6:	ab03      	add	r3, sp, #12
+ 80406f8:	9300      	str	r3, [sp, #0]
+ 80406fa:	462a      	mov	r2, r5
+ 80406fc:	4b05      	ldr	r3, [pc, #20]	@ (8040714 <_svfiprintf_r+0x1f0>)
+ 80406fe:	a904      	add	r1, sp, #16
+ 8040700:	4638      	mov	r0, r7
+ 8040702:	f000 f879 	bl	80407f8 <_printf_i>
+ 8040706:	e7ed      	b.n	80406e4 <_svfiprintf_r+0x1c0>
+ 8040708:	08041da9 	.word	0x08041da9
+ 804070c:	08041db3 	.word	0x08041db3
+ 8040710:	00000000 	.word	0x00000000
+ 8040714:	0804046d 	.word	0x0804046d
+ 8040718:	08041daf 	.word	0x08041daf
+
+0804071c <_printf_common>:
+ 804071c:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
+ 8040720:	4616      	mov	r6, r2
+ 8040722:	4698      	mov	r8, r3
+ 8040724:	688a      	ldr	r2, [r1, #8]
+ 8040726:	690b      	ldr	r3, [r1, #16]
+ 8040728:	f8dd 9020 	ldr.w	r9, [sp, #32]
+ 804072c:	4293      	cmp	r3, r2
+ 804072e:	bfb8      	it	lt
+ 8040730:	4613      	movlt	r3, r2
+ 8040732:	6033      	str	r3, [r6, #0]
+ 8040734:	f891 2043 	ldrb.w	r2, [r1, #67]	@ 0x43
+ 8040738:	4607      	mov	r7, r0
+ 804073a:	460c      	mov	r4, r1
+ 804073c:	b10a      	cbz	r2, 8040742 <_printf_common+0x26>
+ 804073e:	3301      	adds	r3, #1
+ 8040740:	6033      	str	r3, [r6, #0]
+ 8040742:	6823      	ldr	r3, [r4, #0]
+ 8040744:	0699      	lsls	r1, r3, #26
+ 8040746:	bf42      	ittt	mi
+ 8040748:	6833      	ldrmi	r3, [r6, #0]
+ 804074a:	3302      	addmi	r3, #2
+ 804074c:	6033      	strmi	r3, [r6, #0]
+ 804074e:	6825      	ldr	r5, [r4, #0]
+ 8040750:	f015 0506 	ands.w	r5, r5, #6
+ 8040754:	d106      	bne.n	8040764 <_printf_common+0x48>
+ 8040756:	f104 0a19 	add.w	sl, r4, #25
+ 804075a:	68e3      	ldr	r3, [r4, #12]
+ 804075c:	6832      	ldr	r2, [r6, #0]
+ 804075e:	1a9b      	subs	r3, r3, r2
+ 8040760:	42ab      	cmp	r3, r5
+ 8040762:	dc26      	bgt.n	80407b2 <_printf_common+0x96>
+ 8040764:	f894 3043 	ldrb.w	r3, [r4, #67]	@ 0x43
+ 8040768:	6822      	ldr	r2, [r4, #0]
+ 804076a:	3b00      	subs	r3, #0
+ 804076c:	bf18      	it	ne
+ 804076e:	2301      	movne	r3, #1
+ 8040770:	0692      	lsls	r2, r2, #26
+ 8040772:	d42b      	bmi.n	80407cc <_printf_common+0xb0>
+ 8040774:	f104 0243 	add.w	r2, r4, #67	@ 0x43
+ 8040778:	4641      	mov	r1, r8
+ 804077a:	4638      	mov	r0, r7
+ 804077c:	47c8      	blx	r9
+ 804077e:	3001      	adds	r0, #1
+ 8040780:	d01e      	beq.n	80407c0 <_printf_common+0xa4>
+ 8040782:	6823      	ldr	r3, [r4, #0]
+ 8040784:	6922      	ldr	r2, [r4, #16]
+ 8040786:	f003 0306 	and.w	r3, r3, #6
+ 804078a:	2b04      	cmp	r3, #4
+ 804078c:	bf02      	ittt	eq
+ 804078e:	68e5      	ldreq	r5, [r4, #12]
+ 8040790:	6833      	ldreq	r3, [r6, #0]
+ 8040792:	1aed      	subeq	r5, r5, r3
+ 8040794:	68a3      	ldr	r3, [r4, #8]
+ 8040796:	bf0c      	ite	eq
+ 8040798:	ea25 75e5 	biceq.w	r5, r5, r5, asr #31
+ 804079c:	2500      	movne	r5, #0
+ 804079e:	4293      	cmp	r3, r2
+ 80407a0:	bfc4      	itt	gt
+ 80407a2:	1a9b      	subgt	r3, r3, r2
+ 80407a4:	18ed      	addgt	r5, r5, r3
+ 80407a6:	2600      	movs	r6, #0
+ 80407a8:	341a      	adds	r4, #26
+ 80407aa:	42b5      	cmp	r5, r6
+ 80407ac:	d11a      	bne.n	80407e4 <_printf_common+0xc8>
+ 80407ae:	2000      	movs	r0, #0
+ 80407b0:	e008      	b.n	80407c4 <_printf_common+0xa8>
+ 80407b2:	2301      	movs	r3, #1
+ 80407b4:	4652      	mov	r2, sl
+ 80407b6:	4641      	mov	r1, r8
+ 80407b8:	4638      	mov	r0, r7
+ 80407ba:	47c8      	blx	r9
+ 80407bc:	3001      	adds	r0, #1
+ 80407be:	d103      	bne.n	80407c8 <_printf_common+0xac>
+ 80407c0:	f04f 30ff 	mov.w	r0, #4294967295
+ 80407c4:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
+ 80407c8:	3501      	adds	r5, #1
+ 80407ca:	e7c6      	b.n	804075a <_printf_common+0x3e>
+ 80407cc:	18e1      	adds	r1, r4, r3
+ 80407ce:	1c5a      	adds	r2, r3, #1
+ 80407d0:	2030      	movs	r0, #48	@ 0x30
+ 80407d2:	f881 0043 	strb.w	r0, [r1, #67]	@ 0x43
+ 80407d6:	4422      	add	r2, r4
+ 80407d8:	f894 1045 	ldrb.w	r1, [r4, #69]	@ 0x45
+ 80407dc:	f882 1043 	strb.w	r1, [r2, #67]	@ 0x43
+ 80407e0:	3302      	adds	r3, #2
+ 80407e2:	e7c7      	b.n	8040774 <_printf_common+0x58>
+ 80407e4:	2301      	movs	r3, #1
+ 80407e6:	4622      	mov	r2, r4
+ 80407e8:	4641      	mov	r1, r8
+ 80407ea:	4638      	mov	r0, r7
+ 80407ec:	47c8      	blx	r9
+ 80407ee:	3001      	adds	r0, #1
+ 80407f0:	d0e6      	beq.n	80407c0 <_printf_common+0xa4>
+ 80407f2:	3601      	adds	r6, #1
+ 80407f4:	e7d9      	b.n	80407aa <_printf_common+0x8e>
+	...
+
+080407f8 <_printf_i>:
+ 80407f8:	e92d 47ff 	stmdb	sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr}
+ 80407fc:	7e0f      	ldrb	r7, [r1, #24]
+ 80407fe:	9e0c      	ldr	r6, [sp, #48]	@ 0x30
+ 8040800:	2f78      	cmp	r7, #120	@ 0x78
+ 8040802:	4691      	mov	r9, r2
+ 8040804:	4680      	mov	r8, r0
+ 8040806:	460c      	mov	r4, r1
+ 8040808:	469a      	mov	sl, r3
+ 804080a:	f101 0243 	add.w	r2, r1, #67	@ 0x43
+ 804080e:	d807      	bhi.n	8040820 <_printf_i+0x28>
+ 8040810:	2f62      	cmp	r7, #98	@ 0x62
+ 8040812:	d80a      	bhi.n	804082a <_printf_i+0x32>
+ 8040814:	2f00      	cmp	r7, #0
+ 8040816:	f000 80d2 	beq.w	80409be <_printf_i+0x1c6>
+ 804081a:	2f58      	cmp	r7, #88	@ 0x58
+ 804081c:	f000 80b9 	beq.w	8040992 <_printf_i+0x19a>
+ 8040820:	f104 0642 	add.w	r6, r4, #66	@ 0x42
+ 8040824:	f884 7042 	strb.w	r7, [r4, #66]	@ 0x42
+ 8040828:	e03a      	b.n	80408a0 <_printf_i+0xa8>
+ 804082a:	f1a7 0363 	sub.w	r3, r7, #99	@ 0x63
+ 804082e:	2b15      	cmp	r3, #21
+ 8040830:	d8f6      	bhi.n	8040820 <_printf_i+0x28>
+ 8040832:	a101      	add	r1, pc, #4	@ (adr r1, 8040838 <_printf_i+0x40>)
+ 8040834:	f851 f023 	ldr.w	pc, [r1, r3, lsl #2]
+ 8040838:	08040891 	.word	0x08040891
+ 804083c:	080408a5 	.word	0x080408a5
+ 8040840:	08040821 	.word	0x08040821
+ 8040844:	08040821 	.word	0x08040821
+ 8040848:	08040821 	.word	0x08040821
+ 804084c:	08040821 	.word	0x08040821
+ 8040850:	080408a5 	.word	0x080408a5
+ 8040854:	08040821 	.word	0x08040821
+ 8040858:	08040821 	.word	0x08040821
+ 804085c:	08040821 	.word	0x08040821
+ 8040860:	08040821 	.word	0x08040821
+ 8040864:	080409a5 	.word	0x080409a5
+ 8040868:	080408cf 	.word	0x080408cf
+ 804086c:	0804095f 	.word	0x0804095f
+ 8040870:	08040821 	.word	0x08040821
+ 8040874:	08040821 	.word	0x08040821
+ 8040878:	080409c7 	.word	0x080409c7
+ 804087c:	08040821 	.word	0x08040821
+ 8040880:	080408cf 	.word	0x080408cf
+ 8040884:	08040821 	.word	0x08040821
+ 8040888:	08040821 	.word	0x08040821
+ 804088c:	08040967 	.word	0x08040967
+ 8040890:	6833      	ldr	r3, [r6, #0]
+ 8040892:	1d1a      	adds	r2, r3, #4
+ 8040894:	681b      	ldr	r3, [r3, #0]
+ 8040896:	6032      	str	r2, [r6, #0]
+ 8040898:	f104 0642 	add.w	r6, r4, #66	@ 0x42
+ 804089c:	f884 3042 	strb.w	r3, [r4, #66]	@ 0x42
+ 80408a0:	2301      	movs	r3, #1
+ 80408a2:	e09d      	b.n	80409e0 <_printf_i+0x1e8>
+ 80408a4:	6833      	ldr	r3, [r6, #0]
+ 80408a6:	6820      	ldr	r0, [r4, #0]
+ 80408a8:	1d19      	adds	r1, r3, #4
+ 80408aa:	6031      	str	r1, [r6, #0]
+ 80408ac:	0606      	lsls	r6, r0, #24
+ 80408ae:	d501      	bpl.n	80408b4 <_printf_i+0xbc>
+ 80408b0:	681d      	ldr	r5, [r3, #0]
+ 80408b2:	e003      	b.n	80408bc <_printf_i+0xc4>
+ 80408b4:	0645      	lsls	r5, r0, #25
+ 80408b6:	d5fb      	bpl.n	80408b0 <_printf_i+0xb8>
+ 80408b8:	f9b3 5000 	ldrsh.w	r5, [r3]
+ 80408bc:	2d00      	cmp	r5, #0
+ 80408be:	da03      	bge.n	80408c8 <_printf_i+0xd0>
+ 80408c0:	232d      	movs	r3, #45	@ 0x2d
+ 80408c2:	426d      	negs	r5, r5
+ 80408c4:	f884 3043 	strb.w	r3, [r4, #67]	@ 0x43
+ 80408c8:	4859      	ldr	r0, [pc, #356]	@ (8040a30 <_printf_i+0x238>)
+ 80408ca:	230a      	movs	r3, #10
+ 80408cc:	e011      	b.n	80408f2 <_printf_i+0xfa>
+ 80408ce:	6821      	ldr	r1, [r4, #0]
+ 80408d0:	6833      	ldr	r3, [r6, #0]
+ 80408d2:	0608      	lsls	r0, r1, #24
+ 80408d4:	f853 5b04 	ldr.w	r5, [r3], #4
+ 80408d8:	d402      	bmi.n	80408e0 <_printf_i+0xe8>
+ 80408da:	0649      	lsls	r1, r1, #25
+ 80408dc:	bf48      	it	mi
+ 80408de:	b2ad      	uxthmi	r5, r5
+ 80408e0:	2f6f      	cmp	r7, #111	@ 0x6f
+ 80408e2:	4853      	ldr	r0, [pc, #332]	@ (8040a30 <_printf_i+0x238>)
+ 80408e4:	6033      	str	r3, [r6, #0]
+ 80408e6:	bf14      	ite	ne
+ 80408e8:	230a      	movne	r3, #10
+ 80408ea:	2308      	moveq	r3, #8
+ 80408ec:	2100      	movs	r1, #0
+ 80408ee:	f884 1043 	strb.w	r1, [r4, #67]	@ 0x43
+ 80408f2:	6866      	ldr	r6, [r4, #4]
+ 80408f4:	60a6      	str	r6, [r4, #8]
+ 80408f6:	2e00      	cmp	r6, #0
+ 80408f8:	bfa2      	ittt	ge
+ 80408fa:	6821      	ldrge	r1, [r4, #0]
+ 80408fc:	f021 0104 	bicge.w	r1, r1, #4
+ 8040900:	6021      	strge	r1, [r4, #0]
+ 8040902:	b90d      	cbnz	r5, 8040908 <_printf_i+0x110>
+ 8040904:	2e00      	cmp	r6, #0
+ 8040906:	d04b      	beq.n	80409a0 <_printf_i+0x1a8>
+ 8040908:	4616      	mov	r6, r2
+ 804090a:	fbb5 f1f3 	udiv	r1, r5, r3
+ 804090e:	fb03 5711 	mls	r7, r3, r1, r5
+ 8040912:	5dc7      	ldrb	r7, [r0, r7]
+ 8040914:	f806 7d01 	strb.w	r7, [r6, #-1]!
+ 8040918:	462f      	mov	r7, r5
+ 804091a:	42bb      	cmp	r3, r7
+ 804091c:	460d      	mov	r5, r1
+ 804091e:	d9f4      	bls.n	804090a <_printf_i+0x112>
+ 8040920:	2b08      	cmp	r3, #8
+ 8040922:	d10b      	bne.n	804093c <_printf_i+0x144>
+ 8040924:	6823      	ldr	r3, [r4, #0]
+ 8040926:	07df      	lsls	r7, r3, #31
+ 8040928:	d508      	bpl.n	804093c <_printf_i+0x144>
+ 804092a:	6923      	ldr	r3, [r4, #16]
+ 804092c:	6861      	ldr	r1, [r4, #4]
+ 804092e:	4299      	cmp	r1, r3
+ 8040930:	bfde      	ittt	le
+ 8040932:	2330      	movle	r3, #48	@ 0x30
+ 8040934:	f806 3c01 	strble.w	r3, [r6, #-1]
+ 8040938:	f106 36ff 	addle.w	r6, r6, #4294967295
+ 804093c:	1b92      	subs	r2, r2, r6
+ 804093e:	6122      	str	r2, [r4, #16]
+ 8040940:	f8cd a000 	str.w	sl, [sp]
+ 8040944:	464b      	mov	r3, r9
+ 8040946:	aa03      	add	r2, sp, #12
+ 8040948:	4621      	mov	r1, r4
+ 804094a:	4640      	mov	r0, r8
+ 804094c:	f7ff fee6 	bl	804071c <_printf_common>
+ 8040950:	3001      	adds	r0, #1
+ 8040952:	d14a      	bne.n	80409ea <_printf_i+0x1f2>
+ 8040954:	f04f 30ff 	mov.w	r0, #4294967295
+ 8040958:	b004      	add	sp, #16
+ 804095a:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
+ 804095e:	6823      	ldr	r3, [r4, #0]
+ 8040960:	f043 0320 	orr.w	r3, r3, #32
+ 8040964:	6023      	str	r3, [r4, #0]
+ 8040966:	4833      	ldr	r0, [pc, #204]	@ (8040a34 <_printf_i+0x23c>)
+ 8040968:	2778      	movs	r7, #120	@ 0x78
+ 804096a:	f884 7045 	strb.w	r7, [r4, #69]	@ 0x45
+ 804096e:	6823      	ldr	r3, [r4, #0]
+ 8040970:	6831      	ldr	r1, [r6, #0]
+ 8040972:	061f      	lsls	r7, r3, #24
+ 8040974:	f851 5b04 	ldr.w	r5, [r1], #4
+ 8040978:	d402      	bmi.n	8040980 <_printf_i+0x188>
+ 804097a:	065f      	lsls	r7, r3, #25
+ 804097c:	bf48      	it	mi
+ 804097e:	b2ad      	uxthmi	r5, r5
+ 8040980:	6031      	str	r1, [r6, #0]
+ 8040982:	07d9      	lsls	r1, r3, #31
+ 8040984:	bf44      	itt	mi
+ 8040986:	f043 0320 	orrmi.w	r3, r3, #32
+ 804098a:	6023      	strmi	r3, [r4, #0]
+ 804098c:	b11d      	cbz	r5, 8040996 <_printf_i+0x19e>
+ 804098e:	2310      	movs	r3, #16
+ 8040990:	e7ac      	b.n	80408ec <_printf_i+0xf4>
+ 8040992:	4827      	ldr	r0, [pc, #156]	@ (8040a30 <_printf_i+0x238>)
+ 8040994:	e7e9      	b.n	804096a <_printf_i+0x172>
+ 8040996:	6823      	ldr	r3, [r4, #0]
+ 8040998:	f023 0320 	bic.w	r3, r3, #32
+ 804099c:	6023      	str	r3, [r4, #0]
+ 804099e:	e7f6      	b.n	804098e <_printf_i+0x196>
+ 80409a0:	4616      	mov	r6, r2
+ 80409a2:	e7bd      	b.n	8040920 <_printf_i+0x128>
+ 80409a4:	6833      	ldr	r3, [r6, #0]
+ 80409a6:	6825      	ldr	r5, [r4, #0]
+ 80409a8:	6961      	ldr	r1, [r4, #20]
+ 80409aa:	1d18      	adds	r0, r3, #4
+ 80409ac:	6030      	str	r0, [r6, #0]
+ 80409ae:	062e      	lsls	r6, r5, #24
+ 80409b0:	681b      	ldr	r3, [r3, #0]
+ 80409b2:	d501      	bpl.n	80409b8 <_printf_i+0x1c0>
+ 80409b4:	6019      	str	r1, [r3, #0]
+ 80409b6:	e002      	b.n	80409be <_printf_i+0x1c6>
+ 80409b8:	0668      	lsls	r0, r5, #25
+ 80409ba:	d5fb      	bpl.n	80409b4 <_printf_i+0x1bc>
+ 80409bc:	8019      	strh	r1, [r3, #0]
+ 80409be:	2300      	movs	r3, #0
+ 80409c0:	6123      	str	r3, [r4, #16]
+ 80409c2:	4616      	mov	r6, r2
+ 80409c4:	e7bc      	b.n	8040940 <_printf_i+0x148>
+ 80409c6:	6833      	ldr	r3, [r6, #0]
+ 80409c8:	1d1a      	adds	r2, r3, #4
+ 80409ca:	6032      	str	r2, [r6, #0]
+ 80409cc:	681e      	ldr	r6, [r3, #0]
+ 80409ce:	6862      	ldr	r2, [r4, #4]
+ 80409d0:	2100      	movs	r1, #0
+ 80409d2:	4630      	mov	r0, r6
+ 80409d4:	f7df fc9c 	bl	8020310 <memchr>
+ 80409d8:	b108      	cbz	r0, 80409de <_printf_i+0x1e6>
+ 80409da:	1b80      	subs	r0, r0, r6
+ 80409dc:	6060      	str	r0, [r4, #4]
+ 80409de:	6863      	ldr	r3, [r4, #4]
+ 80409e0:	6123      	str	r3, [r4, #16]
+ 80409e2:	2300      	movs	r3, #0
+ 80409e4:	f884 3043 	strb.w	r3, [r4, #67]	@ 0x43
+ 80409e8:	e7aa      	b.n	8040940 <_printf_i+0x148>
+ 80409ea:	6923      	ldr	r3, [r4, #16]
+ 80409ec:	4632      	mov	r2, r6
+ 80409ee:	4649      	mov	r1, r9
+ 80409f0:	4640      	mov	r0, r8
+ 80409f2:	47d0      	blx	sl
+ 80409f4:	3001      	adds	r0, #1
+ 80409f6:	d0ad      	beq.n	8040954 <_printf_i+0x15c>
+ 80409f8:	6823      	ldr	r3, [r4, #0]
+ 80409fa:	079b      	lsls	r3, r3, #30
+ 80409fc:	d413      	bmi.n	8040a26 <_printf_i+0x22e>
+ 80409fe:	68e0      	ldr	r0, [r4, #12]
+ 8040a00:	9b03      	ldr	r3, [sp, #12]
+ 8040a02:	4298      	cmp	r0, r3
+ 8040a04:	bfb8      	it	lt
+ 8040a06:	4618      	movlt	r0, r3
+ 8040a08:	e7a6      	b.n	8040958 <_printf_i+0x160>
+ 8040a0a:	2301      	movs	r3, #1
+ 8040a0c:	4632      	mov	r2, r6
+ 8040a0e:	4649      	mov	r1, r9
+ 8040a10:	4640      	mov	r0, r8
+ 8040a12:	47d0      	blx	sl
+ 8040a14:	3001      	adds	r0, #1
+ 8040a16:	d09d      	beq.n	8040954 <_printf_i+0x15c>
+ 8040a18:	3501      	adds	r5, #1
+ 8040a1a:	68e3      	ldr	r3, [r4, #12]
+ 8040a1c:	9903      	ldr	r1, [sp, #12]
+ 8040a1e:	1a5b      	subs	r3, r3, r1
+ 8040a20:	42ab      	cmp	r3, r5
+ 8040a22:	dcf2      	bgt.n	8040a0a <_printf_i+0x212>
+ 8040a24:	e7eb      	b.n	80409fe <_printf_i+0x206>
+ 8040a26:	2500      	movs	r5, #0
+ 8040a28:	f104 0619 	add.w	r6, r4, #25
+ 8040a2c:	e7f5      	b.n	8040a1a <_printf_i+0x222>
+ 8040a2e:	bf00      	nop
+ 8040a30:	08041dba 	.word	0x08041dba
+ 8040a34:	08041dcb 	.word	0x08041dcb
+
+08040a38 <memmove>:
+ 8040a38:	4288      	cmp	r0, r1
+ 8040a3a:	b510      	push	{r4, lr}
+ 8040a3c:	eb01 0402 	add.w	r4, r1, r2
+ 8040a40:	d902      	bls.n	8040a48 <memmove+0x10>
+ 8040a42:	4284      	cmp	r4, r0
+ 8040a44:	4623      	mov	r3, r4
+ 8040a46:	d807      	bhi.n	8040a58 <memmove+0x20>
+ 8040a48:	1e43      	subs	r3, r0, #1
+ 8040a4a:	42a1      	cmp	r1, r4
+ 8040a4c:	d008      	beq.n	8040a60 <memmove+0x28>
+ 8040a4e:	f811 2b01 	ldrb.w	r2, [r1], #1
+ 8040a52:	f803 2f01 	strb.w	r2, [r3, #1]!
+ 8040a56:	e7f8      	b.n	8040a4a <memmove+0x12>
+ 8040a58:	4402      	add	r2, r0
+ 8040a5a:	4601      	mov	r1, r0
+ 8040a5c:	428a      	cmp	r2, r1
+ 8040a5e:	d100      	bne.n	8040a62 <memmove+0x2a>
+ 8040a60:	bd10      	pop	{r4, pc}
+ 8040a62:	f813 4d01 	ldrb.w	r4, [r3, #-1]!
+ 8040a66:	f802 4d01 	strb.w	r4, [r2, #-1]!
+ 8040a6a:	e7f7      	b.n	8040a5c <memmove+0x24>
+
+08040a6c <_realloc_r>:
+ 8040a6c:	e92d 41f0 	stmdb	sp!, {r4, r5, r6, r7, r8, lr}
+ 8040a70:	4680      	mov	r8, r0
+ 8040a72:	4615      	mov	r5, r2
+ 8040a74:	460c      	mov	r4, r1
+ 8040a76:	b921      	cbnz	r1, 8040a82 <_realloc_r+0x16>
+ 8040a78:	e8bd 41f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, lr}
+ 8040a7c:	4611      	mov	r1, r2
+ 8040a7e:	f7ff badb 	b.w	8040038 <_malloc_r>
+ 8040a82:	b92a      	cbnz	r2, 8040a90 <_realloc_r+0x24>
+ 8040a84:	f7ff fca8 	bl	80403d8 <_free_r>
+ 8040a88:	2400      	movs	r4, #0
+ 8040a8a:	4620      	mov	r0, r4
+ 8040a8c:	e8bd 81f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, pc}
+ 8040a90:	f000 f81a 	bl	8040ac8 <_malloc_usable_size_r>
+ 8040a94:	4285      	cmp	r5, r0
+ 8040a96:	4606      	mov	r6, r0
+ 8040a98:	d802      	bhi.n	8040aa0 <_realloc_r+0x34>
+ 8040a9a:	ebb5 0f50 	cmp.w	r5, r0, lsr #1
+ 8040a9e:	d8f4      	bhi.n	8040a8a <_realloc_r+0x1e>
+ 8040aa0:	4629      	mov	r1, r5
+ 8040aa2:	4640      	mov	r0, r8
+ 8040aa4:	f7ff fac8 	bl	8040038 <_malloc_r>
+ 8040aa8:	4607      	mov	r7, r0
+ 8040aaa:	2800      	cmp	r0, #0
+ 8040aac:	d0ec      	beq.n	8040a88 <_realloc_r+0x1c>
+ 8040aae:	42b5      	cmp	r5, r6
+ 8040ab0:	462a      	mov	r2, r5
+ 8040ab2:	4621      	mov	r1, r4
+ 8040ab4:	bf28      	it	cs
+ 8040ab6:	4632      	movcs	r2, r6
+ 8040ab8:	f7ff fc80 	bl	80403bc <memcpy>
+ 8040abc:	4621      	mov	r1, r4
+ 8040abe:	4640      	mov	r0, r8
+ 8040ac0:	f7ff fc8a 	bl	80403d8 <_free_r>
+ 8040ac4:	463c      	mov	r4, r7
+ 8040ac6:	e7e0      	b.n	8040a8a <_realloc_r+0x1e>
+
+08040ac8 <_malloc_usable_size_r>:
+ 8040ac8:	f851 3c04 	ldr.w	r3, [r1, #-4]
+ 8040acc:	1f18      	subs	r0, r3, #4
+ 8040ace:	2b00      	cmp	r3, #0
+ 8040ad0:	bfbc      	itt	lt
+ 8040ad2:	580b      	ldrlt	r3, [r1, r0]
+ 8040ad4:	18c0      	addlt	r0, r0, r3
+ 8040ad6:	4770      	bx	lr
+
+08040ad8 <atan2>:
+ 8040ad8:	f000 b802 	b.w	8040ae0 <__ieee754_atan2>
+ 8040adc:	0000      	movs	r0, r0
+	...
+
+08040ae0 <__ieee754_atan2>:
+ 8040ae0:	ee11 1a10 	vmov	r1, s2
+ 8040ae4:	eeb0 7b40 	vmov.f64	d7, d0
+ 8040ae8:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+ 8040aea:	ee11 5a90 	vmov	r5, s3
+ 8040aee:	424b      	negs	r3, r1
+ 8040af0:	4f59      	ldr	r7, [pc, #356]	@ (8040c58 <__ieee754_atan2+0x178>)
+ 8040af2:	f025 4200 	bic.w	r2, r5, #2147483648	@ 0x80000000
+ 8040af6:	430b      	orrs	r3, r1
+ 8040af8:	ea42 73d3 	orr.w	r3, r2, r3, lsr #31
+ 8040afc:	42bb      	cmp	r3, r7
+ 8040afe:	d80d      	bhi.n	8040b1c <__ieee754_atan2+0x3c>
+ 8040b00:	ee10 ca10 	vmov	ip, s0
+ 8040b04:	ee17 6a90 	vmov	r6, s15
+ 8040b08:	f1cc 0000 	rsb	r0, ip, #0
+ 8040b0c:	f026 4300 	bic.w	r3, r6, #2147483648	@ 0x80000000
+ 8040b10:	ea40 000c 	orr.w	r0, r0, ip
+ 8040b14:	ea43 70d0 	orr.w	r0, r3, r0, lsr #31
+ 8040b18:	42b8      	cmp	r0, r7
+ 8040b1a:	d904      	bls.n	8040b26 <__ieee754_atan2+0x46>
+ 8040b1c:	ee37 7b01 	vadd.f64	d7, d7, d1
+ 8040b20:	eeb0 0b47 	vmov.f64	d0, d7
+ 8040b24:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
+ 8040b26:	f105 4040 	add.w	r0, r5, #3221225472	@ 0xc0000000
+ 8040b2a:	f500 1080 	add.w	r0, r0, #1048576	@ 0x100000
+ 8040b2e:	4308      	orrs	r0, r1
+ 8040b30:	d103      	bne.n	8040b3a <__ieee754_atan2+0x5a>
+ 8040b32:	e8bd 40f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, lr}
+ 8040b36:	f000 b897 	b.w	8040c68 <atan>
+ 8040b3a:	17ac      	asrs	r4, r5, #30
+ 8040b3c:	f004 0402 	and.w	r4, r4, #2
+ 8040b40:	ea53 0c0c 	orrs.w	ip, r3, ip
+ 8040b44:	ea44 74d6 	orr.w	r4, r4, r6, lsr #31
+ 8040b48:	d107      	bne.n	8040b5a <__ieee754_atan2+0x7a>
+ 8040b4a:	2c02      	cmp	r4, #2
+ 8040b4c:	d05c      	beq.n	8040c08 <__ieee754_atan2+0x128>
+ 8040b4e:	ed9f 6b34 	vldr	d6, [pc, #208]	@ 8040c20 <__ieee754_atan2+0x140>
+ 8040b52:	2c03      	cmp	r4, #3
+ 8040b54:	fe06 7b00 	vseleq.f64	d7, d6, d0
+ 8040b58:	e7e2      	b.n	8040b20 <__ieee754_atan2+0x40>
+ 8040b5a:	4311      	orrs	r1, r2
+ 8040b5c:	d107      	bne.n	8040b6e <__ieee754_atan2+0x8e>
+ 8040b5e:	ed9f 7b32 	vldr	d7, [pc, #200]	@ 8040c28 <__ieee754_atan2+0x148>
+ 8040b62:	ed9f 6b33 	vldr	d6, [pc, #204]	@ 8040c30 <__ieee754_atan2+0x150>
+ 8040b66:	2e00      	cmp	r6, #0
+ 8040b68:	fe27 7b06 	vselge.f64	d7, d7, d6
+ 8040b6c:	e7d8      	b.n	8040b20 <__ieee754_atan2+0x40>
+ 8040b6e:	42ba      	cmp	r2, r7
+ 8040b70:	d10f      	bne.n	8040b92 <__ieee754_atan2+0xb2>
+ 8040b72:	4293      	cmp	r3, r2
+ 8040b74:	f104 34ff 	add.w	r4, r4, #4294967295
+ 8040b78:	d107      	bne.n	8040b8a <__ieee754_atan2+0xaa>
+ 8040b7a:	2c02      	cmp	r4, #2
+ 8040b7c:	d847      	bhi.n	8040c0e <__ieee754_atan2+0x12e>
+ 8040b7e:	4b37      	ldr	r3, [pc, #220]	@ (8040c5c <__ieee754_atan2+0x17c>)
+ 8040b80:	eb03 03c4 	add.w	r3, r3, r4, lsl #3
+ 8040b84:	ed93 7b00 	vldr	d7, [r3]
+ 8040b88:	e7ca      	b.n	8040b20 <__ieee754_atan2+0x40>
+ 8040b8a:	2c02      	cmp	r4, #2
+ 8040b8c:	d842      	bhi.n	8040c14 <__ieee754_atan2+0x134>
+ 8040b8e:	4b34      	ldr	r3, [pc, #208]	@ (8040c60 <__ieee754_atan2+0x180>)
+ 8040b90:	e7f6      	b.n	8040b80 <__ieee754_atan2+0xa0>
+ 8040b92:	42bb      	cmp	r3, r7
+ 8040b94:	d0e3      	beq.n	8040b5e <__ieee754_atan2+0x7e>
+ 8040b96:	1a9b      	subs	r3, r3, r2
+ 8040b98:	f1b3 7f74 	cmp.w	r3, #63963136	@ 0x3d00000
+ 8040b9c:	ea4f 5223 	mov.w	r2, r3, asr #20
+ 8040ba0:	da1a      	bge.n	8040bd8 <__ieee754_atan2+0xf8>
+ 8040ba2:	2d00      	cmp	r5, #0
+ 8040ba4:	da01      	bge.n	8040baa <__ieee754_atan2+0xca>
+ 8040ba6:	323c      	adds	r2, #60	@ 0x3c
+ 8040ba8:	db19      	blt.n	8040bde <__ieee754_atan2+0xfe>
+ 8040baa:	ee87 0b01 	vdiv.f64	d0, d7, d1
+ 8040bae:	f000 f955 	bl	8040e5c <fabs>
+ 8040bb2:	f000 f859 	bl	8040c68 <atan>
+ 8040bb6:	eeb0 7b40 	vmov.f64	d7, d0
+ 8040bba:	2c01      	cmp	r4, #1
+ 8040bbc:	d012      	beq.n	8040be4 <__ieee754_atan2+0x104>
+ 8040bbe:	2c02      	cmp	r4, #2
+ 8040bc0:	d019      	beq.n	8040bf6 <__ieee754_atan2+0x116>
+ 8040bc2:	2c00      	cmp	r4, #0
+ 8040bc4:	d0ac      	beq.n	8040b20 <__ieee754_atan2+0x40>
+ 8040bc6:	ed9f 6b1c 	vldr	d6, [pc, #112]	@ 8040c38 <__ieee754_atan2+0x158>
+ 8040bca:	ee37 7b46 	vsub.f64	d7, d7, d6
+ 8040bce:	ed9f 6b1c 	vldr	d6, [pc, #112]	@ 8040c40 <__ieee754_atan2+0x160>
+ 8040bd2:	ee37 7b46 	vsub.f64	d7, d7, d6
+ 8040bd6:	e7a3      	b.n	8040b20 <__ieee754_atan2+0x40>
+ 8040bd8:	ed9f 7b13 	vldr	d7, [pc, #76]	@ 8040c28 <__ieee754_atan2+0x148>
+ 8040bdc:	e7ed      	b.n	8040bba <__ieee754_atan2+0xda>
+ 8040bde:	ed9f 7b1a 	vldr	d7, [pc, #104]	@ 8040c48 <__ieee754_atan2+0x168>
+ 8040be2:	e7ea      	b.n	8040bba <__ieee754_atan2+0xda>
+ 8040be4:	ee17 1a90 	vmov	r1, s15
+ 8040be8:	ec53 2b17 	vmov	r2, r3, d7
+ 8040bec:	f101 4300 	add.w	r3, r1, #2147483648	@ 0x80000000
+ 8040bf0:	ec43 2b17 	vmov	d7, r2, r3
+ 8040bf4:	e794      	b.n	8040b20 <__ieee754_atan2+0x40>
+ 8040bf6:	ed9f 6b10 	vldr	d6, [pc, #64]	@ 8040c38 <__ieee754_atan2+0x158>
+ 8040bfa:	ee37 7b46 	vsub.f64	d7, d7, d6
+ 8040bfe:	ed9f 6b10 	vldr	d6, [pc, #64]	@ 8040c40 <__ieee754_atan2+0x160>
+ 8040c02:	ee36 7b47 	vsub.f64	d7, d6, d7
+ 8040c06:	e78b      	b.n	8040b20 <__ieee754_atan2+0x40>
+ 8040c08:	ed9f 7b0d 	vldr	d7, [pc, #52]	@ 8040c40 <__ieee754_atan2+0x160>
+ 8040c0c:	e788      	b.n	8040b20 <__ieee754_atan2+0x40>
+ 8040c0e:	ed9f 7b10 	vldr	d7, [pc, #64]	@ 8040c50 <__ieee754_atan2+0x170>
+ 8040c12:	e785      	b.n	8040b20 <__ieee754_atan2+0x40>
+ 8040c14:	ed9f 7b0c 	vldr	d7, [pc, #48]	@ 8040c48 <__ieee754_atan2+0x168>
+ 8040c18:	e782      	b.n	8040b20 <__ieee754_atan2+0x40>
+ 8040c1a:	bf00      	nop
+ 8040c1c:	f3af 8000 	nop.w
+ 8040c20:	54442d18 	.word	0x54442d18
+ 8040c24:	c00921fb 	.word	0xc00921fb
+ 8040c28:	54442d18 	.word	0x54442d18
+ 8040c2c:	3ff921fb 	.word	0x3ff921fb
+ 8040c30:	54442d18 	.word	0x54442d18
+ 8040c34:	bff921fb 	.word	0xbff921fb
+ 8040c38:	33145c07 	.word	0x33145c07
+ 8040c3c:	3ca1a626 	.word	0x3ca1a626
+ 8040c40:	54442d18 	.word	0x54442d18
+ 8040c44:	400921fb 	.word	0x400921fb
+	...
+ 8040c50:	54442d18 	.word	0x54442d18
+ 8040c54:	3fe921fb 	.word	0x3fe921fb
+ 8040c58:	7ff00000 	.word	0x7ff00000
+ 8040c5c:	08041df8 	.word	0x08041df8
+ 8040c60:	08041de0 	.word	0x08041de0
+ 8040c64:	00000000 	.word	0x00000000
+
+08040c68 <atan>:
+ 8040c68:	b538      	push	{r3, r4, r5, lr}
+ 8040c6a:	eeb0 7b40 	vmov.f64	d7, d0
+ 8040c6e:	ee17 5a90 	vmov	r5, s15
+ 8040c72:	4b73      	ldr	r3, [pc, #460]	@ (8040e40 <atan+0x1d8>)
+ 8040c74:	f025 4400 	bic.w	r4, r5, #2147483648	@ 0x80000000
+ 8040c78:	429c      	cmp	r4, r3
+ 8040c7a:	d913      	bls.n	8040ca4 <atan+0x3c>
+ 8040c7c:	4b71      	ldr	r3, [pc, #452]	@ (8040e44 <atan+0x1dc>)
+ 8040c7e:	429c      	cmp	r4, r3
+ 8040c80:	d803      	bhi.n	8040c8a <atan+0x22>
+ 8040c82:	d107      	bne.n	8040c94 <atan+0x2c>
+ 8040c84:	ee10 3a10 	vmov	r3, s0
+ 8040c88:	b123      	cbz	r3, 8040c94 <atan+0x2c>
+ 8040c8a:	ee37 7b07 	vadd.f64	d7, d7, d7
+ 8040c8e:	eeb0 0b47 	vmov.f64	d0, d7
+ 8040c92:	bd38      	pop	{r3, r4, r5, pc}
+ 8040c94:	ed9f 7b4e 	vldr	d7, [pc, #312]	@ 8040dd0 <atan+0x168>
+ 8040c98:	ed9f 6b4f 	vldr	d6, [pc, #316]	@ 8040dd8 <atan+0x170>
+ 8040c9c:	2d00      	cmp	r5, #0
+ 8040c9e:	fe36 7b07 	vselgt.f64	d7, d6, d7
+ 8040ca2:	e7f4      	b.n	8040c8e <atan+0x26>
+ 8040ca4:	4b68      	ldr	r3, [pc, #416]	@ (8040e48 <atan+0x1e0>)
+ 8040ca6:	429c      	cmp	r4, r3
+ 8040ca8:	d811      	bhi.n	8040cce <atan+0x66>
+ 8040caa:	f1a3 73de 	sub.w	r3, r3, #29097984	@ 0x1bc0000
+ 8040cae:	429c      	cmp	r4, r3
+ 8040cb0:	d80a      	bhi.n	8040cc8 <atan+0x60>
+ 8040cb2:	eeb7 5b00 	vmov.f64	d5, #112	@ 0x3f800000  1.0
+ 8040cb6:	ed9f 6b4a 	vldr	d6, [pc, #296]	@ 8040de0 <atan+0x178>
+ 8040cba:	ee30 6b06 	vadd.f64	d6, d0, d6
+ 8040cbe:	eeb4 6bc5 	vcmpe.f64	d6, d5
+ 8040cc2:	eef1 fa10 	vmrs	APSR_nzcv, fpscr
+ 8040cc6:	dce2      	bgt.n	8040c8e <atan+0x26>
+ 8040cc8:	f04f 33ff 	mov.w	r3, #4294967295
+ 8040ccc:	e013      	b.n	8040cf6 <atan+0x8e>
+ 8040cce:	f000 f8c5 	bl	8040e5c <fabs>
+ 8040cd2:	4b5e      	ldr	r3, [pc, #376]	@ (8040e4c <atan+0x1e4>)
+ 8040cd4:	429c      	cmp	r4, r3
+ 8040cd6:	d84f      	bhi.n	8040d78 <atan+0x110>
+ 8040cd8:	f5a3 2350 	sub.w	r3, r3, #851968	@ 0xd0000
+ 8040cdc:	429c      	cmp	r4, r3
+ 8040cde:	d841      	bhi.n	8040d64 <atan+0xfc>
+ 8040ce0:	eeb0 7b00 	vmov.f64	d7, #0	@ 0x40000000  2.0
+ 8040ce4:	eebf 5b00 	vmov.f64	d5, #240	@ 0xbf800000 -1.0
+ 8040ce8:	2300      	movs	r3, #0
+ 8040cea:	eea0 5b07 	vfma.f64	d5, d0, d7
+ 8040cee:	ee30 0b07 	vadd.f64	d0, d0, d7
+ 8040cf2:	ee85 7b00 	vdiv.f64	d7, d5, d0
+ 8040cf6:	ed9f 6b3c 	vldr	d6, [pc, #240]	@ 8040de8 <atan+0x180>
+ 8040cfa:	ee27 4b07 	vmul.f64	d4, d7, d7
+ 8040cfe:	ee24 5b04 	vmul.f64	d5, d4, d4
+ 8040d02:	ed9f 3b3b 	vldr	d3, [pc, #236]	@ 8040df0 <atan+0x188>
+ 8040d06:	eea5 3b06 	vfma.f64	d3, d5, d6
+ 8040d0a:	ed9f 6b3b 	vldr	d6, [pc, #236]	@ 8040df8 <atan+0x190>
+ 8040d0e:	eea3 6b05 	vfma.f64	d6, d3, d5
+ 8040d12:	ed9f 3b3b 	vldr	d3, [pc, #236]	@ 8040e00 <atan+0x198>
+ 8040d16:	eea6 3b05 	vfma.f64	d3, d6, d5
+ 8040d1a:	ed9f 6b3b 	vldr	d6, [pc, #236]	@ 8040e08 <atan+0x1a0>
+ 8040d1e:	eea3 6b05 	vfma.f64	d6, d3, d5
+ 8040d22:	ed9f 3b3b 	vldr	d3, [pc, #236]	@ 8040e10 <atan+0x1a8>
+ 8040d26:	ed9f 2b3c 	vldr	d2, [pc, #240]	@ 8040e18 <atan+0x1b0>
+ 8040d2a:	eea6 3b05 	vfma.f64	d3, d6, d5
+ 8040d2e:	ed9f 6b3c 	vldr	d6, [pc, #240]	@ 8040e20 <atan+0x1b8>
+ 8040d32:	eea5 2b06 	vfma.f64	d2, d5, d6
+ 8040d36:	ed9f 6b3c 	vldr	d6, [pc, #240]	@ 8040e28 <atan+0x1c0>
+ 8040d3a:	eea2 6b05 	vfma.f64	d6, d2, d5
+ 8040d3e:	ed9f 2b3c 	vldr	d2, [pc, #240]	@ 8040e30 <atan+0x1c8>
+ 8040d42:	eea6 2b05 	vfma.f64	d2, d6, d5
+ 8040d46:	ed9f 6b3c 	vldr	d6, [pc, #240]	@ 8040e38 <atan+0x1d0>
+ 8040d4a:	1c5a      	adds	r2, r3, #1
+ 8040d4c:	eea2 6b05 	vfma.f64	d6, d2, d5
+ 8040d50:	ee26 6b05 	vmul.f64	d6, d6, d5
+ 8040d54:	eea3 6b04 	vfma.f64	d6, d3, d4
+ 8040d58:	ee27 6b06 	vmul.f64	d6, d7, d6
+ 8040d5c:	d121      	bne.n	8040da2 <atan+0x13a>
+ 8040d5e:	ee37 7b46 	vsub.f64	d7, d7, d6
+ 8040d62:	e794      	b.n	8040c8e <atan+0x26>
+ 8040d64:	eeb7 7b00 	vmov.f64	d7, #112	@ 0x3f800000  1.0
+ 8040d68:	2301      	movs	r3, #1
+ 8040d6a:	ee30 5b47 	vsub.f64	d5, d0, d7
+ 8040d6e:	ee30 0b07 	vadd.f64	d0, d0, d7
+ 8040d72:	ee85 7b00 	vdiv.f64	d7, d5, d0
+ 8040d76:	e7be      	b.n	8040cf6 <atan+0x8e>
+ 8040d78:	4b35      	ldr	r3, [pc, #212]	@ (8040e50 <atan+0x1e8>)
+ 8040d7a:	429c      	cmp	r4, r3
+ 8040d7c:	d20b      	bcs.n	8040d96 <atan+0x12e>
+ 8040d7e:	eeb7 7b08 	vmov.f64	d7, #120	@ 0x3fc00000  1.5
+ 8040d82:	eeb7 6b00 	vmov.f64	d6, #112	@ 0x3f800000  1.0
+ 8040d86:	ee30 5b47 	vsub.f64	d5, d0, d7
+ 8040d8a:	eea0 6b07 	vfma.f64	d6, d0, d7
+ 8040d8e:	2302      	movs	r3, #2
+ 8040d90:	ee85 7b06 	vdiv.f64	d7, d5, d6
+ 8040d94:	e7af      	b.n	8040cf6 <atan+0x8e>
+ 8040d96:	eebf 6b00 	vmov.f64	d6, #240	@ 0xbf800000 -1.0
+ 8040d9a:	2303      	movs	r3, #3
+ 8040d9c:	ee86 7b00 	vdiv.f64	d7, d6, d0
+ 8040da0:	e7a9      	b.n	8040cf6 <atan+0x8e>
+ 8040da2:	4a2c      	ldr	r2, [pc, #176]	@ (8040e54 <atan+0x1ec>)
+ 8040da4:	492c      	ldr	r1, [pc, #176]	@ (8040e58 <atan+0x1f0>)
+ 8040da6:	eb02 02c3 	add.w	r2, r2, r3, lsl #3
+ 8040daa:	eb01 03c3 	add.w	r3, r1, r3, lsl #3
+ 8040dae:	ed93 5b00 	vldr	d5, [r3]
+ 8040db2:	ee36 6b45 	vsub.f64	d6, d6, d5
+ 8040db6:	ee36 6b47 	vsub.f64	d6, d6, d7
+ 8040dba:	ed92 7b00 	vldr	d7, [r2]
+ 8040dbe:	2d00      	cmp	r5, #0
+ 8040dc0:	ee37 7b46 	vsub.f64	d7, d7, d6
+ 8040dc4:	bfb8      	it	lt
+ 8040dc6:	eeb1 7b47 	vneglt.f64	d7, d7
+ 8040dca:	e760      	b.n	8040c8e <atan+0x26>
+ 8040dcc:	f3af 8000 	nop.w
+ 8040dd0:	54442d18 	.word	0x54442d18
+ 8040dd4:	bff921fb 	.word	0xbff921fb
+ 8040dd8:	54442d18 	.word	0x54442d18
+ 8040ddc:	3ff921fb 	.word	0x3ff921fb
+ 8040de0:	8800759c 	.word	0x8800759c
+ 8040de4:	7e37e43c 	.word	0x7e37e43c
+ 8040de8:	e322da11 	.word	0xe322da11
+ 8040dec:	3f90ad3a 	.word	0x3f90ad3a
+ 8040df0:	24760deb 	.word	0x24760deb
+ 8040df4:	3fa97b4b 	.word	0x3fa97b4b
+ 8040df8:	a0d03d51 	.word	0xa0d03d51
+ 8040dfc:	3fb10d66 	.word	0x3fb10d66
+ 8040e00:	c54c206e 	.word	0xc54c206e
+ 8040e04:	3fb745cd 	.word	0x3fb745cd
+ 8040e08:	920083ff 	.word	0x920083ff
+ 8040e0c:	3fc24924 	.word	0x3fc24924
+ 8040e10:	5555550d 	.word	0x5555550d
+ 8040e14:	3fd55555 	.word	0x3fd55555
+ 8040e18:	52defd9a 	.word	0x52defd9a
+ 8040e1c:	bfadde2d 	.word	0xbfadde2d
+ 8040e20:	2c6a6c2f 	.word	0x2c6a6c2f
+ 8040e24:	bfa2b444 	.word	0xbfa2b444
+ 8040e28:	af749a6d 	.word	0xaf749a6d
+ 8040e2c:	bfb3b0f2 	.word	0xbfb3b0f2
+ 8040e30:	fe231671 	.word	0xfe231671
+ 8040e34:	bfbc71c6 	.word	0xbfbc71c6
+ 8040e38:	9998ebc4 	.word	0x9998ebc4
+ 8040e3c:	bfc99999 	.word	0xbfc99999
+ 8040e40:	440fffff 	.word	0x440fffff
+ 8040e44:	7ff00000 	.word	0x7ff00000
+ 8040e48:	3fdbffff 	.word	0x3fdbffff
+ 8040e4c:	3ff2ffff 	.word	0x3ff2ffff
+ 8040e50:	40038000 	.word	0x40038000
+ 8040e54:	08041e30 	.word	0x08041e30
+ 8040e58:	08041e10 	.word	0x08041e10
+
+08040e5c <fabs>:
+ 8040e5c:	ec51 0b10 	vmov	r0, r1, d0
+ 8040e60:	4602      	mov	r2, r0
+ 8040e62:	f021 4300 	bic.w	r3, r1, #2147483648	@ 0x80000000
+ 8040e66:	ec43 2b10 	vmov	d0, r2, r3
+ 8040e6a:	4770      	bx	lr
+
+08040e6c <_init>:
+ 8040e6c:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+ 8040e6e:	bf00      	nop
+ 8040e70:	bcf8      	pop	{r3, r4, r5, r6, r7}
+ 8040e72:	bc08      	pop	{r3}
+ 8040e74:	469e      	mov	lr, r3
+ 8040e76:	4770      	bx	lr
+
+08040e78 <_fini>:
+ 8040e78:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+ 8040e7a:	bf00      	nop
+ 8040e7c:	bcf8      	pop	{r3, r4, r5, r6, r7}
+ 8040e7e:	bc08      	pop	{r3}
+ 8040e80:	469e      	mov	lr, r3
+ 8040e82:	4770      	bx	lr
diff --git a/Debug/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3.map b/Debug/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3.map
new file mode 100644
index 0000000..4eaa202
--- /dev/null
+++ b/Debug/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3.map
@@ -0,0 +1,20142 @@
+Archive member included to satisfy reference by file (symbol)
+
+F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-exit.o)
+                              F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o (exit)
+F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-malloc.o)
+                              ./Core/BASE/Src/BSP/bsp_Error_Detect.o (malloc)
+F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-mallocr.o)
+                              F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-malloc.o) (_malloc_r)
+F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-mlock.o)
+                              F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-mallocr.o) (__malloc_lock)
+F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-strtoul.o)
+                              ./Core/BASE/Src/MSP/msp_Blast_Machine.o (strtoul)
+F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-ctype_.o)
+                              F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-strtoul.o) (_ctype_)
+F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-findfp.o)
+                              F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-exit.o) (__stdio_exit_handler)
+F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-fwalk.o)
+                              F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-findfp.o) (_fwalk_sglue)
+F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-printf.o)
+                              ./Core/BASE/Src/BSP/bsp_qspi_w25q128.o (printf)
+F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-snprintf.o)
+                              ./Core/BASE/Src/MSP/msp_Blast_Machine.o (snprintf)
+F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-stdio.o)
+                              F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-findfp.o) (__sread)
+F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-vsprintf.o)
+                              ./Core/BASE/Src/BSP/DLT/DLTuc.o (vsprintf)
+F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-memset.o)
+                              F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o (memset)
+F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-strncat.o)
+                              ./Core/BASE/Src/MSP/msp_Blast_Machine.o (strncat)
+F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-strncpy.o)
+                              ./Core/BASE/Src/MSP/msp_Blast_Machine.o (strncpy)
+F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-closer.o)
+                              F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-stdio.o) (_close_r)
+F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-reent.o)
+                              F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-closer.o) (errno)
+F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-impure.o)
+                              F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-malloc.o) (_impure_ptr)
+F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-lseekr.o)
+                              F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-stdio.o) (_lseek_r)
+F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-readr.o)
+                              F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-stdio.o) (_read_r)
+F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-sbrkr.o)
+                              F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-mallocr.o) (_sbrk_r)
+F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-writer.o)
+                              F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-stdio.o) (_write_r)
+F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-errno.o)
+                              ./Core/Src/syscalls.o (__errno)
+F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-init.o)
+                              F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o (__libc_init_array)
+F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-lock.o)
+                              F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-findfp.o) (__retarget_lock_init_recursive)
+F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-strcmp.o)
+                              ./Core/BASE/Src/BSP/bsp_com_helper.o (strcmp)
+F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-memcpy-stub.o)
+                              ./Core/BASE/Src/BSP/bsp_DLT_Log.o (memcpy)
+F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-strlen.o)
+                              ./Core/BASE/Src/BSP/bsp_com_helper.o (strlen)
+F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-freer.o)
+                              F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-malloc.o) (_free_r)
+F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-nano-svfprintf.o)
+                              F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-snprintf.o) (_svfprintf_r)
+F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-nano-vfprintf.o)
+                              F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-printf.o) (_vfprintf_r)
+F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-nano-vfprintf_i.o)
+                              F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-nano-svfprintf.o) (_printf_i)
+F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-fflush.o)
+                              F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-findfp.o) (_fflush_r)
+F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-fvwrite.o)
+                              F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-nano-vfprintf.o) (__sfvwrite_r)
+F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-wbuf.o)
+                              F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-nano-vfprintf.o) (__swbuf_r)
+F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-wsetup.o)
+                              F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-nano-vfprintf.o) (__swsetup_r)
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+                              F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-nano-svfprintf.o) (memmove)
+F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-memchr.o)
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+ .group         0x00000000        0xc ./Core/BASE/Src/BSP/bsp_UpperComputer_Handler.o
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+ .group         0x00000000        0xc ./Core/BASE/Src/BSP/bsp_UpperComputer_Handler.o
+ .text          0x00000000        0x0 ./Core/BASE/Src/BSP/bsp_UpperComputer_Handler.o
+ .data          0x00000000        0x0 ./Core/BASE/Src/BSP/bsp_UpperComputer_Handler.o
+ .bss           0x00000000        0x0 ./Core/BASE/Src/BSP/bsp_UpperComputer_Handler.o
+ .text.send_data_to_upper_computer
+                0x00000000       0x28 ./Core/BASE/Src/BSP/bsp_UpperComputer_Handler.o
+ .debug_macro   0x00000000      0xacc ./Core/BASE/Src/BSP/bsp_UpperComputer_Handler.o
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+ .debug_macro   0x00000000    0x258f9 ./Core/BASE/Src/BSP/bsp_UpperComputer_Handler.o
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+ .debug_macro   0x00000000      0x129 ./Core/BASE/Src/BSP/bsp_UpperComputer_Handler.o
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+ .debug_macro   0x00000000      0x6cc ./Core/BASE/Src/BSP/bsp_UpperComputer_Handler.o
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+
+Memory Configuration
+
+Name             Origin             Length             Attributes
+FLASH            0x08020000         0x0005e800         xr
+DTCMRAM          0x20000000         0x00020000         xrw
+RAM_D1           0x24000000         0x00080000         xrw
+RAM_D2           0x30000000         0x00048000         xrw
+RAM_D3           0x38000000         0x00010000         xrw
+ITCMRAM          0x00000000         0x00010000         xrw
+*default*        0x00000000         0xffffffff
+
+Linker script and memory map
+
+LOAD F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+dp/hard/crti.o
+LOAD F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+dp/hard/crtbegin.o
+LOAD F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o
+LOAD ./Core/BASE/Protobuf/PSource/bsp_CV.pb.o
+LOAD ./Core/BASE/Protobuf/PSource/bsp_Cmd.pb.o
+LOAD ./Core/BASE/Protobuf/PSource/bsp_Error.pb.o
+LOAD ./Core/BASE/Protobuf/PSource/bsp_GV.pb.o
+LOAD ./Core/BASE/Protobuf/PSource/bsp_IAP.pb.o
+LOAD ./Core/BASE/Protobuf/PSource/bsp_IO.pb.o
+LOAD ./Core/BASE/Protobuf/PSource/bsp_IV.pb.o
+LOAD ./Core/BASE/Protobuf/PSource/bsp_PV.pb.o
+LOAD ./Core/BASE/Protobuf/PSource/bsp_ReCmd.pb.o
+LOAD ./Core/BASE/Protobuf/PSource/msp_CMCU.pb.o
+LOAD ./Core/BASE/Protobuf/PSource/msp_KS206.pb.o
+LOAD ./Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.o
+LOAD ./Core/BASE/Protobuf/PSource/msp_MK32.pb.o
+LOAD ./Core/BASE/Protobuf/PSource/msp_Motor.pb.o
+LOAD ./Core/BASE/Protobuf/PSource/msp_TL720D.pb.o
+LOAD ./Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.o
+LOAD ./Core/BASE/Src/BSP/BHBF_ROBOT.o
+LOAD ./Core/BASE/Src/BSP/bsp_DLT_Log.o
+LOAD ./Core/BASE/Src/BSP/bsp_EEPROM.o
+LOAD ./Core/BASE/Src/BSP/bsp_Error_Detect.o
+LOAD ./Core/BASE/Src/BSP/bsp_FDCAN.o
+LOAD ./Core/BASE/Src/BSP/bsp_GPIO.o
+LOAD ./Core/BASE/Src/BSP/bsp_INTERCALL.o
+LOAD ./Core/BASE/Src/BSP/bsp_MB_host.o
+LOAD ./Core/BASE/Src/BSP/bsp_TIMER.o
+LOAD ./Core/BASE/Src/BSP/bsp_UART.o
+LOAD ./Core/BASE/Src/BSP/bsp_UpperComputer_Handler.o
+LOAD ./Core/BASE/Src/BSP/bsp_client_setting.o
+LOAD ./Core/BASE/Src/BSP/bsp_com_helper.o
+LOAD ./Core/BASE/Src/BSP/bsp_cpu_flash.o
+LOAD ./Core/BASE/Src/BSP/bsp_decode_command.o
+LOAD ./Core/BASE/Src/BSP/bsp_qspi_w25q128.o
+LOAD ./Core/BASE/Src/BSP/pb_common.o
+LOAD ./Core/BASE/Src/BSP/pb_decode.o
+LOAD ./Core/BASE/Src/BSP/pb_encode.o
+LOAD ./Core/BASE/Src/BSP/DLT/DLTuc.o
+LOAD ./Core/BASE/Src/MSP/msp_Blast_Machine.o
+LOAD ./Core/BASE/Src/MSP/msp_CMCUU.o
+LOAD ./Core/BASE/Src/MSP/msp_KS206.o
+LOAD ./Core/BASE/Src/MSP/msp_MF_Gyroscope.o
+LOAD ./Core/BASE/Src/MSP/msp_MK32_1.o
+LOAD ./Core/BASE/Src/MSP/msp_PID.o
+LOAD ./Core/BASE/Src/MSP/msp_TL720D.o
+LOAD ./Core/BASE/Src/MSP/msp_TTMotor_ZQ.o
+LOAD ./Core/BASE/Src/MSP/msp_WH_LTE_7S0.o
+LOAD ./Core/Src/adc.o
+LOAD ./Core/Src/dma.o
+LOAD ./Core/Src/eth.o
+LOAD ./Core/Src/fdcan.o
+LOAD ./Core/Src/fsm.o
+LOAD ./Core/Src/gpio.o
+LOAD ./Core/Src/i2c.o
+LOAD ./Core/Src/main.o
+LOAD ./Core/Src/motors.o
+LOAD ./Core/Src/quadspi.o
+LOAD ./Core/Src/robot_state.o
+LOAD ./Core/Src/stm32h7xx_hal_msp.o
+LOAD ./Core/Src/stm32h7xx_it.o
+LOAD ./Core/Src/syscalls.o
+LOAD ./Core/Src/sysmem.o
+LOAD ./Core/Src/system_stm32h7xx.o
+LOAD ./Core/Src/tim.o
+LOAD ./Core/Src/usart.o
+LOAD ./Core/Startup/startup_stm32h743vgtx.o
+LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
+LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.o
+LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.o
+LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
+LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
+LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o
+LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o
+LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o
+LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o
+LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o
+LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o
+LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o
+LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
+LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o
+LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
+LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o
+LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o
+LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.o
+LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
+LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
+LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.o
+LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.o
+START GROUP
+LOAD F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a
+LOAD F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libm.a
+END GROUP
+START GROUP
+LOAD F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+dp/hard\libgcc.a
+LOAD F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a
+END GROUP
+START GROUP
+LOAD F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+dp/hard\libgcc.a
+LOAD F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a
+LOAD F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libnosys.a
+END GROUP
+START GROUP
+LOAD F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+dp/hard\libgcc.a
+LOAD F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a
+LOAD F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libnosys.a
+END GROUP
+LOAD F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+dp/hard/crtend.o
+LOAD F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+dp/hard/crtn.o
+                0x24080000                        _estack = (ORIGIN (RAM_D1) + LENGTH (RAM_D1))
+                0x00000800                        _Min_Heap_Size = 0x800
+                0x00002000                        _Min_Stack_Size = 0x2000
+
+.isr_vector     0x08020000      0x298
+                0x08020000                        . = ALIGN (0x4)
+ *(.isr_vector)
+ .isr_vector    0x08020000      0x298 ./Core/Startup/startup_stm32h743vgtx.o
+                0x08020000                g_pfnVectors
+                0x08020298                        . = ALIGN (0x4)
+
+.text           0x080202a0    0x20be4
+                0x080202a0                        . = ALIGN (0x4)
+ *(.text)
+ .text          0x080202a0       0x40 F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+dp/hard/crtbegin.o
+ .text          0x080202e0       0x14 F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-strcmp.o)
+                0x080202e0                strcmp
+ .text          0x080202f4       0x10 F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-strlen.o)
+                0x080202f4                strlen
+ *fill*         0x08020304        0xc 
+ .text          0x08020310       0xa0 F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-memchr.o)
+                0x08020310                memchr
+ .text          0x080203b0       0x30 F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+dp/hard\libgcc.a(_aeabi_uldivmod.o)
+                0x080203b0                __aeabi_uldivmod
+ .text          0x080203e0      0x2bc F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+dp/hard\libgcc.a(_udivmoddi4.o)
+                0x080203e0                __udivmoddi4
+ .text          0x0802069c        0x4 F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+dp/hard\libgcc.a(_dvmd_tls.o)
+                0x0802069c                __aeabi_idiv0
+                0x0802069c                __aeabi_ldiv0
+ *(.text*)
+ .text.SET_BIT_1
+                0x080206a0       0x28 ./Core/BASE/Src/BSP/BHBF_ROBOT.o
+                0x080206a0                SET_BIT_1
+ .text.SET_BIT_0
+                0x080206c8       0x2a ./Core/BASE/Src/BSP/BHBF_ROBOT.o
+                0x080206c8                SET_BIT_0
+ .text.Get_BIT  0x080206f2       0x24 ./Core/BASE/Src/BSP/BHBF_ROBOT.o
+                0x080206f2                Get_BIT
+ *fill*         0x08020716        0x2 
+ .text.SystemTimer_Intialize
+                0x08020718       0x20 ./Core/BASE/Src/BSP/BHBF_ROBOT.o
+                0x08020718                SystemTimer_Intialize
+ .text.GF_Timer_Count
+                0x08020738       0x1c ./Core/BASE/Src/BSP/BHBF_ROBOT.o
+                0x08020738                GF_Timer_Count
+ .text.dLT_Log_intialize
+                0x08020754       0x68 ./Core/BASE/Src/BSP/bsp_DLT_Log.o
+                0x08020754                dLT_Log_intialize
+ .text.DLT_DataTransmit
+                0x080207bc       0x38 ./Core/BASE/Src/BSP/bsp_DLT_Log.o
+                0x080207bc                DLT_DataTransmit
+ .text.DLT_DataReceiveEndCallback
+                0x080207f4       0x1c ./Core/BASE/Src/BSP/bsp_DLT_Log.o
+                0x080207f4                DLT_DataReceiveEndCallback
+ .text.DLT_LowLevelReceiveDmaToIdle
+                0x08020810       0x28 ./Core/BASE/Src/BSP/bsp_DLT_Log.o
+                0x08020810                DLT_LowLevelReceiveDmaToIdle
+ .text.DltInjectDataRcvd
+                0x08020838       0x64 ./Core/BASE/Src/BSP/bsp_DLT_Log.o
+                0x08020838                DltInjectDataRcvd
+ .text.GetSysTime
+                0x0802089c        0xe ./Core/BASE/Src/BSP/bsp_DLT_Log.o
+                0x0802089c                GetSysTime
+ .text.GF_BSP_EEPROM_Init
+                0x080208aa       0x12 ./Core/BASE/Src/BSP/bsp_EEPROM.o
+                0x080208aa                GF_BSP_EEPROM_Init
+ .text.bsp_InitI2C
+                0x080208bc       0x44 ./Core/BASE/Src/BSP/bsp_EEPROM.o
+                0x080208bc                bsp_InitI2C
+ .text.i2c_Delay
+                0x08020900        0xe ./Core/BASE/Src/BSP/bsp_EEPROM.o
+ *fill*         0x0802090e        0x2 
+ .text.i2c_Start
+                0x08020910       0x38 ./Core/BASE/Src/BSP/bsp_EEPROM.o
+                0x08020910                i2c_Start
+ .text.i2c_Stop
+                0x08020948       0x30 ./Core/BASE/Src/BSP/bsp_EEPROM.o
+                0x08020948                i2c_Stop
+ .text.i2c_SendByte
+                0x08020978       0x78 ./Core/BASE/Src/BSP/bsp_EEPROM.o
+                0x08020978                i2c_SendByte
+ .text.i2c_ReadByte
+                0x080209f0       0x5c ./Core/BASE/Src/BSP/bsp_EEPROM.o
+                0x080209f0                i2c_ReadByte
+ .text.i2c_WaitAck
+                0x08020a4c       0x50 ./Core/BASE/Src/BSP/bsp_EEPROM.o
+                0x08020a4c                i2c_WaitAck
+ .text.i2c_Ack  0x08020a9c       0x3c ./Core/BASE/Src/BSP/bsp_EEPROM.o
+                0x08020a9c                i2c_Ack
+ .text.i2c_NAck
+                0x08020ad8       0x30 ./Core/BASE/Src/BSP/bsp_EEPROM.o
+                0x08020ad8                i2c_NAck
+ .text.i2c_CheckDevice
+                0x08020b08       0x4c ./Core/BASE/Src/BSP/bsp_EEPROM.o
+                0x08020b08                i2c_CheckDevice
+ .text.GF_BSP_EEPROM_CheckOK
+                0x08020b54       0x1e ./Core/BASE/Src/BSP/bsp_EEPROM.o
+                0x08020b54                GF_BSP_EEPROM_CheckOK
+ .text.GF_BSP_EEPROM_ReadBytes
+                0x08020b72       0xbe ./Core/BASE/Src/BSP/bsp_EEPROM.o
+                0x08020b72                GF_BSP_EEPROM_ReadBytes
+ .text.GF_BSP_EEPROM_Get_CV
+                0x08020c30       0x3c ./Core/BASE/Src/BSP/bsp_EEPROM.o
+                0x08020c30                GF_BSP_EEPROM_Get_CV
+ .text.Error_Detect_Intialzie
+                0x08020c6c       0x6c ./Core/BASE/Src/BSP/bsp_Error_Detect.o
+                0x08020c6c                Error_Detect_Intialzie
+ .text.ErrorDetect
+                0x08020cd8       0x28 ./Core/BASE/Src/BSP/bsp_Error_Detect.o
+                0x08020cd8                ErrorDetect
+ .text.GF_BSP_FDCAN_Init
+                0x08020d00       0x74 ./Core/BASE/Src/BSP/bsp_FDCAN.o
+                0x08020d00                GF_BSP_FDCAN_Init
+ .text.HAL_FDCAN_ErrorStatusCallback
+                0x08020d74       0x38 ./Core/BASE/Src/BSP/bsp_FDCAN.o
+                0x08020d74                HAL_FDCAN_ErrorStatusCallback
+ .text.HAL_FDCAN_RxFifo0Callback
+                0x08020dac       0xf4 ./Core/BASE/Src/BSP/bsp_FDCAN.o
+                0x08020dac                HAL_FDCAN_RxFifo0Callback
+ .text.GF_BSP_CANHandler_Init
+                0x08020ea0       0x4c ./Core/BASE/Src/BSP/bsp_FDCAN.o
+                0x08020ea0                GF_BSP_CANHandler_Init
+ .text.GF_BSP_CANHandler_Init_CAN
+                0x08020eec       0xa4 ./Core/BASE/Src/BSP/bsp_FDCAN.o
+                0x08020eec                GF_BSP_CANHandler_Init_CAN
+ .text.GF_BSP_CAN_Timer
+                0x08020f90       0x68 ./Core/BASE/Src/BSP/bsp_FDCAN.o
+                0x08020f90                GF_BSP_CAN_Timer
+ .text.GF_CAN_Send_List_Send
+                0x08020ff8       0xc6 ./Core/BASE/Src/BSP/bsp_FDCAN.o
+                0x08020ff8                GF_CAN_Send_List_Send
+ *fill*         0x080210be        0x2 
+ .text.CAN_Send_t
+                0x080210c0       0xa4 ./Core/BASE/Src/BSP/bsp_FDCAN.o
+                0x080210c0                CAN_Send_t
+ .text.CAN_Send_Data_t
+                0x08021164       0x28 ./Core/BASE/Src/BSP/bsp_FDCAN.o
+                0x08021164                CAN_Send_Data_t
+ .text.CANHandlerAddTxList
+                0x0802118c       0x86 ./Core/BASE/Src/BSP/bsp_FDCAN.o
+                0x0802118c                CANHandlerAddTxList
+ *fill*         0x08021212        0x2 
+ .text.GF_BSP_GPIO_SetIO
+                0x08021214       0xdc ./Core/BASE/Src/BSP/bsp_GPIO.o
+                0x08021214                GF_BSP_GPIO_SetIO
+ .text.GF_BSP_Interrupt_Add_CallBack
+                0x080212f0       0x7c ./Core/BASE/Src/BSP/bsp_INTERCALL.o
+                0x080212f0                GF_BSP_Interrupt_Add_CallBack
+ .text.GF_BSP_Interrupt_Run_CallBack
+                0x0802136c       0x68 ./Core/BASE/Src/BSP/bsp_INTERCALL.o
+                0x0802136c                GF_BSP_Interrupt_Run_CallBack
+ .text.MB_CRC16
+                0x080213d4       0x68 ./Core/BASE/Src/BSP/bsp_MB_host.o
+                0x080213d4                MB_CRC16
+ .text.GF_BSP_TIMER_Init
+                0x0802143c       0x20 ./Core/BASE/Src/BSP/bsp_TIMER.o
+                0x0802143c                GF_BSP_TIMER_Init
+ .text.HAL_TIM_PeriodElapsedCallback
+                0x0802145c       0x38 ./Core/BASE/Src/BSP/bsp_TIMER.o
+                0x0802145c                HAL_TIM_PeriodElapsedCallback
+ .text.GF_BSP_TIMER_DelayUS
+                0x08021494       0x8c ./Core/BASE/Src/BSP/bsp_TIMER.o
+                0x08021494                GF_BSP_TIMER_DelayUS
+ .text.GF_BSP_UARTHandlers_Intialize
+                0x08021520      0x174 ./Core/BASE/Src/BSP/bsp_UART.o
+                0x08021520                GF_BSP_UARTHandlers_Intialize
+ .text.GF_BSP_UART_Timer
+                0x08021694       0x58 ./Core/BASE/Src/BSP/bsp_UART.o
+                0x08021694                GF_BSP_UART_Timer
+ .text.UARTHandlerAddTxList
+                0x080216ec       0xa2 ./Core/BASE/Src/BSP/bsp_UART.o
+                0x080216ec                UARTHandlerAddTxList
+ *fill*         0x0802178e        0x2 
+ .text.UARTHandlerTx
+                0x08021790      0x22c ./Core/BASE/Src/BSP/bsp_UART.o
+                0x08021790                UARTHandlerTx
+ .text.UARTHandlerRX
+                0x080219bc       0x80 ./Core/BASE/Src/BSP/bsp_UART.o
+                0x080219bc                UARTHandlerRX
+ .text.IntializeUARTHandler
+                0x08021a3c       0xe8 ./Core/BASE/Src/BSP/bsp_UART.o
+                0x08021a3c                IntializeUARTHandler
+ .text.Counting
+                0x08021b24       0xb4 ./Core/BASE/Src/BSP/bsp_UART.o
+                0x08021b24                Counting
+ .text.HAL_UART_RxCpltCallback
+                0x08021bd8       0xdc ./Core/BASE/Src/BSP/bsp_UART.o
+                0x08021bd8                HAL_UART_RxCpltCallback
+ .text.HAL_UART_TxCpltCallback
+                0x08021cb4       0xa4 ./Core/BASE/Src/BSP/bsp_UART.o
+                0x08021cb4                HAL_UART_TxCpltCallback
+ .text.GF_UART_Send_List_Send
+                0x08021d58       0xf4 ./Core/BASE/Src/BSP/bsp_UART.o
+                0x08021d58                GF_UART_Send_List_Send
+ .text.upper_Computer_UART_Handler_intialize
+                0x08021e4c       0x48 ./Core/BASE/Src/BSP/bsp_UpperComputer_Handler.o
+                0x08021e4c                upper_Computer_UART_Handler_intialize
+ .text.decode_command_from_computer
+                0x08021e94       0x44 ./Core/BASE/Src/BSP/bsp_UpperComputer_Handler.o
+                0x08021e94                decode_command_from_computer
+ .text.client_setting_intialize
+                0x08021ed8       0xc8 ./Core/BASE/Src/BSP/bsp_client_setting.o
+                0x08021ed8                client_setting_intialize
+ .text.UpdateIV
+                0x08021fa0       0xbc ./Core/BASE/Src/BSP/bsp_client_setting.o
+                0x08021fa0                UpdateIV
+ .text.decode_received_data_from_client
+                0x0802205c      0x1ac ./Core/BASE/Src/BSP/bsp_client_setting.o
+                0x0802205c                decode_received_data_from_client
+ .text.Dispatch_t
+                0x08022208       0x72 ./Core/BASE/Src/BSP/bsp_com_helper.o
+                0x08022208                Dispatch_t
+ .text.Dispatcher_List_Add_t
+                0x0802227a       0xa2 ./Core/BASE/Src/BSP/bsp_com_helper.o
+                0x0802227a                Dispatcher_List_Add_t
+ .text.ComHardWare_List_Add_t
+                0x0802231c       0xd2 ./Core/BASE/Src/BSP/bsp_com_helper.o
+                0x0802231c                ComHardWare_List_Add_t
+ *fill*         0x080223ee        0x2 
+ .text.PCOMHardWare_Check_t
+                0x080223f0      0x124 ./Core/BASE/Src/BSP/bsp_com_helper.o
+                0x080223f0                PCOMHardWare_Check_t
+ .text.Set_PCOMHardWare_t
+                0x08022514       0x58 ./Core/BASE/Src/BSP/bsp_com_helper.o
+                0x08022514                Set_PCOMHardWare_t
+ .text.decode_command_and_feedback
+                0x0802256c       0x1e ./Core/BASE/Src/BSP/bsp_decode_command.o
+                0x0802256c                decode_command_and_feedback
+ *fill*         0x0802258a        0x2 
+ .text.WrapInCmdAndSend
+                0x0802258c      0x134 ./Core/BASE/Src/BSP/bsp_decode_command.o
+                0x0802258c                WrapInCmdAndSend
+ .text.send_received_data_to_upper_computer
+                0x080226c0       0x54 ./Core/BASE/Src/BSP/bsp_decode_command.o
+                0x080226c0                send_received_data_to_upper_computer
+ .text.load_descriptor_values
+                0x08022714      0x2d4 ./Core/BASE/Src/BSP/pb_common.o
+ .text.advance_iterator
+                0x080229e8       0xc0 ./Core/BASE/Src/BSP/pb_common.o
+ .text.pb_field_iter_begin
+                0x08022aa8       0x32 ./Core/BASE/Src/BSP/pb_common.o
+                0x08022aa8                pb_field_iter_begin
+ .text.pb_field_iter_begin_extension
+                0x08022ada       0x60 ./Core/BASE/Src/BSP/pb_common.o
+                0x08022ada                pb_field_iter_begin_extension
+ .text.pb_field_iter_next
+                0x08022b3a       0x2a ./Core/BASE/Src/BSP/pb_common.o
+                0x08022b3a                pb_field_iter_next
+ .text.pb_field_iter_find
+                0x08022b64       0xac ./Core/BASE/Src/BSP/pb_common.o
+                0x08022b64                pb_field_iter_find
+ .text.pb_field_iter_find_extension
+                0x08022c10       0x66 ./Core/BASE/Src/BSP/pb_common.o
+                0x08022c10                pb_field_iter_find_extension
+ .text.pb_const_cast
+                0x08022c76       0x1a ./Core/BASE/Src/BSP/pb_common.o
+ .text.pb_field_iter_begin_const
+                0x08022c90       0x28 ./Core/BASE/Src/BSP/pb_common.o
+                0x08022c90                pb_field_iter_begin_const
+ .text.pb_field_iter_begin_extension_const
+                0x08022cb8       0x24 ./Core/BASE/Src/BSP/pb_common.o
+                0x08022cb8                pb_field_iter_begin_extension_const
+ .text.pb_default_field_callback
+                0x08022cdc       0x6a ./Core/BASE/Src/BSP/pb_common.o
+                0x08022cdc                pb_default_field_callback
+ .text.buf_read
+                0x08022d46       0x38 ./Core/BASE/Src/BSP/pb_decode.o
+ *fill*         0x08022d7e        0x2 
+ .text.pb_read  0x08022d80       0xec ./Core/BASE/Src/BSP/pb_decode.o
+                0x08022d80                pb_read
+ .text.pb_readbyte
+                0x08022e6c       0x78 ./Core/BASE/Src/BSP/pb_decode.o
+ .text.pb_istream_from_buffer
+                0x08022ee4       0x3c ./Core/BASE/Src/BSP/pb_decode.o
+                0x08022ee4                pb_istream_from_buffer
+ .text.pb_decode_varint32_eof
+                0x08022f20      0x154 ./Core/BASE/Src/BSP/pb_decode.o
+ .text.pb_decode_varint32
+                0x08023074       0x1e ./Core/BASE/Src/BSP/pb_decode.o
+                0x08023074                pb_decode_varint32
+ *fill*         0x08023092        0x2 
+ .text.pb_decode_varint
+                0x08023094       0xcc ./Core/BASE/Src/BSP/pb_decode.o
+                0x08023094                pb_decode_varint
+ .text.pb_skip_varint
+                0x08023160       0x38 ./Core/BASE/Src/BSP/pb_decode.o
+ .text.pb_skip_string
+                0x08023198       0x3a ./Core/BASE/Src/BSP/pb_decode.o
+ .text.pb_decode_tag
+                0x080231d2       0x5e ./Core/BASE/Src/BSP/pb_decode.o
+                0x080231d2                pb_decode_tag
+ .text.pb_skip_field
+                0x08023230       0x84 ./Core/BASE/Src/BSP/pb_decode.o
+                0x08023230                pb_skip_field
+ .text.read_raw_value
+                0x080232b4       0xd8 ./Core/BASE/Src/BSP/pb_decode.o
+ .text.pb_make_string_substream
+                0x0802338c       0x74 ./Core/BASE/Src/BSP/pb_decode.o
+                0x0802338c                pb_make_string_substream
+ .text.pb_close_string_substream
+                0x08023400       0x4a ./Core/BASE/Src/BSP/pb_decode.o
+                0x08023400                pb_close_string_substream
+ *fill*         0x0802344a        0x2 
+ .text.decode_basic_field
+                0x0802344c      0x1ec ./Core/BASE/Src/BSP/pb_decode.o
+ .text.decode_static_field
+                0x08023638      0x280 ./Core/BASE/Src/BSP/pb_decode.o
+ .text.decode_pointer_field
+                0x080238b8       0x34 ./Core/BASE/Src/BSP/pb_decode.o
+ .text.decode_callback_field
+                0x080238ec      0x114 ./Core/BASE/Src/BSP/pb_decode.o
+ .text.decode_field
+                0x08023a00       0x7c ./Core/BASE/Src/BSP/pb_decode.o
+ .text.default_extension_decoder
+                0x08023a7c       0x74 ./Core/BASE/Src/BSP/pb_decode.o
+ .text.decode_extension
+                0x08023af0       0x78 ./Core/BASE/Src/BSP/pb_decode.o
+ .text.pb_field_set_to_default
+                0x08023b68      0x182 ./Core/BASE/Src/BSP/pb_decode.o
+ .text.pb_message_set_to_defaults
+                0x08023cea       0xfa ./Core/BASE/Src/BSP/pb_decode.o
+ .text.pb_decode_inner
+                0x08023de4      0x374 ./Core/BASE/Src/BSP/pb_decode.o
+ .text.pb_decode
+                0x08024158       0x26 ./Core/BASE/Src/BSP/pb_decode.o
+                0x08024158                pb_decode
+ .text.pb_decode_bool
+                0x0802417e       0x40 ./Core/BASE/Src/BSP/pb_decode.o
+                0x0802417e                pb_decode_bool
+ .text.pb_decode_svarint
+                0x080241be       0x86 ./Core/BASE/Src/BSP/pb_decode.o
+                0x080241be                pb_decode_svarint
+ .text.pb_decode_fixed32
+                0x08024244       0x38 ./Core/BASE/Src/BSP/pb_decode.o
+                0x08024244                pb_decode_fixed32
+ .text.pb_decode_fixed64
+                0x0802427c       0x3c ./Core/BASE/Src/BSP/pb_decode.o
+                0x0802427c                pb_decode_fixed64
+ .text.pb_dec_bool
+                0x080242b8       0x20 ./Core/BASE/Src/BSP/pb_decode.o
+ .text.pb_dec_varint
+                0x080242d8      0x258 ./Core/BASE/Src/BSP/pb_decode.o
+ .text.pb_dec_bytes
+                0x08024530       0xe8 ./Core/BASE/Src/BSP/pb_decode.o
+ .text.pb_dec_string
+                0x08024618       0xf8 ./Core/BASE/Src/BSP/pb_decode.o
+ .text.pb_dec_submessage
+                0x08024710      0x114 ./Core/BASE/Src/BSP/pb_decode.o
+ .text.pb_dec_fixed_length_bytes
+                0x08024824       0xa8 ./Core/BASE/Src/BSP/pb_decode.o
+ .text.buf_write
+                0x080248cc       0x30 ./Core/BASE/Src/BSP/pb_encode.o
+ .text.pb_ostream_from_buffer
+                0x080248fc       0x40 ./Core/BASE/Src/BSP/pb_encode.o
+                0x080248fc                pb_ostream_from_buffer
+ .text.pb_write
+                0x0802493c       0xa0 ./Core/BASE/Src/BSP/pb_encode.o
+                0x0802493c                pb_write
+ .text.safe_read_bool
+                0x080249dc       0x3c ./Core/BASE/Src/BSP/pb_encode.o
+ .text.encode_array
+                0x08024a18      0x2a8 ./Core/BASE/Src/BSP/pb_encode.o
+ .text.pb_check_proto3_default_value
+                0x08024cc0      0x23c ./Core/BASE/Src/BSP/pb_encode.o
+ .text.encode_basic_field
+                0x08024efc       0xe8 ./Core/BASE/Src/BSP/pb_encode.o
+ .text.encode_callback_field
+                0x08024fe4       0x54 ./Core/BASE/Src/BSP/pb_encode.o
+ .text.encode_field
+                0x08025038       0xe8 ./Core/BASE/Src/BSP/pb_encode.o
+ .text.default_extension_encoder
+                0x08025120       0x54 ./Core/BASE/Src/BSP/pb_encode.o
+ .text.encode_extension_field
+                0x08025174       0x62 ./Core/BASE/Src/BSP/pb_encode.o
+ .text.pb_encode
+                0x080251d6       0x88 ./Core/BASE/Src/BSP/pb_encode.o
+                0x080251d6                pb_encode
+ .text.pb_encode_varint_32
+                0x0802525e       0xd4 ./Core/BASE/Src/BSP/pb_encode.o
+ .text.pb_encode_varint
+                0x08025332       0x56 ./Core/BASE/Src/BSP/pb_encode.o
+                0x08025332                pb_encode_varint
+ .text.pb_encode_svarint
+                0x08025388       0x74 ./Core/BASE/Src/BSP/pb_encode.o
+                0x08025388                pb_encode_svarint
+ .text.pb_encode_fixed32
+                0x080253fc       0x1e ./Core/BASE/Src/BSP/pb_encode.o
+                0x080253fc                pb_encode_fixed32
+ .text.pb_encode_fixed64
+                0x0802541a       0x1e ./Core/BASE/Src/BSP/pb_encode.o
+                0x0802541a                pb_encode_fixed64
+ .text.pb_encode_tag
+                0x08025438       0x52 ./Core/BASE/Src/BSP/pb_encode.o
+                0x08025438                pb_encode_tag
+ *fill*         0x0802548a        0x2 
+ .text.pb_encode_tag_for_field
+                0x0802548c       0x9c ./Core/BASE/Src/BSP/pb_encode.o
+                0x0802548c                pb_encode_tag_for_field
+ .text.pb_encode_string
+                0x08025528       0x42 ./Core/BASE/Src/BSP/pb_encode.o
+                0x08025528                pb_encode_string
+ *fill*         0x0802556a        0x2 
+ .text.pb_encode_submessage
+                0x0802556c      0x11c ./Core/BASE/Src/BSP/pb_encode.o
+                0x0802556c                pb_encode_submessage
+ .text.pb_enc_bool
+                0x08025688       0x34 ./Core/BASE/Src/BSP/pb_encode.o
+ .text.pb_enc_varint
+                0x080256bc      0x184 ./Core/BASE/Src/BSP/pb_encode.o
+ .text.pb_enc_fixed
+                0x08025840       0x5c ./Core/BASE/Src/BSP/pb_encode.o
+ .text.pb_enc_bytes
+                0x0802589c       0x7c ./Core/BASE/Src/BSP/pb_encode.o
+ .text.pb_enc_string
+                0x08025918       0xbc ./Core/BASE/Src/BSP/pb_encode.o
+ .text.pb_enc_submessage
+                0x080259d4       0x8c ./Core/BASE/Src/BSP/pb_encode.o
+ .text.pb_enc_fixed_length_bytes
+                0x08025a60       0x24 ./Core/BASE/Src/BSP/pb_encode.o
+ .text.DLT_RB_Receive_GetNextMessageAddress
+                0x08025a84       0x80 ./Core/BASE/Src/BSP/DLT/DLTuc.o
+ .text.DLT_RB_Receive_Read
+                0x08025b04       0x90 ./Core/BASE/Src/BSP/DLT/DLTuc.o
+ .text.DLT_RB_TransmitRead
+                0x08025b94       0x8c ./Core/BASE/Src/BSP/DLT/DLTuc.o
+ .text.DLT_RB_GetNextWriteIndex
+                0x08025c20       0x6c ./Core/BASE/Src/BSP/DLT/DLTuc.o
+ .text.PrepareDltHeader
+                0x08025c8c      0x190 ./Core/BASE/Src/BSP/DLT/DLTuc.o
+ .text.DLTuc_RawDataReceiveDone
+                0x08025e1c      0x2b0 ./Core/BASE/Src/BSP/DLT/DLTuc.o
+                0x08025e1c                DLTuc_RawDataReceiveDone
+ .text.DLTuc_RegisterInjectionDataReceivedCb
+                0x080260cc       0x20 ./Core/BASE/Src/BSP/DLT/DLTuc.o
+                0x080260cc                DLTuc_RegisterInjectionDataReceivedCb
+ .text.DLTuc_RegisterReceiveSerialDataFunction
+                0x080260ec       0x30 ./Core/BASE/Src/BSP/DLT/DLTuc.o
+                0x080260ec                DLTuc_RegisterReceiveSerialDataFunction
+ .text.DLTuc_RegisterTransmitSerialDataFunction
+                0x0802611c       0x64 ./Core/BASE/Src/BSP/DLT/DLTuc.o
+                0x0802611c                DLTuc_RegisterTransmitSerialDataFunction
+ .text.DLTuc_MessageTransmitDone
+                0x08026180       0xb4 ./Core/BASE/Src/BSP/DLT/DLTuc.o
+                0x08026180                DLTuc_MessageTransmitDone
+ .text.DLTuc_LogOutVarArgs
+                0x08026234      0x138 ./Core/BASE/Src/BSP/DLT/DLTuc.o
+                0x08026234                DLTuc_LogOutVarArgs
+ .text.DLTuc_RegisterGetTimeStampMsCallback
+                0x0802636c       0x20 ./Core/BASE/Src/BSP/DLT/DLTuc.o
+                0x0802636c                DLTuc_RegisterGetTimeStampMsCallback
+ .text.blast_control_intialize
+                0x0802638c       0x20 ./Core/BASE/Src/MSP/msp_Blast_Machine.o
+                0x0802638c                blast_control_intialize
+ .text.Blast_Machine_Control_Fun
+                0x080263ac       0x58 ./Core/BASE/Src/MSP/msp_Blast_Machine.o
+                0x080263ac                Blast_Machine_Control_Fun
+ .text.BlastMachineEncodeHandle
+                0x08026404       0x6c ./Core/BASE/Src/MSP/msp_Blast_Machine.o
+                0x08026404                BlastMachineEncodeHandle
+ .text.Blast_Machine_Open_Fun
+                0x08026470      0x150 ./Core/BASE/Src/MSP/msp_Blast_Machine.o
+                0x08026470                Blast_Machine_Open_Fun
+ .text.Blast_Machine_Close_Fun
+                0x080265c0      0x150 ./Core/BASE/Src/MSP/msp_Blast_Machine.o
+                0x080265c0                Blast_Machine_Close_Fun
+ .text.code_to_str
+                0x08026710       0x80 ./Core/BASE/Src/MSP/msp_Blast_Machine.o
+ .text.str_to_bin
+                0x08026790       0xd2 ./Core/BASE/Src/MSP/msp_Blast_Machine.o
+ .text.bin_to_hex
+                0x08026862      0x18c ./Core/BASE/Src/MSP/msp_Blast_Machine.o
+ .text.hex_to_bytes
+                0x080269ee       0x94 ./Core/BASE/Src/MSP/msp_Blast_Machine.o
+ *fill*         0x08026a82        0x2 
+ .text.encode_to_arrays
+                0x08026a84      0x228 ./Core/BASE/Src/MSP/msp_Blast_Machine.o
+                0x08026a84                encode_to_arrays
+ .text.CMCU_sensor_intialize
+                0x08026cac       0xc4 ./Core/BASE/Src/MSP/msp_CMCUU.o
+                0x08026cac                CMCU_sensor_intialize
+ .text.GF_CMCU_Inquiry
+                0x08026d70       0x44 ./Core/BASE/Src/MSP/msp_CMCUU.o
+                0x08026d70                GF_CMCU_Inquiry
+ .text.decode_cmcu_sensor
+                0x08026db4       0xdc ./Core/BASE/Src/MSP/msp_CMCUU.o
+                0x08026db4                decode_cmcu_sensor
+ .text.CMCU_Command_Comp
+                0x08026e90       0x44 ./Core/BASE/Src/MSP/msp_CMCUU.o
+                0x08026e90                CMCU_Command_Comp
+ .text.GF_MSP_Gyro_MFOG40_Init
+                0x08026ed4       0x60 ./Core/BASE/Src/MSP/msp_MF_Gyroscope.o
+                0x08026ed4                GF_MSP_Gyro_MFOG40_Init
+ .text.GF_Gyro_Unscramble_Callback
+                0x08026f34      0x284 ./Core/BASE/Src/MSP/msp_MF_Gyroscope.o
+                0x08026f34                GF_Gyro_Unscramble_Callback
+ .text.Gyro_Command_Comp
+                0x080271b8      0x168 ./Core/BASE/Src/MSP/msp_MF_Gyroscope.o
+                0x080271b8                Gyro_Command_Comp
+ .text.decode_MK32Data
+                0x08027320       0x5c ./Core/BASE/Src/MSP/msp_MK32_1.o
+                0x08027320                decode_MK32Data
+ *fill*         0x0802737c        0x4 
+ .text.Sbus_Data_Count
+                0x08027380      0x370 ./Core/BASE/Src/MSP/msp_MK32_1.o
+                0x08027380                Sbus_Data_Count
+ .text.MK32_Sbus_UART_Handler_intialize
+                0x080276f0       0xa0 ./Core/BASE/Src/MSP/msp_MK32_1.o
+                0x080276f0                MK32_Sbus_UART_Handler_intialize
+ .text.Speedl_PID
+                0x08027790       0xec ./Core/BASE/Src/MSP/msp_PID.o
+                0x08027790                Speedl_PID
+ .text.GF_MSP_PID_Now_Der_adj_Com_Horizon
+                0x0802787c      0x49c ./Core/BASE/Src/MSP/msp_PID.o
+                0x0802787c                GF_MSP_PID_Now_Der_adj_Com_Horizon
+ .text.TL720D_intialize
+                0x08027d18       0xb4 ./Core/BASE/Src/MSP/msp_TL720D.o
+                0x08027d18                TL720D_intialize
+ .text.decode_TL720D
+                0x08027dcc      0x1b8 ./Core/BASE/Src/MSP/msp_TL720D.o
+                0x08027dcc                decode_TL720D
+ .text.getDeci  0x08027f84       0xf0 ./Core/BASE/Src/MSP/msp_TL720D.o
+                0x08027f84                getDeci
+ .text.ActivateMotor
+                0x08028074       0x40 ./Core/BASE/Src/MSP/msp_TTMotor_ZQ.o
+                0x08028074                ActivateMotor
+ .text.Enable_NMT
+                0x080280b4       0x44 ./Core/BASE/Src/MSP/msp_TTMotor_ZQ.o
+                0x080280b4                Enable_NMT
+ .text.Configure_Asynchronous_Mode
+                0x080280f8       0x7c ./Core/BASE/Src/MSP/msp_TTMotor_ZQ.o
+                0x080280f8                Configure_Asynchronous_Mode
+ .text.Consumer_Or_microcontroller_Heartbeat
+                0x08028174       0x38 ./Core/BASE/Src/MSP/msp_TTMotor_ZQ.o
+                0x08028174                Consumer_Or_microcontroller_Heartbeat
+ .text.CANSendMessageSDO_ADD_To_SendList
+                0x080281ac       0x66 ./Core/BASE/Src/MSP/msp_TTMotor_ZQ.o
+                0x080281ac                CANSendMessageSDO_ADD_To_SendList
+ .text.Postion_Velcocity_Run_SetParameter
+                0x08028212      0x13e ./Core/BASE/Src/MSP/msp_TTMotor_ZQ.o
+                0x08028212                Postion_Velcocity_Run_SetParameter
+ .text.SpeedModeSetup
+                0x08028350      0x100 ./Core/BASE/Src/MSP/msp_TTMotor_ZQ.o
+                0x08028350                SpeedModeSetup
+ .text.TT_SpeedMode_Set_TargetSpeed
+                0x08028450       0x30 ./Core/BASE/Src/MSP/msp_TTMotor_ZQ.o
+                0x08028450                TT_SpeedMode_Set_TargetSpeed
+ .text.TT_Request_Position
+                0x08028480       0x2e ./Core/BASE/Src/MSP/msp_TTMotor_ZQ.o
+                0x08028480                TT_Request_Position
+ .text.Position_Immediately_Setting
+                0x080284ae       0x80 ./Core/BASE/Src/MSP/msp_TTMotor_ZQ.o
+                0x080284ae                Position_Immediately_Setting
+ .text.Position_Lag_Setting
+                0x0802852e       0x80 ./Core/BASE/Src/MSP/msp_TTMotor_ZQ.o
+                0x0802852e                Position_Lag_Setting
+ .text.TT_Request_Velocity
+                0x080285ae       0x2e ./Core/BASE/Src/MSP/msp_TTMotor_ZQ.o
+                0x080285ae                TT_Request_Velocity
+ .text.TT_Request_Fault
+                0x080285dc       0x2e ./Core/BASE/Src/MSP/msp_TTMotor_ZQ.o
+                0x080285dc                TT_Request_Fault
+ .text.TT_Request_Current
+                0x0802860a       0x2e ./Core/BASE/Src/MSP/msp_TTMotor_ZQ.o
+                0x0802860a                TT_Request_Current
+ .text.TT_Analytic_Fun
+                0x08028638      0x4a8 ./Core/BASE/Src/MSP/msp_TTMotor_ZQ.o
+                0x08028638                TT_Analytic_Fun
+ .text.WH_LTE_7S0_intialize
+                0x08028ae0       0xbc ./Core/BASE/Src/MSP/msp_WH_LTE_7S0.o
+                0x08028ae0                WH_LTE_7S0_intialize
+ .text.UpdateGV
+                0x08028b9c       0xb4 ./Core/BASE/Src/MSP/msp_WH_LTE_7S0.o
+                0x08028b9c                UpdateGV
+ .text.decode_received_data_from_computer
+                0x08028c50       0xb4 ./Core/BASE/Src/MSP/msp_WH_LTE_7S0.o
+                0x08028c50                decode_received_data_from_computer
+ .text.MX_ADC2_Init
+                0x08028d04       0xcc ./Core/Src/adc.o
+                0x08028d04                MX_ADC2_Init
+ .text.HAL_ADC_MspInit
+                0x08028dd0       0xe8 ./Core/Src/adc.o
+                0x08028dd0                HAL_ADC_MspInit
+ .text.MX_DMA_Init
+                0x08028eb8       0xa0 ./Core/Src/dma.o
+                0x08028eb8                MX_DMA_Init
+ .text.MX_ETH_Init
+                0x08028f58       0x98 ./Core/Src/eth.o
+                0x08028f58                MX_ETH_Init
+ .text.HAL_ETH_MspInit
+                0x08028ff0      0x178 ./Core/Src/eth.o
+                0x08028ff0                HAL_ETH_MspInit
+ .text.MX_FDCAN1_Init
+                0x08029168       0xc8 ./Core/Src/fdcan.o
+                0x08029168                MX_FDCAN1_Init
+ .text.MX_FDCAN2_Init
+                0x08029230       0xc8 ./Core/Src/fdcan.o
+                0x08029230                MX_FDCAN2_Init
+ .text.HAL_FDCAN_MspInit
+                0x080292f8      0x1bc ./Core/Src/fdcan.o
+                0x080292f8                HAL_FDCAN_MspInit
+ .text.Fsm_Init
+                0x080294b4       0x14 ./Core/Src/fsm.o
+                0x080294b4                Fsm_Init
+ .text.GF_Dispatch
+                0x080294c8      0x34c ./Core/Src/fsm.o
+                0x080294c8                GF_Dispatch
+ .text.action_perfrom
+                0x08029814       0x6c ./Core/Src/fsm.o
+                0x08029814                action_perfrom
+ .text.Robot_Halt_Mode
+                0x08029880       0x20 ./Core/Src/fsm.o
+                0x08029880                Robot_Halt_Mode
+ .text.Robot_Manual_Operation_Mode
+                0x080298a0       0x18 ./Core/Src/fsm.o
+                0x080298a0                Robot_Manual_Operation_Mode
+ .text.UltraStopReverse
+                0x080298b8       0xc4 ./Core/Src/fsm.o
+                0x080298b8                UltraStopReverse
+ .text.UltraStopReverse_Manually_Backward
+                0x0802997c        0xe ./Core/Src/fsm.o
+                0x0802997c                UltraStopReverse_Manually_Backward
+ *fill*         0x0802998a        0x2 
+ .text.PushRod_Contronl
+                0x0802998c       0x50 ./Core/Src/fsm.o
+                0x0802998c                PushRod_Contronl
+ *fill*         0x080299dc        0x4 
+ .text.Robot_Manual_Operation_Function
+                0x080299e0      0x23c ./Core/Src/fsm.o
+                0x080299e0                Robot_Manual_Operation_Function
+ .text.Robot_Swing_Operation_Function
+                0x08029c1c       0x34 ./Core/Src/fsm.o
+                0x08029c1c                Robot_Swing_Operation_Function
+ .text.Horizontal_Operatin_Main_Func
+                0x08029c50       0xd0 ./Core/Src/fsm.o
+                0x08029c50                Horizontal_Operatin_Main_Func
+ .text.Move_Horizontal_Auto_Sub_Func
+                0x08029d20       0xd8 ./Core/Src/fsm.o
+                0x08029d20                Move_Horizontal_Auto_Sub_Func
+ .text.Change_Road_Down_Left_Right
+                0x08029df8       0x84 ./Core/Src/fsm.o
+                0x08029df8                Change_Road_Down_Left_Right
+ *fill*         0x08029e7c        0x4 
+ .text.Horizontal_Manual_Operation_Func
+                0x08029e80      0x268 ./Core/Src/fsm.o
+                0x08029e80                Horizontal_Manual_Operation_Func
+ .text.Vertical_Operatin_Main_Func_Left
+                0x0802a0e8      0x118 ./Core/Src/fsm.o
+                0x0802a0e8                Vertical_Operatin_Main_Func_Left
+ .text.Vertical_Operatin_Main_Func_Right
+                0x0802a200      0x118 ./Core/Src/fsm.o
+                0x0802a200                Vertical_Operatin_Main_Func_Right
+ .text.Move_Vertical_Manual_Sub_Func_Forward
+                0x0802a318       0xac ./Core/Src/fsm.o
+                0x0802a318                Move_Vertical_Manual_Sub_Func_Forward
+ *fill*         0x0802a3c4        0x4 
+ .text.Move_Vertical_Manual_Sub_Func_Backward
+                0x0802a3c8       0xac ./Core/Src/fsm.o
+                0x0802a3c8                Move_Vertical_Manual_Sub_Func_Backward
+ .text.Move_Vertical_Auto_Sub_Func
+                0x0802a474       0xd8 ./Core/Src/fsm.o
+                0x0802a474                Move_Vertical_Auto_Sub_Func
+ .text.Plane_Operatin_Main_Func
+                0x0802a54c       0xd4 ./Core/Src/fsm.o
+                0x0802a54c                Plane_Operatin_Main_Func
+ .text.Move_Plane_Auto_Sub_Func
+                0x0802a620       0xb4 ./Core/Src/fsm.o
+                0x0802a620                Move_Plane_Auto_Sub_Func
+ .text.Plane_Angle_Judge
+                0x0802a6d4       0x24 ./Core/Src/fsm.o
+                0x0802a6d4                Plane_Angle_Judge
+ .text.Region_Automated_Task_Func_Alternately_Plane
+                0x0802a6f8      0x2d8 ./Core/Src/fsm.o
+                0x0802a6f8                Region_Automated_Task_Func_Alternately_Plane
+ .text.Region_Automated_Task_Func_Alternately_Horizontal
+                0x0802a9d0      0x2c0 ./Core/Src/fsm.o
+                0x0802a9d0                Region_Automated_Task_Func_Alternately_Horizontal
+ .text.Vertical_Manual_Operation_Func
+                0x0802ac90      0x258 ./Core/Src/fsm.o
+                0x0802ac90                Vertical_Manual_Operation_Func
+ .text.Plane_Manual_Operation_Func
+                0x0802aee8      0x24c ./Core/Src/fsm.o
+                0x0802aee8                Plane_Manual_Operation_Func
+ .text.Move_Plane_Manual_Sub_Func_Fordwards
+                0x0802b134       0x68 ./Core/Src/fsm.o
+                0x0802b134                Move_Plane_Manual_Sub_Func_Fordwards
+ .text.Move_Plane_Manual_Sub_Func_Backwards
+                0x0802b19c       0x68 ./Core/Src/fsm.o
+                0x0802b19c                Move_Plane_Manual_Sub_Func_Backwards
+ *fill*         0x0802b204        0x4 
+ .text.Plane_X_Backward_Time_Calculation
+                0x0802b208       0x48 ./Core/Src/fsm.o
+                0x0802b208                Plane_X_Backward_Time_Calculation
+ .text.Plane_X_Backward_Time_Calculation_Continuous
+                0x0802b250       0x60 ./Core/Src/fsm.o
+                0x0802b250                Plane_X_Backward_Time_Calculation_Continuous
+ .text.Horizontal_X_Backward_Num_Calculation
+                0x0802b2b0       0x48 ./Core/Src/fsm.o
+                0x0802b2b0                Horizontal_X_Backward_Num_Calculation
+ .text.Horizontal_X_Backward_Time_Calculation_Continuous
+                0x0802b2f8       0x60 ./Core/Src/fsm.o
+                0x0802b2f8                Horizontal_X_Backward_Time_Calculation_Continuous
+ .text.Plane_Y_Lane_Change_Time_Calculation
+                0x0802b358       0x44 ./Core/Src/fsm.o
+                0x0802b358                Plane_Y_Lane_Change_Time_Calculation
+ .text.Horizontal_Y_Lane_Change_Time_Calculation
+                0x0802b39c       0x44 ./Core/Src/fsm.o
+                0x0802b39c                Horizontal_Y_Lane_Change_Time_Calculation
+ .text.Plane_Change_Road_Backward_Num_Calculation
+                0x0802b3e0       0x34 ./Core/Src/fsm.o
+                0x0802b3e0                Plane_Change_Road_Backward_Num_Calculation
+ *fill*         0x0802b414        0x4 
+ .text.Plane_Change_Road_Backward_Time_Calculation_Continuous
+                0x0802b418       0x68 ./Core/Src/fsm.o
+                0x0802b418                Plane_Change_Road_Backward_Time_Calculation_Continuous
+ .text.Horizontal_Change_Road_Backward_Num_Calculation
+                0x0802b480       0x34 ./Core/Src/fsm.o
+                0x0802b480                Horizontal_Change_Road_Backward_Num_Calculation
+ *fill*         0x0802b4b4        0x4 
+ .text.Horizontal_Change_Road_Backward_Time_Calculation_Continuous
+                0x0802b4b8       0x68 ./Core/Src/fsm.o
+                0x0802b4b8                Horizontal_Change_Road_Backward_Time_Calculation_Continuous
+ .text.Move_Horizontal_Manual_Sub_Func_Forwards
+                0x0802b520       0x94 ./Core/Src/fsm.o
+                0x0802b520                Move_Horizontal_Manual_Sub_Func_Forwards
+ .text.Move_Horizontal_Manual_Sub_Func_Backwards
+                0x0802b5b4       0x94 ./Core/Src/fsm.o
+                0x0802b5b4                Move_Horizontal_Manual_Sub_Func_Backwards
+ .text.Horiz_Angle_Judge
+                0x0802b648      0x1ec ./Core/Src/fsm.o
+                0x0802b648                Horiz_Angle_Judge
+ *fill*         0x0802b834        0x4 
+ .text.Horiz_Angle_Judge_4_Direction
+                0x0802b838      0x328 ./Core/Src/fsm.o
+                0x0802b838                Horiz_Angle_Judge_4_Direction
+ .text.Horiz_Angle_Judge_Region
+                0x0802bb60      0x11c ./Core/Src/fsm.o
+                0x0802bb60                Horiz_Angle_Judge_Region
+ *fill*         0x0802bc7c        0x4 
+ .text.Move_Horizontal_Vertical_Task_Forwards_Do_Forwards
+                0x0802bc80       0xa8 ./Core/Src/fsm.o
+                0x0802bc80                Move_Horizontal_Vertical_Task_Forwards_Do_Forwards
+ .text.Move_Horizontal_Task_Change_Road_Backwards_Do
+                0x0802bd28       0xac ./Core/Src/fsm.o
+                0x0802bd28                Move_Horizontal_Task_Change_Road_Backwards_Do
+ .text.Move_Speed_Define
+                0x0802bdd4       0x5c ./Core/Src/fsm.o
+                0x0802bdd4                Move_Speed_Define
+ .text.Robot_Posture_Adjus_Gravity
+                0x0802be30      0x19c ./Core/Src/fsm.o
+                0x0802be30                Robot_Posture_Adjus_Gravity
+ *fill*         0x0802bfcc        0x4 
+ .text.Robot_Posture_Adjus_Plane
+                0x0802bfd0      0x190 ./Core/Src/fsm.o
+                0x0802bfd0                Robot_Posture_Adjus_Plane
+ .text.Vertical_Angle_Judge
+                0x0802c160       0x60 ./Core/Src/fsm.o
+                0x0802c160                Vertical_Angle_Judge
+ .text.Vertical_Angle_Judge_Uptata_1
+                0x0802c1c0       0x60 ./Core/Src/fsm.o
+                0x0802c1c0                Vertical_Angle_Judge_Uptata_1
+ .text.Change_Road_Down_Up_Right_To_Left
+                0x0802c220      0x138 ./Core/Src/fsm.o
+                0x0802c220                Change_Road_Down_Up_Right_To_Left
+ .text.Change_Road_Down_Up_Left_To_Right
+                0x0802c358      0x138 ./Core/Src/fsm.o
+                0x0802c358                Change_Road_Down_Up_Left_To_Right
+ .text.Change_Road_Plane_Continuous_FanDi_Left
+                0x0802c490      0x244 ./Core/Src/fsm.o
+                0x0802c490                Change_Road_Plane_Continuous_FanDi_Left
+ *fill*         0x0802c6d4        0x4 
+ .text.Change_Road_Plane_Continuous_FanDi_Right
+                0x0802c6d8      0x244 ./Core/Src/fsm.o
+                0x0802c6d8                Change_Road_Plane_Continuous_FanDi_Right
+ .text.Move_Plane_Task_Fordwards_Do_Update
+                0x0802c91c       0x94 ./Core/Src/fsm.o
+                0x0802c91c                Move_Plane_Task_Fordwards_Do_Update
+ .text.Move_Horizontal_Vertical_Task_Backwards_Do_Backward
+                0x0802c9b0       0xa8 ./Core/Src/fsm.o
+                0x0802c9b0                Move_Horizontal_Vertical_Task_Backwards_Do_Backward
+ .text.Move_Plane_Task_Backwards_Distance_Do_Update
+                0x0802ca58       0x94 ./Core/Src/fsm.o
+                0x0802ca58                Move_Plane_Task_Backwards_Distance_Do_Update
+ .text.Move_Plane_Task_Backwards_Distance_Do_Update_Turn
+                0x0802caec      0x11c ./Core/Src/fsm.o
+                0x0802caec                Move_Plane_Task_Backwards_Distance_Do_Update_Turn
+ .text.Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin
+                0x0802cc08      0x324 ./Core/Src/fsm.o
+                0x0802cc08                Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin
+ .text.Change_Road_Left
+                0x0802cf2c      0x150 ./Core/Src/fsm.o
+                0x0802cf2c                Change_Road_Left
+ .text.Change_Road_Right
+                0x0802d07c      0x150 ./Core/Src/fsm.o
+                0x0802d07c                Change_Road_Right
+ .text.Forwards_State_Do
+                0x0802d1cc       0x40 ./Core/Src/fsm.o
+                0x0802d1cc                Forwards_State_Do
+ .text.Backwards_State_Do
+                0x0802d20c       0x40 ./Core/Src/fsm.o
+                0x0802d20c                Backwards_State_Do
+ .text.TurnLeft_State_Do
+                0x0802d24c       0x54 ./Core/Src/fsm.o
+                0x0802d24c                TurnLeft_State_Do
+ .text.TurnRight_State_Do
+                0x0802d2a0       0x4c ./Core/Src/fsm.o
+                0x0802d2a0                TurnRight_State_Do
+ .text.TurnRight_State_Do_Plane
+                0x0802d2ec       0x54 ./Core/Src/fsm.o
+                0x0802d2ec                TurnRight_State_Do_Plane
+ .text.TurnLeft_State_Do_Plane
+                0x0802d340       0x4c ./Core/Src/fsm.o
+                0x0802d340                TurnLeft_State_Do_Plane
+ .text.Move_Swing_Left_Func_Do
+                0x0802d38c       0x54 ./Core/Src/fsm.o
+                0x0802d38c                Move_Swing_Left_Func_Do
+ .text.Move_Swing_Right_Func_Do
+                0x0802d3e0       0x54 ./Core/Src/fsm.o
+                0x0802d3e0                Move_Swing_Right_Func_Do
+ .text.Move_Swing_Halt_Func_Do
+                0x0802d434       0x2c ./Core/Src/fsm.o
+                0x0802d434                Move_Swing_Halt_Func_Do
+ .text.Plane_Change_Road_Back_Time_Countinus
+                0x0802d460       0x64 ./Core/Src/fsm.o
+                0x0802d460                Plane_Change_Road_Back_Time_Countinus
+ *fill*         0x0802d4c4        0x4 
+ .text.Horizontal_Change_Road_Back_Time_Compute
+                0x0802d4c8       0xa8 ./Core/Src/fsm.o
+                0x0802d4c8                Horizontal_Change_Road_Back_Time_Compute
+ .text.Vertical_Change_Road_Back_Time_Compute
+                0x0802d570       0x60 ./Core/Src/fsm.o
+                0x0802d570                Vertical_Change_Road_Back_Time_Compute
+ .text.Fight_Alternately_Function_Horizontal
+                0x0802d5d0       0x10 ./Core/Src/fsm.o
+                0x0802d5d0                Fight_Alternately_Function_Horizontal
+ .text.Fight_Countinus_Function_Horizontal
+                0x0802d5e0       0x2c ./Core/Src/fsm.o
+                0x0802d5e0                Fight_Countinus_Function_Horizontal
+ .text.Fight_Alternately_Function_Vertical
+                0x0802d60c       0x10 ./Core/Src/fsm.o
+                0x0802d60c                Fight_Alternately_Function_Vertical
+ .text.Fight_Alternately_Function_Plane
+                0x0802d61c       0x10 ./Core/Src/fsm.o
+                0x0802d61c                Fight_Alternately_Function_Plane
+ .text.Fight_Countinus_Function_Plane
+                0x0802d62c       0x2c ./Core/Src/fsm.o
+                0x0802d62c                Fight_Countinus_Function_Plane
+ .text.Swing_Limit_Contrl
+                0x0802d658      0x304 ./Core/Src/fsm.o
+                0x0802d658                Swing_Limit_Contrl
+ *fill*         0x0802d95c        0x4 
+ .text.Back_Para_Compute
+                0x0802d960      0x120 ./Core/Src/fsm.o
+                0x0802d960                Back_Para_Compute
+ .text.Robot_Platform_Back_Contronl_Horizontal
+                0x0802da80      0x200 ./Core/Src/fsm.o
+                0x0802da80                Robot_Platform_Back_Contronl_Horizontal
+ .text.Robot_Platform_Back_Contronl_Vertical
+                0x0802dc80      0x1c8 ./Core/Src/fsm.o
+                0x0802dc80                Robot_Platform_Back_Contronl_Vertical
+ .text.Robot_Platform_Back_Contronl_Plane
+                0x0802de48      0x1c8 ./Core/Src/fsm.o
+                0x0802de48                Robot_Platform_Back_Contronl_Plane
+ .text.Platform_Back_Para_Compute_Horizontal
+                0x0802e010       0xd8 ./Core/Src/fsm.o
+                0x0802e010                Platform_Back_Para_Compute_Horizontal
+ .text.Platform_Back_Para_Compute_Vertical
+                0x0802e0e8       0xd0 ./Core/Src/fsm.o
+                0x0802e0e8                Platform_Back_Para_Compute_Vertical
+ .text.Platform_Back_Para_Compute_Plane
+                0x0802e1b8       0xb8 ./Core/Src/fsm.o
+                0x0802e1b8                Platform_Back_Para_Compute_Plane
+ .text.IV_control_1
+                0x0802e270      0x130 ./Core/Src/fsm.o
+                0x0802e270                IV_control_1
+ .text.PV_Data_Reading
+                0x0802e3a0       0xf0 ./Core/Src/fsm.o
+                0x0802e3a0                PV_Data_Reading
+ .text.Robot_Main_Mode_Jude
+                0x0802e490      0x104 ./Core/Src/fsm.o
+                0x0802e490                Robot_Main_Mode_Jude
+ .text.EmergencyStop_Hardware_Communication_Detection
+                0x0802e594      0x1e0 ./Core/Src/fsm.o
+                0x0802e594                EmergencyStop_Hardware_Communication_Detection
+ .text.Regional_Horizontal_Automatic_Functionc
+                0x0802e774       0xdc ./Core/Src/fsm.o
+                0x0802e774                Regional_Horizontal_Automatic_Functionc
+ .text.Regional_Plane_Automatic_Functionc
+                0x0802e850       0xd8 ./Core/Src/fsm.o
+                0x0802e850                Regional_Plane_Automatic_Functionc
+ .text.Region_Automated_Task_Func_Continuous_Plane_Uptate_1
+                0x0802e928      0x314 ./Core/Src/fsm.o
+                0x0802e928                Region_Automated_Task_Func_Continuous_Plane_Uptate_1
+ .text.Region_Automated_Task_Func_Continuous_Horizontal
+                0x0802ec3c      0x2b4 ./Core/Src/fsm.o
+                0x0802ec3c                Region_Automated_Task_Func_Continuous_Horizontal
+ .text.Swing_Mode_Determination
+                0x0802eef0      0x19c ./Core/Src/fsm.o
+                0x0802eef0                Swing_Mode_Determination
+ .text.Pressure_Adaptive_Function_Uptata
+                0x0802f08c      0x120 ./Core/Src/fsm.o
+                0x0802f08c                Pressure_Adaptive_Function_Uptata
+ .text.MX_GPIO_Init
+                0x0802f1ac      0x240 ./Core/Src/gpio.o
+                0x0802f1ac                MX_GPIO_Init
+ .text.MX_I2C4_Init
+                0x0802f3ec       0x80 ./Core/Src/i2c.o
+                0x0802f3ec                MX_I2C4_Init
+ .text.HAL_I2C_MspInit
+                0x0802f46c       0xf4 ./Core/Src/i2c.o
+                0x0802f46c                HAL_I2C_MspInit
+ .text.main     0x0802f560      0x160 ./Core/Src/main.o
+                0x0802f560                main
+ .text.SystemClock_Config
+                0x0802f6c0       0xf8 ./Core/Src/main.o
+                0x0802f6c0                SystemClock_Config
+ .text.CV_GV_Init
+                0x0802f7b8      0x130 ./Core/Src/main.o
+                0x0802f7b8                CV_GV_Init
+ .text.GF_Robot_Init
+                0x0802f8e8      0x104 ./Core/Src/main.o
+                0x0802f8e8                GF_Robot_Init
+ .text.MPU_Config
+                0x0802f9ec       0x9c ./Core/Src/main.o
+ .text.Error_Handler
+                0x0802fa88       0x6c ./Core/Src/main.o
+                0x0802fa88                Error_Handler
+ .text.Motor_Controller_intialize
+                0x0802faf4       0x80 ./Core/Src/motors.o
+                0x0802faf4                Motor_Controller_intialize
+ .text.Motor_Controller_intialize_CAN2
+                0x0802fb74       0x68 ./Core/Src/motors.o
+                0x0802fb74                Motor_Controller_intialize_CAN2
+ .text.MotorCommandsLoop
+                0x0802fbdc      0x1d0 ./Core/Src/motors.o
+                0x0802fbdc                MotorCommandsLoop
+ .text.MotorCommandsLoop_2_Position
+                0x0802fdac       0xf0 ./Core/Src/motors.o
+                0x0802fdac                MotorCommandsLoop_2_Position
+ .text.Roughening_MotorDecodeCAN
+                0x0802fe9c       0x98 ./Core/Src/motors.o
+                0x0802fe9c                Roughening_MotorDecodeCAN
+ .text.MX_QUADSPI_Init
+                0x0802ff34       0x58 ./Core/Src/quadspi.o
+                0x0802ff34                MX_QUADSPI_Init
+ .text.HAL_QSPI_MspInit
+                0x0802ff8c      0x17c ./Core/Src/quadspi.o
+                0x0802ff8c                HAL_QSPI_MspInit
+ .text.Move_PushRod_Halt_Func_Do
+                0x08030108       0x18 ./Core/Src/robot_state.o
+                0x08030108                Move_PushRod_Halt_Func_Do
+ .text.Move_PushRod_Up_Func_Do
+                0x08030120       0x18 ./Core/Src/robot_state.o
+                0x08030120                Move_PushRod_Up_Func_Do
+ .text.Move_PushRod_Down_Func_Do
+                0x08030138       0x18 ./Core/Src/robot_state.o
+                0x08030138                Move_PushRod_Down_Func_Do
+ .text.Move_PushRod_Halt_Func_Do_1
+                0x08030150       0x18 ./Core/Src/robot_state.o
+                0x08030150                Move_PushRod_Halt_Func_Do_1
+ .text.HALT_State_Do
+                0x08030168       0x20 ./Core/Src/robot_state.o
+                0x08030168                HALT_State_Do
+ .text.HAL_MspInit
+                0x08030188       0x34 ./Core/Src/stm32h7xx_hal_msp.o
+                0x08030188                HAL_MspInit
+ .text.NMI_Handler
+                0x080301bc        0xc ./Core/Src/stm32h7xx_it.o
+                0x080301bc                NMI_Handler
+ .text.HardFault_Handler
+                0x080301c8        0x8 ./Core/Src/stm32h7xx_it.o
+                0x080301c8                HardFault_Handler
+ .text.MemManage_Handler
+                0x080301d0        0x8 ./Core/Src/stm32h7xx_it.o
+                0x080301d0                MemManage_Handler
+ .text.BusFault_Handler
+                0x080301d8        0x8 ./Core/Src/stm32h7xx_it.o
+                0x080301d8                BusFault_Handler
+ .text.UsageFault_Handler
+                0x080301e0        0x8 ./Core/Src/stm32h7xx_it.o
+                0x080301e0                UsageFault_Handler
+ .text.SVC_Handler
+                0x080301e8        0xe ./Core/Src/stm32h7xx_it.o
+                0x080301e8                SVC_Handler
+ .text.DebugMon_Handler
+                0x080301f6        0xe ./Core/Src/stm32h7xx_it.o
+                0x080301f6                DebugMon_Handler
+ .text.PendSV_Handler
+                0x08030204        0xe ./Core/Src/stm32h7xx_it.o
+                0x08030204                PendSV_Handler
+ .text.SysTick_Handler
+                0x08030212        0xc ./Core/Src/stm32h7xx_it.o
+                0x08030212                SysTick_Handler
+ *fill*         0x0803021e        0x2 
+ .text.DMA1_Stream0_IRQHandler
+                0x08030220       0x14 ./Core/Src/stm32h7xx_it.o
+                0x08030220                DMA1_Stream0_IRQHandler
+ .text.DMA1_Stream1_IRQHandler
+                0x08030234       0x14 ./Core/Src/stm32h7xx_it.o
+                0x08030234                DMA1_Stream1_IRQHandler
+ .text.DMA1_Stream2_IRQHandler
+                0x08030248       0x14 ./Core/Src/stm32h7xx_it.o
+                0x08030248                DMA1_Stream2_IRQHandler
+ .text.DMA1_Stream3_IRQHandler
+                0x0803025c       0x14 ./Core/Src/stm32h7xx_it.o
+                0x0803025c                DMA1_Stream3_IRQHandler
+ .text.DMA1_Stream5_IRQHandler
+                0x08030270       0x14 ./Core/Src/stm32h7xx_it.o
+                0x08030270                DMA1_Stream5_IRQHandler
+ .text.DMA1_Stream6_IRQHandler
+                0x08030284       0x14 ./Core/Src/stm32h7xx_it.o
+                0x08030284                DMA1_Stream6_IRQHandler
+ .text.FDCAN1_IT0_IRQHandler
+                0x08030298       0x14 ./Core/Src/stm32h7xx_it.o
+                0x08030298                FDCAN1_IT0_IRQHandler
+ .text.FDCAN2_IT0_IRQHandler
+                0x080302ac       0x14 ./Core/Src/stm32h7xx_it.o
+                0x080302ac                FDCAN2_IT0_IRQHandler
+ .text.TIM1_UP_IRQHandler
+                0x080302c0       0x14 ./Core/Src/stm32h7xx_it.o
+                0x080302c0                TIM1_UP_IRQHandler
+ .text.USART1_IRQHandler
+                0x080302d4       0x14 ./Core/Src/stm32h7xx_it.o
+                0x080302d4                USART1_IRQHandler
+ .text.USART2_IRQHandler
+                0x080302e8       0x14 ./Core/Src/stm32h7xx_it.o
+                0x080302e8                USART2_IRQHandler
+ .text.USART3_IRQHandler
+                0x080302fc       0x14 ./Core/Src/stm32h7xx_it.o
+                0x080302fc                USART3_IRQHandler
+ .text.TIM8_UP_TIM13_IRQHandler
+                0x08030310       0x14 ./Core/Src/stm32h7xx_it.o
+                0x08030310                TIM8_UP_TIM13_IRQHandler
+ .text.DMA1_Stream7_IRQHandler
+                0x08030324       0x14 ./Core/Src/stm32h7xx_it.o
+                0x08030324                DMA1_Stream7_IRQHandler
+ .text.UART4_IRQHandler
+                0x08030338       0x14 ./Core/Src/stm32h7xx_it.o
+                0x08030338                UART4_IRQHandler
+ .text.UART5_IRQHandler
+                0x0803034c       0x14 ./Core/Src/stm32h7xx_it.o
+                0x0803034c                UART5_IRQHandler
+ .text.ETH_IRQHandler
+                0x08030360       0x14 ./Core/Src/stm32h7xx_it.o
+                0x08030360                ETH_IRQHandler
+ .text.ETH_WKUP_IRQHandler
+                0x08030374       0x14 ./Core/Src/stm32h7xx_it.o
+                0x08030374                ETH_WKUP_IRQHandler
+ .text.USART6_IRQHandler
+                0x08030388       0x14 ./Core/Src/stm32h7xx_it.o
+                0x08030388                USART6_IRQHandler
+ .text.UART7_IRQHandler
+                0x0803039c       0x14 ./Core/Src/stm32h7xx_it.o
+                0x0803039c                UART7_IRQHandler
+ .text.QUADSPI_IRQHandler
+                0x080303b0       0x14 ./Core/Src/stm32h7xx_it.o
+                0x080303b0                QUADSPI_IRQHandler
+ .text.I2C4_EV_IRQHandler
+                0x080303c4       0x14 ./Core/Src/stm32h7xx_it.o
+                0x080303c4                I2C4_EV_IRQHandler
+ .text.I2C4_ER_IRQHandler
+                0x080303d8       0x14 ./Core/Src/stm32h7xx_it.o
+                0x080303d8                I2C4_ER_IRQHandler
+ .text.LPUART1_IRQHandler
+                0x080303ec       0x14 ./Core/Src/stm32h7xx_it.o
+                0x080303ec                LPUART1_IRQHandler
+ .text._sbrk    0x08030400       0x6c ./Core/Src/sysmem.o
+                0x08030400                _sbrk
+ .text.SystemInit
+                0x0803046c      0x11c ./Core/Src/system_stm32h7xx.o
+                0x0803046c                SystemInit
+ .text.MX_TIM1_Init
+                0x08030588       0xa8 ./Core/Src/tim.o
+                0x08030588                MX_TIM1_Init
+ .text.MX_TIM8_Init
+                0x08030630       0xa8 ./Core/Src/tim.o
+                0x08030630                MX_TIM8_Init
+ .text.HAL_TIM_Base_MspInit
+                0x080306d8       0x90 ./Core/Src/tim.o
+                0x080306d8                HAL_TIM_Base_MspInit
+ .text.MX_LPUART1_UART_Init
+                0x08030768       0xa8 ./Core/Src/usart.o
+                0x08030768                MX_LPUART1_UART_Init
+ .text.MX_UART4_Init
+                0x08030810       0x98 ./Core/Src/usart.o
+                0x08030810                MX_UART4_Init
+ .text.MX_UART5_Init
+                0x080308a8       0xb0 ./Core/Src/usart.o
+                0x080308a8                MX_UART5_Init
+ .text.MX_UART7_Init
+                0x08030958       0xa8 ./Core/Src/usart.o
+                0x08030958                MX_UART7_Init
+ .text.MX_USART1_UART_Init
+                0x08030a00       0xa8 ./Core/Src/usart.o
+                0x08030a00                MX_USART1_UART_Init
+ .text.MX_USART2_UART_Init
+                0x08030aa8       0xa8 ./Core/Src/usart.o
+                0x08030aa8                MX_USART2_UART_Init
+ .text.MX_USART3_UART_Init
+                0x08030b50       0xac ./Core/Src/usart.o
+                0x08030b50                MX_USART3_UART_Init
+ .text.MX_USART6_UART_Init
+                0x08030bfc       0xa0 ./Core/Src/usart.o
+                0x08030bfc                MX_USART6_UART_Init
+ .text.HAL_UART_MspInit
+                0x08030c9c      0xb34 ./Core/Src/usart.o
+                0x08030c9c                HAL_UART_MspInit
+ .text.Reset_Handler
+                0x080317d0       0x50 ./Core/Startup/startup_stm32h743vgtx.o
+                0x080317d0                Reset_Handler
+ .text.Default_Handler
+                0x08031820        0x2 ./Core/Startup/startup_stm32h743vgtx.o
+                0x08031820                RTC_Alarm_IRQHandler
+                0x08031820                EXTI2_IRQHandler
+                0x08031820                TIM8_CC_IRQHandler
+                0x08031820                HRTIM1_Master_IRQHandler
+                0x08031820                UART8_IRQHandler
+                0x08031820                SPI4_IRQHandler
+                0x08031820                TIM1_CC_IRQHandler
+                0x08031820                BDMA_Channel6_IRQHandler
+                0x08031820                DMA2_Stream5_IRQHandler
+                0x08031820                HRTIM1_FLT_IRQHandler
+                0x08031820                JPEG_IRQHandler
+                0x08031820                BDMA_Channel1_IRQHandler
+                0x08031820                HRTIM1_TIMD_IRQHandler
+                0x08031820                TAMP_STAMP_IRQHandler
+                0x08031820                EXTI3_IRQHandler
+                0x08031820                LPTIM4_IRQHandler
+                0x08031820                TIM8_TRG_COM_TIM14_IRQHandler
+                0x08031820                LPTIM2_IRQHandler
+                0x08031820                DFSDM1_FLT1_IRQHandler
+                0x08031820                DMAMUX2_OVR_IRQHandler
+                0x08031820                I2C3_ER_IRQHandler
+                0x08031820                DFSDM1_FLT2_IRQHandler
+                0x08031820                MDMA_IRQHandler
+                0x08031820                LPTIM3_IRQHandler
+                0x08031820                HSEM1_IRQHandler
+                0x08031820                EXTI0_IRQHandler
+                0x08031820                I2C2_EV_IRQHandler
+                0x08031820                FPU_IRQHandler
+                0x08031820                OTG_HS_WKUP_IRQHandler
+                0x08031820                FDCAN1_IT1_IRQHandler
+                0x08031820                LTDC_ER_IRQHandler
+                0x08031820                DMA2_Stream2_IRQHandler
+                0x08031820                HRTIM1_TIME_IRQHandler
+                0x08031820                SPI1_IRQHandler
+                0x08031820                TIM6_DAC_IRQHandler
+                0x08031820                DCMI_IRQHandler
+                0x08031820                HRTIM1_TIMC_IRQHandler
+                0x08031820                DMA2_Stream3_IRQHandler
+                0x08031820                SAI2_IRQHandler
+                0x08031820                DFSDM1_FLT3_IRQHandler
+                0x08031820                TIM17_IRQHandler
+                0x08031820                BDMA_Channel7_IRQHandler
+                0x08031820                LPTIM5_IRQHandler
+                0x08031820                ADC3_IRQHandler
+                0x08031820                DMA2_Stream0_IRQHandler
+                0x08031820                TIM4_IRQHandler
+                0x08031820                BDMA_Channel2_IRQHandler
+                0x08031820                I2C1_EV_IRQHandler
+                0x08031820                DMAMUX1_OVR_IRQHandler
+                0x08031820                TIM16_IRQHandler
+                0x08031820                BDMA_Channel5_IRQHandler
+                0x08031820                TIM3_IRQHandler
+                0x08031820                RCC_IRQHandler
+                0x08031820                TIM8_BRK_TIM12_IRQHandler
+                0x08031820                TIM1_TRG_COM_IRQHandler
+                0x08031820                Default_Handler
+                0x08031820                ECC_IRQHandler
+                0x08031820                CEC_IRQHandler
+                0x08031820                EXTI15_10_IRQHandler
+                0x08031820                BDMA_Channel0_IRQHandler
+                0x08031820                ADC_IRQHandler
+                0x08031820                HRTIM1_TIMA_IRQHandler
+                0x08031820                SPI5_IRQHandler
+                0x08031820                TIM7_IRQHandler
+                0x08031820                SDMMC1_IRQHandler
+                0x08031820                TIM5_IRQHandler
+                0x08031820                DMA2_Stream7_IRQHandler
+                0x08031820                TIM15_IRQHandler
+                0x08031820                PVD_AVD_IRQHandler
+                0x08031820                I2C3_EV_IRQHandler
+                0x08031820                EXTI9_5_IRQHandler
+                0x08031820                RTC_WKUP_IRQHandler
+                0x08031820                LTDC_IRQHandler
+                0x08031820                SAI3_IRQHandler
+                0x08031820                SPDIF_RX_IRQHandler
+                0x08031820                SPI2_IRQHandler
+                0x08031820                OTG_HS_EP1_IN_IRQHandler
+                0x08031820                CRS_IRQHandler
+                0x08031820                EXTI4_IRQHandler
+                0x08031820                RNG_IRQHandler
+                0x08031820                HRTIM1_TIMB_IRQHandler
+                0x08031820                FDCAN2_IT1_IRQHandler
+                0x08031820                BDMA_Channel4_IRQHandler
+                0x08031820                OTG_HS_EP1_OUT_IRQHandler
+                0x08031820                WWDG_IRQHandler
+                0x08031820                SPI6_IRQHandler
+                0x08031820                MDIOS_IRQHandler
+                0x08031820                TIM2_IRQHandler
+                0x08031820                OTG_FS_WKUP_IRQHandler
+                0x08031820                OTG_HS_IRQHandler
+                0x08031820                DMA2D_IRQHandler
+                0x08031820                TIM1_BRK_IRQHandler
+                0x08031820                EXTI1_IRQHandler
+                0x08031820                SDMMC2_IRQHandler
+                0x08031820                OTG_FS_EP1_OUT_IRQHandler
+                0x08031820                BDMA_Channel3_IRQHandler
+                0x08031820                MDIOS_WKUP_IRQHandler
+                0x08031820                DFSDM1_FLT0_IRQHandler
+                0x08031820                SAI4_IRQHandler
+                0x08031820                I2C2_ER_IRQHandler
+                0x08031820                DMA2_Stream1_IRQHandler
+                0x08031820                FLASH_IRQHandler
+                0x08031820                DMA2_Stream4_IRQHandler
+                0x08031820                OTG_FS_IRQHandler
+                0x08031820                SPI3_IRQHandler
+                0x08031820                WAKEUP_PIN_IRQHandler
+                0x08031820                DMA1_Stream4_IRQHandler
+                0x08031820                OTG_FS_EP1_IN_IRQHandler
+                0x08031820                I2C1_ER_IRQHandler
+                0x08031820                FMC_IRQHandler
+                0x08031820                FDCAN_CAL_IRQHandler
+                0x08031820                SWPMI1_IRQHandler
+                0x08031820                COMP1_IRQHandler
+                0x08031820                LPTIM1_IRQHandler
+                0x08031820                DMA2_Stream6_IRQHandler
+                0x08031820                SAI1_IRQHandler
+ *fill*         0x08031822        0x2 
+ .text.HAL_Init
+                0x08031824       0x78 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
+                0x08031824                HAL_Init
+ .text.HAL_InitTick
+                0x0803189c       0x6c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
+                0x0803189c                HAL_InitTick
+ .text.HAL_IncTick
+                0x08031908       0x28 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
+                0x08031908                HAL_IncTick
+ .text.HAL_GetTick
+                0x08031930       0x18 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
+                0x08031930                HAL_GetTick
+ .text.HAL_Delay
+                0x08031948       0x48 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
+                0x08031948                HAL_Delay
+ .text.HAL_GetREVID
+                0x08031990       0x18 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
+                0x08031990                HAL_GetREVID
+ .text.HAL_SYSCFG_ETHInterfaceSelect
+                0x080319a8       0x28 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
+                0x080319a8                HAL_SYSCFG_ETHInterfaceSelect
+ .text.LL_ADC_SetCommonClock
+                0x080319d0       0x26 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.o
+ .text.LL_ADC_SetCommonPathInternalCh
+                0x080319f6       0x26 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.o
+ .text.LL_ADC_GetCommonPathInternalCh
+                0x08031a1c       0x1c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.o
+ .text.LL_ADC_SetOffset
+                0x08031a38       0x40 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.o
+ .text.LL_ADC_SetDataRightShift
+                0x08031a78       0x32 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.o
+ .text.LL_ADC_SetOffsetSignedSaturation
+                0x08031aaa       0x36 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.o
+ .text.LL_ADC_REG_SetSequencerRanks
+                0x08031ae0       0x58 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.o
+ .text.LL_ADC_SetChannelSamplingTime
+                0x08031b38       0x56 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.o
+ *fill*         0x08031b8e        0x2 
+ .text.LL_ADC_SetChannelSingleDiff
+                0x08031b90       0x48 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.o
+ .text.LL_ADC_DisableDeepPowerDown
+                0x08031bd8       0x24 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.o
+ .text.LL_ADC_IsDeepPowerDownEnabled
+                0x08031bfc       0x28 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.o
+ .text.LL_ADC_EnableInternalRegulator
+                0x08031c24       0x28 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.o
+ .text.LL_ADC_IsInternalRegulatorEnabled
+                0x08031c4c       0x28 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.o
+ .text.LL_ADC_IsEnabled
+                0x08031c74       0x26 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.o
+ .text.LL_ADC_REG_IsConversionOngoing
+                0x08031c9a       0x26 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.o
+ .text.LL_ADC_INJ_IsConversionOngoing
+                0x08031cc0       0x26 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.o
+ *fill*         0x08031ce6        0x2 
+ .text.HAL_ADC_Init
+                0x08031ce8      0x344 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.o
+                0x08031ce8                HAL_ADC_Init
+ .text.HAL_ADC_ConfigChannel
+                0x0803202c      0x6b8 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.o
+                0x0803202c                HAL_ADC_ConfigChannel
+ .text.ADC_ConfigureBoostMode
+                0x080326e4      0x218 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.o
+                0x080326e4                ADC_ConfigureBoostMode
+ .text.__NVIC_SetPriorityGrouping
+                0x080328fc       0x48 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
+ .text.__NVIC_GetPriorityGrouping
+                0x08032944       0x1c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
+ .text.__NVIC_EnableIRQ
+                0x08032960       0x3c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
+ .text.__NVIC_SetPriority
+                0x0803299c       0x54 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
+ .text.NVIC_EncodePriority
+                0x080329f0       0x66 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
+ *fill*         0x08032a56        0x2 
+ .text.SysTick_Config
+                0x08032a58       0x44 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
+ .text.HAL_NVIC_SetPriorityGrouping
+                0x08032a9c       0x16 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
+                0x08032a9c                HAL_NVIC_SetPriorityGrouping
+ .text.HAL_NVIC_SetPriority
+                0x08032ab2       0x34 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
+                0x08032ab2                HAL_NVIC_SetPriority
+ .text.HAL_NVIC_EnableIRQ
+                0x08032ae6       0x1c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
+                0x08032ae6                HAL_NVIC_EnableIRQ
+ .text.HAL_SYSTICK_Config
+                0x08032b02       0x18 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
+                0x08032b02                HAL_SYSTICK_Config
+ *fill*         0x08032b1a        0x2 
+ .text.HAL_MPU_Disable
+                0x08032b1c       0x30 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
+                0x08032b1c                HAL_MPU_Disable
+ .text.HAL_MPU_Enable
+                0x08032b4c       0x40 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
+                0x08032b4c                HAL_MPU_Enable
+ .text.HAL_MPU_ConfigRegion
+                0x08032b8c       0x80 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
+                0x08032b8c                HAL_MPU_ConfigRegion
+ .text.HAL_DMA_Init
+                0x08032c0c      0x6b8 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
+                0x08032c0c                HAL_DMA_Init
+ .text.HAL_DMA_Start_IT
+                0x080332c4      0x4d4 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
+                0x080332c4                HAL_DMA_Start_IT
+ .text.HAL_DMA_Abort
+                0x08033798      0x63c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
+                0x08033798                HAL_DMA_Abort
+ .text.HAL_DMA_Abort_IT
+                0x08033dd4      0x48c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
+                0x08033dd4                HAL_DMA_Abort_IT
+ .text.HAL_DMA_IRQHandler
+                0x08034260      0xe54 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
+                0x08034260                HAL_DMA_IRQHandler
+ .text.HAL_DMA_GetState
+                0x080350b4       0x1c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
+                0x080350b4                HAL_DMA_GetState
+ .text.DMA_SetConfig
+                0x080350d0      0x358 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
+ .text.DMA_CalcBaseAndBitshift
+                0x08035428      0x164 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
+ .text.DMA_CheckFifoParam
+                0x0803558c       0xf8 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
+ .text.DMA_CalcDMAMUXChannelBaseAndMask
+                0x08035684      0x134 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
+ .text.DMA_CalcDMAMUXRequestGenBaseAndMask
+                0x080357b8       0xe8 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
+ .text.HAL_ETH_Init
+                0x080358a0      0x1fc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+                0x080358a0                HAL_ETH_Init
+ .text.HAL_ETH_IRQHandler
+                0x08035a9c      0x1e8 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+                0x08035a9c                HAL_ETH_IRQHandler
+ .text.HAL_ETH_TxCpltCallback
+                0x08035c84       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+                0x08035c84                HAL_ETH_TxCpltCallback
+ .text.HAL_ETH_RxCpltCallback
+                0x08035c98       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+                0x08035c98                HAL_ETH_RxCpltCallback
+ .text.HAL_ETH_ErrorCallback
+                0x08035cac       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+                0x08035cac                HAL_ETH_ErrorCallback
+ .text.HAL_ETH_PMTCallback
+                0x08035cc0       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+                0x08035cc0                HAL_ETH_PMTCallback
+ .text.HAL_ETH_EEECallback
+                0x08035cd4       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+                0x08035cd4                HAL_ETH_EEECallback
+ .text.HAL_ETH_WakeUpCallback
+                0x08035ce8       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+                0x08035ce8                HAL_ETH_WakeUpCallback
+ .text.HAL_ETH_SetMDIOClockRange
+                0x08035cfc       0xa0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+                0x08035cfc                HAL_ETH_SetMDIOClockRange
+ .text.ETH_SetMACConfig
+                0x08035d9c      0x238 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+ .text.ETH_SetDMAConfig
+                0x08035fd4      0x10c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+ .text.ETH_MACDMAConfig
+                0x080360e0      0x13a ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+ .text.ETH_DMATxDescListInit
+                0x0803621a       0x92 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+ .text.ETH_DMARxDescListInit
+                0x080362ac       0xba ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
+ *fill*         0x08036366        0x2 
+ .text.HAL_FDCAN_Init
+                0x08036368      0x3bc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+                0x08036368                HAL_FDCAN_Init
+ .text.HAL_FDCAN_Start
+                0x08036724       0x56 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+                0x08036724                HAL_FDCAN_Start
+ .text.HAL_FDCAN_AddMessageToTxFifoQ
+                0x0803677a       0xb6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+                0x0803677a                HAL_FDCAN_AddMessageToTxFifoQ
+ .text.HAL_FDCAN_GetRxMessage
+                0x08036830      0x2d8 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+                0x08036830                HAL_FDCAN_GetRxMessage
+ .text.HAL_FDCAN_ActivateNotification
+                0x08036b08       0xf4 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+                0x08036b08                HAL_FDCAN_ActivateNotification
+ .text.HAL_FDCAN_IRQHandler
+                0x08036bfc      0x498 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+                0x08036bfc                HAL_FDCAN_IRQHandler
+ .text.HAL_FDCAN_ClockCalibrationCallback
+                0x08037094       0x16 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+                0x08037094                HAL_FDCAN_ClockCalibrationCallback
+ .text.HAL_FDCAN_TxEventFifoCallback
+                0x080370aa       0x16 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+                0x080370aa                HAL_FDCAN_TxEventFifoCallback
+ .text.HAL_FDCAN_RxFifo1Callback
+                0x080370c0       0x16 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+                0x080370c0                HAL_FDCAN_RxFifo1Callback
+ .text.HAL_FDCAN_TxFifoEmptyCallback
+                0x080370d6       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+                0x080370d6                HAL_FDCAN_TxFifoEmptyCallback
+ .text.HAL_FDCAN_TxBufferCompleteCallback
+                0x080370ea       0x16 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+                0x080370ea                HAL_FDCAN_TxBufferCompleteCallback
+ .text.HAL_FDCAN_TxBufferAbortCallback
+                0x08037100       0x16 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+                0x08037100                HAL_FDCAN_TxBufferAbortCallback
+ .text.HAL_FDCAN_RxBufferNewMessageCallback
+                0x08037116       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+                0x08037116                HAL_FDCAN_RxBufferNewMessageCallback
+ .text.HAL_FDCAN_TimestampWraparoundCallback
+                0x0803712a       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+                0x0803712a                HAL_FDCAN_TimestampWraparoundCallback
+ .text.HAL_FDCAN_TimeoutOccurredCallback
+                0x0803713e       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+                0x0803713e                HAL_FDCAN_TimeoutOccurredCallback
+ .text.HAL_FDCAN_HighPriorityMessageCallback
+                0x08037152       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+                0x08037152                HAL_FDCAN_HighPriorityMessageCallback
+ .text.HAL_FDCAN_ErrorCallback
+                0x08037166       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+                0x08037166                HAL_FDCAN_ErrorCallback
+ .text.HAL_FDCAN_TT_ScheduleSyncCallback
+                0x0803717a       0x16 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+                0x0803717a                HAL_FDCAN_TT_ScheduleSyncCallback
+ .text.HAL_FDCAN_TT_TimeMarkCallback
+                0x08037190       0x16 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+                0x08037190                HAL_FDCAN_TT_TimeMarkCallback
+ .text.HAL_FDCAN_TT_StopWatchCallback
+                0x080371a6       0x18 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+                0x080371a6                HAL_FDCAN_TT_StopWatchCallback
+ .text.HAL_FDCAN_TT_GlobalTimeCallback
+                0x080371be       0x16 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+                0x080371be                HAL_FDCAN_TT_GlobalTimeCallback
+ .text.FDCAN_CalcultateRamBlockAddresses
+                0x080371d4      0x30c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .text.FDCAN_CopyMessageToRAM
+                0x080374e0       0xfc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
+ .text.HAL_GPIO_Init
+                0x080375dc      0x360 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o
+                0x080375dc                HAL_GPIO_Init
+ .text.HAL_GPIO_WritePin
+                0x0803793c       0x32 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o
+                0x0803793c                HAL_GPIO_WritePin
+ *fill*         0x0803796e        0x2 
+ .text.HAL_I2C_Init
+                0x08037970      0x138 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
+                0x08037970                HAL_I2C_Init
+ .text.HAL_I2C_EV_IRQHandler
+                0x08037aa8       0x34 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
+                0x08037aa8                HAL_I2C_EV_IRQHandler
+ .text.HAL_I2C_ER_IRQHandler
+                0x08037adc       0xb6 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
+                0x08037adc                HAL_I2C_ER_IRQHandler
+ .text.HAL_I2C_SlaveTxCpltCallback
+                0x08037b92       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
+                0x08037b92                HAL_I2C_SlaveTxCpltCallback
+ .text.HAL_I2C_SlaveRxCpltCallback
+                0x08037ba6       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
+                0x08037ba6                HAL_I2C_SlaveRxCpltCallback
+ .text.HAL_I2C_AddrCallback
+                0x08037bba       0x1c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
+                0x08037bba                HAL_I2C_AddrCallback
+ .text.HAL_I2C_ListenCpltCallback
+                0x08037bd6       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
+                0x08037bd6                HAL_I2C_ListenCpltCallback
+ .text.HAL_I2C_ErrorCallback
+                0x08037bea       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
+                0x08037bea                HAL_I2C_ErrorCallback
+ .text.HAL_I2C_AbortCpltCallback
+                0x08037bfe       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
+                0x08037bfe                HAL_I2C_AbortCpltCallback
+ .text.I2C_Slave_ISR_IT
+                0x08037c12      0x1f2 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
+ .text.I2C_ITAddrCplt
+                0x08037e04      0x108 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
+ .text.I2C_ITSlaveSeqCplt
+                0x08037f0c       0xb8 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
+ .text.I2C_ITSlaveCplt
+                0x08037fc4      0x4a8 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
+ .text.I2C_ITListenCplt
+                0x0803846c       0xa8 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
+ .text.I2C_ITError
+                0x08038514      0x1e0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
+ .text.I2C_TreatErrorCallback
+                0x080386f4       0x4e ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
+ .text.I2C_Flush_TXDR
+                0x08038742       0x48 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
+ .text.I2C_DMAAbort
+                0x0803878a       0x3c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
+ .text.I2C_Disable_IRQ
+                0x080387c6       0xbc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
+ .text.HAL_I2CEx_ConfigAnalogFilter
+                0x08038882       0x96 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o
+                0x08038882                HAL_I2CEx_ConfigAnalogFilter
+ .text.HAL_I2CEx_ConfigDigitalFilter
+                0x08038918       0x98 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o
+                0x08038918                HAL_I2CEx_ConfigDigitalFilter
+ .text.HAL_MDMA_Abort_IT
+                0x080389b0       0x4e ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
+                0x080389b0                HAL_MDMA_Abort_IT
+ *fill*         0x080389fe        0x2 
+ .text.HAL_PWREx_ConfigSupply
+                0x08038a00       0x74 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o
+                0x08038a00                HAL_PWREx_ConfigSupply
+ .text.HAL_QSPI_Init
+                0x08038a74       0xe8 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.o
+                0x08038a74                HAL_QSPI_Init
+ .text.HAL_QSPI_IRQHandler
+                0x08038b5c      0x374 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.o
+                0x08038b5c                HAL_QSPI_IRQHandler
+ .text.HAL_QSPI_ErrorCallback
+                0x08038ed0       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.o
+                0x08038ed0                HAL_QSPI_ErrorCallback
+ .text.HAL_QSPI_AbortCpltCallback
+                0x08038ee4       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.o
+                0x08038ee4                HAL_QSPI_AbortCpltCallback
+ .text.HAL_QSPI_CmdCpltCallback
+                0x08038ef8       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.o
+                0x08038ef8                HAL_QSPI_CmdCpltCallback
+ .text.HAL_QSPI_RxCpltCallback
+                0x08038f0c       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.o
+                0x08038f0c                HAL_QSPI_RxCpltCallback
+ .text.HAL_QSPI_TxCpltCallback
+                0x08038f20       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.o
+                0x08038f20                HAL_QSPI_TxCpltCallback
+ .text.HAL_QSPI_FifoThresholdCallback
+                0x08038f34       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.o
+                0x08038f34                HAL_QSPI_FifoThresholdCallback
+ .text.HAL_QSPI_StatusMatchCallback
+                0x08038f48       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.o
+                0x08038f48                HAL_QSPI_StatusMatchCallback
+ .text.HAL_QSPI_TimeOutCallback
+                0x08038f5c       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.o
+                0x08038f5c                HAL_QSPI_TimeOutCallback
+ .text.HAL_QSPI_SetTimeout
+                0x08038f70       0x1c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.o
+                0x08038f70                HAL_QSPI_SetTimeout
+ .text.QSPI_DMAAbortCplt
+                0x08038f8c       0x66 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.o
+ .text.QSPI_WaitFlagStateUntilTimeout
+                0x08038ff2       0x6e ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.o
+ .text.HAL_RCC_OscConfig
+                0x08039060      0x8b4 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
+                0x08039060                HAL_RCC_OscConfig
+ .text.HAL_RCC_ClockConfig
+                0x08039914      0x36c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
+                0x08039914                HAL_RCC_ClockConfig
+ .text.HAL_RCC_EnableCSS
+                0x08039c80       0x20 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
+                0x08039c80                HAL_RCC_EnableCSS
+ .text.HAL_RCC_GetSysClockFreq
+                0x08039ca0      0x2f4 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
+                0x08039ca0                HAL_RCC_GetSysClockFreq
+ .text.HAL_RCC_GetHCLKFreq
+                0x08039f94       0x60 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
+                0x08039f94                HAL_RCC_GetHCLKFreq
+ .text.HAL_RCC_GetPCLK1Freq
+                0x08039ff4       0x2c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
+                0x08039ff4                HAL_RCC_GetPCLK1Freq
+ .text.HAL_RCC_GetPCLK2Freq
+                0x0803a020       0x2c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
+                0x0803a020                HAL_RCC_GetPCLK2Freq
+ .text.HAL_RCC_NMI_IRQHandler
+                0x0803a04c       0x28 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
+                0x0803a04c                HAL_RCC_NMI_IRQHandler
+ .text.HAL_RCC_CSSCallback
+                0x0803a074        0xe ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
+                0x0803a074                HAL_RCC_CSSCallback
+ *fill*         0x0803a082        0x2 
+ .text.HAL_RCCEx_PeriphCLKConfig
+                0x0803a084     0x1414 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
+                0x0803a084                HAL_RCCEx_PeriphCLKConfig
+ .text.HAL_RCCEx_GetPeriphCLKFreq
+                0x0803b498      0xb00 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
+                0x0803b498                HAL_RCCEx_GetPeriphCLKFreq
+ .text.HAL_RCCEx_GetD3PCLK1Freq
+                0x0803bf98       0x2c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
+                0x0803bf98                HAL_RCCEx_GetD3PCLK1Freq
+ .text.HAL_RCCEx_GetPLL2ClockFreq
+                0x0803bfc4      0x2a8 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
+                0x0803bfc4                HAL_RCCEx_GetPLL2ClockFreq
+ .text.HAL_RCCEx_GetPLL3ClockFreq
+                0x0803c26c      0x2a8 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
+                0x0803c26c                HAL_RCCEx_GetPLL3ClockFreq
+ .text.HAL_RCCEx_GetPLL1ClockFreq
+                0x0803c514      0x2a4 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
+                0x0803c514                HAL_RCCEx_GetPLL1ClockFreq
+ .text.RCCEx_PLL2_Config
+                0x0803c7b8      0x164 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
+ .text.RCCEx_PLL3_Config
+                0x0803c91c      0x164 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
+ .text.HAL_TIM_Base_Init
+                0x0803ca80       0xae ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+                0x0803ca80                HAL_TIM_Base_Init
+ *fill*         0x0803cb2e        0x2 
+ .text.HAL_TIM_Base_Start_IT
+                0x0803cb30       0xf0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+                0x0803cb30                HAL_TIM_Base_Start_IT
+ .text.HAL_TIM_IRQHandler
+                0x0803cc20      0x20e ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+                0x0803cc20                HAL_TIM_IRQHandler
+ *fill*         0x0803ce2e        0x2 
+ .text.HAL_TIM_ConfigClockSource
+                0x0803ce30      0x1f0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+                0x0803ce30                HAL_TIM_ConfigClockSource
+ .text.HAL_TIM_OC_DelayElapsedCallback
+                0x0803d020       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+                0x0803d020                HAL_TIM_OC_DelayElapsedCallback
+ .text.HAL_TIM_IC_CaptureCallback
+                0x0803d034       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+                0x0803d034                HAL_TIM_IC_CaptureCallback
+ .text.HAL_TIM_PWM_PulseFinishedCallback
+                0x0803d048       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+                0x0803d048                HAL_TIM_PWM_PulseFinishedCallback
+ .text.HAL_TIM_TriggerCallback
+                0x0803d05c       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+                0x0803d05c                HAL_TIM_TriggerCallback
+ .text.TIM_Base_SetConfig
+                0x0803d070      0x14c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+                0x0803d070                TIM_Base_SetConfig
+ .text.TIM_TI1_ConfigInputStage
+                0x0803d1bc       0x5e ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .text.TIM_TI2_ConfigInputStage
+                0x0803d21a       0x60 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ *fill*         0x0803d27a        0x2 
+ .text.TIM_ITRx_SetConfig
+                0x0803d27c       0x3c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+ .text.TIM_ETR_SetConfig
+                0x0803d2b8       0x40 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
+                0x0803d2b8                TIM_ETR_SetConfig
+ .text.HAL_TIMEx_MasterConfigSynchronization
+                0x0803d2f8      0x11c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+                0x0803d2f8                HAL_TIMEx_MasterConfigSynchronization
+ .text.HAL_TIMEx_CommutCallback
+                0x0803d414       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+                0x0803d414                HAL_TIMEx_CommutCallback
+ .text.HAL_TIMEx_BreakCallback
+                0x0803d428       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+                0x0803d428                HAL_TIMEx_BreakCallback
+ .text.HAL_TIMEx_Break2Callback
+                0x0803d43c       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
+                0x0803d43c                HAL_TIMEx_Break2Callback
+ .text.HAL_UART_Init
+                0x0803d450       0xa0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.o
+                0x0803d450                HAL_UART_Init
+ .text.HAL_UART_Transmit
+                0x0803d4f0      0x11c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.o
+                0x0803d4f0                HAL_UART_Transmit
+ .text.HAL_UART_Receive_IT
+                0x0803d60c       0x98 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.o
+                0x0803d60c                HAL_UART_Receive_IT
+ .text.HAL_UART_Transmit_DMA
+                0x0803d6a4      0x100 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.o
+                0x0803d6a4                HAL_UART_Transmit_DMA
+ .text.HAL_UART_IRQHandler
+                0x0803d7a4      0x774 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.o
+                0x0803d7a4                HAL_UART_IRQHandler
+ .text.HAL_UART_TxHalfCpltCallback
+                0x0803df18       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.o
+                0x0803df18                HAL_UART_TxHalfCpltCallback
+ .text.HAL_UART_ErrorCallback
+                0x0803df2c       0x14 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.o
+                0x0803df2c                HAL_UART_ErrorCallback
+ .text.HAL_UARTEx_RxEventCallback
+                0x0803df40       0x18 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.o
+                0x0803df40                HAL_UARTEx_RxEventCallback
+ .text.UART_SetConfig
+                0x0803df58      0xad0 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.o
+                0x0803df58                UART_SetConfig
+ .text.UART_AdvFeatureConfig
+                0x0803ea28      0x144 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.o
+                0x0803ea28                UART_AdvFeatureConfig
+ .text.UART_CheckIdleState
+                0x0803eb6c      0x154 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.o
+                0x0803eb6c                UART_CheckIdleState
+ .text.UART_WaitOnFlagUntilTimeout
+                0x0803ecc0       0xda ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.o
+                0x0803ecc0                UART_WaitOnFlagUntilTimeout
+ *fill*         0x0803ed9a        0x2 
+ .text.UART_Start_Receive_IT
+                0x0803ed9c      0x244 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.o
+                0x0803ed9c                UART_Start_Receive_IT
+ .text.UART_EndTxTransfer
+                0x0803efe0       0x82 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.o
+ *fill*         0x0803f062        0x2 
+ .text.UART_EndRxTransfer
+                0x0803f064       0xcc ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.o
+ .text.UART_DMATransmitCplt
+                0x0803f130       0x96 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.o
+ .text.UART_DMATxHalfCplt
+                0x0803f1c6       0x1c ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.o
+ .text.UART_DMAError
+                0x0803f1e2       0x80 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.o
+ .text.UART_DMAAbortOnError
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+                0x24000110        0x8 ./Core/Src/fsm.o
+                0x24000110                Press_Dis_Value1
+ .data.can1_sendListPeriod
+                0x24000118        0x4 ./Core/Src/main.o
+                0x24000118                can1_sendListPeriod
+ .data.can1_DispacherPeriod
+                0x2400011c        0x4 ./Core/Src/main.o
+                0x2400011c                can1_DispacherPeriod
+ .data.can2_sendListPeriod
+                0x24000120        0x4 ./Core/Src/main.o
+                0x24000120                can2_sendListPeriod
+ .data.can2_DispacherPeriod
+                0x24000124        0x4 ./Core/Src/main.o
+                0x24000124                can2_DispacherPeriod
+ .data.TT_Motor_Need_To_Activate
+                0x24000128        0x1 ./Core/Src/motors.o
+                0x24000128                TT_Motor_Need_To_Activate
+ .data.TT_Motor_Need_To_Activate_1
+                0x24000129        0x1 ./Core/Src/motors.o
+                0x24000129                TT_Motor_Need_To_Activate_1
+ *fill*         0x2400012a        0x2 
+ .data.SystemCoreClock
+                0x2400012c        0x4 ./Core/Src/system_stm32h7xx.o
+                0x2400012c                SystemCoreClock
+ .data.SystemD2Clock
+                0x24000130        0x4 ./Core/Src/system_stm32h7xx.o
+                0x24000130                SystemD2Clock
+ .data.uwTickPrio
+                0x24000134        0x4 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
+                0x24000134                uwTickPrio
+ .data.uwTickFreq
+                0x24000138        0x1 ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
+                0x24000138                uwTickFreq
+ *fill*         0x24000139        0x3 
+ .data._impure_ptr
+                0x2400013c        0x4 F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-impure.o)
+                0x2400013c                _impure_ptr
+ .data._impure_data
+                0x24000140       0x4c F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-impure.o)
+                0x24000140                _impure_data
+ *(.RamFunc)
+ *(.RamFunc*)
+                0x2400018c                        . = ALIGN (0x4)
+                0x2400018c                        _edata = .
+
+.igot.plt       0x2400018c        0x0 load address 0x08041fec
+ .igot.plt      0x2400018c        0x0 F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+dp/hard/crtbegin.o
+
+.RxDecripSection
+                0x2400018c       0x60 load address 0x08041fec
+ .RxDecripSection
+                0x2400018c       0x60 ./Core/Src/eth.o
+                0x2400018c                DMARxDscrTab
+
+.TxDecripSection
+                0x240001ec       0x60 load address 0x0804204c
+ .TxDecripSection
+                0x240001ec       0x60 ./Core/Src/eth.o
+                0x240001ec                DMATxDscrTab
+                0x2400024c                        . = ALIGN (0x4)
+
+.bss            0x24000250     0xb174 load address 0x080420ac
+                0x24000250                        _sbss = .
+                0x24000250                        __bss_start__ = _sbss
+ *(.bss)
+ .bss           0x24000250       0x1c F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+dp/hard/crtbegin.o
+ *(.bss*)
+ .bss.Motor_ID_Errors
+                0x2400026c       0x1c ./Core/BASE/Src/BSP/BHBF_ROBOT.o
+                0x2400026c                Motor_ID_Errors
+ .bss.SystemTimeMiliCount
+                0x24000288        0x4 ./Core/BASE/Src/BSP/BHBF_ROBOT.o
+                0x24000288                SystemTimeMiliCount
+ .bss.SystemErrorCode
+                0x2400028c        0x4 ./Core/BASE/Src/BSP/BHBF_ROBOT.o
+                0x2400028c                SystemErrorCode
+ .bss.TT_Motor  0x24000290       0x10 ./Core/BASE/Src/BSP/BHBF_ROBOT.o
+                0x24000290                TT_Motor
+ .bss.CV        0x240002a0       0x9c ./Core/BASE/Src/BSP/BHBF_ROBOT.o
+                0x240002a0                CV
+ *fill*         0x2400033c        0x4 
+ .bss.GV        0x24000340      0x2a0 ./Core/BASE/Src/BSP/BHBF_ROBOT.o
+                0x24000340                GV
+ .bss.IV        0x240005e0       0x34 ./Core/BASE/Src/BSP/BHBF_ROBOT.o
+                0x240005e0                IV
+ .bss.dLT_Log_UART_Handler
+                0x24000614        0x4 ./Core/BASE/Src/BSP/bsp_DLT_Log.o
+                0x24000614                dLT_Log_UART_Handler
+ .bss.HardWareErrorController
+                0x24000618        0x4 ./Core/BASE/Src/BSP/bsp_Error_Detect.o
+                0x24000618                HardWareErrorController
+ .bss.FD_CAN_1_Handler
+                0x2400061c      0x138 ./Core/BASE/Src/BSP/bsp_FDCAN.o
+                0x2400061c                FD_CAN_1_Handler
+ .bss.FD_CAN_2_Handler
+                0x24000754      0x138 ./Core/BASE/Src/BSP/bsp_FDCAN.o
+                0x24000754                FD_CAN_2_Handler
+ .bss.CAN_RX_HDR
+                0x2400088c       0x28 ./Core/BASE/Src/BSP/bsp_FDCAN.o
+                0x2400088c                CAN_RX_HDR
+ .bss.CAN_Buf   0x240008b4        0x8 ./Core/BASE/Src/BSP/bsp_FDCAN.o
+                0x240008b4                CAN_Buf
+ .bss.CAN_Buf_2
+                0x240008bc        0x8 ./Core/BASE/Src/BSP/bsp_FDCAN.o
+                0x240008bc                CAN_Buf_2
+ .bss.CAN_ID    0x240008c4        0x4 ./Core/BASE/Src/BSP/bsp_FDCAN.o
+                0x240008c4                CAN_ID
+ .bss.CAN_ID_2  0x240008c8        0x4 ./Core/BASE/Src/BSP/bsp_FDCAN.o
+                0x240008c8                CAN_ID_2
+ .bss.TXHeader1
+                0x240008cc       0x24 ./Core/BASE/Src/BSP/bsp_FDCAN.o
+                0x240008cc                TXHeader1
+ .bss.TXHeader2
+                0x240008f0       0x24 ./Core/BASE/Src/BSP/bsp_FDCAN.o
+                0x240008f0                TXHeader2
+ .bss.can_dispacherController
+                0x24000914        0x4 ./Core/BASE/Src/BSP/bsp_FDCAN.o
+                0x24000914                can_dispacherController
+ .bss.V_BSP_InterCall_Array
+                0x24000918      0x39c ./Core/BASE/Src/BSP/bsp_INTERCALL.o
+                0x24000918                V_BSP_InterCall_Array
+ .bss.RS_485_1_UART_Handler
+                0x24000cb4     0x1040 ./Core/BASE/Src/BSP/bsp_UART.o
+                0x24000cb4                RS_485_1_UART_Handler
+ .bss.RS_485_2_UART_Handler
+                0x24001cf4     0x1040 ./Core/BASE/Src/BSP/bsp_UART.o
+                0x24001cf4                RS_485_2_UART_Handler
+ .bss.RS_485_3_UART_Handler
+                0x24002d34     0x1040 ./Core/BASE/Src/BSP/bsp_UART.o
+                0x24002d34                RS_485_3_UART_Handler
+ .bss.RS_485_4_UART_Handler
+                0x24003d74     0x1040 ./Core/BASE/Src/BSP/bsp_UART.o
+                0x24003d74                RS_485_4_UART_Handler
+ .bss.InterCall_DEBUG_UART_Handler
+                0x24004db4     0x1040 ./Core/BASE/Src/BSP/bsp_UART.o
+                0x24004db4                InterCall_DEBUG_UART_Handler
+ .bss.E28_SBUS_UART_Handler
+                0x24005df4     0x1040 ./Core/BASE/Src/BSP/bsp_UART.o
+                0x24005df4                E28_SBUS_UART_Handler
+ .bss.LTE_7S0_Serial_UART_Handler
+                0x24006e34     0x1040 ./Core/BASE/Src/BSP/bsp_UART.o
+                0x24006e34                LTE_7S0_Serial_UART_Handler
+ .bss.LPUART1_UART_Handler
+                0x24007e74     0x1040 ./Core/BASE/Src/BSP/bsp_UART.o
+                0x24007e74                LPUART1_UART_Handler
+ .bss.desulfurizer_message_UART_Handler
+                0x24008eb4        0x4 ./Core/BASE/Src/BSP/bsp_UpperComputer_Handler.o
+                0x24008eb4                desulfurizer_message_UART_Handler
+ .bss.client_setting_Handler
+                0x24008eb8        0x4 ./Core/BASE/Src/BSP/bsp_client_setting.o
+                0x24008eb8                client_setting_Handler
+ .bss.client_setting_dispacher
+                0x24008ebc        0x4 ./Core/BASE/Src/BSP/bsp_client_setting.o
+                0x24008ebc                client_setting_dispacher
+ .bss.str1      0x24008ec0       0x32 ./Core/BASE/Src/BSP/bsp_com_helper.o
+                0x24008ec0                str1
+ *fill*         0x24008ef2        0x2 
+ .bss.send_Cmd  0x24008ef4      0x21c ./Core/BASE/Src/BSP/bsp_decode_command.o
+                0x24008ef4                send_Cmd
+ .bss.DLT_LOG_ENABLE_LEVEL
+                0x24009110        0x1 ./Core/BASE/Src/BSP/DLT/DLTuc.o
+                0x24009110                DLT_LOG_ENABLE_LEVEL
+ *fill*         0x24009111        0x3 
+ .bss.ExtSerialTrDataFunctionCb
+                0x24009114        0x4 ./Core/BASE/Src/BSP/DLT/DLTuc.o
+ .bss.ExtSerialRecDataFunctionCb
+                0x24009118        0x4 ./Core/BASE/Src/BSP/DLT/DLTuc.o
+ .bss.ExtInfoInjectionDataRcvdCb
+                0x2400911c        0x4 ./Core/BASE/Src/BSP/DLT/DLTuc.o
+ .bss.GetSystemTimeMs
+                0x24009120        0x4 ./Core/BASE/Src/BSP/DLT/DLTuc.o
+ .bss.LogDroppedFlag
+                0x24009124        0x1 ./Core/BASE/Src/BSP/DLT/DLTuc.o
+ *fill*         0x24009125        0x3 
+ .bss.PrevLogDropSendTime
+                0x24009128        0x4 ./Core/BASE/Src/BSP/DLT/DLTuc.o
+ .bss.DltLogDroppedInfoBuffer
+                0x2400912c       0x3c ./Core/BASE/Src/BSP/DLT/DLTuc.o
+ .bss.DLtLogDroppedSize
+                0x24009168        0x1 ./Core/BASE/Src/BSP/DLT/DLTuc.o
+ .bss.ActDltMessageCounter
+                0x24009169        0x1 ./Core/BASE/Src/BSP/DLT/DLTuc.o
+ *fill*         0x2400916a        0x2 
+ .bss.DltTrsmtMessagesTab
+                0x2400916c      0xef1 ./Core/BASE/Src/BSP/DLT/DLTuc.o
+ *fill*         0x2400a05d        0x3 
+ .bss.BleMainReceiveRingBuffer
+                0x2400a060        0x8 ./Core/BASE/Src/BSP/DLT/DLTuc.o
+ .bss.BluMainReceiveMessagesTab
+                0x2400a068      0x1fe ./Core/BASE/Src/BSP/DLT/DLTuc.o
+ *fill*         0x2400a266        0x2 
+ .bss.DefaultBlindBuffer.1
+                0x2400a268       0xff ./Core/BASE/Src/BSP/DLT/DLTuc.o
+ *fill*         0x2400a367        0x1 
+ .bss.MessageReceiveBufferAddress.0
+                0x2400a368        0x4 ./Core/BASE/Src/BSP/DLT/DLTuc.o
+ .bss.blastControl
+                0x2400a36c        0x4 ./Core/BASE/Src/MSP/msp_Blast_Machine.o
+                0x2400a36c                blastControl
+ .bss.blastMachineRemoteEncoder_1
+                0x2400a370        0x4 ./Core/BASE/Src/MSP/msp_Blast_Machine.o
+                0x2400a370                blastMachineRemoteEncoder_1
+ .bss.blastMachineRemoteEncoder_2
+                0x2400a374        0x4 ./Core/BASE/Src/MSP/msp_Blast_Machine.o
+                0x2400a374                blastMachineRemoteEncoder_2
+ .bss.blastMachineRemoteEncoderCommand
+                0x2400a378        0x8 ./Core/BASE/Src/MSP/msp_Blast_Machine.o
+                0x2400a378                blastMachineRemoteEncoderCommand
+ .bss.blastMachineRemoteEncoderCommand2
+                0x2400a380        0x8 ./Core/BASE/Src/MSP/msp_Blast_Machine.o
+                0x2400a380                blastMachineRemoteEncoderCommand2
+ .bss.control_open_commend_counts
+                0x2400a388        0x4 ./Core/BASE/Src/MSP/msp_Blast_Machine.o
+                0x2400a388                control_open_commend_counts
+ .bss.control_close_commend_counts
+                0x2400a38c        0x4 ./Core/BASE/Src/MSP/msp_Blast_Machine.o
+                0x2400a38c                control_close_commend_counts
+ .bss.testcounts
+                0x2400a390        0x4 ./Core/BASE/Src/MSP/msp_Blast_Machine.o
+                0x2400a390                testcounts
+ .bss.cmcu_sensor
+                0x2400a394        0x4 ./Core/BASE/Src/MSP/msp_CMCUU.o
+                0x2400a394                cmcu_sensor
+ .bss.CMCU      0x2400a398        0x4 ./Core/BASE/Src/MSP/msp_CMCUU.o
+                0x2400a398                CMCU
+ .bss.cmcu_sensor_dispacherController
+                0x2400a39c        0x4 ./Core/BASE/Src/MSP/msp_CMCUU.o
+                0x2400a39c                cmcu_sensor_dispacherController
+ .bss.Pressure_value
+                0x2400a3a0        0x4 ./Core/BASE/Src/MSP/msp_CMCUU.o
+                0x2400a3a0                Pressure_value
+ .bss.Crc_check
+                0x2400a3a4        0x2 ./Core/BASE/Src/MSP/msp_CMCUU.o
+                0x2400a3a4                Crc_check
+ .bss.crc_checkH
+                0x2400a3a6        0x1 ./Core/BASE/Src/MSP/msp_CMCUU.o
+                0x2400a3a6                crc_checkH
+ .bss.crc_checkL
+                0x2400a3a7        0x1 ./Core/BASE/Src/MSP/msp_CMCUU.o
+                0x2400a3a7                crc_checkL
+ .bss.crc_checkh
+                0x2400a3a8        0x1 ./Core/BASE/Src/MSP/msp_CMCUU.o
+                0x2400a3a8                crc_checkh
+ .bss.crc_checkl
+                0x2400a3a9        0x1 ./Core/BASE/Src/MSP/msp_CMCUU.o
+                0x2400a3a9                crc_checkl
+ *fill*         0x2400a3aa        0x2 
+ .bss.KS206     0x2400a3ac        0x4 ./Core/BASE/Src/MSP/msp_KS206.o
+                0x2400a3ac                KS206
+ .bss.Gyro_mfog40
+                0x2400a3b0        0x4 ./Core/BASE/Src/MSP/msp_MF_Gyroscope.o
+                0x2400a3b0                Gyro_mfog40
+ .bss.Huart_Gyro_MFOG40
+                0x2400a3b4        0x4 ./Core/BASE/Src/MSP/msp_MF_Gyroscope.o
+                0x2400a3b4                Huart_Gyro_MFOG40
+ .bss.Gyro_stas
+                0x2400a3b8        0x1 ./Core/BASE/Src/MSP/msp_MF_Gyroscope.o
+                0x2400a3b8                Gyro_stas
+ *fill*         0x2400a3b9        0x3 
+ .bss.Gyro_Vale_AngularVel0
+                0x2400a3bc        0x1 ./Core/BASE/Src/MSP/msp_MF_Gyroscope.o
+                0x2400a3bc                Gyro_Vale_AngularVel0
+ *fill*         0x2400a3bd        0x3 
+ .bss.Gyro_Vale_AngularVel1
+                0x2400a3c0        0x1 ./Core/BASE/Src/MSP/msp_MF_Gyroscope.o
+                0x2400a3c0                Gyro_Vale_AngularVel1
+ *fill*         0x2400a3c1        0x3 
+ .bss.Gyro_Vale_AngularVel2
+                0x2400a3c4        0x1 ./Core/BASE/Src/MSP/msp_MF_Gyroscope.o
+                0x2400a3c4                Gyro_Vale_AngularVel2
+ *fill*         0x2400a3c5        0x3 
+ .bss.Gyro_Vale_AngularVel3
+                0x2400a3c8        0x1 ./Core/BASE/Src/MSP/msp_MF_Gyroscope.o
+                0x2400a3c8                Gyro_Vale_AngularVel3
+ *fill*         0x2400a3c9        0x3 
+ .bss.Gyro_Vale_Angular0
+                0x2400a3cc        0x1 ./Core/BASE/Src/MSP/msp_MF_Gyroscope.o
+                0x2400a3cc                Gyro_Vale_Angular0
+ *fill*         0x2400a3cd        0x3 
+ .bss.Gyro_Vale_Angular1
+                0x2400a3d0        0x1 ./Core/BASE/Src/MSP/msp_MF_Gyroscope.o
+                0x2400a3d0                Gyro_Vale_Angular1
+ *fill*         0x2400a3d1        0x3 
+ .bss.Gyro_Vale_Angular2
+                0x2400a3d4        0x1 ./Core/BASE/Src/MSP/msp_MF_Gyroscope.o
+                0x2400a3d4                Gyro_Vale_Angular2
+ *fill*         0x2400a3d5        0x3 
+ .bss.Gyro_Vale_Angular3
+                0x2400a3d8        0x1 ./Core/BASE/Src/MSP/msp_MF_Gyroscope.o
+                0x2400a3d8                Gyro_Vale_Angular3
+ *fill*         0x2400a3d9        0x3 
+ .bss.Gyro_Vale_Temper0
+                0x2400a3dc        0x1 ./Core/BASE/Src/MSP/msp_MF_Gyroscope.o
+                0x2400a3dc                Gyro_Vale_Temper0
+ *fill*         0x2400a3dd        0x3 
+ .bss.Gyro_Vale_Temper1
+                0x2400a3e0        0x1 ./Core/BASE/Src/MSP/msp_MF_Gyroscope.o
+                0x2400a3e0                Gyro_Vale_Temper1
+ *fill*         0x2400a3e1        0x3 
+ .bss.Gyro_Vale_Check0
+                0x2400a3e4        0x1 ./Core/BASE/Src/MSP/msp_MF_Gyroscope.o
+                0x2400a3e4                Gyro_Vale_Check0
+ *fill*         0x2400a3e5        0x3 
+ .bss.Gyro_Vale_Check1
+                0x2400a3e8        0x1 ./Core/BASE/Src/MSP/msp_MF_Gyroscope.o
+                0x2400a3e8                Gyro_Vale_Check1
+ .bss.Cheak     0x2400a3e9        0x1 ./Core/BASE/Src/MSP/msp_MF_Gyroscope.o
+                0x2400a3e9                Cheak
+ *fill*         0x2400a3ea        0x6 
+ .bss.Angle_Pi_Pi
+                0x2400a3f0        0x8 ./Core/BASE/Src/MSP/msp_MF_Gyroscope.o
+                0x2400a3f0                Angle_Pi_Pi
+ .bss.P_MK32    0x2400a3f8        0x4 ./Core/BASE/Src/MSP/msp_MK32_1.o
+                0x2400a3f8                P_MK32
+ .bss.MK32_Sbus_Controller
+                0x2400a3fc        0x4 ./Core/BASE/Src/MSP/msp_MK32_1.o
+                0x2400a3fc                MK32_Sbus_Controller
+ .bss.Desire_Angle
+                0x2400a400        0x8 ./Core/BASE/Src/MSP/msp_PID.o
+                0x2400a400                Desire_Angle
+ .bss.k_1_error
+                0x2400a408        0x8 ./Core/BASE/Src/MSP/msp_PID.o
+                0x2400a408                k_1_error
+ .bss.RobotAngle
+                0x2400a410        0x4 ./Core/BASE/Src/MSP/msp_TL720D.o
+                0x2400a410                RobotAngle
+ .bss.TL720D_UART_Handler
+                0x2400a414        0x4 ./Core/BASE/Src/MSP/msp_TL720D.o
+                0x2400a414                TL720D_UART_Handler
+ .bss.SP_MSP_RF_TL720D_Parameters_In
+                0x2400a418        0x4 ./Core/BASE/Src/MSP/msp_TL720D.o
+                0x2400a418                SP_MSP_RF_TL720D_Parameters_In
+ .bss.wh_LTE_7S0_Handler
+                0x2400a41c        0x4 ./Core/BASE/Src/MSP/msp_WH_LTE_7S0.o
+                0x2400a41c                wh_LTE_7S0_Handler
+ .bss.wh_LTE_7S0_dispacher
+                0x2400a420        0x4 ./Core/BASE/Src/MSP/msp_WH_LTE_7S0.o
+                0x2400a420                wh_LTE_7S0_dispacher
+ .bss.hadc2     0x2400a424       0x64 ./Core/Src/adc.o
+                0x2400a424                hadc2
+ .bss.TxConfig  0x2400a488       0x38 ./Core/Src/eth.o
+                0x2400a488                TxConfig
+ .bss.heth      0x2400a4c0       0xb0 ./Core/Src/eth.o
+                0x2400a4c0                heth
+ .bss.MACAddr.0
+                0x2400a570        0x6 ./Core/Src/eth.o
+ *fill*         0x2400a576        0x2 
+ .bss.hfdcan1   0x2400a578       0xa0 ./Core/Src/fdcan.o
+                0x2400a578                hfdcan1
+ .bss.hfdcan2   0x2400a618       0xa0 ./Core/Src/fdcan.o
+                0x2400a618                hfdcan2
+ .bss.HAL_RCC_FDCAN_CLK_ENABLED
+                0x2400a6b8        0x4 ./Core/Src/fdcan.o
+ .bss.index_counter
+                0x2400a6bc        0x4 ./Core/Src/fsm.o
+                0x2400a6bc                index_counter
+ .bss.is_upper_computer_take_over_control
+                0x2400a6c0        0x1 ./Core/Src/fsm.o
+                0x2400a6c0                is_upper_computer_take_over_control
+ *fill*         0x2400a6c1        0x3 
+ .bss.Region_Task_Falg
+                0x2400a6c4        0x4 ./Core/Src/fsm.o
+                0x2400a6c4                Region_Task_Falg
+ .bss.Horzi_Der_Angle_Deg
+                0x2400a6c8        0x8 ./Core/Src/fsm.o
+                0x2400a6c8                Horzi_Der_Angle_Deg
+ .bss.CV_Robot_Deri_Angle_Deg_Grity
+                0x2400a6d0        0x8 ./Core/Src/fsm.o
+                0x2400a6d0                CV_Robot_Deri_Angle_Deg_Grity
+ .bss.CV_Robot_Deri_Angle_Deg_Plane
+                0x2400a6d8        0x8 ./Core/Src/fsm.o
+                0x2400a6d8                CV_Robot_Deri_Angle_Deg_Plane
+ .bss.Robot_Platform_Back_Flag_Y
+                0x2400a6e0        0x4 ./Core/Src/fsm.o
+                0x2400a6e0                Robot_Platform_Back_Flag_Y
+ *fill*         0x2400a6e4        0x4 
+ .bss.Vertical_Der_Angle_Deg
+                0x2400a6e8        0x8 ./Core/Src/fsm.o
+                0x2400a6e8                Vertical_Der_Angle_Deg
+ .bss.Change_Road_Jude_Flag
+                0x2400a6f0        0x4 ./Core/Src/fsm.o
+                0x2400a6f0                Change_Road_Jude_Flag
+ .bss.Swing_Limit_Flag
+                0x2400a6f4        0x4 ./Core/Src/fsm.o
+                0x2400a6f4                Swing_Limit_Flag
+ .bss.Robot_Platform_Back_Flag
+                0x2400a6f8        0x4 ./Core/Src/fsm.o
+                0x2400a6f8                Robot_Platform_Back_Flag
+ .bss.Auto_Job_Back_Time_MS_Count
+                0x2400a6fc        0x4 ./Core/Src/fsm.o
+                0x2400a6fc                Auto_Job_Back_Time_MS_Count
+ .bss.Current_PushRod_STATE
+                0x2400a700        0x1 ./Core/Src/fsm.o
+                0x2400a700                Current_PushRod_STATE
+ *fill*         0x2400a701        0x3 
+ .bss.GV_Robot_Move_Speed
+                0x2400a704        0x4 ./Core/Src/fsm.o
+                0x2400a704                GV_Robot_Move_Speed
+ .bss.GV_Robot_Change_Lane_Distance
+                0x2400a708        0x8 ./Core/Src/fsm.o
+                0x2400a708                GV_Robot_Change_Lane_Distance
+ .bss.GV_Swing_Speed
+                0x2400a710        0x4 ./Core/Src/fsm.o
+                0x2400a710                GV_Swing_Speed
+ .bss.GV_Robot_symmetricalOrNot
+                0x2400a714        0x4 ./Core/Src/fsm.o
+                0x2400a714                GV_Robot_symmetricalOrNot
+ .bss.GV_Robot_Swing_Range_Angle
+                0x2400a718        0x4 ./Core/Src/fsm.o
+                0x2400a718                GV_Robot_Swing_Range_Angle
+ .bss.GV_Robot_asymmetricalAngleSetValue
+                0x2400a71c        0x4 ./Core/Src/fsm.o
+                0x2400a71c                GV_Robot_asymmetricalAngleSetValue
+ .bss.GV_Robot_backMode
+                0x2400a720        0x4 ./Core/Src/fsm.o
+                0x2400a720                GV_Robot_backMode
+ *fill*         0x2400a724        0x4 
+ .bss.GV_Robot_Back_Distance
+                0x2400a728        0x8 ./Core/Src/fsm.o
+                0x2400a728                GV_Robot_Back_Distance
+ .bss.GV_Robot_Back_Speed
+                0x2400a730        0x8 ./Core/Src/fsm.o
+                0x2400a730                GV_Robot_Back_Speed
+ .bss.GV_Robot_Press_Set
+                0x2400a738        0x4 ./Core/Src/fsm.o
+                0x2400a738                GV_Robot_Press_Set
+ *fill*         0x2400a73c        0x4 
+ .bss.GV_Robot_Vertical_Adjust
+                0x2400a740        0x8 ./Core/Src/fsm.o
+                0x2400a740                GV_Robot_Vertical_Adjust
+ .bss.GV_Robot_Length_Homework
+                0x2400a748        0x4 ./Core/Src/fsm.o
+                0x2400a748                GV_Robot_Length_Homework
+ .bss.GV_Robot_Width_Homework
+                0x2400a74c        0x4 ./Core/Src/fsm.o
+                0x2400a74c                GV_Robot_Width_Homework
+ .bss.GV_Operation_Mode
+                0x2400a750        0x4 ./Core/Src/fsm.o
+                0x2400a750                GV_Operation_Mode
+ *fill*         0x2400a754        0x4 
+ .bss.Robot_Speed_Base
+                0x2400a758        0x8 ./Core/Src/fsm.o
+                0x2400a758                Robot_Speed_Base
+ .bss.Robot_Countinus_Speed
+                0x2400a760        0x8 ./Core/Src/fsm.o
+                0x2400a760                Robot_Countinus_Speed
+ .bss.Rock_Angle
+                0x2400a768        0x8 ./Core/Src/fsm.o
+                0x2400a768                Rock_Angle
+ .bss.ctl_flag  0x2400a770        0x4 ./Core/Src/fsm.o
+                0x2400a770                ctl_flag
+ .bss.ctl_flag_1
+                0x2400a774        0x4 ./Core/Src/fsm.o
+                0x2400a774                ctl_flag_1
+ .bss.Switch_Off_Flag
+                0x2400a778        0x1 ./Core/Src/fsm.o
+                0x2400a778                Switch_Off_Flag
+ *fill*         0x2400a779        0x3 
+ .bss.Robot_Main_Flag
+                0x2400a77c        0x4 ./Core/Src/fsm.o
+                0x2400a77c                Robot_Main_Flag
+ .bss.Robot_Angle_G_P_Deg
+                0x2400a780        0x8 ./Core/Src/fsm.o
+                0x2400a780                Robot_Angle_G_P_Deg
+ .bss.MF40G_Angle_Add_Deg
+                0x2400a788        0x8 ./Core/Src/fsm.o
+                0x2400a788                MF40G_Angle_Add_Deg
+ .bss.MF40G_Angle_Add_Count
+                0x2400a790        0x4 ./Core/Src/fsm.o
+                0x2400a790                MF40G_Angle_Add_Count
+ .bss.Forward_Flag_Robot_Manual_Count
+                0x2400a794        0x4 ./Core/Src/fsm.o
+                0x2400a794                Forward_Flag_Robot_Manual_Count
+ .bss.Forward_Flag_Robot_Auto
+                0x2400a798        0x4 ./Core/Src/fsm.o
+                0x2400a798                Forward_Flag_Robot_Auto
+ .bss.Backward_Num_X_Count
+                0x2400a79c        0x4 ./Core/Src/fsm.o
+                0x2400a79c                Backward_Num_X_Count
+ .bss.Plane_Complete_Total_XY
+                0x2400a7a0        0x4 ./Core/Src/fsm.o
+                0x2400a7a0                Plane_Complete_Total_XY
+ .bss.Plane_Complete_Count
+                0x2400a7a4        0x4 ./Core/Src/fsm.o
+                0x2400a7a4                Plane_Complete_Count
+ .bss.Plane_Turn_Angle_Deg
+                0x2400a7a8        0x8 ./Core/Src/fsm.o
+                0x2400a7a8                Plane_Turn_Angle_Deg
+ .bss.Deri_Angle_Deg_X
+                0x2400a7b0       0x10 ./Core/Src/fsm.o
+                0x2400a7b0                Deri_Angle_Deg_X
+ .bss.X_Deri_Angle
+                0x2400a7c0       0x10 ./Core/Src/fsm.o
+                0x2400a7c0                X_Deri_Angle
+ .bss.Backward_Count_X
+                0x2400a7d0        0x4 ./Core/Src/fsm.o
+                0x2400a7d0                Backward_Count_X
+ *fill*         0x2400a7d4        0x4 
+ .bss.Backward_Num_X_Total
+                0x2400a7d8        0x8 ./Core/Src/fsm.o
+                0x2400a7d8                Backward_Num_X_Total
+ .bss.Lane_Change_Num_Total_Y
+                0x2400a7e0        0x8 ./Core/Src/fsm.o
+                0x2400a7e0                Lane_Change_Num_Total_Y
+ .bss.Horizontal_Turn_Angle_Deg
+                0x2400a7e8        0x8 ./Core/Src/fsm.o
+                0x2400a7e8                Horizontal_Turn_Angle_Deg
+ .bss.Horizontal_Complete_Total_XY
+                0x2400a7f0        0x4 ./Core/Src/fsm.o
+                0x2400a7f0                Horizontal_Complete_Total_XY
+ *fill*         0x2400a7f4        0x4 
+ .bss.Der_Angle_Plane
+                0x2400a7f8       0x10 ./Core/Src/fsm.o
+                0x2400a7f8                Der_Angle_Plane
+ .bss.Change_R_L_Count_1
+                0x2400a808        0x4 ./Core/Src/fsm.o
+                0x2400a808                Change_R_L_Count_1
+ .bss.Swing_Time_Count
+                0x2400a80c        0x4 ./Core/Src/fsm.o
+                0x2400a80c                Swing_Time_Count
+ .bss.Swing_Time_All
+                0x2400a810        0x8 ./Core/Src/fsm.o
+                0x2400a810                Swing_Time_All
+ .bss.Swing_Time_Threshold
+                0x2400a818        0x8 ./Core/Src/fsm.o
+                0x2400a818                Swing_Time_Threshold
+ .bss.Left_Target_Pos
+                0x2400a820        0x8 ./Core/Src/fsm.o
+                0x2400a820                Left_Target_Pos
+ .bss.Right_Target_Pos
+                0x2400a828        0x8 ./Core/Src/fsm.o
+                0x2400a828                Right_Target_Pos
+ .bss.Left_Threshold_Pos
+                0x2400a830        0x8 ./Core/Src/fsm.o
+                0x2400a830                Left_Threshold_Pos
+ .bss.Right_Threshold_Pos
+                0x2400a838        0x8 ./Core/Src/fsm.o
+                0x2400a838                Right_Threshold_Pos
+ .bss.Auto_Job_Back_Time_MS_Horizontal
+                0x2400a840        0x8 ./Core/Src/fsm.o
+                0x2400a840                Auto_Job_Back_Time_MS_Horizontal
+ .bss.Auto_Job_Back_Time_MS_Vertical
+                0x2400a848        0x8 ./Core/Src/fsm.o
+                0x2400a848                Auto_Job_Back_Time_MS_Vertical
+ .bss.Horizontal_Back_Speed_Value
+                0x2400a850        0x8 ./Core/Src/fsm.o
+                0x2400a850                Horizontal_Back_Speed_Value
+ .bss.Vertical_Back_Speed_Value
+                0x2400a858        0x8 ./Core/Src/fsm.o
+                0x2400a858                Vertical_Back_Speed_Value
+ .bss.Plane_Back_Speed_Value
+                0x2400a860        0x8 ./Core/Src/fsm.o
+                0x2400a860                Plane_Back_Speed_Value
+ .bss.Swi_Range_Auto
+                0x2400a868        0x8 ./Core/Src/fsm.o
+                0x2400a868                Swi_Range_Auto
+ .bss.Regional_Automatic_Flag
+                0x2400a870        0x4 ./Core/Src/fsm.o
+                0x2400a870                Regional_Automatic_Flag
+ .bss.PushRod_Flag
+                0x2400a874        0x4 ./Core/Src/fsm.o
+                0x2400a874                PushRod_Flag
+ .bss.D_value   0x2400a878        0x8 ./Core/Src/fsm.o
+                0x2400a878                D_value
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+                0x2400a880        0x4 ./Core/Src/fsm.o
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+                0x2400a890        0x4 ./Core/Src/fsm.o
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+                0x2400a894        0x4 ./Core/Src/fsm.o
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+                0x2400a898        0x4 ./Core/Src/fsm.o
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+                0x2400a89c        0x4 ./Core/Src/fsm.o
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+                0x2400a8a0        0x4 ./Core/Src/fsm.o
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+                0x2400a8a4        0x4 ./Core/Src/fsm.o
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+                0x2400a8a8        0x4 ./Core/Src/fsm.o
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+                0x2400a8b0        0x4 ./Core/Src/fsm.o
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+                0x2400a8b4        0x4 ./Core/Src/fsm.o
+ .bss.Change_R_L_Count.20
+                0x2400a8b8        0x4 ./Core/Src/fsm.o
+ .bss.Turn_Count.19
+                0x2400a8bc        0x4 ./Core/Src/fsm.o
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+                0x2400a8c0        0x4 ./Core/Src/fsm.o
+ .bss.Change_R_L_Count.17
+                0x2400a8c4        0x4 ./Core/Src/fsm.o
+ .bss.Initial_Power_Record.16
+                0x2400a8c8        0x4 ./Core/Src/fsm.o
+ .bss.Backward_Time_X_Total.11
+                0x2400a8cc        0x4 ./Core/Src/fsm.o
+ .bss.Lane_Change_Time_Total_Y.10
+                0x2400a8d0        0x4 ./Core/Src/fsm.o
+ .bss.Backward_Time_Count.9
+                0x2400a8d4        0x4 ./Core/Src/fsm.o
+ .bss.Backward_Time_X_Total.8
+                0x2400a8d8        0x4 ./Core/Src/fsm.o
+ .bss.Lane_Change_Time_Total_Y.7
+                0x2400a8dc        0x4 ./Core/Src/fsm.o
+ .bss.Backward_Time_Count.6
+                0x2400a8e0        0x4 ./Core/Src/fsm.o
+ .bss.GV_Robot_Swing_Range_Angle_Last.5
+                0x2400a8e4        0x4 ./Core/Src/fsm.o
+ .bss.Sw_Rust_Mid_Posi.4
+                0x2400a8e8        0x8 ./Core/Src/fsm.o
+ .bss.S1_Last_Value.3
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+                0x2400a8f8        0x8 ./Core/Src/fsm.o
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+                0x2400a908        0x8 ./Core/Src/fsm.o
+ .bss.hi2c4     0x2400a910       0x54 ./Core/Src/i2c.o
+                0x2400a910                hi2c4
+ .bss.Roughening_Motor_Controller
+                0x2400a964        0x4 ./Core/Src/motors.o
+                0x2400a964                Roughening_Motor_Controller
+ .bss.Roughening_Motor_Controller_CAN2
+                0x2400a968        0x4 ./Core/Src/motors.o
+                0x2400a968                Roughening_Motor_Controller_CAN2
+ .bss.Roughening_DispacherController
+                0x2400a96c        0x4 ./Core/Src/motors.o
+                0x2400a96c                Roughening_DispacherController
+ .bss.Roughening_DispacherController_CAN2
+                0x2400a970        0x4 ./Core/Src/motors.o
+                0x2400a970                Roughening_DispacherController_CAN2
+ .bss.a         0x2400a974        0xa ./Core/Src/motors.o
+                0x2400a974                a
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+                0x2400a980        0x4 ./Core/Src/motors.o
+ .bss.hqspi     0x2400a984       0x4c ./Core/Src/quadspi.o
+                0x2400a984                hqspi
+ .bss.Robot_LeftCompensation
+                0x2400a9d0        0x4 ./Core/Src/robot_state.o
+                0x2400a9d0                Robot_LeftCompensation
+ .bss.Robot_RightCompensation
+                0x2400a9d4        0x4 ./Core/Src/robot_state.o
+                0x2400a9d4                Robot_RightCompensation
+ .bss.Robot_Angle_Start_BASE
+                0x2400a9d8        0x4 ./Core/Src/robot_state.o
+                0x2400a9d8                Robot_Angle_Start_BASE
+ .bss.Robot_Angle
+                0x2400a9dc        0x4 ./Core/Src/robot_state.o
+                0x2400a9dc                Robot_Angle
+ .bss.Robot_Deri_Speed
+                0x2400a9e0        0x4 ./Core/Src/robot_state.o
+                0x2400a9e0                Robot_Deri_Speed
+ *fill*         0x2400a9e4        0x4 
+ .bss.Angle_Error_LLL
+                0x2400a9e8        0x8 ./Core/Src/robot_state.o
+                0x2400a9e8                Angle_Error_LLL
+ .bss.CRLU_Flag
+                0x2400a9f0        0x4 ./Core/Src/robot_state.o
+                0x2400a9f0                CRLU_Flag
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+ .bss.htim1     0x2400a9f8       0x4c ./Core/Src/tim.o
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+                0x2400ae9c                huart6
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+                0x2400af30                hdma_uart4_tx
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+                0x2400afa8                hdma_uart5_tx
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+                0x2400b020                hdma_uart7_tx
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+                0x2400dbc8                        . = ALIGN (0x8)
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+                0x000014b0       0x20 F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+dp/hard\libgcc.a(_aeabi_uldivmod.o)
+ .ARM.attributes
+                0x000014d0       0x32 F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+dp/hard\libgcc.a(_udivmoddi4.o)
+ .ARM.attributes
+                0x00001502       0x20 F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+dp/hard\libgcc.a(_dvmd_tls.o)
+ .ARM.attributes
+                0x00001522       0x20 F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+dp/hard/crtn.o
+OUTPUT(BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3.elf elf32-littlearm)
+LOAD linker stubs
+LOAD F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc.a
+LOAD F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libm.a
+LOAD F:/IDE/STM32CubeIDE_1.15.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.12.3.rel1.win32_1.0.100.202403111256/tools/bin/../lib/gcc/arm-none-eabi/12.3.1/thumb/v7e-m+dp/hard\libgcc.a
+
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+ .debug_line_str
+                0x00000000       0x6c ./Core/Startup/startup_stm32h743vgtx.o
diff --git a/Debug/Core/BASE/Protobuf/PSource/bsp_CV.pb.cyclo b/Debug/Core/BASE/Protobuf/PSource/bsp_CV.pb.cyclo
new file mode 100644
index 0000000..e69de29
diff --git a/Debug/Core/BASE/Protobuf/PSource/bsp_CV.pb.d b/Debug/Core/BASE/Protobuf/PSource/bsp_CV.pb.d
new file mode 100644
index 0000000..60aa60a
--- /dev/null
+++ b/Debug/Core/BASE/Protobuf/PSource/bsp_CV.pb.d
@@ -0,0 +1,8 @@
+Core/BASE/Protobuf/PSource/bsp_CV.pb.o: \
+ ../Core/BASE/Protobuf/PSource/bsp_CV.pb.c \
+ ../Core/BASE/Protobuf/PSource/bsp_CV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ ../Core/BASE/Protobuf/PSource/bsp_PV.pb.h
+../Core/BASE/Protobuf/PSource/bsp_CV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+../Core/BASE/Protobuf/PSource/bsp_PV.pb.h:
diff --git a/Debug/Core/BASE/Protobuf/PSource/bsp_CV.pb.o b/Debug/Core/BASE/Protobuf/PSource/bsp_CV.pb.o
new file mode 100644
index 0000000..3b49858
Binary files /dev/null and b/Debug/Core/BASE/Protobuf/PSource/bsp_CV.pb.o differ
diff --git a/Debug/Core/BASE/Protobuf/PSource/bsp_CV.pb.su b/Debug/Core/BASE/Protobuf/PSource/bsp_CV.pb.su
new file mode 100644
index 0000000..e69de29
diff --git a/Debug/Core/BASE/Protobuf/PSource/bsp_Cmd.pb.cyclo b/Debug/Core/BASE/Protobuf/PSource/bsp_Cmd.pb.cyclo
new file mode 100644
index 0000000..e69de29
diff --git a/Debug/Core/BASE/Protobuf/PSource/bsp_Cmd.pb.d b/Debug/Core/BASE/Protobuf/PSource/bsp_Cmd.pb.d
new file mode 100644
index 0000000..bab716b
--- /dev/null
+++ b/Debug/Core/BASE/Protobuf/PSource/bsp_Cmd.pb.d
@@ -0,0 +1,6 @@
+Core/BASE/Protobuf/PSource/bsp_Cmd.pb.o: \
+ ../Core/BASE/Protobuf/PSource/bsp_Cmd.pb.c \
+ ../Core/BASE/Protobuf/PSource/bsp_Cmd.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h
+../Core/BASE/Protobuf/PSource/bsp_Cmd.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
diff --git a/Debug/Core/BASE/Protobuf/PSource/bsp_Cmd.pb.o b/Debug/Core/BASE/Protobuf/PSource/bsp_Cmd.pb.o
new file mode 100644
index 0000000..3593b29
Binary files /dev/null and b/Debug/Core/BASE/Protobuf/PSource/bsp_Cmd.pb.o differ
diff --git a/Debug/Core/BASE/Protobuf/PSource/bsp_Cmd.pb.su b/Debug/Core/BASE/Protobuf/PSource/bsp_Cmd.pb.su
new file mode 100644
index 0000000..e69de29
diff --git a/Debug/Core/BASE/Protobuf/PSource/bsp_Error.pb.cyclo b/Debug/Core/BASE/Protobuf/PSource/bsp_Error.pb.cyclo
new file mode 100644
index 0000000..e69de29
diff --git a/Debug/Core/BASE/Protobuf/PSource/bsp_Error.pb.d b/Debug/Core/BASE/Protobuf/PSource/bsp_Error.pb.d
new file mode 100644
index 0000000..45f8dff
--- /dev/null
+++ b/Debug/Core/BASE/Protobuf/PSource/bsp_Error.pb.d
@@ -0,0 +1,6 @@
+Core/BASE/Protobuf/PSource/bsp_Error.pb.o: \
+ ../Core/BASE/Protobuf/PSource/bsp_Error.pb.c \
+ ../Core/BASE/Protobuf/PSource/bsp_Error.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h
+../Core/BASE/Protobuf/PSource/bsp_Error.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
diff --git a/Debug/Core/BASE/Protobuf/PSource/bsp_Error.pb.o b/Debug/Core/BASE/Protobuf/PSource/bsp_Error.pb.o
new file mode 100644
index 0000000..c859b47
Binary files /dev/null and b/Debug/Core/BASE/Protobuf/PSource/bsp_Error.pb.o differ
diff --git a/Debug/Core/BASE/Protobuf/PSource/bsp_Error.pb.su b/Debug/Core/BASE/Protobuf/PSource/bsp_Error.pb.su
new file mode 100644
index 0000000..e69de29
diff --git a/Debug/Core/BASE/Protobuf/PSource/bsp_GV.pb.cyclo b/Debug/Core/BASE/Protobuf/PSource/bsp_GV.pb.cyclo
new file mode 100644
index 0000000..e69de29
diff --git a/Debug/Core/BASE/Protobuf/PSource/bsp_GV.pb.d b/Debug/Core/BASE/Protobuf/PSource/bsp_GV.pb.d
new file mode 100644
index 0000000..cc3fcc0
--- /dev/null
+++ b/Debug/Core/BASE/Protobuf/PSource/bsp_GV.pb.d
@@ -0,0 +1,24 @@
+Core/BASE/Protobuf/PSource/bsp_GV.pb.o: \
+ ../Core/BASE/Protobuf/PSource/bsp_GV.pb.c \
+ ../Core/BASE/Protobuf/PSource/bsp_GV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ ../Core/BASE/Protobuf/PSource/msp_MK32.pb.h \
+ ../Core/BASE/Protobuf/PSource/msp_Motor.pb.h \
+ ../Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.h \
+ ../Core/BASE/Protobuf/PSource/msp_TL720D.pb.h \
+ ../Core/BASE/Protobuf/PSource/bsp_Error.pb.h \
+ ../Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.h \
+ ../Core/BASE/Protobuf/PSource/bsp_IO.pb.h \
+ ../Core/BASE/Protobuf/PSource/msp_CMCU.pb.h \
+ ../Core/BASE/Protobuf/PSource/msp_KS206.pb.h
+../Core/BASE/Protobuf/PSource/bsp_GV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+../Core/BASE/Protobuf/PSource/msp_MK32.pb.h:
+../Core/BASE/Protobuf/PSource/msp_Motor.pb.h:
+../Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.h:
+../Core/BASE/Protobuf/PSource/msp_TL720D.pb.h:
+../Core/BASE/Protobuf/PSource/bsp_Error.pb.h:
+../Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.h:
+../Core/BASE/Protobuf/PSource/bsp_IO.pb.h:
+../Core/BASE/Protobuf/PSource/msp_CMCU.pb.h:
+../Core/BASE/Protobuf/PSource/msp_KS206.pb.h:
diff --git a/Debug/Core/BASE/Protobuf/PSource/bsp_GV.pb.o b/Debug/Core/BASE/Protobuf/PSource/bsp_GV.pb.o
new file mode 100644
index 0000000..0252bab
Binary files /dev/null and b/Debug/Core/BASE/Protobuf/PSource/bsp_GV.pb.o differ
diff --git a/Debug/Core/BASE/Protobuf/PSource/bsp_GV.pb.su b/Debug/Core/BASE/Protobuf/PSource/bsp_GV.pb.su
new file mode 100644
index 0000000..e69de29
diff --git a/Debug/Core/BASE/Protobuf/PSource/bsp_IAP.pb.cyclo b/Debug/Core/BASE/Protobuf/PSource/bsp_IAP.pb.cyclo
new file mode 100644
index 0000000..e69de29
diff --git a/Debug/Core/BASE/Protobuf/PSource/bsp_IAP.pb.d b/Debug/Core/BASE/Protobuf/PSource/bsp_IAP.pb.d
new file mode 100644
index 0000000..9023f76
--- /dev/null
+++ b/Debug/Core/BASE/Protobuf/PSource/bsp_IAP.pb.d
@@ -0,0 +1,6 @@
+Core/BASE/Protobuf/PSource/bsp_IAP.pb.o: \
+ ../Core/BASE/Protobuf/PSource/bsp_IAP.pb.c \
+ ../Core/BASE/Protobuf/PSource/bsp_IAP.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h
+../Core/BASE/Protobuf/PSource/bsp_IAP.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
diff --git a/Debug/Core/BASE/Protobuf/PSource/bsp_IAP.pb.o b/Debug/Core/BASE/Protobuf/PSource/bsp_IAP.pb.o
new file mode 100644
index 0000000..8b12c59
Binary files /dev/null and b/Debug/Core/BASE/Protobuf/PSource/bsp_IAP.pb.o differ
diff --git a/Debug/Core/BASE/Protobuf/PSource/bsp_IAP.pb.su b/Debug/Core/BASE/Protobuf/PSource/bsp_IAP.pb.su
new file mode 100644
index 0000000..e69de29
diff --git a/Debug/Core/BASE/Protobuf/PSource/bsp_IO.pb.cyclo b/Debug/Core/BASE/Protobuf/PSource/bsp_IO.pb.cyclo
new file mode 100644
index 0000000..e69de29
diff --git a/Debug/Core/BASE/Protobuf/PSource/bsp_IO.pb.d b/Debug/Core/BASE/Protobuf/PSource/bsp_IO.pb.d
new file mode 100644
index 0000000..895edf6
--- /dev/null
+++ b/Debug/Core/BASE/Protobuf/PSource/bsp_IO.pb.d
@@ -0,0 +1,6 @@
+Core/BASE/Protobuf/PSource/bsp_IO.pb.o: \
+ ../Core/BASE/Protobuf/PSource/bsp_IO.pb.c \
+ ../Core/BASE/Protobuf/PSource/bsp_IO.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h
+../Core/BASE/Protobuf/PSource/bsp_IO.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
diff --git a/Debug/Core/BASE/Protobuf/PSource/bsp_IO.pb.o b/Debug/Core/BASE/Protobuf/PSource/bsp_IO.pb.o
new file mode 100644
index 0000000..ab89e92
Binary files /dev/null and b/Debug/Core/BASE/Protobuf/PSource/bsp_IO.pb.o differ
diff --git a/Debug/Core/BASE/Protobuf/PSource/bsp_IO.pb.su b/Debug/Core/BASE/Protobuf/PSource/bsp_IO.pb.su
new file mode 100644
index 0000000..e69de29
diff --git a/Debug/Core/BASE/Protobuf/PSource/bsp_IV.pb.cyclo b/Debug/Core/BASE/Protobuf/PSource/bsp_IV.pb.cyclo
new file mode 100644
index 0000000..e69de29
diff --git a/Debug/Core/BASE/Protobuf/PSource/bsp_IV.pb.d b/Debug/Core/BASE/Protobuf/PSource/bsp_IV.pb.d
new file mode 100644
index 0000000..ef76037
--- /dev/null
+++ b/Debug/Core/BASE/Protobuf/PSource/bsp_IV.pb.d
@@ -0,0 +1,8 @@
+Core/BASE/Protobuf/PSource/bsp_IV.pb.o: \
+ ../Core/BASE/Protobuf/PSource/bsp_IV.pb.c \
+ ../Core/BASE/Protobuf/PSource/bsp_IV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ ../Core/BASE/Protobuf/PSource/bsp_PV.pb.h
+../Core/BASE/Protobuf/PSource/bsp_IV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+../Core/BASE/Protobuf/PSource/bsp_PV.pb.h:
diff --git a/Debug/Core/BASE/Protobuf/PSource/bsp_IV.pb.o b/Debug/Core/BASE/Protobuf/PSource/bsp_IV.pb.o
new file mode 100644
index 0000000..a9dc147
Binary files /dev/null and b/Debug/Core/BASE/Protobuf/PSource/bsp_IV.pb.o differ
diff --git a/Debug/Core/BASE/Protobuf/PSource/bsp_IV.pb.su b/Debug/Core/BASE/Protobuf/PSource/bsp_IV.pb.su
new file mode 100644
index 0000000..e69de29
diff --git a/Debug/Core/BASE/Protobuf/PSource/bsp_PV.pb.cyclo b/Debug/Core/BASE/Protobuf/PSource/bsp_PV.pb.cyclo
new file mode 100644
index 0000000..e69de29
diff --git a/Debug/Core/BASE/Protobuf/PSource/bsp_PV.pb.d b/Debug/Core/BASE/Protobuf/PSource/bsp_PV.pb.d
new file mode 100644
index 0000000..1f7e6c7
--- /dev/null
+++ b/Debug/Core/BASE/Protobuf/PSource/bsp_PV.pb.d
@@ -0,0 +1,6 @@
+Core/BASE/Protobuf/PSource/bsp_PV.pb.o: \
+ ../Core/BASE/Protobuf/PSource/bsp_PV.pb.c \
+ ../Core/BASE/Protobuf/PSource/bsp_PV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h
+../Core/BASE/Protobuf/PSource/bsp_PV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
diff --git a/Debug/Core/BASE/Protobuf/PSource/bsp_PV.pb.o b/Debug/Core/BASE/Protobuf/PSource/bsp_PV.pb.o
new file mode 100644
index 0000000..5c44ced
Binary files /dev/null and b/Debug/Core/BASE/Protobuf/PSource/bsp_PV.pb.o differ
diff --git a/Debug/Core/BASE/Protobuf/PSource/bsp_PV.pb.su b/Debug/Core/BASE/Protobuf/PSource/bsp_PV.pb.su
new file mode 100644
index 0000000..e69de29
diff --git a/Debug/Core/BASE/Protobuf/PSource/bsp_ReCmd.pb.cyclo b/Debug/Core/BASE/Protobuf/PSource/bsp_ReCmd.pb.cyclo
new file mode 100644
index 0000000..e69de29
diff --git a/Debug/Core/BASE/Protobuf/PSource/bsp_ReCmd.pb.d b/Debug/Core/BASE/Protobuf/PSource/bsp_ReCmd.pb.d
new file mode 100644
index 0000000..1da274d
--- /dev/null
+++ b/Debug/Core/BASE/Protobuf/PSource/bsp_ReCmd.pb.d
@@ -0,0 +1,6 @@
+Core/BASE/Protobuf/PSource/bsp_ReCmd.pb.o: \
+ ../Core/BASE/Protobuf/PSource/bsp_ReCmd.pb.c \
+ ../Core/BASE/Protobuf/PSource/bsp_ReCmd.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h
+../Core/BASE/Protobuf/PSource/bsp_ReCmd.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
diff --git a/Debug/Core/BASE/Protobuf/PSource/bsp_ReCmd.pb.o b/Debug/Core/BASE/Protobuf/PSource/bsp_ReCmd.pb.o
new file mode 100644
index 0000000..6b82cea
Binary files /dev/null and b/Debug/Core/BASE/Protobuf/PSource/bsp_ReCmd.pb.o differ
diff --git a/Debug/Core/BASE/Protobuf/PSource/bsp_ReCmd.pb.su b/Debug/Core/BASE/Protobuf/PSource/bsp_ReCmd.pb.su
new file mode 100644
index 0000000..e69de29
diff --git a/Debug/Core/BASE/Protobuf/PSource/msp_CMCU.pb.cyclo b/Debug/Core/BASE/Protobuf/PSource/msp_CMCU.pb.cyclo
new file mode 100644
index 0000000..e69de29
diff --git a/Debug/Core/BASE/Protobuf/PSource/msp_CMCU.pb.d b/Debug/Core/BASE/Protobuf/PSource/msp_CMCU.pb.d
new file mode 100644
index 0000000..f5824ab
--- /dev/null
+++ b/Debug/Core/BASE/Protobuf/PSource/msp_CMCU.pb.d
@@ -0,0 +1,6 @@
+Core/BASE/Protobuf/PSource/msp_CMCU.pb.o: \
+ ../Core/BASE/Protobuf/PSource/msp_CMCU.pb.c \
+ ../Core/BASE/Protobuf/PSource/msp_CMCU.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h
+../Core/BASE/Protobuf/PSource/msp_CMCU.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
diff --git a/Debug/Core/BASE/Protobuf/PSource/msp_CMCU.pb.o b/Debug/Core/BASE/Protobuf/PSource/msp_CMCU.pb.o
new file mode 100644
index 0000000..0a40a07
Binary files /dev/null and b/Debug/Core/BASE/Protobuf/PSource/msp_CMCU.pb.o differ
diff --git a/Debug/Core/BASE/Protobuf/PSource/msp_CMCU.pb.su b/Debug/Core/BASE/Protobuf/PSource/msp_CMCU.pb.su
new file mode 100644
index 0000000..e69de29
diff --git a/Debug/Core/BASE/Protobuf/PSource/msp_KS206.pb.cyclo b/Debug/Core/BASE/Protobuf/PSource/msp_KS206.pb.cyclo
new file mode 100644
index 0000000..e69de29
diff --git a/Debug/Core/BASE/Protobuf/PSource/msp_KS206.pb.d b/Debug/Core/BASE/Protobuf/PSource/msp_KS206.pb.d
new file mode 100644
index 0000000..177a4bd
--- /dev/null
+++ b/Debug/Core/BASE/Protobuf/PSource/msp_KS206.pb.d
@@ -0,0 +1,6 @@
+Core/BASE/Protobuf/PSource/msp_KS206.pb.o: \
+ ../Core/BASE/Protobuf/PSource/msp_KS206.pb.c \
+ ../Core/BASE/Protobuf/PSource/msp_KS206.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h
+../Core/BASE/Protobuf/PSource/msp_KS206.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
diff --git a/Debug/Core/BASE/Protobuf/PSource/msp_KS206.pb.o b/Debug/Core/BASE/Protobuf/PSource/msp_KS206.pb.o
new file mode 100644
index 0000000..7a364d8
Binary files /dev/null and b/Debug/Core/BASE/Protobuf/PSource/msp_KS206.pb.o differ
diff --git a/Debug/Core/BASE/Protobuf/PSource/msp_KS206.pb.su b/Debug/Core/BASE/Protobuf/PSource/msp_KS206.pb.su
new file mode 100644
index 0000000..e69de29
diff --git a/Debug/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.cyclo b/Debug/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.cyclo
new file mode 100644
index 0000000..e69de29
diff --git a/Debug/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.d b/Debug/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.d
new file mode 100644
index 0000000..81b8b1f
--- /dev/null
+++ b/Debug/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.d
@@ -0,0 +1,6 @@
+Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.o: \
+ ../Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.c \
+ ../Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h
+../Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
diff --git a/Debug/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.o b/Debug/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.o
new file mode 100644
index 0000000..961a97b
Binary files /dev/null and b/Debug/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.o differ
diff --git a/Debug/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.su b/Debug/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.su
new file mode 100644
index 0000000..e69de29
diff --git a/Debug/Core/BASE/Protobuf/PSource/msp_MK32.pb.cyclo b/Debug/Core/BASE/Protobuf/PSource/msp_MK32.pb.cyclo
new file mode 100644
index 0000000..e69de29
diff --git a/Debug/Core/BASE/Protobuf/PSource/msp_MK32.pb.d b/Debug/Core/BASE/Protobuf/PSource/msp_MK32.pb.d
new file mode 100644
index 0000000..ebbd460
--- /dev/null
+++ b/Debug/Core/BASE/Protobuf/PSource/msp_MK32.pb.d
@@ -0,0 +1,6 @@
+Core/BASE/Protobuf/PSource/msp_MK32.pb.o: \
+ ../Core/BASE/Protobuf/PSource/msp_MK32.pb.c \
+ ../Core/BASE/Protobuf/PSource/msp_MK32.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h
+../Core/BASE/Protobuf/PSource/msp_MK32.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
diff --git a/Debug/Core/BASE/Protobuf/PSource/msp_MK32.pb.o b/Debug/Core/BASE/Protobuf/PSource/msp_MK32.pb.o
new file mode 100644
index 0000000..dd230f4
Binary files /dev/null and b/Debug/Core/BASE/Protobuf/PSource/msp_MK32.pb.o differ
diff --git a/Debug/Core/BASE/Protobuf/PSource/msp_MK32.pb.su b/Debug/Core/BASE/Protobuf/PSource/msp_MK32.pb.su
new file mode 100644
index 0000000..e69de29
diff --git a/Debug/Core/BASE/Protobuf/PSource/msp_Motor.pb.cyclo b/Debug/Core/BASE/Protobuf/PSource/msp_Motor.pb.cyclo
new file mode 100644
index 0000000..e69de29
diff --git a/Debug/Core/BASE/Protobuf/PSource/msp_Motor.pb.d b/Debug/Core/BASE/Protobuf/PSource/msp_Motor.pb.d
new file mode 100644
index 0000000..3435df5
--- /dev/null
+++ b/Debug/Core/BASE/Protobuf/PSource/msp_Motor.pb.d
@@ -0,0 +1,6 @@
+Core/BASE/Protobuf/PSource/msp_Motor.pb.o: \
+ ../Core/BASE/Protobuf/PSource/msp_Motor.pb.c \
+ ../Core/BASE/Protobuf/PSource/msp_Motor.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h
+../Core/BASE/Protobuf/PSource/msp_Motor.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
diff --git a/Debug/Core/BASE/Protobuf/PSource/msp_Motor.pb.o b/Debug/Core/BASE/Protobuf/PSource/msp_Motor.pb.o
new file mode 100644
index 0000000..359184b
Binary files /dev/null and b/Debug/Core/BASE/Protobuf/PSource/msp_Motor.pb.o differ
diff --git a/Debug/Core/BASE/Protobuf/PSource/msp_Motor.pb.su b/Debug/Core/BASE/Protobuf/PSource/msp_Motor.pb.su
new file mode 100644
index 0000000..e69de29
diff --git a/Debug/Core/BASE/Protobuf/PSource/msp_TL720D.pb.cyclo b/Debug/Core/BASE/Protobuf/PSource/msp_TL720D.pb.cyclo
new file mode 100644
index 0000000..e69de29
diff --git a/Debug/Core/BASE/Protobuf/PSource/msp_TL720D.pb.d b/Debug/Core/BASE/Protobuf/PSource/msp_TL720D.pb.d
new file mode 100644
index 0000000..83a7a3c
--- /dev/null
+++ b/Debug/Core/BASE/Protobuf/PSource/msp_TL720D.pb.d
@@ -0,0 +1,6 @@
+Core/BASE/Protobuf/PSource/msp_TL720D.pb.o: \
+ ../Core/BASE/Protobuf/PSource/msp_TL720D.pb.c \
+ ../Core/BASE/Protobuf/PSource/msp_TL720D.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h
+../Core/BASE/Protobuf/PSource/msp_TL720D.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
diff --git a/Debug/Core/BASE/Protobuf/PSource/msp_TL720D.pb.o b/Debug/Core/BASE/Protobuf/PSource/msp_TL720D.pb.o
new file mode 100644
index 0000000..513093f
Binary files /dev/null and b/Debug/Core/BASE/Protobuf/PSource/msp_TL720D.pb.o differ
diff --git a/Debug/Core/BASE/Protobuf/PSource/msp_TL720D.pb.su b/Debug/Core/BASE/Protobuf/PSource/msp_TL720D.pb.su
new file mode 100644
index 0000000..e69de29
diff --git a/Debug/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.cyclo b/Debug/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.cyclo
new file mode 100644
index 0000000..e69de29
diff --git a/Debug/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.d b/Debug/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.d
new file mode 100644
index 0000000..b60b3b7
--- /dev/null
+++ b/Debug/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.d
@@ -0,0 +1,6 @@
+Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.o: \
+ ../Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.c \
+ ../Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h
+../Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
diff --git a/Debug/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.o b/Debug/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.o
new file mode 100644
index 0000000..be1c073
Binary files /dev/null and b/Debug/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.o differ
diff --git a/Debug/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.su b/Debug/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.su
new file mode 100644
index 0000000..e69de29
diff --git a/Debug/Core/BASE/Protobuf/PSource/subdir.mk b/Debug/Core/BASE/Protobuf/PSource/subdir.mk
new file mode 100644
index 0000000..8cbc4ef
--- /dev/null
+++ b/Debug/Core/BASE/Protobuf/PSource/subdir.mk
@@ -0,0 +1,72 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+# Toolchain: GNU Tools for STM32 (12.3.rel1)
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables 
+C_SRCS += \
+../Core/BASE/Protobuf/PSource/bsp_CV.pb.c \
+../Core/BASE/Protobuf/PSource/bsp_Cmd.pb.c \
+../Core/BASE/Protobuf/PSource/bsp_Error.pb.c \
+../Core/BASE/Protobuf/PSource/bsp_GV.pb.c \
+../Core/BASE/Protobuf/PSource/bsp_IAP.pb.c \
+../Core/BASE/Protobuf/PSource/bsp_IO.pb.c \
+../Core/BASE/Protobuf/PSource/bsp_IV.pb.c \
+../Core/BASE/Protobuf/PSource/bsp_PV.pb.c \
+../Core/BASE/Protobuf/PSource/bsp_ReCmd.pb.c \
+../Core/BASE/Protobuf/PSource/msp_CMCU.pb.c \
+../Core/BASE/Protobuf/PSource/msp_KS206.pb.c \
+../Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.c \
+../Core/BASE/Protobuf/PSource/msp_MK32.pb.c \
+../Core/BASE/Protobuf/PSource/msp_Motor.pb.c \
+../Core/BASE/Protobuf/PSource/msp_TL720D.pb.c \
+../Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.c 
+
+OBJS += \
+./Core/BASE/Protobuf/PSource/bsp_CV.pb.o \
+./Core/BASE/Protobuf/PSource/bsp_Cmd.pb.o \
+./Core/BASE/Protobuf/PSource/bsp_Error.pb.o \
+./Core/BASE/Protobuf/PSource/bsp_GV.pb.o \
+./Core/BASE/Protobuf/PSource/bsp_IAP.pb.o \
+./Core/BASE/Protobuf/PSource/bsp_IO.pb.o \
+./Core/BASE/Protobuf/PSource/bsp_IV.pb.o \
+./Core/BASE/Protobuf/PSource/bsp_PV.pb.o \
+./Core/BASE/Protobuf/PSource/bsp_ReCmd.pb.o \
+./Core/BASE/Protobuf/PSource/msp_CMCU.pb.o \
+./Core/BASE/Protobuf/PSource/msp_KS206.pb.o \
+./Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.o \
+./Core/BASE/Protobuf/PSource/msp_MK32.pb.o \
+./Core/BASE/Protobuf/PSource/msp_Motor.pb.o \
+./Core/BASE/Protobuf/PSource/msp_TL720D.pb.o \
+./Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.o 
+
+C_DEPS += \
+./Core/BASE/Protobuf/PSource/bsp_CV.pb.d \
+./Core/BASE/Protobuf/PSource/bsp_Cmd.pb.d \
+./Core/BASE/Protobuf/PSource/bsp_Error.pb.d \
+./Core/BASE/Protobuf/PSource/bsp_GV.pb.d \
+./Core/BASE/Protobuf/PSource/bsp_IAP.pb.d \
+./Core/BASE/Protobuf/PSource/bsp_IO.pb.d \
+./Core/BASE/Protobuf/PSource/bsp_IV.pb.d \
+./Core/BASE/Protobuf/PSource/bsp_PV.pb.d \
+./Core/BASE/Protobuf/PSource/bsp_ReCmd.pb.d \
+./Core/BASE/Protobuf/PSource/msp_CMCU.pb.d \
+./Core/BASE/Protobuf/PSource/msp_KS206.pb.d \
+./Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.d \
+./Core/BASE/Protobuf/PSource/msp_MK32.pb.d \
+./Core/BASE/Protobuf/PSource/msp_Motor.pb.d \
+./Core/BASE/Protobuf/PSource/msp_TL720D.pb.d \
+./Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.d 
+
+
+# Each subdirectory must supply rules for building sources it contributes
+Core/BASE/Protobuf/PSource/%.o Core/BASE/Protobuf/PSource/%.su Core/BASE/Protobuf/PSource/%.cyclo: ../Core/BASE/Protobuf/PSource/%.c Core/BASE/Protobuf/PSource/subdir.mk
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32H743xx -c -I../Core/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I../Drivers/CMSIS/Include -I"F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc" -I"F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource" -I"F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP" -I"F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
+
+clean: clean-Core-2f-BASE-2f-Protobuf-2f-PSource
+
+clean-Core-2f-BASE-2f-Protobuf-2f-PSource:
+	-$(RM) ./Core/BASE/Protobuf/PSource/bsp_CV.pb.cyclo ./Core/BASE/Protobuf/PSource/bsp_CV.pb.d ./Core/BASE/Protobuf/PSource/bsp_CV.pb.o ./Core/BASE/Protobuf/PSource/bsp_CV.pb.su ./Core/BASE/Protobuf/PSource/bsp_Cmd.pb.cyclo ./Core/BASE/Protobuf/PSource/bsp_Cmd.pb.d ./Core/BASE/Protobuf/PSource/bsp_Cmd.pb.o ./Core/BASE/Protobuf/PSource/bsp_Cmd.pb.su ./Core/BASE/Protobuf/PSource/bsp_Error.pb.cyclo ./Core/BASE/Protobuf/PSource/bsp_Error.pb.d ./Core/BASE/Protobuf/PSource/bsp_Error.pb.o ./Core/BASE/Protobuf/PSource/bsp_Error.pb.su ./Core/BASE/Protobuf/PSource/bsp_GV.pb.cyclo ./Core/BASE/Protobuf/PSource/bsp_GV.pb.d ./Core/BASE/Protobuf/PSource/bsp_GV.pb.o ./Core/BASE/Protobuf/PSource/bsp_GV.pb.su ./Core/BASE/Protobuf/PSource/bsp_IAP.pb.cyclo ./Core/BASE/Protobuf/PSource/bsp_IAP.pb.d ./Core/BASE/Protobuf/PSource/bsp_IAP.pb.o ./Core/BASE/Protobuf/PSource/bsp_IAP.pb.su ./Core/BASE/Protobuf/PSource/bsp_IO.pb.cyclo ./Core/BASE/Protobuf/PSource/bsp_IO.pb.d ./Core/BASE/Protobuf/PSource/bsp_IO.pb.o ./Core/BASE/Protobuf/PSource/bsp_IO.pb.su ./Core/BASE/Protobuf/PSource/bsp_IV.pb.cyclo ./Core/BASE/Protobuf/PSource/bsp_IV.pb.d ./Core/BASE/Protobuf/PSource/bsp_IV.pb.o ./Core/BASE/Protobuf/PSource/bsp_IV.pb.su ./Core/BASE/Protobuf/PSource/bsp_PV.pb.cyclo ./Core/BASE/Protobuf/PSource/bsp_PV.pb.d ./Core/BASE/Protobuf/PSource/bsp_PV.pb.o ./Core/BASE/Protobuf/PSource/bsp_PV.pb.su ./Core/BASE/Protobuf/PSource/bsp_ReCmd.pb.cyclo ./Core/BASE/Protobuf/PSource/bsp_ReCmd.pb.d ./Core/BASE/Protobuf/PSource/bsp_ReCmd.pb.o ./Core/BASE/Protobuf/PSource/bsp_ReCmd.pb.su ./Core/BASE/Protobuf/PSource/msp_CMCU.pb.cyclo ./Core/BASE/Protobuf/PSource/msp_CMCU.pb.d ./Core/BASE/Protobuf/PSource/msp_CMCU.pb.o ./Core/BASE/Protobuf/PSource/msp_CMCU.pb.su ./Core/BASE/Protobuf/PSource/msp_KS206.pb.cyclo ./Core/BASE/Protobuf/PSource/msp_KS206.pb.d ./Core/BASE/Protobuf/PSource/msp_KS206.pb.o ./Core/BASE/Protobuf/PSource/msp_KS206.pb.su ./Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.cyclo ./Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.d ./Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.o ./Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.su ./Core/BASE/Protobuf/PSource/msp_MK32.pb.cyclo ./Core/BASE/Protobuf/PSource/msp_MK32.pb.d ./Core/BASE/Protobuf/PSource/msp_MK32.pb.o ./Core/BASE/Protobuf/PSource/msp_MK32.pb.su ./Core/BASE/Protobuf/PSource/msp_Motor.pb.cyclo ./Core/BASE/Protobuf/PSource/msp_Motor.pb.d ./Core/BASE/Protobuf/PSource/msp_Motor.pb.o ./Core/BASE/Protobuf/PSource/msp_Motor.pb.su ./Core/BASE/Protobuf/PSource/msp_TL720D.pb.cyclo ./Core/BASE/Protobuf/PSource/msp_TL720D.pb.d ./Core/BASE/Protobuf/PSource/msp_TL720D.pb.o ./Core/BASE/Protobuf/PSource/msp_TL720D.pb.su ./Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.cyclo ./Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.d ./Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.o ./Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.su
+
+.PHONY: clean-Core-2f-BASE-2f-Protobuf-2f-PSource
+
diff --git a/Debug/Core/BASE/Src/BSP/BHBF_ROBOT.cyclo b/Debug/Core/BASE/Src/BSP/BHBF_ROBOT.cyclo
new file mode 100644
index 0000000..315ad5b
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/BHBF_ROBOT.cyclo
@@ -0,0 +1,7 @@
+../Core/BASE/Src/BSP/BHBF_ROBOT.c:46:6:SET_BIT_1	1
+../Core/BASE/Src/BSP/BHBF_ROBOT.c:50:6:SET_BIT_0	1
+../Core/BASE/Src/BSP/BHBF_ROBOT.c:54:9:Get_BIT	1
+../Core/BASE/Src/BSP/BHBF_ROBOT.c:61:6:SystemTimer_Intialize	1
+../Core/BASE/Src/BSP/BHBF_ROBOT.c:68:6:GF_Timer_Count	1
+../Core/BASE/Src/BSP/BHBF_ROBOT.c:90:6:CompareTimer	4
+../Core/BASE/Src/BSP/BHBF_ROBOT.c:106:6:CompareTimer_Delay	4
diff --git a/Debug/Core/BASE/Src/BSP/BHBF_ROBOT.d b/Debug/Core/BASE/Src/BSP/BHBF_ROBOT.d
new file mode 100644
index 0000000..8a6aa07
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/BHBF_ROBOT.d
@@ -0,0 +1,204 @@
+Core/BASE/Src/BSP/BHBF_ROBOT.o: ../Core/BASE/Src/BSP/BHBF_ROBOT.c \
+ ../Core/Inc/fsm.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ ../Core/Inc/main.h ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
+ ../Core/Inc/dma.h ../Core/Inc/main.h ../Core/Inc/fdcan.h \
+ ../Core/Inc/i2c.h ../Core/Inc/tim.h ../Core/Inc/usart.h \
+ ../Core/Inc/gpio.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_CV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IAP.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_GPIO.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_com_helper.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_TIMER.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_GV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_TL720D.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IO.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_CMCU.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_common.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTuc.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTucConfig.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_JTBATTERY.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UART.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_pb_decode_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TL720D.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_MK32_1.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_WH_LTE_7S0.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_DLT_Log.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UDP.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_cpu_flash.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_qspi_w25q128.h \
+ ../Core/Inc/quadspi.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UpperComputer_Handler.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TTMotor_ZQ.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_Error_Detect.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IV.pb.h
+../Core/Inc/fsm.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+../Core/Inc/main.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
+../Core/Inc/dma.h:
+../Core/Inc/main.h:
+../Core/Inc/fdcan.h:
+../Core/Inc/i2c.h:
+../Core/Inc/tim.h:
+../Core/Inc/usart.h:
+../Core/Inc/gpio.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_CV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IAP.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_GPIO.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_com_helper.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_TIMER.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_GV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_TL720D.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IO.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_CMCU.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_common.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTuc.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTucConfig.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_JTBATTERY.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UART.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_pb_decode_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TL720D.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_MK32_1.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_WH_LTE_7S0.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_DLT_Log.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UDP.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_cpu_flash.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_qspi_w25q128.h:
+../Core/Inc/quadspi.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UpperComputer_Handler.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TTMotor_ZQ.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_Error_Detect.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IV.pb.h:
diff --git a/Debug/Core/BASE/Src/BSP/BHBF_ROBOT.o b/Debug/Core/BASE/Src/BSP/BHBF_ROBOT.o
new file mode 100644
index 0000000..1f5712c
Binary files /dev/null and b/Debug/Core/BASE/Src/BSP/BHBF_ROBOT.o differ
diff --git a/Debug/Core/BASE/Src/BSP/BHBF_ROBOT.su b/Debug/Core/BASE/Src/BSP/BHBF_ROBOT.su
new file mode 100644
index 0000000..97e165f
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/BHBF_ROBOT.su
@@ -0,0 +1,7 @@
+../Core/BASE/Src/BSP/BHBF_ROBOT.c:46:6:SET_BIT_1	16	static
+../Core/BASE/Src/BSP/BHBF_ROBOT.c:50:6:SET_BIT_0	16	static
+../Core/BASE/Src/BSP/BHBF_ROBOT.c:54:9:Get_BIT	16	static
+../Core/BASE/Src/BSP/BHBF_ROBOT.c:61:6:SystemTimer_Intialize	8	static
+../Core/BASE/Src/BSP/BHBF_ROBOT.c:68:6:GF_Timer_Count	4	static
+../Core/BASE/Src/BSP/BHBF_ROBOT.c:90:6:CompareTimer	16	static
+../Core/BASE/Src/BSP/BHBF_ROBOT.c:106:6:CompareTimer_Delay	32	static
diff --git a/Debug/Core/BASE/Src/BSP/DLT/DLTuc.cyclo b/Debug/Core/BASE/Src/BSP/DLT/DLTuc.cyclo
new file mode 100644
index 0000000..4435104
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/DLT/DLTuc.cyclo
@@ -0,0 +1,12 @@
+../Core/BASE/Src/BSP/DLT/DLTuc.c:220:18:DLT_RB_Receive_GetNextMessageAddress	2
+../Core/BASE/Src/BSP/DLT/DLTuc.c:250:18:DLT_RB_Receive_Read	3
+../Core/BASE/Src/BSP/DLT/DLTuc.c:278:18:DLT_RB_TransmitRead	3
+../Core/BASE/Src/BSP/DLT/DLTuc.c:305:18:DLT_RB_GetNextWriteIndex	2
+../Core/BASE/Src/BSP/DLT/DLTuc.c:326:13:PrepareDltHeader	3
+../Core/BASE/Src/BSP/DLT/DLTuc.c:424:6:DLTuc_RawDataReceiveDone	15
+../Core/BASE/Src/BSP/DLT/DLTuc.c:493:6:DLTuc_RegisterInjectionDataReceivedCb	1
+../Core/BASE/Src/BSP/DLT/DLTuc.c:499:6:DLTuc_RegisterReceiveSerialDataFunction	2
+../Core/BASE/Src/BSP/DLT/DLTuc.c:509:6:DLTuc_RegisterTransmitSerialDataFunction	2
+../Core/BASE/Src/BSP/DLT/DLTuc.c:524:6:DLTuc_MessageTransmitDone	7
+../Core/BASE/Src/BSP/DLT/DLTuc.c:565:6:DLTuc_LogOutVarArgs	6
+../Core/BASE/Src/BSP/DLT/DLTuc.c:631:6:DLTuc_RegisterGetTimeStampMsCallback	1
diff --git a/Debug/Core/BASE/Src/BSP/DLT/DLTuc.d b/Debug/Core/BASE/Src/BSP/DLT/DLTuc.d
new file mode 100644
index 0000000..269bb79
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/DLT/DLTuc.d
@@ -0,0 +1,5 @@
+Core/BASE/Src/BSP/DLT/DLTuc.o: ../Core/BASE/Src/BSP/DLT/DLTuc.c \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTuc.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTucConfig.h
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTuc.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTucConfig.h:
diff --git a/Debug/Core/BASE/Src/BSP/DLT/DLTuc.o b/Debug/Core/BASE/Src/BSP/DLT/DLTuc.o
new file mode 100644
index 0000000..e0fa69d
Binary files /dev/null and b/Debug/Core/BASE/Src/BSP/DLT/DLTuc.o differ
diff --git a/Debug/Core/BASE/Src/BSP/DLT/DLTuc.su b/Debug/Core/BASE/Src/BSP/DLT/DLTuc.su
new file mode 100644
index 0000000..d46ca54
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/DLT/DLTuc.su
@@ -0,0 +1,12 @@
+../Core/BASE/Src/BSP/DLT/DLTuc.c:220:18:DLT_RB_Receive_GetNextMessageAddress	24	static
+../Core/BASE/Src/BSP/DLT/DLTuc.c:250:18:DLT_RB_Receive_Read	24	static
+../Core/BASE/Src/BSP/DLT/DLTuc.c:278:18:DLT_RB_TransmitRead	24	static
+../Core/BASE/Src/BSP/DLT/DLTuc.c:305:18:DLT_RB_GetNextWriteIndex	24	static
+../Core/BASE/Src/BSP/DLT/DLTuc.c:326:13:PrepareDltHeader	32	static
+../Core/BASE/Src/BSP/DLT/DLTuc.c:424:6:DLTuc_RawDataReceiveDone	64	static
+../Core/BASE/Src/BSP/DLT/DLTuc.c:493:6:DLTuc_RegisterInjectionDataReceivedCb	16	static
+../Core/BASE/Src/BSP/DLT/DLTuc.c:499:6:DLTuc_RegisterReceiveSerialDataFunction	16	static
+../Core/BASE/Src/BSP/DLT/DLTuc.c:509:6:DLTuc_RegisterTransmitSerialDataFunction	32	static
+../Core/BASE/Src/BSP/DLT/DLTuc.c:524:6:DLTuc_MessageTransmitDone	24	static
+../Core/BASE/Src/BSP/DLT/DLTuc.c:565:6:DLTuc_LogOutVarArgs	52	static
+../Core/BASE/Src/BSP/DLT/DLTuc.c:631:6:DLTuc_RegisterGetTimeStampMsCallback	16	static
diff --git a/Debug/Core/BASE/Src/BSP/DLT/subdir.mk b/Debug/Core/BASE/Src/BSP/DLT/subdir.mk
new file mode 100644
index 0000000..61b1be0
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/DLT/subdir.mk
@@ -0,0 +1,27 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+# Toolchain: GNU Tools for STM32 (12.3.rel1)
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables 
+C_SRCS += \
+../Core/BASE/Src/BSP/DLT/DLTuc.c 
+
+OBJS += \
+./Core/BASE/Src/BSP/DLT/DLTuc.o 
+
+C_DEPS += \
+./Core/BASE/Src/BSP/DLT/DLTuc.d 
+
+
+# Each subdirectory must supply rules for building sources it contributes
+Core/BASE/Src/BSP/DLT/%.o Core/BASE/Src/BSP/DLT/%.su Core/BASE/Src/BSP/DLT/%.cyclo: ../Core/BASE/Src/BSP/DLT/%.c Core/BASE/Src/BSP/DLT/subdir.mk
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32H743xx -c -I../Core/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I../Drivers/CMSIS/Include -I"F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc" -I"F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource" -I"F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP" -I"F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
+
+clean: clean-Core-2f-BASE-2f-Src-2f-BSP-2f-DLT
+
+clean-Core-2f-BASE-2f-Src-2f-BSP-2f-DLT:
+	-$(RM) ./Core/BASE/Src/BSP/DLT/DLTuc.cyclo ./Core/BASE/Src/BSP/DLT/DLTuc.d ./Core/BASE/Src/BSP/DLT/DLTuc.o ./Core/BASE/Src/BSP/DLT/DLTuc.su
+
+.PHONY: clean-Core-2f-BASE-2f-Src-2f-BSP-2f-DLT
+
diff --git a/Debug/Core/BASE/Src/BSP/bsp_DLT_Log.cyclo b/Debug/Core/BASE/Src/BSP/bsp_DLT_Log.cyclo
new file mode 100644
index 0000000..56e10aa
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/bsp_DLT_Log.cyclo
@@ -0,0 +1,6 @@
+../Core/BASE/Src/BSP/bsp_DLT_Log.c:24:6:dLT_Log_intialize	1
+../Core/BASE/Src/BSP/bsp_DLT_Log.c:43:6:DLT_DataTransmit	1
+../Core/BASE/Src/BSP/bsp_DLT_Log.c:53:6:DLT_DataReceiveEndCallback	1
+../Core/BASE/Src/BSP/bsp_DLT_Log.c:73:6:DLT_LowLevelReceiveDmaToIdle	1
+../Core/BASE/Src/BSP/bsp_DLT_Log.c:80:6:DltInjectDataRcvd	2
+../Core/BASE/Src/BSP/bsp_DLT_Log.c:88:10:GetSysTime	1
diff --git a/Debug/Core/BASE/Src/BSP/bsp_DLT_Log.d b/Debug/Core/BASE/Src/BSP/bsp_DLT_Log.d
new file mode 100644
index 0000000..1663480
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/bsp_DLT_Log.d
@@ -0,0 +1,204 @@
+Core/BASE/Src/BSP/bsp_DLT_Log.o: ../Core/BASE/Src/BSP/bsp_DLT_Log.c \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_DLT_Log.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ ../Core/Inc/main.h ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
+ ../Core/Inc/dma.h ../Core/Inc/main.h ../Core/Inc/fdcan.h \
+ ../Core/Inc/i2c.h ../Core/Inc/tim.h ../Core/Inc/usart.h \
+ ../Core/Inc/gpio.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_CV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IAP.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_GPIO.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_com_helper.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_TIMER.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_GV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_TL720D.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IO.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_CMCU.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_common.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTuc.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTucConfig.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_JTBATTERY.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UART.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_pb_decode_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TL720D.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_MK32_1.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_WH_LTE_7S0.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_DLT_Log.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UDP.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_cpu_flash.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_qspi_w25q128.h \
+ ../Core/Inc/quadspi.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UpperComputer_Handler.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TTMotor_ZQ.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h \
+ ../Core/Inc/fsm.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_Error_Detect.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IV.pb.h
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_DLT_Log.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+../Core/Inc/main.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
+../Core/Inc/dma.h:
+../Core/Inc/main.h:
+../Core/Inc/fdcan.h:
+../Core/Inc/i2c.h:
+../Core/Inc/tim.h:
+../Core/Inc/usart.h:
+../Core/Inc/gpio.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_CV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IAP.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_GPIO.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_com_helper.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_TIMER.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_GV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_TL720D.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IO.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_CMCU.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_common.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTuc.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTucConfig.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_JTBATTERY.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UART.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_pb_decode_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TL720D.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_MK32_1.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_WH_LTE_7S0.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_DLT_Log.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UDP.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_cpu_flash.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_qspi_w25q128.h:
+../Core/Inc/quadspi.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UpperComputer_Handler.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TTMotor_ZQ.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h:
+../Core/Inc/fsm.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_Error_Detect.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IV.pb.h:
diff --git a/Debug/Core/BASE/Src/BSP/bsp_DLT_Log.o b/Debug/Core/BASE/Src/BSP/bsp_DLT_Log.o
new file mode 100644
index 0000000..a8b7fde
Binary files /dev/null and b/Debug/Core/BASE/Src/BSP/bsp_DLT_Log.o differ
diff --git a/Debug/Core/BASE/Src/BSP/bsp_DLT_Log.su b/Debug/Core/BASE/Src/BSP/bsp_DLT_Log.su
new file mode 100644
index 0000000..dd485d7
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/bsp_DLT_Log.su
@@ -0,0 +1,6 @@
+../Core/BASE/Src/BSP/bsp_DLT_Log.c:24:6:dLT_Log_intialize	16	static
+../Core/BASE/Src/BSP/bsp_DLT_Log.c:43:6:DLT_DataTransmit	32	static
+../Core/BASE/Src/BSP/bsp_DLT_Log.c:53:6:DLT_DataReceiveEndCallback	16	static
+../Core/BASE/Src/BSP/bsp_DLT_Log.c:73:6:DLT_LowLevelReceiveDmaToIdle	16	static
+../Core/BASE/Src/BSP/bsp_DLT_Log.c:80:6:DltInjectDataRcvd	40	static
+../Core/BASE/Src/BSP/bsp_DLT_Log.c:88:10:GetSysTime	8	static
diff --git a/Debug/Core/BASE/Src/BSP/bsp_EEPROM.cyclo b/Debug/Core/BASE/Src/BSP/bsp_EEPROM.cyclo
new file mode 100644
index 0000000..aa774af
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/bsp_EEPROM.cyclo
@@ -0,0 +1,20 @@
+../Core/BASE/Src/BSP/bsp_EEPROM.c:38:9:GF_BSP_EEPROM_Init	1
+../Core/BASE/Src/BSP/bsp_EEPROM.c:52:6:bsp_InitI2C	1
+../Core/BASE/Src/BSP/bsp_EEPROM.c:79:13:i2c_Delay	1
+../Core/BASE/Src/BSP/bsp_EEPROM.c:92:6:i2c_Start	1
+../Core/BASE/Src/BSP/bsp_EEPROM.c:113:6:i2c_Stop	1
+../Core/BASE/Src/BSP/bsp_EEPROM.c:132:6:i2c_SendByte	4
+../Core/BASE/Src/BSP/bsp_EEPROM.c:168:9:i2c_ReadByte	3
+../Core/BASE/Src/BSP/bsp_EEPROM.c:198:9:i2c_WaitAck	2
+../Core/BASE/Src/BSP/bsp_EEPROM.c:227:6:i2c_Ack	1
+../Core/BASE/Src/BSP/bsp_EEPROM.c:248:6:i2c_NAck	1
+../Core/BASE/Src/BSP/bsp_EEPROM.c:266:9:i2c_CheckDevice	3
+../Core/BASE/Src/BSP/bsp_EEPROM.c:293:9:GF_BSP_EEPROM_CheckOK	2
+../Core/BASE/Src/BSP/bsp_EEPROM.c:318:9:GF_BSP_EEPROM_ReadBytes	7
+../Core/BASE/Src/BSP/bsp_EEPROM.c:407:9:GF_BSP_EEPROM_WriteBytes	13
+../Core/BASE/Src/BSP/bsp_EEPROM.c:526:18:GF_BSP_EEPROM_Get_CV	1
+../Core/BASE/Src/BSP/bsp_EEPROM.c:535:9:GF_BSP_EEPROM_Set_CV	1
+../Core/BASE/Src/BSP/bsp_EEPROM.c:541:19:GF_BSP_EEPROM_Get_IAP	1
+../Core/BASE/Src/BSP/bsp_EEPROM.c:550:9:GF_BSP_EEPROM_Set_IAP	1
+../Core/BASE/Src/BSP/bsp_EEPROM.c:556:18:GF_BSP_EEPROM_Get_PV	1
+../Core/BASE/Src/BSP/bsp_EEPROM.c:564:9:GF_BSP_EEPROM_Set_PV	1
diff --git a/Debug/Core/BASE/Src/BSP/bsp_EEPROM.d b/Debug/Core/BASE/Src/BSP/bsp_EEPROM.d
new file mode 100644
index 0000000..4bc20c5
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/bsp_EEPROM.d
@@ -0,0 +1,146 @@
+Core/BASE/Src/BSP/bsp_EEPROM.o: ../Core/BASE/Src/BSP/bsp_EEPROM.c \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ ../Core/Inc/main.h ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
+ ../Core/Inc/dma.h ../Core/Inc/main.h ../Core/Inc/fdcan.h \
+ ../Core/Inc/i2c.h ../Core/Inc/tim.h ../Core/Inc/usart.h \
+ ../Core/Inc/gpio.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_GPIO.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_com_helper.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_TIMER.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_GV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_TL720D.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IO.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_CMCU.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_CV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_common.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTuc.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTucConfig.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IAP.pb.h
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+../Core/Inc/main.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
+../Core/Inc/dma.h:
+../Core/Inc/main.h:
+../Core/Inc/fdcan.h:
+../Core/Inc/i2c.h:
+../Core/Inc/tim.h:
+../Core/Inc/usart.h:
+../Core/Inc/gpio.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_GPIO.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_com_helper.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_TIMER.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_GV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_TL720D.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IO.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_CMCU.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_CV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_common.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTuc.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTucConfig.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IAP.pb.h:
diff --git a/Debug/Core/BASE/Src/BSP/bsp_EEPROM.o b/Debug/Core/BASE/Src/BSP/bsp_EEPROM.o
new file mode 100644
index 0000000..0a3941f
Binary files /dev/null and b/Debug/Core/BASE/Src/BSP/bsp_EEPROM.o differ
diff --git a/Debug/Core/BASE/Src/BSP/bsp_EEPROM.su b/Debug/Core/BASE/Src/BSP/bsp_EEPROM.su
new file mode 100644
index 0000000..d76f4be
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/bsp_EEPROM.su
@@ -0,0 +1,20 @@
+../Core/BASE/Src/BSP/bsp_EEPROM.c:38:9:GF_BSP_EEPROM_Init	8	static
+../Core/BASE/Src/BSP/bsp_EEPROM.c:52:6:bsp_InitI2C	32	static
+../Core/BASE/Src/BSP/bsp_EEPROM.c:79:13:i2c_Delay	8	static
+../Core/BASE/Src/BSP/bsp_EEPROM.c:92:6:i2c_Start	8	static
+../Core/BASE/Src/BSP/bsp_EEPROM.c:113:6:i2c_Stop	8	static
+../Core/BASE/Src/BSP/bsp_EEPROM.c:132:6:i2c_SendByte	24	static
+../Core/BASE/Src/BSP/bsp_EEPROM.c:168:9:i2c_ReadByte	16	static
+../Core/BASE/Src/BSP/bsp_EEPROM.c:198:9:i2c_WaitAck	16	static
+../Core/BASE/Src/BSP/bsp_EEPROM.c:227:6:i2c_Ack	8	static
+../Core/BASE/Src/BSP/bsp_EEPROM.c:248:6:i2c_NAck	8	static
+../Core/BASE/Src/BSP/bsp_EEPROM.c:266:9:i2c_CheckDevice	24	static
+../Core/BASE/Src/BSP/bsp_EEPROM.c:293:9:GF_BSP_EEPROM_CheckOK	8	static
+../Core/BASE/Src/BSP/bsp_EEPROM.c:318:9:GF_BSP_EEPROM_ReadBytes	32	static
+../Core/BASE/Src/BSP/bsp_EEPROM.c:407:9:GF_BSP_EEPROM_WriteBytes	24	static
+../Core/BASE/Src/BSP/bsp_EEPROM.c:526:18:GF_BSP_EEPROM_Get_CV	176	static
+../Core/BASE/Src/BSP/bsp_EEPROM.c:535:9:GF_BSP_EEPROM_Set_CV	8	static
+../Core/BASE/Src/BSP/bsp_EEPROM.c:541:19:GF_BSP_EEPROM_Get_IAP	40	static
+../Core/BASE/Src/BSP/bsp_EEPROM.c:550:9:GF_BSP_EEPROM_Set_IAP	32	static
+../Core/BASE/Src/BSP/bsp_EEPROM.c:556:18:GF_BSP_EEPROM_Get_PV	184	static
+../Core/BASE/Src/BSP/bsp_EEPROM.c:564:9:GF_BSP_EEPROM_Set_PV	320	static
diff --git a/Debug/Core/BASE/Src/BSP/bsp_Error_Detect.cyclo b/Debug/Core/BASE/Src/BSP/bsp_Error_Detect.cyclo
new file mode 100644
index 0000000..9cafb0a
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/bsp_Error_Detect.cyclo
@@ -0,0 +1,2 @@
+../Core/BASE/Src/BSP/bsp_Error_Detect.c:11:6:Error_Detect_Intialzie	1
+../Core/BASE/Src/BSP/bsp_Error_Detect.c:24:6:ErrorDetect	2
diff --git a/Debug/Core/BASE/Src/BSP/bsp_Error_Detect.d b/Debug/Core/BASE/Src/BSP/bsp_Error_Detect.d
new file mode 100644
index 0000000..17de6f5
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/bsp_Error_Detect.d
@@ -0,0 +1,205 @@
+Core/BASE/Src/BSP/bsp_Error_Detect.o: \
+ ../Core/BASE/Src/BSP/bsp_Error_Detect.c \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_Error_Detect.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ ../Core/Inc/main.h ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
+ ../Core/Inc/dma.h ../Core/Inc/main.h ../Core/Inc/fdcan.h \
+ ../Core/Inc/i2c.h ../Core/Inc/tim.h ../Core/Inc/usart.h \
+ ../Core/Inc/gpio.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_CV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IAP.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_GPIO.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_com_helper.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_TIMER.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_GV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_TL720D.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IO.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_CMCU.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_common.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTuc.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTucConfig.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_JTBATTERY.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UART.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_pb_decode_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TL720D.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_MK32_1.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_WH_LTE_7S0.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_DLT_Log.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UDP.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_cpu_flash.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_qspi_w25q128.h \
+ ../Core/Inc/quadspi.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UpperComputer_Handler.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TTMotor_ZQ.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h \
+ ../Core/Inc/fsm.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_Error_Detect.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IV.pb.h
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_Error_Detect.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+../Core/Inc/main.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
+../Core/Inc/dma.h:
+../Core/Inc/main.h:
+../Core/Inc/fdcan.h:
+../Core/Inc/i2c.h:
+../Core/Inc/tim.h:
+../Core/Inc/usart.h:
+../Core/Inc/gpio.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_CV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IAP.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_GPIO.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_com_helper.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_TIMER.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_GV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_TL720D.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IO.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_CMCU.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_common.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTuc.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTucConfig.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_JTBATTERY.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UART.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_pb_decode_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TL720D.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_MK32_1.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_WH_LTE_7S0.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_DLT_Log.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UDP.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_cpu_flash.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_qspi_w25q128.h:
+../Core/Inc/quadspi.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UpperComputer_Handler.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TTMotor_ZQ.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h:
+../Core/Inc/fsm.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_Error_Detect.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IV.pb.h:
diff --git a/Debug/Core/BASE/Src/BSP/bsp_Error_Detect.o b/Debug/Core/BASE/Src/BSP/bsp_Error_Detect.o
new file mode 100644
index 0000000..f62e1e5
Binary files /dev/null and b/Debug/Core/BASE/Src/BSP/bsp_Error_Detect.o differ
diff --git a/Debug/Core/BASE/Src/BSP/bsp_Error_Detect.su b/Debug/Core/BASE/Src/BSP/bsp_Error_Detect.su
new file mode 100644
index 0000000..6b774cb
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/bsp_Error_Detect.su
@@ -0,0 +1,2 @@
+../Core/BASE/Src/BSP/bsp_Error_Detect.c:11:6:Error_Detect_Intialzie	16	static
+../Core/BASE/Src/BSP/bsp_Error_Detect.c:24:6:ErrorDetect	8	static
diff --git a/Debug/Core/BASE/Src/BSP/bsp_FDCAN.cyclo b/Debug/Core/BASE/Src/BSP/bsp_FDCAN.cyclo
new file mode 100644
index 0000000..d09a0a5
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/bsp_FDCAN.cyclo
@@ -0,0 +1,11 @@
+../Core/BASE/Src/BSP/bsp_FDCAN.c:23:9:GF_BSP_FDCAN_Init	5
+../Core/BASE/Src/BSP/bsp_FDCAN.c:54:6:HAL_FDCAN_ErrorStatusCallback	3
+../Core/BASE/Src/BSP/bsp_FDCAN.c:67:6:HAL_FDCAN_RxFifo0Callback	7
+../Core/BASE/Src/BSP/bsp_FDCAN.c:118:6:GF_BSP_FDCAN_Senddata	4
+../Core/BASE/Src/BSP/bsp_FDCAN.c:159:6:GF_BSP_CANHandler_Init	1
+../Core/BASE/Src/BSP/bsp_FDCAN.c:173:6:GF_BSP_CANHandler_Init_CAN	1
+../Core/BASE/Src/BSP/bsp_FDCAN.c:202:6:GF_BSP_CAN_Timer	3
+../Core/BASE/Src/BSP/bsp_FDCAN.c:228:6:GF_CAN_Send_List_Send	4
+../Core/BASE/Src/BSP/bsp_FDCAN.c:270:6:CAN_Send_t	4
+../Core/BASE/Src/BSP/bsp_FDCAN.c:314:6:CAN_Send_Data_t	1
+../Core/BASE/Src/BSP/bsp_FDCAN.c:319:6:CANHandlerAddTxList	3
diff --git a/Debug/Core/BASE/Src/BSP/bsp_FDCAN.d b/Debug/Core/BASE/Src/BSP/bsp_FDCAN.d
new file mode 100644
index 0000000..8a9ba70
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/bsp_FDCAN.d
@@ -0,0 +1,152 @@
+Core/BASE/Src/BSP/bsp_FDCAN.o: ../Core/BASE/Src/BSP/bsp_FDCAN.c \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_com_helper.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ ../Core/Inc/main.h ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
+ ../Core/Inc/dma.h ../Core/Inc/main.h ../Core/Inc/fdcan.h \
+ ../Core/Inc/i2c.h ../Core/Inc/tim.h ../Core/Inc/usart.h \
+ ../Core/Inc/gpio.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_CV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IAP.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_GPIO.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_TIMER.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_GV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_TL720D.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IO.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_CMCU.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_common.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTuc.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTucConfig.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TI5MOTOR.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_com_helper.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+../Core/Inc/main.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
+../Core/Inc/dma.h:
+../Core/Inc/main.h:
+../Core/Inc/fdcan.h:
+../Core/Inc/i2c.h:
+../Core/Inc/tim.h:
+../Core/Inc/usart.h:
+../Core/Inc/gpio.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_CV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IAP.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_GPIO.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_TIMER.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_GV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_TL720D.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IO.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_CMCU.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_common.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTuc.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTucConfig.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TI5MOTOR.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h:
diff --git a/Debug/Core/BASE/Src/BSP/bsp_FDCAN.o b/Debug/Core/BASE/Src/BSP/bsp_FDCAN.o
new file mode 100644
index 0000000..5593db2
Binary files /dev/null and b/Debug/Core/BASE/Src/BSP/bsp_FDCAN.o differ
diff --git a/Debug/Core/BASE/Src/BSP/bsp_FDCAN.su b/Debug/Core/BASE/Src/BSP/bsp_FDCAN.su
new file mode 100644
index 0000000..ffcf099
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/bsp_FDCAN.su
@@ -0,0 +1,11 @@
+../Core/BASE/Src/BSP/bsp_FDCAN.c:23:9:GF_BSP_FDCAN_Init	8	static
+../Core/BASE/Src/BSP/bsp_FDCAN.c:54:6:HAL_FDCAN_ErrorStatusCallback	16	static
+../Core/BASE/Src/BSP/bsp_FDCAN.c:67:6:HAL_FDCAN_RxFifo0Callback	16	static
+../Core/BASE/Src/BSP/bsp_FDCAN.c:118:6:GF_BSP_FDCAN_Senddata	24	static
+../Core/BASE/Src/BSP/bsp_FDCAN.c:159:6:GF_BSP_CANHandler_Init	24	static
+../Core/BASE/Src/BSP/bsp_FDCAN.c:173:6:GF_BSP_CANHandler_Init_CAN	24	static
+../Core/BASE/Src/BSP/bsp_FDCAN.c:202:6:GF_BSP_CAN_Timer	8	static
+../Core/BASE/Src/BSP/bsp_FDCAN.c:228:6:GF_CAN_Send_List_Send	24	static
+../Core/BASE/Src/BSP/bsp_FDCAN.c:270:6:CAN_Send_t	24	static
+../Core/BASE/Src/BSP/bsp_FDCAN.c:314:6:CAN_Send_Data_t	16	static
+../Core/BASE/Src/BSP/bsp_FDCAN.c:319:6:CANHandlerAddTxList	40	static
diff --git a/Debug/Core/BASE/Src/BSP/bsp_GPIO.cyclo b/Debug/Core/BASE/Src/BSP/bsp_GPIO.cyclo
new file mode 100644
index 0000000..51bb12f
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/bsp_GPIO.cyclo
@@ -0,0 +1,4 @@
+../Core/BASE/Src/BSP/bsp_GPIO.c:10:9:GF_BSP_GPIO_Init	1
+../Core/BASE/Src/BSP/bsp_GPIO.c:16:6:GF_BSP_GPIO_SetIO	8
+../Core/BASE/Src/BSP/bsp_GPIO.c:53:9:GF_BSP_GPIO_ToggleIO	7
+../Core/BASE/Src/BSP/bsp_GPIO.c:82:9:GF_BSP_GPIO_ReadIO	7
diff --git a/Debug/Core/BASE/Src/BSP/bsp_GPIO.d b/Debug/Core/BASE/Src/BSP/bsp_GPIO.d
new file mode 100644
index 0000000..8c5b44f
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/bsp_GPIO.d
@@ -0,0 +1,206 @@
+Core/BASE/Src/BSP/bsp_GPIO.o: ../Core/BASE/Src/BSP/bsp_GPIO.c \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_GPIO.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ ../Core/Inc/main.h ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
+ ../Core/Inc/dma.h ../Core/Inc/main.h ../Core/Inc/fdcan.h \
+ ../Core/Inc/i2c.h ../Core/Inc/tim.h ../Core/Inc/usart.h \
+ ../Core/Inc/gpio.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_CV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IAP.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_GPIO.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_com_helper.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_TIMER.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_GV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_TL720D.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IO.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_CMCU.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_common.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTuc.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTucConfig.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_JTBATTERY.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UART.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_pb_decode_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TL720D.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_MK32_1.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_WH_LTE_7S0.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_DLT_Log.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UDP.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_cpu_flash.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_qspi_w25q128.h \
+ ../Core/Inc/quadspi.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UpperComputer_Handler.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TTMotor_ZQ.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h \
+ ../Core/Inc/fsm.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_Error_Detect.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IV.pb.h
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_GPIO.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+../Core/Inc/main.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
+../Core/Inc/dma.h:
+../Core/Inc/main.h:
+../Core/Inc/fdcan.h:
+../Core/Inc/i2c.h:
+../Core/Inc/tim.h:
+../Core/Inc/usart.h:
+../Core/Inc/gpio.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_CV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IAP.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_GPIO.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_com_helper.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_TIMER.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_GV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_TL720D.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IO.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_CMCU.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_common.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTuc.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTucConfig.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_JTBATTERY.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UART.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_pb_decode_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TL720D.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_MK32_1.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_WH_LTE_7S0.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_DLT_Log.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UDP.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_cpu_flash.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_qspi_w25q128.h:
+../Core/Inc/quadspi.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UpperComputer_Handler.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TTMotor_ZQ.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h:
+../Core/Inc/fsm.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_Error_Detect.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IV.pb.h:
diff --git a/Debug/Core/BASE/Src/BSP/bsp_GPIO.o b/Debug/Core/BASE/Src/BSP/bsp_GPIO.o
new file mode 100644
index 0000000..1e43afb
Binary files /dev/null and b/Debug/Core/BASE/Src/BSP/bsp_GPIO.o differ
diff --git a/Debug/Core/BASE/Src/BSP/bsp_GPIO.su b/Debug/Core/BASE/Src/BSP/bsp_GPIO.su
new file mode 100644
index 0000000..8bb7436
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/bsp_GPIO.su
@@ -0,0 +1,4 @@
+../Core/BASE/Src/BSP/bsp_GPIO.c:10:9:GF_BSP_GPIO_Init	4	static
+../Core/BASE/Src/BSP/bsp_GPIO.c:16:6:GF_BSP_GPIO_SetIO	24	static
+../Core/BASE/Src/BSP/bsp_GPIO.c:53:9:GF_BSP_GPIO_ToggleIO	16	static
+../Core/BASE/Src/BSP/bsp_GPIO.c:82:9:GF_BSP_GPIO_ReadIO	24	static
diff --git a/Debug/Core/BASE/Src/BSP/bsp_INTERCALL.cyclo b/Debug/Core/BASE/Src/BSP/bsp_INTERCALL.cyclo
new file mode 100644
index 0000000..8144d18
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/bsp_INTERCALL.cyclo
@@ -0,0 +1,2 @@
+../Core/BASE/Src/BSP/bsp_INTERCALL.c:19:9:GF_BSP_Interrupt_Add_CallBack	2
+../Core/BASE/Src/BSP/bsp_INTERCALL.c:31:6:GF_BSP_Interrupt_Run_CallBack	3
diff --git a/Debug/Core/BASE/Src/BSP/bsp_INTERCALL.d b/Debug/Core/BASE/Src/BSP/bsp_INTERCALL.d
new file mode 100644
index 0000000..bf3ab8a
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/bsp_INTERCALL.d
@@ -0,0 +1,146 @@
+Core/BASE/Src/BSP/bsp_INTERCALL.o: ../Core/BASE/Src/BSP/bsp_INTERCALL.c \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ ../Core/Inc/main.h ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
+ ../Core/Inc/dma.h ../Core/Inc/main.h ../Core/Inc/fdcan.h \
+ ../Core/Inc/i2c.h ../Core/Inc/tim.h ../Core/Inc/usart.h \
+ ../Core/Inc/gpio.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_CV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IAP.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_GPIO.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_com_helper.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_TIMER.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_GV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_TL720D.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IO.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_CMCU.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_common.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTuc.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTucConfig.h
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+../Core/Inc/main.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
+../Core/Inc/dma.h:
+../Core/Inc/main.h:
+../Core/Inc/fdcan.h:
+../Core/Inc/i2c.h:
+../Core/Inc/tim.h:
+../Core/Inc/usart.h:
+../Core/Inc/gpio.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_CV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IAP.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_GPIO.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_com_helper.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_TIMER.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_GV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_TL720D.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IO.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_CMCU.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_common.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTuc.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTucConfig.h:
diff --git a/Debug/Core/BASE/Src/BSP/bsp_INTERCALL.o b/Debug/Core/BASE/Src/BSP/bsp_INTERCALL.o
new file mode 100644
index 0000000..02bfc5e
Binary files /dev/null and b/Debug/Core/BASE/Src/BSP/bsp_INTERCALL.o differ
diff --git a/Debug/Core/BASE/Src/BSP/bsp_INTERCALL.su b/Debug/Core/BASE/Src/BSP/bsp_INTERCALL.su
new file mode 100644
index 0000000..4f344c3
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/bsp_INTERCALL.su
@@ -0,0 +1,2 @@
+../Core/BASE/Src/BSP/bsp_INTERCALL.c:19:9:GF_BSP_Interrupt_Add_CallBack	16	static
+../Core/BASE/Src/BSP/bsp_INTERCALL.c:31:6:GF_BSP_Interrupt_Run_CallBack	24	static
diff --git a/Debug/Core/BASE/Src/BSP/bsp_MB_host.cyclo b/Debug/Core/BASE/Src/BSP/bsp_MB_host.cyclo
new file mode 100644
index 0000000..37b0894
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/bsp_MB_host.cyclo
@@ -0,0 +1,11 @@
+../Core/BASE/Src/BSP/bsp_MB_host.c:76:10:MB_CRC16	2
+../Core/BASE/Src/BSP/bsp_MB_host.c:96:6:MB_ReadCoil	1
+../Core/BASE/Src/BSP/bsp_MB_host.c:123:6:MB_WriteCoil	1
+../Core/BASE/Src/BSP/bsp_MB_host.c:147:6:MB_WriteNumCoil	3
+../Core/BASE/Src/BSP/bsp_MB_host.c:189:6:MB_ReadInput	1
+../Core/BASE/Src/BSP/bsp_MB_host.c:215:6:MB_ReadHoldingReg	1
+../Core/BASE/Src/BSP/bsp_MB_host.c:246:6:MB_ReadInputReg	1
+../Core/BASE/Src/BSP/bsp_MB_host.c:271:6:MB_WriteHoldingReg	1
+../Core/BASE/Src/BSP/bsp_MB_host.c:297:6:MB_WriteNumHoldingReg	2
+../Core/BASE/Src/BSP/bsp_MB_host.c:328:9:MB_Decode_HoldingRegs	3
+../Core/BASE/Src/BSP/bsp_MB_host.c:349:9:MB_Decode_InputRegs	3
diff --git a/Debug/Core/BASE/Src/BSP/bsp_MB_host.d b/Debug/Core/BASE/Src/BSP/bsp_MB_host.d
new file mode 100644
index 0000000..7f7cedc
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/bsp_MB_host.d
@@ -0,0 +1,150 @@
+Core/BASE/Src/BSP/bsp_MB_host.o: ../Core/BASE/Src/BSP/bsp_MB_host.c \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ ../Core/Inc/main.h ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
+ ../Core/Inc/dma.h ../Core/Inc/main.h ../Core/Inc/fdcan.h \
+ ../Core/Inc/i2c.h ../Core/Inc/tim.h ../Core/Inc/usart.h \
+ ../Core/Inc/gpio.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_CV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IAP.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_GPIO.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_com_helper.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_TIMER.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_GV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_TL720D.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IO.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_CMCU.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_common.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTuc.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTucConfig.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UART.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+../Core/Inc/main.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
+../Core/Inc/dma.h:
+../Core/Inc/main.h:
+../Core/Inc/fdcan.h:
+../Core/Inc/i2c.h:
+../Core/Inc/tim.h:
+../Core/Inc/usart.h:
+../Core/Inc/gpio.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_CV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IAP.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_GPIO.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_com_helper.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_TIMER.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_GV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_TL720D.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IO.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_CMCU.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_common.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTuc.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTucConfig.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UART.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
diff --git a/Debug/Core/BASE/Src/BSP/bsp_MB_host.o b/Debug/Core/BASE/Src/BSP/bsp_MB_host.o
new file mode 100644
index 0000000..188c597
Binary files /dev/null and b/Debug/Core/BASE/Src/BSP/bsp_MB_host.o differ
diff --git a/Debug/Core/BASE/Src/BSP/bsp_MB_host.su b/Debug/Core/BASE/Src/BSP/bsp_MB_host.su
new file mode 100644
index 0000000..9ab7598
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/bsp_MB_host.su
@@ -0,0 +1,11 @@
+../Core/BASE/Src/BSP/bsp_MB_host.c:76:10:MB_CRC16	24	static
+../Core/BASE/Src/BSP/bsp_MB_host.c:96:6:MB_ReadCoil	32	static
+../Core/BASE/Src/BSP/bsp_MB_host.c:123:6:MB_WriteCoil	32	static
+../Core/BASE/Src/BSP/bsp_MB_host.c:147:6:MB_WriteNumCoil	32	static
+../Core/BASE/Src/BSP/bsp_MB_host.c:189:6:MB_ReadInput	32	static
+../Core/BASE/Src/BSP/bsp_MB_host.c:215:6:MB_ReadHoldingReg	32	static
+../Core/BASE/Src/BSP/bsp_MB_host.c:246:6:MB_ReadInputReg	32	static
+../Core/BASE/Src/BSP/bsp_MB_host.c:271:6:MB_WriteHoldingReg	32	static
+../Core/BASE/Src/BSP/bsp_MB_host.c:297:6:MB_WriteNumHoldingReg	32	static
+../Core/BASE/Src/BSP/bsp_MB_host.c:328:9:MB_Decode_HoldingRegs	32	static
+../Core/BASE/Src/BSP/bsp_MB_host.c:349:9:MB_Decode_InputRegs	32	static
diff --git a/Debug/Core/BASE/Src/BSP/bsp_TIMER.cyclo b/Debug/Core/BASE/Src/BSP/bsp_TIMER.cyclo
new file mode 100644
index 0000000..e471832
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/bsp_TIMER.cyclo
@@ -0,0 +1,3 @@
+../Core/BASE/Src/BSP/bsp_TIMER.c:11:9:GF_BSP_TIMER_Init	1
+../Core/BASE/Src/BSP/bsp_TIMER.c:18:6:HAL_TIM_PeriodElapsedCallback	3
+../Core/BASE/Src/BSP/bsp_TIMER.c:34:6:GF_BSP_TIMER_DelayUS	4
diff --git a/Debug/Core/BASE/Src/BSP/bsp_TIMER.d b/Debug/Core/BASE/Src/BSP/bsp_TIMER.d
new file mode 100644
index 0000000..7295127
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/bsp_TIMER.d
@@ -0,0 +1,146 @@
+Core/BASE/Src/BSP/bsp_TIMER.o: ../Core/BASE/Src/BSP/bsp_TIMER.c \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_TIMER.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ ../Core/Inc/main.h ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
+ ../Core/Inc/dma.h ../Core/Inc/main.h ../Core/Inc/fdcan.h \
+ ../Core/Inc/i2c.h ../Core/Inc/tim.h ../Core/Inc/usart.h \
+ ../Core/Inc/gpio.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_CV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IAP.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_GPIO.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_com_helper.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_TIMER.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_GV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_TL720D.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IO.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_CMCU.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_common.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTuc.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTucConfig.h
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_TIMER.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+../Core/Inc/main.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
+../Core/Inc/dma.h:
+../Core/Inc/main.h:
+../Core/Inc/fdcan.h:
+../Core/Inc/i2c.h:
+../Core/Inc/tim.h:
+../Core/Inc/usart.h:
+../Core/Inc/gpio.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_CV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IAP.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_GPIO.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_com_helper.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_TIMER.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_GV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_TL720D.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IO.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_CMCU.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_common.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTuc.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTucConfig.h:
diff --git a/Debug/Core/BASE/Src/BSP/bsp_TIMER.o b/Debug/Core/BASE/Src/BSP/bsp_TIMER.o
new file mode 100644
index 0000000..e4ddcf0
Binary files /dev/null and b/Debug/Core/BASE/Src/BSP/bsp_TIMER.o differ
diff --git a/Debug/Core/BASE/Src/BSP/bsp_TIMER.su b/Debug/Core/BASE/Src/BSP/bsp_TIMER.su
new file mode 100644
index 0000000..e027ac9
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/bsp_TIMER.su
@@ -0,0 +1,3 @@
+../Core/BASE/Src/BSP/bsp_TIMER.c:11:9:GF_BSP_TIMER_Init	8	static
+../Core/BASE/Src/BSP/bsp_TIMER.c:18:6:HAL_TIM_PeriodElapsedCallback	16	static
+../Core/BASE/Src/BSP/bsp_TIMER.c:34:6:GF_BSP_TIMER_DelayUS	40	static
diff --git a/Debug/Core/BASE/Src/BSP/bsp_UART.cyclo b/Debug/Core/BASE/Src/BSP/bsp_UART.cyclo
new file mode 100644
index 0000000..39aca21
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/bsp_UART.cyclo
@@ -0,0 +1,11 @@
+../Core/BASE/Src/BSP/bsp_UART.c:56:6:GF_BSP_UARTHandlers_Intialize	1
+../Core/BASE/Src/BSP/bsp_UART.c:125:6:GF_BSP_UART_Timer	1
+../Core/BASE/Src/BSP/bsp_UART.c:143:6:UARTHandlerAddTxList	3
+../Core/BASE/Src/BSP/bsp_UART.c:177:6:UARTHandlerTx	16
+../Core/BASE/Src/BSP/bsp_UART.c:265:6:UARTHandlerRX	3
+../Core/BASE/Src/BSP/bsp_UART.c:287:6:IntializeUARTHandler	1
+../Core/BASE/Src/BSP/bsp_UART.c:316:6:Counting	6
+../Core/BASE/Src/BSP/bsp_UART.c:389:6:HAL_UART_RxCpltCallback	9
+../Core/BASE/Src/BSP/bsp_UART.c:440:6:HAL_UART_TxCpltCallback	6
+../Core/BASE/Src/BSP/bsp_UART.c:473:6:GF_BSP_UART_Transmit	19
+../Core/BASE/Src/BSP/bsp_UART.c:590:6:GF_UART_Send_List_Send	4
diff --git a/Debug/Core/BASE/Src/BSP/bsp_UART.d b/Debug/Core/BASE/Src/BSP/bsp_UART.d
new file mode 100644
index 0000000..79eb0e1
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/bsp_UART.d
@@ -0,0 +1,148 @@
+Core/BASE/Src/BSP/bsp_UART.o: ../Core/BASE/Src/BSP/bsp_UART.c \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UART.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ ../Core/Inc/main.h ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
+ ../Core/Inc/dma.h ../Core/Inc/main.h ../Core/Inc/fdcan.h \
+ ../Core/Inc/i2c.h ../Core/Inc/tim.h ../Core/Inc/usart.h \
+ ../Core/Inc/gpio.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_CV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IAP.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_GPIO.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_com_helper.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_TIMER.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_GV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_TL720D.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IO.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_CMCU.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_common.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTuc.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTucConfig.h
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UART.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+../Core/Inc/main.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
+../Core/Inc/dma.h:
+../Core/Inc/main.h:
+../Core/Inc/fdcan.h:
+../Core/Inc/i2c.h:
+../Core/Inc/tim.h:
+../Core/Inc/usart.h:
+../Core/Inc/gpio.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_CV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IAP.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_GPIO.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_com_helper.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_TIMER.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_GV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_TL720D.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IO.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_CMCU.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_common.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTuc.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTucConfig.h:
diff --git a/Debug/Core/BASE/Src/BSP/bsp_UART.o b/Debug/Core/BASE/Src/BSP/bsp_UART.o
new file mode 100644
index 0000000..35825cf
Binary files /dev/null and b/Debug/Core/BASE/Src/BSP/bsp_UART.o differ
diff --git a/Debug/Core/BASE/Src/BSP/bsp_UART.su b/Debug/Core/BASE/Src/BSP/bsp_UART.su
new file mode 100644
index 0000000..67f6770
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/bsp_UART.su
@@ -0,0 +1,11 @@
+../Core/BASE/Src/BSP/bsp_UART.c:56:6:GF_BSP_UARTHandlers_Intialize	32	static
+../Core/BASE/Src/BSP/bsp_UART.c:125:6:GF_BSP_UART_Timer	8	static
+../Core/BASE/Src/BSP/bsp_UART.c:143:6:UARTHandlerAddTxList	40	static
+../Core/BASE/Src/BSP/bsp_UART.c:177:6:UARTHandlerTx	48	static,ignoring_inline_asm
+../Core/BASE/Src/BSP/bsp_UART.c:265:6:UARTHandlerRX	16	static
+../Core/BASE/Src/BSP/bsp_UART.c:287:6:IntializeUARTHandler	24	static
+../Core/BASE/Src/BSP/bsp_UART.c:316:6:Counting	16	static
+../Core/BASE/Src/BSP/bsp_UART.c:389:6:HAL_UART_RxCpltCallback	16	static
+../Core/BASE/Src/BSP/bsp_UART.c:440:6:HAL_UART_TxCpltCallback	16	static
+../Core/BASE/Src/BSP/bsp_UART.c:473:6:GF_BSP_UART_Transmit	120	static,ignoring_inline_asm
+../Core/BASE/Src/BSP/bsp_UART.c:590:6:GF_UART_Send_List_Send	24	static
diff --git a/Debug/Core/BASE/Src/BSP/bsp_UpperComputer_Handler.cyclo b/Debug/Core/BASE/Src/BSP/bsp_UpperComputer_Handler.cyclo
new file mode 100644
index 0000000..60228dd
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/bsp_UpperComputer_Handler.cyclo
@@ -0,0 +1,3 @@
+../Core/BASE/Src/BSP/bsp_UpperComputer_Handler.c:29:6:upper_Computer_UART_Handler_intialize	1
+../Core/BASE/Src/BSP/bsp_UpperComputer_Handler.c:46:6:send_data_to_upper_computer	1
+../Core/BASE/Src/BSP/bsp_UpperComputer_Handler.c:102:6:decode_command_from_computer	4
diff --git a/Debug/Core/BASE/Src/BSP/bsp_UpperComputer_Handler.d b/Debug/Core/BASE/Src/BSP/bsp_UpperComputer_Handler.d
new file mode 100644
index 0000000..3e7f940
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/bsp_UpperComputer_Handler.d
@@ -0,0 +1,219 @@
+Core/BASE/Src/BSP/bsp_UpperComputer_Handler.o: \
+ ../Core/BASE/Src/BSP/bsp_UpperComputer_Handler.c \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_WH_LTE_7S0.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ ../Core/Inc/main.h ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
+ ../Core/Inc/dma.h ../Core/Inc/main.h ../Core/Inc/fdcan.h \
+ ../Core/Inc/i2c.h ../Core/Inc/tim.h ../Core/Inc/usart.h \
+ ../Core/Inc/gpio.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_CV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IAP.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_GPIO.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_com_helper.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_TIMER.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_GV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_TL720D.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IO.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_CMCU.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_common.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTuc.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTucConfig.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Cmd.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_JTBATTERY.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UART.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_pb_decode_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TL720D.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_MK32_1.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_DLT_Log.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UDP.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_cpu_flash.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_qspi_w25q128.h \
+ ../Core/Inc/quadspi.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UpperComputer_Handler.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TTMotor_ZQ.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h \
+ ../Core/Inc/fsm.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_Error_Detect.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_cpu_flash.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_decode_command.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_cpu_flash.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_ReCmd.pb.h
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_WH_LTE_7S0.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+../Core/Inc/main.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
+../Core/Inc/dma.h:
+../Core/Inc/main.h:
+../Core/Inc/fdcan.h:
+../Core/Inc/i2c.h:
+../Core/Inc/tim.h:
+../Core/Inc/usart.h:
+../Core/Inc/gpio.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_CV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IAP.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_GPIO.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_com_helper.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_TIMER.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_GV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_TL720D.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IO.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_CMCU.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_common.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTuc.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTucConfig.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Cmd.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_JTBATTERY.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UART.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_pb_decode_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TL720D.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_MK32_1.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_DLT_Log.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UDP.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_cpu_flash.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_qspi_w25q128.h:
+../Core/Inc/quadspi.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UpperComputer_Handler.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TTMotor_ZQ.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h:
+../Core/Inc/fsm.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_Error_Detect.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_cpu_flash.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_decode_command.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_cpu_flash.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_ReCmd.pb.h:
diff --git a/Debug/Core/BASE/Src/BSP/bsp_UpperComputer_Handler.o b/Debug/Core/BASE/Src/BSP/bsp_UpperComputer_Handler.o
new file mode 100644
index 0000000..a797945
Binary files /dev/null and b/Debug/Core/BASE/Src/BSP/bsp_UpperComputer_Handler.o differ
diff --git a/Debug/Core/BASE/Src/BSP/bsp_UpperComputer_Handler.su b/Debug/Core/BASE/Src/BSP/bsp_UpperComputer_Handler.su
new file mode 100644
index 0000000..359b0db
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/bsp_UpperComputer_Handler.su
@@ -0,0 +1,3 @@
+../Core/BASE/Src/BSP/bsp_UpperComputer_Handler.c:29:6:upper_Computer_UART_Handler_intialize	16	static
+../Core/BASE/Src/BSP/bsp_UpperComputer_Handler.c:46:6:send_data_to_upper_computer	40	static
+../Core/BASE/Src/BSP/bsp_UpperComputer_Handler.c:102:6:decode_command_from_computer	16	static
diff --git a/Debug/Core/BASE/Src/BSP/bsp_client_setting.cyclo b/Debug/Core/BASE/Src/BSP/bsp_client_setting.cyclo
new file mode 100644
index 0000000..ccc223e
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/bsp_client_setting.cyclo
@@ -0,0 +1,3 @@
+../Core/BASE/Src/BSP/bsp_client_setting.c:20:6:client_setting_intialize	2
+../Core/BASE/Src/BSP/bsp_client_setting.c:40:6:UpdateIV	1
+../Core/BASE/Src/BSP/bsp_client_setting.c:61:6:decode_received_data_from_client	11
diff --git a/Debug/Core/BASE/Src/BSP/bsp_client_setting.d b/Debug/Core/BASE/Src/BSP/bsp_client_setting.d
new file mode 100644
index 0000000..42aff14
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/bsp_client_setting.d
@@ -0,0 +1,207 @@
+Core/BASE/Src/BSP/bsp_client_setting.o: \
+ ../Core/BASE/Src/BSP/bsp_client_setting.c \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_client_setting.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ ../Core/Inc/main.h ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
+ ../Core/Inc/dma.h ../Core/Inc/main.h ../Core/Inc/fdcan.h \
+ ../Core/Inc/i2c.h ../Core/Inc/tim.h ../Core/Inc/usart.h \
+ ../Core/Inc/gpio.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_CV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IAP.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_GPIO.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_com_helper.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_TIMER.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_GV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_TL720D.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IO.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_CMCU.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_common.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTuc.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTucConfig.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_JTBATTERY.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UART.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_pb_decode_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TL720D.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_MK32_1.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_WH_LTE_7S0.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_DLT_Log.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UDP.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_cpu_flash.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_qspi_w25q128.h \
+ ../Core/Inc/quadspi.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UpperComputer_Handler.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TTMotor_ZQ.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h \
+ ../Core/Inc/fsm.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_Error_Detect.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_client_setting.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+../Core/Inc/main.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
+../Core/Inc/dma.h:
+../Core/Inc/main.h:
+../Core/Inc/fdcan.h:
+../Core/Inc/i2c.h:
+../Core/Inc/tim.h:
+../Core/Inc/usart.h:
+../Core/Inc/gpio.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_CV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IAP.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_GPIO.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_com_helper.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_TIMER.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_GV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_TL720D.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IO.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_CMCU.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_common.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTuc.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTucConfig.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_JTBATTERY.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UART.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_pb_decode_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TL720D.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_MK32_1.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_WH_LTE_7S0.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_DLT_Log.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UDP.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_cpu_flash.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_qspi_w25q128.h:
+../Core/Inc/quadspi.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UpperComputer_Handler.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TTMotor_ZQ.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h:
+../Core/Inc/fsm.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_Error_Detect.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h:
diff --git a/Debug/Core/BASE/Src/BSP/bsp_client_setting.o b/Debug/Core/BASE/Src/BSP/bsp_client_setting.o
new file mode 100644
index 0000000..8a12c9b
Binary files /dev/null and b/Debug/Core/BASE/Src/BSP/bsp_client_setting.o differ
diff --git a/Debug/Core/BASE/Src/BSP/bsp_client_setting.su b/Debug/Core/BASE/Src/BSP/bsp_client_setting.su
new file mode 100644
index 0000000..4d2d8e5
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/bsp_client_setting.su
@@ -0,0 +1,3 @@
+../Core/BASE/Src/BSP/bsp_client_setting.c:20:6:client_setting_intialize	24	static
+../Core/BASE/Src/BSP/bsp_client_setting.c:40:6:UpdateIV	32	static
+../Core/BASE/Src/BSP/bsp_client_setting.c:61:6:decode_received_data_from_client	240	static
diff --git a/Debug/Core/BASE/Src/BSP/bsp_com_helper.cyclo b/Debug/Core/BASE/Src/BSP/bsp_com_helper.cyclo
new file mode 100644
index 0000000..4cfa96f
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/bsp_com_helper.cyclo
@@ -0,0 +1,5 @@
+../Core/BASE/Src/BSP/bsp_com_helper.c:12:6:Dispatch_t	6
+../Core/BASE/Src/BSP/bsp_com_helper.c:45:6:Dispatcher_List_Add_t	3
+../Core/BASE/Src/BSP/bsp_com_helper.c:80:6:ComHardWare_List_Add_t	3
+../Core/BASE/Src/BSP/bsp_com_helper.c:113:6:PCOMHardWare_Check_t	7
+../Core/BASE/Src/BSP/bsp_com_helper.c:160:5:Set_PCOMHardWare_t	4
diff --git a/Debug/Core/BASE/Src/BSP/bsp_com_helper.d b/Debug/Core/BASE/Src/BSP/bsp_com_helper.d
new file mode 100644
index 0000000..e70a4da
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/bsp_com_helper.d
@@ -0,0 +1,208 @@
+Core/BASE/Src/BSP/bsp_com_helper.o: ../Core/BASE/Src/BSP/bsp_com_helper.c \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_com_helper.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ ../Core/Inc/main.h ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
+ ../Core/Inc/dma.h ../Core/Inc/main.h ../Core/Inc/fdcan.h \
+ ../Core/Inc/i2c.h ../Core/Inc/tim.h ../Core/Inc/usart.h \
+ ../Core/Inc/gpio.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_CV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IAP.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_GPIO.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_com_helper.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_TIMER.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_GV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_TL720D.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IO.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_CMCU.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_common.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTuc.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTucConfig.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTuc.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_JTBATTERY.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UART.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_pb_decode_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TL720D.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_MK32_1.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_WH_LTE_7S0.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_DLT_Log.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UDP.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_cpu_flash.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_qspi_w25q128.h \
+ ../Core/Inc/quadspi.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UpperComputer_Handler.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TTMotor_ZQ.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h \
+ ../Core/Inc/fsm.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_Error_Detect.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IV.pb.h
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_com_helper.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+../Core/Inc/main.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
+../Core/Inc/dma.h:
+../Core/Inc/main.h:
+../Core/Inc/fdcan.h:
+../Core/Inc/i2c.h:
+../Core/Inc/tim.h:
+../Core/Inc/usart.h:
+../Core/Inc/gpio.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_CV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IAP.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_GPIO.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_com_helper.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_TIMER.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_GV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_TL720D.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IO.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_CMCU.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_common.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTuc.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTucConfig.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTuc.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_JTBATTERY.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UART.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_pb_decode_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TL720D.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_MK32_1.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_WH_LTE_7S0.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_DLT_Log.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UDP.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_cpu_flash.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_qspi_w25q128.h:
+../Core/Inc/quadspi.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UpperComputer_Handler.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TTMotor_ZQ.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h:
+../Core/Inc/fsm.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_Error_Detect.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IV.pb.h:
diff --git a/Debug/Core/BASE/Src/BSP/bsp_com_helper.o b/Debug/Core/BASE/Src/BSP/bsp_com_helper.o
new file mode 100644
index 0000000..8183d26
Binary files /dev/null and b/Debug/Core/BASE/Src/BSP/bsp_com_helper.o differ
diff --git a/Debug/Core/BASE/Src/BSP/bsp_com_helper.su b/Debug/Core/BASE/Src/BSP/bsp_com_helper.su
new file mode 100644
index 0000000..1a7a759
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/bsp_com_helper.su
@@ -0,0 +1,5 @@
+../Core/BASE/Src/BSP/bsp_com_helper.c:12:6:Dispatch_t	16	static
+../Core/BASE/Src/BSP/bsp_com_helper.c:45:6:Dispatcher_List_Add_t	24	static
+../Core/BASE/Src/BSP/bsp_com_helper.c:80:6:ComHardWare_List_Add_t	40	static
+../Core/BASE/Src/BSP/bsp_com_helper.c:113:6:PCOMHardWare_Check_t	48	static
+../Core/BASE/Src/BSP/bsp_com_helper.c:160:5:Set_PCOMHardWare_t	32	static
diff --git a/Debug/Core/BASE/Src/BSP/bsp_cpu_flash.cyclo b/Debug/Core/BASE/Src/BSP/bsp_cpu_flash.cyclo
new file mode 100644
index 0000000..f3ed38e
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/bsp_cpu_flash.cyclo
@@ -0,0 +1,9 @@
+../Core/BASE/Src/BSP/bsp_cpu_flash.c:66:10:bsp_GetSector	33
+../Core/BASE/Src/BSP/bsp_cpu_flash.c:128:9:bsp_ReadCpuFlash	4
+../Core/BASE/Src/BSP/bsp_cpu_flash.c:165:9:bsp_CmpCpuFlash	7
+../Core/BASE/Src/BSP/bsp_cpu_flash.c:227:9:bsp_EraseCpuFlash	2
+../Core/BASE/Src/BSP/bsp_cpu_flash.c:279:9:bsp_WriteCpuFlash	8
+../Core/BASE/Src/BSP/bsp_cpu_flash.c:368:6:JumpToApp	2
+../Core/BASE/Src/BSP/bsp_cpu_flash.c:424:6:Copy_Download_Flash_to_Start	3
+../Core/BASE/Src/BSP/bsp_cpu_flash.c:452:6:Copy_Peripheral_Download_Flash_to_App_Start	3
+../Core/BASE/Src/BSP/bsp_cpu_flash.c:482:6:Erase_App_Download_Flash_Addr	2
diff --git a/Debug/Core/BASE/Src/BSP/bsp_cpu_flash.d b/Debug/Core/BASE/Src/BSP/bsp_cpu_flash.d
new file mode 100644
index 0000000..fb64021
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/bsp_cpu_flash.d
@@ -0,0 +1,87 @@
+Core/BASE/Src/BSP/bsp_cpu_flash.o: ../Core/BASE/Src/BSP/bsp_cpu_flash.c \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_cpu_flash.h \
+ ../Core/Inc/main.h ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_qspi_w25q128.h \
+ ../Core/Inc/quadspi.h ../Core/Inc/main.h
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_cpu_flash.h:
+../Core/Inc/main.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_qspi_w25q128.h:
+../Core/Inc/quadspi.h:
+../Core/Inc/main.h:
diff --git a/Debug/Core/BASE/Src/BSP/bsp_cpu_flash.o b/Debug/Core/BASE/Src/BSP/bsp_cpu_flash.o
new file mode 100644
index 0000000..fa22749
Binary files /dev/null and b/Debug/Core/BASE/Src/BSP/bsp_cpu_flash.o differ
diff --git a/Debug/Core/BASE/Src/BSP/bsp_cpu_flash.su b/Debug/Core/BASE/Src/BSP/bsp_cpu_flash.su
new file mode 100644
index 0000000..c334778
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/bsp_cpu_flash.su
@@ -0,0 +1,9 @@
+../Core/BASE/Src/BSP/bsp_cpu_flash.c:66:10:bsp_GetSector	24	static
+../Core/BASE/Src/BSP/bsp_cpu_flash.c:128:9:bsp_ReadCpuFlash	32	static
+../Core/BASE/Src/BSP/bsp_cpu_flash.c:165:9:bsp_CmpCpuFlash	32	static
+../Core/BASE/Src/BSP/bsp_cpu_flash.c:227:9:bsp_EraseCpuFlash	56	static
+../Core/BASE/Src/BSP/bsp_cpu_flash.c:279:9:bsp_WriteCpuFlash	80	static,ignoring_inline_asm
+../Core/BASE/Src/BSP/bsp_cpu_flash.c:368:6:JumpToApp	32	static,ignoring_inline_asm
+../Core/BASE/Src/BSP/bsp_cpu_flash.c:424:6:Copy_Download_Flash_to_Start	56	static
+../Core/BASE/Src/BSP/bsp_cpu_flash.c:452:6:Copy_Peripheral_Download_Flash_to_App_Start	288	static
+../Core/BASE/Src/BSP/bsp_cpu_flash.c:482:6:Erase_App_Download_Flash_Addr	16	static
diff --git a/Debug/Core/BASE/Src/BSP/bsp_decode_command.cyclo b/Debug/Core/BASE/Src/BSP/bsp_decode_command.cyclo
new file mode 100644
index 0000000..22bba5b
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/bsp_decode_command.cyclo
@@ -0,0 +1,4 @@
+../Core/BASE/Src/BSP/bsp_decode_command.c:24:6:decode_command_and_feedback	1
+../Core/BASE/Src/BSP/bsp_decode_command.c:349:6:WrapInCmdAndSend	2
+../Core/BASE/Src/BSP/bsp_decode_command.c:390:6:WrapInCmdAndSendMessage	1
+../Core/BASE/Src/BSP/bsp_decode_command.c:401:6:send_received_data_to_upper_computer	1
diff --git a/Debug/Core/BASE/Src/BSP/bsp_decode_command.d b/Debug/Core/BASE/Src/BSP/bsp_decode_command.d
new file mode 100644
index 0000000..2bd3943
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/bsp_decode_command.d
@@ -0,0 +1,211 @@
+Core/BASE/Src/BSP/bsp_decode_command.o: \
+ ../Core/BASE/Src/BSP/bsp_decode_command.c \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_decode_command.h \
+ ../Core/Inc/main.h ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_WH_LTE_7S0.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ ../Core/Inc/dma.h ../Core/Inc/main.h ../Core/Inc/fdcan.h \
+ ../Core/Inc/i2c.h ../Core/Inc/tim.h ../Core/Inc/usart.h \
+ ../Core/Inc/gpio.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_CV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IAP.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_GPIO.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_com_helper.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_TIMER.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_GV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_TL720D.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IO.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_CMCU.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_common.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTuc.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTucConfig.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Cmd.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_JTBATTERY.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UART.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_pb_decode_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TL720D.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_MK32_1.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_DLT_Log.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UDP.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_cpu_flash.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_qspi_w25q128.h \
+ ../Core/Inc/quadspi.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UpperComputer_Handler.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TTMotor_ZQ.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h \
+ ../Core/Inc/fsm.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_Error_Detect.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_cpu_flash.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_ReCmd.pb.h
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_decode_command.h:
+../Core/Inc/main.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_WH_LTE_7S0.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+../Core/Inc/dma.h:
+../Core/Inc/main.h:
+../Core/Inc/fdcan.h:
+../Core/Inc/i2c.h:
+../Core/Inc/tim.h:
+../Core/Inc/usart.h:
+../Core/Inc/gpio.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_CV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IAP.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_GPIO.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_com_helper.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_TIMER.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_GV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_TL720D.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IO.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_CMCU.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_common.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTuc.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTucConfig.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Cmd.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_JTBATTERY.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UART.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_pb_decode_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TL720D.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_MK32_1.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_DLT_Log.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UDP.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_cpu_flash.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_qspi_w25q128.h:
+../Core/Inc/quadspi.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UpperComputer_Handler.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TTMotor_ZQ.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h:
+../Core/Inc/fsm.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_Error_Detect.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_cpu_flash.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_ReCmd.pb.h:
diff --git a/Debug/Core/BASE/Src/BSP/bsp_decode_command.o b/Debug/Core/BASE/Src/BSP/bsp_decode_command.o
new file mode 100644
index 0000000..39661eb
Binary files /dev/null and b/Debug/Core/BASE/Src/BSP/bsp_decode_command.o differ
diff --git a/Debug/Core/BASE/Src/BSP/bsp_decode_command.su b/Debug/Core/BASE/Src/BSP/bsp_decode_command.su
new file mode 100644
index 0000000..0319282
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/bsp_decode_command.su
@@ -0,0 +1,4 @@
+../Core/BASE/Src/BSP/bsp_decode_command.c:24:6:decode_command_and_feedback	24	static
+../Core/BASE/Src/BSP/bsp_decode_command.c:349:6:WrapInCmdAndSend	64	static
+../Core/BASE/Src/BSP/bsp_decode_command.c:390:6:WrapInCmdAndSendMessage	544	static
+../Core/BASE/Src/BSP/bsp_decode_command.c:401:6:send_received_data_to_upper_computer	560	static
diff --git a/Debug/Core/BASE/Src/BSP/bsp_qspi_w25q128.cyclo b/Debug/Core/BASE/Src/BSP/bsp_qspi_w25q128.cyclo
new file mode 100644
index 0000000..a49bf1d
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/bsp_qspi_w25q128.cyclo
@@ -0,0 +1,11 @@
+../Core/BASE/Src/BSP/bsp_qspi_w25q128.c:33:16:QSPI_W25Qx_AutoPollingMemRead	2
+../Core/BASE/Src/BSP/bsp_qspi_w25q128.c:79:10:QSPI_W25Qx_ReadID	3
+../Core/BASE/Src/BSP/bsp_qspi_w25q128.c:127:13:QSPI_W25Qx_Write_Enable	3
+../Core/BASE/Src/BSP/bsp_qspi_w25q128.c:181:6:QSPI_W25Qx_EraseSector	3
+../Core/BASE/Src/BSP/bsp_qspi_w25q128.c:226:9:QSPI_W25Qx_Write_Buffer	5
+../Core/BASE/Src/BSP/bsp_qspi_w25q128.c:284:13:QSPI_W25Qx_Enter	2
+../Core/BASE/Src/BSP/bsp_qspi_w25q128.c:318:13:QSPI_W25Qx_Exit	2
+../Core/BASE/Src/BSP/bsp_qspi_w25q128.c:352:6:QSPI_W25Qx_Read_Buffer	3
+../Core/BASE/Src/BSP/bsp_qspi_w25q128.c:401:6:QSPI_W25Qx_Reset_Memory	4
+../Core/BASE/Src/BSP/bsp_qspi_w25q128.c:452:6:user_Assert	2
+../Core/BASE/Src/BSP/bsp_qspi_w25q128.c:478:6:QSPI_W25Qx_EraseDownLoadFlash	2
diff --git a/Debug/Core/BASE/Src/BSP/bsp_qspi_w25q128.d b/Debug/Core/BASE/Src/BSP/bsp_qspi_w25q128.d
new file mode 100644
index 0000000..3ecf1c5
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/bsp_qspi_w25q128.d
@@ -0,0 +1,85 @@
+Core/BASE/Src/BSP/bsp_qspi_w25q128.o: \
+ ../Core/BASE/Src/BSP/bsp_qspi_w25q128.c \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_qspi_w25q128.h \
+ ../Core/Inc/quadspi.h ../Core/Inc/main.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_qspi_w25q128.h:
+../Core/Inc/quadspi.h:
+../Core/Inc/main.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Core/BASE/Src/BSP/bsp_qspi_w25q128.o b/Debug/Core/BASE/Src/BSP/bsp_qspi_w25q128.o
new file mode 100644
index 0000000..a862fb5
Binary files /dev/null and b/Debug/Core/BASE/Src/BSP/bsp_qspi_w25q128.o differ
diff --git a/Debug/Core/BASE/Src/BSP/bsp_qspi_w25q128.su b/Debug/Core/BASE/Src/BSP/bsp_qspi_w25q128.su
new file mode 100644
index 0000000..9dc9d7b
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/bsp_qspi_w25q128.su
@@ -0,0 +1,11 @@
+../Core/BASE/Src/BSP/bsp_qspi_w25q128.c:33:16:QSPI_W25Qx_AutoPollingMemRead	96	static
+../Core/BASE/Src/BSP/bsp_qspi_w25q128.c:79:10:QSPI_W25Qx_ReadID	72	static
+../Core/BASE/Src/BSP/bsp_qspi_w25q128.c:127:13:QSPI_W25Qx_Write_Enable	96	static
+../Core/BASE/Src/BSP/bsp_qspi_w25q128.c:181:6:QSPI_W25Qx_EraseSector	72	static
+../Core/BASE/Src/BSP/bsp_qspi_w25q128.c:226:9:QSPI_W25Qx_Write_Buffer	80	static
+../Core/BASE/Src/BSP/bsp_qspi_w25q128.c:284:13:QSPI_W25Qx_Enter	72	static
+../Core/BASE/Src/BSP/bsp_qspi_w25q128.c:318:13:QSPI_W25Qx_Exit	72	static
+../Core/BASE/Src/BSP/bsp_qspi_w25q128.c:352:6:QSPI_W25Qx_Read_Buffer	80	static
+../Core/BASE/Src/BSP/bsp_qspi_w25q128.c:401:6:QSPI_W25Qx_Reset_Memory	64	static
+../Core/BASE/Src/BSP/bsp_qspi_w25q128.c:452:6:user_Assert	16	static
+../Core/BASE/Src/BSP/bsp_qspi_w25q128.c:478:6:QSPI_W25Qx_EraseDownLoadFlash	16	static
diff --git a/Debug/Core/BASE/Src/BSP/pb_common.cyclo b/Debug/Core/BASE/Src/BSP/pb_common.cyclo
new file mode 100644
index 0000000..ab5c668
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/pb_common.cyclo
@@ -0,0 +1,11 @@
+../Core/BASE/Src/BSP/pb_common.c:8:13:load_descriptor_values	15
+../Core/BASE/Src/BSP/pb_common.c:122:13:advance_iterator	4
+../Core/BASE/Src/BSP/pb_common.c:156:6:pb_field_iter_begin	1
+../Core/BASE/Src/BSP/pb_common.c:166:6:pb_field_iter_begin_extension	2
+../Core/BASE/Src/BSP/pb_common.c:188:6:pb_field_iter_next	1
+../Core/BASE/Src/BSP/pb_common.c:195:6:pb_field_iter_find	8
+../Core/BASE/Src/BSP/pb_common.c:246:6:pb_field_iter_find_extension	4
+../Core/BASE/Src/BSP/pb_common.c:277:14:pb_const_cast	1
+../Core/BASE/Src/BSP/pb_common.c:290:6:pb_field_iter_begin_const	1
+../Core/BASE/Src/BSP/pb_common.c:295:6:pb_field_iter_begin_extension_const	1
+../Core/BASE/Src/BSP/pb_common.c:300:6:pb_default_field_callback	7
diff --git a/Debug/Core/BASE/Src/BSP/pb_common.d b/Debug/Core/BASE/Src/BSP/pb_common.d
new file mode 100644
index 0000000..c4e25eb
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/pb_common.d
@@ -0,0 +1,5 @@
+Core/BASE/Src/BSP/pb_common.o: ../Core/BASE/Src/BSP/pb_common.c \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_common.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_common.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
diff --git a/Debug/Core/BASE/Src/BSP/pb_common.o b/Debug/Core/BASE/Src/BSP/pb_common.o
new file mode 100644
index 0000000..267bdff
Binary files /dev/null and b/Debug/Core/BASE/Src/BSP/pb_common.o differ
diff --git a/Debug/Core/BASE/Src/BSP/pb_common.su b/Debug/Core/BASE/Src/BSP/pb_common.su
new file mode 100644
index 0000000..6c264e3
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/pb_common.su
@@ -0,0 +1,11 @@
+../Core/BASE/Src/BSP/pb_common.c:8:13:load_descriptor_values	64	static
+../Core/BASE/Src/BSP/pb_common.c:122:13:advance_iterator	24	static
+../Core/BASE/Src/BSP/pb_common.c:156:6:pb_field_iter_begin	24	static
+../Core/BASE/Src/BSP/pb_common.c:166:6:pb_field_iter_begin_extension	32	static
+../Core/BASE/Src/BSP/pb_common.c:188:6:pb_field_iter_next	16	static
+../Core/BASE/Src/BSP/pb_common.c:195:6:pb_field_iter_find	24	static
+../Core/BASE/Src/BSP/pb_common.c:246:6:pb_field_iter_find_extension	24	static
+../Core/BASE/Src/BSP/pb_common.c:277:14:pb_const_cast	24	static
+../Core/BASE/Src/BSP/pb_common.c:290:6:pb_field_iter_begin_const	24	static
+../Core/BASE/Src/BSP/pb_common.c:295:6:pb_field_iter_begin_extension_const	16	static
+../Core/BASE/Src/BSP/pb_common.c:300:6:pb_default_field_callback	32	static
diff --git a/Debug/Core/BASE/Src/BSP/pb_decode.cyclo b/Debug/Core/BASE/Src/BSP/pb_decode.cyclo
new file mode 100644
index 0000000..1f6c0fa
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/pb_decode.cyclo
@@ -0,0 +1,37 @@
+../Core/BASE/Src/BSP/pb_decode.c:68:25:buf_read	2
+../Core/BASE/Src/BSP/pb_decode.c:81:18:pb_read	11
+../Core/BASE/Src/BSP/pb_decode.c:124:25:pb_readbyte	5
+../Core/BASE/Src/BSP/pb_decode.c:142:14:pb_istream_from_buffer	1
+../Core/BASE/Src/BSP/pb_decode.c:170:25:pb_decode_varint32_eof	19
+../Core/BASE/Src/BSP/pb_decode.c:236:18:pb_decode_varint32	1
+../Core/BASE/Src/BSP/pb_decode.c:242:18:pb_decode_varint	6
+../Core/BASE/Src/BSP/pb_decode.c:265:18:pb_skip_varint	3
+../Core/BASE/Src/BSP/pb_decode.c:276:18:pb_skip_string	2
+../Core/BASE/Src/BSP/pb_decode.c:290:18:pb_decode_tag	2
+../Core/BASE/Src/BSP/pb_decode.c:307:18:pb_skip_field	6
+../Core/BASE/Src/BSP/pb_decode.c:322:25:read_raw_value	10
+../Core/BASE/Src/BSP/pb_decode.c:361:18:pb_make_string_substream	4
+../Core/BASE/Src/BSP/pb_decode.c:376:18:pb_close_string_substream	3
+../Core/BASE/Src/BSP/pb_decode.c:395:25:decode_basic_field	30
+../Core/BASE/Src/BSP/pb_decode.c:466:25:decode_static_field	29
+../Core/BASE/Src/BSP/pb_decode.c:623:25:decode_pointer_field	2
+../Core/BASE/Src/BSP/pb_decode.c:751:25:decode_callback_field	11
+../Core/BASE/Src/BSP/pb_decode.c:797:25:decode_field	6
+../Core/BASE/Src/BSP/pb_decode.c:828:25:default_extension_decoder	5
+../Core/BASE/Src/BSP/pb_decode.c:845:25:decode_extension	5
+../Core/BASE/Src/BSP/pb_decode.c:868:13:pb_field_set_to_default	21
+../Core/BASE/Src/BSP/pb_decode.c:950:13:pb_message_set_to_defaults	10
+../Core/BASE/Src/BSP/pb_decode.c:989:25:pb_decode_inner	40
+../Core/BASE/Src/BSP/pb_decode.c:1153:18:pb_decode_ex	4
+../Core/BASE/Src/BSP/pb_decode.c:1181:18:pb_decode	1
+../Core/BASE/Src/BSP/pb_decode.c:1335:6:pb_release	1
+../Core/BASE/Src/BSP/pb_decode.c:1345:6:pb_decode_bool	2
+../Core/BASE/Src/BSP/pb_decode.c:1355:6:pb_decode_svarint	3
+../Core/BASE/Src/BSP/pb_decode.c:1369:6:pb_decode_fixed32	2
+../Core/BASE/Src/BSP/pb_decode.c:1392:6:pb_decode_fixed64	2
+../Core/BASE/Src/BSP/pb_decode.c:1419:25:pb_dec_bool	1
+../Core/BASE/Src/BSP/pb_decode.c:1424:25:pb_dec_varint	21
+../Core/BASE/Src/BSP/pb_decode.c:1496:25:pb_dec_bytes	10
+../Core/BASE/Src/BSP/pb_decode.c:1536:25:pb_dec_string	11
+../Core/BASE/Src/BSP/pb_decode.c:1586:25:pb_dec_submessage	13
+../Core/BASE/Src/BSP/pb_decode.c:1638:25:pb_dec_fixed_length_bytes	7
diff --git a/Debug/Core/BASE/Src/BSP/pb_decode.d b/Debug/Core/BASE/Src/BSP/pb_decode.d
new file mode 100644
index 0000000..a29e947
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/pb_decode.d
@@ -0,0 +1,9 @@
+Core/BASE/Src/BSP/pb_decode.o: ../Core/BASE/Src/BSP/pb_decode.c \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_common.h
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_common.h:
diff --git a/Debug/Core/BASE/Src/BSP/pb_decode.o b/Debug/Core/BASE/Src/BSP/pb_decode.o
new file mode 100644
index 0000000..f58bd56
Binary files /dev/null and b/Debug/Core/BASE/Src/BSP/pb_decode.o differ
diff --git a/Debug/Core/BASE/Src/BSP/pb_decode.su b/Debug/Core/BASE/Src/BSP/pb_decode.su
new file mode 100644
index 0000000..66efa93
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/pb_decode.su
@@ -0,0 +1,37 @@
+../Core/BASE/Src/BSP/pb_decode.c:68:25:buf_read	32	static
+../Core/BASE/Src/BSP/pb_decode.c:81:18:pb_read	40	static
+../Core/BASE/Src/BSP/pb_decode.c:124:25:pb_readbyte	16	static
+../Core/BASE/Src/BSP/pb_decode.c:142:14:pb_istream_from_buffer	48	static
+../Core/BASE/Src/BSP/pb_decode.c:170:25:pb_decode_varint32_eof	40	static
+../Core/BASE/Src/BSP/pb_decode.c:236:18:pb_decode_varint32	16	static
+../Core/BASE/Src/BSP/pb_decode.c:242:18:pb_decode_varint	72	static
+../Core/BASE/Src/BSP/pb_decode.c:265:18:pb_skip_varint	24	static
+../Core/BASE/Src/BSP/pb_decode.c:276:18:pb_skip_string	24	static
+../Core/BASE/Src/BSP/pb_decode.c:290:18:pb_decode_tag	32	static
+../Core/BASE/Src/BSP/pb_decode.c:307:18:pb_skip_field	16	static
+../Core/BASE/Src/BSP/pb_decode.c:322:25:read_raw_value	32	static
+../Core/BASE/Src/BSP/pb_decode.c:361:18:pb_make_string_substream	32	static
+../Core/BASE/Src/BSP/pb_decode.c:376:18:pb_close_string_substream	16	static
+../Core/BASE/Src/BSP/pb_decode.c:395:25:decode_basic_field	24	static
+../Core/BASE/Src/BSP/pb_decode.c:466:25:decode_static_field	96	static
+../Core/BASE/Src/BSP/pb_decode.c:623:25:decode_pointer_field	24	static
+../Core/BASE/Src/BSP/pb_decode.c:751:25:decode_callback_field	104	static
+../Core/BASE/Src/BSP/pb_decode.c:797:25:decode_field	24	static
+../Core/BASE/Src/BSP/pb_decode.c:828:25:default_extension_decoder	64	static
+../Core/BASE/Src/BSP/pb_decode.c:845:25:decode_extension	40	static
+../Core/BASE/Src/BSP/pb_decode.c:868:13:pb_field_set_to_default	64	static
+../Core/BASE/Src/BSP/pb_decode.c:950:13:pb_message_set_to_defaults	64	static
+../Core/BASE/Src/BSP/pb_decode.c:989:25:pb_decode_inner	112	static
+../Core/BASE/Src/BSP/pb_decode.c:1153:18:pb_decode_ex	48	static
+../Core/BASE/Src/BSP/pb_decode.c:1181:18:pb_decode	32	static
+../Core/BASE/Src/BSP/pb_decode.c:1335:6:pb_release	16	static
+../Core/BASE/Src/BSP/pb_decode.c:1345:6:pb_decode_bool	24	static
+../Core/BASE/Src/BSP/pb_decode.c:1355:6:pb_decode_svarint	40	static
+../Core/BASE/Src/BSP/pb_decode.c:1369:6:pb_decode_fixed32	24	static
+../Core/BASE/Src/BSP/pb_decode.c:1392:6:pb_decode_fixed64	24	static
+../Core/BASE/Src/BSP/pb_decode.c:1419:25:pb_dec_bool	16	static
+../Core/BASE/Src/BSP/pb_decode.c:1424:25:pb_dec_varint	112	static
+../Core/BASE/Src/BSP/pb_decode.c:1496:25:pb_dec_bytes	32	static
+../Core/BASE/Src/BSP/pb_decode.c:1536:25:pb_dec_string	32	static
+../Core/BASE/Src/BSP/pb_decode.c:1586:25:pb_dec_submessage	48	static
+../Core/BASE/Src/BSP/pb_decode.c:1638:25:pb_dec_fixed_length_bytes	24	static
diff --git a/Debug/Core/BASE/Src/BSP/pb_encode.cyclo b/Debug/Core/BASE/Src/BSP/pb_encode.cyclo
new file mode 100644
index 0000000..ed7214e
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/pb_encode.cyclo
@@ -0,0 +1,30 @@
+../Core/BASE/Src/BSP/pb_encode.c:52:25:buf_write	1
+../Core/BASE/Src/BSP/pb_encode.c:62:14:pb_ostream_from_buffer	1
+../Core/BASE/Src/BSP/pb_encode.c:83:18:pb_write	8
+../Core/BASE/Src/BSP/pb_encode.c:114:13:safe_read_bool	3
+../Core/BASE/Src/BSP/pb_encode.c:127:25:encode_array	29
+../Core/BASE/Src/BSP/pb_encode.c:243:25:pb_check_proto3_default_value	23
+../Core/BASE/Src/BSP/pb_encode.c:361:25:encode_basic_field	11
+../Core/BASE/Src/BSP/pb_encode.c:406:25:encode_callback_field	4
+../Core/BASE/Src/BSP/pb_encode.c:417:25:encode_field	13
+../Core/BASE/Src/BSP/pb_encode.c:473:25:default_extension_encoder	3
+../Core/BASE/Src/BSP/pb_encode.c:486:25:encode_extension_field	4
+../Core/BASE/Src/BSP/pb_encode.c:511:18:pb_encode	6
+../Core/BASE/Src/BSP/pb_encode.c:535:18:pb_encode_ex	4
+../Core/BASE/Src/BSP/pb_encode.c:556:6:pb_get_encoded_size	2
+../Core/BASE/Src/BSP/pb_encode.c:572:25:pb_encode_varint_32	6
+../Core/BASE/Src/BSP/pb_encode.c:606:18:pb_encode_varint	2
+../Core/BASE/Src/BSP/pb_encode.c:624:18:pb_encode_svarint	2
+../Core/BASE/Src/BSP/pb_encode.c:636:18:pb_encode_fixed32	1
+../Core/BASE/Src/BSP/pb_encode.c:653:18:pb_encode_fixed64	1
+../Core/BASE/Src/BSP/pb_encode.c:674:18:pb_encode_tag	1
+../Core/BASE/Src/BSP/pb_encode.c:680:6:pb_encode_tag_for_field	6
+../Core/BASE/Src/BSP/pb_encode.c:715:18:pb_encode_string	2
+../Core/BASE/Src/BSP/pb_encode.c:723:18:pb_encode_submessage	8
+../Core/BASE/Src/BSP/pb_encode.c:775:25:pb_enc_bool	1
+../Core/BASE/Src/BSP/pb_encode.c:782:25:pb_enc_varint	13
+../Core/BASE/Src/BSP/pb_encode.c:830:25:pb_enc_fixed	4
+../Core/BASE/Src/BSP/pb_encode.c:855:25:pb_enc_bytes	5
+../Core/BASE/Src/BSP/pb_encode.c:876:25:pb_enc_string	9
+../Core/BASE/Src/BSP/pb_encode.c:929:25:pb_enc_submessage	7
+../Core/BASE/Src/BSP/pb_encode.c:948:25:pb_enc_fixed_length_bytes	1
diff --git a/Debug/Core/BASE/Src/BSP/pb_encode.d b/Debug/Core/BASE/Src/BSP/pb_encode.d
new file mode 100644
index 0000000..8ca38c9
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/pb_encode.d
@@ -0,0 +1,9 @@
+Core/BASE/Src/BSP/pb_encode.o: ../Core/BASE/Src/BSP/pb_encode.c \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_common.h
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_common.h:
diff --git a/Debug/Core/BASE/Src/BSP/pb_encode.o b/Debug/Core/BASE/Src/BSP/pb_encode.o
new file mode 100644
index 0000000..45c6f4f
Binary files /dev/null and b/Debug/Core/BASE/Src/BSP/pb_encode.o differ
diff --git a/Debug/Core/BASE/Src/BSP/pb_encode.su b/Debug/Core/BASE/Src/BSP/pb_encode.su
new file mode 100644
index 0000000..cee471d
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/pb_encode.su
@@ -0,0 +1,30 @@
+../Core/BASE/Src/BSP/pb_encode.c:52:25:buf_write	32	static
+../Core/BASE/Src/BSP/pb_encode.c:62:14:pb_ostream_from_buffer	56	static
+../Core/BASE/Src/BSP/pb_encode.c:83:18:pb_write	24	static
+../Core/BASE/Src/BSP/pb_encode.c:114:13:safe_read_bool	24	static
+../Core/BASE/Src/BSP/pb_encode.c:127:25:encode_array	64	static
+../Core/BASE/Src/BSP/pb_encode.c:243:25:pb_check_proto3_default_value	80	static
+../Core/BASE/Src/BSP/pb_encode.c:361:25:encode_basic_field	16	static
+../Core/BASE/Src/BSP/pb_encode.c:406:25:encode_callback_field	16	static
+../Core/BASE/Src/BSP/pb_encode.c:417:25:encode_field	16	static
+../Core/BASE/Src/BSP/pb_encode.c:473:25:default_extension_encoder	56	static
+../Core/BASE/Src/BSP/pb_encode.c:486:25:encode_extension_field	24	static
+../Core/BASE/Src/BSP/pb_encode.c:511:18:pb_encode	64	static
+../Core/BASE/Src/BSP/pb_encode.c:535:18:pb_encode_ex	32	static
+../Core/BASE/Src/BSP/pb_encode.c:556:6:pb_get_encoded_size	48	static
+../Core/BASE/Src/BSP/pb_encode.c:572:25:pb_encode_varint_32	40	static
+../Core/BASE/Src/BSP/pb_encode.c:606:18:pb_encode_varint	40	static
+../Core/BASE/Src/BSP/pb_encode.c:624:18:pb_encode_svarint	72	static
+../Core/BASE/Src/BSP/pb_encode.c:636:18:pb_encode_fixed32	16	static
+../Core/BASE/Src/BSP/pb_encode.c:653:18:pb_encode_fixed64	16	static
+../Core/BASE/Src/BSP/pb_encode.c:674:18:pb_encode_tag	64	static
+../Core/BASE/Src/BSP/pb_encode.c:680:6:pb_encode_tag_for_field	24	static
+../Core/BASE/Src/BSP/pb_encode.c:715:18:pb_encode_string	32	static
+../Core/BASE/Src/BSP/pb_encode.c:723:18:pb_encode_submessage	64	static
+../Core/BASE/Src/BSP/pb_encode.c:775:25:pb_enc_bool	32	static
+../Core/BASE/Src/BSP/pb_encode.c:782:25:pb_enc_varint	80	static
+../Core/BASE/Src/BSP/pb_encode.c:830:25:pb_enc_fixed	16	static
+../Core/BASE/Src/BSP/pb_encode.c:855:25:pb_enc_bytes	24	static
+../Core/BASE/Src/BSP/pb_encode.c:876:25:pb_enc_string	32	static
+../Core/BASE/Src/BSP/pb_encode.c:929:25:pb_enc_submessage	24	static
+../Core/BASE/Src/BSP/pb_encode.c:948:25:pb_enc_fixed_length_bytes	16	static
diff --git a/Debug/Core/BASE/Src/BSP/subdir.mk b/Debug/Core/BASE/Src/BSP/subdir.mk
new file mode 100644
index 0000000..c5281ee
--- /dev/null
+++ b/Debug/Core/BASE/Src/BSP/subdir.mk
@@ -0,0 +1,81 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+# Toolchain: GNU Tools for STM32 (12.3.rel1)
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables 
+C_SRCS += \
+../Core/BASE/Src/BSP/BHBF_ROBOT.c \
+../Core/BASE/Src/BSP/bsp_DLT_Log.c \
+../Core/BASE/Src/BSP/bsp_EEPROM.c \
+../Core/BASE/Src/BSP/bsp_Error_Detect.c \
+../Core/BASE/Src/BSP/bsp_FDCAN.c \
+../Core/BASE/Src/BSP/bsp_GPIO.c \
+../Core/BASE/Src/BSP/bsp_INTERCALL.c \
+../Core/BASE/Src/BSP/bsp_MB_host.c \
+../Core/BASE/Src/BSP/bsp_TIMER.c \
+../Core/BASE/Src/BSP/bsp_UART.c \
+../Core/BASE/Src/BSP/bsp_UpperComputer_Handler.c \
+../Core/BASE/Src/BSP/bsp_client_setting.c \
+../Core/BASE/Src/BSP/bsp_com_helper.c \
+../Core/BASE/Src/BSP/bsp_cpu_flash.c \
+../Core/BASE/Src/BSP/bsp_decode_command.c \
+../Core/BASE/Src/BSP/bsp_qspi_w25q128.c \
+../Core/BASE/Src/BSP/pb_common.c \
+../Core/BASE/Src/BSP/pb_decode.c \
+../Core/BASE/Src/BSP/pb_encode.c 
+
+OBJS += \
+./Core/BASE/Src/BSP/BHBF_ROBOT.o \
+./Core/BASE/Src/BSP/bsp_DLT_Log.o \
+./Core/BASE/Src/BSP/bsp_EEPROM.o \
+./Core/BASE/Src/BSP/bsp_Error_Detect.o \
+./Core/BASE/Src/BSP/bsp_FDCAN.o \
+./Core/BASE/Src/BSP/bsp_GPIO.o \
+./Core/BASE/Src/BSP/bsp_INTERCALL.o \
+./Core/BASE/Src/BSP/bsp_MB_host.o \
+./Core/BASE/Src/BSP/bsp_TIMER.o \
+./Core/BASE/Src/BSP/bsp_UART.o \
+./Core/BASE/Src/BSP/bsp_UpperComputer_Handler.o \
+./Core/BASE/Src/BSP/bsp_client_setting.o \
+./Core/BASE/Src/BSP/bsp_com_helper.o \
+./Core/BASE/Src/BSP/bsp_cpu_flash.o \
+./Core/BASE/Src/BSP/bsp_decode_command.o \
+./Core/BASE/Src/BSP/bsp_qspi_w25q128.o \
+./Core/BASE/Src/BSP/pb_common.o \
+./Core/BASE/Src/BSP/pb_decode.o \
+./Core/BASE/Src/BSP/pb_encode.o 
+
+C_DEPS += \
+./Core/BASE/Src/BSP/BHBF_ROBOT.d \
+./Core/BASE/Src/BSP/bsp_DLT_Log.d \
+./Core/BASE/Src/BSP/bsp_EEPROM.d \
+./Core/BASE/Src/BSP/bsp_Error_Detect.d \
+./Core/BASE/Src/BSP/bsp_FDCAN.d \
+./Core/BASE/Src/BSP/bsp_GPIO.d \
+./Core/BASE/Src/BSP/bsp_INTERCALL.d \
+./Core/BASE/Src/BSP/bsp_MB_host.d \
+./Core/BASE/Src/BSP/bsp_TIMER.d \
+./Core/BASE/Src/BSP/bsp_UART.d \
+./Core/BASE/Src/BSP/bsp_UpperComputer_Handler.d \
+./Core/BASE/Src/BSP/bsp_client_setting.d \
+./Core/BASE/Src/BSP/bsp_com_helper.d \
+./Core/BASE/Src/BSP/bsp_cpu_flash.d \
+./Core/BASE/Src/BSP/bsp_decode_command.d \
+./Core/BASE/Src/BSP/bsp_qspi_w25q128.d \
+./Core/BASE/Src/BSP/pb_common.d \
+./Core/BASE/Src/BSP/pb_decode.d \
+./Core/BASE/Src/BSP/pb_encode.d 
+
+
+# Each subdirectory must supply rules for building sources it contributes
+Core/BASE/Src/BSP/%.o Core/BASE/Src/BSP/%.su Core/BASE/Src/BSP/%.cyclo: ../Core/BASE/Src/BSP/%.c Core/BASE/Src/BSP/subdir.mk
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32H743xx -c -I../Core/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I../Drivers/CMSIS/Include -I"F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc" -I"F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource" -I"F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP" -I"F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
+
+clean: clean-Core-2f-BASE-2f-Src-2f-BSP
+
+clean-Core-2f-BASE-2f-Src-2f-BSP:
+	-$(RM) ./Core/BASE/Src/BSP/BHBF_ROBOT.cyclo ./Core/BASE/Src/BSP/BHBF_ROBOT.d ./Core/BASE/Src/BSP/BHBF_ROBOT.o ./Core/BASE/Src/BSP/BHBF_ROBOT.su ./Core/BASE/Src/BSP/bsp_DLT_Log.cyclo ./Core/BASE/Src/BSP/bsp_DLT_Log.d ./Core/BASE/Src/BSP/bsp_DLT_Log.o ./Core/BASE/Src/BSP/bsp_DLT_Log.su ./Core/BASE/Src/BSP/bsp_EEPROM.cyclo ./Core/BASE/Src/BSP/bsp_EEPROM.d ./Core/BASE/Src/BSP/bsp_EEPROM.o ./Core/BASE/Src/BSP/bsp_EEPROM.su ./Core/BASE/Src/BSP/bsp_Error_Detect.cyclo ./Core/BASE/Src/BSP/bsp_Error_Detect.d ./Core/BASE/Src/BSP/bsp_Error_Detect.o ./Core/BASE/Src/BSP/bsp_Error_Detect.su ./Core/BASE/Src/BSP/bsp_FDCAN.cyclo ./Core/BASE/Src/BSP/bsp_FDCAN.d ./Core/BASE/Src/BSP/bsp_FDCAN.o ./Core/BASE/Src/BSP/bsp_FDCAN.su ./Core/BASE/Src/BSP/bsp_GPIO.cyclo ./Core/BASE/Src/BSP/bsp_GPIO.d ./Core/BASE/Src/BSP/bsp_GPIO.o ./Core/BASE/Src/BSP/bsp_GPIO.su ./Core/BASE/Src/BSP/bsp_INTERCALL.cyclo ./Core/BASE/Src/BSP/bsp_INTERCALL.d ./Core/BASE/Src/BSP/bsp_INTERCALL.o ./Core/BASE/Src/BSP/bsp_INTERCALL.su ./Core/BASE/Src/BSP/bsp_MB_host.cyclo ./Core/BASE/Src/BSP/bsp_MB_host.d ./Core/BASE/Src/BSP/bsp_MB_host.o ./Core/BASE/Src/BSP/bsp_MB_host.su ./Core/BASE/Src/BSP/bsp_TIMER.cyclo ./Core/BASE/Src/BSP/bsp_TIMER.d ./Core/BASE/Src/BSP/bsp_TIMER.o ./Core/BASE/Src/BSP/bsp_TIMER.su ./Core/BASE/Src/BSP/bsp_UART.cyclo ./Core/BASE/Src/BSP/bsp_UART.d ./Core/BASE/Src/BSP/bsp_UART.o ./Core/BASE/Src/BSP/bsp_UART.su ./Core/BASE/Src/BSP/bsp_UpperComputer_Handler.cyclo ./Core/BASE/Src/BSP/bsp_UpperComputer_Handler.d ./Core/BASE/Src/BSP/bsp_UpperComputer_Handler.o ./Core/BASE/Src/BSP/bsp_UpperComputer_Handler.su ./Core/BASE/Src/BSP/bsp_client_setting.cyclo ./Core/BASE/Src/BSP/bsp_client_setting.d ./Core/BASE/Src/BSP/bsp_client_setting.o ./Core/BASE/Src/BSP/bsp_client_setting.su ./Core/BASE/Src/BSP/bsp_com_helper.cyclo ./Core/BASE/Src/BSP/bsp_com_helper.d ./Core/BASE/Src/BSP/bsp_com_helper.o ./Core/BASE/Src/BSP/bsp_com_helper.su ./Core/BASE/Src/BSP/bsp_cpu_flash.cyclo ./Core/BASE/Src/BSP/bsp_cpu_flash.d ./Core/BASE/Src/BSP/bsp_cpu_flash.o ./Core/BASE/Src/BSP/bsp_cpu_flash.su ./Core/BASE/Src/BSP/bsp_decode_command.cyclo ./Core/BASE/Src/BSP/bsp_decode_command.d ./Core/BASE/Src/BSP/bsp_decode_command.o ./Core/BASE/Src/BSP/bsp_decode_command.su ./Core/BASE/Src/BSP/bsp_qspi_w25q128.cyclo ./Core/BASE/Src/BSP/bsp_qspi_w25q128.d ./Core/BASE/Src/BSP/bsp_qspi_w25q128.o ./Core/BASE/Src/BSP/bsp_qspi_w25q128.su ./Core/BASE/Src/BSP/pb_common.cyclo ./Core/BASE/Src/BSP/pb_common.d ./Core/BASE/Src/BSP/pb_common.o ./Core/BASE/Src/BSP/pb_common.su ./Core/BASE/Src/BSP/pb_decode.cyclo ./Core/BASE/Src/BSP/pb_decode.d ./Core/BASE/Src/BSP/pb_decode.o ./Core/BASE/Src/BSP/pb_decode.su ./Core/BASE/Src/BSP/pb_encode.cyclo ./Core/BASE/Src/BSP/pb_encode.d ./Core/BASE/Src/BSP/pb_encode.o ./Core/BASE/Src/BSP/pb_encode.su
+
+.PHONY: clean-Core-2f-BASE-2f-Src-2f-BSP
+
diff --git a/Debug/Core/BASE/Src/MSP/msp_Blast_Machine.cyclo b/Debug/Core/BASE/Src/MSP/msp_Blast_Machine.cyclo
new file mode 100644
index 0000000..ed816a6
--- /dev/null
+++ b/Debug/Core/BASE/Src/MSP/msp_Blast_Machine.cyclo
@@ -0,0 +1,10 @@
+../Core/BASE/Src/MSP/msp_Blast_Machine.c:22:6:blast_control_intialize	1
+../Core/BASE/Src/MSP/msp_Blast_Machine.c:30:6:Blast_Machine_Control_Fun	7
+../Core/BASE/Src/MSP/msp_Blast_Machine.c:52:5:BlastMachineEncodeHandle	3
+../Core/BASE/Src/MSP/msp_Blast_Machine.c:79:6:Blast_Machine_Open_Fun	9
+../Core/BASE/Src/MSP/msp_Blast_Machine.c:125:6:Blast_Machine_Close_Fun	9
+../Core/BASE/Src/MSP/msp_Blast_Machine.c:178:13:code_to_str	8
+../Core/BASE/Src/MSP/msp_Blast_Machine.c:205:13:str_to_bin	9
+../Core/BASE/Src/MSP/msp_Blast_Machine.c:243:13:bin_to_hex	13
+../Core/BASE/Src/MSP/msp_Blast_Machine.c:295:13:hex_to_bytes	5
+../Core/BASE/Src/MSP/msp_Blast_Machine.c:324:6:encode_to_arrays	17
diff --git a/Debug/Core/BASE/Src/MSP/msp_Blast_Machine.d b/Debug/Core/BASE/Src/MSP/msp_Blast_Machine.d
new file mode 100644
index 0000000..76f6e1c
--- /dev/null
+++ b/Debug/Core/BASE/Src/MSP/msp_Blast_Machine.d
@@ -0,0 +1,209 @@
+Core/BASE/Src/MSP/msp_Blast_Machine.o: \
+ ../Core/BASE/Src/MSP/msp_Blast_Machine.c \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_Blast_Machine.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UART.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ ../Core/Inc/main.h ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
+ ../Core/Inc/dma.h ../Core/Inc/main.h ../Core/Inc/fdcan.h \
+ ../Core/Inc/i2c.h ../Core/Inc/tim.h ../Core/Inc/usart.h \
+ ../Core/Inc/gpio.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_CV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IAP.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_GPIO.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_com_helper.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_TIMER.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_GV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_TL720D.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IO.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_CMCU.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_common.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTuc.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTucConfig.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_JTBATTERY.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_pb_decode_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TL720D.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_MK32_1.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_WH_LTE_7S0.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_DLT_Log.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UDP.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_cpu_flash.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_qspi_w25q128.h \
+ ../Core/Inc/quadspi.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UpperComputer_Handler.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TTMotor_ZQ.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h \
+ ../Core/Inc/fsm.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_Error_Detect.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IV.pb.h
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_Blast_Machine.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UART.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+../Core/Inc/main.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
+../Core/Inc/dma.h:
+../Core/Inc/main.h:
+../Core/Inc/fdcan.h:
+../Core/Inc/i2c.h:
+../Core/Inc/tim.h:
+../Core/Inc/usart.h:
+../Core/Inc/gpio.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_CV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IAP.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_GPIO.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_com_helper.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_TIMER.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_GV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_TL720D.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IO.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_CMCU.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_common.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTuc.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTucConfig.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_JTBATTERY.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_pb_decode_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TL720D.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_MK32_1.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_WH_LTE_7S0.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_DLT_Log.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UDP.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_cpu_flash.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_qspi_w25q128.h:
+../Core/Inc/quadspi.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UpperComputer_Handler.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TTMotor_ZQ.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h:
+../Core/Inc/fsm.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_Error_Detect.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IV.pb.h:
diff --git a/Debug/Core/BASE/Src/MSP/msp_Blast_Machine.o b/Debug/Core/BASE/Src/MSP/msp_Blast_Machine.o
new file mode 100644
index 0000000..87734b8
Binary files /dev/null and b/Debug/Core/BASE/Src/MSP/msp_Blast_Machine.o differ
diff --git a/Debug/Core/BASE/Src/MSP/msp_Blast_Machine.su b/Debug/Core/BASE/Src/MSP/msp_Blast_Machine.su
new file mode 100644
index 0000000..619f47f
--- /dev/null
+++ b/Debug/Core/BASE/Src/MSP/msp_Blast_Machine.su
@@ -0,0 +1,10 @@
+../Core/BASE/Src/MSP/msp_Blast_Machine.c:22:6:blast_control_intialize	16	static
+../Core/BASE/Src/MSP/msp_Blast_Machine.c:30:6:Blast_Machine_Control_Fun	8	static
+../Core/BASE/Src/MSP/msp_Blast_Machine.c:52:5:BlastMachineEncodeHandle	16	static
+../Core/BASE/Src/MSP/msp_Blast_Machine.c:79:6:Blast_Machine_Open_Fun	8	static
+../Core/BASE/Src/MSP/msp_Blast_Machine.c:125:6:Blast_Machine_Close_Fun	8	static
+../Core/BASE/Src/MSP/msp_Blast_Machine.c:178:13:code_to_str	24	static
+../Core/BASE/Src/MSP/msp_Blast_Machine.c:205:13:str_to_bin	24	static
+../Core/BASE/Src/MSP/msp_Blast_Machine.c:243:13:bin_to_hex	64	static
+../Core/BASE/Src/MSP/msp_Blast_Machine.c:295:13:hex_to_bytes	40	static
+../Core/BASE/Src/MSP/msp_Blast_Machine.c:324:6:encode_to_arrays	184	static
diff --git a/Debug/Core/BASE/Src/MSP/msp_CMCUU.cyclo b/Debug/Core/BASE/Src/MSP/msp_CMCUU.cyclo
new file mode 100644
index 0000000..69db9ac
--- /dev/null
+++ b/Debug/Core/BASE/Src/MSP/msp_CMCUU.cyclo
@@ -0,0 +1,4 @@
+../Core/BASE/Src/MSP/msp_CMCUU.c:30:6:CMCU_sensor_intialize	2
+../Core/BASE/Src/MSP/msp_CMCUU.c:48:6:GF_CMCU_Inquiry	1
+../Core/BASE/Src/MSP/msp_CMCUU.c:55:6:decode_cmcu_sensor	6
+../Core/BASE/Src/MSP/msp_CMCUU.c:74:6:CMCU_Command_Comp	3
diff --git a/Debug/Core/BASE/Src/MSP/msp_CMCUU.d b/Debug/Core/BASE/Src/MSP/msp_CMCUU.d
new file mode 100644
index 0000000..c09b708
--- /dev/null
+++ b/Debug/Core/BASE/Src/MSP/msp_CMCUU.d
@@ -0,0 +1,208 @@
+Core/BASE/Src/MSP/msp_CMCUU.o: ../Core/BASE/Src/MSP/msp_CMCUU.c \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_CMCUU.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UART.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ ../Core/Inc/main.h ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
+ ../Core/Inc/dma.h ../Core/Inc/main.h ../Core/Inc/fdcan.h \
+ ../Core/Inc/i2c.h ../Core/Inc/tim.h ../Core/Inc/usart.h \
+ ../Core/Inc/gpio.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_CV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IAP.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_GPIO.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_com_helper.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_TIMER.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_GV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_TL720D.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IO.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_CMCU.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_common.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTuc.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTucConfig.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_CMCU.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_JTBATTERY.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_pb_decode_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TL720D.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_MK32_1.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_WH_LTE_7S0.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_DLT_Log.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UDP.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_cpu_flash.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_qspi_w25q128.h \
+ ../Core/Inc/quadspi.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UpperComputer_Handler.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TTMotor_ZQ.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h \
+ ../Core/Inc/fsm.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_Error_Detect.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IV.pb.h
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_CMCUU.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UART.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+../Core/Inc/main.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
+../Core/Inc/dma.h:
+../Core/Inc/main.h:
+../Core/Inc/fdcan.h:
+../Core/Inc/i2c.h:
+../Core/Inc/tim.h:
+../Core/Inc/usart.h:
+../Core/Inc/gpio.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_CV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IAP.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_GPIO.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_com_helper.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_TIMER.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_GV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_TL720D.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IO.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_CMCU.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_common.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTuc.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTucConfig.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_CMCU.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_JTBATTERY.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_pb_decode_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TL720D.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_MK32_1.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_WH_LTE_7S0.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_DLT_Log.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UDP.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_cpu_flash.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_qspi_w25q128.h:
+../Core/Inc/quadspi.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UpperComputer_Handler.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TTMotor_ZQ.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h:
+../Core/Inc/fsm.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_Error_Detect.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IV.pb.h:
diff --git a/Debug/Core/BASE/Src/MSP/msp_CMCUU.o b/Debug/Core/BASE/Src/MSP/msp_CMCUU.o
new file mode 100644
index 0000000..d511942
Binary files /dev/null and b/Debug/Core/BASE/Src/MSP/msp_CMCUU.o differ
diff --git a/Debug/Core/BASE/Src/MSP/msp_CMCUU.su b/Debug/Core/BASE/Src/MSP/msp_CMCUU.su
new file mode 100644
index 0000000..c8f2550
--- /dev/null
+++ b/Debug/Core/BASE/Src/MSP/msp_CMCUU.su
@@ -0,0 +1,4 @@
+../Core/BASE/Src/MSP/msp_CMCUU.c:30:6:CMCU_sensor_intialize	24	static
+../Core/BASE/Src/MSP/msp_CMCUU.c:48:6:GF_CMCU_Inquiry	8	static
+../Core/BASE/Src/MSP/msp_CMCUU.c:55:6:decode_cmcu_sensor	16	static
+../Core/BASE/Src/MSP/msp_CMCUU.c:74:6:CMCU_Command_Comp	4	static
diff --git a/Debug/Core/BASE/Src/MSP/msp_KS206.cyclo b/Debug/Core/BASE/Src/MSP/msp_KS206.cyclo
new file mode 100644
index 0000000..af4ad16
--- /dev/null
+++ b/Debug/Core/BASE/Src/MSP/msp_KS206.cyclo
@@ -0,0 +1,4 @@
+../Core/BASE/Src/MSP/msp_KS206.c:29:6:KS206_sensor_intialize	2
+../Core/BASE/Src/MSP/msp_KS206.c:52:6:GF_KS206_Inquiry	1
+../Core/BASE/Src/MSP/msp_KS206.c:59:6:decode_ks206_sensor	6
+../Core/BASE/Src/MSP/msp_KS206.c:79:6:KS206_Command_Comp	1
diff --git a/Debug/Core/BASE/Src/MSP/msp_KS206.d b/Debug/Core/BASE/Src/MSP/msp_KS206.d
new file mode 100644
index 0000000..82b88bc
--- /dev/null
+++ b/Debug/Core/BASE/Src/MSP/msp_KS206.d
@@ -0,0 +1,208 @@
+Core/BASE/Src/MSP/msp_KS206.o: ../Core/BASE/Src/MSP/msp_KS206.c \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_KS206.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UART.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ ../Core/Inc/main.h ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
+ ../Core/Inc/dma.h ../Core/Inc/main.h ../Core/Inc/fdcan.h \
+ ../Core/Inc/i2c.h ../Core/Inc/tim.h ../Core/Inc/usart.h \
+ ../Core/Inc/gpio.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_CV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IAP.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_GPIO.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_com_helper.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_TIMER.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_GV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_TL720D.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IO.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_CMCU.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_common.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTuc.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTucConfig.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_JTBATTERY.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_pb_decode_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TL720D.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_MK32_1.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_WH_LTE_7S0.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_DLT_Log.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UDP.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_cpu_flash.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_qspi_w25q128.h \
+ ../Core/Inc/quadspi.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UpperComputer_Handler.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TTMotor_ZQ.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h \
+ ../Core/Inc/fsm.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_Error_Detect.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IV.pb.h
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_KS206.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UART.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+../Core/Inc/main.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
+../Core/Inc/dma.h:
+../Core/Inc/main.h:
+../Core/Inc/fdcan.h:
+../Core/Inc/i2c.h:
+../Core/Inc/tim.h:
+../Core/Inc/usart.h:
+../Core/Inc/gpio.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_CV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IAP.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_GPIO.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_com_helper.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_TIMER.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_GV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_TL720D.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IO.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_CMCU.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_common.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTuc.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTucConfig.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_JTBATTERY.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_pb_decode_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TL720D.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_MK32_1.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_WH_LTE_7S0.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_DLT_Log.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UDP.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_cpu_flash.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_qspi_w25q128.h:
+../Core/Inc/quadspi.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UpperComputer_Handler.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TTMotor_ZQ.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h:
+../Core/Inc/fsm.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_Error_Detect.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IV.pb.h:
diff --git a/Debug/Core/BASE/Src/MSP/msp_KS206.o b/Debug/Core/BASE/Src/MSP/msp_KS206.o
new file mode 100644
index 0000000..db43723
Binary files /dev/null and b/Debug/Core/BASE/Src/MSP/msp_KS206.o differ
diff --git a/Debug/Core/BASE/Src/MSP/msp_KS206.su b/Debug/Core/BASE/Src/MSP/msp_KS206.su
new file mode 100644
index 0000000..96cb0ae
--- /dev/null
+++ b/Debug/Core/BASE/Src/MSP/msp_KS206.su
@@ -0,0 +1,4 @@
+../Core/BASE/Src/MSP/msp_KS206.c:29:6:KS206_sensor_intialize	16	static
+../Core/BASE/Src/MSP/msp_KS206.c:52:6:GF_KS206_Inquiry	8	static
+../Core/BASE/Src/MSP/msp_KS206.c:59:6:decode_ks206_sensor	16	static
+../Core/BASE/Src/MSP/msp_KS206.c:79:6:KS206_Command_Comp	4	static
diff --git a/Debug/Core/BASE/Src/MSP/msp_MF_Gyroscope.cyclo b/Debug/Core/BASE/Src/MSP/msp_MF_Gyroscope.cyclo
new file mode 100644
index 0000000..e580ee7
--- /dev/null
+++ b/Debug/Core/BASE/Src/MSP/msp_MF_Gyroscope.cyclo
@@ -0,0 +1,3 @@
+../Core/BASE/Src/MSP/msp_MF_Gyroscope.c:29:9:GF_MSP_Gyro_MFOG40_Init	1
+../Core/BASE/Src/MSP/msp_MF_Gyroscope.c:39:7:GF_Gyro_Unscramble_Callback	18
+../Core/BASE/Src/MSP/msp_MF_Gyroscope.c:132:6:Gyro_Command_Comp	5
diff --git a/Debug/Core/BASE/Src/MSP/msp_MF_Gyroscope.d b/Debug/Core/BASE/Src/MSP/msp_MF_Gyroscope.d
new file mode 100644
index 0000000..100e485
--- /dev/null
+++ b/Debug/Core/BASE/Src/MSP/msp_MF_Gyroscope.d
@@ -0,0 +1,209 @@
+Core/BASE/Src/MSP/msp_MF_Gyroscope.o: \
+ ../Core/BASE/Src/MSP/msp_MF_Gyroscope.c \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_Error_Detect.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ ../Core/Inc/main.h ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
+ ../Core/Inc/dma.h ../Core/Inc/main.h ../Core/Inc/fdcan.h \
+ ../Core/Inc/i2c.h ../Core/Inc/tim.h ../Core/Inc/usart.h \
+ ../Core/Inc/gpio.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_CV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IAP.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_GPIO.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_com_helper.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_TIMER.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_GV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_TL720D.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IO.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_CMCU.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_common.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTuc.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTucConfig.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_JTBATTERY.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UART.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_pb_decode_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TL720D.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_MK32_1.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_WH_LTE_7S0.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_DLT_Log.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UDP.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_cpu_flash.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_qspi_w25q128.h \
+ ../Core/Inc/quadspi.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UpperComputer_Handler.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TTMotor_ZQ.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h \
+ ../Core/Inc/fsm.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_Error_Detect.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_MF_Gyroscope.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_Error_Detect.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+../Core/Inc/main.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
+../Core/Inc/dma.h:
+../Core/Inc/main.h:
+../Core/Inc/fdcan.h:
+../Core/Inc/i2c.h:
+../Core/Inc/tim.h:
+../Core/Inc/usart.h:
+../Core/Inc/gpio.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_CV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IAP.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_GPIO.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_com_helper.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_TIMER.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_GV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_TL720D.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IO.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_CMCU.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_common.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTuc.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTucConfig.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_JTBATTERY.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UART.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_pb_decode_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TL720D.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_MK32_1.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_WH_LTE_7S0.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_DLT_Log.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UDP.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_cpu_flash.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_qspi_w25q128.h:
+../Core/Inc/quadspi.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UpperComputer_Handler.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TTMotor_ZQ.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h:
+../Core/Inc/fsm.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_Error_Detect.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_MF_Gyroscope.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h:
diff --git a/Debug/Core/BASE/Src/MSP/msp_MF_Gyroscope.o b/Debug/Core/BASE/Src/MSP/msp_MF_Gyroscope.o
new file mode 100644
index 0000000..6ca48c2
Binary files /dev/null and b/Debug/Core/BASE/Src/MSP/msp_MF_Gyroscope.o differ
diff --git a/Debug/Core/BASE/Src/MSP/msp_MF_Gyroscope.su b/Debug/Core/BASE/Src/MSP/msp_MF_Gyroscope.su
new file mode 100644
index 0000000..d19004d
--- /dev/null
+++ b/Debug/Core/BASE/Src/MSP/msp_MF_Gyroscope.su
@@ -0,0 +1,3 @@
+../Core/BASE/Src/MSP/msp_MF_Gyroscope.c:29:9:GF_MSP_Gyro_MFOG40_Init	24	static
+../Core/BASE/Src/MSP/msp_MF_Gyroscope.c:39:7:GF_Gyro_Unscramble_Callback	8	static
+../Core/BASE/Src/MSP/msp_MF_Gyroscope.c:132:6:Gyro_Command_Comp	24	static
diff --git a/Debug/Core/BASE/Src/MSP/msp_MK32_1.cyclo b/Debug/Core/BASE/Src/MSP/msp_MK32_1.cyclo
new file mode 100644
index 0000000..31b4419
--- /dev/null
+++ b/Debug/Core/BASE/Src/MSP/msp_MK32_1.cyclo
@@ -0,0 +1,3 @@
+../Core/BASE/Src/MSP/msp_MK32_1.c:18:6:decode_MK32Data	4
+../Core/BASE/Src/MSP/msp_MK32_1.c:33:6:Sbus_Data_Count	3
+../Core/BASE/Src/MSP/msp_MK32_1.c:78:6:MK32_Sbus_UART_Handler_intialize	2
diff --git a/Debug/Core/BASE/Src/MSP/msp_MK32_1.d b/Debug/Core/BASE/Src/MSP/msp_MK32_1.d
new file mode 100644
index 0000000..3345136
--- /dev/null
+++ b/Debug/Core/BASE/Src/MSP/msp_MK32_1.d
@@ -0,0 +1,204 @@
+Core/BASE/Src/MSP/msp_MK32_1.o: ../Core/BASE/Src/MSP/msp_MK32_1.c \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_MK32_1.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UART.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ ../Core/Inc/main.h ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
+ ../Core/Inc/dma.h ../Core/Inc/main.h ../Core/Inc/fdcan.h \
+ ../Core/Inc/i2c.h ../Core/Inc/tim.h ../Core/Inc/usart.h \
+ ../Core/Inc/gpio.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_CV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IAP.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_GPIO.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_com_helper.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_TIMER.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_GV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_TL720D.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IO.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_CMCU.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_common.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTuc.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTucConfig.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_JTBATTERY.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_pb_decode_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TL720D.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_WH_LTE_7S0.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_DLT_Log.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UDP.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_cpu_flash.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_qspi_w25q128.h \
+ ../Core/Inc/quadspi.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UpperComputer_Handler.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TTMotor_ZQ.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h \
+ ../Core/Inc/fsm.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_Error_Detect.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IV.pb.h
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_MK32_1.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UART.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+../Core/Inc/main.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
+../Core/Inc/dma.h:
+../Core/Inc/main.h:
+../Core/Inc/fdcan.h:
+../Core/Inc/i2c.h:
+../Core/Inc/tim.h:
+../Core/Inc/usart.h:
+../Core/Inc/gpio.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_CV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IAP.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_GPIO.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_com_helper.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_TIMER.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_GV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_TL720D.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IO.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_CMCU.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_common.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTuc.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTucConfig.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_JTBATTERY.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_pb_decode_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TL720D.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_WH_LTE_7S0.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_DLT_Log.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UDP.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_cpu_flash.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_qspi_w25q128.h:
+../Core/Inc/quadspi.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UpperComputer_Handler.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TTMotor_ZQ.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h:
+../Core/Inc/fsm.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_Error_Detect.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IV.pb.h:
diff --git a/Debug/Core/BASE/Src/MSP/msp_MK32_1.o b/Debug/Core/BASE/Src/MSP/msp_MK32_1.o
new file mode 100644
index 0000000..f102192
Binary files /dev/null and b/Debug/Core/BASE/Src/MSP/msp_MK32_1.o differ
diff --git a/Debug/Core/BASE/Src/MSP/msp_MK32_1.su b/Debug/Core/BASE/Src/MSP/msp_MK32_1.su
new file mode 100644
index 0000000..05bb84d
--- /dev/null
+++ b/Debug/Core/BASE/Src/MSP/msp_MK32_1.su
@@ -0,0 +1,3 @@
+../Core/BASE/Src/MSP/msp_MK32_1.c:18:6:decode_MK32Data	16	static
+../Core/BASE/Src/MSP/msp_MK32_1.c:33:6:Sbus_Data_Count	56	static
+../Core/BASE/Src/MSP/msp_MK32_1.c:78:6:MK32_Sbus_UART_Handler_intialize	24	static
diff --git a/Debug/Core/BASE/Src/MSP/msp_PID.cyclo b/Debug/Core/BASE/Src/MSP/msp_PID.cyclo
new file mode 100644
index 0000000..c05a422
--- /dev/null
+++ b/Debug/Core/BASE/Src/MSP/msp_PID.cyclo
@@ -0,0 +1,9 @@
+../Core/BASE/Src/MSP/msp_PID.c:18:6:Speedl_PID	3
+../Core/BASE/Src/MSP/msp_PID.c:46:6:GF_MSP_Auto_Motion_adj	14
+../Core/BASE/Src/MSP/msp_PID.c:162:6:GF_MSP_Auto_adj_Unicycle	9
+../Core/BASE/Src/MSP/msp_PID.c:216:6:GF_MSP_Auto_Motion_adj_Com	15
+../Core/BASE/Src/MSP/msp_PID.c:336:6:GF_MSP_PID_Now_Der_adj_Com	11
+../Core/BASE/Src/MSP/msp_PID.c:435:9:PositionalPID	3
+../Core/BASE/Src/MSP/msp_PID.c:468:5:Angle_Tune_PID	3
+../Core/BASE/Src/MSP/msp_PID.c:509:6:GF_MSP_PID_Now_Der_adj_Com_1	7
+../Core/BASE/Src/MSP/msp_PID.c:590:6:GF_MSP_PID_Now_Der_adj_Com_Horizon	11
diff --git a/Debug/Core/BASE/Src/MSP/msp_PID.d b/Debug/Core/BASE/Src/MSP/msp_PID.d
new file mode 100644
index 0000000..8bff9ab
--- /dev/null
+++ b/Debug/Core/BASE/Src/MSP/msp_PID.d
@@ -0,0 +1,148 @@
+Core/BASE/Src/MSP/msp_PID.o: ../Core/BASE/Src/MSP/msp_PID.c \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_PID.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ ../Core/Inc/main.h ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
+ ../Core/Inc/dma.h ../Core/Inc/main.h ../Core/Inc/fdcan.h \
+ ../Core/Inc/i2c.h ../Core/Inc/tim.h ../Core/Inc/usart.h \
+ ../Core/Inc/gpio.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_CV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IAP.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_GPIO.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_com_helper.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_TIMER.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_GV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_TL720D.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IO.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_CMCU.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_common.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTuc.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTucConfig.h
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_PID.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+../Core/Inc/main.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
+../Core/Inc/dma.h:
+../Core/Inc/main.h:
+../Core/Inc/fdcan.h:
+../Core/Inc/i2c.h:
+../Core/Inc/tim.h:
+../Core/Inc/usart.h:
+../Core/Inc/gpio.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_CV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IAP.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_GPIO.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_com_helper.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_TIMER.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_GV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_TL720D.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IO.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_CMCU.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_common.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTuc.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTucConfig.h:
diff --git a/Debug/Core/BASE/Src/MSP/msp_PID.o b/Debug/Core/BASE/Src/MSP/msp_PID.o
new file mode 100644
index 0000000..0e6e41d
Binary files /dev/null and b/Debug/Core/BASE/Src/MSP/msp_PID.o differ
diff --git a/Debug/Core/BASE/Src/MSP/msp_PID.su b/Debug/Core/BASE/Src/MSP/msp_PID.su
new file mode 100644
index 0000000..02fa004
--- /dev/null
+++ b/Debug/Core/BASE/Src/MSP/msp_PID.su
@@ -0,0 +1,9 @@
+../Core/BASE/Src/MSP/msp_PID.c:18:6:Speedl_PID	64	static
+../Core/BASE/Src/MSP/msp_PID.c:46:6:GF_MSP_Auto_Motion_adj	144	static
+../Core/BASE/Src/MSP/msp_PID.c:162:6:GF_MSP_Auto_adj_Unicycle	112	static
+../Core/BASE/Src/MSP/msp_PID.c:216:6:GF_MSP_Auto_Motion_adj_Com	144	static
+../Core/BASE/Src/MSP/msp_PID.c:336:6:GF_MSP_PID_Now_Der_adj_Com	144	static
+../Core/BASE/Src/MSP/msp_PID.c:435:9:PositionalPID	80	static
+../Core/BASE/Src/MSP/msp_PID.c:468:5:Angle_Tune_PID	32	static
+../Core/BASE/Src/MSP/msp_PID.c:509:6:GF_MSP_PID_Now_Der_adj_Com_1	128	static
+../Core/BASE/Src/MSP/msp_PID.c:590:6:GF_MSP_PID_Now_Der_adj_Com_Horizon	144	static
diff --git a/Debug/Core/BASE/Src/MSP/msp_TL720D.cyclo b/Debug/Core/BASE/Src/MSP/msp_TL720D.cyclo
new file mode 100644
index 0000000..7710dd3
--- /dev/null
+++ b/Debug/Core/BASE/Src/MSP/msp_TL720D.cyclo
@@ -0,0 +1,3 @@
+../Core/BASE/Src/MSP/msp_TL720D.c:24:6:TL720D_intialize	2
+../Core/BASE/Src/MSP/msp_TL720D.c:36:6:decode_TL720D	7
+../Core/BASE/Src/MSP/msp_TL720D.c:65:9:getDeci	3
diff --git a/Debug/Core/BASE/Src/MSP/msp_TL720D.d b/Debug/Core/BASE/Src/MSP/msp_TL720D.d
new file mode 100644
index 0000000..f26c594
--- /dev/null
+++ b/Debug/Core/BASE/Src/MSP/msp_TL720D.d
@@ -0,0 +1,206 @@
+Core/BASE/Src/MSP/msp_TL720D.o: ../Core/BASE/Src/MSP/msp_TL720D.c \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TL720D.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ ../Core/Inc/main.h ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
+ ../Core/Inc/dma.h ../Core/Inc/main.h ../Core/Inc/fdcan.h \
+ ../Core/Inc/i2c.h ../Core/Inc/tim.h ../Core/Inc/usart.h \
+ ../Core/Inc/gpio.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_CV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IAP.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_GPIO.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_com_helper.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_TIMER.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_GV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_TL720D.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IO.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_CMCU.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_common.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTuc.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTucConfig.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UART.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_JTBATTERY.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_pb_decode_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_MK32_1.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_WH_LTE_7S0.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_DLT_Log.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UDP.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_cpu_flash.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_qspi_w25q128.h \
+ ../Core/Inc/quadspi.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UpperComputer_Handler.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TTMotor_ZQ.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h \
+ ../Core/Inc/fsm.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_Error_Detect.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_TL720D.pb.h
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TL720D.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+../Core/Inc/main.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
+../Core/Inc/dma.h:
+../Core/Inc/main.h:
+../Core/Inc/fdcan.h:
+../Core/Inc/i2c.h:
+../Core/Inc/tim.h:
+../Core/Inc/usart.h:
+../Core/Inc/gpio.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_CV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IAP.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_GPIO.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_com_helper.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_TIMER.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_GV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_TL720D.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IO.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_CMCU.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_common.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTuc.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTucConfig.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UART.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_JTBATTERY.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_pb_decode_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_MK32_1.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_WH_LTE_7S0.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_DLT_Log.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UDP.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_cpu_flash.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_qspi_w25q128.h:
+../Core/Inc/quadspi.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UpperComputer_Handler.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TTMotor_ZQ.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h:
+../Core/Inc/fsm.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_Error_Detect.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_TL720D.pb.h:
diff --git a/Debug/Core/BASE/Src/MSP/msp_TL720D.o b/Debug/Core/BASE/Src/MSP/msp_TL720D.o
new file mode 100644
index 0000000..9df1002
Binary files /dev/null and b/Debug/Core/BASE/Src/MSP/msp_TL720D.o differ
diff --git a/Debug/Core/BASE/Src/MSP/msp_TL720D.su b/Debug/Core/BASE/Src/MSP/msp_TL720D.su
new file mode 100644
index 0000000..8b5c86f
--- /dev/null
+++ b/Debug/Core/BASE/Src/MSP/msp_TL720D.su
@@ -0,0 +1,3 @@
+../Core/BASE/Src/MSP/msp_TL720D.c:24:6:TL720D_intialize	40	static
+../Core/BASE/Src/MSP/msp_TL720D.c:36:6:decode_TL720D	32	static
+../Core/BASE/Src/MSP/msp_TL720D.c:65:9:getDeci	24	static
diff --git a/Debug/Core/BASE/Src/MSP/msp_TTMotor_ZQ.cyclo b/Debug/Core/BASE/Src/MSP/msp_TTMotor_ZQ.cyclo
new file mode 100644
index 0000000..40f6778
--- /dev/null
+++ b/Debug/Core/BASE/Src/MSP/msp_TTMotor_ZQ.cyclo
@@ -0,0 +1,23 @@
+../Core/BASE/Src/MSP/msp_TTMotor_ZQ.c:11:6:ActivateMotor	1
+../Core/BASE/Src/MSP/msp_TTMotor_ZQ.c:21:6:Enable_NMT	1
+../Core/BASE/Src/MSP/msp_TTMotor_ZQ.c:28:6:Configure_Asynchronous_Mode	1
+../Core/BASE/Src/MSP/msp_TTMotor_ZQ.c:41:6:Consumer_Or_microcontroller_Heartbeat	1
+../Core/BASE/Src/MSP/msp_TTMotor_ZQ.c:48:6:CANSendMessageSDO_ADD_To_SendList	1
+../Core/BASE/Src/MSP/msp_TTMotor_ZQ.c:64:6:Postion_Velcocity_Run_SetParameter	3
+../Core/BASE/Src/MSP/msp_TTMotor_ZQ.c:110:6:Postion_Velcocity_Set_Position	1
+../Core/BASE/Src/MSP/msp_TTMotor_ZQ.c:126:6:Driver_ReadError	1
+../Core/BASE/Src/MSP/msp_TTMotor_ZQ.c:134:6:SetMotorTargetPosition	1
+../Core/BASE/Src/MSP/msp_TTMotor_ZQ.c:141:6:Postion_Velcocity_Stop	1
+../Core/BASE/Src/MSP/msp_TTMotor_ZQ.c:164:6:SpeedModeSetup	1
+../Core/BASE/Src/MSP/msp_TTMotor_ZQ.c:199:6:TT_SpeedMode_Set_TargetSpeed	1
+../Core/BASE/Src/MSP/msp_TTMotor_ZQ.c:207:6:Swing_Motor_Set_Target_Position	1
+../Core/BASE/Src/MSP/msp_TTMotor_ZQ.c:212:6:Swing_Motor_Read_ReachedEnd	1
+../Core/BASE/Src/MSP/msp_TTMotor_ZQ.c:218:6:Set_Current_Positon_Zero	1
+../Core/BASE/Src/MSP/msp_TTMotor_ZQ.c:246:6:TT_Request_Position	1
+../Core/BASE/Src/MSP/msp_TTMotor_ZQ.c:254:6:Position_Immediately_Setting	1
+../Core/BASE/Src/MSP/msp_TTMotor_ZQ.c:262:6:Position_Lag_Setting	1
+../Core/BASE/Src/MSP/msp_TTMotor_ZQ.c:273:6:Position_Lay_Setting	1
+../Core/BASE/Src/MSP/msp_TTMotor_ZQ.c:297:6:TT_Request_Velocity	1
+../Core/BASE/Src/MSP/msp_TTMotor_ZQ.c:306:6:TT_Request_Fault	1
+../Core/BASE/Src/MSP/msp_TTMotor_ZQ.c:314:6:TT_Request_Current	1
+../Core/BASE/Src/MSP/msp_TTMotor_ZQ.c:321:6:TT_Analytic_Fun	22
diff --git a/Debug/Core/BASE/Src/MSP/msp_TTMotor_ZQ.d b/Debug/Core/BASE/Src/MSP/msp_TTMotor_ZQ.d
new file mode 100644
index 0000000..833ca21
--- /dev/null
+++ b/Debug/Core/BASE/Src/MSP/msp_TTMotor_ZQ.d
@@ -0,0 +1,204 @@
+Core/BASE/Src/MSP/msp_TTMotor_ZQ.o: ../Core/BASE/Src/MSP/msp_TTMotor_ZQ.c \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TTMotor_ZQ.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ ../Core/Inc/main.h ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
+ ../Core/Inc/dma.h ../Core/Inc/main.h ../Core/Inc/fdcan.h \
+ ../Core/Inc/i2c.h ../Core/Inc/tim.h ../Core/Inc/usart.h \
+ ../Core/Inc/gpio.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_CV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IAP.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_GPIO.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_com_helper.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_TIMER.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_GV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_TL720D.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IO.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_CMCU.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_common.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTuc.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTucConfig.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h \
+ ../Core/Inc/fsm.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_JTBATTERY.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UART.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_pb_decode_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TL720D.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_MK32_1.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_WH_LTE_7S0.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_DLT_Log.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UDP.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_cpu_flash.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_qspi_w25q128.h \
+ ../Core/Inc/quadspi.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UpperComputer_Handler.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_Error_Detect.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IV.pb.h
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TTMotor_ZQ.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+../Core/Inc/main.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
+../Core/Inc/dma.h:
+../Core/Inc/main.h:
+../Core/Inc/fdcan.h:
+../Core/Inc/i2c.h:
+../Core/Inc/tim.h:
+../Core/Inc/usart.h:
+../Core/Inc/gpio.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_CV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IAP.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_GPIO.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_com_helper.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_TIMER.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_GV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_TL720D.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IO.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_CMCU.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_common.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTuc.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTucConfig.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h:
+../Core/Inc/fsm.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_JTBATTERY.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UART.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_pb_decode_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TL720D.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_MK32_1.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_WH_LTE_7S0.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_DLT_Log.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UDP.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_cpu_flash.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_qspi_w25q128.h:
+../Core/Inc/quadspi.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UpperComputer_Handler.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_Error_Detect.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IV.pb.h:
diff --git a/Debug/Core/BASE/Src/MSP/msp_TTMotor_ZQ.o b/Debug/Core/BASE/Src/MSP/msp_TTMotor_ZQ.o
new file mode 100644
index 0000000..423041d
Binary files /dev/null and b/Debug/Core/BASE/Src/MSP/msp_TTMotor_ZQ.o differ
diff --git a/Debug/Core/BASE/Src/MSP/msp_TTMotor_ZQ.su b/Debug/Core/BASE/Src/MSP/msp_TTMotor_ZQ.su
new file mode 100644
index 0000000..f0bd63c
--- /dev/null
+++ b/Debug/Core/BASE/Src/MSP/msp_TTMotor_ZQ.su
@@ -0,0 +1,23 @@
+../Core/BASE/Src/MSP/msp_TTMotor_ZQ.c:11:6:ActivateMotor	40	static
+../Core/BASE/Src/MSP/msp_TTMotor_ZQ.c:21:6:Enable_NMT	40	static
+../Core/BASE/Src/MSP/msp_TTMotor_ZQ.c:28:6:Configure_Asynchronous_Mode	40	static
+../Core/BASE/Src/MSP/msp_TTMotor_ZQ.c:41:6:Consumer_Or_microcontroller_Heartbeat	40	static
+../Core/BASE/Src/MSP/msp_TTMotor_ZQ.c:48:6:CANSendMessageSDO_ADD_To_SendList	32	static
+../Core/BASE/Src/MSP/msp_TTMotor_ZQ.c:64:6:Postion_Velcocity_Run_SetParameter	40	static
+../Core/BASE/Src/MSP/msp_TTMotor_ZQ.c:110:6:Postion_Velcocity_Set_Position	40	static
+../Core/BASE/Src/MSP/msp_TTMotor_ZQ.c:126:6:Driver_ReadError	40	static
+../Core/BASE/Src/MSP/msp_TTMotor_ZQ.c:134:6:SetMotorTargetPosition	24	static
+../Core/BASE/Src/MSP/msp_TTMotor_ZQ.c:141:6:Postion_Velcocity_Stop	40	static
+../Core/BASE/Src/MSP/msp_TTMotor_ZQ.c:164:6:SpeedModeSetup	40	static
+../Core/BASE/Src/MSP/msp_TTMotor_ZQ.c:199:6:TT_SpeedMode_Set_TargetSpeed	40	static
+../Core/BASE/Src/MSP/msp_TTMotor_ZQ.c:207:6:Swing_Motor_Set_Target_Position	16	static
+../Core/BASE/Src/MSP/msp_TTMotor_ZQ.c:212:6:Swing_Motor_Read_ReachedEnd	16	static
+../Core/BASE/Src/MSP/msp_TTMotor_ZQ.c:218:6:Set_Current_Positon_Zero	40	static
+../Core/BASE/Src/MSP/msp_TTMotor_ZQ.c:246:6:TT_Request_Position	40	static
+../Core/BASE/Src/MSP/msp_TTMotor_ZQ.c:254:6:Position_Immediately_Setting	40	static
+../Core/BASE/Src/MSP/msp_TTMotor_ZQ.c:262:6:Position_Lag_Setting	40	static
+../Core/BASE/Src/MSP/msp_TTMotor_ZQ.c:273:6:Position_Lay_Setting	40	static
+../Core/BASE/Src/MSP/msp_TTMotor_ZQ.c:297:6:TT_Request_Velocity	40	static
+../Core/BASE/Src/MSP/msp_TTMotor_ZQ.c:306:6:TT_Request_Fault	40	static
+../Core/BASE/Src/MSP/msp_TTMotor_ZQ.c:314:6:TT_Request_Current	40	static
+../Core/BASE/Src/MSP/msp_TTMotor_ZQ.c:321:6:TT_Analytic_Fun	40	static
diff --git a/Debug/Core/BASE/Src/MSP/msp_WH_LTE_7S0.cyclo b/Debug/Core/BASE/Src/MSP/msp_WH_LTE_7S0.cyclo
new file mode 100644
index 0000000..4691115
--- /dev/null
+++ b/Debug/Core/BASE/Src/MSP/msp_WH_LTE_7S0.cyclo
@@ -0,0 +1,6 @@
+../Core/BASE/Src/MSP/msp_WH_LTE_7S0.c:17:6:Reset	1
+../Core/BASE/Src/MSP/msp_WH_LTE_7S0.c:21:6:NormalState	1
+../Core/BASE/Src/MSP/msp_WH_LTE_7S0.c:25:6:WH_LTE_7S0_intialize	2
+../Core/BASE/Src/MSP/msp_WH_LTE_7S0.c:44:6:Send_WH_LTE_7S0_Data	1
+../Core/BASE/Src/MSP/msp_WH_LTE_7S0.c:55:6:UpdateGV	1
+../Core/BASE/Src/MSP/msp_WH_LTE_7S0.c:73:6:decode_received_data_from_computer	4
diff --git a/Debug/Core/BASE/Src/MSP/msp_WH_LTE_7S0.d b/Debug/Core/BASE/Src/MSP/msp_WH_LTE_7S0.d
new file mode 100644
index 0000000..f11c6e6
--- /dev/null
+++ b/Debug/Core/BASE/Src/MSP/msp_WH_LTE_7S0.d
@@ -0,0 +1,212 @@
+Core/BASE/Src/MSP/msp_WH_LTE_7S0.o: ../Core/BASE/Src/MSP/msp_WH_LTE_7S0.c \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ ../Core/Inc/main.h ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
+ ../Core/Inc/dma.h ../Core/Inc/main.h ../Core/Inc/fdcan.h \
+ ../Core/Inc/i2c.h ../Core/Inc/tim.h ../Core/Inc/usart.h \
+ ../Core/Inc/gpio.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_CV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IAP.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_GPIO.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_com_helper.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_TIMER.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_GV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_TL720D.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IO.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_CMCU.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_common.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTuc.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTucConfig.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_JTBATTERY.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UART.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_pb_decode_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TL720D.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_MK32_1.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_WH_LTE_7S0.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_DLT_Log.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UDP.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_cpu_flash.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_qspi_w25q128.h \
+ ../Core/Inc/quadspi.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UpperComputer_Handler.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TTMotor_ZQ.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h \
+ ../Core/Inc/fsm.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_Error_Detect.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_decode_command.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Cmd.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_cpu_flash.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_ReCmd.pb.h
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+../Core/Inc/main.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
+../Core/Inc/dma.h:
+../Core/Inc/main.h:
+../Core/Inc/fdcan.h:
+../Core/Inc/i2c.h:
+../Core/Inc/tim.h:
+../Core/Inc/usart.h:
+../Core/Inc/gpio.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_CV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IAP.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_GPIO.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_com_helper.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_TIMER.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_GV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_TL720D.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IO.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_CMCU.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_common.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTuc.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTucConfig.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_JTBATTERY.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UART.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_pb_decode_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TL720D.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_MK32_1.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_WH_LTE_7S0.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_DLT_Log.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UDP.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_cpu_flash.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_qspi_w25q128.h:
+../Core/Inc/quadspi.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UpperComputer_Handler.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TTMotor_ZQ.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h:
+../Core/Inc/fsm.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_Error_Detect.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_decode_command.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Cmd.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_cpu_flash.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_ReCmd.pb.h:
diff --git a/Debug/Core/BASE/Src/MSP/msp_WH_LTE_7S0.o b/Debug/Core/BASE/Src/MSP/msp_WH_LTE_7S0.o
new file mode 100644
index 0000000..70c65c4
Binary files /dev/null and b/Debug/Core/BASE/Src/MSP/msp_WH_LTE_7S0.o differ
diff --git a/Debug/Core/BASE/Src/MSP/msp_WH_LTE_7S0.su b/Debug/Core/BASE/Src/MSP/msp_WH_LTE_7S0.su
new file mode 100644
index 0000000..9fc312c
--- /dev/null
+++ b/Debug/Core/BASE/Src/MSP/msp_WH_LTE_7S0.su
@@ -0,0 +1,6 @@
+../Core/BASE/Src/MSP/msp_WH_LTE_7S0.c:17:6:Reset	8	static
+../Core/BASE/Src/MSP/msp_WH_LTE_7S0.c:21:6:NormalState	8	static
+../Core/BASE/Src/MSP/msp_WH_LTE_7S0.c:25:6:WH_LTE_7S0_intialize	16	static
+../Core/BASE/Src/MSP/msp_WH_LTE_7S0.c:44:6:Send_WH_LTE_7S0_Data	120	static
+../Core/BASE/Src/MSP/msp_WH_LTE_7S0.c:55:6:UpdateGV	1088	static
+../Core/BASE/Src/MSP/msp_WH_LTE_7S0.c:73:6:decode_received_data_from_computer	1040	static
diff --git a/Debug/Core/BASE/Src/MSP/subdir.mk b/Debug/Core/BASE/Src/MSP/subdir.mk
new file mode 100644
index 0000000..58d4d2a
--- /dev/null
+++ b/Debug/Core/BASE/Src/MSP/subdir.mk
@@ -0,0 +1,51 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+# Toolchain: GNU Tools for STM32 (12.3.rel1)
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables 
+C_SRCS += \
+../Core/BASE/Src/MSP/msp_Blast_Machine.c \
+../Core/BASE/Src/MSP/msp_CMCUU.c \
+../Core/BASE/Src/MSP/msp_KS206.c \
+../Core/BASE/Src/MSP/msp_MF_Gyroscope.c \
+../Core/BASE/Src/MSP/msp_MK32_1.c \
+../Core/BASE/Src/MSP/msp_PID.c \
+../Core/BASE/Src/MSP/msp_TL720D.c \
+../Core/BASE/Src/MSP/msp_TTMotor_ZQ.c \
+../Core/BASE/Src/MSP/msp_WH_LTE_7S0.c 
+
+OBJS += \
+./Core/BASE/Src/MSP/msp_Blast_Machine.o \
+./Core/BASE/Src/MSP/msp_CMCUU.o \
+./Core/BASE/Src/MSP/msp_KS206.o \
+./Core/BASE/Src/MSP/msp_MF_Gyroscope.o \
+./Core/BASE/Src/MSP/msp_MK32_1.o \
+./Core/BASE/Src/MSP/msp_PID.o \
+./Core/BASE/Src/MSP/msp_TL720D.o \
+./Core/BASE/Src/MSP/msp_TTMotor_ZQ.o \
+./Core/BASE/Src/MSP/msp_WH_LTE_7S0.o 
+
+C_DEPS += \
+./Core/BASE/Src/MSP/msp_Blast_Machine.d \
+./Core/BASE/Src/MSP/msp_CMCUU.d \
+./Core/BASE/Src/MSP/msp_KS206.d \
+./Core/BASE/Src/MSP/msp_MF_Gyroscope.d \
+./Core/BASE/Src/MSP/msp_MK32_1.d \
+./Core/BASE/Src/MSP/msp_PID.d \
+./Core/BASE/Src/MSP/msp_TL720D.d \
+./Core/BASE/Src/MSP/msp_TTMotor_ZQ.d \
+./Core/BASE/Src/MSP/msp_WH_LTE_7S0.d 
+
+
+# Each subdirectory must supply rules for building sources it contributes
+Core/BASE/Src/MSP/%.o Core/BASE/Src/MSP/%.su Core/BASE/Src/MSP/%.cyclo: ../Core/BASE/Src/MSP/%.c Core/BASE/Src/MSP/subdir.mk
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32H743xx -c -I../Core/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I../Drivers/CMSIS/Include -I"F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc" -I"F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource" -I"F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP" -I"F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
+
+clean: clean-Core-2f-BASE-2f-Src-2f-MSP
+
+clean-Core-2f-BASE-2f-Src-2f-MSP:
+	-$(RM) ./Core/BASE/Src/MSP/msp_Blast_Machine.cyclo ./Core/BASE/Src/MSP/msp_Blast_Machine.d ./Core/BASE/Src/MSP/msp_Blast_Machine.o ./Core/BASE/Src/MSP/msp_Blast_Machine.su ./Core/BASE/Src/MSP/msp_CMCUU.cyclo ./Core/BASE/Src/MSP/msp_CMCUU.d ./Core/BASE/Src/MSP/msp_CMCUU.o ./Core/BASE/Src/MSP/msp_CMCUU.su ./Core/BASE/Src/MSP/msp_KS206.cyclo ./Core/BASE/Src/MSP/msp_KS206.d ./Core/BASE/Src/MSP/msp_KS206.o ./Core/BASE/Src/MSP/msp_KS206.su ./Core/BASE/Src/MSP/msp_MF_Gyroscope.cyclo ./Core/BASE/Src/MSP/msp_MF_Gyroscope.d ./Core/BASE/Src/MSP/msp_MF_Gyroscope.o ./Core/BASE/Src/MSP/msp_MF_Gyroscope.su ./Core/BASE/Src/MSP/msp_MK32_1.cyclo ./Core/BASE/Src/MSP/msp_MK32_1.d ./Core/BASE/Src/MSP/msp_MK32_1.o ./Core/BASE/Src/MSP/msp_MK32_1.su ./Core/BASE/Src/MSP/msp_PID.cyclo ./Core/BASE/Src/MSP/msp_PID.d ./Core/BASE/Src/MSP/msp_PID.o ./Core/BASE/Src/MSP/msp_PID.su ./Core/BASE/Src/MSP/msp_TL720D.cyclo ./Core/BASE/Src/MSP/msp_TL720D.d ./Core/BASE/Src/MSP/msp_TL720D.o ./Core/BASE/Src/MSP/msp_TL720D.su ./Core/BASE/Src/MSP/msp_TTMotor_ZQ.cyclo ./Core/BASE/Src/MSP/msp_TTMotor_ZQ.d ./Core/BASE/Src/MSP/msp_TTMotor_ZQ.o ./Core/BASE/Src/MSP/msp_TTMotor_ZQ.su ./Core/BASE/Src/MSP/msp_WH_LTE_7S0.cyclo ./Core/BASE/Src/MSP/msp_WH_LTE_7S0.d ./Core/BASE/Src/MSP/msp_WH_LTE_7S0.o ./Core/BASE/Src/MSP/msp_WH_LTE_7S0.su
+
+.PHONY: clean-Core-2f-BASE-2f-Src-2f-MSP
+
diff --git a/Debug/Core/Src/adc.cyclo b/Debug/Core/Src/adc.cyclo
new file mode 100644
index 0000000..9cf35c2
--- /dev/null
+++ b/Debug/Core/Src/adc.cyclo
@@ -0,0 +1,3 @@
+../Core/Src/adc.c:30:6:MX_ADC2_Init	3
+../Core/Src/adc.c:84:6:HAL_ADC_MspInit	3
+../Core/Src/adc.c:130:6:HAL_ADC_MspDeInit	2
diff --git a/Debug/Core/Src/adc.d b/Debug/Core/Src/adc.d
new file mode 100644
index 0000000..650b723
--- /dev/null
+++ b/Debug/Core/Src/adc.d
@@ -0,0 +1,81 @@
+Core/Src/adc.o: ../Core/Src/adc.c ../Core/Inc/adc.h ../Core/Inc/main.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
+../Core/Inc/adc.h:
+../Core/Inc/main.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Core/Src/adc.o b/Debug/Core/Src/adc.o
new file mode 100644
index 0000000..e75487a
Binary files /dev/null and b/Debug/Core/Src/adc.o differ
diff --git a/Debug/Core/Src/adc.su b/Debug/Core/Src/adc.su
new file mode 100644
index 0000000..cf8fb4f
--- /dev/null
+++ b/Debug/Core/Src/adc.su
@@ -0,0 +1,3 @@
+../Core/Src/adc.c:30:6:MX_ADC2_Init	40	static
+../Core/Src/adc.c:84:6:HAL_ADC_MspInit	240	static
+../Core/Src/adc.c:130:6:HAL_ADC_MspDeInit	16	static
diff --git a/Debug/Core/Src/dma.cyclo b/Debug/Core/Src/dma.cyclo
new file mode 100644
index 0000000..a9d9f42
--- /dev/null
+++ b/Debug/Core/Src/dma.cyclo
@@ -0,0 +1 @@
+../Core/Src/dma.c:39:6:MX_DMA_Init	1
diff --git a/Debug/Core/Src/dma.d b/Debug/Core/Src/dma.d
new file mode 100644
index 0000000..afa17a2
--- /dev/null
+++ b/Debug/Core/Src/dma.d
@@ -0,0 +1,81 @@
+Core/Src/dma.o: ../Core/Src/dma.c ../Core/Inc/dma.h ../Core/Inc/main.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
+../Core/Inc/dma.h:
+../Core/Inc/main.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Core/Src/dma.o b/Debug/Core/Src/dma.o
new file mode 100644
index 0000000..21ce8e3
Binary files /dev/null and b/Debug/Core/Src/dma.o differ
diff --git a/Debug/Core/Src/dma.su b/Debug/Core/Src/dma.su
new file mode 100644
index 0000000..802020b
--- /dev/null
+++ b/Debug/Core/Src/dma.su
@@ -0,0 +1 @@
+../Core/Src/dma.c:39:6:MX_DMA_Init	16	static
diff --git a/Debug/Core/Src/eth.cyclo b/Debug/Core/Src/eth.cyclo
new file mode 100644
index 0000000..9b23e9f
--- /dev/null
+++ b/Debug/Core/Src/eth.cyclo
@@ -0,0 +1,3 @@
+../Core/Src/eth.c:51:6:MX_ETH_Init	2
+../Core/Src/eth.c:95:6:HAL_ETH_MspInit	2
+../Core/Src/eth.c:155:6:HAL_ETH_MspDeInit	2
diff --git a/Debug/Core/Src/eth.d b/Debug/Core/Src/eth.d
new file mode 100644
index 0000000..5a3a9d5
--- /dev/null
+++ b/Debug/Core/Src/eth.d
@@ -0,0 +1,81 @@
+Core/Src/eth.o: ../Core/Src/eth.c ../Core/Inc/eth.h ../Core/Inc/main.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
+../Core/Inc/eth.h:
+../Core/Inc/main.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Core/Src/eth.o b/Debug/Core/Src/eth.o
new file mode 100644
index 0000000..91d8846
Binary files /dev/null and b/Debug/Core/Src/eth.o differ
diff --git a/Debug/Core/Src/eth.su b/Debug/Core/Src/eth.su
new file mode 100644
index 0000000..7ee0752
--- /dev/null
+++ b/Debug/Core/Src/eth.su
@@ -0,0 +1,3 @@
+../Core/Src/eth.c:51:6:MX_ETH_Init	8	static
+../Core/Src/eth.c:95:6:HAL_ETH_MspInit	64	static
+../Core/Src/eth.c:155:6:HAL_ETH_MspDeInit	16	static
diff --git a/Debug/Core/Src/fdcan.cyclo b/Debug/Core/Src/fdcan.cyclo
new file mode 100644
index 0000000..f141037
--- /dev/null
+++ b/Debug/Core/Src/fdcan.cyclo
@@ -0,0 +1,4 @@
+../Core/Src/fdcan.c:31:6:MX_FDCAN1_Init	2
+../Core/Src/fdcan.c:79:6:MX_FDCAN2_Init	2
+../Core/Src/fdcan.c:129:6:HAL_FDCAN_MspInit	7
+../Core/Src/fdcan.c:216:6:HAL_FDCAN_MspDeInit	5
diff --git a/Debug/Core/Src/fdcan.d b/Debug/Core/Src/fdcan.d
new file mode 100644
index 0000000..77ae0bf
--- /dev/null
+++ b/Debug/Core/Src/fdcan.d
@@ -0,0 +1,81 @@
+Core/Src/fdcan.o: ../Core/Src/fdcan.c ../Core/Inc/fdcan.h \
+ ../Core/Inc/main.h ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
+../Core/Inc/fdcan.h:
+../Core/Inc/main.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Core/Src/fdcan.o b/Debug/Core/Src/fdcan.o
new file mode 100644
index 0000000..2d222a3
Binary files /dev/null and b/Debug/Core/Src/fdcan.o differ
diff --git a/Debug/Core/Src/fdcan.su b/Debug/Core/Src/fdcan.su
new file mode 100644
index 0000000..ba40ff6
--- /dev/null
+++ b/Debug/Core/Src/fdcan.su
@@ -0,0 +1,4 @@
+../Core/Src/fdcan.c:31:6:MX_FDCAN1_Init	8	static
+../Core/Src/fdcan.c:79:6:MX_FDCAN2_Init	8	static
+../Core/Src/fdcan.c:129:6:HAL_FDCAN_MspInit	248	static
+../Core/Src/fdcan.c:216:6:HAL_FDCAN_MspDeInit	16	static
diff --git a/Debug/Core/Src/fsm.cyclo b/Debug/Core/Src/fsm.cyclo
new file mode 100644
index 0000000..af9dccb
--- /dev/null
+++ b/Debug/Core/Src/fsm.cyclo
@@ -0,0 +1,114 @@
+../Core/Src/fsm.c:213:6:Fsm_Init	1
+../Core/Src/fsm.c:229:6:GF_Dispatch	25
+../Core/Src/fsm.c:346:6:action_perfrom	4
+../Core/Src/fsm.c:367:6:Robot_Halt_Mode	1
+../Core/Src/fsm.c:375:6:Robot_Manual_Operation_Mode	1
+../Core/Src/fsm.c:388:6:UltraStopReverse	10
+../Core/Src/fsm.c:433:6:UltraStopReverse_Manually_Backward	1
+../Core/Src/fsm.c:458:6:PushRod_Contronl	3
+../Core/Src/fsm.c:637:6:Robot_Manual_Operation_Function	16
+../Core/Src/fsm.c:697:6:Robot_Swing_Operation_Function	3
+../Core/Src/fsm.c:716:6:Robot_Swing_Operation_Function_Position	1
+../Core/Src/fsm.c:725:6:Horizontal_Operatin_Main_Func	5
+../Core/Src/fsm.c:768:6:Move_Horizontal_Auto_Sub_Func	10
+../Core/Src/fsm.c:814:6:Change_Road_Down_Left_Right	6
+../Core/Src/fsm.c:840:6:Horizontal_Manual_Operation_Func	16
+../Core/Src/fsm.c:909:6:Vertical_Operatin_Main_Func_Left	7
+../Core/Src/fsm.c:963:6:Vertical_Operatin_Main_Func_Right	7
+../Core/Src/fsm.c:1033:6:Move_Vertical_Manual_Sub_Func_Forward	6
+../Core/Src/fsm.c:1061:6:Move_Vertical_Manual_Sub_Func_Backward	6
+../Core/Src/fsm.c:1090:6:Move_Vertical_Auto_Sub_Func	10
+../Core/Src/fsm.c:1139:6:Move_Vertical_Auto_Sub_Func_Forward	6
+../Core/Src/fsm.c:1165:6:Plane_Operatin_Main_Func	6
+../Core/Src/fsm.c:1213:6:Move_Plane_Auto_Sub_Func	9
+../Core/Src/fsm.c:1255:6:Plane_Angle_Judge	1
+../Core/Src/fsm.c:1271:6:Region_Automated_Task_Func_Alternately_Plane	14
+../Core/Src/fsm.c:1377:6:Region_Automated_Task_Func_Alternately_Horizontal	15
+../Core/Src/fsm.c:1491:6:Vertical_Manual_Operation_Func	16
+../Core/Src/fsm.c:1557:6:Plane_Manual_Operation_Func	16
+../Core/Src/fsm.c:1623:6:Move_Plane_Manual_Sub_Func_Fordwards	5
+../Core/Src/fsm.c:1644:6:Move_Plane_Manual_Sub_Func_Backwards	5
+../Core/Src/fsm.c:1672:6:Plane_X_Backward_Time_Calculation	1
+../Core/Src/fsm.c:1676:6:Plane_X_Backward_Time_Calculation_Continuous	1
+../Core/Src/fsm.c:1681:6:Horizontal_X_Backward_Num_Calculation	1
+../Core/Src/fsm.c:1686:6:Horizontal_X_Backward_Time_Calculation_Continuous	1
+../Core/Src/fsm.c:1693:6:Plane_Y_Lane_Change_Time_Calculation	1
+../Core/Src/fsm.c:1698:6:Horizontal_Y_Lane_Change_Time_Calculation	1
+../Core/Src/fsm.c:1704:6:Plane_Change_Road_Backward_Num_Calculation	1
+../Core/Src/fsm.c:1709:6:Plane_Change_Road_Backward_Time_Calculation_Continuous	1
+../Core/Src/fsm.c:1716:6:Horizontal_Change_Road_Backward_Num_Calculation	1
+../Core/Src/fsm.c:1721:6:Horizontal_Change_Road_Backward_Time_Calculation_Continuous	1
+../Core/Src/fsm.c:1726:6:Plane_Lane_Change_Func	8
+../Core/Src/fsm.c:1768:6:Move_Horizontal_Manual_Sub_Func_Forwards	6
+../Core/Src/fsm.c:1795:6:Move_Horizontal_Manual_Sub_Func_Backwards	6
+../Core/Src/fsm.c:1823:6:Horiz_Angle_Judge	15
+../Core/Src/fsm.c:1905:6:Horiz_Angle_Judge_4_Direction	29
+../Core/Src/fsm.c:1995:6:Horiz_Angle_Judge_Region	3
+../Core/Src/fsm.c:2018:6:Move_Horizontal_Vertical_Task_Forwards_Do_Forwards	1
+../Core/Src/fsm.c:2032:6:Move_Horizontal_Task_Change_Road_Backwards_Do	1
+../Core/Src/fsm.c:2044:6:Move_Plane_Task_Change_Road_Backwards_Do	1
+../Core/Src/fsm.c:2059:6:Move_Speed_Define	1
+../Core/Src/fsm.c:2070:6:Robot_Posture_Adjus_Gravity	5
+../Core/Src/fsm.c:2111:6:Robot_Posture_Adjus_Plane	5
+../Core/Src/fsm.c:2158:6:Vertical_Angle_Judge	1
+../Core/Src/fsm.c:2190:6:Vertical_Angle_Judge_Uptata_1	1
+../Core/Src/fsm.c:2206:6:Change_Road_Down_Up_Right_To_Left	9
+../Core/Src/fsm.c:2254:6:Change_Road_Down_Up_Left_To_Right	9
+../Core/Src/fsm.c:2302:6:Change_Road_Plane	13
+../Core/Src/fsm.c:2372:6:Change_Road_Plane_Continuous_FanDi_Left	13
+../Core/Src/fsm.c:2443:6:Change_Road_Plane_Continuous_FanDi_Right	13
+../Core/Src/fsm.c:2517:6:Move_Plane_Task_Fordwards_Do	1
+../Core/Src/fsm.c:2527:6:Move_Plane_Task_Fordwards_Do_Update	1
+../Core/Src/fsm.c:2540:6:Move_Plane_Task_Backwards_Do	1
+../Core/Src/fsm.c:2550:6:Move_Plane_Task_Backwards_Distance_Do	1
+../Core/Src/fsm.c:2561:6:Move_Horizontal_Vertical_Task_Backwards_Do_Backward	1
+../Core/Src/fsm.c:2577:6:Move_Plane_Task_Backwards_Distance_Do_Update	1
+../Core/Src/fsm.c:2587:6:Move_Plane_Task_Backwards_Distance_Do_Update_Turn	5
+../Core/Src/fsm.c:2620:6:Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin	11
+../Core/Src/fsm.c:2713:6:Move_Plane_Task_Backwards_Swing_Back	1
+../Core/Src/fsm.c:2726:6:Change_Road_Left	9
+../Core/Src/fsm.c:2776:6:Change_Road_Right	9
+../Core/Src/fsm.c:2826:6:Forwards_State_Do	1
+../Core/Src/fsm.c:2833:6:Backwards_State_Do	1
+../Core/Src/fsm.c:2840:6:TurnLeft_State_Do	1
+../Core/Src/fsm.c:2845:6:TurnRight_State_Do	1
+../Core/Src/fsm.c:2851:6:TurnRight_State_Do_Plane	1
+../Core/Src/fsm.c:2857:6:TurnLeft_State_Do_Plane	1
+../Core/Src/fsm.c:2867:6:Move_Swing_Left_Func_Do	1
+../Core/Src/fsm.c:2875:6:Move_Swing_Right_Func_Do	1
+../Core/Src/fsm.c:2884:6:Move_Swing_Halt_Func_Do	1
+../Core/Src/fsm.c:2899:6:Plane_Change_Road_Back_Time_Compute	1
+../Core/Src/fsm.c:2906:6:Plane_Change_Road_Back_Time_Countinus	1
+../Core/Src/fsm.c:2916:6:Horizontal_Change_Road_Back_Time_Compute	2
+../Core/Src/fsm.c:2932:6:Vertical_Change_Road_Back_Time_Compute	1
+../Core/Src/fsm.c:2941:6:Fight_Alternately_Function_Horizontal	1
+../Core/Src/fsm.c:2947:6:Fight_Countinus_Function_Horizontal	1
+../Core/Src/fsm.c:2954:6:Fight_Alternately_Function_Vertical	1
+../Core/Src/fsm.c:2959:6:Fight_Alternately_Function_Plane	1
+../Core/Src/fsm.c:2964:6:Fight_Countinus_Function_Plane	1
+../Core/Src/fsm.c:2991:6:Swing_Limit_Contrl	14
+../Core/Src/fsm.c:3063:6:Back_Para_Compute	1
+../Core/Src/fsm.c:3085:6:Robot_Platform_Back_Contronl_Horizontal	13
+../Core/Src/fsm.c:3145:6:Robot_Platform_Back_Contronl_Vertical	12
+../Core/Src/fsm.c:3203:6:Robot_Plane_Auto_Job_Region_Change_Road	6
+../Core/Src/fsm.c:3235:6:Robot_Platform_Back_Contronl_Plane	12
+../Core/Src/fsm.c:3299:6:Platform_Back_Para_Compute_Horizontal	1
+../Core/Src/fsm.c:3307:6:Platform_Back_Para_Compute_Vertical	1
+../Core/Src/fsm.c:3319:6:Platform_Back_Para_Compute_Plane	1
+../Core/Src/fsm.c:3331:6:Platform_Back_Change_Road_Para_Compute	1
+../Core/Src/fsm.c:3342:6:IV_control	12
+../Core/Src/fsm.c:3391:6:IV_control_1	8
+../Core/Src/fsm.c:3433:6:PV_Data_Reading	1
+../Core/Src/fsm.c:3468:6:Robot_Main_Mode_Jude	2
+../Core/Src/fsm.c:3490:6:EmergencyStop_Hardware_Communication_Detection	20
+../Core/Src/fsm.c:3572:6:EmergencyStop_Hardware_Communication_Detection_1	16
+../Core/Src/fsm.c:3658:6:Regional_Horizontal_Automatic_Functionc	11
+../Core/Src/fsm.c:3712:6:Regional_Plane_Automatic_Functionc	11
+../Core/Src/fsm.c:3771:6:Region_Automated_Task_Func_Continuous_Plane	13
+../Core/Src/fsm.c:3869:6:Region_Automated_Task_Func_Continuous_Plane_Uptate_1	14
+../Core/Src/fsm.c:3988:6:Region_Automated_Task_Func_Continuous_Horizontal	15
+../Core/Src/fsm.c:4091:6:Vertical_Angle_Judge_4_Direction	15
+../Core/Src/fsm.c:4118:6:Swing_Mode_Determination	6
+../Core/Src/fsm.c:4173:6:Back_Para_Compute_Updata	1
+../Core/Src/fsm.c:4187:6:Pressure_Adaptive_Function	9
+../Core/Src/fsm.c:4231:6:Pressure_Adaptive_Function_Uptata	9
diff --git a/Debug/Core/Src/fsm.d b/Debug/Core/Src/fsm.d
new file mode 100644
index 0000000..78ee7d4
--- /dev/null
+++ b/Debug/Core/Src/fsm.d
@@ -0,0 +1,218 @@
+Core/Src/fsm.o: ../Core/Src/fsm.c ../Core/Inc/fsm.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ ../Core/Inc/main.h ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
+ ../Core/Inc/dma.h ../Core/Inc/main.h ../Core/Inc/fdcan.h \
+ ../Core/Inc/i2c.h ../Core/Inc/tim.h ../Core/Inc/usart.h \
+ ../Core/Inc/gpio.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_CV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IAP.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_GPIO.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_com_helper.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_TIMER.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_GV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_TL720D.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IO.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_CMCU.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_common.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTuc.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTucConfig.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_JTBATTERY.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UART.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_pb_decode_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TL720D.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_MK32_1.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_WH_LTE_7S0.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_DLT_Log.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UDP.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_cpu_flash.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_qspi_w25q128.h \
+ ../Core/Inc/quadspi.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UpperComputer_Handler.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TTMotor_ZQ.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_Error_Detect.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_PID.h \
+ ../Core/Inc/robot_state.h ../Core/Inc/motors.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TI5MOTOR.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_Error_Detect.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_Blast_Machine.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h
+../Core/Inc/fsm.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+../Core/Inc/main.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
+../Core/Inc/dma.h:
+../Core/Inc/main.h:
+../Core/Inc/fdcan.h:
+../Core/Inc/i2c.h:
+../Core/Inc/tim.h:
+../Core/Inc/usart.h:
+../Core/Inc/gpio.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_CV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IAP.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_GPIO.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_com_helper.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_TIMER.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_GV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_TL720D.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IO.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_CMCU.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_common.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTuc.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTucConfig.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_JTBATTERY.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UART.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_pb_decode_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TL720D.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_MK32_1.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_WH_LTE_7S0.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_DLT_Log.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UDP.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_cpu_flash.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_qspi_w25q128.h:
+../Core/Inc/quadspi.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UpperComputer_Handler.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TTMotor_ZQ.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_Error_Detect.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_PID.h:
+../Core/Inc/robot_state.h:
+../Core/Inc/motors.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TI5MOTOR.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_Error_Detect.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_Blast_Machine.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h:
diff --git a/Debug/Core/Src/fsm.o b/Debug/Core/Src/fsm.o
new file mode 100644
index 0000000..af10a7c
Binary files /dev/null and b/Debug/Core/Src/fsm.o differ
diff --git a/Debug/Core/Src/fsm.su b/Debug/Core/Src/fsm.su
new file mode 100644
index 0000000..23eb734
--- /dev/null
+++ b/Debug/Core/Src/fsm.su
@@ -0,0 +1,114 @@
+../Core/Src/fsm.c:213:6:Fsm_Init	8	static
+../Core/Src/fsm.c:229:6:GF_Dispatch	40	static
+../Core/Src/fsm.c:346:6:action_perfrom	24	static
+../Core/Src/fsm.c:367:6:Robot_Halt_Mode	8	static
+../Core/Src/fsm.c:375:6:Robot_Manual_Operation_Mode	8	static
+../Core/Src/fsm.c:388:6:UltraStopReverse	16	static
+../Core/Src/fsm.c:433:6:UltraStopReverse_Manually_Backward	4	static
+../Core/Src/fsm.c:458:6:PushRod_Contronl	8	static
+../Core/Src/fsm.c:637:6:Robot_Manual_Operation_Function	48	static
+../Core/Src/fsm.c:697:6:Robot_Swing_Operation_Function	8	static
+../Core/Src/fsm.c:716:6:Robot_Swing_Operation_Function_Position	4	static
+../Core/Src/fsm.c:725:6:Horizontal_Operatin_Main_Func	8	static
+../Core/Src/fsm.c:768:6:Move_Horizontal_Auto_Sub_Func	8	static
+../Core/Src/fsm.c:814:6:Change_Road_Down_Left_Right	16	static
+../Core/Src/fsm.c:840:6:Horizontal_Manual_Operation_Func	40	static
+../Core/Src/fsm.c:909:6:Vertical_Operatin_Main_Func_Left	8	static
+../Core/Src/fsm.c:963:6:Vertical_Operatin_Main_Func_Right	8	static
+../Core/Src/fsm.c:1033:6:Move_Vertical_Manual_Sub_Func_Forward	16	static
+../Core/Src/fsm.c:1061:6:Move_Vertical_Manual_Sub_Func_Backward	16	static
+../Core/Src/fsm.c:1090:6:Move_Vertical_Auto_Sub_Func	8	static
+../Core/Src/fsm.c:1139:6:Move_Vertical_Auto_Sub_Func_Forward	8	static
+../Core/Src/fsm.c:1165:6:Plane_Operatin_Main_Func	8	static
+../Core/Src/fsm.c:1213:6:Move_Plane_Auto_Sub_Func	8	static
+../Core/Src/fsm.c:1255:6:Plane_Angle_Judge	4	static
+../Core/Src/fsm.c:1271:6:Region_Automated_Task_Func_Alternately_Plane	16	static
+../Core/Src/fsm.c:1377:6:Region_Automated_Task_Func_Alternately_Horizontal	16	static
+../Core/Src/fsm.c:1491:6:Vertical_Manual_Operation_Func	40	static
+../Core/Src/fsm.c:1557:6:Plane_Manual_Operation_Func	48	static
+../Core/Src/fsm.c:1623:6:Move_Plane_Manual_Sub_Func_Fordwards	8	static
+../Core/Src/fsm.c:1644:6:Move_Plane_Manual_Sub_Func_Backwards	8	static
+../Core/Src/fsm.c:1672:6:Plane_X_Backward_Time_Calculation	16	static
+../Core/Src/fsm.c:1676:6:Plane_X_Backward_Time_Calculation_Continuous	16	static
+../Core/Src/fsm.c:1681:6:Horizontal_X_Backward_Num_Calculation	16	static
+../Core/Src/fsm.c:1686:6:Horizontal_X_Backward_Time_Calculation_Continuous	16	static
+../Core/Src/fsm.c:1693:6:Plane_Y_Lane_Change_Time_Calculation	16	static
+../Core/Src/fsm.c:1698:6:Horizontal_Y_Lane_Change_Time_Calculation	16	static
+../Core/Src/fsm.c:1704:6:Plane_Change_Road_Backward_Num_Calculation	16	static
+../Core/Src/fsm.c:1709:6:Plane_Change_Road_Backward_Time_Calculation_Continuous	16	static
+../Core/Src/fsm.c:1716:6:Horizontal_Change_Road_Backward_Num_Calculation	16	static
+../Core/Src/fsm.c:1721:6:Horizontal_Change_Road_Backward_Time_Calculation_Continuous	16	static
+../Core/Src/fsm.c:1726:6:Plane_Lane_Change_Func	24	static
+../Core/Src/fsm.c:1768:6:Move_Horizontal_Manual_Sub_Func_Forwards	8	static
+../Core/Src/fsm.c:1795:6:Move_Horizontal_Manual_Sub_Func_Backwards	8	static
+../Core/Src/fsm.c:1823:6:Horiz_Angle_Judge	16	static
+../Core/Src/fsm.c:1905:6:Horiz_Angle_Judge_4_Direction	16	static
+../Core/Src/fsm.c:1995:6:Horiz_Angle_Judge_Region	4	static
+../Core/Src/fsm.c:2018:6:Move_Horizontal_Vertical_Task_Forwards_Do_Forwards	72	static
+../Core/Src/fsm.c:2032:6:Move_Horizontal_Task_Change_Road_Backwards_Do	48	static
+../Core/Src/fsm.c:2044:6:Move_Plane_Task_Change_Road_Backwards_Do	48	static
+../Core/Src/fsm.c:2059:6:Move_Speed_Define	4	static
+../Core/Src/fsm.c:2070:6:Robot_Posture_Adjus_Gravity	40	static
+../Core/Src/fsm.c:2111:6:Robot_Posture_Adjus_Plane	40	static
+../Core/Src/fsm.c:2158:6:Vertical_Angle_Judge	16	static
+../Core/Src/fsm.c:2190:6:Vertical_Angle_Judge_Uptata_1	16	static
+../Core/Src/fsm.c:2206:6:Change_Road_Down_Up_Right_To_Left	24	static
+../Core/Src/fsm.c:2254:6:Change_Road_Down_Up_Left_To_Right	24	static
+../Core/Src/fsm.c:2302:6:Change_Road_Plane	8	static
+../Core/Src/fsm.c:2372:6:Change_Road_Plane_Continuous_FanDi_Left	8	static
+../Core/Src/fsm.c:2443:6:Change_Road_Plane_Continuous_FanDi_Right	8	static
+../Core/Src/fsm.c:2517:6:Move_Plane_Task_Fordwards_Do	56	static
+../Core/Src/fsm.c:2527:6:Move_Plane_Task_Fordwards_Do_Update	72	static
+../Core/Src/fsm.c:2540:6:Move_Plane_Task_Backwards_Do	56	static
+../Core/Src/fsm.c:2550:6:Move_Plane_Task_Backwards_Distance_Do	56	static
+../Core/Src/fsm.c:2561:6:Move_Horizontal_Vertical_Task_Backwards_Do_Backward	72	static
+../Core/Src/fsm.c:2577:6:Move_Plane_Task_Backwards_Distance_Do_Update	72	static
+../Core/Src/fsm.c:2587:6:Move_Plane_Task_Backwards_Distance_Do_Update_Turn	72	static
+../Core/Src/fsm.c:2620:6:Move_Plane_Task_Backwards_Distance_Do_Update_Turn_Origin	72	static
+../Core/Src/fsm.c:2713:6:Move_Plane_Task_Backwards_Swing_Back	56	static
+../Core/Src/fsm.c:2726:6:Change_Road_Left	24	static
+../Core/Src/fsm.c:2776:6:Change_Road_Right	24	static
+../Core/Src/fsm.c:2826:6:Forwards_State_Do	4	static
+../Core/Src/fsm.c:2833:6:Backwards_State_Do	4	static
+../Core/Src/fsm.c:2840:6:TurnLeft_State_Do	4	static
+../Core/Src/fsm.c:2845:6:TurnRight_State_Do	4	static
+../Core/Src/fsm.c:2851:6:TurnRight_State_Do_Plane	4	static
+../Core/Src/fsm.c:2857:6:TurnLeft_State_Do_Plane	4	static
+../Core/Src/fsm.c:2867:6:Move_Swing_Left_Func_Do	4	static
+../Core/Src/fsm.c:2875:6:Move_Swing_Right_Func_Do	4	static
+../Core/Src/fsm.c:2884:6:Move_Swing_Halt_Func_Do	4	static
+../Core/Src/fsm.c:2899:6:Plane_Change_Road_Back_Time_Compute	4	static
+../Core/Src/fsm.c:2906:6:Plane_Change_Road_Back_Time_Countinus	4	static
+../Core/Src/fsm.c:2916:6:Horizontal_Change_Road_Back_Time_Compute	16	static
+../Core/Src/fsm.c:2932:6:Vertical_Change_Road_Back_Time_Compute	4	static
+../Core/Src/fsm.c:2941:6:Fight_Alternately_Function_Horizontal	8	static
+../Core/Src/fsm.c:2947:6:Fight_Countinus_Function_Horizontal	8	static
+../Core/Src/fsm.c:2954:6:Fight_Alternately_Function_Vertical	8	static
+../Core/Src/fsm.c:2959:6:Fight_Alternately_Function_Plane	8	static
+../Core/Src/fsm.c:2964:6:Fight_Countinus_Function_Plane	8	static
+../Core/Src/fsm.c:2991:6:Swing_Limit_Contrl	8	static
+../Core/Src/fsm.c:3063:6:Back_Para_Compute	40	static
+../Core/Src/fsm.c:3085:6:Robot_Platform_Back_Contronl_Horizontal	8	static
+../Core/Src/fsm.c:3145:6:Robot_Platform_Back_Contronl_Vertical	8	static
+../Core/Src/fsm.c:3203:6:Robot_Plane_Auto_Job_Region_Change_Road	8	static
+../Core/Src/fsm.c:3235:6:Robot_Platform_Back_Contronl_Plane	8	static
+../Core/Src/fsm.c:3299:6:Platform_Back_Para_Compute_Horizontal	24	static
+../Core/Src/fsm.c:3307:6:Platform_Back_Para_Compute_Vertical	24	static
+../Core/Src/fsm.c:3319:6:Platform_Back_Para_Compute_Plane	24	static
+../Core/Src/fsm.c:3331:6:Platform_Back_Change_Road_Para_Compute	24	static
+../Core/Src/fsm.c:3342:6:IV_control	4	static
+../Core/Src/fsm.c:3391:6:IV_control_1	8	static
+../Core/Src/fsm.c:3433:6:PV_Data_Reading	4	static
+../Core/Src/fsm.c:3468:6:Robot_Main_Mode_Jude	56	static
+../Core/Src/fsm.c:3490:6:EmergencyStop_Hardware_Communication_Detection	8	static
+../Core/Src/fsm.c:3572:6:EmergencyStop_Hardware_Communication_Detection_1	8	static
+../Core/Src/fsm.c:3658:6:Regional_Horizontal_Automatic_Functionc	8	static
+../Core/Src/fsm.c:3712:6:Regional_Plane_Automatic_Functionc	8	static
+../Core/Src/fsm.c:3771:6:Region_Automated_Task_Func_Continuous_Plane	16	static
+../Core/Src/fsm.c:3869:6:Region_Automated_Task_Func_Continuous_Plane_Uptate_1	16	static
+../Core/Src/fsm.c:3988:6:Region_Automated_Task_Func_Continuous_Horizontal	16	static
+../Core/Src/fsm.c:4091:6:Vertical_Angle_Judge_4_Direction	16	static
+../Core/Src/fsm.c:4118:6:Swing_Mode_Determination	24	static
+../Core/Src/fsm.c:4173:6:Back_Para_Compute_Updata	24	static
+../Core/Src/fsm.c:4187:6:Pressure_Adaptive_Function	24	static
+../Core/Src/fsm.c:4231:6:Pressure_Adaptive_Function_Uptata	24	static
diff --git a/Debug/Core/Src/gpio.cyclo b/Debug/Core/Src/gpio.cyclo
new file mode 100644
index 0000000..1a0fdbe
--- /dev/null
+++ b/Debug/Core/Src/gpio.cyclo
@@ -0,0 +1 @@
+../Core/Src/gpio.c:41:6:MX_GPIO_Init	1
diff --git a/Debug/Core/Src/gpio.d b/Debug/Core/Src/gpio.d
new file mode 100644
index 0000000..d401043
--- /dev/null
+++ b/Debug/Core/Src/gpio.d
@@ -0,0 +1,81 @@
+Core/Src/gpio.o: ../Core/Src/gpio.c ../Core/Inc/gpio.h ../Core/Inc/main.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
+../Core/Inc/gpio.h:
+../Core/Inc/main.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Core/Src/gpio.o b/Debug/Core/Src/gpio.o
new file mode 100644
index 0000000..44d5d8c
Binary files /dev/null and b/Debug/Core/Src/gpio.o differ
diff --git a/Debug/Core/Src/gpio.su b/Debug/Core/Src/gpio.su
new file mode 100644
index 0000000..a82ef21
--- /dev/null
+++ b/Debug/Core/Src/gpio.su
@@ -0,0 +1 @@
+../Core/Src/gpio.c:41:6:MX_GPIO_Init	56	static
diff --git a/Debug/Core/Src/i2c.cyclo b/Debug/Core/Src/i2c.cyclo
new file mode 100644
index 0000000..569806a
--- /dev/null
+++ b/Debug/Core/Src/i2c.cyclo
@@ -0,0 +1,3 @@
+../Core/Src/i2c.c:30:6:MX_I2C4_Init	4
+../Core/Src/i2c.c:73:6:HAL_I2C_MspInit	3
+../Core/Src/i2c.c:119:6:HAL_I2C_MspDeInit	2
diff --git a/Debug/Core/Src/i2c.d b/Debug/Core/Src/i2c.d
new file mode 100644
index 0000000..5196817
--- /dev/null
+++ b/Debug/Core/Src/i2c.d
@@ -0,0 +1,81 @@
+Core/Src/i2c.o: ../Core/Src/i2c.c ../Core/Inc/i2c.h ../Core/Inc/main.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
+../Core/Inc/i2c.h:
+../Core/Inc/main.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Core/Src/i2c.o b/Debug/Core/Src/i2c.o
new file mode 100644
index 0000000..bad395e
Binary files /dev/null and b/Debug/Core/Src/i2c.o differ
diff --git a/Debug/Core/Src/i2c.su b/Debug/Core/Src/i2c.su
new file mode 100644
index 0000000..cafc056
--- /dev/null
+++ b/Debug/Core/Src/i2c.su
@@ -0,0 +1,3 @@
+../Core/Src/i2c.c:30:6:MX_I2C4_Init	8	static
+../Core/Src/i2c.c:73:6:HAL_I2C_MspInit	240	static
+../Core/Src/i2c.c:119:6:HAL_I2C_MspDeInit	16	static
diff --git a/Debug/Core/Src/main.cyclo b/Debug/Core/Src/main.cyclo
new file mode 100644
index 0000000..5315db3
--- /dev/null
+++ b/Debug/Core/Src/main.cyclo
@@ -0,0 +1,6 @@
+../Core/Src/main.c:107:5:main	5
+../Core/Src/main.c:199:6:SystemClock_Config	4
+../Core/Src/main.c:259:6:CV_GV_Init	1
+../Core/Src/main.c:304:6:GF_Robot_Init	1
+../Core/Src/main.c:359:6:MPU_Config	1
+../Core/Src/main.c:411:6:Error_Handler	2
diff --git a/Debug/Core/Src/main.d b/Debug/Core/Src/main.d
new file mode 100644
index 0000000..a7d32f5
--- /dev/null
+++ b/Debug/Core/Src/main.d
@@ -0,0 +1,227 @@
+Core/Src/main.o: ../Core/Src/main.c ../Core/Inc/main.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
+ ../Core/Inc/adc.h ../Core/Inc/main.h ../Core/Inc/dma.h ../Core/Inc/eth.h \
+ ../Core/Inc/fdcan.h ../Core/Inc/i2c.h ../Core/Inc/usart.h \
+ ../Core/Inc/quadspi.h ../Core/Inc/tim.h ../Core/Inc/gpio.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_CV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IAP.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_GPIO.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_com_helper.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_TIMER.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_GV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_TL720D.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IO.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_CMCU.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_common.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTuc.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTucConfig.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_JTBATTERY.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UART.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_pb_decode_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TL720D.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_MK32_1.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_WH_LTE_7S0.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_DLT_Log.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UDP.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_cpu_flash.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_qspi_w25q128.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UpperComputer_Handler.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TTMotor_ZQ.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h \
+ ../Core/Inc/fsm.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_Error_Detect.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IV.pb.h \
+ ../Core/Inc/motors.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TI5MOTOR.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_Error_Detect.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_client_setting.h \
+ ../Core/Inc/robot_state.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_MF_Gyroscope.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_CMCUU.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_KS206.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_Blast_Machine.h
+../Core/Inc/main.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
+../Core/Inc/adc.h:
+../Core/Inc/main.h:
+../Core/Inc/dma.h:
+../Core/Inc/eth.h:
+../Core/Inc/fdcan.h:
+../Core/Inc/i2c.h:
+../Core/Inc/usart.h:
+../Core/Inc/quadspi.h:
+../Core/Inc/tim.h:
+../Core/Inc/gpio.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_CV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IAP.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_GPIO.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_com_helper.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_TIMER.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_GV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_TL720D.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IO.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_CMCU.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_common.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTuc.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTucConfig.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_JTBATTERY.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UART.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_pb_decode_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TL720D.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_MK32_1.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_WH_LTE_7S0.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_DLT_Log.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UDP.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_cpu_flash.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_qspi_w25q128.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UpperComputer_Handler.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TTMotor_ZQ.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h:
+../Core/Inc/fsm.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_Error_Detect.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IV.pb.h:
+../Core/Inc/motors.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TI5MOTOR.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_Error_Detect.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_client_setting.h:
+../Core/Inc/robot_state.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_MF_Gyroscope.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_CMCUU.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_KS206.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_Blast_Machine.h:
diff --git a/Debug/Core/Src/main.o b/Debug/Core/Src/main.o
new file mode 100644
index 0000000..b5b24d2
Binary files /dev/null and b/Debug/Core/Src/main.o differ
diff --git a/Debug/Core/Src/main.su b/Debug/Core/Src/main.su
new file mode 100644
index 0000000..956c683
--- /dev/null
+++ b/Debug/Core/Src/main.su
@@ -0,0 +1,6 @@
+../Core/Src/main.c:107:5:main	24	static,ignoring_inline_asm
+../Core/Src/main.c:199:6:SystemClock_Config	120	static
+../Core/Src/main.c:259:6:CV_GV_Init	176	static
+../Core/Src/main.c:304:6:GF_Robot_Init	56	static
+../Core/Src/main.c:359:6:MPU_Config	24	static
+../Core/Src/main.c:411:6:Error_Handler	24	static,ignoring_inline_asm
diff --git a/Debug/Core/Src/motors.cyclo b/Debug/Core/Src/motors.cyclo
new file mode 100644
index 0000000..1711ada
--- /dev/null
+++ b/Debug/Core/Src/motors.cyclo
@@ -0,0 +1,6 @@
+../Core/Src/motors.c:24:6:Motor_Controller_intialize	1
+../Core/Src/motors.c:40:6:Motor_Controller_intialize_CAN2	1
+../Core/Src/motors.c:58:6:MotorCommandsLoop	4
+../Core/Src/motors.c:102:6:MotorCommandsLoop_2_Position	5
+../Core/Src/motors.c:179:6:MotorCommandsLoop_2	4
+../Core/Src/motors.c:214:6:Roughening_MotorDecodeCAN	5
diff --git a/Debug/Core/Src/motors.d b/Debug/Core/Src/motors.d
new file mode 100644
index 0000000..c20c28b
--- /dev/null
+++ b/Debug/Core/Src/motors.d
@@ -0,0 +1,211 @@
+Core/Src/motors.o: ../Core/Src/motors.c ../Core/Inc/motors.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TI5MOTOR.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ ../Core/Inc/main.h ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
+ ../Core/Inc/dma.h ../Core/Inc/main.h ../Core/Inc/fdcan.h \
+ ../Core/Inc/i2c.h ../Core/Inc/tim.h ../Core/Inc/usart.h \
+ ../Core/Inc/gpio.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_CV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IAP.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_GPIO.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_com_helper.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_TIMER.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_GV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_TL720D.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IO.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_CMCU.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_common.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTuc.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTucConfig.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_Error_Detect.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_JTBATTERY.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UART.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_pb_decode_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TL720D.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_MK32_1.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_WH_LTE_7S0.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_DLT_Log.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UDP.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_cpu_flash.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_qspi_w25q128.h \
+ ../Core/Inc/quadspi.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UpperComputer_Handler.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TTMotor_ZQ.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h \
+ ../Core/Inc/fsm.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_Error_Detect.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h
+../Core/Inc/motors.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TI5MOTOR.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+../Core/Inc/main.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
+../Core/Inc/dma.h:
+../Core/Inc/main.h:
+../Core/Inc/fdcan.h:
+../Core/Inc/i2c.h:
+../Core/Inc/tim.h:
+../Core/Inc/usart.h:
+../Core/Inc/gpio.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_CV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IAP.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_GPIO.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_com_helper.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_TIMER.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_GV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_TL720D.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IO.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_CMCU.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_common.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTuc.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTucConfig.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_Error_Detect.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_JTBATTERY.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UART.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_pb_decode_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TL720D.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_MK32_1.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_WH_LTE_7S0.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_DLT_Log.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UDP.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_cpu_flash.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_qspi_w25q128.h:
+../Core/Inc/quadspi.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UpperComputer_Handler.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TTMotor_ZQ.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h:
+../Core/Inc/fsm.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_Error_Detect.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h:
diff --git a/Debug/Core/Src/motors.o b/Debug/Core/Src/motors.o
new file mode 100644
index 0000000..960eb9f
Binary files /dev/null and b/Debug/Core/Src/motors.o differ
diff --git a/Debug/Core/Src/motors.su b/Debug/Core/Src/motors.su
new file mode 100644
index 0000000..c7c120a
--- /dev/null
+++ b/Debug/Core/Src/motors.su
@@ -0,0 +1,6 @@
+../Core/Src/motors.c:24:6:Motor_Controller_intialize	24	static
+../Core/Src/motors.c:40:6:Motor_Controller_intialize_CAN2	24	static
+../Core/Src/motors.c:58:6:MotorCommandsLoop	24	static
+../Core/Src/motors.c:102:6:MotorCommandsLoop_2_Position	32	static
+../Core/Src/motors.c:179:6:MotorCommandsLoop_2	24	static
+../Core/Src/motors.c:214:6:Roughening_MotorDecodeCAN	24	static
diff --git a/Debug/Core/Src/quadspi.cyclo b/Debug/Core/Src/quadspi.cyclo
new file mode 100644
index 0000000..c9d98cc
--- /dev/null
+++ b/Debug/Core/Src/quadspi.cyclo
@@ -0,0 +1,3 @@
+../Core/Src/quadspi.c:30:6:MX_QUADSPI_Init	2
+../Core/Src/quadspi.c:59:6:HAL_QSPI_MspInit	3
+../Core/Src/quadspi.c:123:6:HAL_QSPI_MspDeInit	2
diff --git a/Debug/Core/Src/quadspi.d b/Debug/Core/Src/quadspi.d
new file mode 100644
index 0000000..bece69a
--- /dev/null
+++ b/Debug/Core/Src/quadspi.d
@@ -0,0 +1,81 @@
+Core/Src/quadspi.o: ../Core/Src/quadspi.c ../Core/Inc/quadspi.h \
+ ../Core/Inc/main.h ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
+../Core/Inc/quadspi.h:
+../Core/Inc/main.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Core/Src/quadspi.o b/Debug/Core/Src/quadspi.o
new file mode 100644
index 0000000..00c0446
Binary files /dev/null and b/Debug/Core/Src/quadspi.o differ
diff --git a/Debug/Core/Src/quadspi.su b/Debug/Core/Src/quadspi.su
new file mode 100644
index 0000000..44237dd
--- /dev/null
+++ b/Debug/Core/Src/quadspi.su
@@ -0,0 +1,3 @@
+../Core/Src/quadspi.c:30:6:MX_QUADSPI_Init	8	static
+../Core/Src/quadspi.c:59:6:HAL_QSPI_MspInit	248	static
+../Core/Src/quadspi.c:123:6:HAL_QSPI_MspDeInit	16	static
diff --git a/Debug/Core/Src/robot_state.cyclo b/Debug/Core/Src/robot_state.cyclo
new file mode 100644
index 0000000..40db9c9
--- /dev/null
+++ b/Debug/Core/Src/robot_state.cyclo
@@ -0,0 +1,11 @@
+../Core/Src/robot_state.c:51:6:Move_PushRod_Halt_Func_Do	1
+../Core/Src/robot_state.c:56:6:Move_PushRod_Up_Func_Do	1
+../Core/Src/robot_state.c:62:6:Move_PushRod_Down_Func_Do	1
+../Core/Src/robot_state.c:68:6:Move_PushRod_Halt_Func_Do_1	1
+../Core/Src/robot_state.c:74:6:Move_PushRod_Up_Func_Do_1	1
+../Core/Src/robot_state.c:81:6:Move_PushRod_Down_Func_Do_1	1
+../Core/Src/robot_state.c:106:6:Abnormal_State_Do	2
+../Core/Src/robot_state.c:114:6:HALT_State_Do	1
+../Core/Src/robot_state.c:130:6:TiltUp_Do	1
+../Core/Src/robot_state.c:139:6:TiltDown_Do	1
+../Core/Src/robot_state.c:157:6:TiltHalt_Do	1
diff --git a/Debug/Core/Src/robot_state.d b/Debug/Core/Src/robot_state.d
new file mode 100644
index 0000000..498fe32
--- /dev/null
+++ b/Debug/Core/Src/robot_state.d
@@ -0,0 +1,210 @@
+Core/Src/robot_state.o: ../Core/Src/robot_state.c \
+ ../Core/Inc/robot_state.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ ../Core/Inc/main.h ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
+ ../Core/Inc/dma.h ../Core/Inc/main.h ../Core/Inc/fdcan.h \
+ ../Core/Inc/i2c.h ../Core/Inc/tim.h ../Core/Inc/usart.h \
+ ../Core/Inc/gpio.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_CV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IAP.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_GPIO.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_com_helper.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_TIMER.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_GV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_TL720D.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IO.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_CMCU.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_common.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTuc.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTucConfig.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_JTBATTERY.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UART.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_pb_decode_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TL720D.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_MK32_1.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_WH_LTE_7S0.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_DLT_Log.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UDP.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_cpu_flash.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_qspi_w25q128.h \
+ ../Core/Inc/quadspi.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UpperComputer_Handler.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TTMotor_ZQ.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h \
+ ../Core/Inc/fsm.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_Error_Detect.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IV.pb.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_GPIO.h \
+ F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_PID.h
+../Core/Inc/robot_state.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+../Core/Inc/main.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
+../Core/Inc/dma.h:
+../Core/Inc/main.h:
+../Core/Inc/fdcan.h:
+../Core/Inc/i2c.h:
+../Core/Inc/tim.h:
+../Core/Inc/usart.h:
+../Core/Inc/gpio.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_CV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IAP.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_GPIO.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_com_helper.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_TIMER.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_PV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_GV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_TL720D.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_Error.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IO.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_CMCU.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_KS206.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_common.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTuc.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/DLTucConfig.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_JTBATTERY.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UART.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/BHBF_ROBOT.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_decode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_EEPROM.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_pb_decode_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/pb_encode.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_MK32.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/msp_Motor.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TL720D.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_MB_host.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_MK32_1.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_WH_LTE_7S0.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_DLT_Log.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UDP.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_cpu_flash.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_qspi_w25q128.h:
+../Core/Inc/quadspi.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_UpperComputer_Handler.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_TTMotor_ZQ.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_include.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_FDCAN.h:
+../Core/Inc/fsm.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_Error_Detect.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource/bsp_IV.pb.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP/bsp_GPIO.h:
+F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP/msp_PID.h:
diff --git a/Debug/Core/Src/robot_state.o b/Debug/Core/Src/robot_state.o
new file mode 100644
index 0000000..e67e84a
Binary files /dev/null and b/Debug/Core/Src/robot_state.o differ
diff --git a/Debug/Core/Src/robot_state.su b/Debug/Core/Src/robot_state.su
new file mode 100644
index 0000000..0133413
--- /dev/null
+++ b/Debug/Core/Src/robot_state.su
@@ -0,0 +1,11 @@
+../Core/Src/robot_state.c:51:6:Move_PushRod_Halt_Func_Do	8	static
+../Core/Src/robot_state.c:56:6:Move_PushRod_Up_Func_Do	8	static
+../Core/Src/robot_state.c:62:6:Move_PushRod_Down_Func_Do	8	static
+../Core/Src/robot_state.c:68:6:Move_PushRod_Halt_Func_Do_1	8	static
+../Core/Src/robot_state.c:74:6:Move_PushRod_Up_Func_Do_1	8	static
+../Core/Src/robot_state.c:81:6:Move_PushRod_Down_Func_Do_1	8	static
+../Core/Src/robot_state.c:106:6:Abnormal_State_Do	8	static
+../Core/Src/robot_state.c:114:6:HALT_State_Do	4	static
+../Core/Src/robot_state.c:130:6:TiltUp_Do	8	static
+../Core/Src/robot_state.c:139:6:TiltDown_Do	8	static
+../Core/Src/robot_state.c:157:6:TiltHalt_Do	8	static
diff --git a/Debug/Core/Src/stm32h7xx_hal_msp.cyclo b/Debug/Core/Src/stm32h7xx_hal_msp.cyclo
new file mode 100644
index 0000000..17fe7d1
--- /dev/null
+++ b/Debug/Core/Src/stm32h7xx_hal_msp.cyclo
@@ -0,0 +1 @@
+../Core/Src/stm32h7xx_hal_msp.c:63:6:HAL_MspInit	1
diff --git a/Debug/Core/Src/stm32h7xx_hal_msp.d b/Debug/Core/Src/stm32h7xx_hal_msp.d
new file mode 100644
index 0000000..ba1faae
--- /dev/null
+++ b/Debug/Core/Src/stm32h7xx_hal_msp.d
@@ -0,0 +1,80 @@
+Core/Src/stm32h7xx_hal_msp.o: ../Core/Src/stm32h7xx_hal_msp.c \
+ ../Core/Inc/main.h ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
+../Core/Inc/main.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Core/Src/stm32h7xx_hal_msp.o b/Debug/Core/Src/stm32h7xx_hal_msp.o
new file mode 100644
index 0000000..fcb6e60
Binary files /dev/null and b/Debug/Core/Src/stm32h7xx_hal_msp.o differ
diff --git a/Debug/Core/Src/stm32h7xx_hal_msp.su b/Debug/Core/Src/stm32h7xx_hal_msp.su
new file mode 100644
index 0000000..f8a2280
--- /dev/null
+++ b/Debug/Core/Src/stm32h7xx_hal_msp.su
@@ -0,0 +1 @@
+../Core/Src/stm32h7xx_hal_msp.c:63:6:HAL_MspInit	16	static
diff --git a/Debug/Core/Src/stm32h7xx_it.cyclo b/Debug/Core/Src/stm32h7xx_it.cyclo
new file mode 100644
index 0000000..a07e326
--- /dev/null
+++ b/Debug/Core/Src/stm32h7xx_it.cyclo
@@ -0,0 +1,33 @@
+../Core/Src/stm32h7xx_it.c:90:6:NMI_Handler	1
+../Core/Src/stm32h7xx_it.c:106:6:HardFault_Handler	1
+../Core/Src/stm32h7xx_it.c:124:6:MemManage_Handler	1
+../Core/Src/stm32h7xx_it.c:139:6:BusFault_Handler	1
+../Core/Src/stm32h7xx_it.c:154:6:UsageFault_Handler	1
+../Core/Src/stm32h7xx_it.c:169:6:SVC_Handler	1
+../Core/Src/stm32h7xx_it.c:182:6:DebugMon_Handler	1
+../Core/Src/stm32h7xx_it.c:195:6:PendSV_Handler	1
+../Core/Src/stm32h7xx_it.c:208:6:SysTick_Handler	1
+../Core/Src/stm32h7xx_it.c:229:6:DMA1_Stream0_IRQHandler	1
+../Core/Src/stm32h7xx_it.c:243:6:DMA1_Stream1_IRQHandler	1
+../Core/Src/stm32h7xx_it.c:257:6:DMA1_Stream2_IRQHandler	1
+../Core/Src/stm32h7xx_it.c:271:6:DMA1_Stream3_IRQHandler	1
+../Core/Src/stm32h7xx_it.c:285:6:DMA1_Stream5_IRQHandler	1
+../Core/Src/stm32h7xx_it.c:299:6:DMA1_Stream6_IRQHandler	1
+../Core/Src/stm32h7xx_it.c:313:6:FDCAN1_IT0_IRQHandler	1
+../Core/Src/stm32h7xx_it.c:327:6:FDCAN2_IT0_IRQHandler	1
+../Core/Src/stm32h7xx_it.c:341:6:TIM1_UP_IRQHandler	1
+../Core/Src/stm32h7xx_it.c:355:6:USART1_IRQHandler	1
+../Core/Src/stm32h7xx_it.c:369:6:USART2_IRQHandler	1
+../Core/Src/stm32h7xx_it.c:383:6:USART3_IRQHandler	1
+../Core/Src/stm32h7xx_it.c:397:6:TIM8_UP_TIM13_IRQHandler	1
+../Core/Src/stm32h7xx_it.c:411:6:DMA1_Stream7_IRQHandler	1
+../Core/Src/stm32h7xx_it.c:425:6:UART4_IRQHandler	1
+../Core/Src/stm32h7xx_it.c:439:6:UART5_IRQHandler	1
+../Core/Src/stm32h7xx_it.c:453:6:ETH_IRQHandler	1
+../Core/Src/stm32h7xx_it.c:467:6:ETH_WKUP_IRQHandler	1
+../Core/Src/stm32h7xx_it.c:481:6:USART6_IRQHandler	1
+../Core/Src/stm32h7xx_it.c:495:6:UART7_IRQHandler	1
+../Core/Src/stm32h7xx_it.c:509:6:QUADSPI_IRQHandler	1
+../Core/Src/stm32h7xx_it.c:523:6:I2C4_EV_IRQHandler	1
+../Core/Src/stm32h7xx_it.c:537:6:I2C4_ER_IRQHandler	1
+../Core/Src/stm32h7xx_it.c:551:6:LPUART1_IRQHandler	1
diff --git a/Debug/Core/Src/stm32h7xx_it.d b/Debug/Core/Src/stm32h7xx_it.d
new file mode 100644
index 0000000..6da08cf
--- /dev/null
+++ b/Debug/Core/Src/stm32h7xx_it.d
@@ -0,0 +1,82 @@
+Core/Src/stm32h7xx_it.o: ../Core/Src/stm32h7xx_it.c ../Core/Inc/main.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h \
+ ../Core/Inc/stm32h7xx_it.h
+../Core/Inc/main.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
+../Core/Inc/stm32h7xx_it.h:
diff --git a/Debug/Core/Src/stm32h7xx_it.o b/Debug/Core/Src/stm32h7xx_it.o
new file mode 100644
index 0000000..b8312d3
Binary files /dev/null and b/Debug/Core/Src/stm32h7xx_it.o differ
diff --git a/Debug/Core/Src/stm32h7xx_it.su b/Debug/Core/Src/stm32h7xx_it.su
new file mode 100644
index 0000000..54cabe6
--- /dev/null
+++ b/Debug/Core/Src/stm32h7xx_it.su
@@ -0,0 +1,33 @@
+../Core/Src/stm32h7xx_it.c:90:6:NMI_Handler	8	static
+../Core/Src/stm32h7xx_it.c:106:6:HardFault_Handler	4	static
+../Core/Src/stm32h7xx_it.c:124:6:MemManage_Handler	4	static
+../Core/Src/stm32h7xx_it.c:139:6:BusFault_Handler	4	static
+../Core/Src/stm32h7xx_it.c:154:6:UsageFault_Handler	4	static
+../Core/Src/stm32h7xx_it.c:169:6:SVC_Handler	4	static
+../Core/Src/stm32h7xx_it.c:182:6:DebugMon_Handler	4	static
+../Core/Src/stm32h7xx_it.c:195:6:PendSV_Handler	4	static
+../Core/Src/stm32h7xx_it.c:208:6:SysTick_Handler	8	static
+../Core/Src/stm32h7xx_it.c:229:6:DMA1_Stream0_IRQHandler	8	static
+../Core/Src/stm32h7xx_it.c:243:6:DMA1_Stream1_IRQHandler	8	static
+../Core/Src/stm32h7xx_it.c:257:6:DMA1_Stream2_IRQHandler	8	static
+../Core/Src/stm32h7xx_it.c:271:6:DMA1_Stream3_IRQHandler	8	static
+../Core/Src/stm32h7xx_it.c:285:6:DMA1_Stream5_IRQHandler	8	static
+../Core/Src/stm32h7xx_it.c:299:6:DMA1_Stream6_IRQHandler	8	static
+../Core/Src/stm32h7xx_it.c:313:6:FDCAN1_IT0_IRQHandler	8	static
+../Core/Src/stm32h7xx_it.c:327:6:FDCAN2_IT0_IRQHandler	8	static
+../Core/Src/stm32h7xx_it.c:341:6:TIM1_UP_IRQHandler	8	static
+../Core/Src/stm32h7xx_it.c:355:6:USART1_IRQHandler	8	static
+../Core/Src/stm32h7xx_it.c:369:6:USART2_IRQHandler	8	static
+../Core/Src/stm32h7xx_it.c:383:6:USART3_IRQHandler	8	static
+../Core/Src/stm32h7xx_it.c:397:6:TIM8_UP_TIM13_IRQHandler	8	static
+../Core/Src/stm32h7xx_it.c:411:6:DMA1_Stream7_IRQHandler	8	static
+../Core/Src/stm32h7xx_it.c:425:6:UART4_IRQHandler	8	static
+../Core/Src/stm32h7xx_it.c:439:6:UART5_IRQHandler	8	static
+../Core/Src/stm32h7xx_it.c:453:6:ETH_IRQHandler	8	static
+../Core/Src/stm32h7xx_it.c:467:6:ETH_WKUP_IRQHandler	8	static
+../Core/Src/stm32h7xx_it.c:481:6:USART6_IRQHandler	8	static
+../Core/Src/stm32h7xx_it.c:495:6:UART7_IRQHandler	8	static
+../Core/Src/stm32h7xx_it.c:509:6:QUADSPI_IRQHandler	8	static
+../Core/Src/stm32h7xx_it.c:523:6:I2C4_EV_IRQHandler	8	static
+../Core/Src/stm32h7xx_it.c:537:6:I2C4_ER_IRQHandler	8	static
+../Core/Src/stm32h7xx_it.c:551:6:LPUART1_IRQHandler	8	static
diff --git a/Debug/Core/Src/subdir.mk b/Debug/Core/Src/subdir.mk
new file mode 100644
index 0000000..28cd118
--- /dev/null
+++ b/Debug/Core/Src/subdir.mk
@@ -0,0 +1,78 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+# Toolchain: GNU Tools for STM32 (12.3.rel1)
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables 
+C_SRCS += \
+../Core/Src/adc.c \
+../Core/Src/dma.c \
+../Core/Src/eth.c \
+../Core/Src/fdcan.c \
+../Core/Src/fsm.c \
+../Core/Src/gpio.c \
+../Core/Src/i2c.c \
+../Core/Src/main.c \
+../Core/Src/motors.c \
+../Core/Src/quadspi.c \
+../Core/Src/robot_state.c \
+../Core/Src/stm32h7xx_hal_msp.c \
+../Core/Src/stm32h7xx_it.c \
+../Core/Src/syscalls.c \
+../Core/Src/sysmem.c \
+../Core/Src/system_stm32h7xx.c \
+../Core/Src/tim.c \
+../Core/Src/usart.c 
+
+OBJS += \
+./Core/Src/adc.o \
+./Core/Src/dma.o \
+./Core/Src/eth.o \
+./Core/Src/fdcan.o \
+./Core/Src/fsm.o \
+./Core/Src/gpio.o \
+./Core/Src/i2c.o \
+./Core/Src/main.o \
+./Core/Src/motors.o \
+./Core/Src/quadspi.o \
+./Core/Src/robot_state.o \
+./Core/Src/stm32h7xx_hal_msp.o \
+./Core/Src/stm32h7xx_it.o \
+./Core/Src/syscalls.o \
+./Core/Src/sysmem.o \
+./Core/Src/system_stm32h7xx.o \
+./Core/Src/tim.o \
+./Core/Src/usart.o 
+
+C_DEPS += \
+./Core/Src/adc.d \
+./Core/Src/dma.d \
+./Core/Src/eth.d \
+./Core/Src/fdcan.d \
+./Core/Src/fsm.d \
+./Core/Src/gpio.d \
+./Core/Src/i2c.d \
+./Core/Src/main.d \
+./Core/Src/motors.d \
+./Core/Src/quadspi.d \
+./Core/Src/robot_state.d \
+./Core/Src/stm32h7xx_hal_msp.d \
+./Core/Src/stm32h7xx_it.d \
+./Core/Src/syscalls.d \
+./Core/Src/sysmem.d \
+./Core/Src/system_stm32h7xx.d \
+./Core/Src/tim.d \
+./Core/Src/usart.d 
+
+
+# Each subdirectory must supply rules for building sources it contributes
+Core/Src/%.o Core/Src/%.su Core/Src/%.cyclo: ../Core/Src/%.c Core/Src/subdir.mk
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32H743xx -c -I../Core/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I../Drivers/CMSIS/Include -I"F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc" -I"F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource" -I"F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP" -I"F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
+
+clean: clean-Core-2f-Src
+
+clean-Core-2f-Src:
+	-$(RM) ./Core/Src/adc.cyclo ./Core/Src/adc.d ./Core/Src/adc.o ./Core/Src/adc.su ./Core/Src/dma.cyclo ./Core/Src/dma.d ./Core/Src/dma.o ./Core/Src/dma.su ./Core/Src/eth.cyclo ./Core/Src/eth.d ./Core/Src/eth.o ./Core/Src/eth.su ./Core/Src/fdcan.cyclo ./Core/Src/fdcan.d ./Core/Src/fdcan.o ./Core/Src/fdcan.su ./Core/Src/fsm.cyclo ./Core/Src/fsm.d ./Core/Src/fsm.o ./Core/Src/fsm.su ./Core/Src/gpio.cyclo ./Core/Src/gpio.d ./Core/Src/gpio.o ./Core/Src/gpio.su ./Core/Src/i2c.cyclo ./Core/Src/i2c.d ./Core/Src/i2c.o ./Core/Src/i2c.su ./Core/Src/main.cyclo ./Core/Src/main.d ./Core/Src/main.o ./Core/Src/main.su ./Core/Src/motors.cyclo ./Core/Src/motors.d ./Core/Src/motors.o ./Core/Src/motors.su ./Core/Src/quadspi.cyclo ./Core/Src/quadspi.d ./Core/Src/quadspi.o ./Core/Src/quadspi.su ./Core/Src/robot_state.cyclo ./Core/Src/robot_state.d ./Core/Src/robot_state.o ./Core/Src/robot_state.su ./Core/Src/stm32h7xx_hal_msp.cyclo ./Core/Src/stm32h7xx_hal_msp.d ./Core/Src/stm32h7xx_hal_msp.o ./Core/Src/stm32h7xx_hal_msp.su ./Core/Src/stm32h7xx_it.cyclo ./Core/Src/stm32h7xx_it.d ./Core/Src/stm32h7xx_it.o ./Core/Src/stm32h7xx_it.su ./Core/Src/syscalls.cyclo ./Core/Src/syscalls.d ./Core/Src/syscalls.o ./Core/Src/syscalls.su ./Core/Src/sysmem.cyclo ./Core/Src/sysmem.d ./Core/Src/sysmem.o ./Core/Src/sysmem.su ./Core/Src/system_stm32h7xx.cyclo ./Core/Src/system_stm32h7xx.d ./Core/Src/system_stm32h7xx.o ./Core/Src/system_stm32h7xx.su ./Core/Src/tim.cyclo ./Core/Src/tim.d ./Core/Src/tim.o ./Core/Src/tim.su ./Core/Src/usart.cyclo ./Core/Src/usart.d ./Core/Src/usart.o ./Core/Src/usart.su
+
+.PHONY: clean-Core-2f-Src
+
diff --git a/Debug/Core/Src/syscalls.cyclo b/Debug/Core/Src/syscalls.cyclo
new file mode 100644
index 0000000..f16427a
--- /dev/null
+++ b/Debug/Core/Src/syscalls.cyclo
@@ -0,0 +1,18 @@
+../Core/Src/syscalls.c:44:6:initialise_monitor_handles	1
+../Core/Src/syscalls.c:48:5:_getpid	1
+../Core/Src/syscalls.c:53:5:_kill	1
+../Core/Src/syscalls.c:59:6:_exit	1
+../Core/Src/syscalls.c:65:27:_read	2
+../Core/Src/syscalls.c:77:27:_write	2
+../Core/Src/syscalls.c:88:5:_close	1
+../Core/Src/syscalls.c:94:5:_fstat	1
+../Core/Src/syscalls.c:100:5:_isatty	1
+../Core/Src/syscalls.c:105:5:_lseek	1
+../Core/Src/syscalls.c:110:5:_open	1
+../Core/Src/syscalls.c:116:5:_wait	1
+../Core/Src/syscalls.c:122:5:_unlink	1
+../Core/Src/syscalls.c:128:5:_times	1
+../Core/Src/syscalls.c:133:5:_stat	1
+../Core/Src/syscalls.c:139:5:_link	1
+../Core/Src/syscalls.c:145:5:_fork	1
+../Core/Src/syscalls.c:151:5:_execve	1
diff --git a/Debug/Core/Src/syscalls.d b/Debug/Core/Src/syscalls.d
new file mode 100644
index 0000000..8667c70
--- /dev/null
+++ b/Debug/Core/Src/syscalls.d
@@ -0,0 +1 @@
+Core/Src/syscalls.o: ../Core/Src/syscalls.c
diff --git a/Debug/Core/Src/syscalls.o b/Debug/Core/Src/syscalls.o
new file mode 100644
index 0000000..b557207
Binary files /dev/null and b/Debug/Core/Src/syscalls.o differ
diff --git a/Debug/Core/Src/syscalls.su b/Debug/Core/Src/syscalls.su
new file mode 100644
index 0000000..a7d10e5
--- /dev/null
+++ b/Debug/Core/Src/syscalls.su
@@ -0,0 +1,18 @@
+../Core/Src/syscalls.c:44:6:initialise_monitor_handles	4	static
+../Core/Src/syscalls.c:48:5:_getpid	4	static
+../Core/Src/syscalls.c:53:5:_kill	16	static
+../Core/Src/syscalls.c:59:6:_exit	16	static
+../Core/Src/syscalls.c:65:27:_read	32	static
+../Core/Src/syscalls.c:77:27:_write	32	static
+../Core/Src/syscalls.c:88:5:_close	16	static
+../Core/Src/syscalls.c:94:5:_fstat	16	static
+../Core/Src/syscalls.c:100:5:_isatty	16	static
+../Core/Src/syscalls.c:105:5:_lseek	24	static
+../Core/Src/syscalls.c:110:5:_open	12	static
+../Core/Src/syscalls.c:116:5:_wait	16	static
+../Core/Src/syscalls.c:122:5:_unlink	16	static
+../Core/Src/syscalls.c:128:5:_times	16	static
+../Core/Src/syscalls.c:133:5:_stat	16	static
+../Core/Src/syscalls.c:139:5:_link	16	static
+../Core/Src/syscalls.c:145:5:_fork	8	static
+../Core/Src/syscalls.c:151:5:_execve	24	static
diff --git a/Debug/Core/Src/sysmem.cyclo b/Debug/Core/Src/sysmem.cyclo
new file mode 100644
index 0000000..0090c10
--- /dev/null
+++ b/Debug/Core/Src/sysmem.cyclo
@@ -0,0 +1 @@
+../Core/Src/sysmem.c:53:7:_sbrk	3
diff --git a/Debug/Core/Src/sysmem.d b/Debug/Core/Src/sysmem.d
new file mode 100644
index 0000000..74fecf9
--- /dev/null
+++ b/Debug/Core/Src/sysmem.d
@@ -0,0 +1 @@
+Core/Src/sysmem.o: ../Core/Src/sysmem.c
diff --git a/Debug/Core/Src/sysmem.o b/Debug/Core/Src/sysmem.o
new file mode 100644
index 0000000..954299e
Binary files /dev/null and b/Debug/Core/Src/sysmem.o differ
diff --git a/Debug/Core/Src/sysmem.su b/Debug/Core/Src/sysmem.su
new file mode 100644
index 0000000..12d5f17
--- /dev/null
+++ b/Debug/Core/Src/sysmem.su
@@ -0,0 +1 @@
+../Core/Src/sysmem.c:53:7:_sbrk	32	static
diff --git a/Debug/Core/Src/system_stm32h7xx.cyclo b/Debug/Core/Src/system_stm32h7xx.cyclo
new file mode 100644
index 0000000..d64aa9e
--- /dev/null
+++ b/Debug/Core/Src/system_stm32h7xx.cyclo
@@ -0,0 +1,2 @@
+../Core/Src/system_stm32h7xx.c:176:6:SystemInit	4
+../Core/Src/system_stm32h7xx.c:341:6:SystemCoreClockUpdate	10
diff --git a/Debug/Core/Src/system_stm32h7xx.d b/Debug/Core/Src/system_stm32h7xx.d
new file mode 100644
index 0000000..7056779
--- /dev/null
+++ b/Debug/Core/Src/system_stm32h7xx.d
@@ -0,0 +1,79 @@
+Core/Src/system_stm32h7xx.o: ../Core/Src/system_stm32h7xx.c \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Core/Src/system_stm32h7xx.o b/Debug/Core/Src/system_stm32h7xx.o
new file mode 100644
index 0000000..13e43ce
Binary files /dev/null and b/Debug/Core/Src/system_stm32h7xx.o differ
diff --git a/Debug/Core/Src/system_stm32h7xx.su b/Debug/Core/Src/system_stm32h7xx.su
new file mode 100644
index 0000000..2c78745
--- /dev/null
+++ b/Debug/Core/Src/system_stm32h7xx.su
@@ -0,0 +1,2 @@
+../Core/Src/system_stm32h7xx.c:176:6:SystemInit	4	static
+../Core/Src/system_stm32h7xx.c:341:6:SystemCoreClockUpdate	48	static
diff --git a/Debug/Core/Src/tim.cyclo b/Debug/Core/Src/tim.cyclo
new file mode 100644
index 0000000..5d08187
--- /dev/null
+++ b/Debug/Core/Src/tim.cyclo
@@ -0,0 +1,4 @@
+../Core/Src/tim.c:31:6:MX_TIM1_Init	4
+../Core/Src/tim.c:73:6:MX_TIM8_Init	4
+../Core/Src/tim.c:115:6:HAL_TIM_Base_MspInit	3
+../Core/Src/tim.c:150:6:HAL_TIM_Base_MspDeInit	3
diff --git a/Debug/Core/Src/tim.d b/Debug/Core/Src/tim.d
new file mode 100644
index 0000000..d98f03b
--- /dev/null
+++ b/Debug/Core/Src/tim.d
@@ -0,0 +1,81 @@
+Core/Src/tim.o: ../Core/Src/tim.c ../Core/Inc/tim.h ../Core/Inc/main.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
+../Core/Inc/tim.h:
+../Core/Inc/main.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Core/Src/tim.o b/Debug/Core/Src/tim.o
new file mode 100644
index 0000000..44e2360
Binary files /dev/null and b/Debug/Core/Src/tim.o differ
diff --git a/Debug/Core/Src/tim.su b/Debug/Core/Src/tim.su
new file mode 100644
index 0000000..514faca
--- /dev/null
+++ b/Debug/Core/Src/tim.su
@@ -0,0 +1,4 @@
+../Core/Src/tim.c:31:6:MX_TIM1_Init	40	static
+../Core/Src/tim.c:73:6:MX_TIM8_Init	40	static
+../Core/Src/tim.c:115:6:HAL_TIM_Base_MspInit	24	static
+../Core/Src/tim.c:150:6:HAL_TIM_Base_MspDeInit	16	static
diff --git a/Debug/Core/Src/usart.cyclo b/Debug/Core/Src/usart.cyclo
new file mode 100644
index 0000000..00073b0
--- /dev/null
+++ b/Debug/Core/Src/usart.cyclo
@@ -0,0 +1,10 @@
+../Core/Src/usart.c:45:6:MX_LPUART1_UART_Init	5
+../Core/Src/usart.c:90:6:MX_UART4_Init	5
+../Core/Src/usart.c:133:6:MX_UART5_Init	5
+../Core/Src/usart.c:178:6:MX_UART7_Init	5
+../Core/Src/usart.c:224:6:MX_USART1_UART_Init	5
+../Core/Src/usart.c:270:6:MX_USART2_UART_Init	5
+../Core/Src/usart.c:319:6:MX_USART3_UART_Init	5
+../Core/Src/usart.c:365:6:MX_USART6_UART_Init	5
+../Core/Src/usart.c:409:6:HAL_UART_MspInit	24
+../Core/Src/usart.c:901:6:HAL_UART_MspDeInit	9
diff --git a/Debug/Core/Src/usart.d b/Debug/Core/Src/usart.d
new file mode 100644
index 0000000..5865d8c
--- /dev/null
+++ b/Debug/Core/Src/usart.d
@@ -0,0 +1,81 @@
+Core/Src/usart.o: ../Core/Src/usart.c ../Core/Inc/usart.h \
+ ../Core/Inc/main.h ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
+../Core/Inc/usart.h:
+../Core/Inc/main.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Core/Src/usart.o b/Debug/Core/Src/usart.o
new file mode 100644
index 0000000..b723f55
Binary files /dev/null and b/Debug/Core/Src/usart.o differ
diff --git a/Debug/Core/Src/usart.su b/Debug/Core/Src/usart.su
new file mode 100644
index 0000000..40bef9f
--- /dev/null
+++ b/Debug/Core/Src/usart.su
@@ -0,0 +1,10 @@
+../Core/Src/usart.c:45:6:MX_LPUART1_UART_Init	8	static
+../Core/Src/usart.c:90:6:MX_UART4_Init	8	static
+../Core/Src/usart.c:133:6:MX_UART5_Init	8	static
+../Core/Src/usart.c:178:6:MX_UART7_Init	8	static
+../Core/Src/usart.c:224:6:MX_USART1_UART_Init	8	static
+../Core/Src/usart.c:270:6:MX_USART2_UART_Init	8	static
+../Core/Src/usart.c:319:6:MX_USART3_UART_Init	8	static
+../Core/Src/usart.c:365:6:MX_USART6_UART_Init	8	static
+../Core/Src/usart.c:409:6:HAL_UART_MspInit	304	static
+../Core/Src/usart.c:901:6:HAL_UART_MspDeInit	16	static
diff --git a/Debug/Core/Startup/startup_stm32h743vgtx.d b/Debug/Core/Startup/startup_stm32h743vgtx.d
new file mode 100644
index 0000000..610cf8d
--- /dev/null
+++ b/Debug/Core/Startup/startup_stm32h743vgtx.d
@@ -0,0 +1,2 @@
+Core/Startup/startup_stm32h743vgtx.o: \
+ ../Core/Startup/startup_stm32h743vgtx.s
diff --git a/Debug/Core/Startup/startup_stm32h743vgtx.o b/Debug/Core/Startup/startup_stm32h743vgtx.o
new file mode 100644
index 0000000..19a371c
Binary files /dev/null and b/Debug/Core/Startup/startup_stm32h743vgtx.o differ
diff --git a/Debug/Core/Startup/subdir.mk b/Debug/Core/Startup/subdir.mk
new file mode 100644
index 0000000..816ddf1
--- /dev/null
+++ b/Debug/Core/Startup/subdir.mk
@@ -0,0 +1,27 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+# Toolchain: GNU Tools for STM32 (12.3.rel1)
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables 
+S_SRCS += \
+../Core/Startup/startup_stm32h743vgtx.s 
+
+OBJS += \
+./Core/Startup/startup_stm32h743vgtx.o 
+
+S_DEPS += \
+./Core/Startup/startup_stm32h743vgtx.d 
+
+
+# Each subdirectory must supply rules for building sources it contributes
+Core/Startup/%.o: ../Core/Startup/%.s Core/Startup/subdir.mk
+	arm-none-eabi-gcc -mcpu=cortex-m7 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" "$<"
+
+clean: clean-Core-2f-Startup
+
+clean-Core-2f-Startup:
+	-$(RM) ./Core/Startup/startup_stm32h743vgtx.d ./Core/Startup/startup_stm32h743vgtx.o
+
+.PHONY: clean-Core-2f-Startup
+
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.cyclo b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.cyclo
new file mode 100644
index 0000000..0a62d50
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.cyclo
@@ -0,0 +1,48 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:134:19:HAL_Init	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:187:19:HAL_DeInit	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:228:13:HAL_MspInit	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:239:13:HAL_MspDeInit	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:262:26:HAL_InitTick	4
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:327:13:HAL_IncTick	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:338:17:HAL_GetTick	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:347:10:HAL_GetTickPrio	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:356:19:HAL_SetTickFreq	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:389:21:HAL_GetTickFreq	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:405:13:HAL_Delay	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:431:13:HAL_SuspendTick	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:447:13:HAL_ResumeTick	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:457:10:HAL_GetHalVersion	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:466:10:HAL_GetREVID	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:475:10:HAL_GetDEVID	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:484:10:HAL_GetUIDw0	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:493:10:HAL_GetUIDw1	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:502:10:HAL_GetUIDw2	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:521:6:HAL_SYSCFG_VREFBUF_VoltageScalingConfig	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:537:6:HAL_SYSCFG_VREFBUF_HighImpedanceConfig	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:549:6:HAL_SYSCFG_VREFBUF_TrimmingConfig	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:561:19:HAL_SYSCFG_EnableVREFBUF	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:587:6:HAL_SYSCFG_DisableVREFBUF	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:601:6:HAL_SYSCFG_ETHInterfaceSelect	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:631:6:HAL_SYSCFG_AnalogSwitchConfig	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:649:6:HAL_SYSCFG_EnableBOOST	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:661:6:HAL_SYSCFG_DisableBOOST	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:677:6:HAL_SYSCFG_CM7BootAddConfig	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:776:6:HAL_EnableCompensationCell	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:787:6:HAL_DisableCompensationCell	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:800:6:HAL_SYSCFG_EnableIOSpeedOptimize	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:816:6:HAL_SYSCFG_DisableIOSpeedOptimize	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:833:6:HAL_SYSCFG_CompensationCodeSelect	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:850:6:HAL_SYSCFG_CompensationCodeConfig	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:912:6:HAL_DBGMCU_EnableDBGSleepMode	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:921:6:HAL_DBGMCU_DisableDBGSleepMode	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:931:6:HAL_DBGMCU_EnableDBGStopMode	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:940:6:HAL_DBGMCU_DisableDBGStopMode	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:949:6:HAL_DBGMCU_EnableDBGStandbyMode	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:958:6:HAL_DBGMCU_DisableDBGStandbyMode	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:1065:6:HAL_SetFMCMemorySwappingConfig	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:1077:10:HAL_GetFMCMemorySwappingConfig	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:1094:6:HAL_EXTI_EdgeConfig	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:1120:6:HAL_EXTI_GenerateSWInterrupt	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:1135:6:HAL_EXTI_D1_ClearFlag	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:1170:6:HAL_EXTI_D1_EventInputConfig	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:1264:6:HAL_EXTI_D3_EventInputConfig	3
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.d
new file mode 100644
index 0000000..4440457
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.d
@@ -0,0 +1,80 @@
+Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o: \
+ ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o
new file mode 100644
index 0000000..250810a
Binary files /dev/null and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o differ
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.su b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.su
new file mode 100644
index 0000000..e5fd6b6
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.su
@@ -0,0 +1,48 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:134:19:HAL_Init	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:187:19:HAL_DeInit	8	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:228:13:HAL_MspInit	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:239:13:HAL_MspDeInit	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:262:26:HAL_InitTick	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:327:13:HAL_IncTick	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:338:17:HAL_GetTick	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:347:10:HAL_GetTickPrio	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:356:19:HAL_SetTickFreq	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:389:21:HAL_GetTickFreq	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:405:13:HAL_Delay	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:431:13:HAL_SuspendTick	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:447:13:HAL_ResumeTick	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:457:10:HAL_GetHalVersion	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:466:10:HAL_GetREVID	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:475:10:HAL_GetDEVID	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:484:10:HAL_GetUIDw0	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:493:10:HAL_GetUIDw1	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:502:10:HAL_GetUIDw2	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:521:6:HAL_SYSCFG_VREFBUF_VoltageScalingConfig	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:537:6:HAL_SYSCFG_VREFBUF_HighImpedanceConfig	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:549:6:HAL_SYSCFG_VREFBUF_TrimmingConfig	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:561:19:HAL_SYSCFG_EnableVREFBUF	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:587:6:HAL_SYSCFG_DisableVREFBUF	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:601:6:HAL_SYSCFG_ETHInterfaceSelect	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:631:6:HAL_SYSCFG_AnalogSwitchConfig	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:649:6:HAL_SYSCFG_EnableBOOST	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:661:6:HAL_SYSCFG_DisableBOOST	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:677:6:HAL_SYSCFG_CM7BootAddConfig	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:776:6:HAL_EnableCompensationCell	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:787:6:HAL_DisableCompensationCell	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:800:6:HAL_SYSCFG_EnableIOSpeedOptimize	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:816:6:HAL_SYSCFG_DisableIOSpeedOptimize	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:833:6:HAL_SYSCFG_CompensationCodeSelect	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:850:6:HAL_SYSCFG_CompensationCodeConfig	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:912:6:HAL_DBGMCU_EnableDBGSleepMode	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:921:6:HAL_DBGMCU_DisableDBGSleepMode	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:931:6:HAL_DBGMCU_EnableDBGStopMode	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:940:6:HAL_DBGMCU_DisableDBGStopMode	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:949:6:HAL_DBGMCU_EnableDBGStandbyMode	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:958:6:HAL_DBGMCU_DisableDBGStandbyMode	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:1065:6:HAL_SetFMCMemorySwappingConfig	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:1077:10:HAL_GetFMCMemorySwappingConfig	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:1094:6:HAL_EXTI_EdgeConfig	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:1120:6:HAL_EXTI_GenerateSWInterrupt	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:1135:6:HAL_EXTI_D1_ClearFlag	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:1170:6:HAL_EXTI_D1_EventInputConfig	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:1264:6:HAL_EXTI_D3_EventInputConfig	32	static
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.cyclo b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.cyclo
new file mode 100644
index 0000000..a4aa1f4
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.cyclo
@@ -0,0 +1,66 @@
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:2663:22:LL_ADC_SetCommonClock	1
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:2731:22:LL_ADC_SetCommonPathInternalCh	1
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:2753:26:LL_ADC_GetCommonPathInternalCh	1
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:3379:22:LL_ADC_SetOffset	1
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:3510:22:LL_ADC_SetDataRightShift	1
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:3552:22:LL_ADC_SetOffsetSignedSaturation	1
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:3928:26:LL_ADC_REG_IsTriggerSourceSWStart	2
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:4255:22:LL_ADC_REG_SetSequencerRanks	1
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:4419:22:LL_ADC_REG_SetDataTransferMode	1
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:4715:26:LL_ADC_INJ_IsTriggerSourceSWStart	2
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:5409:22:LL_ADC_SetChannelSamplingTime	1
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:5555:22:LL_ADC_SetChannelSingleDiff	1
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:5774:22:LL_ADC_SetAnalogWDMonitChannels	1
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:6601:26:LL_ADC_GetMultimode	1
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:6692:26:LL_ADC_GetMultiDMATransfer	1
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:6818:22:LL_ADC_DisableDeepPowerDown	1
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:6832:26:LL_ADC_IsDeepPowerDownEnabled	2
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:6851:22:LL_ADC_EnableInternalRegulator	1
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:6881:26:LL_ADC_IsInternalRegulatorEnabled	2
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:6902:22:LL_ADC_Enable	1
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:6922:22:LL_ADC_Disable	1
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:6941:26:LL_ADC_IsEnabled	2
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:6952:26:LL_ADC_IsDisableOngoing	2
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:7037:22:LL_ADC_REG_StartConversion	1
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:7057:22:LL_ADC_REG_StopConversion	1
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:7073:26:LL_ADC_REG_IsConversionOngoing	2
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:7252:22:LL_ADC_INJ_StopConversion	1
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:7268:26:LL_ADC_INJ_IsConversionOngoing	2
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:7685:22:LL_ADC_ClearFlag_AWD1	1
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:7696:22:LL_ADC_ClearFlag_AWD2	1
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:7707:22:LL_ADC_ClearFlag_AWD3	1
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:8078:22:LL_ADC_EnableIT_AWD1	1
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:8089:22:LL_ADC_EnableIT_AWD2	1
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:8100:22:LL_ADC_EnableIT_AWD3	1
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:8199:22:LL_ADC_DisableIT_AWD1	1
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:8210:22:LL_ADC_DisableIT_AWD2	1
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:8221:22:LL_ADC_DisableIT_AWD3	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c:407:19:HAL_ADC_Init	23
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c:842:19:HAL_ADC_DeInit	11
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c:1095:13:HAL_ADC_MspInit	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c:1112:13:HAL_ADC_MspDeInit	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c:1397:19:HAL_ADC_Start	18
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c:1518:19:HAL_ADC_Stop	4
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c:1572:19:HAL_ADC_PollForConversion	28
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c:1735:19:HAL_ADC_PollForEvent	15
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c:1884:19:HAL_ADC_Start_IT	22
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c:2059:19:HAL_ADC_Stop_IT	4
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c:2112:19:HAL_ADC_Start_DMA	13
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c:2259:19:HAL_ADC_Stop_DMA	7
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c:2344:10:HAL_ADC_GetValue	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c:2361:6:HAL_ADC_IRQHandler	58
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c:2721:13:HAL_ADC_ConvCpltCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c:2736:13:HAL_ADC_ConvHalfCpltCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c:2751:13:HAL_ADC_LevelOutOfWindowCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c:2773:13:HAL_ADC_ErrorCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c:2819:19:HAL_ADC_ConfigChannel	56
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c:3135:19:HAL_ADC_AnalogWDGConfig	49
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c:3497:10:HAL_ADC_GetState	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c:3511:10:HAL_ADC_GetError	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c:3541:19:ADC_ConversionStop	19
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c:3675:19:ADC_Enable	12
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c:3754:19:ADC_Disable	7
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c:3816:6:ADC_DMAConvCplt	9
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c:3894:6:ADC_DMAHalfConvCplt	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c:3912:6:ADC_DMAError	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c:3938:6:ADC_ConfigureBoostMode	33
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.d
new file mode 100644
index 0000000..9985aa4
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.d
@@ -0,0 +1,80 @@
+Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.o: \
+ ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.o
new file mode 100644
index 0000000..f319c96
Binary files /dev/null and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.o differ
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.su b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.su
new file mode 100644
index 0000000..964bf48
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.su
@@ -0,0 +1,66 @@
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:2663:22:LL_ADC_SetCommonClock	16	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:2731:22:LL_ADC_SetCommonPathInternalCh	16	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:2753:26:LL_ADC_GetCommonPathInternalCh	16	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:3379:22:LL_ADC_SetOffset	32	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:3510:22:LL_ADC_SetDataRightShift	24	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:3552:22:LL_ADC_SetOffsetSignedSaturation	32	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:3928:26:LL_ADC_REG_IsTriggerSourceSWStart	16	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:4255:22:LL_ADC_REG_SetSequencerRanks	32	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:4419:22:LL_ADC_REG_SetDataTransferMode	16	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:4715:26:LL_ADC_INJ_IsTriggerSourceSWStart	16	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:5409:22:LL_ADC_SetChannelSamplingTime	32	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:5555:22:LL_ADC_SetChannelSingleDiff	24	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:5774:22:LL_ADC_SetAnalogWDMonitChannels	32	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:6601:26:LL_ADC_GetMultimode	16	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:6692:26:LL_ADC_GetMultiDMATransfer	16	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:6818:22:LL_ADC_DisableDeepPowerDown	16	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:6832:26:LL_ADC_IsDeepPowerDownEnabled	16	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:6851:22:LL_ADC_EnableInternalRegulator	16	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:6881:26:LL_ADC_IsInternalRegulatorEnabled	16	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:6902:22:LL_ADC_Enable	16	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:6922:22:LL_ADC_Disable	16	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:6941:26:LL_ADC_IsEnabled	16	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:6952:26:LL_ADC_IsDisableOngoing	16	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:7037:22:LL_ADC_REG_StartConversion	16	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:7057:22:LL_ADC_REG_StopConversion	16	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:7073:26:LL_ADC_REG_IsConversionOngoing	16	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:7252:22:LL_ADC_INJ_StopConversion	16	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:7268:26:LL_ADC_INJ_IsConversionOngoing	16	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:7685:22:LL_ADC_ClearFlag_AWD1	16	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:7696:22:LL_ADC_ClearFlag_AWD2	16	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:7707:22:LL_ADC_ClearFlag_AWD3	16	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:8078:22:LL_ADC_EnableIT_AWD1	16	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:8089:22:LL_ADC_EnableIT_AWD2	16	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:8100:22:LL_ADC_EnableIT_AWD3	16	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:8199:22:LL_ADC_DisableIT_AWD1	16	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:8210:22:LL_ADC_DisableIT_AWD2	16	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:8221:22:LL_ADC_DisableIT_AWD3	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c:407:19:HAL_ADC_Init	48	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c:842:19:HAL_ADC_DeInit	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c:1095:13:HAL_ADC_MspInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c:1112:13:HAL_ADC_MspDeInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c:1397:19:HAL_ADC_Start	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c:1518:19:HAL_ADC_Stop	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c:1572:19:HAL_ADC_PollForConversion	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c:1735:19:HAL_ADC_PollForEvent	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c:1884:19:HAL_ADC_Start_IT	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c:2059:19:HAL_ADC_Stop_IT	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c:2112:19:HAL_ADC_Start_DMA	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c:2259:19:HAL_ADC_Stop_DMA	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c:2344:10:HAL_ADC_GetValue	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c:2361:6:HAL_ADC_IRQHandler	48	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c:2721:13:HAL_ADC_ConvCpltCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c:2736:13:HAL_ADC_ConvHalfCpltCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c:2751:13:HAL_ADC_LevelOutOfWindowCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c:2773:13:HAL_ADC_ErrorCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c:2819:19:HAL_ADC_ConfigChannel	144	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c:3135:19:HAL_ADC_AnalogWDGConfig	88	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c:3497:10:HAL_ADC_GetState	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c:3511:10:HAL_ADC_GetError	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c:3541:19:ADC_ConversionStop	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c:3675:19:ADC_Enable	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c:3754:19:ADC_Disable	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c:3816:6:ADC_DMAConvCplt	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c:3894:6:ADC_DMAHalfConvCplt	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c:3912:6:ADC_DMAError	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c:3938:6:ADC_ConfigureBoostMode	24	static
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.cyclo b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.cyclo
new file mode 100644
index 0000000..7c4843c
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.cyclo
@@ -0,0 +1,56 @@
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:2731:22:LL_ADC_SetCommonPathInternalCh	1
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:2753:26:LL_ADC_GetCommonPathInternalCh	1
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:2859:22:LL_ADC_SetCalibrationOffsetFactor	1
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:2890:26:LL_ADC_GetCalibrationOffsetFactor	1
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:2925:22:LL_ADC_SetCalibrationLinearFactor	3
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:2965:26:LL_ADC_GetCalibrationLinearFactor	3
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:3379:22:LL_ADC_SetOffset	1
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:3461:26:LL_ADC_GetOffsetChannel	1
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:3552:22:LL_ADC_SetOffsetSignedSaturation	1
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:3928:26:LL_ADC_REG_IsTriggerSourceSWStart	2
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:4715:26:LL_ADC_INJ_IsTriggerSourceSWStart	2
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:5017:26:LL_ADC_INJ_GetTrigAuto	1
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:5063:22:LL_ADC_INJ_SetQueueMode	1
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:5409:22:LL_ADC_SetChannelSamplingTime	1
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:5555:22:LL_ADC_SetChannelSingleDiff	1
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:6601:26:LL_ADC_GetMultimode	1
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:6795:22:LL_ADC_EnableDeepPowerDown	1
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:6870:22:LL_ADC_DisableInternalRegulator	1
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:6941:26:LL_ADC_IsEnabled	2
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:6990:22:LL_ADC_StartCalibration	1
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:7006:26:LL_ADC_IsCalibrationOnGoing	2
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:7037:22:LL_ADC_REG_StartConversion	1
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:7057:22:LL_ADC_REG_StopConversion	1
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:7073:26:LL_ADC_REG_IsConversionOngoing	2
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:7232:22:LL_ADC_INJ_StartConversion	1
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:7268:26:LL_ADC_INJ_IsConversionOngoing	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c:126:19:HAL_ADCEx_Calibration_Start	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c:200:10:HAL_ADCEx_Calibration_GetValue	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c:216:19:HAL_ADCEx_LinearCalibration_GetValue	6
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c:263:19:HAL_ADCEx_Calibration_SetValue	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c:326:19:HAL_ADCEx_LinearCalibration_SetValue	11
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c:417:19:HAL_ADCEx_LinearCalibration_FactorLoad	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c:463:19:HAL_ADCEx_InjectedStart	18
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c:600:19:HAL_ADCEx_InjectedStop	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c:655:19:HAL_ADCEx_InjectedPollForConversion	24
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c:789:19:HAL_ADCEx_InjectedStart_IT	20
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c:950:19:HAL_ADCEx_InjectedStop_IT	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c:1019:19:HAL_ADCEx_MultiModeStart_DMA	13
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c:1156:19:HAL_ADCEx_MultiModeStop_DMA	14
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c:1280:10:HAL_ADCEx_MultiModeGetValue	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c:1326:10:HAL_ADCEx_InjectedGetValue	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c:1361:13:HAL_ADCEx_InjectedConvCpltCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c:1380:13:HAL_ADCEx_InjectedQueueOverflowCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c:1395:13:HAL_ADCEx_LevelOutOfWindow2Callback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c:1410:13:HAL_ADCEx_LevelOutOfWindow3Callback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c:1426:13:HAL_ADCEx_EndOfSamplingCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c:1443:19:HAL_ADCEx_RegularStop	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c:1501:19:HAL_ADCEx_RegularStop_IT	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c:1561:19:HAL_ADCEx_RegularStop_DMA	7
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c:1647:19:HAL_ADCEx_RegularMultiModeStop_DMA	16
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c:1831:19:HAL_ADCEx_InjectedConfigChannel	84
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c:2394:19:HAL_ADCEx_MultiModeConfigChannel	15
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c:2507:19:HAL_ADCEx_EnableInjectedQueue	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c:2548:19:HAL_ADCEx_DisableInjectedQueue	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c:2585:19:HAL_ADCEx_DisableVoltageRegulator	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c:2622:19:HAL_ADCEx_EnterADCDeepPowerDownMode	2
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.d
new file mode 100644
index 0000000..8f68207
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.d
@@ -0,0 +1,80 @@
+Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.o: \
+ ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.o
new file mode 100644
index 0000000..c1cc616
Binary files /dev/null and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.o differ
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.su b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.su
new file mode 100644
index 0000000..7b7651e
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.su
@@ -0,0 +1,56 @@
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:2731:22:LL_ADC_SetCommonPathInternalCh	16	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:2753:26:LL_ADC_GetCommonPathInternalCh	16	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:2859:22:LL_ADC_SetCalibrationOffsetFactor	24	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:2890:26:LL_ADC_GetCalibrationOffsetFactor	16	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:2925:22:LL_ADC_SetCalibrationLinearFactor	32	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:2965:26:LL_ADC_GetCalibrationLinearFactor	24	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:3379:22:LL_ADC_SetOffset	32	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:3461:26:LL_ADC_GetOffsetChannel	24	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:3552:22:LL_ADC_SetOffsetSignedSaturation	32	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:3928:26:LL_ADC_REG_IsTriggerSourceSWStart	16	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:4715:26:LL_ADC_INJ_IsTriggerSourceSWStart	16	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:5017:26:LL_ADC_INJ_GetTrigAuto	16	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:5063:22:LL_ADC_INJ_SetQueueMode	16	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:5409:22:LL_ADC_SetChannelSamplingTime	32	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:5555:22:LL_ADC_SetChannelSingleDiff	24	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:6601:26:LL_ADC_GetMultimode	16	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:6795:22:LL_ADC_EnableDeepPowerDown	16	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:6870:22:LL_ADC_DisableInternalRegulator	16	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:6941:26:LL_ADC_IsEnabled	16	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:6990:22:LL_ADC_StartCalibration	24	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:7006:26:LL_ADC_IsCalibrationOnGoing	16	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:7037:22:LL_ADC_REG_StartConversion	16	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:7057:22:LL_ADC_REG_StopConversion	16	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:7073:26:LL_ADC_REG_IsConversionOngoing	16	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:7232:22:LL_ADC_INJ_StartConversion	16	static
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:7268:26:LL_ADC_INJ_IsConversionOngoing	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c:126:19:HAL_ADCEx_Calibration_Start	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c:200:10:HAL_ADCEx_Calibration_GetValue	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c:216:19:HAL_ADCEx_LinearCalibration_GetValue	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c:263:19:HAL_ADCEx_Calibration_SetValue	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c:326:19:HAL_ADCEx_LinearCalibration_SetValue	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c:417:19:HAL_ADCEx_LinearCalibration_FactorLoad	56	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c:463:19:HAL_ADCEx_InjectedStart	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c:600:19:HAL_ADCEx_InjectedStop	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c:655:19:HAL_ADCEx_InjectedPollForConversion	48	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c:789:19:HAL_ADCEx_InjectedStart_IT	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c:950:19:HAL_ADCEx_InjectedStop_IT	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c:1019:19:HAL_ADCEx_MultiModeStart_DMA	136	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c:1156:19:HAL_ADCEx_MultiModeStop_DMA	136	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c:1280:10:HAL_ADCEx_MultiModeGetValue	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c:1326:10:HAL_ADCEx_InjectedGetValue	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c:1361:13:HAL_ADCEx_InjectedConvCpltCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c:1380:13:HAL_ADCEx_InjectedQueueOverflowCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c:1395:13:HAL_ADCEx_LevelOutOfWindow2Callback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c:1410:13:HAL_ADCEx_LevelOutOfWindow3Callback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c:1426:13:HAL_ADCEx_EndOfSamplingCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c:1443:19:HAL_ADCEx_RegularStop	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c:1501:19:HAL_ADCEx_RegularStop_IT	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c:1561:19:HAL_ADCEx_RegularStop_DMA	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c:1647:19:HAL_ADCEx_RegularMultiModeStop_DMA	128	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c:1831:19:HAL_ADCEx_InjectedConfigChannel	248	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c:2394:19:HAL_ADCEx_MultiModeConfigChannel	136	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c:2507:19:HAL_ADCEx_EnableInjectedQueue	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c:2548:19:HAL_ADCEx_DisableInjectedQueue	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c:2585:19:HAL_ADCEx_DisableVoltageRegulator	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c:2622:19:HAL_ADCEx_EnterADCDeepPowerDownMode	24	static
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.cyclo b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.cyclo
new file mode 100644
index 0000000..42fef06
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.cyclo
@@ -0,0 +1,35 @@
+../Drivers/CMSIS/Include/core_cm7.h:1871:22:__NVIC_SetPriorityGrouping	1
+../Drivers/CMSIS/Include/core_cm7.h:1890:26:__NVIC_GetPriorityGrouping	1
+../Drivers/CMSIS/Include/core_cm7.h:1902:22:__NVIC_EnableIRQ	2
+../Drivers/CMSIS/Include/core_cm7.h:1940:22:__NVIC_DisableIRQ	2
+../Drivers/CMSIS/Include/core_cm7.h:1959:26:__NVIC_GetPendingIRQ	2
+../Drivers/CMSIS/Include/core_cm7.h:1978:22:__NVIC_SetPendingIRQ	2
+../Drivers/CMSIS/Include/core_cm7.h:1993:22:__NVIC_ClearPendingIRQ	2
+../Drivers/CMSIS/Include/core_cm7.h:2010:26:__NVIC_GetActive	2
+../Drivers/CMSIS/Include/core_cm7.h:2032:22:__NVIC_SetPriority	2
+../Drivers/CMSIS/Include/core_cm7.h:2054:26:__NVIC_GetPriority	2
+../Drivers/CMSIS/Include/core_cm7.h:2079:26:NVIC_EncodePriority	2
+../Drivers/CMSIS/Include/core_cm7.h:2106:22:NVIC_DecodePriority	2
+../Drivers/CMSIS/Include/core_cm7.h:2156:34:__NVIC_SystemReset	1
+../Drivers/CMSIS/Include/core_cm7.h:2618:26:SysTick_Config	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:142:6:HAL_NVIC_SetPriorityGrouping	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:164:6:HAL_NVIC_SetPriority	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:186:6:HAL_NVIC_EnableIRQ	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:202:6:HAL_NVIC_DisableIRQ	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:215:6:HAL_NVIC_SystemReset	0
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:228:10:HAL_SYSTICK_Config	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:256:6:HAL_MPU_Disable	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:279:6:HAL_MPU_Enable	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:296:6:HAL_MPU_EnableRegion	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:312:6:HAL_MPU_DisableRegion	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:330:6:HAL_MPU_ConfigRegion	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:368:10:HAL_NVIC_GetPriorityGrouping	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:395:6:HAL_NVIC_GetPriority	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:410:6:HAL_NVIC_SetPendingIRQ	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:428:10:HAL_NVIC_GetPendingIRQ	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:444:6:HAL_NVIC_ClearPendingIRQ	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:461:10:HAL_NVIC_GetActive	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:478:6:HAL_SYSTICK_CLKSourceConfig	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:496:6:HAL_SYSTICK_IRQHandler	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:505:13:HAL_SYSTICK_Callback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:536:10:HAL_GetCurrentCPUID	1
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.d
new file mode 100644
index 0000000..27867e2
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.d
@@ -0,0 +1,80 @@
+Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o: \
+ ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o
new file mode 100644
index 0000000..23bf442
Binary files /dev/null and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o differ
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.su b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.su
new file mode 100644
index 0000000..054acac
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.su
@@ -0,0 +1,35 @@
+../Drivers/CMSIS/Include/core_cm7.h:1871:22:__NVIC_SetPriorityGrouping	24	static
+../Drivers/CMSIS/Include/core_cm7.h:1890:26:__NVIC_GetPriorityGrouping	4	static
+../Drivers/CMSIS/Include/core_cm7.h:1902:22:__NVIC_EnableIRQ	16	static,ignoring_inline_asm
+../Drivers/CMSIS/Include/core_cm7.h:1940:22:__NVIC_DisableIRQ	16	static,ignoring_inline_asm
+../Drivers/CMSIS/Include/core_cm7.h:1959:26:__NVIC_GetPendingIRQ	16	static
+../Drivers/CMSIS/Include/core_cm7.h:1978:22:__NVIC_SetPendingIRQ	16	static
+../Drivers/CMSIS/Include/core_cm7.h:1993:22:__NVIC_ClearPendingIRQ	16	static
+../Drivers/CMSIS/Include/core_cm7.h:2010:26:__NVIC_GetActive	16	static
+../Drivers/CMSIS/Include/core_cm7.h:2032:22:__NVIC_SetPriority	16	static
+../Drivers/CMSIS/Include/core_cm7.h:2054:26:__NVIC_GetPriority	16	static
+../Drivers/CMSIS/Include/core_cm7.h:2079:26:NVIC_EncodePriority	40	static
+../Drivers/CMSIS/Include/core_cm7.h:2106:22:NVIC_DecodePriority	40	static
+../Drivers/CMSIS/Include/core_cm7.h:2156:34:__NVIC_SystemReset	4	static,ignoring_inline_asm
+../Drivers/CMSIS/Include/core_cm7.h:2618:26:SysTick_Config	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:142:6:HAL_NVIC_SetPriorityGrouping	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:164:6:HAL_NVIC_SetPriority	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:186:6:HAL_NVIC_EnableIRQ	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:202:6:HAL_NVIC_DisableIRQ	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:215:6:HAL_NVIC_SystemReset	8	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:228:10:HAL_SYSTICK_Config	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:256:6:HAL_MPU_Disable	4	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:279:6:HAL_MPU_Enable	16	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:296:6:HAL_MPU_EnableRegion	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:312:6:HAL_MPU_DisableRegion	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:330:6:HAL_MPU_ConfigRegion	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:368:10:HAL_NVIC_GetPriorityGrouping	8	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:395:6:HAL_NVIC_GetPriority	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:410:6:HAL_NVIC_SetPendingIRQ	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:428:10:HAL_NVIC_GetPendingIRQ	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:444:6:HAL_NVIC_ClearPendingIRQ	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:461:10:HAL_NVIC_GetActive	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:478:6:HAL_SYSTICK_CLKSourceConfig	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:496:6:HAL_SYSTICK_IRQHandler	8	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:505:13:HAL_SYSTICK_Callback	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:536:10:HAL_GetCurrentCPUID	4	static
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.cyclo b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.cyclo
new file mode 100644
index 0000000..bda50d6
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.cyclo
@@ -0,0 +1,17 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:216:19:HAL_DMA_Init	97
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:468:19:HAL_DMA_DeInit	47
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:625:19:HAL_DMA_Start	36
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:681:19:HAL_DMA_Start_IT	82
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:781:19:HAL_DMA_Abort	106
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:897:19:HAL_DMA_Abort_IT	79
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:981:19:HAL_DMA_PollForTransfer	112
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:1208:6:HAL_DMA_IRQHandler	222
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:1578:19:HAL_DMA_RegisterCallback	10
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:1645:19:HAL_DMA_UnRegisterCallback	11
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:1736:22:HAL_DMA_GetState	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:1747:10:HAL_DMA_GetError	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:1773:13:DMA_SetConfig	55
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:1860:17:DMA_CalcBaseAndBitshift	19
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:1896:26:DMA_CheckFifoParam	15
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:1990:13:DMA_CalcDMAMUXChannelBaseAndMask	12
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:2025:13:DMA_CalcDMAMUXRequestGenBaseAndMask	12
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.d
new file mode 100644
index 0000000..484150e
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.d
@@ -0,0 +1,80 @@
+Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o: \
+ ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o
new file mode 100644
index 0000000..f053b82
Binary files /dev/null and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o differ
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.su b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.su
new file mode 100644
index 0000000..8daecf5
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.su
@@ -0,0 +1,17 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:216:19:HAL_DMA_Init	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:468:19:HAL_DMA_DeInit	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:625:19:HAL_DMA_Start	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:681:19:HAL_DMA_Start_IT	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:781:19:HAL_DMA_Abort	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:897:19:HAL_DMA_Abort_IT	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:981:19:HAL_DMA_PollForTransfer	48	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:1208:6:HAL_DMA_IRQHandler	48	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:1578:19:HAL_DMA_RegisterCallback	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:1645:19:HAL_DMA_UnRegisterCallback	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:1736:22:HAL_DMA_GetState	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:1747:10:HAL_DMA_GetError	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:1773:13:DMA_SetConfig	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:1860:17:DMA_CalcBaseAndBitshift	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:1896:26:DMA_CheckFifoParam	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:1990:13:DMA_CalcDMAMUXChannelBaseAndMask	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:2025:13:DMA_CalcDMAMUXRequestGenBaseAndMask	24	static
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.cyclo b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.cyclo
new file mode 100644
index 0000000..4ddefe6
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.cyclo
@@ -0,0 +1,9 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c:120:19:HAL_DMAEx_MultiBufferStart	63
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c:217:19:HAL_DMAEx_MultiBufferStart_IT	111
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c:357:19:HAL_DMAEx_ChangeMemory	20
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c:396:19:HAL_DMAEx_ConfigMuxSync	19
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c:464:19:HAL_DMAEx_ConfigMuxRequestGenerator	20
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c:530:19:HAL_DMAEx_EnableMuxRequestGenerator	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c:556:19:HAL_DMAEx_DisableMuxRequestGenerator	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c:582:6:HAL_DMAEx_MUX_IRQHandler	6
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c:648:13:DMA_MultiBufferSetConfig	20
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.d
new file mode 100644
index 0000000..c44b6c9
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.d
@@ -0,0 +1,80 @@
+Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o: \
+ ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o
new file mode 100644
index 0000000..94b3a8c
Binary files /dev/null and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o differ
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.su b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.su
new file mode 100644
index 0000000..b27c6e9
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.su
@@ -0,0 +1,9 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c:120:19:HAL_DMAEx_MultiBufferStart	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c:217:19:HAL_DMAEx_MultiBufferStart_IT	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c:357:19:HAL_DMAEx_ChangeMemory	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c:396:19:HAL_DMAEx_ConfigMuxSync	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c:464:19:HAL_DMAEx_ConfigMuxRequestGenerator	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c:530:19:HAL_DMAEx_EnableMuxRequestGenerator	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c:556:19:HAL_DMAEx_DisableMuxRequestGenerator	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c:582:6:HAL_DMAEx_MUX_IRQHandler	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c:648:13:DMA_MultiBufferSetConfig	24	static
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.cyclo b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.cyclo
new file mode 100644
index 0000000..210fbac
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.cyclo
@@ -0,0 +1,56 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:308:19:HAL_ETH_Init	7
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:434:19:HAL_ETH_DeInit	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:467:13:HAL_ETH_MspInit	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:482:13:HAL_ETH_MspDeInit	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:717:19:HAL_ETH_Start	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:763:19:HAL_ETH_Start_IT	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:819:19:HAL_ETH_Stop	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:858:19:HAL_ETH_Stop_IT	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:919:19:HAL_ETH_Transmit	10
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:994:19:HAL_ETH_Transmit_IT	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:1040:19:HAL_ETH_ReadData	14
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:1152:13:ETH_UpdateDescriptor	9
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:1232:19:HAL_ETH_RegisterRxAllocateCallback	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:1253:19:HAL_ETH_UnRegisterRxAllocateCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:1266:13:HAL_ETH_RxAllocateCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:1283:13:HAL_ETH_RxLinkCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:1302:19:HAL_ETH_RegisterRxLinkCallback	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:1322:19:HAL_ETH_UnRegisterRxLinkCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:1337:19:HAL_ETH_GetRxDataErrorCode	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:1352:19:HAL_ETH_RegisterTxFreeCallback	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:1372:19:HAL_ETH_UnRegisterTxFreeCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:1385:13:HAL_ETH_TxFreeCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:1400:19:HAL_ETH_ReleaseTxPacket	8
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:1858:6:HAL_ETH_IRQHandler	13
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2044:13:HAL_ETH_TxCpltCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2059:13:HAL_ETH_RxCpltCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2074:13:HAL_ETH_ErrorCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2089:13:HAL_ETH_PMTCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2104:13:HAL_ETH_EEECallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2119:13:HAL_ETH_WakeUpCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2137:19:HAL_ETH_ReadPHYRegister	4
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2192:19:HAL_ETH_WritePHYRegister	4
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2264:19:HAL_ETH_GetMACConfig	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2336:19:HAL_ETH_GetDMAConfig	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2370:19:HAL_ETH_SetMACConfig	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2397:19:HAL_ETH_SetDMAConfig	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2422:6:HAL_ETH_SetMDIOClockRange	6
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2480:19:HAL_ETH_SetMACFilterConfig	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2514:19:HAL_ETH_GetMACFilterConfig	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2551:19:HAL_ETH_SetSourceMACAddrMatch	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2587:19:HAL_ETH_SetHashTable	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2609:6:HAL_ETH_SetRxVLANIdentifier	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2631:6:HAL_ETH_EnterPowerDownMode	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2653:6:HAL_ETH_ExitPowerDownMode	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2677:19:HAL_ETH_SetWakeUpFilter	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2726:22:HAL_ETH_GetState	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2737:10:HAL_ETH_GetError	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2748:10:HAL_ETH_GetDMAError	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2759:10:HAL_ETH_GetMACError	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2770:10:HAL_ETH_GetMACWakeUpSource	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2787:13:ETH_SetMACConfig	8
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2864:13:ETH_SetDMAConfig	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2905:13:ETH_MACDMAConfig	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2978:13:ETH_DMATxDescListInit	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:3016:13:ETH_DMARxDescListInit	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:3062:17:ETH_Prepare_Tx_Descriptors	26
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.d
new file mode 100644
index 0000000..0c2cacb
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.d
@@ -0,0 +1,80 @@
+Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o: \
+ ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o
new file mode 100644
index 0000000..cc5e5bd
Binary files /dev/null and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o differ
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.su b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.su
new file mode 100644
index 0000000..133d2c4
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.su
@@ -0,0 +1,56 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:308:19:HAL_ETH_Init	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:434:19:HAL_ETH_DeInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:467:13:HAL_ETH_MspInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:482:13:HAL_ETH_MspDeInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:717:19:HAL_ETH_Start	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:763:19:HAL_ETH_Start_IT	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:819:19:HAL_ETH_Stop	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:858:19:HAL_ETH_Stop_IT	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:919:19:HAL_ETH_Transmit	32	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:994:19:HAL_ETH_Transmit_IT	16	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:1040:19:HAL_ETH_ReadData	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:1152:13:ETH_UpdateDescriptor	40	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:1232:19:HAL_ETH_RegisterRxAllocateCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:1253:19:HAL_ETH_UnRegisterRxAllocateCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:1266:13:HAL_ETH_RxAllocateCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:1283:13:HAL_ETH_RxLinkCallback	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:1302:19:HAL_ETH_RegisterRxLinkCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:1322:19:HAL_ETH_UnRegisterRxLinkCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:1337:19:HAL_ETH_GetRxDataErrorCode	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:1352:19:HAL_ETH_RegisterTxFreeCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:1372:19:HAL_ETH_UnRegisterTxFreeCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:1385:13:HAL_ETH_TxFreeCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:1400:19:HAL_ETH_ReleaseTxPacket	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:1858:6:HAL_ETH_IRQHandler	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2044:13:HAL_ETH_TxCpltCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2059:13:HAL_ETH_RxCpltCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2074:13:HAL_ETH_ErrorCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2089:13:HAL_ETH_PMTCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2104:13:HAL_ETH_EEECallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2119:13:HAL_ETH_WakeUpCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2137:19:HAL_ETH_ReadPHYRegister	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2192:19:HAL_ETH_WritePHYRegister	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2264:19:HAL_ETH_GetMACConfig	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2336:19:HAL_ETH_GetDMAConfig	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2370:19:HAL_ETH_SetMACConfig	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2397:19:HAL_ETH_SetDMAConfig	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2422:6:HAL_ETH_SetMDIOClockRange	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2480:19:HAL_ETH_SetMACFilterConfig	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2514:19:HAL_ETH_GetMACFilterConfig	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2551:19:HAL_ETH_SetSourceMACAddrMatch	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2587:19:HAL_ETH_SetHashTable	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2609:6:HAL_ETH_SetRxVLANIdentifier	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2631:6:HAL_ETH_EnterPowerDownMode	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2653:6:HAL_ETH_ExitPowerDownMode	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2677:19:HAL_ETH_SetWakeUpFilter	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2726:22:HAL_ETH_GetState	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2737:10:HAL_ETH_GetError	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2748:10:HAL_ETH_GetDMAError	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2759:10:HAL_ETH_GetMACError	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2770:10:HAL_ETH_GetMACWakeUpSource	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2787:13:ETH_SetMACConfig	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2864:13:ETH_SetDMAConfig	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2905:13:ETH_MACDMAConfig	152	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2978:13:ETH_DMATxDescListInit	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:3016:13:ETH_DMARxDescListInit	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:3062:17:ETH_Prepare_Tx_Descriptors	72	static,ignoring_inline_asm
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.cyclo b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.cyclo
new file mode 100644
index 0000000..a8310ed
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.cyclo
@@ -0,0 +1,20 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:97:6:HAL_ETHEx_EnableARPOffload	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:108:6:HAL_ETHEx_DisableARPOffload	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:120:6:HAL_ETHEx_SetARPAddressMatch	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:138:19:HAL_ETHEx_SetL4FilterConfig	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:187:19:HAL_ETHEx_GetL4FilterConfig	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:238:19:HAL_ETHEx_SetL3FilterConfig	6
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:332:19:HAL_ETHEx_GetL3FilterConfig	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:390:6:HAL_ETHEx_EnableL3L4Filtering	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:402:6:HAL_ETHEx_DisableL3L4Filtering	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:416:19:HAL_ETHEx_GetRxVLANConfig	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:451:19:HAL_ETHEx_SetRxVLANConfig	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:479:6:HAL_ETHEx_SetVLANHashTable	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:495:19:HAL_ETHEx_GetTxVLANConfig	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:530:19:HAL_ETHEx_SetTxVLANConfig	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:561:6:HAL_ETHEx_SetTxVLANIdentifier	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:579:6:HAL_ETHEx_EnableVLANProcessing	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:591:6:HAL_ETHEx_DisableVLANProcessing	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:605:6:HAL_ETHEx_EnterLPIMode	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:623:6:HAL_ETHEx_ExitLPIMode	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:638:10:HAL_ETHEx_GetMACLPIEvent	1
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.d
new file mode 100644
index 0000000..f875103
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.d
@@ -0,0 +1,80 @@
+Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o: \
+ ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o
new file mode 100644
index 0000000..98820eb
Binary files /dev/null and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o differ
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.su b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.su
new file mode 100644
index 0000000..5b61bc3
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.su
@@ -0,0 +1,20 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:97:6:HAL_ETHEx_EnableARPOffload	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:108:6:HAL_ETHEx_DisableARPOffload	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:120:6:HAL_ETHEx_SetARPAddressMatch	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:138:19:HAL_ETHEx_SetL4FilterConfig	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:187:19:HAL_ETHEx_GetL4FilterConfig	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:238:19:HAL_ETHEx_SetL3FilterConfig	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:332:19:HAL_ETHEx_GetL3FilterConfig	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:390:6:HAL_ETHEx_EnableL3L4Filtering	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:402:6:HAL_ETHEx_DisableL3L4Filtering	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:416:19:HAL_ETHEx_GetRxVLANConfig	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:451:19:HAL_ETHEx_SetRxVLANConfig	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:479:6:HAL_ETHEx_SetVLANHashTable	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:495:19:HAL_ETHEx_GetTxVLANConfig	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:530:19:HAL_ETHEx_SetTxVLANConfig	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:561:6:HAL_ETHEx_SetTxVLANIdentifier	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:579:6:HAL_ETHEx_EnableVLANProcessing	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:591:6:HAL_ETHEx_DisableVLANProcessing	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:605:6:HAL_ETHEx_EnterLPIMode	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:623:6:HAL_ETHEx_ExitLPIMode	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:638:10:HAL_ETHEx_GetMACLPIEvent	16	static
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.cyclo b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.cyclo
new file mode 100644
index 0000000..cc87712
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.cyclo
@@ -0,0 +1,9 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c:170:19:HAL_EXTI_SetConfigLine	12
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c:374:19:HAL_EXTI_GetConfigLine	12
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c:512:19:HAL_EXTI_ClearConfigLine	6
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c:612:19:HAL_EXTI_RegisterCallback	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c:644:19:HAL_EXTI_GetHandle	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c:685:6:HAL_EXTI_IRQHandler	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c:737:10:HAL_EXTI_GetPending	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c:788:6:HAL_EXTI_ClearPending	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c:830:6:HAL_EXTI_GenerateSWI	1
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.d
new file mode 100644
index 0000000..e0bca9c
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.d
@@ -0,0 +1,80 @@
+Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o: \
+ ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o
new file mode 100644
index 0000000..c9272b2
Binary files /dev/null and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o differ
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.su b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.su
new file mode 100644
index 0000000..5a82b02
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.su
@@ -0,0 +1,9 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c:170:19:HAL_EXTI_SetConfigLine	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c:374:19:HAL_EXTI_GetConfigLine	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c:512:19:HAL_EXTI_ClearConfigLine	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c:612:19:HAL_EXTI_RegisterCallback	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c:644:19:HAL_EXTI_GetHandle	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c:685:6:HAL_EXTI_IRQHandler	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c:737:10:HAL_EXTI_GetPending	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c:788:6:HAL_EXTI_ClearPending	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c:830:6:HAL_EXTI_GenerateSWI	32	static
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.cyclo b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.cyclo
new file mode 100644
index 0000000..c36218e
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.cyclo
@@ -0,0 +1,100 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:292:19:HAL_FDCAN_Init	22
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:600:19:HAL_FDCAN_DeInit	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:646:13:HAL_FDCAN_MspInit	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:661:13:HAL_FDCAN_MspDeInit	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:676:19:HAL_FDCAN_EnterPowerDownMode	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:711:19:HAL_FDCAN_ExitPowerDownMode	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:1682:19:HAL_FDCAN_ConfigClockCalibration	4
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:1753:10:HAL_FDCAN_GetClockCalibrationState	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:1767:19:HAL_FDCAN_ResetClockCalibrationState	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:1803:10:HAL_FDCAN_GetClockCalibrationCounter	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:1834:19:HAL_FDCAN_ConfigFilter	6
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:1946:19:HAL_FDCAN_ConfigGlobalFilter	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:1986:19:HAL_FDCAN_ConfigExtendedIdMask	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2020:19:HAL_FDCAN_ConfigRxFifoOverwrite	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2063:19:HAL_FDCAN_ConfigFifoWatermark	4
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2113:19:HAL_FDCAN_ConfigRamWatchdog	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2143:19:HAL_FDCAN_ConfigTimestampCounter	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2173:19:HAL_FDCAN_EnableTimestampCounter	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2201:19:HAL_FDCAN_DisableTimestampCounter	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2226:10:HAL_FDCAN_GetTimestampCounter	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2237:19:HAL_FDCAN_ResetTimestampCounter	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2268:19:HAL_FDCAN_ConfigTimeoutCounter	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2299:19:HAL_FDCAN_EnableTimeoutCounter	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2324:19:HAL_FDCAN_DisableTimeoutCounter	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2349:10:HAL_FDCAN_GetTimeoutCounter	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2360:19:HAL_FDCAN_ResetTimeoutCounter	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2390:19:HAL_FDCAN_ConfigTxDelayCompensation	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2420:19:HAL_FDCAN_EnableTxDelayCompensation	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2445:19:HAL_FDCAN_DisableTxDelayCompensation	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2471:19:HAL_FDCAN_EnableISOMode	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2497:19:HAL_FDCAN_DisableISOMode	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2523:19:HAL_FDCAN_EnableEdgeFiltering	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2549:19:HAL_FDCAN_DisableEdgeFiltering	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2613:19:HAL_FDCAN_Start	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2644:19:HAL_FDCAN_Stop	6
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2726:19:HAL_FDCAN_AddMessageToTxFifoQ	4
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2805:19:HAL_FDCAN_AddMessageToTxBuffer	7
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2874:19:HAL_FDCAN_EnableTxBufferRequest	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2901:10:HAL_FDCAN_GetLatestTxFifoQRequestBuffer	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2915:19:HAL_FDCAN_AbortTxRequest	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2944:19:HAL_FDCAN_GetRxMessage	18
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3140:19:HAL_FDCAN_GetTxEvent	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3235:19:HAL_FDCAN_GetHighPriorityMessageStatus	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3254:19:HAL_FDCAN_GetProtocolStatus	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3286:19:HAL_FDCAN_GetErrorCounters	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3314:10:HAL_FDCAN_IsRxBufferMessageAvailable	6
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3351:10:HAL_FDCAN_IsTxBufferMessagePending	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3371:10:HAL_FDCAN_GetRxFifoFillLevel	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3398:10:HAL_FDCAN_GetTxFifoFreeLevel	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3416:10:HAL_FDCAN_IsRestrictedOperationMode	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3432:19:HAL_FDCAN_ExitRestrictedOperationMode	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3499:19:HAL_FDCAN_TT_ConfigOperation	10
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3679:19:HAL_FDCAN_TT_ConfigReferenceMessage	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3730:19:HAL_FDCAN_TT_ConfigTrigger	11
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3840:19:HAL_FDCAN_TT_SetGlobalTime	7
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3914:19:HAL_FDCAN_TT_SetClockSynchronization	7
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3990:19:HAL_FDCAN_TT_ConfigStopWatch	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4051:19:HAL_FDCAN_TT_ConfigRegisterTimeMark	11
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4172:19:HAL_FDCAN_TT_EnableRegisterTimeMarkPulse	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4222:19:HAL_FDCAN_TT_DisableRegisterTimeMarkPulse	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4272:19:HAL_FDCAN_TT_EnableTriggerTimeMarkPulse	6
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4333:19:HAL_FDCAN_TT_DisableTriggerTimeMarkPulse	6
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4394:19:HAL_FDCAN_TT_EnableHardwareGapControl	6
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4455:19:HAL_FDCAN_TT_DisableHardwareGapControl	6
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4518:19:HAL_FDCAN_TT_EnableTimeMarkGapControl	6
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4579:19:HAL_FDCAN_TT_DisableTimeMarkGapControl	6
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4640:19:HAL_FDCAN_TT_SetNextIsGap	7
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4710:19:HAL_FDCAN_TT_SetEndOfGap	7
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4784:19:HAL_FDCAN_TT_ConfigExternalSyncPhase	4
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4825:19:HAL_FDCAN_TT_EnableExternalSynchronization	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4875:19:HAL_FDCAN_TT_DisableExternalSynchronization	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4926:19:HAL_FDCAN_TT_GetOperationStatus	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4991:19:HAL_FDCAN_ConfigInterruptLines	4
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5033:19:HAL_FDCAN_TT_ConfigInterruptLines	4
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5080:19:HAL_FDCAN_ActivateNotification	7
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5144:19:HAL_FDCAN_DeactivateNotification	7
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5203:19:HAL_FDCAN_TT_ActivateNotification	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5253:19:HAL_FDCAN_TT_DeactivateNotification	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5299:6:HAL_FDCAN_IRQHandler	33
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5729:13:HAL_FDCAN_ClockCalibrationCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5748:13:HAL_FDCAN_TxEventFifoCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5767:13:HAL_FDCAN_RxFifo0Callback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5786:13:HAL_FDCAN_RxFifo1Callback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5803:13:HAL_FDCAN_TxFifoEmptyCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5821:13:HAL_FDCAN_TxBufferCompleteCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5840:13:HAL_FDCAN_TxBufferAbortCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5857:13:HAL_FDCAN_RxBufferNewMessageCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5873:13:HAL_FDCAN_TimestampWraparoundCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5889:13:HAL_FDCAN_TimeoutOccurredCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5905:13:HAL_FDCAN_HighPriorityMessageCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5921:13:HAL_FDCAN_ErrorCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5939:13:HAL_FDCAN_ErrorStatusCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5958:13:HAL_FDCAN_TT_ScheduleSyncCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5977:13:HAL_FDCAN_TT_TimeMarkCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5999:13:HAL_FDCAN_TT_StopWatchCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:6019:13:HAL_FDCAN_TT_GlobalTimeCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:6055:24:HAL_FDCAN_GetState	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:6067:10:HAL_FDCAN_GetError	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:6091:26:FDCAN_CalcultateRamBlockAddresses	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:6194:13:FDCAN_CopyMessageToRAM	3
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.d
new file mode 100644
index 0000000..2a5bb49
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.d
@@ -0,0 +1,80 @@
+Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o: \
+ ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o
new file mode 100644
index 0000000..851d2a6
Binary files /dev/null and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o differ
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.su b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.su
new file mode 100644
index 0000000..5f78b5e
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.su
@@ -0,0 +1,100 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:292:19:HAL_FDCAN_Init	104	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:600:19:HAL_FDCAN_DeInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:646:13:HAL_FDCAN_MspInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:661:13:HAL_FDCAN_MspDeInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:676:19:HAL_FDCAN_EnterPowerDownMode	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:711:19:HAL_FDCAN_ExitPowerDownMode	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:1682:19:HAL_FDCAN_ConfigClockCalibration	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:1753:10:HAL_FDCAN_GetClockCalibrationState	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:1767:19:HAL_FDCAN_ResetClockCalibrationState	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:1803:10:HAL_FDCAN_GetClockCalibrationCounter	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:1834:19:HAL_FDCAN_ConfigFilter	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:1946:19:HAL_FDCAN_ConfigGlobalFilter	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:1986:19:HAL_FDCAN_ConfigExtendedIdMask	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2020:19:HAL_FDCAN_ConfigRxFifoOverwrite	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2063:19:HAL_FDCAN_ConfigFifoWatermark	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2113:19:HAL_FDCAN_ConfigRamWatchdog	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2143:19:HAL_FDCAN_ConfigTimestampCounter	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2173:19:HAL_FDCAN_EnableTimestampCounter	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2201:19:HAL_FDCAN_DisableTimestampCounter	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2226:10:HAL_FDCAN_GetTimestampCounter	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2237:19:HAL_FDCAN_ResetTimestampCounter	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2268:19:HAL_FDCAN_ConfigTimeoutCounter	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2299:19:HAL_FDCAN_EnableTimeoutCounter	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2324:19:HAL_FDCAN_DisableTimeoutCounter	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2349:10:HAL_FDCAN_GetTimeoutCounter	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2360:19:HAL_FDCAN_ResetTimeoutCounter	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2390:19:HAL_FDCAN_ConfigTxDelayCompensation	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2420:19:HAL_FDCAN_EnableTxDelayCompensation	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2445:19:HAL_FDCAN_DisableTxDelayCompensation	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2471:19:HAL_FDCAN_EnableISOMode	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2497:19:HAL_FDCAN_DisableISOMode	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2523:19:HAL_FDCAN_EnableEdgeFiltering	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2549:19:HAL_FDCAN_DisableEdgeFiltering	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2613:19:HAL_FDCAN_Start	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2644:19:HAL_FDCAN_Stop	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2726:19:HAL_FDCAN_AddMessageToTxFifoQ	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2805:19:HAL_FDCAN_AddMessageToTxBuffer	56	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2874:19:HAL_FDCAN_EnableTxBufferRequest	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2901:10:HAL_FDCAN_GetLatestTxFifoQRequestBuffer	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2915:19:HAL_FDCAN_AbortTxRequest	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:2944:19:HAL_FDCAN_GetRxMessage	48	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3140:19:HAL_FDCAN_GetTxEvent	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3235:19:HAL_FDCAN_GetHighPriorityMessageStatus	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3254:19:HAL_FDCAN_GetProtocolStatus	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3286:19:HAL_FDCAN_GetErrorCounters	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3314:10:HAL_FDCAN_IsRxBufferMessageAvailable	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3351:10:HAL_FDCAN_IsTxBufferMessagePending	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3371:10:HAL_FDCAN_GetRxFifoFillLevel	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3398:10:HAL_FDCAN_GetTxFifoFreeLevel	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3416:10:HAL_FDCAN_IsRestrictedOperationMode	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3432:19:HAL_FDCAN_ExitRestrictedOperationMode	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3499:19:HAL_FDCAN_TT_ConfigOperation	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3679:19:HAL_FDCAN_TT_ConfigReferenceMessage	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3730:19:HAL_FDCAN_TT_ConfigTrigger	48	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3840:19:HAL_FDCAN_TT_SetGlobalTime	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3914:19:HAL_FDCAN_TT_SetClockSynchronization	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:3990:19:HAL_FDCAN_TT_ConfigStopWatch	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4051:19:HAL_FDCAN_TT_ConfigRegisterTimeMark	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4172:19:HAL_FDCAN_TT_EnableRegisterTimeMarkPulse	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4222:19:HAL_FDCAN_TT_DisableRegisterTimeMarkPulse	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4272:19:HAL_FDCAN_TT_EnableTriggerTimeMarkPulse	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4333:19:HAL_FDCAN_TT_DisableTriggerTimeMarkPulse	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4394:19:HAL_FDCAN_TT_EnableHardwareGapControl	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4455:19:HAL_FDCAN_TT_DisableHardwareGapControl	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4518:19:HAL_FDCAN_TT_EnableTimeMarkGapControl	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4579:19:HAL_FDCAN_TT_DisableTimeMarkGapControl	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4640:19:HAL_FDCAN_TT_SetNextIsGap	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4710:19:HAL_FDCAN_TT_SetEndOfGap	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4784:19:HAL_FDCAN_TT_ConfigExternalSyncPhase	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4825:19:HAL_FDCAN_TT_EnableExternalSynchronization	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4875:19:HAL_FDCAN_TT_DisableExternalSynchronization	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4926:19:HAL_FDCAN_TT_GetOperationStatus	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:4991:19:HAL_FDCAN_ConfigInterruptLines	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5033:19:HAL_FDCAN_TT_ConfigInterruptLines	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5080:19:HAL_FDCAN_ActivateNotification	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5144:19:HAL_FDCAN_DeactivateNotification	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5203:19:HAL_FDCAN_TT_ActivateNotification	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5253:19:HAL_FDCAN_TT_DeactivateNotification	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5299:6:HAL_FDCAN_IRQHandler	96	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5729:13:HAL_FDCAN_ClockCalibrationCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5748:13:HAL_FDCAN_TxEventFifoCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5767:13:HAL_FDCAN_RxFifo0Callback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5786:13:HAL_FDCAN_RxFifo1Callback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5803:13:HAL_FDCAN_TxFifoEmptyCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5821:13:HAL_FDCAN_TxBufferCompleteCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5840:13:HAL_FDCAN_TxBufferAbortCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5857:13:HAL_FDCAN_RxBufferNewMessageCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5873:13:HAL_FDCAN_TimestampWraparoundCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5889:13:HAL_FDCAN_TimeoutOccurredCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5905:13:HAL_FDCAN_HighPriorityMessageCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5921:13:HAL_FDCAN_ErrorCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5939:13:HAL_FDCAN_ErrorStatusCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5958:13:HAL_FDCAN_TT_ScheduleSyncCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5977:13:HAL_FDCAN_TT_TimeMarkCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:5999:13:HAL_FDCAN_TT_StopWatchCallback	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:6019:13:HAL_FDCAN_TT_GlobalTimeCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:6055:24:HAL_FDCAN_GetState	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:6067:10:HAL_FDCAN_GetError	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:6091:26:FDCAN_CalcultateRamBlockAddresses	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c:6194:13:FDCAN_CopyMessageToRAM	40	static
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.cyclo b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.cyclo
new file mode 100644
index 0000000..2b86ec2
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.cyclo
@@ -0,0 +1,14 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c:154:19:HAL_FLASH_Program	10
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c:319:19:HAL_FLASH_Program_IT	9
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c:475:6:HAL_FLASH_IRQHandler	28
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c:810:13:HAL_FLASH_EndOfOperationCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c:828:13:HAL_FLASH_OperationErrorCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c:861:19:HAL_FLASH_Unlock	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c:898:19:HAL_FLASH_Lock	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c:927:19:HAL_FLASH_OB_Unlock	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c:949:19:HAL_FLASH_OB_Lock	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c:967:19:HAL_FLASH_OB_Launch	4
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c:1045:10:HAL_FLASH_GetError	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c:1070:19:FLASH_WaitForLastOperation	13
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c:1154:19:FLASH_OB_WaitForLastOperation	6
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c:1193:19:FLASH_CRC_WaitForLastOperation	10
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.d
new file mode 100644
index 0000000..aaf4e11
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.d
@@ -0,0 +1,80 @@
+Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o: \
+ ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o
new file mode 100644
index 0000000..6f308ec
Binary files /dev/null and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o differ
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.su b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.su
new file mode 100644
index 0000000..a47f78d
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.su
@@ -0,0 +1,14 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c:154:19:HAL_FLASH_Program	48	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c:319:19:HAL_FLASH_Program_IT	40	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c:475:6:HAL_FLASH_IRQHandler	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c:810:13:HAL_FLASH_EndOfOperationCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c:828:13:HAL_FLASH_OperationErrorCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c:861:19:HAL_FLASH_Unlock	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c:898:19:HAL_FLASH_Lock	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c:927:19:HAL_FLASH_OB_Unlock	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c:949:19:HAL_FLASH_OB_Lock	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c:967:19:HAL_FLASH_OB_Launch	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c:1045:10:HAL_FLASH_GetError	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c:1070:19:FLASH_WaitForLastOperation	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c:1154:19:FLASH_OB_WaitForLastOperation	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c:1193:19:FLASH_CRC_WaitForLastOperation	24	static
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.cyclo b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.cyclo
new file mode 100644
index 0000000..41139d7
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.cyclo
@@ -0,0 +1,28 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:186:19:HAL_FLASHEx_Erase	16
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:303:19:HAL_FLASHEx_Erase_IT	13
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:424:19:HAL_FLASHEx_OBProgram	13
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:567:6:HAL_FLASHEx_OBGetConfig	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:635:19:HAL_FLASHEx_Unlock_Bank1	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:657:19:HAL_FLASHEx_Lock_Bank1	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:669:19:HAL_FLASHEx_Unlock_Bank2	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:691:19:HAL_FLASHEx_Lock_Bank2	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:710:19:HAL_FLASHEx_ComputeCRC	9
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1103:13:FLASH_MassErase	4
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1180:6:FLASH_Erase_Sector	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1237:13:FLASH_OB_EnableWRP	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1272:13:FLASH_OB_DisableWRP	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1311:13:FLASH_OB_GetWRP	4
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1357:13:FLASH_OB_RDPConfig	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1374:17:FLASH_OB_GetRDP	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1430:13:FLASH_OB_UserConfig	10
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1618:17:FLASH_OB_GetUser	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1652:13:FLASH_OB_PCROPConfig	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1701:13:FLASH_OB_GetPCROP	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1737:13:FLASH_OB_BOR_LevelConfig	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1754:17:FLASH_OB_GetBOR	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1769:13:FLASH_OB_BootAddConfig	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1807:13:FLASH_OB_GetBootAdd	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1891:13:FLASH_OB_SecureAreaConfig	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1933:13:FLASH_OB_GetSecureArea	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1966:13:FLASH_CRC_AddSector	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1998:13:FLASH_CRC_SelectAddress	2
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.d
new file mode 100644
index 0000000..ae3857e
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.d
@@ -0,0 +1,80 @@
+Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o: \
+ ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o
new file mode 100644
index 0000000..f0f8da4
Binary files /dev/null and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o differ
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.su b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.su
new file mode 100644
index 0000000..1bb7f00
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.su
@@ -0,0 +1,28 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:186:19:HAL_FLASHEx_Erase	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:303:19:HAL_FLASHEx_Erase_IT	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:424:19:HAL_FLASHEx_OBProgram	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:567:6:HAL_FLASHEx_OBGetConfig	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:635:19:HAL_FLASHEx_Unlock_Bank1	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:657:19:HAL_FLASHEx_Lock_Bank1	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:669:19:HAL_FLASHEx_Unlock_Bank2	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:691:19:HAL_FLASHEx_Lock_Bank2	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:710:19:HAL_FLASHEx_ComputeCRC	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1103:13:FLASH_MassErase	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1180:6:FLASH_Erase_Sector	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1237:13:FLASH_OB_EnableWRP	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1272:13:FLASH_OB_DisableWRP	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1311:13:FLASH_OB_GetWRP	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1357:13:FLASH_OB_RDPConfig	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1374:17:FLASH_OB_GetRDP	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1430:13:FLASH_OB_UserConfig	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1618:17:FLASH_OB_GetUser	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1652:13:FLASH_OB_PCROPConfig	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1701:13:FLASH_OB_GetPCROP	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1737:13:FLASH_OB_BOR_LevelConfig	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1754:17:FLASH_OB_GetBOR	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1769:13:FLASH_OB_BootAddConfig	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1807:13:FLASH_OB_GetBootAdd	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1891:13:FLASH_OB_SecureAreaConfig	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1933:13:FLASH_OB_GetSecureArea	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1966:13:FLASH_CRC_AddSector	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1998:13:FLASH_CRC_SelectAddress	24	static
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.cyclo b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.cyclo
new file mode 100644
index 0000000..308d058
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.cyclo
@@ -0,0 +1,8 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c:165:6:HAL_GPIO_Init	22
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c:302:6:HAL_GPIO_DeInit	14
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c:389:15:HAL_GPIO_ReadPin	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c:423:6:HAL_GPIO_WritePin	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c:445:6:HAL_GPIO_TogglePin	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c:470:19:HAL_GPIO_LockPin	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c:505:6:HAL_GPIO_EXTI_IRQHandler	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c:528:13:HAL_GPIO_EXTI_Callback	1
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.d
new file mode 100644
index 0000000..14bc1f8
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.d
@@ -0,0 +1,80 @@
+Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o: \
+ ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o
new file mode 100644
index 0000000..a257dfe
Binary files /dev/null and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o differ
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.su b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.su
new file mode 100644
index 0000000..db18f74
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.su
@@ -0,0 +1,8 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c:165:6:HAL_GPIO_Init	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c:302:6:HAL_GPIO_DeInit	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c:389:15:HAL_GPIO_ReadPin	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c:423:6:HAL_GPIO_WritePin	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c:445:6:HAL_GPIO_TogglePin	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c:470:19:HAL_GPIO_LockPin	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c:505:6:HAL_GPIO_EXTI_IRQHandler	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c:528:13:HAL_GPIO_EXTI_Callback	16	static
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.cyclo b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.cyclo
new file mode 100644
index 0000000..5be35c7
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.cyclo
@@ -0,0 +1,11 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c:159:20:HAL_HSEM_Take	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c:196:19:HAL_HSEM_FastTake	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c:225:10:HAL_HSEM_IsSemTaken	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c:237:7:HAL_HSEM_Release	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c:258:6:HAL_HSEM_ReleaseAll	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c:290:7:HAL_HSEM_SetClearKey	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c:302:10:HAL_HSEM_GetClearKey	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c:329:6:HAL_HSEM_ActivateNotification	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c:353:6:HAL_HSEM_DeactivateNotification	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c:376:6:HAL_HSEM_IRQHandler	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c:422:13:HAL_HSEM_FreeCallback	1
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.d
new file mode 100644
index 0000000..794746e
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.d
@@ -0,0 +1,80 @@
+Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o: \
+ ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o
new file mode 100644
index 0000000..eb2bdf6
Binary files /dev/null and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o differ
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.su b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.su
new file mode 100644
index 0000000..654cf48
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.su
@@ -0,0 +1,11 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c:159:20:HAL_HSEM_Take	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c:196:19:HAL_HSEM_FastTake	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c:225:10:HAL_HSEM_IsSemTaken	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c:237:7:HAL_HSEM_Release	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c:258:6:HAL_HSEM_ReleaseAll	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c:290:7:HAL_HSEM_SetClearKey	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c:302:10:HAL_HSEM_GetClearKey	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c:329:6:HAL_HSEM_ActivateNotification	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c:353:6:HAL_HSEM_DeactivateNotification	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c:376:6:HAL_HSEM_IRQHandler	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c:422:13:HAL_HSEM_FreeCallback	16	static
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.cyclo b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.cyclo
new file mode 100644
index 0000000..d50df94
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.cyclo
@@ -0,0 +1,81 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:535:19:HAL_I2C_Init	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:650:19:HAL_I2C_DeInit	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:696:13:HAL_I2C_MspInit	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:712:13:HAL_I2C_MspDeInit	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:1119:19:HAL_I2C_Master_Transmit	13
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:1260:19:HAL_I2C_Master_Receive	12
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:1378:19:HAL_I2C_Slave_Transmit	17
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:1553:19:HAL_I2C_Slave_Receive	12
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:1683:19:HAL_I2C_Master_Transmit_IT	6
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:1773:19:HAL_I2C_Master_Receive_IT	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:1842:19:HAL_I2C_Slave_Transmit_IT	4
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:1906:19:HAL_I2C_Slave_Receive_IT	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:1958:19:HAL_I2C_Master_Transmit_DMA	9
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:2121:19:HAL_I2C_Master_Receive_DMA	8
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:2266:19:HAL_I2C_Slave_Transmit_DMA	9
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:2402:19:HAL_I2C_Slave_Receive_DMA	7
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:2511:19:HAL_I2C_Mem_Write	15
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:2648:19:HAL_I2C_Mem_Read	15
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:2785:19:HAL_I2C_Mem_Write_IT	7
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:2873:19:HAL_I2C_Mem_Read_IT	7
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:2960:19:HAL_I2C_Mem_Write_DMA	10
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:3106:19:HAL_I2C_Mem_Read_DMA	10
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:3251:19:HAL_I2C_IsDeviceReady	14
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:3377:19:HAL_I2C_Master_Seq_Transmit_IT	14
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:3491:19:HAL_I2C_Master_Seq_Transmit_DMA	19
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:3688:19:HAL_I2C_Master_Seq_Receive_IT	9
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:3775:19:HAL_I2C_Master_Seq_Receive_DMA	12
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:3941:19:HAL_I2C_Slave_Seq_Transmit_IT	11
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4041:19:HAL_I2C_Slave_Seq_Transmit_DMA	17
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4225:19:HAL_I2C_Slave_Seq_Receive_IT	11
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4325:19:HAL_I2C_Slave_Seq_Receive_DMA	17
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4505:19:HAL_I2C_EnableListen_IT	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4529:19:HAL_I2C_DisableListen_IT	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4562:19:HAL_I2C_Master_Abort_IT	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4624:6:HAL_I2C_EV_IRQHandler	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4643:6:HAL_I2C_ER_IRQHandler	8
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4695:13:HAL_I2C_MasterTxCpltCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4711:13:HAL_I2C_MasterRxCpltCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4726:13:HAL_I2C_SlaveTxCpltCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4742:13:HAL_I2C_SlaveRxCpltCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4760:13:HAL_I2C_AddrCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4778:13:HAL_I2C_ListenCpltCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4794:13:HAL_I2C_MemTxCpltCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4810:13:HAL_I2C_MemRxCpltCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4826:13:HAL_I2C_ErrorCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4842:13:HAL_I2C_AbortCpltCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4877:22:HAL_I2C_GetState	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4889:21:HAL_I2C_GetMode	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4900:10:HAL_I2C_GetError	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4925:26:I2C_Master_ISR_IT	24
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:5076:26:I2C_Mem_ISR_IT	20
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:5219:26:I2C_Slave_ISR_IT	25
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:5359:26:I2C_Master_ISR_DMA	18
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:5499:26:I2C_Mem_ISR_DMA	18
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:5647:26:I2C_Slave_ISR_DMA	59
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:5791:26:I2C_RequestMemoryWrite	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:5846:26:I2C_RequestMemoryRead	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:5895:13:I2C_ITAddrCplt	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:5990:13:I2C_ITMasterSeqCplt	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6043:13:I2C_ITSlaveSeqCplt	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6117:13:I2C_ITMasterCplt	12
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6260:13:I2C_ITSlaveCplt	58
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6476:13:I2C_ITListenCplt	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6527:13:I2C_ITError	19
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6658:13:I2C_TreatErrorCallback	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6696:13:I2C_Flush_TXDR	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6717:13:I2C_DMAMasterTransmitCplt	4
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6768:13:I2C_DMASlaveTransmitCplt	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6797:13:I2C_DMAMasterReceiveCplt	4
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6848:13:I2C_DMASlaveReceiveCplt	19
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6877:13:I2C_DMAError	39
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6917:13:I2C_DMAAbort	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6947:26:I2C_WaitOnFlagUntilTimeout	7
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6987:26:I2C_WaitOnTXISFlagUntilTimeout	7
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:7028:26:I2C_WaitOnSTOPFlagUntilTimeout	6
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:7066:26:I2C_WaitOnRXNEFlagUntilTimeout	13
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:7143:26:I2C_IsErrorOccurred	17
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:7284:13:I2C_TransferConfig	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:7311:13:I2C_Enable_IRQ	15
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:7402:13:I2C_Disable_IRQ	9
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:7465:13:I2C_ConvertOtherXferOptions	3
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.d
new file mode 100644
index 0000000..8b662b0
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.d
@@ -0,0 +1,80 @@
+Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o: \
+ ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o
new file mode 100644
index 0000000..b84df25
Binary files /dev/null and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o differ
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.su b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.su
new file mode 100644
index 0000000..bedfd4c
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.su
@@ -0,0 +1,81 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:535:19:HAL_I2C_Init	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:650:19:HAL_I2C_DeInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:696:13:HAL_I2C_MspInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:712:13:HAL_I2C_MspDeInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:1119:19:HAL_I2C_Master_Transmit	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:1260:19:HAL_I2C_Master_Receive	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:1378:19:HAL_I2C_Slave_Transmit	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:1553:19:HAL_I2C_Slave_Receive	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:1683:19:HAL_I2C_Master_Transmit_IT	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:1773:19:HAL_I2C_Master_Receive_IT	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:1842:19:HAL_I2C_Slave_Transmit_IT	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:1906:19:HAL_I2C_Slave_Receive_IT	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:1958:19:HAL_I2C_Master_Transmit_DMA	48	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:2121:19:HAL_I2C_Master_Receive_DMA	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:2266:19:HAL_I2C_Slave_Transmit_DMA	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:2402:19:HAL_I2C_Slave_Receive_DMA	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:2511:19:HAL_I2C_Mem_Write	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:2648:19:HAL_I2C_Mem_Read	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:2785:19:HAL_I2C_Mem_Write_IT	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:2873:19:HAL_I2C_Mem_Read_IT	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:2960:19:HAL_I2C_Mem_Write_DMA	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:3106:19:HAL_I2C_Mem_Read_DMA	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:3251:19:HAL_I2C_IsDeviceReady	48	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:3377:19:HAL_I2C_Master_Seq_Transmit_IT	48	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:3491:19:HAL_I2C_Master_Seq_Transmit_DMA	48	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:3688:19:HAL_I2C_Master_Seq_Receive_IT	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:3775:19:HAL_I2C_Master_Seq_Receive_DMA	48	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:3941:19:HAL_I2C_Slave_Seq_Transmit_IT	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4041:19:HAL_I2C_Slave_Seq_Transmit_DMA	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4225:19:HAL_I2C_Slave_Seq_Receive_IT	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4325:19:HAL_I2C_Slave_Seq_Receive_DMA	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4505:19:HAL_I2C_EnableListen_IT	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4529:19:HAL_I2C_DisableListen_IT	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4562:19:HAL_I2C_Master_Abort_IT	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4624:6:HAL_I2C_EV_IRQHandler	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4643:6:HAL_I2C_ER_IRQHandler	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4695:13:HAL_I2C_MasterTxCpltCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4711:13:HAL_I2C_MasterRxCpltCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4726:13:HAL_I2C_SlaveTxCpltCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4742:13:HAL_I2C_SlaveRxCpltCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4760:13:HAL_I2C_AddrCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4778:13:HAL_I2C_ListenCpltCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4794:13:HAL_I2C_MemTxCpltCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4810:13:HAL_I2C_MemRxCpltCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4826:13:HAL_I2C_ErrorCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4842:13:HAL_I2C_AbortCpltCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4877:22:HAL_I2C_GetState	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4889:21:HAL_I2C_GetMode	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4900:10:HAL_I2C_GetError	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4925:26:I2C_Master_ISR_IT	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:5076:26:I2C_Mem_ISR_IT	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:5219:26:I2C_Slave_ISR_IT	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:5359:26:I2C_Master_ISR_DMA	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:5499:26:I2C_Mem_ISR_DMA	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:5647:26:I2C_Slave_ISR_DMA	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:5791:26:I2C_RequestMemoryWrite	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:5846:26:I2C_RequestMemoryRead	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:5895:13:I2C_ITAddrCplt	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:5990:13:I2C_ITMasterSeqCplt	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6043:13:I2C_ITSlaveSeqCplt	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6117:13:I2C_ITMasterCplt	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6260:13:I2C_ITSlaveCplt	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6476:13:I2C_ITListenCplt	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6527:13:I2C_ITError	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6658:13:I2C_TreatErrorCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6696:13:I2C_Flush_TXDR	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6717:13:I2C_DMAMasterTransmitCplt	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6768:13:I2C_DMASlaveTransmitCplt	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6797:13:I2C_DMAMasterReceiveCplt	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6848:13:I2C_DMASlaveReceiveCplt	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6877:13:I2C_DMAError	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6917:13:I2C_DMAAbort	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6947:26:I2C_WaitOnFlagUntilTimeout	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6987:26:I2C_WaitOnTXISFlagUntilTimeout	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:7028:26:I2C_WaitOnSTOPFlagUntilTimeout	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:7066:26:I2C_WaitOnRXNEFlagUntilTimeout	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:7143:26:I2C_IsErrorOccurred	48	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:7284:13:I2C_TransferConfig	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:7311:13:I2C_Enable_IRQ	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:7402:13:I2C_Disable_IRQ	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:7465:13:I2C_ConvertOtherXferOptions	16	static
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.cyclo b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.cyclo
new file mode 100644
index 0000000..a259241
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.cyclo
@@ -0,0 +1,6 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c:96:19:HAL_I2CEx_ConfigAnalogFilter	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c:140:19:HAL_I2CEx_ConfigDigitalFilter	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c:208:19:HAL_I2CEx_EnableWakeUp	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c:247:19:HAL_I2CEx_DisableWakeUp	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c:316:6:HAL_I2CEx_EnableFastModePlus	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c:347:6:HAL_I2CEx_DisableFastModePlus	1
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.d
new file mode 100644
index 0000000..5c31774
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.d
@@ -0,0 +1,80 @@
+Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o: \
+ ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o
new file mode 100644
index 0000000..3f0caa7
Binary files /dev/null and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o differ
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.su b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.su
new file mode 100644
index 0000000..f5125f3
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.su
@@ -0,0 +1,6 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c:96:19:HAL_I2CEx_ConfigAnalogFilter	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c:140:19:HAL_I2CEx_ConfigDigitalFilter	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c:208:19:HAL_I2CEx_EnableWakeUp	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c:247:19:HAL_I2CEx_DisableWakeUp	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c:316:6:HAL_I2CEx_EnableFastModePlus	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c:347:6:HAL_I2CEx_DisableFastModePlus	24	static
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.cyclo b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.cyclo
new file mode 100644
index 0000000..1af2ba1
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.cyclo
@@ -0,0 +1,21 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:218:19:HAL_MDMA_Init	4
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:294:19:HAL_MDMA_DeInit	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:347:19:HAL_MDMA_ConfigPostRequestMask	6
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:409:19:HAL_MDMA_RegisterCallback	10
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:474:19:HAL_MDMA_UnRegisterCallback	11
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:568:19:HAL_MDMA_LinkedList_CreateNode	13
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:711:19:HAL_MDMA_LinkedList_AddNode	18
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:844:19:HAL_MDMA_LinkedList_RemoveNode	16
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:957:19:HAL_MDMA_LinkedList_EnableCircularMode	7
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:1001:19:HAL_MDMA_LinkedList_DisableCircularMode	7
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:1072:19:HAL_MDMA_Start	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:1132:19:HAL_MDMA_Start_IT	8
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:1215:19:HAL_MDMA_Abort	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:1280:19:HAL_MDMA_Abort_IT	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:1315:19:HAL_MDMA_PollForTransfer	20
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:1462:19:HAL_MDMA_GenerateSWRequest	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:1504:6:HAL_MDMA_IRQHandler	28
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:1722:23:HAL_MDMA_GetState	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:1733:10:HAL_MDMA_GetError	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:1760:13:MDMA_SetConfig	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:1814:13:MDMA_Init	5
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.d
new file mode 100644
index 0000000..f6674f0
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.d
@@ -0,0 +1,80 @@
+Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o: \
+ ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o
new file mode 100644
index 0000000..e109cbe
Binary files /dev/null and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o differ
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.su b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.su
new file mode 100644
index 0000000..5e80aff
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.su
@@ -0,0 +1,21 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:218:19:HAL_MDMA_Init	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:294:19:HAL_MDMA_DeInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:347:19:HAL_MDMA_ConfigPostRequestMask	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:409:19:HAL_MDMA_RegisterCallback	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:474:19:HAL_MDMA_UnRegisterCallback	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:568:19:HAL_MDMA_LinkedList_CreateNode	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:711:19:HAL_MDMA_LinkedList_AddNode	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:844:19:HAL_MDMA_LinkedList_RemoveNode	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:957:19:HAL_MDMA_LinkedList_EnableCircularMode	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:1001:19:HAL_MDMA_LinkedList_DisableCircularMode	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:1072:19:HAL_MDMA_Start	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:1132:19:HAL_MDMA_Start_IT	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:1215:19:HAL_MDMA_Abort	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:1280:19:HAL_MDMA_Abort_IT	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:1315:19:HAL_MDMA_PollForTransfer	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:1462:19:HAL_MDMA_GenerateSWRequest	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:1504:6:HAL_MDMA_IRQHandler	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:1722:23:HAL_MDMA_GetState	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:1733:10:HAL_MDMA_GetError	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:1760:13:MDMA_SetConfig	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:1814:13:MDMA_Init	24	static
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.cyclo b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.cyclo
new file mode 100644
index 0000000..5e025ed
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.cyclo
@@ -0,0 +1,17 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:225:6:HAL_PWR_DeInit	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:236:6:HAL_PWR_EnableBkUpAccess	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:249:6:HAL_PWR_DisableBkUpAccess	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:415:6:HAL_PWR_ConfigPVD	6
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:470:6:HAL_PWR_EnablePVD	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:480:6:HAL_PWR_DisablePVD	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:507:6:HAL_PWR_EnableWakeUpPin	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:536:6:HAL_PWR_DisableWakeUpPin	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:564:6:HAL_PWR_EnterSLEEPMode	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:618:6:HAL_PWR_EnterSTOPMode	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:689:6:HAL_PWR_EnterSTANDBYMode	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:741:6:HAL_PWR_EnableSleepOnExit	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:754:6:HAL_PWR_DisableSleepOnExit	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:767:6:HAL_PWR_EnableSEVOnPend	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:779:6:HAL_PWR_DisableSEVOnPend	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:808:6:HAL_PWR_PVD_IRQHandler	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:853:13:HAL_PWR_PVDCallback	1
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.d
new file mode 100644
index 0000000..279f435
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.d
@@ -0,0 +1,80 @@
+Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o: \
+ ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o
new file mode 100644
index 0000000..cdc066d
Binary files /dev/null and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o differ
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.su b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.su
new file mode 100644
index 0000000..e6b9a7a
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.su
@@ -0,0 +1,17 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:225:6:HAL_PWR_DeInit	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:236:6:HAL_PWR_EnableBkUpAccess	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:249:6:HAL_PWR_DisableBkUpAccess	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:415:6:HAL_PWR_ConfigPVD	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:470:6:HAL_PWR_EnablePVD	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:480:6:HAL_PWR_DisablePVD	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:507:6:HAL_PWR_EnableWakeUpPin	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:536:6:HAL_PWR_DisableWakeUpPin	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:564:6:HAL_PWR_EnterSLEEPMode	16	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:618:6:HAL_PWR_EnterSTOPMode	16	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:689:6:HAL_PWR_EnterSTANDBYMode	4	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:741:6:HAL_PWR_EnableSleepOnExit	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:754:6:HAL_PWR_DisableSleepOnExit	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:767:6:HAL_PWR_EnableSEVOnPend	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:779:6:HAL_PWR_DisableSEVOnPend	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:808:6:HAL_PWR_PVD_IRQHandler	8	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:853:13:HAL_PWR_PVDCallback	4	static
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.cyclo b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.cyclo
new file mode 100644
index 0000000..a82395d
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.cyclo
@@ -0,0 +1,40 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:313:19:HAL_PWREx_ConfigSupply	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:385:10:HAL_PWREx_GetSupplyConfig	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:413:19:HAL_PWREx_ControlVoltageScaling	12
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:512:10:HAL_PWREx_GetVoltageRange	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:538:19:HAL_PWREx_ControlStopModeVoltageScaling	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:553:10:HAL_PWREx_GetStopModeVoltageRange	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:816:6:HAL_PWREx_EnterSTOPMode	4
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:939:6:HAL_PWREx_ClearPendingEvent	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:986:6:HAL_PWREx_EnterSTANDBYMode	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1081:6:HAL_PWREx_ConfigD3Domain	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1212:6:HAL_PWREx_EnableFlashPowerDown	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1226:6:HAL_PWREx_DisableFlashPowerDown	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1302:6:HAL_PWREx_EnableWakeUpPin	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1344:6:HAL_PWREx_DisableWakeUpPin	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1369:10:HAL_PWREx_GetWakeupFlag	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1394:19:HAL_PWREx_ClearWakeupFlag	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1416:6:HAL_PWREx_WAKEUP_PIN_IRQHandler	6
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1477:13:HAL_PWREx_WKUP1_Callback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1488:13:HAL_PWREx_WKUP2_Callback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1500:13:HAL_PWREx_WKUP3_Callback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1512:13:HAL_PWREx_WKUP4_Callback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1524:13:HAL_PWREx_WKUP5_Callback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1536:13:HAL_PWREx_WKUP6_Callback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1625:19:HAL_PWREx_EnableBkUpReg	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1651:19:HAL_PWREx_DisableBkUpReg	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1677:19:HAL_PWREx_EnableUSBReg	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1703:19:HAL_PWREx_DisableUSBReg	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1729:6:HAL_PWREx_EnableUSBVoltageDetector	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1739:6:HAL_PWREx_DisableUSBVoltageDetector	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1755:6:HAL_PWREx_EnableBatteryCharging	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1771:6:HAL_PWREx_DisableBatteryCharging	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1861:6:HAL_PWREx_EnableMonitoring	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1871:6:HAL_PWREx_DisableMonitoring	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1882:10:HAL_PWREx_GetTemperatureLevel	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1913:10:HAL_PWREx_GetVBATLevel	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1976:6:HAL_PWREx_ConfigAVD	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:2025:6:HAL_PWREx_EnableAVD	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:2035:6:HAL_PWREx_DisableAVD	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:2046:6:HAL_PWREx_PVD_AVD_IRQHandler	7
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:2131:13:HAL_PWREx_AVDCallback	1
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.d
new file mode 100644
index 0000000..84cd061
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.d
@@ -0,0 +1,80 @@
+Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o: \
+ ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o
new file mode 100644
index 0000000..020a7f4
Binary files /dev/null and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o differ
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.su b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.su
new file mode 100644
index 0000000..da15a26
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.su
@@ -0,0 +1,40 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:313:19:HAL_PWREx_ConfigSupply	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:385:10:HAL_PWREx_GetSupplyConfig	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:413:19:HAL_PWREx_ControlVoltageScaling	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:512:10:HAL_PWREx_GetVoltageRange	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:538:19:HAL_PWREx_ControlStopModeVoltageScaling	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:553:10:HAL_PWREx_GetStopModeVoltageRange	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:816:6:HAL_PWREx_EnterSTOPMode	24	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:939:6:HAL_PWREx_ClearPendingEvent	4	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:986:6:HAL_PWREx_EnterSTANDBYMode	16	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1081:6:HAL_PWREx_ConfigD3Domain	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1212:6:HAL_PWREx_EnableFlashPowerDown	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1226:6:HAL_PWREx_DisableFlashPowerDown	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1302:6:HAL_PWREx_EnableWakeUpPin	80	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1344:6:HAL_PWREx_DisableWakeUpPin	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1369:10:HAL_PWREx_GetWakeupFlag	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1394:19:HAL_PWREx_ClearWakeupFlag	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1416:6:HAL_PWREx_WAKEUP_PIN_IRQHandler	8	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1477:13:HAL_PWREx_WKUP1_Callback	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1488:13:HAL_PWREx_WKUP2_Callback	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1500:13:HAL_PWREx_WKUP3_Callback	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1512:13:HAL_PWREx_WKUP4_Callback	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1524:13:HAL_PWREx_WKUP5_Callback	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1536:13:HAL_PWREx_WKUP6_Callback	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1625:19:HAL_PWREx_EnableBkUpReg	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1651:19:HAL_PWREx_DisableBkUpReg	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1677:19:HAL_PWREx_EnableUSBReg	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1703:19:HAL_PWREx_DisableUSBReg	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1729:6:HAL_PWREx_EnableUSBVoltageDetector	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1739:6:HAL_PWREx_DisableUSBVoltageDetector	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1755:6:HAL_PWREx_EnableBatteryCharging	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1771:6:HAL_PWREx_DisableBatteryCharging	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1861:6:HAL_PWREx_EnableMonitoring	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1871:6:HAL_PWREx_DisableMonitoring	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1882:10:HAL_PWREx_GetTemperatureLevel	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1913:10:HAL_PWREx_GetVBATLevel	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1976:6:HAL_PWREx_ConfigAVD	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:2025:6:HAL_PWREx_EnableAVD	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:2035:6:HAL_PWREx_DisableAVD	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:2046:6:HAL_PWREx_PVD_AVD_IRQHandler	8	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:2131:13:HAL_PWREx_AVDCallback	4	static
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.cyclo b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.cyclo
new file mode 100644
index 0000000..e5d19e5
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.cyclo
@@ -0,0 +1,38 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:306:19:HAL_QSPI_Init	4
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:400:19:HAL_QSPI_DeInit	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:438:13:HAL_QSPI_MspInit	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:453:13:HAL_QSPI_MspDeInit	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:492:6:HAL_QSPI_IRQHandler	29
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:784:19:HAL_QSPI_Command	6
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:873:19:HAL_QSPI_Command_IT	6
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:973:19:HAL_QSPI_Transmit	8
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:1056:19:HAL_QSPI_Receive	8
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:1141:19:HAL_QSPI_Transmit_IT	4
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:1201:19:HAL_QSPI_Receive_IT	4
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:1265:19:HAL_QSPI_Transmit_DMA	8
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:1378:19:HAL_QSPI_Receive_DMA	8
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:1495:19:HAL_QSPI_AutoPolling	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:1595:19:HAL_QSPI_AutoPolling_IT	4
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:1699:19:HAL_QSPI_MemoryMapped	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:1785:13:HAL_QSPI_ErrorCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:1800:13:HAL_QSPI_AbortCpltCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:1815:13:HAL_QSPI_CmdCpltCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:1830:13:HAL_QSPI_RxCpltCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:1845:13:HAL_QSPI_TxCpltCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:1861:13:HAL_QSPI_FifoThresholdCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:1876:13:HAL_QSPI_StatusMatchCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:1891:13:HAL_QSPI_TimeOutCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:2133:23:HAL_QSPI_GetState	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:2144:10:HAL_QSPI_GetError	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:2154:19:HAL_QSPI_Abort	7
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:2219:19:HAL_QSPI_Abort_IT	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:2284:6:HAL_QSPI_SetTimeout	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:2294:19:HAL_QSPI_SetFifoThreshold	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:2326:10:HAL_QSPI_GetFifoThreshold	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:2338:19:HAL_QSPI_SetFlashID	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:2385:13:QSPI_DMARxCplt	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:2399:13:QSPI_DMATxCplt	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:2413:13:QSPI_DMAError	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:2435:13:QSPI_DMAAbortCplt	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:2478:26:QSPI_WaitFlagStateUntilTimeout	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:2511:13:QSPI_Config	15
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.d
new file mode 100644
index 0000000..93cdc71
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.d
@@ -0,0 +1,80 @@
+Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.o: \
+ ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.o
new file mode 100644
index 0000000..5e2a840
Binary files /dev/null and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.o differ
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.su b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.su
new file mode 100644
index 0000000..9a12232
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.su
@@ -0,0 +1,38 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:306:19:HAL_QSPI_Init	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:400:19:HAL_QSPI_DeInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:438:13:HAL_QSPI_MspInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:453:13:HAL_QSPI_MspDeInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:492:6:HAL_QSPI_IRQHandler	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:784:19:HAL_QSPI_Command	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:873:19:HAL_QSPI_Command_IT	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:973:19:HAL_QSPI_Transmit	48	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:1056:19:HAL_QSPI_Receive	48	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:1141:19:HAL_QSPI_Transmit_IT	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:1201:19:HAL_QSPI_Receive_IT	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:1265:19:HAL_QSPI_Transmit_DMA	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:1378:19:HAL_QSPI_Receive_DMA	48	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:1495:19:HAL_QSPI_AutoPolling	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:1595:19:HAL_QSPI_AutoPolling_IT	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:1699:19:HAL_QSPI_MemoryMapped	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:1785:13:HAL_QSPI_ErrorCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:1800:13:HAL_QSPI_AbortCpltCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:1815:13:HAL_QSPI_CmdCpltCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:1830:13:HAL_QSPI_RxCpltCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:1845:13:HAL_QSPI_TxCpltCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:1861:13:HAL_QSPI_FifoThresholdCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:1876:13:HAL_QSPI_StatusMatchCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:1891:13:HAL_QSPI_TimeOutCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:2133:23:HAL_QSPI_GetState	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:2144:10:HAL_QSPI_GetError	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:2154:19:HAL_QSPI_Abort	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:2219:19:HAL_QSPI_Abort_IT	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:2284:6:HAL_QSPI_SetTimeout	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:2294:19:HAL_QSPI_SetFifoThreshold	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:2326:10:HAL_QSPI_GetFifoThreshold	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:2338:19:HAL_QSPI_SetFlashID	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:2385:13:QSPI_DMARxCplt	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:2399:13:QSPI_DMATxCplt	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:2413:13:QSPI_DMAError	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:2435:13:QSPI_DMAAbortCplt	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:2478:26:QSPI_WaitFlagStateUntilTimeout	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c:2511:13:QSPI_Config	24	static
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.cyclo b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.cyclo
new file mode 100644
index 0000000..3a5a042
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.cyclo
@@ -0,0 +1,14 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c:188:19:HAL_RCC_DeInit	18
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c:405:26:HAL_RCC_OscConfig	89
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c:922:19:HAL_RCC_ClockConfig	36
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c:1286:6:HAL_RCC_MCOConfig	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c:1340:6:HAL_RCC_EnableCSS	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c:1349:6:HAL_RCC_DisableCSS	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c:1388:10:HAL_RCC_GetSysClockFreq	12
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c:1485:10:HAL_RCC_GetHCLKFreq	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c:1517:10:HAL_RCC_GetPCLK1Freq	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c:1535:10:HAL_RCC_GetPCLK2Freq	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c:1552:6:HAL_RCC_GetOscConfig	12
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c:1718:6:HAL_RCC_GetClockConfig	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c:1774:6:HAL_RCC_NMI_IRQHandler	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c:1791:13:HAL_RCC_CSSCallback	1
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.d
new file mode 100644
index 0000000..a60deb2
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.d
@@ -0,0 +1,80 @@
+Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o: \
+ ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o
new file mode 100644
index 0000000..af4483e
Binary files /dev/null and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o differ
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.su b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.su
new file mode 100644
index 0000000..97ae8e5
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.su
@@ -0,0 +1,14 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c:188:19:HAL_RCC_DeInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c:405:26:HAL_RCC_OscConfig	56	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c:922:19:HAL_RCC_ClockConfig	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c:1286:6:HAL_RCC_MCOConfig	56	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c:1340:6:HAL_RCC_EnableCSS	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c:1349:6:HAL_RCC_DisableCSS	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c:1388:10:HAL_RCC_GetSysClockFreq	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c:1485:10:HAL_RCC_GetHCLKFreq	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c:1517:10:HAL_RCC_GetPCLK1Freq	8	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c:1535:10:HAL_RCC_GetPCLK2Freq	8	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c:1552:6:HAL_RCC_GetOscConfig	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c:1718:6:HAL_RCC_GetClockConfig	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c:1774:6:HAL_RCC_NMI_IRQHandler	8	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c:1791:13:HAL_RCC_CSSCallback	4	static
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.cyclo b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.cyclo
new file mode 100644
index 0000000..c2997a5
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.cyclo
@@ -0,0 +1,28 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:105:19:HAL_RCCEx_PeriphCLKConfig	210
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:1692:6:HAL_RCCEx_GetPeriphCLKConfig	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:1881:10:HAL_RCCEx_GetPeriphCLKFreq	146
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:2904:10:HAL_RCCEx_GetD1PCLK1Freq	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:2921:10:HAL_RCCEx_GetD3PCLK1Freq	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:2945:6:HAL_RCCEx_GetPLL2ClockFreq	7
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3014:6:HAL_RCCEx_GetPLL3ClockFreq	7
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3082:6:HAL_RCCEx_GetPLL1ClockFreq	7
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3143:10:HAL_RCCEx_GetD1SysClockFreq	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3183:6:HAL_RCCEx_EnableLSECSS	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3193:6:HAL_RCCEx_DisableLSECSS	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3205:6:HAL_RCCEx_EnableLSECSS_IT	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3232:6:HAL_RCCEx_WakeUpStopCLKConfig	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3247:6:HAL_RCCEx_KerWakeUpStopCLKConfig	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3301:6:HAL_RCCEx_WWDGxSysResetConfig	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3382:6:HAL_RCCEx_CRSConfig	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3432:6:HAL_RCCEx_CRSSoftwareSynchronizationGenerate	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3442:6:HAL_RCCEx_CRSGetSynchronizationInfo	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3475:10:HAL_RCCEx_CRSWaitSynchronization	11
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3559:6:HAL_RCCEx_CRS_IRQHandler	12
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3624:13:HAL_RCCEx_CRS_SyncOkCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3635:13:HAL_RCCEx_CRS_SyncWarnCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3646:13:HAL_RCCEx_CRS_ExpectedSyncCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3662:13:HAL_RCCEx_CRS_ErrorCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3693:26:RCCEx_PLL2_Config	8
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3798:26:RCCEx_PLL3_Config	8
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3895:6:HAL_RCCEx_LSECSS_IRQHandler	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3914:13:HAL_RCCEx_LSECSS_Callback	1
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.d
new file mode 100644
index 0000000..2947cad
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.d
@@ -0,0 +1,80 @@
+Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o: \
+ ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o
new file mode 100644
index 0000000..c59dfb1
Binary files /dev/null and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o differ
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.su b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.su
new file mode 100644
index 0000000..8efd5f8
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.su
@@ -0,0 +1,28 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:105:19:HAL_RCCEx_PeriphCLKConfig	328	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:1692:6:HAL_RCCEx_GetPeriphCLKConfig	72	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:1881:10:HAL_RCCEx_GetPeriphCLKFreq	72	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:2904:10:HAL_RCCEx_GetD1PCLK1Freq	8	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:2921:10:HAL_RCCEx_GetD3PCLK1Freq	8	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:2945:6:HAL_RCCEx_GetPLL2ClockFreq	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3014:6:HAL_RCCEx_GetPLL3ClockFreq	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3082:6:HAL_RCCEx_GetPLL1ClockFreq	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3143:10:HAL_RCCEx_GetD1SysClockFreq	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3183:6:HAL_RCCEx_EnableLSECSS	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3193:6:HAL_RCCEx_DisableLSECSS	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3205:6:HAL_RCCEx_EnableLSECSS_IT	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3232:6:HAL_RCCEx_WakeUpStopCLKConfig	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3247:6:HAL_RCCEx_KerWakeUpStopCLKConfig	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3301:6:HAL_RCCEx_WWDGxSysResetConfig	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3382:6:HAL_RCCEx_CRSConfig	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3432:6:HAL_RCCEx_CRSSoftwareSynchronizationGenerate	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3442:6:HAL_RCCEx_CRSGetSynchronizationInfo	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3475:10:HAL_RCCEx_CRSWaitSynchronization	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3559:6:HAL_RCCEx_CRS_IRQHandler	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3624:13:HAL_RCCEx_CRS_SyncOkCallback	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3635:13:HAL_RCCEx_CRS_SyncWarnCallback	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3646:13:HAL_RCCEx_CRS_ExpectedSyncCallback	4	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3662:13:HAL_RCCEx_CRS_ErrorCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3693:26:RCCEx_PLL2_Config	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3798:26:RCCEx_PLL3_Config	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3895:6:HAL_RCCEx_LSECSS_IRQHandler	8	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3914:13:HAL_RCCEx_LSECSS_Callback	4	static
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.cyclo b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.cyclo
new file mode 100644
index 0000000..d3d6d6b
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.cyclo
@@ -0,0 +1,121 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:269:19:HAL_TIM_Base_Init	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:329:19:HAL_TIM_Base_DeInit	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:372:13:HAL_TIM_Base_MspInit	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:387:13:HAL_TIM_Base_MspDeInit	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:403:19:HAL_TIM_Base_Start	12
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:442:19:HAL_TIM_Base_Stop	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:462:19:HAL_TIM_Base_Start_IT	12
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:504:19:HAL_TIM_Base_Stop_IT	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:529:19:HAL_TIM_Base_Start_DMA	16
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:598:19:HAL_TIM_Base_Stop_DMA	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:653:19:HAL_TIM_OC_Init	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:713:19:HAL_TIM_OC_DeInit	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:756:13:HAL_TIM_OC_MspInit	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:771:13:HAL_TIM_OC_MspDeInit	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:794:19:HAL_TIM_OC_Start	28
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:850:19:HAL_TIM_OC_Stop	16
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:885:19:HAL_TIM_OC_Start_IT	33
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:978:19:HAL_TIM_OC_Stop_IT	21
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:1055:19:HAL_TIM_OC_Start_DMA	45
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:1219:19:HAL_TIM_OC_Stop_DMA	21
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:1322:19:HAL_TIM_PWM_Init	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:1382:19:HAL_TIM_PWM_DeInit	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:1425:13:HAL_TIM_PWM_MspInit	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:1440:13:HAL_TIM_PWM_MspDeInit	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:1463:19:HAL_TIM_PWM_Start	28
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:1519:19:HAL_TIM_PWM_Stop	16
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:1554:19:HAL_TIM_PWM_Start_IT	33
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:1647:19:HAL_TIM_PWM_Stop_IT	21
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:1724:19:HAL_TIM_PWM_Start_DMA	45
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:1887:19:HAL_TIM_PWM_Stop_DMA	21
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:1990:19:HAL_TIM_IC_Init	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2050:19:HAL_TIM_IC_DeInit	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2093:13:HAL_TIM_IC_MspInit	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2108:13:HAL_TIM_IC_MspDeInit	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2129:19:HAL_TIM_IC_Start	29
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2181:19:HAL_TIM_IC_Stop	11
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2211:19:HAL_TIM_IC_Start_IT	34
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2303:19:HAL_TIM_IC_Stop_IT	16
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2375:19:HAL_TIM_IC_Start_DMA	41
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2534:19:HAL_TIM_IC_Stop_DMA	16
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2639:19:HAL_TIM_OnePulse_Init	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2708:19:HAL_TIM_OnePulse_DeInit	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2753:13:HAL_TIM_OnePulse_MspInit	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2768:13:HAL_TIM_OnePulse_MspDeInit	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2788:19:HAL_TIM_OnePulse_Start	11
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2845:19:HAL_TIM_OnePulse_Stop	11
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2888:19:HAL_TIM_OnePulse_Start_IT	11
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2951:19:HAL_TIM_OnePulse_Stop_IT	11
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:3030:19:HAL_TIM_Encoder_Init	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:3145:19:HAL_TIM_Encoder_DeInit	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:3190:13:HAL_TIM_Encoder_MspInit	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:3205:13:HAL_TIM_Encoder_MspDeInit	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:3225:19:HAL_TIM_Encoder_Start	13
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:3319:19:HAL_TIM_Encoder_Stop	15
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:3379:19:HAL_TIM_Encoder_Start_IT	13
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:3479:19:HAL_TIM_Encoder_Stop_IT	15
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:3544:19:HAL_TIM_Encoder_Start_DMA	32
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:3757:19:HAL_TIM_Encoder_Stop_DMA	15
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:3834:6:HAL_TIM_IRQHandler	24
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:4068:19:HAL_TIM_OC_ConfigChannel	8
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:4167:19:HAL_TIM_IC_ConfigChannel	6
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:4268:19:HAL_TIM_PWM_ConfigChannel	8
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:4416:19:HAL_TIM_OnePulse_ConfigChannel	8
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:4571:19:HAL_TIM_DMABurst_WriteStart	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:4631:19:HAL_TIM_DMABurst_MultiWriteStart	25
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:4815:19:HAL_TIM_DMABurst_WriteStop	14
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:4923:19:HAL_TIM_DMABurst_ReadStart	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:4981:19:HAL_TIM_DMABurst_MultiReadStart	25
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5165:19:HAL_TIM_DMABurst_ReadStop	14
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5249:19:HAL_TIM_GenerateEvent	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5288:19:HAL_TIM_ConfigOCrefClear	18
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5446:19:HAL_TIM_ConfigClockSource	30
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5605:19:HAL_TIM_ConfigTI1Input	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5637:19:HAL_TIM_SlaveConfigSynchro	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5677:19:HAL_TIM_SlaveConfigSynchro_IT	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5720:10:HAL_TIM_ReadCapturedValue	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5804:13:HAL_TIM_PeriodElapsedCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5819:13:HAL_TIM_PeriodElapsedHalfCpltCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5834:13:HAL_TIM_OC_DelayElapsedCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5849:13:HAL_TIM_IC_CaptureCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5864:13:HAL_TIM_IC_CaptureHalfCpltCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5879:13:HAL_TIM_PWM_PulseFinishedCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5894:13:HAL_TIM_PWM_PulseFinishedHalfCpltCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5909:13:HAL_TIM_TriggerCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5924:13:HAL_TIM_TriggerHalfCpltCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5939:13:HAL_TIM_ErrorCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6497:22:HAL_TIM_Base_GetState	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6507:22:HAL_TIM_OC_GetState	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6517:22:HAL_TIM_PWM_GetState	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6527:22:HAL_TIM_IC_GetState	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6537:22:HAL_TIM_OnePulse_GetState	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6547:22:HAL_TIM_Encoder_GetState	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6557:23:HAL_TIM_GetActiveChannel	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6575:29:HAL_TIM_GetChannelState	6
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6592:30:HAL_TIM_DMABurstState	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6617:6:TIM_DMAError	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6660:13:TIM_DMADelayPulseCplt	9
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6719:6:TIM_DMADelayPulseHalfCplt	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6758:6:TIM_DMACaptureCplt	9
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6821:6:TIM_DMACaptureHalfCplt	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6860:13:TIM_DMAPeriodElapsedCplt	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6881:13:TIM_DMAPeriodElapsedHalfCplt	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6897:13:TIM_DMATriggerCplt	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6918:13:TIM_DMATriggerHalfCplt	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6935:6:TIM_Base_SetConfig	22
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6990:13:TIM_OC1_SetConfig	11
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:7066:6:TIM_OC2_SetConfig	8
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:7142:13:TIM_OC3_SetConfig	8
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:7217:13:TIM_OC4_SetConfig	6
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:7278:13:TIM_OC5_SetConfig	6
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:7332:13:TIM_OC6_SetConfig	6
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:7387:26:TIM_SlaveTimer_SetConfig	36
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:7531:6:TIM_TI1_SetConfig	10
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:7578:13:TIM_TI1_ConfigInputStage	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:7621:13:TIM_TI2_SetConfig	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:7661:13:TIM_TI2_ConfigInputStage	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:7704:13:TIM_TI3_SetConfig	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:7752:13:TIM_TI4_SetConfig	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:7808:13:TIM_ITRx_SetConfig	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:7838:6:TIM_ETR_SetConfig	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:7870:6:TIM_CCxChannelCmd	1
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.d
new file mode 100644
index 0000000..d59a8eb
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.d
@@ -0,0 +1,80 @@
+Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o: \
+ ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o
new file mode 100644
index 0000000..8a96a5d
Binary files /dev/null and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o differ
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.su b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.su
new file mode 100644
index 0000000..83010e1
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.su
@@ -0,0 +1,121 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:269:19:HAL_TIM_Base_Init	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:329:19:HAL_TIM_Base_DeInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:372:13:HAL_TIM_Base_MspInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:387:13:HAL_TIM_Base_MspDeInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:403:19:HAL_TIM_Base_Start	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:442:19:HAL_TIM_Base_Stop	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:462:19:HAL_TIM_Base_Start_IT	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:504:19:HAL_TIM_Base_Stop_IT	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:529:19:HAL_TIM_Base_Start_DMA	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:598:19:HAL_TIM_Base_Stop_DMA	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:653:19:HAL_TIM_OC_Init	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:713:19:HAL_TIM_OC_DeInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:756:13:HAL_TIM_OC_MspInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:771:13:HAL_TIM_OC_MspDeInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:794:19:HAL_TIM_OC_Start	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:850:19:HAL_TIM_OC_Stop	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:885:19:HAL_TIM_OC_Start_IT	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:978:19:HAL_TIM_OC_Stop_IT	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:1055:19:HAL_TIM_OC_Start_DMA	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:1219:19:HAL_TIM_OC_Stop_DMA	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:1322:19:HAL_TIM_PWM_Init	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:1382:19:HAL_TIM_PWM_DeInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:1425:13:HAL_TIM_PWM_MspInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:1440:13:HAL_TIM_PWM_MspDeInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:1463:19:HAL_TIM_PWM_Start	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:1519:19:HAL_TIM_PWM_Stop	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:1554:19:HAL_TIM_PWM_Start_IT	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:1647:19:HAL_TIM_PWM_Stop_IT	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:1724:19:HAL_TIM_PWM_Start_DMA	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:1887:19:HAL_TIM_PWM_Stop_DMA	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:1990:19:HAL_TIM_IC_Init	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2050:19:HAL_TIM_IC_DeInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2093:13:HAL_TIM_IC_MspInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2108:13:HAL_TIM_IC_MspDeInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2129:19:HAL_TIM_IC_Start	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2181:19:HAL_TIM_IC_Stop	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2211:19:HAL_TIM_IC_Start_IT	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2303:19:HAL_TIM_IC_Stop_IT	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2375:19:HAL_TIM_IC_Start_DMA	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2534:19:HAL_TIM_IC_Stop_DMA	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2639:19:HAL_TIM_OnePulse_Init	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2708:19:HAL_TIM_OnePulse_DeInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2753:13:HAL_TIM_OnePulse_MspInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2768:13:HAL_TIM_OnePulse_MspDeInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2788:19:HAL_TIM_OnePulse_Start	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2845:19:HAL_TIM_OnePulse_Stop	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2888:19:HAL_TIM_OnePulse_Start_IT	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:2951:19:HAL_TIM_OnePulse_Stop_IT	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:3030:19:HAL_TIM_Encoder_Init	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:3145:19:HAL_TIM_Encoder_DeInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:3190:13:HAL_TIM_Encoder_MspInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:3205:13:HAL_TIM_Encoder_MspDeInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:3225:19:HAL_TIM_Encoder_Start	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:3319:19:HAL_TIM_Encoder_Stop	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:3379:19:HAL_TIM_Encoder_Start_IT	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:3479:19:HAL_TIM_Encoder_Stop_IT	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:3544:19:HAL_TIM_Encoder_Start_DMA	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:3757:19:HAL_TIM_Encoder_Stop_DMA	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:3834:6:HAL_TIM_IRQHandler	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:4068:19:HAL_TIM_OC_ConfigChannel	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:4167:19:HAL_TIM_IC_ConfigChannel	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:4268:19:HAL_TIM_PWM_ConfigChannel	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:4416:19:HAL_TIM_OnePulse_ConfigChannel	56	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:4571:19:HAL_TIM_DMABurst_WriteStart	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:4631:19:HAL_TIM_DMABurst_MultiWriteStart	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:4815:19:HAL_TIM_DMABurst_WriteStop	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:4923:19:HAL_TIM_DMABurst_ReadStart	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:4981:19:HAL_TIM_DMABurst_MultiReadStart	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5165:19:HAL_TIM_DMABurst_ReadStop	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5249:19:HAL_TIM_GenerateEvent	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5288:19:HAL_TIM_ConfigOCrefClear	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5446:19:HAL_TIM_ConfigClockSource	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5605:19:HAL_TIM_ConfigTI1Input	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5637:19:HAL_TIM_SlaveConfigSynchro	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5677:19:HAL_TIM_SlaveConfigSynchro_IT	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5720:10:HAL_TIM_ReadCapturedValue	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5804:13:HAL_TIM_PeriodElapsedCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5819:13:HAL_TIM_PeriodElapsedHalfCpltCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5834:13:HAL_TIM_OC_DelayElapsedCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5849:13:HAL_TIM_IC_CaptureCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5864:13:HAL_TIM_IC_CaptureHalfCpltCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5879:13:HAL_TIM_PWM_PulseFinishedCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5894:13:HAL_TIM_PWM_PulseFinishedHalfCpltCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5909:13:HAL_TIM_TriggerCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5924:13:HAL_TIM_TriggerHalfCpltCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:5939:13:HAL_TIM_ErrorCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6497:22:HAL_TIM_Base_GetState	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6507:22:HAL_TIM_OC_GetState	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6517:22:HAL_TIM_PWM_GetState	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6527:22:HAL_TIM_IC_GetState	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6537:22:HAL_TIM_OnePulse_GetState	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6547:22:HAL_TIM_Encoder_GetState	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6557:23:HAL_TIM_GetActiveChannel	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6575:29:HAL_TIM_GetChannelState	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6592:30:HAL_TIM_DMABurstState	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6617:6:TIM_DMAError	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6660:13:TIM_DMADelayPulseCplt	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6719:6:TIM_DMADelayPulseHalfCplt	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6758:6:TIM_DMACaptureCplt	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6821:6:TIM_DMACaptureHalfCplt	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6860:13:TIM_DMAPeriodElapsedCplt	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6881:13:TIM_DMAPeriodElapsedHalfCplt	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6897:13:TIM_DMATriggerCplt	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6918:13:TIM_DMATriggerHalfCplt	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6935:6:TIM_Base_SetConfig	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:6990:13:TIM_OC1_SetConfig	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:7066:6:TIM_OC2_SetConfig	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:7142:13:TIM_OC3_SetConfig	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:7217:13:TIM_OC4_SetConfig	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:7278:13:TIM_OC5_SetConfig	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:7332:13:TIM_OC6_SetConfig	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:7387:26:TIM_SlaveTimer_SetConfig	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:7531:6:TIM_TI1_SetConfig	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:7578:13:TIM_TI1_ConfigInputStage	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:7621:13:TIM_TI2_SetConfig	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:7661:13:TIM_TI2_ConfigInputStage	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:7704:13:TIM_TI3_SetConfig	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:7752:13:TIM_TI4_SetConfig	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:7808:13:TIM_ITRx_SetConfig	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:7838:6:TIM_ETR_SetConfig	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c:7870:6:TIM_CCxChannelCmd	32	static
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.cyclo b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.cyclo
new file mode 100644
index 0000000..f585edb
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.cyclo
@@ -0,0 +1,46 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:152:19:HAL_TIMEx_HallSensor_Init	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:254:19:HAL_TIMEx_HallSensor_DeInit	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:299:13:HAL_TIMEx_HallSensor_MspInit	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:314:13:HAL_TIMEx_HallSensor_MspDeInit	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:329:19:HAL_TIMEx_HallSensor_Start	15
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:383:19:HAL_TIMEx_HallSensor_Stop	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:411:19:HAL_TIMEx_HallSensor_Start_IT	15
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:468:19:HAL_TIMEx_HallSensor_Stop_IT	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:501:19:HAL_TIMEx_HallSensor_Start_DMA	18
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:577:19:HAL_TIMEx_HallSensor_Stop_DMA	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:639:19:HAL_TIMEx_OCN_Start	18
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:690:19:HAL_TIMEx_OCN_Stop	8
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:722:19:HAL_TIMEx_OCN_Start_IT	23
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:809:19:HAL_TIMEx_OCN_Stop_IT	14
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:884:19:HAL_TIMEx_OCN_Start_DMA	32
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:1022:19:HAL_TIMEx_OCN_Stop_DMA	13
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:1112:19:HAL_TIMEx_PWMN_Start	18
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:1162:19:HAL_TIMEx_PWMN_Stop	8
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:1194:19:HAL_TIMEx_PWMN_Start_IT	23
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:1280:19:HAL_TIMEx_PWMN_Stop_IT	14
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:1355:19:HAL_TIMEx_PWMN_Start_DMA	32
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:1493:19:HAL_TIMEx_PWMN_Stop_DMA	13
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:1584:19:HAL_TIMEx_OnePulseN_Start	6
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:1633:19:HAL_TIMEx_OnePulseN_Stop	6
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:1672:19:HAL_TIMEx_OnePulseN_Start_IT	6
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:1727:19:HAL_TIMEx_OnePulseN_Stop_IT	6
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:1813:19:HAL_TIMEx_ConfigCommutEvent	8
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:1875:19:HAL_TIMEx_ConfigCommutEvent_IT	8
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:1938:19:HAL_TIMEx_ConfigCommutEvent_DMA	8
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:1988:19:HAL_TIMEx_MasterConfigSynchronization	12
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2061:19:HAL_TIMEx_ConfigBreakDeadTime	4
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2138:19:HAL_TIMEx_ConfigBreakInput	10
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2321:19:HAL_TIMEx_RemapConfig	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2415:20:HAL_TIMEx_TISelection	6
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2460:19:HAL_TIMEx_GroupChannel5	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2643:13:HAL_TIMEx_CommutCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2657:13:HAL_TIMEx_CommutHalfCpltCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2672:13:HAL_TIMEx_BreakCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2687:13:HAL_TIMEx_Break2Callback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2720:22:HAL_TIMEx_HallSensor_GetState	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2735:29:HAL_TIMEx_GetChannelNState	4
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2764:6:TIMEx_DMACommutationCplt	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2783:6:TIMEx_DMACommutationHalfCplt	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2803:13:TIM_DMADelayPulseNCplt	7
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2853:13:TIM_DMAErrorCCxN	4
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2898:13:TIM_CCxNChannelCmd	1
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.d
new file mode 100644
index 0000000..31b8a65
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.d
@@ -0,0 +1,80 @@
+Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o: \
+ ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o
new file mode 100644
index 0000000..f722c3f
Binary files /dev/null and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o differ
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.su b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.su
new file mode 100644
index 0000000..026056c
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.su
@@ -0,0 +1,46 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:152:19:HAL_TIMEx_HallSensor_Init	48	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:254:19:HAL_TIMEx_HallSensor_DeInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:299:13:HAL_TIMEx_HallSensor_MspInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:314:13:HAL_TIMEx_HallSensor_MspDeInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:329:19:HAL_TIMEx_HallSensor_Start	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:383:19:HAL_TIMEx_HallSensor_Stop	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:411:19:HAL_TIMEx_HallSensor_Start_IT	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:468:19:HAL_TIMEx_HallSensor_Stop_IT	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:501:19:HAL_TIMEx_HallSensor_Start_DMA	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:577:19:HAL_TIMEx_HallSensor_Stop_DMA	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:639:19:HAL_TIMEx_OCN_Start	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:690:19:HAL_TIMEx_OCN_Stop	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:722:19:HAL_TIMEx_OCN_Start_IT	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:809:19:HAL_TIMEx_OCN_Stop_IT	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:884:19:HAL_TIMEx_OCN_Start_DMA	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:1022:19:HAL_TIMEx_OCN_Stop_DMA	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:1112:19:HAL_TIMEx_PWMN_Start	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:1162:19:HAL_TIMEx_PWMN_Stop	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:1194:19:HAL_TIMEx_PWMN_Start_IT	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:1280:19:HAL_TIMEx_PWMN_Stop_IT	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:1355:19:HAL_TIMEx_PWMN_Start_DMA	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:1493:19:HAL_TIMEx_PWMN_Stop_DMA	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:1584:19:HAL_TIMEx_OnePulseN_Start	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:1633:19:HAL_TIMEx_OnePulseN_Stop	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:1672:19:HAL_TIMEx_OnePulseN_Start_IT	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:1727:19:HAL_TIMEx_OnePulseN_Stop_IT	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:1813:19:HAL_TIMEx_ConfigCommutEvent	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:1875:19:HAL_TIMEx_ConfigCommutEvent_IT	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:1938:19:HAL_TIMEx_ConfigCommutEvent_DMA	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:1988:19:HAL_TIMEx_MasterConfigSynchronization	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2061:19:HAL_TIMEx_ConfigBreakDeadTime	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2138:19:HAL_TIMEx_ConfigBreakInput	48	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2321:19:HAL_TIMEx_RemapConfig	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2415:20:HAL_TIMEx_TISelection	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2460:19:HAL_TIMEx_GroupChannel5	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2643:13:HAL_TIMEx_CommutCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2657:13:HAL_TIMEx_CommutHalfCpltCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2672:13:HAL_TIMEx_BreakCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2687:13:HAL_TIMEx_Break2Callback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2720:22:HAL_TIMEx_HallSensor_GetState	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2735:29:HAL_TIMEx_GetChannelNState	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2764:6:TIMEx_DMACommutationCplt	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2783:6:TIMEx_DMACommutationHalfCplt	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2803:13:TIM_DMADelayPulseNCplt	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2853:13:TIM_DMAErrorCCxN	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c:2898:13:TIM_CCxNChannelCmd	32	static
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.cyclo b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.cyclo
new file mode 100644
index 0000000..5496b02
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.cyclo
@@ -0,0 +1,70 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:307:19:HAL_UART_Init	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:382:19:HAL_HalfDuplex_Init	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:457:19:HAL_LIN_Init	7
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:556:19:HAL_MultiProcessor_Init	6
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:632:19:HAL_UART_DeInit	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:679:13:HAL_UART_MspInit	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:694:13:HAL_UART_MspDeInit	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:1117:19:HAL_UART_Transmit	10
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:1207:19:HAL_UART_Receive	15
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:1291:19:HAL_UART_Transmit_IT	11
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:1359:19:HAL_UART_Receive_IT	7
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:1400:19:HAL_UART_Transmit_DMA	7
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:1470:19:HAL_UART_Receive_DMA	7
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:1506:19:HAL_UART_DMAPause	9
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:1536:19:HAL_UART_DMAResume	8
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:1567:19:HAL_UART_DMAStop	13
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:1642:19:HAL_UART_Abort	16
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:1745:19:HAL_UART_AbortTransmit	9
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:1804:19:HAL_UART_AbortReceive	10
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:1872:19:HAL_UART_Abort_IT	19
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2025:19:HAL_UART_AbortTransmit_IT	8
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2116:19:HAL_UART_AbortReceive_IT	9
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2209:6:HAL_UART_IRQHandler	75
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2539:13:HAL_UART_TxCpltCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2554:13:HAL_UART_TxHalfCpltCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2569:13:HAL_UART_RxCpltCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2584:13:HAL_UART_RxHalfCpltCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2599:13:HAL_UART_ErrorCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2614:13:HAL_UART_AbortCpltCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2629:13:HAL_UART_AbortTransmitCpltCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2644:13:HAL_UART_AbortReceiveCpltCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2661:13:HAL_UARTEx_RxEventCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2709:6:HAL_UART_ReceiverTimeout_Config	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2724:19:HAL_UART_EnableReceiverTimeout	4
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2762:19:HAL_UART_DisableReceiverTimeout	4
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2800:19:HAL_MultiProcessor_EnableMuteMode	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2820:19:HAL_MultiProcessor_DisableMuteMode	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2840:6:HAL_MultiProcessor_EnterMuteMode	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2850:19:HAL_HalfDuplex_EnableTransmitter	4
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2873:19:HAL_HalfDuplex_EnableReceiver	4
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2897:19:HAL_LIN_SendBreak	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2942:23:HAL_UART_GetState	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2958:10:HAL_UART_GetError	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3004:19:UART_SetConfig	107
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3268:6:UART_AdvFeatureConfig	10
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3342:19:UART_CheckIdleState	8
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3411:19:UART_WaitOnFlagUntilTimeout	10
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3479:19:UART_Start_Receive_IT	20
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3551:19:UART_Start_Receive_DMA	7
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3608:13:UART_EndTxTransfer	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3624:13:UART_EndRxTransfer	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3650:13:UART_DMATransmitCplt	4
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3684:13:UART_DMATxHalfCplt	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3702:13:UART_DMAReceiveCplt	8
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3763:13:UART_DMARxHalfCplt	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3801:13:UART_DMAError	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3841:13:UART_DMAAbortOnError	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3864:13:UART_DMATxAbortCallback	4
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3919:13:UART_DMARxAbortCallback	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3971:13:UART_DMATxOnlyAbortCallback	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:4004:13:UART_DMARxOnlyAbortCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:4037:13:UART_TxISR_8BIT	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:4066:13:UART_TxISR_16BIT	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:4098:13:UART_TxISR_8BIT_FIFOEN	7
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:4138:13:UART_TxISR_16BIT_FIFOEN	7
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:4179:13:UART_EndTransmit_IT	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:4204:13:UART_RxISR_8BIT	11
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:4295:13:UART_RxISR_16BIT	11
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:4388:13:UART_RxISR_8BIT_FIFOEN	25
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:4550:13:UART_RxISR_16BIT_FIFOEN	25
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.d
new file mode 100644
index 0000000..da62326
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.d
@@ -0,0 +1,80 @@
+Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.o: \
+ ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.o
new file mode 100644
index 0000000..9f10d5d
Binary files /dev/null and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.o differ
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.su b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.su
new file mode 100644
index 0000000..d3db224
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.su
@@ -0,0 +1,70 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:307:19:HAL_UART_Init	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:382:19:HAL_HalfDuplex_Init	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:457:19:HAL_LIN_Init	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:556:19:HAL_MultiProcessor_Init	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:632:19:HAL_UART_DeInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:679:13:HAL_UART_MspInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:694:13:HAL_UART_MspDeInit	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:1117:19:HAL_UART_Transmit	48	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:1207:19:HAL_UART_Receive	48	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:1291:19:HAL_UART_Transmit_IT	72	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:1359:19:HAL_UART_Receive_IT	48	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:1400:19:HAL_UART_Transmit_DMA	48	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:1470:19:HAL_UART_Receive_DMA	48	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:1506:19:HAL_UART_DMAPause	120	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:1536:19:HAL_UART_DMAResume	112	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:1567:19:HAL_UART_DMAStop	72	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:1642:19:HAL_UART_Abort	136	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:1745:19:HAL_UART_AbortTransmit	88	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:1804:19:HAL_UART_AbortReceive	112	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:1872:19:HAL_UART_Abort_IT	144	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2025:19:HAL_UART_AbortTransmit_IT	88	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2116:19:HAL_UART_AbortReceive_IT	112	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2209:6:HAL_UART_IRQHandler	240	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2539:13:HAL_UART_TxCpltCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2554:13:HAL_UART_TxHalfCpltCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2569:13:HAL_UART_RxCpltCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2584:13:HAL_UART_RxHalfCpltCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2599:13:HAL_UART_ErrorCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2614:13:HAL_UART_AbortCpltCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2629:13:HAL_UART_AbortTransmitCpltCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2644:13:HAL_UART_AbortReceiveCpltCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2661:13:HAL_UARTEx_RxEventCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2709:6:HAL_UART_ReceiverTimeout_Config	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2724:19:HAL_UART_EnableReceiverTimeout	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2762:19:HAL_UART_DisableReceiverTimeout	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2800:19:HAL_MultiProcessor_EnableMuteMode	40	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2820:19:HAL_MultiProcessor_DisableMuteMode	40	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2840:6:HAL_MultiProcessor_EnterMuteMode	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2850:19:HAL_HalfDuplex_EnableTransmitter	64	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2873:19:HAL_HalfDuplex_EnableReceiver	64	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2897:19:HAL_LIN_SendBreak	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2942:23:HAL_UART_GetState	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:2958:10:HAL_UART_GetError	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3004:19:UART_SetConfig	104	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3268:6:UART_AdvFeatureConfig	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3342:19:UART_CheckIdleState	104	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3411:19:UART_WaitOnFlagUntilTimeout	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3479:19:UART_Start_Receive_IT	144	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3551:19:UART_Start_Receive_DMA	96	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3608:13:UART_EndTxTransfer	64	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3624:13:UART_EndRxTransfer	88	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3650:13:UART_DMATransmitCplt	72	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3684:13:UART_DMATxHalfCplt	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3702:13:UART_DMAReceiveCplt	120	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3763:13:UART_DMARxHalfCplt	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3801:13:UART_DMAError	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3841:13:UART_DMAAbortOnError	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3864:13:UART_DMATxAbortCallback	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3919:13:UART_DMARxAbortCallback	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:3971:13:UART_DMATxOnlyAbortCallback	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:4004:13:UART_DMARxOnlyAbortCallback	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:4037:13:UART_TxISR_8BIT	64	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:4066:13:UART_TxISR_16BIT	72	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:4098:13:UART_TxISR_8BIT_FIFOEN	72	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:4138:13:UART_TxISR_16BIT_FIFOEN	72	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:4179:13:UART_EndTransmit_IT	40	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:4204:13:UART_RxISR_8BIT	120	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:4295:13:UART_RxISR_16BIT	120	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:4388:13:UART_RxISR_8BIT_FIFOEN	184	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c:4550:13:UART_RxISR_16BIT_FIFOEN	192	static,ignoring_inline_asm
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.cyclo b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.cyclo
new file mode 100644
index 0000000..e1119b4
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.cyclo
@@ -0,0 +1,18 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:166:19:HAL_RS485Ex_Init	5
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:274:13:HAL_UARTEx_WakeupCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:289:13:HAL_UARTEx_RxFifoFullCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:304:13:HAL_UARTEx_TxFifoEmptyCallback	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:389:19:HAL_MultiProcessorEx_AddressLength_Set	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:427:19:HAL_UARTEx_StopModeWakeUpSourceConfig	4
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:482:19:HAL_UARTEx_EnableStopMode	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:501:19:HAL_UARTEx_DisableStopMode	3
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:520:19:HAL_UARTEx_EnableFifoMode	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:561:19:HAL_UARTEx_DisableFifoMode	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:607:19:HAL_UARTEx_SetTxFifoThreshold	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:656:19:HAL_UARTEx_SetRxFifoThreshold	2
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:713:19:HAL_UARTEx_ReceiveToIdle	20
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:836:19:HAL_UARTEx_ReceiveToIdle_IT	6
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:893:19:HAL_UARTEx_ReceiveToIdle_DMA	7
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:961:29:HAL_UARTEx_GetRxEventType	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:985:13:UARTEx_Wakeup_AddressConfig	1
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:1003:13:UARTEx_SetNbDataToProcess	2
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.d
new file mode 100644
index 0000000..360d451
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.d
@@ -0,0 +1,80 @@
+Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.o: \
+ ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \
+ ../Core/Inc/stm32h7xx_hal_conf.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h \
+ ../Drivers/CMSIS/Include/core_cm7.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Include/mpu_armv7.h \
+ ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h \
+ ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h:
+../Core/Inc/stm32h7xx_hal_conf.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h:
+../Drivers/CMSIS/Include/core_cm7.h:
+../Drivers/CMSIS/Include/cmsis_version.h:
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+../Drivers/CMSIS/Include/mpu_armv7.h:
+../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h:
+../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h:
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.o
new file mode 100644
index 0000000..6cc732d
Binary files /dev/null and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.o differ
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.su b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.su
new file mode 100644
index 0000000..d9827e4
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.su
@@ -0,0 +1,18 @@
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:166:19:HAL_RS485Ex_Init	32	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:274:13:HAL_UARTEx_WakeupCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:289:13:HAL_UARTEx_RxFifoFullCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:304:13:HAL_UARTEx_TxFifoEmptyCallback	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:389:19:HAL_MultiProcessorEx_AddressLength_Set	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:427:19:HAL_UARTEx_StopModeWakeUpSourceConfig	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:482:19:HAL_UARTEx_EnableStopMode	40	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:501:19:HAL_UARTEx_DisableStopMode	40	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:520:19:HAL_UARTEx_EnableFifoMode	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:561:19:HAL_UARTEx_DisableFifoMode	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:607:19:HAL_UARTEx_SetTxFifoThreshold	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:656:19:HAL_UARTEx_SetRxFifoThreshold	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:713:19:HAL_UARTEx_ReceiveToIdle	40	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:836:19:HAL_UARTEx_ReceiveToIdle_IT	56	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:893:19:HAL_UARTEx_ReceiveToIdle_DMA	56	static,ignoring_inline_asm
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:961:29:HAL_UARTEx_GetRxEventType	16	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:985:13:UARTEx_Wakeup_AddressConfig	24	static
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c:1003:13:UARTEx_SetNbDataToProcess	24	static
diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/subdir.mk b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/subdir.mk
new file mode 100644
index 0000000..9488a50
--- /dev/null
+++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/subdir.mk
@@ -0,0 +1,103 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+# Toolchain: GNU Tools for STM32 (12.3.rel1)
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables 
+C_SRCS += \
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c \
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c \
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c \
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c \
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c \
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c \
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c \
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c \
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c \
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c \
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c \
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c \
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c \
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c \
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c \
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c \
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c \
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c \
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c \
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c \
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c \
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c \
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c \
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c \
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c \
+../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c 
+
+OBJS += \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.o \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.o \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.o \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.o \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.o 
+
+C_DEPS += \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.d \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.d \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.d \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.d \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.d \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.d \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.d \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.d \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.d \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.d \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.d \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.d \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.d \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.d \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.d \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.d \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.d \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.d \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.d \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.d \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.d \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.d \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.d \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.d \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.d \
+./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.d 
+
+
+# Each subdirectory must supply rules for building sources it contributes
+Drivers/STM32H7xx_HAL_Driver/Src/%.o Drivers/STM32H7xx_HAL_Driver/Src/%.su Drivers/STM32H7xx_HAL_Driver/Src/%.cyclo: ../Drivers/STM32H7xx_HAL_Driver/Src/%.c Drivers/STM32H7xx_HAL_Driver/Src/subdir.mk
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32H743xx -c -I../Core/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I../Drivers/CMSIS/Include -I"F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc" -I"F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Protobuf/PSource" -I"F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/MSP" -I"F:/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4/BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3/Core/BASE/Inc/BSP" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@"
+
+clean: clean-Drivers-2f-STM32H7xx_HAL_Driver-2f-Src
+
+clean-Drivers-2f-STM32H7xx_HAL_Driver-2f-Src:
+	-$(RM) ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.o
+	-$(RM) ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.su
+
+.PHONY: clean-Drivers-2f-STM32H7xx_HAL_Driver-2f-Src
+
diff --git a/Debug/makefile b/Debug/makefile
new file mode 100644
index 0000000..c2ededf
--- /dev/null
+++ b/Debug/makefile
@@ -0,0 +1,114 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+# Toolchain: GNU Tools for STM32 (12.3.rel1)
+################################################################################
+
+-include ../makefile.init
+
+RM := rm -rf
+
+# All of the sources participating in the build are defined here
+-include sources.mk
+-include Drivers/STM32H7xx_HAL_Driver/Src/subdir.mk
+-include Core/Startup/subdir.mk
+-include Core/Src/subdir.mk
+-include Core/BASE/Src/MSP/subdir.mk
+-include Core/BASE/Src/BSP/DLT/subdir.mk
+-include Core/BASE/Src/BSP/subdir.mk
+-include Core/BASE/Protobuf/PSource/subdir.mk
+-include objects.mk
+
+ifneq ($(MAKECMDGOALS),clean)
+ifneq ($(strip $(S_DEPS)),)
+-include $(S_DEPS)
+endif
+ifneq ($(strip $(S_UPPER_DEPS)),)
+-include $(S_UPPER_DEPS)
+endif
+ifneq ($(strip $(C_DEPS)),)
+-include $(C_DEPS)
+endif
+endif
+
+-include ../makefile.defs
+
+OPTIONAL_TOOL_DEPS := \
+$(wildcard ../makefile.defs) \
+$(wildcard ../makefile.init) \
+$(wildcard ../makefile.targets) \
+
+
+BUILD_ARTIFACT_NAME := BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3
+BUILD_ARTIFACT_EXTENSION := elf
+BUILD_ARTIFACT_PREFIX :=
+BUILD_ARTIFACT := $(BUILD_ARTIFACT_PREFIX)$(BUILD_ARTIFACT_NAME)$(if $(BUILD_ARTIFACT_EXTENSION),.$(BUILD_ARTIFACT_EXTENSION),)
+
+# Add inputs and outputs from these tool invocations to the build variables 
+EXECUTABLES += \
+BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3.elf \
+
+MAP_FILES += \
+BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3.map \
+
+SIZE_OUTPUT += \
+default.size.stdout \
+
+OBJDUMP_LIST += \
+BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3.list \
+
+OBJCOPY_HEX += \
+BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3.hex \
+
+OBJCOPY_BIN += \
+BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3.bin \
+
+
+# All Target
+all: main-build
+
+# Main-build Target
+main-build: BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3.elf secondary-outputs
+
+# Tool invocations
+BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3.elf BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3.map: $(OBJS) $(USER_OBJS) F:\BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4\BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3\STM32H743VGTX_FLASH.ld makefile objects.list $(OPTIONAL_TOOL_DEPS)
+	arm-none-eabi-gcc -o "BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3.elf" @"objects.list" $(USER_OBJS) $(LIBS) -mcpu=cortex-m7 -T"F:\BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast4\BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3\STM32H743VGTX_FLASH.ld" --specs=nosys.specs -Wl,-Map="BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3.map" -Wl,--gc-sections -static --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -Wl,--start-group -lc -lm -Wl,--end-group
+	@echo 'Finished building target: $@'
+	@echo ' '
+
+default.size.stdout: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS)
+	arm-none-eabi-size  $(EXECUTABLES)
+	@echo 'Finished building: $@'
+	@echo ' '
+
+BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3.list: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS)
+	arm-none-eabi-objdump -h -S $(EXECUTABLES) > "BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3.list"
+	@echo 'Finished building: $@'
+	@echo ' '
+
+BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3.hex: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS)
+	arm-none-eabi-objcopy  -O ihex $(EXECUTABLES) "BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3.hex"
+	@echo 'Finished building: $@'
+	@echo ' '
+
+BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3.bin: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS)
+	arm-none-eabi-objcopy  -O binary $(EXECUTABLES) "BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3.bin"
+	@echo 'Finished building: $@'
+	@echo ' '
+
+# Other Targets
+clean:
+	-$(RM) BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3.bin BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3.elf BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3.hex BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3.list BHBF_Swing_Rust_V5_1_CAN1_2_Sandblast3.map default.size.stdout
+	-@echo ' '
+
+secondary-outputs: $(SIZE_OUTPUT) $(OBJDUMP_LIST) $(OBJCOPY_HEX) $(OBJCOPY_BIN)
+
+fail-specified-linker-script-missing:
+	@echo 'Error: Cannot find the specified linker script. Check the linker settings in the build configuration.'
+	@exit 2
+
+warn-no-linker-script-specified:
+	@echo 'Warning: No linker script specified. Check the linker settings in the build configuration.'
+
+.PHONY: all clean dependents main-build fail-specified-linker-script-missing warn-no-linker-script-specified
+
+-include ../makefile.targets
diff --git a/Debug/objects.list b/Debug/objects.list
new file mode 100644
index 0000000..5f70abb
--- /dev/null
+++ b/Debug/objects.list
@@ -0,0 +1,90 @@
+"./Core/BASE/Protobuf/PSource/bsp_CV.pb.o"
+"./Core/BASE/Protobuf/PSource/bsp_Cmd.pb.o"
+"./Core/BASE/Protobuf/PSource/bsp_Error.pb.o"
+"./Core/BASE/Protobuf/PSource/bsp_GV.pb.o"
+"./Core/BASE/Protobuf/PSource/bsp_IAP.pb.o"
+"./Core/BASE/Protobuf/PSource/bsp_IO.pb.o"
+"./Core/BASE/Protobuf/PSource/bsp_IV.pb.o"
+"./Core/BASE/Protobuf/PSource/bsp_PV.pb.o"
+"./Core/BASE/Protobuf/PSource/bsp_ReCmd.pb.o"
+"./Core/BASE/Protobuf/PSource/msp_CMCU.pb.o"
+"./Core/BASE/Protobuf/PSource/msp_KS206.pb.o"
+"./Core/BASE/Protobuf/PSource/msp_MFOG40_Gyroscope.pb.o"
+"./Core/BASE/Protobuf/PSource/msp_MK32.pb.o"
+"./Core/BASE/Protobuf/PSource/msp_Motor.pb.o"
+"./Core/BASE/Protobuf/PSource/msp_TL720D.pb.o"
+"./Core/BASE/Protobuf/PSource/msp_ZQ_MotorParameters.pb.o"
+"./Core/BASE/Src/BSP/BHBF_ROBOT.o"
+"./Core/BASE/Src/BSP/bsp_DLT_Log.o"
+"./Core/BASE/Src/BSP/bsp_EEPROM.o"
+"./Core/BASE/Src/BSP/bsp_Error_Detect.o"
+"./Core/BASE/Src/BSP/bsp_FDCAN.o"
+"./Core/BASE/Src/BSP/bsp_GPIO.o"
+"./Core/BASE/Src/BSP/bsp_INTERCALL.o"
+"./Core/BASE/Src/BSP/bsp_MB_host.o"
+"./Core/BASE/Src/BSP/bsp_TIMER.o"
+"./Core/BASE/Src/BSP/bsp_UART.o"
+"./Core/BASE/Src/BSP/bsp_UpperComputer_Handler.o"
+"./Core/BASE/Src/BSP/bsp_client_setting.o"
+"./Core/BASE/Src/BSP/bsp_com_helper.o"
+"./Core/BASE/Src/BSP/bsp_cpu_flash.o"
+"./Core/BASE/Src/BSP/bsp_decode_command.o"
+"./Core/BASE/Src/BSP/bsp_qspi_w25q128.o"
+"./Core/BASE/Src/BSP/pb_common.o"
+"./Core/BASE/Src/BSP/pb_decode.o"
+"./Core/BASE/Src/BSP/pb_encode.o"
+"./Core/BASE/Src/BSP/DLT/DLTuc.o"
+"./Core/BASE/Src/MSP/msp_Blast_Machine.o"
+"./Core/BASE/Src/MSP/msp_CMCUU.o"
+"./Core/BASE/Src/MSP/msp_KS206.o"
+"./Core/BASE/Src/MSP/msp_MF_Gyroscope.o"
+"./Core/BASE/Src/MSP/msp_MK32_1.o"
+"./Core/BASE/Src/MSP/msp_PID.o"
+"./Core/BASE/Src/MSP/msp_TL720D.o"
+"./Core/BASE/Src/MSP/msp_TTMotor_ZQ.o"
+"./Core/BASE/Src/MSP/msp_WH_LTE_7S0.o"
+"./Core/Src/adc.o"
+"./Core/Src/dma.o"
+"./Core/Src/eth.o"
+"./Core/Src/fdcan.o"
+"./Core/Src/fsm.o"
+"./Core/Src/gpio.o"
+"./Core/Src/i2c.o"
+"./Core/Src/main.o"
+"./Core/Src/motors.o"
+"./Core/Src/quadspi.o"
+"./Core/Src/robot_state.o"
+"./Core/Src/stm32h7xx_hal_msp.o"
+"./Core/Src/stm32h7xx_it.o"
+"./Core/Src/syscalls.o"
+"./Core/Src/sysmem.o"
+"./Core/Src/system_stm32h7xx.o"
+"./Core/Src/tim.o"
+"./Core/Src/usart.o"
+"./Core/Startup/startup_stm32h743vgtx.o"
+"./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o"
+"./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.o"
+"./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.o"
+"./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o"
+"./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o"
+"./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o"
+"./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o"
+"./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o"
+"./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o"
+"./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.o"
+"./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o"
+"./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o"
+"./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o"
+"./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o"
+"./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o"
+"./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o"
+"./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o"
+"./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o"
+"./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o"
+"./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.o"
+"./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o"
+"./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o"
+"./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o"
+"./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o"
+"./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.o"
+"./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.o"
diff --git a/Debug/objects.mk b/Debug/objects.mk
new file mode 100644
index 0000000..94e86f7
--- /dev/null
+++ b/Debug/objects.mk
@@ -0,0 +1,9 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+# Toolchain: GNU Tools for STM32 (12.3.rel1)
+################################################################################
+
+USER_OBJS :=
+
+LIBS :=
+
diff --git a/Debug/sources.mk b/Debug/sources.mk
new file mode 100644
index 0000000..833018e
--- /dev/null
+++ b/Debug/sources.mk
@@ -0,0 +1,34 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+# Toolchain: GNU Tools for STM32 (12.3.rel1)
+################################################################################
+
+ELF_SRCS := 
+OBJ_SRCS := 
+S_SRCS := 
+C_SRCS := 
+S_UPPER_SRCS := 
+O_SRCS := 
+CYCLO_FILES := 
+OBJCOPY_HEX := 
+SIZE_OUTPUT := 
+OBJDUMP_LIST := 
+SU_FILES := 
+EXECUTABLES := 
+OBJS := 
+MAP_FILES := 
+S_DEPS := 
+S_UPPER_DEPS := 
+C_DEPS := 
+OBJCOPY_BIN := 
+
+# Every subdirectory with source files must be described here
+SUBDIRS := \
+Core/BASE/Protobuf/PSource \
+Core/BASE/Src/BSP \
+Core/BASE/Src/BSP/DLT \
+Core/BASE/Src/MSP \
+Core/Src \
+Core/Startup \
+Drivers/STM32H7xx_HAL_Driver/Src \
+