CAN_H7_Bootloader.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 00000298 08000000 08000000 00010000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 00005468 08000298 08000298 00010298 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 0000006c 08005700 08005700 00015700 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .init_array 00000004 0800576c 0800576c 0001576c 2**2 CONTENTS, ALLOC, LOAD, DATA 4 .fini_array 00000004 08005770 08005770 00015770 2**2 CONTENTS, ALLOC, LOAD, DATA 5 .data 00000010 24000000 08005774 00020000 2**2 CONTENTS, ALLOC, LOAD, DATA 6 .bss 00000370 24000010 08005784 00020010 2**2 ALLOC 7 ._user_heap_stack 00000600 24000380 08005784 00020380 2**0 ALLOC 8 .ARM.attributes 0000002e 00000000 00000000 00020010 2**0 CONTENTS, READONLY 9 .debug_info 00010553 00000000 00000000 0002003e 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 10 .debug_abbrev 000026c9 00000000 00000000 00030591 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 11 .debug_aranges 00000d18 00000000 00000000 00032c60 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 12 .debug_ranges 00000c10 00000000 00000000 00033978 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_macro 00036ee1 00000000 00000000 00034588 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_line 0001061e 00000000 00000000 0006b469 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_str 001598f2 00000000 00000000 0007ba87 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .comment 00000050 00000000 00000000 001d5379 2**0 CONTENTS, READONLY 17 .debug_frame 00003464 00000000 00000000 001d53cc 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 08000298 <__do_global_dtors_aux>: 8000298: b510 push {r4, lr} 800029a: 4c05 ldr r4, [pc, #20] ; (80002b0 <__do_global_dtors_aux+0x18>) 800029c: 7823 ldrb r3, [r4, #0] 800029e: b933 cbnz r3, 80002ae <__do_global_dtors_aux+0x16> 80002a0: 4b04 ldr r3, [pc, #16] ; (80002b4 <__do_global_dtors_aux+0x1c>) 80002a2: b113 cbz r3, 80002aa <__do_global_dtors_aux+0x12> 80002a4: 4804 ldr r0, [pc, #16] ; (80002b8 <__do_global_dtors_aux+0x20>) 80002a6: f3af 8000 nop.w 80002aa: 2301 movs r3, #1 80002ac: 7023 strb r3, [r4, #0] 80002ae: bd10 pop {r4, pc} 80002b0: 24000010 .word 0x24000010 80002b4: 00000000 .word 0x00000000 80002b8: 080056e8 .word 0x080056e8 080002bc : 80002bc: b508 push {r3, lr} 80002be: 4b03 ldr r3, [pc, #12] ; (80002cc ) 80002c0: b11b cbz r3, 80002ca 80002c2: 4903 ldr r1, [pc, #12] ; (80002d0 ) 80002c4: 4803 ldr r0, [pc, #12] ; (80002d4 ) 80002c6: f3af 8000 nop.w 80002ca: bd08 pop {r3, pc} 80002cc: 00000000 .word 0x00000000 80002d0: 24000014 .word 0x24000014 80002d4: 080056e8 .word 0x080056e8 080002d8 : * 形 参: 无 * 返 回 值: 无 ********************************************************************************************************* */ void bsp_InitCan2(void) { 80002d8: b580 push {r7, lr} 80002da: af00 add r7, sp, #0 MX_FDCAN2_Init(); 80002dc: f000 fc5a bl 8000b94 } 80002e0: bf00 nop 80002e2: bd80 pop {r7, pc} 080002e4 : * 形 参: 无 * 返 回 值: 无 ********************************************************************************************************* */ void bsp_DeInitCan2(void) { 80002e4: b580 push {r7, lr} 80002e6: af00 add r7, sp, #0 HAL_FDCAN_MspDeInit(&hfdcan2); 80002e8: 4802 ldr r0, [pc, #8] ; (80002f4 ) 80002ea: f000 fd3f bl 8000d6c } 80002ee: bf00 nop 80002f0: bd80 pop {r7, pc} 80002f2: bf00 nop 80002f4: 240002bc .word 0x240002bc 080002f8 : * 形 参: hfdcan * 返 回 值: 无 ********************************************************************************************************* */ void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs) { 80002f8: b580 push {r7, lr} 80002fa: b082 sub sp, #8 80002fc: af00 add r7, sp, #0 80002fe: 6078 str r0, [r7, #4] 8000300: 6039 str r1, [r7, #0] if (hfdcan == &hfdcan2) 8000302: 687b ldr r3, [r7, #4] 8000304: 4a19 ldr r2, [pc, #100] ; (800036c ) 8000306: 4293 cmp r3, r2 8000308: d12b bne.n 8000362 { /* Retreive Rx messages from RX FIFO0 */ if(HAL_FDCAN_GetRxMessage(hfdcan, FDCAN_RX_FIFO0, &g_Can2RxHeader, g_Can2RxData)==HAL_OK) 800030a: 4b19 ldr r3, [pc, #100] ; (8000370 ) 800030c: 4a19 ldr r2, [pc, #100] ; (8000374 ) 800030e: 2140 movs r1, #64 ; 0x40 8000310: 6878 ldr r0, [r7, #4] 8000312: f001 fb8f bl 8001a34 8000316: 4603 mov r3, r0 8000318: 2b00 cmp r3, #0 800031a: d122 bne.n 8000362 { /* Activate Rx FIFO 0 watermark notification */ HAL_FDCAN_ActivateNotification(hfdcan, FDCAN_IT_RX_FIFO0_WATERMARK, 0); 800031c: 2200 movs r2, #0 800031e: 2102 movs r1, #2 8000320: 6878 ldr r0, [r7, #4] 8000322: f001 fcf5 bl 8001d10 if(g_Can2RxHeader.Identifier == 0x110 && g_Can2RxHeader.IdType == FDCAN_STANDARD_ID) 8000326: 4b13 ldr r3, [pc, #76] ; (8000374 ) 8000328: 681b ldr r3, [r3, #0] 800032a: f5b3 7f88 cmp.w r3, #272 ; 0x110 800032e: d10a bne.n 8000346 8000330: 4b10 ldr r3, [pc, #64] ; (8000374 ) 8000332: 685b ldr r3, [r3, #4] 8000334: 2b00 cmp r3, #0 8000336: d106 bne.n 8000346 { if(g_Can2RxData[0]==0x55) 8000338: 4b0d ldr r3, [pc, #52] ; (8000370 ) 800033a: 781b ldrb r3, [r3, #0] 800033c: 2b55 cmp r3, #85 ; 0x55 800033e: d102 bne.n 8000346 { Update_EN = 1; 8000340: 4b0d ldr r3, [pc, #52] ; (8000378 ) 8000342: 2201 movs r2, #1 8000344: 701a strb r2, [r3, #0] } } if (g_Can2RxHeader.Identifier == 0x222 && g_Can2RxHeader.IdType == FDCAN_STANDARD_ID) 8000346: 4b0b ldr r3, [pc, #44] ; (8000374 ) 8000348: 681b ldr r3, [r3, #0] 800034a: f240 2222 movw r2, #546 ; 0x222 800034e: 4293 cmp r3, r2 8000350: d107 bne.n 8000362 8000352: 4b08 ldr r3, [pc, #32] ; (8000374 ) 8000354: 685b ldr r3, [r3, #4] 8000356: 2b00 cmp r3, #0 8000358: d103 bne.n 8000362 { bsp_PutMsg(MSG_CAN2_RX, 0); /* 发消息收到数据包，结果在g_Can1RxHeader， g_Can1RxData */ 800035a: 2100 movs r1, #0 800035c: 2004 movs r0, #4 800035e: f000 fa3f bl 80007e0 } } } } 8000362: bf00 nop 8000364: 3708 adds r7, #8 8000366: 46bd mov sp, r7 8000368: bd80 pop {r7, pc} 800036a: bf00 nop 800036c: 240002bc .word 0x240002bc 8000370: 240000f4 .word 0x240000f4 8000374: 240000cc .word 0x240000cc 8000378: 2400035c .word 0x2400035c 0800037c : * 返 回 值: 无 ********************************************************************************************************* */ FDCAN_TxHeaderTypeDef TxHeader; void can2_SendPacket(uint8_t *_DataBuf, uint8_t _Len) { 800037c: b580 push {r7, lr} 800037e: b082 sub sp, #8 8000380: af00 add r7, sp, #0 8000382: 6078 str r0, [r7, #4] 8000384: 460b mov r3, r1 8000386: 70fb strb r3, [r7, #3] if (_Len > 8) 8000388: 78fb ldrb r3, [r7, #3] 800038a: 2b08 cmp r3, #8 800038c: d822 bhi.n 80003d4 { return; } /* Prepare Tx Header */ TxHeader.Identifier = 0x1FF; 800038e: 4b13 ldr r3, [pc, #76] ; (80003dc ) 8000390: f240 12ff movw r2, #511 ; 0x1ff 8000394: 601a str r2, [r3, #0] TxHeader.IdType = FDCAN_STANDARD_ID; 8000396: 4b11 ldr r3, [pc, #68] ; (80003dc ) 8000398: 2200 movs r2, #0 800039a: 605a str r2, [r3, #4] TxHeader.TxFrameType = FDCAN_DATA_FRAME; 800039c: 4b0f ldr r3, [pc, #60] ; (80003dc ) 800039e: 2200 movs r2, #0 80003a0: 609a str r2, [r3, #8] TxHeader.DataLength = (uint32_t)_Len << 16; 80003a2: 78fb ldrb r3, [r7, #3] 80003a4: 041b lsls r3, r3, #16 80003a6: 4a0d ldr r2, [pc, #52] ; (80003dc ) 80003a8: 60d3 str r3, [r2, #12] TxHeader.ErrorStateIndicator = FDCAN_ESI_ACTIVE; 80003aa: 4b0c ldr r3, [pc, #48] ; (80003dc ) 80003ac: 2200 movs r2, #0 80003ae: 611a str r2, [r3, #16] TxHeader.BitRateSwitch = FDCAN_BRS_OFF; 80003b0: 4b0a ldr r3, [pc, #40] ; (80003dc ) 80003b2: 2200 movs r2, #0 80003b4: 615a str r2, [r3, #20] TxHeader.FDFormat = FDCAN_CLASSIC_CAN; 80003b6: 4b09 ldr r3, [pc, #36] ; (80003dc ) 80003b8: 2200 movs r2, #0 80003ba: 619a str r2, [r3, #24] TxHeader.TxEventFifoControl = FDCAN_NO_TX_EVENTS; 80003bc: 4b07 ldr r3, [pc, #28] ; (80003dc ) 80003be: 2200 movs r2, #0 80003c0: 61da str r2, [r3, #28] TxHeader.MessageMarker = 0; 80003c2: 4b06 ldr r3, [pc, #24] ; (80003dc ) 80003c4: 2200 movs r2, #0 80003c6: 621a str r2, [r3, #32] /* Add messages to TX FIFO */ HAL_FDCAN_AddMessageToTxFifoQ(&hfdcan2, &TxHeader, _DataBuf); 80003c8: 687a ldr r2, [r7, #4] 80003ca: 4904 ldr r1, [pc, #16] ; (80003dc ) 80003cc: 4804 ldr r0, [pc, #16] ; (80003e0 ) 80003ce: f001 fad6 bl 800197e 80003d2: e000 b.n 80003d6 return; 80003d4: bf00 nop } 80003d6: 3708 adds r7, #8 80003d8: 46bd mov sp, r7 80003da: bd80 pop {r7, pc} 80003dc: 24000134 .word 0x24000134 80003e0: 240002bc .word 0x240002bc 080003e4 : * 形 参: hfdcan * 返 回 值: 无 ********************************************************************************************************* */ void FDCAN1_IT0_IRQHandler(void) { 80003e4: b580 push {r7, lr} 80003e6: af00 add r7, sp, #0 HAL_FDCAN_IRQHandler(&hfdcan1); 80003e8: 4802 ldr r0, [pc, #8] ; (80003f4 ) 80003ea: f001 fd0b bl 8001e04 } 80003ee: bf00 nop 80003f0: bd80 pop {r7, pc} 80003f2: bf00 nop 80003f4: 2400002c .word 0x2400002c 080003f8 : void FDCAN1_IT1_IRQHandler(void) { 80003f8: b580 push {r7, lr} 80003fa: af00 add r7, sp, #0 HAL_FDCAN_IRQHandler(&hfdcan1); 80003fc: 4802 ldr r0, [pc, #8] ; (8000408 ) 80003fe: f001 fd01 bl 8001e04 } 8000402: bf00 nop 8000404: bd80 pop {r7, pc} 8000406: bf00 nop 8000408: 2400002c .word 0x2400002c 0800040c : void FDCAN2_IT1_IRQHandler(void) { 800040c: b580 push {r7, lr} 800040e: af00 add r7, sp, #0 HAL_FDCAN_IRQHandler(&hfdcan2); 8000410: 4802 ldr r0, [pc, #8] ; (800041c ) 8000412: f001 fcf7 bl 8001e04 } 8000416: bf00 nop 8000418: bd80 pop {r7, pc} 800041a: bf00 nop 800041c: 240002bc .word 0x240002bc 08000420 : void FDCAN_CAL_IRQHandler(void) { 8000420: b580 push {r7, lr} 8000422: af00 add r7, sp, #0 HAL_FDCAN_IRQHandler(&hfdcan1); 8000424: 4803 ldr r0, [pc, #12] ; (8000434 ) 8000426: f001 fced bl 8001e04 HAL_FDCAN_IRQHandler(&hfdcan2); // ??? 800042a: 4803 ldr r0, [pc, #12] ; (8000438 ) 800042c: f001 fcea bl 8001e04 } 8000430: bf00 nop 8000432: bd80 pop {r7, pc} 8000434: 2400002c .word 0x2400002c 8000438: 240002bc .word 0x240002bc 0800043c : * 形 参: 无 * 返 回 值: 扇区号（0-7) ********************************************************************************************************* */ uint32_t bsp_GetSector(uint32_t Address) { 800043c: b480 push {r7} 800043e: b085 sub sp, #20 8000440: af00 add r7, sp, #0 8000442: 6078 str r0, [r7, #4] uint32_t sector = 0; 8000444: 2300 movs r3, #0 8000446: 60fb str r3, [r7, #12] if (((Address < ADDR_FLASH_SECTOR_1_BANK1) && (Address >= ADDR_FLASH_SECTOR_0_BANK1)) || \ 8000448: 687b ldr r3, [r7, #4] 800044a: 4a50 ldr r2, [pc, #320] ; (800058c ) 800044c: 4293 cmp r3, r2 800044e: d803 bhi.n 8000458 8000450: 687b ldr r3, [r7, #4] 8000452: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000 8000456: d207 bcs.n 8000468 8000458: 687b ldr r3, [r7, #4] 800045a: 4a4d ldr r2, [pc, #308] ; (8000590 ) 800045c: 4293 cmp r3, r2 800045e: d806 bhi.n 800046e ((Address < ADDR_FLASH_SECTOR_1_BANK2) && (Address >= ADDR_FLASH_SECTOR_0_BANK2))) 8000460: 687b ldr r3, [r7, #4] 8000462: f1b3 6f01 cmp.w r3, #135266304 ; 0x8100000 8000466: d302 bcc.n 800046e { sector = FLASH_SECTOR_0; 8000468: 2300 movs r3, #0 800046a: 60fb str r3, [r7, #12] 800046c: e086 b.n 800057c } else if (((Address < ADDR_FLASH_SECTOR_2_BANK1) && (Address >= ADDR_FLASH_SECTOR_1_BANK1)) || \ 800046e: 687b ldr r3, [r7, #4] 8000470: 4a48 ldr r2, [pc, #288] ; (8000594 ) 8000472: 4293 cmp r3, r2 8000474: d803 bhi.n 800047e 8000476: 687b ldr r3, [r7, #4] 8000478: 4a44 ldr r2, [pc, #272] ; (800058c ) 800047a: 4293 cmp r3, r2 800047c: d807 bhi.n 800048e 800047e: 687b ldr r3, [r7, #4] 8000480: 4a45 ldr r2, [pc, #276] ; (8000598 ) 8000482: 4293 cmp r3, r2 8000484: d806 bhi.n 8000494 ((Address < ADDR_FLASH_SECTOR_2_BANK2) && (Address >= ADDR_FLASH_SECTOR_1_BANK2))) 8000486: 687b ldr r3, [r7, #4] 8000488: 4a41 ldr r2, [pc, #260] ; (8000590 ) 800048a: 4293 cmp r3, r2 800048c: d902 bls.n 8000494 { sector = FLASH_SECTOR_1; 800048e: 2301 movs r3, #1 8000490: 60fb str r3, [r7, #12] 8000492: e073 b.n 800057c } else if (((Address < ADDR_FLASH_SECTOR_3_BANK1) && (Address >= ADDR_FLASH_SECTOR_2_BANK1)) || \ 8000494: 687b ldr r3, [r7, #4] 8000496: 4a41 ldr r2, [pc, #260] ; (800059c ) 8000498: 4293 cmp r3, r2 800049a: d803 bhi.n 80004a4 800049c: 687b ldr r3, [r7, #4] 800049e: 4a3d ldr r2, [pc, #244] ; (8000594 ) 80004a0: 4293 cmp r3, r2 80004a2: d807 bhi.n 80004b4 80004a4: 687b ldr r3, [r7, #4] 80004a6: 4a3e ldr r2, [pc, #248] ; (80005a0 ) 80004a8: 4293 cmp r3, r2 80004aa: d806 bhi.n 80004ba ((Address < ADDR_FLASH_SECTOR_3_BANK2) && (Address >= ADDR_FLASH_SECTOR_2_BANK2))) 80004ac: 687b ldr r3, [r7, #4] 80004ae: 4a3a ldr r2, [pc, #232] ; (8000598 ) 80004b0: 4293 cmp r3, r2 80004b2: d902 bls.n 80004ba { sector = FLASH_SECTOR_2; 80004b4: 2302 movs r3, #2 80004b6: 60fb str r3, [r7, #12] 80004b8: e060 b.n 800057c } else if (((Address < ADDR_FLASH_SECTOR_4_BANK1) && (Address >= ADDR_FLASH_SECTOR_3_BANK1)) || \ 80004ba: 687b ldr r3, [r7, #4] 80004bc: 4a39 ldr r2, [pc, #228] ; (80005a4 ) 80004be: 4293 cmp r3, r2 80004c0: d803 bhi.n 80004ca 80004c2: 687b ldr r3, [r7, #4] 80004c4: 4a35 ldr r2, [pc, #212] ; (800059c ) 80004c6: 4293 cmp r3, r2 80004c8: d807 bhi.n 80004da 80004ca: 687b ldr r3, [r7, #4] 80004cc: 4a36 ldr r2, [pc, #216] ; (80005a8 ) 80004ce: 4293 cmp r3, r2 80004d0: d806 bhi.n 80004e0 ((Address < ADDR_FLASH_SECTOR_4_BANK2) && (Address >= ADDR_FLASH_SECTOR_3_BANK2))) 80004d2: 687b ldr r3, [r7, #4] 80004d4: 4a32 ldr r2, [pc, #200] ; (80005a0 ) 80004d6: 4293 cmp r3, r2 80004d8: d902 bls.n 80004e0 { sector = FLASH_SECTOR_3; 80004da: 2303 movs r3, #3 80004dc: 60fb str r3, [r7, #12] 80004de: e04d b.n 800057c } else if (((Address < ADDR_FLASH_SECTOR_5_BANK1) && (Address >= ADDR_FLASH_SECTOR_4_BANK1)) || \ 80004e0: 687b ldr r3, [r7, #4] 80004e2: 4a32 ldr r2, [pc, #200] ; (80005ac ) 80004e4: 4293 cmp r3, r2 80004e6: d803 bhi.n 80004f0 80004e8: 687b ldr r3, [r7, #4] 80004ea: 4a2e ldr r2, [pc, #184] ; (80005a4 ) 80004ec: 4293 cmp r3, r2 80004ee: d807 bhi.n 8000500 80004f0: 687b ldr r3, [r7, #4] 80004f2: 4a2f ldr r2, [pc, #188] ; (80005b0 ) 80004f4: 4293 cmp r3, r2 80004f6: d806 bhi.n 8000506 ((Address < ADDR_FLASH_SECTOR_5_BANK2) && (Address >= ADDR_FLASH_SECTOR_4_BANK2))) 80004f8: 687b ldr r3, [r7, #4] 80004fa: 4a2b ldr r2, [pc, #172] ; (80005a8 ) 80004fc: 4293 cmp r3, r2 80004fe: d902 bls.n 8000506 { sector = FLASH_SECTOR_4; 8000500: 2304 movs r3, #4 8000502: 60fb str r3, [r7, #12] 8000504: e03a b.n 800057c } else if (((Address < ADDR_FLASH_SECTOR_6_BANK1) && (Address >= ADDR_FLASH_SECTOR_5_BANK1)) || \ 8000506: 687b ldr r3, [r7, #4] 8000508: 4a2a ldr r2, [pc, #168] ; (80005b4 ) 800050a: 4293 cmp r3, r2 800050c: d803 bhi.n 8000516 800050e: 687b ldr r3, [r7, #4] 8000510: 4a26 ldr r2, [pc, #152] ; (80005ac ) 8000512: 4293 cmp r3, r2 8000514: d807 bhi.n 8000526 8000516: 687b ldr r3, [r7, #4] 8000518: 4a27 ldr r2, [pc, #156] ; (80005b8 ) 800051a: 4293 cmp r3, r2 800051c: d806 bhi.n 800052c ((Address < ADDR_FLASH_SECTOR_6_BANK2) && (Address >= ADDR_FLASH_SECTOR_5_BANK2))) 800051e: 687b ldr r3, [r7, #4] 8000520: 4a23 ldr r2, [pc, #140] ; (80005b0 ) 8000522: 4293 cmp r3, r2 8000524: d902 bls.n 800052c { sector = FLASH_SECTOR_5; 8000526: 2305 movs r3, #5 8000528: 60fb str r3, [r7, #12] 800052a: e027 b.n 800057c } else if (((Address < ADDR_FLASH_SECTOR_7_BANK1) && (Address >= ADDR_FLASH_SECTOR_6_BANK1)) || \ 800052c: 687b ldr r3, [r7, #4] 800052e: 4a23 ldr r2, [pc, #140] ; (80005bc ) 8000530: 4293 cmp r3, r2 8000532: d803 bhi.n 800053c 8000534: 687b ldr r3, [r7, #4] 8000536: 4a1f ldr r2, [pc, #124] ; (80005b4 ) 8000538: 4293 cmp r3, r2 800053a: d807 bhi.n 800054c 800053c: 687b ldr r3, [r7, #4] 800053e: 4a20 ldr r2, [pc, #128] ; (80005c0 ) 8000540: 4293 cmp r3, r2 8000542: d806 bhi.n 8000552 ((Address < ADDR_FLASH_SECTOR_7_BANK2) && (Address >= ADDR_FLASH_SECTOR_6_BANK2))) 8000544: 687b ldr r3, [r7, #4] 8000546: 4a1c ldr r2, [pc, #112] ; (80005b8 ) 8000548: 4293 cmp r3, r2 800054a: d902 bls.n 8000552 { sector = FLASH_SECTOR_6; 800054c: 2306 movs r3, #6 800054e: 60fb str r3, [r7, #12] 8000550: e014 b.n 800057c } else if (((Address < ADDR_FLASH_SECTOR_0_BANK2) && (Address >= ADDR_FLASH_SECTOR_7_BANK1)) || \ 8000552: 687b ldr r3, [r7, #4] 8000554: f1b3 6f01 cmp.w r3, #135266304 ; 0x8100000 8000558: d203 bcs.n 8000562 800055a: 687b ldr r3, [r7, #4] 800055c: 4a17 ldr r2, [pc, #92] ; (80005bc ) 800055e: 4293 cmp r3, r2 8000560: d807 bhi.n 8000572 8000562: 687b ldr r3, [r7, #4] 8000564: 4a17 ldr r2, [pc, #92] ; (80005c4 ) 8000566: 4293 cmp r3, r2 8000568: d806 bhi.n 8000578 ((Address < CPU_FLASH_END_ADDR) && (Address >= ADDR_FLASH_SECTOR_7_BANK2))) 800056a: 687b ldr r3, [r7, #4] 800056c: 4a14 ldr r2, [pc, #80] ; (80005c0 ) 800056e: 4293 cmp r3, r2 8000570: d902 bls.n 8000578 { sector = FLASH_SECTOR_7; 8000572: 2307 movs r3, #7 8000574: 60fb str r3, [r7, #12] 8000576: e001 b.n 800057c } else { sector = FLASH_SECTOR_7; 8000578: 2307 movs r3, #7 800057a: 60fb str r3, [r7, #12] } return sector; 800057c: 68fb ldr r3, [r7, #12] } 800057e: 4618 mov r0, r3 8000580: 3714 adds r7, #20 8000582: 46bd mov sp, r7 8000584: f85d 7b04 ldr.w r7, [sp], #4 8000588: 4770 bx lr 800058a: bf00 nop 800058c: 0801ffff .word 0x0801ffff 8000590: 0811ffff .word 0x0811ffff 8000594: 0803ffff .word 0x0803ffff 8000598: 0813ffff .word 0x0813ffff 800059c: 0805ffff .word 0x0805ffff 80005a0: 0815ffff .word 0x0815ffff 80005a4: 0807ffff .word 0x0807ffff 80005a8: 0817ffff .word 0x0817ffff 80005ac: 0809ffff .word 0x0809ffff 80005b0: 0819ffff .word 0x0819ffff 80005b4: 080bffff .word 0x080bffff 80005b8: 081bffff .word 0x081bffff 80005bc: 080dffff .word 0x080dffff 80005c0: 081dffff .word 0x081dffff 80005c4: 081ffffe .word 0x081ffffe 080005c8 : * FLASH_REQ_ERASE 2 Flash需要先擦除,再写 * FLASH_PARAM_ERR 3 函数参数错误 ********************************************************************************************************* */ uint8_t bsp_CmpCpuFlash(uint32_t _ulFlashAddr, uint8_t *_ucpBuf, uint32_t _ulSize) { 80005c8: b480 push {r7} 80005ca: b087 sub sp, #28 80005cc: af00 add r7, sp, #0 80005ce: 60f8 str r0, [r7, #12] 80005d0: 60b9 str r1, [r7, #8] 80005d2: 607a str r2, [r7, #4] uint32_t i; uint8_t ucIsEqu; /* 相等标志 */ uint8_t ucByte; /* 如果偏移地址超过芯片容量，则不改写输出缓冲区 */ if (_ulFlashAddr + _ulSize > CPU_FLASH_BASE_ADDR + CPU_FLASH_SIZE) 80005d4: 68fa ldr r2, [r7, #12] 80005d6: 687b ldr r3, [r7, #4] 80005d8: 4413 add r3, r2 80005da: f1b3 6f02 cmp.w r3, #136314880 ; 0x8200000 80005de: d901 bls.n 80005e4 { return FLASH_PARAM_ERR; /*　函数参数错误　*/ 80005e0: 2303 movs r3, #3 80005e2: e02b b.n 800063c } /* 长度为0时返回正确 */ if (_ulSize == 0) 80005e4: 687b ldr r3, [r7, #4] 80005e6: 2b00 cmp r3, #0 80005e8: d101 bne.n 80005ee { return FLASH_IS_EQU; /* Flash内容和待写入的数据相等 */ 80005ea: 2300 movs r3, #0 80005ec: e026 b.n 800063c } ucIsEqu = 1; /* 先假设所有字节和待写入的数据相等，如果遇到任何一个不相等，则设置为 0 */ 80005ee: 2301 movs r3, #1 80005f0: 74fb strb r3, [r7, #19] for (i = 0; i < _ulSize; i++) 80005f2: 2300 movs r3, #0 80005f4: 617b str r3, [r7, #20] 80005f6: e017 b.n 8000628 { ucByte = *(uint8_t *)_ulFlashAddr; 80005f8: 68fb ldr r3, [r7, #12] 80005fa: 781b ldrb r3, [r3, #0] 80005fc: 74bb strb r3, [r7, #18] if (ucByte != *_ucpBuf) 80005fe: 68bb ldr r3, [r7, #8] 8000600: 781b ldrb r3, [r3, #0] 8000602: 7cba ldrb r2, [r7, #18] 8000604: 429a cmp r2, r3 8000606: d006 beq.n 8000616 { if (ucByte != 0xFF) 8000608: 7cbb ldrb r3, [r7, #18] 800060a: 2bff cmp r3, #255 ; 0xff 800060c: d001 beq.n 8000612 { return FLASH_REQ_ERASE; /* 需要擦除后再写 */ 800060e: 2302 movs r3, #2 8000610: e014 b.n 800063c } else { ucIsEqu = 0; /* 不相等，需要写 */ 8000612: 2300 movs r3, #0 8000614: 74fb strb r3, [r7, #19] } } _ulFlashAddr++; 8000616: 68fb ldr r3, [r7, #12] 8000618: 3301 adds r3, #1 800061a: 60fb str r3, [r7, #12] _ucpBuf++; 800061c: 68bb ldr r3, [r7, #8] 800061e: 3301 adds r3, #1 8000620: 60bb str r3, [r7, #8] for (i = 0; i < _ulSize; i++) 8000622: 697b ldr r3, [r7, #20] 8000624: 3301 adds r3, #1 8000626: 617b str r3, [r7, #20] 8000628: 697a ldr r2, [r7, #20] 800062a: 687b ldr r3, [r7, #4] 800062c: 429a cmp r2, r3 800062e: d3e3 bcc.n 80005f8 } if (ucIsEqu == 1) 8000630: 7cfb ldrb r3, [r7, #19] 8000632: 2b01 cmp r3, #1 8000634: d101 bne.n 800063a { return FLASH_IS_EQU; /* Flash内容和待写入的数据相等，不需要擦除和写操作 */ 8000636: 2300 movs r3, #0 8000638: e000 b.n 800063c } else { return FLASH_REQ_WRITE; /* Flash不需要擦除，直接写 */ 800063a: 2301 movs r3, #1 } } 800063c: 4618 mov r0, r3 800063e: 371c adds r7, #28 8000640: 46bd mov sp, r7 8000642: f85d 7b04 ldr.w r7, [sp], #4 8000646: 4770 bx lr 08000648 : * HAL_TIMEOUT = 0x03 * ********************************************************************************************************* */ uint8_t bsp_EraseCpuFlash(uint32_t _ulFlashAddr) { 8000648: b580 push {r7, lr} 800064a: b08c sub sp, #48 ; 0x30 800064c: af00 add r7, sp, #0 800064e: 6078 str r0, [r7, #4] uint32_t FirstSector = 0, NbOfSectors = 0; 8000650: 2300 movs r3, #0 8000652: 62fb str r3, [r7, #44] ; 0x2c 8000654: 2300 movs r3, #0 8000656: 62bb str r3, [r7, #40] ; 0x28 FLASH_EraseInitTypeDef EraseInitStruct; uint32_t SECTORError = 0; 8000658: 2300 movs r3, #0 800065a: 60fb str r3, [r7, #12] uint8_t re; /* 解锁 */ HAL_FLASH_Unlock(); 800065c: f002 f972 bl 8002944 /* 获取此地址所在的扇区 */ FirstSector = bsp_GetSector(_ulFlashAddr); 8000660: 6878 ldr r0, [r7, #4] 8000662: f7ff feeb bl 800043c 8000666: 62f8 str r0, [r7, #44] ; 0x2c /* 固定1个扇区 */ NbOfSectors = 1; 8000668: 2301 movs r3, #1 800066a: 62bb str r3, [r7, #40] ; 0x28 /* 擦除扇区配置 */ EraseInitStruct.TypeErase = FLASH_TYPEERASE_SECTORS; 800066c: 2300 movs r3, #0 800066e: 613b str r3, [r7, #16] EraseInitStruct.VoltageRange = FLASH_VOLTAGE_RANGE_3; 8000670: 2320 movs r3, #32 8000672: 623b str r3, [r7, #32] if (_ulFlashAddr >= ADDR_FLASH_SECTOR_0_BANK2) 8000674: 687b ldr r3, [r7, #4] 8000676: f1b3 6f01 cmp.w r3, #135266304 ; 0x8100000 800067a: d302 bcc.n 8000682 { EraseInitStruct.Banks = FLASH_BANK_2; 800067c: 2302 movs r3, #2 800067e: 617b str r3, [r7, #20] 8000680: e001 b.n 8000686 } else { EraseInitStruct.Banks = FLASH_BANK_1; 8000682: 2301 movs r3, #1 8000684: 617b str r3, [r7, #20] } EraseInitStruct.Sector = FirstSector; 8000686: 6afb ldr r3, [r7, #44] ; 0x2c 8000688: 61bb str r3, [r7, #24] EraseInitStruct.NbSectors = NbOfSectors; 800068a: 6abb ldr r3, [r7, #40] ; 0x28 800068c: 61fb str r3, [r7, #28] /* 扇区擦除 */ re = HAL_FLASHEx_Erase(&EraseInitStruct, &SECTORError); 800068e: f107 020c add.w r2, r7, #12 8000692: f107 0310 add.w r3, r7, #16 8000696: 4611 mov r1, r2 8000698: 4618 mov r0, r3 800069a: f002 fa53 bl 8002b44 800069e: 4603 mov r3, r0 80006a0: f887 3027 strb.w r3, [r7, #39] ; 0x27 /* 擦除完毕后，上锁 */ HAL_FLASH_Lock(); 80006a4: f002 f988 bl 80029b8 return re; 80006a8: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 } 80006ac: 4618 mov r0, r3 80006ae: 3730 adds r7, #48 ; 0x30 80006b0: 46bd mov sp, r7 80006b2: bd80 pop {r7, pc} 080006b4 : * _ulSize : 数据大小（单位是字节, 必须是32字节整数倍） * 返 回 值: 0-成功，1-数据长度或地址溢出，2-写Flash出错(估计Flash寿命到) ********************************************************************************************************* */ uint8_t bsp_WriteCpuFlash(uint32_t _ulFlashAddr, uint8_t *_ucpSrc, uint32_t _ulSize) { 80006b4: b580 push {r7, lr} 80006b6: b092 sub sp, #72 ; 0x48 80006b8: af00 add r7, sp, #0 80006ba: 60f8 str r0, [r7, #12] 80006bc: 60b9 str r1, [r7, #8] 80006be: 607a str r2, [r7, #4] uint32_t i; uint8_t ucRet; /* 如果偏移地址超过芯片容量，则不改写输出缓冲区 */ if (_ulFlashAddr + _ulSize > CPU_FLASH_BASE_ADDR + CPU_FLASH_SIZE) 80006c0: 68fa ldr r2, [r7, #12] 80006c2: 687b ldr r3, [r7, #4] 80006c4: 4413 add r3, r2 80006c6: f1b3 6f02 cmp.w r3, #136314880 ; 0x8200000 80006ca: d901 bls.n 80006d0 { return 1; 80006cc: 2301 movs r3, #1 80006ce: e082 b.n 80007d6 } /* 长度为0时不继续操作 */ if (_ulSize == 0) 80006d0: 687b ldr r3, [r7, #4] 80006d2: 2b00 cmp r3, #0 80006d4: d101 bne.n 80006da { return 0; 80006d6: 2300 movs r3, #0 80006d8: e07d b.n 80007d6 } ucRet = bsp_CmpCpuFlash(_ulFlashAddr, _ucpSrc, _ulSize); 80006da: 687a ldr r2, [r7, #4] 80006dc: 68b9 ldr r1, [r7, #8] 80006de: 68f8 ldr r0, [r7, #12] 80006e0: f7ff ff72 bl 80005c8 80006e4: 4603 mov r3, r0 80006e6: f887 3043 strb.w r3, [r7, #67] ; 0x43 if (ucRet == FLASH_IS_EQU) 80006ea: f897 3043 ldrb.w r3, [r7, #67] ; 0x43 80006ee: 2b00 cmp r3, #0 80006f0: d101 bne.n 80006f6 { return 0; 80006f2: 2300 movs r3, #0 80006f4: e06f b.n 80007d6 80006f6: 2301 movs r3, #1 80006f8: 63fb str r3, [r7, #60] ; 0x3c \details Assigns the given value to the Priority Mask Register. \param [in] priMask Priority Mask */ __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) { __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 80006fa: 6bfb ldr r3, [r7, #60] ; 0x3c 80006fc: f383 8810 msr PRIMASK, r3 } 8000700: bf00 nop } __set_PRIMASK(1); /* 关中断 */ /* FLASH 解锁 */ HAL_FLASH_Unlock(); 8000702: f002 f91f bl 8002944 for (i = 0; i < _ulSize / 32; i++) 8000706: 2300 movs r3, #0 8000708: 647b str r3, [r7, #68] ; 0x44 800070a: e019 b.n 8000740 { uint64_t FlashWord[4]; memcpy((char *)FlashWord, _ucpSrc, 32); 800070c: f107 0310 add.w r3, r7, #16 8000710: 2220 movs r2, #32 8000712: 68b9 ldr r1, [r7, #8] 8000714: 4618 mov r0, r3 8000716: f004 ffd1 bl 80056bc _ucpSrc += 32; 800071a: 68bb ldr r3, [r7, #8] 800071c: 3320 adds r3, #32 800071e: 60bb str r3, [r7, #8] if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_FLASHWORD, _ulFlashAddr, (uint64_t)((uint32_t)FlashWord)) == HAL_OK) 8000720: f107 0310 add.w r3, r7, #16 8000724: 461a mov r2, r3 8000726: 68f9 ldr r1, [r7, #12] 8000728: 2001 movs r0, #1 800072a: f002 f879 bl 8002820 800072e: 4603 mov r3, r0 8000730: 2b00 cmp r3, #0 8000732: d144 bne.n 80007be { _ulFlashAddr = _ulFlashAddr + 32; /* 递增，操作下一个256bit */ 8000734: 68fb ldr r3, [r7, #12] 8000736: 3320 adds r3, #32 8000738: 60fb str r3, [r7, #12] for (i = 0; i < _ulSize / 32; i++) 800073a: 6c7b ldr r3, [r7, #68] ; 0x44 800073c: 3301 adds r3, #1 800073e: 647b str r3, [r7, #68] ; 0x44 8000740: 687b ldr r3, [r7, #4] 8000742: 095b lsrs r3, r3, #5 8000744: 6c7a ldr r2, [r7, #68] ; 0x44 8000746: 429a cmp r2, r3 8000748: d3e0 bcc.n 800070c goto err; } } /* 长度不是32字节整数倍 */ if (_ulSize % 32) 800074a: 687b ldr r3, [r7, #4] 800074c: f003 031f and.w r3, r3, #31 8000750: 2b00 cmp r3, #0 8000752: d02a beq.n 80007aa { uint64_t FlashWord[4]; FlashWord[0] = 0; 8000754: f04f 0200 mov.w r2, #0 8000758: f04f 0300 mov.w r3, #0 800075c: e9c7 2304 strd r2, r3, [r7, #16] FlashWord[1] = 0; 8000760: f04f 0200 mov.w r2, #0 8000764: f04f 0300 mov.w r3, #0 8000768: e9c7 2306 strd r2, r3, [r7, #24] FlashWord[2] = 0; 800076c: f04f 0200 mov.w r2, #0 8000770: f04f 0300 mov.w r3, #0 8000774: e9c7 2308 strd r2, r3, [r7, #32] FlashWord[3] = 0; 8000778: f04f 0200 mov.w r2, #0 800077c: f04f 0300 mov.w r3, #0 8000780: e9c7 230a strd r2, r3, [r7, #40] ; 0x28 memcpy((char *)FlashWord, _ucpSrc, _ulSize % 32); 8000784: 687b ldr r3, [r7, #4] 8000786: f003 021f and.w r2, r3, #31 800078a: f107 0310 add.w r3, r7, #16 800078e: 68b9 ldr r1, [r7, #8] 8000790: 4618 mov r0, r3 8000792: f004 ff93 bl 80056bc if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_FLASHWORD, _ulFlashAddr, (uint64_t)((uint32_t)FlashWord)) == HAL_OK) 8000796: f107 0310 add.w r3, r7, #16 800079a: 461a mov r2, r3 800079c: 68f9 ldr r1, [r7, #12] 800079e: 2001 movs r0, #1 80007a0: f002 f83e bl 8002820 80007a4: 4603 mov r3, r0 80007a6: 2b00 cmp r3, #0 80007a8: d10b bne.n 80007c2 goto err; } } /* Flash 加锁，禁止写Flash控制寄存器 */ HAL_FLASH_Lock(); 80007aa: f002 f905 bl 80029b8 80007ae: 2300 movs r3, #0 80007b0: 63bb str r3, [r7, #56] ; 0x38 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 80007b2: 6bbb ldr r3, [r7, #56] ; 0x38 80007b4: f383 8810 msr PRIMASK, r3 } 80007b8: bf00 nop __set_PRIMASK(0); /* 开中断 */ return 0; 80007ba: 2300 movs r3, #0 80007bc: e00b b.n 80007d6 goto err; 80007be: bf00 nop 80007c0: e000 b.n 80007c4 goto err; 80007c2: bf00 nop err: /* Flash 加锁，禁止写Flash控制寄存器 */ HAL_FLASH_Lock(); 80007c4: f002 f8f8 bl 80029b8 80007c8: 2300 movs r3, #0 80007ca: 637b str r3, [r7, #52] ; 0x34 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 80007cc: 6b7b ldr r3, [r7, #52] ; 0x34 80007ce: f383 8810 msr PRIMASK, r3 } 80007d2: bf00 nop __set_PRIMASK(0); /* 开中断 */ return 1; 80007d4: 2301 movs r3, #1 } 80007d6: 4618 mov r0, r3 80007d8: 3748 adds r7, #72 ; 0x48 80007da: 46bd mov sp, r7 80007dc: bd80 pop {r7, pc} ... 080007e0 : * _pMsgParam : 消息参数，一般指向某个特定的结构体. 或者是0 * 返 回 值: 无 ********************************************************************************************************* */ void bsp_PutMsg(uint16_t _MsgCode, uint32_t _MsgParam) { 80007e0: b480 push {r7} 80007e2: b083 sub sp, #12 80007e4: af00 add r7, sp, #0 80007e6: 4603 mov r3, r0 80007e8: 6039 str r1, [r7, #0] 80007ea: 80fb strh r3, [r7, #6] g_tMsg.Buf[g_tMsg.Write].MsgCode = _MsgCode; 80007ec: 4b13 ldr r3, [pc, #76] ; (800083c ) 80007ee: f893 3141 ldrb.w r3, [r3, #321] ; 0x141 80007f2: 4619 mov r1, r3 80007f4: 4a11 ldr r2, [pc, #68] ; (800083c ) 80007f6: 88fb ldrh r3, [r7, #6] 80007f8: f822 3031 strh.w r3, [r2, r1, lsl #3] g_tMsg.Buf[g_tMsg.Write].MsgParam = _MsgParam; 80007fc: 4b0f ldr r3, [pc, #60] ; (800083c ) 80007fe: f893 3141 ldrb.w r3, [r3, #321] ; 0x141 8000802: 4a0e ldr r2, [pc, #56] ; (800083c ) 8000804: 00db lsls r3, r3, #3 8000806: 4413 add r3, r2 8000808: 683a ldr r2, [r7, #0] 800080a: 605a str r2, [r3, #4] if (++g_tMsg.Write >= MSG_FIFO_SIZE) 800080c: 4b0b ldr r3, [pc, #44] ; (800083c ) 800080e: f893 3141 ldrb.w r3, [r3, #321] ; 0x141 8000812: 3301 adds r3, #1 8000814: b2da uxtb r2, r3 8000816: 4b09 ldr r3, [pc, #36] ; (800083c ) 8000818: f883 2141 strb.w r2, [r3, #321] ; 0x141 800081c: 4b07 ldr r3, [pc, #28] ; (800083c ) 800081e: f893 3141 ldrb.w r3, [r3, #321] ; 0x141 8000822: 2b27 cmp r3, #39 ; 0x27 8000824: d903 bls.n 800082e { g_tMsg.Write = 0; 8000826: 4b05 ldr r3, [pc, #20] ; (800083c ) 8000828: 2200 movs r2, #0 800082a: f883 2141 strb.w r2, [r3, #321] ; 0x141 } } 800082e: bf00 nop 8000830: 370c adds r7, #12 8000832: 46bd mov sp, r7 8000834: f85d 7b04 ldr.w r7, [sp], #4 8000838: 4770 bx lr 800083a: bf00 nop 800083c: 24000158 .word 0x24000158 08000840 : * 形 参: 无 * 返 回 值: 0 表示无消息； 1表示有消息 ********************************************************************************************************* */ uint8_t bsp_GetMsg(MSG_T *_pMsg) { 8000840: b480 push {r7} 8000842: b085 sub sp, #20 8000844: af00 add r7, sp, #0 8000846: 6078 str r0, [r7, #4] MSG_T *p; if (g_tMsg.Read == g_tMsg.Write) 8000848: 4b18 ldr r3, [pc, #96] ; (80008ac ) 800084a: f893 2140 ldrb.w r2, [r3, #320] ; 0x140 800084e: 4b17 ldr r3, [pc, #92] ; (80008ac ) 8000850: f893 3141 ldrb.w r3, [r3, #321] ; 0x141 8000854: 429a cmp r2, r3 8000856: d101 bne.n 800085c { return 0; 8000858: 2300 movs r3, #0 800085a: e020 b.n 800089e } else { p = &g_tMsg.Buf[g_tMsg.Read]; 800085c: 4b13 ldr r3, [pc, #76] ; (80008ac ) 800085e: f893 3140 ldrb.w r3, [r3, #320] ; 0x140 8000862: 00db lsls r3, r3, #3 8000864: 4a11 ldr r2, [pc, #68] ; (80008ac ) 8000866: 4413 add r3, r2 8000868: 60fb str r3, [r7, #12] if (++g_tMsg.Read >= MSG_FIFO_SIZE) 800086a: 4b10 ldr r3, [pc, #64] ; (80008ac ) 800086c: f893 3140 ldrb.w r3, [r3, #320] ; 0x140 8000870: 3301 adds r3, #1 8000872: b2da uxtb r2, r3 8000874: 4b0d ldr r3, [pc, #52] ; (80008ac ) 8000876: f883 2140 strb.w r2, [r3, #320] ; 0x140 800087a: 4b0c ldr r3, [pc, #48] ; (80008ac ) 800087c: f893 3140 ldrb.w r3, [r3, #320] ; 0x140 8000880: 2b27 cmp r3, #39 ; 0x27 8000882: d903 bls.n 800088c { g_tMsg.Read = 0; 8000884: 4b09 ldr r3, [pc, #36] ; (80008ac ) 8000886: 2200 movs r2, #0 8000888: f883 2140 strb.w r2, [r3, #320] ; 0x140 } _pMsg->MsgCode = p->MsgCode; 800088c: 68fb ldr r3, [r7, #12] 800088e: 881a ldrh r2, [r3, #0] 8000890: 687b ldr r3, [r7, #4] 8000892: 801a strh r2, [r3, #0] _pMsg->MsgParam = p->MsgParam; 8000894: 68fb ldr r3, [r7, #12] 8000896: 685a ldr r2, [r3, #4] 8000898: 687b ldr r3, [r7, #4] 800089a: 605a str r2, [r3, #4] return 1; 800089c: 2301 movs r3, #1 } } 800089e: 4618 mov r0, r3 80008a0: 3714 adds r7, #20 80008a2: 46bd mov sp, r7 80008a4: f85d 7b04 ldr.w r7, [sp], #4 80008a8: 4770 bx lr 80008aa: bf00 nop 80008ac: 24000158 .word 0x24000158 080008b0 : * 形 参: 无 * 返 回 值: 无 ********************************************************************************************************* */ void DemoCANUpdate(void) { 80008b0: b580 push {r7, lr} 80008b2: b088 sub sp, #32 80008b4: af00 add r7, sp, #0 uint8_t cmd; uint32_t SectorCount = 0; 80008b6: 2300 movs r3, #0 80008b8: 613b str r3, [r7, #16] uint32_t SectorRemain = 0; 80008ba: 2300 movs r3, #0 80008bc: 60fb str r3, [r7, #12] uint32_t i; uint32_t TotalSize = 0; 80008be: 2300 movs r3, #0 80008c0: 61bb str r3, [r7, #24] uint8_t ucState; MSG_T msg; can_Init(); /* 初始化CAN */ 80008c2: f000 f961 bl 8000b88 while (1) { if (bsp_GetMsg(&msg)) 80008c6: 463b mov r3, r7 80008c8: 4618 mov r0, r3 80008ca: f7ff ffb9 bl 8000840 80008ce: 4603 mov r3, r0 80008d0: 2b00 cmp r3, #0 80008d2: f000 80dd beq.w 8000a90 { switch (msg.MsgCode) 80008d6: 883b ldrh r3, [r7, #0] 80008d8: 2b04 cmp r3, #4 80008da: d1f4 bne.n 80008c6 { case MSG_CAN2_RX: /* 接收到CAN设备的应答 */ cmd = g_Can2RxData[0]; 80008dc: 4b6e ldr r3, [pc, #440] ; (8000a98 ) 80008de: 781b ldrb r3, [r3, #0] 80008e0: 72fb strb r3, [r7, #11] /* 开始传输固件命令 **************/ if(cmd == '$') 80008e2: 7afb ldrb r3, [r7, #11] 80008e4: 2b24 cmp r3, #36 ; 0x24 80008e6: d17a bne.n 80009de { /* 接收够224个数据 */ RecSize = g_Can2RxData[1]; 80008e8: 4b6b ldr r3, [pc, #428] ; (8000a98 ) 80008ea: 785b ldrb r3, [r3, #1] 80008ec: 461a mov r2, r3 80008ee: 4b6b ldr r3, [pc, #428] ; (8000a9c ) 80008f0: 601a str r2, [r3, #0] update_index = g_Can2RxData[2] + (g_Can2RxData[3] << 8) + (g_Can2RxData[4] << 16) + (g_Can2RxData[5] << 24); 80008f2: 4b69 ldr r3, [pc, #420] ; (8000a98 ) 80008f4: 789b ldrb r3, [r3, #2] 80008f6: 461a mov r2, r3 80008f8: 4b67 ldr r3, [pc, #412] ; (8000a98 ) 80008fa: 78db ldrb r3, [r3, #3] 80008fc: 021b lsls r3, r3, #8 80008fe: 441a add r2, r3 8000900: 4b65 ldr r3, [pc, #404] ; (8000a98 ) 8000902: 791b ldrb r3, [r3, #4] 8000904: 041b lsls r3, r3, #16 8000906: 441a add r2, r3 8000908: 4b63 ldr r3, [pc, #396] ; (8000a98 ) 800090a: 795b ldrb r3, [r3, #5] 800090c: 061b lsls r3, r3, #24 800090e: 4413 add r3, r2 8000910: 461a mov r2, r3 8000912: 4b63 ldr r3, [pc, #396] ; (8000aa0 ) 8000914: 601a str r2, [r3, #0] if(update_index==update_index_true && Bus_Error==0) 8000916: 4b62 ldr r3, [pc, #392] ; (8000aa0 ) 8000918: 681a ldr r2, [r3, #0] 800091a: 4b62 ldr r3, [pc, #392] ; (8000aa4 ) 800091c: 681b ldr r3, [r3, #0] 800091e: 429a cmp r2, r3 8000920: d14f bne.n 80009c2 8000922: 4b61 ldr r3, [pc, #388] ; (8000aa8 ) 8000924: 681b ldr r3, [r3, #0] 8000926: 2b00 cmp r3, #0 8000928: d14b bne.n 80009c2 { update_sum = g_Can2RxData[6] + (g_Can2RxData[7] << 8); 800092a: 4b5b ldr r3, [pc, #364] ; (8000a98 ) 800092c: 799b ldrb r3, [r3, #6] 800092e: 461a mov r2, r3 8000930: 4b59 ldr r3, [pc, #356] ; (8000a98 ) 8000932: 79db ldrb r3, [r3, #7] 8000934: 021b lsls r3, r3, #8 8000936: 4413 add r3, r2 8000938: 461a mov r2, r3 800093a: 4b5c ldr r3, [pc, #368] ; (8000aac ) 800093c: 601a str r2, [r3, #0] update_sum_true = 0; 800093e: 4b5c ldr r3, [pc, #368] ; (8000ab0 ) 8000940: 2200 movs r2, #0 8000942: 601a str r2, [r3, #0] for(uint8_t i=0;i { update_sum_true = update_sum_true + g_Can2RxData[8+i]; 800094a: 7dfb ldrb r3, [r7, #23] 800094c: 3308 adds r3, #8 800094e: 4a52 ldr r2, [pc, #328] ; (8000a98 ) 8000950: 5cd3 ldrb r3, [r2, r3] 8000952: 461a mov r2, r3 8000954: 4b56 ldr r3, [pc, #344] ; (8000ab0 ) 8000956: 681b ldr r3, [r3, #0] 8000958: 4413 add r3, r2 800095a: 4a55 ldr r2, [pc, #340] ; (8000ab0 ) 800095c: 6013 str r3, [r2, #0] for(uint8_t i=0;i) 8000968: 681b ldr r3, [r3, #0] 800096a: 429a cmp r2, r3 800096c: d3ed bcc.n 800094a } if(update_sum==update_sum_true && Bus_Error==0) 800096e: 4b4f ldr r3, [pc, #316] ; (8000aac ) 8000970: 681a ldr r2, [r3, #0] 8000972: 4b4f ldr r3, [pc, #316] ; (8000ab0 ) 8000974: 681b ldr r3, [r3, #0] 8000976: 429a cmp r2, r3 8000978: d11c bne.n 80009b4 800097a: 4b4b ldr r3, [pc, #300] ; (8000aa8 ) 800097c: 681b ldr r3, [r3, #0] 800097e: 2b00 cmp r3, #0 8000980: d118 bne.n 80009b4 { /* 编程内部Flash, */ ucState = bsp_WriteCpuFlash((uint32_t)(AppAddr + TotalSize), (uint8_t *)&g_Can2RxData[8], RecSize); 8000982: 69ba ldr r2, [r7, #24] 8000984: 4b4b ldr r3, [pc, #300] ; (8000ab4 ) 8000986: 4413 add r3, r2 8000988: 4a44 ldr r2, [pc, #272] ; (8000a9c ) 800098a: 6812 ldr r2, [r2, #0] 800098c: 494a ldr r1, [pc, #296] ; (8000ab8 ) 800098e: 4618 mov r0, r3 8000990: f7ff fe90 bl 80006b4 8000994: 4603 mov r3, r0 8000996: 72bb strb r3, [r7, #10] TotalSize += RecSize; 8000998: 4b40 ldr r3, [pc, #256] ; (8000a9c ) 800099a: 681b ldr r3, [r3, #0] 800099c: 69ba ldr r2, [r7, #24] 800099e: 4413 add r3, r2 80009a0: 61bb str r3, [r7, #24] /* 如果返回非0，表示编程失败 */ if(ucState != 0) 80009a2: 7abb ldrb r3, [r7, #10] 80009a4: 2b00 cmp r3, #0 80009a6: d00b beq.n 80009c0 { Bus_Error++;/* 返回0x60，表示编程失败 */ 80009a8: 4b3f ldr r3, [pc, #252] ; (8000aa8 ) 80009aa: 681b ldr r3, [r3, #0] 80009ac: 3301 adds r3, #1 80009ae: 4a3e ldr r2, [pc, #248] ; (8000aa8 ) 80009b0: 6013 str r3, [r2, #0] if(ucState != 0) 80009b2: e005 b.n 80009c0 } /* 返回0x30，表示编程成功 */ } else { Bus_Error++; 80009b4: 4b3c ldr r3, [pc, #240] ; (8000aa8 ) 80009b6: 681b ldr r3, [r3, #0] 80009b8: 3301 adds r3, #1 80009ba: 4a3b ldr r2, [pc, #236] ; (8000aa8 ) 80009bc: 6013 str r3, [r2, #0] if(update_sum==update_sum_true && Bus_Error==0) 80009be: e009 b.n 80009d4 80009c0: e008 b.n 80009d4 } } else { Bus_Error++; 80009c2: 4b39 ldr r3, [pc, #228] ; (8000aa8 ) 80009c4: 681b ldr r3, [r3, #0] 80009c6: 3301 adds r3, #1 80009c8: 4a37 ldr r2, [pc, #220] ; (8000aa8 ) 80009ca: 6013 str r3, [r2, #0] can2_SendPacket(g_Can2RxData, 4); 80009cc: 2104 movs r1, #4 80009ce: 4832 ldr r0, [pc, #200] ; (8000a98 ) 80009d0: f7ff fcd4 bl 800037c } update_index_true++; 80009d4: 4b33 ldr r3, [pc, #204] ; (8000aa4 ) 80009d6: 681b ldr r3, [r3, #0] 80009d8: 3301 adds r3, #1 80009da: 4a32 ldr r2, [pc, #200] ; (8000aa4 ) 80009dc: 6013 str r3, [r2, #0] } /* 传输完成命令 **************/ if(cmd == '#' && Bus_Error==0) 80009de: 7afb ldrb r3, [r7, #11] 80009e0: 2b23 cmp r3, #35 ; 0x23 80009e2: d10c bne.n 80009fe 80009e4: 4b30 ldr r3, [pc, #192] ; (8000aa8 ) 80009e6: 681b ldr r3, [r3, #0] 80009e8: 2b00 cmp r3, #0 80009ea: d108 bne.n 80009fe { can2_SendPacket(g_Can2RxData, 3); 80009ec: 2103 movs r1, #3 80009ee: 482a ldr r0, [pc, #168] ; (8000a98 ) 80009f0: f7ff fcc4 bl 800037c HAL_Delay(10); 80009f4: 200a movs r0, #10 80009f6: f000 fc47 bl 8001288 JumpToApp(); 80009fa: f000 f863 bl 8000ac4 } /* 接收固件大小命令 */ if(cmd == '*') 80009fe: 7afb ldrb r3, [r7, #11] 8000a00: 2b2a cmp r3, #42 ; 0x2a 8000a02: d147 bne.n 8000a94 { filesize = g_Can2RxData[1] + (g_Can2RxData[2] << 8) + (g_Can2RxData[3] << 16) + (g_Can2RxData[4] << 24); 8000a04: 4b24 ldr r3, [pc, #144] ; (8000a98 ) 8000a06: 785b ldrb r3, [r3, #1] 8000a08: 461a mov r2, r3 8000a0a: 4b23 ldr r3, [pc, #140] ; (8000a98 ) 8000a0c: 789b ldrb r3, [r3, #2] 8000a0e: 021b lsls r3, r3, #8 8000a10: 441a add r2, r3 8000a12: 4b21 ldr r3, [pc, #132] ; (8000a98 ) 8000a14: 78db ldrb r3, [r3, #3] 8000a16: 041b lsls r3, r3, #16 8000a18: 441a add r2, r3 8000a1a: 4b1f ldr r3, [pc, #124] ; (8000a98 ) 8000a1c: 791b ldrb r3, [r3, #4] 8000a1e: 061b lsls r3, r3, #24 8000a20: 4413 add r3, r2 8000a22: 461a mov r2, r3 8000a24: 4b25 ldr r3, [pc, #148] ; (8000abc ) 8000a26: 601a str r2, [r3, #0] uwAppSize = filesize; 8000a28: 4b24 ldr r3, [pc, #144] ; (8000abc ) 8000a2a: 681b ldr r3, [r3, #0] 8000a2c: 4a24 ldr r2, [pc, #144] ; (8000ac0 ) 8000a2e: 6013 str r3, [r2, #0] SectorCount = filesize/(128*1024); 8000a30: 4b22 ldr r3, [pc, #136] ; (8000abc ) 8000a32: 681b ldr r3, [r3, #0] 8000a34: 0c5b lsrs r3, r3, #17 8000a36: 613b str r3, [r7, #16] SectorRemain = filesize%(128*1024); 8000a38: 4b20 ldr r3, [pc, #128] ; (8000abc ) 8000a3a: 681b ldr r3, [r3, #0] 8000a3c: f3c3 0310 ubfx r3, r3, #0, #17 8000a40: 60fb str r3, [r7, #12] Bus_Error=0; 8000a42: 4b19 ldr r3, [pc, #100] ; (8000aa8 ) 8000a44: 2200 movs r2, #0 8000a46: 601a str r2, [r3, #0] update_index_true=0; 8000a48: 4b16 ldr r3, [pc, #88] ; (8000aa4 ) 8000a4a: 2200 movs r2, #0 8000a4c: 601a str r2, [r3, #0] update_sum_true=0; 8000a4e: 4b18 ldr r3, [pc, #96] ; (8000ab0 ) 8000a50: 2200 movs r2, #0 8000a52: 601a str r2, [r3, #0] TotalSize=0; 8000a54: 2300 movs r3, #0 8000a56: 61bb str r3, [r7, #24] for(i = 0; i < SectorCount; i++) 8000a58: 2300 movs r3, #0 8000a5a: 61fb str r3, [r7, #28] 8000a5c: e009 b.n 8000a72 { bsp_EraseCpuFlash((uint32_t)(AppAddr + i*128*1024)); 8000a5e: 69fb ldr r3, [r7, #28] 8000a60: f203 4301 addw r3, r3, #1025 ; 0x401 8000a64: 045b lsls r3, r3, #17 8000a66: 4618 mov r0, r3 8000a68: f7ff fdee bl 8000648 for(i = 0; i < SectorCount; i++) 8000a6c: 69fb ldr r3, [r7, #28] 8000a6e: 3301 adds r3, #1 8000a70: 61fb str r3, [r7, #28] 8000a72: 69fa ldr r2, [r7, #28] 8000a74: 693b ldr r3, [r7, #16] 8000a76: 429a cmp r2, r3 8000a78: d3f1 bcc.n 8000a5e } if(SectorRemain) 8000a7a: 68fb ldr r3, [r7, #12] 8000a7c: 2b00 cmp r3, #0 8000a7e: d009 beq.n 8000a94 { bsp_EraseCpuFlash((uint32_t)(AppAddr + i*128*1024)); 8000a80: 69fb ldr r3, [r7, #28] 8000a82: f203 4301 addw r3, r3, #1025 ; 0x401 8000a86: 045b lsls r3, r3, #17 8000a88: 4618 mov r0, r3 8000a8a: f7ff fddd bl 8000648 } /* 返回0x30，表示擦除成功 */ } break; 8000a8e: e001 b.n 8000a94 } } 8000a90: bf00 nop 8000a92: e718 b.n 80008c6 break; 8000a94: bf00 nop if (bsp_GetMsg(&msg)) 8000a96: e716 b.n 80008c6 8000a98: 240000f4 .word 0x240000f4 8000a9c: 240002a0 .word 0x240002a0 8000aa0: 240002ac .word 0x240002ac 8000aa4: 240002b0 .word 0x240002b0 8000aa8: 240002a8 .word 0x240002a8 8000aac: 240002b4 .word 0x240002b4 8000ab0: 240002b8 .word 0x240002b8 8000ab4: 08020000 .word 0x08020000 8000ab8: 240000fc .word 0x240000fc 8000abc: 240002a4 .word 0x240002a4 8000ac0: 2400029c .word 0x2400029c 08000ac4 : * 形 参: 无 * 返 回 值: 无 ********************************************************************************************************* */ void JumpToApp(void) { 8000ac4: b580 push {r7, lr} 8000ac6: b086 sub sp, #24 8000ac8: af00 add r7, sp, #0 uint32_t i=0; 8000aca: 2300 movs r3, #0 8000acc: 617b str r3, [r7, #20] 8000ace: 2301 movs r3, #1 8000ad0: 60fb str r3, [r7, #12] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8000ad2: 68fb ldr r3, [r7, #12] 8000ad4: f383 8810 msr PRIMASK, r3 } 8000ad8: bf00 nop /* 关闭全局中断 */ DISABLE_INT(); /* 设置所有时钟到默认状态，使用HSI时钟 */ bsp_DeInitCan2(); 8000ada: f7ff fc03 bl 80002e4 __HAL_RCC_GPIOH_CLK_DISABLE(); 8000ade: 4b25 ldr r3, [pc, #148] ; (8000b74 ) 8000ae0: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 8000ae4: 4a23 ldr r2, [pc, #140] ; (8000b74 ) 8000ae6: f023 0380 bic.w r3, r3, #128 ; 0x80 8000aea: f8c2 30e0 str.w r3, [r2, #224] ; 0xe0 __HAL_RCC_GPIOB_CLK_DISABLE(); 8000aee: 4b21 ldr r3, [pc, #132] ; (8000b74 ) 8000af0: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 8000af4: 4a1f ldr r2, [pc, #124] ; (8000b74 ) 8000af6: f023 0302 bic.w r3, r3, #2 8000afa: f8c2 30e0 str.w r3, [r2, #224] ; 0xe0 HAL_RCC_DeInit(); 8000afe: f002 fc87 bl 8003410 /* 关闭滴答定时器，复位到默认值 */ SysTick->CTRL = 0; 8000b02: 4b1d ldr r3, [pc, #116] ; (8000b78 ) 8000b04: 2200 movs r2, #0 8000b06: 601a str r2, [r3, #0] SysTick->LOAD = 0; 8000b08: 4b1b ldr r3, [pc, #108] ; (8000b78 ) 8000b0a: 2200 movs r2, #0 8000b0c: 605a str r2, [r3, #4] SysTick->VAL = 0; 8000b0e: 4b1a ldr r3, [pc, #104] ; (8000b78 ) 8000b10: 2200 movs r2, #0 8000b12: 609a str r2, [r3, #8] /* 关闭所有中断，清除所有中断挂起标志 */ for (i = 0; i < 8; i++) 8000b14: 2300 movs r3, #0 8000b16: 617b str r3, [r7, #20] 8000b18: e010 b.n 8000b3c { NVIC->ICER[i]=0xFFFFFFFF; 8000b1a: 4a18 ldr r2, [pc, #96] ; (8000b7c ) 8000b1c: 697b ldr r3, [r7, #20] 8000b1e: 3320 adds r3, #32 8000b20: f04f 31ff mov.w r1, #4294967295 8000b24: f842 1023 str.w r1, [r2, r3, lsl #2] NVIC->ICPR[i]=0xFFFFFFFF; 8000b28: 4a14 ldr r2, [pc, #80] ; (8000b7c ) 8000b2a: 697b ldr r3, [r7, #20] 8000b2c: 3360 adds r3, #96 ; 0x60 8000b2e: f04f 31ff mov.w r1, #4294967295 8000b32: f842 1023 str.w r1, [r2, r3, lsl #2] for (i = 0; i < 8; i++) 8000b36: 697b ldr r3, [r7, #20] 8000b38: 3301 adds r3, #1 8000b3a: 617b str r3, [r7, #20] 8000b3c: 697b ldr r3, [r7, #20] 8000b3e: 2b07 cmp r3, #7 8000b40: d9eb bls.n 8000b1a 8000b42: 2300 movs r3, #0 8000b44: 603b str r3, [r7, #0] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8000b46: 683b ldr r3, [r7, #0] 8000b48: f383 8810 msr PRIMASK, r3 } 8000b4c: bf00 nop /* 使能全局中断 */ ENABLE_INT(); /* 跳转到应用程序，首地址是MSP，地址+4是复位中断服务程序地址 */ AppJump = (void (*)(void)) (*((uint32_t *) (AppAddr + 4))); 8000b4e: 4b0c ldr r3, [pc, #48] ; (8000b80 ) 8000b50: 681b ldr r3, [r3, #0] 8000b52: 613b str r3, [r7, #16] /* 设置主堆栈指针 */ __set_MSP(*(uint32_t *)AppAddr); 8000b54: 4b0b ldr r3, [pc, #44] ; (8000b84 ) 8000b56: 681b ldr r3, [r3, #0] 8000b58: 607b str r3, [r7, #4] __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); 8000b5a: 687b ldr r3, [r7, #4] 8000b5c: f383 8808 msr MSP, r3 } 8000b60: bf00 nop 8000b62: 2300 movs r3, #0 8000b64: 60bb str r3, [r7, #8] __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); 8000b66: 68bb ldr r3, [r7, #8] 8000b68: f383 8814 msr CONTROL, r3 } 8000b6c: bf00 nop /* 在RTOS工程，这条语句很重要，设置为特权级模式，使用MSP指针 */ __set_CONTROL(0); /* 跳转到系统BootLoader */ AppJump(); 8000b6e: 693b ldr r3, [r7, #16] 8000b70: 4798 blx r3 /* 跳转成功的话，不会执行到这里，用户可以在这里添加代码 */ while (1) 8000b72: e7fe b.n 8000b72 8000b74: 58024400 .word 0x58024400 8000b78: e000e010 .word 0xe000e010 8000b7c: e000e100 .word 0xe000e100 8000b80: 08020004 .word 0x08020004 8000b84: 08020000 .word 0x08020000 08000b88 : * 形 参: 无 * 返 回 值: 无 ********************************************************************************************************* */ void can_Init(void) { 8000b88: b580 push {r7, lr} 8000b8a: af00 add r7, sp, #0 bsp_InitCan2(); 8000b8c: f7ff fba4 bl 80002d8 } 8000b90: bf00 nop 8000b92: bd80 pop {r7, pc} 08000b94 : FDCAN_HandleTypeDef hfdcan2; /* FDCAN2 init function */ void MX_FDCAN2_Init(void) { 8000b94: b580 push {r7, lr} 8000b96: af00 add r7, sp, #0 /* USER CODE END FDCAN2_Init 0 */ /* USER CODE BEGIN FDCAN2_Init 1 */ /* USER CODE END FDCAN2_Init 1 */ hfdcan2.Instance = FDCAN2; 8000b98: 4b3b ldr r3, [pc, #236] ; (8000c88 ) 8000b9a: 4a3c ldr r2, [pc, #240] ; (8000c8c ) 8000b9c: 601a str r2, [r3, #0] hfdcan2.Init.FrameFormat = FDCAN_FRAME_FD_NO_BRS; 8000b9e: 4b3a ldr r3, [pc, #232] ; (8000c88 ) 8000ba0: f44f 7280 mov.w r2, #256 ; 0x100 8000ba4: 609a str r2, [r3, #8] hfdcan2.Init.Mode = FDCAN_MODE_NORMAL; 8000ba6: 4b38 ldr r3, [pc, #224] ; (8000c88 ) 8000ba8: 2200 movs r2, #0 8000baa: 60da str r2, [r3, #12] hfdcan2.Init.AutoRetransmission = DISABLE; 8000bac: 4b36 ldr r3, [pc, #216] ; (8000c88 ) 8000bae: 2200 movs r2, #0 8000bb0: 741a strb r2, [r3, #16] hfdcan2.Init.TransmitPause = DISABLE; 8000bb2: 4b35 ldr r3, [pc, #212] ; (8000c88 ) 8000bb4: 2200 movs r2, #0 8000bb6: 745a strb r2, [r3, #17] hfdcan2.Init.ProtocolException = DISABLE; 8000bb8: 4b33 ldr r3, [pc, #204] ; (8000c88 ) 8000bba: 2200 movs r2, #0 8000bbc: 749a strb r2, [r3, #18] hfdcan2.Init.NominalPrescaler = 10; 8000bbe: 4b32 ldr r3, [pc, #200] ; (8000c88 ) 8000bc0: 220a movs r2, #10 8000bc2: 615a str r2, [r3, #20] hfdcan2.Init.NominalSyncJumpWidth = 1; 8000bc4: 4b30 ldr r3, [pc, #192] ; (8000c88 ) 8000bc6: 2201 movs r2, #1 8000bc8: 619a str r2, [r3, #24] hfdcan2.Init.NominalTimeSeg1 = 5; 8000bca: 4b2f ldr r3, [pc, #188] ; (8000c88 ) 8000bcc: 2205 movs r2, #5 8000bce: 61da str r2, [r3, #28] hfdcan2.Init.NominalTimeSeg2 = 2; 8000bd0: 4b2d ldr r3, [pc, #180] ; (8000c88 ) 8000bd2: 2202 movs r2, #2 8000bd4: 621a str r2, [r3, #32] hfdcan2.Init.DataPrescaler = 10; 8000bd6: 4b2c ldr r3, [pc, #176] ; (8000c88 ) 8000bd8: 220a movs r2, #10 8000bda: 625a str r2, [r3, #36] ; 0x24 hfdcan2.Init.DataSyncJumpWidth = 1; 8000bdc: 4b2a ldr r3, [pc, #168] ; (8000c88 ) 8000bde: 2201 movs r2, #1 8000be0: 629a str r2, [r3, #40] ; 0x28 hfdcan2.Init.DataTimeSeg1 = 5; 8000be2: 4b29 ldr r3, [pc, #164] ; (8000c88 ) 8000be4: 2205 movs r2, #5 8000be6: 62da str r2, [r3, #44] ; 0x2c hfdcan2.Init.DataTimeSeg2 = 2; 8000be8: 4b27 ldr r3, [pc, #156] ; (8000c88 ) 8000bea: 2202 movs r2, #2 8000bec: 631a str r2, [r3, #48] ; 0x30 hfdcan2.Init.MessageRAMOffset = 0; 8000bee: 4b26 ldr r3, [pc, #152] ; (8000c88 ) 8000bf0: 2200 movs r2, #0 8000bf2: 635a str r2, [r3, #52] ; 0x34 hfdcan2.Init.StdFiltersNbr = 0; 8000bf4: 4b24 ldr r3, [pc, #144] ; (8000c88 ) 8000bf6: 2200 movs r2, #0 8000bf8: 639a str r2, [r3, #56] ; 0x38 hfdcan2.Init.ExtFiltersNbr = 0; 8000bfa: 4b23 ldr r3, [pc, #140] ; (8000c88 ) 8000bfc: 2200 movs r2, #0 8000bfe: 63da str r2, [r3, #60] ; 0x3c hfdcan2.Init.RxFifo0ElmtsNbr = 32; 8000c00: 4b21 ldr r3, [pc, #132] ; (8000c88 ) 8000c02: 2220 movs r2, #32 8000c04: 641a str r2, [r3, #64] ; 0x40 hfdcan2.Init.RxFifo0ElmtSize = FDCAN_DATA_BYTES_64; 8000c06: 4b20 ldr r3, [pc, #128] ; (8000c88 ) 8000c08: 2212 movs r2, #18 8000c0a: 645a str r2, [r3, #68] ; 0x44 hfdcan2.Init.RxFifo1ElmtsNbr = 0; 8000c0c: 4b1e ldr r3, [pc, #120] ; (8000c88 ) 8000c0e: 2200 movs r2, #0 8000c10: 649a str r2, [r3, #72] ; 0x48 hfdcan2.Init.RxFifo1ElmtSize = FDCAN_DATA_BYTES_64; 8000c12: 4b1d ldr r3, [pc, #116] ; (8000c88 ) 8000c14: 2212 movs r2, #18 8000c16: 64da str r2, [r3, #76] ; 0x4c hfdcan2.Init.RxBuffersNbr = 0; 8000c18: 4b1b ldr r3, [pc, #108] ; (8000c88 ) 8000c1a: 2200 movs r2, #0 8000c1c: 651a str r2, [r3, #80] ; 0x50 hfdcan2.Init.RxBufferSize = FDCAN_DATA_BYTES_64; 8000c1e: 4b1a ldr r3, [pc, #104] ; (8000c88 ) 8000c20: 2212 movs r2, #18 8000c22: 655a str r2, [r3, #84] ; 0x54 hfdcan2.Init.TxEventsNbr = 0; 8000c24: 4b18 ldr r3, [pc, #96] ; (8000c88 ) 8000c26: 2200 movs r2, #0 8000c28: 659a str r2, [r3, #88] ; 0x58 hfdcan2.Init.TxBuffersNbr = 0; 8000c2a: 4b17 ldr r3, [pc, #92] ; (8000c88 ) 8000c2c: 2200 movs r2, #0 8000c2e: 65da str r2, [r3, #92] ; 0x5c hfdcan2.Init.TxFifoQueueElmtsNbr = 32; 8000c30: 4b15 ldr r3, [pc, #84] ; (8000c88 ) 8000c32: 2220 movs r2, #32 8000c34: 661a str r2, [r3, #96] ; 0x60 hfdcan2.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION; 8000c36: 4b14 ldr r3, [pc, #80] ; (8000c88 ) 8000c38: 2200 movs r2, #0 8000c3a: 665a str r2, [r3, #100] ; 0x64 hfdcan2.Init.TxElmtSize = FDCAN_DATA_BYTES_64; 8000c3c: 4b12 ldr r3, [pc, #72] ; (8000c88 ) 8000c3e: 2212 movs r2, #18 8000c40: 669a str r2, [r3, #104] ; 0x68 if (HAL_FDCAN_Init(&hfdcan2) != HAL_OK) 8000c42: 4811 ldr r0, [pc, #68] ; (8000c88 ) 8000c44: f000 fc92 bl 800156c 8000c48: 4603 mov r3, r0 8000c4a: 2b00 cmp r3, #0 8000c4c: d001 beq.n 8000c52 { Error_Handler(); 8000c4e: f000 f983 bl 8000f58 } /* USER CODE BEGIN FDCAN2_Init 2 */ if (HAL_FDCAN_ActivateNotification(&hfdcan2, FDCAN_IT_RX_FIFO0_NEW_MESSAGE, 0) != HAL_OK) 8000c52: 2200 movs r2, #0 8000c54: 2101 movs r1, #1 8000c56: 480c ldr r0, [pc, #48] ; (8000c88 ) 8000c58: f001 f85a bl 8001d10 8000c5c: 4603 mov r3, r0 8000c5e: 2b00 cmp r3, #0 8000c60: d001 beq.n 8000c66 { Error_Handler(); 8000c62: f000 f979 bl 8000f58 } if (HAL_FDCAN_ActivateNotification(&hfdcan2, FDCAN_IT_BUS_OFF, 0) != HAL_OK) 8000c66: 2200 movs r2, #0 8000c68: f04f 7100 mov.w r1, #33554432 ; 0x2000000 8000c6c: 4806 ldr r0, [pc, #24] ; (8000c88 ) 8000c6e: f001 f84f bl 8001d10 8000c72: 4603 mov r3, r0 8000c74: 2b00 cmp r3, #0 8000c76: d001 beq.n 8000c7c { Error_Handler(); 8000c78: f000 f96e bl 8000f58 } HAL_FDCAN_Start(&hfdcan2); 8000c7c: 4802 ldr r0, [pc, #8] ; (8000c88 ) 8000c7e: f000 fe53 bl 8001928 /* USER CODE END FDCAN2_Init 2 */ } 8000c82: bf00 nop 8000c84: bd80 pop {r7, pc} 8000c86: bf00 nop 8000c88: 240002bc .word 0x240002bc 8000c8c: 4000a400 .word 0x4000a400 08000c90 : void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef* fdcanHandle) { 8000c90: b580 push {r7, lr} 8000c92: b0b8 sub sp, #224 ; 0xe0 8000c94: af00 add r7, sp, #0 8000c96: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000c98: f107 03cc add.w r3, r7, #204 ; 0xcc 8000c9c: 2200 movs r2, #0 8000c9e: 601a str r2, [r3, #0] 8000ca0: 605a str r2, [r3, #4] 8000ca2: 609a str r2, [r3, #8] 8000ca4: 60da str r2, [r3, #12] 8000ca6: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 8000ca8: f107 0310 add.w r3, r7, #16 8000cac: 22bc movs r2, #188 ; 0xbc 8000cae: 2100 movs r1, #0 8000cb0: 4618 mov r0, r3 8000cb2: f004 fd11 bl 80056d8 if(fdcanHandle->Instance==FDCAN2) 8000cb6: 687b ldr r3, [r7, #4] 8000cb8: 681b ldr r3, [r3, #0] 8000cba: 4a29 ldr r2, [pc, #164] ; (8000d60 ) 8000cbc: 4293 cmp r3, r2 8000cbe: d14a bne.n 8000d56 /* USER CODE END FDCAN2_MspInit 0 */ /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_FDCAN; 8000cc0: f44f 4300 mov.w r3, #32768 ; 0x8000 8000cc4: 613b str r3, [r7, #16] PeriphClkInitStruct.FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL; 8000cc6: f04f 5380 mov.w r3, #268435456 ; 0x10000000 8000cca: 67fb str r3, [r7, #124] ; 0x7c if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8000ccc: f107 0310 add.w r3, r7, #16 8000cd0: 4618 mov r0, r3 8000cd2: f003 fc25 bl 8004520 8000cd6: 4603 mov r3, r0 8000cd8: 2b00 cmp r3, #0 8000cda: d001 beq.n 8000ce0 { Error_Handler(); 8000cdc: f000 f93c bl 8000f58 } /* FDCAN2 clock enable */ __HAL_RCC_FDCAN_CLK_ENABLE(); 8000ce0: 4b20 ldr r3, [pc, #128] ; (8000d64 ) 8000ce2: f8d3 30ec ldr.w r3, [r3, #236] ; 0xec 8000ce6: 4a1f ldr r2, [pc, #124] ; (8000d64 ) 8000ce8: f443 7380 orr.w r3, r3, #256 ; 0x100 8000cec: f8c2 30ec str.w r3, [r2, #236] ; 0xec 8000cf0: 4b1c ldr r3, [pc, #112] ; (8000d64 ) 8000cf2: f8d3 30ec ldr.w r3, [r3, #236] ; 0xec 8000cf6: f403 7380 and.w r3, r3, #256 ; 0x100 8000cfa: 60fb str r3, [r7, #12] 8000cfc: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOB_CLK_ENABLE(); 8000cfe: 4b19 ldr r3, [pc, #100] ; (8000d64 ) 8000d00: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 8000d04: 4a17 ldr r2, [pc, #92] ; (8000d64 ) 8000d06: f043 0302 orr.w r3, r3, #2 8000d0a: f8c2 30e0 str.w r3, [r2, #224] ; 0xe0 8000d0e: 4b15 ldr r3, [pc, #84] ; (8000d64 ) 8000d10: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 8000d14: f003 0302 and.w r3, r3, #2 8000d18: 60bb str r3, [r7, #8] 8000d1a: 68bb ldr r3, [r7, #8] /**FDCAN2 GPIO Configuration PB5 ------> FDCAN2_RX PB6 ------> FDCAN2_TX */ GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6; 8000d1c: 2360 movs r3, #96 ; 0x60 8000d1e: f8c7 30cc str.w r3, [r7, #204] ; 0xcc GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8000d22: 2302 movs r3, #2 8000d24: f8c7 30d0 str.w r3, [r7, #208] ; 0xd0 GPIO_InitStruct.Pull = GPIO_NOPULL; 8000d28: 2300 movs r3, #0 8000d2a: f8c7 30d4 str.w r3, [r7, #212] ; 0xd4 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000d2e: 2300 movs r3, #0 8000d30: f8c7 30d8 str.w r3, [r7, #216] ; 0xd8 GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN2; 8000d34: 2309 movs r3, #9 8000d36: f8c7 30dc str.w r3, [r7, #220] ; 0xdc HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8000d3a: f107 03cc add.w r3, r7, #204 ; 0xcc 8000d3e: 4619 mov r1, r3 8000d40: 4809 ldr r0, [pc, #36] ; (8000d68 ) 8000d42: f002 f871 bl 8002e28 /* FDCAN2 interrupt Init */ HAL_NVIC_SetPriority(FDCAN2_IT0_IRQn, 0, 0); 8000d46: 2200 movs r2, #0 8000d48: 2100 movs r1, #0 8000d4a: 2014 movs r0, #20 8000d4c: f000 fbcb bl 80014e6 HAL_NVIC_EnableIRQ(FDCAN2_IT0_IRQn); 8000d50: 2014 movs r0, #20 8000d52: f000 fbe2 bl 800151a /* USER CODE BEGIN FDCAN2_MspInit 1 */ /* USER CODE END FDCAN2_MspInit 1 */ } } 8000d56: bf00 nop 8000d58: 37e0 adds r7, #224 ; 0xe0 8000d5a: 46bd mov sp, r7 8000d5c: bd80 pop {r7, pc} 8000d5e: bf00 nop 8000d60: 4000a400 .word 0x4000a400 8000d64: 58024400 .word 0x58024400 8000d68: 58020400 .word 0x58020400 08000d6c : void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef* fdcanHandle) { 8000d6c: b580 push {r7, lr} 8000d6e: b082 sub sp, #8 8000d70: af00 add r7, sp, #0 8000d72: 6078 str r0, [r7, #4] if(fdcanHandle->Instance==FDCAN2) 8000d74: 687b ldr r3, [r7, #4] 8000d76: 681b ldr r3, [r3, #0] 8000d78: 4a0a ldr r2, [pc, #40] ; (8000da4 ) 8000d7a: 4293 cmp r3, r2 8000d7c: d10e bne.n 8000d9c { /* USER CODE BEGIN FDCAN2_MspDeInit 0 */ /* USER CODE END FDCAN2_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_FDCAN_CLK_DISABLE(); 8000d7e: 4b0a ldr r3, [pc, #40] ; (8000da8 ) 8000d80: f8d3 30ec ldr.w r3, [r3, #236] ; 0xec 8000d84: 4a08 ldr r2, [pc, #32] ; (8000da8 ) 8000d86: f423 7380 bic.w r3, r3, #256 ; 0x100 8000d8a: f8c2 30ec str.w r3, [r2, #236] ; 0xec /**FDCAN2 GPIO Configuration PB5 ------> FDCAN2_RX PB6 ------> FDCAN2_TX */ HAL_GPIO_DeInit(GPIOB, GPIO_PIN_5|GPIO_PIN_6); 8000d8e: 2160 movs r1, #96 ; 0x60 8000d90: 4806 ldr r0, [pc, #24] ; (8000dac ) 8000d92: f002 f9f9 bl 8003188 /* FDCAN2 interrupt Deinit */ HAL_NVIC_DisableIRQ(FDCAN2_IT0_IRQn); 8000d96: 2014 movs r0, #20 8000d98: f000 fbcd bl 8001536 /* USER CODE BEGIN FDCAN2_MspDeInit 1 */ /* USER CODE END FDCAN2_MspDeInit 1 */ } } 8000d9c: bf00 nop 8000d9e: 3708 adds r7, #8 8000da0: 46bd mov sp, r7 8000da2: bd80 pop {r7, pc} 8000da4: 4000a400 .word 0x4000a400 8000da8: 58024400 .word 0x58024400 8000dac: 58020400 .word 0x58020400 08000db0 : /** Configure pins PH0-OSC_IN (PH0) ------> RCC_OSC_IN PH1-OSC_OUT (PH1) ------> RCC_OSC_OUT */ void MX_GPIO_Init(void) { 8000db0: b480 push {r7} 8000db2: b083 sub sp, #12 8000db4: af00 add r7, sp, #0 /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOH_CLK_ENABLE(); 8000db6: 4b12 ldr r3, [pc, #72] ; (8000e00 ) 8000db8: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 8000dbc: 4a10 ldr r2, [pc, #64] ; (8000e00 ) 8000dbe: f043 0380 orr.w r3, r3, #128 ; 0x80 8000dc2: f8c2 30e0 str.w r3, [r2, #224] ; 0xe0 8000dc6: 4b0e ldr r3, [pc, #56] ; (8000e00 ) 8000dc8: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 8000dcc: f003 0380 and.w r3, r3, #128 ; 0x80 8000dd0: 607b str r3, [r7, #4] 8000dd2: 687b ldr r3, [r7, #4] __HAL_RCC_GPIOB_CLK_ENABLE(); 8000dd4: 4b0a ldr r3, [pc, #40] ; (8000e00 ) 8000dd6: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 8000dda: 4a09 ldr r2, [pc, #36] ; (8000e00 ) 8000ddc: f043 0302 orr.w r3, r3, #2 8000de0: f8c2 30e0 str.w r3, [r2, #224] ; 0xe0 8000de4: 4b06 ldr r3, [pc, #24] ; (8000e00 ) 8000de6: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 8000dea: f003 0302 and.w r3, r3, #2 8000dee: 603b str r3, [r7, #0] 8000df0: 683b ldr r3, [r7, #0] } 8000df2: bf00 nop 8000df4: 370c adds r7, #12 8000df6: 46bd mov sp, r7 8000df8: f85d 7b04 ldr.w r7, [sp], #4 8000dfc: 4770 bx lr 8000dfe: bf00 nop 8000e00: 58024400 .word 0x58024400 08000e04
: /** * @brief The application entry point. * @retval int */ int main(void) { 8000e04: b580 push {r7, lr} 8000e06: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 8000e08: f000 f9ac bl 8001164 /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 8000e0c: f000 f82a bl 8000e64 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 8000e10: f7ff ffce bl 8000db0 MX_FDCAN2_Init(); 8000e14: f7ff febe bl 8000b94 /* USER CODE BEGIN 2 */ HAL_Delay(10); 8000e18: 200a movs r0, #10 8000e1a: f000 fa35 bl 8001288 can2_SendPacket(g_Can2RxData, 1); 8000e1e: 2101 movs r1, #1 8000e20: 480e ldr r0, [pc, #56] ; (8000e5c ) 8000e22: f7ff faab bl 800037c HAL_Delay(100); //等待程序更新指令，没有等到，跳转到APP，等到就更新程序 8000e26: 2064 movs r0, #100 ; 0x64 8000e28: f000 fa2e bl 8001288 if(Update_EN) 8000e2c: 4b0c ldr r3, [pc, #48] ; (8000e60 ) 8000e2e: 781b ldrb r3, [r3, #0] 8000e30: 2b00 cmp r3, #0 8000e32: d009 beq.n 8000e48 { can2_SendPacket(g_Can2RxData, 2); 8000e34: 2102 movs r1, #2 8000e36: 4809 ldr r0, [pc, #36] ; (8000e5c ) 8000e38: f7ff faa0 bl 800037c HAL_Delay(10); 8000e3c: 200a movs r0, #10 8000e3e: f000 fa23 bl 8001288 DemoCANUpdate(); 8000e42: f7ff fd35 bl 80008b0 8000e46: e008 b.n 8000e5a } else { can2_SendPacket(g_Can2RxData, 3); 8000e48: 2103 movs r1, #3 8000e4a: 4804 ldr r0, [pc, #16] ; (8000e5c ) 8000e4c: f7ff fa96 bl 800037c HAL_Delay(10); 8000e50: 200a movs r0, #10 8000e52: f000 fa19 bl 8001288 JumpToApp(); 8000e56: f7ff fe35 bl 8000ac4 /* USER CODE END 2 */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) 8000e5a: e7fe b.n 8000e5a 8000e5c: 240000f4 .word 0x240000f4 8000e60: 2400035c .word 0x2400035c 08000e64 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 8000e64: b580 push {r7, lr} 8000e66: b09c sub sp, #112 ; 0x70 8000e68: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 8000e6a: f107 0324 add.w r3, r7, #36 ; 0x24 8000e6e: 224c movs r2, #76 ; 0x4c 8000e70: 2100 movs r1, #0 8000e72: 4618 mov r0, r3 8000e74: f004 fc30 bl 80056d8 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8000e78: 1d3b adds r3, r7, #4 8000e7a: 2220 movs r2, #32 8000e7c: 2100 movs r1, #0 8000e7e: 4618 mov r0, r3 8000e80: f004 fc2a bl 80056d8 /** Supply configuration update enable */ HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); 8000e84: 2002 movs r0, #2 8000e86: f002 fa89 bl 800339c /** Configure the main internal regulator output voltage */ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 8000e8a: 2300 movs r3, #0 8000e8c: 603b str r3, [r7, #0] 8000e8e: 4b30 ldr r3, [pc, #192] ; (8000f50 ) 8000e90: 6adb ldr r3, [r3, #44] ; 0x2c 8000e92: 4a2f ldr r2, [pc, #188] ; (8000f50 ) 8000e94: f023 0301 bic.w r3, r3, #1 8000e98: 62d3 str r3, [r2, #44] ; 0x2c 8000e9a: 4b2d ldr r3, [pc, #180] ; (8000f50 ) 8000e9c: 6adb ldr r3, [r3, #44] ; 0x2c 8000e9e: f003 0301 and.w r3, r3, #1 8000ea2: 603b str r3, [r7, #0] 8000ea4: 4b2b ldr r3, [pc, #172] ; (8000f54 ) 8000ea6: 699b ldr r3, [r3, #24] 8000ea8: 4a2a ldr r2, [pc, #168] ; (8000f54 ) 8000eaa: f443 4340 orr.w r3, r3, #49152 ; 0xc000 8000eae: 6193 str r3, [r2, #24] 8000eb0: 4b28 ldr r3, [pc, #160] ; (8000f54 ) 8000eb2: 699b ldr r3, [r3, #24] 8000eb4: f403 4340 and.w r3, r3, #49152 ; 0xc000 8000eb8: 603b str r3, [r7, #0] 8000eba: 683b ldr r3, [r7, #0] while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} 8000ebc: bf00 nop 8000ebe: 4b25 ldr r3, [pc, #148] ; (8000f54 ) 8000ec0: 699b ldr r3, [r3, #24] 8000ec2: f403 5300 and.w r3, r3, #8192 ; 0x2000 8000ec6: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 8000eca: d1f8 bne.n 8000ebe /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; 8000ecc: 2301 movs r3, #1 8000ece: 627b str r3, [r7, #36] ; 0x24 RCC_OscInitStruct.HSEState = RCC_HSE_ON; 8000ed0: f44f 3380 mov.w r3, #65536 ; 0x10000 8000ed4: 62bb str r3, [r7, #40] ; 0x28 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 8000ed6: 2302 movs r3, #2 8000ed8: 64bb str r3, [r7, #72] ; 0x48 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 8000eda: 2302 movs r3, #2 8000edc: 64fb str r3, [r7, #76] ; 0x4c RCC_OscInitStruct.PLL.PLLM = 2; 8000ede: 2302 movs r3, #2 8000ee0: 653b str r3, [r7, #80] ; 0x50 RCC_OscInitStruct.PLL.PLLN = 64; 8000ee2: 2340 movs r3, #64 ; 0x40 8000ee4: 657b str r3, [r7, #84] ; 0x54 RCC_OscInitStruct.PLL.PLLP = 2; 8000ee6: 2302 movs r3, #2 8000ee8: 65bb str r3, [r7, #88] ; 0x58 RCC_OscInitStruct.PLL.PLLQ = 20; 8000eea: 2314 movs r3, #20 8000eec: 65fb str r3, [r7, #92] ; 0x5c RCC_OscInitStruct.PLL.PLLR = 2; 8000eee: 2302 movs r3, #2 8000ef0: 663b str r3, [r7, #96] ; 0x60 RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_3; 8000ef2: 230c movs r3, #12 8000ef4: 667b str r3, [r7, #100] ; 0x64 RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; 8000ef6: 2300 movs r3, #0 8000ef8: 66bb str r3, [r7, #104] ; 0x68 RCC_OscInitStruct.PLL.PLLFRACN = 0; 8000efa: 2300 movs r3, #0 8000efc: 66fb str r3, [r7, #108] ; 0x6c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 8000efe: f107 0324 add.w r3, r7, #36 ; 0x24 8000f02: 4618 mov r0, r3 8000f04: f002 fbae bl 8003664 8000f08: 4603 mov r3, r0 8000f0a: 2b00 cmp r3, #0 8000f0c: d001 beq.n 8000f12 { Error_Handler(); 8000f0e: f000 f823 bl 8000f58 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 8000f12: 233f movs r3, #63 ; 0x3f 8000f14: 607b str r3, [r7, #4] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 8000f16: 2303 movs r3, #3 8000f18: 60bb str r3, [r7, #8] RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; 8000f1a: 2300 movs r3, #0 8000f1c: 60fb str r3, [r7, #12] RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; 8000f1e: 2308 movs r3, #8 8000f20: 613b str r3, [r7, #16] RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; 8000f22: 2340 movs r3, #64 ; 0x40 8000f24: 617b str r3, [r7, #20] RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; 8000f26: 2340 movs r3, #64 ; 0x40 8000f28: 61bb str r3, [r7, #24] RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; 8000f2a: f44f 6380 mov.w r3, #1024 ; 0x400 8000f2e: 61fb str r3, [r7, #28] RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; 8000f30: 2340 movs r3, #64 ; 0x40 8000f32: 623b str r3, [r7, #32] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) 8000f34: 1d3b adds r3, r7, #4 8000f36: 2102 movs r1, #2 8000f38: 4618 mov r0, r3 8000f3a: f002 ffc1 bl 8003ec0 8000f3e: 4603 mov r3, r0 8000f40: 2b00 cmp r3, #0 8000f42: d001 beq.n 8000f48 { Error_Handler(); 8000f44: f000 f808 bl 8000f58 } } 8000f48: bf00 nop 8000f4a: 3770 adds r7, #112 ; 0x70 8000f4c: 46bd mov sp, r7 8000f4e: bd80 pop {r7, pc} 8000f50: 58000400 .word 0x58000400 8000f54: 58024800 .word 0x58024800 08000f58 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8000f58: b480 push {r7} 8000f5a: af00 add r7, sp, #0 __ASM volatile ("cpsid i" : : : "memory"); 8000f5c: b672 cpsid i } 8000f5e: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 8000f60: e7fe b.n 8000f60 ... 08000f64 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8000f64: b480 push {r7} 8000f66: b083 sub sp, #12 8000f68: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8000f6a: 4b0a ldr r3, [pc, #40] ; (8000f94 ) 8000f6c: f8d3 30f4 ldr.w r3, [r3, #244] ; 0xf4 8000f70: 4a08 ldr r2, [pc, #32] ; (8000f94 ) 8000f72: f043 0302 orr.w r3, r3, #2 8000f76: f8c2 30f4 str.w r3, [r2, #244] ; 0xf4 8000f7a: 4b06 ldr r3, [pc, #24] ; (8000f94 ) 8000f7c: f8d3 30f4 ldr.w r3, [r3, #244] ; 0xf4 8000f80: f003 0302 and.w r3, r3, #2 8000f84: 607b str r3, [r7, #4] 8000f86: 687b ldr r3, [r7, #4] /* System interrupt init*/ /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8000f88: bf00 nop 8000f8a: 370c adds r7, #12 8000f8c: 46bd mov sp, r7 8000f8e: f85d 7b04 ldr.w r7, [sp], #4 8000f92: 4770 bx lr 8000f94: 58024400 .word 0x58024400 08000f98 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 8000f98: b480 push {r7} 8000f9a: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 8000f9c: e7fe b.n 8000f9c 08000f9e : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 8000f9e: b480 push {r7} 8000fa0: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 8000fa2: e7fe b.n 8000fa2 08000fa4 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 8000fa4: b480 push {r7} 8000fa6: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 8000fa8: e7fe b.n 8000fa8 08000faa : /** * @brief This function handles Pre-fetch fault, memory access fault. */ void BusFault_Handler(void) { 8000faa: b480 push {r7} 8000fac: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 8000fae: e7fe b.n 8000fae 08000fb0 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 8000fb0: b480 push {r7} 8000fb2: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 8000fb4: e7fe b.n 8000fb4 08000fb6 : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 8000fb6: b480 push {r7} 8000fb8: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 8000fba: bf00 nop 8000fbc: 46bd mov sp, r7 8000fbe: f85d 7b04 ldr.w r7, [sp], #4 8000fc2: 4770 bx lr 08000fc4 : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 8000fc4: b480 push {r7} 8000fc6: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 8000fc8: bf00 nop 8000fca: 46bd mov sp, r7 8000fcc: f85d 7b04 ldr.w r7, [sp], #4 8000fd0: 4770 bx lr 08000fd2 : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 8000fd2: b480 push {r7} 8000fd4: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 8000fd6: bf00 nop 8000fd8: 46bd mov sp, r7 8000fda: f85d 7b04 ldr.w r7, [sp], #4 8000fde: 4770 bx lr 08000fe0 : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 8000fe0: b580 push {r7, lr} 8000fe2: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 8000fe4: f000 f930 bl 8001248 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 8000fe8: bf00 nop 8000fea: bd80 pop {r7, pc} 08000fec : /** * @brief This function handles FDCAN2 interrupt 0. */ void FDCAN2_IT0_IRQHandler(void) { 8000fec: b580 push {r7, lr} 8000fee: af00 add r7, sp, #0 /* USER CODE BEGIN FDCAN2_IT0_IRQn 0 */ /* USER CODE END FDCAN2_IT0_IRQn 0 */ HAL_FDCAN_IRQHandler(&hfdcan2); 8000ff0: 4802 ldr r0, [pc, #8] ; (8000ffc ) 8000ff2: f000 ff07 bl 8001e04 /* USER CODE BEGIN FDCAN2_IT0_IRQn 1 */ /* USER CODE END FDCAN2_IT0_IRQn 1 */ } 8000ff6: bf00 nop 8000ff8: bd80 pop {r7, pc} 8000ffa: bf00 nop 8000ffc: 240002bc .word 0x240002bc 08001000 : * configuration. * @param None * @retval None */ void SystemInit (void) { 8001000: b480 push {r7} 8001002: af00 add r7, sp, #0 __IO uint32_t tmpreg; #endif /* DATA_IN_D2_SRAM */ /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */ 8001004: 4b37 ldr r3, [pc, #220] ; (80010e4 ) 8001006: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 800100a: 4a36 ldr r2, [pc, #216] ; (80010e4 ) 800100c: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000 8001010: f8c2 3088 str.w r3, [r2, #136] ; 0x88 #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Increasing the CPU frequency */ if(FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) 8001014: 4b34 ldr r3, [pc, #208] ; (80010e8 ) 8001016: 681b ldr r3, [r3, #0] 8001018: f003 030f and.w r3, r3, #15 800101c: 2b06 cmp r3, #6 800101e: d807 bhi.n 8001030 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); 8001020: 4b31 ldr r3, [pc, #196] ; (80010e8 ) 8001022: 681b ldr r3, [r3, #0] 8001024: f023 030f bic.w r3, r3, #15 8001028: 4a2f ldr r2, [pc, #188] ; (80010e8 ) 800102a: f043 0307 orr.w r3, r3, #7 800102e: 6013 str r3, [r2, #0] } /* Set HSION bit */ RCC->CR |= RCC_CR_HSION; 8001030: 4b2e ldr r3, [pc, #184] ; (80010ec ) 8001032: 681b ldr r3, [r3, #0] 8001034: 4a2d ldr r2, [pc, #180] ; (80010ec ) 8001036: f043 0301 orr.w r3, r3, #1 800103a: 6013 str r3, [r2, #0] /* Reset CFGR register */ RCC->CFGR = 0x00000000; 800103c: 4b2b ldr r3, [pc, #172] ; (80010ec ) 800103e: 2200 movs r2, #0 8001040: 611a str r2, [r3, #16] /* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */ RCC->CR &= 0xEAF6ED7FU; 8001042: 4b2a ldr r3, [pc, #168] ; (80010ec ) 8001044: 681a ldr r2, [r3, #0] 8001046: 4929 ldr r1, [pc, #164] ; (80010ec ) 8001048: 4b29 ldr r3, [pc, #164] ; (80010f0 ) 800104a: 4013 ands r3, r2 800104c: 600b str r3, [r1, #0] /* Decreasing the number of wait states because of lower CPU frequency */ if(FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) 800104e: 4b26 ldr r3, [pc, #152] ; (80010e8 ) 8001050: 681b ldr r3, [r3, #0] 8001052: f003 0308 and.w r3, r3, #8 8001056: 2b00 cmp r3, #0 8001058: d007 beq.n 800106a { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); 800105a: 4b23 ldr r3, [pc, #140] ; (80010e8 ) 800105c: 681b ldr r3, [r3, #0] 800105e: f023 030f bic.w r3, r3, #15 8001062: 4a21 ldr r2, [pc, #132] ; (80010e8 ) 8001064: f043 0307 orr.w r3, r3, #7 8001068: 6013 str r3, [r2, #0] } #if defined(D3_SRAM_BASE) /* Reset D1CFGR register */ RCC->D1CFGR = 0x00000000; 800106a: 4b20 ldr r3, [pc, #128] ; (80010ec ) 800106c: 2200 movs r2, #0 800106e: 619a str r2, [r3, #24] /* Reset D2CFGR register */ RCC->D2CFGR = 0x00000000; 8001070: 4b1e ldr r3, [pc, #120] ; (80010ec ) 8001072: 2200 movs r2, #0 8001074: 61da str r2, [r3, #28] /* Reset D3CFGR register */ RCC->D3CFGR = 0x00000000; 8001076: 4b1d ldr r3, [pc, #116] ; (80010ec ) 8001078: 2200 movs r2, #0 800107a: 621a str r2, [r3, #32] /* Reset SRDCFGR register */ RCC->SRDCFGR = 0x00000000; #endif /* Reset PLLCKSELR register */ RCC->PLLCKSELR = 0x02020200; 800107c: 4b1b ldr r3, [pc, #108] ; (80010ec ) 800107e: 4a1d ldr r2, [pc, #116] ; (80010f4 ) 8001080: 629a str r2, [r3, #40] ; 0x28 /* Reset PLLCFGR register */ RCC->PLLCFGR = 0x01FF0000; 8001082: 4b1a ldr r3, [pc, #104] ; (80010ec ) 8001084: 4a1c ldr r2, [pc, #112] ; (80010f8 ) 8001086: 62da str r2, [r3, #44] ; 0x2c /* Reset PLL1DIVR register */ RCC->PLL1DIVR = 0x01010280; 8001088: 4b18 ldr r3, [pc, #96] ; (80010ec ) 800108a: 4a1c ldr r2, [pc, #112] ; (80010fc ) 800108c: 631a str r2, [r3, #48] ; 0x30 /* Reset PLL1FRACR register */ RCC->PLL1FRACR = 0x00000000; 800108e: 4b17 ldr r3, [pc, #92] ; (80010ec ) 8001090: 2200 movs r2, #0 8001092: 635a str r2, [r3, #52] ; 0x34 /* Reset PLL2DIVR register */ RCC->PLL2DIVR = 0x01010280; 8001094: 4b15 ldr r3, [pc, #84] ; (80010ec ) 8001096: 4a19 ldr r2, [pc, #100] ; (80010fc ) 8001098: 639a str r2, [r3, #56] ; 0x38 /* Reset PLL2FRACR register */ RCC->PLL2FRACR = 0x00000000; 800109a: 4b14 ldr r3, [pc, #80] ; (80010ec ) 800109c: 2200 movs r2, #0 800109e: 63da str r2, [r3, #60] ; 0x3c /* Reset PLL3DIVR register */ RCC->PLL3DIVR = 0x01010280; 80010a0: 4b12 ldr r3, [pc, #72] ; (80010ec ) 80010a2: 4a16 ldr r2, [pc, #88] ; (80010fc ) 80010a4: 641a str r2, [r3, #64] ; 0x40 /* Reset PLL3FRACR register */ RCC->PLL3FRACR = 0x00000000; 80010a6: 4b11 ldr r3, [pc, #68] ; (80010ec ) 80010a8: 2200 movs r2, #0 80010aa: 645a str r2, [r3, #68] ; 0x44 /* Reset HSEBYP bit */ RCC->CR &= 0xFFFBFFFFU; 80010ac: 4b0f ldr r3, [pc, #60] ; (80010ec ) 80010ae: 681b ldr r3, [r3, #0] 80010b0: 4a0e ldr r2, [pc, #56] ; (80010ec ) 80010b2: f423 2380 bic.w r3, r3, #262144 ; 0x40000 80010b6: 6013 str r3, [r2, #0] /* Disable all interrupts */ RCC->CIER = 0x00000000; 80010b8: 4b0c ldr r3, [pc, #48] ; (80010ec ) 80010ba: 2200 movs r2, #0 80010bc: 661a str r2, [r3, #96] ; 0x60 #if (STM32H7_DEV_ID == 0x450UL) /* dual core CM7 or single core line */ if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U) 80010be: 4b10 ldr r3, [pc, #64] ; (8001100 ) 80010c0: 681a ldr r2, [r3, #0] 80010c2: 4b10 ldr r3, [pc, #64] ; (8001104 ) 80010c4: 4013 ands r3, r2 80010c6: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 80010ca: d202 bcs.n 80010d2 { /* if stm32h7 revY*/ /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */ *((__IO uint32_t*)0x51008108) = 0x000000001U; 80010cc: 4b0e ldr r3, [pc, #56] ; (8001108 ) 80010ce: 2201 movs r2, #1 80010d0: 601a str r2, [r3, #0] /* * Disable the FMC bank1 (enabled after reset). * This, prevents CPU speculation access on this bank which blocks the use of FMC during * 24us. During this time the others FMC master (such as LTDC) cannot use it! */ FMC_Bank1_R->BTCR[0] = 0x000030D2; 80010d2: 4b0e ldr r3, [pc, #56] ; (800110c ) 80010d4: f243 02d2 movw r2, #12498 ; 0x30d2 80010d8: 601a str r2, [r3, #0] #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM or in Internal FLASH */ #endif /* USER_VECT_TAB_ADDRESS */ #endif /*DUAL_CORE && CORE_CM4*/ } 80010da: bf00 nop 80010dc: 46bd mov sp, r7 80010de: f85d 7b04 ldr.w r7, [sp], #4 80010e2: 4770 bx lr 80010e4: e000ed00 .word 0xe000ed00 80010e8: 52002000 .word 0x52002000 80010ec: 58024400 .word 0x58024400 80010f0: eaf6ed7f .word 0xeaf6ed7f 80010f4: 02020200 .word 0x02020200 80010f8: 01ff0000 .word 0x01ff0000 80010fc: 01010280 .word 0x01010280 8001100: 5c001000 .word 0x5c001000 8001104: ffff0000 .word 0xffff0000 8001108: 51008108 .word 0x51008108 800110c: 52004000 .word 0x52004000 08001110 : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* set stack pointer */ 8001110: f8df d034 ldr.w sp, [pc, #52] ; 8001148 /* Call the clock system initialization function.*/ bl SystemInit 8001114: f7ff ff74 bl 8001000 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 8001118: 480c ldr r0, [pc, #48] ; (800114c ) ldr r1, =_edata 800111a: 490d ldr r1, [pc, #52] ; (8001150 ) ldr r2, =_sidata 800111c: 4a0d ldr r2, [pc, #52] ; (8001154 ) movs r3, #0 800111e: 2300 movs r3, #0 b LoopCopyDataInit 8001120: e002 b.n 8001128 08001122 : CopyDataInit: ldr r4, [r2, r3] 8001122: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 8001124: 50c4 str r4, [r0, r3] adds r3, r3, #4 8001126: 3304 adds r3, #4 08001128 : LoopCopyDataInit: adds r4, r0, r3 8001128: 18c4 adds r4, r0, r3 cmp r4, r1 800112a: 428c cmp r4, r1 bcc CopyDataInit 800112c: d3f9 bcc.n 8001122 /* Zero fill the bss segment. */ ldr r2, =_sbss 800112e: 4a0a ldr r2, [pc, #40] ; (8001158 ) ldr r4, =_ebss 8001130: 4c0a ldr r4, [pc, #40] ; (800115c ) movs r3, #0 8001132: 2300 movs r3, #0 b LoopFillZerobss 8001134: e001 b.n 800113a 08001136 : FillZerobss: str r3, [r2] 8001136: 6013 str r3, [r2, #0] adds r2, r2, #4 8001138: 3204 adds r2, #4 0800113a : LoopFillZerobss: cmp r2, r4 800113a: 42a2 cmp r2, r4 bcc FillZerobss 800113c: d3fb bcc.n 8001136 /* Call static constructors */ bl __libc_init_array 800113e: f004 fa99 bl 8005674 <__libc_init_array> /* Call the application's entry point.*/ bl main 8001142: f7ff fe5f bl 8000e04
bx lr 8001146: 4770 bx lr ldr sp, =_estack /* set stack pointer */ 8001148: 24080000 .word 0x24080000 ldr r0, =_sdata 800114c: 24000000 .word 0x24000000 ldr r1, =_edata 8001150: 24000010 .word 0x24000010 ldr r2, =_sidata 8001154: 08005774 .word 0x08005774 ldr r2, =_sbss 8001158: 24000010 .word 0x24000010 ldr r4, =_ebss 800115c: 24000380 .word 0x24000380 08001160 : * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8001160: e7fe b.n 8001160 ... 08001164 : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 8001164: b580 push {r7, lr} 8001166: b082 sub sp, #8 8001168: af00 add r7, sp, #0 __HAL_ART_CONFIG_BASE_ADDRESS(0x08100000UL); /* Configure the Cortex-M4 ART Base address to the Flash Bank 2 : */ __HAL_ART_ENABLE(); /* Enable the Cortex-M4 ART */ #endif /* DUAL_CORE && CORE_CM4 */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 800116a: 2003 movs r0, #3 800116c: f000 f9b0 bl 80014d0 /* Update the SystemCoreClock global variable */ #if defined(RCC_D1CFGR_D1CPRE) common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); 8001170: f003 f85c bl 800422c 8001174: 4602 mov r2, r0 8001176: 4b15 ldr r3, [pc, #84] ; (80011cc ) 8001178: 699b ldr r3, [r3, #24] 800117a: 0a1b lsrs r3, r3, #8 800117c: f003 030f and.w r3, r3, #15 8001180: 4913 ldr r1, [pc, #76] ; (80011d0 ) 8001182: 5ccb ldrb r3, [r1, r3] 8001184: f003 031f and.w r3, r3, #31 8001188: fa22 f303 lsr.w r3, r2, r3 800118c: 607b str r3, [r7, #4] common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU); #endif /* Update the SystemD2Clock global variable */ #if defined(RCC_D1CFGR_HPRE) SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 800118e: 4b0f ldr r3, [pc, #60] ; (80011cc ) 8001190: 699b ldr r3, [r3, #24] 8001192: f003 030f and.w r3, r3, #15 8001196: 4a0e ldr r2, [pc, #56] ; (80011d0 ) 8001198: 5cd3 ldrb r3, [r2, r3] 800119a: f003 031f and.w r3, r3, #31 800119e: 687a ldr r2, [r7, #4] 80011a0: fa22 f303 lsr.w r3, r2, r3 80011a4: 4a0b ldr r2, [pc, #44] ; (80011d4 ) 80011a6: 6013 str r3, [r2, #0] #endif #if defined(DUAL_CORE) && defined(CORE_CM4) SystemCoreClock = SystemD2Clock; #else SystemCoreClock = common_system_clock; 80011a8: 4a0b ldr r2, [pc, #44] ; (80011d8 ) 80011aa: 687b ldr r3, [r7, #4] 80011ac: 6013 str r3, [r2, #0] #endif /* DUAL_CORE && CORE_CM4 */ /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) 80011ae: 200f movs r0, #15 80011b0: f000 f814 bl 80011dc 80011b4: 4603 mov r3, r0 80011b6: 2b00 cmp r3, #0 80011b8: d001 beq.n 80011be { return HAL_ERROR; 80011ba: 2301 movs r3, #1 80011bc: e002 b.n 80011c4 } /* Init the low level hardware */ HAL_MspInit(); 80011be: f7ff fed1 bl 8000f64 /* Return function status */ return HAL_OK; 80011c2: 2300 movs r3, #0 } 80011c4: 4618 mov r0, r3 80011c6: 3708 adds r7, #8 80011c8: 46bd mov sp, r7 80011ca: bd80 pop {r7, pc} 80011cc: 58024400 .word 0x58024400 80011d0: 0800574c .word 0x0800574c 80011d4: 24000004 .word 0x24000004 80011d8: 24000000 .word 0x24000000 080011dc : * implementation in user file. * @param TickPriority: Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 80011dc: b580 push {r7, lr} 80011de: b082 sub sp, #8 80011e0: af00 add r7, sp, #0 80011e2: 6078 str r0, [r7, #4] /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that don't take the value zero)*/ if((uint32_t)uwTickFreq == 0UL) 80011e4: 4b15 ldr r3, [pc, #84] ; (800123c ) 80011e6: 781b ldrb r3, [r3, #0] 80011e8: 2b00 cmp r3, #0 80011ea: d101 bne.n 80011f0 { return HAL_ERROR; 80011ec: 2301 movs r3, #1 80011ee: e021 b.n 8001234 } /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U) 80011f0: 4b13 ldr r3, [pc, #76] ; (8001240 ) 80011f2: 681a ldr r2, [r3, #0] 80011f4: 4b11 ldr r3, [pc, #68] ; (800123c ) 80011f6: 781b ldrb r3, [r3, #0] 80011f8: 4619 mov r1, r3 80011fa: f44f 737a mov.w r3, #1000 ; 0x3e8 80011fe: fbb3 f3f1 udiv r3, r3, r1 8001202: fbb2 f3f3 udiv r3, r2, r3 8001206: 4618 mov r0, r3 8001208: f000 f9a3 bl 8001552 800120c: 4603 mov r3, r0 800120e: 2b00 cmp r3, #0 8001210: d001 beq.n 8001216 { return HAL_ERROR; 8001212: 2301 movs r3, #1 8001214: e00e b.n 8001234 } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 8001216: 687b ldr r3, [r7, #4] 8001218: 2b0f cmp r3, #15 800121a: d80a bhi.n 8001232 { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 800121c: 2200 movs r2, #0 800121e: 6879 ldr r1, [r7, #4] 8001220: f04f 30ff mov.w r0, #4294967295 8001224: f000 f95f bl 80014e6 uwTickPrio = TickPriority; 8001228: 4a06 ldr r2, [pc, #24] ; (8001244 ) 800122a: 687b ldr r3, [r7, #4] 800122c: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; 800122e: 2300 movs r3, #0 8001230: e000 b.n 8001234 return HAL_ERROR; 8001232: 2301 movs r3, #1 } 8001234: 4618 mov r0, r3 8001236: 3708 adds r7, #8 8001238: 46bd mov sp, r7 800123a: bd80 pop {r7, pc} 800123c: 2400000c .word 0x2400000c 8001240: 24000000 .word 0x24000000 8001244: 24000008 .word 0x24000008 08001248 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8001248: b480 push {r7} 800124a: af00 add r7, sp, #0 uwTick += (uint32_t)uwTickFreq; 800124c: 4b06 ldr r3, [pc, #24] ; (8001268 ) 800124e: 781b ldrb r3, [r3, #0] 8001250: 461a mov r2, r3 8001252: 4b06 ldr r3, [pc, #24] ; (800126c ) 8001254: 681b ldr r3, [r3, #0] 8001256: 4413 add r3, r2 8001258: 4a04 ldr r2, [pc, #16] ; (800126c ) 800125a: 6013 str r3, [r2, #0] } 800125c: bf00 nop 800125e: 46bd mov sp, r7 8001260: f85d 7b04 ldr.w r7, [sp], #4 8001264: 4770 bx lr 8001266: bf00 nop 8001268: 2400000c .word 0x2400000c 800126c: 24000360 .word 0x24000360 08001270 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8001270: b480 push {r7} 8001272: af00 add r7, sp, #0 return uwTick; 8001274: 4b03 ldr r3, [pc, #12] ; (8001284 ) 8001276: 681b ldr r3, [r3, #0] } 8001278: 4618 mov r0, r3 800127a: 46bd mov sp, r7 800127c: f85d 7b04 ldr.w r7, [sp], #4 8001280: 4770 bx lr 8001282: bf00 nop 8001284: 24000360 .word 0x24000360 08001288 : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 8001288: b580 push {r7, lr} 800128a: b084 sub sp, #16 800128c: af00 add r7, sp, #0 800128e: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 8001290: f7ff ffee bl 8001270 8001294: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 8001296: 687b ldr r3, [r7, #4] 8001298: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 800129a: 68fb ldr r3, [r7, #12] 800129c: f1b3 3fff cmp.w r3, #4294967295 80012a0: d005 beq.n 80012ae { wait += (uint32_t)(uwTickFreq); 80012a2: 4b0a ldr r3, [pc, #40] ; (80012cc ) 80012a4: 781b ldrb r3, [r3, #0] 80012a6: 461a mov r2, r3 80012a8: 68fb ldr r3, [r7, #12] 80012aa: 4413 add r3, r2 80012ac: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait) 80012ae: bf00 nop 80012b0: f7ff ffde bl 8001270 80012b4: 4602 mov r2, r0 80012b6: 68bb ldr r3, [r7, #8] 80012b8: 1ad3 subs r3, r2, r3 80012ba: 68fa ldr r2, [r7, #12] 80012bc: 429a cmp r2, r3 80012be: d8f7 bhi.n 80012b0 { } } 80012c0: bf00 nop 80012c2: bf00 nop 80012c4: 3710 adds r7, #16 80012c6: 46bd mov sp, r7 80012c8: bd80 pop {r7, pc} 80012ca: bf00 nop 80012cc: 2400000c .word 0x2400000c 080012d0 : /** * @brief Returns the device revision identifier. * @retval Device revision identifier */ uint32_t HAL_GetREVID(void) { 80012d0: b480 push {r7} 80012d2: af00 add r7, sp, #0 return((DBGMCU->IDCODE) >> 16); 80012d4: 4b03 ldr r3, [pc, #12] ; (80012e4 ) 80012d6: 681b ldr r3, [r3, #0] 80012d8: 0c1b lsrs r3, r3, #16 } 80012da: 4618 mov r0, r3 80012dc: 46bd mov sp, r7 80012de: f85d 7b04 ldr.w r7, [sp], #4 80012e2: 4770 bx lr 80012e4: 5c001000 .word 0x5c001000 080012e8 <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 80012e8: b480 push {r7} 80012ea: b085 sub sp, #20 80012ec: af00 add r7, sp, #0 80012ee: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 80012f0: 687b ldr r3, [r7, #4] 80012f2: f003 0307 and.w r3, r3, #7 80012f6: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 80012f8: 4b0b ldr r3, [pc, #44] ; (8001328 <__NVIC_SetPriorityGrouping+0x40>) 80012fa: 68db ldr r3, [r3, #12] 80012fc: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 80012fe: 68ba ldr r2, [r7, #8] 8001300: f64f 03ff movw r3, #63743 ; 0xf8ff 8001304: 4013 ands r3, r2 8001306: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 8001308: 68fb ldr r3, [r7, #12] 800130a: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 800130c: 68bb ldr r3, [r7, #8] 800130e: 431a orrs r2, r3 reg_value = (reg_value | 8001310: 4b06 ldr r3, [pc, #24] ; (800132c <__NVIC_SetPriorityGrouping+0x44>) 8001312: 4313 orrs r3, r2 8001314: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 8001316: 4a04 ldr r2, [pc, #16] ; (8001328 <__NVIC_SetPriorityGrouping+0x40>) 8001318: 68bb ldr r3, [r7, #8] 800131a: 60d3 str r3, [r2, #12] } 800131c: bf00 nop 800131e: 3714 adds r7, #20 8001320: 46bd mov sp, r7 8001322: f85d 7b04 ldr.w r7, [sp], #4 8001326: 4770 bx lr 8001328: e000ed00 .word 0xe000ed00 800132c: 05fa0000 .word 0x05fa0000 08001330 <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 8001330: b480 push {r7} 8001332: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8001334: 4b04 ldr r3, [pc, #16] ; (8001348 <__NVIC_GetPriorityGrouping+0x18>) 8001336: 68db ldr r3, [r3, #12] 8001338: 0a1b lsrs r3, r3, #8 800133a: f003 0307 and.w r3, r3, #7 } 800133e: 4618 mov r0, r3 8001340: 46bd mov sp, r7 8001342: f85d 7b04 ldr.w r7, [sp], #4 8001346: 4770 bx lr 8001348: e000ed00 .word 0xe000ed00 0800134c <__NVIC_EnableIRQ>: \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { 800134c: b480 push {r7} 800134e: b083 sub sp, #12 8001350: af00 add r7, sp, #0 8001352: 4603 mov r3, r0 8001354: 80fb strh r3, [r7, #6] if ((int32_t)(IRQn) >= 0) 8001356: f9b7 3006 ldrsh.w r3, [r7, #6] 800135a: 2b00 cmp r3, #0 800135c: db0b blt.n 8001376 <__NVIC_EnableIRQ+0x2a> { __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 800135e: 88fb ldrh r3, [r7, #6] 8001360: f003 021f and.w r2, r3, #31 8001364: 4907 ldr r1, [pc, #28] ; (8001384 <__NVIC_EnableIRQ+0x38>) 8001366: f9b7 3006 ldrsh.w r3, [r7, #6] 800136a: 095b lsrs r3, r3, #5 800136c: 2001 movs r0, #1 800136e: fa00 f202 lsl.w r2, r0, r2 8001372: f841 2023 str.w r2, [r1, r3, lsl #2] __COMPILER_BARRIER(); } } 8001376: bf00 nop 8001378: 370c adds r7, #12 800137a: 46bd mov sp, r7 800137c: f85d 7b04 ldr.w r7, [sp], #4 8001380: 4770 bx lr 8001382: bf00 nop 8001384: e000e100 .word 0xe000e100 08001388 <__NVIC_DisableIRQ>: \details Disables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) { 8001388: b480 push {r7} 800138a: b083 sub sp, #12 800138c: af00 add r7, sp, #0 800138e: 4603 mov r3, r0 8001390: 80fb strh r3, [r7, #6] if ((int32_t)(IRQn) >= 0) 8001392: f9b7 3006 ldrsh.w r3, [r7, #6] 8001396: 2b00 cmp r3, #0 8001398: db12 blt.n 80013c0 <__NVIC_DisableIRQ+0x38> { NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 800139a: 88fb ldrh r3, [r7, #6] 800139c: f003 021f and.w r2, r3, #31 80013a0: 490a ldr r1, [pc, #40] ; (80013cc <__NVIC_DisableIRQ+0x44>) 80013a2: f9b7 3006 ldrsh.w r3, [r7, #6] 80013a6: 095b lsrs r3, r3, #5 80013a8: 2001 movs r0, #1 80013aa: fa00 f202 lsl.w r2, r0, r2 80013ae: 3320 adds r3, #32 80013b0: f841 2023 str.w r2, [r1, r3, lsl #2] \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ __STATIC_FORCEINLINE void __DSB(void) { __ASM volatile ("dsb 0xF":::"memory"); 80013b4: f3bf 8f4f dsb sy } 80013b8: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 80013ba: f3bf 8f6f isb sy } 80013be: bf00 nop __DSB(); __ISB(); } } 80013c0: bf00 nop 80013c2: 370c adds r7, #12 80013c4: 46bd mov sp, r7 80013c6: f85d 7b04 ldr.w r7, [sp], #4 80013ca: 4770 bx lr 80013cc: e000e100 .word 0xe000e100 080013d0 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 80013d0: b480 push {r7} 80013d2: b083 sub sp, #12 80013d4: af00 add r7, sp, #0 80013d6: 4603 mov r3, r0 80013d8: 6039 str r1, [r7, #0] 80013da: 80fb strh r3, [r7, #6] if ((int32_t)(IRQn) >= 0) 80013dc: f9b7 3006 ldrsh.w r3, [r7, #6] 80013e0: 2b00 cmp r3, #0 80013e2: db0a blt.n 80013fa <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 80013e4: 683b ldr r3, [r7, #0] 80013e6: b2da uxtb r2, r3 80013e8: 490c ldr r1, [pc, #48] ; (800141c <__NVIC_SetPriority+0x4c>) 80013ea: f9b7 3006 ldrsh.w r3, [r7, #6] 80013ee: 0112 lsls r2, r2, #4 80013f0: b2d2 uxtb r2, r2 80013f2: 440b add r3, r1 80013f4: f883 2300 strb.w r2, [r3, #768] ; 0x300 } else { SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 80013f8: e00a b.n 8001410 <__NVIC_SetPriority+0x40> SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 80013fa: 683b ldr r3, [r7, #0] 80013fc: b2da uxtb r2, r3 80013fe: 4908 ldr r1, [pc, #32] ; (8001420 <__NVIC_SetPriority+0x50>) 8001400: 88fb ldrh r3, [r7, #6] 8001402: f003 030f and.w r3, r3, #15 8001406: 3b04 subs r3, #4 8001408: 0112 lsls r2, r2, #4 800140a: b2d2 uxtb r2, r2 800140c: 440b add r3, r1 800140e: 761a strb r2, [r3, #24] } 8001410: bf00 nop 8001412: 370c adds r7, #12 8001414: 46bd mov sp, r7 8001416: f85d 7b04 ldr.w r7, [sp], #4 800141a: 4770 bx lr 800141c: e000e100 .word 0xe000e100 8001420: e000ed00 .word 0xe000ed00 08001424 : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 8001424: b480 push {r7} 8001426: b089 sub sp, #36 ; 0x24 8001428: af00 add r7, sp, #0 800142a: 60f8 str r0, [r7, #12] 800142c: 60b9 str r1, [r7, #8] 800142e: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8001430: 68fb ldr r3, [r7, #12] 8001432: f003 0307 and.w r3, r3, #7 8001436: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8001438: 69fb ldr r3, [r7, #28] 800143a: f1c3 0307 rsb r3, r3, #7 800143e: 2b04 cmp r3, #4 8001440: bf28 it cs 8001442: 2304 movcs r3, #4 8001444: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 8001446: 69fb ldr r3, [r7, #28] 8001448: 3304 adds r3, #4 800144a: 2b06 cmp r3, #6 800144c: d902 bls.n 8001454 800144e: 69fb ldr r3, [r7, #28] 8001450: 3b03 subs r3, #3 8001452: e000 b.n 8001456 8001454: 2300 movs r3, #0 8001456: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8001458: f04f 32ff mov.w r2, #4294967295 800145c: 69bb ldr r3, [r7, #24] 800145e: fa02 f303 lsl.w r3, r2, r3 8001462: 43da mvns r2, r3 8001464: 68bb ldr r3, [r7, #8] 8001466: 401a ands r2, r3 8001468: 697b ldr r3, [r7, #20] 800146a: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 800146c: f04f 31ff mov.w r1, #4294967295 8001470: 697b ldr r3, [r7, #20] 8001472: fa01 f303 lsl.w r3, r1, r3 8001476: 43d9 mvns r1, r3 8001478: 687b ldr r3, [r7, #4] 800147a: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 800147c: 4313 orrs r3, r2 ); } 800147e: 4618 mov r0, r3 8001480: 3724 adds r7, #36 ; 0x24 8001482: 46bd mov sp, r7 8001484: f85d 7b04 ldr.w r7, [sp], #4 8001488: 4770 bx lr ... 0800148c : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 800148c: b580 push {r7, lr} 800148e: b082 sub sp, #8 8001490: af00 add r7, sp, #0 8001492: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 8001494: 687b ldr r3, [r7, #4] 8001496: 3b01 subs r3, #1 8001498: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 800149c: d301 bcc.n 80014a2 { return (1UL); /* Reload value impossible */ 800149e: 2301 movs r3, #1 80014a0: e00f b.n 80014c2 } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 80014a2: 4a0a ldr r2, [pc, #40] ; (80014cc ) 80014a4: 687b ldr r3, [r7, #4] 80014a6: 3b01 subs r3, #1 80014a8: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 80014aa: 210f movs r1, #15 80014ac: f04f 30ff mov.w r0, #4294967295 80014b0: f7ff ff8e bl 80013d0 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 80014b4: 4b05 ldr r3, [pc, #20] ; (80014cc ) 80014b6: 2200 movs r2, #0 80014b8: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 80014ba: 4b04 ldr r3, [pc, #16] ; (80014cc ) 80014bc: 2207 movs r2, #7 80014be: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 80014c0: 2300 movs r3, #0 } 80014c2: 4618 mov r0, r3 80014c4: 3708 adds r7, #8 80014c6: 46bd mov sp, r7 80014c8: bd80 pop {r7, pc} 80014ca: bf00 nop 80014cc: e000e010 .word 0xe000e010 080014d0 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 80014d0: b580 push {r7, lr} 80014d2: b082 sub sp, #8 80014d4: af00 add r7, sp, #0 80014d6: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 80014d8: 6878 ldr r0, [r7, #4] 80014da: f7ff ff05 bl 80012e8 <__NVIC_SetPriorityGrouping> } 80014de: bf00 nop 80014e0: 3708 adds r7, #8 80014e2: 46bd mov sp, r7 80014e4: bd80 pop {r7, pc} 080014e6 : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 80014e6: b580 push {r7, lr} 80014e8: b086 sub sp, #24 80014ea: af00 add r7, sp, #0 80014ec: 4603 mov r3, r0 80014ee: 60b9 str r1, [r7, #8] 80014f0: 607a str r2, [r7, #4] 80014f2: 81fb strh r3, [r7, #14] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 80014f4: f7ff ff1c bl 8001330 <__NVIC_GetPriorityGrouping> 80014f8: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 80014fa: 687a ldr r2, [r7, #4] 80014fc: 68b9 ldr r1, [r7, #8] 80014fe: 6978 ldr r0, [r7, #20] 8001500: f7ff ff90 bl 8001424 8001504: 4602 mov r2, r0 8001506: f9b7 300e ldrsh.w r3, [r7, #14] 800150a: 4611 mov r1, r2 800150c: 4618 mov r0, r3 800150e: f7ff ff5f bl 80013d0 <__NVIC_SetPriority> } 8001512: bf00 nop 8001514: 3718 adds r7, #24 8001516: 46bd mov sp, r7 8001518: bd80 pop {r7, pc} 0800151a : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 800151a: b580 push {r7, lr} 800151c: b082 sub sp, #8 800151e: af00 add r7, sp, #0 8001520: 4603 mov r3, r0 8001522: 80fb strh r3, [r7, #6] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 8001524: f9b7 3006 ldrsh.w r3, [r7, #6] 8001528: 4618 mov r0, r3 800152a: f7ff ff0f bl 800134c <__NVIC_EnableIRQ> } 800152e: bf00 nop 8001530: 3708 adds r7, #8 8001532: 46bd mov sp, r7 8001534: bd80 pop {r7, pc} 08001536 : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h)) * @retval None */ void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) { 8001536: b580 push {r7, lr} 8001538: b082 sub sp, #8 800153a: af00 add r7, sp, #0 800153c: 4603 mov r3, r0 800153e: 80fb strh r3, [r7, #6] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Disable interrupt */ NVIC_DisableIRQ(IRQn); 8001540: f9b7 3006 ldrsh.w r3, [r7, #6] 8001544: 4618 mov r0, r3 8001546: f7ff ff1f bl 8001388 <__NVIC_DisableIRQ> } 800154a: bf00 nop 800154c: 3708 adds r7, #8 800154e: 46bd mov sp, r7 8001550: bd80 pop {r7, pc} 08001552 : * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. * @retval status - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 8001552: b580 push {r7, lr} 8001554: b082 sub sp, #8 8001556: af00 add r7, sp, #0 8001558: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 800155a: 6878 ldr r0, [r7, #4] 800155c: f7ff ff96 bl 800148c 8001560: 4603 mov r3, r0 } 8001562: 4618 mov r0, r3 8001564: 3708 adds r7, #8 8001566: 46bd mov sp, r7 8001568: bd80 pop {r7, pc} ... 0800156c : * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains * the configuration information for the specified FDCAN. * @retval HAL status */ HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan) { 800156c: b580 push {r7, lr} 800156e: b098 sub sp, #96 ; 0x60 8001570: af00 add r7, sp, #0 8001572: 6078 str r0, [r7, #4] uint32_t tickstart; HAL_StatusTypeDef status; const uint32_t CvtEltSize[] = {0, 0, 0, 0, 0, 1, 2, 3, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0, 7}; 8001574: 4a84 ldr r2, [pc, #528] ; (8001788 ) 8001576: f107 030c add.w r3, r7, #12 800157a: 4611 mov r1, r2 800157c: 224c movs r2, #76 ; 0x4c 800157e: 4618 mov r0, r3 8001580: f004 f89c bl 80056bc /* Check FDCAN handle */ if (hfdcan == NULL) 8001584: 687b ldr r3, [r7, #4] 8001586: 2b00 cmp r3, #0 8001588: d101 bne.n 800158e { return HAL_ERROR; 800158a: 2301 movs r3, #1 800158c: e1c6 b.n 800191c } /* Check FDCAN instance */ if (hfdcan->Instance == FDCAN1) 800158e: 687b ldr r3, [r7, #4] 8001590: 681b ldr r3, [r3, #0] 8001592: 4a7e ldr r2, [pc, #504] ; (800178c ) 8001594: 4293 cmp r3, r2 8001596: d106 bne.n 80015a6 { hfdcan->ttcan = (TTCAN_TypeDef *)((uint32_t)hfdcan->Instance + 0x100U); 8001598: 687b ldr r3, [r7, #4] 800159a: 681b ldr r3, [r3, #0] 800159c: f503 7380 add.w r3, r3, #256 ; 0x100 80015a0: 461a mov r2, r3 80015a2: 687b ldr r3, [r7, #4] 80015a4: 605a str r2, [r3, #4] /* Init the low level hardware: CLOCK, NVIC */ hfdcan->MspInitCallback(hfdcan); } #else if (hfdcan->State == HAL_FDCAN_STATE_RESET) 80015a6: 687b ldr r3, [r7, #4] 80015a8: f893 3098 ldrb.w r3, [r3, #152] ; 0x98 80015ac: b2db uxtb r3, r3 80015ae: 2b00 cmp r3, #0 80015b0: d106 bne.n 80015c0 { /* Allocate lock resource and initialize it */ hfdcan->Lock = HAL_UNLOCKED; 80015b2: 687b ldr r3, [r7, #4] 80015b4: 2200 movs r2, #0 80015b6: f883 2099 strb.w r2, [r3, #153] ; 0x99 /* Init the low level hardware: CLOCK, NVIC */ HAL_FDCAN_MspInit(hfdcan); 80015ba: 6878 ldr r0, [r7, #4] 80015bc: f7ff fb68 bl 8000c90 } #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ /* Exit from Sleep mode */ CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR); 80015c0: 687b ldr r3, [r7, #4] 80015c2: 681b ldr r3, [r3, #0] 80015c4: 699a ldr r2, [r3, #24] 80015c6: 687b ldr r3, [r7, #4] 80015c8: 681b ldr r3, [r3, #0] 80015ca: f022 0210 bic.w r2, r2, #16 80015ce: 619a str r2, [r3, #24] /* Get tick */ tickstart = HAL_GetTick(); 80015d0: f7ff fe4e bl 8001270 80015d4: 65f8 str r0, [r7, #92] ; 0x5c /* Check Sleep mode acknowledge */ while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA) 80015d6: e014 b.n 8001602 { if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE) 80015d8: f7ff fe4a bl 8001270 80015dc: 4602 mov r2, r0 80015de: 6dfb ldr r3, [r7, #92] ; 0x5c 80015e0: 1ad3 subs r3, r2, r3 80015e2: 2b0a cmp r3, #10 80015e4: d90d bls.n 8001602 { /* Update error code */ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; 80015e6: 687b ldr r3, [r7, #4] 80015e8: f8d3 309c ldr.w r3, [r3, #156] ; 0x9c 80015ec: f043 0201 orr.w r2, r3, #1 80015f0: 687b ldr r3, [r7, #4] 80015f2: f8c3 209c str.w r2, [r3, #156] ; 0x9c /* Change FDCAN state */ hfdcan->State = HAL_FDCAN_STATE_ERROR; 80015f6: 687b ldr r3, [r7, #4] 80015f8: 2203 movs r2, #3 80015fa: f883 2098 strb.w r2, [r3, #152] ; 0x98 return HAL_ERROR; 80015fe: 2301 movs r3, #1 8001600: e18c b.n 800191c while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA) 8001602: 687b ldr r3, [r7, #4] 8001604: 681b ldr r3, [r3, #0] 8001606: 699b ldr r3, [r3, #24] 8001608: f003 0308 and.w r3, r3, #8 800160c: 2b08 cmp r3, #8 800160e: d0e3 beq.n 80015d8 } } /* Request initialisation */ SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT); 8001610: 687b ldr r3, [r7, #4] 8001612: 681b ldr r3, [r3, #0] 8001614: 699a ldr r2, [r3, #24] 8001616: 687b ldr r3, [r7, #4] 8001618: 681b ldr r3, [r3, #0] 800161a: f042 0201 orr.w r2, r2, #1 800161e: 619a str r2, [r3, #24] /* Get tick */ tickstart = HAL_GetTick(); 8001620: f7ff fe26 bl 8001270 8001624: 65f8 str r0, [r7, #92] ; 0x5c /* Wait until the INIT bit into CCCR register is set */ while ((hfdcan->Instance->CCCR & FDCAN_CCCR_INIT) == 0U) 8001626: e014 b.n 8001652 { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE) 8001628: f7ff fe22 bl 8001270 800162c: 4602 mov r2, r0 800162e: 6dfb ldr r3, [r7, #92] ; 0x5c 8001630: 1ad3 subs r3, r2, r3 8001632: 2b0a cmp r3, #10 8001634: d90d bls.n 8001652 { /* Update error code */ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; 8001636: 687b ldr r3, [r7, #4] 8001638: f8d3 309c ldr.w r3, [r3, #156] ; 0x9c 800163c: f043 0201 orr.w r2, r3, #1 8001640: 687b ldr r3, [r7, #4] 8001642: f8c3 209c str.w r2, [r3, #156] ; 0x9c /* Change FDCAN state */ hfdcan->State = HAL_FDCAN_STATE_ERROR; 8001646: 687b ldr r3, [r7, #4] 8001648: 2203 movs r2, #3 800164a: f883 2098 strb.w r2, [r3, #152] ; 0x98 return HAL_ERROR; 800164e: 2301 movs r3, #1 8001650: e164 b.n 800191c while ((hfdcan->Instance->CCCR & FDCAN_CCCR_INIT) == 0U) 8001652: 687b ldr r3, [r7, #4] 8001654: 681b ldr r3, [r3, #0] 8001656: 699b ldr r3, [r3, #24] 8001658: f003 0301 and.w r3, r3, #1 800165c: 2b00 cmp r3, #0 800165e: d0e3 beq.n 8001628 } } /* Enable configuration change */ SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CCE); 8001660: 687b ldr r3, [r7, #4] 8001662: 681b ldr r3, [r3, #0] 8001664: 699a ldr r2, [r3, #24] 8001666: 687b ldr r3, [r7, #4] 8001668: 681b ldr r3, [r3, #0] 800166a: f042 0202 orr.w r2, r2, #2 800166e: 619a str r2, [r3, #24] /* Set the no automatic retransmission */ if (hfdcan->Init.AutoRetransmission == ENABLE) 8001670: 687b ldr r3, [r7, #4] 8001672: 7c1b ldrb r3, [r3, #16] 8001674: 2b01 cmp r3, #1 8001676: d108 bne.n 800168a { CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_DAR); 8001678: 687b ldr r3, [r7, #4] 800167a: 681b ldr r3, [r3, #0] 800167c: 699a ldr r2, [r3, #24] 800167e: 687b ldr r3, [r7, #4] 8001680: 681b ldr r3, [r3, #0] 8001682: f022 0240 bic.w r2, r2, #64 ; 0x40 8001686: 619a str r2, [r3, #24] 8001688: e007 b.n 800169a } else { SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_DAR); 800168a: 687b ldr r3, [r7, #4] 800168c: 681b ldr r3, [r3, #0] 800168e: 699a ldr r2, [r3, #24] 8001690: 687b ldr r3, [r7, #4] 8001692: 681b ldr r3, [r3, #0] 8001694: f042 0240 orr.w r2, r2, #64 ; 0x40 8001698: 619a str r2, [r3, #24] } /* Set the transmit pause feature */ if (hfdcan->Init.TransmitPause == ENABLE) 800169a: 687b ldr r3, [r7, #4] 800169c: 7c5b ldrb r3, [r3, #17] 800169e: 2b01 cmp r3, #1 80016a0: d108 bne.n 80016b4 { SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TXP); 80016a2: 687b ldr r3, [r7, #4] 80016a4: 681b ldr r3, [r3, #0] 80016a6: 699a ldr r2, [r3, #24] 80016a8: 687b ldr r3, [r7, #4] 80016aa: 681b ldr r3, [r3, #0] 80016ac: f442 4280 orr.w r2, r2, #16384 ; 0x4000 80016b0: 619a str r2, [r3, #24] 80016b2: e007 b.n 80016c4 } else { CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TXP); 80016b4: 687b ldr r3, [r7, #4] 80016b6: 681b ldr r3, [r3, #0] 80016b8: 699a ldr r2, [r3, #24] 80016ba: 687b ldr r3, [r7, #4] 80016bc: 681b ldr r3, [r3, #0] 80016be: f422 4280 bic.w r2, r2, #16384 ; 0x4000 80016c2: 619a str r2, [r3, #24] } /* Set the Protocol Exception Handling */ if (hfdcan->Init.ProtocolException == ENABLE) 80016c4: 687b ldr r3, [r7, #4] 80016c6: 7c9b ldrb r3, [r3, #18] 80016c8: 2b01 cmp r3, #1 80016ca: d108 bne.n 80016de { CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_PXHD); 80016cc: 687b ldr r3, [r7, #4] 80016ce: 681b ldr r3, [r3, #0] 80016d0: 699a ldr r2, [r3, #24] 80016d2: 687b ldr r3, [r7, #4] 80016d4: 681b ldr r3, [r3, #0] 80016d6: f422 5280 bic.w r2, r2, #4096 ; 0x1000 80016da: 619a str r2, [r3, #24] 80016dc: e007 b.n 80016ee } else { SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_PXHD); 80016de: 687b ldr r3, [r7, #4] 80016e0: 681b ldr r3, [r3, #0] 80016e2: 699a ldr r2, [r3, #24] 80016e4: 687b ldr r3, [r7, #4] 80016e6: 681b ldr r3, [r3, #0] 80016e8: f442 5280 orr.w r2, r2, #4096 ; 0x1000 80016ec: 619a str r2, [r3, #24] } /* Set FDCAN Frame Format */ MODIFY_REG(hfdcan->Instance->CCCR, FDCAN_FRAME_FD_BRS, hfdcan->Init.FrameFormat); 80016ee: 687b ldr r3, [r7, #4] 80016f0: 681b ldr r3, [r3, #0] 80016f2: 699b ldr r3, [r3, #24] 80016f4: f423 7140 bic.w r1, r3, #768 ; 0x300 80016f8: 687b ldr r3, [r7, #4] 80016fa: 689a ldr r2, [r3, #8] 80016fc: 687b ldr r3, [r7, #4] 80016fe: 681b ldr r3, [r3, #0] 8001700: 430a orrs r2, r1 8001702: 619a str r2, [r3, #24] /* Reset FDCAN Operation Mode */ CLEAR_BIT(hfdcan->Instance->CCCR, (FDCAN_CCCR_TEST | FDCAN_CCCR_MON | FDCAN_CCCR_ASM)); 8001704: 687b ldr r3, [r7, #4] 8001706: 681b ldr r3, [r3, #0] 8001708: 699a ldr r2, [r3, #24] 800170a: 687b ldr r3, [r7, #4] 800170c: 681b ldr r3, [r3, #0] 800170e: f022 02a4 bic.w r2, r2, #164 ; 0xa4 8001712: 619a str r2, [r3, #24] CLEAR_BIT(hfdcan->Instance->TEST, FDCAN_TEST_LBCK); 8001714: 687b ldr r3, [r7, #4] 8001716: 681b ldr r3, [r3, #0] 8001718: 691a ldr r2, [r3, #16] 800171a: 687b ldr r3, [r7, #4] 800171c: 681b ldr r3, [r3, #0] 800171e: f022 0210 bic.w r2, r2, #16 8001722: 611a str r2, [r3, #16] CCCR.TEST | 0 | 0 | 0 | 1 | 1 CCCR.MON | 0 | 0 | 1 | 1 | 0 TEST.LBCK | 0 | 0 | 0 | 1 | 1 CCCR.ASM | 0 | 1 | 0 | 0 | 0 */ if (hfdcan->Init.Mode == FDCAN_MODE_RESTRICTED_OPERATION) 8001724: 687b ldr r3, [r7, #4] 8001726: 68db ldr r3, [r3, #12] 8001728: 2b01 cmp r3, #1 800172a: d108 bne.n 800173e { /* Enable Restricted Operation mode */ SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_ASM); 800172c: 687b ldr r3, [r7, #4] 800172e: 681b ldr r3, [r3, #0] 8001730: 699a ldr r2, [r3, #24] 8001732: 687b ldr r3, [r7, #4] 8001734: 681b ldr r3, [r3, #0] 8001736: f042 0204 orr.w r2, r2, #4 800173a: 619a str r2, [r3, #24] 800173c: e030 b.n 80017a0 } else if (hfdcan->Init.Mode != FDCAN_MODE_NORMAL) 800173e: 687b ldr r3, [r7, #4] 8001740: 68db ldr r3, [r3, #12] 8001742: 2b00 cmp r3, #0 8001744: d02c beq.n 80017a0 { if (hfdcan->Init.Mode != FDCAN_MODE_BUS_MONITORING) 8001746: 687b ldr r3, [r7, #4] 8001748: 68db ldr r3, [r3, #12] 800174a: 2b02 cmp r3, #2 800174c: d020 beq.n 8001790 { /* Enable write access to TEST register */ SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TEST); 800174e: 687b ldr r3, [r7, #4] 8001750: 681b ldr r3, [r3, #0] 8001752: 699a ldr r2, [r3, #24] 8001754: 687b ldr r3, [r7, #4] 8001756: 681b ldr r3, [r3, #0] 8001758: f042 0280 orr.w r2, r2, #128 ; 0x80 800175c: 619a str r2, [r3, #24] /* Enable LoopBack mode */ SET_BIT(hfdcan->Instance->TEST, FDCAN_TEST_LBCK); 800175e: 687b ldr r3, [r7, #4] 8001760: 681b ldr r3, [r3, #0] 8001762: 691a ldr r2, [r3, #16] 8001764: 687b ldr r3, [r7, #4] 8001766: 681b ldr r3, [r3, #0] 8001768: f042 0210 orr.w r2, r2, #16 800176c: 611a str r2, [r3, #16] if (hfdcan->Init.Mode == FDCAN_MODE_INTERNAL_LOOPBACK) 800176e: 687b ldr r3, [r7, #4] 8001770: 68db ldr r3, [r3, #12] 8001772: 2b03 cmp r3, #3 8001774: d114 bne.n 80017a0 { SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_MON); 8001776: 687b ldr r3, [r7, #4] 8001778: 681b ldr r3, [r3, #0] 800177a: 699a ldr r2, [r3, #24] 800177c: 687b ldr r3, [r7, #4] 800177e: 681b ldr r3, [r3, #0] 8001780: f042 0220 orr.w r2, r2, #32 8001784: 619a str r2, [r3, #24] 8001786: e00b b.n 80017a0 8001788: 08005700 .word 0x08005700 800178c: 4000a000 .word 0x4000a000 } } else { /* Enable bus monitoring mode */ SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_MON); 8001790: 687b ldr r3, [r7, #4] 8001792: 681b ldr r3, [r3, #0] 8001794: 699a ldr r2, [r3, #24] 8001796: 687b ldr r3, [r7, #4] 8001798: 681b ldr r3, [r3, #0] 800179a: f042 0220 orr.w r2, r2, #32 800179e: 619a str r2, [r3, #24] { /* Nothing to do: normal mode */ } /* Set the nominal bit timing register */ hfdcan->Instance->NBTP = ((((uint32_t)hfdcan->Init.NominalSyncJumpWidth - 1U) << FDCAN_NBTP_NSJW_Pos) | \ 80017a0: 687b ldr r3, [r7, #4] 80017a2: 699b ldr r3, [r3, #24] 80017a4: 3b01 subs r3, #1 80017a6: 065a lsls r2, r3, #25 (((uint32_t)hfdcan->Init.NominalTimeSeg1 - 1U) << FDCAN_NBTP_NTSEG1_Pos) | \ 80017a8: 687b ldr r3, [r7, #4] 80017aa: 69db ldr r3, [r3, #28] 80017ac: 3b01 subs r3, #1 80017ae: 021b lsls r3, r3, #8 hfdcan->Instance->NBTP = ((((uint32_t)hfdcan->Init.NominalSyncJumpWidth - 1U) << FDCAN_NBTP_NSJW_Pos) | \ 80017b0: 431a orrs r2, r3 (((uint32_t)hfdcan->Init.NominalTimeSeg2 - 1U) << FDCAN_NBTP_NTSEG2_Pos) | \ 80017b2: 687b ldr r3, [r7, #4] 80017b4: 6a1b ldr r3, [r3, #32] 80017b6: 3b01 subs r3, #1 (((uint32_t)hfdcan->Init.NominalTimeSeg1 - 1U) << FDCAN_NBTP_NTSEG1_Pos) | \ 80017b8: ea42 0103 orr.w r1, r2, r3 (((uint32_t)hfdcan->Init.NominalPrescaler - 1U) << FDCAN_NBTP_NBRP_Pos)); 80017bc: 687b ldr r3, [r7, #4] 80017be: 695b ldr r3, [r3, #20] 80017c0: 3b01 subs r3, #1 80017c2: 041a lsls r2, r3, #16 hfdcan->Instance->NBTP = ((((uint32_t)hfdcan->Init.NominalSyncJumpWidth - 1U) << FDCAN_NBTP_NSJW_Pos) | \ 80017c4: 687b ldr r3, [r7, #4] 80017c6: 681b ldr r3, [r3, #0] (((uint32_t)hfdcan->Init.NominalTimeSeg2 - 1U) << FDCAN_NBTP_NTSEG2_Pos) | \ 80017c8: 430a orrs r2, r1 hfdcan->Instance->NBTP = ((((uint32_t)hfdcan->Init.NominalSyncJumpWidth - 1U) << FDCAN_NBTP_NSJW_Pos) | \ 80017ca: 61da str r2, [r3, #28] /* If FD operation with BRS is selected, set the data bit timing register */ if (hfdcan->Init.FrameFormat == FDCAN_FRAME_FD_BRS) 80017cc: 687b ldr r3, [r7, #4] 80017ce: 689b ldr r3, [r3, #8] 80017d0: f5b3 7f40 cmp.w r3, #768 ; 0x300 80017d4: d115 bne.n 8001802 { hfdcan->Instance->DBTP = ((((uint32_t)hfdcan->Init.DataSyncJumpWidth - 1U) << FDCAN_DBTP_DSJW_Pos) | \ 80017d6: 687b ldr r3, [r7, #4] 80017d8: 6a9b ldr r3, [r3, #40] ; 0x28 80017da: 1e5a subs r2, r3, #1 (((uint32_t)hfdcan->Init.DataTimeSeg1 - 1U) << FDCAN_DBTP_DTSEG1_Pos) | \ 80017dc: 687b ldr r3, [r7, #4] 80017de: 6adb ldr r3, [r3, #44] ; 0x2c 80017e0: 3b01 subs r3, #1 80017e2: 021b lsls r3, r3, #8 hfdcan->Instance->DBTP = ((((uint32_t)hfdcan->Init.DataSyncJumpWidth - 1U) << FDCAN_DBTP_DSJW_Pos) | \ 80017e4: 431a orrs r2, r3 (((uint32_t)hfdcan->Init.DataTimeSeg2 - 1U) << FDCAN_DBTP_DTSEG2_Pos) | \ 80017e6: 687b ldr r3, [r7, #4] 80017e8: 6b1b ldr r3, [r3, #48] ; 0x30 80017ea: 3b01 subs r3, #1 80017ec: 011b lsls r3, r3, #4 (((uint32_t)hfdcan->Init.DataTimeSeg1 - 1U) << FDCAN_DBTP_DTSEG1_Pos) | \ 80017ee: ea42 0103 orr.w r1, r2, r3 (((uint32_t)hfdcan->Init.DataPrescaler - 1U) << FDCAN_DBTP_DBRP_Pos)); 80017f2: 687b ldr r3, [r7, #4] 80017f4: 6a5b ldr r3, [r3, #36] ; 0x24 80017f6: 3b01 subs r3, #1 80017f8: 041a lsls r2, r3, #16 hfdcan->Instance->DBTP = ((((uint32_t)hfdcan->Init.DataSyncJumpWidth - 1U) << FDCAN_DBTP_DSJW_Pos) | \ 80017fa: 687b ldr r3, [r7, #4] 80017fc: 681b ldr r3, [r3, #0] (((uint32_t)hfdcan->Init.DataTimeSeg2 - 1U) << FDCAN_DBTP_DTSEG2_Pos) | \ 80017fe: 430a orrs r2, r1 hfdcan->Instance->DBTP = ((((uint32_t)hfdcan->Init.DataSyncJumpWidth - 1U) << FDCAN_DBTP_DSJW_Pos) | \ 8001800: 60da str r2, [r3, #12] } if (hfdcan->Init.TxFifoQueueElmtsNbr > 0U) 8001802: 687b ldr r3, [r7, #4] 8001804: 6e1b ldr r3, [r3, #96] ; 0x60 8001806: 2b00 cmp r3, #0 8001808: d00a beq.n 8001820 { /* Select between Tx FIFO and Tx Queue operation modes */ SET_BIT(hfdcan->Instance->TXBC, hfdcan->Init.TxFifoQueueMode); 800180a: 687b ldr r3, [r7, #4] 800180c: 681b ldr r3, [r3, #0] 800180e: f8d3 10c0 ldr.w r1, [r3, #192] ; 0xc0 8001812: 687b ldr r3, [r7, #4] 8001814: 6e5a ldr r2, [r3, #100] ; 0x64 8001816: 687b ldr r3, [r7, #4] 8001818: 681b ldr r3, [r3, #0] 800181a: 430a orrs r2, r1 800181c: f8c3 20c0 str.w r2, [r3, #192] ; 0xc0 } /* Configure Tx element size */ if ((hfdcan->Init.TxBuffersNbr + hfdcan->Init.TxFifoQueueElmtsNbr) > 0U) 8001820: 687b ldr r3, [r7, #4] 8001822: 6dda ldr r2, [r3, #92] ; 0x5c 8001824: 687b ldr r3, [r7, #4] 8001826: 6e1b ldr r3, [r3, #96] ; 0x60 8001828: 4413 add r3, r2 800182a: 2b00 cmp r3, #0 800182c: d011 beq.n 8001852 { MODIFY_REG(hfdcan->Instance->TXESC, FDCAN_TXESC_TBDS, CvtEltSize[hfdcan->Init.TxElmtSize]); 800182e: 687b ldr r3, [r7, #4] 8001830: 681b ldr r3, [r3, #0] 8001832: f8d3 30c8 ldr.w r3, [r3, #200] ; 0xc8 8001836: f023 0107 bic.w r1, r3, #7 800183a: 687b ldr r3, [r7, #4] 800183c: 6e9b ldr r3, [r3, #104] ; 0x68 800183e: 009b lsls r3, r3, #2 8001840: 3360 adds r3, #96 ; 0x60 8001842: 443b add r3, r7 8001844: f853 2c54 ldr.w r2, [r3, #-84] 8001848: 687b ldr r3, [r7, #4] 800184a: 681b ldr r3, [r3, #0] 800184c: 430a orrs r2, r1 800184e: f8c3 20c8 str.w r2, [r3, #200] ; 0xc8 } /* Configure Rx FIFO 0 element size */ if (hfdcan->Init.RxFifo0ElmtsNbr > 0U) 8001852: 687b ldr r3, [r7, #4] 8001854: 6c1b ldr r3, [r3, #64] ; 0x40 8001856: 2b00 cmp r3, #0 8001858: d011 beq.n 800187e { MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_F0DS, (CvtEltSize[hfdcan->Init.RxFifo0ElmtSize] << FDCAN_RXESC_F0DS_Pos)); 800185a: 687b ldr r3, [r7, #4] 800185c: 681b ldr r3, [r3, #0] 800185e: f8d3 30bc ldr.w r3, [r3, #188] ; 0xbc 8001862: f023 0107 bic.w r1, r3, #7 8001866: 687b ldr r3, [r7, #4] 8001868: 6c5b ldr r3, [r3, #68] ; 0x44 800186a: 009b lsls r3, r3, #2 800186c: 3360 adds r3, #96 ; 0x60 800186e: 443b add r3, r7 8001870: f853 2c54 ldr.w r2, [r3, #-84] 8001874: 687b ldr r3, [r7, #4] 8001876: 681b ldr r3, [r3, #0] 8001878: 430a orrs r2, r1 800187a: f8c3 20bc str.w r2, [r3, #188] ; 0xbc } /* Configure Rx FIFO 1 element size */ if (hfdcan->Init.RxFifo1ElmtsNbr > 0U) 800187e: 687b ldr r3, [r7, #4] 8001880: 6c9b ldr r3, [r3, #72] ; 0x48 8001882: 2b00 cmp r3, #0 8001884: d012 beq.n 80018ac { MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_F1DS, (CvtEltSize[hfdcan->Init.RxFifo1ElmtSize] << FDCAN_RXESC_F1DS_Pos)); 8001886: 687b ldr r3, [r7, #4] 8001888: 681b ldr r3, [r3, #0] 800188a: f8d3 30bc ldr.w r3, [r3, #188] ; 0xbc 800188e: f023 0170 bic.w r1, r3, #112 ; 0x70 8001892: 687b ldr r3, [r7, #4] 8001894: 6cdb ldr r3, [r3, #76] ; 0x4c 8001896: 009b lsls r3, r3, #2 8001898: 3360 adds r3, #96 ; 0x60 800189a: 443b add r3, r7 800189c: f853 3c54 ldr.w r3, [r3, #-84] 80018a0: 011a lsls r2, r3, #4 80018a2: 687b ldr r3, [r7, #4] 80018a4: 681b ldr r3, [r3, #0] 80018a6: 430a orrs r2, r1 80018a8: f8c3 20bc str.w r2, [r3, #188] ; 0xbc } /* Configure Rx buffer element size */ if (hfdcan->Init.RxBuffersNbr > 0U) 80018ac: 687b ldr r3, [r7, #4] 80018ae: 6d1b ldr r3, [r3, #80] ; 0x50 80018b0: 2b00 cmp r3, #0 80018b2: d012 beq.n 80018da { MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_RBDS, (CvtEltSize[hfdcan->Init.RxBufferSize] << FDCAN_RXESC_RBDS_Pos)); 80018b4: 687b ldr r3, [r7, #4] 80018b6: 681b ldr r3, [r3, #0] 80018b8: f8d3 30bc ldr.w r3, [r3, #188] ; 0xbc 80018bc: f423 61e0 bic.w r1, r3, #1792 ; 0x700 80018c0: 687b ldr r3, [r7, #4] 80018c2: 6d5b ldr r3, [r3, #84] ; 0x54 80018c4: 009b lsls r3, r3, #2 80018c6: 3360 adds r3, #96 ; 0x60 80018c8: 443b add r3, r7 80018ca: f853 3c54 ldr.w r3, [r3, #-84] 80018ce: 021a lsls r2, r3, #8 80018d0: 687b ldr r3, [r7, #4] 80018d2: 681b ldr r3, [r3, #0] 80018d4: 430a orrs r2, r1 80018d6: f8c3 20bc str.w r2, [r3, #188] ; 0xbc } /* By default operation mode is set to Event-driven communication. If Time-triggered communication is needed, user should call the HAL_FDCAN_TT_ConfigOperation function just after the HAL_FDCAN_Init */ if (hfdcan->Instance == FDCAN1) 80018da: 687b ldr r3, [r7, #4] 80018dc: 681b ldr r3, [r3, #0] 80018de: 4a11 ldr r2, [pc, #68] ; (8001924 ) 80018e0: 4293 cmp r3, r2 80018e2: d107 bne.n 80018f4 { CLEAR_BIT(hfdcan->ttcan->TTOCF, FDCAN_TTOCF_OM); 80018e4: 687b ldr r3, [r7, #4] 80018e6: 685b ldr r3, [r3, #4] 80018e8: 689a ldr r2, [r3, #8] 80018ea: 687b ldr r3, [r7, #4] 80018ec: 685b ldr r3, [r3, #4] 80018ee: f022 0203 bic.w r2, r2, #3 80018f2: 609a str r2, [r3, #8] } /* Initialize the Latest Tx FIFO/Queue request buffer index */ hfdcan->LatestTxFifoQRequest = 0U; 80018f4: 687b ldr r3, [r7, #4] 80018f6: 2200 movs r2, #0 80018f8: f8c3 2094 str.w r2, [r3, #148] ; 0x94 /* Initialize the error code */ hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE; 80018fc: 687b ldr r3, [r7, #4] 80018fe: 2200 movs r2, #0 8001900: f8c3 209c str.w r2, [r3, #156] ; 0x9c /* Initialize the FDCAN state */ hfdcan->State = HAL_FDCAN_STATE_READY; 8001904: 687b ldr r3, [r7, #4] 8001906: 2201 movs r2, #1 8001908: f883 2098 strb.w r2, [r3, #152] ; 0x98 /* Calculate each RAM block address */ status = FDCAN_CalcultateRamBlockAddresses(hfdcan); 800190c: 6878 ldr r0, [r7, #4] 800190e: f000 fd83 bl 8002418 8001912: 4603 mov r3, r0 8001914: f887 305b strb.w r3, [r7, #91] ; 0x5b /* Return function status */ return status; 8001918: f897 305b ldrb.w r3, [r7, #91] ; 0x5b } 800191c: 4618 mov r0, r3 800191e: 3760 adds r7, #96 ; 0x60 8001920: 46bd mov sp, r7 8001922: bd80 pop {r7, pc} 8001924: 4000a000 .word 0x4000a000 08001928 : * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains * the configuration information for the specified FDCAN. * @retval HAL status */ HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan) { 8001928: b480 push {r7} 800192a: b083 sub sp, #12 800192c: af00 add r7, sp, #0 800192e: 6078 str r0, [r7, #4] if (hfdcan->State == HAL_FDCAN_STATE_READY) 8001930: 687b ldr r3, [r7, #4] 8001932: f893 3098 ldrb.w r3, [r3, #152] ; 0x98 8001936: b2db uxtb r3, r3 8001938: 2b01 cmp r3, #1 800193a: d111 bne.n 8001960 { /* Change FDCAN peripheral state */ hfdcan->State = HAL_FDCAN_STATE_BUSY; 800193c: 687b ldr r3, [r7, #4] 800193e: 2202 movs r2, #2 8001940: f883 2098 strb.w r2, [r3, #152] ; 0x98 /* Request leave initialisation */ CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT); 8001944: 687b ldr r3, [r7, #4] 8001946: 681b ldr r3, [r3, #0] 8001948: 699a ldr r2, [r3, #24] 800194a: 687b ldr r3, [r7, #4] 800194c: 681b ldr r3, [r3, #0] 800194e: f022 0201 bic.w r2, r2, #1 8001952: 619a str r2, [r3, #24] /* Reset the FDCAN ErrorCode */ hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE; 8001954: 687b ldr r3, [r7, #4] 8001956: 2200 movs r2, #0 8001958: f8c3 209c str.w r2, [r3, #156] ; 0x9c /* Return function status */ return HAL_OK; 800195c: 2300 movs r3, #0 800195e: e008 b.n 8001972 } else { /* Update error code */ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; 8001960: 687b ldr r3, [r7, #4] 8001962: f8d3 309c ldr.w r3, [r3, #156] ; 0x9c 8001966: f043 0204 orr.w r2, r3, #4 800196a: 687b ldr r3, [r7, #4] 800196c: f8c3 209c str.w r2, [r3, #156] ; 0x9c return HAL_ERROR; 8001970: 2301 movs r3, #1 } } 8001972: 4618 mov r0, r3 8001974: 370c adds r7, #12 8001976: 46bd mov sp, r7 8001978: f85d 7b04 ldr.w r7, [sp], #4 800197c: 4770 bx lr 0800197e : * @param pTxHeader pointer to a FDCAN_TxHeaderTypeDef structure. * @param pTxData pointer to a buffer containing the payload of the Tx frame. * @retval HAL status */ HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData) { 800197e: b580 push {r7, lr} 8001980: b086 sub sp, #24 8001982: af00 add r7, sp, #0 8001984: 60f8 str r0, [r7, #12] 8001986: 60b9 str r1, [r7, #8] 8001988: 607a str r2, [r7, #4] assert_param(IS_FDCAN_BRS(pTxHeader->BitRateSwitch)); assert_param(IS_FDCAN_FDF(pTxHeader->FDFormat)); assert_param(IS_FDCAN_EFC(pTxHeader->TxEventFifoControl)); assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->MessageMarker, 0xFFU)); if (hfdcan->State == HAL_FDCAN_STATE_BUSY) 800198a: 68fb ldr r3, [r7, #12] 800198c: f893 3098 ldrb.w r3, [r3, #152] ; 0x98 8001990: b2db uxtb r3, r3 8001992: 2b02 cmp r3, #2 8001994: d141 bne.n 8001a1a { /* Check that the Tx FIFO/Queue has an allocated area into the RAM */ if ((hfdcan->Instance->TXBC & FDCAN_TXBC_TFQS) == 0U) 8001996: 68fb ldr r3, [r7, #12] 8001998: 681b ldr r3, [r3, #0] 800199a: f8d3 30c0 ldr.w r3, [r3, #192] ; 0xc0 800199e: f003 537c and.w r3, r3, #1056964608 ; 0x3f000000 80019a2: 2b00 cmp r3, #0 80019a4: d109 bne.n 80019ba { /* Update error code */ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM; 80019a6: 68fb ldr r3, [r7, #12] 80019a8: f8d3 309c ldr.w r3, [r3, #156] ; 0x9c 80019ac: f043 0220 orr.w r2, r3, #32 80019b0: 68fb ldr r3, [r7, #12] 80019b2: f8c3 209c str.w r2, [r3, #156] ; 0x9c return HAL_ERROR; 80019b6: 2301 movs r3, #1 80019b8: e038 b.n 8001a2c } /* Check that the Tx FIFO/Queue is not full */ if ((hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFQF) != 0U) 80019ba: 68fb ldr r3, [r7, #12] 80019bc: 681b ldr r3, [r3, #0] 80019be: f8d3 30c4 ldr.w r3, [r3, #196] ; 0xc4 80019c2: f403 1300 and.w r3, r3, #2097152 ; 0x200000 80019c6: 2b00 cmp r3, #0 80019c8: d009 beq.n 80019de { /* Update error code */ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_FULL; 80019ca: 68fb ldr r3, [r7, #12] 80019cc: f8d3 309c ldr.w r3, [r3, #156] ; 0x9c 80019d0: f443 7200 orr.w r2, r3, #512 ; 0x200 80019d4: 68fb ldr r3, [r7, #12] 80019d6: f8c3 209c str.w r2, [r3, #156] ; 0x9c return HAL_ERROR; 80019da: 2301 movs r3, #1 80019dc: e026 b.n 8001a2c } else { /* Retrieve the Tx FIFO PutIndex */ PutIndex = ((hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFQPI) >> FDCAN_TXFQS_TFQPI_Pos); 80019de: 68fb ldr r3, [r7, #12] 80019e0: 681b ldr r3, [r3, #0] 80019e2: f8d3 30c4 ldr.w r3, [r3, #196] ; 0xc4 80019e6: 0c1b lsrs r3, r3, #16 80019e8: f003 031f and.w r3, r3, #31 80019ec: 617b str r3, [r7, #20] /* Add the message to the Tx FIFO/Queue */ FDCAN_CopyMessageToRAM(hfdcan, pTxHeader, pTxData, PutIndex); 80019ee: 697b ldr r3, [r7, #20] 80019f0: 687a ldr r2, [r7, #4] 80019f2: 68b9 ldr r1, [r7, #8] 80019f4: 68f8 ldr r0, [r7, #12] 80019f6: f000 fe95 bl 8002724 /* Activate the corresponding transmission request */ hfdcan->Instance->TXBAR = ((uint32_t)1 << PutIndex); 80019fa: 68fb ldr r3, [r7, #12] 80019fc: 681b ldr r3, [r3, #0] 80019fe: 2101 movs r1, #1 8001a00: 697a ldr r2, [r7, #20] 8001a02: fa01 f202 lsl.w r2, r1, r2 8001a06: f8c3 20d0 str.w r2, [r3, #208] ; 0xd0 /* Store the Latest Tx FIFO/Queue Request Buffer Index */ hfdcan->LatestTxFifoQRequest = ((uint32_t)1 << PutIndex); 8001a0a: 2201 movs r2, #1 8001a0c: 697b ldr r3, [r7, #20] 8001a0e: 409a lsls r2, r3 8001a10: 68fb ldr r3, [r7, #12] 8001a12: f8c3 2094 str.w r2, [r3, #148] ; 0x94 } /* Return function status */ return HAL_OK; 8001a16: 2300 movs r3, #0 8001a18: e008 b.n 8001a2c } else { /* Update error code */ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED; 8001a1a: 68fb ldr r3, [r7, #12] 8001a1c: f8d3 309c ldr.w r3, [r3, #156] ; 0x9c 8001a20: f043 0208 orr.w r2, r3, #8 8001a24: 68fb ldr r3, [r7, #12] 8001a26: f8c3 209c str.w r2, [r3, #156] ; 0x9c return HAL_ERROR; 8001a2a: 2301 movs r3, #1 } } 8001a2c: 4618 mov r0, r3 8001a2e: 3718 adds r7, #24 8001a30: 46bd mov sp, r7 8001a32: bd80 pop {r7, pc} 08001a34 : * @param pRxHeader pointer to a FDCAN_RxHeaderTypeDef structure. * @param pRxData pointer to a buffer where the payload of the Rx frame will be stored. * @retval HAL status */ HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData) { 8001a34: b480 push {r7} 8001a36: b08b sub sp, #44 ; 0x2c 8001a38: af00 add r7, sp, #0 8001a3a: 60f8 str r0, [r7, #12] 8001a3c: 60b9 str r1, [r7, #8] 8001a3e: 607a str r2, [r7, #4] 8001a40: 603b str r3, [r7, #0] uint32_t *RxAddress; uint8_t *pData; uint32_t ByteCounter; uint32_t GetIndex = 0; 8001a42: 2300 movs r3, #0 8001a44: 61fb str r3, [r7, #28] HAL_FDCAN_StateTypeDef state = hfdcan->State; 8001a46: 68fb ldr r3, [r7, #12] 8001a48: f893 3098 ldrb.w r3, [r3, #152] ; 0x98 8001a4c: 76fb strb r3, [r7, #27] if (state == HAL_FDCAN_STATE_BUSY) 8001a4e: 7efb ldrb r3, [r7, #27] 8001a50: 2b02 cmp r3, #2 8001a52: f040 814b bne.w 8001cec { if (RxLocation == FDCAN_RX_FIFO0) /* Rx element is assigned to the Rx FIFO 0 */ 8001a56: 68bb ldr r3, [r7, #8] 8001a58: 2b40 cmp r3, #64 ; 0x40 8001a5a: d14d bne.n 8001af8 { /* Check that the Rx FIFO 0 has an allocated area into the RAM */ if ((hfdcan->Instance->RXF0C & FDCAN_RXF0C_F0S) == 0U) 8001a5c: 68fb ldr r3, [r7, #12] 8001a5e: 681b ldr r3, [r3, #0] 8001a60: f8d3 30a0 ldr.w r3, [r3, #160] ; 0xa0 8001a64: f403 03fe and.w r3, r3, #8323072 ; 0x7f0000 8001a68: 2b00 cmp r3, #0 8001a6a: d109 bne.n 8001a80 { /* Update error code */ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM; 8001a6c: 68fb ldr r3, [r7, #12] 8001a6e: f8d3 309c ldr.w r3, [r3, #156] ; 0x9c 8001a72: f043 0220 orr.w r2, r3, #32 8001a76: 68fb ldr r3, [r7, #12] 8001a78: f8c3 209c str.w r2, [r3, #156] ; 0x9c return HAL_ERROR; 8001a7c: 2301 movs r3, #1 8001a7e: e13e b.n 8001cfe } /* Check that the Rx FIFO 0 is not empty */ if ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0FL) == 0U) 8001a80: 68fb ldr r3, [r7, #12] 8001a82: 681b ldr r3, [r3, #0] 8001a84: f8d3 30a4 ldr.w r3, [r3, #164] ; 0xa4 8001a88: f003 037f and.w r3, r3, #127 ; 0x7f 8001a8c: 2b00 cmp r3, #0 8001a8e: d109 bne.n 8001aa4 { /* Update error code */ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY; 8001a90: 68fb ldr r3, [r7, #12] 8001a92: f8d3 309c ldr.w r3, [r3, #156] ; 0x9c 8001a96: f443 7280 orr.w r2, r3, #256 ; 0x100 8001a9a: 68fb ldr r3, [r7, #12] 8001a9c: f8c3 209c str.w r2, [r3, #156] ; 0x9c return HAL_ERROR; 8001aa0: 2301 movs r3, #1 8001aa2: e12c b.n 8001cfe } else { /* Check that the Rx FIFO 0 is full & overwrite mode is on*/ if(((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0F) >> FDCAN_RXF0S_F0F_Pos) == 1U) 8001aa4: 68fb ldr r3, [r7, #12] 8001aa6: 681b ldr r3, [r3, #0] 8001aa8: f8d3 30a4 ldr.w r3, [r3, #164] ; 0xa4 8001aac: 0e1b lsrs r3, r3, #24 8001aae: f003 0301 and.w r3, r3, #1 8001ab2: 2b01 cmp r3, #1 8001ab4: d10b bne.n 8001ace { if(((hfdcan->Instance->RXF0C & FDCAN_RXF0C_F0OM) >> FDCAN_RXF0C_F0OM_Pos) == FDCAN_RX_FIFO_OVERWRITE) 8001ab6: 68fb ldr r3, [r7, #12] 8001ab8: 681b ldr r3, [r3, #0] 8001aba: f8d3 30a0 ldr.w r3, [r3, #160] ; 0xa0 8001abe: 0fdb lsrs r3, r3, #31 8001ac0: f003 0301 and.w r3, r3, #1 8001ac4: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000 8001ac8: d101 bne.n 8001ace { /* When overwrite status is on discard first message in FIFO */ GetIndex = 1U; 8001aca: 2301 movs r3, #1 8001acc: 61fb str r3, [r7, #28] } } /* Calculate Rx FIFO 0 element index*/ GetIndex += ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0GI) >> FDCAN_RXF0S_F0GI_Pos); 8001ace: 68fb ldr r3, [r7, #12] 8001ad0: 681b ldr r3, [r3, #0] 8001ad2: f8d3 30a4 ldr.w r3, [r3, #164] ; 0xa4 8001ad6: 0a1b lsrs r3, r3, #8 8001ad8: f003 033f and.w r3, r3, #63 ; 0x3f 8001adc: 69fa ldr r2, [r7, #28] 8001ade: 4413 add r3, r2 8001ae0: 61fb str r3, [r7, #28] /* Calculate Rx FIFO 0 element address */ RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO0SA + (GetIndex * hfdcan->Init.RxFifo0ElmtSize * 4U)); 8001ae2: 68fb ldr r3, [r7, #12] 8001ae4: 6f5a ldr r2, [r3, #116] ; 0x74 8001ae6: 68fb ldr r3, [r7, #12] 8001ae8: 6c5b ldr r3, [r3, #68] ; 0x44 8001aea: 69f9 ldr r1, [r7, #28] 8001aec: fb01 f303 mul.w r3, r1, r3 8001af0: 009b lsls r3, r3, #2 8001af2: 4413 add r3, r2 8001af4: 627b str r3, [r7, #36] ; 0x24 8001af6: e069 b.n 8001bcc } } else if (RxLocation == FDCAN_RX_FIFO1) /* Rx element is assigned to the Rx FIFO 1 */ 8001af8: 68bb ldr r3, [r7, #8] 8001afa: 2b41 cmp r3, #65 ; 0x41 8001afc: d14d bne.n 8001b9a { /* Check that the Rx FIFO 1 has an allocated area into the RAM */ if ((hfdcan->Instance->RXF1C & FDCAN_RXF1C_F1S) == 0U) 8001afe: 68fb ldr r3, [r7, #12] 8001b00: 681b ldr r3, [r3, #0] 8001b02: f8d3 30b0 ldr.w r3, [r3, #176] ; 0xb0 8001b06: f403 03fe and.w r3, r3, #8323072 ; 0x7f0000 8001b0a: 2b00 cmp r3, #0 8001b0c: d109 bne.n 8001b22 { /* Update error code */ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM; 8001b0e: 68fb ldr r3, [r7, #12] 8001b10: f8d3 309c ldr.w r3, [r3, #156] ; 0x9c 8001b14: f043 0220 orr.w r2, r3, #32 8001b18: 68fb ldr r3, [r7, #12] 8001b1a: f8c3 209c str.w r2, [r3, #156] ; 0x9c return HAL_ERROR; 8001b1e: 2301 movs r3, #1 8001b20: e0ed b.n 8001cfe } /* Check that the Rx FIFO 0 is not empty */ if ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1FL) == 0U) 8001b22: 68fb ldr r3, [r7, #12] 8001b24: 681b ldr r3, [r3, #0] 8001b26: f8d3 30b4 ldr.w r3, [r3, #180] ; 0xb4 8001b2a: f003 037f and.w r3, r3, #127 ; 0x7f 8001b2e: 2b00 cmp r3, #0 8001b30: d109 bne.n 8001b46 { /* Update error code */ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY; 8001b32: 68fb ldr r3, [r7, #12] 8001b34: f8d3 309c ldr.w r3, [r3, #156] ; 0x9c 8001b38: f443 7280 orr.w r2, r3, #256 ; 0x100 8001b3c: 68fb ldr r3, [r7, #12] 8001b3e: f8c3 209c str.w r2, [r3, #156] ; 0x9c return HAL_ERROR; 8001b42: 2301 movs r3, #1 8001b44: e0db b.n 8001cfe } else { /* Check that the Rx FIFO 1 is full & overwrite mode is on*/ if(((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1F) >> FDCAN_RXF1S_F1F_Pos) == 1U) 8001b46: 68fb ldr r3, [r7, #12] 8001b48: 681b ldr r3, [r3, #0] 8001b4a: f8d3 30b4 ldr.w r3, [r3, #180] ; 0xb4 8001b4e: 0e1b lsrs r3, r3, #24 8001b50: f003 0301 and.w r3, r3, #1 8001b54: 2b01 cmp r3, #1 8001b56: d10b bne.n 8001b70 { if(((hfdcan->Instance->RXF1C & FDCAN_RXF1C_F1OM) >> FDCAN_RXF1C_F1OM_Pos) == FDCAN_RX_FIFO_OVERWRITE) 8001b58: 68fb ldr r3, [r7, #12] 8001b5a: 681b ldr r3, [r3, #0] 8001b5c: f8d3 30b0 ldr.w r3, [r3, #176] ; 0xb0 8001b60: 0fdb lsrs r3, r3, #31 8001b62: f003 0301 and.w r3, r3, #1 8001b66: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000 8001b6a: d101 bne.n 8001b70 { /* When overwrite status is on discard first message in FIFO */ GetIndex = 1U; 8001b6c: 2301 movs r3, #1 8001b6e: 61fb str r3, [r7, #28] } } /* Calculate Rx FIFO 1 element index*/ GetIndex += ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1GI) >> FDCAN_RXF1S_F1GI_Pos); 8001b70: 68fb ldr r3, [r7, #12] 8001b72: 681b ldr r3, [r3, #0] 8001b74: f8d3 30b4 ldr.w r3, [r3, #180] ; 0xb4 8001b78: 0a1b lsrs r3, r3, #8 8001b7a: f003 033f and.w r3, r3, #63 ; 0x3f 8001b7e: 69fa ldr r2, [r7, #28] 8001b80: 4413 add r3, r2 8001b82: 61fb str r3, [r7, #28] /* Calculate Rx FIFO 1 element address */ RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO1SA + (GetIndex * hfdcan->Init.RxFifo1ElmtSize * 4U)); 8001b84: 68fb ldr r3, [r7, #12] 8001b86: 6f9a ldr r2, [r3, #120] ; 0x78 8001b88: 68fb ldr r3, [r7, #12] 8001b8a: 6cdb ldr r3, [r3, #76] ; 0x4c 8001b8c: 69f9 ldr r1, [r7, #28] 8001b8e: fb01 f303 mul.w r3, r1, r3 8001b92: 009b lsls r3, r3, #2 8001b94: 4413 add r3, r2 8001b96: 627b str r3, [r7, #36] ; 0x24 8001b98: e018 b.n 8001bcc } } else /* Rx element is assigned to a dedicated Rx buffer */ { /* Check that the selected buffer has an allocated area into the RAM */ if (RxLocation >= hfdcan->Init.RxBuffersNbr) 8001b9a: 68fb ldr r3, [r7, #12] 8001b9c: 6d1b ldr r3, [r3, #80] ; 0x50 8001b9e: 68ba ldr r2, [r7, #8] 8001ba0: 429a cmp r2, r3 8001ba2: d309 bcc.n 8001bb8 { /* Update error code */ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM; 8001ba4: 68fb ldr r3, [r7, #12] 8001ba6: f8d3 309c ldr.w r3, [r3, #156] ; 0x9c 8001baa: f043 0220 orr.w r2, r3, #32 8001bae: 68fb ldr r3, [r7, #12] 8001bb0: f8c3 209c str.w r2, [r3, #156] ; 0x9c return HAL_ERROR; 8001bb4: 2301 movs r3, #1 8001bb6: e0a2 b.n 8001cfe } else { /* Calculate Rx buffer address */ RxAddress = (uint32_t *)(hfdcan->msgRam.RxBufferSA + (RxLocation * hfdcan->Init.RxBufferSize * 4U)); 8001bb8: 68fb ldr r3, [r7, #12] 8001bba: 6fda ldr r2, [r3, #124] ; 0x7c 8001bbc: 68fb ldr r3, [r7, #12] 8001bbe: 6d5b ldr r3, [r3, #84] ; 0x54 8001bc0: 68b9 ldr r1, [r7, #8] 8001bc2: fb01 f303 mul.w r3, r1, r3 8001bc6: 009b lsls r3, r3, #2 8001bc8: 4413 add r3, r2 8001bca: 627b str r3, [r7, #36] ; 0x24 } } /* Retrieve IdType */ pRxHeader->IdType = *RxAddress & FDCAN_ELEMENT_MASK_XTD; 8001bcc: 6a7b ldr r3, [r7, #36] ; 0x24 8001bce: 681b ldr r3, [r3, #0] 8001bd0: f003 4280 and.w r2, r3, #1073741824 ; 0x40000000 8001bd4: 687b ldr r3, [r7, #4] 8001bd6: 605a str r2, [r3, #4] /* Retrieve Identifier */ if (pRxHeader->IdType == FDCAN_STANDARD_ID) /* Standard ID element */ 8001bd8: 687b ldr r3, [r7, #4] 8001bda: 685b ldr r3, [r3, #4] 8001bdc: 2b00 cmp r3, #0 8001bde: d107 bne.n 8001bf0 { pRxHeader->Identifier = ((*RxAddress & FDCAN_ELEMENT_MASK_STDID) >> 18); 8001be0: 6a7b ldr r3, [r7, #36] ; 0x24 8001be2: 681b ldr r3, [r3, #0] 8001be4: 0c9b lsrs r3, r3, #18 8001be6: f3c3 020a ubfx r2, r3, #0, #11 8001bea: 687b ldr r3, [r7, #4] 8001bec: 601a str r2, [r3, #0] 8001bee: e005 b.n 8001bfc } else /* Extended ID element */ { pRxHeader->Identifier = (*RxAddress & FDCAN_ELEMENT_MASK_EXTID); 8001bf0: 6a7b ldr r3, [r7, #36] ; 0x24 8001bf2: 681b ldr r3, [r3, #0] 8001bf4: f023 4260 bic.w r2, r3, #3758096384 ; 0xe0000000 8001bf8: 687b ldr r3, [r7, #4] 8001bfa: 601a str r2, [r3, #0] } /* Retrieve RxFrameType */ pRxHeader->RxFrameType = (*RxAddress & FDCAN_ELEMENT_MASK_RTR); 8001bfc: 6a7b ldr r3, [r7, #36] ; 0x24 8001bfe: 681b ldr r3, [r3, #0] 8001c00: f003 5200 and.w r2, r3, #536870912 ; 0x20000000 8001c04: 687b ldr r3, [r7, #4] 8001c06: 609a str r2, [r3, #8] /* Retrieve ErrorStateIndicator */ pRxHeader->ErrorStateIndicator = (*RxAddress & FDCAN_ELEMENT_MASK_ESI); 8001c08: 6a7b ldr r3, [r7, #36] ; 0x24 8001c0a: 681b ldr r3, [r3, #0] 8001c0c: f003 4200 and.w r2, r3, #2147483648 ; 0x80000000 8001c10: 687b ldr r3, [r7, #4] 8001c12: 611a str r2, [r3, #16] /* Increment RxAddress pointer to second word of Rx FIFO element */ RxAddress++; 8001c14: 6a7b ldr r3, [r7, #36] ; 0x24 8001c16: 3304 adds r3, #4 8001c18: 627b str r3, [r7, #36] ; 0x24 /* Retrieve RxTimestamp */ pRxHeader->RxTimestamp = (*RxAddress & FDCAN_ELEMENT_MASK_TS); 8001c1a: 6a7b ldr r3, [r7, #36] ; 0x24 8001c1c: 681b ldr r3, [r3, #0] 8001c1e: b29a uxth r2, r3 8001c20: 687b ldr r3, [r7, #4] 8001c22: 61da str r2, [r3, #28] /* Retrieve DataLength */ pRxHeader->DataLength = (*RxAddress & FDCAN_ELEMENT_MASK_DLC); 8001c24: 6a7b ldr r3, [r7, #36] ; 0x24 8001c26: 681b ldr r3, [r3, #0] 8001c28: f403 2270 and.w r2, r3, #983040 ; 0xf0000 8001c2c: 687b ldr r3, [r7, #4] 8001c2e: 60da str r2, [r3, #12] /* Retrieve BitRateSwitch */ pRxHeader->BitRateSwitch = (*RxAddress & FDCAN_ELEMENT_MASK_BRS); 8001c30: 6a7b ldr r3, [r7, #36] ; 0x24 8001c32: 681b ldr r3, [r3, #0] 8001c34: f403 1280 and.w r2, r3, #1048576 ; 0x100000 8001c38: 687b ldr r3, [r7, #4] 8001c3a: 615a str r2, [r3, #20] /* Retrieve FDFormat */ pRxHeader->FDFormat = (*RxAddress & FDCAN_ELEMENT_MASK_FDF); 8001c3c: 6a7b ldr r3, [r7, #36] ; 0x24 8001c3e: 681b ldr r3, [r3, #0] 8001c40: f403 1200 and.w r2, r3, #2097152 ; 0x200000 8001c44: 687b ldr r3, [r7, #4] 8001c46: 619a str r2, [r3, #24] /* Retrieve FilterIndex */ pRxHeader->FilterIndex = ((*RxAddress & FDCAN_ELEMENT_MASK_FIDX) >> 24); 8001c48: 6a7b ldr r3, [r7, #36] ; 0x24 8001c4a: 681b ldr r3, [r3, #0] 8001c4c: 0e1b lsrs r3, r3, #24 8001c4e: f003 027f and.w r2, r3, #127 ; 0x7f 8001c52: 687b ldr r3, [r7, #4] 8001c54: 621a str r2, [r3, #32] /* Retrieve NonMatchingFrame */ pRxHeader->IsFilterMatchingFrame = ((*RxAddress & FDCAN_ELEMENT_MASK_ANMF) >> 31); 8001c56: 6a7b ldr r3, [r7, #36] ; 0x24 8001c58: 681b ldr r3, [r3, #0] 8001c5a: 0fda lsrs r2, r3, #31 8001c5c: 687b ldr r3, [r7, #4] 8001c5e: 625a str r2, [r3, #36] ; 0x24 /* Increment RxAddress pointer to payload of Rx FIFO element */ RxAddress++; 8001c60: 6a7b ldr r3, [r7, #36] ; 0x24 8001c62: 3304 adds r3, #4 8001c64: 627b str r3, [r7, #36] ; 0x24 /* Retrieve Rx payload */ pData = (uint8_t *)RxAddress; 8001c66: 6a7b ldr r3, [r7, #36] ; 0x24 8001c68: 617b str r3, [r7, #20] for (ByteCounter = 0; ByteCounter < DLCtoBytes[pRxHeader->DataLength >> 16]; ByteCounter++) 8001c6a: 2300 movs r3, #0 8001c6c: 623b str r3, [r7, #32] 8001c6e: e00a b.n 8001c86 { pRxData[ByteCounter] = pData[ByteCounter]; 8001c70: 697a ldr r2, [r7, #20] 8001c72: 6a3b ldr r3, [r7, #32] 8001c74: 441a add r2, r3 8001c76: 6839 ldr r1, [r7, #0] 8001c78: 6a3b ldr r3, [r7, #32] 8001c7a: 440b add r3, r1 8001c7c: 7812 ldrb r2, [r2, #0] 8001c7e: 701a strb r2, [r3, #0] for (ByteCounter = 0; ByteCounter < DLCtoBytes[pRxHeader->DataLength >> 16]; ByteCounter++) 8001c80: 6a3b ldr r3, [r7, #32] 8001c82: 3301 adds r3, #1 8001c84: 623b str r3, [r7, #32] 8001c86: 687b ldr r3, [r7, #4] 8001c88: 68db ldr r3, [r3, #12] 8001c8a: 0c1b lsrs r3, r3, #16 8001c8c: 4a1f ldr r2, [pc, #124] ; (8001d0c ) 8001c8e: 5cd3 ldrb r3, [r2, r3] 8001c90: 461a mov r2, r3 8001c92: 6a3b ldr r3, [r7, #32] 8001c94: 4293 cmp r3, r2 8001c96: d3eb bcc.n 8001c70 } if (RxLocation == FDCAN_RX_FIFO0) /* Rx element is assigned to the Rx FIFO 0 */ 8001c98: 68bb ldr r3, [r7, #8] 8001c9a: 2b40 cmp r3, #64 ; 0x40 8001c9c: d105 bne.n 8001caa { /* Acknowledge the Rx FIFO 0 that the oldest element is read so that it increments the GetIndex */ hfdcan->Instance->RXF0A = GetIndex; 8001c9e: 68fb ldr r3, [r7, #12] 8001ca0: 681b ldr r3, [r3, #0] 8001ca2: 69fa ldr r2, [r7, #28] 8001ca4: f8c3 20a8 str.w r2, [r3, #168] ; 0xa8 8001ca8: e01e b.n 8001ce8 } else if (RxLocation == FDCAN_RX_FIFO1) /* Rx element is assigned to the Rx FIFO 1 */ 8001caa: 68bb ldr r3, [r7, #8] 8001cac: 2b41 cmp r3, #65 ; 0x41 8001cae: d105 bne.n 8001cbc { /* Acknowledge the Rx FIFO 1 that the oldest element is read so that it increments the GetIndex */ hfdcan->Instance->RXF1A = GetIndex; 8001cb0: 68fb ldr r3, [r7, #12] 8001cb2: 681b ldr r3, [r3, #0] 8001cb4: 69fa ldr r2, [r7, #28] 8001cb6: f8c3 20b8 str.w r2, [r3, #184] ; 0xb8 8001cba: e015 b.n 8001ce8 } else /* Rx element is assigned to a dedicated Rx buffer */ { /* Clear the New Data flag of the current Rx buffer */ if (RxLocation < FDCAN_RX_BUFFER32) 8001cbc: 68bb ldr r3, [r7, #8] 8001cbe: 2b1f cmp r3, #31 8001cc0: d808 bhi.n 8001cd4 { hfdcan->Instance->NDAT1 = ((uint32_t)1 << RxLocation); 8001cc2: 68fb ldr r3, [r7, #12] 8001cc4: 681b ldr r3, [r3, #0] 8001cc6: 2101 movs r1, #1 8001cc8: 68ba ldr r2, [r7, #8] 8001cca: fa01 f202 lsl.w r2, r1, r2 8001cce: f8c3 2098 str.w r2, [r3, #152] ; 0x98 8001cd2: e009 b.n 8001ce8 } else /* FDCAN_RX_BUFFER32 <= RxLocation <= FDCAN_RX_BUFFER63 */ { hfdcan->Instance->NDAT2 = ((uint32_t)1 << (RxLocation & 0x1FU)); 8001cd4: 68bb ldr r3, [r7, #8] 8001cd6: f003 021f and.w r2, r3, #31 8001cda: 68fb ldr r3, [r7, #12] 8001cdc: 681b ldr r3, [r3, #0] 8001cde: 2101 movs r1, #1 8001ce0: fa01 f202 lsl.w r2, r1, r2 8001ce4: f8c3 209c str.w r2, [r3, #156] ; 0x9c } } /* Return function status */ return HAL_OK; 8001ce8: 2300 movs r3, #0 8001cea: e008 b.n 8001cfe } else { /* Update error code */ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED; 8001cec: 68fb ldr r3, [r7, #12] 8001cee: f8d3 309c ldr.w r3, [r3, #156] ; 0x9c 8001cf2: f043 0208 orr.w r2, r3, #8 8001cf6: 68fb ldr r3, [r7, #12] 8001cf8: f8c3 209c str.w r2, [r3, #156] ; 0x9c return HAL_ERROR; 8001cfc: 2301 movs r3, #1 } } 8001cfe: 4618 mov r0, r3 8001d00: 372c adds r7, #44 ; 0x2c 8001d02: 46bd mov sp, r7 8001d04: f85d 7b04 ldr.w r7, [sp], #4 8001d08: 4770 bx lr 8001d0a: bf00 nop 8001d0c: 0800575c .word 0x0800575c 08001d10 : * - FDCAN_IT_TX_COMPLETE * - FDCAN_IT_TX_ABORT_COMPLETE * @retval HAL status */ HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs, uint32_t BufferIndexes) { 8001d10: b480 push {r7} 8001d12: b087 sub sp, #28 8001d14: af00 add r7, sp, #0 8001d16: 60f8 str r0, [r7, #12] 8001d18: 60b9 str r1, [r7, #8] 8001d1a: 607a str r2, [r7, #4] HAL_FDCAN_StateTypeDef state = hfdcan->State; 8001d1c: 68fb ldr r3, [r7, #12] 8001d1e: f893 3098 ldrb.w r3, [r3, #152] ; 0x98 8001d22: 75fb strb r3, [r7, #23] /* Check function parameters */ assert_param(IS_FDCAN_IT(ActiveITs)); if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) 8001d24: 7dfb ldrb r3, [r7, #23] 8001d26: 2b01 cmp r3, #1 8001d28: d002 beq.n 8001d30 8001d2a: 7dfb ldrb r3, [r7, #23] 8001d2c: 2b02 cmp r3, #2 8001d2e: d155 bne.n 8001ddc { /* Enable Interrupt lines */ if ((ActiveITs & hfdcan->Instance->ILS) == 0U) 8001d30: 68fb ldr r3, [r7, #12] 8001d32: 681b ldr r3, [r3, #0] 8001d34: 6d9a ldr r2, [r3, #88] ; 0x58 8001d36: 68bb ldr r3, [r7, #8] 8001d38: 4013 ands r3, r2 8001d3a: 2b00 cmp r3, #0 8001d3c: d108 bne.n 8001d50 { /* Enable Interrupt line 0 */ SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0); 8001d3e: 68fb ldr r3, [r7, #12] 8001d40: 681b ldr r3, [r3, #0] 8001d42: 6dda ldr r2, [r3, #92] ; 0x5c 8001d44: 68fb ldr r3, [r7, #12] 8001d46: 681b ldr r3, [r3, #0] 8001d48: f042 0201 orr.w r2, r2, #1 8001d4c: 65da str r2, [r3, #92] ; 0x5c 8001d4e: e014 b.n 8001d7a } else if ((ActiveITs & hfdcan->Instance->ILS) == ActiveITs) 8001d50: 68fb ldr r3, [r7, #12] 8001d52: 681b ldr r3, [r3, #0] 8001d54: 6d9a ldr r2, [r3, #88] ; 0x58 8001d56: 68bb ldr r3, [r7, #8] 8001d58: 4013 ands r3, r2 8001d5a: 68ba ldr r2, [r7, #8] 8001d5c: 429a cmp r2, r3 8001d5e: d108 bne.n 8001d72 { /* Enable Interrupt line 1 */ SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1); 8001d60: 68fb ldr r3, [r7, #12] 8001d62: 681b ldr r3, [r3, #0] 8001d64: 6dda ldr r2, [r3, #92] ; 0x5c 8001d66: 68fb ldr r3, [r7, #12] 8001d68: 681b ldr r3, [r3, #0] 8001d6a: f042 0202 orr.w r2, r2, #2 8001d6e: 65da str r2, [r3, #92] ; 0x5c 8001d70: e003 b.n 8001d7a } else { /* Enable Interrupt lines 0 and 1 */ hfdcan->Instance->ILE = (FDCAN_INTERRUPT_LINE0 | FDCAN_INTERRUPT_LINE1); 8001d72: 68fb ldr r3, [r7, #12] 8001d74: 681b ldr r3, [r3, #0] 8001d76: 2203 movs r2, #3 8001d78: 65da str r2, [r3, #92] ; 0x5c } if ((ActiveITs & FDCAN_IT_TX_COMPLETE) != 0U) 8001d7a: 68bb ldr r3, [r7, #8] 8001d7c: f403 7300 and.w r3, r3, #512 ; 0x200 8001d80: 2b00 cmp r3, #0 8001d82: d009 beq.n 8001d98 { /* Enable Tx Buffer Transmission Interrupt to set TC flag in IR register, but interrupt will only occur if TC is enabled in IE register */ SET_BIT(hfdcan->Instance->TXBTIE, BufferIndexes); 8001d84: 68fb ldr r3, [r7, #12] 8001d86: 681b ldr r3, [r3, #0] 8001d88: f8d3 10e0 ldr.w r1, [r3, #224] ; 0xe0 8001d8c: 68fb ldr r3, [r7, #12] 8001d8e: 681b ldr r3, [r3, #0] 8001d90: 687a ldr r2, [r7, #4] 8001d92: 430a orrs r2, r1 8001d94: f8c3 20e0 str.w r2, [r3, #224] ; 0xe0 } if ((ActiveITs & FDCAN_IT_TX_ABORT_COMPLETE) != 0U) 8001d98: 68bb ldr r3, [r7, #8] 8001d9a: f403 6380 and.w r3, r3, #1024 ; 0x400 8001d9e: 2b00 cmp r3, #0 8001da0: d009 beq.n 8001db6 { /* Enable Tx Buffer Cancellation Finished Interrupt to set TCF flag in IR register, but interrupt will only occur if TCF is enabled in IE register */ SET_BIT(hfdcan->Instance->TXBCIE, BufferIndexes); 8001da2: 68fb ldr r3, [r7, #12] 8001da4: 681b ldr r3, [r3, #0] 8001da6: f8d3 10e4 ldr.w r1, [r3, #228] ; 0xe4 8001daa: 68fb ldr r3, [r7, #12] 8001dac: 681b ldr r3, [r3, #0] 8001dae: 687a ldr r2, [r7, #4] 8001db0: 430a orrs r2, r1 8001db2: f8c3 20e4 str.w r2, [r3, #228] ; 0xe4 } /* Enable the selected interrupts */ __HAL_FDCAN_ENABLE_IT(hfdcan, ActiveITs); 8001db6: 68fb ldr r3, [r7, #12] 8001db8: 681b ldr r3, [r3, #0] 8001dba: 6d59 ldr r1, [r3, #84] ; 0x54 8001dbc: 68ba ldr r2, [r7, #8] 8001dbe: 4b0f ldr r3, [pc, #60] ; (8001dfc ) 8001dc0: 4013 ands r3, r2 8001dc2: 68fa ldr r2, [r7, #12] 8001dc4: 6812 ldr r2, [r2, #0] 8001dc6: 430b orrs r3, r1 8001dc8: 6553 str r3, [r2, #84] ; 0x54 8001dca: 4b0d ldr r3, [pc, #52] ; (8001e00 ) 8001dcc: 695a ldr r2, [r3, #20] 8001dce: 68bb ldr r3, [r7, #8] 8001dd0: 0f9b lsrs r3, r3, #30 8001dd2: 490b ldr r1, [pc, #44] ; (8001e00 ) 8001dd4: 4313 orrs r3, r2 8001dd6: 614b str r3, [r1, #20] /* Return function status */ return HAL_OK; 8001dd8: 2300 movs r3, #0 8001dda: e008 b.n 8001dee } else { /* Update error code */ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; 8001ddc: 68fb ldr r3, [r7, #12] 8001dde: f8d3 309c ldr.w r3, [r3, #156] ; 0x9c 8001de2: f043 0202 orr.w r2, r3, #2 8001de6: 68fb ldr r3, [r7, #12] 8001de8: f8c3 209c str.w r2, [r3, #156] ; 0x9c return HAL_ERROR; 8001dec: 2301 movs r3, #1 } } 8001dee: 4618 mov r0, r3 8001df0: 371c adds r7, #28 8001df2: 46bd mov sp, r7 8001df4: f85d 7b04 ldr.w r7, [sp], #4 8001df8: 4770 bx lr 8001dfa: bf00 nop 8001dfc: 3fcfffff .word 0x3fcfffff 8001e00: 4000a800 .word 0x4000a800 08001e04 : * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains * the configuration information for the specified FDCAN. * @retval HAL status */ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan) { 8001e04: b580 push {r7, lr} 8001e06: b096 sub sp, #88 ; 0x58 8001e08: af00 add r7, sp, #0 8001e0a: 6078 str r0, [r7, #4] uint32_t itsourceIE; uint32_t itsourceTTIE; uint32_t itflagIR; uint32_t itflagTTIR; ClkCalibrationITs = (FDCAN_CCU->IR << 30); 8001e0c: 4b9a ldr r3, [pc, #616] ; (8002078 ) 8001e0e: 691b ldr r3, [r3, #16] 8001e10: 079b lsls r3, r3, #30 8001e12: 657b str r3, [r7, #84] ; 0x54 ClkCalibrationITs &= (FDCAN_CCU->IE << 30); 8001e14: 4b98 ldr r3, [pc, #608] ; (8002078 ) 8001e16: 695b ldr r3, [r3, #20] 8001e18: 079b lsls r3, r3, #30 8001e1a: 6d7a ldr r2, [r7, #84] ; 0x54 8001e1c: 4013 ands r3, r2 8001e1e: 657b str r3, [r7, #84] ; 0x54 TxEventFifoITs = hfdcan->Instance->IR & FDCAN_TX_EVENT_FIFO_MASK; 8001e20: 687b ldr r3, [r7, #4] 8001e22: 681b ldr r3, [r3, #0] 8001e24: 6d1b ldr r3, [r3, #80] ; 0x50 8001e26: f403 4370 and.w r3, r3, #61440 ; 0xf000 8001e2a: 653b str r3, [r7, #80] ; 0x50 TxEventFifoITs &= hfdcan->Instance->IE; 8001e2c: 687b ldr r3, [r7, #4] 8001e2e: 681b ldr r3, [r3, #0] 8001e30: 6d5b ldr r3, [r3, #84] ; 0x54 8001e32: 6d3a ldr r2, [r7, #80] ; 0x50 8001e34: 4013 ands r3, r2 8001e36: 653b str r3, [r7, #80] ; 0x50 RxFifo0ITs = hfdcan->Instance->IR & FDCAN_RX_FIFO0_MASK; 8001e38: 687b ldr r3, [r7, #4] 8001e3a: 681b ldr r3, [r3, #0] 8001e3c: 6d1b ldr r3, [r3, #80] ; 0x50 8001e3e: f003 030f and.w r3, r3, #15 8001e42: 64fb str r3, [r7, #76] ; 0x4c RxFifo0ITs &= hfdcan->Instance->IE; 8001e44: 687b ldr r3, [r7, #4] 8001e46: 681b ldr r3, [r3, #0] 8001e48: 6d5b ldr r3, [r3, #84] ; 0x54 8001e4a: 6cfa ldr r2, [r7, #76] ; 0x4c 8001e4c: 4013 ands r3, r2 8001e4e: 64fb str r3, [r7, #76] ; 0x4c RxFifo1ITs = hfdcan->Instance->IR & FDCAN_RX_FIFO1_MASK; 8001e50: 687b ldr r3, [r7, #4] 8001e52: 681b ldr r3, [r3, #0] 8001e54: 6d1b ldr r3, [r3, #80] ; 0x50 8001e56: f003 03f0 and.w r3, r3, #240 ; 0xf0 8001e5a: 64bb str r3, [r7, #72] ; 0x48 RxFifo1ITs &= hfdcan->Instance->IE; 8001e5c: 687b ldr r3, [r7, #4] 8001e5e: 681b ldr r3, [r3, #0] 8001e60: 6d5b ldr r3, [r3, #84] ; 0x54 8001e62: 6cba ldr r2, [r7, #72] ; 0x48 8001e64: 4013 ands r3, r2 8001e66: 64bb str r3, [r7, #72] ; 0x48 Errors = hfdcan->Instance->IR & FDCAN_ERROR_MASK; 8001e68: 687b ldr r3, [r7, #4] 8001e6a: 681b ldr r3, [r3, #0] 8001e6c: 6d1b ldr r3, [r3, #80] ; 0x50 8001e6e: f003 5371 and.w r3, r3, #1010827264 ; 0x3c400000 8001e72: 647b str r3, [r7, #68] ; 0x44 Errors &= hfdcan->Instance->IE; 8001e74: 687b ldr r3, [r7, #4] 8001e76: 681b ldr r3, [r3, #0] 8001e78: 6d5b ldr r3, [r3, #84] ; 0x54 8001e7a: 6c7a ldr r2, [r7, #68] ; 0x44 8001e7c: 4013 ands r3, r2 8001e7e: 647b str r3, [r7, #68] ; 0x44 ErrorStatusITs = hfdcan->Instance->IR & FDCAN_ERROR_STATUS_MASK; 8001e80: 687b ldr r3, [r7, #4] 8001e82: 681b ldr r3, [r3, #0] 8001e84: 6d1b ldr r3, [r3, #80] ; 0x50 8001e86: f003 7360 and.w r3, r3, #58720256 ; 0x3800000 8001e8a: 643b str r3, [r7, #64] ; 0x40 ErrorStatusITs &= hfdcan->Instance->IE; 8001e8c: 687b ldr r3, [r7, #4] 8001e8e: 681b ldr r3, [r3, #0] 8001e90: 6d5b ldr r3, [r3, #84] ; 0x54 8001e92: 6c3a ldr r2, [r7, #64] ; 0x40 8001e94: 4013 ands r3, r2 8001e96: 643b str r3, [r7, #64] ; 0x40 itsourceIE = hfdcan->Instance->IE; 8001e98: 687b ldr r3, [r7, #4] 8001e9a: 681b ldr r3, [r3, #0] 8001e9c: 6d5b ldr r3, [r3, #84] ; 0x54 8001e9e: 63fb str r3, [r7, #60] ; 0x3c itflagIR = hfdcan->Instance->IR; 8001ea0: 687b ldr r3, [r7, #4] 8001ea2: 681b ldr r3, [r3, #0] 8001ea4: 6d1b ldr r3, [r3, #80] ; 0x50 8001ea6: 63bb str r3, [r7, #56] ; 0x38 /* High Priority Message interrupt management *******************************/ if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_RX_HIGH_PRIORITY_MSG) != RESET) 8001ea8: 6bfb ldr r3, [r7, #60] ; 0x3c 8001eaa: 0a1b lsrs r3, r3, #8 8001eac: f003 0301 and.w r3, r3, #1 8001eb0: 2b00 cmp r3, #0 8001eb2: d010 beq.n 8001ed6 { if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG) != RESET) 8001eb4: 6bbb ldr r3, [r7, #56] ; 0x38 8001eb6: 0a1b lsrs r3, r3, #8 8001eb8: f003 0301 and.w r3, r3, #1 8001ebc: 2b00 cmp r3, #0 8001ebe: d00a beq.n 8001ed6 { /* Clear the High Priority Message flag */ __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG); 8001ec0: 687b ldr r3, [r7, #4] 8001ec2: 681b ldr r3, [r3, #0] 8001ec4: f44f 7280 mov.w r2, #256 ; 0x100 8001ec8: 651a str r2, [r3, #80] ; 0x50 8001eca: 4b6b ldr r3, [pc, #428] ; (8002078 ) 8001ecc: 2200 movs r2, #0 8001ece: 611a str r2, [r3, #16] #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hfdcan->HighPriorityMessageCallback(hfdcan); #else /* High Priority Message Callback */ HAL_FDCAN_HighPriorityMessageCallback(hfdcan); 8001ed0: 6878 ldr r0, [r7, #4] 8001ed2: f000 fa54 bl 800237e #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ } } /* Transmission Abort interrupt management **********************************/ if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_TX_ABORT_COMPLETE) != RESET) 8001ed6: 6bfb ldr r3, [r7, #60] ; 0x3c 8001ed8: 0a9b lsrs r3, r3, #10 8001eda: f003 0301 and.w r3, r3, #1 8001ede: 2b00 cmp r3, #0 8001ee0: d01d beq.n 8001f1e { if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_TX_ABORT_COMPLETE) != RESET) 8001ee2: 6bbb ldr r3, [r7, #56] ; 0x38 8001ee4: 0a9b lsrs r3, r3, #10 8001ee6: f003 0301 and.w r3, r3, #1 8001eea: 2b00 cmp r3, #0 8001eec: d017 beq.n 8001f1e { /* List of aborted monitored buffers */ AbortedBuffers = hfdcan->Instance->TXBCF; 8001eee: 687b ldr r3, [r7, #4] 8001ef0: 681b ldr r3, [r3, #0] 8001ef2: f8d3 30dc ldr.w r3, [r3, #220] ; 0xdc 8001ef6: 637b str r3, [r7, #52] ; 0x34 AbortedBuffers &= hfdcan->Instance->TXBCIE; 8001ef8: 687b ldr r3, [r7, #4] 8001efa: 681b ldr r3, [r3, #0] 8001efc: f8d3 30e4 ldr.w r3, [r3, #228] ; 0xe4 8001f00: 6b7a ldr r2, [r7, #52] ; 0x34 8001f02: 4013 ands r3, r2 8001f04: 637b str r3, [r7, #52] ; 0x34 /* Clear the Transmission Cancellation flag */ __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_ABORT_COMPLETE); 8001f06: 687b ldr r3, [r7, #4] 8001f08: 681b ldr r3, [r3, #0] 8001f0a: f44f 6280 mov.w r2, #1024 ; 0x400 8001f0e: 651a str r2, [r3, #80] ; 0x50 8001f10: 4b59 ldr r3, [pc, #356] ; (8002078 ) 8001f12: 2200 movs r2, #0 8001f14: 611a str r2, [r3, #16] #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hfdcan->TxBufferAbortCallback(hfdcan, AbortedBuffers); #else /* Transmission Cancellation Callback */ HAL_FDCAN_TxBufferAbortCallback(hfdcan, AbortedBuffers); 8001f16: 6b79 ldr r1, [r7, #52] ; 0x34 8001f18: 6878 ldr r0, [r7, #4] 8001f1a: f000 fa07 bl 800232c #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ } } /* Clock calibration unit interrupts management *****************************/ if (ClkCalibrationITs != 0U) 8001f1e: 6d7b ldr r3, [r7, #84] ; 0x54 8001f20: 2b00 cmp r3, #0 8001f22: d00d beq.n 8001f40 { /* Clear the Clock Calibration flags */ __HAL_FDCAN_CLEAR_FLAG(hfdcan, ClkCalibrationITs); 8001f24: 687b ldr r3, [r7, #4] 8001f26: 681a ldr r2, [r3, #0] 8001f28: 6d79 ldr r1, [r7, #84] ; 0x54 8001f2a: 4b54 ldr r3, [pc, #336] ; (800207c ) 8001f2c: 400b ands r3, r1 8001f2e: 6513 str r3, [r2, #80] ; 0x50 8001f30: 4a51 ldr r2, [pc, #324] ; (8002078 ) 8001f32: 6d7b ldr r3, [r7, #84] ; 0x54 8001f34: 0f9b lsrs r3, r3, #30 8001f36: 6113 str r3, [r2, #16] #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hfdcan->ClockCalibrationCallback(hfdcan, ClkCalibrationITs); #else /* Clock Calibration Callback */ HAL_FDCAN_ClockCalibrationCallback(hfdcan, ClkCalibrationITs); 8001f38: 6d79 ldr r1, [r7, #84] ; 0x54 8001f3a: 6878 ldr r0, [r7, #4] 8001f3c: f000 f9c0 bl 80022c0 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ } /* Tx event FIFO interrupts management **************************************/ if (TxEventFifoITs != 0U) 8001f40: 6d3b ldr r3, [r7, #80] ; 0x50 8001f42: 2b00 cmp r3, #0 8001f44: d00d beq.n 8001f62 { /* Clear the Tx Event FIFO flags */ __HAL_FDCAN_CLEAR_FLAG(hfdcan, TxEventFifoITs); 8001f46: 687b ldr r3, [r7, #4] 8001f48: 681a ldr r2, [r3, #0] 8001f4a: 6d39 ldr r1, [r7, #80] ; 0x50 8001f4c: 4b4b ldr r3, [pc, #300] ; (800207c ) 8001f4e: 400b ands r3, r1 8001f50: 6513 str r3, [r2, #80] ; 0x50 8001f52: 4a49 ldr r2, [pc, #292] ; (8002078 ) 8001f54: 6d3b ldr r3, [r7, #80] ; 0x50 8001f56: 0f9b lsrs r3, r3, #30 8001f58: 6113 str r3, [r2, #16] #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hfdcan->TxEventFifoCallback(hfdcan, TxEventFifoITs); #else /* Tx Event FIFO Callback */ HAL_FDCAN_TxEventFifoCallback(hfdcan, TxEventFifoITs); 8001f5a: 6d39 ldr r1, [r7, #80] ; 0x50 8001f5c: 6878 ldr r0, [r7, #4] 8001f5e: f000 f9ba bl 80022d6 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ } /* Rx FIFO 0 interrupts management ******************************************/ if (RxFifo0ITs != 0U) 8001f62: 6cfb ldr r3, [r7, #76] ; 0x4c 8001f64: 2b00 cmp r3, #0 8001f66: d00d beq.n 8001f84 { /* Clear the Rx FIFO 0 flags */ __HAL_FDCAN_CLEAR_FLAG(hfdcan, RxFifo0ITs); 8001f68: 687b ldr r3, [r7, #4] 8001f6a: 681a ldr r2, [r3, #0] 8001f6c: 6cf9 ldr r1, [r7, #76] ; 0x4c 8001f6e: 4b43 ldr r3, [pc, #268] ; (800207c ) 8001f70: 400b ands r3, r1 8001f72: 6513 str r3, [r2, #80] ; 0x50 8001f74: 4a40 ldr r2, [pc, #256] ; (8002078 ) 8001f76: 6cfb ldr r3, [r7, #76] ; 0x4c 8001f78: 0f9b lsrs r3, r3, #30 8001f7a: 6113 str r3, [r2, #16] #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hfdcan->RxFifo0Callback(hfdcan, RxFifo0ITs); #else /* Rx FIFO 0 Callback */ HAL_FDCAN_RxFifo0Callback(hfdcan, RxFifo0ITs); 8001f7c: 6cf9 ldr r1, [r7, #76] ; 0x4c 8001f7e: 6878 ldr r0, [r7, #4] 8001f80: f7fe f9ba bl 80002f8 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ } /* Rx FIFO 1 interrupts management ******************************************/ if (RxFifo1ITs != 0U) 8001f84: 6cbb ldr r3, [r7, #72] ; 0x48 8001f86: 2b00 cmp r3, #0 8001f88: d00d beq.n 8001fa6 { /* Clear the Rx FIFO 1 flags */ __HAL_FDCAN_CLEAR_FLAG(hfdcan, RxFifo1ITs); 8001f8a: 687b ldr r3, [r7, #4] 8001f8c: 681a ldr r2, [r3, #0] 8001f8e: 6cb9 ldr r1, [r7, #72] ; 0x48 8001f90: 4b3a ldr r3, [pc, #232] ; (800207c ) 8001f92: 400b ands r3, r1 8001f94: 6513 str r3, [r2, #80] ; 0x50 8001f96: 4a38 ldr r2, [pc, #224] ; (8002078 ) 8001f98: 6cbb ldr r3, [r7, #72] ; 0x48 8001f9a: 0f9b lsrs r3, r3, #30 8001f9c: 6113 str r3, [r2, #16] #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hfdcan->RxFifo1Callback(hfdcan, RxFifo1ITs); #else /* Rx FIFO 1 Callback */ HAL_FDCAN_RxFifo1Callback(hfdcan, RxFifo1ITs); 8001f9e: 6cb9 ldr r1, [r7, #72] ; 0x48 8001fa0: 6878 ldr r0, [r7, #4] 8001fa2: f000 f9a3 bl 80022ec #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ } /* Tx FIFO empty interrupt management ***************************************/ if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_TX_FIFO_EMPTY) != RESET) 8001fa6: 6bfb ldr r3, [r7, #60] ; 0x3c 8001fa8: 0adb lsrs r3, r3, #11 8001faa: f003 0301 and.w r3, r3, #1 8001fae: 2b00 cmp r3, #0 8001fb0: d010 beq.n 8001fd4 { if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_TX_FIFO_EMPTY) != RESET) 8001fb2: 6bbb ldr r3, [r7, #56] ; 0x38 8001fb4: 0adb lsrs r3, r3, #11 8001fb6: f003 0301 and.w r3, r3, #1 8001fba: 2b00 cmp r3, #0 8001fbc: d00a beq.n 8001fd4 { /* Clear the Tx FIFO empty flag */ __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_FIFO_EMPTY); 8001fbe: 687b ldr r3, [r7, #4] 8001fc0: 681b ldr r3, [r3, #0] 8001fc2: f44f 6200 mov.w r2, #2048 ; 0x800 8001fc6: 651a str r2, [r3, #80] ; 0x50 8001fc8: 4b2b ldr r3, [pc, #172] ; (8002078 ) 8001fca: 2200 movs r2, #0 8001fcc: 611a str r2, [r3, #16] #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hfdcan->TxFifoEmptyCallback(hfdcan); #else /* Tx FIFO empty Callback */ HAL_FDCAN_TxFifoEmptyCallback(hfdcan); 8001fce: 6878 ldr r0, [r7, #4] 8001fd0: f000 f997 bl 8002302 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ } } /* Transmission Complete interrupt management *******************************/ if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_TX_COMPLETE) != RESET) 8001fd4: 6bfb ldr r3, [r7, #60] ; 0x3c 8001fd6: 0a5b lsrs r3, r3, #9 8001fd8: f003 0301 and.w r3, r3, #1 8001fdc: 2b00 cmp r3, #0 8001fde: d01d beq.n 800201c { if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_TX_COMPLETE) != RESET) 8001fe0: 6bbb ldr r3, [r7, #56] ; 0x38 8001fe2: 0a5b lsrs r3, r3, #9 8001fe4: f003 0301 and.w r3, r3, #1 8001fe8: 2b00 cmp r3, #0 8001fea: d017 beq.n 800201c { /* List of transmitted monitored buffers */ TransmittedBuffers = hfdcan->Instance->TXBTO; 8001fec: 687b ldr r3, [r7, #4] 8001fee: 681b ldr r3, [r3, #0] 8001ff0: f8d3 30d8 ldr.w r3, [r3, #216] ; 0xd8 8001ff4: 633b str r3, [r7, #48] ; 0x30 TransmittedBuffers &= hfdcan->Instance->TXBTIE; 8001ff6: 687b ldr r3, [r7, #4] 8001ff8: 681b ldr r3, [r3, #0] 8001ffa: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 8001ffe: 6b3a ldr r2, [r7, #48] ; 0x30 8002000: 4013 ands r3, r2 8002002: 633b str r3, [r7, #48] ; 0x30 /* Clear the Transmission Complete flag */ __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_COMPLETE); 8002004: 687b ldr r3, [r7, #4] 8002006: 681b ldr r3, [r3, #0] 8002008: f44f 7200 mov.w r2, #512 ; 0x200 800200c: 651a str r2, [r3, #80] ; 0x50 800200e: 4b1a ldr r3, [pc, #104] ; (8002078 ) 8002010: 2200 movs r2, #0 8002012: 611a str r2, [r3, #16] #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hfdcan->TxBufferCompleteCallback(hfdcan, TransmittedBuffers); #else /* Transmission Complete Callback */ HAL_FDCAN_TxBufferCompleteCallback(hfdcan, TransmittedBuffers); 8002014: 6b39 ldr r1, [r7, #48] ; 0x30 8002016: 6878 ldr r0, [r7, #4] 8002018: f000 f97d bl 8002316 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ } } /* Rx Buffer New Message interrupt management *******************************/ if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_RX_BUFFER_NEW_MESSAGE) != RESET) 800201c: 6bfb ldr r3, [r7, #60] ; 0x3c 800201e: 0cdb lsrs r3, r3, #19 8002020: f003 0301 and.w r3, r3, #1 8002024: 2b00 cmp r3, #0 8002026: d010 beq.n 800204a { if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE) != RESET) 8002028: 6bbb ldr r3, [r7, #56] ; 0x38 800202a: 0cdb lsrs r3, r3, #19 800202c: f003 0301 and.w r3, r3, #1 8002030: 2b00 cmp r3, #0 8002032: d00a beq.n 800204a { /* Clear the Rx Buffer New Message flag */ __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE); 8002034: 687b ldr r3, [r7, #4] 8002036: 681b ldr r3, [r3, #0] 8002038: f44f 2200 mov.w r2, #524288 ; 0x80000 800203c: 651a str r2, [r3, #80] ; 0x50 800203e: 4b0e ldr r3, [pc, #56] ; (8002078 ) 8002040: 2200 movs r2, #0 8002042: 611a str r2, [r3, #16] #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hfdcan->RxBufferNewMessageCallback(hfdcan); #else /* Rx Buffer New Message Callback */ HAL_FDCAN_RxBufferNewMessageCallback(hfdcan); 8002044: 6878 ldr r0, [r7, #4] 8002046: f000 f97c bl 8002342 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ } } /* Timestamp Wraparound interrupt management ********************************/ if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_TIMESTAMP_WRAPAROUND) != RESET) 800204a: 6bfb ldr r3, [r7, #60] ; 0x3c 800204c: 0c1b lsrs r3, r3, #16 800204e: f003 0301 and.w r3, r3, #1 8002052: 2b00 cmp r3, #0 8002054: d016 beq.n 8002084 { if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_TIMESTAMP_WRAPAROUND) != RESET) 8002056: 6bbb ldr r3, [r7, #56] ; 0x38 8002058: 0c1b lsrs r3, r3, #16 800205a: f003 0301 and.w r3, r3, #1 800205e: 2b00 cmp r3, #0 8002060: d010 beq.n 8002084 { /* Clear the Timestamp Wraparound flag */ __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMESTAMP_WRAPAROUND); 8002062: 687b ldr r3, [r7, #4] 8002064: 681b ldr r3, [r3, #0] 8002066: f44f 3280 mov.w r2, #65536 ; 0x10000 800206a: 651a str r2, [r3, #80] ; 0x50 800206c: 4b02 ldr r3, [pc, #8] ; (8002078 ) 800206e: 2200 movs r2, #0 8002070: 611a str r2, [r3, #16] #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hfdcan->TimestampWraparoundCallback(hfdcan); #else /* Timestamp Wraparound Callback */ HAL_FDCAN_TimestampWraparoundCallback(hfdcan); 8002072: 6878 ldr r0, [r7, #4] 8002074: e004 b.n 8002080 8002076: bf00 nop 8002078: 4000a800 .word 0x4000a800 800207c: 3fcfffff .word 0x3fcfffff 8002080: f000 f969 bl 8002356 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ } } /* Timeout Occurred interrupt management ************************************/ if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_TIMEOUT_OCCURRED) != RESET) 8002084: 6bfb ldr r3, [r7, #60] ; 0x3c 8002086: 0c9b lsrs r3, r3, #18 8002088: f003 0301 and.w r3, r3, #1 800208c: 2b00 cmp r3, #0 800208e: d010 beq.n 80020b2 { if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_TIMEOUT_OCCURRED) != RESET) 8002090: 6bbb ldr r3, [r7, #56] ; 0x38 8002092: 0c9b lsrs r3, r3, #18 8002094: f003 0301 and.w r3, r3, #1 8002098: 2b00 cmp r3, #0 800209a: d00a beq.n 80020b2 { /* Clear the Timeout Occurred flag */ __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMEOUT_OCCURRED); 800209c: 687b ldr r3, [r7, #4] 800209e: 681b ldr r3, [r3, #0] 80020a0: f44f 2280 mov.w r2, #262144 ; 0x40000 80020a4: 651a str r2, [r3, #80] ; 0x50 80020a6: 4b83 ldr r3, [pc, #524] ; (80022b4 ) 80020a8: 2200 movs r2, #0 80020aa: 611a str r2, [r3, #16] #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hfdcan->TimeoutOccurredCallback(hfdcan); #else /* Timeout Occurred Callback */ HAL_FDCAN_TimeoutOccurredCallback(hfdcan); 80020ac: 6878 ldr r0, [r7, #4] 80020ae: f000 f95c bl 800236a #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ } } /* Message RAM access failure interrupt management **************************/ if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_RAM_ACCESS_FAILURE) != RESET) 80020b2: 6bfb ldr r3, [r7, #60] ; 0x3c 80020b4: 0c5b lsrs r3, r3, #17 80020b6: f003 0301 and.w r3, r3, #1 80020ba: 2b00 cmp r3, #0 80020bc: d015 beq.n 80020ea { if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_RAM_ACCESS_FAILURE) != RESET) 80020be: 6bbb ldr r3, [r7, #56] ; 0x38 80020c0: 0c5b lsrs r3, r3, #17 80020c2: f003 0301 and.w r3, r3, #1 80020c6: 2b00 cmp r3, #0 80020c8: d00f beq.n 80020ea { /* Clear the Message RAM access failure flag */ __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RAM_ACCESS_FAILURE); 80020ca: 687b ldr r3, [r7, #4] 80020cc: 681b ldr r3, [r3, #0] 80020ce: f44f 3200 mov.w r2, #131072 ; 0x20000 80020d2: 651a str r2, [r3, #80] ; 0x50 80020d4: 4b77 ldr r3, [pc, #476] ; (80022b4 ) 80020d6: 2200 movs r2, #0 80020d8: 611a str r2, [r3, #16] /* Update error code */ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_RAM_ACCESS; 80020da: 687b ldr r3, [r7, #4] 80020dc: f8d3 309c ldr.w r3, [r3, #156] ; 0x9c 80020e0: f043 0280 orr.w r2, r3, #128 ; 0x80 80020e4: 687b ldr r3, [r7, #4] 80020e6: f8c3 209c str.w r2, [r3, #156] ; 0x9c } } /* Error Status interrupts management ***************************************/ if (ErrorStatusITs != 0U) 80020ea: 6c3b ldr r3, [r7, #64] ; 0x40 80020ec: 2b00 cmp r3, #0 80020ee: d00d beq.n 800210c { /* Clear the Error flags */ __HAL_FDCAN_CLEAR_FLAG(hfdcan, ErrorStatusITs); 80020f0: 687b ldr r3, [r7, #4] 80020f2: 681a ldr r2, [r3, #0] 80020f4: 6c39 ldr r1, [r7, #64] ; 0x40 80020f6: 4b70 ldr r3, [pc, #448] ; (80022b8 ) 80020f8: 400b ands r3, r1 80020fa: 6513 str r3, [r2, #80] ; 0x50 80020fc: 4a6d ldr r2, [pc, #436] ; (80022b4 ) 80020fe: 6c3b ldr r3, [r7, #64] ; 0x40 8002100: 0f9b lsrs r3, r3, #30 8002102: 6113 str r3, [r2, #16] #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hfdcan->ErrorStatusCallback(hfdcan, ErrorStatusITs); #else /* Error Status Callback */ HAL_FDCAN_ErrorStatusCallback(hfdcan, ErrorStatusITs); 8002104: 6c39 ldr r1, [r7, #64] ; 0x40 8002106: 6878 ldr r0, [r7, #4] 8002108: f000 f94d bl 80023a6 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ } /* Error interrupts management **********************************************/ if (Errors != 0U) 800210c: 6c7b ldr r3, [r7, #68] ; 0x44 800210e: 2b00 cmp r3, #0 8002110: d011 beq.n 8002136 { /* Clear the Error flags */ __HAL_FDCAN_CLEAR_FLAG(hfdcan, Errors); 8002112: 687b ldr r3, [r7, #4] 8002114: 681a ldr r2, [r3, #0] 8002116: 6c79 ldr r1, [r7, #68] ; 0x44 8002118: 4b67 ldr r3, [pc, #412] ; (80022b8 ) 800211a: 400b ands r3, r1 800211c: 6513 str r3, [r2, #80] ; 0x50 800211e: 4a65 ldr r2, [pc, #404] ; (80022b4 ) 8002120: 6c7b ldr r3, [r7, #68] ; 0x44 8002122: 0f9b lsrs r3, r3, #30 8002124: 6113 str r3, [r2, #16] /* Update error code */ hfdcan->ErrorCode |= Errors; 8002126: 687b ldr r3, [r7, #4] 8002128: f8d3 209c ldr.w r2, [r3, #156] ; 0x9c 800212c: 6c7b ldr r3, [r7, #68] ; 0x44 800212e: 431a orrs r2, r3 8002130: 687b ldr r3, [r7, #4] 8002132: f8c3 209c str.w r2, [r3, #156] ; 0x9c } if (hfdcan->Instance == FDCAN1) 8002136: 687b ldr r3, [r7, #4] 8002138: 681b ldr r3, [r3, #0] 800213a: 4a60 ldr r2, [pc, #384] ; (80022bc ) 800213c: 4293 cmp r3, r2 800213e: f040 80ac bne.w 800229a { if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != 0U) 8002142: 687b ldr r3, [r7, #4] 8002144: 685b ldr r3, [r3, #4] 8002146: 689b ldr r3, [r3, #8] 8002148: f003 0303 and.w r3, r3, #3 800214c: 2b00 cmp r3, #0 800214e: f000 80a4 beq.w 800229a { TTSchedSyncITs = hfdcan->ttcan->TTIR & FDCAN_TT_SCHEDULE_SYNC_MASK; 8002152: 687b ldr r3, [r7, #4] 8002154: 685b ldr r3, [r3, #4] 8002156: 6a1b ldr r3, [r3, #32] 8002158: f003 030f and.w r3, r3, #15 800215c: 62fb str r3, [r7, #44] ; 0x2c TTSchedSyncITs &= hfdcan->ttcan->TTIE; 800215e: 687b ldr r3, [r7, #4] 8002160: 685b ldr r3, [r3, #4] 8002162: 6a5b ldr r3, [r3, #36] ; 0x24 8002164: 6afa ldr r2, [r7, #44] ; 0x2c 8002166: 4013 ands r3, r2 8002168: 62fb str r3, [r7, #44] ; 0x2c TTTimeMarkITs = hfdcan->ttcan->TTIR & FDCAN_TT_TIME_MARK_MASK; 800216a: 687b ldr r3, [r7, #4] 800216c: 685b ldr r3, [r3, #4] 800216e: 6a1b ldr r3, [r3, #32] 8002170: f003 0330 and.w r3, r3, #48 ; 0x30 8002174: 62bb str r3, [r7, #40] ; 0x28 TTTimeMarkITs &= hfdcan->ttcan->TTIE; 8002176: 687b ldr r3, [r7, #4] 8002178: 685b ldr r3, [r3, #4] 800217a: 6a5b ldr r3, [r3, #36] ; 0x24 800217c: 6aba ldr r2, [r7, #40] ; 0x28 800217e: 4013 ands r3, r2 8002180: 62bb str r3, [r7, #40] ; 0x28 TTGlobTimeITs = hfdcan->ttcan->TTIR & FDCAN_TT_GLOBAL_TIME_MASK; 8002182: 687b ldr r3, [r7, #4] 8002184: 685b ldr r3, [r3, #4] 8002186: 6a1b ldr r3, [r3, #32] 8002188: f403 73c0 and.w r3, r3, #384 ; 0x180 800218c: 627b str r3, [r7, #36] ; 0x24 TTGlobTimeITs &= hfdcan->ttcan->TTIE; 800218e: 687b ldr r3, [r7, #4] 8002190: 685b ldr r3, [r3, #4] 8002192: 6a5b ldr r3, [r3, #36] ; 0x24 8002194: 6a7a ldr r2, [r7, #36] ; 0x24 8002196: 4013 ands r3, r2 8002198: 627b str r3, [r7, #36] ; 0x24 TTDistErrors = hfdcan->ttcan->TTIR & FDCAN_TT_DISTURBING_ERROR_MASK; 800219a: 687b ldr r3, [r7, #4] 800219c: 685b ldr r3, [r3, #4] 800219e: 6a1b ldr r3, [r3, #32] 80021a0: f403 43fc and.w r3, r3, #32256 ; 0x7e00 80021a4: 623b str r3, [r7, #32] TTDistErrors &= hfdcan->ttcan->TTIE; 80021a6: 687b ldr r3, [r7, #4] 80021a8: 685b ldr r3, [r3, #4] 80021aa: 6a5b ldr r3, [r3, #36] ; 0x24 80021ac: 6a3a ldr r2, [r7, #32] 80021ae: 4013 ands r3, r2 80021b0: 623b str r3, [r7, #32] TTFatalErrors = hfdcan->ttcan->TTIR & FDCAN_TT_FATAL_ERROR_MASK; 80021b2: 687b ldr r3, [r7, #4] 80021b4: 685b ldr r3, [r3, #4] 80021b6: 6a1b ldr r3, [r3, #32] 80021b8: f403 23f0 and.w r3, r3, #491520 ; 0x78000 80021bc: 61fb str r3, [r7, #28] TTFatalErrors &= hfdcan->ttcan->TTIE; 80021be: 687b ldr r3, [r7, #4] 80021c0: 685b ldr r3, [r3, #4] 80021c2: 6a5b ldr r3, [r3, #36] ; 0x24 80021c4: 69fa ldr r2, [r7, #28] 80021c6: 4013 ands r3, r2 80021c8: 61fb str r3, [r7, #28] itsourceTTIE = hfdcan->ttcan->TTIE; 80021ca: 687b ldr r3, [r7, #4] 80021cc: 685b ldr r3, [r3, #4] 80021ce: 6a5b ldr r3, [r3, #36] ; 0x24 80021d0: 61bb str r3, [r7, #24] itflagTTIR = hfdcan->ttcan->TTIR; 80021d2: 687b ldr r3, [r7, #4] 80021d4: 685b ldr r3, [r3, #4] 80021d6: 6a1b ldr r3, [r3, #32] 80021d8: 617b str r3, [r7, #20] /* TT Schedule Synchronization interrupts management **********************/ if (TTSchedSyncITs != 0U) 80021da: 6afb ldr r3, [r7, #44] ; 0x2c 80021dc: 2b00 cmp r3, #0 80021de: d007 beq.n 80021f0 { /* Clear the TT Schedule Synchronization flags */ __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTSchedSyncITs); 80021e0: 687b ldr r3, [r7, #4] 80021e2: 685b ldr r3, [r3, #4] 80021e4: 6afa ldr r2, [r7, #44] ; 0x2c 80021e6: 621a str r2, [r3, #32] #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hfdcan->TT_ScheduleSyncCallback(hfdcan, TTSchedSyncITs); #else /* TT Schedule Synchronization Callback */ HAL_FDCAN_TT_ScheduleSyncCallback(hfdcan, TTSchedSyncITs); 80021e8: 6af9 ldr r1, [r7, #44] ; 0x2c 80021ea: 6878 ldr r0, [r7, #4] 80021ec: f000 f8e6 bl 80023bc #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ } /* TT Time Mark interrupts management *************************************/ if (TTTimeMarkITs != 0U) 80021f0: 6abb ldr r3, [r7, #40] ; 0x28 80021f2: 2b00 cmp r3, #0 80021f4: d007 beq.n 8002206 { /* Clear the TT Time Mark flags */ __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTTimeMarkITs); 80021f6: 687b ldr r3, [r7, #4] 80021f8: 685b ldr r3, [r3, #4] 80021fa: 6aba ldr r2, [r7, #40] ; 0x28 80021fc: 621a str r2, [r3, #32] #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hfdcan->TT_TimeMarkCallback(hfdcan, TTTimeMarkITs); #else /* TT Time Mark Callback */ HAL_FDCAN_TT_TimeMarkCallback(hfdcan, TTTimeMarkITs); 80021fe: 6ab9 ldr r1, [r7, #40] ; 0x28 8002200: 6878 ldr r0, [r7, #4] 8002202: f000 f8e6 bl 80023d2 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ } /* TT Stop Watch interrupt management *************************************/ if (FDCAN_CHECK_IT_SOURCE(itsourceTTIE, FDCAN_TT_IT_STOP_WATCH) != RESET) 8002206: 69bb ldr r3, [r7, #24] 8002208: 099b lsrs r3, r3, #6 800220a: f003 0301 and.w r3, r3, #1 800220e: 2b00 cmp r3, #0 8002210: d01a beq.n 8002248 { if (FDCAN_CHECK_FLAG(itflagTTIR, FDCAN_TT_FLAG_STOP_WATCH) != RESET) 8002212: 697b ldr r3, [r7, #20] 8002214: 099b lsrs r3, r3, #6 8002216: f003 0301 and.w r3, r3, #1 800221a: 2b00 cmp r3, #0 800221c: d014 beq.n 8002248 { /* Retrieve Stop watch Time and Cycle count */ SWTime = ((hfdcan->ttcan->TTCPT & FDCAN_TTCPT_SWV) >> FDCAN_TTCPT_SWV_Pos); 800221e: 687b ldr r3, [r7, #4] 8002220: 685b ldr r3, [r3, #4] 8002222: 6bdb ldr r3, [r3, #60] ; 0x3c 8002224: 0c1b lsrs r3, r3, #16 8002226: b29b uxth r3, r3 8002228: 613b str r3, [r7, #16] SWCycleCount = ((hfdcan->ttcan->TTCPT & FDCAN_TTCPT_CCV) >> FDCAN_TTCPT_CCV_Pos); 800222a: 687b ldr r3, [r7, #4] 800222c: 685b ldr r3, [r3, #4] 800222e: 6bdb ldr r3, [r3, #60] ; 0x3c 8002230: f003 033f and.w r3, r3, #63 ; 0x3f 8002234: 60fb str r3, [r7, #12] /* Clear the TT Stop Watch flag */ __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, FDCAN_TT_FLAG_STOP_WATCH); 8002236: 687b ldr r3, [r7, #4] 8002238: 685b ldr r3, [r3, #4] 800223a: 2240 movs r2, #64 ; 0x40 800223c: 621a str r2, [r3, #32] #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hfdcan->TT_StopWatchCallback(hfdcan, SWTime, SWCycleCount); #else /* TT Stop Watch Callback */ HAL_FDCAN_TT_StopWatchCallback(hfdcan, SWTime, SWCycleCount); 800223e: 68fa ldr r2, [r7, #12] 8002240: 6939 ldr r1, [r7, #16] 8002242: 6878 ldr r0, [r7, #4] 8002244: f000 f8d0 bl 80023e8 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ } } /* TT Global Time interrupts management ***********************************/ if (TTGlobTimeITs != 0U) 8002248: 6a7b ldr r3, [r7, #36] ; 0x24 800224a: 2b00 cmp r3, #0 800224c: d007 beq.n 800225e { /* Clear the TT Global Time flags */ __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTGlobTimeITs); 800224e: 687b ldr r3, [r7, #4] 8002250: 685b ldr r3, [r3, #4] 8002252: 6a7a ldr r2, [r7, #36] ; 0x24 8002254: 621a str r2, [r3, #32] #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hfdcan->TT_GlobalTimeCallback(hfdcan, TTGlobTimeITs); #else /* TT Global Time Callback */ HAL_FDCAN_TT_GlobalTimeCallback(hfdcan, TTGlobTimeITs); 8002256: 6a79 ldr r1, [r7, #36] ; 0x24 8002258: 6878 ldr r0, [r7, #4] 800225a: f000 f8d1 bl 8002400 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ } /* TT Disturbing Error interrupts management ******************************/ if (TTDistErrors != 0U) 800225e: 6a3b ldr r3, [r7, #32] 8002260: 2b00 cmp r3, #0 8002262: d00b beq.n 800227c { /* Clear the TT Disturbing Error flags */ __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTDistErrors); 8002264: 687b ldr r3, [r7, #4] 8002266: 685b ldr r3, [r3, #4] 8002268: 6a3a ldr r2, [r7, #32] 800226a: 621a str r2, [r3, #32] /* Update error code */ hfdcan->ErrorCode |= TTDistErrors; 800226c: 687b ldr r3, [r7, #4] 800226e: f8d3 209c ldr.w r2, [r3, #156] ; 0x9c 8002272: 6a3b ldr r3, [r7, #32] 8002274: 431a orrs r2, r3 8002276: 687b ldr r3, [r7, #4] 8002278: f8c3 209c str.w r2, [r3, #156] ; 0x9c } /* TT Fatal Error interrupts management ***********************************/ if (TTFatalErrors != 0U) 800227c: 69fb ldr r3, [r7, #28] 800227e: 2b00 cmp r3, #0 8002280: d00b beq.n 800229a { /* Clear the TT Fatal Error flags */ __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTFatalErrors); 8002282: 687b ldr r3, [r7, #4] 8002284: 685b ldr r3, [r3, #4] 8002286: 69fa ldr r2, [r7, #28] 8002288: 621a str r2, [r3, #32] /* Update error code */ hfdcan->ErrorCode |= TTFatalErrors; 800228a: 687b ldr r3, [r7, #4] 800228c: f8d3 209c ldr.w r2, [r3, #156] ; 0x9c 8002290: 69fb ldr r3, [r7, #28] 8002292: 431a orrs r2, r3 8002294: 687b ldr r3, [r7, #4] 8002296: f8c3 209c str.w r2, [r3, #156] ; 0x9c } } } if (hfdcan->ErrorCode != HAL_FDCAN_ERROR_NONE) 800229a: 687b ldr r3, [r7, #4] 800229c: f8d3 309c ldr.w r3, [r3, #156] ; 0x9c 80022a0: 2b00 cmp r3, #0 80022a2: d002 beq.n 80022aa #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hfdcan->ErrorCallback(hfdcan); #else /* Error Callback */ HAL_FDCAN_ErrorCallback(hfdcan); 80022a4: 6878 ldr r0, [r7, #4] 80022a6: f000 f874 bl 8002392 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ } } 80022aa: bf00 nop 80022ac: 3758 adds r7, #88 ; 0x58 80022ae: 46bd mov sp, r7 80022b0: bd80 pop {r7, pc} 80022b2: bf00 nop 80022b4: 4000a800 .word 0x4000a800 80022b8: 3fcfffff .word 0x3fcfffff 80022bc: 4000a000 .word 0x4000a000 080022c0 : * @param ClkCalibrationITs indicates which Clock Calibration interrupts are signaled. * This parameter can be any combination of @arg FDCAN_Clock_Calibration_Interrupts. * @retval None */ __weak void HAL_FDCAN_ClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs) { 80022c0: b480 push {r7} 80022c2: b083 sub sp, #12 80022c4: af00 add r7, sp, #0 80022c6: 6078 str r0, [r7, #4] 80022c8: 6039 str r1, [r7, #0] UNUSED(ClkCalibrationITs); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_FDCAN_ClockCalibrationCallback could be implemented in the user file */ } 80022ca: bf00 nop 80022cc: 370c adds r7, #12 80022ce: 46bd mov sp, r7 80022d0: f85d 7b04 ldr.w r7, [sp], #4 80022d4: 4770 bx lr 080022d6 : * @param TxEventFifoITs indicates which Tx Event FIFO interrupts are signaled. * This parameter can be any combination of @arg FDCAN_Tx_Event_Fifo_Interrupts. * @retval None */ __weak void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs) { 80022d6: b480 push {r7} 80022d8: b083 sub sp, #12 80022da: af00 add r7, sp, #0 80022dc: 6078 str r0, [r7, #4] 80022de: 6039 str r1, [r7, #0] UNUSED(TxEventFifoITs); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_FDCAN_TxEventFifoCallback could be implemented in the user file */ } 80022e0: bf00 nop 80022e2: 370c adds r7, #12 80022e4: 46bd mov sp, r7 80022e6: f85d 7b04 ldr.w r7, [sp], #4 80022ea: 4770 bx lr 080022ec : * @param RxFifo1ITs indicates which Rx FIFO 1 interrupts are signaled. * This parameter can be any combination of @arg FDCAN_Rx_Fifo1_Interrupts. * @retval None */ __weak void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs) { 80022ec: b480 push {r7} 80022ee: b083 sub sp, #12 80022f0: af00 add r7, sp, #0 80022f2: 6078 str r0, [r7, #4] 80022f4: 6039 str r1, [r7, #0] UNUSED(RxFifo1ITs); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_FDCAN_RxFifo1Callback could be implemented in the user file */ } 80022f6: bf00 nop 80022f8: 370c adds r7, #12 80022fa: 46bd mov sp, r7 80022fc: f85d 7b04 ldr.w r7, [sp], #4 8002300: 4770 bx lr 08002302 : * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains * the configuration information for the specified FDCAN. * @retval None */ __weak void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan) { 8002302: b480 push {r7} 8002304: b083 sub sp, #12 8002306: af00 add r7, sp, #0 8002308: 6078 str r0, [r7, #4] UNUSED(hfdcan); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_FDCAN_TxFifoEmptyCallback could be implemented in the user file */ } 800230a: bf00 nop 800230c: 370c adds r7, #12 800230e: 46bd mov sp, r7 8002310: f85d 7b04 ldr.w r7, [sp], #4 8002314: 4770 bx lr 08002316 : * @param BufferIndexes Indexes of the transmitted buffers. * This parameter can be any combination of @arg FDCAN_Tx_location. * @retval None */ __weak void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes) { 8002316: b480 push {r7} 8002318: b083 sub sp, #12 800231a: af00 add r7, sp, #0 800231c: 6078 str r0, [r7, #4] 800231e: 6039 str r1, [r7, #0] UNUSED(BufferIndexes); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_FDCAN_TxBufferCompleteCallback could be implemented in the user file */ } 8002320: bf00 nop 8002322: 370c adds r7, #12 8002324: 46bd mov sp, r7 8002326: f85d 7b04 ldr.w r7, [sp], #4 800232a: 4770 bx lr 0800232c : * @param BufferIndexes Indexes of the aborted buffers. * This parameter can be any combination of @arg FDCAN_Tx_location. * @retval None */ __weak void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes) { 800232c: b480 push {r7} 800232e: b083 sub sp, #12 8002330: af00 add r7, sp, #0 8002332: 6078 str r0, [r7, #4] 8002334: 6039 str r1, [r7, #0] UNUSED(BufferIndexes); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_FDCAN_TxBufferAbortCallback could be implemented in the user file */ } 8002336: bf00 nop 8002338: 370c adds r7, #12 800233a: 46bd mov sp, r7 800233c: f85d 7b04 ldr.w r7, [sp], #4 8002340: 4770 bx lr 08002342 : * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains * the configuration information for the specified FDCAN. * @retval None */ __weak void HAL_FDCAN_RxBufferNewMessageCallback(FDCAN_HandleTypeDef *hfdcan) { 8002342: b480 push {r7} 8002344: b083 sub sp, #12 8002346: af00 add r7, sp, #0 8002348: 6078 str r0, [r7, #4] UNUSED(hfdcan); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_FDCAN_RxBufferNewMessageCallback could be implemented in the user file */ } 800234a: bf00 nop 800234c: 370c adds r7, #12 800234e: 46bd mov sp, r7 8002350: f85d 7b04 ldr.w r7, [sp], #4 8002354: 4770 bx lr 08002356 : * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains * the configuration information for the specified FDCAN. * @retval None */ __weak void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan) { 8002356: b480 push {r7} 8002358: b083 sub sp, #12 800235a: af00 add r7, sp, #0 800235c: 6078 str r0, [r7, #4] UNUSED(hfdcan); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_FDCAN_TimestampWraparoundCallback could be implemented in the user file */ } 800235e: bf00 nop 8002360: 370c adds r7, #12 8002362: 46bd mov sp, r7 8002364: f85d 7b04 ldr.w r7, [sp], #4 8002368: 4770 bx lr 0800236a : * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains * the configuration information for the specified FDCAN. * @retval None */ __weak void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan) { 800236a: b480 push {r7} 800236c: b083 sub sp, #12 800236e: af00 add r7, sp, #0 8002370: 6078 str r0, [r7, #4] UNUSED(hfdcan); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_FDCAN_TimeoutOccurredCallback could be implemented in the user file */ } 8002372: bf00 nop 8002374: 370c adds r7, #12 8002376: 46bd mov sp, r7 8002378: f85d 7b04 ldr.w r7, [sp], #4 800237c: 4770 bx lr 0800237e : * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains * the configuration information for the specified FDCAN. * @retval None */ __weak void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan) { 800237e: b480 push {r7} 8002380: b083 sub sp, #12 8002382: af00 add r7, sp, #0 8002384: 6078 str r0, [r7, #4] UNUSED(hfdcan); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_FDCAN_HighPriorityMessageCallback could be implemented in the user file */ } 8002386: bf00 nop 8002388: 370c adds r7, #12 800238a: 46bd mov sp, r7 800238c: f85d 7b04 ldr.w r7, [sp], #4 8002390: 4770 bx lr 08002392 : * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains * the configuration information for the specified FDCAN. * @retval None */ __weak void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan) { 8002392: b480 push {r7} 8002394: b083 sub sp, #12 8002396: af00 add r7, sp, #0 8002398: 6078 str r0, [r7, #4] UNUSED(hfdcan); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_FDCAN_ErrorCallback could be implemented in the user file */ } 800239a: bf00 nop 800239c: 370c adds r7, #12 800239e: 46bd mov sp, r7 80023a0: f85d 7b04 ldr.w r7, [sp], #4 80023a4: 4770 bx lr 080023a6 : * @param ErrorStatusITs indicates which Error Status interrupts are signaled. * This parameter can be any combination of @arg FDCAN_Error_Status_Interrupts. * @retval None */ __weak void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs) { 80023a6: b480 push {r7} 80023a8: b083 sub sp, #12 80023aa: af00 add r7, sp, #0 80023ac: 6078 str r0, [r7, #4] 80023ae: 6039 str r1, [r7, #0] UNUSED(ErrorStatusITs); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_FDCAN_ErrorStatusCallback could be implemented in the user file */ } 80023b0: bf00 nop 80023b2: 370c adds r7, #12 80023b4: 46bd mov sp, r7 80023b6: f85d 7b04 ldr.w r7, [sp], #4 80023ba: 4770 bx lr 080023bc : * @param TTSchedSyncITs indicates which TT Schedule Synchronization interrupts are signaled. * This parameter can be any combination of @arg FDCAN_TTScheduleSynchronization_Interrupts. * @retval None */ __weak void HAL_FDCAN_TT_ScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs) { 80023bc: b480 push {r7} 80023be: b083 sub sp, #12 80023c0: af00 add r7, sp, #0 80023c2: 6078 str r0, [r7, #4] 80023c4: 6039 str r1, [r7, #0] UNUSED(TTSchedSyncITs); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_FDCAN_TT_ScheduleSyncCallback could be implemented in the user file */ } 80023c6: bf00 nop 80023c8: 370c adds r7, #12 80023ca: 46bd mov sp, r7 80023cc: f85d 7b04 ldr.w r7, [sp], #4 80023d0: 4770 bx lr 080023d2 : * @param TTTimeMarkITs indicates which TT Schedule Synchronization interrupts are signaled. * This parameter can be any combination of @arg FDCAN_TTTimeMark_Interrupts. * @retval None */ __weak void HAL_FDCAN_TT_TimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs) { 80023d2: b480 push {r7} 80023d4: b083 sub sp, #12 80023d6: af00 add r7, sp, #0 80023d8: 6078 str r0, [r7, #4] 80023da: 6039 str r1, [r7, #0] UNUSED(TTTimeMarkITs); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_FDCAN_TT_TimeMarkCallback could be implemented in the user file */ } 80023dc: bf00 nop 80023de: 370c adds r7, #12 80023e0: 46bd mov sp, r7 80023e2: f85d 7b04 ldr.w r7, [sp], #4 80023e6: 4770 bx lr 080023e8 : * @param SWCycleCount Cycle count value captured together with SWTime. * This parameter is a number between 0 and 0x3F. * @retval None */ __weak void HAL_FDCAN_TT_StopWatchCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount) { 80023e8: b480 push {r7} 80023ea: b085 sub sp, #20 80023ec: af00 add r7, sp, #0 80023ee: 60f8 str r0, [r7, #12] 80023f0: 60b9 str r1, [r7, #8] 80023f2: 607a str r2, [r7, #4] UNUSED(SWCycleCount); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_FDCAN_TT_StopWatchCallback could be implemented in the user file */ } 80023f4: bf00 nop 80023f6: 3714 adds r7, #20 80023f8: 46bd mov sp, r7 80023fa: f85d 7b04 ldr.w r7, [sp], #4 80023fe: 4770 bx lr 08002400 : * @param TTGlobTimeITs indicates which TT Global Time interrupts are signaled. * This parameter can be any combination of @arg FDCAN_TTGlobalTime_Interrupts. * @retval None */ __weak void HAL_FDCAN_TT_GlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs) { 8002400: b480 push {r7} 8002402: b083 sub sp, #12 8002404: af00 add r7, sp, #0 8002406: 6078 str r0, [r7, #4] 8002408: 6039 str r1, [r7, #0] UNUSED(TTGlobTimeITs); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_FDCAN_TT_GlobalTimeCallback could be implemented in the user file */ } 800240a: bf00 nop 800240c: 370c adds r7, #12 800240e: 46bd mov sp, r7 8002410: f85d 7b04 ldr.w r7, [sp], #4 8002414: 4770 bx lr ... 08002418 : * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains * the configuration information for the specified FDCAN. * @retval HAL status */ static HAL_StatusTypeDef FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan) { 8002418: b480 push {r7} 800241a: b085 sub sp, #20 800241c: af00 add r7, sp, #0 800241e: 6078 str r0, [r7, #4] uint32_t RAMcounter; uint32_t StartAddress; StartAddress = hfdcan->Init.MessageRAMOffset; 8002420: 687b ldr r3, [r7, #4] 8002422: 6b5b ldr r3, [r3, #52] ; 0x34 8002424: 60bb str r3, [r7, #8] /* Standard filter list start address */ MODIFY_REG(hfdcan->Instance->SIDFC, FDCAN_SIDFC_FLSSA, (StartAddress << FDCAN_SIDFC_FLSSA_Pos)); 8002426: 687b ldr r3, [r7, #4] 8002428: 681b ldr r3, [r3, #0] 800242a: f8d3 2084 ldr.w r2, [r3, #132] ; 0x84 800242e: 4ba7 ldr r3, [pc, #668] ; (80026cc ) 8002430: 4013 ands r3, r2 8002432: 68ba ldr r2, [r7, #8] 8002434: 0091 lsls r1, r2, #2 8002436: 687a ldr r2, [r7, #4] 8002438: 6812 ldr r2, [r2, #0] 800243a: 430b orrs r3, r1 800243c: f8c2 3084 str.w r3, [r2, #132] ; 0x84 /* Standard filter elements number */ MODIFY_REG(hfdcan->Instance->SIDFC, FDCAN_SIDFC_LSS, (hfdcan->Init.StdFiltersNbr << FDCAN_SIDFC_LSS_Pos)); 8002440: 687b ldr r3, [r7, #4] 8002442: 681b ldr r3, [r3, #0] 8002444: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 8002448: f423 017f bic.w r1, r3, #16711680 ; 0xff0000 800244c: 687b ldr r3, [r7, #4] 800244e: 6b9b ldr r3, [r3, #56] ; 0x38 8002450: 041a lsls r2, r3, #16 8002452: 687b ldr r3, [r7, #4] 8002454: 681b ldr r3, [r3, #0] 8002456: 430a orrs r2, r1 8002458: f8c3 2084 str.w r2, [r3, #132] ; 0x84 /* Extended filter list start address */ StartAddress += hfdcan->Init.StdFiltersNbr; 800245c: 687b ldr r3, [r7, #4] 800245e: 6b9b ldr r3, [r3, #56] ; 0x38 8002460: 68ba ldr r2, [r7, #8] 8002462: 4413 add r3, r2 8002464: 60bb str r3, [r7, #8] MODIFY_REG(hfdcan->Instance->XIDFC, FDCAN_XIDFC_FLESA, (StartAddress << FDCAN_XIDFC_FLESA_Pos)); 8002466: 687b ldr r3, [r7, #4] 8002468: 681b ldr r3, [r3, #0] 800246a: f8d3 2088 ldr.w r2, [r3, #136] ; 0x88 800246e: 4b97 ldr r3, [pc, #604] ; (80026cc ) 8002470: 4013 ands r3, r2 8002472: 68ba ldr r2, [r7, #8] 8002474: 0091 lsls r1, r2, #2 8002476: 687a ldr r2, [r7, #4] 8002478: 6812 ldr r2, [r2, #0] 800247a: 430b orrs r3, r1 800247c: f8c2 3088 str.w r3, [r2, #136] ; 0x88 /* Extended filter elements number */ MODIFY_REG(hfdcan->Instance->XIDFC, FDCAN_XIDFC_LSE, (hfdcan->Init.ExtFiltersNbr << FDCAN_XIDFC_LSE_Pos)); 8002480: 687b ldr r3, [r7, #4] 8002482: 681b ldr r3, [r3, #0] 8002484: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 8002488: f423 01fe bic.w r1, r3, #8323072 ; 0x7f0000 800248c: 687b ldr r3, [r7, #4] 800248e: 6bdb ldr r3, [r3, #60] ; 0x3c 8002490: 041a lsls r2, r3, #16 8002492: 687b ldr r3, [r7, #4] 8002494: 681b ldr r3, [r3, #0] 8002496: 430a orrs r2, r1 8002498: f8c3 2088 str.w r2, [r3, #136] ; 0x88 /* Rx FIFO 0 start address */ StartAddress += (hfdcan->Init.ExtFiltersNbr * 2U); 800249c: 687b ldr r3, [r7, #4] 800249e: 6bdb ldr r3, [r3, #60] ; 0x3c 80024a0: 005b lsls r3, r3, #1 80024a2: 68ba ldr r2, [r7, #8] 80024a4: 4413 add r3, r2 80024a6: 60bb str r3, [r7, #8] MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0SA, (StartAddress << FDCAN_RXF0C_F0SA_Pos)); 80024a8: 687b ldr r3, [r7, #4] 80024aa: 681b ldr r3, [r3, #0] 80024ac: f8d3 20a0 ldr.w r2, [r3, #160] ; 0xa0 80024b0: 4b86 ldr r3, [pc, #536] ; (80026cc ) 80024b2: 4013 ands r3, r2 80024b4: 68ba ldr r2, [r7, #8] 80024b6: 0091 lsls r1, r2, #2 80024b8: 687a ldr r2, [r7, #4] 80024ba: 6812 ldr r2, [r2, #0] 80024bc: 430b orrs r3, r1 80024be: f8c2 30a0 str.w r3, [r2, #160] ; 0xa0 /* Rx FIFO 0 elements number */ MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0S, (hfdcan->Init.RxFifo0ElmtsNbr << FDCAN_RXF0C_F0S_Pos)); 80024c2: 687b ldr r3, [r7, #4] 80024c4: 681b ldr r3, [r3, #0] 80024c6: f8d3 30a0 ldr.w r3, [r3, #160] ; 0xa0 80024ca: f423 01fe bic.w r1, r3, #8323072 ; 0x7f0000 80024ce: 687b ldr r3, [r7, #4] 80024d0: 6c1b ldr r3, [r3, #64] ; 0x40 80024d2: 041a lsls r2, r3, #16 80024d4: 687b ldr r3, [r7, #4] 80024d6: 681b ldr r3, [r3, #0] 80024d8: 430a orrs r2, r1 80024da: f8c3 20a0 str.w r2, [r3, #160] ; 0xa0 /* Rx FIFO 1 start address */ StartAddress += (hfdcan->Init.RxFifo0ElmtsNbr * hfdcan->Init.RxFifo0ElmtSize); 80024de: 687b ldr r3, [r7, #4] 80024e0: 6c1b ldr r3, [r3, #64] ; 0x40 80024e2: 687a ldr r2, [r7, #4] 80024e4: 6c52 ldr r2, [r2, #68] ; 0x44 80024e6: fb02 f303 mul.w r3, r2, r3 80024ea: 68ba ldr r2, [r7, #8] 80024ec: 4413 add r3, r2 80024ee: 60bb str r3, [r7, #8] MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1SA, (StartAddress << FDCAN_RXF1C_F1SA_Pos)); 80024f0: 687b ldr r3, [r7, #4] 80024f2: 681b ldr r3, [r3, #0] 80024f4: f8d3 20b0 ldr.w r2, [r3, #176] ; 0xb0 80024f8: 4b74 ldr r3, [pc, #464] ; (80026cc ) 80024fa: 4013 ands r3, r2 80024fc: 68ba ldr r2, [r7, #8] 80024fe: 0091 lsls r1, r2, #2 8002500: 687a ldr r2, [r7, #4] 8002502: 6812 ldr r2, [r2, #0] 8002504: 430b orrs r3, r1 8002506: f8c2 30b0 str.w r3, [r2, #176] ; 0xb0 /* Rx FIFO 1 elements number */ MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1S, (hfdcan->Init.RxFifo1ElmtsNbr << FDCAN_RXF1C_F1S_Pos)); 800250a: 687b ldr r3, [r7, #4] 800250c: 681b ldr r3, [r3, #0] 800250e: f8d3 30b0 ldr.w r3, [r3, #176] ; 0xb0 8002512: f423 01fe bic.w r1, r3, #8323072 ; 0x7f0000 8002516: 687b ldr r3, [r7, #4] 8002518: 6c9b ldr r3, [r3, #72] ; 0x48 800251a: 041a lsls r2, r3, #16 800251c: 687b ldr r3, [r7, #4] 800251e: 681b ldr r3, [r3, #0] 8002520: 430a orrs r2, r1 8002522: f8c3 20b0 str.w r2, [r3, #176] ; 0xb0 /* Rx buffer list start address */ StartAddress += (hfdcan->Init.RxFifo1ElmtsNbr * hfdcan->Init.RxFifo1ElmtSize); 8002526: 687b ldr r3, [r7, #4] 8002528: 6c9b ldr r3, [r3, #72] ; 0x48 800252a: 687a ldr r2, [r7, #4] 800252c: 6cd2 ldr r2, [r2, #76] ; 0x4c 800252e: fb02 f303 mul.w r3, r2, r3 8002532: 68ba ldr r2, [r7, #8] 8002534: 4413 add r3, r2 8002536: 60bb str r3, [r7, #8] MODIFY_REG(hfdcan->Instance->RXBC, FDCAN_RXBC_RBSA, (StartAddress << FDCAN_RXBC_RBSA_Pos)); 8002538: 687b ldr r3, [r7, #4] 800253a: 681b ldr r3, [r3, #0] 800253c: f8d3 20ac ldr.w r2, [r3, #172] ; 0xac 8002540: 4b62 ldr r3, [pc, #392] ; (80026cc ) 8002542: 4013 ands r3, r2 8002544: 68ba ldr r2, [r7, #8] 8002546: 0091 lsls r1, r2, #2 8002548: 687a ldr r2, [r7, #4] 800254a: 6812 ldr r2, [r2, #0] 800254c: 430b orrs r3, r1 800254e: f8c2 30ac str.w r3, [r2, #172] ; 0xac /* Tx event FIFO start address */ StartAddress += (hfdcan->Init.RxBuffersNbr * hfdcan->Init.RxBufferSize); 8002552: 687b ldr r3, [r7, #4] 8002554: 6d1b ldr r3, [r3, #80] ; 0x50 8002556: 687a ldr r2, [r7, #4] 8002558: 6d52 ldr r2, [r2, #84] ; 0x54 800255a: fb02 f303 mul.w r3, r2, r3 800255e: 68ba ldr r2, [r7, #8] 8002560: 4413 add r3, r2 8002562: 60bb str r3, [r7, #8] MODIFY_REG(hfdcan->Instance->TXEFC, FDCAN_TXEFC_EFSA, (StartAddress << FDCAN_TXEFC_EFSA_Pos)); 8002564: 687b ldr r3, [r7, #4] 8002566: 681b ldr r3, [r3, #0] 8002568: f8d3 20f0 ldr.w r2, [r3, #240] ; 0xf0 800256c: 4b57 ldr r3, [pc, #348] ; (80026cc ) 800256e: 4013 ands r3, r2 8002570: 68ba ldr r2, [r7, #8] 8002572: 0091 lsls r1, r2, #2 8002574: 687a ldr r2, [r7, #4] 8002576: 6812 ldr r2, [r2, #0] 8002578: 430b orrs r3, r1 800257a: f8c2 30f0 str.w r3, [r2, #240] ; 0xf0 /* Tx event FIFO elements number */ MODIFY_REG(hfdcan->Instance->TXEFC, FDCAN_TXEFC_EFS, (hfdcan->Init.TxEventsNbr << FDCAN_TXEFC_EFS_Pos)); 800257e: 687b ldr r3, [r7, #4] 8002580: 681b ldr r3, [r3, #0] 8002582: f8d3 30f0 ldr.w r3, [r3, #240] ; 0xf0 8002586: f423 117c bic.w r1, r3, #4128768 ; 0x3f0000 800258a: 687b ldr r3, [r7, #4] 800258c: 6d9b ldr r3, [r3, #88] ; 0x58 800258e: 041a lsls r2, r3, #16 8002590: 687b ldr r3, [r7, #4] 8002592: 681b ldr r3, [r3, #0] 8002594: 430a orrs r2, r1 8002596: f8c3 20f0 str.w r2, [r3, #240] ; 0xf0 /* Tx buffer list start address */ StartAddress += (hfdcan->Init.TxEventsNbr * 2U); 800259a: 687b ldr r3, [r7, #4] 800259c: 6d9b ldr r3, [r3, #88] ; 0x58 800259e: 005b lsls r3, r3, #1 80025a0: 68ba ldr r2, [r7, #8] 80025a2: 4413 add r3, r2 80025a4: 60bb str r3, [r7, #8] MODIFY_REG(hfdcan->Instance->TXBC, FDCAN_TXBC_TBSA, (StartAddress << FDCAN_TXBC_TBSA_Pos)); 80025a6: 687b ldr r3, [r7, #4] 80025a8: 681b ldr r3, [r3, #0] 80025aa: f8d3 20c0 ldr.w r2, [r3, #192] ; 0xc0 80025ae: 4b47 ldr r3, [pc, #284] ; (80026cc ) 80025b0: 4013 ands r3, r2 80025b2: 68ba ldr r2, [r7, #8] 80025b4: 0091 lsls r1, r2, #2 80025b6: 687a ldr r2, [r7, #4] 80025b8: 6812 ldr r2, [r2, #0] 80025ba: 430b orrs r3, r1 80025bc: f8c2 30c0 str.w r3, [r2, #192] ; 0xc0 /* Dedicated Tx buffers number */ MODIFY_REG(hfdcan->Instance->TXBC, FDCAN_TXBC_NDTB, (hfdcan->Init.TxBuffersNbr << FDCAN_TXBC_NDTB_Pos)); 80025c0: 687b ldr r3, [r7, #4] 80025c2: 681b ldr r3, [r3, #0] 80025c4: f8d3 30c0 ldr.w r3, [r3, #192] ; 0xc0 80025c8: f423 117c bic.w r1, r3, #4128768 ; 0x3f0000 80025cc: 687b ldr r3, [r7, #4] 80025ce: 6ddb ldr r3, [r3, #92] ; 0x5c 80025d0: 041a lsls r2, r3, #16 80025d2: 687b ldr r3, [r7, #4] 80025d4: 681b ldr r3, [r3, #0] 80025d6: 430a orrs r2, r1 80025d8: f8c3 20c0 str.w r2, [r3, #192] ; 0xc0 /* Tx FIFO/queue elements number */ MODIFY_REG(hfdcan->Instance->TXBC, FDCAN_TXBC_TFQS, (hfdcan->Init.TxFifoQueueElmtsNbr << FDCAN_TXBC_TFQS_Pos)); 80025dc: 687b ldr r3, [r7, #4] 80025de: 681b ldr r3, [r3, #0] 80025e0: f8d3 30c0 ldr.w r3, [r3, #192] ; 0xc0 80025e4: f023 517c bic.w r1, r3, #1056964608 ; 0x3f000000 80025e8: 687b ldr r3, [r7, #4] 80025ea: 6e1b ldr r3, [r3, #96] ; 0x60 80025ec: 061a lsls r2, r3, #24 80025ee: 687b ldr r3, [r7, #4] 80025f0: 681b ldr r3, [r3, #0] 80025f2: 430a orrs r2, r1 80025f4: f8c3 20c0 str.w r2, [r3, #192] ; 0xc0 hfdcan->msgRam.StandardFilterSA = SRAMCAN_BASE + (hfdcan->Init.MessageRAMOffset * 4U); 80025f8: 687b ldr r3, [r7, #4] 80025fa: 6b5a ldr r2, [r3, #52] ; 0x34 80025fc: 4b34 ldr r3, [pc, #208] ; (80026d0 ) 80025fe: 4413 add r3, r2 8002600: 009a lsls r2, r3, #2 8002602: 687b ldr r3, [r7, #4] 8002604: 66da str r2, [r3, #108] ; 0x6c hfdcan->msgRam.ExtendedFilterSA = hfdcan->msgRam.StandardFilterSA + (hfdcan->Init.StdFiltersNbr * 4U); 8002606: 687b ldr r3, [r7, #4] 8002608: 6eda ldr r2, [r3, #108] ; 0x6c 800260a: 687b ldr r3, [r7, #4] 800260c: 6b9b ldr r3, [r3, #56] ; 0x38 800260e: 009b lsls r3, r3, #2 8002610: 441a add r2, r3 8002612: 687b ldr r3, [r7, #4] 8002614: 671a str r2, [r3, #112] ; 0x70 hfdcan->msgRam.RxFIFO0SA = hfdcan->msgRam.ExtendedFilterSA + (hfdcan->Init.ExtFiltersNbr * 2U * 4U); 8002616: 687b ldr r3, [r7, #4] 8002618: 6f1a ldr r2, [r3, #112] ; 0x70 800261a: 687b ldr r3, [r7, #4] 800261c: 6bdb ldr r3, [r3, #60] ; 0x3c 800261e: 00db lsls r3, r3, #3 8002620: 441a add r2, r3 8002622: 687b ldr r3, [r7, #4] 8002624: 675a str r2, [r3, #116] ; 0x74 hfdcan->msgRam.RxFIFO1SA = hfdcan->msgRam.RxFIFO0SA + (hfdcan->Init.RxFifo0ElmtsNbr * hfdcan->Init.RxFifo0ElmtSize * 4U); 8002626: 687b ldr r3, [r7, #4] 8002628: 6f5a ldr r2, [r3, #116] ; 0x74 800262a: 687b ldr r3, [r7, #4] 800262c: 6c1b ldr r3, [r3, #64] ; 0x40 800262e: 6879 ldr r1, [r7, #4] 8002630: 6c49 ldr r1, [r1, #68] ; 0x44 8002632: fb01 f303 mul.w r3, r1, r3 8002636: 009b lsls r3, r3, #2 8002638: 441a add r2, r3 800263a: 687b ldr r3, [r7, #4] 800263c: 679a str r2, [r3, #120] ; 0x78 hfdcan->msgRam.RxBufferSA = hfdcan->msgRam.RxFIFO1SA + (hfdcan->Init.RxFifo1ElmtsNbr * hfdcan->Init.RxFifo1ElmtSize * 4U); 800263e: 687b ldr r3, [r7, #4] 8002640: 6f9a ldr r2, [r3, #120] ; 0x78 8002642: 687b ldr r3, [r7, #4] 8002644: 6c9b ldr r3, [r3, #72] ; 0x48 8002646: 6879 ldr r1, [r7, #4] 8002648: 6cc9 ldr r1, [r1, #76] ; 0x4c 800264a: fb01 f303 mul.w r3, r1, r3 800264e: 009b lsls r3, r3, #2 8002650: 441a add r2, r3 8002652: 687b ldr r3, [r7, #4] 8002654: 67da str r2, [r3, #124] ; 0x7c hfdcan->msgRam.TxEventFIFOSA = hfdcan->msgRam.RxBufferSA + (hfdcan->Init.RxBuffersNbr * hfdcan->Init.RxBufferSize * 4U); 8002656: 687b ldr r3, [r7, #4] 8002658: 6fda ldr r2, [r3, #124] ; 0x7c 800265a: 687b ldr r3, [r7, #4] 800265c: 6d1b ldr r3, [r3, #80] ; 0x50 800265e: 6879 ldr r1, [r7, #4] 8002660: 6d49 ldr r1, [r1, #84] ; 0x54 8002662: fb01 f303 mul.w r3, r1, r3 8002666: 009b lsls r3, r3, #2 8002668: 441a add r2, r3 800266a: 687b ldr r3, [r7, #4] 800266c: f8c3 2080 str.w r2, [r3, #128] ; 0x80 hfdcan->msgRam.TxBufferSA = hfdcan->msgRam.TxEventFIFOSA + (hfdcan->Init.TxEventsNbr * 2U * 4U); 8002670: 687b ldr r3, [r7, #4] 8002672: f8d3 2080 ldr.w r2, [r3, #128] ; 0x80 8002676: 687b ldr r3, [r7, #4] 8002678: 6d9b ldr r3, [r3, #88] ; 0x58 800267a: 00db lsls r3, r3, #3 800267c: 441a add r2, r3 800267e: 687b ldr r3, [r7, #4] 8002680: f8c3 2084 str.w r2, [r3, #132] ; 0x84 hfdcan->msgRam.TxFIFOQSA = hfdcan->msgRam.TxBufferSA + (hfdcan->Init.TxBuffersNbr * hfdcan->Init.TxElmtSize * 4U); 8002684: 687b ldr r3, [r7, #4] 8002686: f8d3 2084 ldr.w r2, [r3, #132] ; 0x84 800268a: 687b ldr r3, [r7, #4] 800268c: 6ddb ldr r3, [r3, #92] ; 0x5c 800268e: 6879 ldr r1, [r7, #4] 8002690: 6e89 ldr r1, [r1, #104] ; 0x68 8002692: fb01 f303 mul.w r3, r1, r3 8002696: 009b lsls r3, r3, #2 8002698: 441a add r2, r3 800269a: 687b ldr r3, [r7, #4] 800269c: f8c3 2088 str.w r2, [r3, #136] ; 0x88 hfdcan->msgRam.EndAddress = hfdcan->msgRam.TxFIFOQSA + (hfdcan->Init.TxFifoQueueElmtsNbr * hfdcan->Init.TxElmtSize * 4U); 80026a0: 687b ldr r3, [r7, #4] 80026a2: f8d3 2088 ldr.w r2, [r3, #136] ; 0x88 80026a6: 687b ldr r3, [r7, #4] 80026a8: 6e1b ldr r3, [r3, #96] ; 0x60 80026aa: 6879 ldr r1, [r7, #4] 80026ac: 6e89 ldr r1, [r1, #104] ; 0x68 80026ae: fb01 f303 mul.w r3, r1, r3 80026b2: 009b lsls r3, r3, #2 80026b4: 441a add r2, r3 80026b6: 687b ldr r3, [r7, #4] 80026b8: f8c3 2090 str.w r2, [r3, #144] ; 0x90 if (hfdcan->msgRam.EndAddress > FDCAN_MESSAGE_RAM_END_ADDRESS) /* Last address of the Message RAM */ 80026bc: 687b ldr r3, [r7, #4] 80026be: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 80026c2: 4a04 ldr r2, [pc, #16] ; (80026d4 ) 80026c4: 4293 cmp r3, r2 80026c6: d915 bls.n 80026f4 80026c8: e006 b.n 80026d8 80026ca: bf00 nop 80026cc: ffff0003 .word 0xffff0003 80026d0: 10002b00 .word 0x10002b00 80026d4: 4000d3fc .word 0x4000d3fc { /* Update error code. Message RAM overflow */ hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM; 80026d8: 687b ldr r3, [r7, #4] 80026da: f8d3 309c ldr.w r3, [r3, #156] ; 0x9c 80026de: f043 0220 orr.w r2, r3, #32 80026e2: 687b ldr r3, [r7, #4] 80026e4: f8c3 209c str.w r2, [r3, #156] ; 0x9c /* Change FDCAN state */ hfdcan->State = HAL_FDCAN_STATE_ERROR; 80026e8: 687b ldr r3, [r7, #4] 80026ea: 2203 movs r2, #3 80026ec: f883 2098 strb.w r2, [r3, #152] ; 0x98 return HAL_ERROR; 80026f0: 2301 movs r3, #1 80026f2: e010 b.n 8002716 } else { /* Flush the allocated Message RAM area */ for (RAMcounter = hfdcan->msgRam.StandardFilterSA; RAMcounter < hfdcan->msgRam.EndAddress; RAMcounter += 4U) 80026f4: 687b ldr r3, [r7, #4] 80026f6: 6edb ldr r3, [r3, #108] ; 0x6c 80026f8: 60fb str r3, [r7, #12] 80026fa: e005 b.n 8002708 { *(uint32_t *)(RAMcounter) = 0x00000000; 80026fc: 68fb ldr r3, [r7, #12] 80026fe: 2200 movs r2, #0 8002700: 601a str r2, [r3, #0] for (RAMcounter = hfdcan->msgRam.StandardFilterSA; RAMcounter < hfdcan->msgRam.EndAddress; RAMcounter += 4U) 8002702: 68fb ldr r3, [r7, #12] 8002704: 3304 adds r3, #4 8002706: 60fb str r3, [r7, #12] 8002708: 687b ldr r3, [r7, #4] 800270a: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 800270e: 68fa ldr r2, [r7, #12] 8002710: 429a cmp r2, r3 8002712: d3f3 bcc.n 80026fc } } /* Return function status */ return HAL_OK; 8002714: 2300 movs r3, #0 } 8002716: 4618 mov r0, r3 8002718: 3714 adds r7, #20 800271a: 46bd mov sp, r7 800271c: f85d 7b04 ldr.w r7, [sp], #4 8002720: 4770 bx lr 8002722: bf00 nop 08002724 : * @param pTxData pointer to a buffer containing the payload of the Tx frame. * @param BufferIndex index of the buffer to be configured. * @retval HAL status */ static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex) { 8002724: b480 push {r7} 8002726: b089 sub sp, #36 ; 0x24 8002728: af00 add r7, sp, #0 800272a: 60f8 str r0, [r7, #12] 800272c: 60b9 str r1, [r7, #8] 800272e: 607a str r2, [r7, #4] 8002730: 603b str r3, [r7, #0] uint32_t TxElementW2; uint32_t *TxAddress; uint32_t ByteCounter; /* Build first word of Tx header element */ if (pTxHeader->IdType == FDCAN_STANDARD_ID) 8002732: 68bb ldr r3, [r7, #8] 8002734: 685b ldr r3, [r3, #4] 8002736: 2b00 cmp r3, #0 8002738: d10a bne.n 8002750 { TxElementW1 = (pTxHeader->ErrorStateIndicator | 800273a: 68bb ldr r3, [r7, #8] 800273c: 691a ldr r2, [r3, #16] FDCAN_STANDARD_ID | pTxHeader->TxFrameType | 800273e: 68bb ldr r3, [r7, #8] 8002740: 689b ldr r3, [r3, #8] FDCAN_STANDARD_ID | 8002742: 431a orrs r2, r3 (pTxHeader->Identifier << 18)); 8002744: 68bb ldr r3, [r7, #8] 8002746: 681b ldr r3, [r3, #0] 8002748: 049b lsls r3, r3, #18 TxElementW1 = (pTxHeader->ErrorStateIndicator | 800274a: 4313 orrs r3, r2 800274c: 61fb str r3, [r7, #28] 800274e: e00a b.n 8002766 } else /* pTxHeader->IdType == FDCAN_EXTENDED_ID */ { TxElementW1 = (pTxHeader->ErrorStateIndicator | 8002750: 68bb ldr r3, [r7, #8] 8002752: 691a ldr r2, [r3, #16] FDCAN_EXTENDED_ID | pTxHeader->TxFrameType | 8002754: 68bb ldr r3, [r7, #8] 8002756: 689b ldr r3, [r3, #8] FDCAN_EXTENDED_ID | 8002758: 431a orrs r2, r3 pTxHeader->Identifier); 800275a: 68bb ldr r3, [r7, #8] 800275c: 681b ldr r3, [r3, #0] pTxHeader->TxFrameType | 800275e: 4313 orrs r3, r2 TxElementW1 = (pTxHeader->ErrorStateIndicator | 8002760: f043 4380 orr.w r3, r3, #1073741824 ; 0x40000000 8002764: 61fb str r3, [r7, #28] } /* Build second word of Tx header element */ TxElementW2 = ((pTxHeader->MessageMarker << 24) | 8002766: 68bb ldr r3, [r7, #8] 8002768: 6a1b ldr r3, [r3, #32] 800276a: 061a lsls r2, r3, #24 pTxHeader->TxEventFifoControl | 800276c: 68bb ldr r3, [r7, #8] 800276e: 69db ldr r3, [r3, #28] TxElementW2 = ((pTxHeader->MessageMarker << 24) | 8002770: 431a orrs r2, r3 pTxHeader->FDFormat | 8002772: 68bb ldr r3, [r7, #8] 8002774: 699b ldr r3, [r3, #24] pTxHeader->TxEventFifoControl | 8002776: 431a orrs r2, r3 pTxHeader->BitRateSwitch | 8002778: 68bb ldr r3, [r7, #8] 800277a: 695b ldr r3, [r3, #20] pTxHeader->FDFormat | 800277c: 431a orrs r2, r3 pTxHeader->DataLength); 800277e: 68bb ldr r3, [r7, #8] 8002780: 68db ldr r3, [r3, #12] TxElementW2 = ((pTxHeader->MessageMarker << 24) | 8002782: 4313 orrs r3, r2 8002784: 613b str r3, [r7, #16] /* Calculate Tx element address */ TxAddress = (uint32_t *)(hfdcan->msgRam.TxBufferSA + (BufferIndex * hfdcan->Init.TxElmtSize * 4U)); 8002786: 68fb ldr r3, [r7, #12] 8002788: f8d3 2084 ldr.w r2, [r3, #132] ; 0x84 800278c: 68fb ldr r3, [r7, #12] 800278e: 6e9b ldr r3, [r3, #104] ; 0x68 8002790: 6839 ldr r1, [r7, #0] 8002792: fb01 f303 mul.w r3, r1, r3 8002796: 009b lsls r3, r3, #2 8002798: 4413 add r3, r2 800279a: 61bb str r3, [r7, #24] /* Write Tx element header to the message RAM */ *TxAddress = TxElementW1; 800279c: 69bb ldr r3, [r7, #24] 800279e: 69fa ldr r2, [r7, #28] 80027a0: 601a str r2, [r3, #0] TxAddress++; 80027a2: 69bb ldr r3, [r7, #24] 80027a4: 3304 adds r3, #4 80027a6: 61bb str r3, [r7, #24] *TxAddress = TxElementW2; 80027a8: 69bb ldr r3, [r7, #24] 80027aa: 693a ldr r2, [r7, #16] 80027ac: 601a str r2, [r3, #0] TxAddress++; 80027ae: 69bb ldr r3, [r7, #24] 80027b0: 3304 adds r3, #4 80027b2: 61bb str r3, [r7, #24] /* Write Tx payload to the message RAM */ for (ByteCounter = 0; ByteCounter < DLCtoBytes[pTxHeader->DataLength >> 16]; ByteCounter += 4U) 80027b4: 2300 movs r3, #0 80027b6: 617b str r3, [r7, #20] 80027b8: e020 b.n 80027fc { *TxAddress = (((uint32_t)pTxData[ByteCounter + 3U] << 24) | 80027ba: 697b ldr r3, [r7, #20] 80027bc: 3303 adds r3, #3 80027be: 687a ldr r2, [r7, #4] 80027c0: 4413 add r3, r2 80027c2: 781b ldrb r3, [r3, #0] 80027c4: 061a lsls r2, r3, #24 ((uint32_t)pTxData[ByteCounter + 2U] << 16) | 80027c6: 697b ldr r3, [r7, #20] 80027c8: 3302 adds r3, #2 80027ca: 6879 ldr r1, [r7, #4] 80027cc: 440b add r3, r1 80027ce: 781b ldrb r3, [r3, #0] 80027d0: 041b lsls r3, r3, #16 *TxAddress = (((uint32_t)pTxData[ByteCounter + 3U] << 24) | 80027d2: 431a orrs r2, r3 ((uint32_t)pTxData[ByteCounter + 1U] << 8) | 80027d4: 697b ldr r3, [r7, #20] 80027d6: 3301 adds r3, #1 80027d8: 6879 ldr r1, [r7, #4] 80027da: 440b add r3, r1 80027dc: 781b ldrb r3, [r3, #0] 80027de: 021b lsls r3, r3, #8 ((uint32_t)pTxData[ByteCounter + 2U] << 16) | 80027e0: 4313 orrs r3, r2 (uint32_t)pTxData[ByteCounter]); 80027e2: 6879 ldr r1, [r7, #4] 80027e4: 697a ldr r2, [r7, #20] 80027e6: 440a add r2, r1 80027e8: 7812 ldrb r2, [r2, #0] ((uint32_t)pTxData[ByteCounter + 1U] << 8) | 80027ea: 431a orrs r2, r3 *TxAddress = (((uint32_t)pTxData[ByteCounter + 3U] << 24) | 80027ec: 69bb ldr r3, [r7, #24] 80027ee: 601a str r2, [r3, #0] TxAddress++; 80027f0: 69bb ldr r3, [r7, #24] 80027f2: 3304 adds r3, #4 80027f4: 61bb str r3, [r7, #24] for (ByteCounter = 0; ByteCounter < DLCtoBytes[pTxHeader->DataLength >> 16]; ByteCounter += 4U) 80027f6: 697b ldr r3, [r7, #20] 80027f8: 3304 adds r3, #4 80027fa: 617b str r3, [r7, #20] 80027fc: 68bb ldr r3, [r7, #8] 80027fe: 68db ldr r3, [r3, #12] 8002800: 0c1b lsrs r3, r3, #16 8002802: 4a06 ldr r2, [pc, #24] ; (800281c ) 8002804: 5cd3 ldrb r3, [r2, r3] 8002806: 461a mov r2, r3 8002808: 697b ldr r3, [r7, #20] 800280a: 4293 cmp r3, r2 800280c: d3d5 bcc.n 80027ba } } 800280e: bf00 nop 8002810: bf00 nop 8002812: 3724 adds r7, #36 ; 0x24 8002814: 46bd mov sp, r7 8002816: f85d 7b04 ldr.w r7, [sp], #4 800281a: 4770 bx lr 800281c: 0800575c .word 0x0800575c 08002820 : * This parameter shall be 32-bit aligned * * @retval HAL_StatusTypeDef HAL Status */ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t FlashAddress, uint32_t DataAddress) { 8002820: b580 push {r7, lr} 8002822: b08a sub sp, #40 ; 0x28 8002824: af00 add r7, sp, #0 8002826: 60f8 str r0, [r7, #12] 8002828: 60b9 str r1, [r7, #8] 800282a: 607a str r2, [r7, #4] HAL_StatusTypeDef status; __IO uint32_t *dest_addr = (__IO uint32_t *)FlashAddress; 800282c: 68bb ldr r3, [r7, #8] 800282e: 623b str r3, [r7, #32] __IO uint32_t *src_addr = (__IO uint32_t*)DataAddress; 8002830: 687b ldr r3, [r7, #4] 8002832: 61fb str r3, [r7, #28] uint32_t bank; uint8_t row_index = FLASH_NB_32BITWORD_IN_FLASHWORD; 8002834: 2308 movs r3, #8 8002836: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); assert_param(IS_FLASH_PROGRAM_ADDRESS(FlashAddress)); /* Process Locked */ __HAL_LOCK(&pFlash); 8002838: 4b40 ldr r3, [pc, #256] ; (800293c ) 800283a: 7d1b ldrb r3, [r3, #20] 800283c: 2b01 cmp r3, #1 800283e: d101 bne.n 8002844 8002840: 2302 movs r3, #2 8002842: e076 b.n 8002932 8002844: 4b3d ldr r3, [pc, #244] ; (800293c ) 8002846: 2201 movs r2, #1 8002848: 751a strb r2, [r3, #20] #if defined (FLASH_OPTCR_PG_OTP) if((IS_FLASH_PROGRAM_ADDRESS_BANK1(FlashAddress)) || (IS_FLASH_PROGRAM_ADDRESS_OTP(FlashAddress))) #else if(IS_FLASH_PROGRAM_ADDRESS_BANK1(FlashAddress)) 800284a: 68bb ldr r3, [r7, #8] 800284c: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000 8002850: d306 bcc.n 8002860 8002852: 68bb ldr r3, [r7, #8] 8002854: f1b3 6f01 cmp.w r3, #135266304 ; 0x8100000 8002858: d202 bcs.n 8002860 #endif /* FLASH_OPTCR_PG_OTP */ { bank = FLASH_BANK_1; 800285a: 2301 movs r3, #1 800285c: 61bb str r3, [r7, #24] 800285e: e00c b.n 800287a } #if defined (DUAL_BANK) else if(IS_FLASH_PROGRAM_ADDRESS_BANK2(FlashAddress)) 8002860: 68bb ldr r3, [r7, #8] 8002862: f1b3 6f01 cmp.w r3, #135266304 ; 0x8100000 8002866: d306 bcc.n 8002876 8002868: 68bb ldr r3, [r7, #8] 800286a: f1b3 6f02 cmp.w r3, #136314880 ; 0x8200000 800286e: d202 bcs.n 8002876 { bank = FLASH_BANK_2; 8002870: 2302 movs r3, #2 8002872: 61bb str r3, [r7, #24] 8002874: e001 b.n 800287a } #endif /* DUAL_BANK */ else { return HAL_ERROR; 8002876: 2301 movs r3, #1 8002878: e05b b.n 8002932 } /* Reset error code */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; 800287a: 4b30 ldr r3, [pc, #192] ; (800293c ) 800287c: 2200 movs r2, #0 800287e: 619a str r2, [r3, #24] /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, bank); 8002880: 69b9 ldr r1, [r7, #24] 8002882: f24c 3050 movw r0, #50000 ; 0xc350 8002886: f000 f8c1 bl 8002a0c 800288a: 4603 mov r3, r0 800288c: f887 3027 strb.w r3, [r7, #39] ; 0x27 if(status == HAL_OK) 8002890: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 8002894: 2b00 cmp r3, #0 8002896: d147 bne.n 8002928 { #if defined (DUAL_BANK) if(bank == FLASH_BANK_1) 8002898: 69bb ldr r3, [r7, #24] 800289a: 2b01 cmp r3, #1 800289c: d106 bne.n 80028ac } else #endif /* FLASH_OPTCR_PG_OTP */ { /* Set PG bit */ SET_BIT(FLASH->CR1, FLASH_CR_PG); 800289e: 4b28 ldr r3, [pc, #160] ; (8002940 ) 80028a0: 68db ldr r3, [r3, #12] 80028a2: 4a27 ldr r2, [pc, #156] ; (8002940 ) 80028a4: f043 0302 orr.w r3, r3, #2 80028a8: 60d3 str r3, [r2, #12] 80028aa: e007 b.n 80028bc } } else { /* Set PG bit */ SET_BIT(FLASH->CR2, FLASH_CR_PG); 80028ac: 4b24 ldr r3, [pc, #144] ; (8002940 ) 80028ae: f8d3 310c ldr.w r3, [r3, #268] ; 0x10c 80028b2: 4a23 ldr r2, [pc, #140] ; (8002940 ) 80028b4: f043 0302 orr.w r3, r3, #2 80028b8: f8c2 310c str.w r3, [r2, #268] ; 0x10c __ASM volatile ("isb 0xF":::"memory"); 80028bc: f3bf 8f6f isb sy } 80028c0: bf00 nop __ASM volatile ("dsb 0xF":::"memory"); 80028c2: f3bf 8f4f dsb sy } 80028c6: bf00 nop #endif /* FLASH_OPTCR_PG_OTP */ { /* Program the flash word */ do { *dest_addr = *src_addr; 80028c8: 69fb ldr r3, [r7, #28] 80028ca: 681a ldr r2, [r3, #0] 80028cc: 6a3b ldr r3, [r7, #32] 80028ce: 601a str r2, [r3, #0] dest_addr++; 80028d0: 6a3b ldr r3, [r7, #32] 80028d2: 3304 adds r3, #4 80028d4: 623b str r3, [r7, #32] src_addr++; 80028d6: 69fb ldr r3, [r7, #28] 80028d8: 3304 adds r3, #4 80028da: 61fb str r3, [r7, #28] row_index--; 80028dc: 7dfb ldrb r3, [r7, #23] 80028de: 3b01 subs r3, #1 80028e0: 75fb strb r3, [r7, #23] } while (row_index != 0U); 80028e2: 7dfb ldrb r3, [r7, #23] 80028e4: 2b00 cmp r3, #0 80028e6: d1ef bne.n 80028c8 __ASM volatile ("isb 0xF":::"memory"); 80028e8: f3bf 8f6f isb sy } 80028ec: bf00 nop __ASM volatile ("dsb 0xF":::"memory"); 80028ee: f3bf 8f4f dsb sy } 80028f2: bf00 nop __ISB(); __DSB(); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, bank); 80028f4: 69b9 ldr r1, [r7, #24] 80028f6: f24c 3050 movw r0, #50000 ; 0xc350 80028fa: f000 f887 bl 8002a0c 80028fe: 4603 mov r3, r0 8002900: f887 3027 strb.w r3, [r7, #39] ; 0x27 CLEAR_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OTP); } else #endif /* FLASH_OPTCR_PG_OTP */ { if(bank == FLASH_BANK_1) 8002904: 69bb ldr r3, [r7, #24] 8002906: 2b01 cmp r3, #1 8002908: d106 bne.n 8002918 { /* If the program operation is completed, disable the PG */ CLEAR_BIT(FLASH->CR1, FLASH_CR_PG); 800290a: 4b0d ldr r3, [pc, #52] ; (8002940 ) 800290c: 68db ldr r3, [r3, #12] 800290e: 4a0c ldr r2, [pc, #48] ; (8002940 ) 8002910: f023 0302 bic.w r3, r3, #2 8002914: 60d3 str r3, [r2, #12] 8002916: e007 b.n 8002928 } else { /* If the program operation is completed, disable the PG */ CLEAR_BIT(FLASH->CR2, FLASH_CR_PG); 8002918: 4b09 ldr r3, [pc, #36] ; (8002940 ) 800291a: f8d3 310c ldr.w r3, [r3, #268] ; 0x10c 800291e: 4a08 ldr r2, [pc, #32] ; (8002940 ) 8002920: f023 0302 bic.w r3, r3, #2 8002924: f8c2 310c str.w r3, [r2, #268] ; 0x10c } #endif /* DUAL_BANK */ } /* Process Unlocked */ __HAL_UNLOCK(&pFlash); 8002928: 4b04 ldr r3, [pc, #16] ; (800293c ) 800292a: 2200 movs r2, #0 800292c: 751a strb r2, [r3, #20] return status; 800292e: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 } 8002932: 4618 mov r0, r3 8002934: 3728 adds r7, #40 ; 0x28 8002936: 46bd mov sp, r7 8002938: bd80 pop {r7, pc} 800293a: bf00 nop 800293c: 24000364 .word 0x24000364 8002940: 52002000 .word 0x52002000 08002944 : /** * @brief Unlock the FLASH control registers access * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASH_Unlock(void) { 8002944: b480 push {r7} 8002946: af00 add r7, sp, #0 if(READ_BIT(FLASH->CR1, FLASH_CR_LOCK) != 0U) 8002948: 4b18 ldr r3, [pc, #96] ; (80029ac ) 800294a: 68db ldr r3, [r3, #12] 800294c: f003 0301 and.w r3, r3, #1 8002950: 2b00 cmp r3, #0 8002952: d00d beq.n 8002970 { /* Authorize the FLASH Bank1 Registers access */ WRITE_REG(FLASH->KEYR1, FLASH_KEY1); 8002954: 4b15 ldr r3, [pc, #84] ; (80029ac ) 8002956: 4a16 ldr r2, [pc, #88] ; (80029b0 ) 8002958: 605a str r2, [r3, #4] WRITE_REG(FLASH->KEYR1, FLASH_KEY2); 800295a: 4b14 ldr r3, [pc, #80] ; (80029ac ) 800295c: 4a15 ldr r2, [pc, #84] ; (80029b4 ) 800295e: 605a str r2, [r3, #4] /* Verify Flash Bank1 is unlocked */ if (READ_BIT(FLASH->CR1, FLASH_CR_LOCK) != 0U) 8002960: 4b12 ldr r3, [pc, #72] ; (80029ac ) 8002962: 68db ldr r3, [r3, #12] 8002964: f003 0301 and.w r3, r3, #1 8002968: 2b00 cmp r3, #0 800296a: d001 beq.n 8002970 { return HAL_ERROR; 800296c: 2301 movs r3, #1 800296e: e018 b.n 80029a2 } } #if defined (DUAL_BANK) if(READ_BIT(FLASH->CR2, FLASH_CR_LOCK) != 0U) 8002970: 4b0e ldr r3, [pc, #56] ; (80029ac ) 8002972: f8d3 310c ldr.w r3, [r3, #268] ; 0x10c 8002976: f003 0301 and.w r3, r3, #1 800297a: 2b00 cmp r3, #0 800297c: d010 beq.n 80029a0 { /* Authorize the FLASH Bank2 Registers access */ WRITE_REG(FLASH->KEYR2, FLASH_KEY1); 800297e: 4b0b ldr r3, [pc, #44] ; (80029ac ) 8002980: 4a0b ldr r2, [pc, #44] ; (80029b0 ) 8002982: f8c3 2104 str.w r2, [r3, #260] ; 0x104 WRITE_REG(FLASH->KEYR2, FLASH_KEY2); 8002986: 4b09 ldr r3, [pc, #36] ; (80029ac ) 8002988: 4a0a ldr r2, [pc, #40] ; (80029b4 ) 800298a: f8c3 2104 str.w r2, [r3, #260] ; 0x104 /* Verify Flash Bank2 is unlocked */ if (READ_BIT(FLASH->CR2, FLASH_CR_LOCK) != 0U) 800298e: 4b07 ldr r3, [pc, #28] ; (80029ac ) 8002990: f8d3 310c ldr.w r3, [r3, #268] ; 0x10c 8002994: f003 0301 and.w r3, r3, #1 8002998: 2b00 cmp r3, #0 800299a: d001 beq.n 80029a0 { return HAL_ERROR; 800299c: 2301 movs r3, #1 800299e: e000 b.n 80029a2 } } #endif /* DUAL_BANK */ return HAL_OK; 80029a0: 2300 movs r3, #0 } 80029a2: 4618 mov r0, r3 80029a4: 46bd mov sp, r7 80029a6: f85d 7b04 ldr.w r7, [sp], #4 80029aa: 4770 bx lr 80029ac: 52002000 .word 0x52002000 80029b0: 45670123 .word 0x45670123 80029b4: cdef89ab .word 0xcdef89ab 080029b8 : /** * @brief Locks the FLASH control registers access * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASH_Lock(void) { 80029b8: b480 push {r7} 80029ba: af00 add r7, sp, #0 /* Set the LOCK Bit to lock the FLASH Bank1 Control Register access */ SET_BIT(FLASH->CR1, FLASH_CR_LOCK); 80029bc: 4b12 ldr r3, [pc, #72] ; (8002a08 ) 80029be: 68db ldr r3, [r3, #12] 80029c0: 4a11 ldr r2, [pc, #68] ; (8002a08 ) 80029c2: f043 0301 orr.w r3, r3, #1 80029c6: 60d3 str r3, [r2, #12] /* Verify Flash Bank1 is locked */ if (READ_BIT(FLASH->CR1, FLASH_CR_LOCK) == 0U) 80029c8: 4b0f ldr r3, [pc, #60] ; (8002a08 ) 80029ca: 68db ldr r3, [r3, #12] 80029cc: f003 0301 and.w r3, r3, #1 80029d0: 2b00 cmp r3, #0 80029d2: d101 bne.n 80029d8 { return HAL_ERROR; 80029d4: 2301 movs r3, #1 80029d6: e011 b.n 80029fc } #if defined (DUAL_BANK) /* Set the LOCK Bit to lock the FLASH Bank2 Control Register access */ SET_BIT(FLASH->CR2, FLASH_CR_LOCK); 80029d8: 4b0b ldr r3, [pc, #44] ; (8002a08 ) 80029da: f8d3 310c ldr.w r3, [r3, #268] ; 0x10c 80029de: 4a0a ldr r2, [pc, #40] ; (8002a08 ) 80029e0: f043 0301 orr.w r3, r3, #1 80029e4: f8c2 310c str.w r3, [r2, #268] ; 0x10c /* Verify Flash Bank2 is locked */ if (READ_BIT(FLASH->CR2, FLASH_CR_LOCK) == 0U) 80029e8: 4b07 ldr r3, [pc, #28] ; (8002a08 ) 80029ea: f8d3 310c ldr.w r3, [r3, #268] ; 0x10c 80029ee: f003 0301 and.w r3, r3, #1 80029f2: 2b00 cmp r3, #0 80029f4: d101 bne.n 80029fa { return HAL_ERROR; 80029f6: 2301 movs r3, #1 80029f8: e000 b.n 80029fc } #endif /* DUAL_BANK */ return HAL_OK; 80029fa: 2300 movs r3, #0 } 80029fc: 4618 mov r0, r3 80029fe: 46bd mov sp, r7 8002a00: f85d 7b04 ldr.w r7, [sp], #4 8002a04: 4770 bx lr 8002a06: bf00 nop 8002a08: 52002000 .word 0x52002000 08002a0c : * @param Timeout maximum flash operation timeout * @param Bank flash FLASH_BANK_1 or FLASH_BANK_2 * @retval HAL_StatusTypeDef HAL Status */ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout, uint32_t Bank) { 8002a0c: b580 push {r7, lr} 8002a0e: b086 sub sp, #24 8002a10: af00 add r7, sp, #0 8002a12: 6078 str r0, [r7, #4] 8002a14: 6039 str r1, [r7, #0] /* Wait for the FLASH operation to complete by polling on QW flag to be reset. Even if the FLASH operation fails, the QW flag will be reset and an error flag will be set */ uint32_t bsyflag = FLASH_FLAG_QW_BANK1; 8002a16: 2304 movs r3, #4 8002a18: 617b str r3, [r7, #20] uint32_t errorflag = 0; 8002a1a: 2300 movs r3, #0 8002a1c: 613b str r3, [r7, #16] uint32_t tickstart = HAL_GetTick(); 8002a1e: f7fe fc27 bl 8001270 8002a22: 60f8 str r0, [r7, #12] assert_param(IS_FLASH_BANK_EXCLUSIVE(Bank)); #if defined (DUAL_BANK) if (Bank == FLASH_BANK_2) 8002a24: 683b ldr r3, [r7, #0] 8002a26: 2b02 cmp r3, #2 8002a28: d113 bne.n 8002a52 { /* Select bsyflag depending on Bank */ bsyflag = FLASH_FLAG_QW_BANK2; 8002a2a: 4b41 ldr r3, [pc, #260] ; (8002b30 ) 8002a2c: 617b str r3, [r7, #20] } #endif /* DUAL_BANK */ while(__HAL_FLASH_GET_FLAG(bsyflag)) 8002a2e: e010 b.n 8002a52 { if(Timeout != HAL_MAX_DELAY) 8002a30: 687b ldr r3, [r7, #4] 8002a32: f1b3 3fff cmp.w r3, #4294967295 8002a36: d00c beq.n 8002a52 { if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) 8002a38: f7fe fc1a bl 8001270 8002a3c: 4602 mov r2, r0 8002a3e: 68fb ldr r3, [r7, #12] 8002a40: 1ad3 subs r3, r2, r3 8002a42: 687a ldr r2, [r7, #4] 8002a44: 429a cmp r2, r3 8002a46: d302 bcc.n 8002a4e 8002a48: 687b ldr r3, [r7, #4] 8002a4a: 2b00 cmp r3, #0 8002a4c: d101 bne.n 8002a52 { return HAL_TIMEOUT; 8002a4e: 2303 movs r3, #3 8002a50: e06a b.n 8002b28 while(__HAL_FLASH_GET_FLAG(bsyflag)) 8002a52: 697a ldr r2, [r7, #20] 8002a54: 4b37 ldr r3, [pc, #220] ; (8002b34 ) 8002a56: 4013 ands r3, r2 8002a58: 697a ldr r2, [r7, #20] 8002a5a: 429a cmp r2, r3 8002a5c: d10a bne.n 8002a74 8002a5e: 4b36 ldr r3, [pc, #216] ; (8002b38 ) 8002a60: 691a ldr r2, [r3, #16] 8002a62: 697b ldr r3, [r7, #20] 8002a64: 4013 ands r3, r2 8002a66: 697a ldr r2, [r7, #20] 8002a68: 429a cmp r2, r3 8002a6a: bf0c ite eq 8002a6c: 2301 moveq r3, #1 8002a6e: 2300 movne r3, #0 8002a70: b2db uxtb r3, r3 8002a72: e00c b.n 8002a8e 8002a74: 4b30 ldr r3, [pc, #192] ; (8002b38 ) 8002a76: f8d3 3110 ldr.w r3, [r3, #272] ; 0x110 8002a7a: 43da mvns r2, r3 8002a7c: 697b ldr r3, [r7, #20] 8002a7e: 4013 ands r3, r2 8002a80: f023 4300 bic.w r3, r3, #2147483648 ; 0x80000000 8002a84: 2b00 cmp r3, #0 8002a86: bf0c ite eq 8002a88: 2301 moveq r3, #1 8002a8a: 2300 movne r3, #0 8002a8c: b2db uxtb r3, r3 8002a8e: 2b00 cmp r3, #0 8002a90: d1ce bne.n 8002a30 } } } /* Get Error Flags */ if (Bank == FLASH_BANK_1) 8002a92: 683b ldr r3, [r7, #0] 8002a94: 2b01 cmp r3, #1 8002a96: d105 bne.n 8002aa4 { errorflag = FLASH->SR1 & FLASH_FLAG_ALL_ERRORS_BANK1; 8002a98: 4b27 ldr r3, [pc, #156] ; (8002b38 ) 8002a9a: 691a ldr r2, [r3, #16] 8002a9c: 4b27 ldr r3, [pc, #156] ; (8002b3c ) 8002a9e: 4013 ands r3, r2 8002aa0: 613b str r3, [r7, #16] 8002aa2: e007 b.n 8002ab4 } #if defined (DUAL_BANK) else { errorflag = (FLASH->SR2 & FLASH_FLAG_ALL_ERRORS_BANK2) | 0x80000000U; 8002aa4: 4b24 ldr r3, [pc, #144] ; (8002b38 ) 8002aa6: f8d3 2110 ldr.w r2, [r3, #272] ; 0x110 8002aaa: 4b24 ldr r3, [pc, #144] ; (8002b3c ) 8002aac: 4013 ands r3, r2 8002aae: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000 8002ab2: 613b str r3, [r7, #16] } #endif /* DUAL_BANK */ /* In case of error reported in Flash SR1 or SR2 register */ if((errorflag & 0x7FFFFFFFU) != 0U) 8002ab4: 693b ldr r3, [r7, #16] 8002ab6: f023 4300 bic.w r3, r3, #2147483648 ; 0x80000000 8002aba: 2b00 cmp r3, #0 8002abc: d017 beq.n 8002aee { /*Save the error code*/ pFlash.ErrorCode |= errorflag; 8002abe: 4b20 ldr r3, [pc, #128] ; (8002b40 ) 8002ac0: 699a ldr r2, [r3, #24] 8002ac2: 693b ldr r3, [r7, #16] 8002ac4: 4313 orrs r3, r2 8002ac6: 4a1e ldr r2, [pc, #120] ; (8002b40 ) 8002ac8: 6193 str r3, [r2, #24] /* Clear error programming flags */ __HAL_FLASH_CLEAR_FLAG(errorflag); 8002aca: 693a ldr r2, [r7, #16] 8002acc: 4b19 ldr r3, [pc, #100] ; (8002b34 ) 8002ace: 4013 ands r3, r2 8002ad0: 693a ldr r2, [r7, #16] 8002ad2: 429a cmp r2, r3 8002ad4: d103 bne.n 8002ade 8002ad6: 4a18 ldr r2, [pc, #96] ; (8002b38 ) 8002ad8: 693b ldr r3, [r7, #16] 8002ada: 6153 str r3, [r2, #20] 8002adc: e005 b.n 8002aea 8002ade: 4a16 ldr r2, [pc, #88] ; (8002b38 ) 8002ae0: 693b ldr r3, [r7, #16] 8002ae2: f023 4300 bic.w r3, r3, #2147483648 ; 0x80000000 8002ae6: f8c2 3114 str.w r3, [r2, #276] ; 0x114 return HAL_ERROR; 8002aea: 2301 movs r3, #1 8002aec: e01c b.n 8002b28 } /* Check FLASH End of Operation flag */ if(Bank == FLASH_BANK_1) 8002aee: 683b ldr r3, [r7, #0] 8002af0: 2b01 cmp r3, #1 8002af2: d10b bne.n 8002b0c { if (__HAL_FLASH_GET_FLAG_BANK1(FLASH_FLAG_EOP_BANK1)) 8002af4: 4b10 ldr r3, [pc, #64] ; (8002b38 ) 8002af6: 691b ldr r3, [r3, #16] 8002af8: f403 3380 and.w r3, r3, #65536 ; 0x10000 8002afc: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8002b00: d111 bne.n 8002b26 { /* Clear FLASH End of Operation pending bit */ __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_EOP_BANK1); 8002b02: 4b0d ldr r3, [pc, #52] ; (8002b38 ) 8002b04: f44f 3280 mov.w r2, #65536 ; 0x10000 8002b08: 615a str r2, [r3, #20] 8002b0a: e00c b.n 8002b26 } } #if defined (DUAL_BANK) else { if (__HAL_FLASH_GET_FLAG_BANK2(FLASH_FLAG_EOP_BANK2)) 8002b0c: 4b0a ldr r3, [pc, #40] ; (8002b38 ) 8002b0e: f8d3 3110 ldr.w r3, [r3, #272] ; 0x110 8002b12: f403 3380 and.w r3, r3, #65536 ; 0x10000 8002b16: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8002b1a: d104 bne.n 8002b26 { /* Clear FLASH End of Operation pending bit */ __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_EOP_BANK2); 8002b1c: 4b06 ldr r3, [pc, #24] ; (8002b38 ) 8002b1e: f44f 3280 mov.w r2, #65536 ; 0x10000 8002b22: f8c3 2114 str.w r2, [r3, #276] ; 0x114 } } #endif /* DUAL_BANK */ return HAL_OK; 8002b26: 2300 movs r3, #0 } 8002b28: 4618 mov r0, r3 8002b2a: 3718 adds r7, #24 8002b2c: 46bd mov sp, r7 8002b2e: bd80 pop {r7, pc} 8002b30: 80000004 .word 0x80000004 8002b34: 1fef000f .word 0x1fef000f 8002b38: 52002000 .word 0x52002000 8002b3c: 17ee0000 .word 0x17ee0000 8002b40: 24000364 .word 0x24000364 08002b44 : * the sectors have been correctly erased) * * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError) { 8002b44: b580 push {r7, lr} 8002b46: b084 sub sp, #16 8002b48: af00 add r7, sp, #0 8002b4a: 6078 str r0, [r7, #4] 8002b4c: 6039 str r1, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 8002b4e: 2300 movs r3, #0 8002b50: 73fb strb r3, [r7, #15] /* Check the parameters */ assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); assert_param(IS_FLASH_BANK(pEraseInit->Banks)); /* Process Locked */ __HAL_LOCK(&pFlash); 8002b52: 4b5e ldr r3, [pc, #376] ; (8002ccc ) 8002b54: 7d1b ldrb r3, [r3, #20] 8002b56: 2b01 cmp r3, #1 8002b58: d101 bne.n 8002b5e 8002b5a: 2302 movs r3, #2 8002b5c: e0b2 b.n 8002cc4 8002b5e: 4b5b ldr r3, [pc, #364] ; (8002ccc ) 8002b60: 2201 movs r2, #1 8002b62: 751a strb r2, [r3, #20] /* Reset error code */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; 8002b64: 4b59 ldr r3, [pc, #356] ; (8002ccc ) 8002b66: 2200 movs r2, #0 8002b68: 619a str r2, [r3, #24] /* Wait for last operation to be completed on Bank1 */ if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1) 8002b6a: 687b ldr r3, [r7, #4] 8002b6c: 685b ldr r3, [r3, #4] 8002b6e: f003 0301 and.w r3, r3, #1 8002b72: 2b00 cmp r3, #0 8002b74: d009 beq.n 8002b8a { if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK) 8002b76: 2101 movs r1, #1 8002b78: f24c 3050 movw r0, #50000 ; 0xc350 8002b7c: f7ff ff46 bl 8002a0c 8002b80: 4603 mov r3, r0 8002b82: 2b00 cmp r3, #0 8002b84: d001 beq.n 8002b8a { status = HAL_ERROR; 8002b86: 2301 movs r3, #1 8002b88: 73fb strb r3, [r7, #15] } } #if defined (DUAL_BANK) /* Wait for last operation to be completed on Bank2 */ if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2) 8002b8a: 687b ldr r3, [r7, #4] 8002b8c: 685b ldr r3, [r3, #4] 8002b8e: f003 0302 and.w r3, r3, #2 8002b92: 2b00 cmp r3, #0 8002b94: d009 beq.n 8002baa { if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK) 8002b96: 2102 movs r1, #2 8002b98: f24c 3050 movw r0, #50000 ; 0xc350 8002b9c: f7ff ff36 bl 8002a0c 8002ba0: 4603 mov r3, r0 8002ba2: 2b00 cmp r3, #0 8002ba4: d001 beq.n 8002baa { status = HAL_ERROR; 8002ba6: 2301 movs r3, #1 8002ba8: 73fb strb r3, [r7, #15] } } #endif /* DUAL_BANK */ if(status == HAL_OK) 8002baa: 7bfb ldrb r3, [r7, #15] 8002bac: 2b00 cmp r3, #0 8002bae: f040 8085 bne.w 8002cbc { if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) 8002bb2: 687b ldr r3, [r7, #4] 8002bb4: 681b ldr r3, [r3, #0] 8002bb6: 2b01 cmp r3, #1 8002bb8: d136 bne.n 8002c28 { /* Mass erase to be done */ FLASH_MassErase(pEraseInit->VoltageRange, pEraseInit->Banks); 8002bba: 687b ldr r3, [r7, #4] 8002bbc: 691a ldr r2, [r3, #16] 8002bbe: 687b ldr r3, [r7, #4] 8002bc0: 685b ldr r3, [r3, #4] 8002bc2: 4619 mov r1, r3 8002bc4: 4610 mov r0, r2 8002bc6: f000 f887 bl 8002cd8 /* Wait for last operation to be completed on Bank 1 */ if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1) 8002bca: 687b ldr r3, [r7, #4] 8002bcc: 685b ldr r3, [r3, #4] 8002bce: f003 0301 and.w r3, r3, #1 8002bd2: 2b00 cmp r3, #0 8002bd4: d00f beq.n 8002bf6 { if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK) 8002bd6: 2101 movs r1, #1 8002bd8: f24c 3050 movw r0, #50000 ; 0xc350 8002bdc: f7ff ff16 bl 8002a0c 8002be0: 4603 mov r3, r0 8002be2: 2b00 cmp r3, #0 8002be4: d001 beq.n 8002bea { status = HAL_ERROR; 8002be6: 2301 movs r3, #1 8002be8: 73fb strb r3, [r7, #15] } /* if the erase operation is completed, disable the Bank1 BER Bit */ FLASH->CR1 &= (~FLASH_CR_BER); 8002bea: 4b39 ldr r3, [pc, #228] ; (8002cd0 ) 8002bec: 68db ldr r3, [r3, #12] 8002bee: 4a38 ldr r2, [pc, #224] ; (8002cd0 ) 8002bf0: f023 0308 bic.w r3, r3, #8 8002bf4: 60d3 str r3, [r2, #12] } #if defined (DUAL_BANK) /* Wait for last operation to be completed on Bank 2 */ if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2) 8002bf6: 687b ldr r3, [r7, #4] 8002bf8: 685b ldr r3, [r3, #4] 8002bfa: f003 0302 and.w r3, r3, #2 8002bfe: 2b00 cmp r3, #0 8002c00: d05c beq.n 8002cbc { if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK) 8002c02: 2102 movs r1, #2 8002c04: f24c 3050 movw r0, #50000 ; 0xc350 8002c08: f7ff ff00 bl 8002a0c 8002c0c: 4603 mov r3, r0 8002c0e: 2b00 cmp r3, #0 8002c10: d001 beq.n 8002c16 { status = HAL_ERROR; 8002c12: 2301 movs r3, #1 8002c14: 73fb strb r3, [r7, #15] } /* if the erase operation is completed, disable the Bank2 BER Bit */ FLASH->CR2 &= (~FLASH_CR_BER); 8002c16: 4b2e ldr r3, [pc, #184] ; (8002cd0 ) 8002c18: f8d3 310c ldr.w r3, [r3, #268] ; 0x10c 8002c1c: 4a2c ldr r2, [pc, #176] ; (8002cd0 ) 8002c1e: f023 0308 bic.w r3, r3, #8 8002c22: f8c2 310c str.w r3, [r2, #268] ; 0x10c 8002c26: e049 b.n 8002cbc #endif /* DUAL_BANK */ } else { /*Initialization of SectorError variable*/ *SectorError = 0xFFFFFFFFU; 8002c28: 683b ldr r3, [r7, #0] 8002c2a: f04f 32ff mov.w r2, #4294967295 8002c2e: 601a str r2, [r3, #0] /* Erase by sector by sector to be done*/ for(sector_index = pEraseInit->Sector; sector_index < (pEraseInit->NbSectors + pEraseInit->Sector); sector_index++) 8002c30: 687b ldr r3, [r7, #4] 8002c32: 689b ldr r3, [r3, #8] 8002c34: 60bb str r3, [r7, #8] 8002c36: e039 b.n 8002cac { FLASH_Erase_Sector(sector_index, pEraseInit->Banks, pEraseInit->VoltageRange); 8002c38: 687b ldr r3, [r7, #4] 8002c3a: 6859 ldr r1, [r3, #4] 8002c3c: 687b ldr r3, [r7, #4] 8002c3e: 691b ldr r3, [r3, #16] 8002c40: 461a mov r2, r3 8002c42: 68b8 ldr r0, [r7, #8] 8002c44: f000 f8b2 bl 8002dac if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1) 8002c48: 687b ldr r3, [r7, #4] 8002c4a: 685b ldr r3, [r3, #4] 8002c4c: f003 0301 and.w r3, r3, #1 8002c50: 2b00 cmp r3, #0 8002c52: d00c beq.n 8002c6e { /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1); 8002c54: 2101 movs r1, #1 8002c56: f24c 3050 movw r0, #50000 ; 0xc350 8002c5a: f7ff fed7 bl 8002a0c 8002c5e: 4603 mov r3, r0 8002c60: 73fb strb r3, [r7, #15] /* If the erase operation is completed, disable the SER Bit */ FLASH->CR1 &= (~(FLASH_CR_SER | FLASH_CR_SNB)); 8002c62: 4b1b ldr r3, [pc, #108] ; (8002cd0 ) 8002c64: 68da ldr r2, [r3, #12] 8002c66: 491a ldr r1, [pc, #104] ; (8002cd0 ) 8002c68: 4b1a ldr r3, [pc, #104] ; (8002cd4 ) 8002c6a: 4013 ands r3, r2 8002c6c: 60cb str r3, [r1, #12] } #if defined (DUAL_BANK) if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2) 8002c6e: 687b ldr r3, [r7, #4] 8002c70: 685b ldr r3, [r3, #4] 8002c72: f003 0302 and.w r3, r3, #2 8002c76: 2b00 cmp r3, #0 8002c78: d00e beq.n 8002c98 { /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2); 8002c7a: 2102 movs r1, #2 8002c7c: f24c 3050 movw r0, #50000 ; 0xc350 8002c80: f7ff fec4 bl 8002a0c 8002c84: 4603 mov r3, r0 8002c86: 73fb strb r3, [r7, #15] /* If the erase operation is completed, disable the SER Bit */ FLASH->CR2 &= (~(FLASH_CR_SER | FLASH_CR_SNB)); 8002c88: 4b11 ldr r3, [pc, #68] ; (8002cd0 ) 8002c8a: f8d3 210c ldr.w r2, [r3, #268] ; 0x10c 8002c8e: 4910 ldr r1, [pc, #64] ; (8002cd0 ) 8002c90: 4b10 ldr r3, [pc, #64] ; (8002cd4 ) 8002c92: 4013 ands r3, r2 8002c94: f8c1 310c str.w r3, [r1, #268] ; 0x10c } #endif /* DUAL_BANK */ if(status != HAL_OK) 8002c98: 7bfb ldrb r3, [r7, #15] 8002c9a: 2b00 cmp r3, #0 8002c9c: d003 beq.n 8002ca6 { /* In case of error, stop erase procedure and return the faulty sector */ *SectorError = sector_index; 8002c9e: 683b ldr r3, [r7, #0] 8002ca0: 68ba ldr r2, [r7, #8] 8002ca2: 601a str r2, [r3, #0] break; 8002ca4: e00a b.n 8002cbc for(sector_index = pEraseInit->Sector; sector_index < (pEraseInit->NbSectors + pEraseInit->Sector); sector_index++) 8002ca6: 68bb ldr r3, [r7, #8] 8002ca8: 3301 adds r3, #1 8002caa: 60bb str r3, [r7, #8] 8002cac: 687b ldr r3, [r7, #4] 8002cae: 68da ldr r2, [r3, #12] 8002cb0: 687b ldr r3, [r7, #4] 8002cb2: 689b ldr r3, [r3, #8] 8002cb4: 4413 add r3, r2 8002cb6: 68ba ldr r2, [r7, #8] 8002cb8: 429a cmp r2, r3 8002cba: d3bd bcc.n 8002c38 } } } /* Process Unlocked */ __HAL_UNLOCK(&pFlash); 8002cbc: 4b03 ldr r3, [pc, #12] ; (8002ccc ) 8002cbe: 2200 movs r2, #0 8002cc0: 751a strb r2, [r3, #20] return status; 8002cc2: 7bfb ldrb r3, [r7, #15] } 8002cc4: 4618 mov r0, r3 8002cc6: 3710 adds r7, #16 8002cc8: 46bd mov sp, r7 8002cca: bd80 pop {r7, pc} 8002ccc: 24000364 .word 0x24000364 8002cd0: 52002000 .word 0x52002000 8002cd4: fffff8fb .word 0xfffff8fb 08002cd8 : * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased * * @retval HAL Status */ static void FLASH_MassErase(uint32_t VoltageRange, uint32_t Banks) { 8002cd8: b480 push {r7} 8002cda: b083 sub sp, #12 8002cdc: af00 add r7, sp, #0 8002cde: 6078 str r0, [r7, #4] 8002ce0: 6039 str r1, [r7, #0] #endif /* FLASH_CR_PSIZE */ assert_param(IS_FLASH_BANK(Banks)); #if defined (DUAL_BANK) /* Flash Mass Erase */ if((Banks & FLASH_BANK_BOTH) == FLASH_BANK_BOTH) 8002ce2: 683b ldr r3, [r7, #0] 8002ce4: f003 0303 and.w r3, r3, #3 8002ce8: 2b03 cmp r3, #3 8002cea: d122 bne.n 8002d32 { #if defined (FLASH_CR_PSIZE) /* Reset Program/erase VoltageRange for Bank1 and Bank2 */ FLASH->CR1 &= (~FLASH_CR_PSIZE); 8002cec: 4b2e ldr r3, [pc, #184] ; (8002da8 ) 8002cee: 68db ldr r3, [r3, #12] 8002cf0: 4a2d ldr r2, [pc, #180] ; (8002da8 ) 8002cf2: f023 0330 bic.w r3, r3, #48 ; 0x30 8002cf6: 60d3 str r3, [r2, #12] FLASH->CR2 &= (~FLASH_CR_PSIZE); 8002cf8: 4b2b ldr r3, [pc, #172] ; (8002da8 ) 8002cfa: f8d3 310c ldr.w r3, [r3, #268] ; 0x10c 8002cfe: 4a2a ldr r2, [pc, #168] ; (8002da8 ) 8002d00: f023 0330 bic.w r3, r3, #48 ; 0x30 8002d04: f8c2 310c str.w r3, [r2, #268] ; 0x10c /* Set voltage range */ FLASH->CR1 |= VoltageRange; 8002d08: 4b27 ldr r3, [pc, #156] ; (8002da8 ) 8002d0a: 68da ldr r2, [r3, #12] 8002d0c: 4926 ldr r1, [pc, #152] ; (8002da8 ) 8002d0e: 687b ldr r3, [r7, #4] 8002d10: 4313 orrs r3, r2 8002d12: 60cb str r3, [r1, #12] FLASH->CR2 |= VoltageRange; 8002d14: 4b24 ldr r3, [pc, #144] ; (8002da8 ) 8002d16: f8d3 210c ldr.w r2, [r3, #268] ; 0x10c 8002d1a: 4923 ldr r1, [pc, #140] ; (8002da8 ) 8002d1c: 687b ldr r3, [r7, #4] 8002d1e: 4313 orrs r3, r2 8002d20: f8c1 310c str.w r3, [r1, #268] ; 0x10c #endif /* FLASH_CR_PSIZE */ /* Set Mass Erase Bit */ FLASH->OPTCR |= FLASH_OPTCR_MER; 8002d24: 4b20 ldr r3, [pc, #128] ; (8002da8 ) 8002d26: 699b ldr r3, [r3, #24] 8002d28: 4a1f ldr r2, [pc, #124] ; (8002da8 ) 8002d2a: f043 0310 orr.w r3, r3, #16 8002d2e: 6193 str r3, [r2, #24] /* Erase Bank2 */ FLASH->CR2 |= (FLASH_CR_BER | FLASH_CR_START); } #endif /* DUAL_BANK */ } } 8002d30: e033 b.n 8002d9a if((Banks & FLASH_BANK_1) == FLASH_BANK_1) 8002d32: 683b ldr r3, [r7, #0] 8002d34: f003 0301 and.w r3, r3, #1 8002d38: 2b00 cmp r3, #0 8002d3a: d011 beq.n 8002d60 FLASH->CR1 &= (~FLASH_CR_PSIZE); 8002d3c: 4b1a ldr r3, [pc, #104] ; (8002da8 ) 8002d3e: 68db ldr r3, [r3, #12] 8002d40: 4a19 ldr r2, [pc, #100] ; (8002da8 ) 8002d42: f023 0330 bic.w r3, r3, #48 ; 0x30 8002d46: 60d3 str r3, [r2, #12] FLASH->CR1 |= VoltageRange; 8002d48: 4b17 ldr r3, [pc, #92] ; (8002da8 ) 8002d4a: 68da ldr r2, [r3, #12] 8002d4c: 4916 ldr r1, [pc, #88] ; (8002da8 ) 8002d4e: 687b ldr r3, [r7, #4] 8002d50: 4313 orrs r3, r2 8002d52: 60cb str r3, [r1, #12] FLASH->CR1 |= (FLASH_CR_BER | FLASH_CR_START); 8002d54: 4b14 ldr r3, [pc, #80] ; (8002da8 ) 8002d56: 68db ldr r3, [r3, #12] 8002d58: 4a13 ldr r2, [pc, #76] ; (8002da8 ) 8002d5a: f043 0388 orr.w r3, r3, #136 ; 0x88 8002d5e: 60d3 str r3, [r2, #12] if((Banks & FLASH_BANK_2) == FLASH_BANK_2) 8002d60: 683b ldr r3, [r7, #0] 8002d62: f003 0302 and.w r3, r3, #2 8002d66: 2b00 cmp r3, #0 8002d68: d017 beq.n 8002d9a FLASH->CR2 &= (~FLASH_CR_PSIZE); 8002d6a: 4b0f ldr r3, [pc, #60] ; (8002da8 ) 8002d6c: f8d3 310c ldr.w r3, [r3, #268] ; 0x10c 8002d70: 4a0d ldr r2, [pc, #52] ; (8002da8 ) 8002d72: f023 0330 bic.w r3, r3, #48 ; 0x30 8002d76: f8c2 310c str.w r3, [r2, #268] ; 0x10c FLASH->CR2 |= VoltageRange; 8002d7a: 4b0b ldr r3, [pc, #44] ; (8002da8 ) 8002d7c: f8d3 210c ldr.w r2, [r3, #268] ; 0x10c 8002d80: 4909 ldr r1, [pc, #36] ; (8002da8 ) 8002d82: 687b ldr r3, [r7, #4] 8002d84: 4313 orrs r3, r2 8002d86: f8c1 310c str.w r3, [r1, #268] ; 0x10c FLASH->CR2 |= (FLASH_CR_BER | FLASH_CR_START); 8002d8a: 4b07 ldr r3, [pc, #28] ; (8002da8 ) 8002d8c: f8d3 310c ldr.w r3, [r3, #268] ; 0x10c 8002d90: 4a05 ldr r2, [pc, #20] ; (8002da8 ) 8002d92: f043 0388 orr.w r3, r3, #136 ; 0x88 8002d96: f8c2 310c str.w r3, [r2, #268] ; 0x10c } 8002d9a: bf00 nop 8002d9c: 370c adds r7, #12 8002d9e: 46bd mov sp, r7 8002da0: f85d 7b04 ldr.w r7, [sp], #4 8002da4: 4770 bx lr 8002da6: bf00 nop 8002da8: 52002000 .word 0x52002000 08002dac : * @arg FLASH_VOLTAGE_RANGE_4 : Flash program/erase by 64 bits * * @retval None */ void FLASH_Erase_Sector(uint32_t Sector, uint32_t Banks, uint32_t VoltageRange) { 8002dac: b480 push {r7} 8002dae: b085 sub sp, #20 8002db0: af00 add r7, sp, #0 8002db2: 60f8 str r0, [r7, #12] 8002db4: 60b9 str r1, [r7, #8] 8002db6: 607a str r2, [r7, #4] assert_param(IS_VOLTAGERANGE(VoltageRange)); #else UNUSED(VoltageRange); #endif /* FLASH_CR_PSIZE */ if((Banks & FLASH_BANK_1) == FLASH_BANK_1) 8002db8: 68bb ldr r3, [r7, #8] 8002dba: f003 0301 and.w r3, r3, #1 8002dbe: 2b00 cmp r3, #0 8002dc0: d010 beq.n 8002de4 { #if defined (FLASH_CR_PSIZE) /* Reset Program/erase VoltageRange and Sector Number for Bank1 */ FLASH->CR1 &= ~(FLASH_CR_PSIZE | FLASH_CR_SNB); 8002dc2: 4b18 ldr r3, [pc, #96] ; (8002e24 ) 8002dc4: 68db ldr r3, [r3, #12] 8002dc6: 4a17 ldr r2, [pc, #92] ; (8002e24 ) 8002dc8: f423 63e6 bic.w r3, r3, #1840 ; 0x730 8002dcc: 60d3 str r3, [r2, #12] FLASH->CR1 |= (FLASH_CR_SER | VoltageRange | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START); 8002dce: 4b15 ldr r3, [pc, #84] ; (8002e24 ) 8002dd0: 68da ldr r2, [r3, #12] 8002dd2: 68fb ldr r3, [r7, #12] 8002dd4: 0219 lsls r1, r3, #8 8002dd6: 687b ldr r3, [r7, #4] 8002dd8: 430b orrs r3, r1 8002dda: 4313 orrs r3, r2 8002ddc: 4a11 ldr r2, [pc, #68] ; (8002e24 ) 8002dde: f043 0384 orr.w r3, r3, #132 ; 0x84 8002de2: 60d3 str r3, [r2, #12] FLASH->CR1 |= (FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START); #endif /* FLASH_CR_PSIZE */ } #if defined (DUAL_BANK) if((Banks & FLASH_BANK_2) == FLASH_BANK_2) 8002de4: 68bb ldr r3, [r7, #8] 8002de6: f003 0302 and.w r3, r3, #2 8002dea: 2b00 cmp r3, #0 8002dec: d014 beq.n 8002e18 { #if defined (FLASH_CR_PSIZE) /* Reset Program/erase VoltageRange and Sector Number for Bank2 */ FLASH->CR2 &= ~(FLASH_CR_PSIZE | FLASH_CR_SNB); 8002dee: 4b0d ldr r3, [pc, #52] ; (8002e24 ) 8002df0: f8d3 310c ldr.w r3, [r3, #268] ; 0x10c 8002df4: 4a0b ldr r2, [pc, #44] ; (8002e24 ) 8002df6: f423 63e6 bic.w r3, r3, #1840 ; 0x730 8002dfa: f8c2 310c str.w r3, [r2, #268] ; 0x10c FLASH->CR2 |= (FLASH_CR_SER | VoltageRange | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START); 8002dfe: 4b09 ldr r3, [pc, #36] ; (8002e24 ) 8002e00: f8d3 210c ldr.w r2, [r3, #268] ; 0x10c 8002e04: 68fb ldr r3, [r7, #12] 8002e06: 0219 lsls r1, r3, #8 8002e08: 687b ldr r3, [r7, #4] 8002e0a: 430b orrs r3, r1 8002e0c: 4313 orrs r3, r2 8002e0e: 4a05 ldr r2, [pc, #20] ; (8002e24 ) 8002e10: f043 0384 orr.w r3, r3, #132 ; 0x84 8002e14: f8c2 310c str.w r3, [r2, #268] ; 0x10c FLASH->CR2 |= (FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START); #endif /* FLASH_CR_PSIZE */ } #endif /* DUAL_BANK */ } 8002e18: bf00 nop 8002e1a: 3714 adds r7, #20 8002e1c: 46bd mov sp, r7 8002e1e: f85d 7b04 ldr.w r7, [sp], #4 8002e22: 4770 bx lr 8002e24: 52002000 .word 0x52002000 08002e28 : * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 8002e28: b480 push {r7} 8002e2a: b089 sub sp, #36 ; 0x24 8002e2c: af00 add r7, sp, #0 8002e2e: 6078 str r0, [r7, #4] 8002e30: 6039 str r1, [r7, #0] uint32_t position = 0x00U; 8002e32: 2300 movs r3, #0 8002e34: 61fb str r3, [r7, #28] EXTI_Core_TypeDef *EXTI_CurrentCPU; #if defined(DUAL_CORE) && defined(CORE_CM4) EXTI_CurrentCPU = EXTI_D2; /* EXTI for CM4 CPU */ #else EXTI_CurrentCPU = EXTI_D1; /* EXTI for CM7 CPU */ 8002e36: 4b89 ldr r3, [pc, #548] ; (800305c ) 8002e38: 617b str r3, [r7, #20] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00U) 8002e3a: e194 b.n 8003166 { /* Get current io position */ iocurrent = (GPIO_Init->Pin) & (1UL << position); 8002e3c: 683b ldr r3, [r7, #0] 8002e3e: 681a ldr r2, [r3, #0] 8002e40: 2101 movs r1, #1 8002e42: 69fb ldr r3, [r7, #28] 8002e44: fa01 f303 lsl.w r3, r1, r3 8002e48: 4013 ands r3, r2 8002e4a: 613b str r3, [r7, #16] if (iocurrent != 0x00U) 8002e4c: 693b ldr r3, [r7, #16] 8002e4e: 2b00 cmp r3, #0 8002e50: f000 8186 beq.w 8003160 { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) 8002e54: 683b ldr r3, [r7, #0] 8002e56: 685b ldr r3, [r3, #4] 8002e58: f003 0303 and.w r3, r3, #3 8002e5c: 2b01 cmp r3, #1 8002e5e: d005 beq.n 8002e6c 8002e60: 683b ldr r3, [r7, #0] 8002e62: 685b ldr r3, [r3, #4] 8002e64: f003 0303 and.w r3, r3, #3 8002e68: 2b02 cmp r3, #2 8002e6a: d130 bne.n 8002ece { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 8002e6c: 687b ldr r3, [r7, #4] 8002e6e: 689b ldr r3, [r3, #8] 8002e70: 61bb str r3, [r7, #24] temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); 8002e72: 69fb ldr r3, [r7, #28] 8002e74: 005b lsls r3, r3, #1 8002e76: 2203 movs r2, #3 8002e78: fa02 f303 lsl.w r3, r2, r3 8002e7c: 43db mvns r3, r3 8002e7e: 69ba ldr r2, [r7, #24] 8002e80: 4013 ands r3, r2 8002e82: 61bb str r3, [r7, #24] temp |= (GPIO_Init->Speed << (position * 2U)); 8002e84: 683b ldr r3, [r7, #0] 8002e86: 68da ldr r2, [r3, #12] 8002e88: 69fb ldr r3, [r7, #28] 8002e8a: 005b lsls r3, r3, #1 8002e8c: fa02 f303 lsl.w r3, r2, r3 8002e90: 69ba ldr r2, [r7, #24] 8002e92: 4313 orrs r3, r2 8002e94: 61bb str r3, [r7, #24] GPIOx->OSPEEDR = temp; 8002e96: 687b ldr r3, [r7, #4] 8002e98: 69ba ldr r2, [r7, #24] 8002e9a: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 8002e9c: 687b ldr r3, [r7, #4] 8002e9e: 685b ldr r3, [r3, #4] 8002ea0: 61bb str r3, [r7, #24] temp &= ~(GPIO_OTYPER_OT0 << position) ; 8002ea2: 2201 movs r2, #1 8002ea4: 69fb ldr r3, [r7, #28] 8002ea6: fa02 f303 lsl.w r3, r2, r3 8002eaa: 43db mvns r3, r3 8002eac: 69ba ldr r2, [r7, #24] 8002eae: 4013 ands r3, r2 8002eb0: 61bb str r3, [r7, #24] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 8002eb2: 683b ldr r3, [r7, #0] 8002eb4: 685b ldr r3, [r3, #4] 8002eb6: 091b lsrs r3, r3, #4 8002eb8: f003 0201 and.w r2, r3, #1 8002ebc: 69fb ldr r3, [r7, #28] 8002ebe: fa02 f303 lsl.w r3, r2, r3 8002ec2: 69ba ldr r2, [r7, #24] 8002ec4: 4313 orrs r3, r2 8002ec6: 61bb str r3, [r7, #24] GPIOx->OTYPER = temp; 8002ec8: 687b ldr r3, [r7, #4] 8002eca: 69ba ldr r2, [r7, #24] 8002ecc: 605a str r2, [r3, #4] } if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) 8002ece: 683b ldr r3, [r7, #0] 8002ed0: 685b ldr r3, [r3, #4] 8002ed2: f003 0303 and.w r3, r3, #3 8002ed6: 2b03 cmp r3, #3 8002ed8: d017 beq.n 8002f0a { /* Check the Pull parameter */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; 8002eda: 687b ldr r3, [r7, #4] 8002edc: 68db ldr r3, [r3, #12] 8002ede: 61bb str r3, [r7, #24] temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); 8002ee0: 69fb ldr r3, [r7, #28] 8002ee2: 005b lsls r3, r3, #1 8002ee4: 2203 movs r2, #3 8002ee6: fa02 f303 lsl.w r3, r2, r3 8002eea: 43db mvns r3, r3 8002eec: 69ba ldr r2, [r7, #24] 8002eee: 4013 ands r3, r2 8002ef0: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Pull) << (position * 2U)); 8002ef2: 683b ldr r3, [r7, #0] 8002ef4: 689a ldr r2, [r3, #8] 8002ef6: 69fb ldr r3, [r7, #28] 8002ef8: 005b lsls r3, r3, #1 8002efa: fa02 f303 lsl.w r3, r2, r3 8002efe: 69ba ldr r2, [r7, #24] 8002f00: 4313 orrs r3, r2 8002f02: 61bb str r3, [r7, #24] GPIOx->PUPDR = temp; 8002f04: 687b ldr r3, [r7, #4] 8002f06: 69ba ldr r2, [r7, #24] 8002f08: 60da str r2, [r3, #12] } /* In case of Alternate function mode selection */ if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 8002f0a: 683b ldr r3, [r7, #0] 8002f0c: 685b ldr r3, [r3, #4] 8002f0e: f003 0303 and.w r3, r3, #3 8002f12: 2b02 cmp r3, #2 8002f14: d123 bne.n 8002f5e /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3U]; 8002f16: 69fb ldr r3, [r7, #28] 8002f18: 08da lsrs r2, r3, #3 8002f1a: 687b ldr r3, [r7, #4] 8002f1c: 3208 adds r2, #8 8002f1e: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8002f22: 61bb str r3, [r7, #24] temp &= ~(0xFU << ((position & 0x07U) * 4U)); 8002f24: 69fb ldr r3, [r7, #28] 8002f26: f003 0307 and.w r3, r3, #7 8002f2a: 009b lsls r3, r3, #2 8002f2c: 220f movs r2, #15 8002f2e: fa02 f303 lsl.w r3, r2, r3 8002f32: 43db mvns r3, r3 8002f34: 69ba ldr r2, [r7, #24] 8002f36: 4013 ands r3, r2 8002f38: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); 8002f3a: 683b ldr r3, [r7, #0] 8002f3c: 691a ldr r2, [r3, #16] 8002f3e: 69fb ldr r3, [r7, #28] 8002f40: f003 0307 and.w r3, r3, #7 8002f44: 009b lsls r3, r3, #2 8002f46: fa02 f303 lsl.w r3, r2, r3 8002f4a: 69ba ldr r2, [r7, #24] 8002f4c: 4313 orrs r3, r2 8002f4e: 61bb str r3, [r7, #24] GPIOx->AFR[position >> 3U] = temp; 8002f50: 69fb ldr r3, [r7, #28] 8002f52: 08da lsrs r2, r3, #3 8002f54: 687b ldr r3, [r7, #4] 8002f56: 3208 adds r2, #8 8002f58: 69b9 ldr r1, [r7, #24] 8002f5a: f843 1022 str.w r1, [r3, r2, lsl #2] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 8002f5e: 687b ldr r3, [r7, #4] 8002f60: 681b ldr r3, [r3, #0] 8002f62: 61bb str r3, [r7, #24] temp &= ~(GPIO_MODER_MODE0 << (position * 2U)); 8002f64: 69fb ldr r3, [r7, #28] 8002f66: 005b lsls r3, r3, #1 8002f68: 2203 movs r2, #3 8002f6a: fa02 f303 lsl.w r3, r2, r3 8002f6e: 43db mvns r3, r3 8002f70: 69ba ldr r2, [r7, #24] 8002f72: 4013 ands r3, r2 8002f74: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); 8002f76: 683b ldr r3, [r7, #0] 8002f78: 685b ldr r3, [r3, #4] 8002f7a: f003 0203 and.w r2, r3, #3 8002f7e: 69fb ldr r3, [r7, #28] 8002f80: 005b lsls r3, r3, #1 8002f82: fa02 f303 lsl.w r3, r2, r3 8002f86: 69ba ldr r2, [r7, #24] 8002f88: 4313 orrs r3, r2 8002f8a: 61bb str r3, [r7, #24] GPIOx->MODER = temp; 8002f8c: 687b ldr r3, [r7, #4] 8002f8e: 69ba ldr r2, [r7, #24] 8002f90: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U) 8002f92: 683b ldr r3, [r7, #0] 8002f94: 685b ldr r3, [r3, #4] 8002f96: f403 3340 and.w r3, r3, #196608 ; 0x30000 8002f9a: 2b00 cmp r3, #0 8002f9c: f000 80e0 beq.w 8003160 { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8002fa0: 4b2f ldr r3, [pc, #188] ; (8003060 ) 8002fa2: f8d3 30f4 ldr.w r3, [r3, #244] ; 0xf4 8002fa6: 4a2e ldr r2, [pc, #184] ; (8003060 ) 8002fa8: f043 0302 orr.w r3, r3, #2 8002fac: f8c2 30f4 str.w r3, [r2, #244] ; 0xf4 8002fb0: 4b2b ldr r3, [pc, #172] ; (8003060 ) 8002fb2: f8d3 30f4 ldr.w r3, [r3, #244] ; 0xf4 8002fb6: f003 0302 and.w r3, r3, #2 8002fba: 60fb str r3, [r7, #12] 8002fbc: 68fb ldr r3, [r7, #12] temp = SYSCFG->EXTICR[position >> 2U]; 8002fbe: 4a29 ldr r2, [pc, #164] ; (8003064 ) 8002fc0: 69fb ldr r3, [r7, #28] 8002fc2: 089b lsrs r3, r3, #2 8002fc4: 3302 adds r3, #2 8002fc6: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8002fca: 61bb str r3, [r7, #24] temp &= ~(0x0FUL << (4U * (position & 0x03U))); 8002fcc: 69fb ldr r3, [r7, #28] 8002fce: f003 0303 and.w r3, r3, #3 8002fd2: 009b lsls r3, r3, #2 8002fd4: 220f movs r2, #15 8002fd6: fa02 f303 lsl.w r3, r2, r3 8002fda: 43db mvns r3, r3 8002fdc: 69ba ldr r2, [r7, #24] 8002fde: 4013 ands r3, r2 8002fe0: 61bb str r3, [r7, #24] temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))); 8002fe2: 687b ldr r3, [r7, #4] 8002fe4: 4a20 ldr r2, [pc, #128] ; (8003068 ) 8002fe6: 4293 cmp r3, r2 8002fe8: d052 beq.n 8003090 8002fea: 687b ldr r3, [r7, #4] 8002fec: 4a1f ldr r2, [pc, #124] ; (800306c ) 8002fee: 4293 cmp r3, r2 8002ff0: d031 beq.n 8003056 8002ff2: 687b ldr r3, [r7, #4] 8002ff4: 4a1e ldr r2, [pc, #120] ; (8003070 ) 8002ff6: 4293 cmp r3, r2 8002ff8: d02b beq.n 8003052 8002ffa: 687b ldr r3, [r7, #4] 8002ffc: 4a1d ldr r2, [pc, #116] ; (8003074 ) 8002ffe: 4293 cmp r3, r2 8003000: d025 beq.n 800304e 8003002: 687b ldr r3, [r7, #4] 8003004: 4a1c ldr r2, [pc, #112] ; (8003078 ) 8003006: 4293 cmp r3, r2 8003008: d01f beq.n 800304a 800300a: 687b ldr r3, [r7, #4] 800300c: 4a1b ldr r2, [pc, #108] ; (800307c ) 800300e: 4293 cmp r3, r2 8003010: d019 beq.n 8003046 8003012: 687b ldr r3, [r7, #4] 8003014: 4a1a ldr r2, [pc, #104] ; (8003080 ) 8003016: 4293 cmp r3, r2 8003018: d013 beq.n 8003042 800301a: 687b ldr r3, [r7, #4] 800301c: 4a19 ldr r2, [pc, #100] ; (8003084 ) 800301e: 4293 cmp r3, r2 8003020: d00d beq.n 800303e 8003022: 687b ldr r3, [r7, #4] 8003024: 4a18 ldr r2, [pc, #96] ; (8003088 ) 8003026: 4293 cmp r3, r2 8003028: d007 beq.n 800303a 800302a: 687b ldr r3, [r7, #4] 800302c: 4a17 ldr r2, [pc, #92] ; (800308c ) 800302e: 4293 cmp r3, r2 8003030: d101 bne.n 8003036 8003032: 2309 movs r3, #9 8003034: e02d b.n 8003092 8003036: 230a movs r3, #10 8003038: e02b b.n 8003092 800303a: 2308 movs r3, #8 800303c: e029 b.n 8003092 800303e: 2307 movs r3, #7 8003040: e027 b.n 8003092 8003042: 2306 movs r3, #6 8003044: e025 b.n 8003092 8003046: 2305 movs r3, #5 8003048: e023 b.n 8003092 800304a: 2304 movs r3, #4 800304c: e021 b.n 8003092 800304e: 2303 movs r3, #3 8003050: e01f b.n 8003092 8003052: 2302 movs r3, #2 8003054: e01d b.n 8003092 8003056: 2301 movs r3, #1 8003058: e01b b.n 8003092 800305a: bf00 nop 800305c: 58000080 .word 0x58000080 8003060: 58024400 .word 0x58024400 8003064: 58000400 .word 0x58000400 8003068: 58020000 .word 0x58020000 800306c: 58020400 .word 0x58020400 8003070: 58020800 .word 0x58020800 8003074: 58020c00 .word 0x58020c00 8003078: 58021000 .word 0x58021000 800307c: 58021400 .word 0x58021400 8003080: 58021800 .word 0x58021800 8003084: 58021c00 .word 0x58021c00 8003088: 58022000 .word 0x58022000 800308c: 58022400 .word 0x58022400 8003090: 2300 movs r3, #0 8003092: 69fa ldr r2, [r7, #28] 8003094: f002 0203 and.w r2, r2, #3 8003098: 0092 lsls r2, r2, #2 800309a: 4093 lsls r3, r2 800309c: 69ba ldr r2, [r7, #24] 800309e: 4313 orrs r3, r2 80030a0: 61bb str r3, [r7, #24] SYSCFG->EXTICR[position >> 2U] = temp; 80030a2: 4938 ldr r1, [pc, #224] ; (8003184 ) 80030a4: 69fb ldr r3, [r7, #28] 80030a6: 089b lsrs r3, r3, #2 80030a8: 3302 adds r3, #2 80030aa: 69ba ldr r2, [r7, #24] 80030ac: f841 2023 str.w r2, [r1, r3, lsl #2] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR1; 80030b0: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 80030b4: 681b ldr r3, [r3, #0] 80030b6: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 80030b8: 693b ldr r3, [r7, #16] 80030ba: 43db mvns r3, r3 80030bc: 69ba ldr r2, [r7, #24] 80030be: 4013 ands r3, r2 80030c0: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) 80030c2: 683b ldr r3, [r7, #0] 80030c4: 685b ldr r3, [r3, #4] 80030c6: f403 1380 and.w r3, r3, #1048576 ; 0x100000 80030ca: 2b00 cmp r3, #0 80030cc: d003 beq.n 80030d6 { temp |= iocurrent; 80030ce: 69ba ldr r2, [r7, #24] 80030d0: 693b ldr r3, [r7, #16] 80030d2: 4313 orrs r3, r2 80030d4: 61bb str r3, [r7, #24] } EXTI->RTSR1 = temp; 80030d6: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 80030da: 69bb ldr r3, [r7, #24] 80030dc: 6013 str r3, [r2, #0] temp = EXTI->FTSR1; 80030de: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 80030e2: 685b ldr r3, [r3, #4] 80030e4: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 80030e6: 693b ldr r3, [r7, #16] 80030e8: 43db mvns r3, r3 80030ea: 69ba ldr r2, [r7, #24] 80030ec: 4013 ands r3, r2 80030ee: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) 80030f0: 683b ldr r3, [r7, #0] 80030f2: 685b ldr r3, [r3, #4] 80030f4: f403 1300 and.w r3, r3, #2097152 ; 0x200000 80030f8: 2b00 cmp r3, #0 80030fa: d003 beq.n 8003104 { temp |= iocurrent; 80030fc: 69ba ldr r2, [r7, #24] 80030fe: 693b ldr r3, [r7, #16] 8003100: 4313 orrs r3, r2 8003102: 61bb str r3, [r7, #24] } EXTI->FTSR1 = temp; 8003104: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 8003108: 69bb ldr r3, [r7, #24] 800310a: 6053 str r3, [r2, #4] temp = EXTI_CurrentCPU->EMR1; 800310c: 697b ldr r3, [r7, #20] 800310e: 685b ldr r3, [r3, #4] 8003110: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 8003112: 693b ldr r3, [r7, #16] 8003114: 43db mvns r3, r3 8003116: 69ba ldr r2, [r7, #24] 8003118: 4013 ands r3, r2 800311a: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U) 800311c: 683b ldr r3, [r7, #0] 800311e: 685b ldr r3, [r3, #4] 8003120: f403 3300 and.w r3, r3, #131072 ; 0x20000 8003124: 2b00 cmp r3, #0 8003126: d003 beq.n 8003130 { temp |= iocurrent; 8003128: 69ba ldr r2, [r7, #24] 800312a: 693b ldr r3, [r7, #16] 800312c: 4313 orrs r3, r2 800312e: 61bb str r3, [r7, #24] } EXTI_CurrentCPU->EMR1 = temp; 8003130: 697b ldr r3, [r7, #20] 8003132: 69ba ldr r2, [r7, #24] 8003134: 605a str r2, [r3, #4] /* Clear EXTI line configuration */ temp = EXTI_CurrentCPU->IMR1; 8003136: 697b ldr r3, [r7, #20] 8003138: 681b ldr r3, [r3, #0] 800313a: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 800313c: 693b ldr r3, [r7, #16] 800313e: 43db mvns r3, r3 8003140: 69ba ldr r2, [r7, #24] 8003142: 4013 ands r3, r2 8003144: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & EXTI_IT) != 0x00U) 8003146: 683b ldr r3, [r7, #0] 8003148: 685b ldr r3, [r3, #4] 800314a: f403 3380 and.w r3, r3, #65536 ; 0x10000 800314e: 2b00 cmp r3, #0 8003150: d003 beq.n 800315a { temp |= iocurrent; 8003152: 69ba ldr r2, [r7, #24] 8003154: 693b ldr r3, [r7, #16] 8003156: 4313 orrs r3, r2 8003158: 61bb str r3, [r7, #24] } EXTI_CurrentCPU->IMR1 = temp; 800315a: 697b ldr r3, [r7, #20] 800315c: 69ba ldr r2, [r7, #24] 800315e: 601a str r2, [r3, #0] } } position++; 8003160: 69fb ldr r3, [r7, #28] 8003162: 3301 adds r3, #1 8003164: 61fb str r3, [r7, #28] while (((GPIO_Init->Pin) >> position) != 0x00U) 8003166: 683b ldr r3, [r7, #0] 8003168: 681a ldr r2, [r3, #0] 800316a: 69fb ldr r3, [r7, #28] 800316c: fa22 f303 lsr.w r3, r2, r3 8003170: 2b00 cmp r3, #0 8003172: f47f ae63 bne.w 8002e3c } } 8003176: bf00 nop 8003178: bf00 nop 800317a: 3724 adds r7, #36 ; 0x24 800317c: 46bd mov sp, r7 800317e: f85d 7b04 ldr.w r7, [sp], #4 8003182: 4770 bx lr 8003184: 58000400 .word 0x58000400 08003188 : * @param GPIO_Pin: specifies the port bit to be written. * This parameter can be one of GPIO_PIN_x where x can be (0..15). * @retval None */ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) { 8003188: b480 push {r7} 800318a: b087 sub sp, #28 800318c: af00 add r7, sp, #0 800318e: 6078 str r0, [r7, #4] 8003190: 6039 str r1, [r7, #0] uint32_t position = 0x00U; 8003192: 2300 movs r3, #0 8003194: 617b str r3, [r7, #20] EXTI_Core_TypeDef *EXTI_CurrentCPU; #if defined(DUAL_CORE) && defined(CORE_CM4) EXTI_CurrentCPU = EXTI_D2; /* EXTI for CM4 CPU */ #else EXTI_CurrentCPU = EXTI_D1; /* EXTI for CM7 CPU */ 8003196: 4b75 ldr r3, [pc, #468] ; (800336c ) 8003198: 613b str r3, [r7, #16] /* Check the parameters */ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Pin)); /* Configure the port pins */ while ((GPIO_Pin >> position) != 0x00U) 800319a: e0d9 b.n 8003350 { /* Get current io position */ iocurrent = GPIO_Pin & (1UL << position) ; 800319c: 2201 movs r2, #1 800319e: 697b ldr r3, [r7, #20] 80031a0: fa02 f303 lsl.w r3, r2, r3 80031a4: 683a ldr r2, [r7, #0] 80031a6: 4013 ands r3, r2 80031a8: 60fb str r3, [r7, #12] if (iocurrent != 0x00U) 80031aa: 68fb ldr r3, [r7, #12] 80031ac: 2b00 cmp r3, #0 80031ae: f000 80cc beq.w 800334a { /*------------------------- EXTI Mode Configuration --------------------*/ /* Clear the External Interrupt or Event for the current IO */ tmp = SYSCFG->EXTICR[position >> 2U]; 80031b2: 4a6f ldr r2, [pc, #444] ; (8003370 ) 80031b4: 697b ldr r3, [r7, #20] 80031b6: 089b lsrs r3, r3, #2 80031b8: 3302 adds r3, #2 80031ba: f852 3023 ldr.w r3, [r2, r3, lsl #2] 80031be: 60bb str r3, [r7, #8] tmp &= (0x0FUL << (4U * (position & 0x03U))); 80031c0: 697b ldr r3, [r7, #20] 80031c2: f003 0303 and.w r3, r3, #3 80031c6: 009b lsls r3, r3, #2 80031c8: 220f movs r2, #15 80031ca: fa02 f303 lsl.w r3, r2, r3 80031ce: 68ba ldr r2, [r7, #8] 80031d0: 4013 ands r3, r2 80031d2: 60bb str r3, [r7, #8] if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)))) 80031d4: 687b ldr r3, [r7, #4] 80031d6: 4a67 ldr r2, [pc, #412] ; (8003374 ) 80031d8: 4293 cmp r3, r2 80031da: d037 beq.n 800324c 80031dc: 687b ldr r3, [r7, #4] 80031de: 4a66 ldr r2, [pc, #408] ; (8003378 ) 80031e0: 4293 cmp r3, r2 80031e2: d031 beq.n 8003248 80031e4: 687b ldr r3, [r7, #4] 80031e6: 4a65 ldr r2, [pc, #404] ; (800337c ) 80031e8: 4293 cmp r3, r2 80031ea: d02b beq.n 8003244 80031ec: 687b ldr r3, [r7, #4] 80031ee: 4a64 ldr r2, [pc, #400] ; (8003380 ) 80031f0: 4293 cmp r3, r2 80031f2: d025 beq.n 8003240 80031f4: 687b ldr r3, [r7, #4] 80031f6: 4a63 ldr r2, [pc, #396] ; (8003384 ) 80031f8: 4293 cmp r3, r2 80031fa: d01f beq.n 800323c 80031fc: 687b ldr r3, [r7, #4] 80031fe: 4a62 ldr r2, [pc, #392] ; (8003388 ) 8003200: 4293 cmp r3, r2 8003202: d019 beq.n 8003238 8003204: 687b ldr r3, [r7, #4] 8003206: 4a61 ldr r2, [pc, #388] ; (800338c ) 8003208: 4293 cmp r3, r2 800320a: d013 beq.n 8003234 800320c: 687b ldr r3, [r7, #4] 800320e: 4a60 ldr r2, [pc, #384] ; (8003390 ) 8003210: 4293 cmp r3, r2 8003212: d00d beq.n 8003230 8003214: 687b ldr r3, [r7, #4] 8003216: 4a5f ldr r2, [pc, #380] ; (8003394 ) 8003218: 4293 cmp r3, r2 800321a: d007 beq.n 800322c 800321c: 687b ldr r3, [r7, #4] 800321e: 4a5e ldr r2, [pc, #376] ; (8003398 ) 8003220: 4293 cmp r3, r2 8003222: d101 bne.n 8003228 8003224: 2309 movs r3, #9 8003226: e012 b.n 800324e 8003228: 230a movs r3, #10 800322a: e010 b.n 800324e 800322c: 2308 movs r3, #8 800322e: e00e b.n 800324e 8003230: 2307 movs r3, #7 8003232: e00c b.n 800324e 8003234: 2306 movs r3, #6 8003236: e00a b.n 800324e 8003238: 2305 movs r3, #5 800323a: e008 b.n 800324e 800323c: 2304 movs r3, #4 800323e: e006 b.n 800324e 8003240: 2303 movs r3, #3 8003242: e004 b.n 800324e 8003244: 2302 movs r3, #2 8003246: e002 b.n 800324e 8003248: 2301 movs r3, #1 800324a: e000 b.n 800324e 800324c: 2300 movs r3, #0 800324e: 697a ldr r2, [r7, #20] 8003250: f002 0203 and.w r2, r2, #3 8003254: 0092 lsls r2, r2, #2 8003256: 4093 lsls r3, r2 8003258: 68ba ldr r2, [r7, #8] 800325a: 429a cmp r2, r3 800325c: d136 bne.n 80032cc { /* Clear EXTI line configuration for Current CPU */ EXTI_CurrentCPU->IMR1 &= ~(iocurrent); 800325e: 693b ldr r3, [r7, #16] 8003260: 681a ldr r2, [r3, #0] 8003262: 68fb ldr r3, [r7, #12] 8003264: 43db mvns r3, r3 8003266: 401a ands r2, r3 8003268: 693b ldr r3, [r7, #16] 800326a: 601a str r2, [r3, #0] EXTI_CurrentCPU->EMR1 &= ~(iocurrent); 800326c: 693b ldr r3, [r7, #16] 800326e: 685a ldr r2, [r3, #4] 8003270: 68fb ldr r3, [r7, #12] 8003272: 43db mvns r3, r3 8003274: 401a ands r2, r3 8003276: 693b ldr r3, [r7, #16] 8003278: 605a str r2, [r3, #4] /* Clear Rising Falling edge configuration */ EXTI->FTSR1 &= ~(iocurrent); 800327a: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 800327e: 685a ldr r2, [r3, #4] 8003280: 68fb ldr r3, [r7, #12] 8003282: 43db mvns r3, r3 8003284: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 8003288: 4013 ands r3, r2 800328a: 604b str r3, [r1, #4] EXTI->RTSR1 &= ~(iocurrent); 800328c: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 8003290: 681a ldr r2, [r3, #0] 8003292: 68fb ldr r3, [r7, #12] 8003294: 43db mvns r3, r3 8003296: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 800329a: 4013 ands r3, r2 800329c: 600b str r3, [r1, #0] tmp = 0x0FUL << (4U * (position & 0x03U)); 800329e: 697b ldr r3, [r7, #20] 80032a0: f003 0303 and.w r3, r3, #3 80032a4: 009b lsls r3, r3, #2 80032a6: 220f movs r2, #15 80032a8: fa02 f303 lsl.w r3, r2, r3 80032ac: 60bb str r3, [r7, #8] SYSCFG->EXTICR[position >> 2U] &= ~tmp; 80032ae: 4a30 ldr r2, [pc, #192] ; (8003370 ) 80032b0: 697b ldr r3, [r7, #20] 80032b2: 089b lsrs r3, r3, #2 80032b4: 3302 adds r3, #2 80032b6: f852 1023 ldr.w r1, [r2, r3, lsl #2] 80032ba: 68bb ldr r3, [r7, #8] 80032bc: 43da mvns r2, r3 80032be: 482c ldr r0, [pc, #176] ; (8003370 ) 80032c0: 697b ldr r3, [r7, #20] 80032c2: 089b lsrs r3, r3, #2 80032c4: 400a ands r2, r1 80032c6: 3302 adds r3, #2 80032c8: f840 2023 str.w r2, [r0, r3, lsl #2] } /*------------------------- GPIO Mode Configuration --------------------*/ /* Configure IO in Analog Mode */ GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2U)); 80032cc: 687b ldr r3, [r7, #4] 80032ce: 681a ldr r2, [r3, #0] 80032d0: 697b ldr r3, [r7, #20] 80032d2: 005b lsls r3, r3, #1 80032d4: 2103 movs r1, #3 80032d6: fa01 f303 lsl.w r3, r1, r3 80032da: 431a orrs r2, r3 80032dc: 687b ldr r3, [r7, #4] 80032de: 601a str r2, [r3, #0] /* Configure the default Alternate Function in current IO */ GPIOx->AFR[position >> 3U] &= ~(0xFU << ((position & 0x07U) * 4U)) ; 80032e0: 697b ldr r3, [r7, #20] 80032e2: 08da lsrs r2, r3, #3 80032e4: 687b ldr r3, [r7, #4] 80032e6: 3208 adds r2, #8 80032e8: f853 1022 ldr.w r1, [r3, r2, lsl #2] 80032ec: 697b ldr r3, [r7, #20] 80032ee: f003 0307 and.w r3, r3, #7 80032f2: 009b lsls r3, r3, #2 80032f4: 220f movs r2, #15 80032f6: fa02 f303 lsl.w r3, r2, r3 80032fa: 43db mvns r3, r3 80032fc: 697a ldr r2, [r7, #20] 80032fe: 08d2 lsrs r2, r2, #3 8003300: 4019 ands r1, r3 8003302: 687b ldr r3, [r7, #4] 8003304: 3208 adds r2, #8 8003306: f843 1022 str.w r1, [r3, r2, lsl #2] /* Deactivate the Pull-up and Pull-down resistor for the current IO */ GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); 800330a: 687b ldr r3, [r7, #4] 800330c: 68da ldr r2, [r3, #12] 800330e: 697b ldr r3, [r7, #20] 8003310: 005b lsls r3, r3, #1 8003312: 2103 movs r1, #3 8003314: fa01 f303 lsl.w r3, r1, r3 8003318: 43db mvns r3, r3 800331a: 401a ands r2, r3 800331c: 687b ldr r3, [r7, #4] 800331e: 60da str r2, [r3, #12] /* Configure the default value IO Output Type */ GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position) ; 8003320: 687b ldr r3, [r7, #4] 8003322: 685a ldr r2, [r3, #4] 8003324: 2101 movs r1, #1 8003326: 697b ldr r3, [r7, #20] 8003328: fa01 f303 lsl.w r3, r1, r3 800332c: 43db mvns r3, r3 800332e: 401a ands r2, r3 8003330: 687b ldr r3, [r7, #4] 8003332: 605a str r2, [r3, #4] /* Configure the default value for IO Speed */ GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); 8003334: 687b ldr r3, [r7, #4] 8003336: 689a ldr r2, [r3, #8] 8003338: 697b ldr r3, [r7, #20] 800333a: 005b lsls r3, r3, #1 800333c: 2103 movs r1, #3 800333e: fa01 f303 lsl.w r3, r1, r3 8003342: 43db mvns r3, r3 8003344: 401a ands r2, r3 8003346: 687b ldr r3, [r7, #4] 8003348: 609a str r2, [r3, #8] } position++; 800334a: 697b ldr r3, [r7, #20] 800334c: 3301 adds r3, #1 800334e: 617b str r3, [r7, #20] while ((GPIO_Pin >> position) != 0x00U) 8003350: 683a ldr r2, [r7, #0] 8003352: 697b ldr r3, [r7, #20] 8003354: fa22 f303 lsr.w r3, r2, r3 8003358: 2b00 cmp r3, #0 800335a: f47f af1f bne.w 800319c } } 800335e: bf00 nop 8003360: bf00 nop 8003362: 371c adds r7, #28 8003364: 46bd mov sp, r7 8003366: f85d 7b04 ldr.w r7, [sp], #4 800336a: 4770 bx lr 800336c: 58000080 .word 0x58000080 8003370: 58000400 .word 0x58000400 8003374: 58020000 .word 0x58020000 8003378: 58020400 .word 0x58020400 800337c: 58020800 .word 0x58020800 8003380: 58020c00 .word 0x58020c00 8003384: 58021000 .word 0x58021000 8003388: 58021400 .word 0x58021400 800338c: 58021800 .word 0x58021800 8003390: 58021c00 .word 0x58021c00 8003394: 58022000 .word 0x58022000 8003398: 58022400 .word 0x58022400 0800339c : * PWR_SMPS_2V5_SUPPLIES_EXT are used only for lines that supports SMPS * regulator. * @retval HAL status. */ HAL_StatusTypeDef HAL_PWREx_ConfigSupply (uint32_t SupplySource) { 800339c: b580 push {r7, lr} 800339e: b084 sub sp, #16 80033a0: af00 add r7, sp, #0 80033a2: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param (IS_PWR_SUPPLY (SupplySource)); /* Check if supply source was configured */ #if defined (PWR_FLAG_SCUEN) if (__HAL_PWR_GET_FLAG (PWR_FLAG_SCUEN) == 0U) 80033a4: 4b19 ldr r3, [pc, #100] ; (800340c ) 80033a6: 68db ldr r3, [r3, #12] 80033a8: f003 0304 and.w r3, r3, #4 80033ac: 2b04 cmp r3, #4 80033ae: d00a beq.n 80033c6 #else if ((PWR->CR3 & (PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)) != (PWR_CR3_SMPSEN | PWR_CR3_LDOEN)) #endif /* defined (PWR_FLAG_SCUEN) */ { /* Check supply configuration */ if ((PWR->CR3 & PWR_SUPPLY_CONFIG_MASK) != SupplySource) 80033b0: 4b16 ldr r3, [pc, #88] ; (800340c ) 80033b2: 68db ldr r3, [r3, #12] 80033b4: f003 0307 and.w r3, r3, #7 80033b8: 687a ldr r2, [r7, #4] 80033ba: 429a cmp r2, r3 80033bc: d001 beq.n 80033c2 { /* Supply configuration update locked, can't apply a new supply config */ return HAL_ERROR; 80033be: 2301 movs r3, #1 80033c0: e01f b.n 8003402 else { /* Supply configuration update locked, but new supply configuration matches with old supply configuration : nothing to do */ return HAL_OK; 80033c2: 2300 movs r3, #0 80033c4: e01d b.n 8003402 } } /* Set the power supply configuration */ MODIFY_REG (PWR->CR3, PWR_SUPPLY_CONFIG_MASK, SupplySource); 80033c6: 4b11 ldr r3, [pc, #68] ; (800340c ) 80033c8: 68db ldr r3, [r3, #12] 80033ca: f023 0207 bic.w r2, r3, #7 80033ce: 490f ldr r1, [pc, #60] ; (800340c ) 80033d0: 687b ldr r3, [r7, #4] 80033d2: 4313 orrs r3, r2 80033d4: 60cb str r3, [r1, #12] /* Get tick */ tickstart = HAL_GetTick (); 80033d6: f7fd ff4b bl 8001270 80033da: 60f8 str r0, [r7, #12] /* Wait till voltage level flag is set */ while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U) 80033dc: e009 b.n 80033f2 { if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY) 80033de: f7fd ff47 bl 8001270 80033e2: 4602 mov r2, r0 80033e4: 68fb ldr r3, [r7, #12] 80033e6: 1ad3 subs r3, r2, r3 80033e8: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8 80033ec: d901 bls.n 80033f2 { return HAL_ERROR; 80033ee: 2301 movs r3, #1 80033f0: e007 b.n 8003402 while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U) 80033f2: 4b06 ldr r3, [pc, #24] ; (800340c ) 80033f4: 685b ldr r3, [r3, #4] 80033f6: f403 5300 and.w r3, r3, #8192 ; 0x2000 80033fa: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 80033fe: d1ee bne.n 80033de } } } #endif /* defined (SMPS) */ return HAL_OK; 8003400: 2300 movs r3, #0 } 8003402: 4618 mov r0, r3 8003404: 3710 adds r7, #16 8003406: 46bd mov sp, r7 8003408: bd80 pop {r7, pc} 800340a: bf00 nop 800340c: 58024800 .word 0x58024800 08003410 : * - Peripheral clocks * - LSI, LSE and RTC clocks * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_DeInit(void) { 8003410: b580 push {r7, lr} 8003412: b082 sub sp, #8 8003414: af00 add r7, sp, #0 uint32_t tickstart; /* Increasing the CPU frequency */ if(FLASH_LATENCY_DEFAULT > __HAL_FLASH_GET_LATENCY()) 8003416: 4b89 ldr r3, [pc, #548] ; (800363c ) 8003418: 681b ldr r3, [r3, #0] 800341a: f003 030f and.w r3, r3, #15 800341e: 2b06 cmp r3, #6 8003420: d80f bhi.n 8003442 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_DEFAULT); 8003422: 4b86 ldr r3, [pc, #536] ; (800363c ) 8003424: 681b ldr r3, [r3, #0] 8003426: f023 030f bic.w r3, r3, #15 800342a: 4a84 ldr r2, [pc, #528] ; (800363c ) 800342c: f043 0307 orr.w r3, r3, #7 8003430: 6013 str r3, [r2, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_DEFAULT) 8003432: 4b82 ldr r3, [pc, #520] ; (800363c ) 8003434: 681b ldr r3, [r3, #0] 8003436: f003 030f and.w r3, r3, #15 800343a: 2b07 cmp r3, #7 800343c: d001 beq.n 8003442 { return HAL_ERROR; 800343e: 2301 movs r3, #1 8003440: e0f7 b.n 8003632 } /* Get Start Tick */ tickstart = HAL_GetTick(); 8003442: f7fd ff15 bl 8001270 8003446: 6078 str r0, [r7, #4] /* Set HSION bit */ SET_BIT(RCC->CR, RCC_CR_HSION); 8003448: 4b7d ldr r3, [pc, #500] ; (8003640 ) 800344a: 681b ldr r3, [r3, #0] 800344c: 4a7c ldr r2, [pc, #496] ; (8003640 ) 800344e: f043 0301 orr.w r3, r3, #1 8003452: 6013 str r3, [r2, #0] /* Wait till HSI is ready */ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) 8003454: e008 b.n 8003468 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8003456: f7fd ff0b bl 8001270 800345a: 4602 mov r2, r0 800345c: 687b ldr r3, [r7, #4] 800345e: 1ad3 subs r3, r2, r3 8003460: 2b02 cmp r3, #2 8003462: d901 bls.n 8003468 { return HAL_TIMEOUT; 8003464: 2303 movs r3, #3 8003466: e0e4 b.n 8003632 while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) 8003468: 4b75 ldr r3, [pc, #468] ; (8003640 ) 800346a: 681b ldr r3, [r3, #0] 800346c: f003 0304 and.w r3, r3, #4 8003470: 2b00 cmp r3, #0 8003472: d0f0 beq.n 8003456 } } /* Set HSITRIM[6:0] bits to the reset value */ SET_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM_6); 8003474: 4b72 ldr r3, [pc, #456] ; (8003640 ) 8003476: 685b ldr r3, [r3, #4] 8003478: 4a71 ldr r2, [pc, #452] ; (8003640 ) 800347a: f043 4380 orr.w r3, r3, #1073741824 ; 0x40000000 800347e: 6053 str r3, [r2, #4] /* Reset CFGR register */ CLEAR_REG(RCC->CFGR); 8003480: 4b6f ldr r3, [pc, #444] ; (8003640 ) 8003482: 2200 movs r2, #0 8003484: 611a str r2, [r3, #16] /* Update the SystemCoreClock and SystemD2Clock global variables */ SystemCoreClock = HSI_VALUE; 8003486: 4b6f ldr r3, [pc, #444] ; (8003644 ) 8003488: 4a6f ldr r2, [pc, #444] ; (8003648 ) 800348a: 601a str r2, [r3, #0] SystemD2Clock = HSI_VALUE; 800348c: 4b6f ldr r3, [pc, #444] ; (800364c ) 800348e: 4a6e ldr r2, [pc, #440] ; (8003648 ) 8003490: 601a str r2, [r3, #0] /* Adapt Systick interrupt period */ if(HAL_InitTick(uwTickPrio) != HAL_OK) 8003492: 4b6f ldr r3, [pc, #444] ; (8003650 ) 8003494: 681b ldr r3, [r3, #0] 8003496: 4618 mov r0, r3 8003498: f7fd fea0 bl 80011dc 800349c: 4603 mov r3, r0 800349e: 2b00 cmp r3, #0 80034a0: d001 beq.n 80034a6 { return HAL_ERROR; 80034a2: 2301 movs r3, #1 80034a4: e0c5 b.n 8003632 } /* Get Start Tick */ tickstart = HAL_GetTick(); 80034a6: f7fd fee3 bl 8001270 80034aa: 6078 str r0, [r7, #4] /* Wait till clock switch is ready */ while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != 0U) 80034ac: e00a b.n 80034c4 { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 80034ae: f7fd fedf bl 8001270 80034b2: 4602 mov r2, r0 80034b4: 687b ldr r3, [r7, #4] 80034b6: 1ad3 subs r3, r2, r3 80034b8: f241 3288 movw r2, #5000 ; 0x1388 80034bc: 4293 cmp r3, r2 80034be: d901 bls.n 80034c4 { return HAL_TIMEOUT; 80034c0: 2303 movs r3, #3 80034c2: e0b6 b.n 8003632 while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != 0U) 80034c4: 4b5e ldr r3, [pc, #376] ; (8003640 ) 80034c6: 691b ldr r3, [r3, #16] 80034c8: f003 0338 and.w r3, r3, #56 ; 0x38 80034cc: 2b00 cmp r3, #0 80034ce: d1ee bne.n 80034ae } } /* Get Start Tick */ tickstart = HAL_GetTick(); 80034d0: f7fd fece bl 8001270 80034d4: 6078 str r0, [r7, #4] /* Reset CSION, CSIKERON, HSEON, HSI48ON, HSECSSON, HSIDIV bits */ CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSIKERON| RCC_CR_HSIDIV| RCC_CR_HSIDIVF| RCC_CR_CSION | RCC_CR_CSIKERON \ 80034d6: 4b5a ldr r3, [pc, #360] ; (8003640 ) 80034d8: 681a ldr r2, [r3, #0] 80034da: 4959 ldr r1, [pc, #356] ; (8003640 ) 80034dc: 4b5d ldr r3, [pc, #372] ; (8003654 ) 80034de: 4013 ands r3, r2 80034e0: 600b str r3, [r1, #0] | RCC_CR_HSI48ON | RCC_CR_CSSHSEON); /* Wait till HSE is disabled */ while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) 80034e2: e008 b.n 80034f6 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 80034e4: f7fd fec4 bl 8001270 80034e8: 4602 mov r2, r0 80034ea: 687b ldr r3, [r7, #4] 80034ec: 1ad3 subs r3, r2, r3 80034ee: 2b64 cmp r3, #100 ; 0x64 80034f0: d901 bls.n 80034f6 { return HAL_TIMEOUT; 80034f2: 2303 movs r3, #3 80034f4: e09d b.n 8003632 while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) 80034f6: 4b52 ldr r3, [pc, #328] ; (8003640 ) 80034f8: 681b ldr r3, [r3, #0] 80034fa: f403 3300 and.w r3, r3, #131072 ; 0x20000 80034fe: 2b00 cmp r3, #0 8003500: d1f0 bne.n 80034e4 } } /* Get Start Tick */ tickstart = HAL_GetTick(); 8003502: f7fd feb5 bl 8001270 8003506: 6078 str r0, [r7, #4] /* Clear PLLON bit */ CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON); 8003508: 4b4d ldr r3, [pc, #308] ; (8003640 ) 800350a: 681b ldr r3, [r3, #0] 800350c: 4a4c ldr r2, [pc, #304] ; (8003640 ) 800350e: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000 8003512: 6013 str r3, [r2, #0] /* Wait till PLL is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) != 0U) 8003514: e008 b.n 8003528 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8003516: f7fd feab bl 8001270 800351a: 4602 mov r2, r0 800351c: 687b ldr r3, [r7, #4] 800351e: 1ad3 subs r3, r2, r3 8003520: 2b02 cmp r3, #2 8003522: d901 bls.n 8003528 { return HAL_TIMEOUT; 8003524: 2303 movs r3, #3 8003526: e084 b.n 8003632 while (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) != 0U) 8003528: 4b45 ldr r3, [pc, #276] ; (8003640 ) 800352a: 681b ldr r3, [r3, #0] 800352c: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8003530: 2b00 cmp r3, #0 8003532: d1f0 bne.n 8003516 } } /* Get Start Tick */ tickstart = HAL_GetTick(); 8003534: f7fd fe9c bl 8001270 8003538: 6078 str r0, [r7, #4] /* Reset PLL2ON bit */ CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON); 800353a: 4b41 ldr r3, [pc, #260] ; (8003640 ) 800353c: 681b ldr r3, [r3, #0] 800353e: 4a40 ldr r2, [pc, #256] ; (8003640 ) 8003540: f023 6380 bic.w r3, r3, #67108864 ; 0x4000000 8003544: 6013 str r3, [r2, #0] /* Wait till PLL2 is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != 0U) 8003546: e008 b.n 800355a { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8003548: f7fd fe92 bl 8001270 800354c: 4602 mov r2, r0 800354e: 687b ldr r3, [r7, #4] 8003550: 1ad3 subs r3, r2, r3 8003552: 2b02 cmp r3, #2 8003554: d901 bls.n 800355a { return HAL_TIMEOUT; 8003556: 2303 movs r3, #3 8003558: e06b b.n 8003632 while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != 0U) 800355a: 4b39 ldr r3, [pc, #228] ; (8003640 ) 800355c: 681b ldr r3, [r3, #0] 800355e: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 8003562: 2b00 cmp r3, #0 8003564: d1f0 bne.n 8003548 } } /* Get Start Tick */ tickstart = HAL_GetTick(); 8003566: f7fd fe83 bl 8001270 800356a: 6078 str r0, [r7, #4] /* Reset PLL3 bit */ CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON); 800356c: 4b34 ldr r3, [pc, #208] ; (8003640 ) 800356e: 681b ldr r3, [r3, #0] 8003570: 4a33 ldr r2, [pc, #204] ; (8003640 ) 8003572: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 8003576: 6013 str r3, [r2, #0] /* Wait till PLL3 is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != 0U) 8003578: e008 b.n 800358c { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800357a: f7fd fe79 bl 8001270 800357e: 4602 mov r2, r0 8003580: 687b ldr r3, [r7, #4] 8003582: 1ad3 subs r3, r2, r3 8003584: 2b02 cmp r3, #2 8003586: d901 bls.n 800358c { return HAL_TIMEOUT; 8003588: 2303 movs r3, #3 800358a: e052 b.n 8003632 while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != 0U) 800358c: 4b2c ldr r3, [pc, #176] ; (8003640 ) 800358e: 681b ldr r3, [r3, #0] 8003590: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 8003594: 2b00 cmp r3, #0 8003596: d1f0 bne.n 800357a } } #if defined(RCC_D1CFGR_HPRE) /* Reset D1CFGR register */ CLEAR_REG(RCC->D1CFGR); 8003598: 4b29 ldr r3, [pc, #164] ; (8003640 ) 800359a: 2200 movs r2, #0 800359c: 619a str r2, [r3, #24] /* Reset D2CFGR register */ CLEAR_REG(RCC->D2CFGR); 800359e: 4b28 ldr r3, [pc, #160] ; (8003640 ) 80035a0: 2200 movs r2, #0 80035a2: 61da str r2, [r3, #28] /* Reset D3CFGR register */ CLEAR_REG(RCC->D3CFGR); 80035a4: 4b26 ldr r3, [pc, #152] ; (8003640 ) 80035a6: 2200 movs r2, #0 80035a8: 621a str r2, [r3, #32] /* Reset SRDCFGR register */ CLEAR_REG(RCC->SRDCFGR); #endif /* Reset PLLCKSELR register to default value */ RCC->PLLCKSELR= RCC_PLLCKSELR_DIVM1_5|RCC_PLLCKSELR_DIVM2_5|RCC_PLLCKSELR_DIVM3_5; 80035aa: 4b25 ldr r3, [pc, #148] ; (8003640 ) 80035ac: 4a2a ldr r2, [pc, #168] ; (8003658 ) 80035ae: 629a str r2, [r3, #40] ; 0x28 /* Reset PLLCFGR register to default value */ WRITE_REG(RCC->PLLCFGR, 0x01FF0000U); 80035b0: 4b23 ldr r3, [pc, #140] ; (8003640 ) 80035b2: 4a2a ldr r2, [pc, #168] ; (800365c ) 80035b4: 62da str r2, [r3, #44] ; 0x2c /* Reset PLL1DIVR register to default value */ WRITE_REG(RCC->PLL1DIVR,0x01010280U); 80035b6: 4b22 ldr r3, [pc, #136] ; (8003640 ) 80035b8: 4a29 ldr r2, [pc, #164] ; (8003660 ) 80035ba: 631a str r2, [r3, #48] ; 0x30 /* Reset PLL1FRACR register */ CLEAR_REG(RCC->PLL1FRACR); 80035bc: 4b20 ldr r3, [pc, #128] ; (8003640 ) 80035be: 2200 movs r2, #0 80035c0: 635a str r2, [r3, #52] ; 0x34 /* Reset PLL2DIVR register to default value */ WRITE_REG(RCC->PLL2DIVR,0x01010280U); 80035c2: 4b1f ldr r3, [pc, #124] ; (8003640 ) 80035c4: 4a26 ldr r2, [pc, #152] ; (8003660 ) 80035c6: 639a str r2, [r3, #56] ; 0x38 /* Reset PLL2FRACR register */ CLEAR_REG(RCC->PLL2FRACR); 80035c8: 4b1d ldr r3, [pc, #116] ; (8003640 ) 80035ca: 2200 movs r2, #0 80035cc: 63da str r2, [r3, #60] ; 0x3c /* Reset PLL3DIVR register to default value */ WRITE_REG(RCC->PLL3DIVR,0x01010280U); 80035ce: 4b1c ldr r3, [pc, #112] ; (8003640 ) 80035d0: 4a23 ldr r2, [pc, #140] ; (8003660 ) 80035d2: 641a str r2, [r3, #64] ; 0x40 /* Reset PLL3FRACR register */ CLEAR_REG(RCC->PLL3FRACR); 80035d4: 4b1a ldr r3, [pc, #104] ; (8003640 ) 80035d6: 2200 movs r2, #0 80035d8: 645a str r2, [r3, #68] ; 0x44 /* Reset HSEEXT */ CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); #endif /* RCC_CR_HSEEXT */ /* Reset HSEBYP bit */ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); 80035da: 4b19 ldr r3, [pc, #100] ; (8003640 ) 80035dc: 681b ldr r3, [r3, #0] 80035de: 4a18 ldr r2, [pc, #96] ; (8003640 ) 80035e0: f423 2380 bic.w r3, r3, #262144 ; 0x40000 80035e4: 6013 str r3, [r2, #0] /* Disable all interrupts */ CLEAR_REG(RCC->CIER); 80035e6: 4b16 ldr r3, [pc, #88] ; (8003640 ) 80035e8: 2200 movs r2, #0 80035ea: 661a str r2, [r3, #96] ; 0x60 /* Clear all interrupts flags */ WRITE_REG(RCC->CICR,0xFFFFFFFFU); 80035ec: 4b14 ldr r3, [pc, #80] ; (8003640 ) 80035ee: f04f 32ff mov.w r2, #4294967295 80035f2: 669a str r2, [r3, #104] ; 0x68 /* Reset all RSR flags */ SET_BIT(RCC->RSR, RCC_RSR_RMVF); 80035f4: 4b12 ldr r3, [pc, #72] ; (8003640 ) 80035f6: f8d3 30d0 ldr.w r3, [r3, #208] ; 0xd0 80035fa: 4a11 ldr r2, [pc, #68] ; (8003640 ) 80035fc: f443 3380 orr.w r3, r3, #65536 ; 0x10000 8003600: f8c2 30d0 str.w r3, [r2, #208] ; 0xd0 /* Decreasing the number of wait states because of lower CPU frequency */ if(FLASH_LATENCY_DEFAULT < __HAL_FLASH_GET_LATENCY()) 8003604: 4b0d ldr r3, [pc, #52] ; (800363c ) 8003606: 681b ldr r3, [r3, #0] 8003608: f003 0308 and.w r3, r3, #8 800360c: 2b00 cmp r3, #0 800360e: d00f beq.n 8003630 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_DEFAULT); 8003610: 4b0a ldr r3, [pc, #40] ; (800363c ) 8003612: 681b ldr r3, [r3, #0] 8003614: f023 030f bic.w r3, r3, #15 8003618: 4a08 ldr r2, [pc, #32] ; (800363c ) 800361a: f043 0307 orr.w r3, r3, #7 800361e: 6013 str r3, [r2, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_DEFAULT) 8003620: 4b06 ldr r3, [pc, #24] ; (800363c ) 8003622: 681b ldr r3, [r3, #0] 8003624: f003 030f and.w r3, r3, #15 8003628: 2b07 cmp r3, #7 800362a: d001 beq.n 8003630 { return HAL_ERROR; 800362c: 2301 movs r3, #1 800362e: e000 b.n 8003632 } } return HAL_OK; 8003630: 2300 movs r3, #0 } 8003632: 4618 mov r0, r3 8003634: 3708 adds r7, #8 8003636: 46bd mov sp, r7 8003638: bd80 pop {r7, pc} 800363a: bf00 nop 800363c: 52002000 .word 0x52002000 8003640: 58024400 .word 0x58024400 8003644: 24000000 .word 0x24000000 8003648: 03d09000 .word 0x03d09000 800364c: 24000004 .word 0x24000004 8003650: 24000008 .word 0x24000008 8003654: fff6ed45 .word 0xfff6ed45 8003658: 02020200 .word 0x02020200 800365c: 01ff0000 .word 0x01ff0000 8003660: 01010280 .word 0x01010280 08003664 : * supported by this function. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 8003664: b580 push {r7, lr} 8003666: b08c sub sp, #48 ; 0x30 8003668: af00 add r7, sp, #0 800366a: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t temp1_pllckcfg, temp2_pllckcfg; /* Check Null pointer */ if(RCC_OscInitStruct == NULL) 800366c: 687b ldr r3, [r7, #4] 800366e: 2b00 cmp r3, #0 8003670: d102 bne.n 8003678 { return HAL_ERROR; 8003672: 2301 movs r3, #1 8003674: f000 bc1d b.w 8003eb2 } /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 8003678: 687b ldr r3, [r7, #4] 800367a: 681b ldr r3, [r3, #0] 800367c: f003 0301 and.w r3, r3, #1 8003680: 2b00 cmp r3, #0 8003682: f000 8087 beq.w 8003794 { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 8003686: 4b99 ldr r3, [pc, #612] ; (80038ec ) 8003688: 691b ldr r3, [r3, #16] 800368a: f003 0338 and.w r3, r3, #56 ; 0x38 800368e: 62fb str r3, [r7, #44] ; 0x2c const uint32_t temp_pllckselr = RCC->PLLCKSELR; 8003690: 4b96 ldr r3, [pc, #600] ; (80038ec ) 8003692: 6a9b ldr r3, [r3, #40] ; 0x28 8003694: 62bb str r3, [r7, #40] ; 0x28 /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */ if((temp_sysclksrc == RCC_CFGR_SWS_HSE) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSE))) 8003696: 6afb ldr r3, [r7, #44] ; 0x2c 8003698: 2b10 cmp r3, #16 800369a: d007 beq.n 80036ac 800369c: 6afb ldr r3, [r7, #44] ; 0x2c 800369e: 2b18 cmp r3, #24 80036a0: d110 bne.n 80036c4 80036a2: 6abb ldr r3, [r7, #40] ; 0x28 80036a4: f003 0303 and.w r3, r3, #3 80036a8: 2b02 cmp r3, #2 80036aa: d10b bne.n 80036c4 { if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 80036ac: 4b8f ldr r3, [pc, #572] ; (80038ec ) 80036ae: 681b ldr r3, [r3, #0] 80036b0: f403 3300 and.w r3, r3, #131072 ; 0x20000 80036b4: 2b00 cmp r3, #0 80036b6: d06c beq.n 8003792 80036b8: 687b ldr r3, [r7, #4] 80036ba: 685b ldr r3, [r3, #4] 80036bc: 2b00 cmp r3, #0 80036be: d168 bne.n 8003792 { return HAL_ERROR; 80036c0: 2301 movs r3, #1 80036c2: e3f6 b.n 8003eb2 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 80036c4: 687b ldr r3, [r7, #4] 80036c6: 685b ldr r3, [r3, #4] 80036c8: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 80036cc: d106 bne.n 80036dc 80036ce: 4b87 ldr r3, [pc, #540] ; (80038ec ) 80036d0: 681b ldr r3, [r3, #0] 80036d2: 4a86 ldr r2, [pc, #536] ; (80038ec ) 80036d4: f443 3380 orr.w r3, r3, #65536 ; 0x10000 80036d8: 6013 str r3, [r2, #0] 80036da: e02e b.n 800373a 80036dc: 687b ldr r3, [r7, #4] 80036de: 685b ldr r3, [r3, #4] 80036e0: 2b00 cmp r3, #0 80036e2: d10c bne.n 80036fe 80036e4: 4b81 ldr r3, [pc, #516] ; (80038ec ) 80036e6: 681b ldr r3, [r3, #0] 80036e8: 4a80 ldr r2, [pc, #512] ; (80038ec ) 80036ea: f423 3380 bic.w r3, r3, #65536 ; 0x10000 80036ee: 6013 str r3, [r2, #0] 80036f0: 4b7e ldr r3, [pc, #504] ; (80038ec ) 80036f2: 681b ldr r3, [r3, #0] 80036f4: 4a7d ldr r2, [pc, #500] ; (80038ec ) 80036f6: f423 2380 bic.w r3, r3, #262144 ; 0x40000 80036fa: 6013 str r3, [r2, #0] 80036fc: e01d b.n 800373a 80036fe: 687b ldr r3, [r7, #4] 8003700: 685b ldr r3, [r3, #4] 8003702: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 8003706: d10c bne.n 8003722 8003708: 4b78 ldr r3, [pc, #480] ; (80038ec ) 800370a: 681b ldr r3, [r3, #0] 800370c: 4a77 ldr r2, [pc, #476] ; (80038ec ) 800370e: f443 2380 orr.w r3, r3, #262144 ; 0x40000 8003712: 6013 str r3, [r2, #0] 8003714: 4b75 ldr r3, [pc, #468] ; (80038ec ) 8003716: 681b ldr r3, [r3, #0] 8003718: 4a74 ldr r2, [pc, #464] ; (80038ec ) 800371a: f443 3380 orr.w r3, r3, #65536 ; 0x10000 800371e: 6013 str r3, [r2, #0] 8003720: e00b b.n 800373a 8003722: 4b72 ldr r3, [pc, #456] ; (80038ec ) 8003724: 681b ldr r3, [r3, #0] 8003726: 4a71 ldr r2, [pc, #452] ; (80038ec ) 8003728: f423 3380 bic.w r3, r3, #65536 ; 0x10000 800372c: 6013 str r3, [r2, #0] 800372e: 4b6f ldr r3, [pc, #444] ; (80038ec ) 8003730: 681b ldr r3, [r3, #0] 8003732: 4a6e ldr r2, [pc, #440] ; (80038ec ) 8003734: f423 2380 bic.w r3, r3, #262144 ; 0x40000 8003738: 6013 str r3, [r2, #0] /* Check the HSE State */ if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 800373a: 687b ldr r3, [r7, #4] 800373c: 685b ldr r3, [r3, #4] 800373e: 2b00 cmp r3, #0 8003740: d013 beq.n 800376a { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003742: f7fd fd95 bl 8001270 8003746: 6278 str r0, [r7, #36] ; 0x24 /* Wait till HSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 8003748: e008 b.n 800375c { if((uint32_t) (HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) 800374a: f7fd fd91 bl 8001270 800374e: 4602 mov r2, r0 8003750: 6a7b ldr r3, [r7, #36] ; 0x24 8003752: 1ad3 subs r3, r2, r3 8003754: 2b64 cmp r3, #100 ; 0x64 8003756: d901 bls.n 800375c { return HAL_TIMEOUT; 8003758: 2303 movs r3, #3 800375a: e3aa b.n 8003eb2 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 800375c: 4b63 ldr r3, [pc, #396] ; (80038ec ) 800375e: 681b ldr r3, [r3, #0] 8003760: f403 3300 and.w r3, r3, #131072 ; 0x20000 8003764: 2b00 cmp r3, #0 8003766: d0f0 beq.n 800374a 8003768: e014 b.n 8003794 } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800376a: f7fd fd81 bl 8001270 800376e: 6278 str r0, [r7, #36] ; 0x24 /* Wait till HSE is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) 8003770: e008 b.n 8003784 { if((uint32_t) (HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) 8003772: f7fd fd7d bl 8001270 8003776: 4602 mov r2, r0 8003778: 6a7b ldr r3, [r7, #36] ; 0x24 800377a: 1ad3 subs r3, r2, r3 800377c: 2b64 cmp r3, #100 ; 0x64 800377e: d901 bls.n 8003784 { return HAL_TIMEOUT; 8003780: 2303 movs r3, #3 8003782: e396 b.n 8003eb2 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) 8003784: 4b59 ldr r3, [pc, #356] ; (80038ec ) 8003786: 681b ldr r3, [r3, #0] 8003788: f403 3300 and.w r3, r3, #131072 ; 0x20000 800378c: 2b00 cmp r3, #0 800378e: d1f0 bne.n 8003772 8003790: e000 b.n 8003794 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8003792: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 8003794: 687b ldr r3, [r7, #4] 8003796: 681b ldr r3, [r3, #0] 8003798: f003 0302 and.w r3, r3, #2 800379c: 2b00 cmp r3, #0 800379e: f000 80cb beq.w 8003938 /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_HSICALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* When the HSI is used as system clock it will not be disabled */ const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 80037a2: 4b52 ldr r3, [pc, #328] ; (80038ec ) 80037a4: 691b ldr r3, [r3, #16] 80037a6: f003 0338 and.w r3, r3, #56 ; 0x38 80037aa: 623b str r3, [r7, #32] const uint32_t temp_pllckselr = RCC->PLLCKSELR; 80037ac: 4b4f ldr r3, [pc, #316] ; (80038ec ) 80037ae: 6a9b ldr r3, [r3, #40] ; 0x28 80037b0: 61fb str r3, [r7, #28] if((temp_sysclksrc == RCC_CFGR_SWS_HSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSI))) 80037b2: 6a3b ldr r3, [r7, #32] 80037b4: 2b00 cmp r3, #0 80037b6: d007 beq.n 80037c8 80037b8: 6a3b ldr r3, [r7, #32] 80037ba: 2b18 cmp r3, #24 80037bc: d156 bne.n 800386c 80037be: 69fb ldr r3, [r7, #28] 80037c0: f003 0303 and.w r3, r3, #3 80037c4: 2b00 cmp r3, #0 80037c6: d151 bne.n 800386c { /* When HSI is used as system clock it will not be disabled */ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 80037c8: 4b48 ldr r3, [pc, #288] ; (80038ec ) 80037ca: 681b ldr r3, [r3, #0] 80037cc: f003 0304 and.w r3, r3, #4 80037d0: 2b00 cmp r3, #0 80037d2: d005 beq.n 80037e0 80037d4: 687b ldr r3, [r7, #4] 80037d6: 68db ldr r3, [r3, #12] 80037d8: 2b00 cmp r3, #0 80037da: d101 bne.n 80037e0 { return HAL_ERROR; 80037dc: 2301 movs r3, #1 80037de: e368 b.n 8003eb2 } /* Otherwise, only HSI division and calibration are allowed */ else { /* Enable the Internal High Speed oscillator (HSI, HSIDIV2, HSIDIV4, or HSIDIV8) */ __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState); 80037e0: 4b42 ldr r3, [pc, #264] ; (80038ec ) 80037e2: 681b ldr r3, [r3, #0] 80037e4: f023 0219 bic.w r2, r3, #25 80037e8: 687b ldr r3, [r7, #4] 80037ea: 68db ldr r3, [r3, #12] 80037ec: 493f ldr r1, [pc, #252] ; (80038ec ) 80037ee: 4313 orrs r3, r2 80037f0: 600b str r3, [r1, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80037f2: f7fd fd3d bl 8001270 80037f6: 6278 str r0, [r7, #36] ; 0x24 /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 80037f8: e008 b.n 800380c { if((uint32_t) (HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) 80037fa: f7fd fd39 bl 8001270 80037fe: 4602 mov r2, r0 8003800: 6a7b ldr r3, [r7, #36] ; 0x24 8003802: 1ad3 subs r3, r2, r3 8003804: 2b02 cmp r3, #2 8003806: d901 bls.n 800380c { return HAL_TIMEOUT; 8003808: 2303 movs r3, #3 800380a: e352 b.n 8003eb2 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 800380c: 4b37 ldr r3, [pc, #220] ; (80038ec ) 800380e: 681b ldr r3, [r3, #0] 8003810: f003 0304 and.w r3, r3, #4 8003814: 2b00 cmp r3, #0 8003816: d0f0 beq.n 80037fa } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8003818: f7fd fd5a bl 80012d0 800381c: 4603 mov r3, r0 800381e: f241 0203 movw r2, #4099 ; 0x1003 8003822: 4293 cmp r3, r2 8003824: d817 bhi.n 8003856 8003826: 687b ldr r3, [r7, #4] 8003828: 691b ldr r3, [r3, #16] 800382a: 2b40 cmp r3, #64 ; 0x40 800382c: d108 bne.n 8003840 800382e: 4b2f ldr r3, [pc, #188] ; (80038ec ) 8003830: 685b ldr r3, [r3, #4] 8003832: f423 337c bic.w r3, r3, #258048 ; 0x3f000 8003836: 4a2d ldr r2, [pc, #180] ; (80038ec ) 8003838: f443 3300 orr.w r3, r3, #131072 ; 0x20000 800383c: 6053 str r3, [r2, #4] if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 800383e: e07b b.n 8003938 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8003840: 4b2a ldr r3, [pc, #168] ; (80038ec ) 8003842: 685b ldr r3, [r3, #4] 8003844: f423 327c bic.w r2, r3, #258048 ; 0x3f000 8003848: 687b ldr r3, [r7, #4] 800384a: 691b ldr r3, [r3, #16] 800384c: 031b lsls r3, r3, #12 800384e: 4927 ldr r1, [pc, #156] ; (80038ec ) 8003850: 4313 orrs r3, r2 8003852: 604b str r3, [r1, #4] if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 8003854: e070 b.n 8003938 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8003856: 4b25 ldr r3, [pc, #148] ; (80038ec ) 8003858: 685b ldr r3, [r3, #4] 800385a: f023 42fe bic.w r2, r3, #2130706432 ; 0x7f000000 800385e: 687b ldr r3, [r7, #4] 8003860: 691b ldr r3, [r3, #16] 8003862: 061b lsls r3, r3, #24 8003864: 4921 ldr r1, [pc, #132] ; (80038ec ) 8003866: 4313 orrs r3, r2 8003868: 604b str r3, [r1, #4] if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 800386a: e065 b.n 8003938 } else { /* Check the HSI State */ if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF) 800386c: 687b ldr r3, [r7, #4] 800386e: 68db ldr r3, [r3, #12] 8003870: 2b00 cmp r3, #0 8003872: d048 beq.n 8003906 { /* Enable the Internal High Speed oscillator (HSI, HSIDIV2,HSIDIV4, or HSIDIV8) */ __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState); 8003874: 4b1d ldr r3, [pc, #116] ; (80038ec ) 8003876: 681b ldr r3, [r3, #0] 8003878: f023 0219 bic.w r2, r3, #25 800387c: 687b ldr r3, [r7, #4] 800387e: 68db ldr r3, [r3, #12] 8003880: 491a ldr r1, [pc, #104] ; (80038ec ) 8003882: 4313 orrs r3, r2 8003884: 600b str r3, [r1, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003886: f7fd fcf3 bl 8001270 800388a: 6278 str r0, [r7, #36] ; 0x24 /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 800388c: e008 b.n 80038a0 { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) 800388e: f7fd fcef bl 8001270 8003892: 4602 mov r2, r0 8003894: 6a7b ldr r3, [r7, #36] ; 0x24 8003896: 1ad3 subs r3, r2, r3 8003898: 2b02 cmp r3, #2 800389a: d901 bls.n 80038a0 { return HAL_TIMEOUT; 800389c: 2303 movs r3, #3 800389e: e308 b.n 8003eb2 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 80038a0: 4b12 ldr r3, [pc, #72] ; (80038ec ) 80038a2: 681b ldr r3, [r3, #0] 80038a4: f003 0304 and.w r3, r3, #4 80038a8: 2b00 cmp r3, #0 80038aa: d0f0 beq.n 800388e } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 80038ac: f7fd fd10 bl 80012d0 80038b0: 4603 mov r3, r0 80038b2: f241 0203 movw r2, #4099 ; 0x1003 80038b6: 4293 cmp r3, r2 80038b8: d81a bhi.n 80038f0 80038ba: 687b ldr r3, [r7, #4] 80038bc: 691b ldr r3, [r3, #16] 80038be: 2b40 cmp r3, #64 ; 0x40 80038c0: d108 bne.n 80038d4 80038c2: 4b0a ldr r3, [pc, #40] ; (80038ec ) 80038c4: 685b ldr r3, [r3, #4] 80038c6: f423 337c bic.w r3, r3, #258048 ; 0x3f000 80038ca: 4a08 ldr r2, [pc, #32] ; (80038ec ) 80038cc: f443 3300 orr.w r3, r3, #131072 ; 0x20000 80038d0: 6053 str r3, [r2, #4] 80038d2: e031 b.n 8003938 80038d4: 4b05 ldr r3, [pc, #20] ; (80038ec ) 80038d6: 685b ldr r3, [r3, #4] 80038d8: f423 327c bic.w r2, r3, #258048 ; 0x3f000 80038dc: 687b ldr r3, [r7, #4] 80038de: 691b ldr r3, [r3, #16] 80038e0: 031b lsls r3, r3, #12 80038e2: 4902 ldr r1, [pc, #8] ; (80038ec ) 80038e4: 4313 orrs r3, r2 80038e6: 604b str r3, [r1, #4] 80038e8: e026 b.n 8003938 80038ea: bf00 nop 80038ec: 58024400 .word 0x58024400 80038f0: 4b9a ldr r3, [pc, #616] ; (8003b5c ) 80038f2: 685b ldr r3, [r3, #4] 80038f4: f023 42fe bic.w r2, r3, #2130706432 ; 0x7f000000 80038f8: 687b ldr r3, [r7, #4] 80038fa: 691b ldr r3, [r3, #16] 80038fc: 061b lsls r3, r3, #24 80038fe: 4997 ldr r1, [pc, #604] ; (8003b5c ) 8003900: 4313 orrs r3, r2 8003902: 604b str r3, [r1, #4] 8003904: e018 b.n 8003938 } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 8003906: 4b95 ldr r3, [pc, #596] ; (8003b5c ) 8003908: 681b ldr r3, [r3, #0] 800390a: 4a94 ldr r2, [pc, #592] ; (8003b5c ) 800390c: f023 0301 bic.w r3, r3, #1 8003910: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003912: f7fd fcad bl 8001270 8003916: 6278 str r0, [r7, #36] ; 0x24 /* Wait till HSI is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) 8003918: e008 b.n 800392c { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) 800391a: f7fd fca9 bl 8001270 800391e: 4602 mov r2, r0 8003920: 6a7b ldr r3, [r7, #36] ; 0x24 8003922: 1ad3 subs r3, r2, r3 8003924: 2b02 cmp r3, #2 8003926: d901 bls.n 800392c { return HAL_TIMEOUT; 8003928: 2303 movs r3, #3 800392a: e2c2 b.n 8003eb2 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) 800392c: 4b8b ldr r3, [pc, #556] ; (8003b5c ) 800392e: 681b ldr r3, [r3, #0] 8003930: f003 0304 and.w r3, r3, #4 8003934: 2b00 cmp r3, #0 8003936: d1f0 bne.n 800391a } } } } /*----------------------------- CSI Configuration --------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI) 8003938: 687b ldr r3, [r7, #4] 800393a: 681b ldr r3, [r3, #0] 800393c: f003 0310 and.w r3, r3, #16 8003940: 2b00 cmp r3, #0 8003942: f000 80a9 beq.w 8003a98 /* Check the parameters */ assert_param(IS_RCC_CSI(RCC_OscInitStruct->CSIState)); assert_param(IS_RCC_CSICALIBRATION_VALUE(RCC_OscInitStruct->CSICalibrationValue)); /* When the CSI is used as system clock it will not disabled */ const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 8003946: 4b85 ldr r3, [pc, #532] ; (8003b5c ) 8003948: 691b ldr r3, [r3, #16] 800394a: f003 0338 and.w r3, r3, #56 ; 0x38 800394e: 61bb str r3, [r7, #24] const uint32_t temp_pllckselr = RCC->PLLCKSELR; 8003950: 4b82 ldr r3, [pc, #520] ; (8003b5c ) 8003952: 6a9b ldr r3, [r3, #40] ; 0x28 8003954: 617b str r3, [r7, #20] if((temp_sysclksrc == RCC_CFGR_SWS_CSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_CSI))) 8003956: 69bb ldr r3, [r7, #24] 8003958: 2b08 cmp r3, #8 800395a: d007 beq.n 800396c 800395c: 69bb ldr r3, [r7, #24] 800395e: 2b18 cmp r3, #24 8003960: d13a bne.n 80039d8 8003962: 697b ldr r3, [r7, #20] 8003964: f003 0303 and.w r3, r3, #3 8003968: 2b01 cmp r3, #1 800396a: d135 bne.n 80039d8 { /* When CSI is used as system clock it will not disabled */ if((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) 800396c: 4b7b ldr r3, [pc, #492] ; (8003b5c ) 800396e: 681b ldr r3, [r3, #0] 8003970: f403 7380 and.w r3, r3, #256 ; 0x100 8003974: 2b00 cmp r3, #0 8003976: d005 beq.n 8003984 8003978: 687b ldr r3, [r7, #4] 800397a: 69db ldr r3, [r3, #28] 800397c: 2b80 cmp r3, #128 ; 0x80 800397e: d001 beq.n 8003984 { return HAL_ERROR; 8003980: 2301 movs r3, #1 8003982: e296 b.n 8003eb2 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/ __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 8003984: f7fd fca4 bl 80012d0 8003988: 4603 mov r3, r0 800398a: f241 0203 movw r2, #4099 ; 0x1003 800398e: 4293 cmp r3, r2 8003990: d817 bhi.n 80039c2 8003992: 687b ldr r3, [r7, #4] 8003994: 6a1b ldr r3, [r3, #32] 8003996: 2b20 cmp r3, #32 8003998: d108 bne.n 80039ac 800399a: 4b70 ldr r3, [pc, #448] ; (8003b5c ) 800399c: 685b ldr r3, [r3, #4] 800399e: f023 43f8 bic.w r3, r3, #2080374784 ; 0x7c000000 80039a2: 4a6e ldr r2, [pc, #440] ; (8003b5c ) 80039a4: f043 4380 orr.w r3, r3, #1073741824 ; 0x40000000 80039a8: 6053 str r3, [r2, #4] if((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) 80039aa: e075 b.n 8003a98 __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 80039ac: 4b6b ldr r3, [pc, #428] ; (8003b5c ) 80039ae: 685b ldr r3, [r3, #4] 80039b0: f023 42f8 bic.w r2, r3, #2080374784 ; 0x7c000000 80039b4: 687b ldr r3, [r7, #4] 80039b6: 6a1b ldr r3, [r3, #32] 80039b8: 069b lsls r3, r3, #26 80039ba: 4968 ldr r1, [pc, #416] ; (8003b5c ) 80039bc: 4313 orrs r3, r2 80039be: 604b str r3, [r1, #4] if((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) 80039c0: e06a b.n 8003a98 __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 80039c2: 4b66 ldr r3, [pc, #408] ; (8003b5c ) 80039c4: 68db ldr r3, [r3, #12] 80039c6: f023 527c bic.w r2, r3, #1056964608 ; 0x3f000000 80039ca: 687b ldr r3, [r7, #4] 80039cc: 6a1b ldr r3, [r3, #32] 80039ce: 061b lsls r3, r3, #24 80039d0: 4962 ldr r1, [pc, #392] ; (8003b5c ) 80039d2: 4313 orrs r3, r2 80039d4: 60cb str r3, [r1, #12] if((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) 80039d6: e05f b.n 8003a98 } } else { /* Check the CSI State */ if((RCC_OscInitStruct->CSIState)!= RCC_CSI_OFF) 80039d8: 687b ldr r3, [r7, #4] 80039da: 69db ldr r3, [r3, #28] 80039dc: 2b00 cmp r3, #0 80039de: d042 beq.n 8003a66 { /* Enable the Internal High Speed oscillator (CSI). */ __HAL_RCC_CSI_ENABLE(); 80039e0: 4b5e ldr r3, [pc, #376] ; (8003b5c ) 80039e2: 681b ldr r3, [r3, #0] 80039e4: 4a5d ldr r2, [pc, #372] ; (8003b5c ) 80039e6: f043 0380 orr.w r3, r3, #128 ; 0x80 80039ea: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80039ec: f7fd fc40 bl 8001270 80039f0: 6278 str r0, [r7, #36] ; 0x24 /* Wait till CSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) 80039f2: e008 b.n 8003a06 { if((HAL_GetTick() - tickstart ) > CSI_TIMEOUT_VALUE) 80039f4: f7fd fc3c bl 8001270 80039f8: 4602 mov r2, r0 80039fa: 6a7b ldr r3, [r7, #36] ; 0x24 80039fc: 1ad3 subs r3, r2, r3 80039fe: 2b02 cmp r3, #2 8003a00: d901 bls.n 8003a06 { return HAL_TIMEOUT; 8003a02: 2303 movs r3, #3 8003a04: e255 b.n 8003eb2 while(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) 8003a06: 4b55 ldr r3, [pc, #340] ; (8003b5c ) 8003a08: 681b ldr r3, [r3, #0] 8003a0a: f403 7380 and.w r3, r3, #256 ; 0x100 8003a0e: 2b00 cmp r3, #0 8003a10: d0f0 beq.n 80039f4 } } /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/ __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 8003a12: f7fd fc5d bl 80012d0 8003a16: 4603 mov r3, r0 8003a18: f241 0203 movw r2, #4099 ; 0x1003 8003a1c: 4293 cmp r3, r2 8003a1e: d817 bhi.n 8003a50 8003a20: 687b ldr r3, [r7, #4] 8003a22: 6a1b ldr r3, [r3, #32] 8003a24: 2b20 cmp r3, #32 8003a26: d108 bne.n 8003a3a 8003a28: 4b4c ldr r3, [pc, #304] ; (8003b5c ) 8003a2a: 685b ldr r3, [r3, #4] 8003a2c: f023 43f8 bic.w r3, r3, #2080374784 ; 0x7c000000 8003a30: 4a4a ldr r2, [pc, #296] ; (8003b5c ) 8003a32: f043 4380 orr.w r3, r3, #1073741824 ; 0x40000000 8003a36: 6053 str r3, [r2, #4] 8003a38: e02e b.n 8003a98 8003a3a: 4b48 ldr r3, [pc, #288] ; (8003b5c ) 8003a3c: 685b ldr r3, [r3, #4] 8003a3e: f023 42f8 bic.w r2, r3, #2080374784 ; 0x7c000000 8003a42: 687b ldr r3, [r7, #4] 8003a44: 6a1b ldr r3, [r3, #32] 8003a46: 069b lsls r3, r3, #26 8003a48: 4944 ldr r1, [pc, #272] ; (8003b5c ) 8003a4a: 4313 orrs r3, r2 8003a4c: 604b str r3, [r1, #4] 8003a4e: e023 b.n 8003a98 8003a50: 4b42 ldr r3, [pc, #264] ; (8003b5c ) 8003a52: 68db ldr r3, [r3, #12] 8003a54: f023 527c bic.w r2, r3, #1056964608 ; 0x3f000000 8003a58: 687b ldr r3, [r7, #4] 8003a5a: 6a1b ldr r3, [r3, #32] 8003a5c: 061b lsls r3, r3, #24 8003a5e: 493f ldr r1, [pc, #252] ; (8003b5c ) 8003a60: 4313 orrs r3, r2 8003a62: 60cb str r3, [r1, #12] 8003a64: e018 b.n 8003a98 } else { /* Disable the Internal High Speed oscillator (CSI). */ __HAL_RCC_CSI_DISABLE(); 8003a66: 4b3d ldr r3, [pc, #244] ; (8003b5c ) 8003a68: 681b ldr r3, [r3, #0] 8003a6a: 4a3c ldr r2, [pc, #240] ; (8003b5c ) 8003a6c: f023 0380 bic.w r3, r3, #128 ; 0x80 8003a70: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003a72: f7fd fbfd bl 8001270 8003a76: 6278 str r0, [r7, #36] ; 0x24 /* Wait till CSI is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) 8003a78: e008 b.n 8003a8c { if((HAL_GetTick() - tickstart ) > CSI_TIMEOUT_VALUE) 8003a7a: f7fd fbf9 bl 8001270 8003a7e: 4602 mov r2, r0 8003a80: 6a7b ldr r3, [r7, #36] ; 0x24 8003a82: 1ad3 subs r3, r2, r3 8003a84: 2b02 cmp r3, #2 8003a86: d901 bls.n 8003a8c { return HAL_TIMEOUT; 8003a88: 2303 movs r3, #3 8003a8a: e212 b.n 8003eb2 while(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) 8003a8c: 4b33 ldr r3, [pc, #204] ; (8003b5c ) 8003a8e: 681b ldr r3, [r3, #0] 8003a90: f403 7380 and.w r3, r3, #256 ; 0x100 8003a94: 2b00 cmp r3, #0 8003a96: d1f0 bne.n 8003a7a } } } } /*------------------------------ LSI Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 8003a98: 687b ldr r3, [r7, #4] 8003a9a: 681b ldr r3, [r3, #0] 8003a9c: f003 0308 and.w r3, r3, #8 8003aa0: 2b00 cmp r3, #0 8003aa2: d036 beq.n 8003b12 { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF) 8003aa4: 687b ldr r3, [r7, #4] 8003aa6: 695b ldr r3, [r3, #20] 8003aa8: 2b00 cmp r3, #0 8003aaa: d019 beq.n 8003ae0 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 8003aac: 4b2b ldr r3, [pc, #172] ; (8003b5c ) 8003aae: 6f5b ldr r3, [r3, #116] ; 0x74 8003ab0: 4a2a ldr r2, [pc, #168] ; (8003b5c ) 8003ab2: f043 0301 orr.w r3, r3, #1 8003ab6: 6753 str r3, [r2, #116] ; 0x74 /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003ab8: f7fd fbda bl 8001270 8003abc: 6278 str r0, [r7, #36] ; 0x24 /* Wait till LSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) 8003abe: e008 b.n 8003ad2 { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) 8003ac0: f7fd fbd6 bl 8001270 8003ac4: 4602 mov r2, r0 8003ac6: 6a7b ldr r3, [r7, #36] ; 0x24 8003ac8: 1ad3 subs r3, r2, r3 8003aca: 2b02 cmp r3, #2 8003acc: d901 bls.n 8003ad2 { return HAL_TIMEOUT; 8003ace: 2303 movs r3, #3 8003ad0: e1ef b.n 8003eb2 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) 8003ad2: 4b22 ldr r3, [pc, #136] ; (8003b5c ) 8003ad4: 6f5b ldr r3, [r3, #116] ; 0x74 8003ad6: f003 0302 and.w r3, r3, #2 8003ada: 2b00 cmp r3, #0 8003adc: d0f0 beq.n 8003ac0 8003ade: e018 b.n 8003b12 } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 8003ae0: 4b1e ldr r3, [pc, #120] ; (8003b5c ) 8003ae2: 6f5b ldr r3, [r3, #116] ; 0x74 8003ae4: 4a1d ldr r2, [pc, #116] ; (8003b5c ) 8003ae6: f023 0301 bic.w r3, r3, #1 8003aea: 6753 str r3, [r2, #116] ; 0x74 /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003aec: f7fd fbc0 bl 8001270 8003af0: 6278 str r0, [r7, #36] ; 0x24 /* Wait till LSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) 8003af2: e008 b.n 8003b06 { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) 8003af4: f7fd fbbc bl 8001270 8003af8: 4602 mov r2, r0 8003afa: 6a7b ldr r3, [r7, #36] ; 0x24 8003afc: 1ad3 subs r3, r2, r3 8003afe: 2b02 cmp r3, #2 8003b00: d901 bls.n 8003b06 { return HAL_TIMEOUT; 8003b02: 2303 movs r3, #3 8003b04: e1d5 b.n 8003eb2 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) 8003b06: 4b15 ldr r3, [pc, #84] ; (8003b5c ) 8003b08: 6f5b ldr r3, [r3, #116] ; 0x74 8003b0a: f003 0302 and.w r3, r3, #2 8003b0e: 2b00 cmp r3, #0 8003b10: d1f0 bne.n 8003af4 } } } /*------------------------------ HSI48 Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) 8003b12: 687b ldr r3, [r7, #4] 8003b14: 681b ldr r3, [r3, #0] 8003b16: f003 0320 and.w r3, r3, #32 8003b1a: 2b00 cmp r3, #0 8003b1c: d039 beq.n 8003b92 { /* Check the parameters */ assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); /* Check the HSI48 State */ if((RCC_OscInitStruct->HSI48State)!= RCC_HSI48_OFF) 8003b1e: 687b ldr r3, [r7, #4] 8003b20: 699b ldr r3, [r3, #24] 8003b22: 2b00 cmp r3, #0 8003b24: d01c beq.n 8003b60 { /* Enable the Internal Low Speed oscillator (HSI48). */ __HAL_RCC_HSI48_ENABLE(); 8003b26: 4b0d ldr r3, [pc, #52] ; (8003b5c ) 8003b28: 681b ldr r3, [r3, #0] 8003b2a: 4a0c ldr r2, [pc, #48] ; (8003b5c ) 8003b2c: f443 5380 orr.w r3, r3, #4096 ; 0x1000 8003b30: 6013 str r3, [r2, #0] /* Get time-out */ tickstart = HAL_GetTick(); 8003b32: f7fd fb9d bl 8001270 8003b36: 6278 str r0, [r7, #36] ; 0x24 /* Wait till HSI48 is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U) 8003b38: e008 b.n 8003b4c { if((HAL_GetTick() - tickstart ) > HSI48_TIMEOUT_VALUE) 8003b3a: f7fd fb99 bl 8001270 8003b3e: 4602 mov r2, r0 8003b40: 6a7b ldr r3, [r7, #36] ; 0x24 8003b42: 1ad3 subs r3, r2, r3 8003b44: 2b02 cmp r3, #2 8003b46: d901 bls.n 8003b4c { return HAL_TIMEOUT; 8003b48: 2303 movs r3, #3 8003b4a: e1b2 b.n 8003eb2 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U) 8003b4c: 4b03 ldr r3, [pc, #12] ; (8003b5c ) 8003b4e: 681b ldr r3, [r3, #0] 8003b50: f403 5300 and.w r3, r3, #8192 ; 0x2000 8003b54: 2b00 cmp r3, #0 8003b56: d0f0 beq.n 8003b3a 8003b58: e01b b.n 8003b92 8003b5a: bf00 nop 8003b5c: 58024400 .word 0x58024400 } } else { /* Disable the Internal Low Speed oscillator (HSI48). */ __HAL_RCC_HSI48_DISABLE(); 8003b60: 4b9b ldr r3, [pc, #620] ; (8003dd0 ) 8003b62: 681b ldr r3, [r3, #0] 8003b64: 4a9a ldr r2, [pc, #616] ; (8003dd0 ) 8003b66: f423 5380 bic.w r3, r3, #4096 ; 0x1000 8003b6a: 6013 str r3, [r2, #0] /* Get time-out */ tickstart = HAL_GetTick(); 8003b6c: f7fd fb80 bl 8001270 8003b70: 6278 str r0, [r7, #36] ; 0x24 /* Wait till HSI48 is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U) 8003b72: e008 b.n 8003b86 { if((HAL_GetTick() - tickstart ) > HSI48_TIMEOUT_VALUE) 8003b74: f7fd fb7c bl 8001270 8003b78: 4602 mov r2, r0 8003b7a: 6a7b ldr r3, [r7, #36] ; 0x24 8003b7c: 1ad3 subs r3, r2, r3 8003b7e: 2b02 cmp r3, #2 8003b80: d901 bls.n 8003b86 { return HAL_TIMEOUT; 8003b82: 2303 movs r3, #3 8003b84: e195 b.n 8003eb2 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U) 8003b86: 4b92 ldr r3, [pc, #584] ; (8003dd0 ) 8003b88: 681b ldr r3, [r3, #0] 8003b8a: f403 5300 and.w r3, r3, #8192 ; 0x2000 8003b8e: 2b00 cmp r3, #0 8003b90: d1f0 bne.n 8003b74 } } } } /*------------------------------ LSE Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 8003b92: 687b ldr r3, [r7, #4] 8003b94: 681b ldr r3, [r3, #0] 8003b96: f003 0304 and.w r3, r3, #4 8003b9a: 2b00 cmp r3, #0 8003b9c: f000 8081 beq.w 8003ca2 { /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Enable write access to Backup domain */ PWR->CR1 |= PWR_CR1_DBP; 8003ba0: 4b8c ldr r3, [pc, #560] ; (8003dd4 ) 8003ba2: 681b ldr r3, [r3, #0] 8003ba4: 4a8b ldr r2, [pc, #556] ; (8003dd4 ) 8003ba6: f443 7380 orr.w r3, r3, #256 ; 0x100 8003baa: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8003bac: f7fd fb60 bl 8001270 8003bb0: 6278 str r0, [r7, #36] ; 0x24 while((PWR->CR1 & PWR_CR1_DBP) == 0U) 8003bb2: e008 b.n 8003bc6 { if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) 8003bb4: f7fd fb5c bl 8001270 8003bb8: 4602 mov r2, r0 8003bba: 6a7b ldr r3, [r7, #36] ; 0x24 8003bbc: 1ad3 subs r3, r2, r3 8003bbe: 2b64 cmp r3, #100 ; 0x64 8003bc0: d901 bls.n 8003bc6 { return HAL_TIMEOUT; 8003bc2: 2303 movs r3, #3 8003bc4: e175 b.n 8003eb2 while((PWR->CR1 & PWR_CR1_DBP) == 0U) 8003bc6: 4b83 ldr r3, [pc, #524] ; (8003dd4 ) 8003bc8: 681b ldr r3, [r3, #0] 8003bca: f403 7380 and.w r3, r3, #256 ; 0x100 8003bce: 2b00 cmp r3, #0 8003bd0: d0f0 beq.n 8003bb4 } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8003bd2: 687b ldr r3, [r7, #4] 8003bd4: 689b ldr r3, [r3, #8] 8003bd6: 2b01 cmp r3, #1 8003bd8: d106 bne.n 8003be8 8003bda: 4b7d ldr r3, [pc, #500] ; (8003dd0 ) 8003bdc: 6f1b ldr r3, [r3, #112] ; 0x70 8003bde: 4a7c ldr r2, [pc, #496] ; (8003dd0 ) 8003be0: f043 0301 orr.w r3, r3, #1 8003be4: 6713 str r3, [r2, #112] ; 0x70 8003be6: e02d b.n 8003c44 8003be8: 687b ldr r3, [r7, #4] 8003bea: 689b ldr r3, [r3, #8] 8003bec: 2b00 cmp r3, #0 8003bee: d10c bne.n 8003c0a 8003bf0: 4b77 ldr r3, [pc, #476] ; (8003dd0 ) 8003bf2: 6f1b ldr r3, [r3, #112] ; 0x70 8003bf4: 4a76 ldr r2, [pc, #472] ; (8003dd0 ) 8003bf6: f023 0301 bic.w r3, r3, #1 8003bfa: 6713 str r3, [r2, #112] ; 0x70 8003bfc: 4b74 ldr r3, [pc, #464] ; (8003dd0 ) 8003bfe: 6f1b ldr r3, [r3, #112] ; 0x70 8003c00: 4a73 ldr r2, [pc, #460] ; (8003dd0 ) 8003c02: f023 0304 bic.w r3, r3, #4 8003c06: 6713 str r3, [r2, #112] ; 0x70 8003c08: e01c b.n 8003c44 8003c0a: 687b ldr r3, [r7, #4] 8003c0c: 689b ldr r3, [r3, #8] 8003c0e: 2b05 cmp r3, #5 8003c10: d10c bne.n 8003c2c 8003c12: 4b6f ldr r3, [pc, #444] ; (8003dd0 ) 8003c14: 6f1b ldr r3, [r3, #112] ; 0x70 8003c16: 4a6e ldr r2, [pc, #440] ; (8003dd0 ) 8003c18: f043 0304 orr.w r3, r3, #4 8003c1c: 6713 str r3, [r2, #112] ; 0x70 8003c1e: 4b6c ldr r3, [pc, #432] ; (8003dd0 ) 8003c20: 6f1b ldr r3, [r3, #112] ; 0x70 8003c22: 4a6b ldr r2, [pc, #428] ; (8003dd0 ) 8003c24: f043 0301 orr.w r3, r3, #1 8003c28: 6713 str r3, [r2, #112] ; 0x70 8003c2a: e00b b.n 8003c44 8003c2c: 4b68 ldr r3, [pc, #416] ; (8003dd0 ) 8003c2e: 6f1b ldr r3, [r3, #112] ; 0x70 8003c30: 4a67 ldr r2, [pc, #412] ; (8003dd0 ) 8003c32: f023 0301 bic.w r3, r3, #1 8003c36: 6713 str r3, [r2, #112] ; 0x70 8003c38: 4b65 ldr r3, [pc, #404] ; (8003dd0 ) 8003c3a: 6f1b ldr r3, [r3, #112] ; 0x70 8003c3c: 4a64 ldr r2, [pc, #400] ; (8003dd0 ) 8003c3e: f023 0304 bic.w r3, r3, #4 8003c42: 6713 str r3, [r2, #112] ; 0x70 /* Check the LSE State */ if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) 8003c44: 687b ldr r3, [r7, #4] 8003c46: 689b ldr r3, [r3, #8] 8003c48: 2b00 cmp r3, #0 8003c4a: d015 beq.n 8003c78 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003c4c: f7fd fb10 bl 8001270 8003c50: 6278 str r0, [r7, #36] ; 0x24 /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 8003c52: e00a b.n 8003c6a { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) 8003c54: f7fd fb0c bl 8001270 8003c58: 4602 mov r2, r0 8003c5a: 6a7b ldr r3, [r7, #36] ; 0x24 8003c5c: 1ad3 subs r3, r2, r3 8003c5e: f241 3288 movw r2, #5000 ; 0x1388 8003c62: 4293 cmp r3, r2 8003c64: d901 bls.n 8003c6a { return HAL_TIMEOUT; 8003c66: 2303 movs r3, #3 8003c68: e123 b.n 8003eb2 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 8003c6a: 4b59 ldr r3, [pc, #356] ; (8003dd0 ) 8003c6c: 6f1b ldr r3, [r3, #112] ; 0x70 8003c6e: f003 0302 and.w r3, r3, #2 8003c72: 2b00 cmp r3, #0 8003c74: d0ee beq.n 8003c54 8003c76: e014 b.n 8003ca2 } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003c78: f7fd fafa bl 8001270 8003c7c: 6278 str r0, [r7, #36] ; 0x24 /* Wait till LSE is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) 8003c7e: e00a b.n 8003c96 { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) 8003c80: f7fd faf6 bl 8001270 8003c84: 4602 mov r2, r0 8003c86: 6a7b ldr r3, [r7, #36] ; 0x24 8003c88: 1ad3 subs r3, r2, r3 8003c8a: f241 3288 movw r2, #5000 ; 0x1388 8003c8e: 4293 cmp r3, r2 8003c90: d901 bls.n 8003c96 { return HAL_TIMEOUT; 8003c92: 2303 movs r3, #3 8003c94: e10d b.n 8003eb2 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) 8003c96: 4b4e ldr r3, [pc, #312] ; (8003dd0 ) 8003c98: 6f1b ldr r3, [r3, #112] ; 0x70 8003c9a: f003 0302 and.w r3, r3, #2 8003c9e: 2b00 cmp r3, #0 8003ca0: d1ee bne.n 8003c80 } } /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 8003ca2: 687b ldr r3, [r7, #4] 8003ca4: 6a5b ldr r3, [r3, #36] ; 0x24 8003ca6: 2b00 cmp r3, #0 8003ca8: f000 8102 beq.w 8003eb0 { /* Check if the PLL is used as system clock or not */ if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL1) 8003cac: 4b48 ldr r3, [pc, #288] ; (8003dd0 ) 8003cae: 691b ldr r3, [r3, #16] 8003cb0: f003 0338 and.w r3, r3, #56 ; 0x38 8003cb4: 2b18 cmp r3, #24 8003cb6: f000 80bd beq.w 8003e34 { if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 8003cba: 687b ldr r3, [r7, #4] 8003cbc: 6a5b ldr r3, [r3, #36] ; 0x24 8003cbe: 2b02 cmp r3, #2 8003cc0: f040 809e bne.w 8003e00 assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8003cc4: 4b42 ldr r3, [pc, #264] ; (8003dd0 ) 8003cc6: 681b ldr r3, [r3, #0] 8003cc8: 4a41 ldr r2, [pc, #260] ; (8003dd0 ) 8003cca: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000 8003cce: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003cd0: f7fd face bl 8001270 8003cd4: 6278 str r0, [r7, #36] ; 0x24 /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 8003cd6: e008 b.n 8003cea { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 8003cd8: f7fd faca bl 8001270 8003cdc: 4602 mov r2, r0 8003cde: 6a7b ldr r3, [r7, #36] ; 0x24 8003ce0: 1ad3 subs r3, r2, r3 8003ce2: 2b02 cmp r3, #2 8003ce4: d901 bls.n 8003cea { return HAL_TIMEOUT; 8003ce6: 2303 movs r3, #3 8003ce8: e0e3 b.n 8003eb2 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 8003cea: 4b39 ldr r3, [pc, #228] ; (8003dd0 ) 8003cec: 681b ldr r3, [r3, #0] 8003cee: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8003cf2: 2b00 cmp r3, #0 8003cf4: d1f0 bne.n 8003cd8 } } /* Configure the main PLL clock source, multiplication and division factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 8003cf6: 4b36 ldr r3, [pc, #216] ; (8003dd0 ) 8003cf8: 6a9a ldr r2, [r3, #40] ; 0x28 8003cfa: 4b37 ldr r3, [pc, #220] ; (8003dd8 ) 8003cfc: 4013 ands r3, r2 8003cfe: 687a ldr r2, [r7, #4] 8003d00: 6a91 ldr r1, [r2, #40] ; 0x28 8003d02: 687a ldr r2, [r7, #4] 8003d04: 6ad2 ldr r2, [r2, #44] ; 0x2c 8003d06: 0112 lsls r2, r2, #4 8003d08: 430a orrs r2, r1 8003d0a: 4931 ldr r1, [pc, #196] ; (8003dd0 ) 8003d0c: 4313 orrs r3, r2 8003d0e: 628b str r3, [r1, #40] ; 0x28 8003d10: 687b ldr r3, [r7, #4] 8003d12: 6b1b ldr r3, [r3, #48] ; 0x30 8003d14: 3b01 subs r3, #1 8003d16: f3c3 0208 ubfx r2, r3, #0, #9 8003d1a: 687b ldr r3, [r7, #4] 8003d1c: 6b5b ldr r3, [r3, #52] ; 0x34 8003d1e: 3b01 subs r3, #1 8003d20: 025b lsls r3, r3, #9 8003d22: b29b uxth r3, r3 8003d24: 431a orrs r2, r3 8003d26: 687b ldr r3, [r7, #4] 8003d28: 6b9b ldr r3, [r3, #56] ; 0x38 8003d2a: 3b01 subs r3, #1 8003d2c: 041b lsls r3, r3, #16 8003d2e: f403 03fe and.w r3, r3, #8323072 ; 0x7f0000 8003d32: 431a orrs r2, r3 8003d34: 687b ldr r3, [r7, #4] 8003d36: 6bdb ldr r3, [r3, #60] ; 0x3c 8003d38: 3b01 subs r3, #1 8003d3a: 061b lsls r3, r3, #24 8003d3c: f003 43fe and.w r3, r3, #2130706432 ; 0x7f000000 8003d40: 4923 ldr r1, [pc, #140] ; (8003dd0 ) 8003d42: 4313 orrs r3, r2 8003d44: 630b str r3, [r1, #48] ; 0x30 RCC_OscInitStruct->PLL.PLLP, RCC_OscInitStruct->PLL.PLLQ, RCC_OscInitStruct->PLL.PLLR); /* Disable PLLFRACN . */ __HAL_RCC_PLLFRACN_DISABLE(); 8003d46: 4b22 ldr r3, [pc, #136] ; (8003dd0 ) 8003d48: 6adb ldr r3, [r3, #44] ; 0x2c 8003d4a: 4a21 ldr r2, [pc, #132] ; (8003dd0 ) 8003d4c: f023 0301 bic.w r3, r3, #1 8003d50: 62d3 str r3, [r2, #44] ; 0x2c /* Configure PLL PLL1FRACN */ __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN); 8003d52: 4b1f ldr r3, [pc, #124] ; (8003dd0 ) 8003d54: 6b5a ldr r2, [r3, #52] ; 0x34 8003d56: 4b21 ldr r3, [pc, #132] ; (8003ddc ) 8003d58: 4013 ands r3, r2 8003d5a: 687a ldr r2, [r7, #4] 8003d5c: 6c92 ldr r2, [r2, #72] ; 0x48 8003d5e: 00d2 lsls r2, r2, #3 8003d60: 491b ldr r1, [pc, #108] ; (8003dd0 ) 8003d62: 4313 orrs r3, r2 8003d64: 634b str r3, [r1, #52] ; 0x34 /* Select PLL1 input reference frequency range: VCI */ __HAL_RCC_PLL_VCIRANGE(RCC_OscInitStruct->PLL.PLLRGE) ; 8003d66: 4b1a ldr r3, [pc, #104] ; (8003dd0 ) 8003d68: 6adb ldr r3, [r3, #44] ; 0x2c 8003d6a: f023 020c bic.w r2, r3, #12 8003d6e: 687b ldr r3, [r7, #4] 8003d70: 6c1b ldr r3, [r3, #64] ; 0x40 8003d72: 4917 ldr r1, [pc, #92] ; (8003dd0 ) 8003d74: 4313 orrs r3, r2 8003d76: 62cb str r3, [r1, #44] ; 0x2c /* Select PLL1 output frequency range : VCO */ __HAL_RCC_PLL_VCORANGE(RCC_OscInitStruct->PLL.PLLVCOSEL) ; 8003d78: 4b15 ldr r3, [pc, #84] ; (8003dd0 ) 8003d7a: 6adb ldr r3, [r3, #44] ; 0x2c 8003d7c: f023 0202 bic.w r2, r3, #2 8003d80: 687b ldr r3, [r7, #4] 8003d82: 6c5b ldr r3, [r3, #68] ; 0x44 8003d84: 4912 ldr r1, [pc, #72] ; (8003dd0 ) 8003d86: 4313 orrs r3, r2 8003d88: 62cb str r3, [r1, #44] ; 0x2c /* Enable PLL System Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP); 8003d8a: 4b11 ldr r3, [pc, #68] ; (8003dd0 ) 8003d8c: 6adb ldr r3, [r3, #44] ; 0x2c 8003d8e: 4a10 ldr r2, [pc, #64] ; (8003dd0 ) 8003d90: f443 3380 orr.w r3, r3, #65536 ; 0x10000 8003d94: 62d3 str r3, [r2, #44] ; 0x2c /* Enable PLL1Q Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8003d96: 4b0e ldr r3, [pc, #56] ; (8003dd0 ) 8003d98: 6adb ldr r3, [r3, #44] ; 0x2c 8003d9a: 4a0d ldr r2, [pc, #52] ; (8003dd0 ) 8003d9c: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8003da0: 62d3 str r3, [r2, #44] ; 0x2c /* Enable PLL1R Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR); 8003da2: 4b0b ldr r3, [pc, #44] ; (8003dd0 ) 8003da4: 6adb ldr r3, [r3, #44] ; 0x2c 8003da6: 4a0a ldr r2, [pc, #40] ; (8003dd0 ) 8003da8: f443 2380 orr.w r3, r3, #262144 ; 0x40000 8003dac: 62d3 str r3, [r2, #44] ; 0x2c /* Enable PLL1FRACN . */ __HAL_RCC_PLLFRACN_ENABLE(); 8003dae: 4b08 ldr r3, [pc, #32] ; (8003dd0 ) 8003db0: 6adb ldr r3, [r3, #44] ; 0x2c 8003db2: 4a07 ldr r2, [pc, #28] ; (8003dd0 ) 8003db4: f043 0301 orr.w r3, r3, #1 8003db8: 62d3 str r3, [r2, #44] ; 0x2c /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 8003dba: 4b05 ldr r3, [pc, #20] ; (8003dd0 ) 8003dbc: 681b ldr r3, [r3, #0] 8003dbe: 4a04 ldr r2, [pc, #16] ; (8003dd0 ) 8003dc0: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 8003dc4: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003dc6: f7fd fa53 bl 8001270 8003dca: 6278 str r0, [r7, #36] ; 0x24 /* Wait till PLL is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) 8003dcc: e011 b.n 8003df2 8003dce: bf00 nop 8003dd0: 58024400 .word 0x58024400 8003dd4: 58024800 .word 0x58024800 8003dd8: fffffc0c .word 0xfffffc0c 8003ddc: ffff0007 .word 0xffff0007 { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 8003de0: f7fd fa46 bl 8001270 8003de4: 4602 mov r2, r0 8003de6: 6a7b ldr r3, [r7, #36] ; 0x24 8003de8: 1ad3 subs r3, r2, r3 8003dea: 2b02 cmp r3, #2 8003dec: d901 bls.n 8003df2 { return HAL_TIMEOUT; 8003dee: 2303 movs r3, #3 8003df0: e05f b.n 8003eb2 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) 8003df2: 4b32 ldr r3, [pc, #200] ; (8003ebc ) 8003df4: 681b ldr r3, [r3, #0] 8003df6: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8003dfa: 2b00 cmp r3, #0 8003dfc: d0f0 beq.n 8003de0 8003dfe: e057 b.n 8003eb0 } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8003e00: 4b2e ldr r3, [pc, #184] ; (8003ebc ) 8003e02: 681b ldr r3, [r3, #0] 8003e04: 4a2d ldr r2, [pc, #180] ; (8003ebc ) 8003e06: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000 8003e0a: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003e0c: f7fd fa30 bl 8001270 8003e10: 6278 str r0, [r7, #36] ; 0x24 /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 8003e12: e008 b.n 8003e26 { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 8003e14: f7fd fa2c bl 8001270 8003e18: 4602 mov r2, r0 8003e1a: 6a7b ldr r3, [r7, #36] ; 0x24 8003e1c: 1ad3 subs r3, r2, r3 8003e1e: 2b02 cmp r3, #2 8003e20: d901 bls.n 8003e26 { return HAL_TIMEOUT; 8003e22: 2303 movs r3, #3 8003e24: e045 b.n 8003eb2 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 8003e26: 4b25 ldr r3, [pc, #148] ; (8003ebc ) 8003e28: 681b ldr r3, [r3, #0] 8003e2a: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8003e2e: 2b00 cmp r3, #0 8003e30: d1f0 bne.n 8003e14 8003e32: e03d b.n 8003eb0 } } else { /* Do not return HAL_ERROR if request repeats the current configuration */ temp1_pllckcfg = RCC->PLLCKSELR; 8003e34: 4b21 ldr r3, [pc, #132] ; (8003ebc ) 8003e36: 6a9b ldr r3, [r3, #40] ; 0x28 8003e38: 613b str r3, [r7, #16] temp2_pllckcfg = RCC->PLL1DIVR; 8003e3a: 4b20 ldr r3, [pc, #128] ; (8003ebc ) 8003e3c: 6b1b ldr r3, [r3, #48] ; 0x30 8003e3e: 60fb str r3, [r7, #12] if(((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 8003e40: 687b ldr r3, [r7, #4] 8003e42: 6a5b ldr r3, [r3, #36] ; 0x24 8003e44: 2b01 cmp r3, #1 8003e46: d031 beq.n 8003eac (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8003e48: 693b ldr r3, [r7, #16] 8003e4a: f003 0203 and.w r2, r3, #3 8003e4e: 687b ldr r3, [r7, #4] 8003e50: 6a9b ldr r3, [r3, #40] ; 0x28 if(((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 8003e52: 429a cmp r2, r3 8003e54: d12a bne.n 8003eac ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) || 8003e56: 693b ldr r3, [r7, #16] 8003e58: 091b lsrs r3, r3, #4 8003e5a: f003 023f and.w r2, r3, #63 ; 0x3f 8003e5e: 687b ldr r3, [r7, #4] 8003e60: 6adb ldr r3, [r3, #44] ; 0x2c (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8003e62: 429a cmp r2, r3 8003e64: d122 bne.n 8003eac (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) || 8003e66: 68fb ldr r3, [r7, #12] 8003e68: f3c3 0208 ubfx r2, r3, #0, #9 8003e6c: 687b ldr r3, [r7, #4] 8003e6e: 6b1b ldr r3, [r3, #48] ; 0x30 8003e70: 3b01 subs r3, #1 ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) || 8003e72: 429a cmp r2, r3 8003e74: d11a bne.n 8003eac ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) || 8003e76: 68fb ldr r3, [r7, #12] 8003e78: 0a5b lsrs r3, r3, #9 8003e7a: f003 027f and.w r2, r3, #127 ; 0x7f 8003e7e: 687b ldr r3, [r7, #4] 8003e80: 6b5b ldr r3, [r3, #52] ; 0x34 8003e82: 3b01 subs r3, #1 (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) || 8003e84: 429a cmp r2, r3 8003e86: d111 bne.n 8003eac ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) || 8003e88: 68fb ldr r3, [r7, #12] 8003e8a: 0c1b lsrs r3, r3, #16 8003e8c: f003 027f and.w r2, r3, #127 ; 0x7f 8003e90: 687b ldr r3, [r7, #4] 8003e92: 6b9b ldr r3, [r3, #56] ; 0x38 8003e94: 3b01 subs r3, #1 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) || 8003e96: 429a cmp r2, r3 8003e98: d108 bne.n 8003eac ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) != (RCC_OscInitStruct->PLL.PLLR - 1U))) 8003e9a: 68fb ldr r3, [r7, #12] 8003e9c: 0e1b lsrs r3, r3, #24 8003e9e: f003 027f and.w r2, r3, #127 ; 0x7f 8003ea2: 687b ldr r3, [r7, #4] 8003ea4: 6bdb ldr r3, [r3, #60] ; 0x3c 8003ea6: 3b01 subs r3, #1 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) || 8003ea8: 429a cmp r2, r3 8003eaa: d001 beq.n 8003eb0 { return HAL_ERROR; 8003eac: 2301 movs r3, #1 8003eae: e000 b.n 8003eb2 } } } return HAL_OK; 8003eb0: 2300 movs r3, #0 } 8003eb2: 4618 mov r0, r3 8003eb4: 3730 adds r7, #48 ; 0x30 8003eb6: 46bd mov sp, r7 8003eb8: bd80 pop {r7, pc} 8003eba: bf00 nop 8003ebc: 58024400 .word 0x58024400 08003ec0 : * D1CPRE[3:0] bits to ensure that Domain1 core clock not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 8003ec0: b580 push {r7, lr} 8003ec2: b086 sub sp, #24 8003ec4: af00 add r7, sp, #0 8003ec6: 6078 str r0, [r7, #4] 8003ec8: 6039 str r1, [r7, #0] HAL_StatusTypeDef halstatus; uint32_t tickstart; uint32_t common_system_clock; /* Check Null pointer */ if(RCC_ClkInitStruct == NULL) 8003eca: 687b ldr r3, [r7, #4] 8003ecc: 2b00 cmp r3, #0 8003ece: d101 bne.n 8003ed4 { return HAL_ERROR; 8003ed0: 2301 movs r3, #1 8003ed2: e19c b.n 800420e /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) and the supply voltage of the device. */ /* Increasing the CPU frequency */ if(FLatency > __HAL_FLASH_GET_LATENCY()) 8003ed4: 4b8a ldr r3, [pc, #552] ; (8004100 ) 8003ed6: 681b ldr r3, [r3, #0] 8003ed8: f003 030f and.w r3, r3, #15 8003edc: 683a ldr r2, [r7, #0] 8003ede: 429a cmp r2, r3 8003ee0: d910 bls.n 8003f04 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8003ee2: 4b87 ldr r3, [pc, #540] ; (8004100 ) 8003ee4: 681b ldr r3, [r3, #0] 8003ee6: f023 020f bic.w r2, r3, #15 8003eea: 4985 ldr r1, [pc, #532] ; (8004100 ) 8003eec: 683b ldr r3, [r7, #0] 8003eee: 4313 orrs r3, r2 8003ef0: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != FLatency) 8003ef2: 4b83 ldr r3, [pc, #524] ; (8004100 ) 8003ef4: 681b ldr r3, [r3, #0] 8003ef6: f003 030f and.w r3, r3, #15 8003efa: 683a ldr r2, [r7, #0] 8003efc: 429a cmp r2, r3 8003efe: d001 beq.n 8003f04 { return HAL_ERROR; 8003f00: 2301 movs r3, #1 8003f02: e184 b.n 800420e } /* Increasing the BUS frequency divider */ /*-------------------------- D1PCLK1/CDPCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1) 8003f04: 687b ldr r3, [r7, #4] 8003f06: 681b ldr r3, [r3, #0] 8003f08: f003 0304 and.w r3, r3, #4 8003f0c: 2b00 cmp r3, #0 8003f0e: d010 beq.n 8003f32 { #if defined (RCC_D1CFGR_D1PPRE) if((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_D1PPRE)) 8003f10: 687b ldr r3, [r7, #4] 8003f12: 691a ldr r2, [r3, #16] 8003f14: 4b7b ldr r3, [pc, #492] ; (8004104 ) 8003f16: 699b ldr r3, [r3, #24] 8003f18: f003 0370 and.w r3, r3, #112 ; 0x70 8003f1c: 429a cmp r2, r3 8003f1e: d908 bls.n 8003f32 { assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider); 8003f20: 4b78 ldr r3, [pc, #480] ; (8004104 ) 8003f22: 699b ldr r3, [r3, #24] 8003f24: f023 0270 bic.w r2, r3, #112 ; 0x70 8003f28: 687b ldr r3, [r7, #4] 8003f2a: 691b ldr r3, [r3, #16] 8003f2c: 4975 ldr r1, [pc, #468] ; (8004104 ) 8003f2e: 4313 orrs r3, r2 8003f30: 618b str r3, [r1, #24] } #endif } /*-------------------------- PCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8003f32: 687b ldr r3, [r7, #4] 8003f34: 681b ldr r3, [r3, #0] 8003f36: f003 0308 and.w r3, r3, #8 8003f3a: 2b00 cmp r3, #0 8003f3c: d010 beq.n 8003f60 { #if defined (RCC_D2CFGR_D2PPRE1) if((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)) 8003f3e: 687b ldr r3, [r7, #4] 8003f40: 695a ldr r2, [r3, #20] 8003f42: 4b70 ldr r3, [pc, #448] ; (8004104 ) 8003f44: 69db ldr r3, [r3, #28] 8003f46: f003 0370 and.w r3, r3, #112 ; 0x70 8003f4a: 429a cmp r2, r3 8003f4c: d908 bls.n 8003f60 { assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); 8003f4e: 4b6d ldr r3, [pc, #436] ; (8004104 ) 8003f50: 69db ldr r3, [r3, #28] 8003f52: f023 0270 bic.w r2, r3, #112 ; 0x70 8003f56: 687b ldr r3, [r7, #4] 8003f58: 695b ldr r3, [r3, #20] 8003f5a: 496a ldr r1, [pc, #424] ; (8004104 ) 8003f5c: 4313 orrs r3, r2 8003f5e: 61cb str r3, [r1, #28] MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); } #endif } /*-------------------------- PCLK2 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8003f60: 687b ldr r3, [r7, #4] 8003f62: 681b ldr r3, [r3, #0] 8003f64: f003 0310 and.w r3, r3, #16 8003f68: 2b00 cmp r3, #0 8003f6a: d010 beq.n 8003f8e { #if defined(RCC_D2CFGR_D2PPRE2) if((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)) 8003f6c: 687b ldr r3, [r7, #4] 8003f6e: 699a ldr r2, [r3, #24] 8003f70: 4b64 ldr r3, [pc, #400] ; (8004104 ) 8003f72: 69db ldr r3, [r3, #28] 8003f74: f403 63e0 and.w r3, r3, #1792 ; 0x700 8003f78: 429a cmp r2, r3 8003f7a: d908 bls.n 8003f8e { assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); 8003f7c: 4b61 ldr r3, [pc, #388] ; (8004104 ) 8003f7e: 69db ldr r3, [r3, #28] 8003f80: f423 62e0 bic.w r2, r3, #1792 ; 0x700 8003f84: 687b ldr r3, [r7, #4] 8003f86: 699b ldr r3, [r3, #24] 8003f88: 495e ldr r1, [pc, #376] ; (8004104 ) 8003f8a: 4313 orrs r3, r2 8003f8c: 61cb str r3, [r1, #28] } #endif } /*-------------------------- D3PCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1) 8003f8e: 687b ldr r3, [r7, #4] 8003f90: 681b ldr r3, [r3, #0] 8003f92: f003 0320 and.w r3, r3, #32 8003f96: 2b00 cmp r3, #0 8003f98: d010 beq.n 8003fbc { #if defined(RCC_D3CFGR_D3PPRE) if((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->D3CFGR & RCC_D3CFGR_D3PPRE)) 8003f9a: 687b ldr r3, [r7, #4] 8003f9c: 69da ldr r2, [r3, #28] 8003f9e: 4b59 ldr r3, [pc, #356] ; (8004104 ) 8003fa0: 6a1b ldr r3, [r3, #32] 8003fa2: f003 0370 and.w r3, r3, #112 ; 0x70 8003fa6: 429a cmp r2, r3 8003fa8: d908 bls.n 8003fbc { assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider)); MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider) ); 8003faa: 4b56 ldr r3, [pc, #344] ; (8004104 ) 8003fac: 6a1b ldr r3, [r3, #32] 8003fae: f023 0270 bic.w r2, r3, #112 ; 0x70 8003fb2: 687b ldr r3, [r7, #4] 8003fb4: 69db ldr r3, [r3, #28] 8003fb6: 4953 ldr r1, [pc, #332] ; (8004104 ) 8003fb8: 4313 orrs r3, r2 8003fba: 620b str r3, [r1, #32] } #endif } /*-------------------------- HCLK Configuration --------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8003fbc: 687b ldr r3, [r7, #4] 8003fbe: 681b ldr r3, [r3, #0] 8003fc0: f003 0302 and.w r3, r3, #2 8003fc4: 2b00 cmp r3, #0 8003fc6: d010 beq.n 8003fea { #if defined (RCC_D1CFGR_HPRE) if((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_HPRE)) 8003fc8: 687b ldr r3, [r7, #4] 8003fca: 68da ldr r2, [r3, #12] 8003fcc: 4b4d ldr r3, [pc, #308] ; (8004104 ) 8003fce: 699b ldr r3, [r3, #24] 8003fd0: f003 030f and.w r3, r3, #15 8003fd4: 429a cmp r2, r3 8003fd6: d908 bls.n 8003fea { /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 8003fd8: 4b4a ldr r3, [pc, #296] ; (8004104 ) 8003fda: 699b ldr r3, [r3, #24] 8003fdc: f023 020f bic.w r2, r3, #15 8003fe0: 687b ldr r3, [r7, #4] 8003fe2: 68db ldr r3, [r3, #12] 8003fe4: 4947 ldr r1, [pc, #284] ; (8004104 ) 8003fe6: 4313 orrs r3, r2 8003fe8: 618b str r3, [r1, #24] } #endif } /*------------------------- SYSCLK Configuration -------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 8003fea: 687b ldr r3, [r7, #4] 8003fec: 681b ldr r3, [r3, #0] 8003fee: f003 0301 and.w r3, r3, #1 8003ff2: 2b00 cmp r3, #0 8003ff4: d055 beq.n 80040a2 { assert_param(IS_RCC_SYSCLK(RCC_ClkInitStruct->SYSCLKDivider)); assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); #if defined(RCC_D1CFGR_D1CPRE) MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, RCC_ClkInitStruct->SYSCLKDivider); 8003ff6: 4b43 ldr r3, [pc, #268] ; (8004104 ) 8003ff8: 699b ldr r3, [r3, #24] 8003ffa: f423 6270 bic.w r2, r3, #3840 ; 0xf00 8003ffe: 687b ldr r3, [r7, #4] 8004000: 689b ldr r3, [r3, #8] 8004002: 4940 ldr r1, [pc, #256] ; (8004104 ) 8004004: 4313 orrs r3, r2 8004006: 618b str r3, [r1, #24] #else MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE, RCC_ClkInitStruct->SYSCLKDivider); #endif /* HSE is selected as System Clock Source */ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 8004008: 687b ldr r3, [r7, #4] 800400a: 685b ldr r3, [r3, #4] 800400c: 2b02 cmp r3, #2 800400e: d107 bne.n 8004020 { /* Check the HSE ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 8004010: 4b3c ldr r3, [pc, #240] ; (8004104 ) 8004012: 681b ldr r3, [r3, #0] 8004014: f403 3300 and.w r3, r3, #131072 ; 0x20000 8004018: 2b00 cmp r3, #0 800401a: d121 bne.n 8004060 { return HAL_ERROR; 800401c: 2301 movs r3, #1 800401e: e0f6 b.n 800420e } } /* PLL is selected as System Clock Source */ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 8004020: 687b ldr r3, [r7, #4] 8004022: 685b ldr r3, [r3, #4] 8004024: 2b03 cmp r3, #3 8004026: d107 bne.n 8004038 { /* Check the PLL ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) 8004028: 4b36 ldr r3, [pc, #216] ; (8004104 ) 800402a: 681b ldr r3, [r3, #0] 800402c: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8004030: 2b00 cmp r3, #0 8004032: d115 bne.n 8004060 { return HAL_ERROR; 8004034: 2301 movs r3, #1 8004036: e0ea b.n 800420e } } /* CSI is selected as System Clock Source */ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_CSI) 8004038: 687b ldr r3, [r7, #4] 800403a: 685b ldr r3, [r3, #4] 800403c: 2b01 cmp r3, #1 800403e: d107 bne.n 8004050 { /* Check the PLL ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) 8004040: 4b30 ldr r3, [pc, #192] ; (8004104 ) 8004042: 681b ldr r3, [r3, #0] 8004044: f403 7380 and.w r3, r3, #256 ; 0x100 8004048: 2b00 cmp r3, #0 800404a: d109 bne.n 8004060 { return HAL_ERROR; 800404c: 2301 movs r3, #1 800404e: e0de b.n 800420e } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 8004050: 4b2c ldr r3, [pc, #176] ; (8004104 ) 8004052: 681b ldr r3, [r3, #0] 8004054: f003 0304 and.w r3, r3, #4 8004058: 2b00 cmp r3, #0 800405a: d101 bne.n 8004060 { return HAL_ERROR; 800405c: 2301 movs r3, #1 800405e: e0d6 b.n 800420e } } MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); 8004060: 4b28 ldr r3, [pc, #160] ; (8004104 ) 8004062: 691b ldr r3, [r3, #16] 8004064: f023 0207 bic.w r2, r3, #7 8004068: 687b ldr r3, [r7, #4] 800406a: 685b ldr r3, [r3, #4] 800406c: 4925 ldr r1, [pc, #148] ; (8004104 ) 800406e: 4313 orrs r3, r2 8004070: 610b str r3, [r1, #16] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004072: f7fd f8fd bl 8001270 8004076: 6178 str r0, [r7, #20] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8004078: e00a b.n 8004090 { if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) 800407a: f7fd f8f9 bl 8001270 800407e: 4602 mov r2, r0 8004080: 697b ldr r3, [r7, #20] 8004082: 1ad3 subs r3, r2, r3 8004084: f241 3288 movw r2, #5000 ; 0x1388 8004088: 4293 cmp r3, r2 800408a: d901 bls.n 8004090 { return HAL_TIMEOUT; 800408c: 2303 movs r3, #3 800408e: e0be b.n 800420e while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8004090: 4b1c ldr r3, [pc, #112] ; (8004104 ) 8004092: 691b ldr r3, [r3, #16] 8004094: f003 0238 and.w r2, r3, #56 ; 0x38 8004098: 687b ldr r3, [r7, #4] 800409a: 685b ldr r3, [r3, #4] 800409c: 00db lsls r3, r3, #3 800409e: 429a cmp r2, r3 80040a0: d1eb bne.n 800407a } /* Decreasing the BUS frequency divider */ /*-------------------------- HCLK Configuration --------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 80040a2: 687b ldr r3, [r7, #4] 80040a4: 681b ldr r3, [r3, #0] 80040a6: f003 0302 and.w r3, r3, #2 80040aa: 2b00 cmp r3, #0 80040ac: d010 beq.n 80040d0 { #if defined(RCC_D1CFGR_HPRE) if((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_HPRE)) 80040ae: 687b ldr r3, [r7, #4] 80040b0: 68da ldr r2, [r3, #12] 80040b2: 4b14 ldr r3, [pc, #80] ; (8004104 ) 80040b4: 699b ldr r3, [r3, #24] 80040b6: f003 030f and.w r3, r3, #15 80040ba: 429a cmp r2, r3 80040bc: d208 bcs.n 80040d0 { /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 80040be: 4b11 ldr r3, [pc, #68] ; (8004104 ) 80040c0: 699b ldr r3, [r3, #24] 80040c2: f023 020f bic.w r2, r3, #15 80040c6: 687b ldr r3, [r7, #4] 80040c8: 68db ldr r3, [r3, #12] 80040ca: 490e ldr r1, [pc, #56] ; (8004104 ) 80040cc: 4313 orrs r3, r2 80040ce: 618b str r3, [r1, #24] } #endif } /* Decreasing the number of wait states because of lower CPU frequency */ if(FLatency < __HAL_FLASH_GET_LATENCY()) 80040d0: 4b0b ldr r3, [pc, #44] ; (8004100 ) 80040d2: 681b ldr r3, [r3, #0] 80040d4: f003 030f and.w r3, r3, #15 80040d8: 683a ldr r2, [r7, #0] 80040da: 429a cmp r2, r3 80040dc: d214 bcs.n 8004108 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 80040de: 4b08 ldr r3, [pc, #32] ; (8004100 ) 80040e0: 681b ldr r3, [r3, #0] 80040e2: f023 020f bic.w r2, r3, #15 80040e6: 4906 ldr r1, [pc, #24] ; (8004100 ) 80040e8: 683b ldr r3, [r7, #0] 80040ea: 4313 orrs r3, r2 80040ec: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != FLatency) 80040ee: 4b04 ldr r3, [pc, #16] ; (8004100 ) 80040f0: 681b ldr r3, [r3, #0] 80040f2: f003 030f and.w r3, r3, #15 80040f6: 683a ldr r2, [r7, #0] 80040f8: 429a cmp r2, r3 80040fa: d005 beq.n 8004108 { return HAL_ERROR; 80040fc: 2301 movs r3, #1 80040fe: e086 b.n 800420e 8004100: 52002000 .word 0x52002000 8004104: 58024400 .word 0x58024400 } } /*-------------------------- D1PCLK1/CDPCLK Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1) 8004108: 687b ldr r3, [r7, #4] 800410a: 681b ldr r3, [r3, #0] 800410c: f003 0304 and.w r3, r3, #4 8004110: 2b00 cmp r3, #0 8004112: d010 beq.n 8004136 { #if defined(RCC_D1CFGR_D1PPRE) if((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_D1PPRE)) 8004114: 687b ldr r3, [r7, #4] 8004116: 691a ldr r2, [r3, #16] 8004118: 4b3f ldr r3, [pc, #252] ; (8004218 ) 800411a: 699b ldr r3, [r3, #24] 800411c: f003 0370 and.w r3, r3, #112 ; 0x70 8004120: 429a cmp r2, r3 8004122: d208 bcs.n 8004136 { assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider); 8004124: 4b3c ldr r3, [pc, #240] ; (8004218 ) 8004126: 699b ldr r3, [r3, #24] 8004128: f023 0270 bic.w r2, r3, #112 ; 0x70 800412c: 687b ldr r3, [r7, #4] 800412e: 691b ldr r3, [r3, #16] 8004130: 4939 ldr r1, [pc, #228] ; (8004218 ) 8004132: 4313 orrs r3, r2 8004134: 618b str r3, [r1, #24] } #endif } /*-------------------------- PCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8004136: 687b ldr r3, [r7, #4] 8004138: 681b ldr r3, [r3, #0] 800413a: f003 0308 and.w r3, r3, #8 800413e: 2b00 cmp r3, #0 8004140: d010 beq.n 8004164 { #if defined(RCC_D2CFGR_D2PPRE1) if((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)) 8004142: 687b ldr r3, [r7, #4] 8004144: 695a ldr r2, [r3, #20] 8004146: 4b34 ldr r3, [pc, #208] ; (8004218 ) 8004148: 69db ldr r3, [r3, #28] 800414a: f003 0370 and.w r3, r3, #112 ; 0x70 800414e: 429a cmp r2, r3 8004150: d208 bcs.n 8004164 { assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); 8004152: 4b31 ldr r3, [pc, #196] ; (8004218 ) 8004154: 69db ldr r3, [r3, #28] 8004156: f023 0270 bic.w r2, r3, #112 ; 0x70 800415a: 687b ldr r3, [r7, #4] 800415c: 695b ldr r3, [r3, #20] 800415e: 492e ldr r1, [pc, #184] ; (8004218 ) 8004160: 4313 orrs r3, r2 8004162: 61cb str r3, [r1, #28] } #endif } /*-------------------------- PCLK2 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8004164: 687b ldr r3, [r7, #4] 8004166: 681b ldr r3, [r3, #0] 8004168: f003 0310 and.w r3, r3, #16 800416c: 2b00 cmp r3, #0 800416e: d010 beq.n 8004192 { #if defined (RCC_D2CFGR_D2PPRE2) if((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)) 8004170: 687b ldr r3, [r7, #4] 8004172: 699a ldr r2, [r3, #24] 8004174: 4b28 ldr r3, [pc, #160] ; (8004218 ) 8004176: 69db ldr r3, [r3, #28] 8004178: f403 63e0 and.w r3, r3, #1792 ; 0x700 800417c: 429a cmp r2, r3 800417e: d208 bcs.n 8004192 { assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); 8004180: 4b25 ldr r3, [pc, #148] ; (8004218 ) 8004182: 69db ldr r3, [r3, #28] 8004184: f423 62e0 bic.w r2, r3, #1792 ; 0x700 8004188: 687b ldr r3, [r7, #4] 800418a: 699b ldr r3, [r3, #24] 800418c: 4922 ldr r1, [pc, #136] ; (8004218 ) 800418e: 4313 orrs r3, r2 8004190: 61cb str r3, [r1, #28] } #endif } /*-------------------------- D3PCLK1/SRDPCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1) 8004192: 687b ldr r3, [r7, #4] 8004194: 681b ldr r3, [r3, #0] 8004196: f003 0320 and.w r3, r3, #32 800419a: 2b00 cmp r3, #0 800419c: d010 beq.n 80041c0 { #if defined(RCC_D3CFGR_D3PPRE) if((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->D3CFGR & RCC_D3CFGR_D3PPRE)) 800419e: 687b ldr r3, [r7, #4] 80041a0: 69da ldr r2, [r3, #28] 80041a2: 4b1d ldr r3, [pc, #116] ; (8004218 ) 80041a4: 6a1b ldr r3, [r3, #32] 80041a6: f003 0370 and.w r3, r3, #112 ; 0x70 80041aa: 429a cmp r2, r3 80041ac: d208 bcs.n 80041c0 { assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider)); MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider) ); 80041ae: 4b1a ldr r3, [pc, #104] ; (8004218 ) 80041b0: 6a1b ldr r3, [r3, #32] 80041b2: f023 0270 bic.w r2, r3, #112 ; 0x70 80041b6: 687b ldr r3, [r7, #4] 80041b8: 69db ldr r3, [r3, #28] 80041ba: 4917 ldr r1, [pc, #92] ; (8004218 ) 80041bc: 4313 orrs r3, r2 80041be: 620b str r3, [r1, #32] #endif } /* Update the SystemCoreClock global variable */ #if defined(RCC_D1CFGR_D1CPRE) common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); 80041c0: f000 f834 bl 800422c 80041c4: 4602 mov r2, r0 80041c6: 4b14 ldr r3, [pc, #80] ; (8004218 ) 80041c8: 699b ldr r3, [r3, #24] 80041ca: 0a1b lsrs r3, r3, #8 80041cc: f003 030f and.w r3, r3, #15 80041d0: 4912 ldr r1, [pc, #72] ; (800421c ) 80041d2: 5ccb ldrb r3, [r1, r3] 80041d4: f003 031f and.w r3, r3, #31 80041d8: fa22 f303 lsr.w r3, r2, r3 80041dc: 613b str r3, [r7, #16] #else common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU); #endif #if defined(RCC_D1CFGR_HPRE) SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 80041de: 4b0e ldr r3, [pc, #56] ; (8004218 ) 80041e0: 699b ldr r3, [r3, #24] 80041e2: f003 030f and.w r3, r3, #15 80041e6: 4a0d ldr r2, [pc, #52] ; (800421c ) 80041e8: 5cd3 ldrb r3, [r2, r3] 80041ea: f003 031f and.w r3, r3, #31 80041ee: 693a ldr r2, [r7, #16] 80041f0: fa22 f303 lsr.w r3, r2, r3 80041f4: 4a0a ldr r2, [pc, #40] ; (8004220 ) 80041f6: 6013 str r3, [r2, #0] #endif #if defined(DUAL_CORE) && defined(CORE_CM4) SystemCoreClock = SystemD2Clock; #else SystemCoreClock = common_system_clock; 80041f8: 4a0a ldr r2, [pc, #40] ; (8004224 ) 80041fa: 693b ldr r3, [r7, #16] 80041fc: 6013 str r3, [r2, #0] #endif /* DUAL_CORE && CORE_CM4 */ /* Configure the source of time base considering new system clocks settings*/ halstatus = HAL_InitTick (uwTickPrio); 80041fe: 4b0a ldr r3, [pc, #40] ; (8004228 ) 8004200: 681b ldr r3, [r3, #0] 8004202: 4618 mov r0, r3 8004204: f7fc ffea bl 80011dc 8004208: 4603 mov r3, r0 800420a: 73fb strb r3, [r7, #15] return halstatus; 800420c: 7bfb ldrb r3, [r7, #15] } 800420e: 4618 mov r0, r3 8004210: 3718 adds r7, #24 8004212: 46bd mov sp, r7 8004214: bd80 pop {r7, pc} 8004216: bf00 nop 8004218: 58024400 .word 0x58024400 800421c: 0800574c .word 0x0800574c 8004220: 24000004 .word 0x24000004 8004224: 24000000 .word 0x24000000 8004228: 24000008 .word 0x24000008 0800422c : * * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 800422c: b480 push {r7} 800422e: b089 sub sp, #36 ; 0x24 8004230: af00 add r7, sp, #0 float_t fracn1, pllvco; uint32_t sysclockfreq; /* Get SYSCLK source -------------------------------------------------------*/ switch (RCC->CFGR & RCC_CFGR_SWS) 8004232: 4bb3 ldr r3, [pc, #716] ; (8004500 ) 8004234: 691b ldr r3, [r3, #16] 8004236: f003 0338 and.w r3, r3, #56 ; 0x38 800423a: 2b18 cmp r3, #24 800423c: f200 8155 bhi.w 80044ea 8004240: a201 add r2, pc, #4 ; (adr r2, 8004248 ) 8004242: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8004246: bf00 nop 8004248: 080042ad .word 0x080042ad 800424c: 080044eb .word 0x080044eb 8004250: 080044eb .word 0x080044eb 8004254: 080044eb .word 0x080044eb 8004258: 080044eb .word 0x080044eb 800425c: 080044eb .word 0x080044eb 8004260: 080044eb .word 0x080044eb 8004264: 080044eb .word 0x080044eb 8004268: 080042d3 .word 0x080042d3 800426c: 080044eb .word 0x080044eb 8004270: 080044eb .word 0x080044eb 8004274: 080044eb .word 0x080044eb 8004278: 080044eb .word 0x080044eb 800427c: 080044eb .word 0x080044eb 8004280: 080044eb .word 0x080044eb 8004284: 080044eb .word 0x080044eb 8004288: 080042d9 .word 0x080042d9 800428c: 080044eb .word 0x080044eb 8004290: 080044eb .word 0x080044eb 8004294: 080044eb .word 0x080044eb 8004298: 080044eb .word 0x080044eb 800429c: 080044eb .word 0x080044eb 80042a0: 080044eb .word 0x080044eb 80042a4: 080044eb .word 0x080044eb 80042a8: 080042df .word 0x080042df { case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 80042ac: 4b94 ldr r3, [pc, #592] ; (8004500 ) 80042ae: 681b ldr r3, [r3, #0] 80042b0: f003 0320 and.w r3, r3, #32 80042b4: 2b00 cmp r3, #0 80042b6: d009 beq.n 80042cc { sysclockfreq = (uint32_t) (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); 80042b8: 4b91 ldr r3, [pc, #580] ; (8004500 ) 80042ba: 681b ldr r3, [r3, #0] 80042bc: 08db lsrs r3, r3, #3 80042be: f003 0303 and.w r3, r3, #3 80042c2: 4a90 ldr r2, [pc, #576] ; (8004504 ) 80042c4: fa22 f303 lsr.w r3, r2, r3 80042c8: 61bb str r3, [r7, #24] else { sysclockfreq = (uint32_t) HSI_VALUE; } break; 80042ca: e111 b.n 80044f0 sysclockfreq = (uint32_t) HSI_VALUE; 80042cc: 4b8d ldr r3, [pc, #564] ; (8004504 ) 80042ce: 61bb str r3, [r7, #24] break; 80042d0: e10e b.n 80044f0 case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */ sysclockfreq = CSI_VALUE; 80042d2: 4b8d ldr r3, [pc, #564] ; (8004508 ) 80042d4: 61bb str r3, [r7, #24] break; 80042d6: e10b b.n 80044f0 case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ sysclockfreq = HSE_VALUE; 80042d8: 4b8c ldr r3, [pc, #560] ; (800450c ) 80042da: 61bb str r3, [r7, #24] break; 80042dc: e108 b.n 80044f0 case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */ /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN SYSCLK = PLL_VCO / PLLR */ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 80042de: 4b88 ldr r3, [pc, #544] ; (8004500 ) 80042e0: 6a9b ldr r3, [r3, #40] ; 0x28 80042e2: f003 0303 and.w r3, r3, #3 80042e6: 617b str r3, [r7, #20] pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ; 80042e8: 4b85 ldr r3, [pc, #532] ; (8004500 ) 80042ea: 6a9b ldr r3, [r3, #40] ; 0x28 80042ec: 091b lsrs r3, r3, #4 80042ee: f003 033f and.w r3, r3, #63 ; 0x3f 80042f2: 613b str r3, [r7, #16] pllfracen = ((RCC-> PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos); 80042f4: 4b82 ldr r3, [pc, #520] ; (8004500 ) 80042f6: 6adb ldr r3, [r3, #44] ; 0x2c 80042f8: f003 0301 and.w r3, r3, #1 80042fc: 60fb str r3, [r7, #12] fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3)); 80042fe: 4b80 ldr r3, [pc, #512] ; (8004500 ) 8004300: 6b5b ldr r3, [r3, #52] ; 0x34 8004302: 08db lsrs r3, r3, #3 8004304: f3c3 030c ubfx r3, r3, #0, #13 8004308: 68fa ldr r2, [r7, #12] 800430a: fb02 f303 mul.w r3, r2, r3 800430e: ee07 3a90 vmov s15, r3 8004312: eef8 7a67 vcvt.f32.u32 s15, s15 8004316: edc7 7a02 vstr s15, [r7, #8] if (pllm != 0U) 800431a: 693b ldr r3, [r7, #16] 800431c: 2b00 cmp r3, #0 800431e: f000 80e1 beq.w 80044e4 8004322: 697b ldr r3, [r7, #20] 8004324: 2b02 cmp r3, #2 8004326: f000 8083 beq.w 8004430 800432a: 697b ldr r3, [r7, #20] 800432c: 2b02 cmp r3, #2 800432e: f200 80a1 bhi.w 8004474 8004332: 697b ldr r3, [r7, #20] 8004334: 2b00 cmp r3, #0 8004336: d003 beq.n 8004340 8004338: 697b ldr r3, [r7, #20] 800433a: 2b01 cmp r3, #1 800433c: d056 beq.n 80043ec 800433e: e099 b.n 8004474 { switch (pllsource) { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 8004340: 4b6f ldr r3, [pc, #444] ; (8004500 ) 8004342: 681b ldr r3, [r3, #0] 8004344: f003 0320 and.w r3, r3, #32 8004348: 2b00 cmp r3, #0 800434a: d02d beq.n 80043a8 { hsivalue= (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); 800434c: 4b6c ldr r3, [pc, #432] ; (8004500 ) 800434e: 681b ldr r3, [r3, #0] 8004350: 08db lsrs r3, r3, #3 8004352: f003 0303 and.w r3, r3, #3 8004356: 4a6b ldr r2, [pc, #428] ; (8004504 ) 8004358: fa22 f303 lsr.w r3, r2, r3 800435c: 607b str r3, [r7, #4] pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); 800435e: 687b ldr r3, [r7, #4] 8004360: ee07 3a90 vmov s15, r3 8004364: eef8 6a67 vcvt.f32.u32 s13, s15 8004368: 693b ldr r3, [r7, #16] 800436a: ee07 3a90 vmov s15, r3 800436e: eef8 7a67 vcvt.f32.u32 s15, s15 8004372: ee86 7aa7 vdiv.f32 s14, s13, s15 8004376: 4b62 ldr r3, [pc, #392] ; (8004500 ) 8004378: 6b1b ldr r3, [r3, #48] ; 0x30 800437a: f3c3 0308 ubfx r3, r3, #0, #9 800437e: ee07 3a90 vmov s15, r3 8004382: eef8 6a67 vcvt.f32.u32 s13, s15 8004386: ed97 6a02 vldr s12, [r7, #8] 800438a: eddf 5a61 vldr s11, [pc, #388] ; 8004510 800438e: eec6 7a25 vdiv.f32 s15, s12, s11 8004392: ee76 7aa7 vadd.f32 s15, s13, s15 8004396: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 800439a: ee77 7aa6 vadd.f32 s15, s15, s13 800439e: ee67 7a27 vmul.f32 s15, s14, s15 80043a2: edc7 7a07 vstr s15, [r7, #28] } else { pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); } break; 80043a6: e087 b.n 80044b8 pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); 80043a8: 693b ldr r3, [r7, #16] 80043aa: ee07 3a90 vmov s15, r3 80043ae: eef8 7a67 vcvt.f32.u32 s15, s15 80043b2: eddf 6a58 vldr s13, [pc, #352] ; 8004514 80043b6: ee86 7aa7 vdiv.f32 s14, s13, s15 80043ba: 4b51 ldr r3, [pc, #324] ; (8004500 ) 80043bc: 6b1b ldr r3, [r3, #48] ; 0x30 80043be: f3c3 0308 ubfx r3, r3, #0, #9 80043c2: ee07 3a90 vmov s15, r3 80043c6: eef8 6a67 vcvt.f32.u32 s13, s15 80043ca: ed97 6a02 vldr s12, [r7, #8] 80043ce: eddf 5a50 vldr s11, [pc, #320] ; 8004510 80043d2: eec6 7a25 vdiv.f32 s15, s12, s11 80043d6: ee76 7aa7 vadd.f32 s15, s13, s15 80043da: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 80043de: ee77 7aa6 vadd.f32 s15, s15, s13 80043e2: ee67 7a27 vmul.f32 s15, s14, s15 80043e6: edc7 7a07 vstr s15, [r7, #28] break; 80043ea: e065 b.n 80044b8 case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); 80043ec: 693b ldr r3, [r7, #16] 80043ee: ee07 3a90 vmov s15, r3 80043f2: eef8 7a67 vcvt.f32.u32 s15, s15 80043f6: eddf 6a48 vldr s13, [pc, #288] ; 8004518 80043fa: ee86 7aa7 vdiv.f32 s14, s13, s15 80043fe: 4b40 ldr r3, [pc, #256] ; (8004500 ) 8004400: 6b1b ldr r3, [r3, #48] ; 0x30 8004402: f3c3 0308 ubfx r3, r3, #0, #9 8004406: ee07 3a90 vmov s15, r3 800440a: eef8 6a67 vcvt.f32.u32 s13, s15 800440e: ed97 6a02 vldr s12, [r7, #8] 8004412: eddf 5a3f vldr s11, [pc, #252] ; 8004510 8004416: eec6 7a25 vdiv.f32 s15, s12, s11 800441a: ee76 7aa7 vadd.f32 s15, s13, s15 800441e: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 8004422: ee77 7aa6 vadd.f32 s15, s15, s13 8004426: ee67 7a27 vmul.f32 s15, s14, s15 800442a: edc7 7a07 vstr s15, [r7, #28] break; 800442e: e043 b.n 80044b8 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); 8004430: 693b ldr r3, [r7, #16] 8004432: ee07 3a90 vmov s15, r3 8004436: eef8 7a67 vcvt.f32.u32 s15, s15 800443a: eddf 6a38 vldr s13, [pc, #224] ; 800451c 800443e: ee86 7aa7 vdiv.f32 s14, s13, s15 8004442: 4b2f ldr r3, [pc, #188] ; (8004500 ) 8004444: 6b1b ldr r3, [r3, #48] ; 0x30 8004446: f3c3 0308 ubfx r3, r3, #0, #9 800444a: ee07 3a90 vmov s15, r3 800444e: eef8 6a67 vcvt.f32.u32 s13, s15 8004452: ed97 6a02 vldr s12, [r7, #8] 8004456: eddf 5a2e vldr s11, [pc, #184] ; 8004510 800445a: eec6 7a25 vdiv.f32 s15, s12, s11 800445e: ee76 7aa7 vadd.f32 s15, s13, s15 8004462: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 8004466: ee77 7aa6 vadd.f32 s15, s15, s13 800446a: ee67 7a27 vmul.f32 s15, s14, s15 800446e: edc7 7a07 vstr s15, [r7, #28] break; 8004472: e021 b.n 80044b8 default: pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); 8004474: 693b ldr r3, [r7, #16] 8004476: ee07 3a90 vmov s15, r3 800447a: eef8 7a67 vcvt.f32.u32 s15, s15 800447e: eddf 6a26 vldr s13, [pc, #152] ; 8004518 8004482: ee86 7aa7 vdiv.f32 s14, s13, s15 8004486: 4b1e ldr r3, [pc, #120] ; (8004500 ) 8004488: 6b1b ldr r3, [r3, #48] ; 0x30 800448a: f3c3 0308 ubfx r3, r3, #0, #9 800448e: ee07 3a90 vmov s15, r3 8004492: eef8 6a67 vcvt.f32.u32 s13, s15 8004496: ed97 6a02 vldr s12, [r7, #8] 800449a: eddf 5a1d vldr s11, [pc, #116] ; 8004510 800449e: eec6 7a25 vdiv.f32 s15, s12, s11 80044a2: ee76 7aa7 vadd.f32 s15, s13, s15 80044a6: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 80044aa: ee77 7aa6 vadd.f32 s15, s15, s13 80044ae: ee67 7a27 vmul.f32 s15, s14, s15 80044b2: edc7 7a07 vstr s15, [r7, #28] break; 80044b6: bf00 nop } pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ; 80044b8: 4b11 ldr r3, [pc, #68] ; (8004500 ) 80044ba: 6b1b ldr r3, [r3, #48] ; 0x30 80044bc: 0a5b lsrs r3, r3, #9 80044be: f003 037f and.w r3, r3, #127 ; 0x7f 80044c2: 3301 adds r3, #1 80044c4: 603b str r3, [r7, #0] sysclockfreq = (uint32_t)(float_t)(pllvco/(float_t)pllp); 80044c6: 683b ldr r3, [r7, #0] 80044c8: ee07 3a90 vmov s15, r3 80044cc: eeb8 7a67 vcvt.f32.u32 s14, s15 80044d0: edd7 6a07 vldr s13, [r7, #28] 80044d4: eec6 7a87 vdiv.f32 s15, s13, s14 80044d8: eefc 7ae7 vcvt.u32.f32 s15, s15 80044dc: ee17 3a90 vmov r3, s15 80044e0: 61bb str r3, [r7, #24] } else { sysclockfreq = 0U; } break; 80044e2: e005 b.n 80044f0 sysclockfreq = 0U; 80044e4: 2300 movs r3, #0 80044e6: 61bb str r3, [r7, #24] break; 80044e8: e002 b.n 80044f0 default: sysclockfreq = CSI_VALUE; 80044ea: 4b07 ldr r3, [pc, #28] ; (8004508 ) 80044ec: 61bb str r3, [r7, #24] break; 80044ee: bf00 nop } return sysclockfreq; 80044f0: 69bb ldr r3, [r7, #24] } 80044f2: 4618 mov r0, r3 80044f4: 3724 adds r7, #36 ; 0x24 80044f6: 46bd mov sp, r7 80044f8: f85d 7b04 ldr.w r7, [sp], #4 80044fc: 4770 bx lr 80044fe: bf00 nop 8004500: 58024400 .word 0x58024400 8004504: 03d09000 .word 0x03d09000 8004508: 003d0900 .word 0x003d0900 800450c: 017d7840 .word 0x017d7840 8004510: 46000000 .word 0x46000000 8004514: 4c742400 .word 0x4c742400 8004518: 4a742400 .word 0x4a742400 800451c: 4bbebc20 .word 0x4bbebc20 08004520 : * (*) : Available on some STM32H7 lines only. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 8004520: b580 push {r7, lr} 8004522: b086 sub sp, #24 8004524: af00 add r7, sp, #0 8004526: 6078 str r0, [r7, #4] uint32_t tmpreg; uint32_t tickstart; HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ 8004528: 2300 movs r3, #0 800452a: 75fb strb r3, [r7, #23] HAL_StatusTypeDef status = HAL_OK; /* Final status */ 800452c: 2300 movs r3, #0 800452e: 75bb strb r3, [r7, #22] /*---------------------------- SPDIFRX configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) 8004530: 687b ldr r3, [r7, #4] 8004532: 681b ldr r3, [r3, #0] 8004534: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 8004538: 2b00 cmp r3, #0 800453a: d03f beq.n 80045bc { switch(PeriphClkInit->SpdifrxClockSelection) 800453c: 687b ldr r3, [r7, #4] 800453e: 6e5b ldr r3, [r3, #100] ; 0x64 8004540: f5b3 1f40 cmp.w r3, #3145728 ; 0x300000 8004544: d02a beq.n 800459c 8004546: f5b3 1f40 cmp.w r3, #3145728 ; 0x300000 800454a: d824 bhi.n 8004596 800454c: f5b3 1f00 cmp.w r3, #2097152 ; 0x200000 8004550: d018 beq.n 8004584 8004552: f5b3 1f00 cmp.w r3, #2097152 ; 0x200000 8004556: d81e bhi.n 8004596 8004558: 2b00 cmp r3, #0 800455a: d003 beq.n 8004564 800455c: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 8004560: d007 beq.n 8004572 8004562: e018 b.n 8004596 { case RCC_SPDIFRXCLKSOURCE_PLL: /* PLL is used as clock source for SPDIFRX*/ /* Enable PLL1Q Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8004564: 4ba3 ldr r3, [pc, #652] ; (80047f4 ) 8004566: 6adb ldr r3, [r3, #44] ; 0x2c 8004568: 4aa2 ldr r2, [pc, #648] ; (80047f4 ) 800456a: f443 3300 orr.w r3, r3, #131072 ; 0x20000 800456e: 62d3 str r3, [r2, #44] ; 0x2c /* SPDIFRX clock source configuration done later after clock selection check */ break; 8004570: e015 b.n 800459e case RCC_SPDIFRXCLKSOURCE_PLL2: /* PLL2 is used as clock source for SPDIFRX*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE); 8004572: 687b ldr r3, [r7, #4] 8004574: 3304 adds r3, #4 8004576: 2102 movs r1, #2 8004578: 4618 mov r0, r3 800457a: f000 ff17 bl 80053ac 800457e: 4603 mov r3, r0 8004580: 75fb strb r3, [r7, #23] /* SPDIFRX clock source configuration done later after clock selection check */ break; 8004582: e00c b.n 800459e case RCC_SPDIFRXCLKSOURCE_PLL3: /* PLL3 is used as clock source for SPDIFRX*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE); 8004584: 687b ldr r3, [r7, #4] 8004586: 3324 adds r3, #36 ; 0x24 8004588: 2102 movs r1, #2 800458a: 4618 mov r0, r3 800458c: f000 ffc0 bl 8005510 8004590: 4603 mov r3, r0 8004592: 75fb strb r3, [r7, #23] /* SPDIFRX clock source configuration done later after clock selection check */ break; 8004594: e003 b.n 800459e /* Internal OSC clock is used as source of SPDIFRX clock*/ /* SPDIFRX clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8004596: 2301 movs r3, #1 8004598: 75fb strb r3, [r7, #23] break; 800459a: e000 b.n 800459e break; 800459c: bf00 nop } if(ret == HAL_OK) 800459e: 7dfb ldrb r3, [r7, #23] 80045a0: 2b00 cmp r3, #0 80045a2: d109 bne.n 80045b8 { /* Set the source of SPDIFRX clock*/ __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifrxClockSelection); 80045a4: 4b93 ldr r3, [pc, #588] ; (80047f4 ) 80045a6: 6d1b ldr r3, [r3, #80] ; 0x50 80045a8: f423 1240 bic.w r2, r3, #3145728 ; 0x300000 80045ac: 687b ldr r3, [r7, #4] 80045ae: 6e5b ldr r3, [r3, #100] ; 0x64 80045b0: 4990 ldr r1, [pc, #576] ; (80047f4 ) 80045b2: 4313 orrs r3, r2 80045b4: 650b str r3, [r1, #80] ; 0x50 80045b6: e001 b.n 80045bc } else { /* set overall return value */ status = ret; 80045b8: 7dfb ldrb r3, [r7, #23] 80045ba: 75bb strb r3, [r7, #22] } } /*---------------------------- SAI1 configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) 80045bc: 687b ldr r3, [r7, #4] 80045be: 681b ldr r3, [r3, #0] 80045c0: f403 7380 and.w r3, r3, #256 ; 0x100 80045c4: 2b00 cmp r3, #0 80045c6: d03d beq.n 8004644 { switch(PeriphClkInit->Sai1ClockSelection) 80045c8: 687b ldr r3, [r7, #4] 80045ca: 6d5b ldr r3, [r3, #84] ; 0x54 80045cc: 2b04 cmp r3, #4 80045ce: d826 bhi.n 800461e 80045d0: a201 add r2, pc, #4 ; (adr r2, 80045d8 ) 80045d2: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80045d6: bf00 nop 80045d8: 080045ed .word 0x080045ed 80045dc: 080045fb .word 0x080045fb 80045e0: 0800460d .word 0x0800460d 80045e4: 08004625 .word 0x08004625 80045e8: 08004625 .word 0x08004625 { case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1*/ /* Enable SAI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 80045ec: 4b81 ldr r3, [pc, #516] ; (80047f4 ) 80045ee: 6adb ldr r3, [r3, #44] ; 0x2c 80045f0: 4a80 ldr r2, [pc, #512] ; (80047f4 ) 80045f2: f443 3300 orr.w r3, r3, #131072 ; 0x20000 80045f6: 62d3 str r3, [r2, #44] ; 0x2c /* SAI1 clock source configuration done later after clock selection check */ break; 80045f8: e015 b.n 8004626 case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI1*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); 80045fa: 687b ldr r3, [r7, #4] 80045fc: 3304 adds r3, #4 80045fe: 2100 movs r1, #0 8004600: 4618 mov r0, r3 8004602: f000 fed3 bl 80053ac 8004606: 4603 mov r3, r0 8004608: 75fb strb r3, [r7, #23] /* SAI1 clock source configuration done later after clock selection check */ break; 800460a: e00c b.n 8004626 case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI1*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE); 800460c: 687b ldr r3, [r7, #4] 800460e: 3324 adds r3, #36 ; 0x24 8004610: 2100 movs r1, #0 8004612: 4618 mov r0, r3 8004614: f000 ff7c bl 8005510 8004618: 4603 mov r3, r0 800461a: 75fb strb r3, [r7, #23] /* SAI1 clock source configuration done later after clock selection check */ break; 800461c: e003 b.n 8004626 /* HSI, HSE, or CSI oscillator is used as source of SAI1 clock */ /* SAI1 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800461e: 2301 movs r3, #1 8004620: 75fb strb r3, [r7, #23] break; 8004622: e000 b.n 8004626 break; 8004624: bf00 nop } if(ret == HAL_OK) 8004626: 7dfb ldrb r3, [r7, #23] 8004628: 2b00 cmp r3, #0 800462a: d109 bne.n 8004640 { /* Set the source of SAI1 clock*/ __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); 800462c: 4b71 ldr r3, [pc, #452] ; (80047f4 ) 800462e: 6d1b ldr r3, [r3, #80] ; 0x50 8004630: f023 0207 bic.w r2, r3, #7 8004634: 687b ldr r3, [r7, #4] 8004636: 6d5b ldr r3, [r3, #84] ; 0x54 8004638: 496e ldr r1, [pc, #440] ; (80047f4 ) 800463a: 4313 orrs r3, r2 800463c: 650b str r3, [r1, #80] ; 0x50 800463e: e001 b.n 8004644 } else { /* set overall return value */ status = ret; 8004640: 7dfb ldrb r3, [r7, #23] 8004642: 75bb strb r3, [r7, #22] } } #if defined(SAI3) /*---------------------------- SAI2/3 configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI23) == RCC_PERIPHCLK_SAI23) 8004644: 687b ldr r3, [r7, #4] 8004646: 681b ldr r3, [r3, #0] 8004648: f403 7300 and.w r3, r3, #512 ; 0x200 800464c: 2b00 cmp r3, #0 800464e: d042 beq.n 80046d6 { switch(PeriphClkInit->Sai23ClockSelection) 8004650: 687b ldr r3, [r7, #4] 8004652: 6d9b ldr r3, [r3, #88] ; 0x58 8004654: f5b3 7f80 cmp.w r3, #256 ; 0x100 8004658: d02b beq.n 80046b2 800465a: f5b3 7f80 cmp.w r3, #256 ; 0x100 800465e: d825 bhi.n 80046ac 8004660: 2bc0 cmp r3, #192 ; 0xc0 8004662: d028 beq.n 80046b6 8004664: 2bc0 cmp r3, #192 ; 0xc0 8004666: d821 bhi.n 80046ac 8004668: 2b80 cmp r3, #128 ; 0x80 800466a: d016 beq.n 800469a 800466c: 2b80 cmp r3, #128 ; 0x80 800466e: d81d bhi.n 80046ac 8004670: 2b00 cmp r3, #0 8004672: d002 beq.n 800467a 8004674: 2b40 cmp r3, #64 ; 0x40 8004676: d007 beq.n 8004688 8004678: e018 b.n 80046ac { case RCC_SAI23CLKSOURCE_PLL: /* PLL is used as clock source for SAI2/3 */ /* Enable SAI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800467a: 4b5e ldr r3, [pc, #376] ; (80047f4 ) 800467c: 6adb ldr r3, [r3, #44] ; 0x2c 800467e: 4a5d ldr r2, [pc, #372] ; (80047f4 ) 8004680: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8004684: 62d3 str r3, [r2, #44] ; 0x2c /* SAI2/3 clock source configuration done later after clock selection check */ break; 8004686: e017 b.n 80046b8 case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2/3 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); 8004688: 687b ldr r3, [r7, #4] 800468a: 3304 adds r3, #4 800468c: 2100 movs r1, #0 800468e: 4618 mov r0, r3 8004690: f000 fe8c bl 80053ac 8004694: 4603 mov r3, r0 8004696: 75fb strb r3, [r7, #23] /* SAI2/3 clock source configuration done later after clock selection check */ break; 8004698: e00e b.n 80046b8 case RCC_SAI23CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2/3 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE); 800469a: 687b ldr r3, [r7, #4] 800469c: 3324 adds r3, #36 ; 0x24 800469e: 2100 movs r1, #0 80046a0: 4618 mov r0, r3 80046a2: f000 ff35 bl 8005510 80046a6: 4603 mov r3, r0 80046a8: 75fb strb r3, [r7, #23] /* SAI2/3 clock source configuration done later after clock selection check */ break; 80046aa: e005 b.n 80046b8 /* HSI, HSE, or CSI oscillator is used as source of SAI2/3 clock */ /* SAI2/3 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 80046ac: 2301 movs r3, #1 80046ae: 75fb strb r3, [r7, #23] break; 80046b0: e002 b.n 80046b8 break; 80046b2: bf00 nop 80046b4: e000 b.n 80046b8 break; 80046b6: bf00 nop } if(ret == HAL_OK) 80046b8: 7dfb ldrb r3, [r7, #23] 80046ba: 2b00 cmp r3, #0 80046bc: d109 bne.n 80046d2 { /* Set the source of SAI2/3 clock*/ __HAL_RCC_SAI23_CONFIG(PeriphClkInit->Sai23ClockSelection); 80046be: 4b4d ldr r3, [pc, #308] ; (80047f4 ) 80046c0: 6d1b ldr r3, [r3, #80] ; 0x50 80046c2: f423 72e0 bic.w r2, r3, #448 ; 0x1c0 80046c6: 687b ldr r3, [r7, #4] 80046c8: 6d9b ldr r3, [r3, #88] ; 0x58 80046ca: 494a ldr r1, [pc, #296] ; (80047f4 ) 80046cc: 4313 orrs r3, r2 80046ce: 650b str r3, [r1, #80] ; 0x50 80046d0: e001 b.n 80046d6 } else { /* set overall return value */ status = ret; 80046d2: 7dfb ldrb r3, [r7, #23] 80046d4: 75bb strb r3, [r7, #22] } #endif /*SAI2B*/ #if defined(SAI4) /*---------------------------- SAI4A configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4A) == RCC_PERIPHCLK_SAI4A) 80046d6: 687b ldr r3, [r7, #4] 80046d8: 681b ldr r3, [r3, #0] 80046da: f403 6380 and.w r3, r3, #1024 ; 0x400 80046de: 2b00 cmp r3, #0 80046e0: d049 beq.n 8004776 { switch(PeriphClkInit->Sai4AClockSelection) 80046e2: 687b ldr r3, [r7, #4] 80046e4: f8d3 30a4 ldr.w r3, [r3, #164] ; 0xa4 80046e8: f5b3 0f00 cmp.w r3, #8388608 ; 0x800000 80046ec: d030 beq.n 8004750 80046ee: f5b3 0f00 cmp.w r3, #8388608 ; 0x800000 80046f2: d82a bhi.n 800474a 80046f4: f5b3 0fc0 cmp.w r3, #6291456 ; 0x600000 80046f8: d02c beq.n 8004754 80046fa: f5b3 0fc0 cmp.w r3, #6291456 ; 0x600000 80046fe: d824 bhi.n 800474a 8004700: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 8004704: d018 beq.n 8004738 8004706: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 800470a: d81e bhi.n 800474a 800470c: 2b00 cmp r3, #0 800470e: d003 beq.n 8004718 8004710: f5b3 1f00 cmp.w r3, #2097152 ; 0x200000 8004714: d007 beq.n 8004726 8004716: e018 b.n 800474a { case RCC_SAI4ACLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/ /* Enable SAI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8004718: 4b36 ldr r3, [pc, #216] ; (80047f4 ) 800471a: 6adb ldr r3, [r3, #44] ; 0x2c 800471c: 4a35 ldr r2, [pc, #212] ; (80047f4 ) 800471e: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8004722: 62d3 str r3, [r2, #44] ; 0x2c /* SAI1 clock source configuration done later after clock selection check */ break; 8004724: e017 b.n 8004756 case RCC_SAI4ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); 8004726: 687b ldr r3, [r7, #4] 8004728: 3304 adds r3, #4 800472a: 2100 movs r1, #0 800472c: 4618 mov r0, r3 800472e: f000 fe3d bl 80053ac 8004732: 4603 mov r3, r0 8004734: 75fb strb r3, [r7, #23] /* SAI2 clock source configuration done later after clock selection check */ break; 8004736: e00e b.n 8004756 case RCC_SAI4ACLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE); 8004738: 687b ldr r3, [r7, #4] 800473a: 3324 adds r3, #36 ; 0x24 800473c: 2100 movs r1, #0 800473e: 4618 mov r0, r3 8004740: f000 fee6 bl 8005510 8004744: 4603 mov r3, r0 8004746: 75fb strb r3, [r7, #23] /* SAI1 clock source configuration done later after clock selection check */ break; 8004748: e005 b.n 8004756 /* SAI4A clock source configuration done later after clock selection check */ break; #endif /* RCC_VER_3_0 */ default: ret = HAL_ERROR; 800474a: 2301 movs r3, #1 800474c: 75fb strb r3, [r7, #23] break; 800474e: e002 b.n 8004756 break; 8004750: bf00 nop 8004752: e000 b.n 8004756 break; 8004754: bf00 nop } if(ret == HAL_OK) 8004756: 7dfb ldrb r3, [r7, #23] 8004758: 2b00 cmp r3, #0 800475a: d10a bne.n 8004772 { /* Set the source of SAI4A clock*/ __HAL_RCC_SAI4A_CONFIG(PeriphClkInit->Sai4AClockSelection); 800475c: 4b25 ldr r3, [pc, #148] ; (80047f4 ) 800475e: 6d9b ldr r3, [r3, #88] ; 0x58 8004760: f423 0260 bic.w r2, r3, #14680064 ; 0xe00000 8004764: 687b ldr r3, [r7, #4] 8004766: f8d3 30a4 ldr.w r3, [r3, #164] ; 0xa4 800476a: 4922 ldr r1, [pc, #136] ; (80047f4 ) 800476c: 4313 orrs r3, r2 800476e: 658b str r3, [r1, #88] ; 0x58 8004770: e001 b.n 8004776 } else { /* set overall return value */ status = ret; 8004772: 7dfb ldrb r3, [r7, #23] 8004774: 75bb strb r3, [r7, #22] } } /*---------------------------- SAI4B configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4B) == RCC_PERIPHCLK_SAI4B) 8004776: 687b ldr r3, [r7, #4] 8004778: 681b ldr r3, [r3, #0] 800477a: f403 6300 and.w r3, r3, #2048 ; 0x800 800477e: 2b00 cmp r3, #0 8004780: d04b beq.n 800481a { switch(PeriphClkInit->Sai4BClockSelection) 8004782: 687b ldr r3, [r7, #4] 8004784: f8d3 30a8 ldr.w r3, [r3, #168] ; 0xa8 8004788: f1b3 6f80 cmp.w r3, #67108864 ; 0x4000000 800478c: d030 beq.n 80047f0 800478e: f1b3 6f80 cmp.w r3, #67108864 ; 0x4000000 8004792: d82a bhi.n 80047ea 8004794: f1b3 7f40 cmp.w r3, #50331648 ; 0x3000000 8004798: d02e beq.n 80047f8 800479a: f1b3 7f40 cmp.w r3, #50331648 ; 0x3000000 800479e: d824 bhi.n 80047ea 80047a0: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000 80047a4: d018 beq.n 80047d8 80047a6: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000 80047aa: d81e bhi.n 80047ea 80047ac: 2b00 cmp r3, #0 80047ae: d003 beq.n 80047b8 80047b0: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 80047b4: d007 beq.n 80047c6 80047b6: e018 b.n 80047ea { case RCC_SAI4BCLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/ /* Enable SAI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 80047b8: 4b0e ldr r3, [pc, #56] ; (80047f4 ) 80047ba: 6adb ldr r3, [r3, #44] ; 0x2c 80047bc: 4a0d ldr r2, [pc, #52] ; (80047f4 ) 80047be: f443 3300 orr.w r3, r3, #131072 ; 0x20000 80047c2: 62d3 str r3, [r2, #44] ; 0x2c /* SAI1 clock source configuration done later after clock selection check */ break; 80047c4: e019 b.n 80047fa case RCC_SAI4BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); 80047c6: 687b ldr r3, [r7, #4] 80047c8: 3304 adds r3, #4 80047ca: 2100 movs r1, #0 80047cc: 4618 mov r0, r3 80047ce: f000 fded bl 80053ac 80047d2: 4603 mov r3, r0 80047d4: 75fb strb r3, [r7, #23] /* SAI2 clock source configuration done later after clock selection check */ break; 80047d6: e010 b.n 80047fa case RCC_SAI4BCLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 80047d8: 687b ldr r3, [r7, #4] 80047da: 3324 adds r3, #36 ; 0x24 80047dc: 2100 movs r1, #0 80047de: 4618 mov r0, r3 80047e0: f000 fe96 bl 8005510 80047e4: 4603 mov r3, r0 80047e6: 75fb strb r3, [r7, #23] /* SAI1 clock source configuration done later after clock selection check */ break; 80047e8: e007 b.n 80047fa /* SAI4B clock source configuration done later after clock selection check */ break; #endif /* RCC_VER_3_0 */ default: ret = HAL_ERROR; 80047ea: 2301 movs r3, #1 80047ec: 75fb strb r3, [r7, #23] break; 80047ee: e004 b.n 80047fa break; 80047f0: bf00 nop 80047f2: e002 b.n 80047fa 80047f4: 58024400 .word 0x58024400 break; 80047f8: bf00 nop } if(ret == HAL_OK) 80047fa: 7dfb ldrb r3, [r7, #23] 80047fc: 2b00 cmp r3, #0 80047fe: d10a bne.n 8004816 { /* Set the source of SAI4B clock*/ __HAL_RCC_SAI4B_CONFIG(PeriphClkInit->Sai4BClockSelection); 8004800: 4b99 ldr r3, [pc, #612] ; (8004a68 ) 8004802: 6d9b ldr r3, [r3, #88] ; 0x58 8004804: f023 62e0 bic.w r2, r3, #117440512 ; 0x7000000 8004808: 687b ldr r3, [r7, #4] 800480a: f8d3 30a8 ldr.w r3, [r3, #168] ; 0xa8 800480e: 4996 ldr r1, [pc, #600] ; (8004a68 ) 8004810: 4313 orrs r3, r2 8004812: 658b str r3, [r1, #88] ; 0x58 8004814: e001 b.n 800481a } else { /* set overall return value */ status = ret; 8004816: 7dfb ldrb r3, [r7, #23] 8004818: 75bb strb r3, [r7, #22] } #endif /*SAI4*/ #if defined(QUADSPI) /*---------------------------- QSPI configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) 800481a: 687b ldr r3, [r7, #4] 800481c: 681b ldr r3, [r3, #0] 800481e: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8004822: 2b00 cmp r3, #0 8004824: d032 beq.n 800488c { switch(PeriphClkInit->QspiClockSelection) 8004826: 687b ldr r3, [r7, #4] 8004828: 6c9b ldr r3, [r3, #72] ; 0x48 800482a: 2b30 cmp r3, #48 ; 0x30 800482c: d01c beq.n 8004868 800482e: 2b30 cmp r3, #48 ; 0x30 8004830: d817 bhi.n 8004862 8004832: 2b20 cmp r3, #32 8004834: d00c beq.n 8004850 8004836: 2b20 cmp r3, #32 8004838: d813 bhi.n 8004862 800483a: 2b00 cmp r3, #0 800483c: d016 beq.n 800486c 800483e: 2b10 cmp r3, #16 8004840: d10f bne.n 8004862 { case RCC_QSPICLKSOURCE_PLL: /* PLL is used as clock source for QSPI*/ /* Enable QSPI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8004842: 4b89 ldr r3, [pc, #548] ; (8004a68 ) 8004844: 6adb ldr r3, [r3, #44] ; 0x2c 8004846: 4a88 ldr r2, [pc, #544] ; (8004a68 ) 8004848: f443 3300 orr.w r3, r3, #131072 ; 0x20000 800484c: 62d3 str r3, [r2, #44] ; 0x2c /* QSPI clock source configuration done later after clock selection check */ break; 800484e: e00e b.n 800486e case RCC_QSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for QSPI*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE); 8004850: 687b ldr r3, [r7, #4] 8004852: 3304 adds r3, #4 8004854: 2102 movs r1, #2 8004856: 4618 mov r0, r3 8004858: f000 fda8 bl 80053ac 800485c: 4603 mov r3, r0 800485e: 75fb strb r3, [r7, #23] /* QSPI clock source configuration done later after clock selection check */ break; 8004860: e005 b.n 800486e case RCC_QSPICLKSOURCE_D1HCLK: /* Domain1 HCLK clock selected as QSPI kernel peripheral clock */ break; default: ret = HAL_ERROR; 8004862: 2301 movs r3, #1 8004864: 75fb strb r3, [r7, #23] break; 8004866: e002 b.n 800486e break; 8004868: bf00 nop 800486a: e000 b.n 800486e break; 800486c: bf00 nop } if(ret == HAL_OK) 800486e: 7dfb ldrb r3, [r7, #23] 8004870: 2b00 cmp r3, #0 8004872: d109 bne.n 8004888 { /* Set the source of QSPI clock*/ __HAL_RCC_QSPI_CONFIG(PeriphClkInit->QspiClockSelection); 8004874: 4b7c ldr r3, [pc, #496] ; (8004a68 ) 8004876: 6cdb ldr r3, [r3, #76] ; 0x4c 8004878: f023 0230 bic.w r2, r3, #48 ; 0x30 800487c: 687b ldr r3, [r7, #4] 800487e: 6c9b ldr r3, [r3, #72] ; 0x48 8004880: 4979 ldr r1, [pc, #484] ; (8004a68 ) 8004882: 4313 orrs r3, r2 8004884: 64cb str r3, [r1, #76] ; 0x4c 8004886: e001 b.n 800488c } else { /* set overall return value */ status = ret; 8004888: 7dfb ldrb r3, [r7, #23] 800488a: 75bb strb r3, [r7, #22] } } #endif /*OCTOSPI*/ /*---------------------------- SPI1/2/3 configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI123) == RCC_PERIPHCLK_SPI123) 800488c: 687b ldr r3, [r7, #4] 800488e: 681b ldr r3, [r3, #0] 8004890: f403 5380 and.w r3, r3, #4096 ; 0x1000 8004894: 2b00 cmp r3, #0 8004896: d047 beq.n 8004928 { switch(PeriphClkInit->Spi123ClockSelection) 8004898: 687b ldr r3, [r7, #4] 800489a: 6ddb ldr r3, [r3, #92] ; 0x5c 800489c: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 80048a0: d030 beq.n 8004904 80048a2: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 80048a6: d82a bhi.n 80048fe 80048a8: f5b3 5f40 cmp.w r3, #12288 ; 0x3000 80048ac: d02c beq.n 8004908 80048ae: f5b3 5f40 cmp.w r3, #12288 ; 0x3000 80048b2: d824 bhi.n 80048fe 80048b4: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 80048b8: d018 beq.n 80048ec 80048ba: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 80048be: d81e bhi.n 80048fe 80048c0: 2b00 cmp r3, #0 80048c2: d003 beq.n 80048cc 80048c4: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 80048c8: d007 beq.n 80048da 80048ca: e018 b.n 80048fe { case RCC_SPI123CLKSOURCE_PLL: /* PLL is used as clock source for SPI1/2/3 */ /* Enable SPI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 80048cc: 4b66 ldr r3, [pc, #408] ; (8004a68 ) 80048ce: 6adb ldr r3, [r3, #44] ; 0x2c 80048d0: 4a65 ldr r2, [pc, #404] ; (8004a68 ) 80048d2: f443 3300 orr.w r3, r3, #131072 ; 0x20000 80048d6: 62d3 str r3, [r2, #44] ; 0x2c /* SPI1/2/3 clock source configuration done later after clock selection check */ break; 80048d8: e017 b.n 800490a case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI1/2/3 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); 80048da: 687b ldr r3, [r7, #4] 80048dc: 3304 adds r3, #4 80048de: 2100 movs r1, #0 80048e0: 4618 mov r0, r3 80048e2: f000 fd63 bl 80053ac 80048e6: 4603 mov r3, r0 80048e8: 75fb strb r3, [r7, #23] /* SPI1/2/3 clock source configuration done later after clock selection check */ break; 80048ea: e00e b.n 800490a case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI1/2/3 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE); 80048ec: 687b ldr r3, [r7, #4] 80048ee: 3324 adds r3, #36 ; 0x24 80048f0: 2100 movs r1, #0 80048f2: 4618 mov r0, r3 80048f4: f000 fe0c bl 8005510 80048f8: 4603 mov r3, r0 80048fa: 75fb strb r3, [r7, #23] /* SPI1/2/3 clock source configuration done later after clock selection check */ break; 80048fc: e005 b.n 800490a /* HSI, HSE, or CSI oscillator is used as source of SPI1/2/3 clock */ /* SPI1/2/3 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 80048fe: 2301 movs r3, #1 8004900: 75fb strb r3, [r7, #23] break; 8004902: e002 b.n 800490a break; 8004904: bf00 nop 8004906: e000 b.n 800490a break; 8004908: bf00 nop } if(ret == HAL_OK) 800490a: 7dfb ldrb r3, [r7, #23] 800490c: 2b00 cmp r3, #0 800490e: d109 bne.n 8004924 { /* Set the source of SPI1/2/3 clock*/ __HAL_RCC_SPI123_CONFIG(PeriphClkInit->Spi123ClockSelection); 8004910: 4b55 ldr r3, [pc, #340] ; (8004a68 ) 8004912: 6d1b ldr r3, [r3, #80] ; 0x50 8004914: f423 42e0 bic.w r2, r3, #28672 ; 0x7000 8004918: 687b ldr r3, [r7, #4] 800491a: 6ddb ldr r3, [r3, #92] ; 0x5c 800491c: 4952 ldr r1, [pc, #328] ; (8004a68 ) 800491e: 4313 orrs r3, r2 8004920: 650b str r3, [r1, #80] ; 0x50 8004922: e001 b.n 8004928 } else { /* set overall return value */ status = ret; 8004924: 7dfb ldrb r3, [r7, #23] 8004926: 75bb strb r3, [r7, #22] } } /*---------------------------- SPI4/5 configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45) 8004928: 687b ldr r3, [r7, #4] 800492a: 681b ldr r3, [r3, #0] 800492c: f403 5300 and.w r3, r3, #8192 ; 0x2000 8004930: 2b00 cmp r3, #0 8004932: d049 beq.n 80049c8 { switch(PeriphClkInit->Spi45ClockSelection) 8004934: 687b ldr r3, [r7, #4] 8004936: 6e1b ldr r3, [r3, #96] ; 0x60 8004938: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 800493c: d02e beq.n 800499c 800493e: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 8004942: d828 bhi.n 8004996 8004944: f5b3 2f80 cmp.w r3, #262144 ; 0x40000 8004948: d02a beq.n 80049a0 800494a: f5b3 2f80 cmp.w r3, #262144 ; 0x40000 800494e: d822 bhi.n 8004996 8004950: f5b3 3f40 cmp.w r3, #196608 ; 0x30000 8004954: d026 beq.n 80049a4 8004956: f5b3 3f40 cmp.w r3, #196608 ; 0x30000 800495a: d81c bhi.n 8004996 800495c: f5b3 3f00 cmp.w r3, #131072 ; 0x20000 8004960: d010 beq.n 8004984 8004962: f5b3 3f00 cmp.w r3, #131072 ; 0x20000 8004966: d816 bhi.n 8004996 8004968: 2b00 cmp r3, #0 800496a: d01d beq.n 80049a8 800496c: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8004970: d111 bne.n 8004996 /* SPI4/5 clock source configuration done later after clock selection check */ break; case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI4/5 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE); 8004972: 687b ldr r3, [r7, #4] 8004974: 3304 adds r3, #4 8004976: 2101 movs r1, #1 8004978: 4618 mov r0, r3 800497a: f000 fd17 bl 80053ac 800497e: 4603 mov r3, r0 8004980: 75fb strb r3, [r7, #23] /* SPI4/5 clock source configuration done later after clock selection check */ break; 8004982: e012 b.n 80049aa case RCC_SPI45CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI4/5 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE); 8004984: 687b ldr r3, [r7, #4] 8004986: 3324 adds r3, #36 ; 0x24 8004988: 2101 movs r1, #1 800498a: 4618 mov r0, r3 800498c: f000 fdc0 bl 8005510 8004990: 4603 mov r3, r0 8004992: 75fb strb r3, [r7, #23] /* SPI4/5 clock source configuration done later after clock selection check */ break; 8004994: e009 b.n 80049aa /* HSE, oscillator is used as source of SPI4/5 clock */ /* SPI4/5 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8004996: 2301 movs r3, #1 8004998: 75fb strb r3, [r7, #23] break; 800499a: e006 b.n 80049aa break; 800499c: bf00 nop 800499e: e004 b.n 80049aa break; 80049a0: bf00 nop 80049a2: e002 b.n 80049aa break; 80049a4: bf00 nop 80049a6: e000 b.n 80049aa break; 80049a8: bf00 nop } if(ret == HAL_OK) 80049aa: 7dfb ldrb r3, [r7, #23] 80049ac: 2b00 cmp r3, #0 80049ae: d109 bne.n 80049c4 { /* Set the source of SPI4/5 clock*/ __HAL_RCC_SPI45_CONFIG(PeriphClkInit->Spi45ClockSelection); 80049b0: 4b2d ldr r3, [pc, #180] ; (8004a68 ) 80049b2: 6d1b ldr r3, [r3, #80] ; 0x50 80049b4: f423 22e0 bic.w r2, r3, #458752 ; 0x70000 80049b8: 687b ldr r3, [r7, #4] 80049ba: 6e1b ldr r3, [r3, #96] ; 0x60 80049bc: 492a ldr r1, [pc, #168] ; (8004a68 ) 80049be: 4313 orrs r3, r2 80049c0: 650b str r3, [r1, #80] ; 0x50 80049c2: e001 b.n 80049c8 } else { /* set overall return value */ status = ret; 80049c4: 7dfb ldrb r3, [r7, #23] 80049c6: 75bb strb r3, [r7, #22] } } /*---------------------------- SPI6 configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6) 80049c8: 687b ldr r3, [r7, #4] 80049ca: 681b ldr r3, [r3, #0] 80049cc: f403 4380 and.w r3, r3, #16384 ; 0x4000 80049d0: 2b00 cmp r3, #0 80049d2: d04d beq.n 8004a70 { switch(PeriphClkInit->Spi6ClockSelection) 80049d4: 687b ldr r3, [r7, #4] 80049d6: f8d3 30ac ldr.w r3, [r3, #172] ; 0xac 80049da: f1b3 4fa0 cmp.w r3, #1342177280 ; 0x50000000 80049de: d02e beq.n 8004a3e 80049e0: f1b3 4fa0 cmp.w r3, #1342177280 ; 0x50000000 80049e4: d828 bhi.n 8004a38 80049e6: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 80049ea: d02a beq.n 8004a42 80049ec: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 80049f0: d822 bhi.n 8004a38 80049f2: f1b3 5f40 cmp.w r3, #805306368 ; 0x30000000 80049f6: d026 beq.n 8004a46 80049f8: f1b3 5f40 cmp.w r3, #805306368 ; 0x30000000 80049fc: d81c bhi.n 8004a38 80049fe: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 8004a02: d010 beq.n 8004a26 8004a04: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 8004a08: d816 bhi.n 8004a38 8004a0a: 2b00 cmp r3, #0 8004a0c: d01d beq.n 8004a4a 8004a0e: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000 8004a12: d111 bne.n 8004a38 /* SPI6 clock source configuration done later after clock selection check */ break; case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI6*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE); 8004a14: 687b ldr r3, [r7, #4] 8004a16: 3304 adds r3, #4 8004a18: 2101 movs r1, #1 8004a1a: 4618 mov r0, r3 8004a1c: f000 fcc6 bl 80053ac 8004a20: 4603 mov r3, r0 8004a22: 75fb strb r3, [r7, #23] /* SPI6 clock source configuration done later after clock selection check */ break; 8004a24: e012 b.n 8004a4c case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI6*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE); 8004a26: 687b ldr r3, [r7, #4] 8004a28: 3324 adds r3, #36 ; 0x24 8004a2a: 2101 movs r1, #1 8004a2c: 4618 mov r0, r3 8004a2e: f000 fd6f bl 8005510 8004a32: 4603 mov r3, r0 8004a34: 75fb strb r3, [r7, #23] /* SPI6 clock source configuration done later after clock selection check */ break; 8004a36: e009 b.n 8004a4c /* SPI6 clock source configuration done later after clock selection check */ break; #endif default: ret = HAL_ERROR; 8004a38: 2301 movs r3, #1 8004a3a: 75fb strb r3, [r7, #23] break; 8004a3c: e006 b.n 8004a4c break; 8004a3e: bf00 nop 8004a40: e004 b.n 8004a4c break; 8004a42: bf00 nop 8004a44: e002 b.n 8004a4c break; 8004a46: bf00 nop 8004a48: e000 b.n 8004a4c break; 8004a4a: bf00 nop } if(ret == HAL_OK) 8004a4c: 7dfb ldrb r3, [r7, #23] 8004a4e: 2b00 cmp r3, #0 8004a50: d10c bne.n 8004a6c { /* Set the source of SPI6 clock*/ __HAL_RCC_SPI6_CONFIG(PeriphClkInit->Spi6ClockSelection); 8004a52: 4b05 ldr r3, [pc, #20] ; (8004a68 ) 8004a54: 6d9b ldr r3, [r3, #88] ; 0x58 8004a56: f023 42e0 bic.w r2, r3, #1879048192 ; 0x70000000 8004a5a: 687b ldr r3, [r7, #4] 8004a5c: f8d3 30ac ldr.w r3, [r3, #172] ; 0xac 8004a60: 4901 ldr r1, [pc, #4] ; (8004a68 ) 8004a62: 4313 orrs r3, r2 8004a64: 658b str r3, [r1, #88] ; 0x58 8004a66: e003 b.n 8004a70 8004a68: 58024400 .word 0x58024400 } else { /* set overall return value */ status = ret; 8004a6c: 7dfb ldrb r3, [r7, #23] 8004a6e: 75bb strb r3, [r7, #22] } #endif /*DSI*/ #if defined(FDCAN1) || defined(FDCAN2) /*---------------------------- FDCAN configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) 8004a70: 687b ldr r3, [r7, #4] 8004a72: 681b ldr r3, [r3, #0] 8004a74: f403 4300 and.w r3, r3, #32768 ; 0x8000 8004a78: 2b00 cmp r3, #0 8004a7a: d02f beq.n 8004adc { switch(PeriphClkInit->FdcanClockSelection) 8004a7c: 687b ldr r3, [r7, #4] 8004a7e: 6edb ldr r3, [r3, #108] ; 0x6c 8004a80: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 8004a84: d00e beq.n 8004aa4 8004a86: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 8004a8a: d814 bhi.n 8004ab6 8004a8c: 2b00 cmp r3, #0 8004a8e: d015 beq.n 8004abc 8004a90: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000 8004a94: d10f bne.n 8004ab6 { case RCC_FDCANCLKSOURCE_PLL: /* PLL is used as clock source for FDCAN*/ /* Enable FDCAN Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8004a96: 4baf ldr r3, [pc, #700] ; (8004d54 ) 8004a98: 6adb ldr r3, [r3, #44] ; 0x2c 8004a9a: 4aae ldr r2, [pc, #696] ; (8004d54 ) 8004a9c: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8004aa0: 62d3 str r3, [r2, #44] ; 0x2c /* FDCAN clock source configuration done later after clock selection check */ break; 8004aa2: e00c b.n 8004abe case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is used as clock source for FDCAN*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE); 8004aa4: 687b ldr r3, [r7, #4] 8004aa6: 3304 adds r3, #4 8004aa8: 2101 movs r1, #1 8004aaa: 4618 mov r0, r3 8004aac: f000 fc7e bl 80053ac 8004ab0: 4603 mov r3, r0 8004ab2: 75fb strb r3, [r7, #23] /* FDCAN clock source configuration done later after clock selection check */ break; 8004ab4: e003 b.n 8004abe /* HSE is used as clock source for FDCAN*/ /* FDCAN clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8004ab6: 2301 movs r3, #1 8004ab8: 75fb strb r3, [r7, #23] break; 8004aba: e000 b.n 8004abe break; 8004abc: bf00 nop } if(ret == HAL_OK) 8004abe: 7dfb ldrb r3, [r7, #23] 8004ac0: 2b00 cmp r3, #0 8004ac2: d109 bne.n 8004ad8 { /* Set the source of FDCAN clock*/ __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection); 8004ac4: 4ba3 ldr r3, [pc, #652] ; (8004d54 ) 8004ac6: 6d1b ldr r3, [r3, #80] ; 0x50 8004ac8: f023 5240 bic.w r2, r3, #805306368 ; 0x30000000 8004acc: 687b ldr r3, [r7, #4] 8004ace: 6edb ldr r3, [r3, #108] ; 0x6c 8004ad0: 49a0 ldr r1, [pc, #640] ; (8004d54 ) 8004ad2: 4313 orrs r3, r2 8004ad4: 650b str r3, [r1, #80] ; 0x50 8004ad6: e001 b.n 8004adc } else { /* set overall return value */ status = ret; 8004ad8: 7dfb ldrb r3, [r7, #23] 8004ada: 75bb strb r3, [r7, #22] } } #endif /*FDCAN1 || FDCAN2*/ /*---------------------------- FMC configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC) 8004adc: 687b ldr r3, [r7, #4] 8004ade: 681b ldr r3, [r3, #0] 8004ae0: f003 7380 and.w r3, r3, #16777216 ; 0x1000000 8004ae4: 2b00 cmp r3, #0 8004ae6: d032 beq.n 8004b4e { switch(PeriphClkInit->FmcClockSelection) 8004ae8: 687b ldr r3, [r7, #4] 8004aea: 6c5b ldr r3, [r3, #68] ; 0x44 8004aec: 2b03 cmp r3, #3 8004aee: d81b bhi.n 8004b28 8004af0: a201 add r2, pc, #4 ; (adr r2, 8004af8 ) 8004af2: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8004af6: bf00 nop 8004af8: 08004b2f .word 0x08004b2f 8004afc: 08004b09 .word 0x08004b09 8004b00: 08004b17 .word 0x08004b17 8004b04: 08004b2f .word 0x08004b2f { case RCC_FMCCLKSOURCE_PLL: /* PLL is used as clock source for FMC*/ /* Enable FMC Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8004b08: 4b92 ldr r3, [pc, #584] ; (8004d54 ) 8004b0a: 6adb ldr r3, [r3, #44] ; 0x2c 8004b0c: 4a91 ldr r2, [pc, #580] ; (8004d54 ) 8004b0e: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8004b12: 62d3 str r3, [r2, #44] ; 0x2c /* FMC clock source configuration done later after clock selection check */ break; 8004b14: e00c b.n 8004b30 case RCC_FMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for FMC*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE); 8004b16: 687b ldr r3, [r7, #4] 8004b18: 3304 adds r3, #4 8004b1a: 2102 movs r1, #2 8004b1c: 4618 mov r0, r3 8004b1e: f000 fc45 bl 80053ac 8004b22: 4603 mov r3, r0 8004b24: 75fb strb r3, [r7, #23] /* FMC clock source configuration done later after clock selection check */ break; 8004b26: e003 b.n 8004b30 case RCC_FMCCLKSOURCE_HCLK: /* D1/CD HCLK clock selected as FMC kernel peripheral clock */ break; default: ret = HAL_ERROR; 8004b28: 2301 movs r3, #1 8004b2a: 75fb strb r3, [r7, #23] break; 8004b2c: e000 b.n 8004b30 break; 8004b2e: bf00 nop } if(ret == HAL_OK) 8004b30: 7dfb ldrb r3, [r7, #23] 8004b32: 2b00 cmp r3, #0 8004b34: d109 bne.n 8004b4a { /* Set the source of FMC clock*/ __HAL_RCC_FMC_CONFIG(PeriphClkInit->FmcClockSelection); 8004b36: 4b87 ldr r3, [pc, #540] ; (8004d54 ) 8004b38: 6cdb ldr r3, [r3, #76] ; 0x4c 8004b3a: f023 0203 bic.w r2, r3, #3 8004b3e: 687b ldr r3, [r7, #4] 8004b40: 6c5b ldr r3, [r3, #68] ; 0x44 8004b42: 4984 ldr r1, [pc, #528] ; (8004d54 ) 8004b44: 4313 orrs r3, r2 8004b46: 64cb str r3, [r1, #76] ; 0x4c 8004b48: e001 b.n 8004b4e } else { /* set overall return value */ status = ret; 8004b4a: 7dfb ldrb r3, [r7, #23] 8004b4c: 75bb strb r3, [r7, #22] } } /*---------------------------- RTC configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) 8004b4e: 687b ldr r3, [r7, #4] 8004b50: 681b ldr r3, [r3, #0] 8004b52: f403 0380 and.w r3, r3, #4194304 ; 0x400000 8004b56: 2b00 cmp r3, #0 8004b58: f000 8086 beq.w 8004c68 { /* check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* Enable write access to Backup domain */ SET_BIT(PWR->CR1, PWR_CR1_DBP); 8004b5c: 4b7e ldr r3, [pc, #504] ; (8004d58 ) 8004b5e: 681b ldr r3, [r3, #0] 8004b60: 4a7d ldr r2, [pc, #500] ; (8004d58 ) 8004b62: f443 7380 orr.w r3, r3, #256 ; 0x100 8004b66: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8004b68: f7fc fb82 bl 8001270 8004b6c: 6138 str r0, [r7, #16] while((PWR->CR1 & PWR_CR1_DBP) == 0U) 8004b6e: e009 b.n 8004b84 { if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8004b70: f7fc fb7e bl 8001270 8004b74: 4602 mov r2, r0 8004b76: 693b ldr r3, [r7, #16] 8004b78: 1ad3 subs r3, r2, r3 8004b7a: 2b64 cmp r3, #100 ; 0x64 8004b7c: d902 bls.n 8004b84 { ret = HAL_TIMEOUT; 8004b7e: 2303 movs r3, #3 8004b80: 75fb strb r3, [r7, #23] break; 8004b82: e005 b.n 8004b90 while((PWR->CR1 & PWR_CR1_DBP) == 0U) 8004b84: 4b74 ldr r3, [pc, #464] ; (8004d58 ) 8004b86: 681b ldr r3, [r3, #0] 8004b88: f403 7380 and.w r3, r3, #256 ; 0x100 8004b8c: 2b00 cmp r3, #0 8004b8e: d0ef beq.n 8004b70 } } if(ret == HAL_OK) 8004b90: 7dfb ldrb r3, [r7, #23] 8004b92: 2b00 cmp r3, #0 8004b94: d166 bne.n 8004c64 { /* Reset the Backup domain only if the RTC Clock source selection is modified */ if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)) 8004b96: 4b6f ldr r3, [pc, #444] ; (8004d54 ) 8004b98: 6f1a ldr r2, [r3, #112] ; 0x70 8004b9a: 687b ldr r3, [r7, #4] 8004b9c: f8d3 30b0 ldr.w r3, [r3, #176] ; 0xb0 8004ba0: 4053 eors r3, r2 8004ba2: f403 7340 and.w r3, r3, #768 ; 0x300 8004ba6: 2b00 cmp r3, #0 8004ba8: d013 beq.n 8004bd2 { /* Store the content of BDCR register before the reset of Backup Domain */ tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 8004baa: 4b6a ldr r3, [pc, #424] ; (8004d54 ) 8004bac: 6f1b ldr r3, [r3, #112] ; 0x70 8004bae: f423 7340 bic.w r3, r3, #768 ; 0x300 8004bb2: 60fb str r3, [r7, #12] /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 8004bb4: 4b67 ldr r3, [pc, #412] ; (8004d54 ) 8004bb6: 6f1b ldr r3, [r3, #112] ; 0x70 8004bb8: 4a66 ldr r2, [pc, #408] ; (8004d54 ) 8004bba: f443 3380 orr.w r3, r3, #65536 ; 0x10000 8004bbe: 6713 str r3, [r2, #112] ; 0x70 __HAL_RCC_BACKUPRESET_RELEASE(); 8004bc0: 4b64 ldr r3, [pc, #400] ; (8004d54 ) 8004bc2: 6f1b ldr r3, [r3, #112] ; 0x70 8004bc4: 4a63 ldr r2, [pc, #396] ; (8004d54 ) 8004bc6: f423 3380 bic.w r3, r3, #65536 ; 0x10000 8004bca: 6713 str r3, [r2, #112] ; 0x70 /* Restore the Content of BDCR register */ RCC->BDCR = tmpreg; 8004bcc: 4a61 ldr r2, [pc, #388] ; (8004d54 ) 8004bce: 68fb ldr r3, [r7, #12] 8004bd0: 6713 str r3, [r2, #112] ; 0x70 } /* If LSE is selected as RTC clock source (and enabled prior to Backup Domain reset), wait for LSE reactivation */ if(PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE) 8004bd2: 687b ldr r3, [r7, #4] 8004bd4: f8d3 30b0 ldr.w r3, [r3, #176] ; 0xb0 8004bd8: f5b3 7f80 cmp.w r3, #256 ; 0x100 8004bdc: d115 bne.n 8004c0a { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004bde: f7fc fb47 bl 8001270 8004be2: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 8004be4: e00b b.n 8004bfe { if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8004be6: f7fc fb43 bl 8001270 8004bea: 4602 mov r2, r0 8004bec: 693b ldr r3, [r7, #16] 8004bee: 1ad3 subs r3, r2, r3 8004bf0: f241 3288 movw r2, #5000 ; 0x1388 8004bf4: 4293 cmp r3, r2 8004bf6: d902 bls.n 8004bfe { ret = HAL_TIMEOUT; 8004bf8: 2303 movs r3, #3 8004bfa: 75fb strb r3, [r7, #23] break; 8004bfc: e005 b.n 8004c0a while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 8004bfe: 4b55 ldr r3, [pc, #340] ; (8004d54 ) 8004c00: 6f1b ldr r3, [r3, #112] ; 0x70 8004c02: f003 0302 and.w r3, r3, #2 8004c06: 2b00 cmp r3, #0 8004c08: d0ed beq.n 8004be6 } } } if(ret == HAL_OK) 8004c0a: 7dfb ldrb r3, [r7, #23] 8004c0c: 2b00 cmp r3, #0 8004c0e: d126 bne.n 8004c5e { __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 8004c10: 687b ldr r3, [r7, #4] 8004c12: f8d3 30b0 ldr.w r3, [r3, #176] ; 0xb0 8004c16: f403 7340 and.w r3, r3, #768 ; 0x300 8004c1a: f5b3 7f40 cmp.w r3, #768 ; 0x300 8004c1e: d10d bne.n 8004c3c 8004c20: 4b4c ldr r3, [pc, #304] ; (8004d54 ) 8004c22: 691b ldr r3, [r3, #16] 8004c24: f423 527c bic.w r2, r3, #16128 ; 0x3f00 8004c28: 687b ldr r3, [r7, #4] 8004c2a: f8d3 30b0 ldr.w r3, [r3, #176] ; 0xb0 8004c2e: 0919 lsrs r1, r3, #4 8004c30: 4b4a ldr r3, [pc, #296] ; (8004d5c ) 8004c32: 400b ands r3, r1 8004c34: 4947 ldr r1, [pc, #284] ; (8004d54 ) 8004c36: 4313 orrs r3, r2 8004c38: 610b str r3, [r1, #16] 8004c3a: e005 b.n 8004c48 8004c3c: 4b45 ldr r3, [pc, #276] ; (8004d54 ) 8004c3e: 691b ldr r3, [r3, #16] 8004c40: 4a44 ldr r2, [pc, #272] ; (8004d54 ) 8004c42: f423 537c bic.w r3, r3, #16128 ; 0x3f00 8004c46: 6113 str r3, [r2, #16] 8004c48: 4b42 ldr r3, [pc, #264] ; (8004d54 ) 8004c4a: 6f1a ldr r2, [r3, #112] ; 0x70 8004c4c: 687b ldr r3, [r7, #4] 8004c4e: f8d3 30b0 ldr.w r3, [r3, #176] ; 0xb0 8004c52: f3c3 030b ubfx r3, r3, #0, #12 8004c56: 493f ldr r1, [pc, #252] ; (8004d54 ) 8004c58: 4313 orrs r3, r2 8004c5a: 670b str r3, [r1, #112] ; 0x70 8004c5c: e004 b.n 8004c68 } else { /* set overall return value */ status = ret; 8004c5e: 7dfb ldrb r3, [r7, #23] 8004c60: 75bb strb r3, [r7, #22] 8004c62: e001 b.n 8004c68 } } else { /* set overall return value */ status = ret; 8004c64: 7dfb ldrb r3, [r7, #23] 8004c66: 75bb strb r3, [r7, #22] } } /*-------------------------- USART1/6 configuration --------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART16) == RCC_PERIPHCLK_USART16) 8004c68: 687b ldr r3, [r7, #4] 8004c6a: 681b ldr r3, [r3, #0] 8004c6c: f003 0301 and.w r3, r3, #1 8004c70: 2b00 cmp r3, #0 8004c72: f000 8085 beq.w 8004d80 { switch(PeriphClkInit->Usart16ClockSelection) 8004c76: 687b ldr r3, [r7, #4] 8004c78: 6f9b ldr r3, [r3, #120] ; 0x78 8004c7a: 2b28 cmp r3, #40 ; 0x28 8004c7c: d866 bhi.n 8004d4c 8004c7e: a201 add r2, pc, #4 ; (adr r2, 8004c84 ) 8004c80: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8004c84: 08004d61 .word 0x08004d61 8004c88: 08004d4d .word 0x08004d4d 8004c8c: 08004d4d .word 0x08004d4d 8004c90: 08004d4d .word 0x08004d4d 8004c94: 08004d4d .word 0x08004d4d 8004c98: 08004d4d .word 0x08004d4d 8004c9c: 08004d4d .word 0x08004d4d 8004ca0: 08004d4d .word 0x08004d4d 8004ca4: 08004d29 .word 0x08004d29 8004ca8: 08004d4d .word 0x08004d4d 8004cac: 08004d4d .word 0x08004d4d 8004cb0: 08004d4d .word 0x08004d4d 8004cb4: 08004d4d .word 0x08004d4d 8004cb8: 08004d4d .word 0x08004d4d 8004cbc: 08004d4d .word 0x08004d4d 8004cc0: 08004d4d .word 0x08004d4d 8004cc4: 08004d3b .word 0x08004d3b 8004cc8: 08004d4d .word 0x08004d4d 8004ccc: 08004d4d .word 0x08004d4d 8004cd0: 08004d4d .word 0x08004d4d 8004cd4: 08004d4d .word 0x08004d4d 8004cd8: 08004d4d .word 0x08004d4d 8004cdc: 08004d4d .word 0x08004d4d 8004ce0: 08004d4d .word 0x08004d4d 8004ce4: 08004d61 .word 0x08004d61 8004ce8: 08004d4d .word 0x08004d4d 8004cec: 08004d4d .word 0x08004d4d 8004cf0: 08004d4d .word 0x08004d4d 8004cf4: 08004d4d .word 0x08004d4d 8004cf8: 08004d4d .word 0x08004d4d 8004cfc: 08004d4d .word 0x08004d4d 8004d00: 08004d4d .word 0x08004d4d 8004d04: 08004d61 .word 0x08004d61 8004d08: 08004d4d .word 0x08004d4d 8004d0c: 08004d4d .word 0x08004d4d 8004d10: 08004d4d .word 0x08004d4d 8004d14: 08004d4d .word 0x08004d4d 8004d18: 08004d4d .word 0x08004d4d 8004d1c: 08004d4d .word 0x08004d4d 8004d20: 08004d4d .word 0x08004d4d 8004d24: 08004d61 .word 0x08004d61 case RCC_USART16CLKSOURCE_PCLK2: /* CD/D2 PCLK2 as clock source for USART1/6 */ /* USART1/6 clock source configuration done later after clock selection check */ break; case RCC_USART16CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART1/6 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE); 8004d28: 687b ldr r3, [r7, #4] 8004d2a: 3304 adds r3, #4 8004d2c: 2101 movs r1, #1 8004d2e: 4618 mov r0, r3 8004d30: f000 fb3c bl 80053ac 8004d34: 4603 mov r3, r0 8004d36: 75fb strb r3, [r7, #23] /* USART1/6 clock source configuration done later after clock selection check */ break; 8004d38: e013 b.n 8004d62 case RCC_USART16CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART1/6 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE); 8004d3a: 687b ldr r3, [r7, #4] 8004d3c: 3324 adds r3, #36 ; 0x24 8004d3e: 2101 movs r1, #1 8004d40: 4618 mov r0, r3 8004d42: f000 fbe5 bl 8005510 8004d46: 4603 mov r3, r0 8004d48: 75fb strb r3, [r7, #23] /* USART1/6 clock source configuration done later after clock selection check */ break; 8004d4a: e00a b.n 8004d62 /* LSE, oscillator is used as source of USART1/6 clock */ /* USART1/6 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8004d4c: 2301 movs r3, #1 8004d4e: 75fb strb r3, [r7, #23] break; 8004d50: e007 b.n 8004d62 8004d52: bf00 nop 8004d54: 58024400 .word 0x58024400 8004d58: 58024800 .word 0x58024800 8004d5c: 00ffffcf .word 0x00ffffcf break; 8004d60: bf00 nop } if(ret == HAL_OK) 8004d62: 7dfb ldrb r3, [r7, #23] 8004d64: 2b00 cmp r3, #0 8004d66: d109 bne.n 8004d7c { /* Set the source of USART1/6 clock */ __HAL_RCC_USART16_CONFIG(PeriphClkInit->Usart16ClockSelection); 8004d68: 4b96 ldr r3, [pc, #600] ; (8004fc4 ) 8004d6a: 6d5b ldr r3, [r3, #84] ; 0x54 8004d6c: f023 0238 bic.w r2, r3, #56 ; 0x38 8004d70: 687b ldr r3, [r7, #4] 8004d72: 6f9b ldr r3, [r3, #120] ; 0x78 8004d74: 4993 ldr r1, [pc, #588] ; (8004fc4 ) 8004d76: 4313 orrs r3, r2 8004d78: 654b str r3, [r1, #84] ; 0x54 8004d7a: e001 b.n 8004d80 } else { /* set overall return value */ status = ret; 8004d7c: 7dfb ldrb r3, [r7, #23] 8004d7e: 75bb strb r3, [r7, #22] } } /*-------------------------- USART2/3/4/5/7/8 Configuration --------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART234578) == RCC_PERIPHCLK_USART234578) 8004d80: 687b ldr r3, [r7, #4] 8004d82: 681b ldr r3, [r3, #0] 8004d84: f003 0302 and.w r3, r3, #2 8004d88: 2b00 cmp r3, #0 8004d8a: d038 beq.n 8004dfe { switch(PeriphClkInit->Usart234578ClockSelection) 8004d8c: 687b ldr r3, [r7, #4] 8004d8e: 6f5b ldr r3, [r3, #116] ; 0x74 8004d90: 2b05 cmp r3, #5 8004d92: d821 bhi.n 8004dd8 8004d94: a201 add r2, pc, #4 ; (adr r2, 8004d9c ) 8004d96: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8004d9a: bf00 nop 8004d9c: 08004ddf .word 0x08004ddf 8004da0: 08004db5 .word 0x08004db5 8004da4: 08004dc7 .word 0x08004dc7 8004da8: 08004ddf .word 0x08004ddf 8004dac: 08004ddf .word 0x08004ddf 8004db0: 08004ddf .word 0x08004ddf case RCC_USART234578CLKSOURCE_PCLK1: /* CD/D2 PCLK1 as clock source for USART2/3/4/5/7/8 */ /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; case RCC_USART234578CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART2/3/4/5/7/8 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE); 8004db4: 687b ldr r3, [r7, #4] 8004db6: 3304 adds r3, #4 8004db8: 2101 movs r1, #1 8004dba: 4618 mov r0, r3 8004dbc: f000 faf6 bl 80053ac 8004dc0: 4603 mov r3, r0 8004dc2: 75fb strb r3, [r7, #23] /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; 8004dc4: e00c b.n 8004de0 case RCC_USART234578CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART2/3/4/5/7/8 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE); 8004dc6: 687b ldr r3, [r7, #4] 8004dc8: 3324 adds r3, #36 ; 0x24 8004dca: 2101 movs r1, #1 8004dcc: 4618 mov r0, r3 8004dce: f000 fb9f bl 8005510 8004dd2: 4603 mov r3, r0 8004dd4: 75fb strb r3, [r7, #23] /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; 8004dd6: e003 b.n 8004de0 /* LSE, oscillator is used as source of USART2/3/4/5/7/8 clock */ /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8004dd8: 2301 movs r3, #1 8004dda: 75fb strb r3, [r7, #23] break; 8004ddc: e000 b.n 8004de0 break; 8004dde: bf00 nop } if(ret == HAL_OK) 8004de0: 7dfb ldrb r3, [r7, #23] 8004de2: 2b00 cmp r3, #0 8004de4: d109 bne.n 8004dfa { /* Set the source of USART2/3/4/5/7/8 clock */ __HAL_RCC_USART234578_CONFIG(PeriphClkInit->Usart234578ClockSelection); 8004de6: 4b77 ldr r3, [pc, #476] ; (8004fc4 ) 8004de8: 6d5b ldr r3, [r3, #84] ; 0x54 8004dea: f023 0207 bic.w r2, r3, #7 8004dee: 687b ldr r3, [r7, #4] 8004df0: 6f5b ldr r3, [r3, #116] ; 0x74 8004df2: 4974 ldr r1, [pc, #464] ; (8004fc4 ) 8004df4: 4313 orrs r3, r2 8004df6: 654b str r3, [r1, #84] ; 0x54 8004df8: e001 b.n 8004dfe } else { /* set overall return value */ status = ret; 8004dfa: 7dfb ldrb r3, [r7, #23] 8004dfc: 75bb strb r3, [r7, #22] } } /*-------------------------- LPUART1 Configuration -------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) 8004dfe: 687b ldr r3, [r7, #4] 8004e00: 681b ldr r3, [r3, #0] 8004e02: f003 0304 and.w r3, r3, #4 8004e06: 2b00 cmp r3, #0 8004e08: d03a beq.n 8004e80 { switch(PeriphClkInit->Lpuart1ClockSelection) 8004e0a: 687b ldr r3, [r7, #4] 8004e0c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 8004e10: 2b05 cmp r3, #5 8004e12: d821 bhi.n 8004e58 8004e14: a201 add r2, pc, #4 ; (adr r2, 8004e1c ) 8004e16: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8004e1a: bf00 nop 8004e1c: 08004e5f .word 0x08004e5f 8004e20: 08004e35 .word 0x08004e35 8004e24: 08004e47 .word 0x08004e47 8004e28: 08004e5f .word 0x08004e5f 8004e2c: 08004e5f .word 0x08004e5f 8004e30: 08004e5f .word 0x08004e5f case RCC_LPUART1CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPUART1 */ /* LPUART1 clock source configuration done later after clock selection check */ break; case RCC_LPUART1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPUART1 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE); 8004e34: 687b ldr r3, [r7, #4] 8004e36: 3304 adds r3, #4 8004e38: 2101 movs r1, #1 8004e3a: 4618 mov r0, r3 8004e3c: f000 fab6 bl 80053ac 8004e40: 4603 mov r3, r0 8004e42: 75fb strb r3, [r7, #23] /* LPUART1 clock source configuration done later after clock selection check */ break; 8004e44: e00c b.n 8004e60 case RCC_LPUART1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPUART1 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE); 8004e46: 687b ldr r3, [r7, #4] 8004e48: 3324 adds r3, #36 ; 0x24 8004e4a: 2101 movs r1, #1 8004e4c: 4618 mov r0, r3 8004e4e: f000 fb5f bl 8005510 8004e52: 4603 mov r3, r0 8004e54: 75fb strb r3, [r7, #23] /* LPUART1 clock source configuration done later after clock selection check */ break; 8004e56: e003 b.n 8004e60 /* LSE, oscillator is used as source of LPUART1 clock */ /* LPUART1 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8004e58: 2301 movs r3, #1 8004e5a: 75fb strb r3, [r7, #23] break; 8004e5c: e000 b.n 8004e60 break; 8004e5e: bf00 nop } if(ret == HAL_OK) 8004e60: 7dfb ldrb r3, [r7, #23] 8004e62: 2b00 cmp r3, #0 8004e64: d10a bne.n 8004e7c { /* Set the source of LPUART1 clock */ __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); 8004e66: 4b57 ldr r3, [pc, #348] ; (8004fc4 ) 8004e68: 6d9b ldr r3, [r3, #88] ; 0x58 8004e6a: f023 0207 bic.w r2, r3, #7 8004e6e: 687b ldr r3, [r7, #4] 8004e70: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 8004e74: 4953 ldr r1, [pc, #332] ; (8004fc4 ) 8004e76: 4313 orrs r3, r2 8004e78: 658b str r3, [r1, #88] ; 0x58 8004e7a: e001 b.n 8004e80 } else { /* set overall return value */ status = ret; 8004e7c: 7dfb ldrb r3, [r7, #23] 8004e7e: 75bb strb r3, [r7, #22] } } /*---------------------------- LPTIM1 configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) 8004e80: 687b ldr r3, [r7, #4] 8004e82: 681b ldr r3, [r3, #0] 8004e84: f003 0320 and.w r3, r3, #32 8004e88: 2b00 cmp r3, #0 8004e8a: d04b beq.n 8004f24 { switch(PeriphClkInit->Lptim1ClockSelection) 8004e8c: 687b ldr r3, [r7, #4] 8004e8e: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c 8004e92: f1b3 4fa0 cmp.w r3, #1342177280 ; 0x50000000 8004e96: d02e beq.n 8004ef6 8004e98: f1b3 4fa0 cmp.w r3, #1342177280 ; 0x50000000 8004e9c: d828 bhi.n 8004ef0 8004e9e: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 8004ea2: d02a beq.n 8004efa 8004ea4: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 8004ea8: d822 bhi.n 8004ef0 8004eaa: f1b3 5f40 cmp.w r3, #805306368 ; 0x30000000 8004eae: d026 beq.n 8004efe 8004eb0: f1b3 5f40 cmp.w r3, #805306368 ; 0x30000000 8004eb4: d81c bhi.n 8004ef0 8004eb6: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 8004eba: d010 beq.n 8004ede 8004ebc: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 8004ec0: d816 bhi.n 8004ef0 8004ec2: 2b00 cmp r3, #0 8004ec4: d01d beq.n 8004f02 8004ec6: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000 8004eca: d111 bne.n 8004ef0 /* LPTIM1 clock source configuration done later after clock selection check */ break; case RCC_LPTIM1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM1*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); 8004ecc: 687b ldr r3, [r7, #4] 8004ece: 3304 adds r3, #4 8004ed0: 2100 movs r1, #0 8004ed2: 4618 mov r0, r3 8004ed4: f000 fa6a bl 80053ac 8004ed8: 4603 mov r3, r0 8004eda: 75fb strb r3, [r7, #23] /* LPTIM1 clock source configuration done later after clock selection check */ break; 8004edc: e012 b.n 8004f04 case RCC_LPTIM1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM1*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE); 8004ede: 687b ldr r3, [r7, #4] 8004ee0: 3324 adds r3, #36 ; 0x24 8004ee2: 2102 movs r1, #2 8004ee4: 4618 mov r0, r3 8004ee6: f000 fb13 bl 8005510 8004eea: 4603 mov r3, r0 8004eec: 75fb strb r3, [r7, #23] /* LPTIM1 clock source configuration done later after clock selection check */ break; 8004eee: e009 b.n 8004f04 /* HSI, HSE, or CSI oscillator is used as source of LPTIM1 clock */ /* LPTIM1 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8004ef0: 2301 movs r3, #1 8004ef2: 75fb strb r3, [r7, #23] break; 8004ef4: e006 b.n 8004f04 break; 8004ef6: bf00 nop 8004ef8: e004 b.n 8004f04 break; 8004efa: bf00 nop 8004efc: e002 b.n 8004f04 break; 8004efe: bf00 nop 8004f00: e000 b.n 8004f04 break; 8004f02: bf00 nop } if(ret == HAL_OK) 8004f04: 7dfb ldrb r3, [r7, #23] 8004f06: 2b00 cmp r3, #0 8004f08: d10a bne.n 8004f20 { /* Set the source of LPTIM1 clock*/ __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); 8004f0a: 4b2e ldr r3, [pc, #184] ; (8004fc4 ) 8004f0c: 6d5b ldr r3, [r3, #84] ; 0x54 8004f0e: f023 42e0 bic.w r2, r3, #1879048192 ; 0x70000000 8004f12: 687b ldr r3, [r7, #4] 8004f14: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c 8004f18: 492a ldr r1, [pc, #168] ; (8004fc4 ) 8004f1a: 4313 orrs r3, r2 8004f1c: 654b str r3, [r1, #84] ; 0x54 8004f1e: e001 b.n 8004f24 } else { /* set overall return value */ status = ret; 8004f20: 7dfb ldrb r3, [r7, #23] 8004f22: 75bb strb r3, [r7, #22] } } /*---------------------------- LPTIM2 configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) 8004f24: 687b ldr r3, [r7, #4] 8004f26: 681b ldr r3, [r3, #0] 8004f28: f003 0340 and.w r3, r3, #64 ; 0x40 8004f2c: 2b00 cmp r3, #0 8004f2e: d04d beq.n 8004fcc { switch(PeriphClkInit->Lptim2ClockSelection) 8004f30: 687b ldr r3, [r7, #4] 8004f32: f8d3 3098 ldr.w r3, [r3, #152] ; 0x98 8004f36: f5b3 5fa0 cmp.w r3, #5120 ; 0x1400 8004f3a: d02e beq.n 8004f9a 8004f3c: f5b3 5fa0 cmp.w r3, #5120 ; 0x1400 8004f40: d828 bhi.n 8004f94 8004f42: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 8004f46: d02a beq.n 8004f9e 8004f48: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 8004f4c: d822 bhi.n 8004f94 8004f4e: f5b3 6f40 cmp.w r3, #3072 ; 0xc00 8004f52: d026 beq.n 8004fa2 8004f54: f5b3 6f40 cmp.w r3, #3072 ; 0xc00 8004f58: d81c bhi.n 8004f94 8004f5a: f5b3 6f00 cmp.w r3, #2048 ; 0x800 8004f5e: d010 beq.n 8004f82 8004f60: f5b3 6f00 cmp.w r3, #2048 ; 0x800 8004f64: d816 bhi.n 8004f94 8004f66: 2b00 cmp r3, #0 8004f68: d01d beq.n 8004fa6 8004f6a: f5b3 6f80 cmp.w r3, #1024 ; 0x400 8004f6e: d111 bne.n 8004f94 /* LPTIM2 clock source configuration done later after clock selection check */ break; case RCC_LPTIM2CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM2*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); 8004f70: 687b ldr r3, [r7, #4] 8004f72: 3304 adds r3, #4 8004f74: 2100 movs r1, #0 8004f76: 4618 mov r0, r3 8004f78: f000 fa18 bl 80053ac 8004f7c: 4603 mov r3, r0 8004f7e: 75fb strb r3, [r7, #23] /* LPTIM2 clock source configuration done later after clock selection check */ break; 8004f80: e012 b.n 8004fa8 case RCC_LPTIM2CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM2*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE); 8004f82: 687b ldr r3, [r7, #4] 8004f84: 3324 adds r3, #36 ; 0x24 8004f86: 2102 movs r1, #2 8004f88: 4618 mov r0, r3 8004f8a: f000 fac1 bl 8005510 8004f8e: 4603 mov r3, r0 8004f90: 75fb strb r3, [r7, #23] /* LPTIM2 clock source configuration done later after clock selection check */ break; 8004f92: e009 b.n 8004fa8 /* HSI, HSE, or CSI oscillator is used as source of LPTIM2 clock */ /* LPTIM2 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8004f94: 2301 movs r3, #1 8004f96: 75fb strb r3, [r7, #23] break; 8004f98: e006 b.n 8004fa8 break; 8004f9a: bf00 nop 8004f9c: e004 b.n 8004fa8 break; 8004f9e: bf00 nop 8004fa0: e002 b.n 8004fa8 break; 8004fa2: bf00 nop 8004fa4: e000 b.n 8004fa8 break; 8004fa6: bf00 nop } if(ret == HAL_OK) 8004fa8: 7dfb ldrb r3, [r7, #23] 8004faa: 2b00 cmp r3, #0 8004fac: d10c bne.n 8004fc8 { /* Set the source of LPTIM2 clock*/ __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection); 8004fae: 4b05 ldr r3, [pc, #20] ; (8004fc4 ) 8004fb0: 6d9b ldr r3, [r3, #88] ; 0x58 8004fb2: f423 52e0 bic.w r2, r3, #7168 ; 0x1c00 8004fb6: 687b ldr r3, [r7, #4] 8004fb8: f8d3 3098 ldr.w r3, [r3, #152] ; 0x98 8004fbc: 4901 ldr r1, [pc, #4] ; (8004fc4 ) 8004fbe: 4313 orrs r3, r2 8004fc0: 658b str r3, [r1, #88] ; 0x58 8004fc2: e003 b.n 8004fcc 8004fc4: 58024400 .word 0x58024400 } else { /* set overall return value */ status = ret; 8004fc8: 7dfb ldrb r3, [r7, #23] 8004fca: 75bb strb r3, [r7, #22] } } /*---------------------------- LPTIM345 configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM345) == RCC_PERIPHCLK_LPTIM345) 8004fcc: 687b ldr r3, [r7, #4] 8004fce: 681b ldr r3, [r3, #0] 8004fd0: f003 0380 and.w r3, r3, #128 ; 0x80 8004fd4: 2b00 cmp r3, #0 8004fd6: d04b beq.n 8005070 { switch(PeriphClkInit->Lptim345ClockSelection) 8004fd8: 687b ldr r3, [r7, #4] 8004fda: f8d3 309c ldr.w r3, [r3, #156] ; 0x9c 8004fde: f5b3 4f20 cmp.w r3, #40960 ; 0xa000 8004fe2: d02e beq.n 8005042 8004fe4: f5b3 4f20 cmp.w r3, #40960 ; 0xa000 8004fe8: d828 bhi.n 800503c 8004fea: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 8004fee: d02a beq.n 8005046 8004ff0: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 8004ff4: d822 bhi.n 800503c 8004ff6: f5b3 4fc0 cmp.w r3, #24576 ; 0x6000 8004ffa: d026 beq.n 800504a 8004ffc: f5b3 4fc0 cmp.w r3, #24576 ; 0x6000 8005000: d81c bhi.n 800503c 8005002: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 8005006: d010 beq.n 800502a 8005008: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 800500c: d816 bhi.n 800503c 800500e: 2b00 cmp r3, #0 8005010: d01d beq.n 800504e 8005012: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 8005016: d111 bne.n 800503c case RCC_LPTIM345CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPTIM3/4/5 */ /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; case RCC_LPTIM345CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM3/4/5 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); 8005018: 687b ldr r3, [r7, #4] 800501a: 3304 adds r3, #4 800501c: 2100 movs r1, #0 800501e: 4618 mov r0, r3 8005020: f000 f9c4 bl 80053ac 8005024: 4603 mov r3, r0 8005026: 75fb strb r3, [r7, #23] /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; 8005028: e012 b.n 8005050 case RCC_LPTIM345CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM3/4/5 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE); 800502a: 687b ldr r3, [r7, #4] 800502c: 3324 adds r3, #36 ; 0x24 800502e: 2102 movs r1, #2 8005030: 4618 mov r0, r3 8005032: f000 fa6d bl 8005510 8005036: 4603 mov r3, r0 8005038: 75fb strb r3, [r7, #23] /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; 800503a: e009 b.n 8005050 /* HSI, HSE, or CSI oscillator is used as source of LPTIM3/4/5 clock */ /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800503c: 2301 movs r3, #1 800503e: 75fb strb r3, [r7, #23] break; 8005040: e006 b.n 8005050 break; 8005042: bf00 nop 8005044: e004 b.n 8005050 break; 8005046: bf00 nop 8005048: e002 b.n 8005050 break; 800504a: bf00 nop 800504c: e000 b.n 8005050 break; 800504e: bf00 nop } if(ret == HAL_OK) 8005050: 7dfb ldrb r3, [r7, #23] 8005052: 2b00 cmp r3, #0 8005054: d10a bne.n 800506c { /* Set the source of LPTIM3/4/5 clock */ __HAL_RCC_LPTIM345_CONFIG(PeriphClkInit->Lptim345ClockSelection); 8005056: 4b9d ldr r3, [pc, #628] ; (80052cc ) 8005058: 6d9b ldr r3, [r3, #88] ; 0x58 800505a: f423 4260 bic.w r2, r3, #57344 ; 0xe000 800505e: 687b ldr r3, [r7, #4] 8005060: f8d3 309c ldr.w r3, [r3, #156] ; 0x9c 8005064: 4999 ldr r1, [pc, #612] ; (80052cc ) 8005066: 4313 orrs r3, r2 8005068: 658b str r3, [r1, #88] ; 0x58 800506a: e001 b.n 8005070 } else { /* set overall return value */ status = ret; 800506c: 7dfb ldrb r3, [r7, #23] 800506e: 75bb strb r3, [r7, #22] __HAL_RCC_I2C1235_CONFIG(PeriphClkInit->I2c1235ClockSelection); } #else if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C123) == RCC_PERIPHCLK_I2C123) 8005070: 687b ldr r3, [r7, #4] 8005072: 681b ldr r3, [r3, #0] 8005074: f003 0308 and.w r3, r3, #8 8005078: 2b00 cmp r3, #0 800507a: d01a beq.n 80050b2 { /* Check the parameters */ assert_param(IS_RCC_I2C123CLKSOURCE(PeriphClkInit->I2c123ClockSelection)); if ((PeriphClkInit->I2c123ClockSelection )== RCC_I2C123CLKSOURCE_PLL3 ) 800507c: 687b ldr r3, [r7, #4] 800507e: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80 8005082: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 8005086: d10a bne.n 800509e { if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!= HAL_OK) 8005088: 687b ldr r3, [r7, #4] 800508a: 3324 adds r3, #36 ; 0x24 800508c: 2102 movs r1, #2 800508e: 4618 mov r0, r3 8005090: f000 fa3e bl 8005510 8005094: 4603 mov r3, r0 8005096: 2b00 cmp r3, #0 8005098: d001 beq.n 800509e { status = HAL_ERROR; 800509a: 2301 movs r3, #1 800509c: 75bb strb r3, [r7, #22] } } __HAL_RCC_I2C123_CONFIG(PeriphClkInit->I2c123ClockSelection); 800509e: 4b8b ldr r3, [pc, #556] ; (80052cc ) 80050a0: 6d5b ldr r3, [r3, #84] ; 0x54 80050a2: f423 5240 bic.w r2, r3, #12288 ; 0x3000 80050a6: 687b ldr r3, [r7, #4] 80050a8: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80 80050ac: 4987 ldr r1, [pc, #540] ; (80052cc ) 80050ae: 4313 orrs r3, r2 80050b0: 654b str r3, [r1, #84] ; 0x54 } #endif /* I2C5 */ /*------------------------------ I2C4 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) 80050b2: 687b ldr r3, [r7, #4] 80050b4: 681b ldr r3, [r3, #0] 80050b6: f003 0310 and.w r3, r3, #16 80050ba: 2b00 cmp r3, #0 80050bc: d01a beq.n 80050f4 { /* Check the parameters */ assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection)); if ((PeriphClkInit->I2c4ClockSelection) == RCC_I2C4CLKSOURCE_PLL3 ) 80050be: 687b ldr r3, [r7, #4] 80050c0: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 80050c4: f5b3 7f80 cmp.w r3, #256 ; 0x100 80050c8: d10a bne.n 80050e0 { if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!= HAL_OK) 80050ca: 687b ldr r3, [r7, #4] 80050cc: 3324 adds r3, #36 ; 0x24 80050ce: 2102 movs r1, #2 80050d0: 4618 mov r0, r3 80050d2: f000 fa1d bl 8005510 80050d6: 4603 mov r3, r0 80050d8: 2b00 cmp r3, #0 80050da: d001 beq.n 80050e0 { status = HAL_ERROR; 80050dc: 2301 movs r3, #1 80050de: 75bb strb r3, [r7, #22] } } __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection); 80050e0: 4b7a ldr r3, [pc, #488] ; (80052cc ) 80050e2: 6d9b ldr r3, [r3, #88] ; 0x58 80050e4: f423 7240 bic.w r2, r3, #768 ; 0x300 80050e8: 687b ldr r3, [r7, #4] 80050ea: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 80050ee: 4977 ldr r1, [pc, #476] ; (80052cc ) 80050f0: 4313 orrs r3, r2 80050f2: 658b str r3, [r1, #88] ; 0x58 } /*---------------------------- ADC configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) 80050f4: 687b ldr r3, [r7, #4] 80050f6: 681b ldr r3, [r3, #0] 80050f8: f403 2300 and.w r3, r3, #524288 ; 0x80000 80050fc: 2b00 cmp r3, #0 80050fe: d034 beq.n 800516a { switch(PeriphClkInit->AdcClockSelection) 8005100: 687b ldr r3, [r7, #4] 8005102: f8d3 30a0 ldr.w r3, [r3, #160] ; 0xa0 8005106: f5b3 3f00 cmp.w r3, #131072 ; 0x20000 800510a: d01d beq.n 8005148 800510c: f5b3 3f00 cmp.w r3, #131072 ; 0x20000 8005110: d817 bhi.n 8005142 8005112: 2b00 cmp r3, #0 8005114: d003 beq.n 800511e 8005116: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 800511a: d009 beq.n 8005130 800511c: e011 b.n 8005142 { case RCC_ADCCLKSOURCE_PLL2: /* PLL2 is used as clock source for ADC*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); 800511e: 687b ldr r3, [r7, #4] 8005120: 3304 adds r3, #4 8005122: 2100 movs r1, #0 8005124: 4618 mov r0, r3 8005126: f000 f941 bl 80053ac 800512a: 4603 mov r3, r0 800512c: 75fb strb r3, [r7, #23] /* ADC clock source configuration done later after clock selection check */ break; 800512e: e00c b.n 800514a case RCC_ADCCLKSOURCE_PLL3: /* PLL3 is used as clock source for ADC*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE); 8005130: 687b ldr r3, [r7, #4] 8005132: 3324 adds r3, #36 ; 0x24 8005134: 2102 movs r1, #2 8005136: 4618 mov r0, r3 8005138: f000 f9ea bl 8005510 800513c: 4603 mov r3, r0 800513e: 75fb strb r3, [r7, #23] /* ADC clock source configuration done later after clock selection check */ break; 8005140: e003 b.n 800514a /* HSI, HSE, or CSI oscillator is used as source of ADC clock */ /* ADC clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8005142: 2301 movs r3, #1 8005144: 75fb strb r3, [r7, #23] break; 8005146: e000 b.n 800514a break; 8005148: bf00 nop } if(ret == HAL_OK) 800514a: 7dfb ldrb r3, [r7, #23] 800514c: 2b00 cmp r3, #0 800514e: d10a bne.n 8005166 { /* Set the source of ADC clock*/ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); 8005150: 4b5e ldr r3, [pc, #376] ; (80052cc ) 8005152: 6d9b ldr r3, [r3, #88] ; 0x58 8005154: f423 3240 bic.w r2, r3, #196608 ; 0x30000 8005158: 687b ldr r3, [r7, #4] 800515a: f8d3 30a0 ldr.w r3, [r3, #160] ; 0xa0 800515e: 495b ldr r1, [pc, #364] ; (80052cc ) 8005160: 4313 orrs r3, r2 8005162: 658b str r3, [r1, #88] ; 0x58 8005164: e001 b.n 800516a } else { /* set overall return value */ status = ret; 8005166: 7dfb ldrb r3, [r7, #23] 8005168: 75bb strb r3, [r7, #22] } } /*------------------------------ USB Configuration -------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) 800516a: 687b ldr r3, [r7, #4] 800516c: 681b ldr r3, [r3, #0] 800516e: f403 2380 and.w r3, r3, #262144 ; 0x40000 8005172: 2b00 cmp r3, #0 8005174: d033 beq.n 80051de { switch(PeriphClkInit->UsbClockSelection) 8005176: 687b ldr r3, [r7, #4] 8005178: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 800517c: f5b3 1f40 cmp.w r3, #3145728 ; 0x300000 8005180: d01c beq.n 80051bc 8005182: f5b3 1f40 cmp.w r3, #3145728 ; 0x300000 8005186: d816 bhi.n 80051b6 8005188: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 800518c: d003 beq.n 8005196 800518e: f5b3 1f00 cmp.w r3, #2097152 ; 0x200000 8005192: d007 beq.n 80051a4 8005194: e00f b.n 80051b6 { case RCC_USBCLKSOURCE_PLL: /* PLL is used as clock source for USB*/ /* Enable USB Clock output generated form System USB . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8005196: 4b4d ldr r3, [pc, #308] ; (80052cc ) 8005198: 6adb ldr r3, [r3, #44] ; 0x2c 800519a: 4a4c ldr r2, [pc, #304] ; (80052cc ) 800519c: f443 3300 orr.w r3, r3, #131072 ; 0x20000 80051a0: 62d3 str r3, [r2, #44] ; 0x2c /* USB clock source configuration done later after clock selection check */ break; 80051a2: e00c b.n 80051be case RCC_USBCLKSOURCE_PLL3: /* PLL3 is used as clock source for USB*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE); 80051a4: 687b ldr r3, [r7, #4] 80051a6: 3324 adds r3, #36 ; 0x24 80051a8: 2101 movs r1, #1 80051aa: 4618 mov r0, r3 80051ac: f000 f9b0 bl 8005510 80051b0: 4603 mov r3, r0 80051b2: 75fb strb r3, [r7, #23] /* USB clock source configuration done later after clock selection check */ break; 80051b4: e003 b.n 80051be /* HSI48 oscillator is used as source of USB clock */ /* USB clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 80051b6: 2301 movs r3, #1 80051b8: 75fb strb r3, [r7, #23] break; 80051ba: e000 b.n 80051be break; 80051bc: bf00 nop } if(ret == HAL_OK) 80051be: 7dfb ldrb r3, [r7, #23] 80051c0: 2b00 cmp r3, #0 80051c2: d10a bne.n 80051da { /* Set the source of USB clock*/ __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); 80051c4: 4b41 ldr r3, [pc, #260] ; (80052cc ) 80051c6: 6d5b ldr r3, [r3, #84] ; 0x54 80051c8: f423 1240 bic.w r2, r3, #3145728 ; 0x300000 80051cc: 687b ldr r3, [r7, #4] 80051ce: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 80051d2: 493e ldr r1, [pc, #248] ; (80052cc ) 80051d4: 4313 orrs r3, r2 80051d6: 654b str r3, [r1, #84] ; 0x54 80051d8: e001 b.n 80051de } else { /* set overall return value */ status = ret; 80051da: 7dfb ldrb r3, [r7, #23] 80051dc: 75bb strb r3, [r7, #22] } } /*------------------------------------- SDMMC Configuration ------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC) == RCC_PERIPHCLK_SDMMC) 80051de: 687b ldr r3, [r7, #4] 80051e0: 681b ldr r3, [r3, #0] 80051e2: f403 3380 and.w r3, r3, #65536 ; 0x10000 80051e6: 2b00 cmp r3, #0 80051e8: d029 beq.n 800523e { /* Check the parameters */ assert_param(IS_RCC_SDMMC(PeriphClkInit->SdmmcClockSelection)); switch(PeriphClkInit->SdmmcClockSelection) 80051ea: 687b ldr r3, [r7, #4] 80051ec: 6cdb ldr r3, [r3, #76] ; 0x4c 80051ee: 2b00 cmp r3, #0 80051f0: d003 beq.n 80051fa 80051f2: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 80051f6: d007 beq.n 8005208 80051f8: e00f b.n 800521a { case RCC_SDMMCCLKSOURCE_PLL: /* PLL is used as clock source for SDMMC*/ /* Enable SDMMC Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 80051fa: 4b34 ldr r3, [pc, #208] ; (80052cc ) 80051fc: 6adb ldr r3, [r3, #44] ; 0x2c 80051fe: 4a33 ldr r2, [pc, #204] ; (80052cc ) 8005200: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8005204: 62d3 str r3, [r2, #44] ; 0x2c /* SDMMC clock source configuration done later after clock selection check */ break; 8005206: e00b b.n 8005220 case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for SDMMC*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE); 8005208: 687b ldr r3, [r7, #4] 800520a: 3304 adds r3, #4 800520c: 2102 movs r1, #2 800520e: 4618 mov r0, r3 8005210: f000 f8cc bl 80053ac 8005214: 4603 mov r3, r0 8005216: 75fb strb r3, [r7, #23] /* SDMMC clock source configuration done later after clock selection check */ break; 8005218: e002 b.n 8005220 default: ret = HAL_ERROR; 800521a: 2301 movs r3, #1 800521c: 75fb strb r3, [r7, #23] break; 800521e: bf00 nop } if(ret == HAL_OK) 8005220: 7dfb ldrb r3, [r7, #23] 8005222: 2b00 cmp r3, #0 8005224: d109 bne.n 800523a { /* Set the source of SDMMC clock*/ __HAL_RCC_SDMMC_CONFIG(PeriphClkInit->SdmmcClockSelection); 8005226: 4b29 ldr r3, [pc, #164] ; (80052cc ) 8005228: 6cdb ldr r3, [r3, #76] ; 0x4c 800522a: f423 3280 bic.w r2, r3, #65536 ; 0x10000 800522e: 687b ldr r3, [r7, #4] 8005230: 6cdb ldr r3, [r3, #76] ; 0x4c 8005232: 4926 ldr r1, [pc, #152] ; (80052cc ) 8005234: 4313 orrs r3, r2 8005236: 64cb str r3, [r1, #76] ; 0x4c 8005238: e001 b.n 800523e } else { /* set overall return value */ status = ret; 800523a: 7dfb ldrb r3, [r7, #23] 800523c: 75bb strb r3, [r7, #22] } } #if defined(LTDC) /*-------------------------------------- LTDC Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) 800523e: 687b ldr r3, [r7, #4] 8005240: 681b ldr r3, [r3, #0] 8005242: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 8005246: 2b00 cmp r3, #0 8005248: d00a beq.n 8005260 { if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!=HAL_OK) 800524a: 687b ldr r3, [r7, #4] 800524c: 3324 adds r3, #36 ; 0x24 800524e: 2102 movs r1, #2 8005250: 4618 mov r0, r3 8005252: f000 f95d bl 8005510 8005256: 4603 mov r3, r0 8005258: 2b00 cmp r3, #0 800525a: d001 beq.n 8005260 { status=HAL_ERROR; 800525c: 2301 movs r3, #1 800525e: 75bb strb r3, [r7, #22] } } #endif /* LTDC */ /*------------------------------ RNG Configuration -------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) 8005260: 687b ldr r3, [r7, #4] 8005262: 681b ldr r3, [r3, #0] 8005264: f403 3300 and.w r3, r3, #131072 ; 0x20000 8005268: 2b00 cmp r3, #0 800526a: d033 beq.n 80052d4 { switch(PeriphClkInit->RngClockSelection) 800526c: 687b ldr r3, [r7, #4] 800526e: 6fdb ldr r3, [r3, #124] ; 0x7c 8005270: f5b3 7f40 cmp.w r3, #768 ; 0x300 8005274: d017 beq.n 80052a6 8005276: f5b3 7f40 cmp.w r3, #768 ; 0x300 800527a: d811 bhi.n 80052a0 800527c: f5b3 7f00 cmp.w r3, #512 ; 0x200 8005280: d013 beq.n 80052aa 8005282: f5b3 7f00 cmp.w r3, #512 ; 0x200 8005286: d80b bhi.n 80052a0 8005288: 2b00 cmp r3, #0 800528a: d010 beq.n 80052ae 800528c: f5b3 7f80 cmp.w r3, #256 ; 0x100 8005290: d106 bne.n 80052a0 { case RCC_RNGCLKSOURCE_PLL: /* PLL is used as clock source for RNG*/ /* Enable RNG Clock output generated form System RNG . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8005292: 4b0e ldr r3, [pc, #56] ; (80052cc ) 8005294: 6adb ldr r3, [r3, #44] ; 0x2c 8005296: 4a0d ldr r2, [pc, #52] ; (80052cc ) 8005298: f443 3300 orr.w r3, r3, #131072 ; 0x20000 800529c: 62d3 str r3, [r2, #44] ; 0x2c /* RNG clock source configuration done later after clock selection check */ break; 800529e: e007 b.n 80052b0 /* HSI48 oscillator is used as source of RNG clock */ /* RNG clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 80052a0: 2301 movs r3, #1 80052a2: 75fb strb r3, [r7, #23] break; 80052a4: e004 b.n 80052b0 break; 80052a6: bf00 nop 80052a8: e002 b.n 80052b0 break; 80052aa: bf00 nop 80052ac: e000 b.n 80052b0 break; 80052ae: bf00 nop } if(ret == HAL_OK) 80052b0: 7dfb ldrb r3, [r7, #23] 80052b2: 2b00 cmp r3, #0 80052b4: d10c bne.n 80052d0 { /* Set the source of RNG clock*/ __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection); 80052b6: 4b05 ldr r3, [pc, #20] ; (80052cc ) 80052b8: 6d5b ldr r3, [r3, #84] ; 0x54 80052ba: f423 7240 bic.w r2, r3, #768 ; 0x300 80052be: 687b ldr r3, [r7, #4] 80052c0: 6fdb ldr r3, [r3, #124] ; 0x7c 80052c2: 4902 ldr r1, [pc, #8] ; (80052cc ) 80052c4: 4313 orrs r3, r2 80052c6: 654b str r3, [r1, #84] ; 0x54 80052c8: e004 b.n 80052d4 80052ca: bf00 nop 80052cc: 58024400 .word 0x58024400 } else { /* set overall return value */ status = ret; 80052d0: 7dfb ldrb r3, [r7, #23] 80052d2: 75bb strb r3, [r7, #22] } } /*------------------------------ SWPMI1 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) 80052d4: 687b ldr r3, [r7, #4] 80052d6: 681b ldr r3, [r3, #0] 80052d8: f403 1380 and.w r3, r3, #1048576 ; 0x100000 80052dc: 2b00 cmp r3, #0 80052de: d008 beq.n 80052f2 { /* Check the parameters */ assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection)); /* Configure the SWPMI1 interface clock source */ __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection); 80052e0: 4b31 ldr r3, [pc, #196] ; (80053a8 ) 80052e2: 6d1b ldr r3, [r3, #80] ; 0x50 80052e4: f023 4200 bic.w r2, r3, #2147483648 ; 0x80000000 80052e8: 687b ldr r3, [r7, #4] 80052ea: 6f1b ldr r3, [r3, #112] ; 0x70 80052ec: 492e ldr r1, [pc, #184] ; (80053a8 ) 80052ee: 4313 orrs r3, r2 80052f0: 650b str r3, [r1, #80] ; 0x50 } #if defined(HRTIM1) /*------------------------------ HRTIM1 clock Configuration ----------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HRTIM1) == RCC_PERIPHCLK_HRTIM1) 80052f2: 687b ldr r3, [r7, #4] 80052f4: 681b ldr r3, [r3, #0] 80052f6: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 80052fa: 2b00 cmp r3, #0 80052fc: d009 beq.n 8005312 { /* Check the parameters */ assert_param(IS_RCC_HRTIM1CLKSOURCE(PeriphClkInit->Hrtim1ClockSelection)); /* Configure the HRTIM1 clock source */ __HAL_RCC_HRTIM1_CONFIG(PeriphClkInit->Hrtim1ClockSelection); 80052fe: 4b2a ldr r3, [pc, #168] ; (80053a8 ) 8005300: 691b ldr r3, [r3, #16] 8005302: f423 4280 bic.w r2, r3, #16384 ; 0x4000 8005306: 687b ldr r3, [r7, #4] 8005308: f8d3 30b4 ldr.w r3, [r3, #180] ; 0xb4 800530c: 4926 ldr r1, [pc, #152] ; (80053a8 ) 800530e: 4313 orrs r3, r2 8005310: 610b str r3, [r1, #16] } #endif /*HRTIM1*/ /*------------------------------ DFSDM1 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) 8005312: 687b ldr r3, [r7, #4] 8005314: 681b ldr r3, [r3, #0] 8005316: f403 1300 and.w r3, r3, #2097152 ; 0x200000 800531a: 2b00 cmp r3, #0 800531c: d008 beq.n 8005330 { /* Check the parameters */ assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection)); /* Configure the DFSDM1 interface clock source */ __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection); 800531e: 4b22 ldr r3, [pc, #136] ; (80053a8 ) 8005320: 6d1b ldr r3, [r3, #80] ; 0x50 8005322: f023 7280 bic.w r2, r3, #16777216 ; 0x1000000 8005326: 687b ldr r3, [r7, #4] 8005328: 6e9b ldr r3, [r3, #104] ; 0x68 800532a: 491f ldr r1, [pc, #124] ; (80053a8 ) 800532c: 4313 orrs r3, r2 800532e: 650b str r3, [r1, #80] ; 0x50 __HAL_RCC_DFSDM2_CONFIG(PeriphClkInit->Dfsdm2ClockSelection); } #endif /* DFSDM2 */ /*------------------------------------ TIM configuration --------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) 8005330: 687b ldr r3, [r7, #4] 8005332: 681b ldr r3, [r3, #0] 8005334: f003 4380 and.w r3, r3, #1073741824 ; 0x40000000 8005338: 2b00 cmp r3, #0 800533a: d00d beq.n 8005358 { /* Check the parameters */ assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection)); /* Configure Timer Prescaler */ __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); 800533c: 4b1a ldr r3, [pc, #104] ; (80053a8 ) 800533e: 691b ldr r3, [r3, #16] 8005340: 4a19 ldr r2, [pc, #100] ; (80053a8 ) 8005342: f423 4300 bic.w r3, r3, #32768 ; 0x8000 8005346: 6113 str r3, [r2, #16] 8005348: 4b17 ldr r3, [pc, #92] ; (80053a8 ) 800534a: 691a ldr r2, [r3, #16] 800534c: 687b ldr r3, [r7, #4] 800534e: f8d3 30b8 ldr.w r3, [r3, #184] ; 0xb8 8005352: 4915 ldr r1, [pc, #84] ; (80053a8 ) 8005354: 4313 orrs r3, r2 8005356: 610b str r3, [r1, #16] } /*------------------------------------ CKPER configuration --------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER) 8005358: 687b ldr r3, [r7, #4] 800535a: 681b ldr r3, [r3, #0] 800535c: 2b00 cmp r3, #0 800535e: da08 bge.n 8005372 { /* Check the parameters */ assert_param(IS_RCC_CLKPSOURCE(PeriphClkInit->CkperClockSelection)); /* Configure the CKPER clock source */ __HAL_RCC_CLKP_CONFIG(PeriphClkInit->CkperClockSelection); 8005360: 4b11 ldr r3, [pc, #68] ; (80053a8 ) 8005362: 6cdb ldr r3, [r3, #76] ; 0x4c 8005364: f023 5240 bic.w r2, r3, #805306368 ; 0x30000000 8005368: 687b ldr r3, [r7, #4] 800536a: 6d1b ldr r3, [r3, #80] ; 0x50 800536c: 490e ldr r1, [pc, #56] ; (80053a8 ) 800536e: 4313 orrs r3, r2 8005370: 64cb str r3, [r1, #76] ; 0x4c } /*------------------------------ CEC Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) 8005372: 687b ldr r3, [r7, #4] 8005374: 681b ldr r3, [r3, #0] 8005376: f403 0300 and.w r3, r3, #8388608 ; 0x800000 800537a: 2b00 cmp r3, #0 800537c: d009 beq.n 8005392 { /* Check the parameters */ assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); /* Configure the CEC interface clock source */ __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); 800537e: 4b0a ldr r3, [pc, #40] ; (80053a8 ) 8005380: 6d5b ldr r3, [r3, #84] ; 0x54 8005382: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000 8005386: 687b ldr r3, [r7, #4] 8005388: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 800538c: 4906 ldr r1, [pc, #24] ; (80053a8 ) 800538e: 4313 orrs r3, r2 8005390: 654b str r3, [r1, #84] ; 0x54 } if (status == HAL_OK) 8005392: 7dbb ldrb r3, [r7, #22] 8005394: 2b00 cmp r3, #0 8005396: d101 bne.n 800539c { return HAL_OK; 8005398: 2300 movs r3, #0 800539a: e000 b.n 800539e } return HAL_ERROR; 800539c: 2301 movs r3, #1 } 800539e: 4618 mov r0, r3 80053a0: 3718 adds r7, #24 80053a2: 46bd mov sp, r7 80053a4: bd80 pop {r7, pc} 80053a6: bf00 nop 80053a8: 58024400 .word 0x58024400 080053ac : * @note PLL2 is temporary disabled to apply new parameters * * @retval HAL status */ static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider) { 80053ac: b580 push {r7, lr} 80053ae: b084 sub sp, #16 80053b0: af00 add r7, sp, #0 80053b2: 6078 str r0, [r7, #4] 80053b4: 6039 str r1, [r7, #0] uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; 80053b6: 2300 movs r3, #0 80053b8: 73fb strb r3, [r7, #15] assert_param(IS_RCC_PLL2RGE_VALUE(pll2->PLL2RGE)); assert_param(IS_RCC_PLL2VCO_VALUE(pll2->PLL2VCOSEL)); assert_param(IS_RCC_PLLFRACN_VALUE(pll2->PLL2FRACN)); /* Check that PLL2 OSC clock source is already set */ if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 80053ba: 4b53 ldr r3, [pc, #332] ; (8005508 ) 80053bc: 6a9b ldr r3, [r3, #40] ; 0x28 80053be: f003 0303 and.w r3, r3, #3 80053c2: 2b03 cmp r3, #3 80053c4: d101 bne.n 80053ca { return HAL_ERROR; 80053c6: 2301 movs r3, #1 80053c8: e099 b.n 80054fe else { /* Disable PLL2. */ __HAL_RCC_PLL2_DISABLE(); 80053ca: 4b4f ldr r3, [pc, #316] ; (8005508 ) 80053cc: 681b ldr r3, [r3, #0] 80053ce: 4a4e ldr r2, [pc, #312] ; (8005508 ) 80053d0: f023 6380 bic.w r3, r3, #67108864 ; 0x4000000 80053d4: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80053d6: f7fb ff4b bl 8001270 80053da: 60b8 str r0, [r7, #8] /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U) 80053dc: e008 b.n 80053f0 { if( (HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE) 80053de: f7fb ff47 bl 8001270 80053e2: 4602 mov r2, r0 80053e4: 68bb ldr r3, [r7, #8] 80053e6: 1ad3 subs r3, r2, r3 80053e8: 2b02 cmp r3, #2 80053ea: d901 bls.n 80053f0 { return HAL_TIMEOUT; 80053ec: 2303 movs r3, #3 80053ee: e086 b.n 80054fe while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U) 80053f0: 4b45 ldr r3, [pc, #276] ; (8005508 ) 80053f2: 681b ldr r3, [r3, #0] 80053f4: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 80053f8: 2b00 cmp r3, #0 80053fa: d1f0 bne.n 80053de } } /* Configure PLL2 multiplication and division factors. */ __HAL_RCC_PLL2_CONFIG(pll2->PLL2M, 80053fc: 4b42 ldr r3, [pc, #264] ; (8005508 ) 80053fe: 6a9b ldr r3, [r3, #40] ; 0x28 8005400: f423 327c bic.w r2, r3, #258048 ; 0x3f000 8005404: 687b ldr r3, [r7, #4] 8005406: 681b ldr r3, [r3, #0] 8005408: 031b lsls r3, r3, #12 800540a: 493f ldr r1, [pc, #252] ; (8005508 ) 800540c: 4313 orrs r3, r2 800540e: 628b str r3, [r1, #40] ; 0x28 8005410: 687b ldr r3, [r7, #4] 8005412: 685b ldr r3, [r3, #4] 8005414: 3b01 subs r3, #1 8005416: f3c3 0208 ubfx r2, r3, #0, #9 800541a: 687b ldr r3, [r7, #4] 800541c: 689b ldr r3, [r3, #8] 800541e: 3b01 subs r3, #1 8005420: 025b lsls r3, r3, #9 8005422: b29b uxth r3, r3 8005424: 431a orrs r2, r3 8005426: 687b ldr r3, [r7, #4] 8005428: 68db ldr r3, [r3, #12] 800542a: 3b01 subs r3, #1 800542c: 041b lsls r3, r3, #16 800542e: f403 03fe and.w r3, r3, #8323072 ; 0x7f0000 8005432: 431a orrs r2, r3 8005434: 687b ldr r3, [r7, #4] 8005436: 691b ldr r3, [r3, #16] 8005438: 3b01 subs r3, #1 800543a: 061b lsls r3, r3, #24 800543c: f003 43fe and.w r3, r3, #2130706432 ; 0x7f000000 8005440: 4931 ldr r1, [pc, #196] ; (8005508 ) 8005442: 4313 orrs r3, r2 8005444: 638b str r3, [r1, #56] ; 0x38 pll2->PLL2P, pll2->PLL2Q, pll2->PLL2R); /* Select PLL2 input reference frequency range: VCI */ __HAL_RCC_PLL2_VCIRANGE(pll2->PLL2RGE) ; 8005446: 4b30 ldr r3, [pc, #192] ; (8005508 ) 8005448: 6adb ldr r3, [r3, #44] ; 0x2c 800544a: f023 02c0 bic.w r2, r3, #192 ; 0xc0 800544e: 687b ldr r3, [r7, #4] 8005450: 695b ldr r3, [r3, #20] 8005452: 492d ldr r1, [pc, #180] ; (8005508 ) 8005454: 4313 orrs r3, r2 8005456: 62cb str r3, [r1, #44] ; 0x2c /* Select PLL2 output frequency range : VCO */ __HAL_RCC_PLL2_VCORANGE(pll2->PLL2VCOSEL) ; 8005458: 4b2b ldr r3, [pc, #172] ; (8005508 ) 800545a: 6adb ldr r3, [r3, #44] ; 0x2c 800545c: f023 0220 bic.w r2, r3, #32 8005460: 687b ldr r3, [r7, #4] 8005462: 699b ldr r3, [r3, #24] 8005464: 4928 ldr r1, [pc, #160] ; (8005508 ) 8005466: 4313 orrs r3, r2 8005468: 62cb str r3, [r1, #44] ; 0x2c /* Disable PLL2FRACN . */ __HAL_RCC_PLL2FRACN_DISABLE(); 800546a: 4b27 ldr r3, [pc, #156] ; (8005508 ) 800546c: 6adb ldr r3, [r3, #44] ; 0x2c 800546e: 4a26 ldr r2, [pc, #152] ; (8005508 ) 8005470: f023 0310 bic.w r3, r3, #16 8005474: 62d3 str r3, [r2, #44] ; 0x2c /* Configures PLL2 clock Fractional Part Of The Multiplication Factor */ __HAL_RCC_PLL2FRACN_CONFIG(pll2->PLL2FRACN); 8005476: 4b24 ldr r3, [pc, #144] ; (8005508 ) 8005478: 6bda ldr r2, [r3, #60] ; 0x3c 800547a: 4b24 ldr r3, [pc, #144] ; (800550c ) 800547c: 4013 ands r3, r2 800547e: 687a ldr r2, [r7, #4] 8005480: 69d2 ldr r2, [r2, #28] 8005482: 00d2 lsls r2, r2, #3 8005484: 4920 ldr r1, [pc, #128] ; (8005508 ) 8005486: 4313 orrs r3, r2 8005488: 63cb str r3, [r1, #60] ; 0x3c /* Enable PLL2FRACN . */ __HAL_RCC_PLL2FRACN_ENABLE(); 800548a: 4b1f ldr r3, [pc, #124] ; (8005508 ) 800548c: 6adb ldr r3, [r3, #44] ; 0x2c 800548e: 4a1e ldr r2, [pc, #120] ; (8005508 ) 8005490: f043 0310 orr.w r3, r3, #16 8005494: 62d3 str r3, [r2, #44] ; 0x2c /* Enable the PLL2 clock output */ if(Divider == DIVIDER_P_UPDATE) 8005496: 683b ldr r3, [r7, #0] 8005498: 2b00 cmp r3, #0 800549a: d106 bne.n 80054aa { __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP); 800549c: 4b1a ldr r3, [pc, #104] ; (8005508 ) 800549e: 6adb ldr r3, [r3, #44] ; 0x2c 80054a0: 4a19 ldr r2, [pc, #100] ; (8005508 ) 80054a2: f443 2300 orr.w r3, r3, #524288 ; 0x80000 80054a6: 62d3 str r3, [r2, #44] ; 0x2c 80054a8: e00f b.n 80054ca } else if(Divider == DIVIDER_Q_UPDATE) 80054aa: 683b ldr r3, [r7, #0] 80054ac: 2b01 cmp r3, #1 80054ae: d106 bne.n 80054be { __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ); 80054b0: 4b15 ldr r3, [pc, #84] ; (8005508 ) 80054b2: 6adb ldr r3, [r3, #44] ; 0x2c 80054b4: 4a14 ldr r2, [pc, #80] ; (8005508 ) 80054b6: f443 1380 orr.w r3, r3, #1048576 ; 0x100000 80054ba: 62d3 str r3, [r2, #44] ; 0x2c 80054bc: e005 b.n 80054ca } else { __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVR); 80054be: 4b12 ldr r3, [pc, #72] ; (8005508 ) 80054c0: 6adb ldr r3, [r3, #44] ; 0x2c 80054c2: 4a11 ldr r2, [pc, #68] ; (8005508 ) 80054c4: f443 1300 orr.w r3, r3, #2097152 ; 0x200000 80054c8: 62d3 str r3, [r2, #44] ; 0x2c } /* Enable PLL2. */ __HAL_RCC_PLL2_ENABLE(); 80054ca: 4b0f ldr r3, [pc, #60] ; (8005508 ) 80054cc: 681b ldr r3, [r3, #0] 80054ce: 4a0e ldr r2, [pc, #56] ; (8005508 ) 80054d0: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000 80054d4: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80054d6: f7fb fecb bl 8001270 80054da: 60b8 str r0, [r7, #8] /* Wait till PLL2 is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U) 80054dc: e008 b.n 80054f0 { if( (HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE) 80054de: f7fb fec7 bl 8001270 80054e2: 4602 mov r2, r0 80054e4: 68bb ldr r3, [r7, #8] 80054e6: 1ad3 subs r3, r2, r3 80054e8: 2b02 cmp r3, #2 80054ea: d901 bls.n 80054f0 { return HAL_TIMEOUT; 80054ec: 2303 movs r3, #3 80054ee: e006 b.n 80054fe while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U) 80054f0: 4b05 ldr r3, [pc, #20] ; (8005508 ) 80054f2: 681b ldr r3, [r3, #0] 80054f4: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 80054f8: 2b00 cmp r3, #0 80054fa: d0f0 beq.n 80054de } } return status; 80054fc: 7bfb ldrb r3, [r7, #15] } 80054fe: 4618 mov r0, r3 8005500: 3710 adds r7, #16 8005502: 46bd mov sp, r7 8005504: bd80 pop {r7, pc} 8005506: bf00 nop 8005508: 58024400 .word 0x58024400 800550c: ffff0007 .word 0xffff0007 08005510 : * @note PLL3 is temporary disabled to apply new parameters * * @retval HAL status */ static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider) { 8005510: b580 push {r7, lr} 8005512: b084 sub sp, #16 8005514: af00 add r7, sp, #0 8005516: 6078 str r0, [r7, #4] 8005518: 6039 str r1, [r7, #0] uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; 800551a: 2300 movs r3, #0 800551c: 73fb strb r3, [r7, #15] assert_param(IS_RCC_PLL3RGE_VALUE(pll3->PLL3RGE)); assert_param(IS_RCC_PLL3VCO_VALUE(pll3->PLL3VCOSEL)); assert_param(IS_RCC_PLLFRACN_VALUE(pll3->PLL3FRACN)); /* Check that PLL3 OSC clock source is already set */ if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 800551e: 4b53 ldr r3, [pc, #332] ; (800566c ) 8005520: 6a9b ldr r3, [r3, #40] ; 0x28 8005522: f003 0303 and.w r3, r3, #3 8005526: 2b03 cmp r3, #3 8005528: d101 bne.n 800552e { return HAL_ERROR; 800552a: 2301 movs r3, #1 800552c: e099 b.n 8005662 else { /* Disable PLL3. */ __HAL_RCC_PLL3_DISABLE(); 800552e: 4b4f ldr r3, [pc, #316] ; (800566c ) 8005530: 681b ldr r3, [r3, #0] 8005532: 4a4e ldr r2, [pc, #312] ; (800566c ) 8005534: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 8005538: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800553a: f7fb fe99 bl 8001270 800553e: 60b8 str r0, [r7, #8] /* Wait till PLL3 is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U) 8005540: e008 b.n 8005554 { if( (HAL_GetTick() - tickstart ) > PLL3_TIMEOUT_VALUE) 8005542: f7fb fe95 bl 8001270 8005546: 4602 mov r2, r0 8005548: 68bb ldr r3, [r7, #8] 800554a: 1ad3 subs r3, r2, r3 800554c: 2b02 cmp r3, #2 800554e: d901 bls.n 8005554 { return HAL_TIMEOUT; 8005550: 2303 movs r3, #3 8005552: e086 b.n 8005662 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U) 8005554: 4b45 ldr r3, [pc, #276] ; (800566c ) 8005556: 681b ldr r3, [r3, #0] 8005558: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 800555c: 2b00 cmp r3, #0 800555e: d1f0 bne.n 8005542 } } /* Configure the PLL3 multiplication and division factors. */ __HAL_RCC_PLL3_CONFIG(pll3->PLL3M, 8005560: 4b42 ldr r3, [pc, #264] ; (800566c ) 8005562: 6a9b ldr r3, [r3, #40] ; 0x28 8005564: f023 727c bic.w r2, r3, #66060288 ; 0x3f00000 8005568: 687b ldr r3, [r7, #4] 800556a: 681b ldr r3, [r3, #0] 800556c: 051b lsls r3, r3, #20 800556e: 493f ldr r1, [pc, #252] ; (800566c ) 8005570: 4313 orrs r3, r2 8005572: 628b str r3, [r1, #40] ; 0x28 8005574: 687b ldr r3, [r7, #4] 8005576: 685b ldr r3, [r3, #4] 8005578: 3b01 subs r3, #1 800557a: f3c3 0208 ubfx r2, r3, #0, #9 800557e: 687b ldr r3, [r7, #4] 8005580: 689b ldr r3, [r3, #8] 8005582: 3b01 subs r3, #1 8005584: 025b lsls r3, r3, #9 8005586: b29b uxth r3, r3 8005588: 431a orrs r2, r3 800558a: 687b ldr r3, [r7, #4] 800558c: 68db ldr r3, [r3, #12] 800558e: 3b01 subs r3, #1 8005590: 041b lsls r3, r3, #16 8005592: f403 03fe and.w r3, r3, #8323072 ; 0x7f0000 8005596: 431a orrs r2, r3 8005598: 687b ldr r3, [r7, #4] 800559a: 691b ldr r3, [r3, #16] 800559c: 3b01 subs r3, #1 800559e: 061b lsls r3, r3, #24 80055a0: f003 43fe and.w r3, r3, #2130706432 ; 0x7f000000 80055a4: 4931 ldr r1, [pc, #196] ; (800566c ) 80055a6: 4313 orrs r3, r2 80055a8: 640b str r3, [r1, #64] ; 0x40 pll3->PLL3P, pll3->PLL3Q, pll3->PLL3R); /* Select PLL3 input reference frequency range: VCI */ __HAL_RCC_PLL3_VCIRANGE(pll3->PLL3RGE) ; 80055aa: 4b30 ldr r3, [pc, #192] ; (800566c ) 80055ac: 6adb ldr r3, [r3, #44] ; 0x2c 80055ae: f423 6240 bic.w r2, r3, #3072 ; 0xc00 80055b2: 687b ldr r3, [r7, #4] 80055b4: 695b ldr r3, [r3, #20] 80055b6: 492d ldr r1, [pc, #180] ; (800566c ) 80055b8: 4313 orrs r3, r2 80055ba: 62cb str r3, [r1, #44] ; 0x2c /* Select PLL3 output frequency range : VCO */ __HAL_RCC_PLL3_VCORANGE(pll3->PLL3VCOSEL) ; 80055bc: 4b2b ldr r3, [pc, #172] ; (800566c ) 80055be: 6adb ldr r3, [r3, #44] ; 0x2c 80055c0: f423 7200 bic.w r2, r3, #512 ; 0x200 80055c4: 687b ldr r3, [r7, #4] 80055c6: 699b ldr r3, [r3, #24] 80055c8: 4928 ldr r1, [pc, #160] ; (800566c ) 80055ca: 4313 orrs r3, r2 80055cc: 62cb str r3, [r1, #44] ; 0x2c /* Disable PLL3FRACN . */ __HAL_RCC_PLL3FRACN_DISABLE(); 80055ce: 4b27 ldr r3, [pc, #156] ; (800566c ) 80055d0: 6adb ldr r3, [r3, #44] ; 0x2c 80055d2: 4a26 ldr r2, [pc, #152] ; (800566c ) 80055d4: f423 7380 bic.w r3, r3, #256 ; 0x100 80055d8: 62d3 str r3, [r2, #44] ; 0x2c /* Configures PLL3 clock Fractional Part Of The Multiplication Factor */ __HAL_RCC_PLL3FRACN_CONFIG(pll3->PLL3FRACN); 80055da: 4b24 ldr r3, [pc, #144] ; (800566c ) 80055dc: 6c5a ldr r2, [r3, #68] ; 0x44 80055de: 4b24 ldr r3, [pc, #144] ; (8005670 ) 80055e0: 4013 ands r3, r2 80055e2: 687a ldr r2, [r7, #4] 80055e4: 69d2 ldr r2, [r2, #28] 80055e6: 00d2 lsls r2, r2, #3 80055e8: 4920 ldr r1, [pc, #128] ; (800566c ) 80055ea: 4313 orrs r3, r2 80055ec: 644b str r3, [r1, #68] ; 0x44 /* Enable PLL3FRACN . */ __HAL_RCC_PLL3FRACN_ENABLE(); 80055ee: 4b1f ldr r3, [pc, #124] ; (800566c ) 80055f0: 6adb ldr r3, [r3, #44] ; 0x2c 80055f2: 4a1e ldr r2, [pc, #120] ; (800566c ) 80055f4: f443 7380 orr.w r3, r3, #256 ; 0x100 80055f8: 62d3 str r3, [r2, #44] ; 0x2c /* Enable the PLL3 clock output */ if(Divider == DIVIDER_P_UPDATE) 80055fa: 683b ldr r3, [r7, #0] 80055fc: 2b00 cmp r3, #0 80055fe: d106 bne.n 800560e { __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP); 8005600: 4b1a ldr r3, [pc, #104] ; (800566c ) 8005602: 6adb ldr r3, [r3, #44] ; 0x2c 8005604: 4a19 ldr r2, [pc, #100] ; (800566c ) 8005606: f443 0380 orr.w r3, r3, #4194304 ; 0x400000 800560a: 62d3 str r3, [r2, #44] ; 0x2c 800560c: e00f b.n 800562e } else if(Divider == DIVIDER_Q_UPDATE) 800560e: 683b ldr r3, [r7, #0] 8005610: 2b01 cmp r3, #1 8005612: d106 bne.n 8005622 { __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ); 8005614: 4b15 ldr r3, [pc, #84] ; (800566c ) 8005616: 6adb ldr r3, [r3, #44] ; 0x2c 8005618: 4a14 ldr r2, [pc, #80] ; (800566c ) 800561a: f443 0300 orr.w r3, r3, #8388608 ; 0x800000 800561e: 62d3 str r3, [r2, #44] ; 0x2c 8005620: e005 b.n 800562e } else { __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR); 8005622: 4b12 ldr r3, [pc, #72] ; (800566c ) 8005624: 6adb ldr r3, [r3, #44] ; 0x2c 8005626: 4a11 ldr r2, [pc, #68] ; (800566c ) 8005628: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 800562c: 62d3 str r3, [r2, #44] ; 0x2c } /* Enable PLL3. */ __HAL_RCC_PLL3_ENABLE(); 800562e: 4b0f ldr r3, [pc, #60] ; (800566c ) 8005630: 681b ldr r3, [r3, #0] 8005632: 4a0e ldr r2, [pc, #56] ; (800566c ) 8005634: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8005638: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800563a: f7fb fe19 bl 8001270 800563e: 60b8 str r0, [r7, #8] /* Wait till PLL3 is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U) 8005640: e008 b.n 8005654 { if( (HAL_GetTick() - tickstart ) > PLL3_TIMEOUT_VALUE) 8005642: f7fb fe15 bl 8001270 8005646: 4602 mov r2, r0 8005648: 68bb ldr r3, [r7, #8] 800564a: 1ad3 subs r3, r2, r3 800564c: 2b02 cmp r3, #2 800564e: d901 bls.n 8005654 { return HAL_TIMEOUT; 8005650: 2303 movs r3, #3 8005652: e006 b.n 8005662 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U) 8005654: 4b05 ldr r3, [pc, #20] ; (800566c ) 8005656: 681b ldr r3, [r3, #0] 8005658: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 800565c: 2b00 cmp r3, #0 800565e: d0f0 beq.n 8005642 } } return status; 8005660: 7bfb ldrb r3, [r7, #15] } 8005662: 4618 mov r0, r3 8005664: 3710 adds r7, #16 8005666: 46bd mov sp, r7 8005668: bd80 pop {r7, pc} 800566a: bf00 nop 800566c: 58024400 .word 0x58024400 8005670: ffff0007 .word 0xffff0007 08005674 <__libc_init_array>: 8005674: b570 push {r4, r5, r6, lr} 8005676: 4d0d ldr r5, [pc, #52] ; (80056ac <__libc_init_array+0x38>) 8005678: 4c0d ldr r4, [pc, #52] ; (80056b0 <__libc_init_array+0x3c>) 800567a: 1b64 subs r4, r4, r5 800567c: 10a4 asrs r4, r4, #2 800567e: 2600 movs r6, #0 8005680: 42a6 cmp r6, r4 8005682: d109 bne.n 8005698 <__libc_init_array+0x24> 8005684: 4d0b ldr r5, [pc, #44] ; (80056b4 <__libc_init_array+0x40>) 8005686: 4c0c ldr r4, [pc, #48] ; (80056b8 <__libc_init_array+0x44>) 8005688: f000 f82e bl 80056e8 <_init> 800568c: 1b64 subs r4, r4, r5 800568e: 10a4 asrs r4, r4, #2 8005690: 2600 movs r6, #0 8005692: 42a6 cmp r6, r4 8005694: d105 bne.n 80056a2 <__libc_init_array+0x2e> 8005696: bd70 pop {r4, r5, r6, pc} 8005698: f855 3b04 ldr.w r3, [r5], #4 800569c: 4798 blx r3 800569e: 3601 adds r6, #1 80056a0: e7ee b.n 8005680 <__libc_init_array+0xc> 80056a2: f855 3b04 ldr.w r3, [r5], #4 80056a6: 4798 blx r3 80056a8: 3601 adds r6, #1 80056aa: e7f2 b.n 8005692 <__libc_init_array+0x1e> 80056ac: 0800576c .word 0x0800576c 80056b0: 0800576c .word 0x0800576c 80056b4: 0800576c .word 0x0800576c 80056b8: 08005770 .word 0x08005770 080056bc : 80056bc: 440a add r2, r1 80056be: 4291 cmp r1, r2 80056c0: f100 33ff add.w r3, r0, #4294967295 80056c4: d100 bne.n 80056c8 80056c6: 4770 bx lr 80056c8: b510 push {r4, lr} 80056ca: f811 4b01 ldrb.w r4, [r1], #1 80056ce: f803 4f01 strb.w r4, [r3, #1]! 80056d2: 4291 cmp r1, r2 80056d4: d1f9 bne.n 80056ca 80056d6: bd10 pop {r4, pc} 080056d8 : 80056d8: 4402 add r2, r0 80056da: 4603 mov r3, r0 80056dc: 4293 cmp r3, r2 80056de: d100 bne.n 80056e2 80056e0: 4770 bx lr 80056e2: f803 1b01 strb.w r1, [r3], #1 80056e6: e7f9 b.n 80056dc 080056e8 <_init>: 80056e8: b5f8 push {r3, r4, r5, r6, r7, lr} 80056ea: bf00 nop 80056ec: bcf8 pop {r3, r4, r5, r6, r7} 80056ee: bc08 pop {r3} 80056f0: 469e mov lr, r3 80056f2: 4770 bx lr 080056f4 <_fini>: 80056f4: b5f8 push {r3, r4, r5, r6, r7, lr} 80056f6: bf00 nop 80056f8: bcf8 pop {r3, r4, r5, r6, r7} 80056fa: bc08 pop {r3} 80056fc: 469e mov lr, r3 80056fe: 4770 bx lr