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jiecang 推杆小板代码
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JC35W8/Debug/g031_JIECANG_JC35W8.list

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g031_JIECANG_JC35W8.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 000000bc 08000000 08000000 00010000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 0000732c 080000bc 080000bc 000100bc 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 000000cc 080073e8 080073e8 000173e8 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 080074b4 080074b4 00020018 2**0
CONTENTS
4 .ARM 00000008 080074b4 080074b4 000174b4 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
5 .preinit_array 00000000 080074bc 080074bc 00020018 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 080074bc 080074bc 000174bc 2**2
CONTENTS, ALLOC, LOAD, DATA
7 .fini_array 00000004 080074c0 080074c0 000174c0 2**2
CONTENTS, ALLOC, LOAD, DATA
8 .data 00000018 20000000 080074c4 00020000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 00000434 20000018 080074dc 00020018 2**2
ALLOC
10 ._user_heap_stack 00000604 2000044c 080074dc 0002044c 2**0
ALLOC
11 .ARM.attributes 00000028 00000000 00000000 00020018 2**0
CONTENTS, READONLY
12 .debug_info 0001617d 00000000 00000000 00020040 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_abbrev 000031fa 00000000 00000000 000361bd 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_aranges 00001260 00000000 00000000 000393b8 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_ranges 00001120 00000000 00000000 0003a618 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_macro 0001846e 00000000 00000000 0003b738 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_line 00016ffa 00000000 00000000 00053ba6 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_str 00099899 00000000 00000000 0006aba0 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .comment 00000050 00000000 00000000 00104439 2**0
CONTENTS, READONLY
20 .debug_frame 00004160 00000000 00000000 0010448c 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
080000bc <__do_global_dtors_aux>:
80000bc: b510 push {r4, lr}
80000be: 4c06 ldr r4, [pc, #24] ; (80000d8 <__do_global_dtors_aux+0x1c>)
80000c0: 7823 ldrb r3, [r4, #0]
80000c2: 2b00 cmp r3, #0
80000c4: d107 bne.n 80000d6 <__do_global_dtors_aux+0x1a>
80000c6: 4b05 ldr r3, [pc, #20] ; (80000dc <__do_global_dtors_aux+0x20>)
80000c8: 2b00 cmp r3, #0
80000ca: d002 beq.n 80000d2 <__do_global_dtors_aux+0x16>
80000cc: 4804 ldr r0, [pc, #16] ; (80000e0 <__do_global_dtors_aux+0x24>)
80000ce: e000 b.n 80000d2 <__do_global_dtors_aux+0x16>
80000d0: bf00 nop
80000d2: 2301 movs r3, #1
80000d4: 7023 strb r3, [r4, #0]
80000d6: bd10 pop {r4, pc}
80000d8: 20000018 .word 0x20000018
80000dc: 00000000 .word 0x00000000
80000e0: 080073d0 .word 0x080073d0
080000e4 <frame_dummy>:
80000e4: 4b04 ldr r3, [pc, #16] ; (80000f8 <frame_dummy+0x14>)
80000e6: b510 push {r4, lr}
80000e8: 2b00 cmp r3, #0
80000ea: d003 beq.n 80000f4 <frame_dummy+0x10>
80000ec: 4903 ldr r1, [pc, #12] ; (80000fc <frame_dummy+0x18>)
80000ee: 4804 ldr r0, [pc, #16] ; (8000100 <frame_dummy+0x1c>)
80000f0: e000 b.n 80000f4 <frame_dummy+0x10>
80000f2: bf00 nop
80000f4: bd10 pop {r4, pc}
80000f6: 46c0 nop ; (mov r8, r8)
80000f8: 00000000 .word 0x00000000
80000fc: 2000001c .word 0x2000001c
8000100: 080073d0 .word 0x080073d0
08000104 <__udivsi3>:
8000104: 2200 movs r2, #0
8000106: 0843 lsrs r3, r0, #1
8000108: 428b cmp r3, r1
800010a: d374 bcc.n 80001f6 <__udivsi3+0xf2>
800010c: 0903 lsrs r3, r0, #4
800010e: 428b cmp r3, r1
8000110: d35f bcc.n 80001d2 <__udivsi3+0xce>
8000112: 0a03 lsrs r3, r0, #8
8000114: 428b cmp r3, r1
8000116: d344 bcc.n 80001a2 <__udivsi3+0x9e>
8000118: 0b03 lsrs r3, r0, #12
800011a: 428b cmp r3, r1
800011c: d328 bcc.n 8000170 <__udivsi3+0x6c>
800011e: 0c03 lsrs r3, r0, #16
8000120: 428b cmp r3, r1
8000122: d30d bcc.n 8000140 <__udivsi3+0x3c>
8000124: 22ff movs r2, #255 ; 0xff
8000126: 0209 lsls r1, r1, #8
8000128: ba12 rev r2, r2
800012a: 0c03 lsrs r3, r0, #16
800012c: 428b cmp r3, r1
800012e: d302 bcc.n 8000136 <__udivsi3+0x32>
8000130: 1212 asrs r2, r2, #8
8000132: 0209 lsls r1, r1, #8
8000134: d065 beq.n 8000202 <__udivsi3+0xfe>
8000136: 0b03 lsrs r3, r0, #12
8000138: 428b cmp r3, r1
800013a: d319 bcc.n 8000170 <__udivsi3+0x6c>
800013c: e000 b.n 8000140 <__udivsi3+0x3c>
800013e: 0a09 lsrs r1, r1, #8
8000140: 0bc3 lsrs r3, r0, #15
8000142: 428b cmp r3, r1
8000144: d301 bcc.n 800014a <__udivsi3+0x46>
8000146: 03cb lsls r3, r1, #15
8000148: 1ac0 subs r0, r0, r3
800014a: 4152 adcs r2, r2
800014c: 0b83 lsrs r3, r0, #14
800014e: 428b cmp r3, r1
8000150: d301 bcc.n 8000156 <__udivsi3+0x52>
8000152: 038b lsls r3, r1, #14
8000154: 1ac0 subs r0, r0, r3
8000156: 4152 adcs r2, r2
8000158: 0b43 lsrs r3, r0, #13
800015a: 428b cmp r3, r1
800015c: d301 bcc.n 8000162 <__udivsi3+0x5e>
800015e: 034b lsls r3, r1, #13
8000160: 1ac0 subs r0, r0, r3
8000162: 4152 adcs r2, r2
8000164: 0b03 lsrs r3, r0, #12
8000166: 428b cmp r3, r1
8000168: d301 bcc.n 800016e <__udivsi3+0x6a>
800016a: 030b lsls r3, r1, #12
800016c: 1ac0 subs r0, r0, r3
800016e: 4152 adcs r2, r2
8000170: 0ac3 lsrs r3, r0, #11
8000172: 428b cmp r3, r1
8000174: d301 bcc.n 800017a <__udivsi3+0x76>
8000176: 02cb lsls r3, r1, #11
8000178: 1ac0 subs r0, r0, r3
800017a: 4152 adcs r2, r2
800017c: 0a83 lsrs r3, r0, #10
800017e: 428b cmp r3, r1
8000180: d301 bcc.n 8000186 <__udivsi3+0x82>
8000182: 028b lsls r3, r1, #10
8000184: 1ac0 subs r0, r0, r3
8000186: 4152 adcs r2, r2
8000188: 0a43 lsrs r3, r0, #9
800018a: 428b cmp r3, r1
800018c: d301 bcc.n 8000192 <__udivsi3+0x8e>
800018e: 024b lsls r3, r1, #9
8000190: 1ac0 subs r0, r0, r3
8000192: 4152 adcs r2, r2
8000194: 0a03 lsrs r3, r0, #8
8000196: 428b cmp r3, r1
8000198: d301 bcc.n 800019e <__udivsi3+0x9a>
800019a: 020b lsls r3, r1, #8
800019c: 1ac0 subs r0, r0, r3
800019e: 4152 adcs r2, r2
80001a0: d2cd bcs.n 800013e <__udivsi3+0x3a>
80001a2: 09c3 lsrs r3, r0, #7
80001a4: 428b cmp r3, r1
80001a6: d301 bcc.n 80001ac <__udivsi3+0xa8>
80001a8: 01cb lsls r3, r1, #7
80001aa: 1ac0 subs r0, r0, r3
80001ac: 4152 adcs r2, r2
80001ae: 0983 lsrs r3, r0, #6
80001b0: 428b cmp r3, r1
80001b2: d301 bcc.n 80001b8 <__udivsi3+0xb4>
80001b4: 018b lsls r3, r1, #6
80001b6: 1ac0 subs r0, r0, r3
80001b8: 4152 adcs r2, r2
80001ba: 0943 lsrs r3, r0, #5
80001bc: 428b cmp r3, r1
80001be: d301 bcc.n 80001c4 <__udivsi3+0xc0>
80001c0: 014b lsls r3, r1, #5
80001c2: 1ac0 subs r0, r0, r3
80001c4: 4152 adcs r2, r2
80001c6: 0903 lsrs r3, r0, #4
80001c8: 428b cmp r3, r1
80001ca: d301 bcc.n 80001d0 <__udivsi3+0xcc>
80001cc: 010b lsls r3, r1, #4
80001ce: 1ac0 subs r0, r0, r3
80001d0: 4152 adcs r2, r2
80001d2: 08c3 lsrs r3, r0, #3
80001d4: 428b cmp r3, r1
80001d6: d301 bcc.n 80001dc <__udivsi3+0xd8>
80001d8: 00cb lsls r3, r1, #3
80001da: 1ac0 subs r0, r0, r3
80001dc: 4152 adcs r2, r2
80001de: 0883 lsrs r3, r0, #2
80001e0: 428b cmp r3, r1
80001e2: d301 bcc.n 80001e8 <__udivsi3+0xe4>
80001e4: 008b lsls r3, r1, #2
80001e6: 1ac0 subs r0, r0, r3
80001e8: 4152 adcs r2, r2
80001ea: 0843 lsrs r3, r0, #1
80001ec: 428b cmp r3, r1
80001ee: d301 bcc.n 80001f4 <__udivsi3+0xf0>
80001f0: 004b lsls r3, r1, #1
80001f2: 1ac0 subs r0, r0, r3
80001f4: 4152 adcs r2, r2
80001f6: 1a41 subs r1, r0, r1
80001f8: d200 bcs.n 80001fc <__udivsi3+0xf8>
80001fa: 4601 mov r1, r0
80001fc: 4152 adcs r2, r2
80001fe: 4610 mov r0, r2
8000200: 4770 bx lr
8000202: e7ff b.n 8000204 <__udivsi3+0x100>
8000204: b501 push {r0, lr}
8000206: 2000 movs r0, #0
8000208: f000 f806 bl 8000218 <__aeabi_idiv0>
800020c: bd02 pop {r1, pc}
800020e: 46c0 nop ; (mov r8, r8)
08000210 <__aeabi_uidivmod>:
8000210: 2900 cmp r1, #0
8000212: d0f7 beq.n 8000204 <__udivsi3+0x100>
8000214: e776 b.n 8000104 <__udivsi3>
8000216: 4770 bx lr
08000218 <__aeabi_idiv0>:
8000218: 4770 bx lr
800021a: 46c0 nop ; (mov r8, r8)
0800021c <__aeabi_uldivmod>:
800021c: 2b00 cmp r3, #0
800021e: d111 bne.n 8000244 <__aeabi_uldivmod+0x28>
8000220: 2a00 cmp r2, #0
8000222: d10f bne.n 8000244 <__aeabi_uldivmod+0x28>
8000224: 2900 cmp r1, #0
8000226: d100 bne.n 800022a <__aeabi_uldivmod+0xe>
8000228: 2800 cmp r0, #0
800022a: d002 beq.n 8000232 <__aeabi_uldivmod+0x16>
800022c: 2100 movs r1, #0
800022e: 43c9 mvns r1, r1
8000230: 0008 movs r0, r1
8000232: b407 push {r0, r1, r2}
8000234: 4802 ldr r0, [pc, #8] ; (8000240 <__aeabi_uldivmod+0x24>)
8000236: a102 add r1, pc, #8 ; (adr r1, 8000240 <__aeabi_uldivmod+0x24>)
8000238: 1840 adds r0, r0, r1
800023a: 9002 str r0, [sp, #8]
800023c: bd03 pop {r0, r1, pc}
800023e: 46c0 nop ; (mov r8, r8)
8000240: ffffffd9 .word 0xffffffd9
8000244: b403 push {r0, r1}
8000246: 4668 mov r0, sp
8000248: b501 push {r0, lr}
800024a: 9802 ldr r0, [sp, #8]
800024c: f000 f806 bl 800025c <__udivmoddi4>
8000250: 9b01 ldr r3, [sp, #4]
8000252: 469e mov lr, r3
8000254: b002 add sp, #8
8000256: bc0c pop {r2, r3}
8000258: 4770 bx lr
800025a: 46c0 nop ; (mov r8, r8)
0800025c <__udivmoddi4>:
800025c: b5f0 push {r4, r5, r6, r7, lr}
800025e: 4657 mov r7, sl
8000260: 464e mov r6, r9
8000262: 4645 mov r5, r8
8000264: 46de mov lr, fp
8000266: b5e0 push {r5, r6, r7, lr}
8000268: 0004 movs r4, r0
800026a: 000d movs r5, r1
800026c: 4692 mov sl, r2
800026e: 4699 mov r9, r3
8000270: b083 sub sp, #12
8000272: 428b cmp r3, r1
8000274: d830 bhi.n 80002d8 <__udivmoddi4+0x7c>
8000276: d02d beq.n 80002d4 <__udivmoddi4+0x78>
8000278: 4649 mov r1, r9
800027a: 4650 mov r0, sl
800027c: f000 f8ba bl 80003f4 <__clzdi2>
8000280: 0029 movs r1, r5
8000282: 0006 movs r6, r0
8000284: 0020 movs r0, r4
8000286: f000 f8b5 bl 80003f4 <__clzdi2>
800028a: 1a33 subs r3, r6, r0
800028c: 4698 mov r8, r3
800028e: 3b20 subs r3, #32
8000290: 469b mov fp, r3
8000292: d433 bmi.n 80002fc <__udivmoddi4+0xa0>
8000294: 465a mov r2, fp
8000296: 4653 mov r3, sl
8000298: 4093 lsls r3, r2
800029a: 4642 mov r2, r8
800029c: 001f movs r7, r3
800029e: 4653 mov r3, sl
80002a0: 4093 lsls r3, r2
80002a2: 001e movs r6, r3
80002a4: 42af cmp r7, r5
80002a6: d83a bhi.n 800031e <__udivmoddi4+0xc2>
80002a8: 42af cmp r7, r5
80002aa: d100 bne.n 80002ae <__udivmoddi4+0x52>
80002ac: e078 b.n 80003a0 <__udivmoddi4+0x144>
80002ae: 465b mov r3, fp
80002b0: 1ba4 subs r4, r4, r6
80002b2: 41bd sbcs r5, r7
80002b4: 2b00 cmp r3, #0
80002b6: da00 bge.n 80002ba <__udivmoddi4+0x5e>
80002b8: e075 b.n 80003a6 <__udivmoddi4+0x14a>
80002ba: 2200 movs r2, #0
80002bc: 2300 movs r3, #0
80002be: 9200 str r2, [sp, #0]
80002c0: 9301 str r3, [sp, #4]
80002c2: 2301 movs r3, #1
80002c4: 465a mov r2, fp
80002c6: 4093 lsls r3, r2
80002c8: 9301 str r3, [sp, #4]
80002ca: 2301 movs r3, #1
80002cc: 4642 mov r2, r8
80002ce: 4093 lsls r3, r2
80002d0: 9300 str r3, [sp, #0]
80002d2: e028 b.n 8000326 <__udivmoddi4+0xca>
80002d4: 4282 cmp r2, r0
80002d6: d9cf bls.n 8000278 <__udivmoddi4+0x1c>
80002d8: 2200 movs r2, #0
80002da: 2300 movs r3, #0
80002dc: 9200 str r2, [sp, #0]
80002de: 9301 str r3, [sp, #4]
80002e0: 9b0c ldr r3, [sp, #48] ; 0x30
80002e2: 2b00 cmp r3, #0
80002e4: d001 beq.n 80002ea <__udivmoddi4+0x8e>
80002e6: 601c str r4, [r3, #0]
80002e8: 605d str r5, [r3, #4]
80002ea: 9800 ldr r0, [sp, #0]
80002ec: 9901 ldr r1, [sp, #4]
80002ee: b003 add sp, #12
80002f0: bcf0 pop {r4, r5, r6, r7}
80002f2: 46bb mov fp, r7
80002f4: 46b2 mov sl, r6
80002f6: 46a9 mov r9, r5
80002f8: 46a0 mov r8, r4
80002fa: bdf0 pop {r4, r5, r6, r7, pc}
80002fc: 4642 mov r2, r8
80002fe: 2320 movs r3, #32
8000300: 1a9b subs r3, r3, r2
8000302: 4652 mov r2, sl
8000304: 40da lsrs r2, r3
8000306: 4641 mov r1, r8
8000308: 0013 movs r3, r2
800030a: 464a mov r2, r9
800030c: 408a lsls r2, r1
800030e: 0017 movs r7, r2
8000310: 4642 mov r2, r8
8000312: 431f orrs r7, r3
8000314: 4653 mov r3, sl
8000316: 4093 lsls r3, r2
8000318: 001e movs r6, r3
800031a: 42af cmp r7, r5
800031c: d9c4 bls.n 80002a8 <__udivmoddi4+0x4c>
800031e: 2200 movs r2, #0
8000320: 2300 movs r3, #0
8000322: 9200 str r2, [sp, #0]
8000324: 9301 str r3, [sp, #4]
8000326: 4643 mov r3, r8
8000328: 2b00 cmp r3, #0
800032a: d0d9 beq.n 80002e0 <__udivmoddi4+0x84>
800032c: 07fb lsls r3, r7, #31
800032e: 0872 lsrs r2, r6, #1
8000330: 431a orrs r2, r3
8000332: 4646 mov r6, r8
8000334: 087b lsrs r3, r7, #1
8000336: e00e b.n 8000356 <__udivmoddi4+0xfa>
8000338: 42ab cmp r3, r5
800033a: d101 bne.n 8000340 <__udivmoddi4+0xe4>
800033c: 42a2 cmp r2, r4
800033e: d80c bhi.n 800035a <__udivmoddi4+0xfe>
8000340: 1aa4 subs r4, r4, r2
8000342: 419d sbcs r5, r3
8000344: 2001 movs r0, #1
8000346: 1924 adds r4, r4, r4
8000348: 416d adcs r5, r5
800034a: 2100 movs r1, #0
800034c: 3e01 subs r6, #1
800034e: 1824 adds r4, r4, r0
8000350: 414d adcs r5, r1
8000352: 2e00 cmp r6, #0
8000354: d006 beq.n 8000364 <__udivmoddi4+0x108>
8000356: 42ab cmp r3, r5
8000358: d9ee bls.n 8000338 <__udivmoddi4+0xdc>
800035a: 3e01 subs r6, #1
800035c: 1924 adds r4, r4, r4
800035e: 416d adcs r5, r5
8000360: 2e00 cmp r6, #0
8000362: d1f8 bne.n 8000356 <__udivmoddi4+0xfa>
8000364: 9800 ldr r0, [sp, #0]
8000366: 9901 ldr r1, [sp, #4]
8000368: 465b mov r3, fp
800036a: 1900 adds r0, r0, r4
800036c: 4169 adcs r1, r5
800036e: 2b00 cmp r3, #0
8000370: db24 blt.n 80003bc <__udivmoddi4+0x160>
8000372: 002b movs r3, r5
8000374: 465a mov r2, fp
8000376: 4644 mov r4, r8
8000378: 40d3 lsrs r3, r2
800037a: 002a movs r2, r5
800037c: 40e2 lsrs r2, r4
800037e: 001c movs r4, r3
8000380: 465b mov r3, fp
8000382: 0015 movs r5, r2
8000384: 2b00 cmp r3, #0
8000386: db2a blt.n 80003de <__udivmoddi4+0x182>
8000388: 0026 movs r6, r4
800038a: 409e lsls r6, r3
800038c: 0033 movs r3, r6
800038e: 0026 movs r6, r4
8000390: 4647 mov r7, r8
8000392: 40be lsls r6, r7
8000394: 0032 movs r2, r6
8000396: 1a80 subs r0, r0, r2
8000398: 4199 sbcs r1, r3
800039a: 9000 str r0, [sp, #0]
800039c: 9101 str r1, [sp, #4]
800039e: e79f b.n 80002e0 <__udivmoddi4+0x84>
80003a0: 42a3 cmp r3, r4
80003a2: d8bc bhi.n 800031e <__udivmoddi4+0xc2>
80003a4: e783 b.n 80002ae <__udivmoddi4+0x52>
80003a6: 4642 mov r2, r8
80003a8: 2320 movs r3, #32
80003aa: 2100 movs r1, #0
80003ac: 1a9b subs r3, r3, r2
80003ae: 2200 movs r2, #0
80003b0: 9100 str r1, [sp, #0]
80003b2: 9201 str r2, [sp, #4]
80003b4: 2201 movs r2, #1
80003b6: 40da lsrs r2, r3
80003b8: 9201 str r2, [sp, #4]
80003ba: e786 b.n 80002ca <__udivmoddi4+0x6e>
80003bc: 4642 mov r2, r8
80003be: 2320 movs r3, #32
80003c0: 1a9b subs r3, r3, r2
80003c2: 002a movs r2, r5
80003c4: 4646 mov r6, r8
80003c6: 409a lsls r2, r3
80003c8: 0023 movs r3, r4
80003ca: 40f3 lsrs r3, r6
80003cc: 4644 mov r4, r8
80003ce: 4313 orrs r3, r2
80003d0: 002a movs r2, r5
80003d2: 40e2 lsrs r2, r4
80003d4: 001c movs r4, r3
80003d6: 465b mov r3, fp
80003d8: 0015 movs r5, r2
80003da: 2b00 cmp r3, #0
80003dc: dad4 bge.n 8000388 <__udivmoddi4+0x12c>
80003de: 4642 mov r2, r8
80003e0: 002f movs r7, r5
80003e2: 2320 movs r3, #32
80003e4: 0026 movs r6, r4
80003e6: 4097 lsls r7, r2
80003e8: 1a9b subs r3, r3, r2
80003ea: 40de lsrs r6, r3
80003ec: 003b movs r3, r7
80003ee: 4333 orrs r3, r6
80003f0: e7cd b.n 800038e <__udivmoddi4+0x132>
80003f2: 46c0 nop ; (mov r8, r8)
080003f4 <__clzdi2>:
80003f4: b510 push {r4, lr}
80003f6: 2900 cmp r1, #0
80003f8: d103 bne.n 8000402 <__clzdi2+0xe>
80003fa: f000 f807 bl 800040c <__clzsi2>
80003fe: 3020 adds r0, #32
8000400: e002 b.n 8000408 <__clzdi2+0x14>
8000402: 0008 movs r0, r1
8000404: f000 f802 bl 800040c <__clzsi2>
8000408: bd10 pop {r4, pc}
800040a: 46c0 nop ; (mov r8, r8)
0800040c <__clzsi2>:
800040c: 211c movs r1, #28
800040e: 2301 movs r3, #1
8000410: 041b lsls r3, r3, #16
8000412: 4298 cmp r0, r3
8000414: d301 bcc.n 800041a <__clzsi2+0xe>
8000416: 0c00 lsrs r0, r0, #16
8000418: 3910 subs r1, #16
800041a: 0a1b lsrs r3, r3, #8
800041c: 4298 cmp r0, r3
800041e: d301 bcc.n 8000424 <__clzsi2+0x18>
8000420: 0a00 lsrs r0, r0, #8
8000422: 3908 subs r1, #8
8000424: 091b lsrs r3, r3, #4
8000426: 4298 cmp r0, r3
8000428: d301 bcc.n 800042e <__clzsi2+0x22>
800042a: 0900 lsrs r0, r0, #4
800042c: 3904 subs r1, #4
800042e: a202 add r2, pc, #8 ; (adr r2, 8000438 <__clzsi2+0x2c>)
8000430: 5c10 ldrb r0, [r2, r0]
8000432: 1840 adds r0, r0, r1
8000434: 4770 bx lr
8000436: 46c0 nop ; (mov r8, r8)
8000438: 02020304 .word 0x02020304
800043c: 01010101 .word 0x01010101
...
08000448 <MX_ADC1_Init>:
ADC_HandleTypeDef hadc1;
/* ADC1 init function */
void MX_ADC1_Init(void)
{
8000448: b580 push {r7, lr}
800044a: b084 sub sp, #16
800044c: af00 add r7, sp, #0
/* USER CODE BEGIN ADC1_Init 0 */
/* USER CODE END ADC1_Init 0 */
ADC_ChannelConfTypeDef sConfig = {0};
800044e: 1d3b adds r3, r7, #4
8000450: 0018 movs r0, r3
8000452: 230c movs r3, #12
8000454: 001a movs r2, r3
8000456: 2100 movs r1, #0
8000458: f006 ffb2 bl 80073c0 <memset>
/* USER CODE END ADC1_Init 1 */
/** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion)
*/
hadc1.Instance = ADC1;
800045c: 4b2b ldr r3, [pc, #172] ; (800050c <MX_ADC1_Init+0xc4>)
800045e: 4a2c ldr r2, [pc, #176] ; (8000510 <MX_ADC1_Init+0xc8>)
8000460: 601a str r2, [r3, #0]
hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4;
8000462: 4b2a ldr r3, [pc, #168] ; (800050c <MX_ADC1_Init+0xc4>)
8000464: 2280 movs r2, #128 ; 0x80
8000466: 0612 lsls r2, r2, #24
8000468: 605a str r2, [r3, #4]
hadc1.Init.Resolution = ADC_RESOLUTION_12B;
800046a: 4b28 ldr r3, [pc, #160] ; (800050c <MX_ADC1_Init+0xc4>)
800046c: 2200 movs r2, #0
800046e: 609a str r2, [r3, #8]
hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
8000470: 4b26 ldr r3, [pc, #152] ; (800050c <MX_ADC1_Init+0xc4>)
8000472: 2200 movs r2, #0
8000474: 60da str r2, [r3, #12]
hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;
8000476: 4b25 ldr r3, [pc, #148] ; (800050c <MX_ADC1_Init+0xc4>)
8000478: 2200 movs r2, #0
800047a: 611a str r2, [r3, #16]
hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
800047c: 4b23 ldr r3, [pc, #140] ; (800050c <MX_ADC1_Init+0xc4>)
800047e: 2204 movs r2, #4
8000480: 615a str r2, [r3, #20]
hadc1.Init.LowPowerAutoWait = DISABLE;
8000482: 4b22 ldr r3, [pc, #136] ; (800050c <MX_ADC1_Init+0xc4>)
8000484: 2200 movs r2, #0
8000486: 761a strb r2, [r3, #24]
hadc1.Init.LowPowerAutoPowerOff = DISABLE;
8000488: 4b20 ldr r3, [pc, #128] ; (800050c <MX_ADC1_Init+0xc4>)
800048a: 2200 movs r2, #0
800048c: 765a strb r2, [r3, #25]
hadc1.Init.ContinuousConvMode = DISABLE;
800048e: 4b1f ldr r3, [pc, #124] ; (800050c <MX_ADC1_Init+0xc4>)
8000490: 2200 movs r2, #0
8000492: 769a strb r2, [r3, #26]
hadc1.Init.NbrOfConversion = 1;
8000494: 4b1d ldr r3, [pc, #116] ; (800050c <MX_ADC1_Init+0xc4>)
8000496: 2201 movs r2, #1
8000498: 61da str r2, [r3, #28]
hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
800049a: 4b1c ldr r3, [pc, #112] ; (800050c <MX_ADC1_Init+0xc4>)
800049c: 2200 movs r2, #0
800049e: 625a str r2, [r3, #36] ; 0x24
hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
80004a0: 4b1a ldr r3, [pc, #104] ; (800050c <MX_ADC1_Init+0xc4>)
80004a2: 2200 movs r2, #0
80004a4: 629a str r2, [r3, #40] ; 0x28
hadc1.Init.DMAContinuousRequests = DISABLE;
80004a6: 4b19 ldr r3, [pc, #100] ; (800050c <MX_ADC1_Init+0xc4>)
80004a8: 222c movs r2, #44 ; 0x2c
80004aa: 2100 movs r1, #0
80004ac: 5499 strb r1, [r3, r2]
hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED;
80004ae: 4b17 ldr r3, [pc, #92] ; (800050c <MX_ADC1_Init+0xc4>)
80004b0: 2200 movs r2, #0
80004b2: 631a str r2, [r3, #48] ; 0x30
hadc1.Init.SamplingTimeCommon1 = ADC_SAMPLETIME_19CYCLES_5;
80004b4: 4b15 ldr r3, [pc, #84] ; (800050c <MX_ADC1_Init+0xc4>)
80004b6: 2204 movs r2, #4
80004b8: 635a str r2, [r3, #52] ; 0x34
hadc1.Init.SamplingTimeCommon2 = ADC_SAMPLETIME_19CYCLES_5;
80004ba: 4b14 ldr r3, [pc, #80] ; (800050c <MX_ADC1_Init+0xc4>)
80004bc: 2204 movs r2, #4
80004be: 639a str r2, [r3, #56] ; 0x38
hadc1.Init.OversamplingMode = DISABLE;
80004c0: 4b12 ldr r3, [pc, #72] ; (800050c <MX_ADC1_Init+0xc4>)
80004c2: 223c movs r2, #60 ; 0x3c
80004c4: 2100 movs r1, #0
80004c6: 5499 strb r1, [r3, r2]
hadc1.Init.TriggerFrequencyMode = ADC_TRIGGER_FREQ_HIGH;
80004c8: 4b10 ldr r3, [pc, #64] ; (800050c <MX_ADC1_Init+0xc4>)
80004ca: 2200 movs r2, #0
80004cc: 64da str r2, [r3, #76] ; 0x4c
if (HAL_ADC_Init(&hadc1) != HAL_OK)
80004ce: 4b0f ldr r3, [pc, #60] ; (800050c <MX_ADC1_Init+0xc4>)
80004d0: 0018 movs r0, r3
80004d2: f001 fcb5 bl 8001e40 <HAL_ADC_Init>
80004d6: 1e03 subs r3, r0, #0
80004d8: d001 beq.n 80004de <MX_ADC1_Init+0x96>
{
Error_Handler();
80004da: f000 fb84 bl 8000be6 <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_5;
80004de: 1d3b adds r3, r7, #4
80004e0: 4a0c ldr r2, [pc, #48] ; (8000514 <MX_ADC1_Init+0xcc>)
80004e2: 601a str r2, [r3, #0]
sConfig.Rank = ADC_REGULAR_RANK_1;
80004e4: 1d3b adds r3, r7, #4
80004e6: 2200 movs r2, #0
80004e8: 605a str r2, [r3, #4]
sConfig.SamplingTime = ADC_SAMPLINGTIME_COMMON_1;
80004ea: 1d3b adds r3, r7, #4
80004ec: 2200 movs r2, #0
80004ee: 609a str r2, [r3, #8]
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
80004f0: 1d3a adds r2, r7, #4
80004f2: 4b06 ldr r3, [pc, #24] ; (800050c <MX_ADC1_Init+0xc4>)
80004f4: 0011 movs r1, r2
80004f6: 0018 movs r0, r3
80004f8: f001 fff6 bl 80024e8 <HAL_ADC_ConfigChannel>
80004fc: 1e03 subs r3, r0, #0
80004fe: d001 beq.n 8000504 <MX_ADC1_Init+0xbc>
{
Error_Handler();
8000500: f000 fb71 bl 8000be6 <Error_Handler>
}
/* USER CODE BEGIN ADC1_Init 2 */
/* USER CODE END ADC1_Init 2 */
}
8000504: 46c0 nop ; (mov r8, r8)
8000506: 46bd mov sp, r7
8000508: b004 add sp, #16
800050a: bd80 pop {r7, pc}
800050c: 20000034 .word 0x20000034
8000510: 40012400 .word 0x40012400
8000514: 14000020 .word 0x14000020
08000518 <HAL_ADC_MspInit>:
void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle)
{
8000518: b590 push {r4, r7, lr}
800051a: b095 sub sp, #84 ; 0x54
800051c: af00 add r7, sp, #0
800051e: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000520: 233c movs r3, #60 ; 0x3c
8000522: 18fb adds r3, r7, r3
8000524: 0018 movs r0, r3
8000526: 2314 movs r3, #20
8000528: 001a movs r2, r3
800052a: 2100 movs r1, #0
800052c: f006 ff48 bl 80073c0 <memset>
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
8000530: 2414 movs r4, #20
8000532: 193b adds r3, r7, r4
8000534: 0018 movs r0, r3
8000536: 2328 movs r3, #40 ; 0x28
8000538: 001a movs r2, r3
800053a: 2100 movs r1, #0
800053c: f006 ff40 bl 80073c0 <memset>
if(adcHandle->Instance==ADC1)
8000540: 687b ldr r3, [r7, #4]
8000542: 681b ldr r3, [r3, #0]
8000544: 4a24 ldr r2, [pc, #144] ; (80005d8 <HAL_ADC_MspInit+0xc0>)
8000546: 4293 cmp r3, r2
8000548: d141 bne.n 80005ce <HAL_ADC_MspInit+0xb6>
/* USER CODE END ADC1_MspInit 0 */
/** Initializes the peripherals clocks
*/
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
800054a: 193b adds r3, r7, r4
800054c: 2280 movs r2, #128 ; 0x80
800054e: 01d2 lsls r2, r2, #7
8000550: 601a str r2, [r3, #0]
PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_SYSCLK;
8000552: 193b adds r3, r7, r4
8000554: 2200 movs r2, #0
8000556: 61da str r2, [r3, #28]
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
8000558: 193b adds r3, r7, r4
800055a: 0018 movs r0, r3
800055c: f003 fe84 bl 8004268 <HAL_RCCEx_PeriphCLKConfig>
8000560: 1e03 subs r3, r0, #0
8000562: d001 beq.n 8000568 <HAL_ADC_MspInit+0x50>
{
Error_Handler();
8000564: f000 fb3f bl 8000be6 <Error_Handler>
}
/* ADC1 clock enable */
__HAL_RCC_ADC_CLK_ENABLE();
8000568: 4b1c ldr r3, [pc, #112] ; (80005dc <HAL_ADC_MspInit+0xc4>)
800056a: 6c1a ldr r2, [r3, #64] ; 0x40
800056c: 4b1b ldr r3, [pc, #108] ; (80005dc <HAL_ADC_MspInit+0xc4>)
800056e: 2180 movs r1, #128 ; 0x80
8000570: 0349 lsls r1, r1, #13
8000572: 430a orrs r2, r1
8000574: 641a str r2, [r3, #64] ; 0x40
8000576: 4b19 ldr r3, [pc, #100] ; (80005dc <HAL_ADC_MspInit+0xc4>)
8000578: 6c1a ldr r2, [r3, #64] ; 0x40
800057a: 2380 movs r3, #128 ; 0x80
800057c: 035b lsls r3, r3, #13
800057e: 4013 ands r3, r2
8000580: 613b str r3, [r7, #16]
8000582: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
8000584: 4b15 ldr r3, [pc, #84] ; (80005dc <HAL_ADC_MspInit+0xc4>)
8000586: 6b5a ldr r2, [r3, #52] ; 0x34
8000588: 4b14 ldr r3, [pc, #80] ; (80005dc <HAL_ADC_MspInit+0xc4>)
800058a: 2101 movs r1, #1
800058c: 430a orrs r2, r1
800058e: 635a str r2, [r3, #52] ; 0x34
8000590: 4b12 ldr r3, [pc, #72] ; (80005dc <HAL_ADC_MspInit+0xc4>)
8000592: 6b5b ldr r3, [r3, #52] ; 0x34
8000594: 2201 movs r2, #1
8000596: 4013 ands r3, r2
8000598: 60fb str r3, [r7, #12]
800059a: 68fb ldr r3, [r7, #12]
/**ADC1 GPIO Configuration
PA5 ------> ADC1_IN5
*/
GPIO_InitStruct.Pin = GPIO_PIN_5;
800059c: 213c movs r1, #60 ; 0x3c
800059e: 187b adds r3, r7, r1
80005a0: 2220 movs r2, #32
80005a2: 601a str r2, [r3, #0]
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
80005a4: 187b adds r3, r7, r1
80005a6: 2203 movs r2, #3
80005a8: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80005aa: 187b adds r3, r7, r1
80005ac: 2200 movs r2, #0
80005ae: 609a str r2, [r3, #8]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
80005b0: 187a adds r2, r7, r1
80005b2: 23a0 movs r3, #160 ; 0xa0
80005b4: 05db lsls r3, r3, #23
80005b6: 0011 movs r1, r2
80005b8: 0018 movs r0, r3
80005ba: f002 ffc3 bl 8003544 <HAL_GPIO_Init>
/* ADC1 interrupt Init */
HAL_NVIC_SetPriority(ADC1_IRQn, 0, 0);
80005be: 2200 movs r2, #0
80005c0: 2100 movs r1, #0
80005c2: 200c movs r0, #12
80005c4: f002 fc6e bl 8002ea4 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(ADC1_IRQn);
80005c8: 200c movs r0, #12
80005ca: f002 fc80 bl 8002ece <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN ADC1_MspInit 1 */
/* USER CODE END ADC1_MspInit 1 */
}
}
80005ce: 46c0 nop ; (mov r8, r8)
80005d0: 46bd mov sp, r7
80005d2: b015 add sp, #84 ; 0x54
80005d4: bd90 pop {r4, r7, pc}
80005d6: 46c0 nop ; (mov r8, r8)
80005d8: 40012400 .word 0x40012400
80005dc: 40021000 .word 0x40021000
080005e0 <App_Init>:
static void App_UpdateEncoderRegister(void);
static void App_ProcessZeroCommand(void);
static void App_UpdateLed(void);
void App_Init(void)
{
80005e0: b580 push {r7, lr}
80005e2: af00 add r7, sp, #0
/* 上电默认：电机停止 */
HAL_GPIO_WritePin(IO_1_GPIO_Port, IO_1_Pin, GPIO_PIN_RESET);
80005e4: 4b1d ldr r3, [pc, #116] ; (800065c <App_Init+0x7c>)
80005e6: 2200 movs r2, #0
80005e8: 2101 movs r1, #1
80005ea: 0018 movs r0, r3
80005ec: f003 f90e bl 800380c <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(IO_2_GPIO_Port, IO_2_Pin, GPIO_PIN_RESET);
80005f0: 23a0 movs r3, #160 ; 0xa0
80005f2: 05db lsls r3, r3, #23
80005f4: 2200 movs r2, #0
80005f6: 2180 movs r1, #128 ; 0x80
80005f8: 0018 movs r0, r3
80005fa: f003 f907 bl 800380c <HAL_GPIO_WritePin>
/* 状态灯初始熄灭 */
HAL_GPIO_WritePin(LED_GPIO_Port, LED_Pin, GPIO_PIN_RESET);
80005fe: 2380 movs r3, #128 ; 0x80
8000600: 005b lsls r3, r3, #1
8000602: 4816 ldr r0, [pc, #88] ; (800065c <App_Init+0x7c>)
8000604: 2200 movs r2, #0
8000606: 0019 movs r1, r3
8000608: f003 f900 bl 800380c <HAL_GPIO_WritePin>
/* 启动编码器读取 */
HAL_TIM_Encoder_Start(&htim2, TIM_CHANNEL_ALL);
800060c: 4b14 ldr r3, [pc, #80] ; (8000660 <App_Init+0x80>)
800060e: 213c movs r1, #60 ; 0x3c
8000610: 0018 movs r0, r3
8000612: f004 f981 bl 8004918 <HAL_TIM_Encoder_Start>
/* 启动 PWM 输出，并按当前寄存器值设置电流限幅占空比 */
HAL_TIM_PWM_Start(&htim3, TIM_CHANNEL_1);
8000616: 4b13 ldr r3, [pc, #76] ; (8000664 <App_Init+0x84>)
8000618: 2100 movs r1, #0
800061a: 0018 movs r0, r3
800061c: f003 fff6 bl 800460c <HAL_TIM_PWM_Start>
App_SetCurrentLimit(holdingRegisters[3]);
8000620: 4b11 ldr r3, [pc, #68] ; (8000668 <App_Init+0x88>)
8000622: 2206 movs r2, #6
8000624: 5e9b ldrsh r3, [r3, r2]
8000626: b29b uxth r3, r3
8000628: 0018 movs r0, r3
800062a: f000 f8fb bl 8000824 <App_SetCurrentLimit>
/* ADC校准 */
if (HAL_ADCEx_Calibration_Start(&hadc1) != HAL_OK)
800062e: 4b0f ldr r3, [pc, #60] ; (800066c <App_Init+0x8c>)
8000630: 0018 movs r0, r3
8000632: f002 fa95 bl 8002b60 <HAL_ADCEx_Calibration_Start>
8000636: 1e03 subs r3, r0, #0
8000638: d001 beq.n 800063e <App_Init+0x5e>
{
Error_Handler();
800063a: f000 fad4 bl 8000be6 <Error_Handler>
}
/* 启动 ADC 中断采集 */
adcConversionDone = 0;
800063e: 4b0c ldr r3, [pc, #48] ; (8000670 <App_Init+0x90>)
8000640: 2200 movs r2, #0
8000642: 701a strb r2, [r3, #0]
if (HAL_ADC_Start_IT(&hadc1) != HAL_OK)
8000644: 4b09 ldr r3, [pc, #36] ; (800066c <App_Init+0x8c>)
8000646: 0018 movs r0, r3
8000648: f001 fda2 bl 8002190 <HAL_ADC_Start_IT>
800064c: 1e03 subs r3, r0, #0
800064e: d001 beq.n 8000654 <App_Init+0x74>
{
Error_Handler();
8000650: f000 fac9 bl 8000be6 <Error_Handler>
}
}
8000654: 46c0 nop ; (mov r8, r8)
8000656: 46bd mov sp, r7
8000658: bd80 pop {r7, pc}
800065a: 46c0 nop ; (mov r8, r8)
800065c: 50000400 .word 0x50000400
8000660: 200002c4 .word 0x200002c4
8000664: 20000310 .word 0x20000310
8000668: 200000a4 .word 0x200000a4
800066c: 20000034 .word 0x20000034
8000670: 20000098 .word 0x20000098
08000674 <App_Process>:
void App_Process(void)
{
8000674: b580 push {r7, lr}
8000676: af00 add r7, sp, #0
/* 先处理 Modbus 请求，可能更新寄存器 */
Modbus_Process();
8000678: f000 fada bl 8000c30 <Modbus_Process>
App_UpdateMotor(); /*控制推杆上升下降包含自动和手动*/
800067c: f000 f822 bl 80006c4 <App_UpdateMotor>
App_SetCurrentLimit(holdingRegisters[3]); /*限制推杆电机电流*/
8000680: 4b0d ldr r3, [pc, #52] ; (80006b8 <App_Process+0x44>)
8000682: 2206 movs r2, #6
8000684: 5e9b ldrsh r3, [r3, r2]
8000686: b29b uxth r3, r3
8000688: 0018 movs r0, r3
800068a: f000 f8cb bl 8000824 <App_SetCurrentLimit>
App_UpdateEncoderRegister(); /*获取定时器2计数值为编码器数值存到寄存器2*/
800068e: f000 f8e5 bl 800085c <App_UpdateEncoderRegister>
App_ProcessZeroCommand();/*设置当前位置为0*/
8000692: f000 f8f7 bl 8000884 <App_ProcessZeroCommand>
App_UpdateLed(); /*指示灯灯光切换*/
8000696: f000 f913 bl 80008c0 <App_UpdateLed>
/* ADC 单次转换完成后重新启动下一轮转换 */
if (adcConversionDone != 0)
800069a: 4b08 ldr r3, [pc, #32] ; (80006bc <App_Process+0x48>)
800069c: 781b ldrb r3, [r3, #0]
800069e: b2db uxtb r3, r3
80006a0: 2b00 cmp r3, #0
80006a2: d006 beq.n 80006b2 <App_Process+0x3e>
{
adcConversionDone = 0;
80006a4: 4b05 ldr r3, [pc, #20] ; (80006bc <App_Process+0x48>)
80006a6: 2200 movs r2, #0
80006a8: 701a strb r2, [r3, #0]
HAL_ADC_Start_IT(&hadc1);
80006aa: 4b05 ldr r3, [pc, #20] ; (80006c0 <App_Process+0x4c>)
80006ac: 0018 movs r0, r3
80006ae: f001 fd6f bl 8002190 <HAL_ADC_Start_IT>
}
}
80006b2: 46c0 nop ; (mov r8, r8)
80006b4: 46bd mov sp, r7
80006b6: bd80 pop {r7, pc}
80006b8: 200000a4 .word 0x200000a4
80006bc: 20000098 .word 0x20000098
80006c0: 20000034 .word 0x20000034
080006c4 <App_UpdateMotor>:
static void App_UpdateMotor(void)
{
80006c4: b580 push {r7, lr}
80006c6: b086 sub sp, #24
80006c8: af00 add r7, sp, #0
uint8_t io1 = (holdingRegisters[0] != 0) ? 1U : 0U;
80006ca: 4b52 ldr r3, [pc, #328] ; (8000814 <App_UpdateMotor+0x150>)
80006cc: 2200 movs r2, #0
80006ce: 5e9b ldrsh r3, [r3, r2]
80006d0: 2b00 cmp r3, #0
80006d2: d001 beq.n 80006d8 <App_UpdateMotor+0x14>
80006d4: 2201 movs r2, #1
80006d6: e000 b.n 80006da <App_UpdateMotor+0x16>
80006d8: 2200 movs r2, #0
80006da: 2315 movs r3, #21
80006dc: 18fb adds r3, r7, r3
80006de: 701a strb r2, [r3, #0]
uint8_t io2 = (holdingRegisters[1] != 0) ? 1U : 0U;
80006e0: 4b4c ldr r3, [pc, #304] ; (8000814 <App_UpdateMotor+0x150>)
80006e2: 2202 movs r2, #2
80006e4: 5e9b ldrsh r3, [r3, r2]
80006e6: 2b00 cmp r3, #0
80006e8: d001 beq.n 80006ee <App_UpdateMotor+0x2a>
80006ea: 2201 movs r2, #1
80006ec: e000 b.n 80006f0 <App_UpdateMotor+0x2c>
80006ee: 2200 movs r2, #0
80006f0: 2314 movs r3, #20
80006f2: 18fb adds r3, r7, r3
80006f4: 701a strb r2, [r3, #0]
uint8_t up = 0U;
80006f6: 2317 movs r3, #23
80006f8: 18fb adds r3, r7, r3
80006fa: 2200 movs r2, #0
80006fc: 701a strb r2, [r3, #0]
uint8_t down = 0U;
80006fe: 2116 movs r1, #22
8000700: 187b adds r3, r7, r1
8000702: 2200 movs r2, #0
8000704: 701a strb r2, [r3, #0]
/*自动运行至指定位置,最下面值最大，最上面为0*/
if (holdingRegisters[6] != 0 && holdingRegisters[7] < Encoder_Max)
8000706: 4b43 ldr r3, [pc, #268] ; (8000814 <App_UpdateMotor+0x150>)
8000708: 220c movs r2, #12
800070a: 5e9b ldrsh r3, [r3, r2]
800070c: 2b00 cmp r3, #0
800070e: d028 beq.n 8000762 <App_UpdateMotor+0x9e>
8000710: 4b40 ldr r3, [pc, #256] ; (8000814 <App_UpdateMotor+0x150>)
8000712: 220e movs r2, #14
8000714: 5e9b ldrsh r3, [r3, r2]
8000716: 4a40 ldr r2, [pc, #256] ; (8000818 <App_UpdateMotor+0x154>)
8000718: 4293 cmp r3, r2
800071a: dc22 bgt.n 8000762 <App_UpdateMotor+0x9e>
{
/* 自动定位模式：根据当前编码器值和目标位置决定运行方向 */
int32_t currentPosition = (int16_t)(uint16_t)__HAL_TIM_GET_COUNTER(&htim2);
800071c: 4b3f ldr r3, [pc, #252] ; (800081c <App_UpdateMotor+0x158>)
800071e: 681b ldr r3, [r3, #0]
8000720: 6a5b ldr r3, [r3, #36] ; 0x24
8000722: b21b sxth r3, r3
8000724: 613b str r3, [r7, #16]
int32_t targetPosition = (int16_t)holdingRegisters[7];
8000726: 4b3b ldr r3, [pc, #236] ; (8000814 <App_UpdateMotor+0x150>)
8000728: 220e movs r2, #14
800072a: 5e9b ldrsh r3, [r3, r2]
800072c: 60fb str r3, [r7, #12]
int32_t positionError = targetPosition - currentPosition;
800072e: 68fa ldr r2, [r7, #12]
8000730: 693b ldr r3, [r7, #16]
8000732: 1ad3 subs r3, r2, r3
8000734: 60bb str r3, [r7, #8]
int32_t tolerance = (int32_t)holdingRegisters[AUTO_POSITION_TOLERANCE_REG]; /*寄存器9*/
8000736: 4b37 ldr r3, [pc, #220] ; (8000814 <App_UpdateMotor+0x150>)
8000738: 2212 movs r2, #18
800073a: 5e9b ldrsh r3, [r3, r2]
800073c: 607b str r3, [r7, #4]
if (positionError > tolerance)
800073e: 68ba ldr r2, [r7, #8]
8000740: 687b ldr r3, [r7, #4]
8000742: 429a cmp r2, r3
8000744: dd03 ble.n 800074e <App_UpdateMotor+0x8a>
{
down = 1U;
8000746: 187b adds r3, r7, r1
8000748: 2201 movs r2, #1
800074a: 701a strb r2, [r3, #0]
{
800074c: e02a b.n 80007a4 <App_UpdateMotor+0xe0>
}
else if (positionError < -tolerance)
800074e: 687b ldr r3, [r7, #4]
8000750: 425b negs r3, r3
8000752: 68ba ldr r2, [r7, #8]
8000754: 429a cmp r2, r3
8000756: da25 bge.n 80007a4 <App_UpdateMotor+0xe0>
{
up = 1U;
8000758: 2317 movs r3, #23
800075a: 18fb adds r3, r7, r3
800075c: 2201 movs r2, #1
800075e: 701a strb r2, [r3, #0]
{
8000760: e020 b.n 80007a4 <App_UpdateMotor+0xe0>
}
}
else
{
/* 手动模式：保持原有 holdingRegisters[0]、[1] 控制逻辑 */
up = (io1 != 0 && io2 == 0) ? 1U : 0U;
8000762: 2315 movs r3, #21
8000764: 18fb adds r3, r7, r3
8000766: 781b ldrb r3, [r3, #0]
8000768: 2b00 cmp r3, #0
800076a: d006 beq.n 800077a <App_UpdateMotor+0xb6>
800076c: 2314 movs r3, #20
800076e: 18fb adds r3, r7, r3
8000770: 781b ldrb r3, [r3, #0]
8000772: 2b00 cmp r3, #0
8000774: d101 bne.n 800077a <App_UpdateMotor+0xb6>
8000776: 2201 movs r2, #1
8000778: e000 b.n 800077c <App_UpdateMotor+0xb8>
800077a: 2200 movs r2, #0
800077c: 2317 movs r3, #23
800077e: 18fb adds r3, r7, r3
8000780: 701a strb r2, [r3, #0]
down = (io1 == 0 && io2 != 0) ? 1U : 0U;
8000782: 2315 movs r3, #21
8000784: 18fb adds r3, r7, r3
8000786: 781b ldrb r3, [r3, #0]
8000788: 2b00 cmp r3, #0
800078a: d106 bne.n 800079a <App_UpdateMotor+0xd6>
800078c: 2314 movs r3, #20
800078e: 18fb adds r3, r7, r3
8000790: 781b ldrb r3, [r3, #0]
8000792: 2b00 cmp r3, #0
8000794: d001 beq.n 800079a <App_UpdateMotor+0xd6>
8000796: 2201 movs r2, #1
8000798: e000 b.n 800079c <App_UpdateMotor+0xd8>
800079a: 2200 movs r2, #0
800079c: 2316 movs r3, #22
800079e: 18fb adds r3, r7, r3
80007a0: 701a strb r2, [r3, #0]
80007a2: e000 b.n 80007a6 <App_UpdateMotor+0xe2>
{
80007a4: 46c0 nop ; (mov r8, r8)
}
if (up != 0)
80007a6: 2317 movs r3, #23
80007a8: 18fb adds r3, r7, r3
80007aa: 781b ldrb r3, [r3, #0]
80007ac: 2b00 cmp r3, #0
80007ae: d00d beq.n 80007cc <App_UpdateMotor+0x108>
{
/* 正转：IO_1 高，IO_2 低 */
HAL_GPIO_WritePin(IO_1_GPIO_Port, IO_1_Pin, GPIO_PIN_SET);
80007b0: 4b1b ldr r3, [pc, #108] ; (8000820 <App_UpdateMotor+0x15c>)
80007b2: 2201 movs r2, #1
80007b4: 2101 movs r1, #1
80007b6: 0018 movs r0, r3
80007b8: f003 f828 bl 800380c <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(IO_2_GPIO_Port, IO_2_Pin, GPIO_PIN_RESET);
80007bc: 23a0 movs r3, #160 ; 0xa0
80007be: 05db lsls r3, r3, #23
80007c0: 2200 movs r2, #0
80007c2: 2180 movs r1, #128 ; 0x80
80007c4: 0018 movs r0, r3
80007c6: f003 f821 bl 800380c <HAL_GPIO_WritePin>
{
/* 停止：两路都低 */
HAL_GPIO_WritePin(IO_1_GPIO_Port, IO_1_Pin, GPIO_PIN_RESET);
HAL_GPIO_WritePin(IO_2_GPIO_Port, IO_2_Pin, GPIO_PIN_RESET);
}
}
80007ca: e01f b.n 800080c <App_UpdateMotor+0x148>
else if (down != 0)
80007cc: 2316 movs r3, #22
80007ce: 18fb adds r3, r7, r3
80007d0: 781b ldrb r3, [r3, #0]
80007d2: 2b00 cmp r3, #0
80007d4: d00d beq.n 80007f2 <App_UpdateMotor+0x12e>
HAL_GPIO_WritePin(IO_1_GPIO_Port, IO_1_Pin, GPIO_PIN_RESET);
80007d6: 4b12 ldr r3, [pc, #72] ; (8000820 <App_UpdateMotor+0x15c>)
80007d8: 2200 movs r2, #0
80007da: 2101 movs r1, #1
80007dc: 0018 movs r0, r3
80007de: f003 f815 bl 800380c <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(IO_2_GPIO_Port, IO_2_Pin, GPIO_PIN_SET);
80007e2: 23a0 movs r3, #160 ; 0xa0
80007e4: 05db lsls r3, r3, #23
80007e6: 2201 movs r2, #1
80007e8: 2180 movs r1, #128 ; 0x80
80007ea: 0018 movs r0, r3
80007ec: f003 f80e bl 800380c <HAL_GPIO_WritePin>
}
80007f0: e00c b.n 800080c <App_UpdateMotor+0x148>
HAL_GPIO_WritePin(IO_1_GPIO_Port, IO_1_Pin, GPIO_PIN_RESET);
80007f2: 4b0b ldr r3, [pc, #44] ; (8000820 <App_UpdateMotor+0x15c>)
80007f4: 2200 movs r2, #0
80007f6: 2101 movs r1, #1
80007f8: 0018 movs r0, r3
80007fa: f003 f807 bl 800380c <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(IO_2_GPIO_Port, IO_2_Pin, GPIO_PIN_RESET);
80007fe: 23a0 movs r3, #160 ; 0xa0
8000800: 05db lsls r3, r3, #23
8000802: 2200 movs r2, #0
8000804: 2180 movs r1, #128 ; 0x80
8000806: 0018 movs r0, r3
8000808: f003 f800 bl 800380c <HAL_GPIO_WritePin>
}
800080c: 46c0 nop ; (mov r8, r8)
800080e: 46bd mov sp, r7
8000810: b006 add sp, #24
8000812: bd80 pop {r7, pc}
8000814: 200000a4 .word 0x200000a4
8000818: 00001067 .word 0x00001067
800081c: 200002c4 .word 0x200002c4
8000820: 50000400 .word 0x50000400
08000824 <App_SetCurrentLimit>:
static void App_SetCurrentLimit(uint16_t duty)
{
8000824: b580 push {r7, lr}
8000826: b082 sub sp, #8
8000828: af00 add r7, sp, #0
800082a: 0002 movs r2, r0
800082c: 1dbb adds r3, r7, #6
800082e: 801a strh r2, [r3, #0]
if (duty < PWM_DUTY_MIN || duty > PWM_DUTY_MAX)
8000830: 1dbb adds r3, r7, #6
8000832: 881b ldrh r3, [r3, #0]
8000834: 2b00 cmp r3, #0
8000836: d003 beq.n 8000840 <App_SetCurrentLimit+0x1c>
8000838: 1dbb adds r3, r7, #6
800083a: 881b ldrh r3, [r3, #0]
800083c: 2b63 cmp r3, #99 ; 0x63
800083e: d902 bls.n 8000846 <App_SetCurrentLimit+0x22>
{
duty = PWM_DUTY_DEFAULT;
8000840: 1dbb adds r3, r7, #6
8000842: 2263 movs r2, #99 ; 0x63
8000844: 801a strh r2, [r3, #0]
}
__HAL_TIM_SET_COMPARE(&htim3, TIM_CHANNEL_1, duty);
8000846: 4b04 ldr r3, [pc, #16] ; (8000858 <App_SetCurrentLimit+0x34>)
8000848: 681b ldr r3, [r3, #0]
800084a: 1dba adds r2, r7, #6
800084c: 8812 ldrh r2, [r2, #0]
800084e: 635a str r2, [r3, #52] ; 0x34
}
8000850: 46c0 nop ; (mov r8, r8)
8000852: 46bd mov sp, r7
8000854: b002 add sp, #8
8000856: bd80 pop {r7, pc}
8000858: 20000310 .word 0x20000310
0800085c <App_UpdateEncoderRegister>:
static void App_UpdateEncoderRegister(void)
{
800085c: b580 push {r7, lr}
800085e: b082 sub sp, #8
8000860: af00 add r7, sp, #0
int32_t enc = (int32_t)__HAL_TIM_GET_COUNTER(&htim2);
8000862: 4b06 ldr r3, [pc, #24] ; (800087c <App_UpdateEncoderRegister+0x20>)
8000864: 681b ldr r3, [r3, #0]
8000866: 6a5b ldr r3, [r3, #36] ; 0x24
8000868: 607b str r3, [r7, #4]
//holdingRegisters[2] = (uint16_t)(int16_t)enc;
holdingRegisters[2] = (int16_t)enc;
800086a: 687b ldr r3, [r7, #4]
800086c: b21a sxth r2, r3
800086e: 4b04 ldr r3, [pc, #16] ; (8000880 <App_UpdateEncoderRegister+0x24>)
8000870: 809a strh r2, [r3, #4]
}
8000872: 46c0 nop ; (mov r8, r8)
8000874: 46bd mov sp, r7
8000876: b002 add sp, #8
8000878: bd80 pop {r7, pc}
800087a: 46c0 nop ; (mov r8, r8)
800087c: 200002c4 .word 0x200002c4
8000880: 200000a4 .word 0x200000a4
08000884 <App_ProcessZeroCommand>:
static void App_ProcessZeroCommand(void)
{
8000884: b580 push {r7, lr}
8000886: af00 add r7, sp, #0
if (holdingRegisters[5] != lastRegister5)
8000888: 4b0a ldr r3, [pc, #40] ; (80008b4 <App_ProcessZeroCommand+0x30>)
800088a: 220a movs r2, #10
800088c: 5e9b ldrsh r3, [r3, r2]
800088e: 001a movs r2, r3
8000890: 4b09 ldr r3, [pc, #36] ; (80008b8 <App_ProcessZeroCommand+0x34>)
8000892: 881b ldrh r3, [r3, #0]
8000894: 429a cmp r2, r3
8000896: d009 beq.n 80008ac <App_ProcessZeroCommand+0x28>
{
lastRegister5 = holdingRegisters[5];
8000898: 4b06 ldr r3, [pc, #24] ; (80008b4 <App_ProcessZeroCommand+0x30>)
800089a: 220a movs r2, #10
800089c: 5e9b ldrsh r3, [r3, r2]
800089e: b29a uxth r2, r3
80008a0: 4b05 ldr r3, [pc, #20] ; (80008b8 <App_ProcessZeroCommand+0x34>)
80008a2: 801a strh r2, [r3, #0]
__HAL_TIM_SET_COUNTER(&htim2, 0);
80008a4: 4b05 ldr r3, [pc, #20] ; (80008bc <App_ProcessZeroCommand+0x38>)
80008a6: 681b ldr r3, [r3, #0]
80008a8: 2200 movs r2, #0
80008aa: 625a str r2, [r3, #36] ; 0x24
}
}
80008ac: 46c0 nop ; (mov r8, r8)
80008ae: 46bd mov sp, r7
80008b0: bd80 pop {r7, pc}
80008b2: 46c0 nop ; (mov r8, r8)
80008b4: 200000a4 .word 0x200000a4
80008b8: 2000009a .word 0x2000009a
80008bc: 200002c4 .word 0x200002c4
080008c0 <App_UpdateLed>:
static void App_UpdateLed(void)
{
80008c0: b580 push {r7, lr}
80008c2: b086 sub sp, #24
80008c4: af00 add r7, sp, #0
static uint32_t lastToggle = 0;
static GPIO_PinState ledState = GPIO_PIN_RESET;
uint8_t io1 = (holdingRegisters[0] != 0) ? 1U : 0U;
80008c6: 4b34 ldr r3, [pc, #208] ; (8000998 <App_UpdateLed+0xd8>)
80008c8: 2200 movs r2, #0
80008ca: 5e9b ldrsh r3, [r3, r2]
80008cc: 2b00 cmp r3, #0
80008ce: d001 beq.n 80008d4 <App_UpdateLed+0x14>
80008d0: 2201 movs r2, #1
80008d2: e000 b.n 80008d6 <App_UpdateLed+0x16>
80008d4: 2200 movs r2, #0
80008d6: 230f movs r3, #15
80008d8: 18fb adds r3, r7, r3
80008da: 701a strb r2, [r3, #0]
uint8_t io2 = (holdingRegisters[1] != 0) ? 1U : 0U;
80008dc: 4b2e ldr r3, [pc, #184] ; (8000998 <App_UpdateLed+0xd8>)
80008de: 2202 movs r2, #2
80008e0: 5e9b ldrsh r3, [r3, r2]
80008e2: 2b00 cmp r3, #0
80008e4: d001 beq.n 80008ea <App_UpdateLed+0x2a>
80008e6: 2201 movs r2, #1
80008e8: e000 b.n 80008ec <App_UpdateLed+0x2c>
80008ea: 2200 movs r2, #0
80008ec: 210e movs r1, #14
80008ee: 187b adds r3, r7, r1
80008f0: 701a strb r2, [r3, #0]
uint32_t onTime;
uint32_t offTime;
uint32_t period;
uint32_t elapsed;
if (io1 != 0 && io2 == 0)
80008f2: 230f movs r3, #15
80008f4: 18fb adds r3, r7, r3
80008f6: 781b ldrb r3, [r3, #0]
80008f8: 2b00 cmp r3, #0
80008fa: d009 beq.n 8000910 <App_UpdateLed+0x50>
80008fc: 187b adds r3, r7, r1
80008fe: 781b ldrb r3, [r3, #0]
8000900: 2b00 cmp r3, #0
8000902: d105 bne.n 8000910 <App_UpdateLed+0x50>
{
onTime = LED_ON_FORWARD_MS;
8000904: 23c8 movs r3, #200 ; 0xc8
8000906: 009b lsls r3, r3, #2
8000908: 617b str r3, [r7, #20]
offTime = LED_OFF_FORWARD_MS;
800090a: 23c8 movs r3, #200 ; 0xc8
800090c: 613b str r3, [r7, #16]
800090e: e015 b.n 800093c <App_UpdateLed+0x7c>
}
else if (io1 == 0 && io2 != 0)
8000910: 230f movs r3, #15
8000912: 18fb adds r3, r7, r3
8000914: 781b ldrb r3, [r3, #0]
8000916: 2b00 cmp r3, #0
8000918: d10a bne.n 8000930 <App_UpdateLed+0x70>
800091a: 230e movs r3, #14
800091c: 18fb adds r3, r7, r3
800091e: 781b ldrb r3, [r3, #0]
8000920: 2b00 cmp r3, #0
8000922: d005 beq.n 8000930 <App_UpdateLed+0x70>
{
onTime = LED_ON_REVERSE_MS;
8000924: 23c8 movs r3, #200 ; 0xc8
8000926: 617b str r3, [r7, #20]
offTime = LED_OFF_REVERSE_MS;
8000928: 23c8 movs r3, #200 ; 0xc8
800092a: 009b lsls r3, r3, #2
800092c: 613b str r3, [r7, #16]
800092e: e005 b.n 800093c <App_UpdateLed+0x7c>
}
else
{
onTime = LED_ON_STOP_MS;
8000930: 23fa movs r3, #250 ; 0xfa
8000932: 005b lsls r3, r3, #1
8000934: 617b str r3, [r7, #20]
offTime = LED_OFF_STOP_MS;
8000936: 23fa movs r3, #250 ; 0xfa
8000938: 005b lsls r3, r3, #1
800093a: 613b str r3, [r7, #16]
}
period = (ledState == GPIO_PIN_SET) ? onTime : offTime;
800093c: 4b17 ldr r3, [pc, #92] ; (800099c <App_UpdateLed+0xdc>)
800093e: 781b ldrb r3, [r3, #0]
8000940: 2b01 cmp r3, #1
8000942: d101 bne.n 8000948 <App_UpdateLed+0x88>
8000944: 697b ldr r3, [r7, #20]
8000946: e000 b.n 800094a <App_UpdateLed+0x8a>
8000948: 693b ldr r3, [r7, #16]
800094a: 60bb str r3, [r7, #8]
elapsed = HAL_GetTick() - lastToggle;
800094c: f001 f90a bl 8001b64 <HAL_GetTick>
8000950: 0002 movs r2, r0
8000952: 4b13 ldr r3, [pc, #76] ; (80009a0 <App_UpdateLed+0xe0>)
8000954: 681b ldr r3, [r3, #0]
8000956: 1ad3 subs r3, r2, r3
8000958: 607b str r3, [r7, #4]
if (elapsed >= period)
800095a: 687a ldr r2, [r7, #4]
800095c: 68bb ldr r3, [r7, #8]
800095e: 429a cmp r2, r3
8000960: d315 bcc.n 800098e <App_UpdateLed+0xce>
{
ledState = (ledState == GPIO_PIN_SET) ? GPIO_PIN_RESET : GPIO_PIN_SET;
8000962: 4b0e ldr r3, [pc, #56] ; (800099c <App_UpdateLed+0xdc>)
8000964: 781b ldrb r3, [r3, #0]
8000966: 3b01 subs r3, #1
8000968: 1e5a subs r2, r3, #1
800096a: 4193 sbcs r3, r2
800096c: b2db uxtb r3, r3
800096e: 001a movs r2, r3
8000970: 4b0a ldr r3, [pc, #40] ; (800099c <App_UpdateLed+0xdc>)
8000972: 701a strb r2, [r3, #0]
HAL_GPIO_WritePin(LED_GPIO_Port, LED_Pin, ledState);
8000974: 4b09 ldr r3, [pc, #36] ; (800099c <App_UpdateLed+0xdc>)
8000976: 781a ldrb r2, [r3, #0]
8000978: 2380 movs r3, #128 ; 0x80
800097a: 005b lsls r3, r3, #1
800097c: 4809 ldr r0, [pc, #36] ; (80009a4 <App_UpdateLed+0xe4>)
800097e: 0019 movs r1, r3
8000980: f002 ff44 bl 800380c <HAL_GPIO_WritePin>
lastToggle = HAL_GetTick();
8000984: f001 f8ee bl 8001b64 <HAL_GetTick>
8000988: 0002 movs r2, r0
800098a: 4b05 ldr r3, [pc, #20] ; (80009a0 <App_UpdateLed+0xe0>)
800098c: 601a str r2, [r3, #0]
}
}
800098e: 46c0 nop ; (mov r8, r8)
8000990: 46bd mov sp, r7
8000992: b006 add sp, #24
8000994: bd80 pop {r7, pc}
8000996: 46c0 nop ; (mov r8, r8)
8000998: 200000a4 .word 0x200000a4
800099c: 2000009c .word 0x2000009c
80009a0: 200000a0 .word 0x200000a0
80009a4: 50000400 .word 0x50000400
080009a8 <HAL_ADC_ConvCpltCallback>:
/* ADC 转换完成中断回调：把采样电压换算为电流（mA） */
void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc)
{
80009a8: b580 push {r7, lr}
80009aa: b086 sub sp, #24
80009ac: af00 add r7, sp, #0
80009ae: 6078 str r0, [r7, #4]
if (hadc->Instance != ADC1)
80009b0: 687b ldr r3, [r7, #4]
80009b2: 681b ldr r3, [r3, #0]
80009b4: 4a16 ldr r2, [pc, #88] ; (8000a10 <HAL_ADC_ConvCpltCallback+0x68>)
80009b6: 4293 cmp r3, r2
80009b8: d126 bne.n 8000a08 <HAL_ADC_ConvCpltCallback+0x60>
{
return;
}
uint32_t raw = HAL_ADC_GetValue(&hadc1);
80009ba: 4b16 ldr r3, [pc, #88] ; (8000a14 <HAL_ADC_ConvCpltCallback+0x6c>)
80009bc: 0018 movs r0, r3
80009be: f001 fc5f bl 8002280 <HAL_ADC_GetValue>
80009c2: 0003 movs r3, r0
80009c4: 613b str r3, [r7, #16]
uint32_t voltage_mv = (raw * ADC_REFERENCE_MV) / ADC_MAX_CODE;
80009c6: 693b ldr r3, [r7, #16]
80009c8: 4a13 ldr r2, [pc, #76] ; (8000a18 <HAL_ADC_ConvCpltCallback+0x70>)
80009ca: 4353 muls r3, r2
80009cc: 4913 ldr r1, [pc, #76] ; (8000a1c <HAL_ADC_ConvCpltCallback+0x74>)
80009ce: 0018 movs r0, r3
80009d0: f7ff fb98 bl 8000104 <__udivsi3>
80009d4: 0003 movs r3, r0
80009d6: 60fb str r3, [r7, #12]
uint16_t current_ma = (uint16_t)voltage_mv;
80009d8: 2116 movs r1, #22
80009da: 187b adds r3, r7, r1
80009dc: 68fa ldr r2, [r7, #12]
80009de: 801a strh r2, [r3, #0]
if (current_ma > CURRENT_MAX_MA)
80009e0: 187b adds r3, r7, r1
80009e2: 881a ldrh r2, [r3, #0]
80009e4: 23fa movs r3, #250 ; 0xfa
80009e6: 00db lsls r3, r3, #3
80009e8: 429a cmp r2, r3
80009ea: d903 bls.n 80009f4 <HAL_ADC_ConvCpltCallback+0x4c>
{
current_ma = CURRENT_MAX_MA;
80009ec: 187b adds r3, r7, r1
80009ee: 22fa movs r2, #250 ; 0xfa
80009f0: 00d2 lsls r2, r2, #3
80009f2: 801a strh r2, [r3, #0]
}
holdingRegisters[4] = current_ma;
80009f4: 2316 movs r3, #22
80009f6: 18fb adds r3, r7, r3
80009f8: 2200 movs r2, #0
80009fa: 5e9a ldrsh r2, [r3, r2]
80009fc: 4b08 ldr r3, [pc, #32] ; (8000a20 <HAL_ADC_ConvCpltCallback+0x78>)
80009fe: 811a strh r2, [r3, #8]
adcConversionDone = 1;
8000a00: 4b08 ldr r3, [pc, #32] ; (8000a24 <HAL_ADC_ConvCpltCallback+0x7c>)
8000a02: 2201 movs r2, #1
8000a04: 701a strb r2, [r3, #0]
8000a06: e000 b.n 8000a0a <HAL_ADC_ConvCpltCallback+0x62>
return;
8000a08: 46c0 nop ; (mov r8, r8)
}
8000a0a: 46bd mov sp, r7
8000a0c: b006 add sp, #24
8000a0e: bd80 pop {r7, pc}
8000a10: 40012400 .word 0x40012400
8000a14: 20000034 .word 0x20000034
8000a18: 00000ce4 .word 0x00000ce4
8000a1c: 00000fff .word 0x00000fff
8000a20: 200000a4 .word 0x200000a4
8000a24: 20000098 .word 0x20000098
08000a28 <MX_DMA_Init>:
/**
* Enable DMA controller clock
*/
void MX_DMA_Init(void)
{
8000a28: b580 push {r7, lr}
8000a2a: b082 sub sp, #8
8000a2c: af00 add r7, sp, #0
/* DMA controller clock enable */
__HAL_RCC_DMA1_CLK_ENABLE();
8000a2e: 4b0c ldr r3, [pc, #48] ; (8000a60 <MX_DMA_Init+0x38>)
8000a30: 6b9a ldr r2, [r3, #56] ; 0x38
8000a32: 4b0b ldr r3, [pc, #44] ; (8000a60 <MX_DMA_Init+0x38>)
8000a34: 2101 movs r1, #1
8000a36: 430a orrs r2, r1
8000a38: 639a str r2, [r3, #56] ; 0x38
8000a3a: 4b09 ldr r3, [pc, #36] ; (8000a60 <MX_DMA_Init+0x38>)
8000a3c: 6b9b ldr r3, [r3, #56] ; 0x38
8000a3e: 2201 movs r2, #1
8000a40: 4013 ands r3, r2
8000a42: 607b str r3, [r7, #4]
8000a44: 687b ldr r3, [r7, #4]
/* DMA interrupt init */
/* DMA1_Channel1_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
8000a46: 2200 movs r2, #0
8000a48: 2100 movs r1, #0
8000a4a: 2009 movs r0, #9
8000a4c: f002 fa2a bl 8002ea4 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
8000a50: 2009 movs r0, #9
8000a52: f002 fa3c bl 8002ece <HAL_NVIC_EnableIRQ>
}
8000a56: 46c0 nop ; (mov r8, r8)
8000a58: 46bd mov sp, r7
8000a5a: b002 add sp, #8
8000a5c: bd80 pop {r7, pc}
8000a5e: 46c0 nop ; (mov r8, r8)
8000a60: 40021000 .word 0x40021000
08000a64 <MX_GPIO_Init>:
* Output
* EVENT_OUT
* EXTI
*/
void MX_GPIO_Init(void)
{
8000a64: b590 push {r4, r7, lr}
8000a66: b089 sub sp, #36 ; 0x24
8000a68: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000a6a: 240c movs r4, #12
8000a6c: 193b adds r3, r7, r4
8000a6e: 0018 movs r0, r3
8000a70: 2314 movs r3, #20
8000a72: 001a movs r2, r3
8000a74: 2100 movs r1, #0
8000a76: f006 fca3 bl 80073c0 <memset>
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOA_CLK_ENABLE();
8000a7a: 4b28 ldr r3, [pc, #160] ; (8000b1c <MX_GPIO_Init+0xb8>)
8000a7c: 6b5a ldr r2, [r3, #52] ; 0x34
8000a7e: 4b27 ldr r3, [pc, #156] ; (8000b1c <MX_GPIO_Init+0xb8>)
8000a80: 2101 movs r1, #1
8000a82: 430a orrs r2, r1
8000a84: 635a str r2, [r3, #52] ; 0x34
8000a86: 4b25 ldr r3, [pc, #148] ; (8000b1c <MX_GPIO_Init+0xb8>)
8000a88: 6b5b ldr r3, [r3, #52] ; 0x34
8000a8a: 2201 movs r2, #1
8000a8c: 4013 ands r3, r2
8000a8e: 60bb str r3, [r7, #8]
8000a90: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOB_CLK_ENABLE();
8000a92: 4b22 ldr r3, [pc, #136] ; (8000b1c <MX_GPIO_Init+0xb8>)
8000a94: 6b5a ldr r2, [r3, #52] ; 0x34
8000a96: 4b21 ldr r3, [pc, #132] ; (8000b1c <MX_GPIO_Init+0xb8>)
8000a98: 2102 movs r1, #2
8000a9a: 430a orrs r2, r1
8000a9c: 635a str r2, [r3, #52] ; 0x34
8000a9e: 4b1f ldr r3, [pc, #124] ; (8000b1c <MX_GPIO_Init+0xb8>)
8000aa0: 6b5b ldr r3, [r3, #52] ; 0x34
8000aa2: 2202 movs r2, #2
8000aa4: 4013 ands r3, r2
8000aa6: 607b str r3, [r7, #4]
8000aa8: 687b ldr r3, [r7, #4]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOA, DIR_Pin|IO_2_Pin, GPIO_PIN_RESET);
8000aaa: 23a0 movs r3, #160 ; 0xa0
8000aac: 05db lsls r3, r3, #23
8000aae: 2200 movs r2, #0
8000ab0: 2190 movs r1, #144 ; 0x90
8000ab2: 0018 movs r0, r3
8000ab4: f002 feaa bl 800380c <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOB, IO_1_Pin|LED_Pin, GPIO_PIN_RESET);
8000ab8: 2302 movs r3, #2
8000aba: 33ff adds r3, #255 ; 0xff
8000abc: 4818 ldr r0, [pc, #96] ; (8000b20 <MX_GPIO_Init+0xbc>)
8000abe: 2200 movs r2, #0
8000ac0: 0019 movs r1, r3
8000ac2: f002 fea3 bl 800380c <HAL_GPIO_WritePin>
/*Configure GPIO pins : PAPin PAPin */
GPIO_InitStruct.Pin = DIR_Pin|IO_2_Pin;
8000ac6: 193b adds r3, r7, r4
8000ac8: 2290 movs r2, #144 ; 0x90
8000aca: 601a str r2, [r3, #0]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000acc: 193b adds r3, r7, r4
8000ace: 2201 movs r2, #1
8000ad0: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000ad2: 193b adds r3, r7, r4
8000ad4: 2200 movs r2, #0
8000ad6: 609a str r2, [r3, #8]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000ad8: 193b adds r3, r7, r4
8000ada: 2200 movs r2, #0
8000adc: 60da str r2, [r3, #12]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000ade: 193a adds r2, r7, r4
8000ae0: 23a0 movs r3, #160 ; 0xa0
8000ae2: 05db lsls r3, r3, #23
8000ae4: 0011 movs r1, r2
8000ae6: 0018 movs r0, r3
8000ae8: f002 fd2c bl 8003544 <HAL_GPIO_Init>
/*Configure GPIO pins : PBPin PBPin */
GPIO_InitStruct.Pin = IO_1_Pin|LED_Pin;
8000aec: 0021 movs r1, r4
8000aee: 187b adds r3, r7, r1
8000af0: 2202 movs r2, #2
8000af2: 32ff adds r2, #255 ; 0xff
8000af4: 601a str r2, [r3, #0]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000af6: 187b adds r3, r7, r1
8000af8: 2201 movs r2, #1
8000afa: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000afc: 187b adds r3, r7, r1
8000afe: 2200 movs r2, #0
8000b00: 609a str r2, [r3, #8]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000b02: 187b adds r3, r7, r1
8000b04: 2200 movs r2, #0
8000b06: 60da str r2, [r3, #12]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8000b08: 187b adds r3, r7, r1
8000b0a: 4a05 ldr r2, [pc, #20] ; (8000b20 <MX_GPIO_Init+0xbc>)
8000b0c: 0019 movs r1, r3
8000b0e: 0010 movs r0, r2
8000b10: f002 fd18 bl 8003544 <HAL_GPIO_Init>
}
8000b14: 46c0 nop ; (mov r8, r8)
8000b16: 46bd mov sp, r7
8000b18: b009 add sp, #36 ; 0x24
8000b1a: bd90 pop {r4, r7, pc}
8000b1c: 40021000 .word 0x40021000
8000b20: 50000400 .word 0x50000400
08000b24 <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
8000b24: b580 push {r7, lr}
8000b26: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
8000b28: f000 ffa0 bl 8001a6c <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
8000b2c: f000 f813 bl 8000b56 <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
8000b30: f7ff ff98 bl 8000a64 <MX_GPIO_Init>
MX_TIM3_Init();
8000b34: f000 fdba bl 80016ac <MX_TIM3_Init>
MX_DMA_Init();
8000b38: f7ff ff76 bl 8000a28 <MX_DMA_Init>
MX_TIM2_Init();
8000b3c: f000 fd54 bl 80015e8 <MX_TIM2_Init>
MX_ADC1_Init();
8000b40: f7ff fc82 bl 8000448 <MX_ADC1_Init>
MX_USART2_UART_Init();
8000b44: f000 feb4 bl 80018b0 <MX_USART2_UART_Init>
/* USER CODE BEGIN 2 */
App_Init();
8000b48: f7ff fd4a bl 80005e0 <App_Init>
Modbus_Init();
8000b4c: f000 f850 bl 8000bf0 <Modbus_Init>
while (1)
{
/* USER CODE END WHILE */
/* USER CODE BEGIN 3 */
App_Process();
8000b50: f7ff fd90 bl 8000674 <App_Process>
8000b54: e7fc b.n 8000b50 <main+0x2c>
08000b56 <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
8000b56: b590 push {r4, r7, lr}
8000b58: b093 sub sp, #76 ; 0x4c
8000b5a: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
8000b5c: 2410 movs r4, #16
8000b5e: 193b adds r3, r7, r4
8000b60: 0018 movs r0, r3
8000b62: 2338 movs r3, #56 ; 0x38
8000b64: 001a movs r2, r3
8000b66: 2100 movs r1, #0
8000b68: f006 fc2a bl 80073c0 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
8000b6c: 003b movs r3, r7
8000b6e: 0018 movs r0, r3
8000b70: 2310 movs r3, #16
8000b72: 001a movs r2, r3
8000b74: 2100 movs r1, #0
8000b76: f006 fc23 bl 80073c0 <memset>
/** Configure the main internal regulator output voltage
*/
HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
8000b7a: 2380 movs r3, #128 ; 0x80
8000b7c: 009b lsls r3, r3, #2
8000b7e: 0018 movs r0, r3
8000b80: f002 fe62 bl 8003848 <HAL_PWREx_ControlVoltageScaling>
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
8000b84: 193b adds r3, r7, r4
8000b86: 2202 movs r2, #2
8000b88: 601a str r2, [r3, #0]
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
8000b8a: 193b adds r3, r7, r4
8000b8c: 2280 movs r2, #128 ; 0x80
8000b8e: 0052 lsls r2, r2, #1
8000b90: 60da str r2, [r3, #12]
RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1;
8000b92: 193b adds r3, r7, r4
8000b94: 2200 movs r2, #0
8000b96: 611a str r2, [r3, #16]
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
8000b98: 193b adds r3, r7, r4
8000b9a: 2240 movs r2, #64 ; 0x40
8000b9c: 615a str r2, [r3, #20]
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
8000b9e: 193b adds r3, r7, r4
8000ba0: 2200 movs r2, #0
8000ba2: 61da str r2, [r3, #28]
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
8000ba4: 193b adds r3, r7, r4
8000ba6: 0018 movs r0, r3
8000ba8: f002 fe9a bl 80038e0 <HAL_RCC_OscConfig>
8000bac: 1e03 subs r3, r0, #0
8000bae: d001 beq.n 8000bb4 <SystemClock_Config+0x5e>
{
Error_Handler();
8000bb0: f000 f819 bl 8000be6 <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
8000bb4: 003b movs r3, r7
8000bb6: 2207 movs r2, #7
8000bb8: 601a str r2, [r3, #0]
|RCC_CLOCKTYPE_PCLK1;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
8000bba: 003b movs r3, r7
8000bbc: 2200 movs r2, #0
8000bbe: 605a str r2, [r3, #4]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
8000bc0: 003b movs r3, r7
8000bc2: 2200 movs r2, #0
8000bc4: 609a str r2, [r3, #8]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
8000bc6: 003b movs r3, r7
8000bc8: 2200 movs r2, #0
8000bca: 60da str r2, [r3, #12]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
8000bcc: 003b movs r3, r7
8000bce: 2100 movs r1, #0
8000bd0: 0018 movs r0, r3
8000bd2: f003 f99f bl 8003f14 <HAL_RCC_ClockConfig>
8000bd6: 1e03 subs r3, r0, #0
8000bd8: d001 beq.n 8000bde <SystemClock_Config+0x88>
{
Error_Handler();
8000bda: f000 f804 bl 8000be6 <Error_Handler>
}
}
8000bde: 46c0 nop ; (mov r8, r8)
8000be0: 46bd mov sp, r7
8000be2: b013 add sp, #76 ; 0x4c
8000be4: bd90 pop {r4, r7, pc}
08000be6 <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
8000be6: b580 push {r7, lr}
8000be8: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
8000bea: b672 cpsid i
}
8000bec: 46c0 nop ; (mov r8, r8)
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
8000bee: e7fe b.n 8000bee <Error_Handler+0x8>
08000bf0 <Modbus_Init>:
void Modbus_SendExceptionResponse(uint8_t exceptionCode);
uint16_t CalculateCRC(uint8_t *data, uint8_t length);
/* 初始化函数 */
void Modbus_Init(void)
{
8000bf0: b580 push {r7, lr}
8000bf2: af00 add r7, sp, #0
/* RS485 方向控制引脚置为接收状态 */
HAL_GPIO_WritePin(DIR_GPIO_Port, DIR_Pin, GPIO_PIN_RESET);
8000bf4: 23a0 movs r3, #160 ; 0xa0
8000bf6: 05db lsls r3, r3, #23
8000bf8: 2200 movs r2, #0
8000bfa: 2110 movs r1, #16
8000bfc: 0018 movs r0, r3
8000bfe: f002 fe05 bl 800380c <HAL_GPIO_WritePin>
/* 启动串口中断接收 */
modbusBufferIndex = 0;
8000c02: 4b08 ldr r3, [pc, #32] ; (8000c24 <Modbus_Init+0x34>)
8000c04: 2200 movs r2, #0
8000c06: 801a strh r2, [r3, #0]
HAL_UART_Receive_IT(&huart2, (uint8_t *)&modbusBuffer[modbusBufferIndex], 1);
8000c08: 4b06 ldr r3, [pc, #24] ; (8000c24 <Modbus_Init+0x34>)
8000c0a: 881b ldrh r3, [r3, #0]
8000c0c: 001a movs r2, r3
8000c0e: 4b06 ldr r3, [pc, #24] ; (8000c28 <Modbus_Init+0x38>)
8000c10: 18d1 adds r1, r2, r3
8000c12: 4b06 ldr r3, [pc, #24] ; (8000c2c <Modbus_Init+0x3c>)
8000c14: 2201 movs r2, #1
8000c16: 0018 movs r0, r3
8000c18: f004 fc16 bl 8005448 <HAL_UART_Receive_IT>
}
8000c1c: 46c0 nop ; (mov r8, r8)
8000c1e: 46bd mov sp, r7
8000c20: bd80 pop {r7, pc}
8000c22: 46c0 nop ; (mov r8, r8)
8000c24: 200001b8 .word 0x200001b8
8000c28: 200000b8 .word 0x200000b8
8000c2c: 2000035c .word 0x2000035c
08000c30 <Modbus_Process>:
/* Modbus处理函数 - 应在主循环中调用 */
void Modbus_Process(void)
{
8000c30: b590 push {r4, r7, lr}
8000c32: b085 sub sp, #20
8000c34: af00 add r7, sp, #0
uint16_t startAddress = 0;
8000c36: 230e movs r3, #14
8000c38: 18fb adds r3, r7, r3
8000c3a: 2200 movs r2, #0
8000c3c: 801a strh r2, [r3, #0]
uint16_t registerCount = 0;
8000c3e: 230c movs r3, #12
8000c40: 18fb adds r3, r7, r3
8000c42: 2200 movs r2, #0
8000c44: 801a strh r2, [r3, #0]
uint16_t value = 0;
8000c46: 230a movs r3, #10
8000c48: 18fb adds r3, r7, r3
8000c4a: 2200 movs r2, #0
8000c4c: 801a strh r2, [r3, #0]
uint8_t byteCount = 0;
8000c4e: 2309 movs r3, #9
8000c50: 18fb adds r3, r7, r3
8000c52: 2200 movs r2, #0
8000c54: 701a strb r2, [r3, #0]
uint16_t crcReceived;
uint16_t crcCalculated;
if (modbusBufferIndex > 0 && (HAL_GetTick() - lastByteTime) > MODBUS_TIMEOUT_MS)
8000c56: 4b7c ldr r3, [pc, #496] ; (8000e48 <Modbus_Process+0x218>)
8000c58: 881b ldrh r3, [r3, #0]
8000c5a: 2b00 cmp r3, #0
8000c5c: d00a beq.n 8000c74 <Modbus_Process+0x44>
8000c5e: f000 ff81 bl 8001b64 <HAL_GetTick>
8000c62: 0002 movs r2, r0
8000c64: 4b79 ldr r3, [pc, #484] ; (8000e4c <Modbus_Process+0x21c>)
8000c66: 681b ldr r3, [r3, #0]
8000c68: 1ad3 subs r3, r2, r3
8000c6a: 2b05 cmp r3, #5
8000c6c: d902 bls.n 8000c74 <Modbus_Process+0x44>
{
/* 超时，标记消息完成 */
messageComplete = true;
8000c6e: 4b78 ldr r3, [pc, #480] ; (8000e50 <Modbus_Process+0x220>)
8000c70: 2201 movs r2, #1
8000c72: 701a strb r2, [r3, #0]
}
if (!messageComplete)
8000c74: 4b76 ldr r3, [pc, #472] ; (8000e50 <Modbus_Process+0x220>)
8000c76: 781b ldrb r3, [r3, #0]
8000c78: 2201 movs r2, #1
8000c7a: 4053 eors r3, r2
8000c7c: b2db uxtb r3, r3
8000c7e: 2b00 cmp r3, #0
8000c80: d000 beq.n 8000c84 <Modbus_Process+0x54>
8000c82: e0dd b.n 8000e40 <Modbus_Process+0x210>
{
return;
}
/* 一个有效的 RTU 帧至少包含：地址 + 功能码 + 2 字节 CRC */
if (modbusBufferIndex < 4)
8000c84: 4b70 ldr r3, [pc, #448] ; (8000e48 <Modbus_Process+0x218>)
8000c86: 881b ldrh r3, [r3, #0]
8000c88: 2b03 cmp r3, #3
8000c8a: d806 bhi.n 8000c9a <Modbus_Process+0x6a>
{
modbusBufferIndex = 0;
8000c8c: 4b6e ldr r3, [pc, #440] ; (8000e48 <Modbus_Process+0x218>)
8000c8e: 2200 movs r2, #0
8000c90: 801a strh r2, [r3, #0]
messageComplete = false;
8000c92: 4b6f ldr r3, [pc, #444] ; (8000e50 <Modbus_Process+0x220>)
8000c94: 2200 movs r2, #0
8000c96: 701a strb r2, [r3, #0]
return;
8000c98: e0d3 b.n 8000e42 <Modbus_Process+0x212>
}
crcReceived = (uint16_t)((modbusBuffer[modbusBufferIndex - 1] << 8) |
8000c9a: 4b6b ldr r3, [pc, #428] ; (8000e48 <Modbus_Process+0x218>)
8000c9c: 881b ldrh r3, [r3, #0]
8000c9e: 3b01 subs r3, #1
8000ca0: 4a6c ldr r2, [pc, #432] ; (8000e54 <Modbus_Process+0x224>)
8000ca2: 5cd3 ldrb r3, [r2, r3]
8000ca4: 021b lsls r3, r3, #8
8000ca6: b21a sxth r2, r3
modbusBuffer[modbusBufferIndex - 2]);
8000ca8: 4b67 ldr r3, [pc, #412] ; (8000e48 <Modbus_Process+0x218>)
8000caa: 881b ldrh r3, [r3, #0]
8000cac: 3b02 subs r3, #2
8000cae: 4969 ldr r1, [pc, #420] ; (8000e54 <Modbus_Process+0x224>)
8000cb0: 5ccb ldrb r3, [r1, r3]
8000cb2: b21b sxth r3, r3
crcReceived = (uint16_t)((modbusBuffer[modbusBufferIndex - 1] << 8) |
8000cb4: 4313 orrs r3, r2
8000cb6: b21a sxth r2, r3
8000cb8: 1dbb adds r3, r7, #6
8000cba: 801a strh r2, [r3, #0]
crcCalculated = CalculateCRC(modbusBuffer, (uint8_t)(modbusBufferIndex - 2));
8000cbc: 4b62 ldr r3, [pc, #392] ; (8000e48 <Modbus_Process+0x218>)
8000cbe: 881b ldrh r3, [r3, #0]
8000cc0: b2db uxtb r3, r3
8000cc2: 3b02 subs r3, #2
8000cc4: b2da uxtb r2, r3
8000cc6: 1d3c adds r4, r7, #4
8000cc8: 4b62 ldr r3, [pc, #392] ; (8000e54 <Modbus_Process+0x224>)
8000cca: 0011 movs r1, r2
8000ccc: 0018 movs r0, r3
8000cce: f000 fb53 bl 8001378 <CalculateCRC>
8000cd2: 0003 movs r3, r0
8000cd4: 8023 strh r3, [r4, #0]
if (MODBUS_CRC_OFF == 1 || crcReceived == crcCalculated)
8000cd6: 1dba adds r2, r7, #6
8000cd8: 1d3b adds r3, r7, #4
8000cda: 8812 ldrh r2, [r2, #0]
8000cdc: 881b ldrh r3, [r3, #0]
8000cde: 429a cmp r2, r3
8000ce0: d000 beq.n 8000ce4 <Modbus_Process+0xb4>
8000ce2: e09f b.n 8000e24 <Modbus_Process+0x1f4>
{
if (modbusBuffer[0] == MODBUS_SLAVE_ADDRESS) /*ID 0x42*/
8000ce4: 4b5b ldr r3, [pc, #364] ; (8000e54 <Modbus_Process+0x224>)
8000ce6: 781b ldrb r3, [r3, #0]
8000ce8: 2b42 cmp r3, #66 ; 0x42
8000cea: d000 beq.n 8000cee <Modbus_Process+0xbe>
8000cec: e09a b.n 8000e24 <Modbus_Process+0x1f4>
{
switch (modbusBuffer[1])
8000cee: 4b59 ldr r3, [pc, #356] ; (8000e54 <Modbus_Process+0x224>)
8000cf0: 785b ldrb r3, [r3, #1]
8000cf2: 2b10 cmp r3, #16
8000cf4: d051 beq.n 8000d9a <Modbus_Process+0x16a>
8000cf6: dd00 ble.n 8000cfa <Modbus_Process+0xca>
8000cf8: e090 b.n 8000e1c <Modbus_Process+0x1ec>
8000cfa: 2b03 cmp r3, #3
8000cfc: d002 beq.n 8000d04 <Modbus_Process+0xd4>
8000cfe: 2b06 cmp r3, #6
8000d00: d026 beq.n 8000d50 <Modbus_Process+0x120>
8000d02: e08b b.n 8000e1c <Modbus_Process+0x1ec>
{
case MODBUS_FUNCTION_CODE_03:
if (modbusBufferIndex >= 8)
8000d04: 4b50 ldr r3, [pc, #320] ; (8000e48 <Modbus_Process+0x218>)
8000d06: 881b ldrh r3, [r3, #0]
8000d08: 2b07 cmp r3, #7
8000d0a: d800 bhi.n 8000d0e <Modbus_Process+0xde>
8000d0c: e08c b.n 8000e28 <Modbus_Process+0x1f8>
{
startAddress = (uint16_t)((modbusBuffer[2] << 8) | modbusBuffer[3]);
8000d0e: 4b51 ldr r3, [pc, #324] ; (8000e54 <Modbus_Process+0x224>)
8000d10: 789b ldrb r3, [r3, #2]
8000d12: 021b lsls r3, r3, #8
8000d14: b21a sxth r2, r3
8000d16: 4b4f ldr r3, [pc, #316] ; (8000e54 <Modbus_Process+0x224>)
8000d18: 78db ldrb r3, [r3, #3]
8000d1a: b21b sxth r3, r3
8000d1c: 4313 orrs r3, r2
8000d1e: b21a sxth r2, r3
8000d20: 210e movs r1, #14
8000d22: 187b adds r3, r7, r1
8000d24: 801a strh r2, [r3, #0]
registerCount = (uint16_t)((modbusBuffer[4] << 8) | modbusBuffer[5]);
8000d26: 4b4b ldr r3, [pc, #300] ; (8000e54 <Modbus_Process+0x224>)
8000d28: 791b ldrb r3, [r3, #4]
8000d2a: 021b lsls r3, r3, #8
8000d2c: b21a sxth r2, r3
8000d2e: 4b49 ldr r3, [pc, #292] ; (8000e54 <Modbus_Process+0x224>)
8000d30: 795b ldrb r3, [r3, #5]
8000d32: b21b sxth r3, r3
8000d34: 4313 orrs r3, r2
8000d36: b21a sxth r2, r3
8000d38: 200c movs r0, #12
8000d3a: 183b adds r3, r7, r0
8000d3c: 801a strh r2, [r3, #0]
Modbus_HandleFunction03(startAddress, registerCount);
8000d3e: 183b adds r3, r7, r0
8000d40: 881a ldrh r2, [r3, #0]
8000d42: 187b adds r3, r7, r1
8000d44: 881b ldrh r3, [r3, #0]
8000d46: 0011 movs r1, r2
8000d48: 0018 movs r0, r3
8000d4a: f000 f887 bl 8000e5c <Modbus_HandleFunction03>
}
break;
8000d4e: e06b b.n 8000e28 <Modbus_Process+0x1f8>
case MODBUS_FUNCTION_CODE_06:
if (modbusBufferIndex >= 8)
8000d50: 4b3d ldr r3, [pc, #244] ; (8000e48 <Modbus_Process+0x218>)
8000d52: 881b ldrh r3, [r3, #0]
8000d54: 2b07 cmp r3, #7
8000d56: d969 bls.n 8000e2c <Modbus_Process+0x1fc>
{
startAddress = (uint16_t)((modbusBuffer[2] << 8) | modbusBuffer[3]);
8000d58: 4b3e ldr r3, [pc, #248] ; (8000e54 <Modbus_Process+0x224>)
8000d5a: 789b ldrb r3, [r3, #2]
8000d5c: 021b lsls r3, r3, #8
8000d5e: b21a sxth r2, r3
8000d60: 4b3c ldr r3, [pc, #240] ; (8000e54 <Modbus_Process+0x224>)
8000d62: 78db ldrb r3, [r3, #3]
8000d64: b21b sxth r3, r3
8000d66: 4313 orrs r3, r2
8000d68: b21a sxth r2, r3
8000d6a: 210e movs r1, #14
8000d6c: 187b adds r3, r7, r1
8000d6e: 801a strh r2, [r3, #0]
value = (uint16_t)((modbusBuffer[4] << 8) | modbusBuffer[5]);
8000d70: 4b38 ldr r3, [pc, #224] ; (8000e54 <Modbus_Process+0x224>)
8000d72: 791b ldrb r3, [r3, #4]
8000d74: 021b lsls r3, r3, #8
8000d76: b21a sxth r2, r3
8000d78: 4b36 ldr r3, [pc, #216] ; (8000e54 <Modbus_Process+0x224>)
8000d7a: 795b ldrb r3, [r3, #5]
8000d7c: b21b sxth r3, r3
8000d7e: 4313 orrs r3, r2
8000d80: b21a sxth r2, r3
8000d82: 200a movs r0, #10
8000d84: 183b adds r3, r7, r0
8000d86: 801a strh r2, [r3, #0]
Modbus_HandleFunction06(startAddress, value);
8000d88: 183b adds r3, r7, r0
8000d8a: 881a ldrh r2, [r3, #0]
8000d8c: 187b adds r3, r7, r1
8000d8e: 881b ldrh r3, [r3, #0]
8000d90: 0011 movs r1, r2
8000d92: 0018 movs r0, r3
8000d94: f000 f90c bl 8000fb0 <Modbus_HandleFunction06>
}
break;
8000d98: e048 b.n 8000e2c <Modbus_Process+0x1fc>
case MODBUS_FUNCTION_CODE_10:
if (modbusBufferIndex >= 9)
8000d9a: 4b2b ldr r3, [pc, #172] ; (8000e48 <Modbus_Process+0x218>)
8000d9c: 881b ldrh r3, [r3, #0]
8000d9e: 2b08 cmp r3, #8
8000da0: d946 bls.n 8000e30 <Modbus_Process+0x200>
{
startAddress = (uint16_t)((modbusBuffer[2] << 8) | modbusBuffer[3]);
8000da2: 4b2c ldr r3, [pc, #176] ; (8000e54 <Modbus_Process+0x224>)
8000da4: 789b ldrb r3, [r3, #2]
8000da6: 021b lsls r3, r3, #8
8000da8: b21a sxth r2, r3
8000daa: 4b2a ldr r3, [pc, #168] ; (8000e54 <Modbus_Process+0x224>)
8000dac: 78db ldrb r3, [r3, #3]
8000dae: b21b sxth r3, r3
8000db0: 4313 orrs r3, r2
8000db2: b21a sxth r2, r3
8000db4: 240e movs r4, #14
8000db6: 193b adds r3, r7, r4
8000db8: 801a strh r2, [r3, #0]
registerCount = (uint16_t)((modbusBuffer[4] << 8) | modbusBuffer[5]);
8000dba: 4b26 ldr r3, [pc, #152] ; (8000e54 <Modbus_Process+0x224>)
8000dbc: 791b ldrb r3, [r3, #4]
8000dbe: 021b lsls r3, r3, #8
8000dc0: b21a sxth r2, r3
8000dc2: 4b24 ldr r3, [pc, #144] ; (8000e54 <Modbus_Process+0x224>)
8000dc4: 795b ldrb r3, [r3, #5]
8000dc6: b21b sxth r3, r3
8000dc8: 4313 orrs r3, r2
8000dca: b21a sxth r2, r3
8000dcc: 210c movs r1, #12
8000dce: 187b adds r3, r7, r1
8000dd0: 801a strh r2, [r3, #0]
byteCount = modbusBuffer[6];
8000dd2: 2009 movs r0, #9
8000dd4: 183b adds r3, r7, r0
8000dd6: 4a1f ldr r2, [pc, #124] ; (8000e54 <Modbus_Process+0x224>)
8000dd8: 7992 ldrb r2, [r2, #6]
8000dda: 701a strb r2, [r3, #0]
/* 检查数据长度是否正确 */
if (byteCount == (uint8_t)(registerCount * 2U) &&
8000ddc: 187b adds r3, r7, r1
8000dde: 881b ldrh r3, [r3, #0]
8000de0: b2db uxtb r3, r3
8000de2: 18db adds r3, r3, r3
8000de4: b2db uxtb r3, r3
8000de6: 183a adds r2, r7, r0
8000de8: 7812 ldrb r2, [r2, #0]
8000dea: 429a cmp r2, r3
8000dec: d112 bne.n 8000e14 <Modbus_Process+0x1e4>
(modbusBufferIndex - 2U) >= (uint16_t)(7U + byteCount))
8000dee: 4b16 ldr r3, [pc, #88] ; (8000e48 <Modbus_Process+0x218>)
8000df0: 881b ldrh r3, [r3, #0]
8000df2: 3b02 subs r3, #2
8000df4: 183a adds r2, r7, r0
8000df6: 7812 ldrb r2, [r2, #0]
8000df8: b292 uxth r2, r2
8000dfa: 3207 adds r2, #7
8000dfc: b292 uxth r2, r2
if (byteCount == (uint8_t)(registerCount * 2U) &&
8000dfe: 4293 cmp r3, r2
8000e00: d308 bcc.n 8000e14 <Modbus_Process+0x1e4>
{
Modbus_HandleFunction10(startAddress, registerCount, &modbusBuffer[7]);
8000e02: 4a15 ldr r2, [pc, #84] ; (8000e58 <Modbus_Process+0x228>)
8000e04: 187b adds r3, r7, r1
8000e06: 8819 ldrh r1, [r3, #0]
8000e08: 193b adds r3, r7, r4
8000e0a: 881b ldrh r3, [r3, #0]
8000e0c: 0018 movs r0, r3
8000e0e: f000 f981 bl 8001114 <Modbus_HandleFunction10>
else
{
Modbus_SendExceptionResponse(0x03);
}
}
break;
8000e12: e00d b.n 8000e30 <Modbus_Process+0x200>
Modbus_SendExceptionResponse(0x03);
8000e14: 2003 movs r0, #3
8000e16: f000 fa5b bl 80012d0 <Modbus_SendExceptionResponse>
break;
8000e1a: e009 b.n 8000e30 <Modbus_Process+0x200>
default:
Modbus_SendExceptionResponse(0x01);
8000e1c: 2001 movs r0, #1
8000e1e: f000 fa57 bl 80012d0 <Modbus_SendExceptionResponse>
break;
8000e22: e006 b.n 8000e32 <Modbus_Process+0x202>
}
}
8000e24: 46c0 nop ; (mov r8, r8)
8000e26: e004 b.n 8000e32 <Modbus_Process+0x202>
break;
8000e28: 46c0 nop ; (mov r8, r8)
8000e2a: e002 b.n 8000e32 <Modbus_Process+0x202>
break;
8000e2c: 46c0 nop ; (mov r8, r8)
8000e2e: e000 b.n 8000e32 <Modbus_Process+0x202>
break;
8000e30: 46c0 nop ; (mov r8, r8)
}
/* 重置缓冲区 */
modbusBufferIndex = 0;
8000e32: 4b05 ldr r3, [pc, #20] ; (8000e48 <Modbus_Process+0x218>)
8000e34: 2200 movs r2, #0
8000e36: 801a strh r2, [r3, #0]
messageComplete = false;
8000e38: 4b05 ldr r3, [pc, #20] ; (8000e50 <Modbus_Process+0x220>)
8000e3a: 2200 movs r2, #0
8000e3c: 701a strb r2, [r3, #0]
8000e3e: e000 b.n 8000e42 <Modbus_Process+0x212>
return;
8000e40: 46c0 nop ; (mov r8, r8)
}
8000e42: 46bd mov sp, r7
8000e44: b005 add sp, #20
8000e46: bd90 pop {r4, r7, pc}
8000e48: 200001b8 .word 0x200001b8
8000e4c: 200001bc .word 0x200001bc
8000e50: 200001c0 .word 0x200001c0
8000e54: 200000b8 .word 0x200000b8
8000e58: 200000bf .word 0x200000bf
08000e5c <Modbus_HandleFunction03>:
/* 处理功能码03 */
void Modbus_HandleFunction03(uint16_t startAddress, uint16_t registerCount)
{
8000e5c: b5f0 push {r4, r5, r6, r7, lr}
8000e5e: b087 sub sp, #28
8000e60: af00 add r7, sp, #0
8000e62: 0002 movs r2, r0
8000e64: 1dbb adds r3, r7, #6
8000e66: 801a strh r2, [r3, #0]
8000e68: 1d3b adds r3, r7, #4
8000e6a: 1c0a adds r2, r1, #0
8000e6c: 801a strh r2, [r3, #0]
/* 检查地址和数量是否合法 */
if ((startAddress + registerCount) > (REGISTER_START_ADDRESS + REGISTER_COUNT) ||
8000e6e: 1dbb adds r3, r7, #6
8000e70: 881a ldrh r2, [r3, #0]
8000e72: 1d3b adds r3, r7, #4
8000e74: 881b ldrh r3, [r3, #0]
8000e76: 18d3 adds r3, r2, r3
8000e78: 2b0a cmp r3, #10
8000e7a: dc03 bgt.n 8000e84 <Modbus_HandleFunction03+0x28>
8000e7c: 1d3b adds r3, r7, #4
8000e7e: 881b ldrh r3, [r3, #0]
8000e80: 2b7d cmp r3, #125 ; 0x7d
8000e82: d903 bls.n 8000e8c <Modbus_HandleFunction03+0x30>
registerCount > 0x7D)
{
Modbus_SendExceptionResponse(0x02);
8000e84: 2002 movs r0, #2
8000e86: f000 fa23 bl 80012d0 <Modbus_SendExceptionResponse>
return;
8000e8a: e089 b.n 8000fa0 <Modbus_HandleFunction03+0x144>
}
uint8_t byteCount = (uint8_t)(registerCount * 2U);
8000e8c: 1d3b adds r3, r7, #4
8000e8e: 881b ldrh r3, [r3, #0]
8000e90: b2db uxtb r3, r3
8000e92: 2413 movs r4, #19
8000e94: 193a adds r2, r7, r4
8000e96: 18db adds r3, r3, r3
8000e98: 7013 strb r3, [r2, #0]
uint8_t index = 0;
8000e9a: 2017 movs r0, #23
8000e9c: 183b adds r3, r7, r0
8000e9e: 2200 movs r2, #0
8000ea0: 701a strb r2, [r3, #0]
response[index++] = MODBUS_SLAVE_ADDRESS;
8000ea2: 183b adds r3, r7, r0
8000ea4: 781b ldrb r3, [r3, #0]
8000ea6: 183a adds r2, r7, r0
8000ea8: 1c59 adds r1, r3, #1
8000eaa: 7011 strb r1, [r2, #0]
8000eac: 001a movs r2, r3
8000eae: 4b3e ldr r3, [pc, #248] ; (8000fa8 <Modbus_HandleFunction03+0x14c>)
8000eb0: 2142 movs r1, #66 ; 0x42
8000eb2: 5499 strb r1, [r3, r2]
response[index++] = MODBUS_FUNCTION_CODE_03;
8000eb4: 183b adds r3, r7, r0
8000eb6: 781b ldrb r3, [r3, #0]
8000eb8: 183a adds r2, r7, r0
8000eba: 1c59 adds r1, r3, #1
8000ebc: 7011 strb r1, [r2, #0]
8000ebe: 001a movs r2, r3
8000ec0: 4b39 ldr r3, [pc, #228] ; (8000fa8 <Modbus_HandleFunction03+0x14c>)
8000ec2: 2103 movs r1, #3
8000ec4: 5499 strb r1, [r3, r2]
response[index++] = byteCount;
8000ec6: 183b adds r3, r7, r0
8000ec8: 781b ldrb r3, [r3, #0]
8000eca: 183a adds r2, r7, r0
8000ecc: 1c59 adds r1, r3, #1
8000ece: 7011 strb r1, [r2, #0]
8000ed0: 0019 movs r1, r3
8000ed2: 4b35 ldr r3, [pc, #212] ; (8000fa8 <Modbus_HandleFunction03+0x14c>)
8000ed4: 193a adds r2, r7, r4
8000ed6: 7812 ldrb r2, [r2, #0]
8000ed8: 545a strb r2, [r3, r1]
for (uint16_t i = 0; i < registerCount; i++)
8000eda: 2314 movs r3, #20
8000edc: 18fb adds r3, r7, r3
8000ede: 2200 movs r2, #0
8000ee0: 801a strh r2, [r3, #0]
8000ee2: e029 b.n 8000f38 <Modbus_HandleFunction03+0xdc>
{
uint16_t regValue = holdingRegisters[(startAddress - REGISTER_START_ADDRESS) + i];
8000ee4: 1dbb adds r3, r7, #6
8000ee6: 881a ldrh r2, [r3, #0]
8000ee8: 2514 movs r5, #20
8000eea: 197b adds r3, r7, r5
8000eec: 881b ldrh r3, [r3, #0]
8000eee: 18d2 adds r2, r2, r3
8000ef0: 4b2e ldr r3, [pc, #184] ; (8000fac <Modbus_HandleFunction03+0x150>)
8000ef2: 0052 lsls r2, r2, #1
8000ef4: 5ed2 ldrsh r2, [r2, r3]
8000ef6: 260e movs r6, #14
8000ef8: 19bb adds r3, r7, r6
8000efa: 801a strh r2, [r3, #0]
response[index++] = (uint8_t)((regValue >> 8) & 0xFF);
8000efc: 19bb adds r3, r7, r6
8000efe: 881b ldrh r3, [r3, #0]
8000f00: 0a1b lsrs r3, r3, #8
8000f02: b299 uxth r1, r3
8000f04: 2417 movs r4, #23
8000f06: 193b adds r3, r7, r4
8000f08: 781b ldrb r3, [r3, #0]
8000f0a: 193a adds r2, r7, r4
8000f0c: 1c58 adds r0, r3, #1
8000f0e: 7010 strb r0, [r2, #0]
8000f10: 001a movs r2, r3
8000f12: b2c9 uxtb r1, r1
8000f14: 4b24 ldr r3, [pc, #144] ; (8000fa8 <Modbus_HandleFunction03+0x14c>)
8000f16: 5499 strb r1, [r3, r2]
response[index++] = (uint8_t)(regValue & 0xFF);
8000f18: 193b adds r3, r7, r4
8000f1a: 781b ldrb r3, [r3, #0]
8000f1c: 193a adds r2, r7, r4
8000f1e: 1c59 adds r1, r3, #1
8000f20: 7011 strb r1, [r2, #0]
8000f22: 001a movs r2, r3
8000f24: 19bb adds r3, r7, r6
8000f26: 881b ldrh r3, [r3, #0]
8000f28: b2d9 uxtb r1, r3
8000f2a: 4b1f ldr r3, [pc, #124] ; (8000fa8 <Modbus_HandleFunction03+0x14c>)
8000f2c: 5499 strb r1, [r3, r2]
for (uint16_t i = 0; i < registerCount; i++)
8000f2e: 197b adds r3, r7, r5
8000f30: 881a ldrh r2, [r3, #0]
8000f32: 197b adds r3, r7, r5
8000f34: 3201 adds r2, #1
8000f36: 801a strh r2, [r3, #0]
8000f38: 2314 movs r3, #20
8000f3a: 18fa adds r2, r7, r3
8000f3c: 1d3b adds r3, r7, #4
8000f3e: 8812 ldrh r2, [r2, #0]
8000f40: 881b ldrh r3, [r3, #0]
8000f42: 429a cmp r2, r3
8000f44: d3ce bcc.n 8000ee4 <Modbus_HandleFunction03+0x88>
}
uint16_t crc = CalculateCRC(response, index);
8000f46: 2610 movs r6, #16
8000f48: 19bc adds r4, r7, r6
8000f4a: 2517 movs r5, #23
8000f4c: 197b adds r3, r7, r5
8000f4e: 781a ldrb r2, [r3, #0]
8000f50: 4b15 ldr r3, [pc, #84] ; (8000fa8 <Modbus_HandleFunction03+0x14c>)
8000f52: 0011 movs r1, r2
8000f54: 0018 movs r0, r3
8000f56: f000 fa0f bl 8001378 <CalculateCRC>
8000f5a: 0003 movs r3, r0
8000f5c: 8023 strh r3, [r4, #0]
response[index++] = (uint8_t)(crc & 0xFF);
8000f5e: 0028 movs r0, r5
8000f60: 183b adds r3, r7, r0
8000f62: 781b ldrb r3, [r3, #0]
8000f64: 183a adds r2, r7, r0
8000f66: 1c59 adds r1, r3, #1
8000f68: 7011 strb r1, [r2, #0]
8000f6a: 001a movs r2, r3
8000f6c: 19bb adds r3, r7, r6
8000f6e: 881b ldrh r3, [r3, #0]
8000f70: b2d9 uxtb r1, r3
8000f72: 4b0d ldr r3, [pc, #52] ; (8000fa8 <Modbus_HandleFunction03+0x14c>)
8000f74: 5499 strb r1, [r3, r2]
response[index++] = (uint8_t)((crc >> 8) & 0xFF);
8000f76: 19bb adds r3, r7, r6
8000f78: 881b ldrh r3, [r3, #0]
8000f7a: 0a1b lsrs r3, r3, #8
8000f7c: b299 uxth r1, r3
8000f7e: 183b adds r3, r7, r0
8000f80: 781b ldrb r3, [r3, #0]
8000f82: 0004 movs r4, r0
8000f84: 183a adds r2, r7, r0
8000f86: 1c58 adds r0, r3, #1
8000f88: 7010 strb r0, [r2, #0]
8000f8a: 001a movs r2, r3
8000f8c: b2c9 uxtb r1, r1
8000f8e: 4b06 ldr r3, [pc, #24] ; (8000fa8 <Modbus_HandleFunction03+0x14c>)
8000f90: 5499 strb r1, [r3, r2]
Modbus_SendResponse(response, index);
8000f92: 193b adds r3, r7, r4
8000f94: 781a ldrb r2, [r3, #0]
8000f96: 4b04 ldr r3, [pc, #16] ; (8000fa8 <Modbus_HandleFunction03+0x14c>)
8000f98: 0011 movs r1, r2
8000f9a: 0018 movs r0, r3
8000f9c: f000 f9d0 bl 8001340 <Modbus_SendResponse>
}
8000fa0: 46bd mov sp, r7
8000fa2: b007 add sp, #28
8000fa4: bdf0 pop {r4, r5, r6, r7, pc}
8000fa6: 46c0 nop ; (mov r8, r8)
8000fa8: 200001c4 .word 0x200001c4
8000fac: 200000a4 .word 0x200000a4
08000fb0 <Modbus_HandleFunction06>:
/* 处理功能码06 */
void Modbus_HandleFunction06(uint16_t registerAddress, uint16_t value)
{
8000fb0: b5f0 push {r4, r5, r6, r7, lr}
8000fb2: b085 sub sp, #20
8000fb4: af00 add r7, sp, #0
8000fb6: 0002 movs r2, r0
8000fb8: 1dbb adds r3, r7, #6
8000fba: 801a strh r2, [r3, #0]
8000fbc: 1d3b adds r3, r7, #4
8000fbe: 1c0a adds r2, r1, #0
8000fc0: 801a strh r2, [r3, #0]
/* 检查地址是否合法 */
if (registerAddress >= (REGISTER_START_ADDRESS + REGISTER_COUNT))
8000fc2: 1dbb adds r3, r7, #6
8000fc4: 881b ldrh r3, [r3, #0]
8000fc6: 2b09 cmp r3, #9
8000fc8: d903 bls.n 8000fd2 <Modbus_HandleFunction06+0x22>
{
Modbus_SendExceptionResponse(0x02);
8000fca: 2002 movs r0, #2
8000fcc: f000 f980 bl 80012d0 <Modbus_SendExceptionResponse>
return;
8000fd0: e096 b.n 8001100 <Modbus_HandleFunction06+0x150>
}
uint16_t regIndex = registerAddress - REGISTER_START_ADDRESS;
8000fd2: 210c movs r1, #12
8000fd4: 187b adds r3, r7, r1
8000fd6: 1dba adds r2, r7, #6
8000fd8: 8812 ldrh r2, [r2, #0]
8000fda: 801a strh r2, [r3, #0]
uint16_t responseValue = holdingRegisters[regIndex];
8000fdc: 187b adds r3, r7, r1
8000fde: 881a ldrh r2, [r3, #0]
8000fe0: 4b49 ldr r3, [pc, #292] ; (8001108 <Modbus_HandleFunction06+0x158>)
8000fe2: 0052 lsls r2, r2, #1
8000fe4: 5ed2 ldrsh r2, [r2, r3]
8000fe6: 200e movs r0, #14
8000fe8: 183b adds r3, r7, r0
8000fea: 801a strh r2, [r3, #0]
/* 只有可写寄存器才更新值 */
if (registerWritable[regIndex] == 1)
8000fec: 187b adds r3, r7, r1
8000fee: 881b ldrh r3, [r3, #0]
8000ff0: 4a46 ldr r2, [pc, #280] ; (800110c <Modbus_HandleFunction06+0x15c>)
8000ff2: 5cd3 ldrb r3, [r2, r3]
8000ff4: 2b01 cmp r3, #1
8000ff6: d10b bne.n 8001010 <Modbus_HandleFunction06+0x60>
{
holdingRegisters[regIndex] = value;
8000ff8: 187b adds r3, r7, r1
8000ffa: 881a ldrh r2, [r3, #0]
8000ffc: 1d3b adds r3, r7, #4
8000ffe: 2100 movs r1, #0
8001000: 5e59 ldrsh r1, [r3, r1]
8001002: 4b41 ldr r3, [pc, #260] ; (8001108 <Modbus_HandleFunction06+0x158>)
8001004: 0052 lsls r2, r2, #1
8001006: 52d1 strh r1, [r2, r3]
responseValue = value;
8001008: 183b adds r3, r7, r0
800100a: 1d3a adds r2, r7, #4
800100c: 8812 ldrh r2, [r2, #0]
800100e: 801a strh r2, [r3, #0]
}
/* 准备响应帧 - 功能码06的响应是原请求帧的原样返回 */
uint8_t index = 0;
8001010: 200b movs r0, #11
8001012: 183b adds r3, r7, r0
8001014: 2200 movs r2, #0
8001016: 701a strb r2, [r3, #0]
response[index++] = MODBUS_SLAVE_ADDRESS;
8001018: 183b adds r3, r7, r0
800101a: 781b ldrb r3, [r3, #0]
800101c: 183a adds r2, r7, r0
800101e: 1c59 adds r1, r3, #1
8001020: 7011 strb r1, [r2, #0]
8001022: 001a movs r2, r3
8001024: 4b3a ldr r3, [pc, #232] ; (8001110 <Modbus_HandleFunction06+0x160>)
8001026: 2142 movs r1, #66 ; 0x42
8001028: 5499 strb r1, [r3, r2]
response[index++] = MODBUS_FUNCTION_CODE_06;
800102a: 183b adds r3, r7, r0
800102c: 781b ldrb r3, [r3, #0]
800102e: 183a adds r2, r7, r0
8001030: 1c59 adds r1, r3, #1
8001032: 7011 strb r1, [r2, #0]
8001034: 001a movs r2, r3
8001036: 4b36 ldr r3, [pc, #216] ; (8001110 <Modbus_HandleFunction06+0x160>)
8001038: 2106 movs r1, #6
800103a: 5499 strb r1, [r3, r2]
response[index++] = (uint8_t)((registerAddress >> 8) & 0xFF);
800103c: 1dbb adds r3, r7, #6
800103e: 881b ldrh r3, [r3, #0]
8001040: 0a1b lsrs r3, r3, #8
8001042: b299 uxth r1, r3
8001044: 183b adds r3, r7, r0
8001046: 781b ldrb r3, [r3, #0]
8001048: 0004 movs r4, r0
800104a: 183a adds r2, r7, r0
800104c: 1c58 adds r0, r3, #1
800104e: 7010 strb r0, [r2, #0]
8001050: 001a movs r2, r3
8001052: b2c9 uxtb r1, r1
8001054: 4b2e ldr r3, [pc, #184] ; (8001110 <Modbus_HandleFunction06+0x160>)
8001056: 5499 strb r1, [r3, r2]
response[index++] = (uint8_t)(registerAddress & 0xFF);
8001058: 0020 movs r0, r4
800105a: 183b adds r3, r7, r0
800105c: 781b ldrb r3, [r3, #0]
800105e: 183a adds r2, r7, r0
8001060: 1c59 adds r1, r3, #1
8001062: 7011 strb r1, [r2, #0]
8001064: 001a movs r2, r3
8001066: 1dbb adds r3, r7, #6
8001068: 881b ldrh r3, [r3, #0]
800106a: b2d9 uxtb r1, r3
800106c: 4b28 ldr r3, [pc, #160] ; (8001110 <Modbus_HandleFunction06+0x160>)
800106e: 5499 strb r1, [r3, r2]
response[index++] = (uint8_t)((responseValue >> 8) & 0xFF);
8001070: 250e movs r5, #14
8001072: 197b adds r3, r7, r5
8001074: 881b ldrh r3, [r3, #0]
8001076: 0a1b lsrs r3, r3, #8
8001078: b299 uxth r1, r3
800107a: 183b adds r3, r7, r0
800107c: 781b ldrb r3, [r3, #0]
800107e: 0004 movs r4, r0
8001080: 183a adds r2, r7, r0
8001082: 1c58 adds r0, r3, #1
8001084: 7010 strb r0, [r2, #0]
8001086: 001a movs r2, r3
8001088: b2c9 uxtb r1, r1
800108a: 4b21 ldr r3, [pc, #132] ; (8001110 <Modbus_HandleFunction06+0x160>)
800108c: 5499 strb r1, [r3, r2]
response[index++] = (uint8_t)(responseValue & 0xFF);
800108e: 0020 movs r0, r4
8001090: 183b adds r3, r7, r0
8001092: 781b ldrb r3, [r3, #0]
8001094: 183a adds r2, r7, r0
8001096: 1c59 adds r1, r3, #1
8001098: 7011 strb r1, [r2, #0]
800109a: 001a movs r2, r3
800109c: 197b adds r3, r7, r5
800109e: 881b ldrh r3, [r3, #0]
80010a0: b2d9 uxtb r1, r3
80010a2: 4b1b ldr r3, [pc, #108] ; (8001110 <Modbus_HandleFunction06+0x160>)
80010a4: 5499 strb r1, [r3, r2]
/* 计算CRC并添加到响应帧 */
uint16_t crc = CalculateCRC(response, index);
80010a6: 2608 movs r6, #8
80010a8: 19bc adds r4, r7, r6
80010aa: 0005 movs r5, r0
80010ac: 183b adds r3, r7, r0
80010ae: 781a ldrb r2, [r3, #0]
80010b0: 4b17 ldr r3, [pc, #92] ; (8001110 <Modbus_HandleFunction06+0x160>)
80010b2: 0011 movs r1, r2
80010b4: 0018 movs r0, r3
80010b6: f000 f95f bl 8001378 <CalculateCRC>
80010ba: 0003 movs r3, r0
80010bc: 8023 strh r3, [r4, #0]
response[index++] = (uint8_t)(crc & 0xFF);
80010be: 0028 movs r0, r5
80010c0: 183b adds r3, r7, r0
80010c2: 781b ldrb r3, [r3, #0]
80010c4: 183a adds r2, r7, r0
80010c6: 1c59 adds r1, r3, #1
80010c8: 7011 strb r1, [r2, #0]
80010ca: 001a movs r2, r3
80010cc: 19bb adds r3, r7, r6
80010ce: 881b ldrh r3, [r3, #0]
80010d0: b2d9 uxtb r1, r3
80010d2: 4b0f ldr r3, [pc, #60] ; (8001110 <Modbus_HandleFunction06+0x160>)
80010d4: 5499 strb r1, [r3, r2]
response[index++] = (uint8_t)((crc >> 8) & 0xFF);
80010d6: 19bb adds r3, r7, r6
80010d8: 881b ldrh r3, [r3, #0]
80010da: 0a1b lsrs r3, r3, #8
80010dc: b299 uxth r1, r3
80010de: 183b adds r3, r7, r0
80010e0: 781b ldrb r3, [r3, #0]
80010e2: 0004 movs r4, r0
80010e4: 183a adds r2, r7, r0
80010e6: 1c58 adds r0, r3, #1
80010e8: 7010 strb r0, [r2, #0]
80010ea: 001a movs r2, r3
80010ec: b2c9 uxtb r1, r1
80010ee: 4b08 ldr r3, [pc, #32] ; (8001110 <Modbus_HandleFunction06+0x160>)
80010f0: 5499 strb r1, [r3, r2]
/* 发送响应 */
Modbus_SendResponse(response, index);
80010f2: 193b adds r3, r7, r4
80010f4: 781a ldrb r2, [r3, #0]
80010f6: 4b06 ldr r3, [pc, #24] ; (8001110 <Modbus_HandleFunction06+0x160>)
80010f8: 0011 movs r1, r2
80010fa: 0018 movs r0, r3
80010fc: f000 f920 bl 8001340 <Modbus_SendResponse>
}
8001100: 46bd mov sp, r7
8001102: b005 add sp, #20
8001104: bdf0 pop {r4, r5, r6, r7, pc}
8001106: 46c0 nop ; (mov r8, r8)
8001108: 200000a4 .word 0x200000a4
800110c: 20000000 .word 0x20000000
8001110: 200001c4 .word 0x200001c4
08001114 <Modbus_HandleFunction10>:
/* 处理功能码0x10 */
void Modbus_HandleFunction10(uint16_t startAddress, uint16_t registerCount, uint8_t *data)
{
8001114: b5f0 push {r4, r5, r6, r7, lr}
8001116: b087 sub sp, #28
8001118: af00 add r7, sp, #0
800111a: 603a str r2, [r7, #0]
800111c: 1dbb adds r3, r7, #6
800111e: 1c02 adds r2, r0, #0
8001120: 801a strh r2, [r3, #0]
8001122: 1d3b adds r3, r7, #4
8001124: 1c0a adds r2, r1, #0
8001126: 801a strh r2, [r3, #0]
/* 检查地址和数量是否合法 */
if ((startAddress + registerCount) > (REGISTER_START_ADDRESS + REGISTER_COUNT) ||
8001128: 1dbb adds r3, r7, #6
800112a: 881a ldrh r2, [r3, #0]
800112c: 1d3b adds r3, r7, #4
800112e: 881b ldrh r3, [r3, #0]
8001130: 18d3 adds r3, r2, r3
8001132: 2b0a cmp r3, #10
8001134: dc07 bgt.n 8001146 <Modbus_HandleFunction10+0x32>
8001136: 1d3b adds r3, r7, #4
8001138: 881b ldrh r3, [r3, #0]
800113a: 2b00 cmp r3, #0
800113c: d003 beq.n 8001146 <Modbus_HandleFunction10+0x32>
registerCount == 0 || registerCount > 0x7B)
800113e: 1d3b adds r3, r7, #4
8001140: 881b ldrh r3, [r3, #0]
8001142: 2b7b cmp r3, #123 ; 0x7b
8001144: d903 bls.n 800114e <Modbus_HandleFunction10+0x3a>
{
Modbus_SendExceptionResponse(0x02);
8001146: 2002 movs r0, #2
8001148: f000 f8c2 bl 80012d0 <Modbus_SendExceptionResponse>
return;
800114c: e0b6 b.n 80012bc <Modbus_HandleFunction10+0x1a8>
}
/* 处理每个寄存器 */
for (uint16_t i = 0; i < registerCount; i++)
800114e: 2316 movs r3, #22
8001150: 18fb adds r3, r7, r3
8001152: 2200 movs r2, #0
8001154: 801a strh r2, [r3, #0]
8001156: e033 b.n 80011c0 <Modbus_HandleFunction10+0xac>
{
uint16_t regIndex = (startAddress - REGISTER_START_ADDRESS) + i;
8001158: 2010 movs r0, #16
800115a: 183b adds r3, r7, r0
800115c: 1db9 adds r1, r7, #6
800115e: 2416 movs r4, #22
8001160: 193a adds r2, r7, r4
8001162: 8809 ldrh r1, [r1, #0]
8001164: 8812 ldrh r2, [r2, #0]
8001166: 188a adds r2, r1, r2
8001168: 801a strh r2, [r3, #0]
uint16_t value = (uint16_t)((data[i * 2] << 8) | data[i * 2 + 1]);
800116a: 0021 movs r1, r4
800116c: 187b adds r3, r7, r1
800116e: 881b ldrh r3, [r3, #0]
8001170: 005b lsls r3, r3, #1
8001172: 001a movs r2, r3
8001174: 683b ldr r3, [r7, #0]
8001176: 189b adds r3, r3, r2
8001178: 781b ldrb r3, [r3, #0]
800117a: 021b lsls r3, r3, #8
800117c: b21a sxth r2, r3
800117e: 187b adds r3, r7, r1
8001180: 881b ldrh r3, [r3, #0]
8001182: 005b lsls r3, r3, #1
8001184: 3301 adds r3, #1
8001186: 6839 ldr r1, [r7, #0]
8001188: 18cb adds r3, r1, r3
800118a: 781b ldrb r3, [r3, #0]
800118c: b21b sxth r3, r3
800118e: 4313 orrs r3, r2
8001190: b21a sxth r2, r3
8001192: 210e movs r1, #14
8001194: 187b adds r3, r7, r1
8001196: 801a strh r2, [r3, #0]
/* 只有可写寄存器才更新值 */
if (registerWritable[regIndex] == 1)
8001198: 183b adds r3, r7, r0
800119a: 881b ldrh r3, [r3, #0]
800119c: 4a49 ldr r2, [pc, #292] ; (80012c4 <Modbus_HandleFunction10+0x1b0>)
800119e: 5cd3 ldrb r3, [r2, r3]
80011a0: 2b01 cmp r3, #1
80011a2: d107 bne.n 80011b4 <Modbus_HandleFunction10+0xa0>
{
holdingRegisters[regIndex] = value;
80011a4: 183b adds r3, r7, r0
80011a6: 881a ldrh r2, [r3, #0]
80011a8: 187b adds r3, r7, r1
80011aa: 2100 movs r1, #0
80011ac: 5e59 ldrsh r1, [r3, r1]
80011ae: 4b46 ldr r3, [pc, #280] ; (80012c8 <Modbus_HandleFunction10+0x1b4>)
80011b0: 0052 lsls r2, r2, #1
80011b2: 52d1 strh r1, [r2, r3]
for (uint16_t i = 0; i < registerCount; i++)
80011b4: 2116 movs r1, #22
80011b6: 187b adds r3, r7, r1
80011b8: 881a ldrh r2, [r3, #0]
80011ba: 187b adds r3, r7, r1
80011bc: 3201 adds r2, #1
80011be: 801a strh r2, [r3, #0]
80011c0: 2316 movs r3, #22
80011c2: 18fa adds r2, r7, r3
80011c4: 1d3b adds r3, r7, #4
80011c6: 8812 ldrh r2, [r2, #0]
80011c8: 881b ldrh r3, [r3, #0]
80011ca: 429a cmp r2, r3
80011cc: d3c4 bcc.n 8001158 <Modbus_HandleFunction10+0x44>
}
}
/* 准备响应帧 - 功能码0x10的响应包含起始地址和写入数量 */
uint8_t index = 0;
80011ce: 2015 movs r0, #21
80011d0: 183b adds r3, r7, r0
80011d2: 2200 movs r2, #0
80011d4: 701a strb r2, [r3, #0]
response[index++] = MODBUS_SLAVE_ADDRESS;
80011d6: 183b adds r3, r7, r0
80011d8: 781b ldrb r3, [r3, #0]
80011da: 183a adds r2, r7, r0
80011dc: 1c59 adds r1, r3, #1
80011de: 7011 strb r1, [r2, #0]
80011e0: 001a movs r2, r3
80011e2: 4b3a ldr r3, [pc, #232] ; (80012cc <Modbus_HandleFunction10+0x1b8>)
80011e4: 2142 movs r1, #66 ; 0x42
80011e6: 5499 strb r1, [r3, r2]
response[index++] = MODBUS_FUNCTION_CODE_10;
80011e8: 183b adds r3, r7, r0
80011ea: 781b ldrb r3, [r3, #0]
80011ec: 183a adds r2, r7, r0
80011ee: 1c59 adds r1, r3, #1
80011f0: 7011 strb r1, [r2, #0]
80011f2: 001a movs r2, r3
80011f4: 4b35 ldr r3, [pc, #212] ; (80012cc <Modbus_HandleFunction10+0x1b8>)
80011f6: 2110 movs r1, #16
80011f8: 5499 strb r1, [r3, r2]
response[index++] = (uint8_t)((startAddress >> 8) & 0xFF);
80011fa: 1dbb adds r3, r7, #6
80011fc: 881b ldrh r3, [r3, #0]
80011fe: 0a1b lsrs r3, r3, #8
8001200: b299 uxth r1, r3
8001202: 183b adds r3, r7, r0
8001204: 781b ldrb r3, [r3, #0]
8001206: 0004 movs r4, r0
8001208: 183a adds r2, r7, r0
800120a: 1c58 adds r0, r3, #1
800120c: 7010 strb r0, [r2, #0]
800120e: 001a movs r2, r3
8001210: b2c9 uxtb r1, r1
8001212: 4b2e ldr r3, [pc, #184] ; (80012cc <Modbus_HandleFunction10+0x1b8>)
8001214: 5499 strb r1, [r3, r2]
response[index++] = (uint8_t)(startAddress & 0xFF);
8001216: 0020 movs r0, r4
8001218: 183b adds r3, r7, r0
800121a: 781b ldrb r3, [r3, #0]
800121c: 183a adds r2, r7, r0
800121e: 1c59 adds r1, r3, #1
8001220: 7011 strb r1, [r2, #0]
8001222: 001a movs r2, r3
8001224: 1dbb adds r3, r7, #6
8001226: 881b ldrh r3, [r3, #0]
8001228: b2d9 uxtb r1, r3
800122a: 4b28 ldr r3, [pc, #160] ; (80012cc <Modbus_HandleFunction10+0x1b8>)
800122c: 5499 strb r1, [r3, r2]
response[index++] = (uint8_t)((registerCount >> 8) & 0xFF);
800122e: 1d3b adds r3, r7, #4
8001230: 881b ldrh r3, [r3, #0]
8001232: 0a1b lsrs r3, r3, #8
8001234: b299 uxth r1, r3
8001236: 183b adds r3, r7, r0
8001238: 781b ldrb r3, [r3, #0]
800123a: 0004 movs r4, r0
800123c: 183a adds r2, r7, r0
800123e: 1c58 adds r0, r3, #1
8001240: 7010 strb r0, [r2, #0]
8001242: 001a movs r2, r3
8001244: b2c9 uxtb r1, r1
8001246: 4b21 ldr r3, [pc, #132] ; (80012cc <Modbus_HandleFunction10+0x1b8>)
8001248: 5499 strb r1, [r3, r2]
response[index++] = (uint8_t)(registerCount & 0xFF);
800124a: 0020 movs r0, r4
800124c: 183b adds r3, r7, r0
800124e: 781b ldrb r3, [r3, #0]
8001250: 183a adds r2, r7, r0
8001252: 1c59 adds r1, r3, #1
8001254: 7011 strb r1, [r2, #0]
8001256: 001a movs r2, r3
8001258: 1d3b adds r3, r7, #4
800125a: 881b ldrh r3, [r3, #0]
800125c: b2d9 uxtb r1, r3
800125e: 4b1b ldr r3, [pc, #108] ; (80012cc <Modbus_HandleFunction10+0x1b8>)
8001260: 5499 strb r1, [r3, r2]
/* 计算CRC并添加到响应帧 */
uint16_t crc = CalculateCRC(response, index);
8001262: 2612 movs r6, #18
8001264: 19bc adds r4, r7, r6
8001266: 0005 movs r5, r0
8001268: 183b adds r3, r7, r0
800126a: 781a ldrb r2, [r3, #0]
800126c: 4b17 ldr r3, [pc, #92] ; (80012cc <Modbus_HandleFunction10+0x1b8>)
800126e: 0011 movs r1, r2
8001270: 0018 movs r0, r3
8001272: f000 f881 bl 8001378 <CalculateCRC>
8001276: 0003 movs r3, r0
8001278: 8023 strh r3, [r4, #0]
response[index++] = (uint8_t)(crc & 0xFF);
800127a: 0028 movs r0, r5
800127c: 183b adds r3, r7, r0
800127e: 781b ldrb r3, [r3, #0]
8001280: 183a adds r2, r7, r0
8001282: 1c59 adds r1, r3, #1
8001284: 7011 strb r1, [r2, #0]
8001286: 001a movs r2, r3
8001288: 19bb adds r3, r7, r6
800128a: 881b ldrh r3, [r3, #0]
800128c: b2d9 uxtb r1, r3
800128e: 4b0f ldr r3, [pc, #60] ; (80012cc <Modbus_HandleFunction10+0x1b8>)
8001290: 5499 strb r1, [r3, r2]
response[index++] = (uint8_t)((crc >> 8) & 0xFF);
8001292: 19bb adds r3, r7, r6
8001294: 881b ldrh r3, [r3, #0]
8001296: 0a1b lsrs r3, r3, #8
8001298: b299 uxth r1, r3
800129a: 183b adds r3, r7, r0
800129c: 781b ldrb r3, [r3, #0]
800129e: 0004 movs r4, r0
80012a0: 183a adds r2, r7, r0
80012a2: 1c58 adds r0, r3, #1
80012a4: 7010 strb r0, [r2, #0]
80012a6: 001a movs r2, r3
80012a8: b2c9 uxtb r1, r1
80012aa: 4b08 ldr r3, [pc, #32] ; (80012cc <Modbus_HandleFunction10+0x1b8>)
80012ac: 5499 strb r1, [r3, r2]
/* 发送响应 */
Modbus_SendResponse(response, index);
80012ae: 193b adds r3, r7, r4
80012b0: 781a ldrb r2, [r3, #0]
80012b2: 4b06 ldr r3, [pc, #24] ; (80012cc <Modbus_HandleFunction10+0x1b8>)
80012b4: 0011 movs r1, r2
80012b6: 0018 movs r0, r3
80012b8: f000 f842 bl 8001340 <Modbus_SendResponse>
}
80012bc: 46bd mov sp, r7
80012be: b007 add sp, #28
80012c0: bdf0 pop {r4, r5, r6, r7, pc}
80012c2: 46c0 nop ; (mov r8, r8)
80012c4: 20000000 .word 0x20000000
80012c8: 200000a4 .word 0x200000a4
80012cc: 200001c4 .word 0x200001c4
080012d0 <Modbus_SendExceptionResponse>:
/* 发送异常响应 */
void Modbus_SendExceptionResponse(uint8_t exceptionCode)
{
80012d0: b5b0 push {r4, r5, r7, lr}
80012d2: b084 sub sp, #16
80012d4: af00 add r7, sp, #0
80012d6: 0002 movs r2, r0
80012d8: 1dfb adds r3, r7, #7
80012da: 701a strb r2, [r3, #0]
response[0] = MODBUS_SLAVE_ADDRESS;
80012dc: 4b16 ldr r3, [pc, #88] ; (8001338 <Modbus_SendExceptionResponse+0x68>)
80012de: 2242 movs r2, #66 ; 0x42
80012e0: 701a strb r2, [r3, #0]
response[1] = modbusBuffer[1] | 0x80;
80012e2: 4b16 ldr r3, [pc, #88] ; (800133c <Modbus_SendExceptionResponse+0x6c>)
80012e4: 785b ldrb r3, [r3, #1]
80012e6: 2280 movs r2, #128 ; 0x80
80012e8: 4252 negs r2, r2
80012ea: 4313 orrs r3, r2
80012ec: b2da uxtb r2, r3
80012ee: 4b12 ldr r3, [pc, #72] ; (8001338 <Modbus_SendExceptionResponse+0x68>)
80012f0: 705a strb r2, [r3, #1]
response[2] = exceptionCode;
80012f2: 4b11 ldr r3, [pc, #68] ; (8001338 <Modbus_SendExceptionResponse+0x68>)
80012f4: 1dfa adds r2, r7, #7
80012f6: 7812 ldrb r2, [r2, #0]
80012f8: 709a strb r2, [r3, #2]
uint16_t crc = CalculateCRC(response, 3);
80012fa: 250e movs r5, #14
80012fc: 197c adds r4, r7, r5
80012fe: 4b0e ldr r3, [pc, #56] ; (8001338 <Modbus_SendExceptionResponse+0x68>)
8001300: 2103 movs r1, #3
8001302: 0018 movs r0, r3
8001304: f000 f838 bl 8001378 <CalculateCRC>
8001308: 0003 movs r3, r0
800130a: 8023 strh r3, [r4, #0]
response[3] = (uint8_t)(crc & 0xFF);
800130c: 0029 movs r1, r5
800130e: 187b adds r3, r7, r1
8001310: 881b ldrh r3, [r3, #0]
8001312: b2da uxtb r2, r3
8001314: 4b08 ldr r3, [pc, #32] ; (8001338 <Modbus_SendExceptionResponse+0x68>)
8001316: 70da strb r2, [r3, #3]
response[4] = (uint8_t)((crc >> 8) & 0xFF);
8001318: 187b adds r3, r7, r1
800131a: 881b ldrh r3, [r3, #0]
800131c: 0a1b lsrs r3, r3, #8
800131e: b29b uxth r3, r3
8001320: b2da uxtb r2, r3
8001322: 4b05 ldr r3, [pc, #20] ; (8001338 <Modbus_SendExceptionResponse+0x68>)
8001324: 711a strb r2, [r3, #4]
Modbus_SendResponse(response, 5);
8001326: 4b04 ldr r3, [pc, #16] ; (8001338 <Modbus_SendExceptionResponse+0x68>)
8001328: 2105 movs r1, #5
800132a: 0018 movs r0, r3
800132c: f000 f808 bl 8001340 <Modbus_SendResponse>
}
8001330: 46c0 nop ; (mov r8, r8)
8001332: 46bd mov sp, r7
8001334: b004 add sp, #16
8001336: bdb0 pop {r4, r5, r7, pc}
8001338: 200001c4 .word 0x200001c4
800133c: 200000b8 .word 0x200000b8
08001340 <Modbus_SendResponse>:
/* 发送响应 */
void Modbus_SendResponse(uint8_t *data, uint8_t length)
{
8001340: b580 push {r7, lr}
8001342: b082 sub sp, #8
8001344: af00 add r7, sp, #0
8001346: 6078 str r0, [r7, #4]
8001348: 000a movs r2, r1
800134a: 1cfb adds r3, r7, #3
800134c: 701a strb r2, [r3, #0]
/* 使能RS485发送 */
HAL_GPIO_WritePin(DIR_GPIO_Port, DIR_Pin, GPIO_PIN_SET);
800134e: 23a0 movs r3, #160 ; 0xa0
8001350: 05db lsls r3, r3, #23
8001352: 2201 movs r2, #1
8001354: 2110 movs r1, #16
8001356: 0018 movs r0, r3
8001358: f002 fa58 bl 800380c <HAL_GPIO_WritePin>
/* DMA 发送数据，发送完成后在 HAL_UART_TxCpltCallback 中切回接收 */
HAL_UART_Transmit_DMA(&huart2, data, length);
800135c: 1cfb adds r3, r7, #3
800135e: 781b ldrb r3, [r3, #0]
8001360: b29a uxth r2, r3
8001362: 6879 ldr r1, [r7, #4]
8001364: 4b03 ldr r3, [pc, #12] ; (8001374 <Modbus_SendResponse+0x34>)
8001366: 0018 movs r0, r3
8001368: f004 f8d8 bl 800551c <HAL_UART_Transmit_DMA>
}
800136c: 46c0 nop ; (mov r8, r8)
800136e: 46bd mov sp, r7
8001370: b002 add sp, #8
8001372: bd80 pop {r7, pc}
8001374: 2000035c .word 0x2000035c
08001378 <CalculateCRC>:
/* CRC计算 */
uint16_t CalculateCRC(uint8_t *data, uint8_t length)
{
8001378: b580 push {r7, lr}
800137a: b084 sub sp, #16
800137c: af00 add r7, sp, #0
800137e: 6078 str r0, [r7, #4]
8001380: 000a movs r2, r1
8001382: 1cfb adds r3, r7, #3
8001384: 701a strb r2, [r3, #0]
uint16_t crc = 0xFFFF;
8001386: 230e movs r3, #14
8001388: 18fb adds r3, r7, r3
800138a: 2201 movs r2, #1
800138c: 4252 negs r2, r2
800138e: 801a strh r2, [r3, #0]
for (uint8_t i = 0; i < length; i++)
8001390: 230d movs r3, #13
8001392: 18fb adds r3, r7, r3
8001394: 2200 movs r2, #0
8001396: 701a strb r2, [r3, #0]
8001398: e03a b.n 8001410 <CalculateCRC+0x98>
{
crc ^= (uint16_t)data[i];
800139a: 230d movs r3, #13
800139c: 18fb adds r3, r7, r3
800139e: 781b ldrb r3, [r3, #0]
80013a0: 687a ldr r2, [r7, #4]
80013a2: 18d3 adds r3, r2, r3
80013a4: 781b ldrb r3, [r3, #0]
80013a6: b299 uxth r1, r3
80013a8: 220e movs r2, #14
80013aa: 18bb adds r3, r7, r2
80013ac: 18ba adds r2, r7, r2
80013ae: 8812 ldrh r2, [r2, #0]
80013b0: 404a eors r2, r1
80013b2: 801a strh r2, [r3, #0]
for (uint8_t j = 0; j < 8; j++)
80013b4: 230c movs r3, #12
80013b6: 18fb adds r3, r7, r3
80013b8: 2200 movs r2, #0
80013ba: 701a strb r2, [r3, #0]
80013bc: e01d b.n 80013fa <CalculateCRC+0x82>
{
if ((crc & 0x0001) != 0)
80013be: 210e movs r1, #14
80013c0: 187b adds r3, r7, r1
80013c2: 881b ldrh r3, [r3, #0]
80013c4: 2201 movs r2, #1
80013c6: 4013 ands r3, r2
80013c8: d00b beq.n 80013e2 <CalculateCRC+0x6a>
{
crc >>= 1;
80013ca: 187b adds r3, r7, r1
80013cc: 187a adds r2, r7, r1
80013ce: 8812 ldrh r2, [r2, #0]
80013d0: 0852 lsrs r2, r2, #1
80013d2: 801a strh r2, [r3, #0]
crc ^= 0xA001;
80013d4: 187b adds r3, r7, r1
80013d6: 187a adds r2, r7, r1
80013d8: 8812 ldrh r2, [r2, #0]
80013da: 4914 ldr r1, [pc, #80] ; (800142c <CalculateCRC+0xb4>)
80013dc: 404a eors r2, r1
80013de: 801a strh r2, [r3, #0]
80013e0: e005 b.n 80013ee <CalculateCRC+0x76>
}
else
{
crc >>= 1;
80013e2: 220e movs r2, #14
80013e4: 18bb adds r3, r7, r2
80013e6: 18ba adds r2, r7, r2
80013e8: 8812 ldrh r2, [r2, #0]
80013ea: 0852 lsrs r2, r2, #1
80013ec: 801a strh r2, [r3, #0]
for (uint8_t j = 0; j < 8; j++)
80013ee: 210c movs r1, #12
80013f0: 187b adds r3, r7, r1
80013f2: 781a ldrb r2, [r3, #0]
80013f4: 187b adds r3, r7, r1
80013f6: 3201 adds r2, #1
80013f8: 701a strb r2, [r3, #0]
80013fa: 230c movs r3, #12
80013fc: 18fb adds r3, r7, r3
80013fe: 781b ldrb r3, [r3, #0]
8001400: 2b07 cmp r3, #7
8001402: d9dc bls.n 80013be <CalculateCRC+0x46>
for (uint8_t i = 0; i < length; i++)
8001404: 210d movs r1, #13
8001406: 187b adds r3, r7, r1
8001408: 781a ldrb r2, [r3, #0]
800140a: 187b adds r3, r7, r1
800140c: 3201 adds r2, #1
800140e: 701a strb r2, [r3, #0]
8001410: 230d movs r3, #13
8001412: 18fa adds r2, r7, r3
8001414: 1cfb adds r3, r7, #3
8001416: 7812 ldrb r2, [r2, #0]
8001418: 781b ldrb r3, [r3, #0]
800141a: 429a cmp r2, r3
800141c: d3bd bcc.n 800139a <CalculateCRC+0x22>
}
}
}
return crc;
800141e: 230e movs r3, #14
8001420: 18fb adds r3, r7, r3
8001422: 881b ldrh r3, [r3, #0]
}
8001424: 0018 movs r0, r3
8001426: 46bd mov sp, r7
8001428: b004 add sp, #16
800142a: bd80 pop {r7, pc}
800142c: ffffa001 .word 0xffffa001
08001430 <HAL_UART_RxCpltCallback>:
/* UART接收中断回调函数 */
void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
{
8001430: b580 push {r7, lr}
8001432: b082 sub sp, #8
8001434: af00 add r7, sp, #0
8001436: 6078 str r0, [r7, #4]
if (huart != &huart2)
8001438: 687a ldr r2, [r7, #4]
800143a: 4b19 ldr r3, [pc, #100] ; (80014a0 <HAL_UART_RxCpltCallback+0x70>)
800143c: 429a cmp r2, r3
800143e: d12b bne.n 8001498 <HAL_UART_RxCpltCallback+0x68>
{
return;
}
lastByteTime = HAL_GetTick();
8001440: f000 fb90 bl 8001b64 <HAL_GetTick>
8001444: 0002 movs r2, r0
8001446: 4b17 ldr r3, [pc, #92] ; (80014a4 <HAL_UART_RxCpltCallback+0x74>)
8001448: 601a str r2, [r3, #0]
if (modbusBufferIndex < MODBUS_BUFFER_SIZE)
800144a: 4b17 ldr r3, [pc, #92] ; (80014a8 <HAL_UART_RxCpltCallback+0x78>)
800144c: 881b ldrh r3, [r3, #0]
800144e: 2bff cmp r3, #255 ; 0xff
8001450: d805 bhi.n 800145e <HAL_UART_RxCpltCallback+0x2e>
{
/* HAL 已经将接收到的字节写入 modbusBuffer[modbusBufferIndex]，
此处只需向后移动索引。 */
modbusBufferIndex++;
8001452: 4b15 ldr r3, [pc, #84] ; (80014a8 <HAL_UART_RxCpltCallback+0x78>)
8001454: 881b ldrh r3, [r3, #0]
8001456: 3301 adds r3, #1
8001458: b29a uxth r2, r3
800145a: 4b13 ldr r3, [pc, #76] ; (80014a8 <HAL_UART_RxCpltCallback+0x78>)
800145c: 801a strh r2, [r3, #0]
}
if (modbusBufferIndex < MODBUS_BUFFER_SIZE)
800145e: 4b12 ldr r3, [pc, #72] ; (80014a8 <HAL_UART_RxCpltCallback+0x78>)
8001460: 881b ldrh r3, [r3, #0]
8001462: 2bff cmp r3, #255 ; 0xff
8001464: d80a bhi.n 800147c <HAL_UART_RxCpltCallback+0x4c>
{
HAL_UART_Receive_IT(&huart2, (uint8_t *)&modbusBuffer[modbusBufferIndex], 1);
8001466: 4b10 ldr r3, [pc, #64] ; (80014a8 <HAL_UART_RxCpltCallback+0x78>)
8001468: 881b ldrh r3, [r3, #0]
800146a: 001a movs r2, r3
800146c: 4b0f ldr r3, [pc, #60] ; (80014ac <HAL_UART_RxCpltCallback+0x7c>)
800146e: 18d1 adds r1, r2, r3
8001470: 4b0b ldr r3, [pc, #44] ; (80014a0 <HAL_UART_RxCpltCallback+0x70>)
8001472: 2201 movs r2, #1
8001474: 0018 movs r0, r3
8001476: f003 ffe7 bl 8005448 <HAL_UART_Receive_IT>
800147a: e00e b.n 800149a <HAL_UART_RxCpltCallback+0x6a>
}
else
{
/* 缓冲区满，丢弃并等待下一帧 */
modbusBufferIndex = 0;
800147c: 4b0a ldr r3, [pc, #40] ; (80014a8 <HAL_UART_RxCpltCallback+0x78>)
800147e: 2200 movs r2, #0
8001480: 801a strh r2, [r3, #0]
HAL_UART_Receive_IT(&huart2, (uint8_t *)&modbusBuffer[modbusBufferIndex], 1);
8001482: 4b09 ldr r3, [pc, #36] ; (80014a8 <HAL_UART_RxCpltCallback+0x78>)
8001484: 881b ldrh r3, [r3, #0]
8001486: 001a movs r2, r3
8001488: 4b08 ldr r3, [pc, #32] ; (80014ac <HAL_UART_RxCpltCallback+0x7c>)
800148a: 18d1 adds r1, r2, r3
800148c: 4b04 ldr r3, [pc, #16] ; (80014a0 <HAL_UART_RxCpltCallback+0x70>)
800148e: 2201 movs r2, #1
8001490: 0018 movs r0, r3
8001492: f003 ffd9 bl 8005448 <HAL_UART_Receive_IT>
8001496: e000 b.n 800149a <HAL_UART_RxCpltCallback+0x6a>
return;
8001498: 46c0 nop ; (mov r8, r8)
}
}
800149a: 46bd mov sp, r7
800149c: b002 add sp, #8
800149e: bd80 pop {r7, pc}
80014a0: 2000035c .word 0x2000035c
80014a4: 200001bc .word 0x200001bc
80014a8: 200001b8 .word 0x200001b8
80014ac: 200000b8 .word 0x200000b8
080014b0 <HAL_UART_TxCpltCallback>:
/* UART发送完成回调：切回RS485接收方向 */
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
{
80014b0: b580 push {r7, lr}
80014b2: b082 sub sp, #8
80014b4: af00 add r7, sp, #0
80014b6: 6078 str r0, [r7, #4]
if (huart == &huart2)
80014b8: 687a ldr r2, [r7, #4]
80014ba: 4b07 ldr r3, [pc, #28] ; (80014d8 <HAL_UART_TxCpltCallback+0x28>)
80014bc: 429a cmp r2, r3
80014be: d106 bne.n 80014ce <HAL_UART_TxCpltCallback+0x1e>
{
HAL_GPIO_WritePin(DIR_GPIO_Port, DIR_Pin, GPIO_PIN_RESET);
80014c0: 23a0 movs r3, #160 ; 0xa0
80014c2: 05db lsls r3, r3, #23
80014c4: 2200 movs r2, #0
80014c6: 2110 movs r1, #16
80014c8: 0018 movs r0, r3
80014ca: f002 f99f bl 800380c <HAL_GPIO_WritePin>
}
}
80014ce: 46c0 nop ; (mov r8, r8)
80014d0: 46bd mov sp, r7
80014d2: b002 add sp, #8
80014d4: bd80 pop {r7, pc}
80014d6: 46c0 nop ; (mov r8, r8)
80014d8: 2000035c .word 0x2000035c
080014dc <HAL_UART_ErrorCallback>:
/* UART错误回调：重新同步接收 */
void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
{
80014dc: b580 push {r7, lr}
80014de: b082 sub sp, #8
80014e0: af00 add r7, sp, #0
80014e2: 6078 str r0, [r7, #4]
if (huart == &huart2)
80014e4: 687a ldr r2, [r7, #4]
80014e6: 4b0a ldr r3, [pc, #40] ; (8001510 <HAL_UART_ErrorCallback+0x34>)
80014e8: 429a cmp r2, r3
80014ea: d10c bne.n 8001506 <HAL_UART_ErrorCallback+0x2a>
{
modbusBufferIndex = 0;
80014ec: 4b09 ldr r3, [pc, #36] ; (8001514 <HAL_UART_ErrorCallback+0x38>)
80014ee: 2200 movs r2, #0
80014f0: 801a strh r2, [r3, #0]
HAL_UART_Receive_IT(&huart2, (uint8_t *)&modbusBuffer[modbusBufferIndex], 1);
80014f2: 4b08 ldr r3, [pc, #32] ; (8001514 <HAL_UART_ErrorCallback+0x38>)
80014f4: 881b ldrh r3, [r3, #0]
80014f6: 001a movs r2, r3
80014f8: 4b07 ldr r3, [pc, #28] ; (8001518 <HAL_UART_ErrorCallback+0x3c>)
80014fa: 18d1 adds r1, r2, r3
80014fc: 4b04 ldr r3, [pc, #16] ; (8001510 <HAL_UART_ErrorCallback+0x34>)
80014fe: 2201 movs r2, #1
8001500: 0018 movs r0, r3
8001502: f003 ffa1 bl 8005448 <HAL_UART_Receive_IT>
}
}
8001506: 46c0 nop ; (mov r8, r8)
8001508: 46bd mov sp, r7
800150a: b002 add sp, #8
800150c: bd80 pop {r7, pc}
800150e: 46c0 nop ; (mov r8, r8)
8001510: 2000035c .word 0x2000035c
8001514: 200001b8 .word 0x200001b8
8001518: 200000b8 .word 0x200000b8
0800151c <HAL_MspInit>:
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
800151c: b580 push {r7, lr}
800151e: b082 sub sp, #8
8001520: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8001522: 4b0f ldr r3, [pc, #60] ; (8001560 <HAL_MspInit+0x44>)
8001524: 6c1a ldr r2, [r3, #64] ; 0x40
8001526: 4b0e ldr r3, [pc, #56] ; (8001560 <HAL_MspInit+0x44>)
8001528: 2101 movs r1, #1
800152a: 430a orrs r2, r1
800152c: 641a str r2, [r3, #64] ; 0x40
800152e: 4b0c ldr r3, [pc, #48] ; (8001560 <HAL_MspInit+0x44>)
8001530: 6c1b ldr r3, [r3, #64] ; 0x40
8001532: 2201 movs r2, #1
8001534: 4013 ands r3, r2
8001536: 607b str r3, [r7, #4]
8001538: 687b ldr r3, [r7, #4]
__HAL_RCC_PWR_CLK_ENABLE();
800153a: 4b09 ldr r3, [pc, #36] ; (8001560 <HAL_MspInit+0x44>)
800153c: 6bda ldr r2, [r3, #60] ; 0x3c
800153e: 4b08 ldr r3, [pc, #32] ; (8001560 <HAL_MspInit+0x44>)
8001540: 2180 movs r1, #128 ; 0x80
8001542: 0549 lsls r1, r1, #21
8001544: 430a orrs r2, r1
8001546: 63da str r2, [r3, #60] ; 0x3c
8001548: 4b05 ldr r3, [pc, #20] ; (8001560 <HAL_MspInit+0x44>)
800154a: 6bda ldr r2, [r3, #60] ; 0x3c
800154c: 2380 movs r3, #128 ; 0x80
800154e: 055b lsls r3, r3, #21
8001550: 4013 ands r3, r2
8001552: 603b str r3, [r7, #0]
8001554: 683b ldr r3, [r7, #0]
/* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
8001556: 46c0 nop ; (mov r8, r8)
8001558: 46bd mov sp, r7
800155a: b002 add sp, #8
800155c: bd80 pop {r7, pc}
800155e: 46c0 nop ; (mov r8, r8)
8001560: 40021000 .word 0x40021000
08001564 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
8001564: b580 push {r7, lr}
8001566: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
8001568: e7fe b.n 8001568 <NMI_Handler+0x4>
0800156a <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
800156a: b580 push {r7, lr}
800156c: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
800156e: e7fe b.n 800156e <HardFault_Handler+0x4>
08001570 <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
8001570: b580 push {r7, lr}
8001572: af00 add r7, sp, #0
/* USER CODE END SVC_IRQn 0 */
/* USER CODE BEGIN SVC_IRQn 1 */
/* USER CODE END SVC_IRQn 1 */
}
8001574: 46c0 nop ; (mov r8, r8)
8001576: 46bd mov sp, r7
8001578: bd80 pop {r7, pc}
0800157a <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
800157a: b580 push {r7, lr}
800157c: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
800157e: 46c0 nop ; (mov r8, r8)
8001580: 46bd mov sp, r7
8001582: bd80 pop {r7, pc}
08001584 <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
8001584: b580 push {r7, lr}
8001586: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
8001588: f000 fada bl 8001b40 <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
800158c: 46c0 nop ; (mov r8, r8)
800158e: 46bd mov sp, r7
8001590: bd80 pop {r7, pc}
...
08001594 <DMA1_Channel1_IRQHandler>:
/**
* @brief This function handles DMA1 channel 1 interrupt.
*/
void DMA1_Channel1_IRQHandler(void)
{
8001594: b580 push {r7, lr}
8001596: af00 add r7, sp, #0
/* USER CODE BEGIN DMA1_Channel1_IRQn 0 */
/* USER CODE END DMA1_Channel1_IRQn 0 */
HAL_DMA_IRQHandler(&hdma_usart2_tx);
8001598: 4b03 ldr r3, [pc, #12] ; (80015a8 <DMA1_Channel1_IRQHandler+0x14>)
800159a: 0018 movs r0, r3
800159c: f001 fe90 bl 80032c0 <HAL_DMA_IRQHandler>
/* USER CODE BEGIN DMA1_Channel1_IRQn 1 */
/* USER CODE END DMA1_Channel1_IRQn 1 */
}
80015a0: 46c0 nop ; (mov r8, r8)
80015a2: 46bd mov sp, r7
80015a4: bd80 pop {r7, pc}
80015a6: 46c0 nop ; (mov r8, r8)
80015a8: 200003ec .word 0x200003ec
080015ac <ADC1_IRQHandler>:
/**
* @brief This function handles ADC1 interrupt.
*/
void ADC1_IRQHandler(void)
{
80015ac: b580 push {r7, lr}
80015ae: af00 add r7, sp, #0
/* USER CODE BEGIN ADC1_IRQn 0 */
/* USER CODE END ADC1_IRQn 0 */
HAL_ADC_IRQHandler(&hadc1);
80015b0: 4b03 ldr r3, [pc, #12] ; (80015c0 <ADC1_IRQHandler+0x14>)
80015b2: 0018 movs r0, r3
80015b4: f000 fe70 bl 8002298 <HAL_ADC_IRQHandler>
/* USER CODE BEGIN ADC1_IRQn 1 */
/* USER CODE END ADC1_IRQn 1 */
}
80015b8: 46c0 nop ; (mov r8, r8)
80015ba: 46bd mov sp, r7
80015bc: bd80 pop {r7, pc}
80015be: 46c0 nop ; (mov r8, r8)
80015c0: 20000034 .word 0x20000034
080015c4 <USART2_IRQHandler>:
/**
* @brief This function handles USART2 global interrupt / USART2 wake-up interrupt through EXTI line 26.
*/
void USART2_IRQHandler(void)
{
80015c4: b580 push {r7, lr}
80015c6: af00 add r7, sp, #0
/* USER CODE BEGIN USART2_IRQn 0 */
/* USER CODE END USART2_IRQn 0 */
HAL_UART_IRQHandler(&huart2);
80015c8: 4b03 ldr r3, [pc, #12] ; (80015d8 <USART2_IRQHandler+0x14>)
80015ca: 0018 movs r0, r3
80015cc: f004 f84c bl 8005668 <HAL_UART_IRQHandler>
/* USER CODE BEGIN USART2_IRQn 1 */
/* USER CODE END USART2_IRQn 1 */
}
80015d0: 46c0 nop ; (mov r8, r8)
80015d2: 46bd mov sp, r7
80015d4: bd80 pop {r7, pc}
80015d6: 46c0 nop ; (mov r8, r8)
80015d8: 2000035c .word 0x2000035c
080015dc <SystemInit>:
* @brief Setup the microcontroller system.
* @param None
* @retval None
*/
void SystemInit(void)
{
80015dc: b580 push {r7, lr}
80015de: af00 add r7, sp, #0
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation */
#endif /* USER_VECT_TAB_ADDRESS */
}
80015e0: 46c0 nop ; (mov r8, r8)
80015e2: 46bd mov sp, r7
80015e4: bd80 pop {r7, pc}
...
080015e8 <MX_TIM2_Init>:
TIM_HandleTypeDef htim2;
TIM_HandleTypeDef htim3;
/* TIM2 init function */
void MX_TIM2_Init(void)
{
80015e8: b590 push {r4, r7, lr}
80015ea: b08d sub sp, #52 ; 0x34
80015ec: af00 add r7, sp, #0
/* USER CODE BEGIN TIM2_Init 0 */
/* USER CODE END TIM2_Init 0 */
TIM_Encoder_InitTypeDef sConfig = {0};
80015ee: 240c movs r4, #12
80015f0: 193b adds r3, r7, r4
80015f2: 0018 movs r0, r3
80015f4: 2324 movs r3, #36 ; 0x24
80015f6: 001a movs r2, r3
80015f8: 2100 movs r1, #0
80015fa: f005 fee1 bl 80073c0 <memset>
TIM_MasterConfigTypeDef sMasterConfig = {0};
80015fe: 003b movs r3, r7
8001600: 0018 movs r0, r3
8001602: 230c movs r3, #12
8001604: 001a movs r2, r3
8001606: 2100 movs r1, #0
8001608: f005 feda bl 80073c0 <memset>
/* USER CODE BEGIN TIM2_Init 1 */
/* USER CODE END TIM2_Init 1 */
htim2.Instance = TIM2;
800160c: 4b26 ldr r3, [pc, #152] ; (80016a8 <MX_TIM2_Init+0xc0>)
800160e: 2280 movs r2, #128 ; 0x80
8001610: 05d2 lsls r2, r2, #23
8001612: 601a str r2, [r3, #0]
htim2.Init.Prescaler = 0;
8001614: 4b24 ldr r3, [pc, #144] ; (80016a8 <MX_TIM2_Init+0xc0>)
8001616: 2200 movs r2, #0
8001618: 605a str r2, [r3, #4]
htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
800161a: 4b23 ldr r3, [pc, #140] ; (80016a8 <MX_TIM2_Init+0xc0>)
800161c: 2200 movs r2, #0
800161e: 609a str r2, [r3, #8]
htim2.Init.Period = 4294967295;
8001620: 4b21 ldr r3, [pc, #132] ; (80016a8 <MX_TIM2_Init+0xc0>)
8001622: 2201 movs r2, #1
8001624: 4252 negs r2, r2
8001626: 60da str r2, [r3, #12]
htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
8001628: 4b1f ldr r3, [pc, #124] ; (80016a8 <MX_TIM2_Init+0xc0>)
800162a: 2200 movs r2, #0
800162c: 611a str r2, [r3, #16]
htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
800162e: 4b1e ldr r3, [pc, #120] ; (80016a8 <MX_TIM2_Init+0xc0>)
8001630: 2200 movs r2, #0
8001632: 619a str r2, [r3, #24]
sConfig.EncoderMode = TIM_ENCODERMODE_TI12;
8001634: 0021 movs r1, r4
8001636: 187b adds r3, r7, r1
8001638: 2203 movs r2, #3
800163a: 601a str r2, [r3, #0]
sConfig.IC1Polarity = TIM_ICPOLARITY_RISING;
800163c: 187b adds r3, r7, r1
800163e: 2200 movs r2, #0
8001640: 605a str r2, [r3, #4]
sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI;
8001642: 187b adds r3, r7, r1
8001644: 2201 movs r2, #1
8001646: 609a str r2, [r3, #8]
sConfig.IC1Prescaler = TIM_ICPSC_DIV1;
8001648: 187b adds r3, r7, r1
800164a: 2200 movs r2, #0
800164c: 60da str r2, [r3, #12]
sConfig.IC1Filter = 5;
800164e: 187b adds r3, r7, r1
8001650: 2205 movs r2, #5
8001652: 611a str r2, [r3, #16]
sConfig.IC2Polarity = TIM_ICPOLARITY_RISING;
8001654: 187b adds r3, r7, r1
8001656: 2200 movs r2, #0
8001658: 615a str r2, [r3, #20]
sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI;
800165a: 187b adds r3, r7, r1
800165c: 2201 movs r2, #1
800165e: 619a str r2, [r3, #24]
sConfig.IC2Prescaler = TIM_ICPSC_DIV1;
8001660: 187b adds r3, r7, r1
8001662: 2200 movs r2, #0
8001664: 61da str r2, [r3, #28]
sConfig.IC2Filter = 5;
8001666: 187b adds r3, r7, r1
8001668: 2205 movs r2, #5
800166a: 621a str r2, [r3, #32]
if (HAL_TIM_Encoder_Init(&htim2, &sConfig) != HAL_OK)
800166c: 187a adds r2, r7, r1
800166e: 4b0e ldr r3, [pc, #56] ; (80016a8 <MX_TIM2_Init+0xc0>)
8001670: 0011 movs r1, r2
8001672: 0018 movs r0, r3
8001674: f003 f8a8 bl 80047c8 <HAL_TIM_Encoder_Init>
8001678: 1e03 subs r3, r0, #0
800167a: d001 beq.n 8001680 <MX_TIM2_Init+0x98>
{
Error_Handler();
800167c: f7ff fab3 bl 8000be6 <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
8001680: 003b movs r3, r7
8001682: 2200 movs r2, #0
8001684: 601a str r2, [r3, #0]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
8001686: 003b movs r3, r7
8001688: 2200 movs r2, #0
800168a: 609a str r2, [r3, #8]
if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
800168c: 003a movs r2, r7
800168e: 4b06 ldr r3, [pc, #24] ; (80016a8 <MX_TIM2_Init+0xc0>)
8001690: 0011 movs r1, r2
8001692: 0018 movs r0, r3
8001694: f003 fe1a bl 80052cc <HAL_TIMEx_MasterConfigSynchronization>
8001698: 1e03 subs r3, r0, #0
800169a: d001 beq.n 80016a0 <MX_TIM2_Init+0xb8>
{
Error_Handler();
800169c: f7ff faa3 bl 8000be6 <Error_Handler>
}
/* USER CODE BEGIN TIM2_Init 2 */
/* USER CODE END TIM2_Init 2 */
}
80016a0: 46c0 nop ; (mov r8, r8)
80016a2: 46bd mov sp, r7
80016a4: b00d add sp, #52 ; 0x34
80016a6: bd90 pop {r4, r7, pc}
80016a8: 200002c4 .word 0x200002c4
080016ac <MX_TIM3_Init>:
/* TIM3 init function */
void MX_TIM3_Init(void)
{
80016ac: b580 push {r7, lr}
80016ae: b08a sub sp, #40 ; 0x28
80016b0: af00 add r7, sp, #0
/* USER CODE BEGIN TIM3_Init 0 */
/* USER CODE END TIM3_Init 0 */
TIM_MasterConfigTypeDef sMasterConfig = {0};
80016b2: 231c movs r3, #28
80016b4: 18fb adds r3, r7, r3
80016b6: 0018 movs r0, r3
80016b8: 230c movs r3, #12
80016ba: 001a movs r2, r3
80016bc: 2100 movs r1, #0
80016be: f005 fe7f bl 80073c0 <memset>
TIM_OC_InitTypeDef sConfigOC = {0};
80016c2: 003b movs r3, r7
80016c4: 0018 movs r0, r3
80016c6: 231c movs r3, #28
80016c8: 001a movs r2, r3
80016ca: 2100 movs r1, #0
80016cc: f005 fe78 bl 80073c0 <memset>
/* USER CODE BEGIN TIM3_Init 1 */
/* USER CODE END TIM3_Init 1 */
htim3.Instance = TIM3;
80016d0: 4b24 ldr r3, [pc, #144] ; (8001764 <MX_TIM3_Init+0xb8>)
80016d2: 4a25 ldr r2, [pc, #148] ; (8001768 <MX_TIM3_Init+0xbc>)
80016d4: 601a str r2, [r3, #0]
htim3.Init.Prescaler = 0;
80016d6: 4b23 ldr r3, [pc, #140] ; (8001764 <MX_TIM3_Init+0xb8>)
80016d8: 2200 movs r2, #0
80016da: 605a str r2, [r3, #4]
htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
80016dc: 4b21 ldr r3, [pc, #132] ; (8001764 <MX_TIM3_Init+0xb8>)
80016de: 2200 movs r2, #0
80016e0: 609a str r2, [r3, #8]
htim3.Init.Period = 100;
80016e2: 4b20 ldr r3, [pc, #128] ; (8001764 <MX_TIM3_Init+0xb8>)
80016e4: 2264 movs r2, #100 ; 0x64
80016e6: 60da str r2, [r3, #12]
htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
80016e8: 4b1e ldr r3, [pc, #120] ; (8001764 <MX_TIM3_Init+0xb8>)
80016ea: 2200 movs r2, #0
80016ec: 611a str r2, [r3, #16]
htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE;
80016ee: 4b1d ldr r3, [pc, #116] ; (8001764 <MX_TIM3_Init+0xb8>)
80016f0: 2280 movs r2, #128 ; 0x80
80016f2: 619a str r2, [r3, #24]
if (HAL_TIM_PWM_Init(&htim3) != HAL_OK)
80016f4: 4b1b ldr r3, [pc, #108] ; (8001764 <MX_TIM3_Init+0xb8>)
80016f6: 0018 movs r0, r3
80016f8: f002 ff30 bl 800455c <HAL_TIM_PWM_Init>
80016fc: 1e03 subs r3, r0, #0
80016fe: d001 beq.n 8001704 <MX_TIM3_Init+0x58>
{
Error_Handler();
8001700: f7ff fa71 bl 8000be6 <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
8001704: 211c movs r1, #28
8001706: 187b adds r3, r7, r1
8001708: 2200 movs r2, #0
800170a: 601a str r2, [r3, #0]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
800170c: 187b adds r3, r7, r1
800170e: 2200 movs r2, #0
8001710: 609a str r2, [r3, #8]
if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
8001712: 187a adds r2, r7, r1
8001714: 4b13 ldr r3, [pc, #76] ; (8001764 <MX_TIM3_Init+0xb8>)
8001716: 0011 movs r1, r2
8001718: 0018 movs r0, r3
800171a: f003 fdd7 bl 80052cc <HAL_TIMEx_MasterConfigSynchronization>
800171e: 1e03 subs r3, r0, #0
8001720: d001 beq.n 8001726 <MX_TIM3_Init+0x7a>
{
Error_Handler();
8001722: f7ff fa60 bl 8000be6 <Error_Handler>
}
sConfigOC.OCMode = TIM_OCMODE_PWM1;
8001726: 003b movs r3, r7
8001728: 2260 movs r2, #96 ; 0x60
800172a: 601a str r2, [r3, #0]
sConfigOC.Pulse = 80;
800172c: 003b movs r3, r7
800172e: 2250 movs r2, #80 ; 0x50
8001730: 605a str r2, [r3, #4]
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
8001732: 003b movs r3, r7
8001734: 2200 movs r2, #0
8001736: 609a str r2, [r3, #8]
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
8001738: 003b movs r3, r7
800173a: 2200 movs r2, #0
800173c: 611a str r2, [r3, #16]
if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
800173e: 0039 movs r1, r7
8001740: 4b08 ldr r3, [pc, #32] ; (8001764 <MX_TIM3_Init+0xb8>)
8001742: 2200 movs r2, #0
8001744: 0018 movs r0, r3
8001746: f003 f98b bl 8004a60 <HAL_TIM_PWM_ConfigChannel>
800174a: 1e03 subs r3, r0, #0
800174c: d001 beq.n 8001752 <MX_TIM3_Init+0xa6>
{
Error_Handler();
800174e: f7ff fa4a bl 8000be6 <Error_Handler>
}
/* USER CODE BEGIN TIM3_Init 2 */
/* USER CODE END TIM3_Init 2 */
HAL_TIM_MspPostInit(&htim3);
8001752: 4b04 ldr r3, [pc, #16] ; (8001764 <MX_TIM3_Init+0xb8>)
8001754: 0018 movs r0, r3
8001756: f000 f86f bl 8001838 <HAL_TIM_MspPostInit>
}
800175a: 46c0 nop ; (mov r8, r8)
800175c: 46bd mov sp, r7
800175e: b00a add sp, #40 ; 0x28
8001760: bd80 pop {r7, pc}
8001762: 46c0 nop ; (mov r8, r8)
8001764: 20000310 .word 0x20000310
8001768: 40000400 .word 0x40000400
0800176c <HAL_TIM_Encoder_MspInit>:
void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef* tim_encoderHandle)
{
800176c: b590 push {r4, r7, lr}
800176e: b08b sub sp, #44 ; 0x2c
8001770: af00 add r7, sp, #0
8001772: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001774: 2414 movs r4, #20
8001776: 193b adds r3, r7, r4
8001778: 0018 movs r0, r3
800177a: 2314 movs r3, #20
800177c: 001a movs r2, r3
800177e: 2100 movs r1, #0
8001780: f005 fe1e bl 80073c0 <memset>
if(tim_encoderHandle->Instance==TIM2)
8001784: 687b ldr r3, [r7, #4]
8001786: 681a ldr r2, [r3, #0]
8001788: 2380 movs r3, #128 ; 0x80
800178a: 05db lsls r3, r3, #23
800178c: 429a cmp r2, r3
800178e: d12e bne.n 80017ee <HAL_TIM_Encoder_MspInit+0x82>
{
/* USER CODE BEGIN TIM2_MspInit 0 */
/* USER CODE END TIM2_MspInit 0 */
/* TIM2 clock enable */
__HAL_RCC_TIM2_CLK_ENABLE();
8001790: 4b19 ldr r3, [pc, #100] ; (80017f8 <HAL_TIM_Encoder_MspInit+0x8c>)
8001792: 6bda ldr r2, [r3, #60] ; 0x3c
8001794: 4b18 ldr r3, [pc, #96] ; (80017f8 <HAL_TIM_Encoder_MspInit+0x8c>)
8001796: 2101 movs r1, #1
8001798: 430a orrs r2, r1
800179a: 63da str r2, [r3, #60] ; 0x3c
800179c: 4b16 ldr r3, [pc, #88] ; (80017f8 <HAL_TIM_Encoder_MspInit+0x8c>)
800179e: 6bdb ldr r3, [r3, #60] ; 0x3c
80017a0: 2201 movs r2, #1
80017a2: 4013 ands r3, r2
80017a4: 613b str r3, [r7, #16]
80017a6: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
80017a8: 4b13 ldr r3, [pc, #76] ; (80017f8 <HAL_TIM_Encoder_MspInit+0x8c>)
80017aa: 6b5a ldr r2, [r3, #52] ; 0x34
80017ac: 4b12 ldr r3, [pc, #72] ; (80017f8 <HAL_TIM_Encoder_MspInit+0x8c>)
80017ae: 2101 movs r1, #1
80017b0: 430a orrs r2, r1
80017b2: 635a str r2, [r3, #52] ; 0x34
80017b4: 4b10 ldr r3, [pc, #64] ; (80017f8 <HAL_TIM_Encoder_MspInit+0x8c>)
80017b6: 6b5b ldr r3, [r3, #52] ; 0x34
80017b8: 2201 movs r2, #1
80017ba: 4013 ands r3, r2
80017bc: 60fb str r3, [r7, #12]
80017be: 68fb ldr r3, [r7, #12]
/**TIM2 GPIO Configuration
PA0 ------> TIM2_CH1
PA1 ------> TIM2_CH2
*/
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1;
80017c0: 0021 movs r1, r4
80017c2: 187b adds r3, r7, r1
80017c4: 2203 movs r2, #3
80017c6: 601a str r2, [r3, #0]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80017c8: 187b adds r3, r7, r1
80017ca: 2202 movs r2, #2
80017cc: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80017ce: 187b adds r3, r7, r1
80017d0: 2200 movs r2, #0
80017d2: 609a str r2, [r3, #8]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80017d4: 187b adds r3, r7, r1
80017d6: 2200 movs r2, #0
80017d8: 60da str r2, [r3, #12]
GPIO_InitStruct.Alternate = GPIO_AF2_TIM2;
80017da: 187b adds r3, r7, r1
80017dc: 2202 movs r2, #2
80017de: 611a str r2, [r3, #16]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
80017e0: 187a adds r2, r7, r1
80017e2: 23a0 movs r3, #160 ; 0xa0
80017e4: 05db lsls r3, r3, #23
80017e6: 0011 movs r1, r2
80017e8: 0018 movs r0, r3
80017ea: f001 feab bl 8003544 <HAL_GPIO_Init>
/* USER CODE BEGIN TIM2_MspInit 1 */
/* USER CODE END TIM2_MspInit 1 */
}
}
80017ee: 46c0 nop ; (mov r8, r8)
80017f0: 46bd mov sp, r7
80017f2: b00b add sp, #44 ; 0x2c
80017f4: bd90 pop {r4, r7, pc}
80017f6: 46c0 nop ; (mov r8, r8)
80017f8: 40021000 .word 0x40021000
080017fc <HAL_TIM_PWM_MspInit>:
void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* tim_pwmHandle)
{
80017fc: b580 push {r7, lr}
80017fe: b084 sub sp, #16
8001800: af00 add r7, sp, #0
8001802: 6078 str r0, [r7, #4]
if(tim_pwmHandle->Instance==TIM3)
8001804: 687b ldr r3, [r7, #4]
8001806: 681b ldr r3, [r3, #0]
8001808: 4a09 ldr r2, [pc, #36] ; (8001830 <HAL_TIM_PWM_MspInit+0x34>)
800180a: 4293 cmp r3, r2
800180c: d10b bne.n 8001826 <HAL_TIM_PWM_MspInit+0x2a>
{
/* USER CODE BEGIN TIM3_MspInit 0 */
/* USER CODE END TIM3_MspInit 0 */
/* TIM3 clock enable */
__HAL_RCC_TIM3_CLK_ENABLE();
800180e: 4b09 ldr r3, [pc, #36] ; (8001834 <HAL_TIM_PWM_MspInit+0x38>)
8001810: 6bda ldr r2, [r3, #60] ; 0x3c
8001812: 4b08 ldr r3, [pc, #32] ; (8001834 <HAL_TIM_PWM_MspInit+0x38>)
8001814: 2102 movs r1, #2
8001816: 430a orrs r2, r1
8001818: 63da str r2, [r3, #60] ; 0x3c
800181a: 4b06 ldr r3, [pc, #24] ; (8001834 <HAL_TIM_PWM_MspInit+0x38>)
800181c: 6bdb ldr r3, [r3, #60] ; 0x3c
800181e: 2202 movs r2, #2
8001820: 4013 ands r3, r2
8001822: 60fb str r3, [r7, #12]
8001824: 68fb ldr r3, [r7, #12]
/* USER CODE BEGIN TIM3_MspInit 1 */
/* USER CODE END TIM3_MspInit 1 */
}
}
8001826: 46c0 nop ; (mov r8, r8)
8001828: 46bd mov sp, r7
800182a: b004 add sp, #16
800182c: bd80 pop {r7, pc}
800182e: 46c0 nop ; (mov r8, r8)
8001830: 40000400 .word 0x40000400
8001834: 40021000 .word 0x40021000
08001838 <HAL_TIM_MspPostInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* timHandle)
{
8001838: b590 push {r4, r7, lr}
800183a: b089 sub sp, #36 ; 0x24
800183c: af00 add r7, sp, #0
800183e: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001840: 240c movs r4, #12
8001842: 193b adds r3, r7, r4
8001844: 0018 movs r0, r3
8001846: 2314 movs r3, #20
8001848: 001a movs r2, r3
800184a: 2100 movs r1, #0
800184c: f005 fdb8 bl 80073c0 <memset>
if(timHandle->Instance==TIM3)
8001850: 687b ldr r3, [r7, #4]
8001852: 681b ldr r3, [r3, #0]
8001854: 4a14 ldr r2, [pc, #80] ; (80018a8 <HAL_TIM_MspPostInit+0x70>)
8001856: 4293 cmp r3, r2
8001858: d122 bne.n 80018a0 <HAL_TIM_MspPostInit+0x68>
{
/* USER CODE BEGIN TIM3_MspPostInit 0 */
/* USER CODE END TIM3_MspPostInit 0 */
__HAL_RCC_GPIOA_CLK_ENABLE();
800185a: 4b14 ldr r3, [pc, #80] ; (80018ac <HAL_TIM_MspPostInit+0x74>)
800185c: 6b5a ldr r2, [r3, #52] ; 0x34
800185e: 4b13 ldr r3, [pc, #76] ; (80018ac <HAL_TIM_MspPostInit+0x74>)
8001860: 2101 movs r1, #1
8001862: 430a orrs r2, r1
8001864: 635a str r2, [r3, #52] ; 0x34
8001866: 4b11 ldr r3, [pc, #68] ; (80018ac <HAL_TIM_MspPostInit+0x74>)
8001868: 6b5b ldr r3, [r3, #52] ; 0x34
800186a: 2201 movs r2, #1
800186c: 4013 ands r3, r2
800186e: 60bb str r3, [r7, #8]
8001870: 68bb ldr r3, [r7, #8]
/**TIM3 GPIO Configuration
PA6 ------> TIM3_CH1
*/
GPIO_InitStruct.Pin = GPIO_PIN_6;
8001872: 0021 movs r1, r4
8001874: 187b adds r3, r7, r1
8001876: 2240 movs r2, #64 ; 0x40
8001878: 601a str r2, [r3, #0]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800187a: 187b adds r3, r7, r1
800187c: 2202 movs r2, #2
800187e: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001880: 187b adds r3, r7, r1
8001882: 2200 movs r2, #0
8001884: 609a str r2, [r3, #8]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001886: 187b adds r3, r7, r1
8001888: 2200 movs r2, #0
800188a: 60da str r2, [r3, #12]
GPIO_InitStruct.Alternate = GPIO_AF1_TIM3;
800188c: 187b adds r3, r7, r1
800188e: 2201 movs r2, #1
8001890: 611a str r2, [r3, #16]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8001892: 187a adds r2, r7, r1
8001894: 23a0 movs r3, #160 ; 0xa0
8001896: 05db lsls r3, r3, #23
8001898: 0011 movs r1, r2
800189a: 0018 movs r0, r3
800189c: f001 fe52 bl 8003544 <HAL_GPIO_Init>
/* USER CODE BEGIN TIM3_MspPostInit 1 */
/* USER CODE END TIM3_MspPostInit 1 */
}
}
80018a0: 46c0 nop ; (mov r8, r8)
80018a2: 46bd mov sp, r7
80018a4: b009 add sp, #36 ; 0x24
80018a6: bd90 pop {r4, r7, pc}
80018a8: 40000400 .word 0x40000400
80018ac: 40021000 .word 0x40021000
080018b0 <MX_USART2_UART_Init>:
DMA_HandleTypeDef hdma_usart2_tx;
/* USART2 init function */
void MX_USART2_UART_Init(void)
{
80018b0: b580 push {r7, lr}
80018b2: af00 add r7, sp, #0
/* USER CODE END USART2_Init 0 */
/* USER CODE BEGIN USART2_Init 1 */
/* USER CODE END USART2_Init 1 */
huart2.Instance = USART2;
80018b4: 4b16 ldr r3, [pc, #88] ; (8001910 <MX_USART2_UART_Init+0x60>)
80018b6: 4a17 ldr r2, [pc, #92] ; (8001914 <MX_USART2_UART_Init+0x64>)
80018b8: 601a str r2, [r3, #0]
huart2.Init.BaudRate = 115200;
80018ba: 4b15 ldr r3, [pc, #84] ; (8001910 <MX_USART2_UART_Init+0x60>)
80018bc: 22e1 movs r2, #225 ; 0xe1
80018be: 0252 lsls r2, r2, #9
80018c0: 605a str r2, [r3, #4]
huart2.Init.WordLength = UART_WORDLENGTH_8B;
80018c2: 4b13 ldr r3, [pc, #76] ; (8001910 <MX_USART2_UART_Init+0x60>)
80018c4: 2200 movs r2, #0
80018c6: 609a str r2, [r3, #8]
huart2.Init.StopBits = UART_STOPBITS_1;
80018c8: 4b11 ldr r3, [pc, #68] ; (8001910 <MX_USART2_UART_Init+0x60>)
80018ca: 2200 movs r2, #0
80018cc: 60da str r2, [r3, #12]
huart2.Init.Parity = UART_PARITY_NONE;
80018ce: 4b10 ldr r3, [pc, #64] ; (8001910 <MX_USART2_UART_Init+0x60>)
80018d0: 2200 movs r2, #0
80018d2: 611a str r2, [r3, #16]
huart2.Init.Mode = UART_MODE_TX_RX;
80018d4: 4b0e ldr r3, [pc, #56] ; (8001910 <MX_USART2_UART_Init+0x60>)
80018d6: 220c movs r2, #12
80018d8: 615a str r2, [r3, #20]
huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
80018da: 4b0d ldr r3, [pc, #52] ; (8001910 <MX_USART2_UART_Init+0x60>)
80018dc: 2200 movs r2, #0
80018de: 619a str r2, [r3, #24]
huart2.Init.OverSampling = UART_OVERSAMPLING_16;
80018e0: 4b0b ldr r3, [pc, #44] ; (8001910 <MX_USART2_UART_Init+0x60>)
80018e2: 2200 movs r2, #0
80018e4: 61da str r2, [r3, #28]
huart2.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
80018e6: 4b0a ldr r3, [pc, #40] ; (8001910 <MX_USART2_UART_Init+0x60>)
80018e8: 2200 movs r2, #0
80018ea: 621a str r2, [r3, #32]
huart2.Init.ClockPrescaler = UART_PRESCALER_DIV1;
80018ec: 4b08 ldr r3, [pc, #32] ; (8001910 <MX_USART2_UART_Init+0x60>)
80018ee: 2200 movs r2, #0
80018f0: 625a str r2, [r3, #36] ; 0x24
huart2.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
80018f2: 4b07 ldr r3, [pc, #28] ; (8001910 <MX_USART2_UART_Init+0x60>)
80018f4: 2200 movs r2, #0
80018f6: 629a str r2, [r3, #40] ; 0x28
if (HAL_UART_Init(&huart2) != HAL_OK)
80018f8: 4b05 ldr r3, [pc, #20] ; (8001910 <MX_USART2_UART_Init+0x60>)
80018fa: 0018 movs r0, r3
80018fc: f003 fd4e bl 800539c <HAL_UART_Init>
8001900: 1e03 subs r3, r0, #0
8001902: d001 beq.n 8001908 <MX_USART2_UART_Init+0x58>
{
Error_Handler();
8001904: f7ff f96f bl 8000be6 <Error_Handler>
}
/* USER CODE BEGIN USART2_Init 2 */
/* USER CODE END USART2_Init 2 */
}
8001908: 46c0 nop ; (mov r8, r8)
800190a: 46bd mov sp, r7
800190c: bd80 pop {r7, pc}
800190e: 46c0 nop ; (mov r8, r8)
8001910: 2000035c .word 0x2000035c
8001914: 40004400 .word 0x40004400
08001918 <HAL_UART_MspInit>:
void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle)
{
8001918: b590 push {r4, r7, lr}
800191a: b08b sub sp, #44 ; 0x2c
800191c: af00 add r7, sp, #0
800191e: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001920: 2414 movs r4, #20
8001922: 193b adds r3, r7, r4
8001924: 0018 movs r0, r3
8001926: 2314 movs r3, #20
8001928: 001a movs r2, r3
800192a: 2100 movs r1, #0
800192c: f005 fd48 bl 80073c0 <memset>
if(uartHandle->Instance==USART2)
8001930: 687b ldr r3, [r7, #4]
8001932: 681b ldr r3, [r3, #0]
8001934: 4a34 ldr r2, [pc, #208] ; (8001a08 <HAL_UART_MspInit+0xf0>)
8001936: 4293 cmp r3, r2
8001938: d161 bne.n 80019fe <HAL_UART_MspInit+0xe6>
{
/* USER CODE BEGIN USART2_MspInit 0 */
/* USER CODE END USART2_MspInit 0 */
/* USART2 clock enable */
__HAL_RCC_USART2_CLK_ENABLE();
800193a: 4b34 ldr r3, [pc, #208] ; (8001a0c <HAL_UART_MspInit+0xf4>)
800193c: 6bda ldr r2, [r3, #60] ; 0x3c
800193e: 4b33 ldr r3, [pc, #204] ; (8001a0c <HAL_UART_MspInit+0xf4>)
8001940: 2180 movs r1, #128 ; 0x80
8001942: 0289 lsls r1, r1, #10
8001944: 430a orrs r2, r1
8001946: 63da str r2, [r3, #60] ; 0x3c
8001948: 4b30 ldr r3, [pc, #192] ; (8001a0c <HAL_UART_MspInit+0xf4>)
800194a: 6bda ldr r2, [r3, #60] ; 0x3c
800194c: 2380 movs r3, #128 ; 0x80
800194e: 029b lsls r3, r3, #10
8001950: 4013 ands r3, r2
8001952: 613b str r3, [r7, #16]
8001954: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
8001956: 4b2d ldr r3, [pc, #180] ; (8001a0c <HAL_UART_MspInit+0xf4>)
8001958: 6b5a ldr r2, [r3, #52] ; 0x34
800195a: 4b2c ldr r3, [pc, #176] ; (8001a0c <HAL_UART_MspInit+0xf4>)
800195c: 2101 movs r1, #1
800195e: 430a orrs r2, r1
8001960: 635a str r2, [r3, #52] ; 0x34
8001962: 4b2a ldr r3, [pc, #168] ; (8001a0c <HAL_UART_MspInit+0xf4>)
8001964: 6b5b ldr r3, [r3, #52] ; 0x34
8001966: 2201 movs r2, #1
8001968: 4013 ands r3, r2
800196a: 60fb str r3, [r7, #12]
800196c: 68fb ldr r3, [r7, #12]
/**USART2 GPIO Configuration
PA2 ------> USART2_TX
PA3 ------> USART2_RX
*/
GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3;
800196e: 0021 movs r1, r4
8001970: 187b adds r3, r7, r1
8001972: 220c movs r2, #12
8001974: 601a str r2, [r3, #0]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001976: 187b adds r3, r7, r1
8001978: 2202 movs r2, #2
800197a: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800197c: 187b adds r3, r7, r1
800197e: 2200 movs r2, #0
8001980: 609a str r2, [r3, #8]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001982: 187b adds r3, r7, r1
8001984: 2200 movs r2, #0
8001986: 60da str r2, [r3, #12]
GPIO_InitStruct.Alternate = GPIO_AF1_USART2;
8001988: 187b adds r3, r7, r1
800198a: 2201 movs r2, #1
800198c: 611a str r2, [r3, #16]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
800198e: 187a adds r2, r7, r1
8001990: 23a0 movs r3, #160 ; 0xa0
8001992: 05db lsls r3, r3, #23
8001994: 0011 movs r1, r2
8001996: 0018 movs r0, r3
8001998: f001 fdd4 bl 8003544 <HAL_GPIO_Init>
/* USART2 DMA Init */
/* USART2_TX Init */
hdma_usart2_tx.Instance = DMA1_Channel1;
800199c: 4b1c ldr r3, [pc, #112] ; (8001a10 <HAL_UART_MspInit+0xf8>)
800199e: 4a1d ldr r2, [pc, #116] ; (8001a14 <HAL_UART_MspInit+0xfc>)
80019a0: 601a str r2, [r3, #0]
hdma_usart2_tx.Init.Request = DMA_REQUEST_USART2_TX;
80019a2: 4b1b ldr r3, [pc, #108] ; (8001a10 <HAL_UART_MspInit+0xf8>)
80019a4: 2235 movs r2, #53 ; 0x35
80019a6: 605a str r2, [r3, #4]
hdma_usart2_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
80019a8: 4b19 ldr r3, [pc, #100] ; (8001a10 <HAL_UART_MspInit+0xf8>)
80019aa: 2210 movs r2, #16
80019ac: 609a str r2, [r3, #8]
hdma_usart2_tx.Init.PeriphInc = DMA_PINC_DISABLE;
80019ae: 4b18 ldr r3, [pc, #96] ; (8001a10 <HAL_UART_MspInit+0xf8>)
80019b0: 2200 movs r2, #0
80019b2: 60da str r2, [r3, #12]
hdma_usart2_tx.Init.MemInc = DMA_MINC_ENABLE;
80019b4: 4b16 ldr r3, [pc, #88] ; (8001a10 <HAL_UART_MspInit+0xf8>)
80019b6: 2280 movs r2, #128 ; 0x80
80019b8: 611a str r2, [r3, #16]
hdma_usart2_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
80019ba: 4b15 ldr r3, [pc, #84] ; (8001a10 <HAL_UART_MspInit+0xf8>)
80019bc: 2200 movs r2, #0
80019be: 615a str r2, [r3, #20]
hdma_usart2_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
80019c0: 4b13 ldr r3, [pc, #76] ; (8001a10 <HAL_UART_MspInit+0xf8>)
80019c2: 2200 movs r2, #0
80019c4: 619a str r2, [r3, #24]
hdma_usart2_tx.Init.Mode = DMA_NORMAL;
80019c6: 4b12 ldr r3, [pc, #72] ; (8001a10 <HAL_UART_MspInit+0xf8>)
80019c8: 2200 movs r2, #0
80019ca: 61da str r2, [r3, #28]
hdma_usart2_tx.Init.Priority = DMA_PRIORITY_LOW;
80019cc: 4b10 ldr r3, [pc, #64] ; (8001a10 <HAL_UART_MspInit+0xf8>)
80019ce: 2200 movs r2, #0
80019d0: 621a str r2, [r3, #32]
if (HAL_DMA_Init(&hdma_usart2_tx) != HAL_OK)
80019d2: 4b0f ldr r3, [pc, #60] ; (8001a10 <HAL_UART_MspInit+0xf8>)
80019d4: 0018 movs r0, r3
80019d6: f001 fa97 bl 8002f08 <HAL_DMA_Init>
80019da: 1e03 subs r3, r0, #0
80019dc: d001 beq.n 80019e2 <HAL_UART_MspInit+0xca>
{
Error_Handler();
80019de: f7ff f902 bl 8000be6 <Error_Handler>
}
__HAL_LINKDMA(uartHandle,hdmatx,hdma_usart2_tx);
80019e2: 687b ldr r3, [r7, #4]
80019e4: 4a0a ldr r2, [pc, #40] ; (8001a10 <HAL_UART_MspInit+0xf8>)
80019e6: 679a str r2, [r3, #120] ; 0x78
80019e8: 4b09 ldr r3, [pc, #36] ; (8001a10 <HAL_UART_MspInit+0xf8>)
80019ea: 687a ldr r2, [r7, #4]
80019ec: 629a str r2, [r3, #40] ; 0x28
/* USART2 interrupt Init */
HAL_NVIC_SetPriority(USART2_IRQn, 0, 0);
80019ee: 2200 movs r2, #0
80019f0: 2100 movs r1, #0
80019f2: 201c movs r0, #28
80019f4: f001 fa56 bl 8002ea4 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(USART2_IRQn);
80019f8: 201c movs r0, #28
80019fa: f001 fa68 bl 8002ece <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN USART2_MspInit 1 */
/* USER CODE END USART2_MspInit 1 */
}
}
80019fe: 46c0 nop ; (mov r8, r8)
8001a00: 46bd mov sp, r7
8001a02: b00b add sp, #44 ; 0x2c
8001a04: bd90 pop {r4, r7, pc}
8001a06: 46c0 nop ; (mov r8, r8)
8001a08: 40004400 .word 0x40004400
8001a0c: 40021000 .word 0x40021000
8001a10: 200003ec .word 0x200003ec
8001a14: 40020008 .word 0x40020008
08001a18 <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
8001a18: 480d ldr r0, [pc, #52] ; (8001a50 <LoopForever+0x2>)
mov sp, r0 /* set stack pointer */
8001a1a: 4685 mov sp, r0
/* Call the clock system initialization function.*/
bl SystemInit
8001a1c: f7ff fdde bl 80015dc <SystemInit>
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
8001a20: 480c ldr r0, [pc, #48] ; (8001a54 <LoopForever+0x6>)
ldr r1, =_edata
8001a22: 490d ldr r1, [pc, #52] ; (8001a58 <LoopForever+0xa>)
ldr r2, =_sidata
8001a24: 4a0d ldr r2, [pc, #52] ; (8001a5c <LoopForever+0xe>)
movs r3, #0
8001a26: 2300 movs r3, #0
b LoopCopyDataInit
8001a28: e002 b.n 8001a30 <LoopCopyDataInit>
08001a2a <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
8001a2a: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
8001a2c: 50c4 str r4, [r0, r3]
adds r3, r3, #4
8001a2e: 3304 adds r3, #4
08001a30 <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
8001a30: 18c4 adds r4, r0, r3
cmp r4, r1
8001a32: 428c cmp r4, r1
bcc CopyDataInit
8001a34: d3f9 bcc.n 8001a2a <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
8001a36: 4a0a ldr r2, [pc, #40] ; (8001a60 <LoopForever+0x12>)
ldr r4, =_ebss
8001a38: 4c0a ldr r4, [pc, #40] ; (8001a64 <LoopForever+0x16>)
movs r3, #0
8001a3a: 2300 movs r3, #0
b LoopFillZerobss
8001a3c: e001 b.n 8001a42 <LoopFillZerobss>
08001a3e <FillZerobss>:
FillZerobss:
str r3, [r2]
8001a3e: 6013 str r3, [r2, #0]
adds r2, r2, #4
8001a40: 3204 adds r2, #4
08001a42 <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
8001a42: 42a2 cmp r2, r4
bcc FillZerobss
8001a44: d3fb bcc.n 8001a3e <FillZerobss>
/* Call static constructors */
bl __libc_init_array
8001a46: f005 fc97 bl 8007378 <__libc_init_array>
/* Call the application s entry point.*/
bl main
8001a4a: f7ff f86b bl 8000b24 <main>
08001a4e <LoopForever>:
LoopForever:
b LoopForever
8001a4e: e7fe b.n 8001a4e <LoopForever>
ldr r0, =_estack
8001a50: 20002000 .word 0x20002000
ldr r0, =_sdata
8001a54: 20000000 .word 0x20000000
ldr r1, =_edata
8001a58: 20000018 .word 0x20000018
ldr r2, =_sidata
8001a5c: 080074c4 .word 0x080074c4
ldr r2, =_sbss
8001a60: 20000018 .word 0x20000018
ldr r4, =_ebss
8001a64: 2000044c .word 0x2000044c
08001a68 <DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler>:
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8001a68: e7fe b.n 8001a68 <DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler>
...
08001a6c <HAL_Init>:
* each 1ms in the SysTick_Handler() interrupt handler.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
8001a6c: b580 push {r7, lr}
8001a6e: b082 sub sp, #8
8001a70: af00 add r7, sp, #0
HAL_StatusTypeDef status = HAL_OK;
8001a72: 1dfb adds r3, r7, #7
8001a74: 2200 movs r2, #0
8001a76: 701a strb r2, [r3, #0]
#if (INSTRUCTION_CACHE_ENABLE == 0U)
__HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
#endif /* INSTRUCTION_CACHE_ENABLE */
#if (PREFETCH_ENABLE != 0U)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
8001a78: 4b0b ldr r3, [pc, #44] ; (8001aa8 <HAL_Init+0x3c>)
8001a7a: 681a ldr r2, [r3, #0]
8001a7c: 4b0a ldr r3, [pc, #40] ; (8001aa8 <HAL_Init+0x3c>)
8001a7e: 2180 movs r1, #128 ; 0x80
8001a80: 0049 lsls r1, r1, #1
8001a82: 430a orrs r2, r1
8001a84: 601a str r2, [r3, #0]
#endif /* PREFETCH_ENABLE */
/* Use SysTick as time base source and configure 1ms tick (default clock after Reset is HSI) */
if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
8001a86: 2003 movs r0, #3
8001a88: f000 f810 bl 8001aac <HAL_InitTick>
8001a8c: 1e03 subs r3, r0, #0
8001a8e: d003 beq.n 8001a98 <HAL_Init+0x2c>
{
status = HAL_ERROR;
8001a90: 1dfb adds r3, r7, #7
8001a92: 2201 movs r2, #1
8001a94: 701a strb r2, [r3, #0]
8001a96: e001 b.n 8001a9c <HAL_Init+0x30>
}
else
{
/* Init the low level hardware */
HAL_MspInit();
8001a98: f7ff fd40 bl 800151c <HAL_MspInit>
}
/* Return function status */
return status;
8001a9c: 1dfb adds r3, r7, #7
8001a9e: 781b ldrb r3, [r3, #0]
}
8001aa0: 0018 movs r0, r3
8001aa2: 46bd mov sp, r7
8001aa4: b002 add sp, #8
8001aa6: bd80 pop {r7, pc}
8001aa8: 40022000 .word 0x40022000
08001aac <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
8001aac: b590 push {r4, r7, lr}
8001aae: b085 sub sp, #20
8001ab0: af00 add r7, sp, #0
8001ab2: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
8001ab4: 230f movs r3, #15
8001ab6: 18fb adds r3, r7, r3
8001ab8: 2200 movs r2, #0
8001aba: 701a strb r2, [r3, #0]
/* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that doesn't take the value zero)*/
if ((uint32_t)uwTickFreq != 0U)
8001abc: 4b1d ldr r3, [pc, #116] ; (8001b34 <HAL_InitTick+0x88>)
8001abe: 781b ldrb r3, [r3, #0]
8001ac0: 2b00 cmp r3, #0
8001ac2: d02b beq.n 8001b1c <HAL_InitTick+0x70>
{
/*Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U /(uint32_t)uwTickFreq)) == 0U)
8001ac4: 4b1c ldr r3, [pc, #112] ; (8001b38 <HAL_InitTick+0x8c>)
8001ac6: 681c ldr r4, [r3, #0]
8001ac8: 4b1a ldr r3, [pc, #104] ; (8001b34 <HAL_InitTick+0x88>)
8001aca: 781b ldrb r3, [r3, #0]
8001acc: 0019 movs r1, r3
8001ace: 23fa movs r3, #250 ; 0xfa
8001ad0: 0098 lsls r0, r3, #2
8001ad2: f7fe fb17 bl 8000104 <__udivsi3>
8001ad6: 0003 movs r3, r0
8001ad8: 0019 movs r1, r3
8001ada: 0020 movs r0, r4
8001adc: f7fe fb12 bl 8000104 <__udivsi3>
8001ae0: 0003 movs r3, r0
8001ae2: 0018 movs r0, r3
8001ae4: f001 fa03 bl 8002eee <HAL_SYSTICK_Config>
8001ae8: 1e03 subs r3, r0, #0
8001aea: d112 bne.n 8001b12 <HAL_InitTick+0x66>
{
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
8001aec: 687b ldr r3, [r7, #4]
8001aee: 2b03 cmp r3, #3
8001af0: d80a bhi.n 8001b08 <HAL_InitTick+0x5c>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
8001af2: 6879 ldr r1, [r7, #4]
8001af4: 2301 movs r3, #1
8001af6: 425b negs r3, r3
8001af8: 2200 movs r2, #0
8001afa: 0018 movs r0, r3
8001afc: f001 f9d2 bl 8002ea4 <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
8001b00: 4b0e ldr r3, [pc, #56] ; (8001b3c <HAL_InitTick+0x90>)
8001b02: 687a ldr r2, [r7, #4]
8001b04: 601a str r2, [r3, #0]
8001b06: e00d b.n 8001b24 <HAL_InitTick+0x78>
}
else
{
status = HAL_ERROR;
8001b08: 230f movs r3, #15
8001b0a: 18fb adds r3, r7, r3
8001b0c: 2201 movs r2, #1
8001b0e: 701a strb r2, [r3, #0]
8001b10: e008 b.n 8001b24 <HAL_InitTick+0x78>
}
}
else
{
status = HAL_ERROR;
8001b12: 230f movs r3, #15
8001b14: 18fb adds r3, r7, r3
8001b16: 2201 movs r2, #1
8001b18: 701a strb r2, [r3, #0]
8001b1a: e003 b.n 8001b24 <HAL_InitTick+0x78>
}
}
else
{
status = HAL_ERROR;
8001b1c: 230f movs r3, #15
8001b1e: 18fb adds r3, r7, r3
8001b20: 2201 movs r2, #1
8001b22: 701a strb r2, [r3, #0]
}
/* Return function status */
return status;
8001b24: 230f movs r3, #15
8001b26: 18fb adds r3, r7, r3
8001b28: 781b ldrb r3, [r3, #0]
}
8001b2a: 0018 movs r0, r3
8001b2c: 46bd mov sp, r7
8001b2e: b005 add sp, #20
8001b30: bd90 pop {r4, r7, pc}
8001b32: 46c0 nop ; (mov r8, r8)
8001b34: 20000014 .word 0x20000014
8001b38: 2000000c .word 0x2000000c
8001b3c: 20000010 .word 0x20000010
08001b40 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
8001b40: b580 push {r7, lr}
8001b42: af00 add r7, sp, #0
uwTick += (uint32_t)uwTickFreq;
8001b44: 4b05 ldr r3, [pc, #20] ; (8001b5c <HAL_IncTick+0x1c>)
8001b46: 781b ldrb r3, [r3, #0]
8001b48: 001a movs r2, r3
8001b4a: 4b05 ldr r3, [pc, #20] ; (8001b60 <HAL_IncTick+0x20>)
8001b4c: 681b ldr r3, [r3, #0]
8001b4e: 18d2 adds r2, r2, r3
8001b50: 4b03 ldr r3, [pc, #12] ; (8001b60 <HAL_IncTick+0x20>)
8001b52: 601a str r2, [r3, #0]
}
8001b54: 46c0 nop ; (mov r8, r8)
8001b56: 46bd mov sp, r7
8001b58: bd80 pop {r7, pc}
8001b5a: 46c0 nop ; (mov r8, r8)
8001b5c: 20000014 .word 0x20000014
8001b60: 20000448 .word 0x20000448
08001b64 <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
8001b64: b580 push {r7, lr}
8001b66: af00 add r7, sp, #0
return uwTick;
8001b68: 4b02 ldr r3, [pc, #8] ; (8001b74 <HAL_GetTick+0x10>)
8001b6a: 681b ldr r3, [r3, #0]
}
8001b6c: 0018 movs r0, r3
8001b6e: 46bd mov sp, r7
8001b70: bd80 pop {r7, pc}
8001b72: 46c0 nop ; (mov r8, r8)
8001b74: 20000448 .word 0x20000448
08001b78 <LL_ADC_SetCommonPathInternalCh>:
* @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
* @arg @ref LL_ADC_PATH_INTERNAL_VBAT
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
{
8001b78: b580 push {r7, lr}
8001b7a: b082 sub sp, #8
8001b7c: af00 add r7, sp, #0
8001b7e: 6078 str r0, [r7, #4]
8001b80: 6039 str r1, [r7, #0]
MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal);
8001b82: 687b ldr r3, [r7, #4]
8001b84: 681b ldr r3, [r3, #0]
8001b86: 4a05 ldr r2, [pc, #20] ; (8001b9c <LL_ADC_SetCommonPathInternalCh+0x24>)
8001b88: 401a ands r2, r3
8001b8a: 683b ldr r3, [r7, #0]
8001b8c: 431a orrs r2, r3
8001b8e: 687b ldr r3, [r7, #4]
8001b90: 601a str r2, [r3, #0]
}
8001b92: 46c0 nop ; (mov r8, r8)
8001b94: 46bd mov sp, r7
8001b96: b002 add sp, #8
8001b98: bd80 pop {r7, pc}
8001b9a: 46c0 nop ; (mov r8, r8)
8001b9c: fe3fffff .word 0xfe3fffff
08001ba0 <LL_ADC_GetCommonPathInternalCh>:
* @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
* @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
* @arg @ref LL_ADC_PATH_INTERNAL_VBAT
*/
__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
{
8001ba0: b580 push {r7, lr}
8001ba2: b082 sub sp, #8
8001ba4: af00 add r7, sp, #0
8001ba6: 6078 str r0, [r7, #4]
return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN));
8001ba8: 687b ldr r3, [r7, #4]
8001baa: 681a ldr r2, [r3, #0]
8001bac: 23e0 movs r3, #224 ; 0xe0
8001bae: 045b lsls r3, r3, #17
8001bb0: 4013 ands r3, r2
}
8001bb2: 0018 movs r0, r3
8001bb4: 46bd mov sp, r7
8001bb6: b002 add sp, #8
8001bb8: bd80 pop {r7, pc}
08001bba <LL_ADC_SetSamplingTimeCommonChannels>:
* @arg @ref LL_ADC_SAMPLINGTIME_160CYCLES_5
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uint32_t SamplingTimeY,
uint32_t SamplingTime)
{
8001bba: b580 push {r7, lr}
8001bbc: b084 sub sp, #16
8001bbe: af00 add r7, sp, #0
8001bc0: 60f8 str r0, [r7, #12]
8001bc2: 60b9 str r1, [r7, #8]
8001bc4: 607a str r2, [r7, #4]
MODIFY_REG(ADCx->SMPR,
8001bc6: 68fb ldr r3, [r7, #12]
8001bc8: 695b ldr r3, [r3, #20]
8001bca: 68ba ldr r2, [r7, #8]
8001bcc: 2104 movs r1, #4
8001bce: 400a ands r2, r1
8001bd0: 2107 movs r1, #7
8001bd2: 4091 lsls r1, r2
8001bd4: 000a movs r2, r1
8001bd6: 43d2 mvns r2, r2
8001bd8: 401a ands r2, r3
8001bda: 68bb ldr r3, [r7, #8]
8001bdc: 2104 movs r1, #4
8001bde: 400b ands r3, r1
8001be0: 6879 ldr r1, [r7, #4]
8001be2: 4099 lsls r1, r3
8001be4: 000b movs r3, r1
8001be6: 431a orrs r2, r3
8001be8: 68fb ldr r3, [r7, #12]
8001bea: 615a str r2, [r3, #20]
ADC_SMPR_SMP1 << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK),
SamplingTime << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK));
}
8001bec: 46c0 nop ; (mov r8, r8)
8001bee: 46bd mov sp, r7
8001bf0: b004 add sp, #16
8001bf2: bd80 pop {r7, pc}
08001bf4 <LL_ADC_GetSamplingTimeCommonChannels>:
* @arg @ref LL_ADC_SAMPLINGTIME_39CYCLES_5
* @arg @ref LL_ADC_SAMPLINGTIME_79CYCLES_5
* @arg @ref LL_ADC_SAMPLINGTIME_160CYCLES_5
*/
__STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uint32_t SamplingTimeY)
{
8001bf4: b580 push {r7, lr}
8001bf6: b082 sub sp, #8
8001bf8: af00 add r7, sp, #0
8001bfa: 6078 str r0, [r7, #4]
8001bfc: 6039 str r1, [r7, #0]
return (uint32_t)((READ_BIT(ADCx->SMPR, ADC_SMPR_SMP1 << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK)))
8001bfe: 687b ldr r3, [r7, #4]
8001c00: 695b ldr r3, [r3, #20]
8001c02: 683a ldr r2, [r7, #0]
8001c04: 2104 movs r1, #4
8001c06: 400a ands r2, r1
8001c08: 2107 movs r1, #7
8001c0a: 4091 lsls r1, r2
8001c0c: 000a movs r2, r1
8001c0e: 401a ands r2, r3
>> (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK));
8001c10: 683b ldr r3, [r7, #0]
8001c12: 2104 movs r1, #4
8001c14: 400b ands r3, r1
return (uint32_t)((READ_BIT(ADCx->SMPR, ADC_SMPR_SMP1 << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK)))
8001c16: 40da lsrs r2, r3
8001c18: 0013 movs r3, r2
}
8001c1a: 0018 movs r0, r3
8001c1c: 46bd mov sp, r7
8001c1e: b002 add sp, #8
8001c20: bd80 pop {r7, pc}
08001c22 <LL_ADC_REG_IsTriggerSourceSWStart>:
* @param ADCx ADC instance
* @retval Value "0" if trigger source external trigger
* Value "1" if trigger source SW start.
*/
__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
{
8001c22: b580 push {r7, lr}
8001c24: b082 sub sp, #8
8001c26: af00 add r7, sp, #0
8001c28: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN)) ? 1UL : 0UL);
8001c2a: 687b ldr r3, [r7, #4]
8001c2c: 68da ldr r2, [r3, #12]
8001c2e: 23c0 movs r3, #192 ; 0xc0
8001c30: 011b lsls r3, r3, #4
8001c32: 4013 ands r3, r2
8001c34: d101 bne.n 8001c3a <LL_ADC_REG_IsTriggerSourceSWStart+0x18>
8001c36: 2301 movs r3, #1
8001c38: e000 b.n 8001c3c <LL_ADC_REG_IsTriggerSourceSWStart+0x1a>
8001c3a: 2300 movs r3, #0
}
8001c3c: 0018 movs r0, r3
8001c3e: 46bd mov sp, r7
8001c40: b002 add sp, #8
8001c42: bd80 pop {r7, pc}
08001c44 <LL_ADC_REG_SetSequencerRanks>:
* only if sequencer is set in mode "not fully configurable",
* refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
* @retval None
*/
__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
{
8001c44: b580 push {r7, lr}
8001c46: b084 sub sp, #16
8001c48: af00 add r7, sp, #0
8001c4a: 60f8 str r0, [r7, #12]
8001c4c: 60b9 str r1, [r7, #8]
8001c4e: 607a str r2, [r7, #4]
/* Set bits with content of parameter "Channel" with bits position */
/* in register depending on parameter "Rank". */
/* Parameters "Rank" and "Channel" are used with masks because containing */
/* other bits reserved for other purpose. */
MODIFY_REG(ADCx->CHSELR,
8001c50: 68fb ldr r3, [r7, #12]
8001c52: 6a9b ldr r3, [r3, #40] ; 0x28
8001c54: 68ba ldr r2, [r7, #8]
8001c56: 211f movs r1, #31
8001c58: 400a ands r2, r1
8001c5a: 210f movs r1, #15
8001c5c: 4091 lsls r1, r2
8001c5e: 000a movs r2, r1
8001c60: 43d2 mvns r2, r2
8001c62: 401a ands r2, r3
8001c64: 687b ldr r3, [r7, #4]
8001c66: 0e9b lsrs r3, r3, #26
8001c68: 210f movs r1, #15
8001c6a: 4019 ands r1, r3
8001c6c: 68bb ldr r3, [r7, #8]
8001c6e: 201f movs r0, #31
8001c70: 4003 ands r3, r0
8001c72: 4099 lsls r1, r3
8001c74: 000b movs r3, r1
8001c76: 431a orrs r2, r3
8001c78: 68fb ldr r3, [r7, #12]
8001c7a: 629a str r2, [r3, #40] ; 0x28
ADC_CHSELR_SQ1 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
((Channel & ADC_CHANNEL_ID_NUMBER_MASK_SEQ) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
}
8001c7c: 46c0 nop ; (mov r8, r8)
8001c7e: 46bd mov sp, r7
8001c80: b004 add sp, #16
8001c82: bd80 pop {r7, pc}
08001c84 <LL_ADC_REG_SetSequencerChAdd>:
* only if sequencer is set in mode "not fully configurable",
* refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
* @retval None
*/
__STATIC_INLINE void LL_ADC_REG_SetSequencerChAdd(ADC_TypeDef *ADCx, uint32_t Channel)
{
8001c84: b580 push {r7, lr}
8001c86: b082 sub sp, #8
8001c88: af00 add r7, sp, #0
8001c8a: 6078 str r0, [r7, #4]
8001c8c: 6039 str r1, [r7, #0]
/* Parameter "Channel" is used with masks because containing */
/* other bits reserved for other purpose. */
SET_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
8001c8e: 687b ldr r3, [r7, #4]
8001c90: 6a9a ldr r2, [r3, #40] ; 0x28
8001c92: 683b ldr r3, [r7, #0]
8001c94: 035b lsls r3, r3, #13
8001c96: 0b5b lsrs r3, r3, #13
8001c98: 431a orrs r2, r3
8001c9a: 687b ldr r3, [r7, #4]
8001c9c: 629a str r2, [r3, #40] ; 0x28
}
8001c9e: 46c0 nop ; (mov r8, r8)
8001ca0: 46bd mov sp, r7
8001ca2: b002 add sp, #8
8001ca4: bd80 pop {r7, pc}
08001ca6 <LL_ADC_REG_SetSequencerChRem>:
* only if sequencer is set in mode "not fully configurable",
* refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
* @retval None
*/
__STATIC_INLINE void LL_ADC_REG_SetSequencerChRem(ADC_TypeDef *ADCx, uint32_t Channel)
{
8001ca6: b580 push {r7, lr}
8001ca8: b082 sub sp, #8
8001caa: af00 add r7, sp, #0
8001cac: 6078 str r0, [r7, #4]
8001cae: 6039 str r1, [r7, #0]
/* Parameter "Channel" is used with masks because containing */
/* other bits reserved for other purpose. */
CLEAR_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
8001cb0: 687b ldr r3, [r7, #4]
8001cb2: 6a9b ldr r3, [r3, #40] ; 0x28
8001cb4: 683a ldr r2, [r7, #0]
8001cb6: 0352 lsls r2, r2, #13
8001cb8: 0b52 lsrs r2, r2, #13
8001cba: 43d2 mvns r2, r2
8001cbc: 401a ands r2, r3
8001cbe: 687b ldr r3, [r7, #4]
8001cc0: 629a str r2, [r3, #40] ; 0x28
}
8001cc2: 46c0 nop ; (mov r8, r8)
8001cc4: 46bd mov sp, r7
8001cc6: b002 add sp, #8
8001cc8: bd80 pop {r7, pc}
08001cca <LL_ADC_REG_GetDMATransfer>:
* @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
* @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
* @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
*/
__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
{
8001cca: b580 push {r7, lr}
8001ccc: b082 sub sp, #8
8001cce: af00 add r7, sp, #0
8001cd0: 6078 str r0, [r7, #4]
return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG));
8001cd2: 687b ldr r3, [r7, #4]
8001cd4: 68db ldr r3, [r3, #12]
8001cd6: 2203 movs r2, #3
8001cd8: 4013 ands r3, r2
}
8001cda: 0018 movs r0, r3
8001cdc: 46bd mov sp, r7
8001cde: b002 add sp, #8
8001ce0: bd80 pop {r7, pc}
...
08001ce4 <LL_ADC_SetChannelSamplingTime>:
* @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1
* @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTimeY)
{
8001ce4: b580 push {r7, lr}
8001ce6: b084 sub sp, #16
8001ce8: af00 add r7, sp, #0
8001cea: 60f8 str r0, [r7, #12]
8001cec: 60b9 str r1, [r7, #8]
8001cee: 607a str r2, [r7, #4]
/* Parameter "Channel" is used with masks because containing */
/* other bits reserved for other purpose. */
MODIFY_REG(ADCx->SMPR,
8001cf0: 68fb ldr r3, [r7, #12]
8001cf2: 695b ldr r3, [r3, #20]
8001cf4: 68ba ldr r2, [r7, #8]
8001cf6: 0212 lsls r2, r2, #8
8001cf8: 43d2 mvns r2, r2
8001cfa: 401a ands r2, r3
8001cfc: 68bb ldr r3, [r7, #8]
8001cfe: 021b lsls r3, r3, #8
8001d00: 6879 ldr r1, [r7, #4]
8001d02: 400b ands r3, r1
8001d04: 4904 ldr r1, [pc, #16] ; (8001d18 <LL_ADC_SetChannelSamplingTime+0x34>)
8001d06: 400b ands r3, r1
8001d08: 431a orrs r2, r3
8001d0a: 68fb ldr r3, [r7, #12]
8001d0c: 615a str r2, [r3, #20]
(Channel << ADC_SMPR_SMPSEL0_BITOFFSET_POS),
(Channel << ADC_SMPR_SMPSEL0_BITOFFSET_POS) & (SamplingTimeY & ADC_SAMPLING_TIME_CH_MASK)
);
}
8001d0e: 46c0 nop ; (mov r8, r8)
8001d10: 46bd mov sp, r7
8001d12: b004 add sp, #16
8001d14: bd80 pop {r7, pc}
8001d16: 46c0 nop ; (mov r8, r8)
8001d18: 07ffff00 .word 0x07ffff00
08001d1c <LL_ADC_EnableInternalRegulator>:
* @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
{
8001d1c: b580 push {r7, lr}
8001d1e: b082 sub sp, #8
8001d20: af00 add r7, sp, #0
8001d22: 6078 str r0, [r7, #4]
/* Note: Write register with some additional bits forced to state reset */
/* instead of modifying only the selected bit for this function, */
/* to not interfere with bits with HW property "rs". */
MODIFY_REG(ADCx->CR,
8001d24: 687b ldr r3, [r7, #4]
8001d26: 689b ldr r3, [r3, #8]
8001d28: 4a05 ldr r2, [pc, #20] ; (8001d40 <LL_ADC_EnableInternalRegulator+0x24>)
8001d2a: 4013 ands r3, r2
8001d2c: 2280 movs r2, #128 ; 0x80
8001d2e: 0552 lsls r2, r2, #21
8001d30: 431a orrs r2, r3
8001d32: 687b ldr r3, [r7, #4]
8001d34: 609a str r2, [r3, #8]
ADC_CR_BITS_PROPERTY_RS,
ADC_CR_ADVREGEN);
}
8001d36: 46c0 nop ; (mov r8, r8)
8001d38: 46bd mov sp, r7
8001d3a: b002 add sp, #8
8001d3c: bd80 pop {r7, pc}
8001d3e: 46c0 nop ; (mov r8, r8)
8001d40: 6fffffe8 .word 0x6fffffe8
08001d44 <LL_ADC_IsInternalRegulatorEnabled>:
* @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled
* @param ADCx ADC instance
* @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
*/
__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx)
{
8001d44: b580 push {r7, lr}
8001d46: b082 sub sp, #8
8001d48: af00 add r7, sp, #0
8001d4a: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
8001d4c: 687b ldr r3, [r7, #4]
8001d4e: 689a ldr r2, [r3, #8]
8001d50: 2380 movs r3, #128 ; 0x80
8001d52: 055b lsls r3, r3, #21
8001d54: 401a ands r2, r3
8001d56: 2380 movs r3, #128 ; 0x80
8001d58: 055b lsls r3, r3, #21
8001d5a: 429a cmp r2, r3
8001d5c: d101 bne.n 8001d62 <LL_ADC_IsInternalRegulatorEnabled+0x1e>
8001d5e: 2301 movs r3, #1
8001d60: e000 b.n 8001d64 <LL_ADC_IsInternalRegulatorEnabled+0x20>
8001d62: 2300 movs r3, #0
}
8001d64: 0018 movs r0, r3
8001d66: 46bd mov sp, r7
8001d68: b002 add sp, #8
8001d6a: bd80 pop {r7, pc}
08001d6c <LL_ADC_Enable>:
* @rmtoll CR ADEN LL_ADC_Enable
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
{
8001d6c: b580 push {r7, lr}
8001d6e: b082 sub sp, #8
8001d70: af00 add r7, sp, #0
8001d72: 6078 str r0, [r7, #4]
/* Note: Write register with some additional bits forced to state reset */
/* instead of modifying only the selected bit for this function, */
/* to not interfere with bits with HW property "rs". */
MODIFY_REG(ADCx->CR,
8001d74: 687b ldr r3, [r7, #4]
8001d76: 689b ldr r3, [r3, #8]
8001d78: 4a04 ldr r2, [pc, #16] ; (8001d8c <LL_ADC_Enable+0x20>)
8001d7a: 4013 ands r3, r2
8001d7c: 2201 movs r2, #1
8001d7e: 431a orrs r2, r3
8001d80: 687b ldr r3, [r7, #4]
8001d82: 609a str r2, [r3, #8]
ADC_CR_BITS_PROPERTY_RS,
ADC_CR_ADEN);
}
8001d84: 46c0 nop ; (mov r8, r8)
8001d86: 46bd mov sp, r7
8001d88: b002 add sp, #8
8001d8a: bd80 pop {r7, pc}
8001d8c: 7fffffe8 .word 0x7fffffe8
08001d90 <LL_ADC_Disable>:
* @rmtoll CR ADDIS LL_ADC_Disable
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
{
8001d90: b580 push {r7, lr}
8001d92: b082 sub sp, #8
8001d94: af00 add r7, sp, #0
8001d96: 6078 str r0, [r7, #4]
/* Note: Write register with some additional bits forced to state reset */
/* instead of modifying only the selected bit for this function, */
/* to not interfere with bits with HW property "rs". */
MODIFY_REG(ADCx->CR,
8001d98: 687b ldr r3, [r7, #4]
8001d9a: 689b ldr r3, [r3, #8]
8001d9c: 4a04 ldr r2, [pc, #16] ; (8001db0 <LL_ADC_Disable+0x20>)
8001d9e: 4013 ands r3, r2
8001da0: 2202 movs r2, #2
8001da2: 431a orrs r2, r3
8001da4: 687b ldr r3, [r7, #4]
8001da6: 609a str r2, [r3, #8]
ADC_CR_BITS_PROPERTY_RS,
ADC_CR_ADDIS);
}
8001da8: 46c0 nop ; (mov r8, r8)
8001daa: 46bd mov sp, r7
8001dac: b002 add sp, #8
8001dae: bd80 pop {r7, pc}
8001db0: 7fffffe8 .word 0x7fffffe8
08001db4 <LL_ADC_IsEnabled>:
* @rmtoll CR ADEN LL_ADC_IsEnabled
* @param ADCx ADC instance
* @retval 0: ADC is disabled, 1: ADC is enabled.
*/
__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
{
8001db4: b580 push {r7, lr}
8001db6: b082 sub sp, #8
8001db8: af00 add r7, sp, #0
8001dba: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
8001dbc: 687b ldr r3, [r7, #4]
8001dbe: 689b ldr r3, [r3, #8]
8001dc0: 2201 movs r2, #1
8001dc2: 4013 ands r3, r2
8001dc4: 2b01 cmp r3, #1
8001dc6: d101 bne.n 8001dcc <LL_ADC_IsEnabled+0x18>
8001dc8: 2301 movs r3, #1
8001dca: e000 b.n 8001dce <LL_ADC_IsEnabled+0x1a>
8001dcc: 2300 movs r3, #0
}
8001dce: 0018 movs r0, r3
8001dd0: 46bd mov sp, r7
8001dd2: b002 add sp, #8
8001dd4: bd80 pop {r7, pc}
08001dd6 <LL_ADC_IsDisableOngoing>:
* @rmtoll CR ADDIS LL_ADC_IsDisableOngoing
* @param ADCx ADC instance
* @retval 0: no ADC disable command on going.
*/
__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx)
{
8001dd6: b580 push {r7, lr}
8001dd8: b082 sub sp, #8
8001dda: af00 add r7, sp, #0
8001ddc: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);
8001dde: 687b ldr r3, [r7, #4]
8001de0: 689b ldr r3, [r3, #8]
8001de2: 2202 movs r2, #2
8001de4: 4013 ands r3, r2
8001de6: 2b02 cmp r3, #2
8001de8: d101 bne.n 8001dee <LL_ADC_IsDisableOngoing+0x18>
8001dea: 2301 movs r3, #1
8001dec: e000 b.n 8001df0 <LL_ADC_IsDisableOngoing+0x1a>
8001dee: 2300 movs r3, #0
}
8001df0: 0018 movs r0, r3
8001df2: 46bd mov sp, r7
8001df4: b002 add sp, #8
8001df6: bd80 pop {r7, pc}
08001df8 <LL_ADC_REG_StartConversion>:
* @rmtoll CR ADSTART LL_ADC_REG_StartConversion
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
{
8001df8: b580 push {r7, lr}
8001dfa: b082 sub sp, #8
8001dfc: af00 add r7, sp, #0
8001dfe: 6078 str r0, [r7, #4]
/* Note: Write register with some additional bits forced to state reset */
/* instead of modifying only the selected bit for this function, */
/* to not interfere with bits with HW property "rs". */
MODIFY_REG(ADCx->CR,
8001e00: 687b ldr r3, [r7, #4]
8001e02: 689b ldr r3, [r3, #8]
8001e04: 4a04 ldr r2, [pc, #16] ; (8001e18 <LL_ADC_REG_StartConversion+0x20>)
8001e06: 4013 ands r3, r2
8001e08: 2204 movs r2, #4
8001e0a: 431a orrs r2, r3
8001e0c: 687b ldr r3, [r7, #4]
8001e0e: 609a str r2, [r3, #8]
ADC_CR_BITS_PROPERTY_RS,
ADC_CR_ADSTART);
}
8001e10: 46c0 nop ; (mov r8, r8)
8001e12: 46bd mov sp, r7
8001e14: b002 add sp, #8
8001e16: bd80 pop {r7, pc}
8001e18: 7fffffe8 .word 0x7fffffe8
08001e1c <LL_ADC_REG_IsConversionOngoing>:
* @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing
* @param ADCx ADC instance
* @retval 0: no conversion is on going on ADC group regular.
*/
__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx)
{
8001e1c: b580 push {r7, lr}
8001e1e: b082 sub sp, #8
8001e20: af00 add r7, sp, #0
8001e22: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
8001e24: 687b ldr r3, [r7, #4]
8001e26: 689b ldr r3, [r3, #8]
8001e28: 2204 movs r2, #4
8001e2a: 4013 ands r3, r2
8001e2c: 2b04 cmp r3, #4
8001e2e: d101 bne.n 8001e34 <LL_ADC_REG_IsConversionOngoing+0x18>
8001e30: 2301 movs r3, #1
8001e32: e000 b.n 8001e36 <LL_ADC_REG_IsConversionOngoing+0x1a>
8001e34: 2300 movs r3, #0
}
8001e36: 0018 movs r0, r3
8001e38: 46bd mov sp, r7
8001e3a: b002 add sp, #8
8001e3c: bd80 pop {r7, pc}
...
08001e40 <HAL_ADC_Init>:
* of structure "ADC_InitTypeDef".
* @param hadc ADC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
{
8001e40: b580 push {r7, lr}
8001e42: b088 sub sp, #32
8001e44: af00 add r7, sp, #0
8001e46: 6078 str r0, [r7, #4]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
8001e48: 231f movs r3, #31
8001e4a: 18fb adds r3, r7, r3
8001e4c: 2200 movs r2, #0
8001e4e: 701a strb r2, [r3, #0]
uint32_t tmpCFGR1 = 0UL;
8001e50: 2300 movs r3, #0
8001e52: 61bb str r3, [r7, #24]
uint32_t tmpCFGR2 = 0UL;
8001e54: 2300 movs r3, #0
8001e56: 617b str r3, [r7, #20]
uint32_t tmp_adc_reg_is_conversion_on_going;
__IO uint32_t wait_loop_index = 0UL;
8001e58: 2300 movs r3, #0
8001e5a: 60fb str r3, [r7, #12]
/* Check ADC handle */
if (hadc == NULL)
8001e5c: 687b ldr r3, [r7, #4]
8001e5e: 2b00 cmp r3, #0
8001e60: d101 bne.n 8001e66 <HAL_ADC_Init+0x26>
{
return HAL_ERROR;
8001e62: 2301 movs r3, #1
8001e64: e17f b.n 8002166 <HAL_ADC_Init+0x326>
/* continuous mode is disabled. */
assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE)));
/* Actions performed only if ADC is coming from state reset: */
/* - Initialization of ADC MSP */
if (hadc->State == HAL_ADC_STATE_RESET)
8001e66: 687b ldr r3, [r7, #4]
8001e68: 6d9b ldr r3, [r3, #88] ; 0x58
8001e6a: 2b00 cmp r3, #0
8001e6c: d10a bne.n 8001e84 <HAL_ADC_Init+0x44>
/* Init the low level hardware */
hadc->MspInitCallback(hadc);
#else
/* Init the low level hardware */
HAL_ADC_MspInit(hadc);
8001e6e: 687b ldr r3, [r7, #4]
8001e70: 0018 movs r0, r3
8001e72: f7fe fb51 bl 8000518 <HAL_ADC_MspInit>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Set ADC error code to none */
ADC_CLEAR_ERRORCODE(hadc);
8001e76: 687b ldr r3, [r7, #4]
8001e78: 2200 movs r2, #0
8001e7a: 65da str r2, [r3, #92] ; 0x5c
/* Initialize Lock */
hadc->Lock = HAL_UNLOCKED;
8001e7c: 687b ldr r3, [r7, #4]
8001e7e: 2254 movs r2, #84 ; 0x54
8001e80: 2100 movs r1, #0
8001e82: 5499 strb r1, [r3, r2]
}
if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
8001e84: 687b ldr r3, [r7, #4]
8001e86: 681b ldr r3, [r3, #0]
8001e88: 0018 movs r0, r3
8001e8a: f7ff ff5b bl 8001d44 <LL_ADC_IsInternalRegulatorEnabled>
8001e8e: 1e03 subs r3, r0, #0
8001e90: d115 bne.n 8001ebe <HAL_ADC_Init+0x7e>
{
/* Enable ADC internal voltage regulator */
LL_ADC_EnableInternalRegulator(hadc->Instance);
8001e92: 687b ldr r3, [r7, #4]
8001e94: 681b ldr r3, [r3, #0]
8001e96: 0018 movs r0, r3
8001e98: f7ff ff40 bl 8001d1c <LL_ADC_EnableInternalRegulator>
/* Delay for ADC stabilization time */
/* Wait loop initialization and execution */
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */
wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
8001e9c: 4bb4 ldr r3, [pc, #720] ; (8002170 <HAL_ADC_Init+0x330>)
8001e9e: 681b ldr r3, [r3, #0]
8001ea0: 49b4 ldr r1, [pc, #720] ; (8002174 <HAL_ADC_Init+0x334>)
8001ea2: 0018 movs r0, r3
8001ea4: f7fe f92e bl 8000104 <__udivsi3>
8001ea8: 0003 movs r3, r0
8001eaa: 3301 adds r3, #1
8001eac: 005b lsls r3, r3, #1
8001eae: 60fb str r3, [r7, #12]
while (wait_loop_index != 0UL)
8001eb0: e002 b.n 8001eb8 <HAL_ADC_Init+0x78>
{
wait_loop_index--;
8001eb2: 68fb ldr r3, [r7, #12]
8001eb4: 3b01 subs r3, #1
8001eb6: 60fb str r3, [r7, #12]
while (wait_loop_index != 0UL)
8001eb8: 68fb ldr r3, [r7, #12]
8001eba: 2b00 cmp r3, #0
8001ebc: d1f9 bne.n 8001eb2 <HAL_ADC_Init+0x72>
}
/* Verification that ADC voltage regulator is correctly enabled, whether */
/* or not ADC is coming from state reset (if any potential problem of */
/* clocking, voltage regulator would not be enabled). */
if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
8001ebe: 687b ldr r3, [r7, #4]
8001ec0: 681b ldr r3, [r3, #0]
8001ec2: 0018 movs r0, r3
8001ec4: f7ff ff3e bl 8001d44 <LL_ADC_IsInternalRegulatorEnabled>
8001ec8: 1e03 subs r3, r0, #0
8001eca: d10f bne.n 8001eec <HAL_ADC_Init+0xac>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
8001ecc: 687b ldr r3, [r7, #4]
8001ece: 6d9b ldr r3, [r3, #88] ; 0x58
8001ed0: 2210 movs r2, #16
8001ed2: 431a orrs r2, r3
8001ed4: 687b ldr r3, [r7, #4]
8001ed6: 659a str r2, [r3, #88] ; 0x58
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8001ed8: 687b ldr r3, [r7, #4]
8001eda: 6ddb ldr r3, [r3, #92] ; 0x5c
8001edc: 2201 movs r2, #1
8001ede: 431a orrs r2, r3
8001ee0: 687b ldr r3, [r7, #4]
8001ee2: 65da str r2, [r3, #92] ; 0x5c
tmp_hal_status = HAL_ERROR;
8001ee4: 231f movs r3, #31
8001ee6: 18fb adds r3, r7, r3
8001ee8: 2201 movs r2, #1
8001eea: 701a strb r2, [r3, #0]
/* Configuration of ADC parameters if previous preliminary actions are */
/* correctly completed and if there is no conversion on going on regular */
/* group (ADC may already be enabled at this point if HAL_ADC_Init() is */
/* called to update a parameter on the fly). */
tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
8001eec: 687b ldr r3, [r7, #4]
8001eee: 681b ldr r3, [r3, #0]
8001ef0: 0018 movs r0, r3
8001ef2: f7ff ff93 bl 8001e1c <LL_ADC_REG_IsConversionOngoing>
8001ef6: 0003 movs r3, r0
8001ef8: 613b str r3, [r7, #16]
if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
8001efa: 687b ldr r3, [r7, #4]
8001efc: 6d9b ldr r3, [r3, #88] ; 0x58
8001efe: 2210 movs r2, #16
8001f00: 4013 ands r3, r2
8001f02: d000 beq.n 8001f06 <HAL_ADC_Init+0xc6>
8001f04: e122 b.n 800214c <HAL_ADC_Init+0x30c>
&& (tmp_adc_reg_is_conversion_on_going == 0UL)
8001f06: 693b ldr r3, [r7, #16]
8001f08: 2b00 cmp r3, #0
8001f0a: d000 beq.n 8001f0e <HAL_ADC_Init+0xce>
8001f0c: e11e b.n 800214c <HAL_ADC_Init+0x30c>
)
{
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
8001f0e: 687b ldr r3, [r7, #4]
8001f10: 6d9b ldr r3, [r3, #88] ; 0x58
8001f12: 4a99 ldr r2, [pc, #612] ; (8002178 <HAL_ADC_Init+0x338>)
8001f14: 4013 ands r3, r2
8001f16: 2202 movs r2, #2
8001f18: 431a orrs r2, r3
8001f1a: 687b ldr r3, [r7, #4]
8001f1c: 659a str r2, [r3, #88] ; 0x58
/* - DMA continuous request */
/* - Trigger frequency mode */
/* Note: If low power mode AutoPowerOff is enabled, ADC enable */
/* and disable phases are performed automatically by hardware */
/* (in this case, flag ADC_FLAG_RDY is not set). */
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
8001f1e: 687b ldr r3, [r7, #4]
8001f20: 681b ldr r3, [r3, #0]
8001f22: 0018 movs r0, r3
8001f24: f7ff ff46 bl 8001db4 <LL_ADC_IsEnabled>
8001f28: 1e03 subs r3, r0, #0
8001f2a: d000 beq.n 8001f2e <HAL_ADC_Init+0xee>
8001f2c: e0ad b.n 800208a <HAL_ADC_Init+0x24a>
/* without needing to reconfigure all other ADC groups/channels */
/* parameters): */
/* - internal measurement paths (VrefInt, ...) */
/* (set into HAL_ADC_ConfigChannel() ) */
tmpCFGR1 |= (hadc->Init.Resolution |
8001f2e: 687b ldr r3, [r7, #4]
8001f30: 689a ldr r2, [r3, #8]
ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
8001f32: 687b ldr r3, [r7, #4]
8001f34: 7e1b ldrb r3, [r3, #24]
8001f36: 039b lsls r3, r3, #14
tmpCFGR1 |= (hadc->Init.Resolution |
8001f38: 431a orrs r2, r3
ADC_CFGR1_AUTOOFF((uint32_t)hadc->Init.LowPowerAutoPowerOff) |
8001f3a: 687b ldr r3, [r7, #4]
8001f3c: 7e5b ldrb r3, [r3, #25]
8001f3e: 03db lsls r3, r3, #15
ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
8001f40: 431a orrs r2, r3
ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
8001f42: 687b ldr r3, [r7, #4]
8001f44: 7e9b ldrb r3, [r3, #26]
8001f46: 035b lsls r3, r3, #13
ADC_CFGR1_AUTOOFF((uint32_t)hadc->Init.LowPowerAutoPowerOff) |
8001f48: 431a orrs r2, r3
ADC_CFGR1_OVERRUN(hadc->Init.Overrun) |
8001f4a: 687b ldr r3, [r7, #4]
8001f4c: 6b1b ldr r3, [r3, #48] ; 0x30
8001f4e: 2b00 cmp r3, #0
8001f50: d002 beq.n 8001f58 <HAL_ADC_Init+0x118>
8001f52: 2380 movs r3, #128 ; 0x80
8001f54: 015b lsls r3, r3, #5
8001f56: e000 b.n 8001f5a <HAL_ADC_Init+0x11a>
8001f58: 2300 movs r3, #0
ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
8001f5a: 431a orrs r2, r3
hadc->Init.DataAlign |
8001f5c: 687b ldr r3, [r7, #4]
8001f5e: 68db ldr r3, [r3, #12]
ADC_CFGR1_OVERRUN(hadc->Init.Overrun) |
8001f60: 431a orrs r2, r3
ADC_SCAN_SEQ_MODE(hadc->Init.ScanConvMode) |
8001f62: 687b ldr r3, [r7, #4]
8001f64: 691b ldr r3, [r3, #16]
8001f66: 2b00 cmp r3, #0
8001f68: da04 bge.n 8001f74 <HAL_ADC_Init+0x134>
8001f6a: 687b ldr r3, [r7, #4]
8001f6c: 691b ldr r3, [r3, #16]
8001f6e: 005b lsls r3, r3, #1
8001f70: 085b lsrs r3, r3, #1
8001f72: e001 b.n 8001f78 <HAL_ADC_Init+0x138>
8001f74: 2380 movs r3, #128 ; 0x80
8001f76: 039b lsls r3, r3, #14
hadc->Init.DataAlign |
8001f78: 431a orrs r2, r3
ADC_CFGR1_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests));
8001f7a: 687b ldr r3, [r7, #4]
8001f7c: 212c movs r1, #44 ; 0x2c
8001f7e: 5c5b ldrb r3, [r3, r1]
8001f80: 005b lsls r3, r3, #1
ADC_SCAN_SEQ_MODE(hadc->Init.ScanConvMode) |
8001f82: 4313 orrs r3, r2
tmpCFGR1 |= (hadc->Init.Resolution |
8001f84: 69ba ldr r2, [r7, #24]
8001f86: 4313 orrs r3, r2
8001f88: 61bb str r3, [r7, #24]
/* Update setting of discontinuous mode only if continuous mode is disabled */
if (hadc->Init.DiscontinuousConvMode == ENABLE)
8001f8a: 687b ldr r3, [r7, #4]
8001f8c: 2220 movs r2, #32
8001f8e: 5c9b ldrb r3, [r3, r2]
8001f90: 2b01 cmp r3, #1
8001f92: d115 bne.n 8001fc0 <HAL_ADC_Init+0x180>
{
if (hadc->Init.ContinuousConvMode == DISABLE)
8001f94: 687b ldr r3, [r7, #4]
8001f96: 7e9b ldrb r3, [r3, #26]
8001f98: 2b00 cmp r3, #0
8001f9a: d105 bne.n 8001fa8 <HAL_ADC_Init+0x168>
{
/* Enable the selected ADC group regular discontinuous mode */
tmpCFGR1 |= ADC_CFGR1_DISCEN;
8001f9c: 69bb ldr r3, [r7, #24]
8001f9e: 2280 movs r2, #128 ; 0x80
8001fa0: 0252 lsls r2, r2, #9
8001fa2: 4313 orrs r3, r2
8001fa4: 61bb str r3, [r7, #24]
8001fa6: e00b b.n 8001fc0 <HAL_ADC_Init+0x180>
/* ADC regular group discontinuous was intended to be enabled, */
/* but ADC regular group modes continuous and sequencer discontinuous */
/* cannot be enabled simultaneously. */
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
8001fa8: 687b ldr r3, [r7, #4]
8001faa: 6d9b ldr r3, [r3, #88] ; 0x58
8001fac: 2220 movs r2, #32
8001fae: 431a orrs r2, r3
8001fb0: 687b ldr r3, [r7, #4]
8001fb2: 659a str r2, [r3, #88] ; 0x58
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8001fb4: 687b ldr r3, [r7, #4]
8001fb6: 6ddb ldr r3, [r3, #92] ; 0x5c
8001fb8: 2201 movs r2, #1
8001fba: 431a orrs r2, r3
8001fbc: 687b ldr r3, [r7, #4]
8001fbe: 65da str r2, [r3, #92] ; 0x5c
/* Enable external trigger if trigger selection is different of software */
/* start. */
/* Note: This configuration keeps the hardware feature of parameter */
/* ExternalTrigConvEdge "trigger edge none" equivalent to */
/* software start. */
if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
8001fc0: 687b ldr r3, [r7, #4]
8001fc2: 6a5b ldr r3, [r3, #36] ; 0x24
8001fc4: 2b00 cmp r3, #0
8001fc6: d00a beq.n 8001fde <HAL_ADC_Init+0x19e>
{
tmpCFGR1 |= ((hadc->Init.ExternalTrigConv & ADC_CFGR1_EXTSEL) |
8001fc8: 687b ldr r3, [r7, #4]
8001fca: 6a5a ldr r2, [r3, #36] ; 0x24
8001fcc: 23e0 movs r3, #224 ; 0xe0
8001fce: 005b lsls r3, r3, #1
8001fd0: 401a ands r2, r3
hadc->Init.ExternalTrigConvEdge);
8001fd2: 687b ldr r3, [r7, #4]
8001fd4: 6a9b ldr r3, [r3, #40] ; 0x28
tmpCFGR1 |= ((hadc->Init.ExternalTrigConv & ADC_CFGR1_EXTSEL) |
8001fd6: 4313 orrs r3, r2
8001fd8: 69ba ldr r2, [r7, #24]
8001fda: 4313 orrs r3, r2
8001fdc: 61bb str r3, [r7, #24]
}
/* Update ADC configuration register with previous settings */
MODIFY_REG(hadc->Instance->CFGR1,
8001fde: 687b ldr r3, [r7, #4]
8001fe0: 681b ldr r3, [r3, #0]
8001fe2: 68db ldr r3, [r3, #12]
8001fe4: 4a65 ldr r2, [pc, #404] ; (800217c <HAL_ADC_Init+0x33c>)
8001fe6: 4013 ands r3, r2
8001fe8: 0019 movs r1, r3
8001fea: 687b ldr r3, [r7, #4]
8001fec: 681b ldr r3, [r3, #0]
8001fee: 69ba ldr r2, [r7, #24]
8001ff0: 430a orrs r2, r1
8001ff2: 60da str r2, [r3, #12]
ADC_CFGR1_ALIGN |
ADC_CFGR1_SCANDIR |
ADC_CFGR1_DMACFG,
tmpCFGR1);
tmpCFGR2 |= ((hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) |
8001ff4: 687b ldr r3, [r7, #4]
8001ff6: 685b ldr r3, [r3, #4]
8001ff8: 0f9b lsrs r3, r3, #30
8001ffa: 079a lsls r2, r3, #30
hadc->Init.TriggerFrequencyMode
8001ffc: 687b ldr r3, [r7, #4]
8001ffe: 6cdb ldr r3, [r3, #76] ; 0x4c
tmpCFGR2 |= ((hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) |
8002000: 4313 orrs r3, r2
8002002: 697a ldr r2, [r7, #20]
8002004: 4313 orrs r3, r2
8002006: 617b str r3, [r7, #20]
);
if (hadc->Init.OversamplingMode == ENABLE)
8002008: 687b ldr r3, [r7, #4]
800200a: 223c movs r2, #60 ; 0x3c
800200c: 5c9b ldrb r3, [r3, r2]
800200e: 2b01 cmp r3, #1
8002010: d111 bne.n 8002036 <HAL_ADC_Init+0x1f6>
{
tmpCFGR2 |= (ADC_CFGR2_OVSE |
(hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) |
8002012: 687b ldr r3, [r7, #4]
8002014: 685b ldr r3, [r3, #4]
8002016: 0f9b lsrs r3, r3, #30
8002018: 079a lsls r2, r3, #30
hadc->Init.Oversampling.Ratio |
800201a: 687b ldr r3, [r7, #4]
800201c: 6c1b ldr r3, [r3, #64] ; 0x40
(hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) |
800201e: 431a orrs r2, r3
hadc->Init.Oversampling.RightBitShift |
8002020: 687b ldr r3, [r7, #4]
8002022: 6c5b ldr r3, [r3, #68] ; 0x44
hadc->Init.Oversampling.Ratio |
8002024: 431a orrs r2, r3
hadc->Init.Oversampling.TriggeredMode
8002026: 687b ldr r3, [r7, #4]
8002028: 6c9b ldr r3, [r3, #72] ; 0x48
hadc->Init.Oversampling.RightBitShift |
800202a: 431a orrs r2, r3
tmpCFGR2 |= (ADC_CFGR2_OVSE |
800202c: 697b ldr r3, [r7, #20]
800202e: 4313 orrs r3, r2
8002030: 2201 movs r2, #1
8002032: 4313 orrs r3, r2
8002034: 617b str r3, [r7, #20]
);
}
MODIFY_REG(hadc->Instance->CFGR2,
8002036: 687b ldr r3, [r7, #4]
8002038: 681b ldr r3, [r3, #0]
800203a: 691b ldr r3, [r3, #16]
800203c: 4a50 ldr r2, [pc, #320] ; (8002180 <HAL_ADC_Init+0x340>)
800203e: 4013 ands r3, r2
8002040: 0019 movs r1, r3
8002042: 687b ldr r3, [r7, #4]
8002044: 681b ldr r3, [r3, #0]
8002046: 697a ldr r2, [r7, #20]
8002048: 430a orrs r2, r1
800204a: 611a str r2, [r3, #16]
ADC_CFGR2_TOVS,
tmpCFGR2);
/* Configuration of ADC clock mode: asynchronous clock source */
/* with selectable prescaler. */
if (((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV1) &&
800204c: 687b ldr r3, [r7, #4]
800204e: 685a ldr r2, [r3, #4]
8002050: 23c0 movs r3, #192 ; 0xc0
8002052: 061b lsls r3, r3, #24
8002054: 429a cmp r2, r3
8002056: d018 beq.n 800208a <HAL_ADC_Init+0x24a>
((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV2) &&
8002058: 687b ldr r3, [r7, #4]
800205a: 685a ldr r2, [r3, #4]
if (((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV1) &&
800205c: 2380 movs r3, #128 ; 0x80
800205e: 05db lsls r3, r3, #23
8002060: 429a cmp r2, r3
8002062: d012 beq.n 800208a <HAL_ADC_Init+0x24a>
((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV4))
8002064: 687b ldr r3, [r7, #4]
8002066: 685a ldr r2, [r3, #4]
((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV2) &&
8002068: 2380 movs r3, #128 ; 0x80
800206a: 061b lsls r3, r3, #24
800206c: 429a cmp r2, r3
800206e: d00c beq.n 800208a <HAL_ADC_Init+0x24a>
{
MODIFY_REG(ADC1_COMMON->CCR,
8002070: 4b44 ldr r3, [pc, #272] ; (8002184 <HAL_ADC_Init+0x344>)
8002072: 681b ldr r3, [r3, #0]
8002074: 4a44 ldr r2, [pc, #272] ; (8002188 <HAL_ADC_Init+0x348>)
8002076: 4013 ands r3, r2
8002078: 0019 movs r1, r3
800207a: 687b ldr r3, [r7, #4]
800207c: 685a ldr r2, [r3, #4]
800207e: 23f0 movs r3, #240 ; 0xf0
8002080: 039b lsls r3, r3, #14
8002082: 401a ands r2, r3
8002084: 4b3f ldr r3, [pc, #252] ; (8002184 <HAL_ADC_Init+0x344>)
8002086: 430a orrs r2, r1
8002088: 601a str r2, [r3, #0]
hadc->Init.ClockPrescaler & ADC_CCR_PRESC);
}
}
/* Channel sampling time configuration */
LL_ADC_SetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_1, hadc->Init.SamplingTimeCommon1);
800208a: 687b ldr r3, [r7, #4]
800208c: 6818 ldr r0, [r3, #0]
800208e: 687b ldr r3, [r7, #4]
8002090: 6b5b ldr r3, [r3, #52] ; 0x34
8002092: 001a movs r2, r3
8002094: 2100 movs r1, #0
8002096: f7ff fd90 bl 8001bba <LL_ADC_SetSamplingTimeCommonChannels>
LL_ADC_SetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_2, hadc->Init.SamplingTimeCommon2);
800209a: 687b ldr r3, [r7, #4]
800209c: 6818 ldr r0, [r3, #0]
800209e: 687b ldr r3, [r7, #4]
80020a0: 6b9b ldr r3, [r3, #56] ; 0x38
80020a2: 493a ldr r1, [pc, #232] ; (800218c <HAL_ADC_Init+0x34c>)
80020a4: 001a movs r2, r3
80020a6: f7ff fd88 bl 8001bba <LL_ADC_SetSamplingTimeCommonChannels>
/* emulated by software for alignment over all STM32 devices. */
/* - if scan mode is enabled, regular channels sequence length is set to */
/* parameter "NbrOfConversion". */
/* Channels must be configured into each rank using function */
/* "HAL_ADC_ConfigChannel()". */
if (hadc->Init.ScanConvMode == ADC_SCAN_DISABLE)
80020aa: 687b ldr r3, [r7, #4]
80020ac: 691b ldr r3, [r3, #16]
80020ae: 2b00 cmp r3, #0
80020b0: d109 bne.n 80020c6 <HAL_ADC_Init+0x286>
{
/* Set sequencer scan length by clearing ranks above rank 1 */
/* and do not modify rank 1 value. */
SET_BIT(hadc->Instance->CHSELR,
80020b2: 687b ldr r3, [r7, #4]
80020b4: 681b ldr r3, [r3, #0]
80020b6: 6a9a ldr r2, [r3, #40] ; 0x28
80020b8: 687b ldr r3, [r7, #4]
80020ba: 681b ldr r3, [r3, #0]
80020bc: 2110 movs r1, #16
80020be: 4249 negs r1, r1
80020c0: 430a orrs r2, r1
80020c2: 629a str r2, [r3, #40] ; 0x28
80020c4: e018 b.n 80020f8 <HAL_ADC_Init+0x2b8>
ADC_CHSELR_SQ2_TO_SQ8);
}
else if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
80020c6: 687b ldr r3, [r7, #4]
80020c8: 691a ldr r2, [r3, #16]
80020ca: 2380 movs r3, #128 ; 0x80
80020cc: 039b lsls r3, r3, #14
80020ce: 429a cmp r2, r3
80020d0: d112 bne.n 80020f8 <HAL_ADC_Init+0x2b8>
/* therefore after the first call of "HAL_ADC_Init()", */
/* each rank corresponding to parameter "NbrOfConversion" */
/* must be set using "HAL_ADC_ConfigChannel()". */
/* - Set sequencer scan length by clearing ranks above maximum rank */
/* and do not modify other ranks value. */
MODIFY_REG(hadc->Instance->CHSELR,
80020d2: 687b ldr r3, [r7, #4]
80020d4: 681b ldr r3, [r3, #0]
80020d6: 6a9b ldr r3, [r3, #40] ; 0x28
80020d8: 687b ldr r3, [r7, #4]
80020da: 69db ldr r3, [r3, #28]
80020dc: 3b01 subs r3, #1
80020de: 009b lsls r3, r3, #2
80020e0: 221c movs r2, #28
80020e2: 4013 ands r3, r2
80020e4: 2210 movs r2, #16
80020e6: 4252 negs r2, r2
80020e8: 409a lsls r2, r3
80020ea: 0011 movs r1, r2
80020ec: 687b ldr r3, [r7, #4]
80020ee: 6e1a ldr r2, [r3, #96] ; 0x60
80020f0: 687b ldr r3, [r7, #4]
80020f2: 681b ldr r3, [r3, #0]
80020f4: 430a orrs r2, r1
80020f6: 629a str r2, [r3, #40] ; 0x28
);
}
/* Check back that ADC registers have effectively been configured to */
/* ensure of no potential problem of ADC core peripheral clocking. */
if(LL_ADC_GetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_1)
80020f8: 687b ldr r3, [r7, #4]
80020fa: 681b ldr r3, [r3, #0]
80020fc: 2100 movs r1, #0
80020fe: 0018 movs r0, r3
8002100: f7ff fd78 bl 8001bf4 <LL_ADC_GetSamplingTimeCommonChannels>
8002104: 0002 movs r2, r0
== hadc->Init.SamplingTimeCommon1)
8002106: 687b ldr r3, [r7, #4]
8002108: 6b5b ldr r3, [r3, #52] ; 0x34
if(LL_ADC_GetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_1)
800210a: 429a cmp r2, r3
800210c: d10b bne.n 8002126 <HAL_ADC_Init+0x2e6>
{
/* Set ADC error code to none */
ADC_CLEAR_ERRORCODE(hadc);
800210e: 687b ldr r3, [r7, #4]
8002110: 2200 movs r2, #0
8002112: 65da str r2, [r3, #92] ; 0x5c
/* Set the ADC state */
ADC_STATE_CLR_SET(hadc->State,
8002114: 687b ldr r3, [r7, #4]
8002116: 6d9b ldr r3, [r3, #88] ; 0x58
8002118: 2203 movs r2, #3
800211a: 4393 bics r3, r2
800211c: 2201 movs r2, #1
800211e: 431a orrs r2, r3
8002120: 687b ldr r3, [r7, #4]
8002122: 659a str r2, [r3, #88] ; 0x58
if(LL_ADC_GetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_1)
8002124: e01c b.n 8002160 <HAL_ADC_Init+0x320>
HAL_ADC_STATE_READY);
}
else
{
/* Update ADC state machine to error */
ADC_STATE_CLR_SET(hadc->State,
8002126: 687b ldr r3, [r7, #4]
8002128: 6d9b ldr r3, [r3, #88] ; 0x58
800212a: 2212 movs r2, #18
800212c: 4393 bics r3, r2
800212e: 2210 movs r2, #16
8002130: 431a orrs r2, r3
8002132: 687b ldr r3, [r7, #4]
8002134: 659a str r2, [r3, #88] ; 0x58
HAL_ADC_STATE_BUSY_INTERNAL,
HAL_ADC_STATE_ERROR_INTERNAL);
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8002136: 687b ldr r3, [r7, #4]
8002138: 6ddb ldr r3, [r3, #92] ; 0x5c
800213a: 2201 movs r2, #1
800213c: 431a orrs r2, r3
800213e: 687b ldr r3, [r7, #4]
8002140: 65da str r2, [r3, #92] ; 0x5c
tmp_hal_status = HAL_ERROR;
8002142: 231f movs r3, #31
8002144: 18fb adds r3, r7, r3
8002146: 2201 movs r2, #1
8002148: 701a strb r2, [r3, #0]
if(LL_ADC_GetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_1)
800214a: e009 b.n 8002160 <HAL_ADC_Init+0x320>
}
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
800214c: 687b ldr r3, [r7, #4]
800214e: 6d9b ldr r3, [r3, #88] ; 0x58
8002150: 2210 movs r2, #16
8002152: 431a orrs r2, r3
8002154: 687b ldr r3, [r7, #4]
8002156: 659a str r2, [r3, #88] ; 0x58
tmp_hal_status = HAL_ERROR;
8002158: 231f movs r3, #31
800215a: 18fb adds r3, r7, r3
800215c: 2201 movs r2, #1
800215e: 701a strb r2, [r3, #0]
}
return tmp_hal_status;
8002160: 231f movs r3, #31
8002162: 18fb adds r3, r7, r3
8002164: 781b ldrb r3, [r3, #0]
}
8002166: 0018 movs r0, r3
8002168: 46bd mov sp, r7
800216a: b008 add sp, #32
800216c: bd80 pop {r7, pc}
800216e: 46c0 nop ; (mov r8, r8)
8002170: 2000000c .word 0x2000000c
8002174: 00030d40 .word 0x00030d40
8002178: fffffefd .word 0xfffffefd
800217c: fffe0201 .word 0xfffe0201
8002180: 1ffffc02 .word 0x1ffffc02
8002184: 40012708 .word 0x40012708
8002188: ffc3ffff .word 0xffc3ffff
800218c: 07ffff04 .word 0x07ffff04
08002190 <HAL_ADC_Start_IT>:
* before calling HAL_ADC_Start_IT().
* @param hadc ADC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc)
{
8002190: b5b0 push {r4, r5, r7, lr}
8002192: b084 sub sp, #16
8002194: af00 add r7, sp, #0
8002196: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
/* Perform ADC enable and conversion start if no conversion is on going */
if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
8002198: 687b ldr r3, [r7, #4]
800219a: 681b ldr r3, [r3, #0]
800219c: 0018 movs r0, r3
800219e: f7ff fe3d bl 8001e1c <LL_ADC_REG_IsConversionOngoing>
80021a2: 1e03 subs r3, r0, #0
80021a4: d15f bne.n 8002266 <HAL_ADC_Start_IT+0xd6>
{
__HAL_LOCK(hadc);
80021a6: 687b ldr r3, [r7, #4]
80021a8: 2254 movs r2, #84 ; 0x54
80021aa: 5c9b ldrb r3, [r3, r2]
80021ac: 2b01 cmp r3, #1
80021ae: d101 bne.n 80021b4 <HAL_ADC_Start_IT+0x24>
80021b0: 2302 movs r3, #2
80021b2: e05f b.n 8002274 <HAL_ADC_Start_IT+0xe4>
80021b4: 687b ldr r3, [r7, #4]
80021b6: 2254 movs r2, #84 ; 0x54
80021b8: 2101 movs r1, #1
80021ba: 5499 strb r1, [r3, r2]
/* Enable the ADC peripheral */
tmp_hal_status = ADC_Enable(hadc);
80021bc: 250f movs r5, #15
80021be: 197c adds r4, r7, r5
80021c0: 687b ldr r3, [r7, #4]
80021c2: 0018 movs r0, r3
80021c4: f000 fb68 bl 8002898 <ADC_Enable>
80021c8: 0003 movs r3, r0
80021ca: 7023 strb r3, [r4, #0]
/* Start conversion if ADC is effectively enabled */
if (tmp_hal_status == HAL_OK)
80021cc: 197b adds r3, r7, r5
80021ce: 781b ldrb r3, [r3, #0]
80021d0: 2b00 cmp r3, #0
80021d2: d143 bne.n 800225c <HAL_ADC_Start_IT+0xcc>
{
/* Set ADC state */
/* - Clear state bitfield related to regular group conversion results */
/* - Set state bitfield related to regular operation */
ADC_STATE_CLR_SET(hadc->State,
80021d4: 687b ldr r3, [r7, #4]
80021d6: 6d9b ldr r3, [r3, #88] ; 0x58
80021d8: 4a28 ldr r2, [pc, #160] ; (800227c <HAL_ADC_Start_IT+0xec>)
80021da: 4013 ands r3, r2
80021dc: 2280 movs r2, #128 ; 0x80
80021de: 0052 lsls r2, r2, #1
80021e0: 431a orrs r2, r3
80021e2: 687b ldr r3, [r7, #4]
80021e4: 659a str r2, [r3, #88] ; 0x58
HAL_ADC_STATE_REG_BUSY);
/* Set ADC error code */
/* Reset all ADC error code fields */
ADC_CLEAR_ERRORCODE(hadc);
80021e6: 687b ldr r3, [r7, #4]
80021e8: 2200 movs r2, #0
80021ea: 65da str r2, [r3, #92] ; 0x5c
/* Clear ADC group regular conversion flag and overrun flag */
/* (To ensure of no unknown state from potential previous ADC operations) */
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
80021ec: 687b ldr r3, [r7, #4]
80021ee: 681b ldr r3, [r3, #0]
80021f0: 221c movs r2, #28
80021f2: 601a str r2, [r3, #0]
/* Process unlocked */
/* Unlock before starting ADC conversions: in case of potential */
/* interruption, to let the process to ADC IRQ Handler. */
__HAL_UNLOCK(hadc);
80021f4: 687b ldr r3, [r7, #4]
80021f6: 2254 movs r2, #84 ; 0x54
80021f8: 2100 movs r1, #0
80021fa: 5499 strb r1, [r3, r2]
/* Disable all interruptions before enabling the desired ones */
__HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
80021fc: 687b ldr r3, [r7, #4]
80021fe: 681b ldr r3, [r3, #0]
8002200: 685a ldr r2, [r3, #4]
8002202: 687b ldr r3, [r7, #4]
8002204: 681b ldr r3, [r3, #0]
8002206: 211c movs r1, #28
8002208: 438a bics r2, r1
800220a: 605a str r2, [r3, #4]
/* Enable ADC end of conversion interrupt */
switch (hadc->Init.EOCSelection)
800220c: 687b ldr r3, [r7, #4]
800220e: 695b ldr r3, [r3, #20]
8002210: 2b08 cmp r3, #8
8002212: d108 bne.n 8002226 <HAL_ADC_Start_IT+0x96>
{
case ADC_EOC_SEQ_CONV:
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOS);
8002214: 687b ldr r3, [r7, #4]
8002216: 681b ldr r3, [r3, #0]
8002218: 685a ldr r2, [r3, #4]
800221a: 687b ldr r3, [r7, #4]
800221c: 681b ldr r3, [r3, #0]
800221e: 2108 movs r1, #8
8002220: 430a orrs r2, r1
8002222: 605a str r2, [r3, #4]
break;
8002224: e008 b.n 8002238 <HAL_ADC_Start_IT+0xa8>
/* case ADC_EOC_SINGLE_CONV */
default:
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
8002226: 687b ldr r3, [r7, #4]
8002228: 681b ldr r3, [r3, #0]
800222a: 685a ldr r2, [r3, #4]
800222c: 687b ldr r3, [r7, #4]
800222e: 681b ldr r3, [r3, #0]
8002230: 2104 movs r1, #4
8002232: 430a orrs r2, r1
8002234: 605a str r2, [r3, #4]
break;
8002236: 46c0 nop ; (mov r8, r8)
/* Enable ADC overrun interrupt */
/* If hadc->Init.Overrun is set to ADC_OVR_DATA_PRESERVED, only then is
ADC_IT_OVR enabled; otherwise data overwrite is considered as normal
behavior and no CPU time is lost for a non-processed interruption */
if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
8002238: 687b ldr r3, [r7, #4]
800223a: 6b1b ldr r3, [r3, #48] ; 0x30
800223c: 2b00 cmp r3, #0
800223e: d107 bne.n 8002250 <HAL_ADC_Start_IT+0xc0>
{
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
8002240: 687b ldr r3, [r7, #4]
8002242: 681b ldr r3, [r3, #0]
8002244: 685a ldr r2, [r3, #4]
8002246: 687b ldr r3, [r7, #4]
8002248: 681b ldr r3, [r3, #0]
800224a: 2110 movs r1, #16
800224c: 430a orrs r2, r1
800224e: 605a str r2, [r3, #4]
/* Enable conversion of regular group. */
/* If software start has been selected, conversion starts immediately. */
/* If external trigger has been selected, conversion will start at next */
/* trigger event. */
/* Start ADC group regular conversion */
LL_ADC_REG_StartConversion(hadc->Instance);
8002250: 687b ldr r3, [r7, #4]
8002252: 681b ldr r3, [r3, #0]
8002254: 0018 movs r0, r3
8002256: f7ff fdcf bl 8001df8 <LL_ADC_REG_StartConversion>
800225a: e008 b.n 800226e <HAL_ADC_Start_IT+0xde>
}
else
{
__HAL_UNLOCK(hadc);
800225c: 687b ldr r3, [r7, #4]
800225e: 2254 movs r2, #84 ; 0x54
8002260: 2100 movs r1, #0
8002262: 5499 strb r1, [r3, r2]
8002264: e003 b.n 800226e <HAL_ADC_Start_IT+0xde>
}
}
else
{
tmp_hal_status = HAL_BUSY;
8002266: 230f movs r3, #15
8002268: 18fb adds r3, r7, r3
800226a: 2202 movs r2, #2
800226c: 701a strb r2, [r3, #0]
}
return tmp_hal_status;
800226e: 230f movs r3, #15
8002270: 18fb adds r3, r7, r3
8002272: 781b ldrb r3, [r3, #0]
}
8002274: 0018 movs r0, r3
8002276: 46bd mov sp, r7
8002278: b004 add sp, #16
800227a: bdb0 pop {r4, r5, r7, pc}
800227c: fffff0fe .word 0xfffff0fe
08002280 <HAL_ADC_GetValue>:
* or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
* @param hadc ADC handle
* @retval ADC group regular conversion data
*/
uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc)
{
8002280: b580 push {r7, lr}
8002282: b082 sub sp, #8
8002284: af00 add r7, sp, #0
8002286: 6078 str r0, [r7, #4]
/* Note: EOC flag is not cleared here by software because automatically */
/* cleared by hardware when reading register DR. */
/* Return ADC converted value */
return hadc->Instance->DR;
8002288: 687b ldr r3, [r7, #4]
800228a: 681b ldr r3, [r3, #0]
800228c: 6c1b ldr r3, [r3, #64] ; 0x40
}
800228e: 0018 movs r0, r3
8002290: 46bd mov sp, r7
8002292: b002 add sp, #8
8002294: bd80 pop {r7, pc}
...
08002298 <HAL_ADC_IRQHandler>:
* @brief Handle ADC interrupt request.
* @param hadc ADC handle
* @retval None
*/
void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc)
{
8002298: b580 push {r7, lr}
800229a: b086 sub sp, #24
800229c: af00 add r7, sp, #0
800229e: 6078 str r0, [r7, #4]
uint32_t overrun_error = 0UL; /* flag set if overrun occurrence has to be considered as an error */
80022a0: 2300 movs r3, #0
80022a2: 617b str r3, [r7, #20]
uint32_t tmp_isr = hadc->Instance->ISR;
80022a4: 687b ldr r3, [r7, #4]
80022a6: 681b ldr r3, [r3, #0]
80022a8: 681b ldr r3, [r3, #0]
80022aa: 613b str r3, [r7, #16]
uint32_t tmp_ier = hadc->Instance->IER;
80022ac: 687b ldr r3, [r7, #4]
80022ae: 681b ldr r3, [r3, #0]
80022b0: 685b ldr r3, [r3, #4]
80022b2: 60fb str r3, [r7, #12]
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
/* ========== Check End of Sampling flag for ADC group regular ========== */
if (((tmp_isr & ADC_FLAG_EOSMP) == ADC_FLAG_EOSMP) && ((tmp_ier & ADC_IT_EOSMP) == ADC_IT_EOSMP))
80022b4: 693b ldr r3, [r7, #16]
80022b6: 2202 movs r2, #2
80022b8: 4013 ands r3, r2
80022ba: d017 beq.n 80022ec <HAL_ADC_IRQHandler+0x54>
80022bc: 68fb ldr r3, [r7, #12]
80022be: 2202 movs r2, #2
80022c0: 4013 ands r3, r2
80022c2: d013 beq.n 80022ec <HAL_ADC_IRQHandler+0x54>
{
/* Update state machine on end of sampling status if not in error state */
if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
80022c4: 687b ldr r3, [r7, #4]
80022c6: 6d9b ldr r3, [r3, #88] ; 0x58
80022c8: 2210 movs r2, #16
80022ca: 4013 ands r3, r2
80022cc: d106 bne.n 80022dc <HAL_ADC_IRQHandler+0x44>
{
/* Set ADC state */
SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
80022ce: 687b ldr r3, [r7, #4]
80022d0: 6d9b ldr r3, [r3, #88] ; 0x58
80022d2: 2280 movs r2, #128 ; 0x80
80022d4: 0112 lsls r2, r2, #4
80022d6: 431a orrs r2, r3
80022d8: 687b ldr r3, [r7, #4]
80022da: 659a str r2, [r3, #88] ; 0x58
/* End Of Sampling callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->EndOfSamplingCallback(hadc);
#else
HAL_ADCEx_EndOfSamplingCallback(hadc);
80022dc: 687b ldr r3, [r7, #4]
80022de: 0018 movs r0, r3
80022e0: f000 fd24 bl 8002d2c <HAL_ADCEx_EndOfSamplingCallback>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Clear regular group conversion flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
80022e4: 687b ldr r3, [r7, #4]
80022e6: 681b ldr r3, [r3, #0]
80022e8: 2202 movs r2, #2
80022ea: 601a str r2, [r3, #0]
}
/* ====== Check ADC group regular end of unitary conversion sequence conversions ===== */
if ((((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) ||
80022ec: 693b ldr r3, [r7, #16]
80022ee: 2204 movs r2, #4
80022f0: 4013 ands r3, r2
80022f2: d003 beq.n 80022fc <HAL_ADC_IRQHandler+0x64>
80022f4: 68fb ldr r3, [r7, #12]
80022f6: 2204 movs r2, #4
80022f8: 4013 ands r3, r2
80022fa: d107 bne.n 800230c <HAL_ADC_IRQHandler+0x74>
(((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS)))
80022fc: 693b ldr r3, [r7, #16]
80022fe: 2208 movs r2, #8
8002300: 4013 ands r3, r2
if ((((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) ||
8002302: d04d beq.n 80023a0 <HAL_ADC_IRQHandler+0x108>
(((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS)))
8002304: 68fb ldr r3, [r7, #12]
8002306: 2208 movs r2, #8
8002308: 4013 ands r3, r2
800230a: d049 beq.n 80023a0 <HAL_ADC_IRQHandler+0x108>
{
/* Update state machine on conversion status if not in error state */
if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
800230c: 687b ldr r3, [r7, #4]
800230e: 6d9b ldr r3, [r3, #88] ; 0x58
8002310: 2210 movs r2, #16
8002312: 4013 ands r3, r2
8002314: d106 bne.n 8002324 <HAL_ADC_IRQHandler+0x8c>
{
/* Set ADC state */
SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
8002316: 687b ldr r3, [r7, #4]
8002318: 6d9b ldr r3, [r3, #88] ; 0x58
800231a: 2280 movs r2, #128 ; 0x80
800231c: 0092 lsls r2, r2, #2
800231e: 431a orrs r2, r3
8002320: 687b ldr r3, [r7, #4]
8002322: 659a str r2, [r3, #88] ; 0x58
}
/* Determine whether any further conversion upcoming on group regular */
/* by external trigger, continuous mode or scan sequence on going */
/* to disable interruption. */
if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
8002324: 687b ldr r3, [r7, #4]
8002326: 681b ldr r3, [r3, #0]
8002328: 0018 movs r0, r3
800232a: f7ff fc7a bl 8001c22 <LL_ADC_REG_IsTriggerSourceSWStart>
800232e: 1e03 subs r3, r0, #0
8002330: d02e beq.n 8002390 <HAL_ADC_IRQHandler+0xf8>
&& (hadc->Init.ContinuousConvMode == DISABLE)
8002332: 687b ldr r3, [r7, #4]
8002334: 7e9b ldrb r3, [r3, #26]
8002336: 2b00 cmp r3, #0
8002338: d12a bne.n 8002390 <HAL_ADC_IRQHandler+0xf8>
)
{
/* If End of Sequence is reached, disable interrupts */
if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
800233a: 687b ldr r3, [r7, #4]
800233c: 681b ldr r3, [r3, #0]
800233e: 681b ldr r3, [r3, #0]
8002340: 2208 movs r2, #8
8002342: 4013 ands r3, r2
8002344: 2b08 cmp r3, #8
8002346: d123 bne.n 8002390 <HAL_ADC_IRQHandler+0xf8>
{
/* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
/* ADSTART==0 (no conversion on going) */
if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
8002348: 687b ldr r3, [r7, #4]
800234a: 681b ldr r3, [r3, #0]
800234c: 0018 movs r0, r3
800234e: f7ff fd65 bl 8001e1c <LL_ADC_REG_IsConversionOngoing>
8002352: 1e03 subs r3, r0, #0
8002354: d110 bne.n 8002378 <HAL_ADC_IRQHandler+0xe0>
{
/* Disable ADC end of single conversion interrupt on group regular */
/* Note: Overrun interrupt was enabled with EOC interrupt in */
/* HAL_Start_IT(), but is not disabled here because can be used */
/* by overrun IRQ process below. */
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
8002356: 687b ldr r3, [r7, #4]
8002358: 681b ldr r3, [r3, #0]
800235a: 685a ldr r2, [r3, #4]
800235c: 687b ldr r3, [r7, #4]
800235e: 681b ldr r3, [r3, #0]
8002360: 210c movs r1, #12
8002362: 438a bics r2, r1
8002364: 605a str r2, [r3, #4]
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
8002366: 687b ldr r3, [r7, #4]
8002368: 6d9b ldr r3, [r3, #88] ; 0x58
800236a: 4a56 ldr r2, [pc, #344] ; (80024c4 <HAL_ADC_IRQHandler+0x22c>)
800236c: 4013 ands r3, r2
800236e: 2201 movs r2, #1
8002370: 431a orrs r2, r3
8002372: 687b ldr r3, [r7, #4]
8002374: 659a str r2, [r3, #88] ; 0x58
8002376: e00b b.n 8002390 <HAL_ADC_IRQHandler+0xf8>
HAL_ADC_STATE_READY);
}
else
{
/* Change ADC state to error state */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
8002378: 687b ldr r3, [r7, #4]
800237a: 6d9b ldr r3, [r3, #88] ; 0x58
800237c: 2220 movs r2, #32
800237e: 431a orrs r2, r3
8002380: 687b ldr r3, [r7, #4]
8002382: 659a str r2, [r3, #88] ; 0x58
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8002384: 687b ldr r3, [r7, #4]
8002386: 6ddb ldr r3, [r3, #92] ; 0x5c
8002388: 2201 movs r2, #1
800238a: 431a orrs r2, r3
800238c: 687b ldr r3, [r7, #4]
800238e: 65da str r2, [r3, #92] ; 0x5c
/* possibility to use: */
/* " if ( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->ConvCpltCallback(hadc);
#else
HAL_ADC_ConvCpltCallback(hadc);
8002390: 687b ldr r3, [r7, #4]
8002392: 0018 movs r0, r3
8002394: f7fe fb08 bl 80009a8 <HAL_ADC_ConvCpltCallback>
/* Clear regular group conversion flag */
/* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */
/* conversion flags clear induces the release of the preserved data.*/
/* Therefore, if the preserved data value is needed, it must be */
/* read preliminarily into HAL_ADC_ConvCpltCallback(). */
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
8002398: 687b ldr r3, [r7, #4]
800239a: 681b ldr r3, [r3, #0]
800239c: 220c movs r2, #12
800239e: 601a str r2, [r3, #0]
}
/* ========== Check Analog watchdog 1 flag ========== */
if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1))
80023a0: 693b ldr r3, [r7, #16]
80023a2: 2280 movs r2, #128 ; 0x80
80023a4: 4013 ands r3, r2
80023a6: d012 beq.n 80023ce <HAL_ADC_IRQHandler+0x136>
80023a8: 68fb ldr r3, [r7, #12]
80023aa: 2280 movs r2, #128 ; 0x80
80023ac: 4013 ands r3, r2
80023ae: d00e beq.n 80023ce <HAL_ADC_IRQHandler+0x136>
{
/* Set ADC state */
SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
80023b0: 687b ldr r3, [r7, #4]
80023b2: 6d9b ldr r3, [r3, #88] ; 0x58
80023b4: 2280 movs r2, #128 ; 0x80
80023b6: 0252 lsls r2, r2, #9
80023b8: 431a orrs r2, r3
80023ba: 687b ldr r3, [r7, #4]
80023bc: 659a str r2, [r3, #88] ; 0x58
/* Level out of window 1 callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->LevelOutOfWindowCallback(hadc);
#else
HAL_ADC_LevelOutOfWindowCallback(hadc);
80023be: 687b ldr r3, [r7, #4]
80023c0: 0018 movs r0, r3
80023c2: f000 f881 bl 80024c8 <HAL_ADC_LevelOutOfWindowCallback>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Clear ADC analog watchdog flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
80023c6: 687b ldr r3, [r7, #4]
80023c8: 681b ldr r3, [r3, #0]
80023ca: 2280 movs r2, #128 ; 0x80
80023cc: 601a str r2, [r3, #0]
}
/* ========== Check analog watchdog 2 flag ========== */
if (((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) && ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2))
80023ce: 693a ldr r2, [r7, #16]
80023d0: 2380 movs r3, #128 ; 0x80
80023d2: 005b lsls r3, r3, #1
80023d4: 4013 ands r3, r2
80023d6: d014 beq.n 8002402 <HAL_ADC_IRQHandler+0x16a>
80023d8: 68fa ldr r2, [r7, #12]
80023da: 2380 movs r3, #128 ; 0x80
80023dc: 005b lsls r3, r3, #1
80023de: 4013 ands r3, r2
80023e0: d00f beq.n 8002402 <HAL_ADC_IRQHandler+0x16a>
{
/* Set ADC state */
SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
80023e2: 687b ldr r3, [r7, #4]
80023e4: 6d9b ldr r3, [r3, #88] ; 0x58
80023e6: 2280 movs r2, #128 ; 0x80
80023e8: 0292 lsls r2, r2, #10
80023ea: 431a orrs r2, r3
80023ec: 687b ldr r3, [r7, #4]
80023ee: 659a str r2, [r3, #88] ; 0x58
/* Level out of window 2 callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->LevelOutOfWindow2Callback(hadc);
#else
HAL_ADCEx_LevelOutOfWindow2Callback(hadc);
80023f0: 687b ldr r3, [r7, #4]
80023f2: 0018 movs r0, r3
80023f4: f000 fc8a bl 8002d0c <HAL_ADCEx_LevelOutOfWindow2Callback>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Clear ADC analog watchdog flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
80023f8: 687b ldr r3, [r7, #4]
80023fa: 681b ldr r3, [r3, #0]
80023fc: 2280 movs r2, #128 ; 0x80
80023fe: 0052 lsls r2, r2, #1
8002400: 601a str r2, [r3, #0]
}
/* ========== Check analog watchdog 3 flag ========== */
if (((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3))
8002402: 693a ldr r2, [r7, #16]
8002404: 2380 movs r3, #128 ; 0x80
8002406: 009b lsls r3, r3, #2
8002408: 4013 ands r3, r2
800240a: d014 beq.n 8002436 <HAL_ADC_IRQHandler+0x19e>
800240c: 68fa ldr r2, [r7, #12]
800240e: 2380 movs r3, #128 ; 0x80
8002410: 009b lsls r3, r3, #2
8002412: 4013 ands r3, r2
8002414: d00f beq.n 8002436 <HAL_ADC_IRQHandler+0x19e>
{
/* Set ADC state */
SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
8002416: 687b ldr r3, [r7, #4]
8002418: 6d9b ldr r3, [r3, #88] ; 0x58
800241a: 2280 movs r2, #128 ; 0x80
800241c: 02d2 lsls r2, r2, #11
800241e: 431a orrs r2, r3
8002420: 687b ldr r3, [r7, #4]
8002422: 659a str r2, [r3, #88] ; 0x58
/* Level out of window 3 callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->LevelOutOfWindow3Callback(hadc);
#else
HAL_ADCEx_LevelOutOfWindow3Callback(hadc);
8002424: 687b ldr r3, [r7, #4]
8002426: 0018 movs r0, r3
8002428: f000 fc78 bl 8002d1c <HAL_ADCEx_LevelOutOfWindow3Callback>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Clear ADC analog watchdog flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
800242c: 687b ldr r3, [r7, #4]
800242e: 681b ldr r3, [r3, #0]
8002430: 2280 movs r2, #128 ; 0x80
8002432: 0092 lsls r2, r2, #2
8002434: 601a str r2, [r3, #0]
}
/* ========== Check Overrun flag ========== */
if (((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) && ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR))
8002436: 693b ldr r3, [r7, #16]
8002438: 2210 movs r2, #16
800243a: 4013 ands r3, r2
800243c: d02b beq.n 8002496 <HAL_ADC_IRQHandler+0x1fe>
800243e: 68fb ldr r3, [r7, #12]
8002440: 2210 movs r2, #16
8002442: 4013 ands r3, r2
8002444: d027 beq.n 8002496 <HAL_ADC_IRQHandler+0x1fe>
/* overrun event is not considered as an error. */
/* (cf ref manual "Managing conversions without using the DMA and without */
/* overrun ") */
/* Exception for usage with DMA overrun event always considered as an */
/* error. */
if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
8002446: 687b ldr r3, [r7, #4]
8002448: 6b1b ldr r3, [r3, #48] ; 0x30
800244a: 2b00 cmp r3, #0
800244c: d102 bne.n 8002454 <HAL_ADC_IRQHandler+0x1bc>
{
overrun_error = 1UL;
800244e: 2301 movs r3, #1
8002450: 617b str r3, [r7, #20]
8002452: e008 b.n 8002466 <HAL_ADC_IRQHandler+0x1ce>
}
else
{
/* Check DMA configuration */
if (LL_ADC_REG_GetDMATransfer(hadc->Instance) != LL_ADC_REG_DMA_TRANSFER_NONE)
8002454: 687b ldr r3, [r7, #4]
8002456: 681b ldr r3, [r3, #0]
8002458: 0018 movs r0, r3
800245a: f7ff fc36 bl 8001cca <LL_ADC_REG_GetDMATransfer>
800245e: 1e03 subs r3, r0, #0
8002460: d001 beq.n 8002466 <HAL_ADC_IRQHandler+0x1ce>
{
overrun_error = 1UL;
8002462: 2301 movs r3, #1
8002464: 617b str r3, [r7, #20]
}
}
if (overrun_error == 1UL)
8002466: 697b ldr r3, [r7, #20]
8002468: 2b01 cmp r3, #1
800246a: d110 bne.n 800248e <HAL_ADC_IRQHandler+0x1f6>
{
/* Change ADC state to error state */
SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
800246c: 687b ldr r3, [r7, #4]
800246e: 6d9b ldr r3, [r3, #88] ; 0x58
8002470: 2280 movs r2, #128 ; 0x80
8002472: 00d2 lsls r2, r2, #3
8002474: 431a orrs r2, r3
8002476: 687b ldr r3, [r7, #4]
8002478: 659a str r2, [r3, #88] ; 0x58
/* Set ADC error code to overrun */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
800247a: 687b ldr r3, [r7, #4]
800247c: 6ddb ldr r3, [r3, #92] ; 0x5c
800247e: 2202 movs r2, #2
8002480: 431a orrs r2, r3
8002482: 687b ldr r3, [r7, #4]
8002484: 65da str r2, [r3, #92] ; 0x5c
/* Therefore, old ADC conversion data can be retrieved in */
/* function "HAL_ADC_ErrorCallback()". */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->ErrorCallback(hadc);
#else
HAL_ADC_ErrorCallback(hadc);
8002486: 687b ldr r3, [r7, #4]
8002488: 0018 movs r0, r3
800248a: f000 f825 bl 80024d8 <HAL_ADC_ErrorCallback>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
}
/* Clear ADC overrun flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
800248e: 687b ldr r3, [r7, #4]
8002490: 681b ldr r3, [r3, #0]
8002492: 2210 movs r2, #16
8002494: 601a str r2, [r3, #0]
}
/* ========== Check channel configuration ready flag ========== */
if (((tmp_isr & ADC_FLAG_CCRDY) == ADC_FLAG_CCRDY) && ((tmp_ier & ADC_IT_CCRDY) == ADC_IT_CCRDY))
8002496: 693a ldr r2, [r7, #16]
8002498: 2380 movs r3, #128 ; 0x80
800249a: 019b lsls r3, r3, #6
800249c: 4013 ands r3, r2
800249e: d00d beq.n 80024bc <HAL_ADC_IRQHandler+0x224>
80024a0: 68fa ldr r2, [r7, #12]
80024a2: 2380 movs r3, #128 ; 0x80
80024a4: 019b lsls r3, r3, #6
80024a6: 4013 ands r3, r2
80024a8: d008 beq.n 80024bc <HAL_ADC_IRQHandler+0x224>
{
/* Channel configuration ready callback */
HAL_ADCEx_ChannelConfigReadyCallback(hadc);
80024aa: 687b ldr r3, [r7, #4]
80024ac: 0018 movs r0, r3
80024ae: f000 fc45 bl 8002d3c <HAL_ADCEx_ChannelConfigReadyCallback>
/* Clear ADC analog watchdog flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_CCRDY);
80024b2: 687b ldr r3, [r7, #4]
80024b4: 681b ldr r3, [r3, #0]
80024b6: 2280 movs r2, #128 ; 0x80
80024b8: 0192 lsls r2, r2, #6
80024ba: 601a str r2, [r3, #0]
}
}
80024bc: 46c0 nop ; (mov r8, r8)
80024be: 46bd mov sp, r7
80024c0: b006 add sp, #24
80024c2: bd80 pop {r7, pc}
80024c4: fffffefe .word 0xfffffefe
080024c8 <HAL_ADC_LevelOutOfWindowCallback>:
* @brief Analog watchdog 1 callback in non-blocking mode.
* @param hadc ADC handle
* @retval None
*/
__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc)
{
80024c8: b580 push {r7, lr}
80024ca: b082 sub sp, #8
80024cc: af00 add r7, sp, #0
80024ce: 6078 str r0, [r7, #4]
UNUSED(hadc);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file.
*/
}
80024d0: 46c0 nop ; (mov r8, r8)
80024d2: 46bd mov sp, r7
80024d4: b002 add sp, #8
80024d6: bd80 pop {r7, pc}
080024d8 <HAL_ADC_ErrorCallback>:
* (this function is also clearing overrun flag)
* @param hadc ADC handle
* @retval None
*/
__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
{
80024d8: b580 push {r7, lr}
80024da: b082 sub sp, #8
80024dc: af00 add r7, sp, #0
80024de: 6078 str r0, [r7, #4]
UNUSED(hadc);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_ADC_ErrorCallback must be implemented in the user file.
*/
}
80024e0: 46c0 nop ; (mov r8, r8)
80024e2: 46bd mov sp, r7
80024e4: b002 add sp, #8
80024e6: bd80 pop {r7, pc}
080024e8 <HAL_ADC_ConfigChannel>:
* @param hadc ADC handle
* @param pConfig Structure of ADC channel assigned to ADC group regular.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *pConfig)
{
80024e8: b580 push {r7, lr}
80024ea: b086 sub sp, #24
80024ec: af00 add r7, sp, #0
80024ee: 6078 str r0, [r7, #4]
80024f0: 6039 str r1, [r7, #0]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
80024f2: 2317 movs r3, #23
80024f4: 18fb adds r3, r7, r3
80024f6: 2200 movs r2, #0
80024f8: 701a strb r2, [r3, #0]
uint32_t tmp_config_internal_channel;
__IO uint32_t wait_loop_index = 0UL;
80024fa: 2300 movs r3, #0
80024fc: 60fb str r3, [r7, #12]
assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
assert_param(IS_ADC_REGULAR_RANK(pConfig->Rank));
}
__HAL_LOCK(hadc);
80024fe: 687b ldr r3, [r7, #4]
8002500: 2254 movs r2, #84 ; 0x54
8002502: 5c9b ldrb r3, [r3, r2]
8002504: 2b01 cmp r3, #1
8002506: d101 bne.n 800250c <HAL_ADC_ConfigChannel+0x24>
8002508: 2302 movs r3, #2
800250a: e1c0 b.n 800288e <HAL_ADC_ConfigChannel+0x3a6>
800250c: 687b ldr r3, [r7, #4]
800250e: 2254 movs r2, #84 ; 0x54
8002510: 2101 movs r1, #1
8002512: 5499 strb r1, [r3, r2]
/* Parameters that can be updated when ADC is disabled or enabled without */
/* conversion on going on regular group: */
/* - Channel number */
/* - Channel sampling time */
/* - Management of internal measurement channels: VrefInt/TempSensor/Vbat */
if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
8002514: 687b ldr r3, [r7, #4]
8002516: 681b ldr r3, [r3, #0]
8002518: 0018 movs r0, r3
800251a: f7ff fc7f bl 8001e1c <LL_ADC_REG_IsConversionOngoing>
800251e: 1e03 subs r3, r0, #0
8002520: d000 beq.n 8002524 <HAL_ADC_ConfigChannel+0x3c>
8002522: e1a3 b.n 800286c <HAL_ADC_ConfigChannel+0x384>
/* If sequencer set to not fully configurable with channel rank set to */
/* none, remove the channel from the sequencer. */
/* Otherwise (sequencer set to fully configurable or to to not fully */
/* configurable with channel rank to be set), configure the selected */
/* channel. */
if (pConfig->Rank != ADC_RANK_NONE)
8002524: 683b ldr r3, [r7, #0]
8002526: 685b ldr r3, [r3, #4]
8002528: 2b02 cmp r3, #2
800252a: d100 bne.n 800252e <HAL_ADC_ConfigChannel+0x46>
800252c: e143 b.n 80027b6 <HAL_ADC_ConfigChannel+0x2ce>
/* Note: ADC channel configuration requires few ADC clock cycles */
/* to be ready. Processing of ADC settings in this function */
/* induce that a specific wait time is not necessary. */
/* For more details on ADC channel configuration ready, */
/* refer to function "LL_ADC_IsActiveFlag_CCRDY()". */
if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) ||
800252e: 687b ldr r3, [r7, #4]
8002530: 691a ldr r2, [r3, #16]
8002532: 2380 movs r3, #128 ; 0x80
8002534: 061b lsls r3, r3, #24
8002536: 429a cmp r2, r3
8002538: d004 beq.n 8002544 <HAL_ADC_ConfigChannel+0x5c>
(hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED_BACKWARD))
800253a: 687b ldr r3, [r7, #4]
800253c: 691b ldr r3, [r3, #16]
if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) ||
800253e: 4ac1 ldr r2, [pc, #772] ; (8002844 <HAL_ADC_ConfigChannel+0x35c>)
8002540: 4293 cmp r3, r2
8002542: d108 bne.n 8002556 <HAL_ADC_ConfigChannel+0x6e>
{
/* Sequencer set to not fully configurable: */
/* Set the channel by enabling the corresponding bitfield. */
LL_ADC_REG_SetSequencerChAdd(hadc->Instance, pConfig->Channel);
8002544: 687b ldr r3, [r7, #4]
8002546: 681a ldr r2, [r3, #0]
8002548: 683b ldr r3, [r7, #0]
800254a: 681b ldr r3, [r3, #0]
800254c: 0019 movs r1, r3
800254e: 0010 movs r0, r2
8002550: f7ff fb98 bl 8001c84 <LL_ADC_REG_SetSequencerChAdd>
8002554: e0c9 b.n 80026ea <HAL_ADC_ConfigChannel+0x202>
{
/* Sequencer set to fully configurable: */
/* Set the channel by entering it into the selected rank. */
/* Memorize the channel set into variable in HAL ADC handle */
MODIFY_REG(hadc->ADCGroupRegularSequencerRanks,
8002556: 687b ldr r3, [r7, #4]
8002558: 6e1a ldr r2, [r3, #96] ; 0x60
800255a: 683b ldr r3, [r7, #0]
800255c: 685b ldr r3, [r3, #4]
800255e: 211f movs r1, #31
8002560: 400b ands r3, r1
8002562: 210f movs r1, #15
8002564: 4099 lsls r1, r3
8002566: 000b movs r3, r1
8002568: 43db mvns r3, r3
800256a: 4013 ands r3, r2
800256c: 0019 movs r1, r3
800256e: 683b ldr r3, [r7, #0]
8002570: 681b ldr r3, [r3, #0]
8002572: 035b lsls r3, r3, #13
8002574: 0b5b lsrs r3, r3, #13
8002576: d105 bne.n 8002584 <HAL_ADC_ConfigChannel+0x9c>
8002578: 683b ldr r3, [r7, #0]
800257a: 681b ldr r3, [r3, #0]
800257c: 0e9b lsrs r3, r3, #26
800257e: 221f movs r2, #31
8002580: 4013 ands r3, r2
8002582: e098 b.n 80026b6 <HAL_ADC_ConfigChannel+0x1ce>
8002584: 683b ldr r3, [r7, #0]
8002586: 681b ldr r3, [r3, #0]
8002588: 2201 movs r2, #1
800258a: 4013 ands r3, r2
800258c: d000 beq.n 8002590 <HAL_ADC_ConfigChannel+0xa8>
800258e: e091 b.n 80026b4 <HAL_ADC_ConfigChannel+0x1cc>
8002590: 683b ldr r3, [r7, #0]
8002592: 681b ldr r3, [r3, #0]
8002594: 2202 movs r2, #2
8002596: 4013 ands r3, r2
8002598: d000 beq.n 800259c <HAL_ADC_ConfigChannel+0xb4>
800259a: e089 b.n 80026b0 <HAL_ADC_ConfigChannel+0x1c8>
800259c: 683b ldr r3, [r7, #0]
800259e: 681b ldr r3, [r3, #0]
80025a0: 2204 movs r2, #4
80025a2: 4013 ands r3, r2
80025a4: d000 beq.n 80025a8 <HAL_ADC_ConfigChannel+0xc0>
80025a6: e081 b.n 80026ac <HAL_ADC_ConfigChannel+0x1c4>
80025a8: 683b ldr r3, [r7, #0]
80025aa: 681b ldr r3, [r3, #0]
80025ac: 2208 movs r2, #8
80025ae: 4013 ands r3, r2
80025b0: d000 beq.n 80025b4 <HAL_ADC_ConfigChannel+0xcc>
80025b2: e079 b.n 80026a8 <HAL_ADC_ConfigChannel+0x1c0>
80025b4: 683b ldr r3, [r7, #0]
80025b6: 681b ldr r3, [r3, #0]
80025b8: 2210 movs r2, #16
80025ba: 4013 ands r3, r2
80025bc: d000 beq.n 80025c0 <HAL_ADC_ConfigChannel+0xd8>
80025be: e071 b.n 80026a4 <HAL_ADC_ConfigChannel+0x1bc>
80025c0: 683b ldr r3, [r7, #0]
80025c2: 681b ldr r3, [r3, #0]
80025c4: 2220 movs r2, #32
80025c6: 4013 ands r3, r2
80025c8: d000 beq.n 80025cc <HAL_ADC_ConfigChannel+0xe4>
80025ca: e069 b.n 80026a0 <HAL_ADC_ConfigChannel+0x1b8>
80025cc: 683b ldr r3, [r7, #0]
80025ce: 681b ldr r3, [r3, #0]
80025d0: 2240 movs r2, #64 ; 0x40
80025d2: 4013 ands r3, r2
80025d4: d000 beq.n 80025d8 <HAL_ADC_ConfigChannel+0xf0>
80025d6: e061 b.n 800269c <HAL_ADC_ConfigChannel+0x1b4>
80025d8: 683b ldr r3, [r7, #0]
80025da: 681b ldr r3, [r3, #0]
80025dc: 2280 movs r2, #128 ; 0x80
80025de: 4013 ands r3, r2
80025e0: d000 beq.n 80025e4 <HAL_ADC_ConfigChannel+0xfc>
80025e2: e059 b.n 8002698 <HAL_ADC_ConfigChannel+0x1b0>
80025e4: 683b ldr r3, [r7, #0]
80025e6: 681a ldr r2, [r3, #0]
80025e8: 2380 movs r3, #128 ; 0x80
80025ea: 005b lsls r3, r3, #1
80025ec: 4013 ands r3, r2
80025ee: d151 bne.n 8002694 <HAL_ADC_ConfigChannel+0x1ac>
80025f0: 683b ldr r3, [r7, #0]
80025f2: 681a ldr r2, [r3, #0]
80025f4: 2380 movs r3, #128 ; 0x80
80025f6: 009b lsls r3, r3, #2
80025f8: 4013 ands r3, r2
80025fa: d149 bne.n 8002690 <HAL_ADC_ConfigChannel+0x1a8>
80025fc: 683b ldr r3, [r7, #0]
80025fe: 681a ldr r2, [r3, #0]
8002600: 2380 movs r3, #128 ; 0x80
8002602: 00db lsls r3, r3, #3
8002604: 4013 ands r3, r2
8002606: d141 bne.n 800268c <HAL_ADC_ConfigChannel+0x1a4>
8002608: 683b ldr r3, [r7, #0]
800260a: 681a ldr r2, [r3, #0]
800260c: 2380 movs r3, #128 ; 0x80
800260e: 011b lsls r3, r3, #4
8002610: 4013 ands r3, r2
8002612: d139 bne.n 8002688 <HAL_ADC_ConfigChannel+0x1a0>
8002614: 683b ldr r3, [r7, #0]
8002616: 681a ldr r2, [r3, #0]
8002618: 2380 movs r3, #128 ; 0x80
800261a: 015b lsls r3, r3, #5
800261c: 4013 ands r3, r2
800261e: d131 bne.n 8002684 <HAL_ADC_ConfigChannel+0x19c>
8002620: 683b ldr r3, [r7, #0]
8002622: 681a ldr r2, [r3, #0]
8002624: 2380 movs r3, #128 ; 0x80
8002626: 019b lsls r3, r3, #6
8002628: 4013 ands r3, r2
800262a: d129 bne.n 8002680 <HAL_ADC_ConfigChannel+0x198>
800262c: 683b ldr r3, [r7, #0]
800262e: 681a ldr r2, [r3, #0]
8002630: 2380 movs r3, #128 ; 0x80
8002632: 01db lsls r3, r3, #7
8002634: 4013 ands r3, r2
8002636: d121 bne.n 800267c <HAL_ADC_ConfigChannel+0x194>
8002638: 683b ldr r3, [r7, #0]
800263a: 681a ldr r2, [r3, #0]
800263c: 2380 movs r3, #128 ; 0x80
800263e: 021b lsls r3, r3, #8
8002640: 4013 ands r3, r2
8002642: d119 bne.n 8002678 <HAL_ADC_ConfigChannel+0x190>
8002644: 683b ldr r3, [r7, #0]
8002646: 681a ldr r2, [r3, #0]
8002648: 2380 movs r3, #128 ; 0x80
800264a: 025b lsls r3, r3, #9
800264c: 4013 ands r3, r2
800264e: d111 bne.n 8002674 <HAL_ADC_ConfigChannel+0x18c>
8002650: 683b ldr r3, [r7, #0]
8002652: 681a ldr r2, [r3, #0]
8002654: 2380 movs r3, #128 ; 0x80
8002656: 029b lsls r3, r3, #10
8002658: 4013 ands r3, r2
800265a: d109 bne.n 8002670 <HAL_ADC_ConfigChannel+0x188>
800265c: 683b ldr r3, [r7, #0]
800265e: 681a ldr r2, [r3, #0]
8002660: 2380 movs r3, #128 ; 0x80
8002662: 02db lsls r3, r3, #11
8002664: 4013 ands r3, r2
8002666: d001 beq.n 800266c <HAL_ADC_ConfigChannel+0x184>
8002668: 2312 movs r3, #18
800266a: e024 b.n 80026b6 <HAL_ADC_ConfigChannel+0x1ce>
800266c: 2300 movs r3, #0
800266e: e022 b.n 80026b6 <HAL_ADC_ConfigChannel+0x1ce>
8002670: 2311 movs r3, #17
8002672: e020 b.n 80026b6 <HAL_ADC_ConfigChannel+0x1ce>
8002674: 2310 movs r3, #16
8002676: e01e b.n 80026b6 <HAL_ADC_ConfigChannel+0x1ce>
8002678: 230f movs r3, #15
800267a: e01c b.n 80026b6 <HAL_ADC_ConfigChannel+0x1ce>
800267c: 230e movs r3, #14
800267e: e01a b.n 80026b6 <HAL_ADC_ConfigChannel+0x1ce>
8002680: 230d movs r3, #13
8002682: e018 b.n 80026b6 <HAL_ADC_ConfigChannel+0x1ce>
8002684: 230c movs r3, #12
8002686: e016 b.n 80026b6 <HAL_ADC_ConfigChannel+0x1ce>
8002688: 230b movs r3, #11
800268a: e014 b.n 80026b6 <HAL_ADC_ConfigChannel+0x1ce>
800268c: 230a movs r3, #10
800268e: e012 b.n 80026b6 <HAL_ADC_ConfigChannel+0x1ce>
8002690: 2309 movs r3, #9
8002692: e010 b.n 80026b6 <HAL_ADC_ConfigChannel+0x1ce>
8002694: 2308 movs r3, #8
8002696: e00e b.n 80026b6 <HAL_ADC_ConfigChannel+0x1ce>
8002698: 2307 movs r3, #7
800269a: e00c b.n 80026b6 <HAL_ADC_ConfigChannel+0x1ce>
800269c: 2306 movs r3, #6
800269e: e00a b.n 80026b6 <HAL_ADC_ConfigChannel+0x1ce>
80026a0: 2305 movs r3, #5
80026a2: e008 b.n 80026b6 <HAL_ADC_ConfigChannel+0x1ce>
80026a4: 2304 movs r3, #4
80026a6: e006 b.n 80026b6 <HAL_ADC_ConfigChannel+0x1ce>
80026a8: 2303 movs r3, #3
80026aa: e004 b.n 80026b6 <HAL_ADC_ConfigChannel+0x1ce>
80026ac: 2302 movs r3, #2
80026ae: e002 b.n 80026b6 <HAL_ADC_ConfigChannel+0x1ce>
80026b0: 2301 movs r3, #1
80026b2: e000 b.n 80026b6 <HAL_ADC_ConfigChannel+0x1ce>
80026b4: 2300 movs r3, #0
80026b6: 683a ldr r2, [r7, #0]
80026b8: 6852 ldr r2, [r2, #4]
80026ba: 201f movs r0, #31
80026bc: 4002 ands r2, r0
80026be: 4093 lsls r3, r2
80026c0: 000a movs r2, r1
80026c2: 431a orrs r2, r3
80026c4: 687b ldr r3, [r7, #4]
80026c6: 661a str r2, [r3, #96] ; 0x60
/* If the selected rank is below ADC group regular sequencer length, */
/* apply the configuration in ADC register. */
/* Note: Otherwise, configuration is not applied. */
/* To apply it, parameter'NbrOfConversion' must be increased. */
if (((pConfig->Rank >> 2UL) + 1UL) <= hadc->Init.NbrOfConversion)
80026c8: 683b ldr r3, [r7, #0]
80026ca: 685b ldr r3, [r3, #4]
80026cc: 089b lsrs r3, r3, #2
80026ce: 1c5a adds r2, r3, #1
80026d0: 687b ldr r3, [r7, #4]
80026d2: 69db ldr r3, [r3, #28]
80026d4: 429a cmp r2, r3
80026d6: d808 bhi.n 80026ea <HAL_ADC_ConfigChannel+0x202>
{
LL_ADC_REG_SetSequencerRanks(hadc->Instance, pConfig->Rank, pConfig->Channel);
80026d8: 687b ldr r3, [r7, #4]
80026da: 6818 ldr r0, [r3, #0]
80026dc: 683b ldr r3, [r7, #0]
80026de: 6859 ldr r1, [r3, #4]
80026e0: 683b ldr r3, [r7, #0]
80026e2: 681b ldr r3, [r3, #0]
80026e4: 001a movs r2, r3
80026e6: f7ff faad bl 8001c44 <LL_ADC_REG_SetSequencerRanks>
}
}
/* Set sampling time of the selected ADC channel */
LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfig->Channel, pConfig->SamplingTime);
80026ea: 687b ldr r3, [r7, #4]
80026ec: 6818 ldr r0, [r3, #0]
80026ee: 683b ldr r3, [r7, #0]
80026f0: 6819 ldr r1, [r3, #0]
80026f2: 683b ldr r3, [r7, #0]
80026f4: 689b ldr r3, [r3, #8]
80026f6: 001a movs r2, r3
80026f8: f7ff faf4 bl 8001ce4 <LL_ADC_SetChannelSamplingTime>
/* internal measurement paths enable: If internal channel selected, */
/* enable dedicated internal buffers and path. */
/* Note: these internal measurement paths can be disabled using */
/* HAL_ADC_DeInit() or removing the channel from sequencer with */
/* channel configuration parameter "Rank". */
if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfig->Channel))
80026fc: 683b ldr r3, [r7, #0]
80026fe: 681b ldr r3, [r3, #0]
8002700: 2b00 cmp r3, #0
8002702: db00 blt.n 8002706 <HAL_ADC_ConfigChannel+0x21e>
8002704: e0bc b.n 8002880 <HAL_ADC_ConfigChannel+0x398>
{
tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
8002706: 4b50 ldr r3, [pc, #320] ; (8002848 <HAL_ADC_ConfigChannel+0x360>)
8002708: 0018 movs r0, r3
800270a: f7ff fa49 bl 8001ba0 <LL_ADC_GetCommonPathInternalCh>
800270e: 0003 movs r3, r0
8002710: 613b str r3, [r7, #16]
/* If the requested internal measurement path has already been enabled, */
/* bypass the configuration processing. */
if ((pConfig->Channel == ADC_CHANNEL_TEMPSENSOR) &&
8002712: 683b ldr r3, [r7, #0]
8002714: 681b ldr r3, [r3, #0]
8002716: 4a4d ldr r2, [pc, #308] ; (800284c <HAL_ADC_ConfigChannel+0x364>)
8002718: 4293 cmp r3, r2
800271a: d122 bne.n 8002762 <HAL_ADC_ConfigChannel+0x27a>
((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
800271c: 693a ldr r2, [r7, #16]
800271e: 2380 movs r3, #128 ; 0x80
8002720: 041b lsls r3, r3, #16
8002722: 4013 ands r3, r2
if ((pConfig->Channel == ADC_CHANNEL_TEMPSENSOR) &&
8002724: d11d bne.n 8002762 <HAL_ADC_ConfigChannel+0x27a>
{
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
8002726: 693b ldr r3, [r7, #16]
8002728: 2280 movs r2, #128 ; 0x80
800272a: 0412 lsls r2, r2, #16
800272c: 4313 orrs r3, r2
800272e: 4a46 ldr r2, [pc, #280] ; (8002848 <HAL_ADC_ConfigChannel+0x360>)
8002730: 0019 movs r1, r3
8002732: 0010 movs r0, r2
8002734: f7ff fa20 bl 8001b78 <LL_ADC_SetCommonPathInternalCh>
/* Delay for temperature sensor stabilization time */
/* Wait loop initialization and execution */
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */
wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
8002738: 4b45 ldr r3, [pc, #276] ; (8002850 <HAL_ADC_ConfigChannel+0x368>)
800273a: 681b ldr r3, [r3, #0]
800273c: 4945 ldr r1, [pc, #276] ; (8002854 <HAL_ADC_ConfigChannel+0x36c>)
800273e: 0018 movs r0, r3
8002740: f7fd fce0 bl 8000104 <__udivsi3>
8002744: 0003 movs r3, r0
8002746: 1c5a adds r2, r3, #1
8002748: 0013 movs r3, r2
800274a: 005b lsls r3, r3, #1
800274c: 189b adds r3, r3, r2
800274e: 009b lsls r3, r3, #2
8002750: 60fb str r3, [r7, #12]
while (wait_loop_index != 0UL)
8002752: e002 b.n 800275a <HAL_ADC_ConfigChannel+0x272>
{
wait_loop_index--;
8002754: 68fb ldr r3, [r7, #12]
8002756: 3b01 subs r3, #1
8002758: 60fb str r3, [r7, #12]
while (wait_loop_index != 0UL)
800275a: 68fb ldr r3, [r7, #12]
800275c: 2b00 cmp r3, #0
800275e: d1f9 bne.n 8002754 <HAL_ADC_ConfigChannel+0x26c>
if ((pConfig->Channel == ADC_CHANNEL_TEMPSENSOR) &&
8002760: e08e b.n 8002880 <HAL_ADC_ConfigChannel+0x398>
}
}
else if ((pConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
8002762: 683b ldr r3, [r7, #0]
8002764: 681b ldr r3, [r3, #0]
8002766: 4a3c ldr r2, [pc, #240] ; (8002858 <HAL_ADC_ConfigChannel+0x370>)
8002768: 4293 cmp r3, r2
800276a: d10e bne.n 800278a <HAL_ADC_ConfigChannel+0x2a2>
800276c: 693a ldr r2, [r7, #16]
800276e: 2380 movs r3, #128 ; 0x80
8002770: 045b lsls r3, r3, #17
8002772: 4013 ands r3, r2
8002774: d109 bne.n 800278a <HAL_ADC_ConfigChannel+0x2a2>
{
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
8002776: 693b ldr r3, [r7, #16]
8002778: 2280 movs r2, #128 ; 0x80
800277a: 0452 lsls r2, r2, #17
800277c: 4313 orrs r3, r2
800277e: 4a32 ldr r2, [pc, #200] ; (8002848 <HAL_ADC_ConfigChannel+0x360>)
8002780: 0019 movs r1, r3
8002782: 0010 movs r0, r2
8002784: f7ff f9f8 bl 8001b78 <LL_ADC_SetCommonPathInternalCh>
8002788: e07a b.n 8002880 <HAL_ADC_ConfigChannel+0x398>
LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
}
else if ((pConfig->Channel == ADC_CHANNEL_VREFINT) &&
800278a: 683b ldr r3, [r7, #0]
800278c: 681b ldr r3, [r3, #0]
800278e: 4a33 ldr r2, [pc, #204] ; (800285c <HAL_ADC_ConfigChannel+0x374>)
8002790: 4293 cmp r3, r2
8002792: d000 beq.n 8002796 <HAL_ADC_ConfigChannel+0x2ae>
8002794: e074 b.n 8002880 <HAL_ADC_ConfigChannel+0x398>
((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
8002796: 693a ldr r2, [r7, #16]
8002798: 2380 movs r3, #128 ; 0x80
800279a: 03db lsls r3, r3, #15
800279c: 4013 ands r3, r2
else if ((pConfig->Channel == ADC_CHANNEL_VREFINT) &&
800279e: d000 beq.n 80027a2 <HAL_ADC_ConfigChannel+0x2ba>
80027a0: e06e b.n 8002880 <HAL_ADC_ConfigChannel+0x398>
{
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
80027a2: 693b ldr r3, [r7, #16]
80027a4: 2280 movs r2, #128 ; 0x80
80027a6: 03d2 lsls r2, r2, #15
80027a8: 4313 orrs r3, r2
80027aa: 4a27 ldr r2, [pc, #156] ; (8002848 <HAL_ADC_ConfigChannel+0x360>)
80027ac: 0019 movs r1, r3
80027ae: 0010 movs r0, r2
80027b0: f7ff f9e2 bl 8001b78 <LL_ADC_SetCommonPathInternalCh>
80027b4: e064 b.n 8002880 <HAL_ADC_ConfigChannel+0x398>
/* Regular sequencer configuration */
/* Note: Case of sequencer set to fully configurable: */
/* Sequencer rank cannot be disabled, only affected to */
/* another channel. */
/* To remove a rank, use parameter 'NbrOfConversion". */
if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) ||
80027b6: 687b ldr r3, [r7, #4]
80027b8: 691a ldr r2, [r3, #16]
80027ba: 2380 movs r3, #128 ; 0x80
80027bc: 061b lsls r3, r3, #24
80027be: 429a cmp r2, r3
80027c0: d004 beq.n 80027cc <HAL_ADC_ConfigChannel+0x2e4>
(hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED_BACKWARD))
80027c2: 687b ldr r3, [r7, #4]
80027c4: 691b ldr r3, [r3, #16]
if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) ||
80027c6: 4a1f ldr r2, [pc, #124] ; (8002844 <HAL_ADC_ConfigChannel+0x35c>)
80027c8: 4293 cmp r3, r2
80027ca: d107 bne.n 80027dc <HAL_ADC_ConfigChannel+0x2f4>
{
/* Sequencer set to not fully configurable: */
/* Reset the channel by disabling the corresponding bitfield. */
LL_ADC_REG_SetSequencerChRem(hadc->Instance, pConfig->Channel);
80027cc: 687b ldr r3, [r7, #4]
80027ce: 681a ldr r2, [r3, #0]
80027d0: 683b ldr r3, [r7, #0]
80027d2: 681b ldr r3, [r3, #0]
80027d4: 0019 movs r1, r3
80027d6: 0010 movs r0, r2
80027d8: f7ff fa65 bl 8001ca6 <LL_ADC_REG_SetSequencerChRem>
}
/* Management of internal measurement channels: Vbat/VrefInt/TempSensor. */
/* If internal channel selected, enable dedicated internal buffers and */
/* paths. */
if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfig->Channel))
80027dc: 683b ldr r3, [r7, #0]
80027de: 681b ldr r3, [r3, #0]
80027e0: 2b00 cmp r3, #0
80027e2: da4d bge.n 8002880 <HAL_ADC_ConfigChannel+0x398>
{
tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
80027e4: 4b18 ldr r3, [pc, #96] ; (8002848 <HAL_ADC_ConfigChannel+0x360>)
80027e6: 0018 movs r0, r3
80027e8: f7ff f9da bl 8001ba0 <LL_ADC_GetCommonPathInternalCh>
80027ec: 0003 movs r3, r0
80027ee: 613b str r3, [r7, #16]
if (pConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
80027f0: 683b ldr r3, [r7, #0]
80027f2: 681b ldr r3, [r3, #0]
80027f4: 4a15 ldr r2, [pc, #84] ; (800284c <HAL_ADC_ConfigChannel+0x364>)
80027f6: 4293 cmp r3, r2
80027f8: d108 bne.n 800280c <HAL_ADC_ConfigChannel+0x324>
{
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
80027fa: 693b ldr r3, [r7, #16]
80027fc: 4a18 ldr r2, [pc, #96] ; (8002860 <HAL_ADC_ConfigChannel+0x378>)
80027fe: 4013 ands r3, r2
8002800: 4a11 ldr r2, [pc, #68] ; (8002848 <HAL_ADC_ConfigChannel+0x360>)
8002802: 0019 movs r1, r3
8002804: 0010 movs r0, r2
8002806: f7ff f9b7 bl 8001b78 <LL_ADC_SetCommonPathInternalCh>
800280a: e039 b.n 8002880 <HAL_ADC_ConfigChannel+0x398>
~LL_ADC_PATH_INTERNAL_TEMPSENSOR & tmp_config_internal_channel);
}
else if (pConfig->Channel == ADC_CHANNEL_VBAT)
800280c: 683b ldr r3, [r7, #0]
800280e: 681b ldr r3, [r3, #0]
8002810: 4a11 ldr r2, [pc, #68] ; (8002858 <HAL_ADC_ConfigChannel+0x370>)
8002812: 4293 cmp r3, r2
8002814: d108 bne.n 8002828 <HAL_ADC_ConfigChannel+0x340>
{
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
8002816: 693b ldr r3, [r7, #16]
8002818: 4a12 ldr r2, [pc, #72] ; (8002864 <HAL_ADC_ConfigChannel+0x37c>)
800281a: 4013 ands r3, r2
800281c: 4a0a ldr r2, [pc, #40] ; (8002848 <HAL_ADC_ConfigChannel+0x360>)
800281e: 0019 movs r1, r3
8002820: 0010 movs r0, r2
8002822: f7ff f9a9 bl 8001b78 <LL_ADC_SetCommonPathInternalCh>
8002826: e02b b.n 8002880 <HAL_ADC_ConfigChannel+0x398>
~LL_ADC_PATH_INTERNAL_VBAT & tmp_config_internal_channel);
}
else if (pConfig->Channel == ADC_CHANNEL_VREFINT)
8002828: 683b ldr r3, [r7, #0]
800282a: 681b ldr r3, [r3, #0]
800282c: 4a0b ldr r2, [pc, #44] ; (800285c <HAL_ADC_ConfigChannel+0x374>)
800282e: 4293 cmp r3, r2
8002830: d126 bne.n 8002880 <HAL_ADC_ConfigChannel+0x398>
{
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
8002832: 693b ldr r3, [r7, #16]
8002834: 4a0c ldr r2, [pc, #48] ; (8002868 <HAL_ADC_ConfigChannel+0x380>)
8002836: 4013 ands r3, r2
8002838: 4a03 ldr r2, [pc, #12] ; (8002848 <HAL_ADC_ConfigChannel+0x360>)
800283a: 0019 movs r1, r3
800283c: 0010 movs r0, r2
800283e: f7ff f99b bl 8001b78 <LL_ADC_SetCommonPathInternalCh>
8002842: e01d b.n 8002880 <HAL_ADC_ConfigChannel+0x398>
8002844: 80000004 .word 0x80000004
8002848: 40012708 .word 0x40012708
800284c: b0001000 .word 0xb0001000
8002850: 2000000c .word 0x2000000c
8002854: 00030d40 .word 0x00030d40
8002858: b8004000 .word 0xb8004000
800285c: b4002000 .word 0xb4002000
8002860: ff7fffff .word 0xff7fffff
8002864: feffffff .word 0xfeffffff
8002868: ffbfffff .word 0xffbfffff
/* channel could be done on neither of the channel configuration structure */
/* parameters. */
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
800286c: 687b ldr r3, [r7, #4]
800286e: 6d9b ldr r3, [r3, #88] ; 0x58
8002870: 2220 movs r2, #32
8002872: 431a orrs r2, r3
8002874: 687b ldr r3, [r7, #4]
8002876: 659a str r2, [r3, #88] ; 0x58
tmp_hal_status = HAL_ERROR;
8002878: 2317 movs r3, #23
800287a: 18fb adds r3, r7, r3
800287c: 2201 movs r2, #1
800287e: 701a strb r2, [r3, #0]
}
__HAL_UNLOCK(hadc);
8002880: 687b ldr r3, [r7, #4]
8002882: 2254 movs r2, #84 ; 0x54
8002884: 2100 movs r1, #0
8002886: 5499 strb r1, [r3, r2]
return tmp_hal_status;
8002888: 2317 movs r3, #23
800288a: 18fb adds r3, r7, r3
800288c: 781b ldrb r3, [r3, #0]
}
800288e: 0018 movs r0, r3
8002890: 46bd mov sp, r7
8002892: b006 add sp, #24
8002894: bd80 pop {r7, pc}
8002896: 46c0 nop ; (mov r8, r8)
08002898 <ADC_Enable>:
* and voltage regulator must be enabled (done into HAL_ADC_Init()).
* @param hadc ADC handle
* @retval HAL status.
*/
HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc)
{
8002898: b580 push {r7, lr}
800289a: b084 sub sp, #16
800289c: af00 add r7, sp, #0
800289e: 6078 str r0, [r7, #4]
uint32_t tickstart;
__IO uint32_t wait_loop_index = 0UL;
80028a0: 2300 movs r3, #0
80028a2: 60bb str r3, [r7, #8]
/* ADC enable and wait for ADC ready (in case of ADC is disabled or */
/* enabling phase not yet completed: flag ADC ready not yet set). */
/* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
/* causes: ADC clock not running, ...). */
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
80028a4: 687b ldr r3, [r7, #4]
80028a6: 681b ldr r3, [r3, #0]
80028a8: 0018 movs r0, r3
80028aa: f7ff fa83 bl 8001db4 <LL_ADC_IsEnabled>
80028ae: 1e03 subs r3, r0, #0
80028b0: d000 beq.n 80028b4 <ADC_Enable+0x1c>
80028b2: e069 b.n 8002988 <ADC_Enable+0xf0>
{
/* Check if conditions to enable the ADC are fulfilled */
if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL)
80028b4: 687b ldr r3, [r7, #4]
80028b6: 681b ldr r3, [r3, #0]
80028b8: 689b ldr r3, [r3, #8]
80028ba: 4a36 ldr r2, [pc, #216] ; (8002994 <ADC_Enable+0xfc>)
80028bc: 4013 ands r3, r2
80028be: d00d beq.n 80028dc <ADC_Enable+0x44>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
80028c0: 687b ldr r3, [r7, #4]
80028c2: 6d9b ldr r3, [r3, #88] ; 0x58
80028c4: 2210 movs r2, #16
80028c6: 431a orrs r2, r3
80028c8: 687b ldr r3, [r7, #4]
80028ca: 659a str r2, [r3, #88] ; 0x58
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
80028cc: 687b ldr r3, [r7, #4]
80028ce: 6ddb ldr r3, [r3, #92] ; 0x5c
80028d0: 2201 movs r2, #1
80028d2: 431a orrs r2, r3
80028d4: 687b ldr r3, [r7, #4]
80028d6: 65da str r2, [r3, #92] ; 0x5c
return HAL_ERROR;
80028d8: 2301 movs r3, #1
80028da: e056 b.n 800298a <ADC_Enable+0xf2>
}
/* Enable the ADC peripheral */
LL_ADC_Enable(hadc->Instance);
80028dc: 687b ldr r3, [r7, #4]
80028de: 681b ldr r3, [r3, #0]
80028e0: 0018 movs r0, r3
80028e2: f7ff fa43 bl 8001d6c <LL_ADC_Enable>
if ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_TEMPSENSOR) != 0UL)
80028e6: 4b2c ldr r3, [pc, #176] ; (8002998 <ADC_Enable+0x100>)
80028e8: 0018 movs r0, r3
80028ea: f7ff f959 bl 8001ba0 <LL_ADC_GetCommonPathInternalCh>
80028ee: 0002 movs r2, r0
80028f0: 2380 movs r3, #128 ; 0x80
80028f2: 041b lsls r3, r3, #16
80028f4: 4013 ands r3, r2
80028f6: d00f beq.n 8002918 <ADC_Enable+0x80>
/* Delay for temperature sensor buffer stabilization time */
/* Wait loop initialization and execution */
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */
wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
80028f8: 4b28 ldr r3, [pc, #160] ; (800299c <ADC_Enable+0x104>)
80028fa: 681b ldr r3, [r3, #0]
80028fc: 4928 ldr r1, [pc, #160] ; (80029a0 <ADC_Enable+0x108>)
80028fe: 0018 movs r0, r3
8002900: f7fd fc00 bl 8000104 <__udivsi3>
8002904: 0003 movs r3, r0
8002906: 3301 adds r3, #1
8002908: 60bb str r3, [r7, #8]
while (wait_loop_index != 0UL)
800290a: e002 b.n 8002912 <ADC_Enable+0x7a>
{
wait_loop_index--;
800290c: 68bb ldr r3, [r7, #8]
800290e: 3b01 subs r3, #1
8002910: 60bb str r3, [r7, #8]
while (wait_loop_index != 0UL)
8002912: 68bb ldr r3, [r7, #8]
8002914: 2b00 cmp r3, #0
8002916: d1f9 bne.n 800290c <ADC_Enable+0x74>
}
}
/* If low power mode AutoPowerOff is enabled, power-on/off phases are */
/* performed automatically by hardware and flag ADC ready is not set. */
if (hadc->Init.LowPowerAutoPowerOff != ENABLE)
8002918: 687b ldr r3, [r7, #4]
800291a: 7e5b ldrb r3, [r3, #25]
800291c: 2b01 cmp r3, #1
800291e: d033 beq.n 8002988 <ADC_Enable+0xf0>
{
/* Wait for ADC effectively enabled */
tickstart = HAL_GetTick();
8002920: f7ff f920 bl 8001b64 <HAL_GetTick>
8002924: 0003 movs r3, r0
8002926: 60fb str r3, [r7, #12]
while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
8002928: e027 b.n 800297a <ADC_Enable+0xe2>
The workaround is to continue setting ADEN until ADRDY is becomes 1.
Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this
4 ADC clock cycle duration */
/* Note: Test of ADC enabled required due to hardware constraint to */
/* not enable ADC if already enabled. */
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
800292a: 687b ldr r3, [r7, #4]
800292c: 681b ldr r3, [r3, #0]
800292e: 0018 movs r0, r3
8002930: f7ff fa40 bl 8001db4 <LL_ADC_IsEnabled>
8002934: 1e03 subs r3, r0, #0
8002936: d104 bne.n 8002942 <ADC_Enable+0xaa>
{
LL_ADC_Enable(hadc->Instance);
8002938: 687b ldr r3, [r7, #4]
800293a: 681b ldr r3, [r3, #0]
800293c: 0018 movs r0, r3
800293e: f7ff fa15 bl 8001d6c <LL_ADC_Enable>
}
if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
8002942: f7ff f90f bl 8001b64 <HAL_GetTick>
8002946: 0002 movs r2, r0
8002948: 68fb ldr r3, [r7, #12]
800294a: 1ad3 subs r3, r2, r3
800294c: 2b02 cmp r3, #2
800294e: d914 bls.n 800297a <ADC_Enable+0xe2>
{
/* New check to avoid false timeout detection in case of preemption */
if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
8002950: 687b ldr r3, [r7, #4]
8002952: 681b ldr r3, [r3, #0]
8002954: 681b ldr r3, [r3, #0]
8002956: 2201 movs r2, #1
8002958: 4013 ands r3, r2
800295a: 2b01 cmp r3, #1
800295c: d00d beq.n 800297a <ADC_Enable+0xe2>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
800295e: 687b ldr r3, [r7, #4]
8002960: 6d9b ldr r3, [r3, #88] ; 0x58
8002962: 2210 movs r2, #16
8002964: 431a orrs r2, r3
8002966: 687b ldr r3, [r7, #4]
8002968: 659a str r2, [r3, #88] ; 0x58
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
800296a: 687b ldr r3, [r7, #4]
800296c: 6ddb ldr r3, [r3, #92] ; 0x5c
800296e: 2201 movs r2, #1
8002970: 431a orrs r2, r3
8002972: 687b ldr r3, [r7, #4]
8002974: 65da str r2, [r3, #92] ; 0x5c
return HAL_ERROR;
8002976: 2301 movs r3, #1
8002978: e007 b.n 800298a <ADC_Enable+0xf2>
while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
800297a: 687b ldr r3, [r7, #4]
800297c: 681b ldr r3, [r3, #0]
800297e: 681b ldr r3, [r3, #0]
8002980: 2201 movs r2, #1
8002982: 4013 ands r3, r2
8002984: 2b01 cmp r3, #1
8002986: d1d0 bne.n 800292a <ADC_Enable+0x92>
}
}
}
/* Return HAL status */
return HAL_OK;
8002988: 2300 movs r3, #0
}
800298a: 0018 movs r0, r3
800298c: 46bd mov sp, r7
800298e: b004 add sp, #16
8002990: bd80 pop {r7, pc}
8002992: 46c0 nop ; (mov r8, r8)
8002994: 80000017 .word 0x80000017
8002998: 40012708 .word 0x40012708
800299c: 2000000c .word 0x2000000c
80029a0: 00030d40 .word 0x00030d40
080029a4 <ADC_Disable>:
* stopped.
* @param hadc ADC handle
* @retval HAL status.
*/
HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc)
{
80029a4: b580 push {r7, lr}
80029a6: b084 sub sp, #16
80029a8: af00 add r7, sp, #0
80029aa: 6078 str r0, [r7, #4]
uint32_t tickstart;
const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(hadc->Instance);
80029ac: 687b ldr r3, [r7, #4]
80029ae: 681b ldr r3, [r3, #0]
80029b0: 0018 movs r0, r3
80029b2: f7ff fa10 bl 8001dd6 <LL_ADC_IsDisableOngoing>
80029b6: 0003 movs r3, r0
80029b8: 60fb str r3, [r7, #12]
/* Verification if ADC is not already disabled: */
/* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */
/* disabled. */
if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL)
80029ba: 687b ldr r3, [r7, #4]
80029bc: 681b ldr r3, [r3, #0]
80029be: 0018 movs r0, r3
80029c0: f7ff f9f8 bl 8001db4 <LL_ADC_IsEnabled>
80029c4: 1e03 subs r3, r0, #0
80029c6: d046 beq.n 8002a56 <ADC_Disable+0xb2>
&& (tmp_adc_is_disable_on_going == 0UL)
80029c8: 68fb ldr r3, [r7, #12]
80029ca: 2b00 cmp r3, #0
80029cc: d143 bne.n 8002a56 <ADC_Disable+0xb2>
)
{
/* Check if conditions to disable the ADC are fulfilled */
if ((hadc->Instance->CR & (ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN)
80029ce: 687b ldr r3, [r7, #4]
80029d0: 681b ldr r3, [r3, #0]
80029d2: 689b ldr r3, [r3, #8]
80029d4: 2205 movs r2, #5
80029d6: 4013 ands r3, r2
80029d8: 2b01 cmp r3, #1
80029da: d10d bne.n 80029f8 <ADC_Disable+0x54>
{
/* Disable the ADC peripheral */
LL_ADC_Disable(hadc->Instance);
80029dc: 687b ldr r3, [r7, #4]
80029de: 681b ldr r3, [r3, #0]
80029e0: 0018 movs r0, r3
80029e2: f7ff f9d5 bl 8001d90 <LL_ADC_Disable>
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY));
80029e6: 687b ldr r3, [r7, #4]
80029e8: 681b ldr r3, [r3, #0]
80029ea: 2203 movs r2, #3
80029ec: 601a str r2, [r3, #0]
return HAL_ERROR;
}
/* Wait for ADC effectively disabled */
/* Get tick count */
tickstart = HAL_GetTick();
80029ee: f7ff f8b9 bl 8001b64 <HAL_GetTick>
80029f2: 0003 movs r3, r0
80029f4: 60bb str r3, [r7, #8]
while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
80029f6: e028 b.n 8002a4a <ADC_Disable+0xa6>
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
80029f8: 687b ldr r3, [r7, #4]
80029fa: 6d9b ldr r3, [r3, #88] ; 0x58
80029fc: 2210 movs r2, #16
80029fe: 431a orrs r2, r3
8002a00: 687b ldr r3, [r7, #4]
8002a02: 659a str r2, [r3, #88] ; 0x58
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8002a04: 687b ldr r3, [r7, #4]
8002a06: 6ddb ldr r3, [r3, #92] ; 0x5c
8002a08: 2201 movs r2, #1
8002a0a: 431a orrs r2, r3
8002a0c: 687b ldr r3, [r7, #4]
8002a0e: 65da str r2, [r3, #92] ; 0x5c
return HAL_ERROR;
8002a10: 2301 movs r3, #1
8002a12: e021 b.n 8002a58 <ADC_Disable+0xb4>
{
if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
8002a14: f7ff f8a6 bl 8001b64 <HAL_GetTick>
8002a18: 0002 movs r2, r0
8002a1a: 68bb ldr r3, [r7, #8]
8002a1c: 1ad3 subs r3, r2, r3
8002a1e: 2b02 cmp r3, #2
8002a20: d913 bls.n 8002a4a <ADC_Disable+0xa6>
{
/* New check to avoid false timeout detection in case of preemption */
if ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
8002a22: 687b ldr r3, [r7, #4]
8002a24: 681b ldr r3, [r3, #0]
8002a26: 689b ldr r3, [r3, #8]
8002a28: 2201 movs r2, #1
8002a2a: 4013 ands r3, r2
8002a2c: d00d beq.n 8002a4a <ADC_Disable+0xa6>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
8002a2e: 687b ldr r3, [r7, #4]
8002a30: 6d9b ldr r3, [r3, #88] ; 0x58
8002a32: 2210 movs r2, #16
8002a34: 431a orrs r2, r3
8002a36: 687b ldr r3, [r7, #4]
8002a38: 659a str r2, [r3, #88] ; 0x58
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8002a3a: 687b ldr r3, [r7, #4]
8002a3c: 6ddb ldr r3, [r3, #92] ; 0x5c
8002a3e: 2201 movs r2, #1
8002a40: 431a orrs r2, r3
8002a42: 687b ldr r3, [r7, #4]
8002a44: 65da str r2, [r3, #92] ; 0x5c
return HAL_ERROR;
8002a46: 2301 movs r3, #1
8002a48: e006 b.n 8002a58 <ADC_Disable+0xb4>
while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
8002a4a: 687b ldr r3, [r7, #4]
8002a4c: 681b ldr r3, [r3, #0]
8002a4e: 689b ldr r3, [r3, #8]
8002a50: 2201 movs r2, #1
8002a52: 4013 ands r3, r2
8002a54: d1de bne.n 8002a14 <ADC_Disable+0x70>
}
}
}
/* Return HAL status */
return HAL_OK;
8002a56: 2300 movs r3, #0
}
8002a58: 0018 movs r0, r3
8002a5a: 46bd mov sp, r7
8002a5c: b004 add sp, #16
8002a5e: bd80 pop {r7, pc}
08002a60 <LL_ADC_SetCalibrationFactor>:
{
8002a60: b580 push {r7, lr}
8002a62: b082 sub sp, #8
8002a64: af00 add r7, sp, #0
8002a66: 6078 str r0, [r7, #4]
8002a68: 6039 str r1, [r7, #0]
MODIFY_REG(ADCx->CALFACT,
8002a6a: 687b ldr r3, [r7, #4]
8002a6c: 22b4 movs r2, #180 ; 0xb4
8002a6e: 589b ldr r3, [r3, r2]
8002a70: 227f movs r2, #127 ; 0x7f
8002a72: 4393 bics r3, r2
8002a74: 001a movs r2, r3
8002a76: 683b ldr r3, [r7, #0]
8002a78: 431a orrs r2, r3
8002a7a: 687b ldr r3, [r7, #4]
8002a7c: 21b4 movs r1, #180 ; 0xb4
8002a7e: 505a str r2, [r3, r1]
}
8002a80: 46c0 nop ; (mov r8, r8)
8002a82: 46bd mov sp, r7
8002a84: b002 add sp, #8
8002a86: bd80 pop {r7, pc}
08002a88 <LL_ADC_GetCalibrationFactor>:
{
8002a88: b580 push {r7, lr}
8002a8a: b082 sub sp, #8
8002a8c: af00 add r7, sp, #0
8002a8e: 6078 str r0, [r7, #4]
return (uint32_t)(READ_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT));
8002a90: 687b ldr r3, [r7, #4]
8002a92: 22b4 movs r2, #180 ; 0xb4
8002a94: 589b ldr r3, [r3, r2]
8002a96: 227f movs r2, #127 ; 0x7f
8002a98: 4013 ands r3, r2
}
8002a9a: 0018 movs r0, r3
8002a9c: 46bd mov sp, r7
8002a9e: b002 add sp, #8
8002aa0: bd80 pop {r7, pc}
...
08002aa4 <LL_ADC_Enable>:
{
8002aa4: b580 push {r7, lr}
8002aa6: b082 sub sp, #8
8002aa8: af00 add r7, sp, #0
8002aaa: 6078 str r0, [r7, #4]
MODIFY_REG(ADCx->CR,
8002aac: 687b ldr r3, [r7, #4]
8002aae: 689b ldr r3, [r3, #8]
8002ab0: 4a04 ldr r2, [pc, #16] ; (8002ac4 <LL_ADC_Enable+0x20>)
8002ab2: 4013 ands r3, r2
8002ab4: 2201 movs r2, #1
8002ab6: 431a orrs r2, r3
8002ab8: 687b ldr r3, [r7, #4]
8002aba: 609a str r2, [r3, #8]
}
8002abc: 46c0 nop ; (mov r8, r8)
8002abe: 46bd mov sp, r7
8002ac0: b002 add sp, #8
8002ac2: bd80 pop {r7, pc}
8002ac4: 7fffffe8 .word 0x7fffffe8
08002ac8 <LL_ADC_Disable>:
{
8002ac8: b580 push {r7, lr}
8002aca: b082 sub sp, #8
8002acc: af00 add r7, sp, #0
8002ace: 6078 str r0, [r7, #4]
MODIFY_REG(ADCx->CR,
8002ad0: 687b ldr r3, [r7, #4]
8002ad2: 689b ldr r3, [r3, #8]
8002ad4: 4a04 ldr r2, [pc, #16] ; (8002ae8 <LL_ADC_Disable+0x20>)
8002ad6: 4013 ands r3, r2
8002ad8: 2202 movs r2, #2
8002ada: 431a orrs r2, r3
8002adc: 687b ldr r3, [r7, #4]
8002ade: 609a str r2, [r3, #8]
}
8002ae0: 46c0 nop ; (mov r8, r8)
8002ae2: 46bd mov sp, r7
8002ae4: b002 add sp, #8
8002ae6: bd80 pop {r7, pc}
8002ae8: 7fffffe8 .word 0x7fffffe8
08002aec <LL_ADC_IsEnabled>:
{
8002aec: b580 push {r7, lr}
8002aee: b082 sub sp, #8
8002af0: af00 add r7, sp, #0
8002af2: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
8002af4: 687b ldr r3, [r7, #4]
8002af6: 689b ldr r3, [r3, #8]
8002af8: 2201 movs r2, #1
8002afa: 4013 ands r3, r2
8002afc: 2b01 cmp r3, #1
8002afe: d101 bne.n 8002b04 <LL_ADC_IsEnabled+0x18>
8002b00: 2301 movs r3, #1
8002b02: e000 b.n 8002b06 <LL_ADC_IsEnabled+0x1a>
8002b04: 2300 movs r3, #0
}
8002b06: 0018 movs r0, r3
8002b08: 46bd mov sp, r7
8002b0a: b002 add sp, #8
8002b0c: bd80 pop {r7, pc}
...
08002b10 <LL_ADC_StartCalibration>:
{
8002b10: b580 push {r7, lr}
8002b12: b082 sub sp, #8
8002b14: af00 add r7, sp, #0
8002b16: 6078 str r0, [r7, #4]
MODIFY_REG(ADCx->CR,
8002b18: 687b ldr r3, [r7, #4]
8002b1a: 689b ldr r3, [r3, #8]
8002b1c: 4a05 ldr r2, [pc, #20] ; (8002b34 <LL_ADC_StartCalibration+0x24>)
8002b1e: 4013 ands r3, r2
8002b20: 2280 movs r2, #128 ; 0x80
8002b22: 0612 lsls r2, r2, #24
8002b24: 431a orrs r2, r3
8002b26: 687b ldr r3, [r7, #4]
8002b28: 609a str r2, [r3, #8]
}
8002b2a: 46c0 nop ; (mov r8, r8)
8002b2c: 46bd mov sp, r7
8002b2e: b002 add sp, #8
8002b30: bd80 pop {r7, pc}
8002b32: 46c0 nop ; (mov r8, r8)
8002b34: 7fffffe8 .word 0x7fffffe8
08002b38 <LL_ADC_IsCalibrationOnGoing>:
{
8002b38: b580 push {r7, lr}
8002b3a: b082 sub sp, #8
8002b3c: af00 add r7, sp, #0
8002b3e: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL);
8002b40: 687b ldr r3, [r7, #4]
8002b42: 689b ldr r3, [r3, #8]
8002b44: 0fdb lsrs r3, r3, #31
8002b46: 07da lsls r2, r3, #31
8002b48: 2380 movs r3, #128 ; 0x80
8002b4a: 061b lsls r3, r3, #24
8002b4c: 429a cmp r2, r3
8002b4e: d101 bne.n 8002b54 <LL_ADC_IsCalibrationOnGoing+0x1c>
8002b50: 2301 movs r3, #1
8002b52: e000 b.n 8002b56 <LL_ADC_IsCalibrationOnGoing+0x1e>
8002b54: 2300 movs r3, #0
}
8002b56: 0018 movs r0, r3
8002b58: 46bd mov sp, r7
8002b5a: b002 add sp, #8
8002b5c: bd80 pop {r7, pc}
...
08002b60 <HAL_ADCEx_Calibration_Start>:
* HAL_ADC_GetValue() (value on 7 bits: from DR[6;0]).
* @param hadc ADC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc)
{
8002b60: b590 push {r4, r7, lr}
8002b62: b089 sub sp, #36 ; 0x24
8002b64: af00 add r7, sp, #0
8002b66: 6078 str r0, [r7, #4]
HAL_StatusTypeDef tmp_hal_status;
__IO uint32_t wait_loop_index = 0UL;
8002b68: 2300 movs r3, #0
8002b6a: 60bb str r3, [r7, #8]
uint32_t backup_setting_cfgr1;
uint32_t calibration_index;
uint32_t calibration_factor_accumulated = 0;
8002b6c: 2300 movs r3, #0
8002b6e: 61bb str r3, [r7, #24]
uint32_t tickstart;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
__HAL_LOCK(hadc);
8002b70: 687b ldr r3, [r7, #4]
8002b72: 2254 movs r2, #84 ; 0x54
8002b74: 5c9b ldrb r3, [r3, r2]
8002b76: 2b01 cmp r3, #1
8002b78: d101 bne.n 8002b7e <HAL_ADCEx_Calibration_Start+0x1e>
8002b7a: 2302 movs r3, #2
8002b7c: e0ba b.n 8002cf4 <HAL_ADCEx_Calibration_Start+0x194>
8002b7e: 687b ldr r3, [r7, #4]
8002b80: 2254 movs r2, #84 ; 0x54
8002b82: 2101 movs r1, #1
8002b84: 5499 strb r1, [r3, r2]
/* Calibration prerequisite: ADC must be disabled. */
/* Disable the ADC (if not already disabled) */
tmp_hal_status = ADC_Disable(hadc);
8002b86: 2317 movs r3, #23
8002b88: 18fc adds r4, r7, r3
8002b8a: 687b ldr r3, [r7, #4]
8002b8c: 0018 movs r0, r3
8002b8e: f7ff ff09 bl 80029a4 <ADC_Disable>
8002b92: 0003 movs r3, r0
8002b94: 7023 strb r3, [r4, #0]
/* Check if ADC is effectively disabled */
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
8002b96: 687b ldr r3, [r7, #4]
8002b98: 681b ldr r3, [r3, #0]
8002b9a: 0018 movs r0, r3
8002b9c: f7ff ffa6 bl 8002aec <LL_ADC_IsEnabled>
8002ba0: 1e03 subs r3, r0, #0
8002ba2: d000 beq.n 8002ba6 <HAL_ADCEx_Calibration_Start+0x46>
8002ba4: e099 b.n 8002cda <HAL_ADCEx_Calibration_Start+0x17a>
{
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
8002ba6: 687b ldr r3, [r7, #4]
8002ba8: 6d9b ldr r3, [r3, #88] ; 0x58
8002baa: 4a54 ldr r2, [pc, #336] ; (8002cfc <HAL_ADCEx_Calibration_Start+0x19c>)
8002bac: 4013 ands r3, r2
8002bae: 2202 movs r2, #2
8002bb0: 431a orrs r2, r3
8002bb2: 687b ldr r3, [r7, #4]
8002bb4: 659a str r2, [r3, #88] ; 0x58
/* Note: Specificity of this STM32 series: Calibration factor is */
/* available in data register and also transferred by DMA. */
/* To not insert ADC calibration factor among ADC conversion data */
/* in array variable, DMA transfer must be disabled during */
/* calibration. */
backup_setting_cfgr1 = READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG | ADC_CFGR1_AUTOFF);
8002bb6: 687b ldr r3, [r7, #4]
8002bb8: 681b ldr r3, [r3, #0]
8002bba: 68db ldr r3, [r3, #12]
8002bbc: 4a50 ldr r2, [pc, #320] ; (8002d00 <HAL_ADCEx_Calibration_Start+0x1a0>)
8002bbe: 4013 ands r3, r2
8002bc0: 613b str r3, [r7, #16]
CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG | ADC_CFGR1_AUTOFF);
8002bc2: 687b ldr r3, [r7, #4]
8002bc4: 681b ldr r3, [r3, #0]
8002bc6: 68da ldr r2, [r3, #12]
8002bc8: 687b ldr r3, [r7, #4]
8002bca: 681b ldr r3, [r3, #0]
8002bcc: 494d ldr r1, [pc, #308] ; (8002d04 <HAL_ADCEx_Calibration_Start+0x1a4>)
8002bce: 400a ands r2, r1
8002bd0: 60da str r2, [r3, #12]
/* ADC calibration procedure */
/* Note: Perform an averaging of 8 calibrations for optimized accuracy */
for (calibration_index = 0UL; calibration_index < 8UL; calibration_index++)
8002bd2: 2300 movs r3, #0
8002bd4: 61fb str r3, [r7, #28]
8002bd6: e02d b.n 8002c34 <HAL_ADCEx_Calibration_Start+0xd4>
{
/* Start ADC calibration */
LL_ADC_StartCalibration(hadc->Instance);
8002bd8: 687b ldr r3, [r7, #4]
8002bda: 681b ldr r3, [r3, #0]
8002bdc: 0018 movs r0, r3
8002bde: f7ff ff97 bl 8002b10 <LL_ADC_StartCalibration>
/* Wait for calibration completion */
while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL)
8002be2: e014 b.n 8002c0e <HAL_ADCEx_Calibration_Start+0xae>
{
wait_loop_index++;
8002be4: 68bb ldr r3, [r7, #8]
8002be6: 3301 adds r3, #1
8002be8: 60bb str r3, [r7, #8]
if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT)
8002bea: 68bb ldr r3, [r7, #8]
8002bec: 4a46 ldr r2, [pc, #280] ; (8002d08 <HAL_ADCEx_Calibration_Start+0x1a8>)
8002bee: 4293 cmp r3, r2
8002bf0: d90d bls.n 8002c0e <HAL_ADCEx_Calibration_Start+0xae>
{
/* Update ADC state machine to error */
ADC_STATE_CLR_SET(hadc->State,
8002bf2: 687b ldr r3, [r7, #4]
8002bf4: 6d9b ldr r3, [r3, #88] ; 0x58
8002bf6: 2212 movs r2, #18
8002bf8: 4393 bics r3, r2
8002bfa: 2210 movs r2, #16
8002bfc: 431a orrs r2, r3
8002bfe: 687b ldr r3, [r7, #4]
8002c00: 659a str r2, [r3, #88] ; 0x58
HAL_ADC_STATE_BUSY_INTERNAL,
HAL_ADC_STATE_ERROR_INTERNAL);
__HAL_UNLOCK(hadc);
8002c02: 687b ldr r3, [r7, #4]
8002c04: 2254 movs r2, #84 ; 0x54
8002c06: 2100 movs r1, #0
8002c08: 5499 strb r1, [r3, r2]
return HAL_ERROR;
8002c0a: 2301 movs r3, #1
8002c0c: e072 b.n 8002cf4 <HAL_ADCEx_Calibration_Start+0x194>
while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL)
8002c0e: 687b ldr r3, [r7, #4]
8002c10: 681b ldr r3, [r3, #0]
8002c12: 0018 movs r0, r3
8002c14: f7ff ff90 bl 8002b38 <LL_ADC_IsCalibrationOnGoing>
8002c18: 1e03 subs r3, r0, #0
8002c1a: d1e3 bne.n 8002be4 <HAL_ADCEx_Calibration_Start+0x84>
}
}
calibration_factor_accumulated += LL_ADC_GetCalibrationFactor(hadc->Instance);
8002c1c: 687b ldr r3, [r7, #4]
8002c1e: 681b ldr r3, [r3, #0]
8002c20: 0018 movs r0, r3
8002c22: f7ff ff31 bl 8002a88 <LL_ADC_GetCalibrationFactor>
8002c26: 0002 movs r2, r0
8002c28: 69bb ldr r3, [r7, #24]
8002c2a: 189b adds r3, r3, r2
8002c2c: 61bb str r3, [r7, #24]
for (calibration_index = 0UL; calibration_index < 8UL; calibration_index++)
8002c2e: 69fb ldr r3, [r7, #28]
8002c30: 3301 adds r3, #1
8002c32: 61fb str r3, [r7, #28]
8002c34: 69fb ldr r3, [r7, #28]
8002c36: 2b07 cmp r3, #7
8002c38: d9ce bls.n 8002bd8 <HAL_ADCEx_Calibration_Start+0x78>
}
/* Compute average */
calibration_factor_accumulated /= calibration_index;
8002c3a: 69f9 ldr r1, [r7, #28]
8002c3c: 69b8 ldr r0, [r7, #24]
8002c3e: f7fd fa61 bl 8000104 <__udivsi3>
8002c42: 0003 movs r3, r0
8002c44: 61bb str r3, [r7, #24]
/* Apply calibration factor */
LL_ADC_Enable(hadc->Instance);
8002c46: 687b ldr r3, [r7, #4]
8002c48: 681b ldr r3, [r3, #0]
8002c4a: 0018 movs r0, r3
8002c4c: f7ff ff2a bl 8002aa4 <LL_ADC_Enable>
LL_ADC_SetCalibrationFactor(hadc->Instance, calibration_factor_accumulated);
8002c50: 687b ldr r3, [r7, #4]
8002c52: 681b ldr r3, [r3, #0]
8002c54: 69ba ldr r2, [r7, #24]
8002c56: 0011 movs r1, r2
8002c58: 0018 movs r0, r3
8002c5a: f7ff ff01 bl 8002a60 <LL_ADC_SetCalibrationFactor>
LL_ADC_Disable(hadc->Instance);
8002c5e: 687b ldr r3, [r7, #4]
8002c60: 681b ldr r3, [r3, #0]
8002c62: 0018 movs r0, r3
8002c64: f7ff ff30 bl 8002ac8 <LL_ADC_Disable>
/* Wait for ADC effectively disabled before changing configuration */
/* Get tick count */
tickstart = HAL_GetTick();
8002c68: f7fe ff7c bl 8001b64 <HAL_GetTick>
8002c6c: 0003 movs r3, r0
8002c6e: 60fb str r3, [r7, #12]
while (LL_ADC_IsEnabled(hadc->Instance) != 0UL)
8002c70: e01b b.n 8002caa <HAL_ADCEx_Calibration_Start+0x14a>
{
if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
8002c72: f7fe ff77 bl 8001b64 <HAL_GetTick>
8002c76: 0002 movs r2, r0
8002c78: 68fb ldr r3, [r7, #12]
8002c7a: 1ad3 subs r3, r2, r3
8002c7c: 2b02 cmp r3, #2
8002c7e: d914 bls.n 8002caa <HAL_ADCEx_Calibration_Start+0x14a>
{
/* New check to avoid false timeout detection in case of preemption */
if (LL_ADC_IsEnabled(hadc->Instance) != 0UL)
8002c80: 687b ldr r3, [r7, #4]
8002c82: 681b ldr r3, [r3, #0]
8002c84: 0018 movs r0, r3
8002c86: f7ff ff31 bl 8002aec <LL_ADC_IsEnabled>
8002c8a: 1e03 subs r3, r0, #0
8002c8c: d00d beq.n 8002caa <HAL_ADCEx_Calibration_Start+0x14a>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
8002c8e: 687b ldr r3, [r7, #4]
8002c90: 6d9b ldr r3, [r3, #88] ; 0x58
8002c92: 2210 movs r2, #16
8002c94: 431a orrs r2, r3
8002c96: 687b ldr r3, [r7, #4]
8002c98: 659a str r2, [r3, #88] ; 0x58
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8002c9a: 687b ldr r3, [r7, #4]
8002c9c: 6ddb ldr r3, [r3, #92] ; 0x5c
8002c9e: 2201 movs r2, #1
8002ca0: 431a orrs r2, r3
8002ca2: 687b ldr r3, [r7, #4]
8002ca4: 65da str r2, [r3, #92] ; 0x5c
return HAL_ERROR;
8002ca6: 2301 movs r3, #1
8002ca8: e024 b.n 8002cf4 <HAL_ADCEx_Calibration_Start+0x194>
while (LL_ADC_IsEnabled(hadc->Instance) != 0UL)
8002caa: 687b ldr r3, [r7, #4]
8002cac: 681b ldr r3, [r3, #0]
8002cae: 0018 movs r0, r3
8002cb0: f7ff ff1c bl 8002aec <LL_ADC_IsEnabled>
8002cb4: 1e03 subs r3, r0, #0
8002cb6: d1dc bne.n 8002c72 <HAL_ADCEx_Calibration_Start+0x112>
}
}
}
/* Restore configuration after calibration */
SET_BIT(hadc->Instance->CFGR1, backup_setting_cfgr1);
8002cb8: 687b ldr r3, [r7, #4]
8002cba: 681b ldr r3, [r3, #0]
8002cbc: 68d9 ldr r1, [r3, #12]
8002cbe: 687b ldr r3, [r7, #4]
8002cc0: 681b ldr r3, [r3, #0]
8002cc2: 693a ldr r2, [r7, #16]
8002cc4: 430a orrs r2, r1
8002cc6: 60da str r2, [r3, #12]
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
8002cc8: 687b ldr r3, [r7, #4]
8002cca: 6d9b ldr r3, [r3, #88] ; 0x58
8002ccc: 2203 movs r2, #3
8002cce: 4393 bics r3, r2
8002cd0: 2201 movs r2, #1
8002cd2: 431a orrs r2, r3
8002cd4: 687b ldr r3, [r7, #4]
8002cd6: 659a str r2, [r3, #88] ; 0x58
8002cd8: e005 b.n 8002ce6 <HAL_ADCEx_Calibration_Start+0x186>
HAL_ADC_STATE_BUSY_INTERNAL,
HAL_ADC_STATE_READY);
}
else
{
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
8002cda: 687b ldr r3, [r7, #4]
8002cdc: 6d9b ldr r3, [r3, #88] ; 0x58
8002cde: 2210 movs r2, #16
8002ce0: 431a orrs r2, r3
8002ce2: 687b ldr r3, [r7, #4]
8002ce4: 659a str r2, [r3, #88] ; 0x58
/* Note: No need to update variable "tmp_hal_status" here: already set */
/* to state "HAL_ERROR" by function disabling the ADC. */
}
__HAL_UNLOCK(hadc);
8002ce6: 687b ldr r3, [r7, #4]
8002ce8: 2254 movs r2, #84 ; 0x54
8002cea: 2100 movs r1, #0
8002cec: 5499 strb r1, [r3, r2]
return tmp_hal_status;
8002cee: 2317 movs r3, #23
8002cf0: 18fb adds r3, r7, r3
8002cf2: 781b ldrb r3, [r3, #0]
}
8002cf4: 0018 movs r0, r3
8002cf6: 46bd mov sp, r7
8002cf8: b009 add sp, #36 ; 0x24
8002cfa: bd90 pop {r4, r7, pc}
8002cfc: fffffefd .word 0xfffffefd
8002d00: 00008003 .word 0x00008003
8002d04: ffff7ffc .word 0xffff7ffc
8002d08: 0002f1ff .word 0x0002f1ff
08002d0c <HAL_ADCEx_LevelOutOfWindow2Callback>:
* @brief Analog watchdog 2 callback in non-blocking mode.
* @param hadc ADC handle
* @retval None
*/
__weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc)
{
8002d0c: b580 push {r7, lr}
8002d0e: b082 sub sp, #8
8002d10: af00 add r7, sp, #0
8002d12: 6078 str r0, [r7, #4]
UNUSED(hadc);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_ADCEx_LevelOutOfWindow2Callback must be implemented in the user file.
*/
}
8002d14: 46c0 nop ; (mov r8, r8)
8002d16: 46bd mov sp, r7
8002d18: b002 add sp, #8
8002d1a: bd80 pop {r7, pc}
08002d1c <HAL_ADCEx_LevelOutOfWindow3Callback>:
* @brief Analog watchdog 3 callback in non-blocking mode.
* @param hadc ADC handle
* @retval None
*/
__weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc)
{
8002d1c: b580 push {r7, lr}
8002d1e: b082 sub sp, #8
8002d20: af00 add r7, sp, #0
8002d22: 6078 str r0, [r7, #4]
UNUSED(hadc);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_ADCEx_LevelOutOfWindow3Callback must be implemented in the user file.
*/
}
8002d24: 46c0 nop ; (mov r8, r8)
8002d26: 46bd mov sp, r7
8002d28: b002 add sp, #8
8002d2a: bd80 pop {r7, pc}
08002d2c <HAL_ADCEx_EndOfSamplingCallback>:
* @brief End Of Sampling callback in non-blocking mode.
* @param hadc ADC handle
* @retval None
*/
__weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc)
{
8002d2c: b580 push {r7, lr}
8002d2e: b082 sub sp, #8
8002d30: af00 add r7, sp, #0
8002d32: 6078 str r0, [r7, #4]
UNUSED(hadc);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_ADCEx_EndOfSamplingCallback must be implemented in the user file.
*/
}
8002d34: 46c0 nop ; (mov r8, r8)
8002d36: 46bd mov sp, r7
8002d38: b002 add sp, #8
8002d3a: bd80 pop {r7, pc}
08002d3c <HAL_ADCEx_ChannelConfigReadyCallback>:
* @brief ADC channel configuration ready callback in non-blocking mode.
* @param hadc ADC handle
* @retval None
*/
__weak void HAL_ADCEx_ChannelConfigReadyCallback(ADC_HandleTypeDef *hadc)
{
8002d3c: b580 push {r7, lr}
8002d3e: b082 sub sp, #8
8002d40: af00 add r7, sp, #0
8002d42: 6078 str r0, [r7, #4]
UNUSED(hadc);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_ADCEx_ChannelConfigReadyCallback must be implemented in the user file.
*/
}
8002d44: 46c0 nop ; (mov r8, r8)
8002d46: 46bd mov sp, r7
8002d48: b002 add sp, #8
8002d4a: bd80 pop {r7, pc}
08002d4c <__NVIC_EnableIRQ>:
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
8002d4c: b580 push {r7, lr}
8002d4e: b082 sub sp, #8
8002d50: af00 add r7, sp, #0
8002d52: 0002 movs r2, r0
8002d54: 1dfb adds r3, r7, #7
8002d56: 701a strb r2, [r3, #0]
if ((int32_t)(IRQn) >= 0)
8002d58: 1dfb adds r3, r7, #7
8002d5a: 781b ldrb r3, [r3, #0]
8002d5c: 2b7f cmp r3, #127 ; 0x7f
8002d5e: d809 bhi.n 8002d74 <__NVIC_EnableIRQ+0x28>
{
__COMPILER_BARRIER();
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
8002d60: 1dfb adds r3, r7, #7
8002d62: 781b ldrb r3, [r3, #0]
8002d64: 001a movs r2, r3
8002d66: 231f movs r3, #31
8002d68: 401a ands r2, r3
8002d6a: 4b04 ldr r3, [pc, #16] ; (8002d7c <__NVIC_EnableIRQ+0x30>)
8002d6c: 2101 movs r1, #1
8002d6e: 4091 lsls r1, r2
8002d70: 000a movs r2, r1
8002d72: 601a str r2, [r3, #0]
__COMPILER_BARRIER();
}
}
8002d74: 46c0 nop ; (mov r8, r8)
8002d76: 46bd mov sp, r7
8002d78: b002 add sp, #8
8002d7a: bd80 pop {r7, pc}
8002d7c: e000e100 .word 0xe000e100
08002d80 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
8002d80: b590 push {r4, r7, lr}
8002d82: b083 sub sp, #12
8002d84: af00 add r7, sp, #0
8002d86: 0002 movs r2, r0
8002d88: 6039 str r1, [r7, #0]
8002d8a: 1dfb adds r3, r7, #7
8002d8c: 701a strb r2, [r3, #0]
if ((int32_t)(IRQn) >= 0)
8002d8e: 1dfb adds r3, r7, #7
8002d90: 781b ldrb r3, [r3, #0]
8002d92: 2b7f cmp r3, #127 ; 0x7f
8002d94: d828 bhi.n 8002de8 <__NVIC_SetPriority+0x68>
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
8002d96: 4a2f ldr r2, [pc, #188] ; (8002e54 <__NVIC_SetPriority+0xd4>)
8002d98: 1dfb adds r3, r7, #7
8002d9a: 781b ldrb r3, [r3, #0]
8002d9c: b25b sxtb r3, r3
8002d9e: 089b lsrs r3, r3, #2
8002da0: 33c0 adds r3, #192 ; 0xc0
8002da2: 009b lsls r3, r3, #2
8002da4: 589b ldr r3, [r3, r2]
8002da6: 1dfa adds r2, r7, #7
8002da8: 7812 ldrb r2, [r2, #0]
8002daa: 0011 movs r1, r2
8002dac: 2203 movs r2, #3
8002dae: 400a ands r2, r1
8002db0: 00d2 lsls r2, r2, #3
8002db2: 21ff movs r1, #255 ; 0xff
8002db4: 4091 lsls r1, r2
8002db6: 000a movs r2, r1
8002db8: 43d2 mvns r2, r2
8002dba: 401a ands r2, r3
8002dbc: 0011 movs r1, r2
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
8002dbe: 683b ldr r3, [r7, #0]
8002dc0: 019b lsls r3, r3, #6
8002dc2: 22ff movs r2, #255 ; 0xff
8002dc4: 401a ands r2, r3
8002dc6: 1dfb adds r3, r7, #7
8002dc8: 781b ldrb r3, [r3, #0]
8002dca: 0018 movs r0, r3
8002dcc: 2303 movs r3, #3
8002dce: 4003 ands r3, r0
8002dd0: 00db lsls r3, r3, #3
8002dd2: 409a lsls r2, r3
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
8002dd4: 481f ldr r0, [pc, #124] ; (8002e54 <__NVIC_SetPriority+0xd4>)
8002dd6: 1dfb adds r3, r7, #7
8002dd8: 781b ldrb r3, [r3, #0]
8002dda: b25b sxtb r3, r3
8002ddc: 089b lsrs r3, r3, #2
8002dde: 430a orrs r2, r1
8002de0: 33c0 adds r3, #192 ; 0xc0
8002de2: 009b lsls r3, r3, #2
8002de4: 501a str r2, [r3, r0]
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
8002de6: e031 b.n 8002e4c <__NVIC_SetPriority+0xcc>
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
8002de8: 4a1b ldr r2, [pc, #108] ; (8002e58 <__NVIC_SetPriority+0xd8>)
8002dea: 1dfb adds r3, r7, #7
8002dec: 781b ldrb r3, [r3, #0]
8002dee: 0019 movs r1, r3
8002df0: 230f movs r3, #15
8002df2: 400b ands r3, r1
8002df4: 3b08 subs r3, #8
8002df6: 089b lsrs r3, r3, #2
8002df8: 3306 adds r3, #6
8002dfa: 009b lsls r3, r3, #2
8002dfc: 18d3 adds r3, r2, r3
8002dfe: 3304 adds r3, #4
8002e00: 681b ldr r3, [r3, #0]
8002e02: 1dfa adds r2, r7, #7
8002e04: 7812 ldrb r2, [r2, #0]
8002e06: 0011 movs r1, r2
8002e08: 2203 movs r2, #3
8002e0a: 400a ands r2, r1
8002e0c: 00d2 lsls r2, r2, #3
8002e0e: 21ff movs r1, #255 ; 0xff
8002e10: 4091 lsls r1, r2
8002e12: 000a movs r2, r1
8002e14: 43d2 mvns r2, r2
8002e16: 401a ands r2, r3
8002e18: 0011 movs r1, r2
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
8002e1a: 683b ldr r3, [r7, #0]
8002e1c: 019b lsls r3, r3, #6
8002e1e: 22ff movs r2, #255 ; 0xff
8002e20: 401a ands r2, r3
8002e22: 1dfb adds r3, r7, #7
8002e24: 781b ldrb r3, [r3, #0]
8002e26: 0018 movs r0, r3
8002e28: 2303 movs r3, #3
8002e2a: 4003 ands r3, r0
8002e2c: 00db lsls r3, r3, #3
8002e2e: 409a lsls r2, r3
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
8002e30: 4809 ldr r0, [pc, #36] ; (8002e58 <__NVIC_SetPriority+0xd8>)
8002e32: 1dfb adds r3, r7, #7
8002e34: 781b ldrb r3, [r3, #0]
8002e36: 001c movs r4, r3
8002e38: 230f movs r3, #15
8002e3a: 4023 ands r3, r4
8002e3c: 3b08 subs r3, #8
8002e3e: 089b lsrs r3, r3, #2
8002e40: 430a orrs r2, r1
8002e42: 3306 adds r3, #6
8002e44: 009b lsls r3, r3, #2
8002e46: 18c3 adds r3, r0, r3
8002e48: 3304 adds r3, #4
8002e4a: 601a str r2, [r3, #0]
}
8002e4c: 46c0 nop ; (mov r8, r8)
8002e4e: 46bd mov sp, r7
8002e50: b003 add sp, #12
8002e52: bd90 pop {r4, r7, pc}
8002e54: e000e100 .word 0xe000e100
8002e58: e000ed00 .word 0xe000ed00
08002e5c <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
8002e5c: b580 push {r7, lr}
8002e5e: b082 sub sp, #8
8002e60: af00 add r7, sp, #0
8002e62: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
8002e64: 687b ldr r3, [r7, #4]
8002e66: 1e5a subs r2, r3, #1
8002e68: 2380 movs r3, #128 ; 0x80
8002e6a: 045b lsls r3, r3, #17
8002e6c: 429a cmp r2, r3
8002e6e: d301 bcc.n 8002e74 <SysTick_Config+0x18>
{
return (1UL); /* Reload value impossible */
8002e70: 2301 movs r3, #1
8002e72: e010 b.n 8002e96 <SysTick_Config+0x3a>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
8002e74: 4b0a ldr r3, [pc, #40] ; (8002ea0 <SysTick_Config+0x44>)
8002e76: 687a ldr r2, [r7, #4]
8002e78: 3a01 subs r2, #1
8002e7a: 605a str r2, [r3, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
8002e7c: 2301 movs r3, #1
8002e7e: 425b negs r3, r3
8002e80: 2103 movs r1, #3
8002e82: 0018 movs r0, r3
8002e84: f7ff ff7c bl 8002d80 <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
8002e88: 4b05 ldr r3, [pc, #20] ; (8002ea0 <SysTick_Config+0x44>)
8002e8a: 2200 movs r2, #0
8002e8c: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
8002e8e: 4b04 ldr r3, [pc, #16] ; (8002ea0 <SysTick_Config+0x44>)
8002e90: 2207 movs r2, #7
8002e92: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
8002e94: 2300 movs r3, #0
}
8002e96: 0018 movs r0, r3
8002e98: 46bd mov sp, r7
8002e9a: b002 add sp, #8
8002e9c: bd80 pop {r7, pc}
8002e9e: 46c0 nop ; (mov r8, r8)
8002ea0: e000e010 .word 0xe000e010
08002ea4 <HAL_NVIC_SetPriority>:
* with stm32g0xx devices, this parameter is a dummy value and it is ignored, because
* no subpriority supported in Cortex M0+ based products.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
8002ea4: b580 push {r7, lr}
8002ea6: b084 sub sp, #16
8002ea8: af00 add r7, sp, #0
8002eaa: 60b9 str r1, [r7, #8]
8002eac: 607a str r2, [r7, #4]
8002eae: 210f movs r1, #15
8002eb0: 187b adds r3, r7, r1
8002eb2: 1c02 adds r2, r0, #0
8002eb4: 701a strb r2, [r3, #0]
/* Prevent unused argument(s) compilation warning */
UNUSED(SubPriority);
/* Check the parameters */
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
NVIC_SetPriority(IRQn, PreemptPriority);
8002eb6: 68ba ldr r2, [r7, #8]
8002eb8: 187b adds r3, r7, r1
8002eba: 781b ldrb r3, [r3, #0]
8002ebc: b25b sxtb r3, r3
8002ebe: 0011 movs r1, r2
8002ec0: 0018 movs r0, r3
8002ec2: f7ff ff5d bl 8002d80 <__NVIC_SetPriority>
}
8002ec6: 46c0 nop ; (mov r8, r8)
8002ec8: 46bd mov sp, r7
8002eca: b004 add sp, #16
8002ecc: bd80 pop {r7, pc}
08002ece <HAL_NVIC_EnableIRQ>:
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g0xxxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
8002ece: b580 push {r7, lr}
8002ed0: b082 sub sp, #8
8002ed2: af00 add r7, sp, #0
8002ed4: 0002 movs r2, r0
8002ed6: 1dfb adds r3, r7, #7
8002ed8: 701a strb r2, [r3, #0]
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
8002eda: 1dfb adds r3, r7, #7
8002edc: 781b ldrb r3, [r3, #0]
8002ede: b25b sxtb r3, r3
8002ee0: 0018 movs r0, r3
8002ee2: f7ff ff33 bl 8002d4c <__NVIC_EnableIRQ>
}
8002ee6: 46c0 nop ; (mov r8, r8)
8002ee8: 46bd mov sp, r7
8002eea: b002 add sp, #8
8002eec: bd80 pop {r7, pc}
08002eee <HAL_SYSTICK_Config>:
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
8002eee: b580 push {r7, lr}
8002ef0: b082 sub sp, #8
8002ef2: af00 add r7, sp, #0
8002ef4: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
8002ef6: 687b ldr r3, [r7, #4]
8002ef8: 0018 movs r0, r3
8002efa: f7ff ffaf bl 8002e5c <SysTick_Config>
8002efe: 0003 movs r3, r0
}
8002f00: 0018 movs r0, r3
8002f02: 46bd mov sp, r7
8002f04: b002 add sp, #8
8002f06: bd80 pop {r7, pc}
08002f08 <HAL_DMA_Init>:
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
{
8002f08: b580 push {r7, lr}
8002f0a: b082 sub sp, #8
8002f0c: af00 add r7, sp, #0
8002f0e: 6078 str r0, [r7, #4]
/* Check the DMA handle allocation */
if (hdma == NULL)
8002f10: 687b ldr r3, [r7, #4]
8002f12: 2b00 cmp r3, #0
8002f14: d101 bne.n 8002f1a <HAL_DMA_Init+0x12>
{
return HAL_ERROR;
8002f16: 2301 movs r3, #1
8002f18: e077 b.n 800300a <HAL_DMA_Init+0x102>
/* DMA2 */
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U;
hdma->DmaBaseAddress = DMA2;
}
#else
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
8002f1a: 687b ldr r3, [r7, #4]
8002f1c: 681b ldr r3, [r3, #0]
8002f1e: 4a3d ldr r2, [pc, #244] ; (8003014 <HAL_DMA_Init+0x10c>)
8002f20: 4694 mov ip, r2
8002f22: 4463 add r3, ip
8002f24: 2114 movs r1, #20
8002f26: 0018 movs r0, r3
8002f28: f7fd f8ec bl 8000104 <__udivsi3>
8002f2c: 0003 movs r3, r0
8002f2e: 009a lsls r2, r3, #2
8002f30: 687b ldr r3, [r7, #4]
8002f32: 641a str r2, [r3, #64] ; 0x40
#endif /* DMA2 */
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
8002f34: 687b ldr r3, [r7, #4]
8002f36: 2225 movs r2, #37 ; 0x25
8002f38: 2102 movs r1, #2
8002f3a: 5499 strb r1, [r3, r2]
/* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */
CLEAR_BIT(hdma->Instance->CCR, (DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \
8002f3c: 687b ldr r3, [r7, #4]
8002f3e: 681b ldr r3, [r3, #0]
8002f40: 681a ldr r2, [r3, #0]
8002f42: 687b ldr r3, [r7, #4]
8002f44: 681b ldr r3, [r3, #0]
8002f46: 4934 ldr r1, [pc, #208] ; (8003018 <HAL_DMA_Init+0x110>)
8002f48: 400a ands r2, r1
8002f4a: 601a str r2, [r3, #0]
DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \
DMA_CCR_DIR | DMA_CCR_MEM2MEM));
/* Set the DMA Channel configuration */
SET_BIT(hdma->Instance->CCR, (hdma->Init.Direction | \
8002f4c: 687b ldr r3, [r7, #4]
8002f4e: 681b ldr r3, [r3, #0]
8002f50: 6819 ldr r1, [r3, #0]
8002f52: 687b ldr r3, [r7, #4]
8002f54: 689a ldr r2, [r3, #8]
8002f56: 687b ldr r3, [r7, #4]
8002f58: 68db ldr r3, [r3, #12]
8002f5a: 431a orrs r2, r3
8002f5c: 687b ldr r3, [r7, #4]
8002f5e: 691b ldr r3, [r3, #16]
8002f60: 431a orrs r2, r3
8002f62: 687b ldr r3, [r7, #4]
8002f64: 695b ldr r3, [r3, #20]
8002f66: 431a orrs r2, r3
8002f68: 687b ldr r3, [r7, #4]
8002f6a: 699b ldr r3, [r3, #24]
8002f6c: 431a orrs r2, r3
8002f6e: 687b ldr r3, [r7, #4]
8002f70: 69db ldr r3, [r3, #28]
8002f72: 431a orrs r2, r3
8002f74: 687b ldr r3, [r7, #4]
8002f76: 6a1b ldr r3, [r3, #32]
8002f78: 431a orrs r2, r3
8002f7a: 687b ldr r3, [r7, #4]
8002f7c: 681b ldr r3, [r3, #0]
8002f7e: 430a orrs r2, r1
8002f80: 601a str r2, [r3, #0]
hdma->Init.Mode | hdma->Init.Priority));
/* Initialize parameters for DMAMUX channel :
DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask
*/
DMA_CalcDMAMUXChannelBaseAndMask(hdma);
8002f82: 687b ldr r3, [r7, #4]
8002f84: 0018 movs r0, r3
8002f86: f000 fa8d bl 80034a4 <DMA_CalcDMAMUXChannelBaseAndMask>
if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
8002f8a: 687b ldr r3, [r7, #4]
8002f8c: 689a ldr r2, [r3, #8]
8002f8e: 2380 movs r3, #128 ; 0x80
8002f90: 01db lsls r3, r3, #7
8002f92: 429a cmp r2, r3
8002f94: d102 bne.n 8002f9c <HAL_DMA_Init+0x94>
{
/* if memory to memory force the request to 0*/
hdma->Init.Request = DMA_REQUEST_MEM2MEM;
8002f96: 687b ldr r3, [r7, #4]
8002f98: 2200 movs r2, #0
8002f9a: 605a str r2, [r3, #4]
}
/* Set peripheral request to DMAMUX channel */
hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID);
8002f9c: 687b ldr r3, [r7, #4]
8002f9e: 685a ldr r2, [r3, #4]
8002fa0: 687b ldr r3, [r7, #4]
8002fa2: 6c5b ldr r3, [r3, #68] ; 0x44
8002fa4: 213f movs r1, #63 ; 0x3f
8002fa6: 400a ands r2, r1
8002fa8: 601a str r2, [r3, #0]
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
8002faa: 687b ldr r3, [r7, #4]
8002fac: 6c9b ldr r3, [r3, #72] ; 0x48
8002fae: 687a ldr r2, [r7, #4]
8002fb0: 6cd2 ldr r2, [r2, #76] ; 0x4c
8002fb2: 605a str r2, [r3, #4]
if (((hdma->Init.Request > 0UL) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3)))
8002fb4: 687b ldr r3, [r7, #4]
8002fb6: 685b ldr r3, [r3, #4]
8002fb8: 2b00 cmp r3, #0
8002fba: d011 beq.n 8002fe0 <HAL_DMA_Init+0xd8>
8002fbc: 687b ldr r3, [r7, #4]
8002fbe: 685b ldr r3, [r3, #4]
8002fc0: 2b04 cmp r3, #4
8002fc2: d80d bhi.n 8002fe0 <HAL_DMA_Init+0xd8>
{
/* Initialize parameters for DMAMUX request generator :
DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask
*/
DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
8002fc4: 687b ldr r3, [r7, #4]
8002fc6: 0018 movs r0, r3
8002fc8: f000 fa98 bl 80034fc <DMA_CalcDMAMUXRequestGenBaseAndMask>
/* Reset the DMAMUX request generator register*/
hdma->DMAmuxRequestGen->RGCR = 0U;
8002fcc: 687b ldr r3, [r7, #4]
8002fce: 6d1b ldr r3, [r3, #80] ; 0x50
8002fd0: 2200 movs r2, #0
8002fd2: 601a str r2, [r3, #0]
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
8002fd4: 687b ldr r3, [r7, #4]
8002fd6: 6d5b ldr r3, [r3, #84] ; 0x54
8002fd8: 687a ldr r2, [r7, #4]
8002fda: 6d92 ldr r2, [r2, #88] ; 0x58
8002fdc: 605a str r2, [r3, #4]
8002fde: e008 b.n 8002ff2 <HAL_DMA_Init+0xea>
}
else
{
hdma->DMAmuxRequestGen = 0U;
8002fe0: 687b ldr r3, [r7, #4]
8002fe2: 2200 movs r2, #0
8002fe4: 651a str r2, [r3, #80] ; 0x50
hdma->DMAmuxRequestGenStatus = 0U;
8002fe6: 687b ldr r3, [r7, #4]
8002fe8: 2200 movs r2, #0
8002fea: 655a str r2, [r3, #84] ; 0x54
hdma->DMAmuxRequestGenStatusMask = 0U;
8002fec: 687b ldr r3, [r7, #4]
8002fee: 2200 movs r2, #0
8002ff0: 659a str r2, [r3, #88] ; 0x58
}
/* Initialize the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
8002ff2: 687b ldr r3, [r7, #4]
8002ff4: 2200 movs r2, #0
8002ff6: 63da str r2, [r3, #60] ; 0x3c
/* Initialize the DMA state*/
hdma->State = HAL_DMA_STATE_READY;
8002ff8: 687b ldr r3, [r7, #4]
8002ffa: 2225 movs r2, #37 ; 0x25
8002ffc: 2101 movs r1, #1
8002ffe: 5499 strb r1, [r3, r2]
/* Release Lock */
__HAL_UNLOCK(hdma);
8003000: 687b ldr r3, [r7, #4]
8003002: 2224 movs r2, #36 ; 0x24
8003004: 2100 movs r1, #0
8003006: 5499 strb r1, [r3, r2]
return HAL_OK;
8003008: 2300 movs r3, #0
}
800300a: 0018 movs r0, r3
800300c: 46bd mov sp, r7
800300e: b002 add sp, #8
8003010: bd80 pop {r7, pc}
8003012: 46c0 nop ; (mov r8, r8)
8003014: bffdfff8 .word 0xbffdfff8
8003018: ffff800f .word 0xffff800f
0800301c <HAL_DMA_Start_IT>:
* @param DataLength The length of data to be transferred from source to destination
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress,
uint32_t DataLength)
{
800301c: b580 push {r7, lr}
800301e: b086 sub sp, #24
8003020: af00 add r7, sp, #0
8003022: 60f8 str r0, [r7, #12]
8003024: 60b9 str r1, [r7, #8]
8003026: 607a str r2, [r7, #4]
8003028: 603b str r3, [r7, #0]
HAL_StatusTypeDef status = HAL_OK;
800302a: 2317 movs r3, #23
800302c: 18fb adds r3, r7, r3
800302e: 2200 movs r2, #0
8003030: 701a strb r2, [r3, #0]
/* Check the parameters */
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
/* Process locked */
__HAL_LOCK(hdma);
8003032: 68fb ldr r3, [r7, #12]
8003034: 2224 movs r2, #36 ; 0x24
8003036: 5c9b ldrb r3, [r3, r2]
8003038: 2b01 cmp r3, #1
800303a: d101 bne.n 8003040 <HAL_DMA_Start_IT+0x24>
800303c: 2302 movs r3, #2
800303e: e06f b.n 8003120 <HAL_DMA_Start_IT+0x104>
8003040: 68fb ldr r3, [r7, #12]
8003042: 2224 movs r2, #36 ; 0x24
8003044: 2101 movs r1, #1
8003046: 5499 strb r1, [r3, r2]
if (hdma->State == HAL_DMA_STATE_READY)
8003048: 68fb ldr r3, [r7, #12]
800304a: 2225 movs r2, #37 ; 0x25
800304c: 5c9b ldrb r3, [r3, r2]
800304e: b2db uxtb r3, r3
8003050: 2b01 cmp r3, #1
8003052: d157 bne.n 8003104 <HAL_DMA_Start_IT+0xe8>
{
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
8003054: 68fb ldr r3, [r7, #12]
8003056: 2225 movs r2, #37 ; 0x25
8003058: 2102 movs r1, #2
800305a: 5499 strb r1, [r3, r2]
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
800305c: 68fb ldr r3, [r7, #12]
800305e: 2200 movs r2, #0
8003060: 63da str r2, [r3, #60] ; 0x3c
/* Disable the peripheral */
__HAL_DMA_DISABLE(hdma);
8003062: 68fb ldr r3, [r7, #12]
8003064: 681b ldr r3, [r3, #0]
8003066: 681a ldr r2, [r3, #0]
8003068: 68fb ldr r3, [r7, #12]
800306a: 681b ldr r3, [r3, #0]
800306c: 2101 movs r1, #1
800306e: 438a bics r2, r1
8003070: 601a str r2, [r3, #0]
/* Configure the source, destination address and the data length & clear flags*/
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
8003072: 683b ldr r3, [r7, #0]
8003074: 687a ldr r2, [r7, #4]
8003076: 68b9 ldr r1, [r7, #8]
8003078: 68f8 ldr r0, [r7, #12]
800307a: f000 f9d3 bl 8003424 <DMA_SetConfig>
/* Enable the transfer complete interrupt */
/* Enable the transfer Error interrupt */
if (NULL != hdma->XferHalfCpltCallback)
800307e: 68fb ldr r3, [r7, #12]
8003080: 6b1b ldr r3, [r3, #48] ; 0x30
8003082: 2b00 cmp r3, #0
8003084: d008 beq.n 8003098 <HAL_DMA_Start_IT+0x7c>
{
/* Enable the Half transfer complete interrupt as well */
__HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
8003086: 68fb ldr r3, [r7, #12]
8003088: 681b ldr r3, [r3, #0]
800308a: 681a ldr r2, [r3, #0]
800308c: 68fb ldr r3, [r7, #12]
800308e: 681b ldr r3, [r3, #0]
8003090: 210e movs r1, #14
8003092: 430a orrs r2, r1
8003094: 601a str r2, [r3, #0]
8003096: e00f b.n 80030b8 <HAL_DMA_Start_IT+0x9c>
}
else
{
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
8003098: 68fb ldr r3, [r7, #12]
800309a: 681b ldr r3, [r3, #0]
800309c: 681a ldr r2, [r3, #0]
800309e: 68fb ldr r3, [r7, #12]
80030a0: 681b ldr r3, [r3, #0]
80030a2: 2104 movs r1, #4
80030a4: 438a bics r2, r1
80030a6: 601a str r2, [r3, #0]
__HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
80030a8: 68fb ldr r3, [r7, #12]
80030aa: 681b ldr r3, [r3, #0]
80030ac: 681a ldr r2, [r3, #0]
80030ae: 68fb ldr r3, [r7, #12]
80030b0: 681b ldr r3, [r3, #0]
80030b2: 210a movs r1, #10
80030b4: 430a orrs r2, r1
80030b6: 601a str r2, [r3, #0]
}
/* Check if DMAMUX Synchronization is enabled*/
if ((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
80030b8: 68fb ldr r3, [r7, #12]
80030ba: 6c5b ldr r3, [r3, #68] ; 0x44
80030bc: 681a ldr r2, [r3, #0]
80030be: 2380 movs r3, #128 ; 0x80
80030c0: 025b lsls r3, r3, #9
80030c2: 4013 ands r3, r2
80030c4: d008 beq.n 80030d8 <HAL_DMA_Start_IT+0xbc>
{
/* Enable DMAMUX sync overrun IT*/
hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
80030c6: 68fb ldr r3, [r7, #12]
80030c8: 6c5b ldr r3, [r3, #68] ; 0x44
80030ca: 681a ldr r2, [r3, #0]
80030cc: 68fb ldr r3, [r7, #12]
80030ce: 6c5b ldr r3, [r3, #68] ; 0x44
80030d0: 2180 movs r1, #128 ; 0x80
80030d2: 0049 lsls r1, r1, #1
80030d4: 430a orrs r2, r1
80030d6: 601a str r2, [r3, #0]
}
if (hdma->DMAmuxRequestGen != 0U)
80030d8: 68fb ldr r3, [r7, #12]
80030da: 6d1b ldr r3, [r3, #80] ; 0x50
80030dc: 2b00 cmp r3, #0
80030de: d008 beq.n 80030f2 <HAL_DMA_Start_IT+0xd6>
{
/* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/
/* enable the request gen overrun IT*/
hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
80030e0: 68fb ldr r3, [r7, #12]
80030e2: 6d1b ldr r3, [r3, #80] ; 0x50
80030e4: 681a ldr r2, [r3, #0]
80030e6: 68fb ldr r3, [r7, #12]
80030e8: 6d1b ldr r3, [r3, #80] ; 0x50
80030ea: 2180 movs r1, #128 ; 0x80
80030ec: 0049 lsls r1, r1, #1
80030ee: 430a orrs r2, r1
80030f0: 601a str r2, [r3, #0]
}
/* Enable the Peripheral */
__HAL_DMA_ENABLE(hdma);
80030f2: 68fb ldr r3, [r7, #12]
80030f4: 681b ldr r3, [r3, #0]
80030f6: 681a ldr r2, [r3, #0]
80030f8: 68fb ldr r3, [r7, #12]
80030fa: 681b ldr r3, [r3, #0]
80030fc: 2101 movs r1, #1
80030fe: 430a orrs r2, r1
8003100: 601a str r2, [r3, #0]
8003102: e00a b.n 800311a <HAL_DMA_Start_IT+0xfe>
}
else
{
/* Change the error code */
hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
8003104: 68fb ldr r3, [r7, #12]
8003106: 2280 movs r2, #128 ; 0x80
8003108: 63da str r2, [r3, #60] ; 0x3c
/* Process Unlocked */
__HAL_UNLOCK(hdma);
800310a: 68fb ldr r3, [r7, #12]
800310c: 2224 movs r2, #36 ; 0x24
800310e: 2100 movs r1, #0
8003110: 5499 strb r1, [r3, r2]
/* Return error status */
status = HAL_ERROR;
8003112: 2317 movs r3, #23
8003114: 18fb adds r3, r7, r3
8003116: 2201 movs r2, #1
8003118: 701a strb r2, [r3, #0]
}
return status;
800311a: 2317 movs r3, #23
800311c: 18fb adds r3, r7, r3
800311e: 781b ldrb r3, [r3, #0]
}
8003120: 0018 movs r0, r3
8003122: 46bd mov sp, r7
8003124: b006 add sp, #24
8003126: bd80 pop {r7, pc}
08003128 <HAL_DMA_Abort>:
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
{
8003128: b580 push {r7, lr}
800312a: b082 sub sp, #8
800312c: af00 add r7, sp, #0
800312e: 6078 str r0, [r7, #4]
/* Check the DMA peripheral handle */
if (NULL == hdma)
8003130: 687b ldr r3, [r7, #4]
8003132: 2b00 cmp r3, #0
8003134: d101 bne.n 800313a <HAL_DMA_Abort+0x12>
{
return HAL_ERROR;
8003136: 2301 movs r3, #1
8003138: e050 b.n 80031dc <HAL_DMA_Abort+0xb4>
}
/* Check the DMA peripheral state */
if (hdma->State != HAL_DMA_STATE_BUSY)
800313a: 687b ldr r3, [r7, #4]
800313c: 2225 movs r2, #37 ; 0x25
800313e: 5c9b ldrb r3, [r3, r2]
8003140: b2db uxtb r3, r3
8003142: 2b02 cmp r3, #2
8003144: d008 beq.n 8003158 <HAL_DMA_Abort+0x30>
{
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
8003146: 687b ldr r3, [r7, #4]
8003148: 2204 movs r2, #4
800314a: 63da str r2, [r3, #60] ; 0x3c
/* Process Unlocked */
__HAL_UNLOCK(hdma);
800314c: 687b ldr r3, [r7, #4]
800314e: 2224 movs r2, #36 ; 0x24
8003150: 2100 movs r1, #0
8003152: 5499 strb r1, [r3, r2]
return HAL_ERROR;
8003154: 2301 movs r3, #1
8003156: e041 b.n 80031dc <HAL_DMA_Abort+0xb4>
}
else
{
/* Disable DMA IT */
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
8003158: 687b ldr r3, [r7, #4]
800315a: 681b ldr r3, [r3, #0]
800315c: 681a ldr r2, [r3, #0]
800315e: 687b ldr r3, [r7, #4]
8003160: 681b ldr r3, [r3, #0]
8003162: 210e movs r1, #14
8003164: 438a bics r2, r1
8003166: 601a str r2, [r3, #0]
/* disable the DMAMUX sync overrun IT*/
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
8003168: 687b ldr r3, [r7, #4]
800316a: 6c5b ldr r3, [r3, #68] ; 0x44
800316c: 681a ldr r2, [r3, #0]
800316e: 687b ldr r3, [r7, #4]
8003170: 6c5b ldr r3, [r3, #68] ; 0x44
8003172: 491c ldr r1, [pc, #112] ; (80031e4 <HAL_DMA_Abort+0xbc>)
8003174: 400a ands r2, r1
8003176: 601a str r2, [r3, #0]
/* Disable the channel */
__HAL_DMA_DISABLE(hdma);
8003178: 687b ldr r3, [r7, #4]
800317a: 681b ldr r3, [r3, #0]
800317c: 681a ldr r2, [r3, #0]
800317e: 687b ldr r3, [r7, #4]
8003180: 681b ldr r3, [r3, #0]
8003182: 2101 movs r1, #1
8003184: 438a bics r2, r1
8003186: 601a str r2, [r3, #0]
/* Clear all flags */
#if defined(DMA2)
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
#else
__HAL_DMA_CLEAR_FLAG(hdma, ((DMA_FLAG_GI1) << (hdma->ChannelIndex & 0x1CU)));
8003188: 4b17 ldr r3, [pc, #92] ; (80031e8 <HAL_DMA_Abort+0xc0>)
800318a: 6859 ldr r1, [r3, #4]
800318c: 687b ldr r3, [r7, #4]
800318e: 6c1b ldr r3, [r3, #64] ; 0x40
8003190: 221c movs r2, #28
8003192: 4013 ands r3, r2
8003194: 2201 movs r2, #1
8003196: 409a lsls r2, r3
8003198: 4b13 ldr r3, [pc, #76] ; (80031e8 <HAL_DMA_Abort+0xc0>)
800319a: 430a orrs r2, r1
800319c: 605a str r2, [r3, #4]
#endif /* DMA2 */
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
800319e: 687b ldr r3, [r7, #4]
80031a0: 6c9b ldr r3, [r3, #72] ; 0x48
80031a2: 687a ldr r2, [r7, #4]
80031a4: 6cd2 ldr r2, [r2, #76] ; 0x4c
80031a6: 605a str r2, [r3, #4]
if (hdma->DMAmuxRequestGen != 0U)
80031a8: 687b ldr r3, [r7, #4]
80031aa: 6d1b ldr r3, [r3, #80] ; 0x50
80031ac: 2b00 cmp r3, #0
80031ae: d00c beq.n 80031ca <HAL_DMA_Abort+0xa2>
{
/* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
/* disable the request gen overrun IT*/
hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
80031b0: 687b ldr r3, [r7, #4]
80031b2: 6d1b ldr r3, [r3, #80] ; 0x50
80031b4: 681a ldr r2, [r3, #0]
80031b6: 687b ldr r3, [r7, #4]
80031b8: 6d1b ldr r3, [r3, #80] ; 0x50
80031ba: 490a ldr r1, [pc, #40] ; (80031e4 <HAL_DMA_Abort+0xbc>)
80031bc: 400a ands r2, r1
80031be: 601a str r2, [r3, #0]
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
80031c0: 687b ldr r3, [r7, #4]
80031c2: 6d5b ldr r3, [r3, #84] ; 0x54
80031c4: 687a ldr r2, [r7, #4]
80031c6: 6d92 ldr r2, [r2, #88] ; 0x58
80031c8: 605a str r2, [r3, #4]
}
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
80031ca: 687b ldr r3, [r7, #4]
80031cc: 2225 movs r2, #37 ; 0x25
80031ce: 2101 movs r1, #1
80031d0: 5499 strb r1, [r3, r2]
/* Process Unlocked */
__HAL_UNLOCK(hdma);
80031d2: 687b ldr r3, [r7, #4]
80031d4: 2224 movs r2, #36 ; 0x24
80031d6: 2100 movs r1, #0
80031d8: 5499 strb r1, [r3, r2]
}
return HAL_OK;
80031da: 2300 movs r3, #0
}
80031dc: 0018 movs r0, r3
80031de: 46bd mov sp, r7
80031e0: b002 add sp, #8
80031e2: bd80 pop {r7, pc}
80031e4: fffffeff .word 0xfffffeff
80031e8: 40020000 .word 0x40020000
080031ec <HAL_DMA_Abort_IT>:
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
{
80031ec: b580 push {r7, lr}
80031ee: b084 sub sp, #16
80031f0: af00 add r7, sp, #0
80031f2: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
80031f4: 210f movs r1, #15
80031f6: 187b adds r3, r7, r1
80031f8: 2200 movs r2, #0
80031fa: 701a strb r2, [r3, #0]
if (hdma->State != HAL_DMA_STATE_BUSY)
80031fc: 687b ldr r3, [r7, #4]
80031fe: 2225 movs r2, #37 ; 0x25
8003200: 5c9b ldrb r3, [r3, r2]
8003202: b2db uxtb r3, r3
8003204: 2b02 cmp r3, #2
8003206: d006 beq.n 8003216 <HAL_DMA_Abort_IT+0x2a>
{
/* no transfer ongoing */
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
8003208: 687b ldr r3, [r7, #4]
800320a: 2204 movs r2, #4
800320c: 63da str r2, [r3, #60] ; 0x3c
status = HAL_ERROR;
800320e: 187b adds r3, r7, r1
8003210: 2201 movs r2, #1
8003212: 701a strb r2, [r3, #0]
8003214: e049 b.n 80032aa <HAL_DMA_Abort_IT+0xbe>
}
else
{
/* Disable DMA IT */
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
8003216: 687b ldr r3, [r7, #4]
8003218: 681b ldr r3, [r3, #0]
800321a: 681a ldr r2, [r3, #0]
800321c: 687b ldr r3, [r7, #4]
800321e: 681b ldr r3, [r3, #0]
8003220: 210e movs r1, #14
8003222: 438a bics r2, r1
8003224: 601a str r2, [r3, #0]
/* Disable the channel */
__HAL_DMA_DISABLE(hdma);
8003226: 687b ldr r3, [r7, #4]
8003228: 681b ldr r3, [r3, #0]
800322a: 681a ldr r2, [r3, #0]
800322c: 687b ldr r3, [r7, #4]
800322e: 681b ldr r3, [r3, #0]
8003230: 2101 movs r1, #1
8003232: 438a bics r2, r1
8003234: 601a str r2, [r3, #0]
/* disable the DMAMUX sync overrun IT*/
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
8003236: 687b ldr r3, [r7, #4]
8003238: 6c5b ldr r3, [r3, #68] ; 0x44
800323a: 681a ldr r2, [r3, #0]
800323c: 687b ldr r3, [r7, #4]
800323e: 6c5b ldr r3, [r3, #68] ; 0x44
8003240: 491d ldr r1, [pc, #116] ; (80032b8 <HAL_DMA_Abort_IT+0xcc>)
8003242: 400a ands r2, r1
8003244: 601a str r2, [r3, #0]
/* Clear all flags */
#if defined(DMA2)
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
#else
__HAL_DMA_CLEAR_FLAG(hdma, ((DMA_FLAG_GI1) << (hdma->ChannelIndex & 0x1CU)));
8003246: 4b1d ldr r3, [pc, #116] ; (80032bc <HAL_DMA_Abort_IT+0xd0>)
8003248: 6859 ldr r1, [r3, #4]
800324a: 687b ldr r3, [r7, #4]
800324c: 6c1b ldr r3, [r3, #64] ; 0x40
800324e: 221c movs r2, #28
8003250: 4013 ands r3, r2
8003252: 2201 movs r2, #1
8003254: 409a lsls r2, r3
8003256: 4b19 ldr r3, [pc, #100] ; (80032bc <HAL_DMA_Abort_IT+0xd0>)
8003258: 430a orrs r2, r1
800325a: 605a str r2, [r3, #4]
#endif /* DMA2 */
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
800325c: 687b ldr r3, [r7, #4]
800325e: 6c9b ldr r3, [r3, #72] ; 0x48
8003260: 687a ldr r2, [r7, #4]
8003262: 6cd2 ldr r2, [r2, #76] ; 0x4c
8003264: 605a str r2, [r3, #4]
if (hdma->DMAmuxRequestGen != 0U)
8003266: 687b ldr r3, [r7, #4]
8003268: 6d1b ldr r3, [r3, #80] ; 0x50
800326a: 2b00 cmp r3, #0
800326c: d00c beq.n 8003288 <HAL_DMA_Abort_IT+0x9c>
{
/* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
/* disable the request gen overrun IT*/
hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
800326e: 687b ldr r3, [r7, #4]
8003270: 6d1b ldr r3, [r3, #80] ; 0x50
8003272: 681a ldr r2, [r3, #0]
8003274: 687b ldr r3, [r7, #4]
8003276: 6d1b ldr r3, [r3, #80] ; 0x50
8003278: 490f ldr r1, [pc, #60] ; (80032b8 <HAL_DMA_Abort_IT+0xcc>)
800327a: 400a ands r2, r1
800327c: 601a str r2, [r3, #0]
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
800327e: 687b ldr r3, [r7, #4]
8003280: 6d5b ldr r3, [r3, #84] ; 0x54
8003282: 687a ldr r2, [r7, #4]
8003284: 6d92 ldr r2, [r2, #88] ; 0x58
8003286: 605a str r2, [r3, #4]
}
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
8003288: 687b ldr r3, [r7, #4]
800328a: 2225 movs r2, #37 ; 0x25
800328c: 2101 movs r1, #1
800328e: 5499 strb r1, [r3, r2]
/* Process Unlocked */
__HAL_UNLOCK(hdma);
8003290: 687b ldr r3, [r7, #4]
8003292: 2224 movs r2, #36 ; 0x24
8003294: 2100 movs r1, #0
8003296: 5499 strb r1, [r3, r2]
/* Call User Abort callback */
if (hdma->XferAbortCallback != NULL)
8003298: 687b ldr r3, [r7, #4]
800329a: 6b9b ldr r3, [r3, #56] ; 0x38
800329c: 2b00 cmp r3, #0
800329e: d004 beq.n 80032aa <HAL_DMA_Abort_IT+0xbe>
{
hdma->XferAbortCallback(hdma);
80032a0: 687b ldr r3, [r7, #4]
80032a2: 6b9b ldr r3, [r3, #56] ; 0x38
80032a4: 687a ldr r2, [r7, #4]
80032a6: 0010 movs r0, r2
80032a8: 4798 blx r3
}
}
return status;
80032aa: 230f movs r3, #15
80032ac: 18fb adds r3, r7, r3
80032ae: 781b ldrb r3, [r3, #0]
}
80032b0: 0018 movs r0, r3
80032b2: 46bd mov sp, r7
80032b4: b004 add sp, #16
80032b6: bd80 pop {r7, pc}
80032b8: fffffeff .word 0xfffffeff
80032bc: 40020000 .word 0x40020000
080032c0 <HAL_DMA_IRQHandler>:
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval None
*/
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
{
80032c0: b580 push {r7, lr}
80032c2: b084 sub sp, #16
80032c4: af00 add r7, sp, #0
80032c6: 6078 str r0, [r7, #4]
#if defined(DMA2)
uint32_t flag_it = hdma->DmaBaseAddress->ISR;
#else
uint32_t flag_it = DMA1->ISR;
80032c8: 4b55 ldr r3, [pc, #340] ; (8003420 <HAL_DMA_IRQHandler+0x160>)
80032ca: 681b ldr r3, [r3, #0]
80032cc: 60fb str r3, [r7, #12]
#endif /* DMA2 */
uint32_t source_it = hdma->Instance->CCR;
80032ce: 687b ldr r3, [r7, #4]
80032d0: 681b ldr r3, [r3, #0]
80032d2: 681b ldr r3, [r3, #0]
80032d4: 60bb str r3, [r7, #8]
/* Half Transfer Complete Interrupt management ******************************/
if (((flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_HT) != 0U))
80032d6: 687b ldr r3, [r7, #4]
80032d8: 6c1b ldr r3, [r3, #64] ; 0x40
80032da: 221c movs r2, #28
80032dc: 4013 ands r3, r2
80032de: 2204 movs r2, #4
80032e0: 409a lsls r2, r3
80032e2: 0013 movs r3, r2
80032e4: 68fa ldr r2, [r7, #12]
80032e6: 4013 ands r3, r2
80032e8: d027 beq.n 800333a <HAL_DMA_IRQHandler+0x7a>
80032ea: 68bb ldr r3, [r7, #8]
80032ec: 2204 movs r2, #4
80032ee: 4013 ands r3, r2
80032f0: d023 beq.n 800333a <HAL_DMA_IRQHandler+0x7a>
{
/* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
80032f2: 687b ldr r3, [r7, #4]
80032f4: 681b ldr r3, [r3, #0]
80032f6: 681b ldr r3, [r3, #0]
80032f8: 2220 movs r2, #32
80032fa: 4013 ands r3, r2
80032fc: d107 bne.n 800330e <HAL_DMA_IRQHandler+0x4e>
{
/* Disable the half transfer interrupt */
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
80032fe: 687b ldr r3, [r7, #4]
8003300: 681b ldr r3, [r3, #0]
8003302: 681a ldr r2, [r3, #0]
8003304: 687b ldr r3, [r7, #4]
8003306: 681b ldr r3, [r3, #0]
8003308: 2104 movs r1, #4
800330a: 438a bics r2, r1
800330c: 601a str r2, [r3, #0]
}
/* Clear the half transfer complete flag */
#if defined(DMA2)
hdma->DmaBaseAddress->IFCR = DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1CU);
#else
__HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU)));
800330e: 4b44 ldr r3, [pc, #272] ; (8003420 <HAL_DMA_IRQHandler+0x160>)
8003310: 6859 ldr r1, [r3, #4]
8003312: 687b ldr r3, [r7, #4]
8003314: 6c1b ldr r3, [r3, #64] ; 0x40
8003316: 221c movs r2, #28
8003318: 4013 ands r3, r2
800331a: 2204 movs r2, #4
800331c: 409a lsls r2, r3
800331e: 4b40 ldr r3, [pc, #256] ; (8003420 <HAL_DMA_IRQHandler+0x160>)
8003320: 430a orrs r2, r1
8003322: 605a str r2, [r3, #4]
#endif /* DMA2 */
/* DMA peripheral state is not updated in Half Transfer */
/* but in Transfer Complete case */
if (hdma->XferHalfCpltCallback != NULL)
8003324: 687b ldr r3, [r7, #4]
8003326: 6b1b ldr r3, [r3, #48] ; 0x30
8003328: 2b00 cmp r3, #0
800332a: d100 bne.n 800332e <HAL_DMA_IRQHandler+0x6e>
800332c: e073 b.n 8003416 <HAL_DMA_IRQHandler+0x156>
{
/* Half transfer callback */
hdma->XferHalfCpltCallback(hdma);
800332e: 687b ldr r3, [r7, #4]
8003330: 6b1b ldr r3, [r3, #48] ; 0x30
8003332: 687a ldr r2, [r7, #4]
8003334: 0010 movs r0, r2
8003336: 4798 blx r3
if (hdma->XferHalfCpltCallback != NULL)
8003338: e06d b.n 8003416 <HAL_DMA_IRQHandler+0x156>
}
}
/* Transfer Complete Interrupt management ***********************************/
else if ((0U != (flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU)))) && (0U != (source_it & DMA_IT_TC)))
800333a: 687b ldr r3, [r7, #4]
800333c: 6c1b ldr r3, [r3, #64] ; 0x40
800333e: 221c movs r2, #28
8003340: 4013 ands r3, r2
8003342: 2202 movs r2, #2
8003344: 409a lsls r2, r3
8003346: 0013 movs r3, r2
8003348: 68fa ldr r2, [r7, #12]
800334a: 4013 ands r3, r2
800334c: d02e beq.n 80033ac <HAL_DMA_IRQHandler+0xec>
800334e: 68bb ldr r3, [r7, #8]
8003350: 2202 movs r2, #2
8003352: 4013 ands r3, r2
8003354: d02a beq.n 80033ac <HAL_DMA_IRQHandler+0xec>
{
if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
8003356: 687b ldr r3, [r7, #4]
8003358: 681b ldr r3, [r3, #0]
800335a: 681b ldr r3, [r3, #0]
800335c: 2220 movs r2, #32
800335e: 4013 ands r3, r2
8003360: d10b bne.n 800337a <HAL_DMA_IRQHandler+0xba>
{
/* Disable the transfer complete and error interrupt */
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
8003362: 687b ldr r3, [r7, #4]
8003364: 681b ldr r3, [r3, #0]
8003366: 681a ldr r2, [r3, #0]
8003368: 687b ldr r3, [r7, #4]
800336a: 681b ldr r3, [r3, #0]
800336c: 210a movs r1, #10
800336e: 438a bics r2, r1
8003370: 601a str r2, [r3, #0]
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
8003372: 687b ldr r3, [r7, #4]
8003374: 2225 movs r2, #37 ; 0x25
8003376: 2101 movs r1, #1
8003378: 5499 strb r1, [r3, r2]
}
/* Clear the transfer complete flag */
__HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU)));
800337a: 4b29 ldr r3, [pc, #164] ; (8003420 <HAL_DMA_IRQHandler+0x160>)
800337c: 6859 ldr r1, [r3, #4]
800337e: 687b ldr r3, [r7, #4]
8003380: 6c1b ldr r3, [r3, #64] ; 0x40
8003382: 221c movs r2, #28
8003384: 4013 ands r3, r2
8003386: 2202 movs r2, #2
8003388: 409a lsls r2, r3
800338a: 4b25 ldr r3, [pc, #148] ; (8003420 <HAL_DMA_IRQHandler+0x160>)
800338c: 430a orrs r2, r1
800338e: 605a str r2, [r3, #4]
/* Process Unlocked */
__HAL_UNLOCK(hdma);
8003390: 687b ldr r3, [r7, #4]
8003392: 2224 movs r2, #36 ; 0x24
8003394: 2100 movs r1, #0
8003396: 5499 strb r1, [r3, r2]
if (hdma->XferCpltCallback != NULL)
8003398: 687b ldr r3, [r7, #4]
800339a: 6adb ldr r3, [r3, #44] ; 0x2c
800339c: 2b00 cmp r3, #0
800339e: d03a beq.n 8003416 <HAL_DMA_IRQHandler+0x156>
{
/* Transfer complete callback */
hdma->XferCpltCallback(hdma);
80033a0: 687b ldr r3, [r7, #4]
80033a2: 6adb ldr r3, [r3, #44] ; 0x2c
80033a4: 687a ldr r2, [r7, #4]
80033a6: 0010 movs r0, r2
80033a8: 4798 blx r3
if (hdma->XferCpltCallback != NULL)
80033aa: e034 b.n 8003416 <HAL_DMA_IRQHandler+0x156>
}
}
/* Transfer Error Interrupt management **************************************/
else if (((flag_it & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_TE) != 0U))
80033ac: 687b ldr r3, [r7, #4]
80033ae: 6c1b ldr r3, [r3, #64] ; 0x40
80033b0: 221c movs r2, #28
80033b2: 4013 ands r3, r2
80033b4: 2208 movs r2, #8
80033b6: 409a lsls r2, r3
80033b8: 0013 movs r3, r2
80033ba: 68fa ldr r2, [r7, #12]
80033bc: 4013 ands r3, r2
80033be: d02b beq.n 8003418 <HAL_DMA_IRQHandler+0x158>
80033c0: 68bb ldr r3, [r7, #8]
80033c2: 2208 movs r2, #8
80033c4: 4013 ands r3, r2
80033c6: d027 beq.n 8003418 <HAL_DMA_IRQHandler+0x158>
{
/* When a DMA transfer error occurs */
/* A hardware clear of its EN bits is performed */
/* Disable ALL DMA IT */
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
80033c8: 687b ldr r3, [r7, #4]
80033ca: 681b ldr r3, [r3, #0]
80033cc: 681a ldr r2, [r3, #0]
80033ce: 687b ldr r3, [r7, #4]
80033d0: 681b ldr r3, [r3, #0]
80033d2: 210e movs r1, #14
80033d4: 438a bics r2, r1
80033d6: 601a str r2, [r3, #0]
/* Clear all flags */
#if defined(DMA2)
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
#else
__HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_GI1 << (hdma->ChannelIndex & 0x1CU)));
80033d8: 4b11 ldr r3, [pc, #68] ; (8003420 <HAL_DMA_IRQHandler+0x160>)
80033da: 6859 ldr r1, [r3, #4]
80033dc: 687b ldr r3, [r7, #4]
80033de: 6c1b ldr r3, [r3, #64] ; 0x40
80033e0: 221c movs r2, #28
80033e2: 4013 ands r3, r2
80033e4: 2201 movs r2, #1
80033e6: 409a lsls r2, r3
80033e8: 4b0d ldr r3, [pc, #52] ; (8003420 <HAL_DMA_IRQHandler+0x160>)
80033ea: 430a orrs r2, r1
80033ec: 605a str r2, [r3, #4]
#endif /* DMA2 */
/* Update error code */
hdma->ErrorCode = HAL_DMA_ERROR_TE;
80033ee: 687b ldr r3, [r7, #4]
80033f0: 2201 movs r2, #1
80033f2: 63da str r2, [r3, #60] ; 0x3c
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
80033f4: 687b ldr r3, [r7, #4]
80033f6: 2225 movs r2, #37 ; 0x25
80033f8: 2101 movs r1, #1
80033fa: 5499 strb r1, [r3, r2]
/* Process Unlocked */
__HAL_UNLOCK(hdma);
80033fc: 687b ldr r3, [r7, #4]
80033fe: 2224 movs r2, #36 ; 0x24
8003400: 2100 movs r1, #0
8003402: 5499 strb r1, [r3, r2]
if (hdma->XferErrorCallback != NULL)
8003404: 687b ldr r3, [r7, #4]
8003406: 6b5b ldr r3, [r3, #52] ; 0x34
8003408: 2b00 cmp r3, #0
800340a: d005 beq.n 8003418 <HAL_DMA_IRQHandler+0x158>
{
/* Transfer error callback */
hdma->XferErrorCallback(hdma);
800340c: 687b ldr r3, [r7, #4]
800340e: 6b5b ldr r3, [r3, #52] ; 0x34
8003410: 687a ldr r2, [r7, #4]
8003412: 0010 movs r0, r2
8003414: 4798 blx r3
}
else
{
/* Nothing To Do */
}
return;
8003416: 46c0 nop ; (mov r8, r8)
8003418: 46c0 nop ; (mov r8, r8)
}
800341a: 46bd mov sp, r7
800341c: b004 add sp, #16
800341e: bd80 pop {r7, pc}
8003420: 40020000 .word 0x40020000
08003424 <DMA_SetConfig>:
* @param DstAddress The destination memory Buffer address
* @param DataLength The length of data to be transferred from source to destination
* @retval HAL status
*/
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
8003424: b580 push {r7, lr}
8003426: b084 sub sp, #16
8003428: af00 add r7, sp, #0
800342a: 60f8 str r0, [r7, #12]
800342c: 60b9 str r1, [r7, #8]
800342e: 607a str r2, [r7, #4]
8003430: 603b str r3, [r7, #0]
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
8003432: 68fb ldr r3, [r7, #12]
8003434: 6c9b ldr r3, [r3, #72] ; 0x48
8003436: 68fa ldr r2, [r7, #12]
8003438: 6cd2 ldr r2, [r2, #76] ; 0x4c
800343a: 605a str r2, [r3, #4]
if (hdma->DMAmuxRequestGen != 0U)
800343c: 68fb ldr r3, [r7, #12]
800343e: 6d1b ldr r3, [r3, #80] ; 0x50
8003440: 2b00 cmp r3, #0
8003442: d004 beq.n 800344e <DMA_SetConfig+0x2a>
{
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
8003444: 68fb ldr r3, [r7, #12]
8003446: 6d5b ldr r3, [r3, #84] ; 0x54
8003448: 68fa ldr r2, [r7, #12]
800344a: 6d92 ldr r2, [r2, #88] ; 0x58
800344c: 605a str r2, [r3, #4]
/* Clear all flags */
#if defined(DMA2)
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
#else
__HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_GI1 << (hdma->ChannelIndex & 0x1CU)));
800344e: 4b14 ldr r3, [pc, #80] ; (80034a0 <DMA_SetConfig+0x7c>)
8003450: 6859 ldr r1, [r3, #4]
8003452: 68fb ldr r3, [r7, #12]
8003454: 6c1b ldr r3, [r3, #64] ; 0x40
8003456: 221c movs r2, #28
8003458: 4013 ands r3, r2
800345a: 2201 movs r2, #1
800345c: 409a lsls r2, r3
800345e: 4b10 ldr r3, [pc, #64] ; (80034a0 <DMA_SetConfig+0x7c>)
8003460: 430a orrs r2, r1
8003462: 605a str r2, [r3, #4]
#endif /* DMA2 */
/* Configure DMA Channel data length */
hdma->Instance->CNDTR = DataLength;
8003464: 68fb ldr r3, [r7, #12]
8003466: 681b ldr r3, [r3, #0]
8003468: 683a ldr r2, [r7, #0]
800346a: 605a str r2, [r3, #4]
/* Memory to Peripheral */
if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
800346c: 68fb ldr r3, [r7, #12]
800346e: 689b ldr r3, [r3, #8]
8003470: 2b10 cmp r3, #16
8003472: d108 bne.n 8003486 <DMA_SetConfig+0x62>
{
/* Configure DMA Channel destination address */
hdma->Instance->CPAR = DstAddress;
8003474: 68fb ldr r3, [r7, #12]
8003476: 681b ldr r3, [r3, #0]
8003478: 687a ldr r2, [r7, #4]
800347a: 609a str r2, [r3, #8]
/* Configure DMA Channel source address */
hdma->Instance->CMAR = SrcAddress;
800347c: 68fb ldr r3, [r7, #12]
800347e: 681b ldr r3, [r3, #0]
8003480: 68ba ldr r2, [r7, #8]
8003482: 60da str r2, [r3, #12]
hdma->Instance->CPAR = SrcAddress;
/* Configure DMA Channel destination address */
hdma->Instance->CMAR = DstAddress;
}
}
8003484: e007 b.n 8003496 <DMA_SetConfig+0x72>
hdma->Instance->CPAR = SrcAddress;
8003486: 68fb ldr r3, [r7, #12]
8003488: 681b ldr r3, [r3, #0]
800348a: 68ba ldr r2, [r7, #8]
800348c: 609a str r2, [r3, #8]
hdma->Instance->CMAR = DstAddress;
800348e: 68fb ldr r3, [r7, #12]
8003490: 681b ldr r3, [r3, #0]
8003492: 687a ldr r2, [r7, #4]
8003494: 60da str r2, [r3, #12]
}
8003496: 46c0 nop ; (mov r8, r8)
8003498: 46bd mov sp, r7
800349a: b004 add sp, #16
800349c: bd80 pop {r7, pc}
800349e: 46c0 nop ; (mov r8, r8)
80034a0: 40020000 .word 0x40020000
080034a4 <DMA_CalcDMAMUXChannelBaseAndMask>:
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval None
*/
static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma)
{
80034a4: b580 push {r7, lr}
80034a6: b084 sub sp, #16
80034a8: af00 add r7, sp, #0
80034aa: 6078 str r0, [r7, #4]
/* Prepare channel_number used for DMAmuxChannelStatusMask computation */
channel_number = (((((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U) + 7U);
}
#else
/* Associate a DMA Channel to a DMAMUX channel */
hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX1_Channel0 + ((hdma->ChannelIndex >> 2U) * ((uint32_t)DMAMUX1_Channel1 - (uint32_t)DMAMUX1_Channel0)));
80034ac: 687b ldr r3, [r7, #4]
80034ae: 6c1b ldr r3, [r3, #64] ; 0x40
80034b0: 089b lsrs r3, r3, #2
80034b2: 4a10 ldr r2, [pc, #64] ; (80034f4 <DMA_CalcDMAMUXChannelBaseAndMask+0x50>)
80034b4: 4694 mov ip, r2
80034b6: 4463 add r3, ip
80034b8: 009b lsls r3, r3, #2
80034ba: 001a movs r2, r3
80034bc: 687b ldr r3, [r7, #4]
80034be: 645a str r2, [r3, #68] ; 0x44
/* Prepare channel_number used for DMAmuxChannelStatusMask computation */
channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U;
80034c0: 687b ldr r3, [r7, #4]
80034c2: 681b ldr r3, [r3, #0]
80034c4: 001a movs r2, r3
80034c6: 23ff movs r3, #255 ; 0xff
80034c8: 4013 ands r3, r2
80034ca: 3b08 subs r3, #8
80034cc: 2114 movs r1, #20
80034ce: 0018 movs r0, r3
80034d0: f7fc fe18 bl 8000104 <__udivsi3>
80034d4: 0003 movs r3, r0
80034d6: 60fb str r3, [r7, #12]
#endif /* DMA2 */
/* Initialize the field DMAmuxChannelStatus to DMAMUX1_ChannelStatus base */
hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus;
80034d8: 687b ldr r3, [r7, #4]
80034da: 4a07 ldr r2, [pc, #28] ; (80034f8 <DMA_CalcDMAMUXChannelBaseAndMask+0x54>)
80034dc: 649a str r2, [r3, #72] ; 0x48
/* Initialize the field DMAmuxChannelStatusMask with the corresponding index of the DMAMUX channel selected for the current ChannelIndex */
hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1FU);
80034de: 68fb ldr r3, [r7, #12]
80034e0: 221f movs r2, #31
80034e2: 4013 ands r3, r2
80034e4: 2201 movs r2, #1
80034e6: 409a lsls r2, r3
80034e8: 687b ldr r3, [r7, #4]
80034ea: 64da str r2, [r3, #76] ; 0x4c
}
80034ec: 46c0 nop ; (mov r8, r8)
80034ee: 46bd mov sp, r7
80034f0: b004 add sp, #16
80034f2: bd80 pop {r7, pc}
80034f4: 10008200 .word 0x10008200
80034f8: 40020880 .word 0x40020880
080034fc <DMA_CalcDMAMUXRequestGenBaseAndMask>:
* the configuration information for the specified DMA Channel.
* @retval None
*/
static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma)
{
80034fc: b580 push {r7, lr}
80034fe: b084 sub sp, #16
8003500: af00 add r7, sp, #0
8003502: 6078 str r0, [r7, #4]
uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID;
8003504: 687b ldr r3, [r7, #4]
8003506: 685b ldr r3, [r3, #4]
8003508: 223f movs r2, #63 ; 0x3f
800350a: 4013 ands r3, r2
800350c: 60fb str r3, [r7, #12]
/* DMA Channels are connected to DMAMUX1 request generator blocks*/
hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U)));
800350e: 68fb ldr r3, [r7, #12]
8003510: 4a0a ldr r2, [pc, #40] ; (800353c <DMA_CalcDMAMUXRequestGenBaseAndMask+0x40>)
8003512: 4694 mov ip, r2
8003514: 4463 add r3, ip
8003516: 009b lsls r3, r3, #2
8003518: 001a movs r2, r3
800351a: 687b ldr r3, [r7, #4]
800351c: 651a str r2, [r3, #80] ; 0x50
hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus;
800351e: 687b ldr r3, [r7, #4]
8003520: 4a07 ldr r2, [pc, #28] ; (8003540 <DMA_CalcDMAMUXRequestGenBaseAndMask+0x44>)
8003522: 655a str r2, [r3, #84] ; 0x54
/* here "Request" is either DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR3, i.e. <= 4*/
hdma->DMAmuxRequestGenStatusMask = 1UL << ((request - 1U) & 0x3U);
8003524: 68fb ldr r3, [r7, #12]
8003526: 3b01 subs r3, #1
8003528: 2203 movs r2, #3
800352a: 4013 ands r3, r2
800352c: 2201 movs r2, #1
800352e: 409a lsls r2, r3
8003530: 687b ldr r3, [r7, #4]
8003532: 659a str r2, [r3, #88] ; 0x58
}
8003534: 46c0 nop ; (mov r8, r8)
8003536: 46bd mov sp, r7
8003538: b004 add sp, #16
800353a: bd80 pop {r7, pc}
800353c: 1000823f .word 0x1000823f
8003540: 40020940 .word 0x40020940
08003544 <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
8003544: b580 push {r7, lr}
8003546: b086 sub sp, #24
8003548: af00 add r7, sp, #0
800354a: 6078 str r0, [r7, #4]
800354c: 6039 str r1, [r7, #0]
uint32_t position = 0x00u;
800354e: 2300 movs r3, #0
8003550: 617b str r3, [r7, #20]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0x00u)
8003552: e147 b.n 80037e4 <HAL_GPIO_Init+0x2a0>
{
/* Get current io position */
iocurrent = (GPIO_Init->Pin) & (1uL << position);
8003554: 683b ldr r3, [r7, #0]
8003556: 681b ldr r3, [r3, #0]
8003558: 2101 movs r1, #1
800355a: 697a ldr r2, [r7, #20]
800355c: 4091 lsls r1, r2
800355e: 000a movs r2, r1
8003560: 4013 ands r3, r2
8003562: 60fb str r3, [r7, #12]
if (iocurrent != 0x00u)
8003564: 68fb ldr r3, [r7, #12]
8003566: 2b00 cmp r3, #0
8003568: d100 bne.n 800356c <HAL_GPIO_Init+0x28>
800356a: e138 b.n 80037de <HAL_GPIO_Init+0x29a>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
800356c: 683b ldr r3, [r7, #0]
800356e: 685b ldr r3, [r3, #4]
8003570: 2203 movs r2, #3
8003572: 4013 ands r3, r2
8003574: 2b01 cmp r3, #1
8003576: d005 beq.n 8003584 <HAL_GPIO_Init+0x40>
8003578: 683b ldr r3, [r7, #0]
800357a: 685b ldr r3, [r3, #4]
800357c: 2203 movs r2, #3
800357e: 4013 ands r3, r2
8003580: 2b02 cmp r3, #2
8003582: d130 bne.n 80035e6 <HAL_GPIO_Init+0xa2>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
8003584: 687b ldr r3, [r7, #4]
8003586: 689b ldr r3, [r3, #8]
8003588: 613b str r3, [r7, #16]
temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));
800358a: 697b ldr r3, [r7, #20]
800358c: 005b lsls r3, r3, #1
800358e: 2203 movs r2, #3
8003590: 409a lsls r2, r3
8003592: 0013 movs r3, r2
8003594: 43da mvns r2, r3
8003596: 693b ldr r3, [r7, #16]
8003598: 4013 ands r3, r2
800359a: 613b str r3, [r7, #16]
temp |= (GPIO_Init->Speed << (position * 2u));
800359c: 683b ldr r3, [r7, #0]
800359e: 68da ldr r2, [r3, #12]
80035a0: 697b ldr r3, [r7, #20]
80035a2: 005b lsls r3, r3, #1
80035a4: 409a lsls r2, r3
80035a6: 0013 movs r3, r2
80035a8: 693a ldr r2, [r7, #16]
80035aa: 4313 orrs r3, r2
80035ac: 613b str r3, [r7, #16]
GPIOx->OSPEEDR = temp;
80035ae: 687b ldr r3, [r7, #4]
80035b0: 693a ldr r2, [r7, #16]
80035b2: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
80035b4: 687b ldr r3, [r7, #4]
80035b6: 685b ldr r3, [r3, #4]
80035b8: 613b str r3, [r7, #16]
temp &= ~(GPIO_OTYPER_OT0 << position) ;
80035ba: 2201 movs r2, #1
80035bc: 697b ldr r3, [r7, #20]
80035be: 409a lsls r2, r3
80035c0: 0013 movs r3, r2
80035c2: 43da mvns r2, r3
80035c4: 693b ldr r3, [r7, #16]
80035c6: 4013 ands r3, r2
80035c8: 613b str r3, [r7, #16]
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
80035ca: 683b ldr r3, [r7, #0]
80035cc: 685b ldr r3, [r3, #4]
80035ce: 091b lsrs r3, r3, #4
80035d0: 2201 movs r2, #1
80035d2: 401a ands r2, r3
80035d4: 697b ldr r3, [r7, #20]
80035d6: 409a lsls r2, r3
80035d8: 0013 movs r3, r2
80035da: 693a ldr r2, [r7, #16]
80035dc: 4313 orrs r3, r2
80035de: 613b str r3, [r7, #16]
GPIOx->OTYPER = temp;
80035e0: 687b ldr r3, [r7, #4]
80035e2: 693a ldr r2, [r7, #16]
80035e4: 605a str r2, [r3, #4]
}
if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
80035e6: 683b ldr r3, [r7, #0]
80035e8: 685b ldr r3, [r3, #4]
80035ea: 2203 movs r2, #3
80035ec: 4013 ands r3, r2
80035ee: 2b03 cmp r3, #3
80035f0: d017 beq.n 8003622 <HAL_GPIO_Init+0xde>
{
/* Check the Pull parameter */
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
80035f2: 687b ldr r3, [r7, #4]
80035f4: 68db ldr r3, [r3, #12]
80035f6: 613b str r3, [r7, #16]
temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2u));
80035f8: 697b ldr r3, [r7, #20]
80035fa: 005b lsls r3, r3, #1
80035fc: 2203 movs r2, #3
80035fe: 409a lsls r2, r3
8003600: 0013 movs r3, r2
8003602: 43da mvns r2, r3
8003604: 693b ldr r3, [r7, #16]
8003606: 4013 ands r3, r2
8003608: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Pull) << (position * 2u));
800360a: 683b ldr r3, [r7, #0]
800360c: 689a ldr r2, [r3, #8]
800360e: 697b ldr r3, [r7, #20]
8003610: 005b lsls r3, r3, #1
8003612: 409a lsls r2, r3
8003614: 0013 movs r3, r2
8003616: 693a ldr r2, [r7, #16]
8003618: 4313 orrs r3, r2
800361a: 613b str r3, [r7, #16]
GPIOx->PUPDR = temp;
800361c: 687b ldr r3, [r7, #4]
800361e: 693a ldr r2, [r7, #16]
8003620: 60da str r2, [r3, #12]
}
/* In case of Alternate function mode selection */
if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
8003622: 683b ldr r3, [r7, #0]
8003624: 685b ldr r3, [r3, #4]
8003626: 2203 movs r2, #3
8003628: 4013 ands r3, r2
800362a: 2b02 cmp r3, #2
800362c: d123 bne.n 8003676 <HAL_GPIO_Init+0x132>
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3u];
800362e: 697b ldr r3, [r7, #20]
8003630: 08da lsrs r2, r3, #3
8003632: 687b ldr r3, [r7, #4]
8003634: 3208 adds r2, #8
8003636: 0092 lsls r2, r2, #2
8003638: 58d3 ldr r3, [r2, r3]
800363a: 613b str r3, [r7, #16]
temp &= ~(0xFu << ((position & 0x07u) * 4u));
800363c: 697b ldr r3, [r7, #20]
800363e: 2207 movs r2, #7
8003640: 4013 ands r3, r2
8003642: 009b lsls r3, r3, #2
8003644: 220f movs r2, #15
8003646: 409a lsls r2, r3
8003648: 0013 movs r3, r2
800364a: 43da mvns r2, r3
800364c: 693b ldr r3, [r7, #16]
800364e: 4013 ands r3, r2
8003650: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
8003652: 683b ldr r3, [r7, #0]
8003654: 691a ldr r2, [r3, #16]
8003656: 697b ldr r3, [r7, #20]
8003658: 2107 movs r1, #7
800365a: 400b ands r3, r1
800365c: 009b lsls r3, r3, #2
800365e: 409a lsls r2, r3
8003660: 0013 movs r3, r2
8003662: 693a ldr r2, [r7, #16]
8003664: 4313 orrs r3, r2
8003666: 613b str r3, [r7, #16]
GPIOx->AFR[position >> 3u] = temp;
8003668: 697b ldr r3, [r7, #20]
800366a: 08da lsrs r2, r3, #3
800366c: 687b ldr r3, [r7, #4]
800366e: 3208 adds r2, #8
8003670: 0092 lsls r2, r2, #2
8003672: 6939 ldr r1, [r7, #16]
8003674: 50d1 str r1, [r2, r3]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
8003676: 687b ldr r3, [r7, #4]
8003678: 681b ldr r3, [r3, #0]
800367a: 613b str r3, [r7, #16]
temp &= ~(GPIO_MODER_MODE0 << (position * 2u));
800367c: 697b ldr r3, [r7, #20]
800367e: 005b lsls r3, r3, #1
8003680: 2203 movs r2, #3
8003682: 409a lsls r2, r3
8003684: 0013 movs r3, r2
8003686: 43da mvns r2, r3
8003688: 693b ldr r3, [r7, #16]
800368a: 4013 ands r3, r2
800368c: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
800368e: 683b ldr r3, [r7, #0]
8003690: 685b ldr r3, [r3, #4]
8003692: 2203 movs r2, #3
8003694: 401a ands r2, r3
8003696: 697b ldr r3, [r7, #20]
8003698: 005b lsls r3, r3, #1
800369a: 409a lsls r2, r3
800369c: 0013 movs r3, r2
800369e: 693a ldr r2, [r7, #16]
80036a0: 4313 orrs r3, r2
80036a2: 613b str r3, [r7, #16]
GPIOx->MODER = temp;
80036a4: 687b ldr r3, [r7, #4]
80036a6: 693a ldr r2, [r7, #16]
80036a8: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
80036aa: 683b ldr r3, [r7, #0]
80036ac: 685a ldr r2, [r3, #4]
80036ae: 23c0 movs r3, #192 ; 0xc0
80036b0: 029b lsls r3, r3, #10
80036b2: 4013 ands r3, r2
80036b4: d100 bne.n 80036b8 <HAL_GPIO_Init+0x174>
80036b6: e092 b.n 80037de <HAL_GPIO_Init+0x29a>
{
temp = EXTI->EXTICR[position >> 2u];
80036b8: 4a50 ldr r2, [pc, #320] ; (80037fc <HAL_GPIO_Init+0x2b8>)
80036ba: 697b ldr r3, [r7, #20]
80036bc: 089b lsrs r3, r3, #2
80036be: 3318 adds r3, #24
80036c0: 009b lsls r3, r3, #2
80036c2: 589b ldr r3, [r3, r2]
80036c4: 613b str r3, [r7, #16]
temp &= ~(0x0FuL << (8u * (position & 0x03u)));
80036c6: 697b ldr r3, [r7, #20]
80036c8: 2203 movs r2, #3
80036ca: 4013 ands r3, r2
80036cc: 00db lsls r3, r3, #3
80036ce: 220f movs r2, #15
80036d0: 409a lsls r2, r3
80036d2: 0013 movs r3, r2
80036d4: 43da mvns r2, r3
80036d6: 693b ldr r3, [r7, #16]
80036d8: 4013 ands r3, r2
80036da: 613b str r3, [r7, #16]
temp |= (GPIO_GET_INDEX(GPIOx) << (8u * (position & 0x03u)));
80036dc: 687a ldr r2, [r7, #4]
80036de: 23a0 movs r3, #160 ; 0xa0
80036e0: 05db lsls r3, r3, #23
80036e2: 429a cmp r2, r3
80036e4: d013 beq.n 800370e <HAL_GPIO_Init+0x1ca>
80036e6: 687b ldr r3, [r7, #4]
80036e8: 4a45 ldr r2, [pc, #276] ; (8003800 <HAL_GPIO_Init+0x2bc>)
80036ea: 4293 cmp r3, r2
80036ec: d00d beq.n 800370a <HAL_GPIO_Init+0x1c6>
80036ee: 687b ldr r3, [r7, #4]
80036f0: 4a44 ldr r2, [pc, #272] ; (8003804 <HAL_GPIO_Init+0x2c0>)
80036f2: 4293 cmp r3, r2
80036f4: d007 beq.n 8003706 <HAL_GPIO_Init+0x1c2>
80036f6: 687b ldr r3, [r7, #4]
80036f8: 4a43 ldr r2, [pc, #268] ; (8003808 <HAL_GPIO_Init+0x2c4>)
80036fa: 4293 cmp r3, r2
80036fc: d101 bne.n 8003702 <HAL_GPIO_Init+0x1be>
80036fe: 2303 movs r3, #3
8003700: e006 b.n 8003710 <HAL_GPIO_Init+0x1cc>
8003702: 2305 movs r3, #5
8003704: e004 b.n 8003710 <HAL_GPIO_Init+0x1cc>
8003706: 2302 movs r3, #2
8003708: e002 b.n 8003710 <HAL_GPIO_Init+0x1cc>
800370a: 2301 movs r3, #1
800370c: e000 b.n 8003710 <HAL_GPIO_Init+0x1cc>
800370e: 2300 movs r3, #0
8003710: 697a ldr r2, [r7, #20]
8003712: 2103 movs r1, #3
8003714: 400a ands r2, r1
8003716: 00d2 lsls r2, r2, #3
8003718: 4093 lsls r3, r2
800371a: 693a ldr r2, [r7, #16]
800371c: 4313 orrs r3, r2
800371e: 613b str r3, [r7, #16]
EXTI->EXTICR[position >> 2u] = temp;
8003720: 4936 ldr r1, [pc, #216] ; (80037fc <HAL_GPIO_Init+0x2b8>)
8003722: 697b ldr r3, [r7, #20]
8003724: 089b lsrs r3, r3, #2
8003726: 3318 adds r3, #24
8003728: 009b lsls r3, r3, #2
800372a: 693a ldr r2, [r7, #16]
800372c: 505a str r2, [r3, r1]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR1;
800372e: 4b33 ldr r3, [pc, #204] ; (80037fc <HAL_GPIO_Init+0x2b8>)
8003730: 681b ldr r3, [r3, #0]
8003732: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8003734: 68fb ldr r3, [r7, #12]
8003736: 43da mvns r2, r3
8003738: 693b ldr r3, [r7, #16]
800373a: 4013 ands r3, r2
800373c: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
800373e: 683b ldr r3, [r7, #0]
8003740: 685a ldr r2, [r3, #4]
8003742: 2380 movs r3, #128 ; 0x80
8003744: 035b lsls r3, r3, #13
8003746: 4013 ands r3, r2
8003748: d003 beq.n 8003752 <HAL_GPIO_Init+0x20e>
{
temp |= iocurrent;
800374a: 693a ldr r2, [r7, #16]
800374c: 68fb ldr r3, [r7, #12]
800374e: 4313 orrs r3, r2
8003750: 613b str r3, [r7, #16]
}
EXTI->RTSR1 = temp;
8003752: 4b2a ldr r3, [pc, #168] ; (80037fc <HAL_GPIO_Init+0x2b8>)
8003754: 693a ldr r2, [r7, #16]
8003756: 601a str r2, [r3, #0]
temp = EXTI->FTSR1;
8003758: 4b28 ldr r3, [pc, #160] ; (80037fc <HAL_GPIO_Init+0x2b8>)
800375a: 685b ldr r3, [r3, #4]
800375c: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
800375e: 68fb ldr r3, [r7, #12]
8003760: 43da mvns r2, r3
8003762: 693b ldr r3, [r7, #16]
8003764: 4013 ands r3, r2
8003766: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
8003768: 683b ldr r3, [r7, #0]
800376a: 685a ldr r2, [r3, #4]
800376c: 2380 movs r3, #128 ; 0x80
800376e: 039b lsls r3, r3, #14
8003770: 4013 ands r3, r2
8003772: d003 beq.n 800377c <HAL_GPIO_Init+0x238>
{
temp |= iocurrent;
8003774: 693a ldr r2, [r7, #16]
8003776: 68fb ldr r3, [r7, #12]
8003778: 4313 orrs r3, r2
800377a: 613b str r3, [r7, #16]
}
EXTI->FTSR1 = temp;
800377c: 4b1f ldr r3, [pc, #124] ; (80037fc <HAL_GPIO_Init+0x2b8>)
800377e: 693a ldr r2, [r7, #16]
8003780: 605a str r2, [r3, #4]
/* Clear EXTI line configuration */
temp = EXTI->EMR1;
8003782: 4a1e ldr r2, [pc, #120] ; (80037fc <HAL_GPIO_Init+0x2b8>)
8003784: 2384 movs r3, #132 ; 0x84
8003786: 58d3 ldr r3, [r2, r3]
8003788: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
800378a: 68fb ldr r3, [r7, #12]
800378c: 43da mvns r2, r3
800378e: 693b ldr r3, [r7, #16]
8003790: 4013 ands r3, r2
8003792: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
8003794: 683b ldr r3, [r7, #0]
8003796: 685a ldr r2, [r3, #4]
8003798: 2380 movs r3, #128 ; 0x80
800379a: 029b lsls r3, r3, #10
800379c: 4013 ands r3, r2
800379e: d003 beq.n 80037a8 <HAL_GPIO_Init+0x264>
{
temp |= iocurrent;
80037a0: 693a ldr r2, [r7, #16]
80037a2: 68fb ldr r3, [r7, #12]
80037a4: 4313 orrs r3, r2
80037a6: 613b str r3, [r7, #16]
}
EXTI->EMR1 = temp;
80037a8: 4914 ldr r1, [pc, #80] ; (80037fc <HAL_GPIO_Init+0x2b8>)
80037aa: 2284 movs r2, #132 ; 0x84
80037ac: 693b ldr r3, [r7, #16]
80037ae: 508b str r3, [r1, r2]
temp = EXTI->IMR1;
80037b0: 4a12 ldr r2, [pc, #72] ; (80037fc <HAL_GPIO_Init+0x2b8>)
80037b2: 2380 movs r3, #128 ; 0x80
80037b4: 58d3 ldr r3, [r2, r3]
80037b6: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
80037b8: 68fb ldr r3, [r7, #12]
80037ba: 43da mvns r2, r3
80037bc: 693b ldr r3, [r7, #16]
80037be: 4013 ands r3, r2
80037c0: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & EXTI_IT) != 0x00u)
80037c2: 683b ldr r3, [r7, #0]
80037c4: 685a ldr r2, [r3, #4]
80037c6: 2380 movs r3, #128 ; 0x80
80037c8: 025b lsls r3, r3, #9
80037ca: 4013 ands r3, r2
80037cc: d003 beq.n 80037d6 <HAL_GPIO_Init+0x292>
{
temp |= iocurrent;
80037ce: 693a ldr r2, [r7, #16]
80037d0: 68fb ldr r3, [r7, #12]
80037d2: 4313 orrs r3, r2
80037d4: 613b str r3, [r7, #16]
}
EXTI->IMR1 = temp;
80037d6: 4909 ldr r1, [pc, #36] ; (80037fc <HAL_GPIO_Init+0x2b8>)
80037d8: 2280 movs r2, #128 ; 0x80
80037da: 693b ldr r3, [r7, #16]
80037dc: 508b str r3, [r1, r2]
}
}
position++;
80037de: 697b ldr r3, [r7, #20]
80037e0: 3301 adds r3, #1
80037e2: 617b str r3, [r7, #20]
while (((GPIO_Init->Pin) >> position) != 0x00u)
80037e4: 683b ldr r3, [r7, #0]
80037e6: 681a ldr r2, [r3, #0]
80037e8: 697b ldr r3, [r7, #20]
80037ea: 40da lsrs r2, r3
80037ec: 1e13 subs r3, r2, #0
80037ee: d000 beq.n 80037f2 <HAL_GPIO_Init+0x2ae>
80037f0: e6b0 b.n 8003554 <HAL_GPIO_Init+0x10>
}
}
80037f2: 46c0 nop ; (mov r8, r8)
80037f4: 46c0 nop ; (mov r8, r8)
80037f6: 46bd mov sp, r7
80037f8: b006 add sp, #24
80037fa: bd80 pop {r7, pc}
80037fc: 40021800 .word 0x40021800
8003800: 50000400 .word 0x50000400
8003804: 50000800 .word 0x50000800
8003808: 50000c00 .word 0x50000c00
0800380c <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
800380c: b580 push {r7, lr}
800380e: b082 sub sp, #8
8003810: af00 add r7, sp, #0
8003812: 6078 str r0, [r7, #4]
8003814: 0008 movs r0, r1
8003816: 0011 movs r1, r2
8003818: 1cbb adds r3, r7, #2
800381a: 1c02 adds r2, r0, #0
800381c: 801a strh r2, [r3, #0]
800381e: 1c7b adds r3, r7, #1
8003820: 1c0a adds r2, r1, #0
8003822: 701a strb r2, [r3, #0]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if (PinState != GPIO_PIN_RESET)
8003824: 1c7b adds r3, r7, #1
8003826: 781b ldrb r3, [r3, #0]
8003828: 2b00 cmp r3, #0
800382a: d004 beq.n 8003836 <HAL_GPIO_WritePin+0x2a>
{
GPIOx->BSRR = (uint32_t)GPIO_Pin;
800382c: 1cbb adds r3, r7, #2
800382e: 881a ldrh r2, [r3, #0]
8003830: 687b ldr r3, [r7, #4]
8003832: 619a str r2, [r3, #24]
}
else
{
GPIOx->BRR = (uint32_t)GPIO_Pin;
}
}
8003834: e003 b.n 800383e <HAL_GPIO_WritePin+0x32>
GPIOx->BRR = (uint32_t)GPIO_Pin;
8003836: 1cbb adds r3, r7, #2
8003838: 881a ldrh r2, [r3, #0]
800383a: 687b ldr r3, [r7, #4]
800383c: 629a str r2, [r3, #40] ; 0x28
}
800383e: 46c0 nop ; (mov r8, r8)
8003840: 46bd mov sp, r7
8003842: b002 add sp, #8
8003844: bd80 pop {r7, pc}
...
08003848 <HAL_PWREx_ControlVoltageScaling>:
* cleared before returning the status. If the flag is not cleared within
* 6 microseconds, HAL_TIMEOUT status is reported.
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
{
8003848: b580 push {r7, lr}
800384a: b084 sub sp, #16
800384c: af00 add r7, sp, #0
800384e: 6078 str r0, [r7, #4]
uint32_t wait_loop_index;
assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
/* Modify voltage scaling range */
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling);
8003850: 4b19 ldr r3, [pc, #100] ; (80038b8 <HAL_PWREx_ControlVoltageScaling+0x70>)
8003852: 681b ldr r3, [r3, #0]
8003854: 4a19 ldr r2, [pc, #100] ; (80038bc <HAL_PWREx_ControlVoltageScaling+0x74>)
8003856: 4013 ands r3, r2
8003858: 0019 movs r1, r3
800385a: 4b17 ldr r3, [pc, #92] ; (80038b8 <HAL_PWREx_ControlVoltageScaling+0x70>)
800385c: 687a ldr r2, [r7, #4]
800385e: 430a orrs r2, r1
8003860: 601a str r2, [r3, #0]
/* In case of Range 1 selected, we need to ensure that main regulator reaches new value */
if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)
8003862: 687a ldr r2, [r7, #4]
8003864: 2380 movs r3, #128 ; 0x80
8003866: 009b lsls r3, r3, #2
8003868: 429a cmp r2, r3
800386a: d11f bne.n 80038ac <HAL_PWREx_ControlVoltageScaling+0x64>
{
/* Set timeout value */
wait_loop_index = ((PWR_VOSF_SETTING_DELAY_6_US * SystemCoreClock) / 1000000U) + 1U;
800386c: 4b14 ldr r3, [pc, #80] ; (80038c0 <HAL_PWREx_ControlVoltageScaling+0x78>)
800386e: 681a ldr r2, [r3, #0]
8003870: 0013 movs r3, r2
8003872: 005b lsls r3, r3, #1
8003874: 189b adds r3, r3, r2
8003876: 005b lsls r3, r3, #1
8003878: 4912 ldr r1, [pc, #72] ; (80038c4 <HAL_PWREx_ControlVoltageScaling+0x7c>)
800387a: 0018 movs r0, r3
800387c: f7fc fc42 bl 8000104 <__udivsi3>
8003880: 0003 movs r3, r0
8003882: 3301 adds r3, #1
8003884: 60fb str r3, [r7, #12]
/* Wait until VOSF is reset */
while (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
8003886: e008 b.n 800389a <HAL_PWREx_ControlVoltageScaling+0x52>
{
if (wait_loop_index != 0U)
8003888: 68fb ldr r3, [r7, #12]
800388a: 2b00 cmp r3, #0
800388c: d003 beq.n 8003896 <HAL_PWREx_ControlVoltageScaling+0x4e>
{
wait_loop_index--;
800388e: 68fb ldr r3, [r7, #12]
8003890: 3b01 subs r3, #1
8003892: 60fb str r3, [r7, #12]
8003894: e001 b.n 800389a <HAL_PWREx_ControlVoltageScaling+0x52>
}
else
{
return HAL_TIMEOUT;
8003896: 2303 movs r3, #3
8003898: e009 b.n 80038ae <HAL_PWREx_ControlVoltageScaling+0x66>
while (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
800389a: 4b07 ldr r3, [pc, #28] ; (80038b8 <HAL_PWREx_ControlVoltageScaling+0x70>)
800389c: 695a ldr r2, [r3, #20]
800389e: 2380 movs r3, #128 ; 0x80
80038a0: 00db lsls r3, r3, #3
80038a2: 401a ands r2, r3
80038a4: 2380 movs r3, #128 ; 0x80
80038a6: 00db lsls r3, r3, #3
80038a8: 429a cmp r2, r3
80038aa: d0ed beq.n 8003888 <HAL_PWREx_ControlVoltageScaling+0x40>
}
}
}
return HAL_OK;
80038ac: 2300 movs r3, #0
}
80038ae: 0018 movs r0, r3
80038b0: 46bd mov sp, r7
80038b2: b004 add sp, #16
80038b4: bd80 pop {r7, pc}
80038b6: 46c0 nop ; (mov r8, r8)
80038b8: 40007000 .word 0x40007000
80038bc: fffff9ff .word 0xfffff9ff
80038c0: 2000000c .word 0x2000000c
80038c4: 000f4240 .word 0x000f4240
080038c8 <LL_RCC_GetAPB1Prescaler>:
* @arg @ref LL_RCC_APB1_DIV_4
* @arg @ref LL_RCC_APB1_DIV_8
* @arg @ref LL_RCC_APB1_DIV_16
*/
__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
{
80038c8: b580 push {r7, lr}
80038ca: af00 add r7, sp, #0
return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE));
80038cc: 4b03 ldr r3, [pc, #12] ; (80038dc <LL_RCC_GetAPB1Prescaler+0x14>)
80038ce: 689a ldr r2, [r3, #8]
80038d0: 23e0 movs r3, #224 ; 0xe0
80038d2: 01db lsls r3, r3, #7
80038d4: 4013 ands r3, r2
}
80038d6: 0018 movs r0, r3
80038d8: 46bd mov sp, r7
80038da: bd80 pop {r7, pc}
80038dc: 40021000 .word 0x40021000
080038e0 <HAL_RCC_OscConfig>:
* supported by this function. User should request a transition to LSE Off
* first and then to LSE On or LSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
80038e0: b580 push {r7, lr}
80038e2: b088 sub sp, #32
80038e4: af00 add r7, sp, #0
80038e6: 6078 str r0, [r7, #4]
uint32_t tickstart;
uint32_t temp_sysclksrc;
uint32_t temp_pllckcfg;
/* Check Null pointer */
if (RCC_OscInitStruct == NULL)
80038e8: 687b ldr r3, [r7, #4]
80038ea: 2b00 cmp r3, #0
80038ec: d101 bne.n 80038f2 <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
80038ee: 2301 movs r3, #1
80038f0: e2fe b.n 8003ef0 <HAL_RCC_OscConfig+0x610>
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
80038f2: 687b ldr r3, [r7, #4]
80038f4: 681b ldr r3, [r3, #0]
80038f6: 2201 movs r2, #1
80038f8: 4013 ands r3, r2
80038fa: d100 bne.n 80038fe <HAL_RCC_OscConfig+0x1e>
80038fc: e07c b.n 80039f8 <HAL_RCC_OscConfig+0x118>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
80038fe: 4bc3 ldr r3, [pc, #780] ; (8003c0c <HAL_RCC_OscConfig+0x32c>)
8003900: 689b ldr r3, [r3, #8]
8003902: 2238 movs r2, #56 ; 0x38
8003904: 4013 ands r3, r2
8003906: 61bb str r3, [r7, #24]
temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE();
8003908: 4bc0 ldr r3, [pc, #768] ; (8003c0c <HAL_RCC_OscConfig+0x32c>)
800390a: 68db ldr r3, [r3, #12]
800390c: 2203 movs r2, #3
800390e: 4013 ands r3, r2
8003910: 617b str r3, [r7, #20]
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
if (((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_pllckcfg == RCC_PLLSOURCE_HSE))
8003912: 69bb ldr r3, [r7, #24]
8003914: 2b10 cmp r3, #16
8003916: d102 bne.n 800391e <HAL_RCC_OscConfig+0x3e>
8003918: 697b ldr r3, [r7, #20]
800391a: 2b03 cmp r3, #3
800391c: d002 beq.n 8003924 <HAL_RCC_OscConfig+0x44>
|| (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSE))
800391e: 69bb ldr r3, [r7, #24]
8003920: 2b08 cmp r3, #8
8003922: d10b bne.n 800393c <HAL_RCC_OscConfig+0x5c>
{
if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8003924: 4bb9 ldr r3, [pc, #740] ; (8003c0c <HAL_RCC_OscConfig+0x32c>)
8003926: 681a ldr r2, [r3, #0]
8003928: 2380 movs r3, #128 ; 0x80
800392a: 029b lsls r3, r3, #10
800392c: 4013 ands r3, r2
800392e: d062 beq.n 80039f6 <HAL_RCC_OscConfig+0x116>
8003930: 687b ldr r3, [r7, #4]
8003932: 685b ldr r3, [r3, #4]
8003934: 2b00 cmp r3, #0
8003936: d15e bne.n 80039f6 <HAL_RCC_OscConfig+0x116>
{
return HAL_ERROR;
8003938: 2301 movs r3, #1
800393a: e2d9 b.n 8003ef0 <HAL_RCC_OscConfig+0x610>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
800393c: 687b ldr r3, [r7, #4]
800393e: 685a ldr r2, [r3, #4]
8003940: 2380 movs r3, #128 ; 0x80
8003942: 025b lsls r3, r3, #9
8003944: 429a cmp r2, r3
8003946: d107 bne.n 8003958 <HAL_RCC_OscConfig+0x78>
8003948: 4bb0 ldr r3, [pc, #704] ; (8003c0c <HAL_RCC_OscConfig+0x32c>)
800394a: 681a ldr r2, [r3, #0]
800394c: 4baf ldr r3, [pc, #700] ; (8003c0c <HAL_RCC_OscConfig+0x32c>)
800394e: 2180 movs r1, #128 ; 0x80
8003950: 0249 lsls r1, r1, #9
8003952: 430a orrs r2, r1
8003954: 601a str r2, [r3, #0]
8003956: e020 b.n 800399a <HAL_RCC_OscConfig+0xba>
8003958: 687b ldr r3, [r7, #4]
800395a: 685a ldr r2, [r3, #4]
800395c: 23a0 movs r3, #160 ; 0xa0
800395e: 02db lsls r3, r3, #11
8003960: 429a cmp r2, r3
8003962: d10e bne.n 8003982 <HAL_RCC_OscConfig+0xa2>
8003964: 4ba9 ldr r3, [pc, #676] ; (8003c0c <HAL_RCC_OscConfig+0x32c>)
8003966: 681a ldr r2, [r3, #0]
8003968: 4ba8 ldr r3, [pc, #672] ; (8003c0c <HAL_RCC_OscConfig+0x32c>)
800396a: 2180 movs r1, #128 ; 0x80
800396c: 02c9 lsls r1, r1, #11
800396e: 430a orrs r2, r1
8003970: 601a str r2, [r3, #0]
8003972: 4ba6 ldr r3, [pc, #664] ; (8003c0c <HAL_RCC_OscConfig+0x32c>)
8003974: 681a ldr r2, [r3, #0]
8003976: 4ba5 ldr r3, [pc, #660] ; (8003c0c <HAL_RCC_OscConfig+0x32c>)
8003978: 2180 movs r1, #128 ; 0x80
800397a: 0249 lsls r1, r1, #9
800397c: 430a orrs r2, r1
800397e: 601a str r2, [r3, #0]
8003980: e00b b.n 800399a <HAL_RCC_OscConfig+0xba>
8003982: 4ba2 ldr r3, [pc, #648] ; (8003c0c <HAL_RCC_OscConfig+0x32c>)
8003984: 681a ldr r2, [r3, #0]
8003986: 4ba1 ldr r3, [pc, #644] ; (8003c0c <HAL_RCC_OscConfig+0x32c>)
8003988: 49a1 ldr r1, [pc, #644] ; (8003c10 <HAL_RCC_OscConfig+0x330>)
800398a: 400a ands r2, r1
800398c: 601a str r2, [r3, #0]
800398e: 4b9f ldr r3, [pc, #636] ; (8003c0c <HAL_RCC_OscConfig+0x32c>)
8003990: 681a ldr r2, [r3, #0]
8003992: 4b9e ldr r3, [pc, #632] ; (8003c0c <HAL_RCC_OscConfig+0x32c>)
8003994: 499f ldr r1, [pc, #636] ; (8003c14 <HAL_RCC_OscConfig+0x334>)
8003996: 400a ands r2, r1
8003998: 601a str r2, [r3, #0]
/* Check the HSE State */
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
800399a: 687b ldr r3, [r7, #4]
800399c: 685b ldr r3, [r3, #4]
800399e: 2b00 cmp r3, #0
80039a0: d014 beq.n 80039cc <HAL_RCC_OscConfig+0xec>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
80039a2: f7fe f8df bl 8001b64 <HAL_GetTick>
80039a6: 0003 movs r3, r0
80039a8: 613b str r3, [r7, #16]
/* Wait till HSE is ready */
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
80039aa: e008 b.n 80039be <HAL_RCC_OscConfig+0xde>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
80039ac: f7fe f8da bl 8001b64 <HAL_GetTick>
80039b0: 0002 movs r2, r0
80039b2: 693b ldr r3, [r7, #16]
80039b4: 1ad3 subs r3, r2, r3
80039b6: 2b64 cmp r3, #100 ; 0x64
80039b8: d901 bls.n 80039be <HAL_RCC_OscConfig+0xde>
{
return HAL_TIMEOUT;
80039ba: 2303 movs r3, #3
80039bc: e298 b.n 8003ef0 <HAL_RCC_OscConfig+0x610>
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
80039be: 4b93 ldr r3, [pc, #588] ; (8003c0c <HAL_RCC_OscConfig+0x32c>)
80039c0: 681a ldr r2, [r3, #0]
80039c2: 2380 movs r3, #128 ; 0x80
80039c4: 029b lsls r3, r3, #10
80039c6: 4013 ands r3, r2
80039c8: d0f0 beq.n 80039ac <HAL_RCC_OscConfig+0xcc>
80039ca: e015 b.n 80039f8 <HAL_RCC_OscConfig+0x118>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
80039cc: f7fe f8ca bl 8001b64 <HAL_GetTick>
80039d0: 0003 movs r3, r0
80039d2: 613b str r3, [r7, #16]
/* Wait till HSE is disabled */
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
80039d4: e008 b.n 80039e8 <HAL_RCC_OscConfig+0x108>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
80039d6: f7fe f8c5 bl 8001b64 <HAL_GetTick>
80039da: 0002 movs r2, r0
80039dc: 693b ldr r3, [r7, #16]
80039de: 1ad3 subs r3, r2, r3
80039e0: 2b64 cmp r3, #100 ; 0x64
80039e2: d901 bls.n 80039e8 <HAL_RCC_OscConfig+0x108>
{
return HAL_TIMEOUT;
80039e4: 2303 movs r3, #3
80039e6: e283 b.n 8003ef0 <HAL_RCC_OscConfig+0x610>
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
80039e8: 4b88 ldr r3, [pc, #544] ; (8003c0c <HAL_RCC_OscConfig+0x32c>)
80039ea: 681a ldr r2, [r3, #0]
80039ec: 2380 movs r3, #128 ; 0x80
80039ee: 029b lsls r3, r3, #10
80039f0: 4013 ands r3, r2
80039f2: d1f0 bne.n 80039d6 <HAL_RCC_OscConfig+0xf6>
80039f4: e000 b.n 80039f8 <HAL_RCC_OscConfig+0x118>
if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
80039f6: 46c0 nop ; (mov r8, r8)
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
80039f8: 687b ldr r3, [r7, #4]
80039fa: 681b ldr r3, [r3, #0]
80039fc: 2202 movs r2, #2
80039fe: 4013 ands r3, r2
8003a00: d100 bne.n 8003a04 <HAL_RCC_OscConfig+0x124>
8003a02: e099 b.n 8003b38 <HAL_RCC_OscConfig+0x258>
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
assert_param(IS_RCC_HSIDIV(RCC_OscInitStruct->HSIDiv));
/* Check if HSI16 is used as system clock or as PLL source when PLL is selected as system clock */
temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
8003a04: 4b81 ldr r3, [pc, #516] ; (8003c0c <HAL_RCC_OscConfig+0x32c>)
8003a06: 689b ldr r3, [r3, #8]
8003a08: 2238 movs r2, #56 ; 0x38
8003a0a: 4013 ands r3, r2
8003a0c: 61bb str r3, [r7, #24]
temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE();
8003a0e: 4b7f ldr r3, [pc, #508] ; (8003c0c <HAL_RCC_OscConfig+0x32c>)
8003a10: 68db ldr r3, [r3, #12]
8003a12: 2203 movs r2, #3
8003a14: 4013 ands r3, r2
8003a16: 617b str r3, [r7, #20]
if (((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_pllckcfg == RCC_PLLSOURCE_HSI))
8003a18: 69bb ldr r3, [r7, #24]
8003a1a: 2b10 cmp r3, #16
8003a1c: d102 bne.n 8003a24 <HAL_RCC_OscConfig+0x144>
8003a1e: 697b ldr r3, [r7, #20]
8003a20: 2b02 cmp r3, #2
8003a22: d002 beq.n 8003a2a <HAL_RCC_OscConfig+0x14a>
|| (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI))
8003a24: 69bb ldr r3, [r7, #24]
8003a26: 2b00 cmp r3, #0
8003a28: d135 bne.n 8003a96 <HAL_RCC_OscConfig+0x1b6>
{
/* When HSI is used as system clock or as PLL input clock it can not be disabled */
if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
8003a2a: 4b78 ldr r3, [pc, #480] ; (8003c0c <HAL_RCC_OscConfig+0x32c>)
8003a2c: 681a ldr r2, [r3, #0]
8003a2e: 2380 movs r3, #128 ; 0x80
8003a30: 00db lsls r3, r3, #3
8003a32: 4013 ands r3, r2
8003a34: d005 beq.n 8003a42 <HAL_RCC_OscConfig+0x162>
8003a36: 687b ldr r3, [r7, #4]
8003a38: 68db ldr r3, [r3, #12]
8003a3a: 2b00 cmp r3, #0
8003a3c: d101 bne.n 8003a42 <HAL_RCC_OscConfig+0x162>
{
return HAL_ERROR;
8003a3e: 2301 movs r3, #1
8003a40: e256 b.n 8003ef0 <HAL_RCC_OscConfig+0x610>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8003a42: 4b72 ldr r3, [pc, #456] ; (8003c0c <HAL_RCC_OscConfig+0x32c>)
8003a44: 685b ldr r3, [r3, #4]
8003a46: 4a74 ldr r2, [pc, #464] ; (8003c18 <HAL_RCC_OscConfig+0x338>)
8003a48: 4013 ands r3, r2
8003a4a: 0019 movs r1, r3
8003a4c: 687b ldr r3, [r7, #4]
8003a4e: 695b ldr r3, [r3, #20]
8003a50: 021a lsls r2, r3, #8
8003a52: 4b6e ldr r3, [pc, #440] ; (8003c0c <HAL_RCC_OscConfig+0x32c>)
8003a54: 430a orrs r2, r1
8003a56: 605a str r2, [r3, #4]
if (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI)
8003a58: 69bb ldr r3, [r7, #24]
8003a5a: 2b00 cmp r3, #0
8003a5c: d112 bne.n 8003a84 <HAL_RCC_OscConfig+0x1a4>
{
/* Adjust the HSI16 division factor */
__HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv);
8003a5e: 4b6b ldr r3, [pc, #428] ; (8003c0c <HAL_RCC_OscConfig+0x32c>)
8003a60: 681b ldr r3, [r3, #0]
8003a62: 4a6e ldr r2, [pc, #440] ; (8003c1c <HAL_RCC_OscConfig+0x33c>)
8003a64: 4013 ands r3, r2
8003a66: 0019 movs r1, r3
8003a68: 687b ldr r3, [r7, #4]
8003a6a: 691a ldr r2, [r3, #16]
8003a6c: 4b67 ldr r3, [pc, #412] ; (8003c0c <HAL_RCC_OscConfig+0x32c>)
8003a6e: 430a orrs r2, r1
8003a70: 601a str r2, [r3, #0]
/* Update the SystemCoreClock global variable with HSISYS value */
SystemCoreClock = (HSI_VALUE / (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos)));
8003a72: 4b66 ldr r3, [pc, #408] ; (8003c0c <HAL_RCC_OscConfig+0x32c>)
8003a74: 681b ldr r3, [r3, #0]
8003a76: 0adb lsrs r3, r3, #11
8003a78: 2207 movs r2, #7
8003a7a: 4013 ands r3, r2
8003a7c: 4a68 ldr r2, [pc, #416] ; (8003c20 <HAL_RCC_OscConfig+0x340>)
8003a7e: 40da lsrs r2, r3
8003a80: 4b68 ldr r3, [pc, #416] ; (8003c24 <HAL_RCC_OscConfig+0x344>)
8003a82: 601a str r2, [r3, #0]
}
/* Adapt Systick interrupt period */
if (HAL_InitTick(uwTickPrio) != HAL_OK)
8003a84: 4b68 ldr r3, [pc, #416] ; (8003c28 <HAL_RCC_OscConfig+0x348>)
8003a86: 681b ldr r3, [r3, #0]
8003a88: 0018 movs r0, r3
8003a8a: f7fe f80f bl 8001aac <HAL_InitTick>
8003a8e: 1e03 subs r3, r0, #0
8003a90: d051 beq.n 8003b36 <HAL_RCC_OscConfig+0x256>
{
return HAL_ERROR;
8003a92: 2301 movs r3, #1
8003a94: e22c b.n 8003ef0 <HAL_RCC_OscConfig+0x610>
}
}
else
{
/* Check the HSI State */
if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
8003a96: 687b ldr r3, [r7, #4]
8003a98: 68db ldr r3, [r3, #12]
8003a9a: 2b00 cmp r3, #0
8003a9c: d030 beq.n 8003b00 <HAL_RCC_OscConfig+0x220>
{
/* Configure the HSI16 division factor */
__HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv);
8003a9e: 4b5b ldr r3, [pc, #364] ; (8003c0c <HAL_RCC_OscConfig+0x32c>)
8003aa0: 681b ldr r3, [r3, #0]
8003aa2: 4a5e ldr r2, [pc, #376] ; (8003c1c <HAL_RCC_OscConfig+0x33c>)
8003aa4: 4013 ands r3, r2
8003aa6: 0019 movs r1, r3
8003aa8: 687b ldr r3, [r7, #4]
8003aaa: 691a ldr r2, [r3, #16]
8003aac: 4b57 ldr r3, [pc, #348] ; (8003c0c <HAL_RCC_OscConfig+0x32c>)
8003aae: 430a orrs r2, r1
8003ab0: 601a str r2, [r3, #0]
/* Enable the Internal High Speed oscillator (HSI16). */
__HAL_RCC_HSI_ENABLE();
8003ab2: 4b56 ldr r3, [pc, #344] ; (8003c0c <HAL_RCC_OscConfig+0x32c>)
8003ab4: 681a ldr r2, [r3, #0]
8003ab6: 4b55 ldr r3, [pc, #340] ; (8003c0c <HAL_RCC_OscConfig+0x32c>)
8003ab8: 2180 movs r1, #128 ; 0x80
8003aba: 0049 lsls r1, r1, #1
8003abc: 430a orrs r2, r1
8003abe: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003ac0: f7fe f850 bl 8001b64 <HAL_GetTick>
8003ac4: 0003 movs r3, r0
8003ac6: 613b str r3, [r7, #16]
/* Wait till HSI is ready */
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
8003ac8: e008 b.n 8003adc <HAL_RCC_OscConfig+0x1fc>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
8003aca: f7fe f84b bl 8001b64 <HAL_GetTick>
8003ace: 0002 movs r2, r0
8003ad0: 693b ldr r3, [r7, #16]
8003ad2: 1ad3 subs r3, r2, r3
8003ad4: 2b02 cmp r3, #2
8003ad6: d901 bls.n 8003adc <HAL_RCC_OscConfig+0x1fc>
{
return HAL_TIMEOUT;
8003ad8: 2303 movs r3, #3
8003ada: e209 b.n 8003ef0 <HAL_RCC_OscConfig+0x610>
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
8003adc: 4b4b ldr r3, [pc, #300] ; (8003c0c <HAL_RCC_OscConfig+0x32c>)
8003ade: 681a ldr r2, [r3, #0]
8003ae0: 2380 movs r3, #128 ; 0x80
8003ae2: 00db lsls r3, r3, #3
8003ae4: 4013 ands r3, r2
8003ae6: d0f0 beq.n 8003aca <HAL_RCC_OscConfig+0x1ea>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8003ae8: 4b48 ldr r3, [pc, #288] ; (8003c0c <HAL_RCC_OscConfig+0x32c>)
8003aea: 685b ldr r3, [r3, #4]
8003aec: 4a4a ldr r2, [pc, #296] ; (8003c18 <HAL_RCC_OscConfig+0x338>)
8003aee: 4013 ands r3, r2
8003af0: 0019 movs r1, r3
8003af2: 687b ldr r3, [r7, #4]
8003af4: 695b ldr r3, [r3, #20]
8003af6: 021a lsls r2, r3, #8
8003af8: 4b44 ldr r3, [pc, #272] ; (8003c0c <HAL_RCC_OscConfig+0x32c>)
8003afa: 430a orrs r2, r1
8003afc: 605a str r2, [r3, #4]
8003afe: e01b b.n 8003b38 <HAL_RCC_OscConfig+0x258>
}
else
{
/* Disable the Internal High Speed oscillator (HSI16). */
__HAL_RCC_HSI_DISABLE();
8003b00: 4b42 ldr r3, [pc, #264] ; (8003c0c <HAL_RCC_OscConfig+0x32c>)
8003b02: 681a ldr r2, [r3, #0]
8003b04: 4b41 ldr r3, [pc, #260] ; (8003c0c <HAL_RCC_OscConfig+0x32c>)
8003b06: 4949 ldr r1, [pc, #292] ; (8003c2c <HAL_RCC_OscConfig+0x34c>)
8003b08: 400a ands r2, r1
8003b0a: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003b0c: f7fe f82a bl 8001b64 <HAL_GetTick>
8003b10: 0003 movs r3, r0
8003b12: 613b str r3, [r7, #16]
/* Wait till HSI is disabled */
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
8003b14: e008 b.n 8003b28 <HAL_RCC_OscConfig+0x248>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
8003b16: f7fe f825 bl 8001b64 <HAL_GetTick>
8003b1a: 0002 movs r2, r0
8003b1c: 693b ldr r3, [r7, #16]
8003b1e: 1ad3 subs r3, r2, r3
8003b20: 2b02 cmp r3, #2
8003b22: d901 bls.n 8003b28 <HAL_RCC_OscConfig+0x248>
{
return HAL_TIMEOUT;
8003b24: 2303 movs r3, #3
8003b26: e1e3 b.n 8003ef0 <HAL_RCC_OscConfig+0x610>
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
8003b28: 4b38 ldr r3, [pc, #224] ; (8003c0c <HAL_RCC_OscConfig+0x32c>)
8003b2a: 681a ldr r2, [r3, #0]
8003b2c: 2380 movs r3, #128 ; 0x80
8003b2e: 00db lsls r3, r3, #3
8003b30: 4013 ands r3, r2
8003b32: d1f0 bne.n 8003b16 <HAL_RCC_OscConfig+0x236>
8003b34: e000 b.n 8003b38 <HAL_RCC_OscConfig+0x258>
if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
8003b36: 46c0 nop ; (mov r8, r8)
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
8003b38: 687b ldr r3, [r7, #4]
8003b3a: 681b ldr r3, [r3, #0]
8003b3c: 2208 movs r2, #8
8003b3e: 4013 ands r3, r2
8003b40: d047 beq.n 8003bd2 <HAL_RCC_OscConfig+0x2f2>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check if LSI is used as system clock */
if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSI)
8003b42: 4b32 ldr r3, [pc, #200] ; (8003c0c <HAL_RCC_OscConfig+0x32c>)
8003b44: 689b ldr r3, [r3, #8]
8003b46: 2238 movs r2, #56 ; 0x38
8003b48: 4013 ands r3, r2
8003b4a: 2b18 cmp r3, #24
8003b4c: d10a bne.n 8003b64 <HAL_RCC_OscConfig+0x284>
{
/* When LSI is used as system clock it will not be disabled */
if ((((RCC->CSR) & RCC_CSR_LSIRDY) != 0U) && (RCC_OscInitStruct->LSIState == RCC_LSI_OFF))
8003b4e: 4b2f ldr r3, [pc, #188] ; (8003c0c <HAL_RCC_OscConfig+0x32c>)
8003b50: 6e1b ldr r3, [r3, #96] ; 0x60
8003b52: 2202 movs r2, #2
8003b54: 4013 ands r3, r2
8003b56: d03c beq.n 8003bd2 <HAL_RCC_OscConfig+0x2f2>
8003b58: 687b ldr r3, [r7, #4]
8003b5a: 699b ldr r3, [r3, #24]
8003b5c: 2b00 cmp r3, #0
8003b5e: d138 bne.n 8003bd2 <HAL_RCC_OscConfig+0x2f2>
{
return HAL_ERROR;
8003b60: 2301 movs r3, #1
8003b62: e1c5 b.n 8003ef0 <HAL_RCC_OscConfig+0x610>
}
}
else
{
/* Check the LSI State */
if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
8003b64: 687b ldr r3, [r7, #4]
8003b66: 699b ldr r3, [r3, #24]
8003b68: 2b00 cmp r3, #0
8003b6a: d019 beq.n 8003ba0 <HAL_RCC_OscConfig+0x2c0>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
8003b6c: 4b27 ldr r3, [pc, #156] ; (8003c0c <HAL_RCC_OscConfig+0x32c>)
8003b6e: 6e1a ldr r2, [r3, #96] ; 0x60
8003b70: 4b26 ldr r3, [pc, #152] ; (8003c0c <HAL_RCC_OscConfig+0x32c>)
8003b72: 2101 movs r1, #1
8003b74: 430a orrs r2, r1
8003b76: 661a str r2, [r3, #96] ; 0x60
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003b78: f7fd fff4 bl 8001b64 <HAL_GetTick>
8003b7c: 0003 movs r3, r0
8003b7e: 613b str r3, [r7, #16]
/* Wait till LSI is ready */
while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
8003b80: e008 b.n 8003b94 <HAL_RCC_OscConfig+0x2b4>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
8003b82: f7fd ffef bl 8001b64 <HAL_GetTick>
8003b86: 0002 movs r2, r0
8003b88: 693b ldr r3, [r7, #16]
8003b8a: 1ad3 subs r3, r2, r3
8003b8c: 2b02 cmp r3, #2
8003b8e: d901 bls.n 8003b94 <HAL_RCC_OscConfig+0x2b4>
{
return HAL_TIMEOUT;
8003b90: 2303 movs r3, #3
8003b92: e1ad b.n 8003ef0 <HAL_RCC_OscConfig+0x610>
while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
8003b94: 4b1d ldr r3, [pc, #116] ; (8003c0c <HAL_RCC_OscConfig+0x32c>)
8003b96: 6e1b ldr r3, [r3, #96] ; 0x60
8003b98: 2202 movs r2, #2
8003b9a: 4013 ands r3, r2
8003b9c: d0f1 beq.n 8003b82 <HAL_RCC_OscConfig+0x2a2>
8003b9e: e018 b.n 8003bd2 <HAL_RCC_OscConfig+0x2f2>
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
8003ba0: 4b1a ldr r3, [pc, #104] ; (8003c0c <HAL_RCC_OscConfig+0x32c>)
8003ba2: 6e1a ldr r2, [r3, #96] ; 0x60
8003ba4: 4b19 ldr r3, [pc, #100] ; (8003c0c <HAL_RCC_OscConfig+0x32c>)
8003ba6: 2101 movs r1, #1
8003ba8: 438a bics r2, r1
8003baa: 661a str r2, [r3, #96] ; 0x60
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003bac: f7fd ffda bl 8001b64 <HAL_GetTick>
8003bb0: 0003 movs r3, r0
8003bb2: 613b str r3, [r7, #16]
/* Wait till LSI is disabled */
while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
8003bb4: e008 b.n 8003bc8 <HAL_RCC_OscConfig+0x2e8>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
8003bb6: f7fd ffd5 bl 8001b64 <HAL_GetTick>
8003bba: 0002 movs r2, r0
8003bbc: 693b ldr r3, [r7, #16]
8003bbe: 1ad3 subs r3, r2, r3
8003bc0: 2b02 cmp r3, #2
8003bc2: d901 bls.n 8003bc8 <HAL_RCC_OscConfig+0x2e8>
{
return HAL_TIMEOUT;
8003bc4: 2303 movs r3, #3
8003bc6: e193 b.n 8003ef0 <HAL_RCC_OscConfig+0x610>
while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
8003bc8: 4b10 ldr r3, [pc, #64] ; (8003c0c <HAL_RCC_OscConfig+0x32c>)
8003bca: 6e1b ldr r3, [r3, #96] ; 0x60
8003bcc: 2202 movs r2, #2
8003bce: 4013 ands r3, r2
8003bd0: d1f1 bne.n 8003bb6 <HAL_RCC_OscConfig+0x2d6>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
8003bd2: 687b ldr r3, [r7, #4]
8003bd4: 681b ldr r3, [r3, #0]
8003bd6: 2204 movs r2, #4
8003bd8: 4013 ands r3, r2
8003bda: d100 bne.n 8003bde <HAL_RCC_OscConfig+0x2fe>
8003bdc: e0c6 b.n 8003d6c <HAL_RCC_OscConfig+0x48c>
{
FlagStatus pwrclkchanged = RESET;
8003bde: 231f movs r3, #31
8003be0: 18fb adds r3, r7, r3
8003be2: 2200 movs r2, #0
8003be4: 701a strb r2, [r3, #0]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* When the LSE is used as system clock, it is not allowed disable it */
if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSE)
8003be6: 4b09 ldr r3, [pc, #36] ; (8003c0c <HAL_RCC_OscConfig+0x32c>)
8003be8: 689b ldr r3, [r3, #8]
8003bea: 2238 movs r2, #56 ; 0x38
8003bec: 4013 ands r3, r2
8003bee: 2b20 cmp r3, #32
8003bf0: d11e bne.n 8003c30 <HAL_RCC_OscConfig+0x350>
{
if ((((RCC->BDCR) & RCC_BDCR_LSERDY) != 0U) && (RCC_OscInitStruct->LSEState == RCC_LSE_OFF))
8003bf2: 4b06 ldr r3, [pc, #24] ; (8003c0c <HAL_RCC_OscConfig+0x32c>)
8003bf4: 6ddb ldr r3, [r3, #92] ; 0x5c
8003bf6: 2202 movs r2, #2
8003bf8: 4013 ands r3, r2
8003bfa: d100 bne.n 8003bfe <HAL_RCC_OscConfig+0x31e>
8003bfc: e0b6 b.n 8003d6c <HAL_RCC_OscConfig+0x48c>
8003bfe: 687b ldr r3, [r7, #4]
8003c00: 689b ldr r3, [r3, #8]
8003c02: 2b00 cmp r3, #0
8003c04: d000 beq.n 8003c08 <HAL_RCC_OscConfig+0x328>
8003c06: e0b1 b.n 8003d6c <HAL_RCC_OscConfig+0x48c>
{
return HAL_ERROR;
8003c08: 2301 movs r3, #1
8003c0a: e171 b.n 8003ef0 <HAL_RCC_OscConfig+0x610>
8003c0c: 40021000 .word 0x40021000
8003c10: fffeffff .word 0xfffeffff
8003c14: fffbffff .word 0xfffbffff
8003c18: ffff80ff .word 0xffff80ff
8003c1c: ffffc7ff .word 0xffffc7ff
8003c20: 00f42400 .word 0x00f42400
8003c24: 2000000c .word 0x2000000c
8003c28: 20000010 .word 0x20000010
8003c2c: fffffeff .word 0xfffffeff
}
else
{
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if (__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U)
8003c30: 4bb1 ldr r3, [pc, #708] ; (8003ef8 <HAL_RCC_OscConfig+0x618>)
8003c32: 6bda ldr r2, [r3, #60] ; 0x3c
8003c34: 2380 movs r3, #128 ; 0x80
8003c36: 055b lsls r3, r3, #21
8003c38: 4013 ands r3, r2
8003c3a: d101 bne.n 8003c40 <HAL_RCC_OscConfig+0x360>
8003c3c: 2301 movs r3, #1
8003c3e: e000 b.n 8003c42 <HAL_RCC_OscConfig+0x362>
8003c40: 2300 movs r3, #0
8003c42: 2b00 cmp r3, #0
8003c44: d011 beq.n 8003c6a <HAL_RCC_OscConfig+0x38a>
{
__HAL_RCC_PWR_CLK_ENABLE();
8003c46: 4bac ldr r3, [pc, #688] ; (8003ef8 <HAL_RCC_OscConfig+0x618>)
8003c48: 6bda ldr r2, [r3, #60] ; 0x3c
8003c4a: 4bab ldr r3, [pc, #684] ; (8003ef8 <HAL_RCC_OscConfig+0x618>)
8003c4c: 2180 movs r1, #128 ; 0x80
8003c4e: 0549 lsls r1, r1, #21
8003c50: 430a orrs r2, r1
8003c52: 63da str r2, [r3, #60] ; 0x3c
8003c54: 4ba8 ldr r3, [pc, #672] ; (8003ef8 <HAL_RCC_OscConfig+0x618>)
8003c56: 6bda ldr r2, [r3, #60] ; 0x3c
8003c58: 2380 movs r3, #128 ; 0x80
8003c5a: 055b lsls r3, r3, #21
8003c5c: 4013 ands r3, r2
8003c5e: 60fb str r3, [r7, #12]
8003c60: 68fb ldr r3, [r7, #12]
pwrclkchanged = SET;
8003c62: 231f movs r3, #31
8003c64: 18fb adds r3, r7, r3
8003c66: 2201 movs r2, #1
8003c68: 701a strb r2, [r3, #0]
}
if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
8003c6a: 4ba4 ldr r3, [pc, #656] ; (8003efc <HAL_RCC_OscConfig+0x61c>)
8003c6c: 681a ldr r2, [r3, #0]
8003c6e: 2380 movs r3, #128 ; 0x80
8003c70: 005b lsls r3, r3, #1
8003c72: 4013 ands r3, r2
8003c74: d11a bne.n 8003cac <HAL_RCC_OscConfig+0x3cc>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR1, PWR_CR1_DBP);
8003c76: 4ba1 ldr r3, [pc, #644] ; (8003efc <HAL_RCC_OscConfig+0x61c>)
8003c78: 681a ldr r2, [r3, #0]
8003c7a: 4ba0 ldr r3, [pc, #640] ; (8003efc <HAL_RCC_OscConfig+0x61c>)
8003c7c: 2180 movs r1, #128 ; 0x80
8003c7e: 0049 lsls r1, r1, #1
8003c80: 430a orrs r2, r1
8003c82: 601a str r2, [r3, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
8003c84: f7fd ff6e bl 8001b64 <HAL_GetTick>
8003c88: 0003 movs r3, r0
8003c8a: 613b str r3, [r7, #16]
while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
8003c8c: e008 b.n 8003ca0 <HAL_RCC_OscConfig+0x3c0>
{
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8003c8e: f7fd ff69 bl 8001b64 <HAL_GetTick>
8003c92: 0002 movs r2, r0
8003c94: 693b ldr r3, [r7, #16]
8003c96: 1ad3 subs r3, r2, r3
8003c98: 2b02 cmp r3, #2
8003c9a: d901 bls.n 8003ca0 <HAL_RCC_OscConfig+0x3c0>
{
return HAL_TIMEOUT;
8003c9c: 2303 movs r3, #3
8003c9e: e127 b.n 8003ef0 <HAL_RCC_OscConfig+0x610>
while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
8003ca0: 4b96 ldr r3, [pc, #600] ; (8003efc <HAL_RCC_OscConfig+0x61c>)
8003ca2: 681a ldr r2, [r3, #0]
8003ca4: 2380 movs r3, #128 ; 0x80
8003ca6: 005b lsls r3, r3, #1
8003ca8: 4013 ands r3, r2
8003caa: d0f0 beq.n 8003c8e <HAL_RCC_OscConfig+0x3ae>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
8003cac: 687b ldr r3, [r7, #4]
8003cae: 689b ldr r3, [r3, #8]
8003cb0: 2b01 cmp r3, #1
8003cb2: d106 bne.n 8003cc2 <HAL_RCC_OscConfig+0x3e2>
8003cb4: 4b90 ldr r3, [pc, #576] ; (8003ef8 <HAL_RCC_OscConfig+0x618>)
8003cb6: 6dda ldr r2, [r3, #92] ; 0x5c
8003cb8: 4b8f ldr r3, [pc, #572] ; (8003ef8 <HAL_RCC_OscConfig+0x618>)
8003cba: 2101 movs r1, #1
8003cbc: 430a orrs r2, r1
8003cbe: 65da str r2, [r3, #92] ; 0x5c
8003cc0: e01c b.n 8003cfc <HAL_RCC_OscConfig+0x41c>
8003cc2: 687b ldr r3, [r7, #4]
8003cc4: 689b ldr r3, [r3, #8]
8003cc6: 2b05 cmp r3, #5
8003cc8: d10c bne.n 8003ce4 <HAL_RCC_OscConfig+0x404>
8003cca: 4b8b ldr r3, [pc, #556] ; (8003ef8 <HAL_RCC_OscConfig+0x618>)
8003ccc: 6dda ldr r2, [r3, #92] ; 0x5c
8003cce: 4b8a ldr r3, [pc, #552] ; (8003ef8 <HAL_RCC_OscConfig+0x618>)
8003cd0: 2104 movs r1, #4
8003cd2: 430a orrs r2, r1
8003cd4: 65da str r2, [r3, #92] ; 0x5c
8003cd6: 4b88 ldr r3, [pc, #544] ; (8003ef8 <HAL_RCC_OscConfig+0x618>)
8003cd8: 6dda ldr r2, [r3, #92] ; 0x5c
8003cda: 4b87 ldr r3, [pc, #540] ; (8003ef8 <HAL_RCC_OscConfig+0x618>)
8003cdc: 2101 movs r1, #1
8003cde: 430a orrs r2, r1
8003ce0: 65da str r2, [r3, #92] ; 0x5c
8003ce2: e00b b.n 8003cfc <HAL_RCC_OscConfig+0x41c>
8003ce4: 4b84 ldr r3, [pc, #528] ; (8003ef8 <HAL_RCC_OscConfig+0x618>)
8003ce6: 6dda ldr r2, [r3, #92] ; 0x5c
8003ce8: 4b83 ldr r3, [pc, #524] ; (8003ef8 <HAL_RCC_OscConfig+0x618>)
8003cea: 2101 movs r1, #1
8003cec: 438a bics r2, r1
8003cee: 65da str r2, [r3, #92] ; 0x5c
8003cf0: 4b81 ldr r3, [pc, #516] ; (8003ef8 <HAL_RCC_OscConfig+0x618>)
8003cf2: 6dda ldr r2, [r3, #92] ; 0x5c
8003cf4: 4b80 ldr r3, [pc, #512] ; (8003ef8 <HAL_RCC_OscConfig+0x618>)
8003cf6: 2104 movs r1, #4
8003cf8: 438a bics r2, r1
8003cfa: 65da str r2, [r3, #92] ; 0x5c
/* Check the LSE State */
if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
8003cfc: 687b ldr r3, [r7, #4]
8003cfe: 689b ldr r3, [r3, #8]
8003d00: 2b00 cmp r3, #0
8003d02: d014 beq.n 8003d2e <HAL_RCC_OscConfig+0x44e>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003d04: f7fd ff2e bl 8001b64 <HAL_GetTick>
8003d08: 0003 movs r3, r0
8003d0a: 613b str r3, [r7, #16]
/* Wait till LSE is ready */
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
8003d0c: e009 b.n 8003d22 <HAL_RCC_OscConfig+0x442>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8003d0e: f7fd ff29 bl 8001b64 <HAL_GetTick>
8003d12: 0002 movs r2, r0
8003d14: 693b ldr r3, [r7, #16]
8003d16: 1ad3 subs r3, r2, r3
8003d18: 4a79 ldr r2, [pc, #484] ; (8003f00 <HAL_RCC_OscConfig+0x620>)
8003d1a: 4293 cmp r3, r2
8003d1c: d901 bls.n 8003d22 <HAL_RCC_OscConfig+0x442>
{
return HAL_TIMEOUT;
8003d1e: 2303 movs r3, #3
8003d20: e0e6 b.n 8003ef0 <HAL_RCC_OscConfig+0x610>
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
8003d22: 4b75 ldr r3, [pc, #468] ; (8003ef8 <HAL_RCC_OscConfig+0x618>)
8003d24: 6ddb ldr r3, [r3, #92] ; 0x5c
8003d26: 2202 movs r2, #2
8003d28: 4013 ands r3, r2
8003d2a: d0f0 beq.n 8003d0e <HAL_RCC_OscConfig+0x42e>
8003d2c: e013 b.n 8003d56 <HAL_RCC_OscConfig+0x476>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003d2e: f7fd ff19 bl 8001b64 <HAL_GetTick>
8003d32: 0003 movs r3, r0
8003d34: 613b str r3, [r7, #16]
/* Wait till LSE is disabled */
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
8003d36: e009 b.n 8003d4c <HAL_RCC_OscConfig+0x46c>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8003d38: f7fd ff14 bl 8001b64 <HAL_GetTick>
8003d3c: 0002 movs r2, r0
8003d3e: 693b ldr r3, [r7, #16]
8003d40: 1ad3 subs r3, r2, r3
8003d42: 4a6f ldr r2, [pc, #444] ; (8003f00 <HAL_RCC_OscConfig+0x620>)
8003d44: 4293 cmp r3, r2
8003d46: d901 bls.n 8003d4c <HAL_RCC_OscConfig+0x46c>
{
return HAL_TIMEOUT;
8003d48: 2303 movs r3, #3
8003d4a: e0d1 b.n 8003ef0 <HAL_RCC_OscConfig+0x610>
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
8003d4c: 4b6a ldr r3, [pc, #424] ; (8003ef8 <HAL_RCC_OscConfig+0x618>)
8003d4e: 6ddb ldr r3, [r3, #92] ; 0x5c
8003d50: 2202 movs r2, #2
8003d52: 4013 ands r3, r2
8003d54: d1f0 bne.n 8003d38 <HAL_RCC_OscConfig+0x458>
}
}
}
/* Restore clock configuration if changed */
if (pwrclkchanged == SET)
8003d56: 231f movs r3, #31
8003d58: 18fb adds r3, r7, r3
8003d5a: 781b ldrb r3, [r3, #0]
8003d5c: 2b01 cmp r3, #1
8003d5e: d105 bne.n 8003d6c <HAL_RCC_OscConfig+0x48c>
{
__HAL_RCC_PWR_CLK_DISABLE();
8003d60: 4b65 ldr r3, [pc, #404] ; (8003ef8 <HAL_RCC_OscConfig+0x618>)
8003d62: 6bda ldr r2, [r3, #60] ; 0x3c
8003d64: 4b64 ldr r3, [pc, #400] ; (8003ef8 <HAL_RCC_OscConfig+0x618>)
8003d66: 4967 ldr r1, [pc, #412] ; (8003f04 <HAL_RCC_OscConfig+0x624>)
8003d68: 400a ands r2, r1
8003d6a: 63da str r2, [r3, #60] ; 0x3c
#endif /* RCC_HSI48_SUPPORT */
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE)
8003d6c: 687b ldr r3, [r7, #4]
8003d6e: 69db ldr r3, [r3, #28]
8003d70: 2b00 cmp r3, #0
8003d72: d100 bne.n 8003d76 <HAL_RCC_OscConfig+0x496>
8003d74: e0bb b.n 8003eee <HAL_RCC_OscConfig+0x60e>
{
/* Check if the PLL is used as system clock or not */
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
8003d76: 4b60 ldr r3, [pc, #384] ; (8003ef8 <HAL_RCC_OscConfig+0x618>)
8003d78: 689b ldr r3, [r3, #8]
8003d7a: 2238 movs r2, #56 ; 0x38
8003d7c: 4013 ands r3, r2
8003d7e: 2b10 cmp r3, #16
8003d80: d100 bne.n 8003d84 <HAL_RCC_OscConfig+0x4a4>
8003d82: e07b b.n 8003e7c <HAL_RCC_OscConfig+0x59c>
{
if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON)
8003d84: 687b ldr r3, [r7, #4]
8003d86: 69db ldr r3, [r3, #28]
8003d88: 2b02 cmp r3, #2
8003d8a: d156 bne.n 8003e3a <HAL_RCC_OscConfig+0x55a>
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
#endif /* RCC_PLLQ_SUPPORT */
assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8003d8c: 4b5a ldr r3, [pc, #360] ; (8003ef8 <HAL_RCC_OscConfig+0x618>)
8003d8e: 681a ldr r2, [r3, #0]
8003d90: 4b59 ldr r3, [pc, #356] ; (8003ef8 <HAL_RCC_OscConfig+0x618>)
8003d92: 495d ldr r1, [pc, #372] ; (8003f08 <HAL_RCC_OscConfig+0x628>)
8003d94: 400a ands r2, r1
8003d96: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003d98: f7fd fee4 bl 8001b64 <HAL_GetTick>
8003d9c: 0003 movs r3, r0
8003d9e: 613b str r3, [r7, #16]
/* Wait till PLL is ready */
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
8003da0: e008 b.n 8003db4 <HAL_RCC_OscConfig+0x4d4>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8003da2: f7fd fedf bl 8001b64 <HAL_GetTick>
8003da6: 0002 movs r2, r0
8003da8: 693b ldr r3, [r7, #16]
8003daa: 1ad3 subs r3, r2, r3
8003dac: 2b02 cmp r3, #2
8003dae: d901 bls.n 8003db4 <HAL_RCC_OscConfig+0x4d4>
{
return HAL_TIMEOUT;
8003db0: 2303 movs r3, #3
8003db2: e09d b.n 8003ef0 <HAL_RCC_OscConfig+0x610>
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
8003db4: 4b50 ldr r3, [pc, #320] ; (8003ef8 <HAL_RCC_OscConfig+0x618>)
8003db6: 681a ldr r2, [r3, #0]
8003db8: 2380 movs r3, #128 ; 0x80
8003dba: 049b lsls r3, r3, #18
8003dbc: 4013 ands r3, r2
8003dbe: d1f0 bne.n 8003da2 <HAL_RCC_OscConfig+0x4c2>
}
}
/* Configure the main PLL clock source, multiplication and division factors. */
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
8003dc0: 4b4d ldr r3, [pc, #308] ; (8003ef8 <HAL_RCC_OscConfig+0x618>)
8003dc2: 68db ldr r3, [r3, #12]
8003dc4: 4a51 ldr r2, [pc, #324] ; (8003f0c <HAL_RCC_OscConfig+0x62c>)
8003dc6: 4013 ands r3, r2
8003dc8: 0019 movs r1, r3
8003dca: 687b ldr r3, [r7, #4]
8003dcc: 6a1a ldr r2, [r3, #32]
8003dce: 687b ldr r3, [r7, #4]
8003dd0: 6a5b ldr r3, [r3, #36] ; 0x24
8003dd2: 431a orrs r2, r3
8003dd4: 687b ldr r3, [r7, #4]
8003dd6: 6a9b ldr r3, [r3, #40] ; 0x28
8003dd8: 021b lsls r3, r3, #8
8003dda: 431a orrs r2, r3
8003ddc: 687b ldr r3, [r7, #4]
8003dde: 6adb ldr r3, [r3, #44] ; 0x2c
8003de0: 431a orrs r2, r3
8003de2: 687b ldr r3, [r7, #4]
8003de4: 6b1b ldr r3, [r3, #48] ; 0x30
8003de6: 431a orrs r2, r3
8003de8: 687b ldr r3, [r7, #4]
8003dea: 6b5b ldr r3, [r3, #52] ; 0x34
8003dec: 431a orrs r2, r3
8003dee: 4b42 ldr r3, [pc, #264] ; (8003ef8 <HAL_RCC_OscConfig+0x618>)
8003df0: 430a orrs r2, r1
8003df2: 60da str r2, [r3, #12]
RCC_OscInitStruct->PLL.PLLQ,
#endif /* RCC_PLLQ_SUPPORT */
RCC_OscInitStruct->PLL.PLLR);
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
8003df4: 4b40 ldr r3, [pc, #256] ; (8003ef8 <HAL_RCC_OscConfig+0x618>)
8003df6: 681a ldr r2, [r3, #0]
8003df8: 4b3f ldr r3, [pc, #252] ; (8003ef8 <HAL_RCC_OscConfig+0x618>)
8003dfa: 2180 movs r1, #128 ; 0x80
8003dfc: 0449 lsls r1, r1, #17
8003dfe: 430a orrs r2, r1
8003e00: 601a str r2, [r3, #0]
/* Enable PLLR Clock output. */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLRCLK);
8003e02: 4b3d ldr r3, [pc, #244] ; (8003ef8 <HAL_RCC_OscConfig+0x618>)
8003e04: 68da ldr r2, [r3, #12]
8003e06: 4b3c ldr r3, [pc, #240] ; (8003ef8 <HAL_RCC_OscConfig+0x618>)
8003e08: 2180 movs r1, #128 ; 0x80
8003e0a: 0549 lsls r1, r1, #21
8003e0c: 430a orrs r2, r1
8003e0e: 60da str r2, [r3, #12]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003e10: f7fd fea8 bl 8001b64 <HAL_GetTick>
8003e14: 0003 movs r3, r0
8003e16: 613b str r3, [r7, #16]
/* Wait till PLL is ready */
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
8003e18: e008 b.n 8003e2c <HAL_RCC_OscConfig+0x54c>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8003e1a: f7fd fea3 bl 8001b64 <HAL_GetTick>
8003e1e: 0002 movs r2, r0
8003e20: 693b ldr r3, [r7, #16]
8003e22: 1ad3 subs r3, r2, r3
8003e24: 2b02 cmp r3, #2
8003e26: d901 bls.n 8003e2c <HAL_RCC_OscConfig+0x54c>
{
return HAL_TIMEOUT;
8003e28: 2303 movs r3, #3
8003e2a: e061 b.n 8003ef0 <HAL_RCC_OscConfig+0x610>
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
8003e2c: 4b32 ldr r3, [pc, #200] ; (8003ef8 <HAL_RCC_OscConfig+0x618>)
8003e2e: 681a ldr r2, [r3, #0]
8003e30: 2380 movs r3, #128 ; 0x80
8003e32: 049b lsls r3, r3, #18
8003e34: 4013 ands r3, r2
8003e36: d0f0 beq.n 8003e1a <HAL_RCC_OscConfig+0x53a>
8003e38: e059 b.n 8003eee <HAL_RCC_OscConfig+0x60e>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8003e3a: 4b2f ldr r3, [pc, #188] ; (8003ef8 <HAL_RCC_OscConfig+0x618>)
8003e3c: 681a ldr r2, [r3, #0]
8003e3e: 4b2e ldr r3, [pc, #184] ; (8003ef8 <HAL_RCC_OscConfig+0x618>)
8003e40: 4931 ldr r1, [pc, #196] ; (8003f08 <HAL_RCC_OscConfig+0x628>)
8003e42: 400a ands r2, r1
8003e44: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003e46: f7fd fe8d bl 8001b64 <HAL_GetTick>
8003e4a: 0003 movs r3, r0
8003e4c: 613b str r3, [r7, #16]
/* Wait till PLL is disabled */
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
8003e4e: e008 b.n 8003e62 <HAL_RCC_OscConfig+0x582>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8003e50: f7fd fe88 bl 8001b64 <HAL_GetTick>
8003e54: 0002 movs r2, r0
8003e56: 693b ldr r3, [r7, #16]
8003e58: 1ad3 subs r3, r2, r3
8003e5a: 2b02 cmp r3, #2
8003e5c: d901 bls.n 8003e62 <HAL_RCC_OscConfig+0x582>
{
return HAL_TIMEOUT;
8003e5e: 2303 movs r3, #3
8003e60: e046 b.n 8003ef0 <HAL_RCC_OscConfig+0x610>
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
8003e62: 4b25 ldr r3, [pc, #148] ; (8003ef8 <HAL_RCC_OscConfig+0x618>)
8003e64: 681a ldr r2, [r3, #0]
8003e66: 2380 movs r3, #128 ; 0x80
8003e68: 049b lsls r3, r3, #18
8003e6a: 4013 ands r3, r2
8003e6c: d1f0 bne.n 8003e50 <HAL_RCC_OscConfig+0x570>
}
}
/* Unselect main PLL clock source and disable main PLL outputs to save power */
#if defined(RCC_PLLQ_SUPPORT)
RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLPEN | RCC_PLLCFGR_PLLQEN | RCC_PLLCFGR_PLLREN);
8003e6e: 4b22 ldr r3, [pc, #136] ; (8003ef8 <HAL_RCC_OscConfig+0x618>)
8003e70: 68da ldr r2, [r3, #12]
8003e72: 4b21 ldr r3, [pc, #132] ; (8003ef8 <HAL_RCC_OscConfig+0x618>)
8003e74: 4926 ldr r1, [pc, #152] ; (8003f10 <HAL_RCC_OscConfig+0x630>)
8003e76: 400a ands r2, r1
8003e78: 60da str r2, [r3, #12]
8003e7a: e038 b.n 8003eee <HAL_RCC_OscConfig+0x60e>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
8003e7c: 687b ldr r3, [r7, #4]
8003e7e: 69db ldr r3, [r3, #28]
8003e80: 2b01 cmp r3, #1
8003e82: d101 bne.n 8003e88 <HAL_RCC_OscConfig+0x5a8>
{
return HAL_ERROR;
8003e84: 2301 movs r3, #1
8003e86: e033 b.n 8003ef0 <HAL_RCC_OscConfig+0x610>
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
temp_pllckcfg = RCC->PLLCFGR;
8003e88: 4b1b ldr r3, [pc, #108] ; (8003ef8 <HAL_RCC_OscConfig+0x618>)
8003e8a: 68db ldr r3, [r3, #12]
8003e8c: 617b str r3, [r7, #20]
if ((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8003e8e: 697b ldr r3, [r7, #20]
8003e90: 2203 movs r2, #3
8003e92: 401a ands r2, r3
8003e94: 687b ldr r3, [r7, #4]
8003e96: 6a1b ldr r3, [r3, #32]
8003e98: 429a cmp r2, r3
8003e9a: d126 bne.n 8003eea <HAL_RCC_OscConfig+0x60a>
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
8003e9c: 697b ldr r3, [r7, #20]
8003e9e: 2270 movs r2, #112 ; 0x70
8003ea0: 401a ands r2, r3
8003ea2: 687b ldr r3, [r7, #4]
8003ea4: 6a5b ldr r3, [r3, #36] ; 0x24
if ((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8003ea6: 429a cmp r2, r3
8003ea8: d11f bne.n 8003eea <HAL_RCC_OscConfig+0x60a>
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
8003eaa: 697a ldr r2, [r7, #20]
8003eac: 23fe movs r3, #254 ; 0xfe
8003eae: 01db lsls r3, r3, #7
8003eb0: 401a ands r2, r3
8003eb2: 687b ldr r3, [r7, #4]
8003eb4: 6a9b ldr r3, [r3, #40] ; 0x28
8003eb6: 021b lsls r3, r3, #8
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
8003eb8: 429a cmp r2, r3
8003eba: d116 bne.n 8003eea <HAL_RCC_OscConfig+0x60a>
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) ||
8003ebc: 697a ldr r2, [r7, #20]
8003ebe: 23f8 movs r3, #248 ; 0xf8
8003ec0: 039b lsls r3, r3, #14
8003ec2: 401a ands r2, r3
8003ec4: 687b ldr r3, [r7, #4]
8003ec6: 6adb ldr r3, [r3, #44] ; 0x2c
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
8003ec8: 429a cmp r2, r3
8003eca: d10e bne.n 8003eea <HAL_RCC_OscConfig+0x60a>
#if defined (RCC_PLLQ_SUPPORT)
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ) ||
8003ecc: 697a ldr r2, [r7, #20]
8003ece: 23e0 movs r3, #224 ; 0xe0
8003ed0: 051b lsls r3, r3, #20
8003ed2: 401a ands r2, r3
8003ed4: 687b ldr r3, [r7, #4]
8003ed6: 6b1b ldr r3, [r3, #48] ; 0x30
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) ||
8003ed8: 429a cmp r2, r3
8003eda: d106 bne.n 8003eea <HAL_RCC_OscConfig+0x60a>
#endif /* RCC_PLLQ_SUPPORT */
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLR) != RCC_OscInitStruct->PLL.PLLR))
8003edc: 697b ldr r3, [r7, #20]
8003ede: 0f5b lsrs r3, r3, #29
8003ee0: 075a lsls r2, r3, #29
8003ee2: 687b ldr r3, [r7, #4]
8003ee4: 6b5b ldr r3, [r3, #52] ; 0x34
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ) ||
8003ee6: 429a cmp r2, r3
8003ee8: d001 beq.n 8003eee <HAL_RCC_OscConfig+0x60e>
{
return HAL_ERROR;
8003eea: 2301 movs r3, #1
8003eec: e000 b.n 8003ef0 <HAL_RCC_OscConfig+0x610>
}
}
}
}
return HAL_OK;
8003eee: 2300 movs r3, #0
}
8003ef0: 0018 movs r0, r3
8003ef2: 46bd mov sp, r7
8003ef4: b008 add sp, #32
8003ef6: bd80 pop {r7, pc}
8003ef8: 40021000 .word 0x40021000
8003efc: 40007000 .word 0x40007000
8003f00: 00001388 .word 0x00001388
8003f04: efffffff .word 0xefffffff
8003f08: feffffff .word 0xfeffffff
8003f0c: 11c1808c .word 0x11c1808c
8003f10: eefefffc .word 0xeefefffc
08003f14 <HAL_RCC_ClockConfig>:
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
* (for more details refer to section above "Initialization/de-initialization functions")
* @retval None
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
8003f14: b580 push {r7, lr}
8003f16: b084 sub sp, #16
8003f18: af00 add r7, sp, #0
8003f1a: 6078 str r0, [r7, #4]
8003f1c: 6039 str r1, [r7, #0]
uint32_t tickstart;
/* Check Null pointer */
if (RCC_ClkInitStruct == NULL)
8003f1e: 687b ldr r3, [r7, #4]
8003f20: 2b00 cmp r3, #0
8003f22: d101 bne.n 8003f28 <HAL_RCC_ClockConfig+0x14>
{
return HAL_ERROR;
8003f24: 2301 movs r3, #1
8003f26: e0e9 b.n 80040fc <HAL_RCC_ClockConfig+0x1e8>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the FLASH clock
(HCLK) and the supply voltage of the device. */
/* Increasing the number of wait states because of higher CPU frequency */
if (FLatency > __HAL_FLASH_GET_LATENCY())
8003f28: 4b76 ldr r3, [pc, #472] ; (8004104 <HAL_RCC_ClockConfig+0x1f0>)
8003f2a: 681b ldr r3, [r3, #0]
8003f2c: 2207 movs r2, #7
8003f2e: 4013 ands r3, r2
8003f30: 683a ldr r2, [r7, #0]
8003f32: 429a cmp r2, r3
8003f34: d91e bls.n 8003f74 <HAL_RCC_ClockConfig+0x60>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8003f36: 4b73 ldr r3, [pc, #460] ; (8004104 <HAL_RCC_ClockConfig+0x1f0>)
8003f38: 681b ldr r3, [r3, #0]
8003f3a: 2207 movs r2, #7
8003f3c: 4393 bics r3, r2
8003f3e: 0019 movs r1, r3
8003f40: 4b70 ldr r3, [pc, #448] ; (8004104 <HAL_RCC_ClockConfig+0x1f0>)
8003f42: 683a ldr r2, [r7, #0]
8003f44: 430a orrs r2, r1
8003f46: 601a str r2, [r3, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by polling the FLASH_ACR register */
tickstart = HAL_GetTick();
8003f48: f7fd fe0c bl 8001b64 <HAL_GetTick>
8003f4c: 0003 movs r3, r0
8003f4e: 60fb str r3, [r7, #12]
while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
8003f50: e009 b.n 8003f66 <HAL_RCC_ClockConfig+0x52>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
8003f52: f7fd fe07 bl 8001b64 <HAL_GetTick>
8003f56: 0002 movs r2, r0
8003f58: 68fb ldr r3, [r7, #12]
8003f5a: 1ad3 subs r3, r2, r3
8003f5c: 4a6a ldr r2, [pc, #424] ; (8004108 <HAL_RCC_ClockConfig+0x1f4>)
8003f5e: 4293 cmp r3, r2
8003f60: d901 bls.n 8003f66 <HAL_RCC_ClockConfig+0x52>
{
return HAL_TIMEOUT;
8003f62: 2303 movs r3, #3
8003f64: e0ca b.n 80040fc <HAL_RCC_ClockConfig+0x1e8>
while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
8003f66: 4b67 ldr r3, [pc, #412] ; (8004104 <HAL_RCC_ClockConfig+0x1f0>)
8003f68: 681b ldr r3, [r3, #0]
8003f6a: 2207 movs r2, #7
8003f6c: 4013 ands r3, r2
8003f6e: 683a ldr r2, [r7, #0]
8003f70: 429a cmp r2, r3
8003f72: d1ee bne.n 8003f52 <HAL_RCC_ClockConfig+0x3e>
}
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
8003f74: 687b ldr r3, [r7, #4]
8003f76: 681b ldr r3, [r3, #0]
8003f78: 2202 movs r2, #2
8003f7a: 4013 ands r3, r2
8003f7c: d015 beq.n 8003faa <HAL_RCC_ClockConfig+0x96>
{
/* Set the highest APB divider in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8003f7e: 687b ldr r3, [r7, #4]
8003f80: 681b ldr r3, [r3, #0]
8003f82: 2204 movs r2, #4
8003f84: 4013 ands r3, r2
8003f86: d006 beq.n 8003f96 <HAL_RCC_ClockConfig+0x82>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_HCLK_DIV16);
8003f88: 4b60 ldr r3, [pc, #384] ; (800410c <HAL_RCC_ClockConfig+0x1f8>)
8003f8a: 689a ldr r2, [r3, #8]
8003f8c: 4b5f ldr r3, [pc, #380] ; (800410c <HAL_RCC_ClockConfig+0x1f8>)
8003f8e: 21e0 movs r1, #224 ; 0xe0
8003f90: 01c9 lsls r1, r1, #7
8003f92: 430a orrs r2, r1
8003f94: 609a str r2, [r3, #8]
}
/* Set the new HCLK clock divider */
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8003f96: 4b5d ldr r3, [pc, #372] ; (800410c <HAL_RCC_ClockConfig+0x1f8>)
8003f98: 689b ldr r3, [r3, #8]
8003f9a: 4a5d ldr r2, [pc, #372] ; (8004110 <HAL_RCC_ClockConfig+0x1fc>)
8003f9c: 4013 ands r3, r2
8003f9e: 0019 movs r1, r3
8003fa0: 687b ldr r3, [r7, #4]
8003fa2: 689a ldr r2, [r3, #8]
8003fa4: 4b59 ldr r3, [pc, #356] ; (800410c <HAL_RCC_ClockConfig+0x1f8>)
8003fa6: 430a orrs r2, r1
8003fa8: 609a str r2, [r3, #8]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
8003faa: 687b ldr r3, [r7, #4]
8003fac: 681b ldr r3, [r3, #0]
8003fae: 2201 movs r2, #1
8003fb0: 4013 ands r3, r2
8003fb2: d057 beq.n 8004064 <HAL_RCC_ClockConfig+0x150>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
8003fb4: 687b ldr r3, [r7, #4]
8003fb6: 685b ldr r3, [r3, #4]
8003fb8: 2b01 cmp r3, #1
8003fba: d107 bne.n 8003fcc <HAL_RCC_ClockConfig+0xb8>
{
/* Check the HSE ready flag */
if (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
8003fbc: 4b53 ldr r3, [pc, #332] ; (800410c <HAL_RCC_ClockConfig+0x1f8>)
8003fbe: 681a ldr r2, [r3, #0]
8003fc0: 2380 movs r3, #128 ; 0x80
8003fc2: 029b lsls r3, r3, #10
8003fc4: 4013 ands r3, r2
8003fc6: d12b bne.n 8004020 <HAL_RCC_ClockConfig+0x10c>
{
return HAL_ERROR;
8003fc8: 2301 movs r3, #1
8003fca: e097 b.n 80040fc <HAL_RCC_ClockConfig+0x1e8>
}
}
/* PLL is selected as System Clock Source */
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
8003fcc: 687b ldr r3, [r7, #4]
8003fce: 685b ldr r3, [r3, #4]
8003fd0: 2b02 cmp r3, #2
8003fd2: d107 bne.n 8003fe4 <HAL_RCC_ClockConfig+0xd0>
{
/* Check the PLL ready flag */
if (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
8003fd4: 4b4d ldr r3, [pc, #308] ; (800410c <HAL_RCC_ClockConfig+0x1f8>)
8003fd6: 681a ldr r2, [r3, #0]
8003fd8: 2380 movs r3, #128 ; 0x80
8003fda: 049b lsls r3, r3, #18
8003fdc: 4013 ands r3, r2
8003fde: d11f bne.n 8004020 <HAL_RCC_ClockConfig+0x10c>
{
return HAL_ERROR;
8003fe0: 2301 movs r3, #1
8003fe2: e08b b.n 80040fc <HAL_RCC_ClockConfig+0x1e8>
}
}
/* HSI is selected as System Clock Source */
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)
8003fe4: 687b ldr r3, [r7, #4]
8003fe6: 685b ldr r3, [r3, #4]
8003fe8: 2b00 cmp r3, #0
8003fea: d107 bne.n 8003ffc <HAL_RCC_ClockConfig+0xe8>
{
/* Check the HSI ready flag */
if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
8003fec: 4b47 ldr r3, [pc, #284] ; (800410c <HAL_RCC_ClockConfig+0x1f8>)
8003fee: 681a ldr r2, [r3, #0]
8003ff0: 2380 movs r3, #128 ; 0x80
8003ff2: 00db lsls r3, r3, #3
8003ff4: 4013 ands r3, r2
8003ff6: d113 bne.n 8004020 <HAL_RCC_ClockConfig+0x10c>
{
return HAL_ERROR;
8003ff8: 2301 movs r3, #1
8003ffa: e07f b.n 80040fc <HAL_RCC_ClockConfig+0x1e8>
}
}
/* LSI is selected as System Clock Source */
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_LSI)
8003ffc: 687b ldr r3, [r7, #4]
8003ffe: 685b ldr r3, [r3, #4]
8004000: 2b03 cmp r3, #3
8004002: d106 bne.n 8004012 <HAL_RCC_ClockConfig+0xfe>
{
/* Check the LSI ready flag */
if (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
8004004: 4b41 ldr r3, [pc, #260] ; (800410c <HAL_RCC_ClockConfig+0x1f8>)
8004006: 6e1b ldr r3, [r3, #96] ; 0x60
8004008: 2202 movs r2, #2
800400a: 4013 ands r3, r2
800400c: d108 bne.n 8004020 <HAL_RCC_ClockConfig+0x10c>
{
return HAL_ERROR;
800400e: 2301 movs r3, #1
8004010: e074 b.n 80040fc <HAL_RCC_ClockConfig+0x1e8>
}
/* LSE is selected as System Clock Source */
else
{
/* Check the LSE ready flag */
if (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
8004012: 4b3e ldr r3, [pc, #248] ; (800410c <HAL_RCC_ClockConfig+0x1f8>)
8004014: 6ddb ldr r3, [r3, #92] ; 0x5c
8004016: 2202 movs r2, #2
8004018: 4013 ands r3, r2
800401a: d101 bne.n 8004020 <HAL_RCC_ClockConfig+0x10c>
{
return HAL_ERROR;
800401c: 2301 movs r3, #1
800401e: e06d b.n 80040fc <HAL_RCC_ClockConfig+0x1e8>
}
}
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
8004020: 4b3a ldr r3, [pc, #232] ; (800410c <HAL_RCC_ClockConfig+0x1f8>)
8004022: 689b ldr r3, [r3, #8]
8004024: 2207 movs r2, #7
8004026: 4393 bics r3, r2
8004028: 0019 movs r1, r3
800402a: 687b ldr r3, [r7, #4]
800402c: 685a ldr r2, [r3, #4]
800402e: 4b37 ldr r3, [pc, #220] ; (800410c <HAL_RCC_ClockConfig+0x1f8>)
8004030: 430a orrs r2, r1
8004032: 609a str r2, [r3, #8]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8004034: f7fd fd96 bl 8001b64 <HAL_GetTick>
8004038: 0003 movs r3, r0
800403a: 60fb str r3, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
800403c: e009 b.n 8004052 <HAL_RCC_ClockConfig+0x13e>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
800403e: f7fd fd91 bl 8001b64 <HAL_GetTick>
8004042: 0002 movs r2, r0
8004044: 68fb ldr r3, [r7, #12]
8004046: 1ad3 subs r3, r2, r3
8004048: 4a2f ldr r2, [pc, #188] ; (8004108 <HAL_RCC_ClockConfig+0x1f4>)
800404a: 4293 cmp r3, r2
800404c: d901 bls.n 8004052 <HAL_RCC_ClockConfig+0x13e>
{
return HAL_TIMEOUT;
800404e: 2303 movs r3, #3
8004050: e054 b.n 80040fc <HAL_RCC_ClockConfig+0x1e8>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8004052: 4b2e ldr r3, [pc, #184] ; (800410c <HAL_RCC_ClockConfig+0x1f8>)
8004054: 689b ldr r3, [r3, #8]
8004056: 2238 movs r2, #56 ; 0x38
8004058: 401a ands r2, r3
800405a: 687b ldr r3, [r7, #4]
800405c: 685b ldr r3, [r3, #4]
800405e: 00db lsls r3, r3, #3
8004060: 429a cmp r2, r3
8004062: d1ec bne.n 800403e <HAL_RCC_ClockConfig+0x12a>
}
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if (FLatency < __HAL_FLASH_GET_LATENCY())
8004064: 4b27 ldr r3, [pc, #156] ; (8004104 <HAL_RCC_ClockConfig+0x1f0>)
8004066: 681b ldr r3, [r3, #0]
8004068: 2207 movs r2, #7
800406a: 4013 ands r3, r2
800406c: 683a ldr r2, [r7, #0]
800406e: 429a cmp r2, r3
8004070: d21e bcs.n 80040b0 <HAL_RCC_ClockConfig+0x19c>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8004072: 4b24 ldr r3, [pc, #144] ; (8004104 <HAL_RCC_ClockConfig+0x1f0>)
8004074: 681b ldr r3, [r3, #0]
8004076: 2207 movs r2, #7
8004078: 4393 bics r3, r2
800407a: 0019 movs r1, r3
800407c: 4b21 ldr r3, [pc, #132] ; (8004104 <HAL_RCC_ClockConfig+0x1f0>)
800407e: 683a ldr r2, [r7, #0]
8004080: 430a orrs r2, r1
8004082: 601a str r2, [r3, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by polling the FLASH_ACR register */
tickstart = HAL_GetTick();
8004084: f7fd fd6e bl 8001b64 <HAL_GetTick>
8004088: 0003 movs r3, r0
800408a: 60fb str r3, [r7, #12]
while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
800408c: e009 b.n 80040a2 <HAL_RCC_ClockConfig+0x18e>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
800408e: f7fd fd69 bl 8001b64 <HAL_GetTick>
8004092: 0002 movs r2, r0
8004094: 68fb ldr r3, [r7, #12]
8004096: 1ad3 subs r3, r2, r3
8004098: 4a1b ldr r2, [pc, #108] ; (8004108 <HAL_RCC_ClockConfig+0x1f4>)
800409a: 4293 cmp r3, r2
800409c: d901 bls.n 80040a2 <HAL_RCC_ClockConfig+0x18e>
{
return HAL_TIMEOUT;
800409e: 2303 movs r3, #3
80040a0: e02c b.n 80040fc <HAL_RCC_ClockConfig+0x1e8>
while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
80040a2: 4b18 ldr r3, [pc, #96] ; (8004104 <HAL_RCC_ClockConfig+0x1f0>)
80040a4: 681b ldr r3, [r3, #0]
80040a6: 2207 movs r2, #7
80040a8: 4013 ands r3, r2
80040aa: 683a ldr r2, [r7, #0]
80040ac: 429a cmp r2, r3
80040ae: d1ee bne.n 800408e <HAL_RCC_ClockConfig+0x17a>
}
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
80040b0: 687b ldr r3, [r7, #4]
80040b2: 681b ldr r3, [r3, #0]
80040b4: 2204 movs r2, #4
80040b6: 4013 ands r3, r2
80040b8: d009 beq.n 80040ce <HAL_RCC_ClockConfig+0x1ba>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider);
80040ba: 4b14 ldr r3, [pc, #80] ; (800410c <HAL_RCC_ClockConfig+0x1f8>)
80040bc: 689b ldr r3, [r3, #8]
80040be: 4a15 ldr r2, [pc, #84] ; (8004114 <HAL_RCC_ClockConfig+0x200>)
80040c0: 4013 ands r3, r2
80040c2: 0019 movs r1, r3
80040c4: 687b ldr r3, [r7, #4]
80040c6: 68da ldr r2, [r3, #12]
80040c8: 4b10 ldr r3, [pc, #64] ; (800410c <HAL_RCC_ClockConfig+0x1f8>)
80040ca: 430a orrs r2, r1
80040cc: 609a str r2, [r3, #8]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]) & 0x1FU));
80040ce: f000 f829 bl 8004124 <HAL_RCC_GetSysClockFreq>
80040d2: 0001 movs r1, r0
80040d4: 4b0d ldr r3, [pc, #52] ; (800410c <HAL_RCC_ClockConfig+0x1f8>)
80040d6: 689b ldr r3, [r3, #8]
80040d8: 0a1b lsrs r3, r3, #8
80040da: 220f movs r2, #15
80040dc: 401a ands r2, r3
80040de: 4b0e ldr r3, [pc, #56] ; (8004118 <HAL_RCC_ClockConfig+0x204>)
80040e0: 0092 lsls r2, r2, #2
80040e2: 58d3 ldr r3, [r2, r3]
80040e4: 221f movs r2, #31
80040e6: 4013 ands r3, r2
80040e8: 000a movs r2, r1
80040ea: 40da lsrs r2, r3
80040ec: 4b0b ldr r3, [pc, #44] ; (800411c <HAL_RCC_ClockConfig+0x208>)
80040ee: 601a str r2, [r3, #0]
/* Configure the source of time base considering new system clocks settings*/
return HAL_InitTick(uwTickPrio);
80040f0: 4b0b ldr r3, [pc, #44] ; (8004120 <HAL_RCC_ClockConfig+0x20c>)
80040f2: 681b ldr r3, [r3, #0]
80040f4: 0018 movs r0, r3
80040f6: f7fd fcd9 bl 8001aac <HAL_InitTick>
80040fa: 0003 movs r3, r0
}
80040fc: 0018 movs r0, r3
80040fe: 46bd mov sp, r7
8004100: b004 add sp, #16
8004102: bd80 pop {r7, pc}
8004104: 40022000 .word 0x40022000
8004108: 00001388 .word 0x00001388
800410c: 40021000 .word 0x40021000
8004110: fffff0ff .word 0xfffff0ff
8004114: ffff8fff .word 0xffff8fff
8004118: 080073e8 .word 0x080073e8
800411c: 2000000c .word 0x2000000c
8004120: 20000010 .word 0x20000010
08004124 <HAL_RCC_GetSysClockFreq>:
*
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
8004124: b580 push {r7, lr}
8004126: b086 sub sp, #24
8004128: af00 add r7, sp, #0
uint32_t pllvco, pllsource, pllr, pllm, hsidiv;
uint32_t sysclockfreq;
if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
800412a: 4b3c ldr r3, [pc, #240] ; (800421c <HAL_RCC_GetSysClockFreq+0xf8>)
800412c: 689b ldr r3, [r3, #8]
800412e: 2238 movs r2, #56 ; 0x38
8004130: 4013 ands r3, r2
8004132: d10f bne.n 8004154 <HAL_RCC_GetSysClockFreq+0x30>
{
/* HSISYS can be derived for HSI16 */
hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos));
8004134: 4b39 ldr r3, [pc, #228] ; (800421c <HAL_RCC_GetSysClockFreq+0xf8>)
8004136: 681b ldr r3, [r3, #0]
8004138: 0adb lsrs r3, r3, #11
800413a: 2207 movs r2, #7
800413c: 4013 ands r3, r2
800413e: 2201 movs r2, #1
8004140: 409a lsls r2, r3
8004142: 0013 movs r3, r2
8004144: 603b str r3, [r7, #0]
/* HSI used as system clock source */
sysclockfreq = (HSI_VALUE / hsidiv);
8004146: 6839 ldr r1, [r7, #0]
8004148: 4835 ldr r0, [pc, #212] ; (8004220 <HAL_RCC_GetSysClockFreq+0xfc>)
800414a: f7fb ffdb bl 8000104 <__udivsi3>
800414e: 0003 movs r3, r0
8004150: 613b str r3, [r7, #16]
8004152: e05d b.n 8004210 <HAL_RCC_GetSysClockFreq+0xec>
}
else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
8004154: 4b31 ldr r3, [pc, #196] ; (800421c <HAL_RCC_GetSysClockFreq+0xf8>)
8004156: 689b ldr r3, [r3, #8]
8004158: 2238 movs r2, #56 ; 0x38
800415a: 4013 ands r3, r2
800415c: 2b08 cmp r3, #8
800415e: d102 bne.n 8004166 <HAL_RCC_GetSysClockFreq+0x42>
{
/* HSE used as system clock source */
sysclockfreq = HSE_VALUE;
8004160: 4b30 ldr r3, [pc, #192] ; (8004224 <HAL_RCC_GetSysClockFreq+0x100>)
8004162: 613b str r3, [r7, #16]
8004164: e054 b.n 8004210 <HAL_RCC_GetSysClockFreq+0xec>
}
else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK)
8004166: 4b2d ldr r3, [pc, #180] ; (800421c <HAL_RCC_GetSysClockFreq+0xf8>)
8004168: 689b ldr r3, [r3, #8]
800416a: 2238 movs r2, #56 ; 0x38
800416c: 4013 ands r3, r2
800416e: 2b10 cmp r3, #16
8004170: d138 bne.n 80041e4 <HAL_RCC_GetSysClockFreq+0xc0>
/* PLL used as system clock source */
/* PLL_VCO = ((HSE_VALUE or HSI_VALUE)/ PLLM) * PLLN
SYSCLK = PLL_VCO / PLLR
*/
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
8004172: 4b2a ldr r3, [pc, #168] ; (800421c <HAL_RCC_GetSysClockFreq+0xf8>)
8004174: 68db ldr r3, [r3, #12]
8004176: 2203 movs r2, #3
8004178: 4013 ands r3, r2
800417a: 60fb str r3, [r7, #12]
pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
800417c: 4b27 ldr r3, [pc, #156] ; (800421c <HAL_RCC_GetSysClockFreq+0xf8>)
800417e: 68db ldr r3, [r3, #12]
8004180: 091b lsrs r3, r3, #4
8004182: 2207 movs r2, #7
8004184: 4013 ands r3, r2
8004186: 3301 adds r3, #1
8004188: 60bb str r3, [r7, #8]
switch (pllsource)
800418a: 68fb ldr r3, [r7, #12]
800418c: 2b03 cmp r3, #3
800418e: d10d bne.n 80041ac <HAL_RCC_GetSysClockFreq+0x88>
{
case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
8004190: 68b9 ldr r1, [r7, #8]
8004192: 4824 ldr r0, [pc, #144] ; (8004224 <HAL_RCC_GetSysClockFreq+0x100>)
8004194: f7fb ffb6 bl 8000104 <__udivsi3>
8004198: 0003 movs r3, r0
800419a: 0019 movs r1, r3
800419c: 4b1f ldr r3, [pc, #124] ; (800421c <HAL_RCC_GetSysClockFreq+0xf8>)
800419e: 68db ldr r3, [r3, #12]
80041a0: 0a1b lsrs r3, r3, #8
80041a2: 227f movs r2, #127 ; 0x7f
80041a4: 4013 ands r3, r2
80041a6: 434b muls r3, r1
80041a8: 617b str r3, [r7, #20]
break;
80041aa: e00d b.n 80041c8 <HAL_RCC_GetSysClockFreq+0xa4>
case RCC_PLLSOURCE_HSI: /* HSI16 used as PLL clock source */
default: /* HSI16 used as PLL clock source */
pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos) ;
80041ac: 68b9 ldr r1, [r7, #8]
80041ae: 481c ldr r0, [pc, #112] ; (8004220 <HAL_RCC_GetSysClockFreq+0xfc>)
80041b0: f7fb ffa8 bl 8000104 <__udivsi3>
80041b4: 0003 movs r3, r0
80041b6: 0019 movs r1, r3
80041b8: 4b18 ldr r3, [pc, #96] ; (800421c <HAL_RCC_GetSysClockFreq+0xf8>)
80041ba: 68db ldr r3, [r3, #12]
80041bc: 0a1b lsrs r3, r3, #8
80041be: 227f movs r2, #127 ; 0x7f
80041c0: 4013 ands r3, r2
80041c2: 434b muls r3, r1
80041c4: 617b str r3, [r7, #20]
break;
80041c6: 46c0 nop ; (mov r8, r8)
}
pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U);
80041c8: 4b14 ldr r3, [pc, #80] ; (800421c <HAL_RCC_GetSysClockFreq+0xf8>)
80041ca: 68db ldr r3, [r3, #12]
80041cc: 0f5b lsrs r3, r3, #29
80041ce: 2207 movs r2, #7
80041d0: 4013 ands r3, r2
80041d2: 3301 adds r3, #1
80041d4: 607b str r3, [r7, #4]
sysclockfreq = pllvco / pllr;
80041d6: 6879 ldr r1, [r7, #4]
80041d8: 6978 ldr r0, [r7, #20]
80041da: f7fb ff93 bl 8000104 <__udivsi3>
80041de: 0003 movs r3, r0
80041e0: 613b str r3, [r7, #16]
80041e2: e015 b.n 8004210 <HAL_RCC_GetSysClockFreq+0xec>
}
else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSE)
80041e4: 4b0d ldr r3, [pc, #52] ; (800421c <HAL_RCC_GetSysClockFreq+0xf8>)
80041e6: 689b ldr r3, [r3, #8]
80041e8: 2238 movs r2, #56 ; 0x38
80041ea: 4013 ands r3, r2
80041ec: 2b20 cmp r3, #32
80041ee: d103 bne.n 80041f8 <HAL_RCC_GetSysClockFreq+0xd4>
{
/* LSE used as system clock source */
sysclockfreq = LSE_VALUE;
80041f0: 2380 movs r3, #128 ; 0x80
80041f2: 021b lsls r3, r3, #8
80041f4: 613b str r3, [r7, #16]
80041f6: e00b b.n 8004210 <HAL_RCC_GetSysClockFreq+0xec>
}
else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSI)
80041f8: 4b08 ldr r3, [pc, #32] ; (800421c <HAL_RCC_GetSysClockFreq+0xf8>)
80041fa: 689b ldr r3, [r3, #8]
80041fc: 2238 movs r2, #56 ; 0x38
80041fe: 4013 ands r3, r2
8004200: 2b18 cmp r3, #24
8004202: d103 bne.n 800420c <HAL_RCC_GetSysClockFreq+0xe8>
{
/* LSI used as system clock source */
sysclockfreq = LSI_VALUE;
8004204: 23fa movs r3, #250 ; 0xfa
8004206: 01db lsls r3, r3, #7
8004208: 613b str r3, [r7, #16]
800420a: e001 b.n 8004210 <HAL_RCC_GetSysClockFreq+0xec>
}
else
{
sysclockfreq = 0U;
800420c: 2300 movs r3, #0
800420e: 613b str r3, [r7, #16]
}
return sysclockfreq;
8004210: 693b ldr r3, [r7, #16]
}
8004212: 0018 movs r0, r3
8004214: 46bd mov sp, r7
8004216: b006 add sp, #24
8004218: bd80 pop {r7, pc}
800421a: 46c0 nop ; (mov r8, r8)
800421c: 40021000 .word 0x40021000
8004220: 00f42400 .word 0x00f42400
8004224: 007a1200 .word 0x007a1200
08004228 <HAL_RCC_GetHCLKFreq>:
*
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
* @retval HCLK frequency in Hz
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
8004228: b580 push {r7, lr}
800422a: af00 add r7, sp, #0
return SystemCoreClock;
800422c: 4b02 ldr r3, [pc, #8] ; (8004238 <HAL_RCC_GetHCLKFreq+0x10>)
800422e: 681b ldr r3, [r3, #0]
}
8004230: 0018 movs r0, r3
8004232: 46bd mov sp, r7
8004234: bd80 pop {r7, pc}
8004236: 46c0 nop ; (mov r8, r8)
8004238: 2000000c .word 0x2000000c
0800423c <HAL_RCC_GetPCLK1Freq>:
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK1 frequency in Hz
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
800423c: b5b0 push {r4, r5, r7, lr}
800423e: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return ((uint32_t)(__LL_RCC_CALC_PCLK1_FREQ(HAL_RCC_GetHCLKFreq(), LL_RCC_GetAPB1Prescaler())));
8004240: f7ff fff2 bl 8004228 <HAL_RCC_GetHCLKFreq>
8004244: 0004 movs r4, r0
8004246: f7ff fb3f bl 80038c8 <LL_RCC_GetAPB1Prescaler>
800424a: 0003 movs r3, r0
800424c: 0b1a lsrs r2, r3, #12
800424e: 4b05 ldr r3, [pc, #20] ; (8004264 <HAL_RCC_GetPCLK1Freq+0x28>)
8004250: 0092 lsls r2, r2, #2
8004252: 58d3 ldr r3, [r2, r3]
8004254: 221f movs r2, #31
8004256: 4013 ands r3, r2
8004258: 40dc lsrs r4, r3
800425a: 0023 movs r3, r4
}
800425c: 0018 movs r0, r3
800425e: 46bd mov sp, r7
8004260: bdb0 pop {r4, r5, r7, pc}
8004262: 46c0 nop ; (mov r8, r8)
8004264: 08007428 .word 0x08007428
08004268 <HAL_RCCEx_PeriphCLKConfig>:
* the RTC clock source: in this case the access to Backup domain is enabled.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
8004268: b580 push {r7, lr}
800426a: b086 sub sp, #24
800426c: af00 add r7, sp, #0
800426e: 6078 str r0, [r7, #4]
uint32_t tmpregister;
uint32_t tickstart;
HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
8004270: 2313 movs r3, #19
8004272: 18fb adds r3, r7, r3
8004274: 2200 movs r2, #0
8004276: 701a strb r2, [r3, #0]
HAL_StatusTypeDef status = HAL_OK; /* Final status */
8004278: 2312 movs r3, #18
800427a: 18fb adds r3, r7, r3
800427c: 2200 movs r2, #0
800427e: 701a strb r2, [r3, #0]
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
/*-------------------------- RTC clock source configuration ----------------------*/
if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
8004280: 687b ldr r3, [r7, #4]
8004282: 681a ldr r2, [r3, #0]
8004284: 2380 movs r3, #128 ; 0x80
8004286: 029b lsls r3, r3, #10
8004288: 4013 ands r3, r2
800428a: d100 bne.n 800428e <HAL_RCCEx_PeriphCLKConfig+0x26>
800428c: e0a3 b.n 80043d6 <HAL_RCCEx_PeriphCLKConfig+0x16e>
{
FlagStatus pwrclkchanged = RESET;
800428e: 2011 movs r0, #17
8004290: 183b adds r3, r7, r0
8004292: 2200 movs r2, #0
8004294: 701a strb r2, [r3, #0]
/* Check for RTC Parameters used to output RTCCLK */
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
/* Enable Power Clock */
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
8004296: 4ba5 ldr r3, [pc, #660] ; (800452c <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
8004298: 6bda ldr r2, [r3, #60] ; 0x3c
800429a: 2380 movs r3, #128 ; 0x80
800429c: 055b lsls r3, r3, #21
800429e: 4013 ands r3, r2
80042a0: d110 bne.n 80042c4 <HAL_RCCEx_PeriphCLKConfig+0x5c>
{
__HAL_RCC_PWR_CLK_ENABLE();
80042a2: 4ba2 ldr r3, [pc, #648] ; (800452c <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
80042a4: 6bda ldr r2, [r3, #60] ; 0x3c
80042a6: 4ba1 ldr r3, [pc, #644] ; (800452c <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
80042a8: 2180 movs r1, #128 ; 0x80
80042aa: 0549 lsls r1, r1, #21
80042ac: 430a orrs r2, r1
80042ae: 63da str r2, [r3, #60] ; 0x3c
80042b0: 4b9e ldr r3, [pc, #632] ; (800452c <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
80042b2: 6bda ldr r2, [r3, #60] ; 0x3c
80042b4: 2380 movs r3, #128 ; 0x80
80042b6: 055b lsls r3, r3, #21
80042b8: 4013 ands r3, r2
80042ba: 60bb str r3, [r7, #8]
80042bc: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
80042be: 183b adds r3, r7, r0
80042c0: 2201 movs r2, #1
80042c2: 701a strb r2, [r3, #0]
}
/* Enable write access to Backup domain */
SET_BIT(PWR->CR1, PWR_CR1_DBP);
80042c4: 4b9a ldr r3, [pc, #616] ; (8004530 <HAL_RCCEx_PeriphCLKConfig+0x2c8>)
80042c6: 681a ldr r2, [r3, #0]
80042c8: 4b99 ldr r3, [pc, #612] ; (8004530 <HAL_RCCEx_PeriphCLKConfig+0x2c8>)
80042ca: 2180 movs r1, #128 ; 0x80
80042cc: 0049 lsls r1, r1, #1
80042ce: 430a orrs r2, r1
80042d0: 601a str r2, [r3, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
80042d2: f7fd fc47 bl 8001b64 <HAL_GetTick>
80042d6: 0003 movs r3, r0
80042d8: 60fb str r3, [r7, #12]
while ((PWR->CR1 & PWR_CR1_DBP) == 0U)
80042da: e00b b.n 80042f4 <HAL_RCCEx_PeriphCLKConfig+0x8c>
{
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
80042dc: f7fd fc42 bl 8001b64 <HAL_GetTick>
80042e0: 0002 movs r2, r0
80042e2: 68fb ldr r3, [r7, #12]
80042e4: 1ad3 subs r3, r2, r3
80042e6: 2b02 cmp r3, #2
80042e8: d904 bls.n 80042f4 <HAL_RCCEx_PeriphCLKConfig+0x8c>
{
ret = HAL_TIMEOUT;
80042ea: 2313 movs r3, #19
80042ec: 18fb adds r3, r7, r3
80042ee: 2203 movs r2, #3
80042f0: 701a strb r2, [r3, #0]
break;
80042f2: e005 b.n 8004300 <HAL_RCCEx_PeriphCLKConfig+0x98>
while ((PWR->CR1 & PWR_CR1_DBP) == 0U)
80042f4: 4b8e ldr r3, [pc, #568] ; (8004530 <HAL_RCCEx_PeriphCLKConfig+0x2c8>)
80042f6: 681a ldr r2, [r3, #0]
80042f8: 2380 movs r3, #128 ; 0x80
80042fa: 005b lsls r3, r3, #1
80042fc: 4013 ands r3, r2
80042fe: d0ed beq.n 80042dc <HAL_RCCEx_PeriphCLKConfig+0x74>
}
}
if (ret == HAL_OK)
8004300: 2313 movs r3, #19
8004302: 18fb adds r3, r7, r3
8004304: 781b ldrb r3, [r3, #0]
8004306: 2b00 cmp r3, #0
8004308: d154 bne.n 80043b4 <HAL_RCCEx_PeriphCLKConfig+0x14c>
{
/* Reset the Backup domain only if the RTC Clock source selection is modified from default */
tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL);
800430a: 4b88 ldr r3, [pc, #544] ; (800452c <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
800430c: 6dda ldr r2, [r3, #92] ; 0x5c
800430e: 23c0 movs r3, #192 ; 0xc0
8004310: 009b lsls r3, r3, #2
8004312: 4013 ands r3, r2
8004314: 617b str r3, [r7, #20]
/* Reset the Backup domain only if the RTC Clock source selection is modified */
if ((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection))
8004316: 697b ldr r3, [r7, #20]
8004318: 2b00 cmp r3, #0
800431a: d019 beq.n 8004350 <HAL_RCCEx_PeriphCLKConfig+0xe8>
800431c: 687b ldr r3, [r7, #4]
800431e: 6a5b ldr r3, [r3, #36] ; 0x24
8004320: 697a ldr r2, [r7, #20]
8004322: 429a cmp r2, r3
8004324: d014 beq.n 8004350 <HAL_RCCEx_PeriphCLKConfig+0xe8>
{
/* Store the content of BDCR register before the reset of Backup Domain */
tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
8004326: 4b81 ldr r3, [pc, #516] ; (800452c <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
8004328: 6ddb ldr r3, [r3, #92] ; 0x5c
800432a: 4a82 ldr r2, [pc, #520] ; (8004534 <HAL_RCCEx_PeriphCLKConfig+0x2cc>)
800432c: 4013 ands r3, r2
800432e: 617b str r3, [r7, #20]
/* RTC Clock selection can be changed only if the Backup Domain is reset */
__HAL_RCC_BACKUPRESET_FORCE();
8004330: 4b7e ldr r3, [pc, #504] ; (800452c <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
8004332: 6dda ldr r2, [r3, #92] ; 0x5c
8004334: 4b7d ldr r3, [pc, #500] ; (800452c <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
8004336: 2180 movs r1, #128 ; 0x80
8004338: 0249 lsls r1, r1, #9
800433a: 430a orrs r2, r1
800433c: 65da str r2, [r3, #92] ; 0x5c
__HAL_RCC_BACKUPRESET_RELEASE();
800433e: 4b7b ldr r3, [pc, #492] ; (800452c <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
8004340: 6dda ldr r2, [r3, #92] ; 0x5c
8004342: 4b7a ldr r3, [pc, #488] ; (800452c <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
8004344: 497c ldr r1, [pc, #496] ; (8004538 <HAL_RCCEx_PeriphCLKConfig+0x2d0>)
8004346: 400a ands r2, r1
8004348: 65da str r2, [r3, #92] ; 0x5c
/* Restore the Content of BDCR register */
RCC->BDCR = tmpregister;
800434a: 4b78 ldr r3, [pc, #480] ; (800452c <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
800434c: 697a ldr r2, [r7, #20]
800434e: 65da str r2, [r3, #92] ; 0x5c
}
/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON))
8004350: 697b ldr r3, [r7, #20]
8004352: 2201 movs r2, #1
8004354: 4013 ands r3, r2
8004356: d016 beq.n 8004386 <HAL_RCCEx_PeriphCLKConfig+0x11e>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8004358: f7fd fc04 bl 8001b64 <HAL_GetTick>
800435c: 0003 movs r3, r0
800435e: 60fb str r3, [r7, #12]
/* Wait till LSE is ready */
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
8004360: e00c b.n 800437c <HAL_RCCEx_PeriphCLKConfig+0x114>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8004362: f7fd fbff bl 8001b64 <HAL_GetTick>
8004366: 0002 movs r2, r0
8004368: 68fb ldr r3, [r7, #12]
800436a: 1ad3 subs r3, r2, r3
800436c: 4a73 ldr r2, [pc, #460] ; (800453c <HAL_RCCEx_PeriphCLKConfig+0x2d4>)
800436e: 4293 cmp r3, r2
8004370: d904 bls.n 800437c <HAL_RCCEx_PeriphCLKConfig+0x114>
{
ret = HAL_TIMEOUT;
8004372: 2313 movs r3, #19
8004374: 18fb adds r3, r7, r3
8004376: 2203 movs r2, #3
8004378: 701a strb r2, [r3, #0]
break;
800437a: e004 b.n 8004386 <HAL_RCCEx_PeriphCLKConfig+0x11e>
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
800437c: 4b6b ldr r3, [pc, #428] ; (800452c <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
800437e: 6ddb ldr r3, [r3, #92] ; 0x5c
8004380: 2202 movs r2, #2
8004382: 4013 ands r3, r2
8004384: d0ed beq.n 8004362 <HAL_RCCEx_PeriphCLKConfig+0xfa>
}
}
}
if (ret == HAL_OK)
8004386: 2313 movs r3, #19
8004388: 18fb adds r3, r7, r3
800438a: 781b ldrb r3, [r3, #0]
800438c: 2b00 cmp r3, #0
800438e: d10a bne.n 80043a6 <HAL_RCCEx_PeriphCLKConfig+0x13e>
{
/* Apply new RTC clock source selection */
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
8004390: 4b66 ldr r3, [pc, #408] ; (800452c <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
8004392: 6ddb ldr r3, [r3, #92] ; 0x5c
8004394: 4a67 ldr r2, [pc, #412] ; (8004534 <HAL_RCCEx_PeriphCLKConfig+0x2cc>)
8004396: 4013 ands r3, r2
8004398: 0019 movs r1, r3
800439a: 687b ldr r3, [r7, #4]
800439c: 6a5a ldr r2, [r3, #36] ; 0x24
800439e: 4b63 ldr r3, [pc, #396] ; (800452c <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
80043a0: 430a orrs r2, r1
80043a2: 65da str r2, [r3, #92] ; 0x5c
80043a4: e00c b.n 80043c0 <HAL_RCCEx_PeriphCLKConfig+0x158>
}
else
{
/* set overall return value */
status = ret;
80043a6: 2312 movs r3, #18
80043a8: 18fb adds r3, r7, r3
80043aa: 2213 movs r2, #19
80043ac: 18ba adds r2, r7, r2
80043ae: 7812 ldrb r2, [r2, #0]
80043b0: 701a strb r2, [r3, #0]
80043b2: e005 b.n 80043c0 <HAL_RCCEx_PeriphCLKConfig+0x158>
}
}
else
{
/* set overall return value */
status = ret;
80043b4: 2312 movs r3, #18
80043b6: 18fb adds r3, r7, r3
80043b8: 2213 movs r2, #19
80043ba: 18ba adds r2, r7, r2
80043bc: 7812 ldrb r2, [r2, #0]
80043be: 701a strb r2, [r3, #0]
}
/* Restore clock configuration if changed */
if (pwrclkchanged == SET)
80043c0: 2311 movs r3, #17
80043c2: 18fb adds r3, r7, r3
80043c4: 781b ldrb r3, [r3, #0]
80043c6: 2b01 cmp r3, #1
80043c8: d105 bne.n 80043d6 <HAL_RCCEx_PeriphCLKConfig+0x16e>
{
__HAL_RCC_PWR_CLK_DISABLE();
80043ca: 4b58 ldr r3, [pc, #352] ; (800452c <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
80043cc: 6bda ldr r2, [r3, #60] ; 0x3c
80043ce: 4b57 ldr r3, [pc, #348] ; (800452c <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
80043d0: 495b ldr r1, [pc, #364] ; (8004540 <HAL_RCCEx_PeriphCLKConfig+0x2d8>)
80043d2: 400a ands r2, r1
80043d4: 63da str r2, [r3, #60] ; 0x3c
}
}
/*-------------------------- USART1 clock source configuration -------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
80043d6: 687b ldr r3, [r7, #4]
80043d8: 681b ldr r3, [r3, #0]
80043da: 2201 movs r2, #1
80043dc: 4013 ands r3, r2
80043de: d009 beq.n 80043f4 <HAL_RCCEx_PeriphCLKConfig+0x18c>
{
/* Check the parameters */
assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
/* Configure the USART1 clock source */
__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
80043e0: 4b52 ldr r3, [pc, #328] ; (800452c <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
80043e2: 6d5b ldr r3, [r3, #84] ; 0x54
80043e4: 2203 movs r2, #3
80043e6: 4393 bics r3, r2
80043e8: 0019 movs r1, r3
80043ea: 687b ldr r3, [r7, #4]
80043ec: 685a ldr r2, [r3, #4]
80043ee: 4b4f ldr r3, [pc, #316] ; (800452c <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
80043f0: 430a orrs r2, r1
80043f2: 655a str r2, [r3, #84] ; 0x54
}
#endif /* RCC_CCIPR_USART3SEL */
#if defined(LPUART1)
/*-------------------------- LPUART1 clock source configuration ------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
80043f4: 687b ldr r3, [r7, #4]
80043f6: 681b ldr r3, [r3, #0]
80043f8: 2210 movs r2, #16
80043fa: 4013 ands r3, r2
80043fc: d009 beq.n 8004412 <HAL_RCCEx_PeriphCLKConfig+0x1aa>
{
/* Check the parameters */
assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));
/* Configure the LPUART1 clock source */
__HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
80043fe: 4b4b ldr r3, [pc, #300] ; (800452c <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
8004400: 6d5b ldr r3, [r3, #84] ; 0x54
8004402: 4a50 ldr r2, [pc, #320] ; (8004544 <HAL_RCCEx_PeriphCLKConfig+0x2dc>)
8004404: 4013 ands r3, r2
8004406: 0019 movs r1, r3
8004408: 687b ldr r3, [r7, #4]
800440a: 689a ldr r2, [r3, #8]
800440c: 4b47 ldr r3, [pc, #284] ; (800452c <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
800440e: 430a orrs r2, r1
8004410: 655a str r2, [r3, #84] ; 0x54
}
#endif /* LPUART2 */
#if defined(RCC_CCIPR_LPTIM1SEL)
/*-------------------------- LPTIM1 clock source configuration -------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1))
8004412: 687b ldr r3, [r7, #4]
8004414: 681a ldr r2, [r3, #0]
8004416: 2380 movs r3, #128 ; 0x80
8004418: 009b lsls r3, r3, #2
800441a: 4013 ands r3, r2
800441c: d009 beq.n 8004432 <HAL_RCCEx_PeriphCLKConfig+0x1ca>
{
assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection));
__HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
800441e: 4b43 ldr r3, [pc, #268] ; (800452c <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
8004420: 6d5b ldr r3, [r3, #84] ; 0x54
8004422: 4a49 ldr r2, [pc, #292] ; (8004548 <HAL_RCCEx_PeriphCLKConfig+0x2e0>)
8004424: 4013 ands r3, r2
8004426: 0019 movs r1, r3
8004428: 687b ldr r3, [r7, #4]
800442a: 695a ldr r2, [r3, #20]
800442c: 4b3f ldr r3, [pc, #252] ; (800452c <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
800442e: 430a orrs r2, r1
8004430: 655a str r2, [r3, #84] ; 0x54
}
#endif /* RCC_CCIPR_LPTIM1SEL */
#if defined(RCC_CCIPR_LPTIM2SEL)
/*-------------------------- LPTIM2 clock source configuration -------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2))
8004432: 687b ldr r3, [r7, #4]
8004434: 681a ldr r2, [r3, #0]
8004436: 2380 movs r3, #128 ; 0x80
8004438: 00db lsls r3, r3, #3
800443a: 4013 ands r3, r2
800443c: d009 beq.n 8004452 <HAL_RCCEx_PeriphCLKConfig+0x1ea>
{
assert_param(IS_RCC_LPTIM2CLKSOURCE(PeriphClkInit->Lptim2ClockSelection));
__HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);
800443e: 4b3b ldr r3, [pc, #236] ; (800452c <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
8004440: 6d5b ldr r3, [r3, #84] ; 0x54
8004442: 4a42 ldr r2, [pc, #264] ; (800454c <HAL_RCCEx_PeriphCLKConfig+0x2e4>)
8004444: 4013 ands r3, r2
8004446: 0019 movs r1, r3
8004448: 687b ldr r3, [r7, #4]
800444a: 699a ldr r2, [r3, #24]
800444c: 4b37 ldr r3, [pc, #220] ; (800452c <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
800444e: 430a orrs r2, r1
8004450: 655a str r2, [r3, #84] ; 0x54
}
#endif /* RCC_CCIPR_LPTIM2SEL */
/*-------------------------- I2C1 clock source configuration ---------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
8004452: 687b ldr r3, [r7, #4]
8004454: 681b ldr r3, [r3, #0]
8004456: 2220 movs r2, #32
8004458: 4013 ands r3, r2
800445a: d009 beq.n 8004470 <HAL_RCCEx_PeriphCLKConfig+0x208>
{
/* Check the parameters */
assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
/* Configure the I2C1 clock source */
__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
800445c: 4b33 ldr r3, [pc, #204] ; (800452c <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
800445e: 6d5b ldr r3, [r3, #84] ; 0x54
8004460: 4a3b ldr r2, [pc, #236] ; (8004550 <HAL_RCCEx_PeriphCLKConfig+0x2e8>)
8004462: 4013 ands r3, r2
8004464: 0019 movs r1, r3
8004466: 687b ldr r3, [r7, #4]
8004468: 68da ldr r2, [r3, #12]
800446a: 4b30 ldr r3, [pc, #192] ; (800452c <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
800446c: 430a orrs r2, r1
800446e: 655a str r2, [r3, #84] ; 0x54
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLQCLK);
}
}
#endif /* RNG */
/*-------------------------- ADC clock source configuration ----------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
8004470: 687b ldr r3, [r7, #4]
8004472: 681a ldr r2, [r3, #0]
8004474: 2380 movs r3, #128 ; 0x80
8004476: 01db lsls r3, r3, #7
8004478: 4013 ands r3, r2
800447a: d015 beq.n 80044a8 <HAL_RCCEx_PeriphCLKConfig+0x240>
{
/* Check the parameters */
assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection));
/* Configure the ADC interface clock source */
__HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
800447c: 4b2b ldr r3, [pc, #172] ; (800452c <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
800447e: 6d5b ldr r3, [r3, #84] ; 0x54
8004480: 009b lsls r3, r3, #2
8004482: 0899 lsrs r1, r3, #2
8004484: 687b ldr r3, [r7, #4]
8004486: 69da ldr r2, [r3, #28]
8004488: 4b28 ldr r3, [pc, #160] ; (800452c <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
800448a: 430a orrs r2, r1
800448c: 655a str r2, [r3, #84] ; 0x54
if (PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLADC)
800448e: 687b ldr r3, [r7, #4]
8004490: 69da ldr r2, [r3, #28]
8004492: 2380 movs r3, #128 ; 0x80
8004494: 05db lsls r3, r3, #23
8004496: 429a cmp r2, r3
8004498: d106 bne.n 80044a8 <HAL_RCCEx_PeriphCLKConfig+0x240>
{
/* Enable PLLPCLK output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLPCLK);
800449a: 4b24 ldr r3, [pc, #144] ; (800452c <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
800449c: 68da ldr r2, [r3, #12]
800449e: 4b23 ldr r3, [pc, #140] ; (800452c <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
80044a0: 2180 movs r1, #128 ; 0x80
80044a2: 0249 lsls r1, r1, #9
80044a4: 430a orrs r2, r1
80044a6: 60da str r2, [r3, #12]
}
#endif /* CEC */
#if defined(RCC_CCIPR_TIM1SEL)
/*-------------------------- TIM1 clock source configuration ---------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1)
80044a8: 687b ldr r3, [r7, #4]
80044aa: 681a ldr r2, [r3, #0]
80044ac: 2380 movs r3, #128 ; 0x80
80044ae: 039b lsls r3, r3, #14
80044b0: 4013 ands r3, r2
80044b2: d016 beq.n 80044e2 <HAL_RCCEx_PeriphCLKConfig+0x27a>
{
/* Check the parameters */
assert_param(IS_RCC_TIM1CLKSOURCE(PeriphClkInit->Tim1ClockSelection));
/* Configure the TIM1 clock source */
__HAL_RCC_TIM1_CONFIG(PeriphClkInit->Tim1ClockSelection);
80044b4: 4b1d ldr r3, [pc, #116] ; (800452c <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
80044b6: 6d5b ldr r3, [r3, #84] ; 0x54
80044b8: 4a26 ldr r2, [pc, #152] ; (8004554 <HAL_RCCEx_PeriphCLKConfig+0x2ec>)
80044ba: 4013 ands r3, r2
80044bc: 0019 movs r1, r3
80044be: 687b ldr r3, [r7, #4]
80044c0: 6a1a ldr r2, [r3, #32]
80044c2: 4b1a ldr r3, [pc, #104] ; (800452c <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
80044c4: 430a orrs r2, r1
80044c6: 655a str r2, [r3, #84] ; 0x54
if (PeriphClkInit->Tim1ClockSelection == RCC_TIM1CLKSOURCE_PLL)
80044c8: 687b ldr r3, [r7, #4]
80044ca: 6a1a ldr r2, [r3, #32]
80044cc: 2380 movs r3, #128 ; 0x80
80044ce: 03db lsls r3, r3, #15
80044d0: 429a cmp r2, r3
80044d2: d106 bne.n 80044e2 <HAL_RCCEx_PeriphCLKConfig+0x27a>
{
/* Enable PLLQCLK output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLQCLK);
80044d4: 4b15 ldr r3, [pc, #84] ; (800452c <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
80044d6: 68da ldr r2, [r3, #12]
80044d8: 4b14 ldr r3, [pc, #80] ; (800452c <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
80044da: 2180 movs r1, #128 ; 0x80
80044dc: 0449 lsls r1, r1, #17
80044de: 430a orrs r2, r1
80044e0: 60da str r2, [r3, #12]
}
}
#endif /* RCC_CCIPR_TIM15SEL */
/*-------------------------- I2S1 clock source configuration ---------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1)
80044e2: 687b ldr r3, [r7, #4]
80044e4: 681a ldr r2, [r3, #0]
80044e6: 2380 movs r3, #128 ; 0x80
80044e8: 011b lsls r3, r3, #4
80044ea: 4013 ands r3, r2
80044ec: d016 beq.n 800451c <HAL_RCCEx_PeriphCLKConfig+0x2b4>
{
/* Check the parameters */
assert_param(IS_RCC_I2S1CLKSOURCE(PeriphClkInit->I2s1ClockSelection));
/* Configure the I2S1 clock source */
__HAL_RCC_I2S1_CONFIG(PeriphClkInit->I2s1ClockSelection);
80044ee: 4b0f ldr r3, [pc, #60] ; (800452c <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
80044f0: 6d5b ldr r3, [r3, #84] ; 0x54
80044f2: 4a19 ldr r2, [pc, #100] ; (8004558 <HAL_RCCEx_PeriphCLKConfig+0x2f0>)
80044f4: 4013 ands r3, r2
80044f6: 0019 movs r1, r3
80044f8: 687b ldr r3, [r7, #4]
80044fa: 691a ldr r2, [r3, #16]
80044fc: 4b0b ldr r3, [pc, #44] ; (800452c <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
80044fe: 430a orrs r2, r1
8004500: 655a str r2, [r3, #84] ; 0x54
if (PeriphClkInit->I2s1ClockSelection == RCC_I2S1CLKSOURCE_PLL)
8004502: 687b ldr r3, [r7, #4]
8004504: 691a ldr r2, [r3, #16]
8004506: 2380 movs r3, #128 ; 0x80
8004508: 01db lsls r3, r3, #7
800450a: 429a cmp r2, r3
800450c: d106 bne.n 800451c <HAL_RCCEx_PeriphCLKConfig+0x2b4>
{
/* Enable PLLPCLK output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLPCLK);
800450e: 4b07 ldr r3, [pc, #28] ; (800452c <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
8004510: 68da ldr r2, [r3, #12]
8004512: 4b06 ldr r3, [pc, #24] ; (800452c <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
8004514: 2180 movs r1, #128 ; 0x80
8004516: 0249 lsls r1, r1, #9
8004518: 430a orrs r2, r1
800451a: 60da str r2, [r3, #12]
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLQCLK);
}
}
#endif /* FDCAN1 || FDCAN2 */
return status;
800451c: 2312 movs r3, #18
800451e: 18fb adds r3, r7, r3
8004520: 781b ldrb r3, [r3, #0]
}
8004522: 0018 movs r0, r3
8004524: 46bd mov sp, r7
8004526: b006 add sp, #24
8004528: bd80 pop {r7, pc}
800452a: 46c0 nop ; (mov r8, r8)
800452c: 40021000 .word 0x40021000
8004530: 40007000 .word 0x40007000
8004534: fffffcff .word 0xfffffcff
8004538: fffeffff .word 0xfffeffff
800453c: 00001388 .word 0x00001388
8004540: efffffff .word 0xefffffff
8004544: fffff3ff .word 0xfffff3ff
8004548: fff3ffff .word 0xfff3ffff
800454c: ffcfffff .word 0xffcfffff
8004550: ffffcfff .word 0xffffcfff
8004554: ffbfffff .word 0xffbfffff
8004558: ffff3fff .word 0xffff3fff
0800455c <HAL_TIM_PWM_Init>:
* Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
* @param htim TIM PWM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
{
800455c: b580 push {r7, lr}
800455e: b082 sub sp, #8
8004560: af00 add r7, sp, #0
8004562: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
8004564: 687b ldr r3, [r7, #4]
8004566: 2b00 cmp r3, #0
8004568: d101 bne.n 800456e <HAL_TIM_PWM_Init+0x12>
{
return HAL_ERROR;
800456a: 2301 movs r3, #1
800456c: e04a b.n 8004604 <HAL_TIM_PWM_Init+0xa8>
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
800456e: 687b ldr r3, [r7, #4]
8004570: 223d movs r2, #61 ; 0x3d
8004572: 5c9b ldrb r3, [r3, r2]
8004574: b2db uxtb r3, r3
8004576: 2b00 cmp r3, #0
8004578: d107 bne.n 800458a <HAL_TIM_PWM_Init+0x2e>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
800457a: 687b ldr r3, [r7, #4]
800457c: 223c movs r2, #60 ; 0x3c
800457e: 2100 movs r1, #0
8004580: 5499 strb r1, [r3, r2]
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->PWM_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_PWM_MspInit(htim);
8004582: 687b ldr r3, [r7, #4]
8004584: 0018 movs r0, r3
8004586: f7fd f939 bl 80017fc <HAL_TIM_PWM_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
800458a: 687b ldr r3, [r7, #4]
800458c: 223d movs r2, #61 ; 0x3d
800458e: 2102 movs r1, #2
8004590: 5499 strb r1, [r3, r2]
/* Init the base time for the PWM */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
8004592: 687b ldr r3, [r7, #4]
8004594: 681a ldr r2, [r3, #0]
8004596: 687b ldr r3, [r7, #4]
8004598: 3304 adds r3, #4
800459a: 0019 movs r1, r3
800459c: 0010 movs r0, r2
800459e: f000 fb5f bl 8004c60 <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
80045a2: 687b ldr r3, [r7, #4]
80045a4: 2248 movs r2, #72 ; 0x48
80045a6: 2101 movs r1, #1
80045a8: 5499 strb r1, [r3, r2]
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
80045aa: 687b ldr r3, [r7, #4]
80045ac: 223e movs r2, #62 ; 0x3e
80045ae: 2101 movs r1, #1
80045b0: 5499 strb r1, [r3, r2]
80045b2: 687b ldr r3, [r7, #4]
80045b4: 223f movs r2, #63 ; 0x3f
80045b6: 2101 movs r1, #1
80045b8: 5499 strb r1, [r3, r2]
80045ba: 687b ldr r3, [r7, #4]
80045bc: 2240 movs r2, #64 ; 0x40
80045be: 2101 movs r1, #1
80045c0: 5499 strb r1, [r3, r2]
80045c2: 687b ldr r3, [r7, #4]
80045c4: 2241 movs r2, #65 ; 0x41
80045c6: 2101 movs r1, #1
80045c8: 5499 strb r1, [r3, r2]
80045ca: 687b ldr r3, [r7, #4]
80045cc: 2242 movs r2, #66 ; 0x42
80045ce: 2101 movs r1, #1
80045d0: 5499 strb r1, [r3, r2]
80045d2: 687b ldr r3, [r7, #4]
80045d4: 2243 movs r2, #67 ; 0x43
80045d6: 2101 movs r1, #1
80045d8: 5499 strb r1, [r3, r2]
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
80045da: 687b ldr r3, [r7, #4]
80045dc: 2244 movs r2, #68 ; 0x44
80045de: 2101 movs r1, #1
80045e0: 5499 strb r1, [r3, r2]
80045e2: 687b ldr r3, [r7, #4]
80045e4: 2245 movs r2, #69 ; 0x45
80045e6: 2101 movs r1, #1
80045e8: 5499 strb r1, [r3, r2]
80045ea: 687b ldr r3, [r7, #4]
80045ec: 2246 movs r2, #70 ; 0x46
80045ee: 2101 movs r1, #1
80045f0: 5499 strb r1, [r3, r2]
80045f2: 687b ldr r3, [r7, #4]
80045f4: 2247 movs r2, #71 ; 0x47
80045f6: 2101 movs r1, #1
80045f8: 5499 strb r1, [r3, r2]
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
80045fa: 687b ldr r3, [r7, #4]
80045fc: 223d movs r2, #61 ; 0x3d
80045fe: 2101 movs r1, #1
8004600: 5499 strb r1, [r3, r2]
return HAL_OK;
8004602: 2300 movs r3, #0
}
8004604: 0018 movs r0, r3
8004606: 46bd mov sp, r7
8004608: b002 add sp, #8
800460a: bd80 pop {r7, pc}
0800460c <HAL_TIM_PWM_Start>:
* @arg TIM_CHANNEL_5: TIM Channel 5 selected
* @arg TIM_CHANNEL_6: TIM Channel 6 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
800460c: b580 push {r7, lr}
800460e: b084 sub sp, #16
8004610: af00 add r7, sp, #0
8004612: 6078 str r0, [r7, #4]
8004614: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
/* Check the TIM channel state */
if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
8004616: 683b ldr r3, [r7, #0]
8004618: 2b00 cmp r3, #0
800461a: d108 bne.n 800462e <HAL_TIM_PWM_Start+0x22>
800461c: 687b ldr r3, [r7, #4]
800461e: 223e movs r2, #62 ; 0x3e
8004620: 5c9b ldrb r3, [r3, r2]
8004622: b2db uxtb r3, r3
8004624: 3b01 subs r3, #1
8004626: 1e5a subs r2, r3, #1
8004628: 4193 sbcs r3, r2
800462a: b2db uxtb r3, r3
800462c: e037 b.n 800469e <HAL_TIM_PWM_Start+0x92>
800462e: 683b ldr r3, [r7, #0]
8004630: 2b04 cmp r3, #4
8004632: d108 bne.n 8004646 <HAL_TIM_PWM_Start+0x3a>
8004634: 687b ldr r3, [r7, #4]
8004636: 223f movs r2, #63 ; 0x3f
8004638: 5c9b ldrb r3, [r3, r2]
800463a: b2db uxtb r3, r3
800463c: 3b01 subs r3, #1
800463e: 1e5a subs r2, r3, #1
8004640: 4193 sbcs r3, r2
8004642: b2db uxtb r3, r3
8004644: e02b b.n 800469e <HAL_TIM_PWM_Start+0x92>
8004646: 683b ldr r3, [r7, #0]
8004648: 2b08 cmp r3, #8
800464a: d108 bne.n 800465e <HAL_TIM_PWM_Start+0x52>
800464c: 687b ldr r3, [r7, #4]
800464e: 2240 movs r2, #64 ; 0x40
8004650: 5c9b ldrb r3, [r3, r2]
8004652: b2db uxtb r3, r3
8004654: 3b01 subs r3, #1
8004656: 1e5a subs r2, r3, #1
8004658: 4193 sbcs r3, r2
800465a: b2db uxtb r3, r3
800465c: e01f b.n 800469e <HAL_TIM_PWM_Start+0x92>
800465e: 683b ldr r3, [r7, #0]
8004660: 2b0c cmp r3, #12
8004662: d108 bne.n 8004676 <HAL_TIM_PWM_Start+0x6a>
8004664: 687b ldr r3, [r7, #4]
8004666: 2241 movs r2, #65 ; 0x41
8004668: 5c9b ldrb r3, [r3, r2]
800466a: b2db uxtb r3, r3
800466c: 3b01 subs r3, #1
800466e: 1e5a subs r2, r3, #1
8004670: 4193 sbcs r3, r2
8004672: b2db uxtb r3, r3
8004674: e013 b.n 800469e <HAL_TIM_PWM_Start+0x92>
8004676: 683b ldr r3, [r7, #0]
8004678: 2b10 cmp r3, #16
800467a: d108 bne.n 800468e <HAL_TIM_PWM_Start+0x82>
800467c: 687b ldr r3, [r7, #4]
800467e: 2242 movs r2, #66 ; 0x42
8004680: 5c9b ldrb r3, [r3, r2]
8004682: b2db uxtb r3, r3
8004684: 3b01 subs r3, #1
8004686: 1e5a subs r2, r3, #1
8004688: 4193 sbcs r3, r2
800468a: b2db uxtb r3, r3
800468c: e007 b.n 800469e <HAL_TIM_PWM_Start+0x92>
800468e: 687b ldr r3, [r7, #4]
8004690: 2243 movs r2, #67 ; 0x43
8004692: 5c9b ldrb r3, [r3, r2]
8004694: b2db uxtb r3, r3
8004696: 3b01 subs r3, #1
8004698: 1e5a subs r2, r3, #1
800469a: 4193 sbcs r3, r2
800469c: b2db uxtb r3, r3
800469e: 2b00 cmp r3, #0
80046a0: d001 beq.n 80046a6 <HAL_TIM_PWM_Start+0x9a>
{
return HAL_ERROR;
80046a2: 2301 movs r3, #1
80046a4: e081 b.n 80047aa <HAL_TIM_PWM_Start+0x19e>
}
/* Set the TIM channel state */
TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
80046a6: 683b ldr r3, [r7, #0]
80046a8: 2b00 cmp r3, #0
80046aa: d104 bne.n 80046b6 <HAL_TIM_PWM_Start+0xaa>
80046ac: 687b ldr r3, [r7, #4]
80046ae: 223e movs r2, #62 ; 0x3e
80046b0: 2102 movs r1, #2
80046b2: 5499 strb r1, [r3, r2]
80046b4: e023 b.n 80046fe <HAL_TIM_PWM_Start+0xf2>
80046b6: 683b ldr r3, [r7, #0]
80046b8: 2b04 cmp r3, #4
80046ba: d104 bne.n 80046c6 <HAL_TIM_PWM_Start+0xba>
80046bc: 687b ldr r3, [r7, #4]
80046be: 223f movs r2, #63 ; 0x3f
80046c0: 2102 movs r1, #2
80046c2: 5499 strb r1, [r3, r2]
80046c4: e01b b.n 80046fe <HAL_TIM_PWM_Start+0xf2>
80046c6: 683b ldr r3, [r7, #0]
80046c8: 2b08 cmp r3, #8
80046ca: d104 bne.n 80046d6 <HAL_TIM_PWM_Start+0xca>
80046cc: 687b ldr r3, [r7, #4]
80046ce: 2240 movs r2, #64 ; 0x40
80046d0: 2102 movs r1, #2
80046d2: 5499 strb r1, [r3, r2]
80046d4: e013 b.n 80046fe <HAL_TIM_PWM_Start+0xf2>
80046d6: 683b ldr r3, [r7, #0]
80046d8: 2b0c cmp r3, #12
80046da: d104 bne.n 80046e6 <HAL_TIM_PWM_Start+0xda>
80046dc: 687b ldr r3, [r7, #4]
80046de: 2241 movs r2, #65 ; 0x41
80046e0: 2102 movs r1, #2
80046e2: 5499 strb r1, [r3, r2]
80046e4: e00b b.n 80046fe <HAL_TIM_PWM_Start+0xf2>
80046e6: 683b ldr r3, [r7, #0]
80046e8: 2b10 cmp r3, #16
80046ea: d104 bne.n 80046f6 <HAL_TIM_PWM_Start+0xea>
80046ec: 687b ldr r3, [r7, #4]
80046ee: 2242 movs r2, #66 ; 0x42
80046f0: 2102 movs r1, #2
80046f2: 5499 strb r1, [r3, r2]
80046f4: e003 b.n 80046fe <HAL_TIM_PWM_Start+0xf2>
80046f6: 687b ldr r3, [r7, #4]
80046f8: 2243 movs r2, #67 ; 0x43
80046fa: 2102 movs r1, #2
80046fc: 5499 strb r1, [r3, r2]
/* Enable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
80046fe: 687b ldr r3, [r7, #4]
8004700: 681b ldr r3, [r3, #0]
8004702: 6839 ldr r1, [r7, #0]
8004704: 2201 movs r2, #1
8004706: 0018 movs r0, r3
8004708: f000 fdbc bl 8005284 <TIM_CCxChannelCmd>
if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
800470c: 687b ldr r3, [r7, #4]
800470e: 681b ldr r3, [r3, #0]
8004710: 4a28 ldr r2, [pc, #160] ; (80047b4 <HAL_TIM_PWM_Start+0x1a8>)
8004712: 4293 cmp r3, r2
8004714: d009 beq.n 800472a <HAL_TIM_PWM_Start+0x11e>
8004716: 687b ldr r3, [r7, #4]
8004718: 681b ldr r3, [r3, #0]
800471a: 4a27 ldr r2, [pc, #156] ; (80047b8 <HAL_TIM_PWM_Start+0x1ac>)
800471c: 4293 cmp r3, r2
800471e: d004 beq.n 800472a <HAL_TIM_PWM_Start+0x11e>
8004720: 687b ldr r3, [r7, #4]
8004722: 681b ldr r3, [r3, #0]
8004724: 4a25 ldr r2, [pc, #148] ; (80047bc <HAL_TIM_PWM_Start+0x1b0>)
8004726: 4293 cmp r3, r2
8004728: d101 bne.n 800472e <HAL_TIM_PWM_Start+0x122>
800472a: 2301 movs r3, #1
800472c: e000 b.n 8004730 <HAL_TIM_PWM_Start+0x124>
800472e: 2300 movs r3, #0
8004730: 2b00 cmp r3, #0
8004732: d008 beq.n 8004746 <HAL_TIM_PWM_Start+0x13a>
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
8004734: 687b ldr r3, [r7, #4]
8004736: 681b ldr r3, [r3, #0]
8004738: 6c5a ldr r2, [r3, #68] ; 0x44
800473a: 687b ldr r3, [r7, #4]
800473c: 681b ldr r3, [r3, #0]
800473e: 2180 movs r1, #128 ; 0x80
8004740: 0209 lsls r1, r1, #8
8004742: 430a orrs r2, r1
8004744: 645a str r2, [r3, #68] ; 0x44
}
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
8004746: 687b ldr r3, [r7, #4]
8004748: 681b ldr r3, [r3, #0]
800474a: 4a1a ldr r2, [pc, #104] ; (80047b4 <HAL_TIM_PWM_Start+0x1a8>)
800474c: 4293 cmp r3, r2
800474e: d00a beq.n 8004766 <HAL_TIM_PWM_Start+0x15a>
8004750: 687b ldr r3, [r7, #4]
8004752: 681a ldr r2, [r3, #0]
8004754: 2380 movs r3, #128 ; 0x80
8004756: 05db lsls r3, r3, #23
8004758: 429a cmp r2, r3
800475a: d004 beq.n 8004766 <HAL_TIM_PWM_Start+0x15a>
800475c: 687b ldr r3, [r7, #4]
800475e: 681b ldr r3, [r3, #0]
8004760: 4a17 ldr r2, [pc, #92] ; (80047c0 <HAL_TIM_PWM_Start+0x1b4>)
8004762: 4293 cmp r3, r2
8004764: d116 bne.n 8004794 <HAL_TIM_PWM_Start+0x188>
{
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
8004766: 687b ldr r3, [r7, #4]
8004768: 681b ldr r3, [r3, #0]
800476a: 689b ldr r3, [r3, #8]
800476c: 4a15 ldr r2, [pc, #84] ; (80047c4 <HAL_TIM_PWM_Start+0x1b8>)
800476e: 4013 ands r3, r2
8004770: 60fb str r3, [r7, #12]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8004772: 68fb ldr r3, [r7, #12]
8004774: 2b06 cmp r3, #6
8004776: d016 beq.n 80047a6 <HAL_TIM_PWM_Start+0x19a>
8004778: 68fa ldr r2, [r7, #12]
800477a: 2380 movs r3, #128 ; 0x80
800477c: 025b lsls r3, r3, #9
800477e: 429a cmp r2, r3
8004780: d011 beq.n 80047a6 <HAL_TIM_PWM_Start+0x19a>
{
__HAL_TIM_ENABLE(htim);
8004782: 687b ldr r3, [r7, #4]
8004784: 681b ldr r3, [r3, #0]
8004786: 681a ldr r2, [r3, #0]
8004788: 687b ldr r3, [r7, #4]
800478a: 681b ldr r3, [r3, #0]
800478c: 2101 movs r1, #1
800478e: 430a orrs r2, r1
8004790: 601a str r2, [r3, #0]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8004792: e008 b.n 80047a6 <HAL_TIM_PWM_Start+0x19a>
}
}
else
{
__HAL_TIM_ENABLE(htim);
8004794: 687b ldr r3, [r7, #4]
8004796: 681b ldr r3, [r3, #0]
8004798: 681a ldr r2, [r3, #0]
800479a: 687b ldr r3, [r7, #4]
800479c: 681b ldr r3, [r3, #0]
800479e: 2101 movs r1, #1
80047a0: 430a orrs r2, r1
80047a2: 601a str r2, [r3, #0]
80047a4: e000 b.n 80047a8 <HAL_TIM_PWM_Start+0x19c>
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
80047a6: 46c0 nop ; (mov r8, r8)
}
/* Return function status */
return HAL_OK;
80047a8: 2300 movs r3, #0
}
80047aa: 0018 movs r0, r3
80047ac: 46bd mov sp, r7
80047ae: b004 add sp, #16
80047b0: bd80 pop {r7, pc}
80047b2: 46c0 nop ; (mov r8, r8)
80047b4: 40012c00 .word 0x40012c00
80047b8: 40014400 .word 0x40014400
80047bc: 40014800 .word 0x40014800
80047c0: 40000400 .word 0x40000400
80047c4: 00010007 .word 0x00010007
080047c8 <HAL_TIM_Encoder_Init>:
* @param htim TIM Encoder Interface handle
* @param sConfig TIM Encoder Interface configuration structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
{
80047c8: b580 push {r7, lr}
80047ca: b086 sub sp, #24
80047cc: af00 add r7, sp, #0
80047ce: 6078 str r0, [r7, #4]
80047d0: 6039 str r1, [r7, #0]
uint32_t tmpsmcr;
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Check the TIM handle allocation */
if (htim == NULL)
80047d2: 687b ldr r3, [r7, #4]
80047d4: 2b00 cmp r3, #0
80047d6: d101 bne.n 80047dc <HAL_TIM_Encoder_Init+0x14>
{
return HAL_ERROR;
80047d8: 2301 movs r3, #1
80047da: e090 b.n 80048fe <HAL_TIM_Encoder_Init+0x136>
assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
if (htim->State == HAL_TIM_STATE_RESET)
80047dc: 687b ldr r3, [r7, #4]
80047de: 223d movs r2, #61 ; 0x3d
80047e0: 5c9b ldrb r3, [r3, r2]
80047e2: b2db uxtb r3, r3
80047e4: 2b00 cmp r3, #0
80047e6: d107 bne.n 80047f8 <HAL_TIM_Encoder_Init+0x30>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
80047e8: 687b ldr r3, [r7, #4]
80047ea: 223c movs r2, #60 ; 0x3c
80047ec: 2100 movs r1, #0
80047ee: 5499 strb r1, [r3, r2]
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->Encoder_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_Encoder_MspInit(htim);
80047f0: 687b ldr r3, [r7, #4]
80047f2: 0018 movs r0, r3
80047f4: f7fc ffba bl 800176c <HAL_TIM_Encoder_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
80047f8: 687b ldr r3, [r7, #4]
80047fa: 223d movs r2, #61 ; 0x3d
80047fc: 2102 movs r1, #2
80047fe: 5499 strb r1, [r3, r2]
/* Reset the SMS and ECE bits */
htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
8004800: 687b ldr r3, [r7, #4]
8004802: 681b ldr r3, [r3, #0]
8004804: 689a ldr r2, [r3, #8]
8004806: 687b ldr r3, [r7, #4]
8004808: 681b ldr r3, [r3, #0]
800480a: 493f ldr r1, [pc, #252] ; (8004908 <HAL_TIM_Encoder_Init+0x140>)
800480c: 400a ands r2, r1
800480e: 609a str r2, [r3, #8]
/* Configure the Time base in the Encoder Mode */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
8004810: 687b ldr r3, [r7, #4]
8004812: 681a ldr r2, [r3, #0]
8004814: 687b ldr r3, [r7, #4]
8004816: 3304 adds r3, #4
8004818: 0019 movs r1, r3
800481a: 0010 movs r0, r2
800481c: f000 fa20 bl 8004c60 <TIM_Base_SetConfig>
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
8004820: 687b ldr r3, [r7, #4]
8004822: 681b ldr r3, [r3, #0]
8004824: 689b ldr r3, [r3, #8]
8004826: 617b str r3, [r7, #20]
/* Get the TIMx CCMR1 register value */
tmpccmr1 = htim->Instance->CCMR1;
8004828: 687b ldr r3, [r7, #4]
800482a: 681b ldr r3, [r3, #0]
800482c: 699b ldr r3, [r3, #24]
800482e: 613b str r3, [r7, #16]
/* Get the TIMx CCER register value */
tmpccer = htim->Instance->CCER;
8004830: 687b ldr r3, [r7, #4]
8004832: 681b ldr r3, [r3, #0]
8004834: 6a1b ldr r3, [r3, #32]
8004836: 60fb str r3, [r7, #12]
/* Set the encoder Mode */
tmpsmcr |= sConfig->EncoderMode;
8004838: 683b ldr r3, [r7, #0]
800483a: 681b ldr r3, [r3, #0]
800483c: 697a ldr r2, [r7, #20]
800483e: 4313 orrs r3, r2
8004840: 617b str r3, [r7, #20]
/* Select the Capture Compare 1 and the Capture Compare 2 as input */
tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
8004842: 693b ldr r3, [r7, #16]
8004844: 4a31 ldr r2, [pc, #196] ; (800490c <HAL_TIM_Encoder_Init+0x144>)
8004846: 4013 ands r3, r2
8004848: 613b str r3, [r7, #16]
tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
800484a: 683b ldr r3, [r7, #0]
800484c: 689a ldr r2, [r3, #8]
800484e: 683b ldr r3, [r7, #0]
8004850: 699b ldr r3, [r3, #24]
8004852: 021b lsls r3, r3, #8
8004854: 4313 orrs r3, r2
8004856: 693a ldr r2, [r7, #16]
8004858: 4313 orrs r3, r2
800485a: 613b str r3, [r7, #16]
/* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
800485c: 693b ldr r3, [r7, #16]
800485e: 4a2c ldr r2, [pc, #176] ; (8004910 <HAL_TIM_Encoder_Init+0x148>)
8004860: 4013 ands r3, r2
8004862: 613b str r3, [r7, #16]
tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
8004864: 693b ldr r3, [r7, #16]
8004866: 4a2b ldr r2, [pc, #172] ; (8004914 <HAL_TIM_Encoder_Init+0x14c>)
8004868: 4013 ands r3, r2
800486a: 613b str r3, [r7, #16]
tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
800486c: 683b ldr r3, [r7, #0]
800486e: 68da ldr r2, [r3, #12]
8004870: 683b ldr r3, [r7, #0]
8004872: 69db ldr r3, [r3, #28]
8004874: 021b lsls r3, r3, #8
8004876: 4313 orrs r3, r2
8004878: 693a ldr r2, [r7, #16]
800487a: 4313 orrs r3, r2
800487c: 613b str r3, [r7, #16]
tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
800487e: 683b ldr r3, [r7, #0]
8004880: 691b ldr r3, [r3, #16]
8004882: 011a lsls r2, r3, #4
8004884: 683b ldr r3, [r7, #0]
8004886: 6a1b ldr r3, [r3, #32]
8004888: 031b lsls r3, r3, #12
800488a: 4313 orrs r3, r2
800488c: 693a ldr r2, [r7, #16]
800488e: 4313 orrs r3, r2
8004890: 613b str r3, [r7, #16]
/* Set the TI1 and the TI2 Polarities */
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
8004892: 68fb ldr r3, [r7, #12]
8004894: 2222 movs r2, #34 ; 0x22
8004896: 4393 bics r3, r2
8004898: 60fb str r3, [r7, #12]
tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
800489a: 68fb ldr r3, [r7, #12]
800489c: 2288 movs r2, #136 ; 0x88
800489e: 4393 bics r3, r2
80048a0: 60fb str r3, [r7, #12]
tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
80048a2: 683b ldr r3, [r7, #0]
80048a4: 685a ldr r2, [r3, #4]
80048a6: 683b ldr r3, [r7, #0]
80048a8: 695b ldr r3, [r3, #20]
80048aa: 011b lsls r3, r3, #4
80048ac: 4313 orrs r3, r2
80048ae: 68fa ldr r2, [r7, #12]
80048b0: 4313 orrs r3, r2
80048b2: 60fb str r3, [r7, #12]
/* Write to TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
80048b4: 687b ldr r3, [r7, #4]
80048b6: 681b ldr r3, [r3, #0]
80048b8: 697a ldr r2, [r7, #20]
80048ba: 609a str r2, [r3, #8]
/* Write to TIMx CCMR1 */
htim->Instance->CCMR1 = tmpccmr1;
80048bc: 687b ldr r3, [r7, #4]
80048be: 681b ldr r3, [r3, #0]
80048c0: 693a ldr r2, [r7, #16]
80048c2: 619a str r2, [r3, #24]
/* Write to TIMx CCER */
htim->Instance->CCER = tmpccer;
80048c4: 687b ldr r3, [r7, #4]
80048c6: 681b ldr r3, [r3, #0]
80048c8: 68fa ldr r2, [r7, #12]
80048ca: 621a str r2, [r3, #32]
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
80048cc: 687b ldr r3, [r7, #4]
80048ce: 2248 movs r2, #72 ; 0x48
80048d0: 2101 movs r1, #1
80048d2: 5499 strb r1, [r3, r2]
/* Set the TIM channels state */
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
80048d4: 687b ldr r3, [r7, #4]
80048d6: 223e movs r2, #62 ; 0x3e
80048d8: 2101 movs r1, #1
80048da: 5499 strb r1, [r3, r2]
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
80048dc: 687b ldr r3, [r7, #4]
80048de: 223f movs r2, #63 ; 0x3f
80048e0: 2101 movs r1, #1
80048e2: 5499 strb r1, [r3, r2]
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
80048e4: 687b ldr r3, [r7, #4]
80048e6: 2244 movs r2, #68 ; 0x44
80048e8: 2101 movs r1, #1
80048ea: 5499 strb r1, [r3, r2]
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
80048ec: 687b ldr r3, [r7, #4]
80048ee: 2245 movs r2, #69 ; 0x45
80048f0: 2101 movs r1, #1
80048f2: 5499 strb r1, [r3, r2]
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
80048f4: 687b ldr r3, [r7, #4]
80048f6: 223d movs r2, #61 ; 0x3d
80048f8: 2101 movs r1, #1
80048fa: 5499 strb r1, [r3, r2]
return HAL_OK;
80048fc: 2300 movs r3, #0
}
80048fe: 0018 movs r0, r3
8004900: 46bd mov sp, r7
8004902: b006 add sp, #24
8004904: bd80 pop {r7, pc}
8004906: 46c0 nop ; (mov r8, r8)
8004908: fffebff8 .word 0xfffebff8
800490c: fffffcfc .word 0xfffffcfc
8004910: fffff3f3 .word 0xfffff3f3
8004914: ffff0f0f .word 0xffff0f0f
08004918 <HAL_TIM_Encoder_Start>:
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
8004918: b590 push {r4, r7, lr}
800491a: b085 sub sp, #20
800491c: af00 add r7, sp, #0
800491e: 6078 str r0, [r7, #4]
8004920: 6039 str r1, [r7, #0]
HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
8004922: 200f movs r0, #15
8004924: 183b adds r3, r7, r0
8004926: 687a ldr r2, [r7, #4]
8004928: 213e movs r1, #62 ; 0x3e
800492a: 5c52 ldrb r2, [r2, r1]
800492c: 701a strb r2, [r3, #0]
HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
800492e: 230e movs r3, #14
8004930: 18fb adds r3, r7, r3
8004932: 687a ldr r2, [r7, #4]
8004934: 213f movs r1, #63 ; 0x3f
8004936: 5c52 ldrb r2, [r2, r1]
8004938: 701a strb r2, [r3, #0]
HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
800493a: 240d movs r4, #13
800493c: 193b adds r3, r7, r4
800493e: 687a ldr r2, [r7, #4]
8004940: 2144 movs r1, #68 ; 0x44
8004942: 5c52 ldrb r2, [r2, r1]
8004944: 701a strb r2, [r3, #0]
HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
8004946: 230c movs r3, #12
8004948: 18fb adds r3, r7, r3
800494a: 687a ldr r2, [r7, #4]
800494c: 2145 movs r1, #69 ; 0x45
800494e: 5c52 ldrb r2, [r2, r1]
8004950: 701a strb r2, [r3, #0]
/* Check the parameters */
assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
/* Set the TIM channel(s) state */
if (Channel == TIM_CHANNEL_1)
8004952: 683b ldr r3, [r7, #0]
8004954: 2b00 cmp r3, #0
8004956: d112 bne.n 800497e <HAL_TIM_Encoder_Start+0x66>
{
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
8004958: 183b adds r3, r7, r0
800495a: 781b ldrb r3, [r3, #0]
800495c: 2b01 cmp r3, #1
800495e: d103 bne.n 8004968 <HAL_TIM_Encoder_Start+0x50>
|| (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
8004960: 193b adds r3, r7, r4
8004962: 781b ldrb r3, [r3, #0]
8004964: 2b01 cmp r3, #1
8004966: d001 beq.n 800496c <HAL_TIM_Encoder_Start+0x54>
{
return HAL_ERROR;
8004968: 2301 movs r3, #1
800496a: e075 b.n 8004a58 <HAL_TIM_Encoder_Start+0x140>
}
else
{
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
800496c: 687b ldr r3, [r7, #4]
800496e: 223e movs r2, #62 ; 0x3e
8004970: 2102 movs r1, #2
8004972: 5499 strb r1, [r3, r2]
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
8004974: 687b ldr r3, [r7, #4]
8004976: 2244 movs r2, #68 ; 0x44
8004978: 2102 movs r1, #2
800497a: 5499 strb r1, [r3, r2]
800497c: e03d b.n 80049fa <HAL_TIM_Encoder_Start+0xe2>
}
}
else if (Channel == TIM_CHANNEL_2)
800497e: 683b ldr r3, [r7, #0]
8004980: 2b04 cmp r3, #4
8004982: d114 bne.n 80049ae <HAL_TIM_Encoder_Start+0x96>
{
if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
8004984: 230e movs r3, #14
8004986: 18fb adds r3, r7, r3
8004988: 781b ldrb r3, [r3, #0]
800498a: 2b01 cmp r3, #1
800498c: d104 bne.n 8004998 <HAL_TIM_Encoder_Start+0x80>
|| (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
800498e: 230c movs r3, #12
8004990: 18fb adds r3, r7, r3
8004992: 781b ldrb r3, [r3, #0]
8004994: 2b01 cmp r3, #1
8004996: d001 beq.n 800499c <HAL_TIM_Encoder_Start+0x84>
{
return HAL_ERROR;
8004998: 2301 movs r3, #1
800499a: e05d b.n 8004a58 <HAL_TIM_Encoder_Start+0x140>
}
else
{
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
800499c: 687b ldr r3, [r7, #4]
800499e: 223f movs r2, #63 ; 0x3f
80049a0: 2102 movs r1, #2
80049a2: 5499 strb r1, [r3, r2]
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
80049a4: 687b ldr r3, [r7, #4]
80049a6: 2245 movs r2, #69 ; 0x45
80049a8: 2102 movs r1, #2
80049aa: 5499 strb r1, [r3, r2]
80049ac: e025 b.n 80049fa <HAL_TIM_Encoder_Start+0xe2>
}
}
else
{
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
80049ae: 230f movs r3, #15
80049b0: 18fb adds r3, r7, r3
80049b2: 781b ldrb r3, [r3, #0]
80049b4: 2b01 cmp r3, #1
80049b6: d10e bne.n 80049d6 <HAL_TIM_Encoder_Start+0xbe>
|| (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
80049b8: 230e movs r3, #14
80049ba: 18fb adds r3, r7, r3
80049bc: 781b ldrb r3, [r3, #0]
80049be: 2b01 cmp r3, #1
80049c0: d109 bne.n 80049d6 <HAL_TIM_Encoder_Start+0xbe>
|| (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
80049c2: 230d movs r3, #13
80049c4: 18fb adds r3, r7, r3
80049c6: 781b ldrb r3, [r3, #0]
80049c8: 2b01 cmp r3, #1
80049ca: d104 bne.n 80049d6 <HAL_TIM_Encoder_Start+0xbe>
|| (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
80049cc: 230c movs r3, #12
80049ce: 18fb adds r3, r7, r3
80049d0: 781b ldrb r3, [r3, #0]
80049d2: 2b01 cmp r3, #1
80049d4: d001 beq.n 80049da <HAL_TIM_Encoder_Start+0xc2>
{
return HAL_ERROR;
80049d6: 2301 movs r3, #1
80049d8: e03e b.n 8004a58 <HAL_TIM_Encoder_Start+0x140>
}
else
{
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
80049da: 687b ldr r3, [r7, #4]
80049dc: 223e movs r2, #62 ; 0x3e
80049de: 2102 movs r1, #2
80049e0: 5499 strb r1, [r3, r2]
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
80049e2: 687b ldr r3, [r7, #4]
80049e4: 223f movs r2, #63 ; 0x3f
80049e6: 2102 movs r1, #2
80049e8: 5499 strb r1, [r3, r2]
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
80049ea: 687b ldr r3, [r7, #4]
80049ec: 2244 movs r2, #68 ; 0x44
80049ee: 2102 movs r1, #2
80049f0: 5499 strb r1, [r3, r2]
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
80049f2: 687b ldr r3, [r7, #4]
80049f4: 2245 movs r2, #69 ; 0x45
80049f6: 2102 movs r1, #2
80049f8: 5499 strb r1, [r3, r2]
}
}
/* Enable the encoder interface channels */
switch (Channel)
80049fa: 683b ldr r3, [r7, #0]
80049fc: 2b00 cmp r3, #0
80049fe: d003 beq.n 8004a08 <HAL_TIM_Encoder_Start+0xf0>
8004a00: 683b ldr r3, [r7, #0]
8004a02: 2b04 cmp r3, #4
8004a04: d008 beq.n 8004a18 <HAL_TIM_Encoder_Start+0x100>
8004a06: e00f b.n 8004a28 <HAL_TIM_Encoder_Start+0x110>
{
case TIM_CHANNEL_1:
{
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
8004a08: 687b ldr r3, [r7, #4]
8004a0a: 681b ldr r3, [r3, #0]
8004a0c: 2201 movs r2, #1
8004a0e: 2100 movs r1, #0
8004a10: 0018 movs r0, r3
8004a12: f000 fc37 bl 8005284 <TIM_CCxChannelCmd>
break;
8004a16: e016 b.n 8004a46 <HAL_TIM_Encoder_Start+0x12e>
}
case TIM_CHANNEL_2:
{
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
8004a18: 687b ldr r3, [r7, #4]
8004a1a: 681b ldr r3, [r3, #0]
8004a1c: 2201 movs r2, #1
8004a1e: 2104 movs r1, #4
8004a20: 0018 movs r0, r3
8004a22: f000 fc2f bl 8005284 <TIM_CCxChannelCmd>
break;
8004a26: e00e b.n 8004a46 <HAL_TIM_Encoder_Start+0x12e>
}
default :
{
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
8004a28: 687b ldr r3, [r7, #4]
8004a2a: 681b ldr r3, [r3, #0]
8004a2c: 2201 movs r2, #1
8004a2e: 2100 movs r1, #0
8004a30: 0018 movs r0, r3
8004a32: f000 fc27 bl 8005284 <TIM_CCxChannelCmd>
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
8004a36: 687b ldr r3, [r7, #4]
8004a38: 681b ldr r3, [r3, #0]
8004a3a: 2201 movs r2, #1
8004a3c: 2104 movs r1, #4
8004a3e: 0018 movs r0, r3
8004a40: f000 fc20 bl 8005284 <TIM_CCxChannelCmd>
break;
8004a44: 46c0 nop ; (mov r8, r8)
}
}
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
8004a46: 687b ldr r3, [r7, #4]
8004a48: 681b ldr r3, [r3, #0]
8004a4a: 681a ldr r2, [r3, #0]
8004a4c: 687b ldr r3, [r7, #4]
8004a4e: 681b ldr r3, [r3, #0]
8004a50: 2101 movs r1, #1
8004a52: 430a orrs r2, r1
8004a54: 601a str r2, [r3, #0]
/* Return function status */
return HAL_OK;
8004a56: 2300 movs r3, #0
}
8004a58: 0018 movs r0, r3
8004a5a: 46bd mov sp, r7
8004a5c: b005 add sp, #20
8004a5e: bd90 pop {r4, r7, pc}
08004a60 <HAL_TIM_PWM_ConfigChannel>:
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
const TIM_OC_InitTypeDef *sConfig,
uint32_t Channel)
{
8004a60: b580 push {r7, lr}
8004a62: b086 sub sp, #24
8004a64: af00 add r7, sp, #0
8004a66: 60f8 str r0, [r7, #12]
8004a68: 60b9 str r1, [r7, #8]
8004a6a: 607a str r2, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
8004a6c: 2317 movs r3, #23
8004a6e: 18fb adds r3, r7, r3
8004a70: 2200 movs r2, #0
8004a72: 701a strb r2, [r3, #0]
assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
/* Process Locked */
__HAL_LOCK(htim);
8004a74: 68fb ldr r3, [r7, #12]
8004a76: 223c movs r2, #60 ; 0x3c
8004a78: 5c9b ldrb r3, [r3, r2]
8004a7a: 2b01 cmp r3, #1
8004a7c: d101 bne.n 8004a82 <HAL_TIM_PWM_ConfigChannel+0x22>
8004a7e: 2302 movs r3, #2
8004a80: e0e5 b.n 8004c4e <HAL_TIM_PWM_ConfigChannel+0x1ee>
8004a82: 68fb ldr r3, [r7, #12]
8004a84: 223c movs r2, #60 ; 0x3c
8004a86: 2101 movs r1, #1
8004a88: 5499 strb r1, [r3, r2]
switch (Channel)
8004a8a: 687b ldr r3, [r7, #4]
8004a8c: 2b14 cmp r3, #20
8004a8e: d900 bls.n 8004a92 <HAL_TIM_PWM_ConfigChannel+0x32>
8004a90: e0d1 b.n 8004c36 <HAL_TIM_PWM_ConfigChannel+0x1d6>
8004a92: 687b ldr r3, [r7, #4]
8004a94: 009a lsls r2, r3, #2
8004a96: 4b70 ldr r3, [pc, #448] ; (8004c58 <HAL_TIM_PWM_ConfigChannel+0x1f8>)
8004a98: 18d3 adds r3, r2, r3
8004a9a: 681b ldr r3, [r3, #0]
8004a9c: 469f mov pc, r3
{
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
/* Configure the Channel 1 in PWM mode */
TIM_OC1_SetConfig(htim->Instance, sConfig);
8004a9e: 68fb ldr r3, [r7, #12]
8004aa0: 681b ldr r3, [r3, #0]
8004aa2: 68ba ldr r2, [r7, #8]
8004aa4: 0011 movs r1, r2
8004aa6: 0018 movs r0, r3
8004aa8: f000 f950 bl 8004d4c <TIM_OC1_SetConfig>
/* Set the Preload enable bit for channel1 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
8004aac: 68fb ldr r3, [r7, #12]
8004aae: 681b ldr r3, [r3, #0]
8004ab0: 699a ldr r2, [r3, #24]
8004ab2: 68fb ldr r3, [r7, #12]
8004ab4: 681b ldr r3, [r3, #0]
8004ab6: 2108 movs r1, #8
8004ab8: 430a orrs r2, r1
8004aba: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
8004abc: 68fb ldr r3, [r7, #12]
8004abe: 681b ldr r3, [r3, #0]
8004ac0: 699a ldr r2, [r3, #24]
8004ac2: 68fb ldr r3, [r7, #12]
8004ac4: 681b ldr r3, [r3, #0]
8004ac6: 2104 movs r1, #4
8004ac8: 438a bics r2, r1
8004aca: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode;
8004acc: 68fb ldr r3, [r7, #12]
8004ace: 681b ldr r3, [r3, #0]
8004ad0: 6999 ldr r1, [r3, #24]
8004ad2: 68bb ldr r3, [r7, #8]
8004ad4: 691a ldr r2, [r3, #16]
8004ad6: 68fb ldr r3, [r7, #12]
8004ad8: 681b ldr r3, [r3, #0]
8004ada: 430a orrs r2, r1
8004adc: 619a str r2, [r3, #24]
break;
8004ade: e0af b.n 8004c40 <HAL_TIM_PWM_ConfigChannel+0x1e0>
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
/* Configure the Channel 2 in PWM mode */
TIM_OC2_SetConfig(htim->Instance, sConfig);
8004ae0: 68fb ldr r3, [r7, #12]
8004ae2: 681b ldr r3, [r3, #0]
8004ae4: 68ba ldr r2, [r7, #8]
8004ae6: 0011 movs r1, r2
8004ae8: 0018 movs r0, r3
8004aea: f000 f9af bl 8004e4c <TIM_OC2_SetConfig>
/* Set the Preload enable bit for channel2 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
8004aee: 68fb ldr r3, [r7, #12]
8004af0: 681b ldr r3, [r3, #0]
8004af2: 699a ldr r2, [r3, #24]
8004af4: 68fb ldr r3, [r7, #12]
8004af6: 681b ldr r3, [r3, #0]
8004af8: 2180 movs r1, #128 ; 0x80
8004afa: 0109 lsls r1, r1, #4
8004afc: 430a orrs r2, r1
8004afe: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
8004b00: 68fb ldr r3, [r7, #12]
8004b02: 681b ldr r3, [r3, #0]
8004b04: 699a ldr r2, [r3, #24]
8004b06: 68fb ldr r3, [r7, #12]
8004b08: 681b ldr r3, [r3, #0]
8004b0a: 4954 ldr r1, [pc, #336] ; (8004c5c <HAL_TIM_PWM_ConfigChannel+0x1fc>)
8004b0c: 400a ands r2, r1
8004b0e: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
8004b10: 68fb ldr r3, [r7, #12]
8004b12: 681b ldr r3, [r3, #0]
8004b14: 6999 ldr r1, [r3, #24]
8004b16: 68bb ldr r3, [r7, #8]
8004b18: 691b ldr r3, [r3, #16]
8004b1a: 021a lsls r2, r3, #8
8004b1c: 68fb ldr r3, [r7, #12]
8004b1e: 681b ldr r3, [r3, #0]
8004b20: 430a orrs r2, r1
8004b22: 619a str r2, [r3, #24]
break;
8004b24: e08c b.n 8004c40 <HAL_TIM_PWM_ConfigChannel+0x1e0>
{
/* Check the parameters */
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
/* Configure the Channel 3 in PWM mode */
TIM_OC3_SetConfig(htim->Instance, sConfig);
8004b26: 68fb ldr r3, [r7, #12]
8004b28: 681b ldr r3, [r3, #0]
8004b2a: 68ba ldr r2, [r7, #8]
8004b2c: 0011 movs r1, r2
8004b2e: 0018 movs r0, r3
8004b30: f000 fa0a bl 8004f48 <TIM_OC3_SetConfig>
/* Set the Preload enable bit for channel3 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
8004b34: 68fb ldr r3, [r7, #12]
8004b36: 681b ldr r3, [r3, #0]
8004b38: 69da ldr r2, [r3, #28]
8004b3a: 68fb ldr r3, [r7, #12]
8004b3c: 681b ldr r3, [r3, #0]
8004b3e: 2108 movs r1, #8
8004b40: 430a orrs r2, r1
8004b42: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
8004b44: 68fb ldr r3, [r7, #12]
8004b46: 681b ldr r3, [r3, #0]
8004b48: 69da ldr r2, [r3, #28]
8004b4a: 68fb ldr r3, [r7, #12]
8004b4c: 681b ldr r3, [r3, #0]
8004b4e: 2104 movs r1, #4
8004b50: 438a bics r2, r1
8004b52: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode;
8004b54: 68fb ldr r3, [r7, #12]
8004b56: 681b ldr r3, [r3, #0]
8004b58: 69d9 ldr r1, [r3, #28]
8004b5a: 68bb ldr r3, [r7, #8]
8004b5c: 691a ldr r2, [r3, #16]
8004b5e: 68fb ldr r3, [r7, #12]
8004b60: 681b ldr r3, [r3, #0]
8004b62: 430a orrs r2, r1
8004b64: 61da str r2, [r3, #28]
break;
8004b66: e06b b.n 8004c40 <HAL_TIM_PWM_ConfigChannel+0x1e0>
{
/* Check the parameters */
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
/* Configure the Channel 4 in PWM mode */
TIM_OC4_SetConfig(htim->Instance, sConfig);
8004b68: 68fb ldr r3, [r7, #12]
8004b6a: 681b ldr r3, [r3, #0]
8004b6c: 68ba ldr r2, [r7, #8]
8004b6e: 0011 movs r1, r2
8004b70: 0018 movs r0, r3
8004b72: f000 fa6b bl 800504c <TIM_OC4_SetConfig>
/* Set the Preload enable bit for channel4 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
8004b76: 68fb ldr r3, [r7, #12]
8004b78: 681b ldr r3, [r3, #0]
8004b7a: 69da ldr r2, [r3, #28]
8004b7c: 68fb ldr r3, [r7, #12]
8004b7e: 681b ldr r3, [r3, #0]
8004b80: 2180 movs r1, #128 ; 0x80
8004b82: 0109 lsls r1, r1, #4
8004b84: 430a orrs r2, r1
8004b86: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
8004b88: 68fb ldr r3, [r7, #12]
8004b8a: 681b ldr r3, [r3, #0]
8004b8c: 69da ldr r2, [r3, #28]
8004b8e: 68fb ldr r3, [r7, #12]
8004b90: 681b ldr r3, [r3, #0]
8004b92: 4932 ldr r1, [pc, #200] ; (8004c5c <HAL_TIM_PWM_ConfigChannel+0x1fc>)
8004b94: 400a ands r2, r1
8004b96: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
8004b98: 68fb ldr r3, [r7, #12]
8004b9a: 681b ldr r3, [r3, #0]
8004b9c: 69d9 ldr r1, [r3, #28]
8004b9e: 68bb ldr r3, [r7, #8]
8004ba0: 691b ldr r3, [r3, #16]
8004ba2: 021a lsls r2, r3, #8
8004ba4: 68fb ldr r3, [r7, #12]
8004ba6: 681b ldr r3, [r3, #0]
8004ba8: 430a orrs r2, r1
8004baa: 61da str r2, [r3, #28]
break;
8004bac: e048 b.n 8004c40 <HAL_TIM_PWM_ConfigChannel+0x1e0>
{
/* Check the parameters */
assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
/* Configure the Channel 5 in PWM mode */
TIM_OC5_SetConfig(htim->Instance, sConfig);
8004bae: 68fb ldr r3, [r7, #12]
8004bb0: 681b ldr r3, [r3, #0]
8004bb2: 68ba ldr r2, [r7, #8]
8004bb4: 0011 movs r1, r2
8004bb6: 0018 movs r0, r3
8004bb8: f000 faac bl 8005114 <TIM_OC5_SetConfig>
/* Set the Preload enable bit for channel5*/
htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
8004bbc: 68fb ldr r3, [r7, #12]
8004bbe: 681b ldr r3, [r3, #0]
8004bc0: 6d5a ldr r2, [r3, #84] ; 0x54
8004bc2: 68fb ldr r3, [r7, #12]
8004bc4: 681b ldr r3, [r3, #0]
8004bc6: 2108 movs r1, #8
8004bc8: 430a orrs r2, r1
8004bca: 655a str r2, [r3, #84] ; 0x54
/* Configure the Output Fast mode */
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
8004bcc: 68fb ldr r3, [r7, #12]
8004bce: 681b ldr r3, [r3, #0]
8004bd0: 6d5a ldr r2, [r3, #84] ; 0x54
8004bd2: 68fb ldr r3, [r7, #12]
8004bd4: 681b ldr r3, [r3, #0]
8004bd6: 2104 movs r1, #4
8004bd8: 438a bics r2, r1
8004bda: 655a str r2, [r3, #84] ; 0x54
htim->Instance->CCMR3 |= sConfig->OCFastMode;
8004bdc: 68fb ldr r3, [r7, #12]
8004bde: 681b ldr r3, [r3, #0]
8004be0: 6d59 ldr r1, [r3, #84] ; 0x54
8004be2: 68bb ldr r3, [r7, #8]
8004be4: 691a ldr r2, [r3, #16]
8004be6: 68fb ldr r3, [r7, #12]
8004be8: 681b ldr r3, [r3, #0]
8004bea: 430a orrs r2, r1
8004bec: 655a str r2, [r3, #84] ; 0x54
break;
8004bee: e027 b.n 8004c40 <HAL_TIM_PWM_ConfigChannel+0x1e0>
{
/* Check the parameters */
assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
/* Configure the Channel 6 in PWM mode */
TIM_OC6_SetConfig(htim->Instance, sConfig);
8004bf0: 68fb ldr r3, [r7, #12]
8004bf2: 681b ldr r3, [r3, #0]
8004bf4: 68ba ldr r2, [r7, #8]
8004bf6: 0011 movs r1, r2
8004bf8: 0018 movs r0, r3
8004bfa: f000 fae5 bl 80051c8 <TIM_OC6_SetConfig>
/* Set the Preload enable bit for channel6 */
htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
8004bfe: 68fb ldr r3, [r7, #12]
8004c00: 681b ldr r3, [r3, #0]
8004c02: 6d5a ldr r2, [r3, #84] ; 0x54
8004c04: 68fb ldr r3, [r7, #12]
8004c06: 681b ldr r3, [r3, #0]
8004c08: 2180 movs r1, #128 ; 0x80
8004c0a: 0109 lsls r1, r1, #4
8004c0c: 430a orrs r2, r1
8004c0e: 655a str r2, [r3, #84] ; 0x54
/* Configure the Output Fast mode */
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
8004c10: 68fb ldr r3, [r7, #12]
8004c12: 681b ldr r3, [r3, #0]
8004c14: 6d5a ldr r2, [r3, #84] ; 0x54
8004c16: 68fb ldr r3, [r7, #12]
8004c18: 681b ldr r3, [r3, #0]
8004c1a: 4910 ldr r1, [pc, #64] ; (8004c5c <HAL_TIM_PWM_ConfigChannel+0x1fc>)
8004c1c: 400a ands r2, r1
8004c1e: 655a str r2, [r3, #84] ; 0x54
htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
8004c20: 68fb ldr r3, [r7, #12]
8004c22: 681b ldr r3, [r3, #0]
8004c24: 6d59 ldr r1, [r3, #84] ; 0x54
8004c26: 68bb ldr r3, [r7, #8]
8004c28: 691b ldr r3, [r3, #16]
8004c2a: 021a lsls r2, r3, #8
8004c2c: 68fb ldr r3, [r7, #12]
8004c2e: 681b ldr r3, [r3, #0]
8004c30: 430a orrs r2, r1
8004c32: 655a str r2, [r3, #84] ; 0x54
break;
8004c34: e004 b.n 8004c40 <HAL_TIM_PWM_ConfigChannel+0x1e0>
}
default:
status = HAL_ERROR;
8004c36: 2317 movs r3, #23
8004c38: 18fb adds r3, r7, r3
8004c3a: 2201 movs r2, #1
8004c3c: 701a strb r2, [r3, #0]
break;
8004c3e: 46c0 nop ; (mov r8, r8)
}
__HAL_UNLOCK(htim);
8004c40: 68fb ldr r3, [r7, #12]
8004c42: 223c movs r2, #60 ; 0x3c
8004c44: 2100 movs r1, #0
8004c46: 5499 strb r1, [r3, r2]
return status;
8004c48: 2317 movs r3, #23
8004c4a: 18fb adds r3, r7, r3
8004c4c: 781b ldrb r3, [r3, #0]
}
8004c4e: 0018 movs r0, r3
8004c50: 46bd mov sp, r7
8004c52: b006 add sp, #24
8004c54: bd80 pop {r7, pc}
8004c56: 46c0 nop ; (mov r8, r8)
8004c58: 08007448 .word 0x08007448
8004c5c: fffffbff .word 0xfffffbff
08004c60 <TIM_Base_SetConfig>:
* @param TIMx TIM peripheral
* @param Structure TIM Base configuration structure
* @retval None
*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
{
8004c60: b580 push {r7, lr}
8004c62: b084 sub sp, #16
8004c64: af00 add r7, sp, #0
8004c66: 6078 str r0, [r7, #4]
8004c68: 6039 str r1, [r7, #0]
uint32_t tmpcr1;
tmpcr1 = TIMx->CR1;
8004c6a: 687b ldr r3, [r7, #4]
8004c6c: 681b ldr r3, [r3, #0]
8004c6e: 60fb str r3, [r7, #12]
/* Set TIM Time Base Unit parameters ---------------------------------------*/
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
8004c70: 687b ldr r3, [r7, #4]
8004c72: 4a30 ldr r2, [pc, #192] ; (8004d34 <TIM_Base_SetConfig+0xd4>)
8004c74: 4293 cmp r3, r2
8004c76: d008 beq.n 8004c8a <TIM_Base_SetConfig+0x2a>
8004c78: 687a ldr r2, [r7, #4]
8004c7a: 2380 movs r3, #128 ; 0x80
8004c7c: 05db lsls r3, r3, #23
8004c7e: 429a cmp r2, r3
8004c80: d003 beq.n 8004c8a <TIM_Base_SetConfig+0x2a>
8004c82: 687b ldr r3, [r7, #4]
8004c84: 4a2c ldr r2, [pc, #176] ; (8004d38 <TIM_Base_SetConfig+0xd8>)
8004c86: 4293 cmp r3, r2
8004c88: d108 bne.n 8004c9c <TIM_Base_SetConfig+0x3c>
{
/* Select the Counter Mode */
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
8004c8a: 68fb ldr r3, [r7, #12]
8004c8c: 2270 movs r2, #112 ; 0x70
8004c8e: 4393 bics r3, r2
8004c90: 60fb str r3, [r7, #12]
tmpcr1 |= Structure->CounterMode;
8004c92: 683b ldr r3, [r7, #0]
8004c94: 685b ldr r3, [r3, #4]
8004c96: 68fa ldr r2, [r7, #12]
8004c98: 4313 orrs r3, r2
8004c9a: 60fb str r3, [r7, #12]
}
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
8004c9c: 687b ldr r3, [r7, #4]
8004c9e: 4a25 ldr r2, [pc, #148] ; (8004d34 <TIM_Base_SetConfig+0xd4>)
8004ca0: 4293 cmp r3, r2
8004ca2: d014 beq.n 8004cce <TIM_Base_SetConfig+0x6e>
8004ca4: 687a ldr r2, [r7, #4]
8004ca6: 2380 movs r3, #128 ; 0x80
8004ca8: 05db lsls r3, r3, #23
8004caa: 429a cmp r2, r3
8004cac: d00f beq.n 8004cce <TIM_Base_SetConfig+0x6e>
8004cae: 687b ldr r3, [r7, #4]
8004cb0: 4a21 ldr r2, [pc, #132] ; (8004d38 <TIM_Base_SetConfig+0xd8>)
8004cb2: 4293 cmp r3, r2
8004cb4: d00b beq.n 8004cce <TIM_Base_SetConfig+0x6e>
8004cb6: 687b ldr r3, [r7, #4]
8004cb8: 4a20 ldr r2, [pc, #128] ; (8004d3c <TIM_Base_SetConfig+0xdc>)
8004cba: 4293 cmp r3, r2
8004cbc: d007 beq.n 8004cce <TIM_Base_SetConfig+0x6e>
8004cbe: 687b ldr r3, [r7, #4]
8004cc0: 4a1f ldr r2, [pc, #124] ; (8004d40 <TIM_Base_SetConfig+0xe0>)
8004cc2: 4293 cmp r3, r2
8004cc4: d003 beq.n 8004cce <TIM_Base_SetConfig+0x6e>
8004cc6: 687b ldr r3, [r7, #4]
8004cc8: 4a1e ldr r2, [pc, #120] ; (8004d44 <TIM_Base_SetConfig+0xe4>)
8004cca: 4293 cmp r3, r2
8004ccc: d108 bne.n 8004ce0 <TIM_Base_SetConfig+0x80>
{
/* Set the clock division */
tmpcr1 &= ~TIM_CR1_CKD;
8004cce: 68fb ldr r3, [r7, #12]
8004cd0: 4a1d ldr r2, [pc, #116] ; (8004d48 <TIM_Base_SetConfig+0xe8>)
8004cd2: 4013 ands r3, r2
8004cd4: 60fb str r3, [r7, #12]
tmpcr1 |= (uint32_t)Structure->ClockDivision;
8004cd6: 683b ldr r3, [r7, #0]
8004cd8: 68db ldr r3, [r3, #12]
8004cda: 68fa ldr r2, [r7, #12]
8004cdc: 4313 orrs r3, r2
8004cde: 60fb str r3, [r7, #12]
}
/* Set the auto-reload preload */
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
8004ce0: 68fb ldr r3, [r7, #12]
8004ce2: 2280 movs r2, #128 ; 0x80
8004ce4: 4393 bics r3, r2
8004ce6: 001a movs r2, r3
8004ce8: 683b ldr r3, [r7, #0]
8004cea: 695b ldr r3, [r3, #20]
8004cec: 4313 orrs r3, r2
8004cee: 60fb str r3, [r7, #12]
TIMx->CR1 = tmpcr1;
8004cf0: 687b ldr r3, [r7, #4]
8004cf2: 68fa ldr r2, [r7, #12]
8004cf4: 601a str r2, [r3, #0]
/* Set the Autoreload value */
TIMx->ARR = (uint32_t)Structure->Period ;
8004cf6: 683b ldr r3, [r7, #0]
8004cf8: 689a ldr r2, [r3, #8]
8004cfa: 687b ldr r3, [r7, #4]
8004cfc: 62da str r2, [r3, #44] ; 0x2c
/* Set the Prescaler value */
TIMx->PSC = Structure->Prescaler;
8004cfe: 683b ldr r3, [r7, #0]
8004d00: 681a ldr r2, [r3, #0]
8004d02: 687b ldr r3, [r7, #4]
8004d04: 629a str r2, [r3, #40] ; 0x28
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
8004d06: 687b ldr r3, [r7, #4]
8004d08: 4a0a ldr r2, [pc, #40] ; (8004d34 <TIM_Base_SetConfig+0xd4>)
8004d0a: 4293 cmp r3, r2
8004d0c: d007 beq.n 8004d1e <TIM_Base_SetConfig+0xbe>
8004d0e: 687b ldr r3, [r7, #4]
8004d10: 4a0b ldr r2, [pc, #44] ; (8004d40 <TIM_Base_SetConfig+0xe0>)
8004d12: 4293 cmp r3, r2
8004d14: d003 beq.n 8004d1e <TIM_Base_SetConfig+0xbe>
8004d16: 687b ldr r3, [r7, #4]
8004d18: 4a0a ldr r2, [pc, #40] ; (8004d44 <TIM_Base_SetConfig+0xe4>)
8004d1a: 4293 cmp r3, r2
8004d1c: d103 bne.n 8004d26 <TIM_Base_SetConfig+0xc6>
{
/* Set the Repetition Counter value */
TIMx->RCR = Structure->RepetitionCounter;
8004d1e: 683b ldr r3, [r7, #0]
8004d20: 691a ldr r2, [r3, #16]
8004d22: 687b ldr r3, [r7, #4]
8004d24: 631a str r2, [r3, #48] ; 0x30
}
/* Generate an update event to reload the Prescaler
and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
8004d26: 687b ldr r3, [r7, #4]
8004d28: 2201 movs r2, #1
8004d2a: 615a str r2, [r3, #20]
}
8004d2c: 46c0 nop ; (mov r8, r8)
8004d2e: 46bd mov sp, r7
8004d30: b004 add sp, #16
8004d32: bd80 pop {r7, pc}
8004d34: 40012c00 .word 0x40012c00
8004d38: 40000400 .word 0x40000400
8004d3c: 40002000 .word 0x40002000
8004d40: 40014400 .word 0x40014400
8004d44: 40014800 .word 0x40014800
8004d48: fffffcff .word 0xfffffcff
08004d4c <TIM_OC1_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
8004d4c: b580 push {r7, lr}
8004d4e: b086 sub sp, #24
8004d50: af00 add r7, sp, #0
8004d52: 6078 str r0, [r7, #4]
8004d54: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 1: Reset the CC1E Bit */
TIMx->CCER &= ~TIM_CCER_CC1E;
8004d56: 687b ldr r3, [r7, #4]
8004d58: 6a1b ldr r3, [r3, #32]
8004d5a: 2201 movs r2, #1
8004d5c: 4393 bics r3, r2
8004d5e: 001a movs r2, r3
8004d60: 687b ldr r3, [r7, #4]
8004d62: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8004d64: 687b ldr r3, [r7, #4]
8004d66: 6a1b ldr r3, [r3, #32]
8004d68: 617b str r3, [r7, #20]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8004d6a: 687b ldr r3, [r7, #4]
8004d6c: 685b ldr r3, [r3, #4]
8004d6e: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
8004d70: 687b ldr r3, [r7, #4]
8004d72: 699b ldr r3, [r3, #24]
8004d74: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~TIM_CCMR1_OC1M;
8004d76: 68fb ldr r3, [r7, #12]
8004d78: 4a2e ldr r2, [pc, #184] ; (8004e34 <TIM_OC1_SetConfig+0xe8>)
8004d7a: 4013 ands r3, r2
8004d7c: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC1S;
8004d7e: 68fb ldr r3, [r7, #12]
8004d80: 2203 movs r2, #3
8004d82: 4393 bics r3, r2
8004d84: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
8004d86: 683b ldr r3, [r7, #0]
8004d88: 681b ldr r3, [r3, #0]
8004d8a: 68fa ldr r2, [r7, #12]
8004d8c: 4313 orrs r3, r2
8004d8e: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC1P;
8004d90: 697b ldr r3, [r7, #20]
8004d92: 2202 movs r2, #2
8004d94: 4393 bics r3, r2
8004d96: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= OC_Config->OCPolarity;
8004d98: 683b ldr r3, [r7, #0]
8004d9a: 689b ldr r3, [r3, #8]
8004d9c: 697a ldr r2, [r7, #20]
8004d9e: 4313 orrs r3, r2
8004da0: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
8004da2: 687b ldr r3, [r7, #4]
8004da4: 4a24 ldr r2, [pc, #144] ; (8004e38 <TIM_OC1_SetConfig+0xec>)
8004da6: 4293 cmp r3, r2
8004da8: d007 beq.n 8004dba <TIM_OC1_SetConfig+0x6e>
8004daa: 687b ldr r3, [r7, #4]
8004dac: 4a23 ldr r2, [pc, #140] ; (8004e3c <TIM_OC1_SetConfig+0xf0>)
8004dae: 4293 cmp r3, r2
8004db0: d003 beq.n 8004dba <TIM_OC1_SetConfig+0x6e>
8004db2: 687b ldr r3, [r7, #4]
8004db4: 4a22 ldr r2, [pc, #136] ; (8004e40 <TIM_OC1_SetConfig+0xf4>)
8004db6: 4293 cmp r3, r2
8004db8: d10c bne.n 8004dd4 <TIM_OC1_SetConfig+0x88>
{
/* Check parameters */
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC1NP;
8004dba: 697b ldr r3, [r7, #20]
8004dbc: 2208 movs r2, #8
8004dbe: 4393 bics r3, r2
8004dc0: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= OC_Config->OCNPolarity;
8004dc2: 683b ldr r3, [r7, #0]
8004dc4: 68db ldr r3, [r3, #12]
8004dc6: 697a ldr r2, [r7, #20]
8004dc8: 4313 orrs r3, r2
8004dca: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC1NE;
8004dcc: 697b ldr r3, [r7, #20]
8004dce: 2204 movs r2, #4
8004dd0: 4393 bics r3, r2
8004dd2: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
8004dd4: 687b ldr r3, [r7, #4]
8004dd6: 4a18 ldr r2, [pc, #96] ; (8004e38 <TIM_OC1_SetConfig+0xec>)
8004dd8: 4293 cmp r3, r2
8004dda: d007 beq.n 8004dec <TIM_OC1_SetConfig+0xa0>
8004ddc: 687b ldr r3, [r7, #4]
8004dde: 4a17 ldr r2, [pc, #92] ; (8004e3c <TIM_OC1_SetConfig+0xf0>)
8004de0: 4293 cmp r3, r2
8004de2: d003 beq.n 8004dec <TIM_OC1_SetConfig+0xa0>
8004de4: 687b ldr r3, [r7, #4]
8004de6: 4a16 ldr r2, [pc, #88] ; (8004e40 <TIM_OC1_SetConfig+0xf4>)
8004de8: 4293 cmp r3, r2
8004dea: d111 bne.n 8004e10 <TIM_OC1_SetConfig+0xc4>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS1;
8004dec: 693b ldr r3, [r7, #16]
8004dee: 4a15 ldr r2, [pc, #84] ; (8004e44 <TIM_OC1_SetConfig+0xf8>)
8004df0: 4013 ands r3, r2
8004df2: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS1N;
8004df4: 693b ldr r3, [r7, #16]
8004df6: 4a14 ldr r2, [pc, #80] ; (8004e48 <TIM_OC1_SetConfig+0xfc>)
8004df8: 4013 ands r3, r2
8004dfa: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= OC_Config->OCIdleState;
8004dfc: 683b ldr r3, [r7, #0]
8004dfe: 695b ldr r3, [r3, #20]
8004e00: 693a ldr r2, [r7, #16]
8004e02: 4313 orrs r3, r2
8004e04: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= OC_Config->OCNIdleState;
8004e06: 683b ldr r3, [r7, #0]
8004e08: 699b ldr r3, [r3, #24]
8004e0a: 693a ldr r2, [r7, #16]
8004e0c: 4313 orrs r3, r2
8004e0e: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8004e10: 687b ldr r3, [r7, #4]
8004e12: 693a ldr r2, [r7, #16]
8004e14: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
8004e16: 687b ldr r3, [r7, #4]
8004e18: 68fa ldr r2, [r7, #12]
8004e1a: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR1 = OC_Config->Pulse;
8004e1c: 683b ldr r3, [r7, #0]
8004e1e: 685a ldr r2, [r3, #4]
8004e20: 687b ldr r3, [r7, #4]
8004e22: 635a str r2, [r3, #52] ; 0x34
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8004e24: 687b ldr r3, [r7, #4]
8004e26: 697a ldr r2, [r7, #20]
8004e28: 621a str r2, [r3, #32]
}
8004e2a: 46c0 nop ; (mov r8, r8)
8004e2c: 46bd mov sp, r7
8004e2e: b006 add sp, #24
8004e30: bd80 pop {r7, pc}
8004e32: 46c0 nop ; (mov r8, r8)
8004e34: fffeff8f .word 0xfffeff8f
8004e38: 40012c00 .word 0x40012c00
8004e3c: 40014400 .word 0x40014400
8004e40: 40014800 .word 0x40014800
8004e44: fffffeff .word 0xfffffeff
8004e48: fffffdff .word 0xfffffdff
08004e4c <TIM_OC2_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
8004e4c: b580 push {r7, lr}
8004e4e: b086 sub sp, #24
8004e50: af00 add r7, sp, #0
8004e52: 6078 str r0, [r7, #4]
8004e54: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
8004e56: 687b ldr r3, [r7, #4]
8004e58: 6a1b ldr r3, [r3, #32]
8004e5a: 2210 movs r2, #16
8004e5c: 4393 bics r3, r2
8004e5e: 001a movs r2, r3
8004e60: 687b ldr r3, [r7, #4]
8004e62: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8004e64: 687b ldr r3, [r7, #4]
8004e66: 6a1b ldr r3, [r3, #32]
8004e68: 617b str r3, [r7, #20]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8004e6a: 687b ldr r3, [r7, #4]
8004e6c: 685b ldr r3, [r3, #4]
8004e6e: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
8004e70: 687b ldr r3, [r7, #4]
8004e72: 699b ldr r3, [r3, #24]
8004e74: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR1_OC2M;
8004e76: 68fb ldr r3, [r7, #12]
8004e78: 4a2c ldr r2, [pc, #176] ; (8004f2c <TIM_OC2_SetConfig+0xe0>)
8004e7a: 4013 ands r3, r2
8004e7c: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC2S;
8004e7e: 68fb ldr r3, [r7, #12]
8004e80: 4a2b ldr r2, [pc, #172] ; (8004f30 <TIM_OC2_SetConfig+0xe4>)
8004e82: 4013 ands r3, r2
8004e84: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
8004e86: 683b ldr r3, [r7, #0]
8004e88: 681b ldr r3, [r3, #0]
8004e8a: 021b lsls r3, r3, #8
8004e8c: 68fa ldr r2, [r7, #12]
8004e8e: 4313 orrs r3, r2
8004e90: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC2P;
8004e92: 697b ldr r3, [r7, #20]
8004e94: 2220 movs r2, #32
8004e96: 4393 bics r3, r2
8004e98: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 4U);
8004e9a: 683b ldr r3, [r7, #0]
8004e9c: 689b ldr r3, [r3, #8]
8004e9e: 011b lsls r3, r3, #4
8004ea0: 697a ldr r2, [r7, #20]
8004ea2: 4313 orrs r3, r2
8004ea4: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
8004ea6: 687b ldr r3, [r7, #4]
8004ea8: 4a22 ldr r2, [pc, #136] ; (8004f34 <TIM_OC2_SetConfig+0xe8>)
8004eaa: 4293 cmp r3, r2
8004eac: d10d bne.n 8004eca <TIM_OC2_SetConfig+0x7e>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC2NP;
8004eae: 697b ldr r3, [r7, #20]
8004eb0: 2280 movs r2, #128 ; 0x80
8004eb2: 4393 bics r3, r2
8004eb4: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 4U);
8004eb6: 683b ldr r3, [r7, #0]
8004eb8: 68db ldr r3, [r3, #12]
8004eba: 011b lsls r3, r3, #4
8004ebc: 697a ldr r2, [r7, #20]
8004ebe: 4313 orrs r3, r2
8004ec0: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC2NE;
8004ec2: 697b ldr r3, [r7, #20]
8004ec4: 2240 movs r2, #64 ; 0x40
8004ec6: 4393 bics r3, r2
8004ec8: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
8004eca: 687b ldr r3, [r7, #4]
8004ecc: 4a19 ldr r2, [pc, #100] ; (8004f34 <TIM_OC2_SetConfig+0xe8>)
8004ece: 4293 cmp r3, r2
8004ed0: d007 beq.n 8004ee2 <TIM_OC2_SetConfig+0x96>
8004ed2: 687b ldr r3, [r7, #4]
8004ed4: 4a18 ldr r2, [pc, #96] ; (8004f38 <TIM_OC2_SetConfig+0xec>)
8004ed6: 4293 cmp r3, r2
8004ed8: d003 beq.n 8004ee2 <TIM_OC2_SetConfig+0x96>
8004eda: 687b ldr r3, [r7, #4]
8004edc: 4a17 ldr r2, [pc, #92] ; (8004f3c <TIM_OC2_SetConfig+0xf0>)
8004ede: 4293 cmp r3, r2
8004ee0: d113 bne.n 8004f0a <TIM_OC2_SetConfig+0xbe>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS2;
8004ee2: 693b ldr r3, [r7, #16]
8004ee4: 4a16 ldr r2, [pc, #88] ; (8004f40 <TIM_OC2_SetConfig+0xf4>)
8004ee6: 4013 ands r3, r2
8004ee8: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS2N;
8004eea: 693b ldr r3, [r7, #16]
8004eec: 4a15 ldr r2, [pc, #84] ; (8004f44 <TIM_OC2_SetConfig+0xf8>)
8004eee: 4013 ands r3, r2
8004ef0: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 2U);
8004ef2: 683b ldr r3, [r7, #0]
8004ef4: 695b ldr r3, [r3, #20]
8004ef6: 009b lsls r3, r3, #2
8004ef8: 693a ldr r2, [r7, #16]
8004efa: 4313 orrs r3, r2
8004efc: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 2U);
8004efe: 683b ldr r3, [r7, #0]
8004f00: 699b ldr r3, [r3, #24]
8004f02: 009b lsls r3, r3, #2
8004f04: 693a ldr r2, [r7, #16]
8004f06: 4313 orrs r3, r2
8004f08: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8004f0a: 687b ldr r3, [r7, #4]
8004f0c: 693a ldr r2, [r7, #16]
8004f0e: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
8004f10: 687b ldr r3, [r7, #4]
8004f12: 68fa ldr r2, [r7, #12]
8004f14: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR2 = OC_Config->Pulse;
8004f16: 683b ldr r3, [r7, #0]
8004f18: 685a ldr r2, [r3, #4]
8004f1a: 687b ldr r3, [r7, #4]
8004f1c: 639a str r2, [r3, #56] ; 0x38
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8004f1e: 687b ldr r3, [r7, #4]
8004f20: 697a ldr r2, [r7, #20]
8004f22: 621a str r2, [r3, #32]
}
8004f24: 46c0 nop ; (mov r8, r8)
8004f26: 46bd mov sp, r7
8004f28: b006 add sp, #24
8004f2a: bd80 pop {r7, pc}
8004f2c: feff8fff .word 0xfeff8fff
8004f30: fffffcff .word 0xfffffcff
8004f34: 40012c00 .word 0x40012c00
8004f38: 40014400 .word 0x40014400
8004f3c: 40014800 .word 0x40014800
8004f40: fffffbff .word 0xfffffbff
8004f44: fffff7ff .word 0xfffff7ff
08004f48 <TIM_OC3_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
8004f48: b580 push {r7, lr}
8004f4a: b086 sub sp, #24
8004f4c: af00 add r7, sp, #0
8004f4e: 6078 str r0, [r7, #4]
8004f50: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 3: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC3E;
8004f52: 687b ldr r3, [r7, #4]
8004f54: 6a1b ldr r3, [r3, #32]
8004f56: 4a33 ldr r2, [pc, #204] ; (8005024 <TIM_OC3_SetConfig+0xdc>)
8004f58: 401a ands r2, r3
8004f5a: 687b ldr r3, [r7, #4]
8004f5c: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8004f5e: 687b ldr r3, [r7, #4]
8004f60: 6a1b ldr r3, [r3, #32]
8004f62: 617b str r3, [r7, #20]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8004f64: 687b ldr r3, [r7, #4]
8004f66: 685b ldr r3, [r3, #4]
8004f68: 613b str r3, [r7, #16]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
8004f6a: 687b ldr r3, [r7, #4]
8004f6c: 69db ldr r3, [r3, #28]
8004f6e: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC3M;
8004f70: 68fb ldr r3, [r7, #12]
8004f72: 4a2d ldr r2, [pc, #180] ; (8005028 <TIM_OC3_SetConfig+0xe0>)
8004f74: 4013 ands r3, r2
8004f76: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC3S;
8004f78: 68fb ldr r3, [r7, #12]
8004f7a: 2203 movs r2, #3
8004f7c: 4393 bics r3, r2
8004f7e: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
8004f80: 683b ldr r3, [r7, #0]
8004f82: 681b ldr r3, [r3, #0]
8004f84: 68fa ldr r2, [r7, #12]
8004f86: 4313 orrs r3, r2
8004f88: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC3P;
8004f8a: 697b ldr r3, [r7, #20]
8004f8c: 4a27 ldr r2, [pc, #156] ; (800502c <TIM_OC3_SetConfig+0xe4>)
8004f8e: 4013 ands r3, r2
8004f90: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 8U);
8004f92: 683b ldr r3, [r7, #0]
8004f94: 689b ldr r3, [r3, #8]
8004f96: 021b lsls r3, r3, #8
8004f98: 697a ldr r2, [r7, #20]
8004f9a: 4313 orrs r3, r2
8004f9c: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
8004f9e: 687b ldr r3, [r7, #4]
8004fa0: 4a23 ldr r2, [pc, #140] ; (8005030 <TIM_OC3_SetConfig+0xe8>)
8004fa2: 4293 cmp r3, r2
8004fa4: d10d bne.n 8004fc2 <TIM_OC3_SetConfig+0x7a>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC3NP;
8004fa6: 697b ldr r3, [r7, #20]
8004fa8: 4a22 ldr r2, [pc, #136] ; (8005034 <TIM_OC3_SetConfig+0xec>)
8004faa: 4013 ands r3, r2
8004fac: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 8U);
8004fae: 683b ldr r3, [r7, #0]
8004fb0: 68db ldr r3, [r3, #12]
8004fb2: 021b lsls r3, r3, #8
8004fb4: 697a ldr r2, [r7, #20]
8004fb6: 4313 orrs r3, r2
8004fb8: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC3NE;
8004fba: 697b ldr r3, [r7, #20]
8004fbc: 4a1e ldr r2, [pc, #120] ; (8005038 <TIM_OC3_SetConfig+0xf0>)
8004fbe: 4013 ands r3, r2
8004fc0: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
8004fc2: 687b ldr r3, [r7, #4]
8004fc4: 4a1a ldr r2, [pc, #104] ; (8005030 <TIM_OC3_SetConfig+0xe8>)
8004fc6: 4293 cmp r3, r2
8004fc8: d007 beq.n 8004fda <TIM_OC3_SetConfig+0x92>
8004fca: 687b ldr r3, [r7, #4]
8004fcc: 4a1b ldr r2, [pc, #108] ; (800503c <TIM_OC3_SetConfig+0xf4>)
8004fce: 4293 cmp r3, r2
8004fd0: d003 beq.n 8004fda <TIM_OC3_SetConfig+0x92>
8004fd2: 687b ldr r3, [r7, #4]
8004fd4: 4a1a ldr r2, [pc, #104] ; (8005040 <TIM_OC3_SetConfig+0xf8>)
8004fd6: 4293 cmp r3, r2
8004fd8: d113 bne.n 8005002 <TIM_OC3_SetConfig+0xba>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS3;
8004fda: 693b ldr r3, [r7, #16]
8004fdc: 4a19 ldr r2, [pc, #100] ; (8005044 <TIM_OC3_SetConfig+0xfc>)
8004fde: 4013 ands r3, r2
8004fe0: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS3N;
8004fe2: 693b ldr r3, [r7, #16]
8004fe4: 4a18 ldr r2, [pc, #96] ; (8005048 <TIM_OC3_SetConfig+0x100>)
8004fe6: 4013 ands r3, r2
8004fe8: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 4U);
8004fea: 683b ldr r3, [r7, #0]
8004fec: 695b ldr r3, [r3, #20]
8004fee: 011b lsls r3, r3, #4
8004ff0: 693a ldr r2, [r7, #16]
8004ff2: 4313 orrs r3, r2
8004ff4: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 4U);
8004ff6: 683b ldr r3, [r7, #0]
8004ff8: 699b ldr r3, [r3, #24]
8004ffa: 011b lsls r3, r3, #4
8004ffc: 693a ldr r2, [r7, #16]
8004ffe: 4313 orrs r3, r2
8005000: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8005002: 687b ldr r3, [r7, #4]
8005004: 693a ldr r2, [r7, #16]
8005006: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
8005008: 687b ldr r3, [r7, #4]
800500a: 68fa ldr r2, [r7, #12]
800500c: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR3 = OC_Config->Pulse;
800500e: 683b ldr r3, [r7, #0]
8005010: 685a ldr r2, [r3, #4]
8005012: 687b ldr r3, [r7, #4]
8005014: 63da str r2, [r3, #60] ; 0x3c
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8005016: 687b ldr r3, [r7, #4]
8005018: 697a ldr r2, [r7, #20]
800501a: 621a str r2, [r3, #32]
}
800501c: 46c0 nop ; (mov r8, r8)
800501e: 46bd mov sp, r7
8005020: b006 add sp, #24
8005022: bd80 pop {r7, pc}
8005024: fffffeff .word 0xfffffeff
8005028: fffeff8f .word 0xfffeff8f
800502c: fffffdff .word 0xfffffdff
8005030: 40012c00 .word 0x40012c00
8005034: fffff7ff .word 0xfffff7ff
8005038: fffffbff .word 0xfffffbff
800503c: 40014400 .word 0x40014400
8005040: 40014800 .word 0x40014800
8005044: ffffefff .word 0xffffefff
8005048: ffffdfff .word 0xffffdfff
0800504c <TIM_OC4_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
800504c: b580 push {r7, lr}
800504e: b086 sub sp, #24
8005050: af00 add r7, sp, #0
8005052: 6078 str r0, [r7, #4]
8005054: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 4: Reset the CC4E Bit */
TIMx->CCER &= ~TIM_CCER_CC4E;
8005056: 687b ldr r3, [r7, #4]
8005058: 6a1b ldr r3, [r3, #32]
800505a: 4a26 ldr r2, [pc, #152] ; (80050f4 <TIM_OC4_SetConfig+0xa8>)
800505c: 401a ands r2, r3
800505e: 687b ldr r3, [r7, #4]
8005060: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8005062: 687b ldr r3, [r7, #4]
8005064: 6a1b ldr r3, [r3, #32]
8005066: 613b str r3, [r7, #16]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8005068: 687b ldr r3, [r7, #4]
800506a: 685b ldr r3, [r3, #4]
800506c: 617b str r3, [r7, #20]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
800506e: 687b ldr r3, [r7, #4]
8005070: 69db ldr r3, [r3, #28]
8005072: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC4M;
8005074: 68fb ldr r3, [r7, #12]
8005076: 4a20 ldr r2, [pc, #128] ; (80050f8 <TIM_OC4_SetConfig+0xac>)
8005078: 4013 ands r3, r2
800507a: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC4S;
800507c: 68fb ldr r3, [r7, #12]
800507e: 4a1f ldr r2, [pc, #124] ; (80050fc <TIM_OC4_SetConfig+0xb0>)
8005080: 4013 ands r3, r2
8005082: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
8005084: 683b ldr r3, [r7, #0]
8005086: 681b ldr r3, [r3, #0]
8005088: 021b lsls r3, r3, #8
800508a: 68fa ldr r2, [r7, #12]
800508c: 4313 orrs r3, r2
800508e: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC4P;
8005090: 693b ldr r3, [r7, #16]
8005092: 4a1b ldr r2, [pc, #108] ; (8005100 <TIM_OC4_SetConfig+0xb4>)
8005094: 4013 ands r3, r2
8005096: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 12U);
8005098: 683b ldr r3, [r7, #0]
800509a: 689b ldr r3, [r3, #8]
800509c: 031b lsls r3, r3, #12
800509e: 693a ldr r2, [r7, #16]
80050a0: 4313 orrs r3, r2
80050a2: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
80050a4: 687b ldr r3, [r7, #4]
80050a6: 4a17 ldr r2, [pc, #92] ; (8005104 <TIM_OC4_SetConfig+0xb8>)
80050a8: 4293 cmp r3, r2
80050aa: d007 beq.n 80050bc <TIM_OC4_SetConfig+0x70>
80050ac: 687b ldr r3, [r7, #4]
80050ae: 4a16 ldr r2, [pc, #88] ; (8005108 <TIM_OC4_SetConfig+0xbc>)
80050b0: 4293 cmp r3, r2
80050b2: d003 beq.n 80050bc <TIM_OC4_SetConfig+0x70>
80050b4: 687b ldr r3, [r7, #4]
80050b6: 4a15 ldr r2, [pc, #84] ; (800510c <TIM_OC4_SetConfig+0xc0>)
80050b8: 4293 cmp r3, r2
80050ba: d109 bne.n 80050d0 <TIM_OC4_SetConfig+0x84>
{
/* Check parameters */
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS4;
80050bc: 697b ldr r3, [r7, #20]
80050be: 4a14 ldr r2, [pc, #80] ; (8005110 <TIM_OC4_SetConfig+0xc4>)
80050c0: 4013 ands r3, r2
80050c2: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 6U);
80050c4: 683b ldr r3, [r7, #0]
80050c6: 695b ldr r3, [r3, #20]
80050c8: 019b lsls r3, r3, #6
80050ca: 697a ldr r2, [r7, #20]
80050cc: 4313 orrs r3, r2
80050ce: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
80050d0: 687b ldr r3, [r7, #4]
80050d2: 697a ldr r2, [r7, #20]
80050d4: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
80050d6: 687b ldr r3, [r7, #4]
80050d8: 68fa ldr r2, [r7, #12]
80050da: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR4 = OC_Config->Pulse;
80050dc: 683b ldr r3, [r7, #0]
80050de: 685a ldr r2, [r3, #4]
80050e0: 687b ldr r3, [r7, #4]
80050e2: 641a str r2, [r3, #64] ; 0x40
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
80050e4: 687b ldr r3, [r7, #4]
80050e6: 693a ldr r2, [r7, #16]
80050e8: 621a str r2, [r3, #32]
}
80050ea: 46c0 nop ; (mov r8, r8)
80050ec: 46bd mov sp, r7
80050ee: b006 add sp, #24
80050f0: bd80 pop {r7, pc}
80050f2: 46c0 nop ; (mov r8, r8)
80050f4: ffffefff .word 0xffffefff
80050f8: feff8fff .word 0xfeff8fff
80050fc: fffffcff .word 0xfffffcff
8005100: ffffdfff .word 0xffffdfff
8005104: 40012c00 .word 0x40012c00
8005108: 40014400 .word 0x40014400
800510c: 40014800 .word 0x40014800
8005110: ffffbfff .word 0xffffbfff
08005114 <TIM_OC5_SetConfig>:
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
const TIM_OC_InitTypeDef *OC_Config)
{
8005114: b580 push {r7, lr}
8005116: b086 sub sp, #24
8005118: af00 add r7, sp, #0
800511a: 6078 str r0, [r7, #4]
800511c: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the output: Reset the CCxE Bit */
TIMx->CCER &= ~TIM_CCER_CC5E;
800511e: 687b ldr r3, [r7, #4]
8005120: 6a1b ldr r3, [r3, #32]
8005122: 4a23 ldr r2, [pc, #140] ; (80051b0 <TIM_OC5_SetConfig+0x9c>)
8005124: 401a ands r2, r3
8005126: 687b ldr r3, [r7, #4]
8005128: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
800512a: 687b ldr r3, [r7, #4]
800512c: 6a1b ldr r3, [r3, #32]
800512e: 613b str r3, [r7, #16]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8005130: 687b ldr r3, [r7, #4]
8005132: 685b ldr r3, [r3, #4]
8005134: 617b str r3, [r7, #20]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR3;
8005136: 687b ldr r3, [r7, #4]
8005138: 6d5b ldr r3, [r3, #84] ; 0x54
800513a: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~(TIM_CCMR3_OC5M);
800513c: 68fb ldr r3, [r7, #12]
800513e: 4a1d ldr r2, [pc, #116] ; (80051b4 <TIM_OC5_SetConfig+0xa0>)
8005140: 4013 ands r3, r2
8005142: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
8005144: 683b ldr r3, [r7, #0]
8005146: 681b ldr r3, [r3, #0]
8005148: 68fa ldr r2, [r7, #12]
800514a: 4313 orrs r3, r2
800514c: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC5P;
800514e: 693b ldr r3, [r7, #16]
8005150: 4a19 ldr r2, [pc, #100] ; (80051b8 <TIM_OC5_SetConfig+0xa4>)
8005152: 4013 ands r3, r2
8005154: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 16U);
8005156: 683b ldr r3, [r7, #0]
8005158: 689b ldr r3, [r3, #8]
800515a: 041b lsls r3, r3, #16
800515c: 693a ldr r2, [r7, #16]
800515e: 4313 orrs r3, r2
8005160: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
8005162: 687b ldr r3, [r7, #4]
8005164: 4a15 ldr r2, [pc, #84] ; (80051bc <TIM_OC5_SetConfig+0xa8>)
8005166: 4293 cmp r3, r2
8005168: d007 beq.n 800517a <TIM_OC5_SetConfig+0x66>
800516a: 687b ldr r3, [r7, #4]
800516c: 4a14 ldr r2, [pc, #80] ; (80051c0 <TIM_OC5_SetConfig+0xac>)
800516e: 4293 cmp r3, r2
8005170: d003 beq.n 800517a <TIM_OC5_SetConfig+0x66>
8005172: 687b ldr r3, [r7, #4]
8005174: 4a13 ldr r2, [pc, #76] ; (80051c4 <TIM_OC5_SetConfig+0xb0>)
8005176: 4293 cmp r3, r2
8005178: d109 bne.n 800518e <TIM_OC5_SetConfig+0x7a>
{
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS5;
800517a: 697b ldr r3, [r7, #20]
800517c: 4a0c ldr r2, [pc, #48] ; (80051b0 <TIM_OC5_SetConfig+0x9c>)
800517e: 4013 ands r3, r2
8005180: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 8U);
8005182: 683b ldr r3, [r7, #0]
8005184: 695b ldr r3, [r3, #20]
8005186: 021b lsls r3, r3, #8
8005188: 697a ldr r2, [r7, #20]
800518a: 4313 orrs r3, r2
800518c: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
800518e: 687b ldr r3, [r7, #4]
8005190: 697a ldr r2, [r7, #20]
8005192: 605a str r2, [r3, #4]
/* Write to TIMx CCMR3 */
TIMx->CCMR3 = tmpccmrx;
8005194: 687b ldr r3, [r7, #4]
8005196: 68fa ldr r2, [r7, #12]
8005198: 655a str r2, [r3, #84] ; 0x54
/* Set the Capture Compare Register value */
TIMx->CCR5 = OC_Config->Pulse;
800519a: 683b ldr r3, [r7, #0]
800519c: 685a ldr r2, [r3, #4]
800519e: 687b ldr r3, [r7, #4]
80051a0: 659a str r2, [r3, #88] ; 0x58
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
80051a2: 687b ldr r3, [r7, #4]
80051a4: 693a ldr r2, [r7, #16]
80051a6: 621a str r2, [r3, #32]
}
80051a8: 46c0 nop ; (mov r8, r8)
80051aa: 46bd mov sp, r7
80051ac: b006 add sp, #24
80051ae: bd80 pop {r7, pc}
80051b0: fffeffff .word 0xfffeffff
80051b4: fffeff8f .word 0xfffeff8f
80051b8: fffdffff .word 0xfffdffff
80051bc: 40012c00 .word 0x40012c00
80051c0: 40014400 .word 0x40014400
80051c4: 40014800 .word 0x40014800
080051c8 <TIM_OC6_SetConfig>:
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
const TIM_OC_InitTypeDef *OC_Config)
{
80051c8: b580 push {r7, lr}
80051ca: b086 sub sp, #24
80051cc: af00 add r7, sp, #0
80051ce: 6078 str r0, [r7, #4]
80051d0: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the output: Reset the CCxE Bit */
TIMx->CCER &= ~TIM_CCER_CC6E;
80051d2: 687b ldr r3, [r7, #4]
80051d4: 6a1b ldr r3, [r3, #32]
80051d6: 4a24 ldr r2, [pc, #144] ; (8005268 <TIM_OC6_SetConfig+0xa0>)
80051d8: 401a ands r2, r3
80051da: 687b ldr r3, [r7, #4]
80051dc: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
80051de: 687b ldr r3, [r7, #4]
80051e0: 6a1b ldr r3, [r3, #32]
80051e2: 613b str r3, [r7, #16]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
80051e4: 687b ldr r3, [r7, #4]
80051e6: 685b ldr r3, [r3, #4]
80051e8: 617b str r3, [r7, #20]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR3;
80051ea: 687b ldr r3, [r7, #4]
80051ec: 6d5b ldr r3, [r3, #84] ; 0x54
80051ee: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~(TIM_CCMR3_OC6M);
80051f0: 68fb ldr r3, [r7, #12]
80051f2: 4a1e ldr r2, [pc, #120] ; (800526c <TIM_OC6_SetConfig+0xa4>)
80051f4: 4013 ands r3, r2
80051f6: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
80051f8: 683b ldr r3, [r7, #0]
80051fa: 681b ldr r3, [r3, #0]
80051fc: 021b lsls r3, r3, #8
80051fe: 68fa ldr r2, [r7, #12]
8005200: 4313 orrs r3, r2
8005202: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= (uint32_t)~TIM_CCER_CC6P;
8005204: 693b ldr r3, [r7, #16]
8005206: 4a1a ldr r2, [pc, #104] ; (8005270 <TIM_OC6_SetConfig+0xa8>)
8005208: 4013 ands r3, r2
800520a: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 20U);
800520c: 683b ldr r3, [r7, #0]
800520e: 689b ldr r3, [r3, #8]
8005210: 051b lsls r3, r3, #20
8005212: 693a ldr r2, [r7, #16]
8005214: 4313 orrs r3, r2
8005216: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
8005218: 687b ldr r3, [r7, #4]
800521a: 4a16 ldr r2, [pc, #88] ; (8005274 <TIM_OC6_SetConfig+0xac>)
800521c: 4293 cmp r3, r2
800521e: d007 beq.n 8005230 <TIM_OC6_SetConfig+0x68>
8005220: 687b ldr r3, [r7, #4]
8005222: 4a15 ldr r2, [pc, #84] ; (8005278 <TIM_OC6_SetConfig+0xb0>)
8005224: 4293 cmp r3, r2
8005226: d003 beq.n 8005230 <TIM_OC6_SetConfig+0x68>
8005228: 687b ldr r3, [r7, #4]
800522a: 4a14 ldr r2, [pc, #80] ; (800527c <TIM_OC6_SetConfig+0xb4>)
800522c: 4293 cmp r3, r2
800522e: d109 bne.n 8005244 <TIM_OC6_SetConfig+0x7c>
{
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS6;
8005230: 697b ldr r3, [r7, #20]
8005232: 4a13 ldr r2, [pc, #76] ; (8005280 <TIM_OC6_SetConfig+0xb8>)
8005234: 4013 ands r3, r2
8005236: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 10U);
8005238: 683b ldr r3, [r7, #0]
800523a: 695b ldr r3, [r3, #20]
800523c: 029b lsls r3, r3, #10
800523e: 697a ldr r2, [r7, #20]
8005240: 4313 orrs r3, r2
8005242: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8005244: 687b ldr r3, [r7, #4]
8005246: 697a ldr r2, [r7, #20]
8005248: 605a str r2, [r3, #4]
/* Write to TIMx CCMR3 */
TIMx->CCMR3 = tmpccmrx;
800524a: 687b ldr r3, [r7, #4]
800524c: 68fa ldr r2, [r7, #12]
800524e: 655a str r2, [r3, #84] ; 0x54
/* Set the Capture Compare Register value */
TIMx->CCR6 = OC_Config->Pulse;
8005250: 683b ldr r3, [r7, #0]
8005252: 685a ldr r2, [r3, #4]
8005254: 687b ldr r3, [r7, #4]
8005256: 65da str r2, [r3, #92] ; 0x5c
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8005258: 687b ldr r3, [r7, #4]
800525a: 693a ldr r2, [r7, #16]
800525c: 621a str r2, [r3, #32]
}
800525e: 46c0 nop ; (mov r8, r8)
8005260: 46bd mov sp, r7
8005262: b006 add sp, #24
8005264: bd80 pop {r7, pc}
8005266: 46c0 nop ; (mov r8, r8)
8005268: ffefffff .word 0xffefffff
800526c: feff8fff .word 0xfeff8fff
8005270: ffdfffff .word 0xffdfffff
8005274: 40012c00 .word 0x40012c00
8005278: 40014400 .word 0x40014400
800527c: 40014800 .word 0x40014800
8005280: fffbffff .word 0xfffbffff
08005284 <TIM_CCxChannelCmd>:
* @param ChannelState specifies the TIM Channel CCxE bit new state.
* This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
* @retval None
*/
void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
{
8005284: b580 push {r7, lr}
8005286: b086 sub sp, #24
8005288: af00 add r7, sp, #0
800528a: 60f8 str r0, [r7, #12]
800528c: 60b9 str r1, [r7, #8]
800528e: 607a str r2, [r7, #4]
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(TIMx));
assert_param(IS_TIM_CHANNELS(Channel));
tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
8005290: 68bb ldr r3, [r7, #8]
8005292: 221f movs r2, #31
8005294: 4013 ands r3, r2
8005296: 2201 movs r2, #1
8005298: 409a lsls r2, r3
800529a: 0013 movs r3, r2
800529c: 617b str r3, [r7, #20]
/* Reset the CCxE Bit */
TIMx->CCER &= ~tmp;
800529e: 68fb ldr r3, [r7, #12]
80052a0: 6a1b ldr r3, [r3, #32]
80052a2: 697a ldr r2, [r7, #20]
80052a4: 43d2 mvns r2, r2
80052a6: 401a ands r2, r3
80052a8: 68fb ldr r3, [r7, #12]
80052aa: 621a str r2, [r3, #32]
/* Set or reset the CCxE Bit */
TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
80052ac: 68fb ldr r3, [r7, #12]
80052ae: 6a1a ldr r2, [r3, #32]
80052b0: 68bb ldr r3, [r7, #8]
80052b2: 211f movs r1, #31
80052b4: 400b ands r3, r1
80052b6: 6879 ldr r1, [r7, #4]
80052b8: 4099 lsls r1, r3
80052ba: 000b movs r3, r1
80052bc: 431a orrs r2, r3
80052be: 68fb ldr r3, [r7, #12]
80052c0: 621a str r2, [r3, #32]
}
80052c2: 46c0 nop ; (mov r8, r8)
80052c4: 46bd mov sp, r7
80052c6: b006 add sp, #24
80052c8: bd80 pop {r7, pc}
...
080052cc <HAL_TIMEx_MasterConfigSynchronization>:
* mode.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
const TIM_MasterConfigTypeDef *sMasterConfig)
{
80052cc: b580 push {r7, lr}
80052ce: b084 sub sp, #16
80052d0: af00 add r7, sp, #0
80052d2: 6078 str r0, [r7, #4]
80052d4: 6039 str r1, [r7, #0]
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
/* Check input state */
__HAL_LOCK(htim);
80052d6: 687b ldr r3, [r7, #4]
80052d8: 223c movs r2, #60 ; 0x3c
80052da: 5c9b ldrb r3, [r3, r2]
80052dc: 2b01 cmp r3, #1
80052de: d101 bne.n 80052e4 <HAL_TIMEx_MasterConfigSynchronization+0x18>
80052e0: 2302 movs r3, #2
80052e2: e050 b.n 8005386 <HAL_TIMEx_MasterConfigSynchronization+0xba>
80052e4: 687b ldr r3, [r7, #4]
80052e6: 223c movs r2, #60 ; 0x3c
80052e8: 2101 movs r1, #1
80052ea: 5499 strb r1, [r3, r2]
/* Change the handler state */
htim->State = HAL_TIM_STATE_BUSY;
80052ec: 687b ldr r3, [r7, #4]
80052ee: 223d movs r2, #61 ; 0x3d
80052f0: 2102 movs r1, #2
80052f2: 5499 strb r1, [r3, r2]
/* Get the TIMx CR2 register value */
tmpcr2 = htim->Instance->CR2;
80052f4: 687b ldr r3, [r7, #4]
80052f6: 681b ldr r3, [r3, #0]
80052f8: 685b ldr r3, [r3, #4]
80052fa: 60fb str r3, [r7, #12]
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
80052fc: 687b ldr r3, [r7, #4]
80052fe: 681b ldr r3, [r3, #0]
8005300: 689b ldr r3, [r3, #8]
8005302: 60bb str r3, [r7, #8]
/* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
8005304: 687b ldr r3, [r7, #4]
8005306: 681b ldr r3, [r3, #0]
8005308: 4a21 ldr r2, [pc, #132] ; (8005390 <HAL_TIMEx_MasterConfigSynchronization+0xc4>)
800530a: 4293 cmp r3, r2
800530c: d108 bne.n 8005320 <HAL_TIMEx_MasterConfigSynchronization+0x54>
{
/* Check the parameters */
assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
/* Clear the MMS2 bits */
tmpcr2 &= ~TIM_CR2_MMS2;
800530e: 68fb ldr r3, [r7, #12]
8005310: 4a20 ldr r2, [pc, #128] ; (8005394 <HAL_TIMEx_MasterConfigSynchronization+0xc8>)
8005312: 4013 ands r3, r2
8005314: 60fb str r3, [r7, #12]
/* Select the TRGO2 source*/
tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
8005316: 683b ldr r3, [r7, #0]
8005318: 685b ldr r3, [r3, #4]
800531a: 68fa ldr r2, [r7, #12]
800531c: 4313 orrs r3, r2
800531e: 60fb str r3, [r7, #12]
}
/* Reset the MMS Bits */
tmpcr2 &= ~TIM_CR2_MMS;
8005320: 68fb ldr r3, [r7, #12]
8005322: 2270 movs r2, #112 ; 0x70
8005324: 4393 bics r3, r2
8005326: 60fb str r3, [r7, #12]
/* Select the TRGO source */
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
8005328: 683b ldr r3, [r7, #0]
800532a: 681b ldr r3, [r3, #0]
800532c: 68fa ldr r2, [r7, #12]
800532e: 4313 orrs r3, r2
8005330: 60fb str r3, [r7, #12]
/* Update TIMx CR2 */
htim->Instance->CR2 = tmpcr2;
8005332: 687b ldr r3, [r7, #4]
8005334: 681b ldr r3, [r3, #0]
8005336: 68fa ldr r2, [r7, #12]
8005338: 605a str r2, [r3, #4]
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
800533a: 687b ldr r3, [r7, #4]
800533c: 681b ldr r3, [r3, #0]
800533e: 4a14 ldr r2, [pc, #80] ; (8005390 <HAL_TIMEx_MasterConfigSynchronization+0xc4>)
8005340: 4293 cmp r3, r2
8005342: d00a beq.n 800535a <HAL_TIMEx_MasterConfigSynchronization+0x8e>
8005344: 687b ldr r3, [r7, #4]
8005346: 681a ldr r2, [r3, #0]
8005348: 2380 movs r3, #128 ; 0x80
800534a: 05db lsls r3, r3, #23
800534c: 429a cmp r2, r3
800534e: d004 beq.n 800535a <HAL_TIMEx_MasterConfigSynchronization+0x8e>
8005350: 687b ldr r3, [r7, #4]
8005352: 681b ldr r3, [r3, #0]
8005354: 4a10 ldr r2, [pc, #64] ; (8005398 <HAL_TIMEx_MasterConfigSynchronization+0xcc>)
8005356: 4293 cmp r3, r2
8005358: d10c bne.n 8005374 <HAL_TIMEx_MasterConfigSynchronization+0xa8>
{
/* Reset the MSM Bit */
tmpsmcr &= ~TIM_SMCR_MSM;
800535a: 68bb ldr r3, [r7, #8]
800535c: 2280 movs r2, #128 ; 0x80
800535e: 4393 bics r3, r2
8005360: 60bb str r3, [r7, #8]
/* Set master mode */
tmpsmcr |= sMasterConfig->MasterSlaveMode;
8005362: 683b ldr r3, [r7, #0]
8005364: 689b ldr r3, [r3, #8]
8005366: 68ba ldr r2, [r7, #8]
8005368: 4313 orrs r3, r2
800536a: 60bb str r3, [r7, #8]
/* Update TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
800536c: 687b ldr r3, [r7, #4]
800536e: 681b ldr r3, [r3, #0]
8005370: 68ba ldr r2, [r7, #8]
8005372: 609a str r2, [r3, #8]
}
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
8005374: 687b ldr r3, [r7, #4]
8005376: 223d movs r2, #61 ; 0x3d
8005378: 2101 movs r1, #1
800537a: 5499 strb r1, [r3, r2]
__HAL_UNLOCK(htim);
800537c: 687b ldr r3, [r7, #4]
800537e: 223c movs r2, #60 ; 0x3c
8005380: 2100 movs r1, #0
8005382: 5499 strb r1, [r3, r2]
return HAL_OK;
8005384: 2300 movs r3, #0
}
8005386: 0018 movs r0, r3
8005388: 46bd mov sp, r7
800538a: b004 add sp, #16
800538c: bd80 pop {r7, pc}
800538e: 46c0 nop ; (mov r8, r8)
8005390: 40012c00 .word 0x40012c00
8005394: ff0fffff .word 0xff0fffff
8005398: 40000400 .word 0x40000400
0800539c <HAL_UART_Init>:
* parameters in the UART_InitTypeDef and initialize the associated handle.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
800539c: b580 push {r7, lr}
800539e: b082 sub sp, #8
80053a0: af00 add r7, sp, #0
80053a2: 6078 str r0, [r7, #4]
/* Check the UART handle allocation */
if (huart == NULL)
80053a4: 687b ldr r3, [r7, #4]
80053a6: 2b00 cmp r3, #0
80053a8: d101 bne.n 80053ae <HAL_UART_Init+0x12>
{
return HAL_ERROR;
80053aa: 2301 movs r3, #1
80053ac: e046 b.n 800543c <HAL_UART_Init+0xa0>
{
/* Check the parameters */
assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
}
if (huart->gState == HAL_UART_STATE_RESET)
80053ae: 687b ldr r3, [r7, #4]
80053b0: 2284 movs r2, #132 ; 0x84
80053b2: 589b ldr r3, [r3, r2]
80053b4: 2b00 cmp r3, #0
80053b6: d107 bne.n 80053c8 <HAL_UART_Init+0x2c>
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
80053b8: 687b ldr r3, [r7, #4]
80053ba: 2280 movs r2, #128 ; 0x80
80053bc: 2100 movs r1, #0
80053be: 5499 strb r1, [r3, r2]
/* Init the low level hardware */
huart->MspInitCallback(huart);
#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
80053c0: 687b ldr r3, [r7, #4]
80053c2: 0018 movs r0, r3
80053c4: f7fc faa8 bl 8001918 <HAL_UART_MspInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
80053c8: 687b ldr r3, [r7, #4]
80053ca: 2284 movs r2, #132 ; 0x84
80053cc: 2124 movs r1, #36 ; 0x24
80053ce: 5099 str r1, [r3, r2]
__HAL_UART_DISABLE(huart);
80053d0: 687b ldr r3, [r7, #4]
80053d2: 681b ldr r3, [r3, #0]
80053d4: 681a ldr r2, [r3, #0]
80053d6: 687b ldr r3, [r7, #4]
80053d8: 681b ldr r3, [r3, #0]
80053da: 2101 movs r1, #1
80053dc: 438a bics r2, r1
80053de: 601a str r2, [r3, #0]
/* Set the UART Communication parameters */
if (UART_SetConfig(huart) == HAL_ERROR)
80053e0: 687b ldr r3, [r7, #4]
80053e2: 0018 movs r0, r3
80053e4: f000 fc6e bl 8005cc4 <UART_SetConfig>
80053e8: 0003 movs r3, r0
80053ea: 2b01 cmp r3, #1
80053ec: d101 bne.n 80053f2 <HAL_UART_Init+0x56>
{
return HAL_ERROR;
80053ee: 2301 movs r3, #1
80053f0: e024 b.n 800543c <HAL_UART_Init+0xa0>
}
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
80053f2: 687b ldr r3, [r7, #4]
80053f4: 6a9b ldr r3, [r3, #40] ; 0x28
80053f6: 2b00 cmp r3, #0
80053f8: d003 beq.n 8005402 <HAL_UART_Init+0x66>
{
UART_AdvFeatureConfig(huart);
80053fa: 687b ldr r3, [r7, #4]
80053fc: 0018 movs r0, r3
80053fe: f000 fed9 bl 80061b4 <UART_AdvFeatureConfig>
}
/* In asynchronous mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
8005402: 687b ldr r3, [r7, #4]
8005404: 681b ldr r3, [r3, #0]
8005406: 685a ldr r2, [r3, #4]
8005408: 687b ldr r3, [r7, #4]
800540a: 681b ldr r3, [r3, #0]
800540c: 490d ldr r1, [pc, #52] ; (8005444 <HAL_UART_Init+0xa8>)
800540e: 400a ands r2, r1
8005410: 605a str r2, [r3, #4]
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
8005412: 687b ldr r3, [r7, #4]
8005414: 681b ldr r3, [r3, #0]
8005416: 689a ldr r2, [r3, #8]
8005418: 687b ldr r3, [r7, #4]
800541a: 681b ldr r3, [r3, #0]
800541c: 212a movs r1, #42 ; 0x2a
800541e: 438a bics r2, r1
8005420: 609a str r2, [r3, #8]
__HAL_UART_ENABLE(huart);
8005422: 687b ldr r3, [r7, #4]
8005424: 681b ldr r3, [r3, #0]
8005426: 681a ldr r2, [r3, #0]
8005428: 687b ldr r3, [r7, #4]
800542a: 681b ldr r3, [r3, #0]
800542c: 2101 movs r1, #1
800542e: 430a orrs r2, r1
8005430: 601a str r2, [r3, #0]
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
return (UART_CheckIdleState(huart));
8005432: 687b ldr r3, [r7, #4]
8005434: 0018 movs r0, r3
8005436: f000 ff71 bl 800631c <UART_CheckIdleState>
800543a: 0003 movs r3, r0
}
800543c: 0018 movs r0, r3
800543e: 46bd mov sp, r7
8005440: b002 add sp, #8
8005442: bd80 pop {r7, pc}
8005444: ffffb7ff .word 0xffffb7ff
08005448 <HAL_UART_Receive_IT>:
* @param pData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{
8005448: b580 push {r7, lr}
800544a: b088 sub sp, #32
800544c: af00 add r7, sp, #0
800544e: 60f8 str r0, [r7, #12]
8005450: 60b9 str r1, [r7, #8]
8005452: 1dbb adds r3, r7, #6
8005454: 801a strh r2, [r3, #0]
/* Check that a Rx process is not already ongoing */
if (huart->RxState == HAL_UART_STATE_READY)
8005456: 68fb ldr r3, [r7, #12]
8005458: 2288 movs r2, #136 ; 0x88
800545a: 589b ldr r3, [r3, r2]
800545c: 2b20 cmp r3, #32
800545e: d155 bne.n 800550c <HAL_UART_Receive_IT+0xc4>
{
if ((pData == NULL) || (Size == 0U))
8005460: 68bb ldr r3, [r7, #8]
8005462: 2b00 cmp r3, #0
8005464: d003 beq.n 800546e <HAL_UART_Receive_IT+0x26>
8005466: 1dbb adds r3, r7, #6
8005468: 881b ldrh r3, [r3, #0]
800546a: 2b00 cmp r3, #0
800546c: d101 bne.n 8005472 <HAL_UART_Receive_IT+0x2a>
{
return HAL_ERROR;
800546e: 2301 movs r3, #1
8005470: e04d b.n 800550e <HAL_UART_Receive_IT+0xc6>
}
/* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
should be aligned on a u16 frontier, as data to be received from RDR will be
handled through a u16 cast. */
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
8005472: 68fb ldr r3, [r7, #12]
8005474: 689a ldr r2, [r3, #8]
8005476: 2380 movs r3, #128 ; 0x80
8005478: 015b lsls r3, r3, #5
800547a: 429a cmp r2, r3
800547c: d109 bne.n 8005492 <HAL_UART_Receive_IT+0x4a>
800547e: 68fb ldr r3, [r7, #12]
8005480: 691b ldr r3, [r3, #16]
8005482: 2b00 cmp r3, #0
8005484: d105 bne.n 8005492 <HAL_UART_Receive_IT+0x4a>
{
if ((((uint32_t)pData) & 1U) != 0U)
8005486: 68bb ldr r3, [r7, #8]
8005488: 2201 movs r2, #1
800548a: 4013 ands r3, r2
800548c: d001 beq.n 8005492 <HAL_UART_Receive_IT+0x4a>
{
return HAL_ERROR;
800548e: 2301 movs r3, #1
8005490: e03d b.n 800550e <HAL_UART_Receive_IT+0xc6>
}
}
__HAL_LOCK(huart);
8005492: 68fb ldr r3, [r7, #12]
8005494: 2280 movs r2, #128 ; 0x80
8005496: 5c9b ldrb r3, [r3, r2]
8005498: 2b01 cmp r3, #1
800549a: d101 bne.n 80054a0 <HAL_UART_Receive_IT+0x58>
800549c: 2302 movs r3, #2
800549e: e036 b.n 800550e <HAL_UART_Receive_IT+0xc6>
80054a0: 68fb ldr r3, [r7, #12]
80054a2: 2280 movs r2, #128 ; 0x80
80054a4: 2101 movs r1, #1
80054a6: 5499 strb r1, [r3, r2]
/* Set Reception type to Standard reception */
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
80054a8: 68fb ldr r3, [r7, #12]
80054aa: 2200 movs r2, #0
80054ac: 66da str r2, [r3, #108] ; 0x6c
if (!(IS_LPUART_INSTANCE(huart->Instance)))
80054ae: 68fb ldr r3, [r7, #12]
80054b0: 681b ldr r3, [r3, #0]
80054b2: 4a19 ldr r2, [pc, #100] ; (8005518 <HAL_UART_Receive_IT+0xd0>)
80054b4: 4293 cmp r3, r2
80054b6: d020 beq.n 80054fa <HAL_UART_Receive_IT+0xb2>
{
/* Check that USART RTOEN bit is set */
if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
80054b8: 68fb ldr r3, [r7, #12]
80054ba: 681b ldr r3, [r3, #0]
80054bc: 685a ldr r2, [r3, #4]
80054be: 2380 movs r3, #128 ; 0x80
80054c0: 041b lsls r3, r3, #16
80054c2: 4013 ands r3, r2
80054c4: d019 beq.n 80054fa <HAL_UART_Receive_IT+0xb2>
*/
__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
80054c6: f3ef 8310 mrs r3, PRIMASK
80054ca: 613b str r3, [r7, #16]
return(result);
80054cc: 693b ldr r3, [r7, #16]
{
/* Enable the UART Receiver Timeout Interrupt */
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
80054ce: 61fb str r3, [r7, #28]
80054d0: 2301 movs r3, #1
80054d2: 617b str r3, [r7, #20]
\details Assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80054d4: 697b ldr r3, [r7, #20]
80054d6: f383 8810 msr PRIMASK, r3
}
80054da: 46c0 nop ; (mov r8, r8)
80054dc: 68fb ldr r3, [r7, #12]
80054de: 681b ldr r3, [r3, #0]
80054e0: 681a ldr r2, [r3, #0]
80054e2: 68fb ldr r3, [r7, #12]
80054e4: 681b ldr r3, [r3, #0]
80054e6: 2180 movs r1, #128 ; 0x80
80054e8: 04c9 lsls r1, r1, #19
80054ea: 430a orrs r2, r1
80054ec: 601a str r2, [r3, #0]
80054ee: 69fb ldr r3, [r7, #28]
80054f0: 61bb str r3, [r7, #24]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80054f2: 69bb ldr r3, [r7, #24]
80054f4: f383 8810 msr PRIMASK, r3
}
80054f8: 46c0 nop ; (mov r8, r8)
}
}
return (UART_Start_Receive_IT(huart, pData, Size));
80054fa: 1dbb adds r3, r7, #6
80054fc: 881a ldrh r2, [r3, #0]
80054fe: 68b9 ldr r1, [r7, #8]
8005500: 68fb ldr r3, [r7, #12]
8005502: 0018 movs r0, r3
8005504: f001 f81c bl 8006540 <UART_Start_Receive_IT>
8005508: 0003 movs r3, r0
800550a: e000 b.n 800550e <HAL_UART_Receive_IT+0xc6>
}
else
{
return HAL_BUSY;
800550c: 2302 movs r3, #2
}
}
800550e: 0018 movs r0, r3
8005510: 46bd mov sp, r7
8005512: b008 add sp, #32
8005514: bd80 pop {r7, pc}
8005516: 46c0 nop ; (mov r8, r8)
8005518: 40008000 .word 0x40008000
0800551c <HAL_UART_Transmit_DMA>:
* @param pData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size)
{
800551c: b580 push {r7, lr}
800551e: b088 sub sp, #32
8005520: af00 add r7, sp, #0
8005522: 60f8 str r0, [r7, #12]
8005524: 60b9 str r1, [r7, #8]
8005526: 1dbb adds r3, r7, #6
8005528: 801a strh r2, [r3, #0]
/* Check that a Tx process is not already ongoing */
if (huart->gState == HAL_UART_STATE_READY)
800552a: 68fb ldr r3, [r7, #12]
800552c: 2284 movs r2, #132 ; 0x84
800552e: 589b ldr r3, [r3, r2]
8005530: 2b20 cmp r3, #32
8005532: d000 beq.n 8005536 <HAL_UART_Transmit_DMA+0x1a>
8005534: e08c b.n 8005650 <HAL_UART_Transmit_DMA+0x134>
{
if ((pData == NULL) || (Size == 0U))
8005536: 68bb ldr r3, [r7, #8]
8005538: 2b00 cmp r3, #0
800553a: d003 beq.n 8005544 <HAL_UART_Transmit_DMA+0x28>
800553c: 1dbb adds r3, r7, #6
800553e: 881b ldrh r3, [r3, #0]
8005540: 2b00 cmp r3, #0
8005542: d101 bne.n 8005548 <HAL_UART_Transmit_DMA+0x2c>
{
return HAL_ERROR;
8005544: 2301 movs r3, #1
8005546: e084 b.n 8005652 <HAL_UART_Transmit_DMA+0x136>
}
/* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
should be aligned on a u16 frontier, as data copy into TDR will be
handled by DMA from a u16 frontier. */
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
8005548: 68fb ldr r3, [r7, #12]
800554a: 689a ldr r2, [r3, #8]
800554c: 2380 movs r3, #128 ; 0x80
800554e: 015b lsls r3, r3, #5
8005550: 429a cmp r2, r3
8005552: d109 bne.n 8005568 <HAL_UART_Transmit_DMA+0x4c>
8005554: 68fb ldr r3, [r7, #12]
8005556: 691b ldr r3, [r3, #16]
8005558: 2b00 cmp r3, #0
800555a: d105 bne.n 8005568 <HAL_UART_Transmit_DMA+0x4c>
{
if ((((uint32_t)pData) & 1U) != 0U)
800555c: 68bb ldr r3, [r7, #8]
800555e: 2201 movs r2, #1
8005560: 4013 ands r3, r2
8005562: d001 beq.n 8005568 <HAL_UART_Transmit_DMA+0x4c>
{
return HAL_ERROR;
8005564: 2301 movs r3, #1
8005566: e074 b.n 8005652 <HAL_UART_Transmit_DMA+0x136>
}
}
__HAL_LOCK(huart);
8005568: 68fb ldr r3, [r7, #12]
800556a: 2280 movs r2, #128 ; 0x80
800556c: 5c9b ldrb r3, [r3, r2]
800556e: 2b01 cmp r3, #1
8005570: d101 bne.n 8005576 <HAL_UART_Transmit_DMA+0x5a>
8005572: 2302 movs r3, #2
8005574: e06d b.n 8005652 <HAL_UART_Transmit_DMA+0x136>
8005576: 68fb ldr r3, [r7, #12]
8005578: 2280 movs r2, #128 ; 0x80
800557a: 2101 movs r1, #1
800557c: 5499 strb r1, [r3, r2]
huart->pTxBuffPtr = pData;
800557e: 68fb ldr r3, [r7, #12]
8005580: 68ba ldr r2, [r7, #8]
8005582: 651a str r2, [r3, #80] ; 0x50
huart->TxXferSize = Size;
8005584: 68fb ldr r3, [r7, #12]
8005586: 1dba adds r2, r7, #6
8005588: 2154 movs r1, #84 ; 0x54
800558a: 8812 ldrh r2, [r2, #0]
800558c: 525a strh r2, [r3, r1]
huart->TxXferCount = Size;
800558e: 68fb ldr r3, [r7, #12]
8005590: 1dba adds r2, r7, #6
8005592: 2156 movs r1, #86 ; 0x56
8005594: 8812 ldrh r2, [r2, #0]
8005596: 525a strh r2, [r3, r1]
huart->ErrorCode = HAL_UART_ERROR_NONE;
8005598: 68fb ldr r3, [r7, #12]
800559a: 228c movs r2, #140 ; 0x8c
800559c: 2100 movs r1, #0
800559e: 5099 str r1, [r3, r2]
huart->gState = HAL_UART_STATE_BUSY_TX;
80055a0: 68fb ldr r3, [r7, #12]
80055a2: 2284 movs r2, #132 ; 0x84
80055a4: 2121 movs r1, #33 ; 0x21
80055a6: 5099 str r1, [r3, r2]
if (huart->hdmatx != NULL)
80055a8: 68fb ldr r3, [r7, #12]
80055aa: 6f9b ldr r3, [r3, #120] ; 0x78
80055ac: 2b00 cmp r3, #0
80055ae: d02c beq.n 800560a <HAL_UART_Transmit_DMA+0xee>
{
/* Set the UART DMA transfer complete callback */
huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
80055b0: 68fb ldr r3, [r7, #12]
80055b2: 6f9b ldr r3, [r3, #120] ; 0x78
80055b4: 4a29 ldr r2, [pc, #164] ; (800565c <HAL_UART_Transmit_DMA+0x140>)
80055b6: 62da str r2, [r3, #44] ; 0x2c
/* Set the UART DMA Half transfer complete callback */
huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
80055b8: 68fb ldr r3, [r7, #12]
80055ba: 6f9b ldr r3, [r3, #120] ; 0x78
80055bc: 4a28 ldr r2, [pc, #160] ; (8005660 <HAL_UART_Transmit_DMA+0x144>)
80055be: 631a str r2, [r3, #48] ; 0x30
/* Set the DMA error callback */
huart->hdmatx->XferErrorCallback = UART_DMAError;
80055c0: 68fb ldr r3, [r7, #12]
80055c2: 6f9b ldr r3, [r3, #120] ; 0x78
80055c4: 4a27 ldr r2, [pc, #156] ; (8005664 <HAL_UART_Transmit_DMA+0x148>)
80055c6: 635a str r2, [r3, #52] ; 0x34
/* Set the DMA abort callback */
huart->hdmatx->XferAbortCallback = NULL;
80055c8: 68fb ldr r3, [r7, #12]
80055ca: 6f9b ldr r3, [r3, #120] ; 0x78
80055cc: 2200 movs r2, #0
80055ce: 639a str r2, [r3, #56] ; 0x38
/* Enable the UART transmit DMA channel */
if (HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, Size) != HAL_OK)
80055d0: 68fb ldr r3, [r7, #12]
80055d2: 6f98 ldr r0, [r3, #120] ; 0x78
80055d4: 68fb ldr r3, [r7, #12]
80055d6: 6d1b ldr r3, [r3, #80] ; 0x50
80055d8: 0019 movs r1, r3
80055da: 68fb ldr r3, [r7, #12]
80055dc: 681b ldr r3, [r3, #0]
80055de: 3328 adds r3, #40 ; 0x28
80055e0: 001a movs r2, r3
80055e2: 1dbb adds r3, r7, #6
80055e4: 881b ldrh r3, [r3, #0]
80055e6: f7fd fd19 bl 800301c <HAL_DMA_Start_IT>
80055ea: 1e03 subs r3, r0, #0
80055ec: d00d beq.n 800560a <HAL_UART_Transmit_DMA+0xee>
{
/* Set error code to DMA */
huart->ErrorCode = HAL_UART_ERROR_DMA;
80055ee: 68fb ldr r3, [r7, #12]
80055f0: 228c movs r2, #140 ; 0x8c
80055f2: 2110 movs r1, #16
80055f4: 5099 str r1, [r3, r2]
__HAL_UNLOCK(huart);
80055f6: 68fb ldr r3, [r7, #12]
80055f8: 2280 movs r2, #128 ; 0x80
80055fa: 2100 movs r1, #0
80055fc: 5499 strb r1, [r3, r2]
/* Restore huart->gState to ready */
huart->gState = HAL_UART_STATE_READY;
80055fe: 68fb ldr r3, [r7, #12]
8005600: 2284 movs r2, #132 ; 0x84
8005602: 2120 movs r1, #32
8005604: 5099 str r1, [r3, r2]
return HAL_ERROR;
8005606: 2301 movs r3, #1
8005608: e023 b.n 8005652 <HAL_UART_Transmit_DMA+0x136>
}
}
/* Clear the TC flag in the ICR register */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
800560a: 68fb ldr r3, [r7, #12]
800560c: 681b ldr r3, [r3, #0]
800560e: 2240 movs r2, #64 ; 0x40
8005610: 621a str r2, [r3, #32]
__HAL_UNLOCK(huart);
8005612: 68fb ldr r3, [r7, #12]
8005614: 2280 movs r2, #128 ; 0x80
8005616: 2100 movs r1, #0
8005618: 5499 strb r1, [r3, r2]
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
800561a: f3ef 8310 mrs r3, PRIMASK
800561e: 613b str r3, [r7, #16]
return(result);
8005620: 693b ldr r3, [r7, #16]
/* Enable the DMA transfer for transmit request by setting the DMAT bit
in the UART CR3 register */
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
8005622: 61fb str r3, [r7, #28]
8005624: 2301 movs r3, #1
8005626: 617b str r3, [r7, #20]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8005628: 697b ldr r3, [r7, #20]
800562a: f383 8810 msr PRIMASK, r3
}
800562e: 46c0 nop ; (mov r8, r8)
8005630: 68fb ldr r3, [r7, #12]
8005632: 681b ldr r3, [r3, #0]
8005634: 689a ldr r2, [r3, #8]
8005636: 68fb ldr r3, [r7, #12]
8005638: 681b ldr r3, [r3, #0]
800563a: 2180 movs r1, #128 ; 0x80
800563c: 430a orrs r2, r1
800563e: 609a str r2, [r3, #8]
8005640: 69fb ldr r3, [r7, #28]
8005642: 61bb str r3, [r7, #24]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8005644: 69bb ldr r3, [r7, #24]
8005646: f383 8810 msr PRIMASK, r3
}
800564a: 46c0 nop ; (mov r8, r8)
return HAL_OK;
800564c: 2300 movs r3, #0
800564e: e000 b.n 8005652 <HAL_UART_Transmit_DMA+0x136>
}
else
{
return HAL_BUSY;
8005650: 2302 movs r3, #2
}
}
8005652: 0018 movs r0, r3
8005654: 46bd mov sp, r7
8005656: b008 add sp, #32
8005658: bd80 pop {r7, pc}
800565a: 46c0 nop ; (mov r8, r8)
800565c: 080068e5 .word 0x080068e5
8005660: 0800697d .word 0x0800697d
8005664: 0800699b .word 0x0800699b
08005668 <HAL_UART_IRQHandler>:
* @brief Handle UART interrupt request.
* @param huart UART handle.
* @retval None
*/
void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
{
8005668: b5b0 push {r4, r5, r7, lr}
800566a: b0aa sub sp, #168 ; 0xa8
800566c: af00 add r7, sp, #0
800566e: 6078 str r0, [r7, #4]
uint32_t isrflags = READ_REG(huart->Instance->ISR);
8005670: 687b ldr r3, [r7, #4]
8005672: 681b ldr r3, [r3, #0]
8005674: 69db ldr r3, [r3, #28]
8005676: 22a4 movs r2, #164 ; 0xa4
8005678: 18b9 adds r1, r7, r2
800567a: 600b str r3, [r1, #0]
uint32_t cr1its = READ_REG(huart->Instance->CR1);
800567c: 687b ldr r3, [r7, #4]
800567e: 681b ldr r3, [r3, #0]
8005680: 681b ldr r3, [r3, #0]
8005682: 20a0 movs r0, #160 ; 0xa0
8005684: 1839 adds r1, r7, r0
8005686: 600b str r3, [r1, #0]
uint32_t cr3its = READ_REG(huart->Instance->CR3);
8005688: 687b ldr r3, [r7, #4]
800568a: 681b ldr r3, [r3, #0]
800568c: 689b ldr r3, [r3, #8]
800568e: 249c movs r4, #156 ; 0x9c
8005690: 1939 adds r1, r7, r4
8005692: 600b str r3, [r1, #0]
uint32_t errorflags;
uint32_t errorcode;
/* If no error occurs */
errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
8005694: 0011 movs r1, r2
8005696: 18bb adds r3, r7, r2
8005698: 681b ldr r3, [r3, #0]
800569a: 4aa0 ldr r2, [pc, #640] ; (800591c <HAL_UART_IRQHandler+0x2b4>)
800569c: 4013 ands r3, r2
800569e: 2298 movs r2, #152 ; 0x98
80056a0: 18bd adds r5, r7, r2
80056a2: 602b str r3, [r5, #0]
if (errorflags == 0U)
80056a4: 18bb adds r3, r7, r2
80056a6: 681b ldr r3, [r3, #0]
80056a8: 2b00 cmp r3, #0
80056aa: d11a bne.n 80056e2 <HAL_UART_IRQHandler+0x7a>
{
/* UART in mode Receiver ---------------------------------------------------*/
if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
80056ac: 187b adds r3, r7, r1
80056ae: 681b ldr r3, [r3, #0]
80056b0: 2220 movs r2, #32
80056b2: 4013 ands r3, r2
80056b4: d015 beq.n 80056e2 <HAL_UART_IRQHandler+0x7a>
&& (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
80056b6: 183b adds r3, r7, r0
80056b8: 681b ldr r3, [r3, #0]
80056ba: 2220 movs r2, #32
80056bc: 4013 ands r3, r2
80056be: d105 bne.n 80056cc <HAL_UART_IRQHandler+0x64>
|| ((cr3its & USART_CR3_RXFTIE) != 0U)))
80056c0: 193b adds r3, r7, r4
80056c2: 681a ldr r2, [r3, #0]
80056c4: 2380 movs r3, #128 ; 0x80
80056c6: 055b lsls r3, r3, #21
80056c8: 4013 ands r3, r2
80056ca: d00a beq.n 80056e2 <HAL_UART_IRQHandler+0x7a>
{
if (huart->RxISR != NULL)
80056cc: 687b ldr r3, [r7, #4]
80056ce: 6f1b ldr r3, [r3, #112] ; 0x70
80056d0: 2b00 cmp r3, #0
80056d2: d100 bne.n 80056d6 <HAL_UART_IRQHandler+0x6e>
80056d4: e2cf b.n 8005c76 <HAL_UART_IRQHandler+0x60e>
{
huart->RxISR(huart);
80056d6: 687b ldr r3, [r7, #4]
80056d8: 6f1b ldr r3, [r3, #112] ; 0x70
80056da: 687a ldr r2, [r7, #4]
80056dc: 0010 movs r0, r2
80056de: 4798 blx r3
}
return;
80056e0: e2c9 b.n 8005c76 <HAL_UART_IRQHandler+0x60e>
}
}
/* If some errors occur */
if ((errorflags != 0U)
80056e2: 2398 movs r3, #152 ; 0x98
80056e4: 18fb adds r3, r7, r3
80056e6: 681b ldr r3, [r3, #0]
80056e8: 2b00 cmp r3, #0
80056ea: d100 bne.n 80056ee <HAL_UART_IRQHandler+0x86>
80056ec: e11e b.n 800592c <HAL_UART_IRQHandler+0x2c4>
&& ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)
80056ee: 239c movs r3, #156 ; 0x9c
80056f0: 18fb adds r3, r7, r3
80056f2: 681b ldr r3, [r3, #0]
80056f4: 4a8a ldr r2, [pc, #552] ; (8005920 <HAL_UART_IRQHandler+0x2b8>)
80056f6: 4013 ands r3, r2
80056f8: d106 bne.n 8005708 <HAL_UART_IRQHandler+0xa0>
|| ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U))))
80056fa: 23a0 movs r3, #160 ; 0xa0
80056fc: 18fb adds r3, r7, r3
80056fe: 681b ldr r3, [r3, #0]
8005700: 4a88 ldr r2, [pc, #544] ; (8005924 <HAL_UART_IRQHandler+0x2bc>)
8005702: 4013 ands r3, r2
8005704: d100 bne.n 8005708 <HAL_UART_IRQHandler+0xa0>
8005706: e111 b.n 800592c <HAL_UART_IRQHandler+0x2c4>
{
/* UART parity error interrupt occurred -------------------------------------*/
if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
8005708: 23a4 movs r3, #164 ; 0xa4
800570a: 18fb adds r3, r7, r3
800570c: 681b ldr r3, [r3, #0]
800570e: 2201 movs r2, #1
8005710: 4013 ands r3, r2
8005712: d012 beq.n 800573a <HAL_UART_IRQHandler+0xd2>
8005714: 23a0 movs r3, #160 ; 0xa0
8005716: 18fb adds r3, r7, r3
8005718: 681a ldr r2, [r3, #0]
800571a: 2380 movs r3, #128 ; 0x80
800571c: 005b lsls r3, r3, #1
800571e: 4013 ands r3, r2
8005720: d00b beq.n 800573a <HAL_UART_IRQHandler+0xd2>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
8005722: 687b ldr r3, [r7, #4]
8005724: 681b ldr r3, [r3, #0]
8005726: 2201 movs r2, #1
8005728: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_PE;
800572a: 687b ldr r3, [r7, #4]
800572c: 228c movs r2, #140 ; 0x8c
800572e: 589b ldr r3, [r3, r2]
8005730: 2201 movs r2, #1
8005732: 431a orrs r2, r3
8005734: 687b ldr r3, [r7, #4]
8005736: 218c movs r1, #140 ; 0x8c
8005738: 505a str r2, [r3, r1]
}
/* UART frame error interrupt occurred --------------------------------------*/
if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
800573a: 23a4 movs r3, #164 ; 0xa4
800573c: 18fb adds r3, r7, r3
800573e: 681b ldr r3, [r3, #0]
8005740: 2202 movs r2, #2
8005742: 4013 ands r3, r2
8005744: d011 beq.n 800576a <HAL_UART_IRQHandler+0x102>
8005746: 239c movs r3, #156 ; 0x9c
8005748: 18fb adds r3, r7, r3
800574a: 681b ldr r3, [r3, #0]
800574c: 2201 movs r2, #1
800574e: 4013 ands r3, r2
8005750: d00b beq.n 800576a <HAL_UART_IRQHandler+0x102>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
8005752: 687b ldr r3, [r7, #4]
8005754: 681b ldr r3, [r3, #0]
8005756: 2202 movs r2, #2
8005758: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_FE;
800575a: 687b ldr r3, [r7, #4]
800575c: 228c movs r2, #140 ; 0x8c
800575e: 589b ldr r3, [r3, r2]
8005760: 2204 movs r2, #4
8005762: 431a orrs r2, r3
8005764: 687b ldr r3, [r7, #4]
8005766: 218c movs r1, #140 ; 0x8c
8005768: 505a str r2, [r3, r1]
}
/* UART noise error interrupt occurred --------------------------------------*/
if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
800576a: 23a4 movs r3, #164 ; 0xa4
800576c: 18fb adds r3, r7, r3
800576e: 681b ldr r3, [r3, #0]
8005770: 2204 movs r2, #4
8005772: 4013 ands r3, r2
8005774: d011 beq.n 800579a <HAL_UART_IRQHandler+0x132>
8005776: 239c movs r3, #156 ; 0x9c
8005778: 18fb adds r3, r7, r3
800577a: 681b ldr r3, [r3, #0]
800577c: 2201 movs r2, #1
800577e: 4013 ands r3, r2
8005780: d00b beq.n 800579a <HAL_UART_IRQHandler+0x132>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
8005782: 687b ldr r3, [r7, #4]
8005784: 681b ldr r3, [r3, #0]
8005786: 2204 movs r2, #4
8005788: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_NE;
800578a: 687b ldr r3, [r7, #4]
800578c: 228c movs r2, #140 ; 0x8c
800578e: 589b ldr r3, [r3, r2]
8005790: 2202 movs r2, #2
8005792: 431a orrs r2, r3
8005794: 687b ldr r3, [r7, #4]
8005796: 218c movs r1, #140 ; 0x8c
8005798: 505a str r2, [r3, r1]
}
/* UART Over-Run interrupt occurred -----------------------------------------*/
if (((isrflags & USART_ISR_ORE) != 0U)
800579a: 23a4 movs r3, #164 ; 0xa4
800579c: 18fb adds r3, r7, r3
800579e: 681b ldr r3, [r3, #0]
80057a0: 2208 movs r2, #8
80057a2: 4013 ands r3, r2
80057a4: d017 beq.n 80057d6 <HAL_UART_IRQHandler+0x16e>
&& (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
80057a6: 23a0 movs r3, #160 ; 0xa0
80057a8: 18fb adds r3, r7, r3
80057aa: 681b ldr r3, [r3, #0]
80057ac: 2220 movs r2, #32
80057ae: 4013 ands r3, r2
80057b0: d105 bne.n 80057be <HAL_UART_IRQHandler+0x156>
((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)))
80057b2: 239c movs r3, #156 ; 0x9c
80057b4: 18fb adds r3, r7, r3
80057b6: 681b ldr r3, [r3, #0]
80057b8: 4a59 ldr r2, [pc, #356] ; (8005920 <HAL_UART_IRQHandler+0x2b8>)
80057ba: 4013 ands r3, r2
&& (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
80057bc: d00b beq.n 80057d6 <HAL_UART_IRQHandler+0x16e>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
80057be: 687b ldr r3, [r7, #4]
80057c0: 681b ldr r3, [r3, #0]
80057c2: 2208 movs r2, #8
80057c4: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_ORE;
80057c6: 687b ldr r3, [r7, #4]
80057c8: 228c movs r2, #140 ; 0x8c
80057ca: 589b ldr r3, [r3, r2]
80057cc: 2208 movs r2, #8
80057ce: 431a orrs r2, r3
80057d0: 687b ldr r3, [r7, #4]
80057d2: 218c movs r1, #140 ; 0x8c
80057d4: 505a str r2, [r3, r1]
}
/* UART Receiver Timeout interrupt occurred ---------------------------------*/
if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
80057d6: 23a4 movs r3, #164 ; 0xa4
80057d8: 18fb adds r3, r7, r3
80057da: 681a ldr r2, [r3, #0]
80057dc: 2380 movs r3, #128 ; 0x80
80057de: 011b lsls r3, r3, #4
80057e0: 4013 ands r3, r2
80057e2: d013 beq.n 800580c <HAL_UART_IRQHandler+0x1a4>
80057e4: 23a0 movs r3, #160 ; 0xa0
80057e6: 18fb adds r3, r7, r3
80057e8: 681a ldr r2, [r3, #0]
80057ea: 2380 movs r3, #128 ; 0x80
80057ec: 04db lsls r3, r3, #19
80057ee: 4013 ands r3, r2
80057f0: d00c beq.n 800580c <HAL_UART_IRQHandler+0x1a4>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
80057f2: 687b ldr r3, [r7, #4]
80057f4: 681b ldr r3, [r3, #0]
80057f6: 2280 movs r2, #128 ; 0x80
80057f8: 0112 lsls r2, r2, #4
80057fa: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_RTO;
80057fc: 687b ldr r3, [r7, #4]
80057fe: 228c movs r2, #140 ; 0x8c
8005800: 589b ldr r3, [r3, r2]
8005802: 2220 movs r2, #32
8005804: 431a orrs r2, r3
8005806: 687b ldr r3, [r7, #4]
8005808: 218c movs r1, #140 ; 0x8c
800580a: 505a str r2, [r3, r1]
}
/* Call UART Error Call back function if need be ----------------------------*/
if (huart->ErrorCode != HAL_UART_ERROR_NONE)
800580c: 687b ldr r3, [r7, #4]
800580e: 228c movs r2, #140 ; 0x8c
8005810: 589b ldr r3, [r3, r2]
8005812: 2b00 cmp r3, #0
8005814: d100 bne.n 8005818 <HAL_UART_IRQHandler+0x1b0>
8005816: e230 b.n 8005c7a <HAL_UART_IRQHandler+0x612>
{
/* UART in mode Receiver --------------------------------------------------*/
if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
8005818: 23a4 movs r3, #164 ; 0xa4
800581a: 18fb adds r3, r7, r3
800581c: 681b ldr r3, [r3, #0]
800581e: 2220 movs r2, #32
8005820: 4013 ands r3, r2
8005822: d015 beq.n 8005850 <HAL_UART_IRQHandler+0x1e8>
&& (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
8005824: 23a0 movs r3, #160 ; 0xa0
8005826: 18fb adds r3, r7, r3
8005828: 681b ldr r3, [r3, #0]
800582a: 2220 movs r2, #32
800582c: 4013 ands r3, r2
800582e: d106 bne.n 800583e <HAL_UART_IRQHandler+0x1d6>
|| ((cr3its & USART_CR3_RXFTIE) != 0U)))
8005830: 239c movs r3, #156 ; 0x9c
8005832: 18fb adds r3, r7, r3
8005834: 681a ldr r2, [r3, #0]
8005836: 2380 movs r3, #128 ; 0x80
8005838: 055b lsls r3, r3, #21
800583a: 4013 ands r3, r2
800583c: d008 beq.n 8005850 <HAL_UART_IRQHandler+0x1e8>
{
if (huart->RxISR != NULL)
800583e: 687b ldr r3, [r7, #4]
8005840: 6f1b ldr r3, [r3, #112] ; 0x70
8005842: 2b00 cmp r3, #0
8005844: d004 beq.n 8005850 <HAL_UART_IRQHandler+0x1e8>
{
huart->RxISR(huart);
8005846: 687b ldr r3, [r7, #4]
8005848: 6f1b ldr r3, [r3, #112] ; 0x70
800584a: 687a ldr r2, [r7, #4]
800584c: 0010 movs r0, r2
800584e: 4798 blx r3
/* If Error is to be considered as blocking :
- Receiver Timeout error in Reception
- Overrun error in Reception
- any error occurs in DMA mode reception
*/
errorcode = huart->ErrorCode;
8005850: 687b ldr r3, [r7, #4]
8005852: 228c movs r2, #140 ; 0x8c
8005854: 589b ldr r3, [r3, r2]
8005856: 2194 movs r1, #148 ; 0x94
8005858: 187a adds r2, r7, r1
800585a: 6013 str r3, [r2, #0]
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
800585c: 687b ldr r3, [r7, #4]
800585e: 681b ldr r3, [r3, #0]
8005860: 689b ldr r3, [r3, #8]
8005862: 2240 movs r2, #64 ; 0x40
8005864: 4013 ands r3, r2
8005866: 2b40 cmp r3, #64 ; 0x40
8005868: d004 beq.n 8005874 <HAL_UART_IRQHandler+0x20c>
((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U))
800586a: 187b adds r3, r7, r1
800586c: 681b ldr r3, [r3, #0]
800586e: 2228 movs r2, #40 ; 0x28
8005870: 4013 ands r3, r2
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
8005872: d047 beq.n 8005904 <HAL_UART_IRQHandler+0x29c>
{
/* Blocking error : transfer is aborted
Set the UART state ready to be able to start again the process,
Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
UART_EndRxTransfer(huart);
8005874: 687b ldr r3, [r7, #4]
8005876: 0018 movs r0, r3
8005878: f000 ffce bl 8006818 <UART_EndRxTransfer>
/* Abort the UART DMA Rx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
800587c: 687b ldr r3, [r7, #4]
800587e: 681b ldr r3, [r3, #0]
8005880: 689b ldr r3, [r3, #8]
8005882: 2240 movs r2, #64 ; 0x40
8005884: 4013 ands r3, r2
8005886: 2b40 cmp r3, #64 ; 0x40
8005888: d137 bne.n 80058fa <HAL_UART_IRQHandler+0x292>
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
800588a: f3ef 8310 mrs r3, PRIMASK
800588e: 663b str r3, [r7, #96] ; 0x60
return(result);
8005890: 6e3b ldr r3, [r7, #96] ; 0x60
{
/* Disable the UART DMA Rx request if enabled */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
8005892: 2090 movs r0, #144 ; 0x90
8005894: 183a adds r2, r7, r0
8005896: 6013 str r3, [r2, #0]
8005898: 2301 movs r3, #1
800589a: 667b str r3, [r7, #100] ; 0x64
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
800589c: 6e7b ldr r3, [r7, #100] ; 0x64
800589e: f383 8810 msr PRIMASK, r3
}
80058a2: 46c0 nop ; (mov r8, r8)
80058a4: 687b ldr r3, [r7, #4]
80058a6: 681b ldr r3, [r3, #0]
80058a8: 689a ldr r2, [r3, #8]
80058aa: 687b ldr r3, [r7, #4]
80058ac: 681b ldr r3, [r3, #0]
80058ae: 2140 movs r1, #64 ; 0x40
80058b0: 438a bics r2, r1
80058b2: 609a str r2, [r3, #8]
80058b4: 183b adds r3, r7, r0
80058b6: 681b ldr r3, [r3, #0]
80058b8: 66bb str r3, [r7, #104] ; 0x68
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80058ba: 6ebb ldr r3, [r7, #104] ; 0x68
80058bc: f383 8810 msr PRIMASK, r3
}
80058c0: 46c0 nop ; (mov r8, r8)
/* Abort the UART DMA Rx channel */
if (huart->hdmarx != NULL)
80058c2: 687b ldr r3, [r7, #4]
80058c4: 6fdb ldr r3, [r3, #124] ; 0x7c
80058c6: 2b00 cmp r3, #0
80058c8: d012 beq.n 80058f0 <HAL_UART_IRQHandler+0x288>
{
/* Set the UART DMA Abort callback :
will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
80058ca: 687b ldr r3, [r7, #4]
80058cc: 6fdb ldr r3, [r3, #124] ; 0x7c
80058ce: 4a16 ldr r2, [pc, #88] ; (8005928 <HAL_UART_IRQHandler+0x2c0>)
80058d0: 639a str r2, [r3, #56] ; 0x38
/* Abort DMA RX */
if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
80058d2: 687b ldr r3, [r7, #4]
80058d4: 6fdb ldr r3, [r3, #124] ; 0x7c
80058d6: 0018 movs r0, r3
80058d8: f7fd fc88 bl 80031ec <HAL_DMA_Abort_IT>
80058dc: 1e03 subs r3, r0, #0
80058de: d01a beq.n 8005916 <HAL_UART_IRQHandler+0x2ae>
{
/* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
huart->hdmarx->XferAbortCallback(huart->hdmarx);
80058e0: 687b ldr r3, [r7, #4]
80058e2: 6fdb ldr r3, [r3, #124] ; 0x7c
80058e4: 6b9a ldr r2, [r3, #56] ; 0x38
80058e6: 687b ldr r3, [r7, #4]
80058e8: 6fdb ldr r3, [r3, #124] ; 0x7c
80058ea: 0018 movs r0, r3
80058ec: 4790 blx r2
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
80058ee: e012 b.n 8005916 <HAL_UART_IRQHandler+0x2ae>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
80058f0: 687b ldr r3, [r7, #4]
80058f2: 0018 movs r0, r3
80058f4: f7fb fdf2 bl 80014dc <HAL_UART_ErrorCallback>
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
80058f8: e00d b.n 8005916 <HAL_UART_IRQHandler+0x2ae>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
80058fa: 687b ldr r3, [r7, #4]
80058fc: 0018 movs r0, r3
80058fe: f7fb fded bl 80014dc <HAL_UART_ErrorCallback>
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
8005902: e008 b.n 8005916 <HAL_UART_IRQHandler+0x2ae>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
8005904: 687b ldr r3, [r7, #4]
8005906: 0018 movs r0, r3
8005908: f7fb fde8 bl 80014dc <HAL_UART_ErrorCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
huart->ErrorCode = HAL_UART_ERROR_NONE;
800590c: 687b ldr r3, [r7, #4]
800590e: 228c movs r2, #140 ; 0x8c
8005910: 2100 movs r1, #0
8005912: 5099 str r1, [r3, r2]
}
}
return;
8005914: e1b1 b.n 8005c7a <HAL_UART_IRQHandler+0x612>
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
8005916: 46c0 nop ; (mov r8, r8)
return;
8005918: e1af b.n 8005c7a <HAL_UART_IRQHandler+0x612>
800591a: 46c0 nop ; (mov r8, r8)
800591c: 0000080f .word 0x0000080f
8005920: 10000001 .word 0x10000001
8005924: 04000120 .word 0x04000120
8005928: 08006a21 .word 0x08006a21
} /* End if some error occurs */
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
800592c: 687b ldr r3, [r7, #4]
800592e: 6edb ldr r3, [r3, #108] ; 0x6c
8005930: 2b01 cmp r3, #1
8005932: d000 beq.n 8005936 <HAL_UART_IRQHandler+0x2ce>
8005934: e135 b.n 8005ba2 <HAL_UART_IRQHandler+0x53a>
&& ((isrflags & USART_ISR_IDLE) != 0U)
8005936: 23a4 movs r3, #164 ; 0xa4
8005938: 18fb adds r3, r7, r3
800593a: 681b ldr r3, [r3, #0]
800593c: 2210 movs r2, #16
800593e: 4013 ands r3, r2
8005940: d100 bne.n 8005944 <HAL_UART_IRQHandler+0x2dc>
8005942: e12e b.n 8005ba2 <HAL_UART_IRQHandler+0x53a>
&& ((cr1its & USART_ISR_IDLE) != 0U))
8005944: 23a0 movs r3, #160 ; 0xa0
8005946: 18fb adds r3, r7, r3
8005948: 681b ldr r3, [r3, #0]
800594a: 2210 movs r2, #16
800594c: 4013 ands r3, r2
800594e: d100 bne.n 8005952 <HAL_UART_IRQHandler+0x2ea>
8005950: e127 b.n 8005ba2 <HAL_UART_IRQHandler+0x53a>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
8005952: 687b ldr r3, [r7, #4]
8005954: 681b ldr r3, [r3, #0]
8005956: 2210 movs r2, #16
8005958: 621a str r2, [r3, #32]
/* Check if DMA mode is enabled in UART */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
800595a: 687b ldr r3, [r7, #4]
800595c: 681b ldr r3, [r3, #0]
800595e: 689b ldr r3, [r3, #8]
8005960: 2240 movs r2, #64 ; 0x40
8005962: 4013 ands r3, r2
8005964: 2b40 cmp r3, #64 ; 0x40
8005966: d000 beq.n 800596a <HAL_UART_IRQHandler+0x302>
8005968: e09e b.n 8005aa8 <HAL_UART_IRQHandler+0x440>
{
/* DMA mode enabled */
/* Check received length : If all expected data are received, do nothing,
(DMA cplt callback will be called).
Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx);
800596a: 687b ldr r3, [r7, #4]
800596c: 6fdb ldr r3, [r3, #124] ; 0x7c
800596e: 681b ldr r3, [r3, #0]
8005970: 685a ldr r2, [r3, #4]
8005972: 217e movs r1, #126 ; 0x7e
8005974: 187b adds r3, r7, r1
8005976: 801a strh r2, [r3, #0]
if ((nb_remaining_rx_data > 0U)
8005978: 187b adds r3, r7, r1
800597a: 881b ldrh r3, [r3, #0]
800597c: 2b00 cmp r3, #0
800597e: d100 bne.n 8005982 <HAL_UART_IRQHandler+0x31a>
8005980: e17d b.n 8005c7e <HAL_UART_IRQHandler+0x616>
&& (nb_remaining_rx_data < huart->RxXferSize))
8005982: 687b ldr r3, [r7, #4]
8005984: 225c movs r2, #92 ; 0x5c
8005986: 5a9b ldrh r3, [r3, r2]
8005988: 187a adds r2, r7, r1
800598a: 8812 ldrh r2, [r2, #0]
800598c: 429a cmp r2, r3
800598e: d300 bcc.n 8005992 <HAL_UART_IRQHandler+0x32a>
8005990: e175 b.n 8005c7e <HAL_UART_IRQHandler+0x616>
{
/* Reception is not complete */
huart->RxXferCount = nb_remaining_rx_data;
8005992: 687b ldr r3, [r7, #4]
8005994: 187a adds r2, r7, r1
8005996: 215e movs r1, #94 ; 0x5e
8005998: 8812 ldrh r2, [r2, #0]
800599a: 525a strh r2, [r3, r1]
/* In Normal mode, end DMA xfer and HAL UART Rx process*/
if (HAL_IS_BIT_CLR(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC))
800599c: 687b ldr r3, [r7, #4]
800599e: 6fdb ldr r3, [r3, #124] ; 0x7c
80059a0: 681b ldr r3, [r3, #0]
80059a2: 681b ldr r3, [r3, #0]
80059a4: 2220 movs r2, #32
80059a6: 4013 ands r3, r2
80059a8: d16f bne.n 8005a8a <HAL_UART_IRQHandler+0x422>
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
80059aa: f3ef 8310 mrs r3, PRIMASK
80059ae: 633b str r3, [r7, #48] ; 0x30
return(result);
80059b0: 6b3b ldr r3, [r7, #48] ; 0x30
{
/* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
80059b2: 67bb str r3, [r7, #120] ; 0x78
80059b4: 2301 movs r3, #1
80059b6: 637b str r3, [r7, #52] ; 0x34
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80059b8: 6b7b ldr r3, [r7, #52] ; 0x34
80059ba: f383 8810 msr PRIMASK, r3
}
80059be: 46c0 nop ; (mov r8, r8)
80059c0: 687b ldr r3, [r7, #4]
80059c2: 681b ldr r3, [r3, #0]
80059c4: 681a ldr r2, [r3, #0]
80059c6: 687b ldr r3, [r7, #4]
80059c8: 681b ldr r3, [r3, #0]
80059ca: 49b1 ldr r1, [pc, #708] ; (8005c90 <HAL_UART_IRQHandler+0x628>)
80059cc: 400a ands r2, r1
80059ce: 601a str r2, [r3, #0]
80059d0: 6fbb ldr r3, [r7, #120] ; 0x78
80059d2: 63bb str r3, [r7, #56] ; 0x38
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80059d4: 6bbb ldr r3, [r7, #56] ; 0x38
80059d6: f383 8810 msr PRIMASK, r3
}
80059da: 46c0 nop ; (mov r8, r8)
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
80059dc: f3ef 8310 mrs r3, PRIMASK
80059e0: 63fb str r3, [r7, #60] ; 0x3c
return(result);
80059e2: 6bfb ldr r3, [r7, #60] ; 0x3c
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
80059e4: 677b str r3, [r7, #116] ; 0x74
80059e6: 2301 movs r3, #1
80059e8: 643b str r3, [r7, #64] ; 0x40
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80059ea: 6c3b ldr r3, [r7, #64] ; 0x40
80059ec: f383 8810 msr PRIMASK, r3
}
80059f0: 46c0 nop ; (mov r8, r8)
80059f2: 687b ldr r3, [r7, #4]
80059f4: 681b ldr r3, [r3, #0]
80059f6: 689a ldr r2, [r3, #8]
80059f8: 687b ldr r3, [r7, #4]
80059fa: 681b ldr r3, [r3, #0]
80059fc: 2101 movs r1, #1
80059fe: 438a bics r2, r1
8005a00: 609a str r2, [r3, #8]
8005a02: 6f7b ldr r3, [r7, #116] ; 0x74
8005a04: 647b str r3, [r7, #68] ; 0x44
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8005a06: 6c7b ldr r3, [r7, #68] ; 0x44
8005a08: f383 8810 msr PRIMASK, r3
}
8005a0c: 46c0 nop ; (mov r8, r8)
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8005a0e: f3ef 8310 mrs r3, PRIMASK
8005a12: 64bb str r3, [r7, #72] ; 0x48
return(result);
8005a14: 6cbb ldr r3, [r7, #72] ; 0x48
/* Disable the DMA transfer for the receiver request by resetting the DMAR bit
in the UART CR3 register */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
8005a16: 673b str r3, [r7, #112] ; 0x70
8005a18: 2301 movs r3, #1
8005a1a: 64fb str r3, [r7, #76] ; 0x4c
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8005a1c: 6cfb ldr r3, [r7, #76] ; 0x4c
8005a1e: f383 8810 msr PRIMASK, r3
}
8005a22: 46c0 nop ; (mov r8, r8)
8005a24: 687b ldr r3, [r7, #4]
8005a26: 681b ldr r3, [r3, #0]
8005a28: 689a ldr r2, [r3, #8]
8005a2a: 687b ldr r3, [r7, #4]
8005a2c: 681b ldr r3, [r3, #0]
8005a2e: 2140 movs r1, #64 ; 0x40
8005a30: 438a bics r2, r1
8005a32: 609a str r2, [r3, #8]
8005a34: 6f3b ldr r3, [r7, #112] ; 0x70
8005a36: 653b str r3, [r7, #80] ; 0x50
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8005a38: 6d3b ldr r3, [r7, #80] ; 0x50
8005a3a: f383 8810 msr PRIMASK, r3
}
8005a3e: 46c0 nop ; (mov r8, r8)
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
8005a40: 687b ldr r3, [r7, #4]
8005a42: 2288 movs r2, #136 ; 0x88
8005a44: 2120 movs r1, #32
8005a46: 5099 str r1, [r3, r2]
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8005a48: 687b ldr r3, [r7, #4]
8005a4a: 2200 movs r2, #0
8005a4c: 66da str r2, [r3, #108] ; 0x6c
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8005a4e: f3ef 8310 mrs r3, PRIMASK
8005a52: 657b str r3, [r7, #84] ; 0x54
return(result);
8005a54: 6d7b ldr r3, [r7, #84] ; 0x54
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8005a56: 66fb str r3, [r7, #108] ; 0x6c
8005a58: 2301 movs r3, #1
8005a5a: 65bb str r3, [r7, #88] ; 0x58
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8005a5c: 6dbb ldr r3, [r7, #88] ; 0x58
8005a5e: f383 8810 msr PRIMASK, r3
}
8005a62: 46c0 nop ; (mov r8, r8)
8005a64: 687b ldr r3, [r7, #4]
8005a66: 681b ldr r3, [r3, #0]
8005a68: 681a ldr r2, [r3, #0]
8005a6a: 687b ldr r3, [r7, #4]
8005a6c: 681b ldr r3, [r3, #0]
8005a6e: 2110 movs r1, #16
8005a70: 438a bics r2, r1
8005a72: 601a str r2, [r3, #0]
8005a74: 6efb ldr r3, [r7, #108] ; 0x6c
8005a76: 65fb str r3, [r7, #92] ; 0x5c
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8005a78: 6dfb ldr r3, [r7, #92] ; 0x5c
8005a7a: f383 8810 msr PRIMASK, r3
}
8005a7e: 46c0 nop ; (mov r8, r8)
/* Last bytes received, so no need as the abort is immediate */
(void)HAL_DMA_Abort(huart->hdmarx);
8005a80: 687b ldr r3, [r7, #4]
8005a82: 6fdb ldr r3, [r3, #124] ; 0x7c
8005a84: 0018 movs r0, r3
8005a86: f7fd fb4f bl 8003128 <HAL_DMA_Abort>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
8005a8a: 687b ldr r3, [r7, #4]
8005a8c: 225c movs r2, #92 ; 0x5c
8005a8e: 5a9a ldrh r2, [r3, r2]
8005a90: 687b ldr r3, [r7, #4]
8005a92: 215e movs r1, #94 ; 0x5e
8005a94: 5a5b ldrh r3, [r3, r1]
8005a96: b29b uxth r3, r3
8005a98: 1ad3 subs r3, r2, r3
8005a9a: b29a uxth r2, r3
8005a9c: 687b ldr r3, [r7, #4]
8005a9e: 0011 movs r1, r2
8005aa0: 0018 movs r0, r3
8005aa2: f000 f903 bl 8005cac <HAL_UARTEx_RxEventCallback>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
return;
8005aa6: e0ea b.n 8005c7e <HAL_UART_IRQHandler+0x616>
else
{
/* DMA mode not enabled */
/* Check received length : If all expected data are received, do nothing.
Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
8005aa8: 687b ldr r3, [r7, #4]
8005aaa: 225c movs r2, #92 ; 0x5c
8005aac: 5a99 ldrh r1, [r3, r2]
8005aae: 687b ldr r3, [r7, #4]
8005ab0: 225e movs r2, #94 ; 0x5e
8005ab2: 5a9b ldrh r3, [r3, r2]
8005ab4: b29a uxth r2, r3
8005ab6: 208e movs r0, #142 ; 0x8e
8005ab8: 183b adds r3, r7, r0
8005aba: 1a8a subs r2, r1, r2
8005abc: 801a strh r2, [r3, #0]
if ((huart->RxXferCount > 0U)
8005abe: 687b ldr r3, [r7, #4]
8005ac0: 225e movs r2, #94 ; 0x5e
8005ac2: 5a9b ldrh r3, [r3, r2]
8005ac4: b29b uxth r3, r3
8005ac6: 2b00 cmp r3, #0
8005ac8: d100 bne.n 8005acc <HAL_UART_IRQHandler+0x464>
8005aca: e0da b.n 8005c82 <HAL_UART_IRQHandler+0x61a>
&& (nb_rx_data > 0U))
8005acc: 183b adds r3, r7, r0
8005ace: 881b ldrh r3, [r3, #0]
8005ad0: 2b00 cmp r3, #0
8005ad2: d100 bne.n 8005ad6 <HAL_UART_IRQHandler+0x46e>
8005ad4: e0d5 b.n 8005c82 <HAL_UART_IRQHandler+0x61a>
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8005ad6: f3ef 8310 mrs r3, PRIMASK
8005ada: 60fb str r3, [r7, #12]
return(result);
8005adc: 68fb ldr r3, [r7, #12]
{
/* Disable the UART Parity Error Interrupt and RXNE interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
8005ade: 2488 movs r4, #136 ; 0x88
8005ae0: 193a adds r2, r7, r4
8005ae2: 6013 str r3, [r2, #0]
8005ae4: 2301 movs r3, #1
8005ae6: 613b str r3, [r7, #16]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8005ae8: 693b ldr r3, [r7, #16]
8005aea: f383 8810 msr PRIMASK, r3
}
8005aee: 46c0 nop ; (mov r8, r8)
8005af0: 687b ldr r3, [r7, #4]
8005af2: 681b ldr r3, [r3, #0]
8005af4: 681a ldr r2, [r3, #0]
8005af6: 687b ldr r3, [r7, #4]
8005af8: 681b ldr r3, [r3, #0]
8005afa: 4966 ldr r1, [pc, #408] ; (8005c94 <HAL_UART_IRQHandler+0x62c>)
8005afc: 400a ands r2, r1
8005afe: 601a str r2, [r3, #0]
8005b00: 193b adds r3, r7, r4
8005b02: 681b ldr r3, [r3, #0]
8005b04: 617b str r3, [r7, #20]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8005b06: 697b ldr r3, [r7, #20]
8005b08: f383 8810 msr PRIMASK, r3
}
8005b0c: 46c0 nop ; (mov r8, r8)
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8005b0e: f3ef 8310 mrs r3, PRIMASK
8005b12: 61bb str r3, [r7, #24]
return(result);
8005b14: 69bb ldr r3, [r7, #24]
/* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
8005b16: 2484 movs r4, #132 ; 0x84
8005b18: 193a adds r2, r7, r4
8005b1a: 6013 str r3, [r2, #0]
8005b1c: 2301 movs r3, #1
8005b1e: 61fb str r3, [r7, #28]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8005b20: 69fb ldr r3, [r7, #28]
8005b22: f383 8810 msr PRIMASK, r3
}
8005b26: 46c0 nop ; (mov r8, r8)
8005b28: 687b ldr r3, [r7, #4]
8005b2a: 681b ldr r3, [r3, #0]
8005b2c: 689a ldr r2, [r3, #8]
8005b2e: 687b ldr r3, [r7, #4]
8005b30: 681b ldr r3, [r3, #0]
8005b32: 4959 ldr r1, [pc, #356] ; (8005c98 <HAL_UART_IRQHandler+0x630>)
8005b34: 400a ands r2, r1
8005b36: 609a str r2, [r3, #8]
8005b38: 193b adds r3, r7, r4
8005b3a: 681b ldr r3, [r3, #0]
8005b3c: 623b str r3, [r7, #32]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8005b3e: 6a3b ldr r3, [r7, #32]
8005b40: f383 8810 msr PRIMASK, r3
}
8005b44: 46c0 nop ; (mov r8, r8)
/* Rx process is completed, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
8005b46: 687b ldr r3, [r7, #4]
8005b48: 2288 movs r2, #136 ; 0x88
8005b4a: 2120 movs r1, #32
8005b4c: 5099 str r1, [r3, r2]
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8005b4e: 687b ldr r3, [r7, #4]
8005b50: 2200 movs r2, #0
8005b52: 66da str r2, [r3, #108] ; 0x6c
/* Clear RxISR function pointer */
huart->RxISR = NULL;
8005b54: 687b ldr r3, [r7, #4]
8005b56: 2200 movs r2, #0
8005b58: 671a str r2, [r3, #112] ; 0x70
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8005b5a: f3ef 8310 mrs r3, PRIMASK
8005b5e: 627b str r3, [r7, #36] ; 0x24
return(result);
8005b60: 6a7b ldr r3, [r7, #36] ; 0x24
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8005b62: 2480 movs r4, #128 ; 0x80
8005b64: 193a adds r2, r7, r4
8005b66: 6013 str r3, [r2, #0]
8005b68: 2301 movs r3, #1
8005b6a: 62bb str r3, [r7, #40] ; 0x28
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8005b6c: 6abb ldr r3, [r7, #40] ; 0x28
8005b6e: f383 8810 msr PRIMASK, r3
}
8005b72: 46c0 nop ; (mov r8, r8)
8005b74: 687b ldr r3, [r7, #4]
8005b76: 681b ldr r3, [r3, #0]
8005b78: 681a ldr r2, [r3, #0]
8005b7a: 687b ldr r3, [r7, #4]
8005b7c: 681b ldr r3, [r3, #0]
8005b7e: 2110 movs r1, #16
8005b80: 438a bics r2, r1
8005b82: 601a str r2, [r3, #0]
8005b84: 193b adds r3, r7, r4
8005b86: 681b ldr r3, [r3, #0]
8005b88: 62fb str r3, [r7, #44] ; 0x2c
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8005b8a: 6afb ldr r3, [r7, #44] ; 0x2c
8005b8c: f383 8810 msr PRIMASK, r3
}
8005b90: 46c0 nop ; (mov r8, r8)
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx complete callback*/
huart->RxEventCallback(huart, nb_rx_data);
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, nb_rx_data);
8005b92: 183b adds r3, r7, r0
8005b94: 881a ldrh r2, [r3, #0]
8005b96: 687b ldr r3, [r7, #4]
8005b98: 0011 movs r1, r2
8005b9a: 0018 movs r0, r3
8005b9c: f000 f886 bl 8005cac <HAL_UARTEx_RxEventCallback>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
return;
8005ba0: e06f b.n 8005c82 <HAL_UART_IRQHandler+0x61a>
}
}
/* UART wakeup from Stop mode interrupt occurred ---------------------------*/
if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U))
8005ba2: 23a4 movs r3, #164 ; 0xa4
8005ba4: 18fb adds r3, r7, r3
8005ba6: 681a ldr r2, [r3, #0]
8005ba8: 2380 movs r3, #128 ; 0x80
8005baa: 035b lsls r3, r3, #13
8005bac: 4013 ands r3, r2
8005bae: d010 beq.n 8005bd2 <HAL_UART_IRQHandler+0x56a>
8005bb0: 239c movs r3, #156 ; 0x9c
8005bb2: 18fb adds r3, r7, r3
8005bb4: 681a ldr r2, [r3, #0]
8005bb6: 2380 movs r3, #128 ; 0x80
8005bb8: 03db lsls r3, r3, #15
8005bba: 4013 ands r3, r2
8005bbc: d009 beq.n 8005bd2 <HAL_UART_IRQHandler+0x56a>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF);
8005bbe: 687b ldr r3, [r7, #4]
8005bc0: 681b ldr r3, [r3, #0]
8005bc2: 2280 movs r2, #128 ; 0x80
8005bc4: 0352 lsls r2, r2, #13
8005bc6: 621a str r2, [r3, #32]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/* Call registered Wakeup Callback */
huart->WakeupCallback(huart);
#else
/* Call legacy weak Wakeup Callback */
HAL_UARTEx_WakeupCallback(huart);
8005bc8: 687b ldr r3, [r7, #4]
8005bca: 0018 movs r0, r3
8005bcc: f001 fbbc bl 8007348 <HAL_UARTEx_WakeupCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
return;
8005bd0: e05a b.n 8005c88 <HAL_UART_IRQHandler+0x620>
}
/* UART in mode Transmitter ------------------------------------------------*/
if (((isrflags & USART_ISR_TXE_TXFNF) != 0U)
8005bd2: 23a4 movs r3, #164 ; 0xa4
8005bd4: 18fb adds r3, r7, r3
8005bd6: 681b ldr r3, [r3, #0]
8005bd8: 2280 movs r2, #128 ; 0x80
8005bda: 4013 ands r3, r2
8005bdc: d016 beq.n 8005c0c <HAL_UART_IRQHandler+0x5a4>
&& (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)
8005bde: 23a0 movs r3, #160 ; 0xa0
8005be0: 18fb adds r3, r7, r3
8005be2: 681b ldr r3, [r3, #0]
8005be4: 2280 movs r2, #128 ; 0x80
8005be6: 4013 ands r3, r2
8005be8: d106 bne.n 8005bf8 <HAL_UART_IRQHandler+0x590>
|| ((cr3its & USART_CR3_TXFTIE) != 0U)))
8005bea: 239c movs r3, #156 ; 0x9c
8005bec: 18fb adds r3, r7, r3
8005bee: 681a ldr r2, [r3, #0]
8005bf0: 2380 movs r3, #128 ; 0x80
8005bf2: 041b lsls r3, r3, #16
8005bf4: 4013 ands r3, r2
8005bf6: d009 beq.n 8005c0c <HAL_UART_IRQHandler+0x5a4>
{
if (huart->TxISR != NULL)
8005bf8: 687b ldr r3, [r7, #4]
8005bfa: 6f5b ldr r3, [r3, #116] ; 0x74
8005bfc: 2b00 cmp r3, #0
8005bfe: d042 beq.n 8005c86 <HAL_UART_IRQHandler+0x61e>
{
huart->TxISR(huart);
8005c00: 687b ldr r3, [r7, #4]
8005c02: 6f5b ldr r3, [r3, #116] ; 0x74
8005c04: 687a ldr r2, [r7, #4]
8005c06: 0010 movs r0, r2
8005c08: 4798 blx r3
}
return;
8005c0a: e03c b.n 8005c86 <HAL_UART_IRQHandler+0x61e>
}
/* UART in mode Transmitter (transmission end) -----------------------------*/
if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
8005c0c: 23a4 movs r3, #164 ; 0xa4
8005c0e: 18fb adds r3, r7, r3
8005c10: 681b ldr r3, [r3, #0]
8005c12: 2240 movs r2, #64 ; 0x40
8005c14: 4013 ands r3, r2
8005c16: d00a beq.n 8005c2e <HAL_UART_IRQHandler+0x5c6>
8005c18: 23a0 movs r3, #160 ; 0xa0
8005c1a: 18fb adds r3, r7, r3
8005c1c: 681b ldr r3, [r3, #0]
8005c1e: 2240 movs r2, #64 ; 0x40
8005c20: 4013 ands r3, r2
8005c22: d004 beq.n 8005c2e <HAL_UART_IRQHandler+0x5c6>
{
UART_EndTransmit_IT(huart);
8005c24: 687b ldr r3, [r7, #4]
8005c26: 0018 movs r0, r3
8005c28: f000 ff11 bl 8006a4e <UART_EndTransmit_IT>
return;
8005c2c: e02c b.n 8005c88 <HAL_UART_IRQHandler+0x620>
}
/* UART TX Fifo Empty occurred ----------------------------------------------*/
if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U))
8005c2e: 23a4 movs r3, #164 ; 0xa4
8005c30: 18fb adds r3, r7, r3
8005c32: 681a ldr r2, [r3, #0]
8005c34: 2380 movs r3, #128 ; 0x80
8005c36: 041b lsls r3, r3, #16
8005c38: 4013 ands r3, r2
8005c3a: d00b beq.n 8005c54 <HAL_UART_IRQHandler+0x5ec>
8005c3c: 23a0 movs r3, #160 ; 0xa0
8005c3e: 18fb adds r3, r7, r3
8005c40: 681a ldr r2, [r3, #0]
8005c42: 2380 movs r3, #128 ; 0x80
8005c44: 05db lsls r3, r3, #23
8005c46: 4013 ands r3, r2
8005c48: d004 beq.n 8005c54 <HAL_UART_IRQHandler+0x5ec>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/* Call registered Tx Fifo Empty Callback */
huart->TxFifoEmptyCallback(huart);
#else
/* Call legacy weak Tx Fifo Empty Callback */
HAL_UARTEx_TxFifoEmptyCallback(huart);
8005c4a: 687b ldr r3, [r7, #4]
8005c4c: 0018 movs r0, r3
8005c4e: f001 fb8b bl 8007368 <HAL_UARTEx_TxFifoEmptyCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
return;
8005c52: e019 b.n 8005c88 <HAL_UART_IRQHandler+0x620>
}
/* UART RX Fifo Full occurred ----------------------------------------------*/
if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U))
8005c54: 23a4 movs r3, #164 ; 0xa4
8005c56: 18fb adds r3, r7, r3
8005c58: 681a ldr r2, [r3, #0]
8005c5a: 2380 movs r3, #128 ; 0x80
8005c5c: 045b lsls r3, r3, #17
8005c5e: 4013 ands r3, r2
8005c60: d012 beq.n 8005c88 <HAL_UART_IRQHandler+0x620>
8005c62: 23a0 movs r3, #160 ; 0xa0
8005c64: 18fb adds r3, r7, r3
8005c66: 681b ldr r3, [r3, #0]
8005c68: 2b00 cmp r3, #0
8005c6a: da0d bge.n 8005c88 <HAL_UART_IRQHandler+0x620>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/* Call registered Rx Fifo Full Callback */
huart->RxFifoFullCallback(huart);
#else
/* Call legacy weak Rx Fifo Full Callback */
HAL_UARTEx_RxFifoFullCallback(huart);
8005c6c: 687b ldr r3, [r7, #4]
8005c6e: 0018 movs r0, r3
8005c70: f001 fb72 bl 8007358 <HAL_UARTEx_RxFifoFullCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
return;
8005c74: e008 b.n 8005c88 <HAL_UART_IRQHandler+0x620>
return;
8005c76: 46c0 nop ; (mov r8, r8)
8005c78: e006 b.n 8005c88 <HAL_UART_IRQHandler+0x620>
return;
8005c7a: 46c0 nop ; (mov r8, r8)
8005c7c: e004 b.n 8005c88 <HAL_UART_IRQHandler+0x620>
return;
8005c7e: 46c0 nop ; (mov r8, r8)
8005c80: e002 b.n 8005c88 <HAL_UART_IRQHandler+0x620>
return;
8005c82: 46c0 nop ; (mov r8, r8)
8005c84: e000 b.n 8005c88 <HAL_UART_IRQHandler+0x620>
return;
8005c86: 46c0 nop ; (mov r8, r8)
}
}
8005c88: 46bd mov sp, r7
8005c8a: b02a add sp, #168 ; 0xa8
8005c8c: bdb0 pop {r4, r5, r7, pc}
8005c8e: 46c0 nop ; (mov r8, r8)
8005c90: fffffeff .word 0xfffffeff
8005c94: fffffedf .word 0xfffffedf
8005c98: effffffe .word 0xeffffffe
08005c9c <HAL_UART_TxHalfCpltCallback>:
* @brief Tx Half Transfer completed callback.
* @param huart UART handle.
* @retval None
*/
__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
{
8005c9c: b580 push {r7, lr}
8005c9e: b082 sub sp, #8
8005ca0: af00 add r7, sp, #0
8005ca2: 6078 str r0, [r7, #4]
UNUSED(huart);
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_UART_TxHalfCpltCallback can be implemented in the user file.
*/
}
8005ca4: 46c0 nop ; (mov r8, r8)
8005ca6: 46bd mov sp, r7
8005ca8: b002 add sp, #8
8005caa: bd80 pop {r7, pc}
08005cac <HAL_UARTEx_RxEventCallback>:
* @param Size Number of data available in application reception buffer (indicates a position in
* reception buffer until which, data are available)
* @retval None
*/
__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size)
{
8005cac: b580 push {r7, lr}
8005cae: b082 sub sp, #8
8005cb0: af00 add r7, sp, #0
8005cb2: 6078 str r0, [r7, #4]
8005cb4: 000a movs r2, r1
8005cb6: 1cbb adds r3, r7, #2
8005cb8: 801a strh r2, [r3, #0]
UNUSED(Size);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_UARTEx_RxEventCallback can be implemented in the user file.
*/
}
8005cba: 46c0 nop ; (mov r8, r8)
8005cbc: 46bd mov sp, r7
8005cbe: b002 add sp, #8
8005cc0: bd80 pop {r7, pc}
...
08005cc4 <UART_SetConfig>:
* @brief Configure the UART peripheral.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
{
8005cc4: b5b0 push {r4, r5, r7, lr}
8005cc6: b090 sub sp, #64 ; 0x40
8005cc8: af00 add r7, sp, #0
8005cca: 6278 str r0, [r7, #36] ; 0x24
uint32_t tmpreg;
uint16_t brrtemp;
UART_ClockSourceTypeDef clocksource;
uint32_t usartdiv;
HAL_StatusTypeDef ret = HAL_OK;
8005ccc: 231a movs r3, #26
8005cce: 2220 movs r2, #32
8005cd0: 189b adds r3, r3, r2
8005cd2: 19db adds r3, r3, r7
8005cd4: 2200 movs r2, #0
8005cd6: 701a strb r2, [r3, #0]
* the UART Word Length, Parity, Mode and oversampling:
* set the M bits according to huart->Init.WordLength value
* set PCE and PS bits according to huart->Init.Parity value
* set TE and RE bits according to huart->Init.Mode value
* set OVER8 bit according to huart->Init.OverSampling value */
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
8005cd8: 6a7b ldr r3, [r7, #36] ; 0x24
8005cda: 689a ldr r2, [r3, #8]
8005cdc: 6a7b ldr r3, [r7, #36] ; 0x24
8005cde: 691b ldr r3, [r3, #16]
8005ce0: 431a orrs r2, r3
8005ce2: 6a7b ldr r3, [r7, #36] ; 0x24
8005ce4: 695b ldr r3, [r3, #20]
8005ce6: 431a orrs r2, r3
8005ce8: 6a7b ldr r3, [r7, #36] ; 0x24
8005cea: 69db ldr r3, [r3, #28]
8005cec: 4313 orrs r3, r2
8005cee: 63fb str r3, [r7, #60] ; 0x3c
MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
8005cf0: 6a7b ldr r3, [r7, #36] ; 0x24
8005cf2: 681b ldr r3, [r3, #0]
8005cf4: 681b ldr r3, [r3, #0]
8005cf6: 4ac4 ldr r2, [pc, #784] ; (8006008 <UART_SetConfig+0x344>)
8005cf8: 4013 ands r3, r2
8005cfa: 0019 movs r1, r3
8005cfc: 6a7b ldr r3, [r7, #36] ; 0x24
8005cfe: 681a ldr r2, [r3, #0]
8005d00: 6bfb ldr r3, [r7, #60] ; 0x3c
8005d02: 430b orrs r3, r1
8005d04: 6013 str r3, [r2, #0]
/*-------------------------- USART CR2 Configuration -----------------------*/
/* Configure the UART Stop Bits: Set STOP[13:12] bits according
* to huart->Init.StopBits value */
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
8005d06: 6a7b ldr r3, [r7, #36] ; 0x24
8005d08: 681b ldr r3, [r3, #0]
8005d0a: 685b ldr r3, [r3, #4]
8005d0c: 4abf ldr r2, [pc, #764] ; (800600c <UART_SetConfig+0x348>)
8005d0e: 4013 ands r3, r2
8005d10: 0018 movs r0, r3
8005d12: 6a7b ldr r3, [r7, #36] ; 0x24
8005d14: 68d9 ldr r1, [r3, #12]
8005d16: 6a7b ldr r3, [r7, #36] ; 0x24
8005d18: 681a ldr r2, [r3, #0]
8005d1a: 0003 movs r3, r0
8005d1c: 430b orrs r3, r1
8005d1e: 6053 str r3, [r2, #4]
/* Configure
* - UART HardWare Flow Control: set CTSE and RTSE bits according
* to huart->Init.HwFlowCtl value
* - one-bit sampling method versus three samples' majority rule according
* to huart->Init.OneBitSampling (not applicable to LPUART) */
tmpreg = (uint32_t)huart->Init.HwFlowCtl;
8005d20: 6a7b ldr r3, [r7, #36] ; 0x24
8005d22: 699b ldr r3, [r3, #24]
8005d24: 63fb str r3, [r7, #60] ; 0x3c
if (!(UART_INSTANCE_LOWPOWER(huart)))
8005d26: 6a7b ldr r3, [r7, #36] ; 0x24
8005d28: 681b ldr r3, [r3, #0]
8005d2a: 4ab9 ldr r2, [pc, #740] ; (8006010 <UART_SetConfig+0x34c>)
8005d2c: 4293 cmp r3, r2
8005d2e: d004 beq.n 8005d3a <UART_SetConfig+0x76>
{
tmpreg |= huart->Init.OneBitSampling;
8005d30: 6a7b ldr r3, [r7, #36] ; 0x24
8005d32: 6a1b ldr r3, [r3, #32]
8005d34: 6bfa ldr r2, [r7, #60] ; 0x3c
8005d36: 4313 orrs r3, r2
8005d38: 63fb str r3, [r7, #60] ; 0x3c
}
MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
8005d3a: 6a7b ldr r3, [r7, #36] ; 0x24
8005d3c: 681b ldr r3, [r3, #0]
8005d3e: 689b ldr r3, [r3, #8]
8005d40: 4ab4 ldr r2, [pc, #720] ; (8006014 <UART_SetConfig+0x350>)
8005d42: 4013 ands r3, r2
8005d44: 0019 movs r1, r3
8005d46: 6a7b ldr r3, [r7, #36] ; 0x24
8005d48: 681a ldr r2, [r3, #0]
8005d4a: 6bfb ldr r3, [r7, #60] ; 0x3c
8005d4c: 430b orrs r3, r1
8005d4e: 6093 str r3, [r2, #8]
/*-------------------------- USART PRESC Configuration -----------------------*/
/* Configure
* - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */
MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
8005d50: 6a7b ldr r3, [r7, #36] ; 0x24
8005d52: 681b ldr r3, [r3, #0]
8005d54: 6adb ldr r3, [r3, #44] ; 0x2c
8005d56: 220f movs r2, #15
8005d58: 4393 bics r3, r2
8005d5a: 0018 movs r0, r3
8005d5c: 6a7b ldr r3, [r7, #36] ; 0x24
8005d5e: 6a59 ldr r1, [r3, #36] ; 0x24
8005d60: 6a7b ldr r3, [r7, #36] ; 0x24
8005d62: 681a ldr r2, [r3, #0]
8005d64: 0003 movs r3, r0
8005d66: 430b orrs r3, r1
8005d68: 62d3 str r3, [r2, #44] ; 0x2c
/*-------------------------- USART BRR Configuration -----------------------*/
UART_GETCLOCKSOURCE(huart, clocksource);
8005d6a: 6a7b ldr r3, [r7, #36] ; 0x24
8005d6c: 681b ldr r3, [r3, #0]
8005d6e: 4aaa ldr r2, [pc, #680] ; (8006018 <UART_SetConfig+0x354>)
8005d70: 4293 cmp r3, r2
8005d72: d131 bne.n 8005dd8 <UART_SetConfig+0x114>
8005d74: 4ba9 ldr r3, [pc, #676] ; (800601c <UART_SetConfig+0x358>)
8005d76: 6d5b ldr r3, [r3, #84] ; 0x54
8005d78: 2203 movs r2, #3
8005d7a: 4013 ands r3, r2
8005d7c: 2b03 cmp r3, #3
8005d7e: d01d beq.n 8005dbc <UART_SetConfig+0xf8>
8005d80: d823 bhi.n 8005dca <UART_SetConfig+0x106>
8005d82: 2b02 cmp r3, #2
8005d84: d00c beq.n 8005da0 <UART_SetConfig+0xdc>
8005d86: d820 bhi.n 8005dca <UART_SetConfig+0x106>
8005d88: 2b00 cmp r3, #0
8005d8a: d002 beq.n 8005d92 <UART_SetConfig+0xce>
8005d8c: 2b01 cmp r3, #1
8005d8e: d00e beq.n 8005dae <UART_SetConfig+0xea>
8005d90: e01b b.n 8005dca <UART_SetConfig+0x106>
8005d92: 231b movs r3, #27
8005d94: 2220 movs r2, #32
8005d96: 189b adds r3, r3, r2
8005d98: 19db adds r3, r3, r7
8005d9a: 2200 movs r2, #0
8005d9c: 701a strb r2, [r3, #0]
8005d9e: e071 b.n 8005e84 <UART_SetConfig+0x1c0>
8005da0: 231b movs r3, #27
8005da2: 2220 movs r2, #32
8005da4: 189b adds r3, r3, r2
8005da6: 19db adds r3, r3, r7
8005da8: 2202 movs r2, #2
8005daa: 701a strb r2, [r3, #0]
8005dac: e06a b.n 8005e84 <UART_SetConfig+0x1c0>
8005dae: 231b movs r3, #27
8005db0: 2220 movs r2, #32
8005db2: 189b adds r3, r3, r2
8005db4: 19db adds r3, r3, r7
8005db6: 2204 movs r2, #4
8005db8: 701a strb r2, [r3, #0]
8005dba: e063 b.n 8005e84 <UART_SetConfig+0x1c0>
8005dbc: 231b movs r3, #27
8005dbe: 2220 movs r2, #32
8005dc0: 189b adds r3, r3, r2
8005dc2: 19db adds r3, r3, r7
8005dc4: 2208 movs r2, #8
8005dc6: 701a strb r2, [r3, #0]
8005dc8: e05c b.n 8005e84 <UART_SetConfig+0x1c0>
8005dca: 231b movs r3, #27
8005dcc: 2220 movs r2, #32
8005dce: 189b adds r3, r3, r2
8005dd0: 19db adds r3, r3, r7
8005dd2: 2210 movs r2, #16
8005dd4: 701a strb r2, [r3, #0]
8005dd6: e055 b.n 8005e84 <UART_SetConfig+0x1c0>
8005dd8: 6a7b ldr r3, [r7, #36] ; 0x24
8005dda: 681b ldr r3, [r3, #0]
8005ddc: 4a90 ldr r2, [pc, #576] ; (8006020 <UART_SetConfig+0x35c>)
8005dde: 4293 cmp r3, r2
8005de0: d106 bne.n 8005df0 <UART_SetConfig+0x12c>
8005de2: 231b movs r3, #27
8005de4: 2220 movs r2, #32
8005de6: 189b adds r3, r3, r2
8005de8: 19db adds r3, r3, r7
8005dea: 2200 movs r2, #0
8005dec: 701a strb r2, [r3, #0]
8005dee: e049 b.n 8005e84 <UART_SetConfig+0x1c0>
8005df0: 6a7b ldr r3, [r7, #36] ; 0x24
8005df2: 681b ldr r3, [r3, #0]
8005df4: 4a86 ldr r2, [pc, #536] ; (8006010 <UART_SetConfig+0x34c>)
8005df6: 4293 cmp r3, r2
8005df8: d13e bne.n 8005e78 <UART_SetConfig+0x1b4>
8005dfa: 4b88 ldr r3, [pc, #544] ; (800601c <UART_SetConfig+0x358>)
8005dfc: 6d5a ldr r2, [r3, #84] ; 0x54
8005dfe: 23c0 movs r3, #192 ; 0xc0
8005e00: 011b lsls r3, r3, #4
8005e02: 4013 ands r3, r2
8005e04: 22c0 movs r2, #192 ; 0xc0
8005e06: 0112 lsls r2, r2, #4
8005e08: 4293 cmp r3, r2
8005e0a: d027 beq.n 8005e5c <UART_SetConfig+0x198>
8005e0c: 22c0 movs r2, #192 ; 0xc0
8005e0e: 0112 lsls r2, r2, #4
8005e10: 4293 cmp r3, r2
8005e12: d82a bhi.n 8005e6a <UART_SetConfig+0x1a6>
8005e14: 2280 movs r2, #128 ; 0x80
8005e16: 0112 lsls r2, r2, #4
8005e18: 4293 cmp r3, r2
8005e1a: d011 beq.n 8005e40 <UART_SetConfig+0x17c>
8005e1c: 2280 movs r2, #128 ; 0x80
8005e1e: 0112 lsls r2, r2, #4
8005e20: 4293 cmp r3, r2
8005e22: d822 bhi.n 8005e6a <UART_SetConfig+0x1a6>
8005e24: 2b00 cmp r3, #0
8005e26: d004 beq.n 8005e32 <UART_SetConfig+0x16e>
8005e28: 2280 movs r2, #128 ; 0x80
8005e2a: 00d2 lsls r2, r2, #3
8005e2c: 4293 cmp r3, r2
8005e2e: d00e beq.n 8005e4e <UART_SetConfig+0x18a>
8005e30: e01b b.n 8005e6a <UART_SetConfig+0x1a6>
8005e32: 231b movs r3, #27
8005e34: 2220 movs r2, #32
8005e36: 189b adds r3, r3, r2
8005e38: 19db adds r3, r3, r7
8005e3a: 2200 movs r2, #0
8005e3c: 701a strb r2, [r3, #0]
8005e3e: e021 b.n 8005e84 <UART_SetConfig+0x1c0>
8005e40: 231b movs r3, #27
8005e42: 2220 movs r2, #32
8005e44: 189b adds r3, r3, r2
8005e46: 19db adds r3, r3, r7
8005e48: 2202 movs r2, #2
8005e4a: 701a strb r2, [r3, #0]
8005e4c: e01a b.n 8005e84 <UART_SetConfig+0x1c0>
8005e4e: 231b movs r3, #27
8005e50: 2220 movs r2, #32
8005e52: 189b adds r3, r3, r2
8005e54: 19db adds r3, r3, r7
8005e56: 2204 movs r2, #4
8005e58: 701a strb r2, [r3, #0]
8005e5a: e013 b.n 8005e84 <UART_SetConfig+0x1c0>
8005e5c: 231b movs r3, #27
8005e5e: 2220 movs r2, #32
8005e60: 189b adds r3, r3, r2
8005e62: 19db adds r3, r3, r7
8005e64: 2208 movs r2, #8
8005e66: 701a strb r2, [r3, #0]
8005e68: e00c b.n 8005e84 <UART_SetConfig+0x1c0>
8005e6a: 231b movs r3, #27
8005e6c: 2220 movs r2, #32
8005e6e: 189b adds r3, r3, r2
8005e70: 19db adds r3, r3, r7
8005e72: 2210 movs r2, #16
8005e74: 701a strb r2, [r3, #0]
8005e76: e005 b.n 8005e84 <UART_SetConfig+0x1c0>
8005e78: 231b movs r3, #27
8005e7a: 2220 movs r2, #32
8005e7c: 189b adds r3, r3, r2
8005e7e: 19db adds r3, r3, r7
8005e80: 2210 movs r2, #16
8005e82: 701a strb r2, [r3, #0]
/* Check LPUART instance */
if (UART_INSTANCE_LOWPOWER(huart))
8005e84: 6a7b ldr r3, [r7, #36] ; 0x24
8005e86: 681b ldr r3, [r3, #0]
8005e88: 4a61 ldr r2, [pc, #388] ; (8006010 <UART_SetConfig+0x34c>)
8005e8a: 4293 cmp r3, r2
8005e8c: d000 beq.n 8005e90 <UART_SetConfig+0x1cc>
8005e8e: e092 b.n 8005fb6 <UART_SetConfig+0x2f2>
{
/* Retrieve frequency clock */
switch (clocksource)
8005e90: 231b movs r3, #27
8005e92: 2220 movs r2, #32
8005e94: 189b adds r3, r3, r2
8005e96: 19db adds r3, r3, r7
8005e98: 781b ldrb r3, [r3, #0]
8005e9a: 2b08 cmp r3, #8
8005e9c: d015 beq.n 8005eca <UART_SetConfig+0x206>
8005e9e: dc18 bgt.n 8005ed2 <UART_SetConfig+0x20e>
8005ea0: 2b04 cmp r3, #4
8005ea2: d00d beq.n 8005ec0 <UART_SetConfig+0x1fc>
8005ea4: dc15 bgt.n 8005ed2 <UART_SetConfig+0x20e>
8005ea6: 2b00 cmp r3, #0
8005ea8: d002 beq.n 8005eb0 <UART_SetConfig+0x1ec>
8005eaa: 2b02 cmp r3, #2
8005eac: d005 beq.n 8005eba <UART_SetConfig+0x1f6>
8005eae: e010 b.n 8005ed2 <UART_SetConfig+0x20e>
{
case UART_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
8005eb0: f7fe f9c4 bl 800423c <HAL_RCC_GetPCLK1Freq>
8005eb4: 0003 movs r3, r0
8005eb6: 637b str r3, [r7, #52] ; 0x34
break;
8005eb8: e014 b.n 8005ee4 <UART_SetConfig+0x220>
case UART_CLOCKSOURCE_HSI:
pclk = (uint32_t) HSI_VALUE;
8005eba: 4b5a ldr r3, [pc, #360] ; (8006024 <UART_SetConfig+0x360>)
8005ebc: 637b str r3, [r7, #52] ; 0x34
break;
8005ebe: e011 b.n 8005ee4 <UART_SetConfig+0x220>
case UART_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
8005ec0: f7fe f930 bl 8004124 <HAL_RCC_GetSysClockFreq>
8005ec4: 0003 movs r3, r0
8005ec6: 637b str r3, [r7, #52] ; 0x34
break;
8005ec8: e00c b.n 8005ee4 <UART_SetConfig+0x220>
case UART_CLOCKSOURCE_LSE:
pclk = (uint32_t) LSE_VALUE;
8005eca: 2380 movs r3, #128 ; 0x80
8005ecc: 021b lsls r3, r3, #8
8005ece: 637b str r3, [r7, #52] ; 0x34
break;
8005ed0: e008 b.n 8005ee4 <UART_SetConfig+0x220>
default:
pclk = 0U;
8005ed2: 2300 movs r3, #0
8005ed4: 637b str r3, [r7, #52] ; 0x34
ret = HAL_ERROR;
8005ed6: 231a movs r3, #26
8005ed8: 2220 movs r2, #32
8005eda: 189b adds r3, r3, r2
8005edc: 19db adds r3, r3, r7
8005ede: 2201 movs r2, #1
8005ee0: 701a strb r2, [r3, #0]
break;
8005ee2: 46c0 nop ; (mov r8, r8)
}
/* If proper clock source reported */
if (pclk != 0U)
8005ee4: 6b7b ldr r3, [r7, #52] ; 0x34
8005ee6: 2b00 cmp r3, #0
8005ee8: d100 bne.n 8005eec <UART_SetConfig+0x228>
8005eea: e147 b.n 800617c <UART_SetConfig+0x4b8>
{
/* Compute clock after Prescaler */
lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]);
8005eec: 6a7b ldr r3, [r7, #36] ; 0x24
8005eee: 6a5a ldr r2, [r3, #36] ; 0x24
8005ef0: 4b4d ldr r3, [pc, #308] ; (8006028 <UART_SetConfig+0x364>)
8005ef2: 0052 lsls r2, r2, #1
8005ef4: 5ad3 ldrh r3, [r2, r3]
8005ef6: 0019 movs r1, r3
8005ef8: 6b78 ldr r0, [r7, #52] ; 0x34
8005efa: f7fa f903 bl 8000104 <__udivsi3>
8005efe: 0003 movs r3, r0
8005f00: 62bb str r3, [r7, #40] ; 0x28
/* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */
if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) ||
8005f02: 6a7b ldr r3, [r7, #36] ; 0x24
8005f04: 685a ldr r2, [r3, #4]
8005f06: 0013 movs r3, r2
8005f08: 005b lsls r3, r3, #1
8005f0a: 189b adds r3, r3, r2
8005f0c: 6aba ldr r2, [r7, #40] ; 0x28
8005f0e: 429a cmp r2, r3
8005f10: d305 bcc.n 8005f1e <UART_SetConfig+0x25a>
(lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate)))
8005f12: 6a7b ldr r3, [r7, #36] ; 0x24
8005f14: 685b ldr r3, [r3, #4]
8005f16: 031b lsls r3, r3, #12
if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) ||
8005f18: 6aba ldr r2, [r7, #40] ; 0x28
8005f1a: 429a cmp r2, r3
8005f1c: d906 bls.n 8005f2c <UART_SetConfig+0x268>
{
ret = HAL_ERROR;
8005f1e: 231a movs r3, #26
8005f20: 2220 movs r2, #32
8005f22: 189b adds r3, r3, r2
8005f24: 19db adds r3, r3, r7
8005f26: 2201 movs r2, #1
8005f28: 701a strb r2, [r3, #0]
8005f2a: e127 b.n 800617c <UART_SetConfig+0x4b8>
}
else
{
/* Check computed UsartDiv value is in allocated range
(it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */
usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
8005f2c: 6b7b ldr r3, [r7, #52] ; 0x34
8005f2e: 61bb str r3, [r7, #24]
8005f30: 2300 movs r3, #0
8005f32: 61fb str r3, [r7, #28]
8005f34: 6a7b ldr r3, [r7, #36] ; 0x24
8005f36: 6a5a ldr r2, [r3, #36] ; 0x24
8005f38: 4b3b ldr r3, [pc, #236] ; (8006028 <UART_SetConfig+0x364>)
8005f3a: 0052 lsls r2, r2, #1
8005f3c: 5ad3 ldrh r3, [r2, r3]
8005f3e: 613b str r3, [r7, #16]
8005f40: 2300 movs r3, #0
8005f42: 617b str r3, [r7, #20]
8005f44: 693a ldr r2, [r7, #16]
8005f46: 697b ldr r3, [r7, #20]
8005f48: 69b8 ldr r0, [r7, #24]
8005f4a: 69f9 ldr r1, [r7, #28]
8005f4c: f7fa f966 bl 800021c <__aeabi_uldivmod>
8005f50: 0002 movs r2, r0
8005f52: 000b movs r3, r1
8005f54: 0e11 lsrs r1, r2, #24
8005f56: 021d lsls r5, r3, #8
8005f58: 430d orrs r5, r1
8005f5a: 0214 lsls r4, r2, #8
8005f5c: 6a7b ldr r3, [r7, #36] ; 0x24
8005f5e: 685b ldr r3, [r3, #4]
8005f60: 085b lsrs r3, r3, #1
8005f62: 60bb str r3, [r7, #8]
8005f64: 2300 movs r3, #0
8005f66: 60fb str r3, [r7, #12]
8005f68: 68b8 ldr r0, [r7, #8]
8005f6a: 68f9 ldr r1, [r7, #12]
8005f6c: 1900 adds r0, r0, r4
8005f6e: 4169 adcs r1, r5
8005f70: 6a7b ldr r3, [r7, #36] ; 0x24
8005f72: 685b ldr r3, [r3, #4]
8005f74: 603b str r3, [r7, #0]
8005f76: 2300 movs r3, #0
8005f78: 607b str r3, [r7, #4]
8005f7a: 683a ldr r2, [r7, #0]
8005f7c: 687b ldr r3, [r7, #4]
8005f7e: f7fa f94d bl 800021c <__aeabi_uldivmod>
8005f82: 0002 movs r2, r0
8005f84: 000b movs r3, r1
8005f86: 0013 movs r3, r2
8005f88: 633b str r3, [r7, #48] ; 0x30
if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))
8005f8a: 6b3a ldr r2, [r7, #48] ; 0x30
8005f8c: 23c0 movs r3, #192 ; 0xc0
8005f8e: 009b lsls r3, r3, #2
8005f90: 429a cmp r2, r3
8005f92: d309 bcc.n 8005fa8 <UART_SetConfig+0x2e4>
8005f94: 6b3a ldr r2, [r7, #48] ; 0x30
8005f96: 2380 movs r3, #128 ; 0x80
8005f98: 035b lsls r3, r3, #13
8005f9a: 429a cmp r2, r3
8005f9c: d204 bcs.n 8005fa8 <UART_SetConfig+0x2e4>
{
huart->Instance->BRR = usartdiv;
8005f9e: 6a7b ldr r3, [r7, #36] ; 0x24
8005fa0: 681b ldr r3, [r3, #0]
8005fa2: 6b3a ldr r2, [r7, #48] ; 0x30
8005fa4: 60da str r2, [r3, #12]
8005fa6: e0e9 b.n 800617c <UART_SetConfig+0x4b8>
}
else
{
ret = HAL_ERROR;
8005fa8: 231a movs r3, #26
8005faa: 2220 movs r2, #32
8005fac: 189b adds r3, r3, r2
8005fae: 19db adds r3, r3, r7
8005fb0: 2201 movs r2, #1
8005fb2: 701a strb r2, [r3, #0]
8005fb4: e0e2 b.n 800617c <UART_SetConfig+0x4b8>
} /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) ||
(lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */
} /* if (pclk != 0) */
}
/* Check UART Over Sampling to set Baud Rate Register */
else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
8005fb6: 6a7b ldr r3, [r7, #36] ; 0x24
8005fb8: 69da ldr r2, [r3, #28]
8005fba: 2380 movs r3, #128 ; 0x80
8005fbc: 021b lsls r3, r3, #8
8005fbe: 429a cmp r2, r3
8005fc0: d000 beq.n 8005fc4 <UART_SetConfig+0x300>
8005fc2: e083 b.n 80060cc <UART_SetConfig+0x408>
{
switch (clocksource)
8005fc4: 231b movs r3, #27
8005fc6: 2220 movs r2, #32
8005fc8: 189b adds r3, r3, r2
8005fca: 19db adds r3, r3, r7
8005fcc: 781b ldrb r3, [r3, #0]
8005fce: 2b08 cmp r3, #8
8005fd0: d015 beq.n 8005ffe <UART_SetConfig+0x33a>
8005fd2: dc2b bgt.n 800602c <UART_SetConfig+0x368>
8005fd4: 2b04 cmp r3, #4
8005fd6: d00d beq.n 8005ff4 <UART_SetConfig+0x330>
8005fd8: dc28 bgt.n 800602c <UART_SetConfig+0x368>
8005fda: 2b00 cmp r3, #0
8005fdc: d002 beq.n 8005fe4 <UART_SetConfig+0x320>
8005fde: 2b02 cmp r3, #2
8005fe0: d005 beq.n 8005fee <UART_SetConfig+0x32a>
8005fe2: e023 b.n 800602c <UART_SetConfig+0x368>
{
case UART_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
8005fe4: f7fe f92a bl 800423c <HAL_RCC_GetPCLK1Freq>
8005fe8: 0003 movs r3, r0
8005fea: 637b str r3, [r7, #52] ; 0x34
break;
8005fec: e027 b.n 800603e <UART_SetConfig+0x37a>
case UART_CLOCKSOURCE_HSI:
pclk = (uint32_t) HSI_VALUE;
8005fee: 4b0d ldr r3, [pc, #52] ; (8006024 <UART_SetConfig+0x360>)
8005ff0: 637b str r3, [r7, #52] ; 0x34
break;
8005ff2: e024 b.n 800603e <UART_SetConfig+0x37a>
case UART_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
8005ff4: f7fe f896 bl 8004124 <HAL_RCC_GetSysClockFreq>
8005ff8: 0003 movs r3, r0
8005ffa: 637b str r3, [r7, #52] ; 0x34
break;
8005ffc: e01f b.n 800603e <UART_SetConfig+0x37a>
case UART_CLOCKSOURCE_LSE:
pclk = (uint32_t) LSE_VALUE;
8005ffe: 2380 movs r3, #128 ; 0x80
8006000: 021b lsls r3, r3, #8
8006002: 637b str r3, [r7, #52] ; 0x34
break;
8006004: e01b b.n 800603e <UART_SetConfig+0x37a>
8006006: 46c0 nop ; (mov r8, r8)
8006008: cfff69f3 .word 0xcfff69f3
800600c: ffffcfff .word 0xffffcfff
8006010: 40008000 .word 0x40008000
8006014: 11fff4ff .word 0x11fff4ff
8006018: 40013800 .word 0x40013800
800601c: 40021000 .word 0x40021000
8006020: 40004400 .word 0x40004400
8006024: 00f42400 .word 0x00f42400
8006028: 0800749c .word 0x0800749c
default:
pclk = 0U;
800602c: 2300 movs r3, #0
800602e: 637b str r3, [r7, #52] ; 0x34
ret = HAL_ERROR;
8006030: 231a movs r3, #26
8006032: 2220 movs r2, #32
8006034: 189b adds r3, r3, r2
8006036: 19db adds r3, r3, r7
8006038: 2201 movs r2, #1
800603a: 701a strb r2, [r3, #0]
break;
800603c: 46c0 nop ; (mov r8, r8)
}
/* USARTDIV must be greater than or equal to 0d16 */
if (pclk != 0U)
800603e: 6b7b ldr r3, [r7, #52] ; 0x34
8006040: 2b00 cmp r3, #0
8006042: d100 bne.n 8006046 <UART_SetConfig+0x382>
8006044: e09a b.n 800617c <UART_SetConfig+0x4b8>
{
usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
8006046: 6a7b ldr r3, [r7, #36] ; 0x24
8006048: 6a5a ldr r2, [r3, #36] ; 0x24
800604a: 4b58 ldr r3, [pc, #352] ; (80061ac <UART_SetConfig+0x4e8>)
800604c: 0052 lsls r2, r2, #1
800604e: 5ad3 ldrh r3, [r2, r3]
8006050: 0019 movs r1, r3
8006052: 6b78 ldr r0, [r7, #52] ; 0x34
8006054: f7fa f856 bl 8000104 <__udivsi3>
8006058: 0003 movs r3, r0
800605a: 005a lsls r2, r3, #1
800605c: 6a7b ldr r3, [r7, #36] ; 0x24
800605e: 685b ldr r3, [r3, #4]
8006060: 085b lsrs r3, r3, #1
8006062: 18d2 adds r2, r2, r3
8006064: 6a7b ldr r3, [r7, #36] ; 0x24
8006066: 685b ldr r3, [r3, #4]
8006068: 0019 movs r1, r3
800606a: 0010 movs r0, r2
800606c: f7fa f84a bl 8000104 <__udivsi3>
8006070: 0003 movs r3, r0
8006072: 633b str r3, [r7, #48] ; 0x30
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
8006074: 6b3b ldr r3, [r7, #48] ; 0x30
8006076: 2b0f cmp r3, #15
8006078: d921 bls.n 80060be <UART_SetConfig+0x3fa>
800607a: 6b3a ldr r2, [r7, #48] ; 0x30
800607c: 2380 movs r3, #128 ; 0x80
800607e: 025b lsls r3, r3, #9
8006080: 429a cmp r2, r3
8006082: d21c bcs.n 80060be <UART_SetConfig+0x3fa>
{
brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
8006084: 6b3b ldr r3, [r7, #48] ; 0x30
8006086: b29a uxth r2, r3
8006088: 200e movs r0, #14
800608a: 2420 movs r4, #32
800608c: 1903 adds r3, r0, r4
800608e: 19db adds r3, r3, r7
8006090: 210f movs r1, #15
8006092: 438a bics r2, r1
8006094: 801a strh r2, [r3, #0]
brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
8006096: 6b3b ldr r3, [r7, #48] ; 0x30
8006098: 085b lsrs r3, r3, #1
800609a: b29b uxth r3, r3
800609c: 2207 movs r2, #7
800609e: 4013 ands r3, r2
80060a0: b299 uxth r1, r3
80060a2: 1903 adds r3, r0, r4
80060a4: 19db adds r3, r3, r7
80060a6: 1902 adds r2, r0, r4
80060a8: 19d2 adds r2, r2, r7
80060aa: 8812 ldrh r2, [r2, #0]
80060ac: 430a orrs r2, r1
80060ae: 801a strh r2, [r3, #0]
huart->Instance->BRR = brrtemp;
80060b0: 6a7b ldr r3, [r7, #36] ; 0x24
80060b2: 681b ldr r3, [r3, #0]
80060b4: 1902 adds r2, r0, r4
80060b6: 19d2 adds r2, r2, r7
80060b8: 8812 ldrh r2, [r2, #0]
80060ba: 60da str r2, [r3, #12]
80060bc: e05e b.n 800617c <UART_SetConfig+0x4b8>
}
else
{
ret = HAL_ERROR;
80060be: 231a movs r3, #26
80060c0: 2220 movs r2, #32
80060c2: 189b adds r3, r3, r2
80060c4: 19db adds r3, r3, r7
80060c6: 2201 movs r2, #1
80060c8: 701a strb r2, [r3, #0]
80060ca: e057 b.n 800617c <UART_SetConfig+0x4b8>
}
}
}
else
{
switch (clocksource)
80060cc: 231b movs r3, #27
80060ce: 2220 movs r2, #32
80060d0: 189b adds r3, r3, r2
80060d2: 19db adds r3, r3, r7
80060d4: 781b ldrb r3, [r3, #0]
80060d6: 2b08 cmp r3, #8
80060d8: d015 beq.n 8006106 <UART_SetConfig+0x442>
80060da: dc18 bgt.n 800610e <UART_SetConfig+0x44a>
80060dc: 2b04 cmp r3, #4
80060de: d00d beq.n 80060fc <UART_SetConfig+0x438>
80060e0: dc15 bgt.n 800610e <UART_SetConfig+0x44a>
80060e2: 2b00 cmp r3, #0
80060e4: d002 beq.n 80060ec <UART_SetConfig+0x428>
80060e6: 2b02 cmp r3, #2
80060e8: d005 beq.n 80060f6 <UART_SetConfig+0x432>
80060ea: e010 b.n 800610e <UART_SetConfig+0x44a>
{
case UART_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
80060ec: f7fe f8a6 bl 800423c <HAL_RCC_GetPCLK1Freq>
80060f0: 0003 movs r3, r0
80060f2: 637b str r3, [r7, #52] ; 0x34
break;
80060f4: e014 b.n 8006120 <UART_SetConfig+0x45c>
case UART_CLOCKSOURCE_HSI:
pclk = (uint32_t) HSI_VALUE;
80060f6: 4b2e ldr r3, [pc, #184] ; (80061b0 <UART_SetConfig+0x4ec>)
80060f8: 637b str r3, [r7, #52] ; 0x34
break;
80060fa: e011 b.n 8006120 <UART_SetConfig+0x45c>
case UART_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
80060fc: f7fe f812 bl 8004124 <HAL_RCC_GetSysClockFreq>
8006100: 0003 movs r3, r0
8006102: 637b str r3, [r7, #52] ; 0x34
break;
8006104: e00c b.n 8006120 <UART_SetConfig+0x45c>
case UART_CLOCKSOURCE_LSE:
pclk = (uint32_t) LSE_VALUE;
8006106: 2380 movs r3, #128 ; 0x80
8006108: 021b lsls r3, r3, #8
800610a: 637b str r3, [r7, #52] ; 0x34
break;
800610c: e008 b.n 8006120 <UART_SetConfig+0x45c>
default:
pclk = 0U;
800610e: 2300 movs r3, #0
8006110: 637b str r3, [r7, #52] ; 0x34
ret = HAL_ERROR;
8006112: 231a movs r3, #26
8006114: 2220 movs r2, #32
8006116: 189b adds r3, r3, r2
8006118: 19db adds r3, r3, r7
800611a: 2201 movs r2, #1
800611c: 701a strb r2, [r3, #0]
break;
800611e: 46c0 nop ; (mov r8, r8)
}
if (pclk != 0U)
8006120: 6b7b ldr r3, [r7, #52] ; 0x34
8006122: 2b00 cmp r3, #0
8006124: d02a beq.n 800617c <UART_SetConfig+0x4b8>
{
/* USARTDIV must be greater than or equal to 0d16 */
usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
8006126: 6a7b ldr r3, [r7, #36] ; 0x24
8006128: 6a5a ldr r2, [r3, #36] ; 0x24
800612a: 4b20 ldr r3, [pc, #128] ; (80061ac <UART_SetConfig+0x4e8>)
800612c: 0052 lsls r2, r2, #1
800612e: 5ad3 ldrh r3, [r2, r3]
8006130: 0019 movs r1, r3
8006132: 6b78 ldr r0, [r7, #52] ; 0x34
8006134: f7f9 ffe6 bl 8000104 <__udivsi3>
8006138: 0003 movs r3, r0
800613a: 001a movs r2, r3
800613c: 6a7b ldr r3, [r7, #36] ; 0x24
800613e: 685b ldr r3, [r3, #4]
8006140: 085b lsrs r3, r3, #1
8006142: 18d2 adds r2, r2, r3
8006144: 6a7b ldr r3, [r7, #36] ; 0x24
8006146: 685b ldr r3, [r3, #4]
8006148: 0019 movs r1, r3
800614a: 0010 movs r0, r2
800614c: f7f9 ffda bl 8000104 <__udivsi3>
8006150: 0003 movs r3, r0
8006152: 633b str r3, [r7, #48] ; 0x30
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
8006154: 6b3b ldr r3, [r7, #48] ; 0x30
8006156: 2b0f cmp r3, #15
8006158: d90a bls.n 8006170 <UART_SetConfig+0x4ac>
800615a: 6b3a ldr r2, [r7, #48] ; 0x30
800615c: 2380 movs r3, #128 ; 0x80
800615e: 025b lsls r3, r3, #9
8006160: 429a cmp r2, r3
8006162: d205 bcs.n 8006170 <UART_SetConfig+0x4ac>
{
huart->Instance->BRR = (uint16_t)usartdiv;
8006164: 6b3b ldr r3, [r7, #48] ; 0x30
8006166: b29a uxth r2, r3
8006168: 6a7b ldr r3, [r7, #36] ; 0x24
800616a: 681b ldr r3, [r3, #0]
800616c: 60da str r2, [r3, #12]
800616e: e005 b.n 800617c <UART_SetConfig+0x4b8>
}
else
{
ret = HAL_ERROR;
8006170: 231a movs r3, #26
8006172: 2220 movs r2, #32
8006174: 189b adds r3, r3, r2
8006176: 19db adds r3, r3, r7
8006178: 2201 movs r2, #1
800617a: 701a strb r2, [r3, #0]
}
}
}
/* Initialize the number of data to process during RX/TX ISR execution */
huart->NbTxDataToProcess = 1;
800617c: 6a7b ldr r3, [r7, #36] ; 0x24
800617e: 226a movs r2, #106 ; 0x6a
8006180: 2101 movs r1, #1
8006182: 5299 strh r1, [r3, r2]
huart->NbRxDataToProcess = 1;
8006184: 6a7b ldr r3, [r7, #36] ; 0x24
8006186: 2268 movs r2, #104 ; 0x68
8006188: 2101 movs r1, #1
800618a: 5299 strh r1, [r3, r2]
/* Clear ISR function pointers */
huart->RxISR = NULL;
800618c: 6a7b ldr r3, [r7, #36] ; 0x24
800618e: 2200 movs r2, #0
8006190: 671a str r2, [r3, #112] ; 0x70
huart->TxISR = NULL;
8006192: 6a7b ldr r3, [r7, #36] ; 0x24
8006194: 2200 movs r2, #0
8006196: 675a str r2, [r3, #116] ; 0x74
return ret;
8006198: 231a movs r3, #26
800619a: 2220 movs r2, #32
800619c: 189b adds r3, r3, r2
800619e: 19db adds r3, r3, r7
80061a0: 781b ldrb r3, [r3, #0]
}
80061a2: 0018 movs r0, r3
80061a4: 46bd mov sp, r7
80061a6: b010 add sp, #64 ; 0x40
80061a8: bdb0 pop {r4, r5, r7, pc}
80061aa: 46c0 nop ; (mov r8, r8)
80061ac: 0800749c .word 0x0800749c
80061b0: 00f42400 .word 0x00f42400
080061b4 <UART_AdvFeatureConfig>:
* @brief Configure the UART peripheral advanced features.
* @param huart UART handle.
* @retval None
*/
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
{
80061b4: b580 push {r7, lr}
80061b6: b082 sub sp, #8
80061b8: af00 add r7, sp, #0
80061ba: 6078 str r0, [r7, #4]
/* Check whether the set of advanced features to configure is properly set */
assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
/* if required, configure TX pin active level inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
80061bc: 687b ldr r3, [r7, #4]
80061be: 6a9b ldr r3, [r3, #40] ; 0x28
80061c0: 2201 movs r2, #1
80061c2: 4013 ands r3, r2
80061c4: d00b beq.n 80061de <UART_AdvFeatureConfig+0x2a>
{
assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
80061c6: 687b ldr r3, [r7, #4]
80061c8: 681b ldr r3, [r3, #0]
80061ca: 685b ldr r3, [r3, #4]
80061cc: 4a4a ldr r2, [pc, #296] ; (80062f8 <UART_AdvFeatureConfig+0x144>)
80061ce: 4013 ands r3, r2
80061d0: 0019 movs r1, r3
80061d2: 687b ldr r3, [r7, #4]
80061d4: 6ada ldr r2, [r3, #44] ; 0x2c
80061d6: 687b ldr r3, [r7, #4]
80061d8: 681b ldr r3, [r3, #0]
80061da: 430a orrs r2, r1
80061dc: 605a str r2, [r3, #4]
}
/* if required, configure RX pin active level inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
80061de: 687b ldr r3, [r7, #4]
80061e0: 6a9b ldr r3, [r3, #40] ; 0x28
80061e2: 2202 movs r2, #2
80061e4: 4013 ands r3, r2
80061e6: d00b beq.n 8006200 <UART_AdvFeatureConfig+0x4c>
{
assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
80061e8: 687b ldr r3, [r7, #4]
80061ea: 681b ldr r3, [r3, #0]
80061ec: 685b ldr r3, [r3, #4]
80061ee: 4a43 ldr r2, [pc, #268] ; (80062fc <UART_AdvFeatureConfig+0x148>)
80061f0: 4013 ands r3, r2
80061f2: 0019 movs r1, r3
80061f4: 687b ldr r3, [r7, #4]
80061f6: 6b1a ldr r2, [r3, #48] ; 0x30
80061f8: 687b ldr r3, [r7, #4]
80061fa: 681b ldr r3, [r3, #0]
80061fc: 430a orrs r2, r1
80061fe: 605a str r2, [r3, #4]
}
/* if required, configure data inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
8006200: 687b ldr r3, [r7, #4]
8006202: 6a9b ldr r3, [r3, #40] ; 0x28
8006204: 2204 movs r2, #4
8006206: 4013 ands r3, r2
8006208: d00b beq.n 8006222 <UART_AdvFeatureConfig+0x6e>
{
assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
800620a: 687b ldr r3, [r7, #4]
800620c: 681b ldr r3, [r3, #0]
800620e: 685b ldr r3, [r3, #4]
8006210: 4a3b ldr r2, [pc, #236] ; (8006300 <UART_AdvFeatureConfig+0x14c>)
8006212: 4013 ands r3, r2
8006214: 0019 movs r1, r3
8006216: 687b ldr r3, [r7, #4]
8006218: 6b5a ldr r2, [r3, #52] ; 0x34
800621a: 687b ldr r3, [r7, #4]
800621c: 681b ldr r3, [r3, #0]
800621e: 430a orrs r2, r1
8006220: 605a str r2, [r3, #4]
}
/* if required, configure RX/TX pins swap */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
8006222: 687b ldr r3, [r7, #4]
8006224: 6a9b ldr r3, [r3, #40] ; 0x28
8006226: 2208 movs r2, #8
8006228: 4013 ands r3, r2
800622a: d00b beq.n 8006244 <UART_AdvFeatureConfig+0x90>
{
assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
800622c: 687b ldr r3, [r7, #4]
800622e: 681b ldr r3, [r3, #0]
8006230: 685b ldr r3, [r3, #4]
8006232: 4a34 ldr r2, [pc, #208] ; (8006304 <UART_AdvFeatureConfig+0x150>)
8006234: 4013 ands r3, r2
8006236: 0019 movs r1, r3
8006238: 687b ldr r3, [r7, #4]
800623a: 6b9a ldr r2, [r3, #56] ; 0x38
800623c: 687b ldr r3, [r7, #4]
800623e: 681b ldr r3, [r3, #0]
8006240: 430a orrs r2, r1
8006242: 605a str r2, [r3, #4]
}
/* if required, configure RX overrun detection disabling */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
8006244: 687b ldr r3, [r7, #4]
8006246: 6a9b ldr r3, [r3, #40] ; 0x28
8006248: 2210 movs r2, #16
800624a: 4013 ands r3, r2
800624c: d00b beq.n 8006266 <UART_AdvFeatureConfig+0xb2>
{
assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
800624e: 687b ldr r3, [r7, #4]
8006250: 681b ldr r3, [r3, #0]
8006252: 689b ldr r3, [r3, #8]
8006254: 4a2c ldr r2, [pc, #176] ; (8006308 <UART_AdvFeatureConfig+0x154>)
8006256: 4013 ands r3, r2
8006258: 0019 movs r1, r3
800625a: 687b ldr r3, [r7, #4]
800625c: 6bda ldr r2, [r3, #60] ; 0x3c
800625e: 687b ldr r3, [r7, #4]
8006260: 681b ldr r3, [r3, #0]
8006262: 430a orrs r2, r1
8006264: 609a str r2, [r3, #8]
}
/* if required, configure DMA disabling on reception error */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
8006266: 687b ldr r3, [r7, #4]
8006268: 6a9b ldr r3, [r3, #40] ; 0x28
800626a: 2220 movs r2, #32
800626c: 4013 ands r3, r2
800626e: d00b beq.n 8006288 <UART_AdvFeatureConfig+0xd4>
{
assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
8006270: 687b ldr r3, [r7, #4]
8006272: 681b ldr r3, [r3, #0]
8006274: 689b ldr r3, [r3, #8]
8006276: 4a25 ldr r2, [pc, #148] ; (800630c <UART_AdvFeatureConfig+0x158>)
8006278: 4013 ands r3, r2
800627a: 0019 movs r1, r3
800627c: 687b ldr r3, [r7, #4]
800627e: 6c1a ldr r2, [r3, #64] ; 0x40
8006280: 687b ldr r3, [r7, #4]
8006282: 681b ldr r3, [r3, #0]
8006284: 430a orrs r2, r1
8006286: 609a str r2, [r3, #8]
}
/* if required, configure auto Baud rate detection scheme */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
8006288: 687b ldr r3, [r7, #4]
800628a: 6a9b ldr r3, [r3, #40] ; 0x28
800628c: 2240 movs r2, #64 ; 0x40
800628e: 4013 ands r3, r2
8006290: d01d beq.n 80062ce <UART_AdvFeatureConfig+0x11a>
{
assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
8006292: 687b ldr r3, [r7, #4]
8006294: 681b ldr r3, [r3, #0]
8006296: 685b ldr r3, [r3, #4]
8006298: 4a1d ldr r2, [pc, #116] ; (8006310 <UART_AdvFeatureConfig+0x15c>)
800629a: 4013 ands r3, r2
800629c: 0019 movs r1, r3
800629e: 687b ldr r3, [r7, #4]
80062a0: 6c5a ldr r2, [r3, #68] ; 0x44
80062a2: 687b ldr r3, [r7, #4]
80062a4: 681b ldr r3, [r3, #0]
80062a6: 430a orrs r2, r1
80062a8: 605a str r2, [r3, #4]
/* set auto Baudrate detection parameters if detection is enabled */
if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
80062aa: 687b ldr r3, [r7, #4]
80062ac: 6c5a ldr r2, [r3, #68] ; 0x44
80062ae: 2380 movs r3, #128 ; 0x80
80062b0: 035b lsls r3, r3, #13
80062b2: 429a cmp r2, r3
80062b4: d10b bne.n 80062ce <UART_AdvFeatureConfig+0x11a>
{
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
80062b6: 687b ldr r3, [r7, #4]
80062b8: 681b ldr r3, [r3, #0]
80062ba: 685b ldr r3, [r3, #4]
80062bc: 4a15 ldr r2, [pc, #84] ; (8006314 <UART_AdvFeatureConfig+0x160>)
80062be: 4013 ands r3, r2
80062c0: 0019 movs r1, r3
80062c2: 687b ldr r3, [r7, #4]
80062c4: 6c9a ldr r2, [r3, #72] ; 0x48
80062c6: 687b ldr r3, [r7, #4]
80062c8: 681b ldr r3, [r3, #0]
80062ca: 430a orrs r2, r1
80062cc: 605a str r2, [r3, #4]
}
}
/* if required, configure MSB first on communication line */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
80062ce: 687b ldr r3, [r7, #4]
80062d0: 6a9b ldr r3, [r3, #40] ; 0x28
80062d2: 2280 movs r2, #128 ; 0x80
80062d4: 4013 ands r3, r2
80062d6: d00b beq.n 80062f0 <UART_AdvFeatureConfig+0x13c>
{
assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
80062d8: 687b ldr r3, [r7, #4]
80062da: 681b ldr r3, [r3, #0]
80062dc: 685b ldr r3, [r3, #4]
80062de: 4a0e ldr r2, [pc, #56] ; (8006318 <UART_AdvFeatureConfig+0x164>)
80062e0: 4013 ands r3, r2
80062e2: 0019 movs r1, r3
80062e4: 687b ldr r3, [r7, #4]
80062e6: 6cda ldr r2, [r3, #76] ; 0x4c
80062e8: 687b ldr r3, [r7, #4]
80062ea: 681b ldr r3, [r3, #0]
80062ec: 430a orrs r2, r1
80062ee: 605a str r2, [r3, #4]
}
}
80062f0: 46c0 nop ; (mov r8, r8)
80062f2: 46bd mov sp, r7
80062f4: b002 add sp, #8
80062f6: bd80 pop {r7, pc}
80062f8: fffdffff .word 0xfffdffff
80062fc: fffeffff .word 0xfffeffff
8006300: fffbffff .word 0xfffbffff
8006304: ffff7fff .word 0xffff7fff
8006308: ffffefff .word 0xffffefff
800630c: ffffdfff .word 0xffffdfff
8006310: ffefffff .word 0xffefffff
8006314: ff9fffff .word 0xff9fffff
8006318: fff7ffff .word 0xfff7ffff
0800631c <UART_CheckIdleState>:
* @brief Check the UART Idle State.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
{
800631c: b580 push {r7, lr}
800631e: b086 sub sp, #24
8006320: af02 add r7, sp, #8
8006322: 6078 str r0, [r7, #4]
uint32_t tickstart;
/* Initialize the UART ErrorCode */
huart->ErrorCode = HAL_UART_ERROR_NONE;
8006324: 687b ldr r3, [r7, #4]
8006326: 228c movs r2, #140 ; 0x8c
8006328: 2100 movs r1, #0
800632a: 5099 str r1, [r3, r2]
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
800632c: f7fb fc1a bl 8001b64 <HAL_GetTick>
8006330: 0003 movs r3, r0
8006332: 60fb str r3, [r7, #12]
/* Check if the Transmitter is enabled */
if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
8006334: 687b ldr r3, [r7, #4]
8006336: 681b ldr r3, [r3, #0]
8006338: 681b ldr r3, [r3, #0]
800633a: 2208 movs r2, #8
800633c: 4013 ands r3, r2
800633e: 2b08 cmp r3, #8
8006340: d10c bne.n 800635c <UART_CheckIdleState+0x40>
{
/* Wait until TEACK flag is set */
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
8006342: 68fb ldr r3, [r7, #12]
8006344: 2280 movs r2, #128 ; 0x80
8006346: 0391 lsls r1, r2, #14
8006348: 6878 ldr r0, [r7, #4]
800634a: 4a18 ldr r2, [pc, #96] ; (80063ac <UART_CheckIdleState+0x90>)
800634c: 9200 str r2, [sp, #0]
800634e: 2200 movs r2, #0
8006350: f000 f82e bl 80063b0 <UART_WaitOnFlagUntilTimeout>
8006354: 1e03 subs r3, r0, #0
8006356: d001 beq.n 800635c <UART_CheckIdleState+0x40>
{
/* Timeout occurred */
return HAL_TIMEOUT;
8006358: 2303 movs r3, #3
800635a: e023 b.n 80063a4 <UART_CheckIdleState+0x88>
}
}
/* Check if the Receiver is enabled */
if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
800635c: 687b ldr r3, [r7, #4]
800635e: 681b ldr r3, [r3, #0]
8006360: 681b ldr r3, [r3, #0]
8006362: 2204 movs r2, #4
8006364: 4013 ands r3, r2
8006366: 2b04 cmp r3, #4
8006368: d10c bne.n 8006384 <UART_CheckIdleState+0x68>
{
/* Wait until REACK flag is set */
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
800636a: 68fb ldr r3, [r7, #12]
800636c: 2280 movs r2, #128 ; 0x80
800636e: 03d1 lsls r1, r2, #15
8006370: 6878 ldr r0, [r7, #4]
8006372: 4a0e ldr r2, [pc, #56] ; (80063ac <UART_CheckIdleState+0x90>)
8006374: 9200 str r2, [sp, #0]
8006376: 2200 movs r2, #0
8006378: f000 f81a bl 80063b0 <UART_WaitOnFlagUntilTimeout>
800637c: 1e03 subs r3, r0, #0
800637e: d001 beq.n 8006384 <UART_CheckIdleState+0x68>
{
/* Timeout occurred */
return HAL_TIMEOUT;
8006380: 2303 movs r3, #3
8006382: e00f b.n 80063a4 <UART_CheckIdleState+0x88>
}
}
/* Initialize the UART State */
huart->gState = HAL_UART_STATE_READY;
8006384: 687b ldr r3, [r7, #4]
8006386: 2284 movs r2, #132 ; 0x84
8006388: 2120 movs r1, #32
800638a: 5099 str r1, [r3, r2]
huart->RxState = HAL_UART_STATE_READY;
800638c: 687b ldr r3, [r7, #4]
800638e: 2288 movs r2, #136 ; 0x88
8006390: 2120 movs r1, #32
8006392: 5099 str r1, [r3, r2]
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8006394: 687b ldr r3, [r7, #4]
8006396: 2200 movs r2, #0
8006398: 66da str r2, [r3, #108] ; 0x6c
__HAL_UNLOCK(huart);
800639a: 687b ldr r3, [r7, #4]
800639c: 2280 movs r2, #128 ; 0x80
800639e: 2100 movs r1, #0
80063a0: 5499 strb r1, [r3, r2]
return HAL_OK;
80063a2: 2300 movs r3, #0
}
80063a4: 0018 movs r0, r3
80063a6: 46bd mov sp, r7
80063a8: b004 add sp, #16
80063aa: bd80 pop {r7, pc}
80063ac: 01ffffff .word 0x01ffffff
080063b0 <UART_WaitOnFlagUntilTimeout>:
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
uint32_t Tickstart, uint32_t Timeout)
{
80063b0: b580 push {r7, lr}
80063b2: b094 sub sp, #80 ; 0x50
80063b4: af00 add r7, sp, #0
80063b6: 60f8 str r0, [r7, #12]
80063b8: 60b9 str r1, [r7, #8]
80063ba: 603b str r3, [r7, #0]
80063bc: 1dfb adds r3, r7, #7
80063be: 701a strb r2, [r3, #0]
/* Wait until flag is set */
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
80063c0: e0a7 b.n 8006512 <UART_WaitOnFlagUntilTimeout+0x162>
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
80063c2: 6dbb ldr r3, [r7, #88] ; 0x58
80063c4: 3301 adds r3, #1
80063c6: d100 bne.n 80063ca <UART_WaitOnFlagUntilTimeout+0x1a>
80063c8: e0a3 b.n 8006512 <UART_WaitOnFlagUntilTimeout+0x162>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
80063ca: f7fb fbcb bl 8001b64 <HAL_GetTick>
80063ce: 0002 movs r2, r0
80063d0: 683b ldr r3, [r7, #0]
80063d2: 1ad3 subs r3, r2, r3
80063d4: 6dba ldr r2, [r7, #88] ; 0x58
80063d6: 429a cmp r2, r3
80063d8: d302 bcc.n 80063e0 <UART_WaitOnFlagUntilTimeout+0x30>
80063da: 6dbb ldr r3, [r7, #88] ; 0x58
80063dc: 2b00 cmp r3, #0
80063de: d13f bne.n 8006460 <UART_WaitOnFlagUntilTimeout+0xb0>
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
80063e0: f3ef 8310 mrs r3, PRIMASK
80063e4: 62bb str r3, [r7, #40] ; 0x28
return(result);
80063e6: 6abb ldr r3, [r7, #40] ; 0x28
{
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
interrupts for the interrupt process */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE |
80063e8: 647b str r3, [r7, #68] ; 0x44
80063ea: 2301 movs r3, #1
80063ec: 62fb str r3, [r7, #44] ; 0x2c
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80063ee: 6afb ldr r3, [r7, #44] ; 0x2c
80063f0: f383 8810 msr PRIMASK, r3
}
80063f4: 46c0 nop ; (mov r8, r8)
80063f6: 68fb ldr r3, [r7, #12]
80063f8: 681b ldr r3, [r3, #0]
80063fa: 681a ldr r2, [r3, #0]
80063fc: 68fb ldr r3, [r7, #12]
80063fe: 681b ldr r3, [r3, #0]
8006400: 494e ldr r1, [pc, #312] ; (800653c <UART_WaitOnFlagUntilTimeout+0x18c>)
8006402: 400a ands r2, r1
8006404: 601a str r2, [r3, #0]
8006406: 6c7b ldr r3, [r7, #68] ; 0x44
8006408: 633b str r3, [r7, #48] ; 0x30
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
800640a: 6b3b ldr r3, [r7, #48] ; 0x30
800640c: f383 8810 msr PRIMASK, r3
}
8006410: 46c0 nop ; (mov r8, r8)
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8006412: f3ef 8310 mrs r3, PRIMASK
8006416: 637b str r3, [r7, #52] ; 0x34
return(result);
8006418: 6b7b ldr r3, [r7, #52] ; 0x34
USART_CR1_TXEIE_TXFNFIE));
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
800641a: 643b str r3, [r7, #64] ; 0x40
800641c: 2301 movs r3, #1
800641e: 63bb str r3, [r7, #56] ; 0x38
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006420: 6bbb ldr r3, [r7, #56] ; 0x38
8006422: f383 8810 msr PRIMASK, r3
}
8006426: 46c0 nop ; (mov r8, r8)
8006428: 68fb ldr r3, [r7, #12]
800642a: 681b ldr r3, [r3, #0]
800642c: 689a ldr r2, [r3, #8]
800642e: 68fb ldr r3, [r7, #12]
8006430: 681b ldr r3, [r3, #0]
8006432: 2101 movs r1, #1
8006434: 438a bics r2, r1
8006436: 609a str r2, [r3, #8]
8006438: 6c3b ldr r3, [r7, #64] ; 0x40
800643a: 63fb str r3, [r7, #60] ; 0x3c
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
800643c: 6bfb ldr r3, [r7, #60] ; 0x3c
800643e: f383 8810 msr PRIMASK, r3
}
8006442: 46c0 nop ; (mov r8, r8)
huart->gState = HAL_UART_STATE_READY;
8006444: 68fb ldr r3, [r7, #12]
8006446: 2284 movs r2, #132 ; 0x84
8006448: 2120 movs r1, #32
800644a: 5099 str r1, [r3, r2]
huart->RxState = HAL_UART_STATE_READY;
800644c: 68fb ldr r3, [r7, #12]
800644e: 2288 movs r2, #136 ; 0x88
8006450: 2120 movs r1, #32
8006452: 5099 str r1, [r3, r2]
__HAL_UNLOCK(huart);
8006454: 68fb ldr r3, [r7, #12]
8006456: 2280 movs r2, #128 ; 0x80
8006458: 2100 movs r1, #0
800645a: 5499 strb r1, [r3, r2]
return HAL_TIMEOUT;
800645c: 2303 movs r3, #3
800645e: e069 b.n 8006534 <UART_WaitOnFlagUntilTimeout+0x184>
}
if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U)
8006460: 68fb ldr r3, [r7, #12]
8006462: 681b ldr r3, [r3, #0]
8006464: 681b ldr r3, [r3, #0]
8006466: 2204 movs r2, #4
8006468: 4013 ands r3, r2
800646a: d052 beq.n 8006512 <UART_WaitOnFlagUntilTimeout+0x162>
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
800646c: 68fb ldr r3, [r7, #12]
800646e: 681b ldr r3, [r3, #0]
8006470: 69da ldr r2, [r3, #28]
8006472: 2380 movs r3, #128 ; 0x80
8006474: 011b lsls r3, r3, #4
8006476: 401a ands r2, r3
8006478: 2380 movs r3, #128 ; 0x80
800647a: 011b lsls r3, r3, #4
800647c: 429a cmp r2, r3
800647e: d148 bne.n 8006512 <UART_WaitOnFlagUntilTimeout+0x162>
{
/* Clear Receiver Timeout flag*/
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
8006480: 68fb ldr r3, [r7, #12]
8006482: 681b ldr r3, [r3, #0]
8006484: 2280 movs r2, #128 ; 0x80
8006486: 0112 lsls r2, r2, #4
8006488: 621a str r2, [r3, #32]
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
800648a: f3ef 8310 mrs r3, PRIMASK
800648e: 613b str r3, [r7, #16]
return(result);
8006490: 693b ldr r3, [r7, #16]
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
interrupts for the interrupt process */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE |
8006492: 64fb str r3, [r7, #76] ; 0x4c
8006494: 2301 movs r3, #1
8006496: 617b str r3, [r7, #20]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006498: 697b ldr r3, [r7, #20]
800649a: f383 8810 msr PRIMASK, r3
}
800649e: 46c0 nop ; (mov r8, r8)
80064a0: 68fb ldr r3, [r7, #12]
80064a2: 681b ldr r3, [r3, #0]
80064a4: 681a ldr r2, [r3, #0]
80064a6: 68fb ldr r3, [r7, #12]
80064a8: 681b ldr r3, [r3, #0]
80064aa: 4924 ldr r1, [pc, #144] ; (800653c <UART_WaitOnFlagUntilTimeout+0x18c>)
80064ac: 400a ands r2, r1
80064ae: 601a str r2, [r3, #0]
80064b0: 6cfb ldr r3, [r7, #76] ; 0x4c
80064b2: 61bb str r3, [r7, #24]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80064b4: 69bb ldr r3, [r7, #24]
80064b6: f383 8810 msr PRIMASK, r3
}
80064ba: 46c0 nop ; (mov r8, r8)
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
80064bc: f3ef 8310 mrs r3, PRIMASK
80064c0: 61fb str r3, [r7, #28]
return(result);
80064c2: 69fb ldr r3, [r7, #28]
USART_CR1_TXEIE_TXFNFIE));
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
80064c4: 64bb str r3, [r7, #72] ; 0x48
80064c6: 2301 movs r3, #1
80064c8: 623b str r3, [r7, #32]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80064ca: 6a3b ldr r3, [r7, #32]
80064cc: f383 8810 msr PRIMASK, r3
}
80064d0: 46c0 nop ; (mov r8, r8)
80064d2: 68fb ldr r3, [r7, #12]
80064d4: 681b ldr r3, [r3, #0]
80064d6: 689a ldr r2, [r3, #8]
80064d8: 68fb ldr r3, [r7, #12]
80064da: 681b ldr r3, [r3, #0]
80064dc: 2101 movs r1, #1
80064de: 438a bics r2, r1
80064e0: 609a str r2, [r3, #8]
80064e2: 6cbb ldr r3, [r7, #72] ; 0x48
80064e4: 627b str r3, [r7, #36] ; 0x24
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80064e6: 6a7b ldr r3, [r7, #36] ; 0x24
80064e8: f383 8810 msr PRIMASK, r3
}
80064ec: 46c0 nop ; (mov r8, r8)
huart->gState = HAL_UART_STATE_READY;
80064ee: 68fb ldr r3, [r7, #12]
80064f0: 2284 movs r2, #132 ; 0x84
80064f2: 2120 movs r1, #32
80064f4: 5099 str r1, [r3, r2]
huart->RxState = HAL_UART_STATE_READY;
80064f6: 68fb ldr r3, [r7, #12]
80064f8: 2288 movs r2, #136 ; 0x88
80064fa: 2120 movs r1, #32
80064fc: 5099 str r1, [r3, r2]
huart->ErrorCode = HAL_UART_ERROR_RTO;
80064fe: 68fb ldr r3, [r7, #12]
8006500: 228c movs r2, #140 ; 0x8c
8006502: 2120 movs r1, #32
8006504: 5099 str r1, [r3, r2]
/* Process Unlocked */
__HAL_UNLOCK(huart);
8006506: 68fb ldr r3, [r7, #12]
8006508: 2280 movs r2, #128 ; 0x80
800650a: 2100 movs r1, #0
800650c: 5499 strb r1, [r3, r2]
return HAL_TIMEOUT;
800650e: 2303 movs r3, #3
8006510: e010 b.n 8006534 <UART_WaitOnFlagUntilTimeout+0x184>
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
8006512: 68fb ldr r3, [r7, #12]
8006514: 681b ldr r3, [r3, #0]
8006516: 69db ldr r3, [r3, #28]
8006518: 68ba ldr r2, [r7, #8]
800651a: 4013 ands r3, r2
800651c: 68ba ldr r2, [r7, #8]
800651e: 1ad3 subs r3, r2, r3
8006520: 425a negs r2, r3
8006522: 4153 adcs r3, r2
8006524: b2db uxtb r3, r3
8006526: 001a movs r2, r3
8006528: 1dfb adds r3, r7, #7
800652a: 781b ldrb r3, [r3, #0]
800652c: 429a cmp r2, r3
800652e: d100 bne.n 8006532 <UART_WaitOnFlagUntilTimeout+0x182>
8006530: e747 b.n 80063c2 <UART_WaitOnFlagUntilTimeout+0x12>
}
}
}
}
return HAL_OK;
8006532: 2300 movs r3, #0
}
8006534: 0018 movs r0, r3
8006536: 46bd mov sp, r7
8006538: b014 add sp, #80 ; 0x50
800653a: bd80 pop {r7, pc}
800653c: fffffe5f .word 0xfffffe5f
08006540 <UART_Start_Receive_IT>:
* @param pData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{
8006540: b580 push {r7, lr}
8006542: b098 sub sp, #96 ; 0x60
8006544: af00 add r7, sp, #0
8006546: 60f8 str r0, [r7, #12]
8006548: 60b9 str r1, [r7, #8]
800654a: 1dbb adds r3, r7, #6
800654c: 801a strh r2, [r3, #0]
huart->pRxBuffPtr = pData;
800654e: 68fb ldr r3, [r7, #12]
8006550: 68ba ldr r2, [r7, #8]
8006552: 659a str r2, [r3, #88] ; 0x58
huart->RxXferSize = Size;
8006554: 68fb ldr r3, [r7, #12]
8006556: 1dba adds r2, r7, #6
8006558: 215c movs r1, #92 ; 0x5c
800655a: 8812 ldrh r2, [r2, #0]
800655c: 525a strh r2, [r3, r1]
huart->RxXferCount = Size;
800655e: 68fb ldr r3, [r7, #12]
8006560: 1dba adds r2, r7, #6
8006562: 215e movs r1, #94 ; 0x5e
8006564: 8812 ldrh r2, [r2, #0]
8006566: 525a strh r2, [r3, r1]
huart->RxISR = NULL;
8006568: 68fb ldr r3, [r7, #12]
800656a: 2200 movs r2, #0
800656c: 671a str r2, [r3, #112] ; 0x70
/* Computation of UART mask to apply to RDR register */
UART_MASK_COMPUTATION(huart);
800656e: 68fb ldr r3, [r7, #12]
8006570: 689a ldr r2, [r3, #8]
8006572: 2380 movs r3, #128 ; 0x80
8006574: 015b lsls r3, r3, #5
8006576: 429a cmp r2, r3
8006578: d10d bne.n 8006596 <UART_Start_Receive_IT+0x56>
800657a: 68fb ldr r3, [r7, #12]
800657c: 691b ldr r3, [r3, #16]
800657e: 2b00 cmp r3, #0
8006580: d104 bne.n 800658c <UART_Start_Receive_IT+0x4c>
8006582: 68fb ldr r3, [r7, #12]
8006584: 2260 movs r2, #96 ; 0x60
8006586: 497f ldr r1, [pc, #508] ; (8006784 <UART_Start_Receive_IT+0x244>)
8006588: 5299 strh r1, [r3, r2]
800658a: e02e b.n 80065ea <UART_Start_Receive_IT+0xaa>
800658c: 68fb ldr r3, [r7, #12]
800658e: 2260 movs r2, #96 ; 0x60
8006590: 21ff movs r1, #255 ; 0xff
8006592: 5299 strh r1, [r3, r2]
8006594: e029 b.n 80065ea <UART_Start_Receive_IT+0xaa>
8006596: 68fb ldr r3, [r7, #12]
8006598: 689b ldr r3, [r3, #8]
800659a: 2b00 cmp r3, #0
800659c: d10d bne.n 80065ba <UART_Start_Receive_IT+0x7a>
800659e: 68fb ldr r3, [r7, #12]
80065a0: 691b ldr r3, [r3, #16]
80065a2: 2b00 cmp r3, #0
80065a4: d104 bne.n 80065b0 <UART_Start_Receive_IT+0x70>
80065a6: 68fb ldr r3, [r7, #12]
80065a8: 2260 movs r2, #96 ; 0x60
80065aa: 21ff movs r1, #255 ; 0xff
80065ac: 5299 strh r1, [r3, r2]
80065ae: e01c b.n 80065ea <UART_Start_Receive_IT+0xaa>
80065b0: 68fb ldr r3, [r7, #12]
80065b2: 2260 movs r2, #96 ; 0x60
80065b4: 217f movs r1, #127 ; 0x7f
80065b6: 5299 strh r1, [r3, r2]
80065b8: e017 b.n 80065ea <UART_Start_Receive_IT+0xaa>
80065ba: 68fb ldr r3, [r7, #12]
80065bc: 689a ldr r2, [r3, #8]
80065be: 2380 movs r3, #128 ; 0x80
80065c0: 055b lsls r3, r3, #21
80065c2: 429a cmp r2, r3
80065c4: d10d bne.n 80065e2 <UART_Start_Receive_IT+0xa2>
80065c6: 68fb ldr r3, [r7, #12]
80065c8: 691b ldr r3, [r3, #16]
80065ca: 2b00 cmp r3, #0
80065cc: d104 bne.n 80065d8 <UART_Start_Receive_IT+0x98>
80065ce: 68fb ldr r3, [r7, #12]
80065d0: 2260 movs r2, #96 ; 0x60
80065d2: 217f movs r1, #127 ; 0x7f
80065d4: 5299 strh r1, [r3, r2]
80065d6: e008 b.n 80065ea <UART_Start_Receive_IT+0xaa>
80065d8: 68fb ldr r3, [r7, #12]
80065da: 2260 movs r2, #96 ; 0x60
80065dc: 213f movs r1, #63 ; 0x3f
80065de: 5299 strh r1, [r3, r2]
80065e0: e003 b.n 80065ea <UART_Start_Receive_IT+0xaa>
80065e2: 68fb ldr r3, [r7, #12]
80065e4: 2260 movs r2, #96 ; 0x60
80065e6: 2100 movs r1, #0
80065e8: 5299 strh r1, [r3, r2]
huart->ErrorCode = HAL_UART_ERROR_NONE;
80065ea: 68fb ldr r3, [r7, #12]
80065ec: 228c movs r2, #140 ; 0x8c
80065ee: 2100 movs r1, #0
80065f0: 5099 str r1, [r3, r2]
huart->RxState = HAL_UART_STATE_BUSY_RX;
80065f2: 68fb ldr r3, [r7, #12]
80065f4: 2288 movs r2, #136 ; 0x88
80065f6: 2122 movs r1, #34 ; 0x22
80065f8: 5099 str r1, [r3, r2]
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
80065fa: f3ef 8310 mrs r3, PRIMASK
80065fe: 643b str r3, [r7, #64] ; 0x40
return(result);
8006600: 6c3b ldr r3, [r7, #64] ; 0x40
/* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
8006602: 65fb str r3, [r7, #92] ; 0x5c
8006604: 2301 movs r3, #1
8006606: 647b str r3, [r7, #68] ; 0x44
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006608: 6c7b ldr r3, [r7, #68] ; 0x44
800660a: f383 8810 msr PRIMASK, r3
}
800660e: 46c0 nop ; (mov r8, r8)
8006610: 68fb ldr r3, [r7, #12]
8006612: 681b ldr r3, [r3, #0]
8006614: 689a ldr r2, [r3, #8]
8006616: 68fb ldr r3, [r7, #12]
8006618: 681b ldr r3, [r3, #0]
800661a: 2101 movs r1, #1
800661c: 430a orrs r2, r1
800661e: 609a str r2, [r3, #8]
8006620: 6dfb ldr r3, [r7, #92] ; 0x5c
8006622: 64bb str r3, [r7, #72] ; 0x48
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006624: 6cbb ldr r3, [r7, #72] ; 0x48
8006626: f383 8810 msr PRIMASK, r3
}
800662a: 46c0 nop ; (mov r8, r8)
/* Configure Rx interrupt processing */
if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess))
800662c: 68fb ldr r3, [r7, #12]
800662e: 6e5a ldr r2, [r3, #100] ; 0x64
8006630: 2380 movs r3, #128 ; 0x80
8006632: 059b lsls r3, r3, #22
8006634: 429a cmp r2, r3
8006636: d154 bne.n 80066e2 <UART_Start_Receive_IT+0x1a2>
8006638: 68fb ldr r3, [r7, #12]
800663a: 2268 movs r2, #104 ; 0x68
800663c: 5a9b ldrh r3, [r3, r2]
800663e: 1dba adds r2, r7, #6
8006640: 8812 ldrh r2, [r2, #0]
8006642: 429a cmp r2, r3
8006644: d34d bcc.n 80066e2 <UART_Start_Receive_IT+0x1a2>
{
/* Set the Rx ISR function pointer according to the data word length */
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
8006646: 68fb ldr r3, [r7, #12]
8006648: 689a ldr r2, [r3, #8]
800664a: 2380 movs r3, #128 ; 0x80
800664c: 015b lsls r3, r3, #5
800664e: 429a cmp r2, r3
8006650: d107 bne.n 8006662 <UART_Start_Receive_IT+0x122>
8006652: 68fb ldr r3, [r7, #12]
8006654: 691b ldr r3, [r3, #16]
8006656: 2b00 cmp r3, #0
8006658: d103 bne.n 8006662 <UART_Start_Receive_IT+0x122>
{
huart->RxISR = UART_RxISR_16BIT_FIFOEN;
800665a: 68fb ldr r3, [r7, #12]
800665c: 4a4a ldr r2, [pc, #296] ; (8006788 <UART_Start_Receive_IT+0x248>)
800665e: 671a str r2, [r3, #112] ; 0x70
8006660: e002 b.n 8006668 <UART_Start_Receive_IT+0x128>
}
else
{
huart->RxISR = UART_RxISR_8BIT_FIFOEN;
8006662: 68fb ldr r3, [r7, #12]
8006664: 4a49 ldr r2, [pc, #292] ; (800678c <UART_Start_Receive_IT+0x24c>)
8006666: 671a str r2, [r3, #112] ; 0x70
}
__HAL_UNLOCK(huart);
8006668: 68fb ldr r3, [r7, #12]
800666a: 2280 movs r2, #128 ; 0x80
800666c: 2100 movs r1, #0
800666e: 5499 strb r1, [r3, r2]
/* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */
if (huart->Init.Parity != UART_PARITY_NONE)
8006670: 68fb ldr r3, [r7, #12]
8006672: 691b ldr r3, [r3, #16]
8006674: 2b00 cmp r3, #0
8006676: d019 beq.n 80066ac <UART_Start_Receive_IT+0x16c>
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8006678: f3ef 8310 mrs r3, PRIMASK
800667c: 637b str r3, [r7, #52] ; 0x34
return(result);
800667e: 6b7b ldr r3, [r7, #52] ; 0x34
{
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
8006680: 65bb str r3, [r7, #88] ; 0x58
8006682: 2301 movs r3, #1
8006684: 63bb str r3, [r7, #56] ; 0x38
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006686: 6bbb ldr r3, [r7, #56] ; 0x38
8006688: f383 8810 msr PRIMASK, r3
}
800668c: 46c0 nop ; (mov r8, r8)
800668e: 68fb ldr r3, [r7, #12]
8006690: 681b ldr r3, [r3, #0]
8006692: 681a ldr r2, [r3, #0]
8006694: 68fb ldr r3, [r7, #12]
8006696: 681b ldr r3, [r3, #0]
8006698: 2180 movs r1, #128 ; 0x80
800669a: 0049 lsls r1, r1, #1
800669c: 430a orrs r2, r1
800669e: 601a str r2, [r3, #0]
80066a0: 6dbb ldr r3, [r7, #88] ; 0x58
80066a2: 63fb str r3, [r7, #60] ; 0x3c
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80066a4: 6bfb ldr r3, [r7, #60] ; 0x3c
80066a6: f383 8810 msr PRIMASK, r3
}
80066aa: 46c0 nop ; (mov r8, r8)
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
80066ac: f3ef 8310 mrs r3, PRIMASK
80066b0: 62bb str r3, [r7, #40] ; 0x28
return(result);
80066b2: 6abb ldr r3, [r7, #40] ; 0x28
}
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
80066b4: 657b str r3, [r7, #84] ; 0x54
80066b6: 2301 movs r3, #1
80066b8: 62fb str r3, [r7, #44] ; 0x2c
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80066ba: 6afb ldr r3, [r7, #44] ; 0x2c
80066bc: f383 8810 msr PRIMASK, r3
}
80066c0: 46c0 nop ; (mov r8, r8)
80066c2: 68fb ldr r3, [r7, #12]
80066c4: 681b ldr r3, [r3, #0]
80066c6: 689a ldr r2, [r3, #8]
80066c8: 68fb ldr r3, [r7, #12]
80066ca: 681b ldr r3, [r3, #0]
80066cc: 2180 movs r1, #128 ; 0x80
80066ce: 0549 lsls r1, r1, #21
80066d0: 430a orrs r2, r1
80066d2: 609a str r2, [r3, #8]
80066d4: 6d7b ldr r3, [r7, #84] ; 0x54
80066d6: 633b str r3, [r7, #48] ; 0x30
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80066d8: 6b3b ldr r3, [r7, #48] ; 0x30
80066da: f383 8810 msr PRIMASK, r3
}
80066de: 46c0 nop ; (mov r8, r8)
80066e0: e04b b.n 800677a <UART_Start_Receive_IT+0x23a>
}
else
{
/* Set the Rx ISR function pointer according to the data word length */
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
80066e2: 68fb ldr r3, [r7, #12]
80066e4: 689a ldr r2, [r3, #8]
80066e6: 2380 movs r3, #128 ; 0x80
80066e8: 015b lsls r3, r3, #5
80066ea: 429a cmp r2, r3
80066ec: d107 bne.n 80066fe <UART_Start_Receive_IT+0x1be>
80066ee: 68fb ldr r3, [r7, #12]
80066f0: 691b ldr r3, [r3, #16]
80066f2: 2b00 cmp r3, #0
80066f4: d103 bne.n 80066fe <UART_Start_Receive_IT+0x1be>
{
huart->RxISR = UART_RxISR_16BIT;
80066f6: 68fb ldr r3, [r7, #12]
80066f8: 4a25 ldr r2, [pc, #148] ; (8006790 <UART_Start_Receive_IT+0x250>)
80066fa: 671a str r2, [r3, #112] ; 0x70
80066fc: e002 b.n 8006704 <UART_Start_Receive_IT+0x1c4>
}
else
{
huart->RxISR = UART_RxISR_8BIT;
80066fe: 68fb ldr r3, [r7, #12]
8006700: 4a24 ldr r2, [pc, #144] ; (8006794 <UART_Start_Receive_IT+0x254>)
8006702: 671a str r2, [r3, #112] ; 0x70
}
__HAL_UNLOCK(huart);
8006704: 68fb ldr r3, [r7, #12]
8006706: 2280 movs r2, #128 ; 0x80
8006708: 2100 movs r1, #0
800670a: 5499 strb r1, [r3, r2]
/* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
if (huart->Init.Parity != UART_PARITY_NONE)
800670c: 68fb ldr r3, [r7, #12]
800670e: 691b ldr r3, [r3, #16]
8006710: 2b00 cmp r3, #0
8006712: d019 beq.n 8006748 <UART_Start_Receive_IT+0x208>
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8006714: f3ef 8310 mrs r3, PRIMASK
8006718: 61fb str r3, [r7, #28]
return(result);
800671a: 69fb ldr r3, [r7, #28]
{
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
800671c: 64fb str r3, [r7, #76] ; 0x4c
800671e: 2301 movs r3, #1
8006720: 623b str r3, [r7, #32]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006722: 6a3b ldr r3, [r7, #32]
8006724: f383 8810 msr PRIMASK, r3
}
8006728: 46c0 nop ; (mov r8, r8)
800672a: 68fb ldr r3, [r7, #12]
800672c: 681b ldr r3, [r3, #0]
800672e: 681a ldr r2, [r3, #0]
8006730: 68fb ldr r3, [r7, #12]
8006732: 681b ldr r3, [r3, #0]
8006734: 2190 movs r1, #144 ; 0x90
8006736: 0049 lsls r1, r1, #1
8006738: 430a orrs r2, r1
800673a: 601a str r2, [r3, #0]
800673c: 6cfb ldr r3, [r7, #76] ; 0x4c
800673e: 627b str r3, [r7, #36] ; 0x24
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006740: 6a7b ldr r3, [r7, #36] ; 0x24
8006742: f383 8810 msr PRIMASK, r3
}
8006746: e018 b.n 800677a <UART_Start_Receive_IT+0x23a>
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8006748: f3ef 8310 mrs r3, PRIMASK
800674c: 613b str r3, [r7, #16]
return(result);
800674e: 693b ldr r3, [r7, #16]
}
else
{
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
8006750: 653b str r3, [r7, #80] ; 0x50
8006752: 2301 movs r3, #1
8006754: 617b str r3, [r7, #20]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006756: 697b ldr r3, [r7, #20]
8006758: f383 8810 msr PRIMASK, r3
}
800675c: 46c0 nop ; (mov r8, r8)
800675e: 68fb ldr r3, [r7, #12]
8006760: 681b ldr r3, [r3, #0]
8006762: 681a ldr r2, [r3, #0]
8006764: 68fb ldr r3, [r7, #12]
8006766: 681b ldr r3, [r3, #0]
8006768: 2120 movs r1, #32
800676a: 430a orrs r2, r1
800676c: 601a str r2, [r3, #0]
800676e: 6d3b ldr r3, [r7, #80] ; 0x50
8006770: 61bb str r3, [r7, #24]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006772: 69bb ldr r3, [r7, #24]
8006774: f383 8810 msr PRIMASK, r3
}
8006778: 46c0 nop ; (mov r8, r8)
}
}
return HAL_OK;
800677a: 2300 movs r3, #0
}
800677c: 0018 movs r0, r3
800677e: 46bd mov sp, r7
8006780: b018 add sp, #96 ; 0x60
8006782: bd80 pop {r7, pc}
8006784: 000001ff .word 0x000001ff
8006788: 08007065 .word 0x08007065
800678c: 08006d81 .word 0x08006d81
8006790: 08006c15 .word 0x08006c15
8006794: 08006aa9 .word 0x08006aa9
08006798 <UART_EndTxTransfer>:
* @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
* @param huart UART handle.
* @retval None
*/
static void UART_EndTxTransfer(UART_HandleTypeDef *huart)
{
8006798: b580 push {r7, lr}
800679a: b08a sub sp, #40 ; 0x28
800679c: af00 add r7, sp, #0
800679e: 6078 str r0, [r7, #4]
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
80067a0: f3ef 8310 mrs r3, PRIMASK
80067a4: 60bb str r3, [r7, #8]
return(result);
80067a6: 68bb ldr r3, [r7, #8]
/* Disable TXEIE, TCIE, TXFT interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
80067a8: 627b str r3, [r7, #36] ; 0x24
80067aa: 2301 movs r3, #1
80067ac: 60fb str r3, [r7, #12]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80067ae: 68fb ldr r3, [r7, #12]
80067b0: f383 8810 msr PRIMASK, r3
}
80067b4: 46c0 nop ; (mov r8, r8)
80067b6: 687b ldr r3, [r7, #4]
80067b8: 681b ldr r3, [r3, #0]
80067ba: 681a ldr r2, [r3, #0]
80067bc: 687b ldr r3, [r7, #4]
80067be: 681b ldr r3, [r3, #0]
80067c0: 21c0 movs r1, #192 ; 0xc0
80067c2: 438a bics r2, r1
80067c4: 601a str r2, [r3, #0]
80067c6: 6a7b ldr r3, [r7, #36] ; 0x24
80067c8: 613b str r3, [r7, #16]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80067ca: 693b ldr r3, [r7, #16]
80067cc: f383 8810 msr PRIMASK, r3
}
80067d0: 46c0 nop ; (mov r8, r8)
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
80067d2: f3ef 8310 mrs r3, PRIMASK
80067d6: 617b str r3, [r7, #20]
return(result);
80067d8: 697b ldr r3, [r7, #20]
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE));
80067da: 623b str r3, [r7, #32]
80067dc: 2301 movs r3, #1
80067de: 61bb str r3, [r7, #24]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80067e0: 69bb ldr r3, [r7, #24]
80067e2: f383 8810 msr PRIMASK, r3
}
80067e6: 46c0 nop ; (mov r8, r8)
80067e8: 687b ldr r3, [r7, #4]
80067ea: 681b ldr r3, [r3, #0]
80067ec: 689a ldr r2, [r3, #8]
80067ee: 687b ldr r3, [r7, #4]
80067f0: 681b ldr r3, [r3, #0]
80067f2: 4908 ldr r1, [pc, #32] ; (8006814 <UART_EndTxTransfer+0x7c>)
80067f4: 400a ands r2, r1
80067f6: 609a str r2, [r3, #8]
80067f8: 6a3b ldr r3, [r7, #32]
80067fa: 61fb str r3, [r7, #28]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80067fc: 69fb ldr r3, [r7, #28]
80067fe: f383 8810 msr PRIMASK, r3
}
8006802: 46c0 nop ; (mov r8, r8)
/* At end of Tx process, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
8006804: 687b ldr r3, [r7, #4]
8006806: 2284 movs r2, #132 ; 0x84
8006808: 2120 movs r1, #32
800680a: 5099 str r1, [r3, r2]
}
800680c: 46c0 nop ; (mov r8, r8)
800680e: 46bd mov sp, r7
8006810: b00a add sp, #40 ; 0x28
8006812: bd80 pop {r7, pc}
8006814: ff7fffff .word 0xff7fffff
08006818 <UART_EndRxTransfer>:
* @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
* @param huart UART handle.
* @retval None
*/
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
{
8006818: b580 push {r7, lr}
800681a: b08e sub sp, #56 ; 0x38
800681c: af00 add r7, sp, #0
800681e: 6078 str r0, [r7, #4]
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8006820: f3ef 8310 mrs r3, PRIMASK
8006824: 617b str r3, [r7, #20]
return(result);
8006826: 697b ldr r3, [r7, #20]
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
8006828: 637b str r3, [r7, #52] ; 0x34
800682a: 2301 movs r3, #1
800682c: 61bb str r3, [r7, #24]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
800682e: 69bb ldr r3, [r7, #24]
8006830: f383 8810 msr PRIMASK, r3
}
8006834: 46c0 nop ; (mov r8, r8)
8006836: 687b ldr r3, [r7, #4]
8006838: 681b ldr r3, [r3, #0]
800683a: 681a ldr r2, [r3, #0]
800683c: 687b ldr r3, [r7, #4]
800683e: 681b ldr r3, [r3, #0]
8006840: 4926 ldr r1, [pc, #152] ; (80068dc <UART_EndRxTransfer+0xc4>)
8006842: 400a ands r2, r1
8006844: 601a str r2, [r3, #0]
8006846: 6b7b ldr r3, [r7, #52] ; 0x34
8006848: 61fb str r3, [r7, #28]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
800684a: 69fb ldr r3, [r7, #28]
800684c: f383 8810 msr PRIMASK, r3
}
8006850: 46c0 nop ; (mov r8, r8)
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8006852: f3ef 8310 mrs r3, PRIMASK
8006856: 623b str r3, [r7, #32]
return(result);
8006858: 6a3b ldr r3, [r7, #32]
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
800685a: 633b str r3, [r7, #48] ; 0x30
800685c: 2301 movs r3, #1
800685e: 627b str r3, [r7, #36] ; 0x24
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006860: 6a7b ldr r3, [r7, #36] ; 0x24
8006862: f383 8810 msr PRIMASK, r3
}
8006866: 46c0 nop ; (mov r8, r8)
8006868: 687b ldr r3, [r7, #4]
800686a: 681b ldr r3, [r3, #0]
800686c: 689a ldr r2, [r3, #8]
800686e: 687b ldr r3, [r7, #4]
8006870: 681b ldr r3, [r3, #0]
8006872: 491b ldr r1, [pc, #108] ; (80068e0 <UART_EndRxTransfer+0xc8>)
8006874: 400a ands r2, r1
8006876: 609a str r2, [r3, #8]
8006878: 6b3b ldr r3, [r7, #48] ; 0x30
800687a: 62bb str r3, [r7, #40] ; 0x28
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
800687c: 6abb ldr r3, [r7, #40] ; 0x28
800687e: f383 8810 msr PRIMASK, r3
}
8006882: 46c0 nop ; (mov r8, r8)
/* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
8006884: 687b ldr r3, [r7, #4]
8006886: 6edb ldr r3, [r3, #108] ; 0x6c
8006888: 2b01 cmp r3, #1
800688a: d118 bne.n 80068be <UART_EndRxTransfer+0xa6>
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
800688c: f3ef 8310 mrs r3, PRIMASK
8006890: 60bb str r3, [r7, #8]
return(result);
8006892: 68bb ldr r3, [r7, #8]
{
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8006894: 62fb str r3, [r7, #44] ; 0x2c
8006896: 2301 movs r3, #1
8006898: 60fb str r3, [r7, #12]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
800689a: 68fb ldr r3, [r7, #12]
800689c: f383 8810 msr PRIMASK, r3
}
80068a0: 46c0 nop ; (mov r8, r8)
80068a2: 687b ldr r3, [r7, #4]
80068a4: 681b ldr r3, [r3, #0]
80068a6: 681a ldr r2, [r3, #0]
80068a8: 687b ldr r3, [r7, #4]
80068aa: 681b ldr r3, [r3, #0]
80068ac: 2110 movs r1, #16
80068ae: 438a bics r2, r1
80068b0: 601a str r2, [r3, #0]
80068b2: 6afb ldr r3, [r7, #44] ; 0x2c
80068b4: 613b str r3, [r7, #16]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80068b6: 693b ldr r3, [r7, #16]
80068b8: f383 8810 msr PRIMASK, r3
}
80068bc: 46c0 nop ; (mov r8, r8)
}
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
80068be: 687b ldr r3, [r7, #4]
80068c0: 2288 movs r2, #136 ; 0x88
80068c2: 2120 movs r1, #32
80068c4: 5099 str r1, [r3, r2]
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
80068c6: 687b ldr r3, [r7, #4]
80068c8: 2200 movs r2, #0
80068ca: 66da str r2, [r3, #108] ; 0x6c
/* Reset RxIsr function pointer */
huart->RxISR = NULL;
80068cc: 687b ldr r3, [r7, #4]
80068ce: 2200 movs r2, #0
80068d0: 671a str r2, [r3, #112] ; 0x70
}
80068d2: 46c0 nop ; (mov r8, r8)
80068d4: 46bd mov sp, r7
80068d6: b00e add sp, #56 ; 0x38
80068d8: bd80 pop {r7, pc}
80068da: 46c0 nop ; (mov r8, r8)
80068dc: fffffedf .word 0xfffffedf
80068e0: effffffe .word 0xeffffffe
080068e4 <UART_DMATransmitCplt>:
* @brief DMA UART transmit process complete callback.
* @param hdma DMA handle.
* @retval None
*/
static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
{
80068e4: b580 push {r7, lr}
80068e6: b08c sub sp, #48 ; 0x30
80068e8: af00 add r7, sp, #0
80068ea: 6078 str r0, [r7, #4]
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
80068ec: 687b ldr r3, [r7, #4]
80068ee: 6a9b ldr r3, [r3, #40] ; 0x28
80068f0: 62fb str r3, [r7, #44] ; 0x2c
/* DMA Normal mode */
if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
80068f2: 687b ldr r3, [r7, #4]
80068f4: 681b ldr r3, [r3, #0]
80068f6: 681b ldr r3, [r3, #0]
80068f8: 2220 movs r2, #32
80068fa: 4013 ands r3, r2
80068fc: d135 bne.n 800696a <UART_DMATransmitCplt+0x86>
{
huart->TxXferCount = 0U;
80068fe: 6afb ldr r3, [r7, #44] ; 0x2c
8006900: 2256 movs r2, #86 ; 0x56
8006902: 2100 movs r1, #0
8006904: 5299 strh r1, [r3, r2]
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8006906: f3ef 8310 mrs r3, PRIMASK
800690a: 60fb str r3, [r7, #12]
return(result);
800690c: 68fb ldr r3, [r7, #12]
/* Disable the DMA transfer for transmit request by resetting the DMAT bit
in the UART CR3 register */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
800690e: 62bb str r3, [r7, #40] ; 0x28
8006910: 2301 movs r3, #1
8006912: 613b str r3, [r7, #16]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006914: 693b ldr r3, [r7, #16]
8006916: f383 8810 msr PRIMASK, r3
}
800691a: 46c0 nop ; (mov r8, r8)
800691c: 6afb ldr r3, [r7, #44] ; 0x2c
800691e: 681b ldr r3, [r3, #0]
8006920: 689a ldr r2, [r3, #8]
8006922: 6afb ldr r3, [r7, #44] ; 0x2c
8006924: 681b ldr r3, [r3, #0]
8006926: 2180 movs r1, #128 ; 0x80
8006928: 438a bics r2, r1
800692a: 609a str r2, [r3, #8]
800692c: 6abb ldr r3, [r7, #40] ; 0x28
800692e: 617b str r3, [r7, #20]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006930: 697b ldr r3, [r7, #20]
8006932: f383 8810 msr PRIMASK, r3
}
8006936: 46c0 nop ; (mov r8, r8)
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8006938: f3ef 8310 mrs r3, PRIMASK
800693c: 61bb str r3, [r7, #24]
return(result);
800693e: 69bb ldr r3, [r7, #24]
/* Enable the UART Transmit Complete Interrupt */
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
8006940: 627b str r3, [r7, #36] ; 0x24
8006942: 2301 movs r3, #1
8006944: 61fb str r3, [r7, #28]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006946: 69fb ldr r3, [r7, #28]
8006948: f383 8810 msr PRIMASK, r3
}
800694c: 46c0 nop ; (mov r8, r8)
800694e: 6afb ldr r3, [r7, #44] ; 0x2c
8006950: 681b ldr r3, [r3, #0]
8006952: 681a ldr r2, [r3, #0]
8006954: 6afb ldr r3, [r7, #44] ; 0x2c
8006956: 681b ldr r3, [r3, #0]
8006958: 2140 movs r1, #64 ; 0x40
800695a: 430a orrs r2, r1
800695c: 601a str r2, [r3, #0]
800695e: 6a7b ldr r3, [r7, #36] ; 0x24
8006960: 623b str r3, [r7, #32]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006962: 6a3b ldr r3, [r7, #32]
8006964: f383 8810 msr PRIMASK, r3
}
8006968: e004 b.n 8006974 <UART_DMATransmitCplt+0x90>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Tx complete callback*/
huart->TxCpltCallback(huart);
#else
/*Call legacy weak Tx complete callback*/
HAL_UART_TxCpltCallback(huart);
800696a: 6afb ldr r3, [r7, #44] ; 0x2c
800696c: 0018 movs r0, r3
800696e: f7fa fd9f bl 80014b0 <HAL_UART_TxCpltCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
}
8006972: 46c0 nop ; (mov r8, r8)
8006974: 46c0 nop ; (mov r8, r8)
8006976: 46bd mov sp, r7
8006978: b00c add sp, #48 ; 0x30
800697a: bd80 pop {r7, pc}
0800697c <UART_DMATxHalfCplt>:
* @brief DMA UART transmit process half complete callback.
* @param hdma DMA handle.
* @retval None
*/
static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
{
800697c: b580 push {r7, lr}
800697e: b084 sub sp, #16
8006980: af00 add r7, sp, #0
8006982: 6078 str r0, [r7, #4]
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
8006984: 687b ldr r3, [r7, #4]
8006986: 6a9b ldr r3, [r3, #40] ; 0x28
8006988: 60fb str r3, [r7, #12]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Tx Half complete callback*/
huart->TxHalfCpltCallback(huart);
#else
/*Call legacy weak Tx Half complete callback*/
HAL_UART_TxHalfCpltCallback(huart);
800698a: 68fb ldr r3, [r7, #12]
800698c: 0018 movs r0, r3
800698e: f7ff f985 bl 8005c9c <HAL_UART_TxHalfCpltCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
8006992: 46c0 nop ; (mov r8, r8)
8006994: 46bd mov sp, r7
8006996: b004 add sp, #16
8006998: bd80 pop {r7, pc}
0800699a <UART_DMAError>:
* @brief DMA UART communication error callback.
* @param hdma DMA handle.
* @retval None
*/
static void UART_DMAError(DMA_HandleTypeDef *hdma)
{
800699a: b580 push {r7, lr}
800699c: b086 sub sp, #24
800699e: af00 add r7, sp, #0
80069a0: 6078 str r0, [r7, #4]
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
80069a2: 687b ldr r3, [r7, #4]
80069a4: 6a9b ldr r3, [r3, #40] ; 0x28
80069a6: 617b str r3, [r7, #20]
const HAL_UART_StateTypeDef gstate = huart->gState;
80069a8: 697b ldr r3, [r7, #20]
80069aa: 2284 movs r2, #132 ; 0x84
80069ac: 589b ldr r3, [r3, r2]
80069ae: 613b str r3, [r7, #16]
const HAL_UART_StateTypeDef rxstate = huart->RxState;
80069b0: 697b ldr r3, [r7, #20]
80069b2: 2288 movs r2, #136 ; 0x88
80069b4: 589b ldr r3, [r3, r2]
80069b6: 60fb str r3, [r7, #12]
/* Stop UART DMA Tx request if ongoing */
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
80069b8: 697b ldr r3, [r7, #20]
80069ba: 681b ldr r3, [r3, #0]
80069bc: 689b ldr r3, [r3, #8]
80069be: 2280 movs r2, #128 ; 0x80
80069c0: 4013 ands r3, r2
80069c2: 2b80 cmp r3, #128 ; 0x80
80069c4: d10a bne.n 80069dc <UART_DMAError+0x42>
80069c6: 693b ldr r3, [r7, #16]
80069c8: 2b21 cmp r3, #33 ; 0x21
80069ca: d107 bne.n 80069dc <UART_DMAError+0x42>
(gstate == HAL_UART_STATE_BUSY_TX))
{
huart->TxXferCount = 0U;
80069cc: 697b ldr r3, [r7, #20]
80069ce: 2256 movs r2, #86 ; 0x56
80069d0: 2100 movs r1, #0
80069d2: 5299 strh r1, [r3, r2]
UART_EndTxTransfer(huart);
80069d4: 697b ldr r3, [r7, #20]
80069d6: 0018 movs r0, r3
80069d8: f7ff fede bl 8006798 <UART_EndTxTransfer>
}
/* Stop UART DMA Rx request if ongoing */
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
80069dc: 697b ldr r3, [r7, #20]
80069de: 681b ldr r3, [r3, #0]
80069e0: 689b ldr r3, [r3, #8]
80069e2: 2240 movs r2, #64 ; 0x40
80069e4: 4013 ands r3, r2
80069e6: 2b40 cmp r3, #64 ; 0x40
80069e8: d10a bne.n 8006a00 <UART_DMAError+0x66>
80069ea: 68fb ldr r3, [r7, #12]
80069ec: 2b22 cmp r3, #34 ; 0x22
80069ee: d107 bne.n 8006a00 <UART_DMAError+0x66>
(rxstate == HAL_UART_STATE_BUSY_RX))
{
huart->RxXferCount = 0U;
80069f0: 697b ldr r3, [r7, #20]
80069f2: 225e movs r2, #94 ; 0x5e
80069f4: 2100 movs r1, #0
80069f6: 5299 strh r1, [r3, r2]
UART_EndRxTransfer(huart);
80069f8: 697b ldr r3, [r7, #20]
80069fa: 0018 movs r0, r3
80069fc: f7ff ff0c bl 8006818 <UART_EndRxTransfer>
}
huart->ErrorCode |= HAL_UART_ERROR_DMA;
8006a00: 697b ldr r3, [r7, #20]
8006a02: 228c movs r2, #140 ; 0x8c
8006a04: 589b ldr r3, [r3, r2]
8006a06: 2210 movs r2, #16
8006a08: 431a orrs r2, r3
8006a0a: 697b ldr r3, [r7, #20]
8006a0c: 218c movs r1, #140 ; 0x8c
8006a0e: 505a str r2, [r3, r1]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
8006a10: 697b ldr r3, [r7, #20]
8006a12: 0018 movs r0, r3
8006a14: f7fa fd62 bl 80014dc <HAL_UART_ErrorCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
8006a18: 46c0 nop ; (mov r8, r8)
8006a1a: 46bd mov sp, r7
8006a1c: b006 add sp, #24
8006a1e: bd80 pop {r7, pc}
08006a20 <UART_DMAAbortOnError>:
* (To be called at end of DMA Abort procedure following error occurrence).
* @param hdma DMA handle.
* @retval None
*/
static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
{
8006a20: b580 push {r7, lr}
8006a22: b084 sub sp, #16
8006a24: af00 add r7, sp, #0
8006a26: 6078 str r0, [r7, #4]
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
8006a28: 687b ldr r3, [r7, #4]
8006a2a: 6a9b ldr r3, [r3, #40] ; 0x28
8006a2c: 60fb str r3, [r7, #12]
huart->RxXferCount = 0U;
8006a2e: 68fb ldr r3, [r7, #12]
8006a30: 225e movs r2, #94 ; 0x5e
8006a32: 2100 movs r1, #0
8006a34: 5299 strh r1, [r3, r2]
huart->TxXferCount = 0U;
8006a36: 68fb ldr r3, [r7, #12]
8006a38: 2256 movs r2, #86 ; 0x56
8006a3a: 2100 movs r1, #0
8006a3c: 5299 strh r1, [r3, r2]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
8006a3e: 68fb ldr r3, [r7, #12]
8006a40: 0018 movs r0, r3
8006a42: f7fa fd4b bl 80014dc <HAL_UART_ErrorCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
8006a46: 46c0 nop ; (mov r8, r8)
8006a48: 46bd mov sp, r7
8006a4a: b004 add sp, #16
8006a4c: bd80 pop {r7, pc}
08006a4e <UART_EndTransmit_IT>:
* @param huart pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
static void UART_EndTransmit_IT(UART_HandleTypeDef *huart)
{
8006a4e: b580 push {r7, lr}
8006a50: b086 sub sp, #24
8006a52: af00 add r7, sp, #0
8006a54: 6078 str r0, [r7, #4]
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8006a56: f3ef 8310 mrs r3, PRIMASK
8006a5a: 60bb str r3, [r7, #8]
return(result);
8006a5c: 68bb ldr r3, [r7, #8]
/* Disable the UART Transmit Complete Interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
8006a5e: 617b str r3, [r7, #20]
8006a60: 2301 movs r3, #1
8006a62: 60fb str r3, [r7, #12]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006a64: 68fb ldr r3, [r7, #12]
8006a66: f383 8810 msr PRIMASK, r3
}
8006a6a: 46c0 nop ; (mov r8, r8)
8006a6c: 687b ldr r3, [r7, #4]
8006a6e: 681b ldr r3, [r3, #0]
8006a70: 681a ldr r2, [r3, #0]
8006a72: 687b ldr r3, [r7, #4]
8006a74: 681b ldr r3, [r3, #0]
8006a76: 2140 movs r1, #64 ; 0x40
8006a78: 438a bics r2, r1
8006a7a: 601a str r2, [r3, #0]
8006a7c: 697b ldr r3, [r7, #20]
8006a7e: 613b str r3, [r7, #16]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006a80: 693b ldr r3, [r7, #16]
8006a82: f383 8810 msr PRIMASK, r3
}
8006a86: 46c0 nop ; (mov r8, r8)
/* Tx process is ended, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
8006a88: 687b ldr r3, [r7, #4]
8006a8a: 2284 movs r2, #132 ; 0x84
8006a8c: 2120 movs r1, #32
8006a8e: 5099 str r1, [r3, r2]
/* Cleat TxISR function pointer */
huart->TxISR = NULL;
8006a90: 687b ldr r3, [r7, #4]
8006a92: 2200 movs r2, #0
8006a94: 675a str r2, [r3, #116] ; 0x74
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Tx complete callback*/
huart->TxCpltCallback(huart);
#else
/*Call legacy weak Tx complete callback*/
HAL_UART_TxCpltCallback(huart);
8006a96: 687b ldr r3, [r7, #4]
8006a98: 0018 movs r0, r3
8006a9a: f7fa fd09 bl 80014b0 <HAL_UART_TxCpltCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
8006a9e: 46c0 nop ; (mov r8, r8)
8006aa0: 46bd mov sp, r7
8006aa2: b006 add sp, #24
8006aa4: bd80 pop {r7, pc}
...
08006aa8 <UART_RxISR_8BIT>:
* @brief RX interrupt handler for 7 or 8 bits data word length .
* @param huart UART handle.
* @retval None
*/
static void UART_RxISR_8BIT(UART_HandleTypeDef *huart)
{
8006aa8: b580 push {r7, lr}
8006aaa: b090 sub sp, #64 ; 0x40
8006aac: af00 add r7, sp, #0
8006aae: 6078 str r0, [r7, #4]
uint16_t uhMask = huart->Mask;
8006ab0: 203e movs r0, #62 ; 0x3e
8006ab2: 183b adds r3, r7, r0
8006ab4: 687a ldr r2, [r7, #4]
8006ab6: 2160 movs r1, #96 ; 0x60
8006ab8: 5a52 ldrh r2, [r2, r1]
8006aba: 801a strh r2, [r3, #0]
uint16_t uhdata;
/* Check that a Rx process is ongoing */
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
8006abc: 687b ldr r3, [r7, #4]
8006abe: 2288 movs r2, #136 ; 0x88
8006ac0: 589b ldr r3, [r3, r2]
8006ac2: 2b22 cmp r3, #34 ; 0x22
8006ac4: d000 beq.n 8006ac8 <UART_RxISR_8BIT+0x20>
8006ac6: e097 b.n 8006bf8 <UART_RxISR_8BIT+0x150>
{
uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
8006ac8: 687b ldr r3, [r7, #4]
8006aca: 681b ldr r3, [r3, #0]
8006acc: 6a5a ldr r2, [r3, #36] ; 0x24
8006ace: 213c movs r1, #60 ; 0x3c
8006ad0: 187b adds r3, r7, r1
8006ad2: 801a strh r2, [r3, #0]
*huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
8006ad4: 187b adds r3, r7, r1
8006ad6: 881b ldrh r3, [r3, #0]
8006ad8: b2da uxtb r2, r3
8006ada: 183b adds r3, r7, r0
8006adc: 881b ldrh r3, [r3, #0]
8006ade: b2d9 uxtb r1, r3
8006ae0: 687b ldr r3, [r7, #4]
8006ae2: 6d9b ldr r3, [r3, #88] ; 0x58
8006ae4: 400a ands r2, r1
8006ae6: b2d2 uxtb r2, r2
8006ae8: 701a strb r2, [r3, #0]
huart->pRxBuffPtr++;
8006aea: 687b ldr r3, [r7, #4]
8006aec: 6d9b ldr r3, [r3, #88] ; 0x58
8006aee: 1c5a adds r2, r3, #1
8006af0: 687b ldr r3, [r7, #4]
8006af2: 659a str r2, [r3, #88] ; 0x58
huart->RxXferCount--;
8006af4: 687b ldr r3, [r7, #4]
8006af6: 225e movs r2, #94 ; 0x5e
8006af8: 5a9b ldrh r3, [r3, r2]
8006afa: b29b uxth r3, r3
8006afc: 3b01 subs r3, #1
8006afe: b299 uxth r1, r3
8006b00: 687b ldr r3, [r7, #4]
8006b02: 225e movs r2, #94 ; 0x5e
8006b04: 5299 strh r1, [r3, r2]
if (huart->RxXferCount == 0U)
8006b06: 687b ldr r3, [r7, #4]
8006b08: 225e movs r2, #94 ; 0x5e
8006b0a: 5a9b ldrh r3, [r3, r2]
8006b0c: b29b uxth r3, r3
8006b0e: 2b00 cmp r3, #0
8006b10: d000 beq.n 8006b14 <UART_RxISR_8BIT+0x6c>
8006b12: e079 b.n 8006c08 <UART_RxISR_8BIT+0x160>
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8006b14: f3ef 8310 mrs r3, PRIMASK
8006b18: 61bb str r3, [r7, #24]
return(result);
8006b1a: 69bb ldr r3, [r7, #24]
{
/* Disable the UART Parity Error Interrupt and RXNE interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
8006b1c: 63bb str r3, [r7, #56] ; 0x38
8006b1e: 2301 movs r3, #1
8006b20: 61fb str r3, [r7, #28]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006b22: 69fb ldr r3, [r7, #28]
8006b24: f383 8810 msr PRIMASK, r3
}
8006b28: 46c0 nop ; (mov r8, r8)
8006b2a: 687b ldr r3, [r7, #4]
8006b2c: 681b ldr r3, [r3, #0]
8006b2e: 681a ldr r2, [r3, #0]
8006b30: 687b ldr r3, [r7, #4]
8006b32: 681b ldr r3, [r3, #0]
8006b34: 4936 ldr r1, [pc, #216] ; (8006c10 <UART_RxISR_8BIT+0x168>)
8006b36: 400a ands r2, r1
8006b38: 601a str r2, [r3, #0]
8006b3a: 6bbb ldr r3, [r7, #56] ; 0x38
8006b3c: 623b str r3, [r7, #32]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006b3e: 6a3b ldr r3, [r7, #32]
8006b40: f383 8810 msr PRIMASK, r3
}
8006b44: 46c0 nop ; (mov r8, r8)
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8006b46: f3ef 8310 mrs r3, PRIMASK
8006b4a: 627b str r3, [r7, #36] ; 0x24
return(result);
8006b4c: 6a7b ldr r3, [r7, #36] ; 0x24
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
8006b4e: 637b str r3, [r7, #52] ; 0x34
8006b50: 2301 movs r3, #1
8006b52: 62bb str r3, [r7, #40] ; 0x28
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006b54: 6abb ldr r3, [r7, #40] ; 0x28
8006b56: f383 8810 msr PRIMASK, r3
}
8006b5a: 46c0 nop ; (mov r8, r8)
8006b5c: 687b ldr r3, [r7, #4]
8006b5e: 681b ldr r3, [r3, #0]
8006b60: 689a ldr r2, [r3, #8]
8006b62: 687b ldr r3, [r7, #4]
8006b64: 681b ldr r3, [r3, #0]
8006b66: 2101 movs r1, #1
8006b68: 438a bics r2, r1
8006b6a: 609a str r2, [r3, #8]
8006b6c: 6b7b ldr r3, [r7, #52] ; 0x34
8006b6e: 62fb str r3, [r7, #44] ; 0x2c
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006b70: 6afb ldr r3, [r7, #44] ; 0x2c
8006b72: f383 8810 msr PRIMASK, r3
}
8006b76: 46c0 nop ; (mov r8, r8)
/* Rx process is completed, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
8006b78: 687b ldr r3, [r7, #4]
8006b7a: 2288 movs r2, #136 ; 0x88
8006b7c: 2120 movs r1, #32
8006b7e: 5099 str r1, [r3, r2]
/* Clear RxISR function pointer */
huart->RxISR = NULL;
8006b80: 687b ldr r3, [r7, #4]
8006b82: 2200 movs r2, #0
8006b84: 671a str r2, [r3, #112] ; 0x70
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
8006b86: 687b ldr r3, [r7, #4]
8006b88: 6edb ldr r3, [r3, #108] ; 0x6c
8006b8a: 2b01 cmp r3, #1
8006b8c: d12f bne.n 8006bee <UART_RxISR_8BIT+0x146>
{
/* Set reception type to Standard */
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8006b8e: 687b ldr r3, [r7, #4]
8006b90: 2200 movs r2, #0
8006b92: 66da str r2, [r3, #108] ; 0x6c
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8006b94: f3ef 8310 mrs r3, PRIMASK
8006b98: 60fb str r3, [r7, #12]
return(result);
8006b9a: 68fb ldr r3, [r7, #12]
/* Disable IDLE interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8006b9c: 633b str r3, [r7, #48] ; 0x30
8006b9e: 2301 movs r3, #1
8006ba0: 613b str r3, [r7, #16]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006ba2: 693b ldr r3, [r7, #16]
8006ba4: f383 8810 msr PRIMASK, r3
}
8006ba8: 46c0 nop ; (mov r8, r8)
8006baa: 687b ldr r3, [r7, #4]
8006bac: 681b ldr r3, [r3, #0]
8006bae: 681a ldr r2, [r3, #0]
8006bb0: 687b ldr r3, [r7, #4]
8006bb2: 681b ldr r3, [r3, #0]
8006bb4: 2110 movs r1, #16
8006bb6: 438a bics r2, r1
8006bb8: 601a str r2, [r3, #0]
8006bba: 6b3b ldr r3, [r7, #48] ; 0x30
8006bbc: 617b str r3, [r7, #20]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006bbe: 697b ldr r3, [r7, #20]
8006bc0: f383 8810 msr PRIMASK, r3
}
8006bc4: 46c0 nop ; (mov r8, r8)
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
8006bc6: 687b ldr r3, [r7, #4]
8006bc8: 681b ldr r3, [r3, #0]
8006bca: 69db ldr r3, [r3, #28]
8006bcc: 2210 movs r2, #16
8006bce: 4013 ands r3, r2
8006bd0: 2b10 cmp r3, #16
8006bd2: d103 bne.n 8006bdc <UART_RxISR_8BIT+0x134>
{
/* Clear IDLE Flag */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
8006bd4: 687b ldr r3, [r7, #4]
8006bd6: 681b ldr r3, [r3, #0]
8006bd8: 2210 movs r2, #16
8006bda: 621a str r2, [r3, #32]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize);
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
8006bdc: 687b ldr r3, [r7, #4]
8006bde: 225c movs r2, #92 ; 0x5c
8006be0: 5a9a ldrh r2, [r3, r2]
8006be2: 687b ldr r3, [r7, #4]
8006be4: 0011 movs r1, r2
8006be6: 0018 movs r0, r3
8006be8: f7ff f860 bl 8005cac <HAL_UARTEx_RxEventCallback>
else
{
/* Clear RXNE interrupt flag */
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
}
}
8006bec: e00c b.n 8006c08 <UART_RxISR_8BIT+0x160>
HAL_UART_RxCpltCallback(huart);
8006bee: 687b ldr r3, [r7, #4]
8006bf0: 0018 movs r0, r3
8006bf2: f7fa fc1d bl 8001430 <HAL_UART_RxCpltCallback>
}
8006bf6: e007 b.n 8006c08 <UART_RxISR_8BIT+0x160>
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
8006bf8: 687b ldr r3, [r7, #4]
8006bfa: 681b ldr r3, [r3, #0]
8006bfc: 699a ldr r2, [r3, #24]
8006bfe: 687b ldr r3, [r7, #4]
8006c00: 681b ldr r3, [r3, #0]
8006c02: 2108 movs r1, #8
8006c04: 430a orrs r2, r1
8006c06: 619a str r2, [r3, #24]
}
8006c08: 46c0 nop ; (mov r8, r8)
8006c0a: 46bd mov sp, r7
8006c0c: b010 add sp, #64 ; 0x40
8006c0e: bd80 pop {r7, pc}
8006c10: fffffedf .word 0xfffffedf
08006c14 <UART_RxISR_16BIT>:
* interruptions have been enabled by HAL_UART_Receive_IT()
* @param huart UART handle.
* @retval None
*/
static void UART_RxISR_16BIT(UART_HandleTypeDef *huart)
{
8006c14: b580 push {r7, lr}
8006c16: b090 sub sp, #64 ; 0x40
8006c18: af00 add r7, sp, #0
8006c1a: 6078 str r0, [r7, #4]
uint16_t *tmp;
uint16_t uhMask = huart->Mask;
8006c1c: 203e movs r0, #62 ; 0x3e
8006c1e: 183b adds r3, r7, r0
8006c20: 687a ldr r2, [r7, #4]
8006c22: 2160 movs r1, #96 ; 0x60
8006c24: 5a52 ldrh r2, [r2, r1]
8006c26: 801a strh r2, [r3, #0]
uint16_t uhdata;
/* Check that a Rx process is ongoing */
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
8006c28: 687b ldr r3, [r7, #4]
8006c2a: 2288 movs r2, #136 ; 0x88
8006c2c: 589b ldr r3, [r3, r2]
8006c2e: 2b22 cmp r3, #34 ; 0x22
8006c30: d000 beq.n 8006c34 <UART_RxISR_16BIT+0x20>
8006c32: e097 b.n 8006d64 <UART_RxISR_16BIT+0x150>
{
uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
8006c34: 687b ldr r3, [r7, #4]
8006c36: 681b ldr r3, [r3, #0]
8006c38: 6a5a ldr r2, [r3, #36] ; 0x24
8006c3a: 213c movs r1, #60 ; 0x3c
8006c3c: 187b adds r3, r7, r1
8006c3e: 801a strh r2, [r3, #0]
tmp = (uint16_t *) huart->pRxBuffPtr ;
8006c40: 687b ldr r3, [r7, #4]
8006c42: 6d9b ldr r3, [r3, #88] ; 0x58
8006c44: 63bb str r3, [r7, #56] ; 0x38
*tmp = (uint16_t)(uhdata & uhMask);
8006c46: 187b adds r3, r7, r1
8006c48: 183a adds r2, r7, r0
8006c4a: 881b ldrh r3, [r3, #0]
8006c4c: 8812 ldrh r2, [r2, #0]
8006c4e: 4013 ands r3, r2
8006c50: b29a uxth r2, r3
8006c52: 6bbb ldr r3, [r7, #56] ; 0x38
8006c54: 801a strh r2, [r3, #0]
huart->pRxBuffPtr += 2U;
8006c56: 687b ldr r3, [r7, #4]
8006c58: 6d9b ldr r3, [r3, #88] ; 0x58
8006c5a: 1c9a adds r2, r3, #2
8006c5c: 687b ldr r3, [r7, #4]
8006c5e: 659a str r2, [r3, #88] ; 0x58
huart->RxXferCount--;
8006c60: 687b ldr r3, [r7, #4]
8006c62: 225e movs r2, #94 ; 0x5e
8006c64: 5a9b ldrh r3, [r3, r2]
8006c66: b29b uxth r3, r3
8006c68: 3b01 subs r3, #1
8006c6a: b299 uxth r1, r3
8006c6c: 687b ldr r3, [r7, #4]
8006c6e: 225e movs r2, #94 ; 0x5e
8006c70: 5299 strh r1, [r3, r2]
if (huart->RxXferCount == 0U)
8006c72: 687b ldr r3, [r7, #4]
8006c74: 225e movs r2, #94 ; 0x5e
8006c76: 5a9b ldrh r3, [r3, r2]
8006c78: b29b uxth r3, r3
8006c7a: 2b00 cmp r3, #0
8006c7c: d000 beq.n 8006c80 <UART_RxISR_16BIT+0x6c>
8006c7e: e079 b.n 8006d74 <UART_RxISR_16BIT+0x160>
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8006c80: f3ef 8310 mrs r3, PRIMASK
8006c84: 617b str r3, [r7, #20]
return(result);
8006c86: 697b ldr r3, [r7, #20]
{
/* Disable the UART Parity Error Interrupt and RXNE interrupt*/
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
8006c88: 637b str r3, [r7, #52] ; 0x34
8006c8a: 2301 movs r3, #1
8006c8c: 61bb str r3, [r7, #24]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006c8e: 69bb ldr r3, [r7, #24]
8006c90: f383 8810 msr PRIMASK, r3
}
8006c94: 46c0 nop ; (mov r8, r8)
8006c96: 687b ldr r3, [r7, #4]
8006c98: 681b ldr r3, [r3, #0]
8006c9a: 681a ldr r2, [r3, #0]
8006c9c: 687b ldr r3, [r7, #4]
8006c9e: 681b ldr r3, [r3, #0]
8006ca0: 4936 ldr r1, [pc, #216] ; (8006d7c <UART_RxISR_16BIT+0x168>)
8006ca2: 400a ands r2, r1
8006ca4: 601a str r2, [r3, #0]
8006ca6: 6b7b ldr r3, [r7, #52] ; 0x34
8006ca8: 61fb str r3, [r7, #28]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006caa: 69fb ldr r3, [r7, #28]
8006cac: f383 8810 msr PRIMASK, r3
}
8006cb0: 46c0 nop ; (mov r8, r8)
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8006cb2: f3ef 8310 mrs r3, PRIMASK
8006cb6: 623b str r3, [r7, #32]
return(result);
8006cb8: 6a3b ldr r3, [r7, #32]
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
8006cba: 633b str r3, [r7, #48] ; 0x30
8006cbc: 2301 movs r3, #1
8006cbe: 627b str r3, [r7, #36] ; 0x24
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006cc0: 6a7b ldr r3, [r7, #36] ; 0x24
8006cc2: f383 8810 msr PRIMASK, r3
}
8006cc6: 46c0 nop ; (mov r8, r8)
8006cc8: 687b ldr r3, [r7, #4]
8006cca: 681b ldr r3, [r3, #0]
8006ccc: 689a ldr r2, [r3, #8]
8006cce: 687b ldr r3, [r7, #4]
8006cd0: 681b ldr r3, [r3, #0]
8006cd2: 2101 movs r1, #1
8006cd4: 438a bics r2, r1
8006cd6: 609a str r2, [r3, #8]
8006cd8: 6b3b ldr r3, [r7, #48] ; 0x30
8006cda: 62bb str r3, [r7, #40] ; 0x28
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006cdc: 6abb ldr r3, [r7, #40] ; 0x28
8006cde: f383 8810 msr PRIMASK, r3
}
8006ce2: 46c0 nop ; (mov r8, r8)
/* Rx process is completed, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
8006ce4: 687b ldr r3, [r7, #4]
8006ce6: 2288 movs r2, #136 ; 0x88
8006ce8: 2120 movs r1, #32
8006cea: 5099 str r1, [r3, r2]
/* Clear RxISR function pointer */
huart->RxISR = NULL;
8006cec: 687b ldr r3, [r7, #4]
8006cee: 2200 movs r2, #0
8006cf0: 671a str r2, [r3, #112] ; 0x70
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
8006cf2: 687b ldr r3, [r7, #4]
8006cf4: 6edb ldr r3, [r3, #108] ; 0x6c
8006cf6: 2b01 cmp r3, #1
8006cf8: d12f bne.n 8006d5a <UART_RxISR_16BIT+0x146>
{
/* Set reception type to Standard */
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8006cfa: 687b ldr r3, [r7, #4]
8006cfc: 2200 movs r2, #0
8006cfe: 66da str r2, [r3, #108] ; 0x6c
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8006d00: f3ef 8310 mrs r3, PRIMASK
8006d04: 60bb str r3, [r7, #8]
return(result);
8006d06: 68bb ldr r3, [r7, #8]
/* Disable IDLE interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8006d08: 62fb str r3, [r7, #44] ; 0x2c
8006d0a: 2301 movs r3, #1
8006d0c: 60fb str r3, [r7, #12]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006d0e: 68fb ldr r3, [r7, #12]
8006d10: f383 8810 msr PRIMASK, r3
}
8006d14: 46c0 nop ; (mov r8, r8)
8006d16: 687b ldr r3, [r7, #4]
8006d18: 681b ldr r3, [r3, #0]
8006d1a: 681a ldr r2, [r3, #0]
8006d1c: 687b ldr r3, [r7, #4]
8006d1e: 681b ldr r3, [r3, #0]
8006d20: 2110 movs r1, #16
8006d22: 438a bics r2, r1
8006d24: 601a str r2, [r3, #0]
8006d26: 6afb ldr r3, [r7, #44] ; 0x2c
8006d28: 613b str r3, [r7, #16]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006d2a: 693b ldr r3, [r7, #16]
8006d2c: f383 8810 msr PRIMASK, r3
}
8006d30: 46c0 nop ; (mov r8, r8)
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
8006d32: 687b ldr r3, [r7, #4]
8006d34: 681b ldr r3, [r3, #0]
8006d36: 69db ldr r3, [r3, #28]
8006d38: 2210 movs r2, #16
8006d3a: 4013 ands r3, r2
8006d3c: 2b10 cmp r3, #16
8006d3e: d103 bne.n 8006d48 <UART_RxISR_16BIT+0x134>
{
/* Clear IDLE Flag */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
8006d40: 687b ldr r3, [r7, #4]
8006d42: 681b ldr r3, [r3, #0]
8006d44: 2210 movs r2, #16
8006d46: 621a str r2, [r3, #32]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize);
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
8006d48: 687b ldr r3, [r7, #4]
8006d4a: 225c movs r2, #92 ; 0x5c
8006d4c: 5a9a ldrh r2, [r3, r2]
8006d4e: 687b ldr r3, [r7, #4]
8006d50: 0011 movs r1, r2
8006d52: 0018 movs r0, r3
8006d54: f7fe ffaa bl 8005cac <HAL_UARTEx_RxEventCallback>
else
{
/* Clear RXNE interrupt flag */
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
}
}
8006d58: e00c b.n 8006d74 <UART_RxISR_16BIT+0x160>
HAL_UART_RxCpltCallback(huart);
8006d5a: 687b ldr r3, [r7, #4]
8006d5c: 0018 movs r0, r3
8006d5e: f7fa fb67 bl 8001430 <HAL_UART_RxCpltCallback>
}
8006d62: e007 b.n 8006d74 <UART_RxISR_16BIT+0x160>
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
8006d64: 687b ldr r3, [r7, #4]
8006d66: 681b ldr r3, [r3, #0]
8006d68: 699a ldr r2, [r3, #24]
8006d6a: 687b ldr r3, [r7, #4]
8006d6c: 681b ldr r3, [r3, #0]
8006d6e: 2108 movs r1, #8
8006d70: 430a orrs r2, r1
8006d72: 619a str r2, [r3, #24]
}
8006d74: 46c0 nop ; (mov r8, r8)
8006d76: 46bd mov sp, r7
8006d78: b010 add sp, #64 ; 0x40
8006d7a: bd80 pop {r7, pc}
8006d7c: fffffedf .word 0xfffffedf
08006d80 <UART_RxISR_8BIT_FIFOEN>:
* interruptions have been enabled by HAL_UART_Receive_IT()
* @param huart UART handle.
* @retval None
*/
static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)
{
8006d80: b580 push {r7, lr}
8006d82: b09c sub sp, #112 ; 0x70
8006d84: af00 add r7, sp, #0
8006d86: 6078 str r0, [r7, #4]
uint16_t uhMask = huart->Mask;
8006d88: 236a movs r3, #106 ; 0x6a
8006d8a: 18fb adds r3, r7, r3
8006d8c: 687a ldr r2, [r7, #4]
8006d8e: 2160 movs r1, #96 ; 0x60
8006d90: 5a52 ldrh r2, [r2, r1]
8006d92: 801a strh r2, [r3, #0]
uint16_t uhdata;
uint16_t nb_rx_data;
uint16_t rxdatacount;
uint32_t isrflags = READ_REG(huart->Instance->ISR);
8006d94: 687b ldr r3, [r7, #4]
8006d96: 681b ldr r3, [r3, #0]
8006d98: 69db ldr r3, [r3, #28]
8006d9a: 66fb str r3, [r7, #108] ; 0x6c
uint32_t cr1its = READ_REG(huart->Instance->CR1);
8006d9c: 687b ldr r3, [r7, #4]
8006d9e: 681b ldr r3, [r3, #0]
8006da0: 681b ldr r3, [r3, #0]
8006da2: 667b str r3, [r7, #100] ; 0x64
uint32_t cr3its = READ_REG(huart->Instance->CR3);
8006da4: 687b ldr r3, [r7, #4]
8006da6: 681b ldr r3, [r3, #0]
8006da8: 689b ldr r3, [r3, #8]
8006daa: 663b str r3, [r7, #96] ; 0x60
/* Check that a Rx process is ongoing */
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
8006dac: 687b ldr r3, [r7, #4]
8006dae: 2288 movs r2, #136 ; 0x88
8006db0: 589b ldr r3, [r3, r2]
8006db2: 2b22 cmp r3, #34 ; 0x22
8006db4: d000 beq.n 8006db8 <UART_RxISR_8BIT_FIFOEN+0x38>
8006db6: e141 b.n 800703c <UART_RxISR_8BIT_FIFOEN+0x2bc>
{
nb_rx_data = huart->NbRxDataToProcess;
8006db8: 235e movs r3, #94 ; 0x5e
8006dba: 18fb adds r3, r7, r3
8006dbc: 687a ldr r2, [r7, #4]
8006dbe: 2168 movs r1, #104 ; 0x68
8006dc0: 5a52 ldrh r2, [r2, r1]
8006dc2: 801a strh r2, [r3, #0]
while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
8006dc4: e0e8 b.n 8006f98 <UART_RxISR_8BIT_FIFOEN+0x218>
{
uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
8006dc6: 687b ldr r3, [r7, #4]
8006dc8: 681b ldr r3, [r3, #0]
8006dca: 6a5a ldr r2, [r3, #36] ; 0x24
8006dcc: 215c movs r1, #92 ; 0x5c
8006dce: 187b adds r3, r7, r1
8006dd0: 801a strh r2, [r3, #0]
*huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
8006dd2: 187b adds r3, r7, r1
8006dd4: 881b ldrh r3, [r3, #0]
8006dd6: b2da uxtb r2, r3
8006dd8: 236a movs r3, #106 ; 0x6a
8006dda: 18fb adds r3, r7, r3
8006ddc: 881b ldrh r3, [r3, #0]
8006dde: b2d9 uxtb r1, r3
8006de0: 687b ldr r3, [r7, #4]
8006de2: 6d9b ldr r3, [r3, #88] ; 0x58
8006de4: 400a ands r2, r1
8006de6: b2d2 uxtb r2, r2
8006de8: 701a strb r2, [r3, #0]
huart->pRxBuffPtr++;
8006dea: 687b ldr r3, [r7, #4]
8006dec: 6d9b ldr r3, [r3, #88] ; 0x58
8006dee: 1c5a adds r2, r3, #1
8006df0: 687b ldr r3, [r7, #4]
8006df2: 659a str r2, [r3, #88] ; 0x58
huart->RxXferCount--;
8006df4: 687b ldr r3, [r7, #4]
8006df6: 225e movs r2, #94 ; 0x5e
8006df8: 5a9b ldrh r3, [r3, r2]
8006dfa: b29b uxth r3, r3
8006dfc: 3b01 subs r3, #1
8006dfe: b299 uxth r1, r3
8006e00: 687b ldr r3, [r7, #4]
8006e02: 225e movs r2, #94 ; 0x5e
8006e04: 5299 strh r1, [r3, r2]
isrflags = READ_REG(huart->Instance->ISR);
8006e06: 687b ldr r3, [r7, #4]
8006e08: 681b ldr r3, [r3, #0]
8006e0a: 69db ldr r3, [r3, #28]
8006e0c: 66fb str r3, [r7, #108] ; 0x6c
/* If some non blocking errors occurred */
if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U)
8006e0e: 6efb ldr r3, [r7, #108] ; 0x6c
8006e10: 2207 movs r2, #7
8006e12: 4013 ands r3, r2
8006e14: d049 beq.n 8006eaa <UART_RxISR_8BIT_FIFOEN+0x12a>
{
/* UART parity error interrupt occurred -------------------------------------*/
if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
8006e16: 6efb ldr r3, [r7, #108] ; 0x6c
8006e18: 2201 movs r2, #1
8006e1a: 4013 ands r3, r2
8006e1c: d010 beq.n 8006e40 <UART_RxISR_8BIT_FIFOEN+0xc0>
8006e1e: 6e7a ldr r2, [r7, #100] ; 0x64
8006e20: 2380 movs r3, #128 ; 0x80
8006e22: 005b lsls r3, r3, #1
8006e24: 4013 ands r3, r2
8006e26: d00b beq.n 8006e40 <UART_RxISR_8BIT_FIFOEN+0xc0>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
8006e28: 687b ldr r3, [r7, #4]
8006e2a: 681b ldr r3, [r3, #0]
8006e2c: 2201 movs r2, #1
8006e2e: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_PE;
8006e30: 687b ldr r3, [r7, #4]
8006e32: 228c movs r2, #140 ; 0x8c
8006e34: 589b ldr r3, [r3, r2]
8006e36: 2201 movs r2, #1
8006e38: 431a orrs r2, r3
8006e3a: 687b ldr r3, [r7, #4]
8006e3c: 218c movs r1, #140 ; 0x8c
8006e3e: 505a str r2, [r3, r1]
}
/* UART frame error interrupt occurred --------------------------------------*/
if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
8006e40: 6efb ldr r3, [r7, #108] ; 0x6c
8006e42: 2202 movs r2, #2
8006e44: 4013 ands r3, r2
8006e46: d00f beq.n 8006e68 <UART_RxISR_8BIT_FIFOEN+0xe8>
8006e48: 6e3b ldr r3, [r7, #96] ; 0x60
8006e4a: 2201 movs r2, #1
8006e4c: 4013 ands r3, r2
8006e4e: d00b beq.n 8006e68 <UART_RxISR_8BIT_FIFOEN+0xe8>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
8006e50: 687b ldr r3, [r7, #4]
8006e52: 681b ldr r3, [r3, #0]
8006e54: 2202 movs r2, #2
8006e56: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_FE;
8006e58: 687b ldr r3, [r7, #4]
8006e5a: 228c movs r2, #140 ; 0x8c
8006e5c: 589b ldr r3, [r3, r2]
8006e5e: 2204 movs r2, #4
8006e60: 431a orrs r2, r3
8006e62: 687b ldr r3, [r7, #4]
8006e64: 218c movs r1, #140 ; 0x8c
8006e66: 505a str r2, [r3, r1]
}
/* UART noise error interrupt occurred --------------------------------------*/
if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
8006e68: 6efb ldr r3, [r7, #108] ; 0x6c
8006e6a: 2204 movs r2, #4
8006e6c: 4013 ands r3, r2
8006e6e: d00f beq.n 8006e90 <UART_RxISR_8BIT_FIFOEN+0x110>
8006e70: 6e3b ldr r3, [r7, #96] ; 0x60
8006e72: 2201 movs r2, #1
8006e74: 4013 ands r3, r2
8006e76: d00b beq.n 8006e90 <UART_RxISR_8BIT_FIFOEN+0x110>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
8006e78: 687b ldr r3, [r7, #4]
8006e7a: 681b ldr r3, [r3, #0]
8006e7c: 2204 movs r2, #4
8006e7e: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_NE;
8006e80: 687b ldr r3, [r7, #4]
8006e82: 228c movs r2, #140 ; 0x8c
8006e84: 589b ldr r3, [r3, r2]
8006e86: 2202 movs r2, #2
8006e88: 431a orrs r2, r3
8006e8a: 687b ldr r3, [r7, #4]
8006e8c: 218c movs r1, #140 ; 0x8c
8006e8e: 505a str r2, [r3, r1]
}
/* Call UART Error Call back function if need be ----------------------------*/
if (huart->ErrorCode != HAL_UART_ERROR_NONE)
8006e90: 687b ldr r3, [r7, #4]
8006e92: 228c movs r2, #140 ; 0x8c
8006e94: 589b ldr r3, [r3, r2]
8006e96: 2b00 cmp r3, #0
8006e98: d007 beq.n 8006eaa <UART_RxISR_8BIT_FIFOEN+0x12a>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
8006e9a: 687b ldr r3, [r7, #4]
8006e9c: 0018 movs r0, r3
8006e9e: f7fa fb1d bl 80014dc <HAL_UART_ErrorCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
huart->ErrorCode = HAL_UART_ERROR_NONE;
8006ea2: 687b ldr r3, [r7, #4]
8006ea4: 228c movs r2, #140 ; 0x8c
8006ea6: 2100 movs r1, #0
8006ea8: 5099 str r1, [r3, r2]
}
}
if (huart->RxXferCount == 0U)
8006eaa: 687b ldr r3, [r7, #4]
8006eac: 225e movs r2, #94 ; 0x5e
8006eae: 5a9b ldrh r3, [r3, r2]
8006eb0: b29b uxth r3, r3
8006eb2: 2b00 cmp r3, #0
8006eb4: d170 bne.n 8006f98 <UART_RxISR_8BIT_FIFOEN+0x218>
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8006eb6: f3ef 8310 mrs r3, PRIMASK
8006eba: 62fb str r3, [r7, #44] ; 0x2c
return(result);
8006ebc: 6afb ldr r3, [r7, #44] ; 0x2c
{
/* Disable the UART Parity Error Interrupt and RXFT interrupt*/
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
8006ebe: 65bb str r3, [r7, #88] ; 0x58
8006ec0: 2301 movs r3, #1
8006ec2: 633b str r3, [r7, #48] ; 0x30
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006ec4: 6b3b ldr r3, [r7, #48] ; 0x30
8006ec6: f383 8810 msr PRIMASK, r3
}
8006eca: 46c0 nop ; (mov r8, r8)
8006ecc: 687b ldr r3, [r7, #4]
8006ece: 681b ldr r3, [r3, #0]
8006ed0: 681a ldr r2, [r3, #0]
8006ed2: 687b ldr r3, [r7, #4]
8006ed4: 681b ldr r3, [r3, #0]
8006ed6: 495f ldr r1, [pc, #380] ; (8007054 <UART_RxISR_8BIT_FIFOEN+0x2d4>)
8006ed8: 400a ands r2, r1
8006eda: 601a str r2, [r3, #0]
8006edc: 6dbb ldr r3, [r7, #88] ; 0x58
8006ede: 637b str r3, [r7, #52] ; 0x34
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006ee0: 6b7b ldr r3, [r7, #52] ; 0x34
8006ee2: f383 8810 msr PRIMASK, r3
}
8006ee6: 46c0 nop ; (mov r8, r8)
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8006ee8: f3ef 8310 mrs r3, PRIMASK
8006eec: 63bb str r3, [r7, #56] ; 0x38
return(result);
8006eee: 6bbb ldr r3, [r7, #56] ; 0x38
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error)
and RX FIFO Threshold interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
8006ef0: 657b str r3, [r7, #84] ; 0x54
8006ef2: 2301 movs r3, #1
8006ef4: 63fb str r3, [r7, #60] ; 0x3c
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006ef6: 6bfb ldr r3, [r7, #60] ; 0x3c
8006ef8: f383 8810 msr PRIMASK, r3
}
8006efc: 46c0 nop ; (mov r8, r8)
8006efe: 687b ldr r3, [r7, #4]
8006f00: 681b ldr r3, [r3, #0]
8006f02: 689a ldr r2, [r3, #8]
8006f04: 687b ldr r3, [r7, #4]
8006f06: 681b ldr r3, [r3, #0]
8006f08: 4953 ldr r1, [pc, #332] ; (8007058 <UART_RxISR_8BIT_FIFOEN+0x2d8>)
8006f0a: 400a ands r2, r1
8006f0c: 609a str r2, [r3, #8]
8006f0e: 6d7b ldr r3, [r7, #84] ; 0x54
8006f10: 643b str r3, [r7, #64] ; 0x40
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006f12: 6c3b ldr r3, [r7, #64] ; 0x40
8006f14: f383 8810 msr PRIMASK, r3
}
8006f18: 46c0 nop ; (mov r8, r8)
/* Rx process is completed, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
8006f1a: 687b ldr r3, [r7, #4]
8006f1c: 2288 movs r2, #136 ; 0x88
8006f1e: 2120 movs r1, #32
8006f20: 5099 str r1, [r3, r2]
/* Clear RxISR function pointer */
huart->RxISR = NULL;
8006f22: 687b ldr r3, [r7, #4]
8006f24: 2200 movs r2, #0
8006f26: 671a str r2, [r3, #112] ; 0x70
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
8006f28: 687b ldr r3, [r7, #4]
8006f2a: 6edb ldr r3, [r3, #108] ; 0x6c
8006f2c: 2b01 cmp r3, #1
8006f2e: d12f bne.n 8006f90 <UART_RxISR_8BIT_FIFOEN+0x210>
{
/* Set reception type to Standard */
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8006f30: 687b ldr r3, [r7, #4]
8006f32: 2200 movs r2, #0
8006f34: 66da str r2, [r3, #108] ; 0x6c
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8006f36: f3ef 8310 mrs r3, PRIMASK
8006f3a: 623b str r3, [r7, #32]
return(result);
8006f3c: 6a3b ldr r3, [r7, #32]
/* Disable IDLE interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8006f3e: 653b str r3, [r7, #80] ; 0x50
8006f40: 2301 movs r3, #1
8006f42: 627b str r3, [r7, #36] ; 0x24
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006f44: 6a7b ldr r3, [r7, #36] ; 0x24
8006f46: f383 8810 msr PRIMASK, r3
}
8006f4a: 46c0 nop ; (mov r8, r8)
8006f4c: 687b ldr r3, [r7, #4]
8006f4e: 681b ldr r3, [r3, #0]
8006f50: 681a ldr r2, [r3, #0]
8006f52: 687b ldr r3, [r7, #4]
8006f54: 681b ldr r3, [r3, #0]
8006f56: 2110 movs r1, #16
8006f58: 438a bics r2, r1
8006f5a: 601a str r2, [r3, #0]
8006f5c: 6d3b ldr r3, [r7, #80] ; 0x50
8006f5e: 62bb str r3, [r7, #40] ; 0x28
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006f60: 6abb ldr r3, [r7, #40] ; 0x28
8006f62: f383 8810 msr PRIMASK, r3
}
8006f66: 46c0 nop ; (mov r8, r8)
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
8006f68: 687b ldr r3, [r7, #4]
8006f6a: 681b ldr r3, [r3, #0]
8006f6c: 69db ldr r3, [r3, #28]
8006f6e: 2210 movs r2, #16
8006f70: 4013 ands r3, r2
8006f72: 2b10 cmp r3, #16
8006f74: d103 bne.n 8006f7e <UART_RxISR_8BIT_FIFOEN+0x1fe>
{
/* Clear IDLE Flag */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
8006f76: 687b ldr r3, [r7, #4]
8006f78: 681b ldr r3, [r3, #0]
8006f7a: 2210 movs r2, #16
8006f7c: 621a str r2, [r3, #32]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize);
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
8006f7e: 687b ldr r3, [r7, #4]
8006f80: 225c movs r2, #92 ; 0x5c
8006f82: 5a9a ldrh r2, [r3, r2]
8006f84: 687b ldr r3, [r7, #4]
8006f86: 0011 movs r1, r2
8006f88: 0018 movs r0, r3
8006f8a: f7fe fe8f bl 8005cac <HAL_UARTEx_RxEventCallback>
8006f8e: e003 b.n 8006f98 <UART_RxISR_8BIT_FIFOEN+0x218>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx complete callback*/
huart->RxCpltCallback(huart);
#else
/*Call legacy weak Rx complete callback*/
HAL_UART_RxCpltCallback(huart);
8006f90: 687b ldr r3, [r7, #4]
8006f92: 0018 movs r0, r3
8006f94: f7fa fa4c bl 8001430 <HAL_UART_RxCpltCallback>
while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
8006f98: 235e movs r3, #94 ; 0x5e
8006f9a: 18fb adds r3, r7, r3
8006f9c: 881b ldrh r3, [r3, #0]
8006f9e: 2b00 cmp r3, #0
8006fa0: d004 beq.n 8006fac <UART_RxISR_8BIT_FIFOEN+0x22c>
8006fa2: 6efb ldr r3, [r7, #108] ; 0x6c
8006fa4: 2220 movs r2, #32
8006fa6: 4013 ands r3, r2
8006fa8: d000 beq.n 8006fac <UART_RxISR_8BIT_FIFOEN+0x22c>
8006faa: e70c b.n 8006dc6 <UART_RxISR_8BIT_FIFOEN+0x46>
/* When remaining number of bytes to receive is less than the RX FIFO
threshold, next incoming frames are processed as if FIFO mode was
disabled (i.e. one interrupt per received frame).
*/
rxdatacount = huart->RxXferCount;
8006fac: 204e movs r0, #78 ; 0x4e
8006fae: 183b adds r3, r7, r0
8006fb0: 687a ldr r2, [r7, #4]
8006fb2: 215e movs r1, #94 ; 0x5e
8006fb4: 5a52 ldrh r2, [r2, r1]
8006fb6: 801a strh r2, [r3, #0]
if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
8006fb8: 0001 movs r1, r0
8006fba: 187b adds r3, r7, r1
8006fbc: 881b ldrh r3, [r3, #0]
8006fbe: 2b00 cmp r3, #0
8006fc0: d044 beq.n 800704c <UART_RxISR_8BIT_FIFOEN+0x2cc>
8006fc2: 687b ldr r3, [r7, #4]
8006fc4: 2268 movs r2, #104 ; 0x68
8006fc6: 5a9b ldrh r3, [r3, r2]
8006fc8: 187a adds r2, r7, r1
8006fca: 8812 ldrh r2, [r2, #0]
8006fcc: 429a cmp r2, r3
8006fce: d23d bcs.n 800704c <UART_RxISR_8BIT_FIFOEN+0x2cc>
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8006fd0: f3ef 8310 mrs r3, PRIMASK
8006fd4: 60bb str r3, [r7, #8]
return(result);
8006fd6: 68bb ldr r3, [r7, #8]
{
/* Disable the UART RXFT interrupt*/
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
8006fd8: 64bb str r3, [r7, #72] ; 0x48
8006fda: 2301 movs r3, #1
8006fdc: 60fb str r3, [r7, #12]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006fde: 68fb ldr r3, [r7, #12]
8006fe0: f383 8810 msr PRIMASK, r3
}
8006fe4: 46c0 nop ; (mov r8, r8)
8006fe6: 687b ldr r3, [r7, #4]
8006fe8: 681b ldr r3, [r3, #0]
8006fea: 689a ldr r2, [r3, #8]
8006fec: 687b ldr r3, [r7, #4]
8006fee: 681b ldr r3, [r3, #0]
8006ff0: 491a ldr r1, [pc, #104] ; (800705c <UART_RxISR_8BIT_FIFOEN+0x2dc>)
8006ff2: 400a ands r2, r1
8006ff4: 609a str r2, [r3, #8]
8006ff6: 6cbb ldr r3, [r7, #72] ; 0x48
8006ff8: 613b str r3, [r7, #16]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006ffa: 693b ldr r3, [r7, #16]
8006ffc: f383 8810 msr PRIMASK, r3
}
8007000: 46c0 nop ; (mov r8, r8)
/* Update the RxISR function pointer */
huart->RxISR = UART_RxISR_8BIT;
8007002: 687b ldr r3, [r7, #4]
8007004: 4a16 ldr r2, [pc, #88] ; (8007060 <UART_RxISR_8BIT_FIFOEN+0x2e0>)
8007006: 671a str r2, [r3, #112] ; 0x70
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8007008: f3ef 8310 mrs r3, PRIMASK
800700c: 617b str r3, [r7, #20]
return(result);
800700e: 697b ldr r3, [r7, #20]
/* Enable the UART Data Register Not Empty interrupt */
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
8007010: 647b str r3, [r7, #68] ; 0x44
8007012: 2301 movs r3, #1
8007014: 61bb str r3, [r7, #24]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8007016: 69bb ldr r3, [r7, #24]
8007018: f383 8810 msr PRIMASK, r3
}
800701c: 46c0 nop ; (mov r8, r8)
800701e: 687b ldr r3, [r7, #4]
8007020: 681b ldr r3, [r3, #0]
8007022: 681a ldr r2, [r3, #0]
8007024: 687b ldr r3, [r7, #4]
8007026: 681b ldr r3, [r3, #0]
8007028: 2120 movs r1, #32
800702a: 430a orrs r2, r1
800702c: 601a str r2, [r3, #0]
800702e: 6c7b ldr r3, [r7, #68] ; 0x44
8007030: 61fb str r3, [r7, #28]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8007032: 69fb ldr r3, [r7, #28]
8007034: f383 8810 msr PRIMASK, r3
}
8007038: 46c0 nop ; (mov r8, r8)
else
{
/* Clear RXNE interrupt flag */
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
}
}
800703a: e007 b.n 800704c <UART_RxISR_8BIT_FIFOEN+0x2cc>
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
800703c: 687b ldr r3, [r7, #4]
800703e: 681b ldr r3, [r3, #0]
8007040: 699a ldr r2, [r3, #24]
8007042: 687b ldr r3, [r7, #4]
8007044: 681b ldr r3, [r3, #0]
8007046: 2108 movs r1, #8
8007048: 430a orrs r2, r1
800704a: 619a str r2, [r3, #24]
}
800704c: 46c0 nop ; (mov r8, r8)
800704e: 46bd mov sp, r7
8007050: b01c add sp, #112 ; 0x70
8007052: bd80 pop {r7, pc}
8007054: fffffeff .word 0xfffffeff
8007058: effffffe .word 0xeffffffe
800705c: efffffff .word 0xefffffff
8007060: 08006aa9 .word 0x08006aa9
08007064 <UART_RxISR_16BIT_FIFOEN>:
* interruptions have been enabled by HAL_UART_Receive_IT()
* @param huart UART handle.
* @retval None
*/
static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
{
8007064: b580 push {r7, lr}
8007066: b09e sub sp, #120 ; 0x78
8007068: af00 add r7, sp, #0
800706a: 6078 str r0, [r7, #4]
uint16_t *tmp;
uint16_t uhMask = huart->Mask;
800706c: 2372 movs r3, #114 ; 0x72
800706e: 18fb adds r3, r7, r3
8007070: 687a ldr r2, [r7, #4]
8007072: 2160 movs r1, #96 ; 0x60
8007074: 5a52 ldrh r2, [r2, r1]
8007076: 801a strh r2, [r3, #0]
uint16_t uhdata;
uint16_t nb_rx_data;
uint16_t rxdatacount;
uint32_t isrflags = READ_REG(huart->Instance->ISR);
8007078: 687b ldr r3, [r7, #4]
800707a: 681b ldr r3, [r3, #0]
800707c: 69db ldr r3, [r3, #28]
800707e: 677b str r3, [r7, #116] ; 0x74
uint32_t cr1its = READ_REG(huart->Instance->CR1);
8007080: 687b ldr r3, [r7, #4]
8007082: 681b ldr r3, [r3, #0]
8007084: 681b ldr r3, [r3, #0]
8007086: 66fb str r3, [r7, #108] ; 0x6c
uint32_t cr3its = READ_REG(huart->Instance->CR3);
8007088: 687b ldr r3, [r7, #4]
800708a: 681b ldr r3, [r3, #0]
800708c: 689b ldr r3, [r3, #8]
800708e: 66bb str r3, [r7, #104] ; 0x68
/* Check that a Rx process is ongoing */
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
8007090: 687b ldr r3, [r7, #4]
8007092: 2288 movs r2, #136 ; 0x88
8007094: 589b ldr r3, [r3, r2]
8007096: 2b22 cmp r3, #34 ; 0x22
8007098: d000 beq.n 800709c <UART_RxISR_16BIT_FIFOEN+0x38>
800709a: e141 b.n 8007320 <UART_RxISR_16BIT_FIFOEN+0x2bc>
{
nb_rx_data = huart->NbRxDataToProcess;
800709c: 2366 movs r3, #102 ; 0x66
800709e: 18fb adds r3, r7, r3
80070a0: 687a ldr r2, [r7, #4]
80070a2: 2168 movs r1, #104 ; 0x68
80070a4: 5a52 ldrh r2, [r2, r1]
80070a6: 801a strh r2, [r3, #0]
while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
80070a8: e0e8 b.n 800727c <UART_RxISR_16BIT_FIFOEN+0x218>
{
uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
80070aa: 687b ldr r3, [r7, #4]
80070ac: 681b ldr r3, [r3, #0]
80070ae: 6a5a ldr r2, [r3, #36] ; 0x24
80070b0: 2164 movs r1, #100 ; 0x64
80070b2: 187b adds r3, r7, r1
80070b4: 801a strh r2, [r3, #0]
tmp = (uint16_t *) huart->pRxBuffPtr ;
80070b6: 687b ldr r3, [r7, #4]
80070b8: 6d9b ldr r3, [r3, #88] ; 0x58
80070ba: 663b str r3, [r7, #96] ; 0x60
*tmp = (uint16_t)(uhdata & uhMask);
80070bc: 187b adds r3, r7, r1
80070be: 2272 movs r2, #114 ; 0x72
80070c0: 18ba adds r2, r7, r2
80070c2: 881b ldrh r3, [r3, #0]
80070c4: 8812 ldrh r2, [r2, #0]
80070c6: 4013 ands r3, r2
80070c8: b29a uxth r2, r3
80070ca: 6e3b ldr r3, [r7, #96] ; 0x60
80070cc: 801a strh r2, [r3, #0]
huart->pRxBuffPtr += 2U;
80070ce: 687b ldr r3, [r7, #4]
80070d0: 6d9b ldr r3, [r3, #88] ; 0x58
80070d2: 1c9a adds r2, r3, #2
80070d4: 687b ldr r3, [r7, #4]
80070d6: 659a str r2, [r3, #88] ; 0x58
huart->RxXferCount--;
80070d8: 687b ldr r3, [r7, #4]
80070da: 225e movs r2, #94 ; 0x5e
80070dc: 5a9b ldrh r3, [r3, r2]
80070de: b29b uxth r3, r3
80070e0: 3b01 subs r3, #1
80070e2: b299 uxth r1, r3
80070e4: 687b ldr r3, [r7, #4]
80070e6: 225e movs r2, #94 ; 0x5e
80070e8: 5299 strh r1, [r3, r2]
isrflags = READ_REG(huart->Instance->ISR);
80070ea: 687b ldr r3, [r7, #4]
80070ec: 681b ldr r3, [r3, #0]
80070ee: 69db ldr r3, [r3, #28]
80070f0: 677b str r3, [r7, #116] ; 0x74
/* If some non blocking errors occurred */
if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U)
80070f2: 6f7b ldr r3, [r7, #116] ; 0x74
80070f4: 2207 movs r2, #7
80070f6: 4013 ands r3, r2
80070f8: d049 beq.n 800718e <UART_RxISR_16BIT_FIFOEN+0x12a>
{
/* UART parity error interrupt occurred -------------------------------------*/
if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
80070fa: 6f7b ldr r3, [r7, #116] ; 0x74
80070fc: 2201 movs r2, #1
80070fe: 4013 ands r3, r2
8007100: d010 beq.n 8007124 <UART_RxISR_16BIT_FIFOEN+0xc0>
8007102: 6efa ldr r2, [r7, #108] ; 0x6c
8007104: 2380 movs r3, #128 ; 0x80
8007106: 005b lsls r3, r3, #1
8007108: 4013 ands r3, r2
800710a: d00b beq.n 8007124 <UART_RxISR_16BIT_FIFOEN+0xc0>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
800710c: 687b ldr r3, [r7, #4]
800710e: 681b ldr r3, [r3, #0]
8007110: 2201 movs r2, #1
8007112: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_PE;
8007114: 687b ldr r3, [r7, #4]
8007116: 228c movs r2, #140 ; 0x8c
8007118: 589b ldr r3, [r3, r2]
800711a: 2201 movs r2, #1
800711c: 431a orrs r2, r3
800711e: 687b ldr r3, [r7, #4]
8007120: 218c movs r1, #140 ; 0x8c
8007122: 505a str r2, [r3, r1]
}
/* UART frame error interrupt occurred --------------------------------------*/
if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
8007124: 6f7b ldr r3, [r7, #116] ; 0x74
8007126: 2202 movs r2, #2
8007128: 4013 ands r3, r2
800712a: d00f beq.n 800714c <UART_RxISR_16BIT_FIFOEN+0xe8>
800712c: 6ebb ldr r3, [r7, #104] ; 0x68
800712e: 2201 movs r2, #1
8007130: 4013 ands r3, r2
8007132: d00b beq.n 800714c <UART_RxISR_16BIT_FIFOEN+0xe8>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
8007134: 687b ldr r3, [r7, #4]
8007136: 681b ldr r3, [r3, #0]
8007138: 2202 movs r2, #2
800713a: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_FE;
800713c: 687b ldr r3, [r7, #4]
800713e: 228c movs r2, #140 ; 0x8c
8007140: 589b ldr r3, [r3, r2]
8007142: 2204 movs r2, #4
8007144: 431a orrs r2, r3
8007146: 687b ldr r3, [r7, #4]
8007148: 218c movs r1, #140 ; 0x8c
800714a: 505a str r2, [r3, r1]
}
/* UART noise error interrupt occurred --------------------------------------*/
if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
800714c: 6f7b ldr r3, [r7, #116] ; 0x74
800714e: 2204 movs r2, #4
8007150: 4013 ands r3, r2
8007152: d00f beq.n 8007174 <UART_RxISR_16BIT_FIFOEN+0x110>
8007154: 6ebb ldr r3, [r7, #104] ; 0x68
8007156: 2201 movs r2, #1
8007158: 4013 ands r3, r2
800715a: d00b beq.n 8007174 <UART_RxISR_16BIT_FIFOEN+0x110>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
800715c: 687b ldr r3, [r7, #4]
800715e: 681b ldr r3, [r3, #0]
8007160: 2204 movs r2, #4
8007162: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_NE;
8007164: 687b ldr r3, [r7, #4]
8007166: 228c movs r2, #140 ; 0x8c
8007168: 589b ldr r3, [r3, r2]
800716a: 2202 movs r2, #2
800716c: 431a orrs r2, r3
800716e: 687b ldr r3, [r7, #4]
8007170: 218c movs r1, #140 ; 0x8c
8007172: 505a str r2, [r3, r1]
}
/* Call UART Error Call back function if need be ----------------------------*/
if (huart->ErrorCode != HAL_UART_ERROR_NONE)
8007174: 687b ldr r3, [r7, #4]
8007176: 228c movs r2, #140 ; 0x8c
8007178: 589b ldr r3, [r3, r2]
800717a: 2b00 cmp r3, #0
800717c: d007 beq.n 800718e <UART_RxISR_16BIT_FIFOEN+0x12a>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
800717e: 687b ldr r3, [r7, #4]
8007180: 0018 movs r0, r3
8007182: f7fa f9ab bl 80014dc <HAL_UART_ErrorCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
huart->ErrorCode = HAL_UART_ERROR_NONE;
8007186: 687b ldr r3, [r7, #4]
8007188: 228c movs r2, #140 ; 0x8c
800718a: 2100 movs r1, #0
800718c: 5099 str r1, [r3, r2]
}
}
if (huart->RxXferCount == 0U)
800718e: 687b ldr r3, [r7, #4]
8007190: 225e movs r2, #94 ; 0x5e
8007192: 5a9b ldrh r3, [r3, r2]
8007194: b29b uxth r3, r3
8007196: 2b00 cmp r3, #0
8007198: d170 bne.n 800727c <UART_RxISR_16BIT_FIFOEN+0x218>
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
800719a: f3ef 8310 mrs r3, PRIMASK
800719e: 633b str r3, [r7, #48] ; 0x30
return(result);
80071a0: 6b3b ldr r3, [r7, #48] ; 0x30
{
/* Disable the UART Parity Error Interrupt and RXFT interrupt*/
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
80071a2: 65fb str r3, [r7, #92] ; 0x5c
80071a4: 2301 movs r3, #1
80071a6: 637b str r3, [r7, #52] ; 0x34
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80071a8: 6b7b ldr r3, [r7, #52] ; 0x34
80071aa: f383 8810 msr PRIMASK, r3
}
80071ae: 46c0 nop ; (mov r8, r8)
80071b0: 687b ldr r3, [r7, #4]
80071b2: 681b ldr r3, [r3, #0]
80071b4: 681a ldr r2, [r3, #0]
80071b6: 687b ldr r3, [r7, #4]
80071b8: 681b ldr r3, [r3, #0]
80071ba: 495f ldr r1, [pc, #380] ; (8007338 <UART_RxISR_16BIT_FIFOEN+0x2d4>)
80071bc: 400a ands r2, r1
80071be: 601a str r2, [r3, #0]
80071c0: 6dfb ldr r3, [r7, #92] ; 0x5c
80071c2: 63bb str r3, [r7, #56] ; 0x38
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80071c4: 6bbb ldr r3, [r7, #56] ; 0x38
80071c6: f383 8810 msr PRIMASK, r3
}
80071ca: 46c0 nop ; (mov r8, r8)
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
80071cc: f3ef 8310 mrs r3, PRIMASK
80071d0: 63fb str r3, [r7, #60] ; 0x3c
return(result);
80071d2: 6bfb ldr r3, [r7, #60] ; 0x3c
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error)
and RX FIFO Threshold interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
80071d4: 65bb str r3, [r7, #88] ; 0x58
80071d6: 2301 movs r3, #1
80071d8: 643b str r3, [r7, #64] ; 0x40
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80071da: 6c3b ldr r3, [r7, #64] ; 0x40
80071dc: f383 8810 msr PRIMASK, r3
}
80071e0: 46c0 nop ; (mov r8, r8)
80071e2: 687b ldr r3, [r7, #4]
80071e4: 681b ldr r3, [r3, #0]
80071e6: 689a ldr r2, [r3, #8]
80071e8: 687b ldr r3, [r7, #4]
80071ea: 681b ldr r3, [r3, #0]
80071ec: 4953 ldr r1, [pc, #332] ; (800733c <UART_RxISR_16BIT_FIFOEN+0x2d8>)
80071ee: 400a ands r2, r1
80071f0: 609a str r2, [r3, #8]
80071f2: 6dbb ldr r3, [r7, #88] ; 0x58
80071f4: 647b str r3, [r7, #68] ; 0x44
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80071f6: 6c7b ldr r3, [r7, #68] ; 0x44
80071f8: f383 8810 msr PRIMASK, r3
}
80071fc: 46c0 nop ; (mov r8, r8)
/* Rx process is completed, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
80071fe: 687b ldr r3, [r7, #4]
8007200: 2288 movs r2, #136 ; 0x88
8007202: 2120 movs r1, #32
8007204: 5099 str r1, [r3, r2]
/* Clear RxISR function pointer */
huart->RxISR = NULL;
8007206: 687b ldr r3, [r7, #4]
8007208: 2200 movs r2, #0
800720a: 671a str r2, [r3, #112] ; 0x70
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
800720c: 687b ldr r3, [r7, #4]
800720e: 6edb ldr r3, [r3, #108] ; 0x6c
8007210: 2b01 cmp r3, #1
8007212: d12f bne.n 8007274 <UART_RxISR_16BIT_FIFOEN+0x210>
{
/* Set reception type to Standard */
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8007214: 687b ldr r3, [r7, #4]
8007216: 2200 movs r2, #0
8007218: 66da str r2, [r3, #108] ; 0x6c
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
800721a: f3ef 8310 mrs r3, PRIMASK
800721e: 627b str r3, [r7, #36] ; 0x24
return(result);
8007220: 6a7b ldr r3, [r7, #36] ; 0x24
/* Disable IDLE interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8007222: 657b str r3, [r7, #84] ; 0x54
8007224: 2301 movs r3, #1
8007226: 62bb str r3, [r7, #40] ; 0x28
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8007228: 6abb ldr r3, [r7, #40] ; 0x28
800722a: f383 8810 msr PRIMASK, r3
}
800722e: 46c0 nop ; (mov r8, r8)
8007230: 687b ldr r3, [r7, #4]
8007232: 681b ldr r3, [r3, #0]
8007234: 681a ldr r2, [r3, #0]
8007236: 687b ldr r3, [r7, #4]
8007238: 681b ldr r3, [r3, #0]
800723a: 2110 movs r1, #16
800723c: 438a bics r2, r1
800723e: 601a str r2, [r3, #0]
8007240: 6d7b ldr r3, [r7, #84] ; 0x54
8007242: 62fb str r3, [r7, #44] ; 0x2c
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8007244: 6afb ldr r3, [r7, #44] ; 0x2c
8007246: f383 8810 msr PRIMASK, r3
}
800724a: 46c0 nop ; (mov r8, r8)
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
800724c: 687b ldr r3, [r7, #4]
800724e: 681b ldr r3, [r3, #0]
8007250: 69db ldr r3, [r3, #28]
8007252: 2210 movs r2, #16
8007254: 4013 ands r3, r2
8007256: 2b10 cmp r3, #16
8007258: d103 bne.n 8007262 <UART_RxISR_16BIT_FIFOEN+0x1fe>
{
/* Clear IDLE Flag */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
800725a: 687b ldr r3, [r7, #4]
800725c: 681b ldr r3, [r3, #0]
800725e: 2210 movs r2, #16
8007260: 621a str r2, [r3, #32]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize);
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
8007262: 687b ldr r3, [r7, #4]
8007264: 225c movs r2, #92 ; 0x5c
8007266: 5a9a ldrh r2, [r3, r2]
8007268: 687b ldr r3, [r7, #4]
800726a: 0011 movs r1, r2
800726c: 0018 movs r0, r3
800726e: f7fe fd1d bl 8005cac <HAL_UARTEx_RxEventCallback>
8007272: e003 b.n 800727c <UART_RxISR_16BIT_FIFOEN+0x218>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx complete callback*/
huart->RxCpltCallback(huart);
#else
/*Call legacy weak Rx complete callback*/
HAL_UART_RxCpltCallback(huart);
8007274: 687b ldr r3, [r7, #4]
8007276: 0018 movs r0, r3
8007278: f7fa f8da bl 8001430 <HAL_UART_RxCpltCallback>
while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
800727c: 2366 movs r3, #102 ; 0x66
800727e: 18fb adds r3, r7, r3
8007280: 881b ldrh r3, [r3, #0]
8007282: 2b00 cmp r3, #0
8007284: d004 beq.n 8007290 <UART_RxISR_16BIT_FIFOEN+0x22c>
8007286: 6f7b ldr r3, [r7, #116] ; 0x74
8007288: 2220 movs r2, #32
800728a: 4013 ands r3, r2
800728c: d000 beq.n 8007290 <UART_RxISR_16BIT_FIFOEN+0x22c>
800728e: e70c b.n 80070aa <UART_RxISR_16BIT_FIFOEN+0x46>
/* When remaining number of bytes to receive is less than the RX FIFO
threshold, next incoming frames are processed as if FIFO mode was
disabled (i.e. one interrupt per received frame).
*/
rxdatacount = huart->RxXferCount;
8007290: 2052 movs r0, #82 ; 0x52
8007292: 183b adds r3, r7, r0
8007294: 687a ldr r2, [r7, #4]
8007296: 215e movs r1, #94 ; 0x5e
8007298: 5a52 ldrh r2, [r2, r1]
800729a: 801a strh r2, [r3, #0]
if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
800729c: 0001 movs r1, r0
800729e: 187b adds r3, r7, r1
80072a0: 881b ldrh r3, [r3, #0]
80072a2: 2b00 cmp r3, #0
80072a4: d044 beq.n 8007330 <UART_RxISR_16BIT_FIFOEN+0x2cc>
80072a6: 687b ldr r3, [r7, #4]
80072a8: 2268 movs r2, #104 ; 0x68
80072aa: 5a9b ldrh r3, [r3, r2]
80072ac: 187a adds r2, r7, r1
80072ae: 8812 ldrh r2, [r2, #0]
80072b0: 429a cmp r2, r3
80072b2: d23d bcs.n 8007330 <UART_RxISR_16BIT_FIFOEN+0x2cc>
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
80072b4: f3ef 8310 mrs r3, PRIMASK
80072b8: 60fb str r3, [r7, #12]
return(result);
80072ba: 68fb ldr r3, [r7, #12]
{
/* Disable the UART RXFT interrupt*/
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
80072bc: 64fb str r3, [r7, #76] ; 0x4c
80072be: 2301 movs r3, #1
80072c0: 613b str r3, [r7, #16]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80072c2: 693b ldr r3, [r7, #16]
80072c4: f383 8810 msr PRIMASK, r3
}
80072c8: 46c0 nop ; (mov r8, r8)
80072ca: 687b ldr r3, [r7, #4]
80072cc: 681b ldr r3, [r3, #0]
80072ce: 689a ldr r2, [r3, #8]
80072d0: 687b ldr r3, [r7, #4]
80072d2: 681b ldr r3, [r3, #0]
80072d4: 491a ldr r1, [pc, #104] ; (8007340 <UART_RxISR_16BIT_FIFOEN+0x2dc>)
80072d6: 400a ands r2, r1
80072d8: 609a str r2, [r3, #8]
80072da: 6cfb ldr r3, [r7, #76] ; 0x4c
80072dc: 617b str r3, [r7, #20]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80072de: 697b ldr r3, [r7, #20]
80072e0: f383 8810 msr PRIMASK, r3
}
80072e4: 46c0 nop ; (mov r8, r8)
/* Update the RxISR function pointer */
huart->RxISR = UART_RxISR_16BIT;
80072e6: 687b ldr r3, [r7, #4]
80072e8: 4a16 ldr r2, [pc, #88] ; (8007344 <UART_RxISR_16BIT_FIFOEN+0x2e0>)
80072ea: 671a str r2, [r3, #112] ; 0x70
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
80072ec: f3ef 8310 mrs r3, PRIMASK
80072f0: 61bb str r3, [r7, #24]
return(result);
80072f2: 69bb ldr r3, [r7, #24]
/* Enable the UART Data Register Not Empty interrupt */
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
80072f4: 64bb str r3, [r7, #72] ; 0x48
80072f6: 2301 movs r3, #1
80072f8: 61fb str r3, [r7, #28]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80072fa: 69fb ldr r3, [r7, #28]
80072fc: f383 8810 msr PRIMASK, r3
}
8007300: 46c0 nop ; (mov r8, r8)
8007302: 687b ldr r3, [r7, #4]
8007304: 681b ldr r3, [r3, #0]
8007306: 681a ldr r2, [r3, #0]
8007308: 687b ldr r3, [r7, #4]
800730a: 681b ldr r3, [r3, #0]
800730c: 2120 movs r1, #32
800730e: 430a orrs r2, r1
8007310: 601a str r2, [r3, #0]
8007312: 6cbb ldr r3, [r7, #72] ; 0x48
8007314: 623b str r3, [r7, #32]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8007316: 6a3b ldr r3, [r7, #32]
8007318: f383 8810 msr PRIMASK, r3
}
800731c: 46c0 nop ; (mov r8, r8)
else
{
/* Clear RXNE interrupt flag */
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
}
}
800731e: e007 b.n 8007330 <UART_RxISR_16BIT_FIFOEN+0x2cc>
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
8007320: 687b ldr r3, [r7, #4]
8007322: 681b ldr r3, [r3, #0]
8007324: 699a ldr r2, [r3, #24]
8007326: 687b ldr r3, [r7, #4]
8007328: 681b ldr r3, [r3, #0]
800732a: 2108 movs r1, #8
800732c: 430a orrs r2, r1
800732e: 619a str r2, [r3, #24]
}
8007330: 46c0 nop ; (mov r8, r8)
8007332: 46bd mov sp, r7
8007334: b01e add sp, #120 ; 0x78
8007336: bd80 pop {r7, pc}
8007338: fffffeff .word 0xfffffeff
800733c: effffffe .word 0xeffffffe
8007340: efffffff .word 0xefffffff
8007344: 08006c15 .word 0x08006c15
08007348 <HAL_UARTEx_WakeupCallback>:
* @brief UART wakeup from Stop mode callback.
* @param huart UART handle.
* @retval None
*/
__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
{
8007348: b580 push {r7, lr}
800734a: b082 sub sp, #8
800734c: af00 add r7, sp, #0
800734e: 6078 str r0, [r7, #4]
UNUSED(huart);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_UARTEx_WakeupCallback can be implemented in the user file.
*/
}
8007350: 46c0 nop ; (mov r8, r8)
8007352: 46bd mov sp, r7
8007354: b002 add sp, #8
8007356: bd80 pop {r7, pc}
08007358 <HAL_UARTEx_RxFifoFullCallback>:
* @brief UART RX Fifo full callback.
* @param huart UART handle.
* @retval None
*/
__weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart)
{
8007358: b580 push {r7, lr}
800735a: b082 sub sp, #8
800735c: af00 add r7, sp, #0
800735e: 6078 str r0, [r7, #4]
UNUSED(huart);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file.
*/
}
8007360: 46c0 nop ; (mov r8, r8)
8007362: 46bd mov sp, r7
8007364: b002 add sp, #8
8007366: bd80 pop {r7, pc}
08007368 <HAL_UARTEx_TxFifoEmptyCallback>:
* @brief UART TX Fifo empty callback.
* @param huart UART handle.
* @retval None
*/
__weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart)
{
8007368: b580 push {r7, lr}
800736a: b082 sub sp, #8
800736c: af00 add r7, sp, #0
800736e: 6078 str r0, [r7, #4]
UNUSED(huart);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file.
*/
}
8007370: 46c0 nop ; (mov r8, r8)
8007372: 46bd mov sp, r7
8007374: b002 add sp, #8
8007376: bd80 pop {r7, pc}
08007378 <__libc_init_array>:
8007378: b570 push {r4, r5, r6, lr}
800737a: 2600 movs r6, #0
800737c: 4d0c ldr r5, [pc, #48] ; (80073b0 <__libc_init_array+0x38>)
800737e: 4c0d ldr r4, [pc, #52] ; (80073b4 <__libc_init_array+0x3c>)
8007380: 1b64 subs r4, r4, r5
8007382: 10a4 asrs r4, r4, #2
8007384: 42a6 cmp r6, r4
8007386: d109 bne.n 800739c <__libc_init_array+0x24>
8007388: 2600 movs r6, #0
800738a: f000 f821 bl 80073d0 <_init>
800738e: 4d0a ldr r5, [pc, #40] ; (80073b8 <__libc_init_array+0x40>)
8007390: 4c0a ldr r4, [pc, #40] ; (80073bc <__libc_init_array+0x44>)
8007392: 1b64 subs r4, r4, r5
8007394: 10a4 asrs r4, r4, #2
8007396: 42a6 cmp r6, r4
8007398: d105 bne.n 80073a6 <__libc_init_array+0x2e>
800739a: bd70 pop {r4, r5, r6, pc}
800739c: 00b3 lsls r3, r6, #2
800739e: 58eb ldr r3, [r5, r3]
80073a0: 4798 blx r3
80073a2: 3601 adds r6, #1
80073a4: e7ee b.n 8007384 <__libc_init_array+0xc>
80073a6: 00b3 lsls r3, r6, #2
80073a8: 58eb ldr r3, [r5, r3]
80073aa: 4798 blx r3
80073ac: 3601 adds r6, #1
80073ae: e7f2 b.n 8007396 <__libc_init_array+0x1e>
80073b0: 080074bc .word 0x080074bc
80073b4: 080074bc .word 0x080074bc
80073b8: 080074bc .word 0x080074bc
80073bc: 080074c0 .word 0x080074c0
080073c0 <memset>:
80073c0: 0003 movs r3, r0
80073c2: 1882 adds r2, r0, r2
80073c4: 4293 cmp r3, r2
80073c6: d100 bne.n 80073ca <memset+0xa>
80073c8: 4770 bx lr
80073ca: 7019 strb r1, [r3, #0]
80073cc: 3301 adds r3, #1
80073ce: e7f9 b.n 80073c4 <memset+0x4>
080073d0 <_init>:
80073d0: b5f8 push {r3, r4, r5, r6, r7, lr}
80073d2: 46c0 nop ; (mov r8, r8)
80073d4: bcf8 pop {r3, r4, r5, r6, r7}
80073d6: bc08 pop {r3}
80073d8: 469e mov lr, r3
80073da: 4770 bx lr
080073dc <_fini>:
80073dc: b5f8 push {r3, r4, r5, r6, r7, lr}
80073de: 46c0 nop ; (mov r8, r8)
80073e0: bcf8 pop {r3, r4, r5, r6, r7}
80073e2: bc08 pop {r3}
80073e4: 469e mov lr, r3
80073e6: 4770 bx lr