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jiecang 推杆小板代码
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JC35W8/Debug/g031_JIECANG_JC35W8.list

21007 lines
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g031_JIECANG_JC35W8.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 000000bc 08000000 08000000 00010000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 00007314 080000bc 080000bc 000100bc 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 000000cc 080073d0 080073d0 000173d0 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 0800749c 0800749c 00020018 2**0
CONTENTS
4 .ARM 00000008 0800749c 0800749c 0001749c 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
5 .preinit_array 00000000 080074a4 080074a4 00020018 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 080074a4 080074a4 000174a4 2**2
CONTENTS, ALLOC, LOAD, DATA
7 .fini_array 00000004 080074a8 080074a8 000174a8 2**2
CONTENTS, ALLOC, LOAD, DATA
8 .data 00000018 20000000 080074ac 00020000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 00000438 20000018 080074c4 00020018 2**2
ALLOC
10 ._user_heap_stack 00000600 20000450 080074c4 00020450 2**0
ALLOC
11 .ARM.attributes 00000028 00000000 00000000 00020018 2**0
CONTENTS, READONLY
12 .debug_info 00016190 00000000 00000000 00020040 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_abbrev 000031fa 00000000 00000000 000361d0 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_aranges 00001260 00000000 00000000 000393d0 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_ranges 00001120 00000000 00000000 0003a630 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_macro 0001846e 00000000 00000000 0003b750 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_line 00016ff7 00000000 00000000 00053bbe 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_str 000998a1 00000000 00000000 0006abb5 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .comment 00000050 00000000 00000000 00104456 2**0
CONTENTS, READONLY
20 .debug_frame 00004160 00000000 00000000 001044a8 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
080000bc <__do_global_dtors_aux>:
80000bc: b510 push {r4, lr}
80000be: 4c06 ldr r4, [pc, #24] ; (80000d8 <__do_global_dtors_aux+0x1c>)
80000c0: 7823 ldrb r3, [r4, #0]
80000c2: 2b00 cmp r3, #0
80000c4: d107 bne.n 80000d6 <__do_global_dtors_aux+0x1a>
80000c6: 4b05 ldr r3, [pc, #20] ; (80000dc <__do_global_dtors_aux+0x20>)
80000c8: 2b00 cmp r3, #0
80000ca: d002 beq.n 80000d2 <__do_global_dtors_aux+0x16>
80000cc: 4804 ldr r0, [pc, #16] ; (80000e0 <__do_global_dtors_aux+0x24>)
80000ce: e000 b.n 80000d2 <__do_global_dtors_aux+0x16>
80000d0: bf00 nop
80000d2: 2301 movs r3, #1
80000d4: 7023 strb r3, [r4, #0]
80000d6: bd10 pop {r4, pc}
80000d8: 20000018 .word 0x20000018
80000dc: 00000000 .word 0x00000000
80000e0: 080073b8 .word 0x080073b8
080000e4 <frame_dummy>:
80000e4: 4b04 ldr r3, [pc, #16] ; (80000f8 <frame_dummy+0x14>)
80000e6: b510 push {r4, lr}
80000e8: 2b00 cmp r3, #0
80000ea: d003 beq.n 80000f4 <frame_dummy+0x10>
80000ec: 4903 ldr r1, [pc, #12] ; (80000fc <frame_dummy+0x18>)
80000ee: 4804 ldr r0, [pc, #16] ; (8000100 <frame_dummy+0x1c>)
80000f0: e000 b.n 80000f4 <frame_dummy+0x10>
80000f2: bf00 nop
80000f4: bd10 pop {r4, pc}
80000f6: 46c0 nop ; (mov r8, r8)
80000f8: 00000000 .word 0x00000000
80000fc: 2000001c .word 0x2000001c
8000100: 080073b8 .word 0x080073b8
08000104 <__udivsi3>:
8000104: 2200 movs r2, #0
8000106: 0843 lsrs r3, r0, #1
8000108: 428b cmp r3, r1
800010a: d374 bcc.n 80001f6 <__udivsi3+0xf2>
800010c: 0903 lsrs r3, r0, #4
800010e: 428b cmp r3, r1
8000110: d35f bcc.n 80001d2 <__udivsi3+0xce>
8000112: 0a03 lsrs r3, r0, #8
8000114: 428b cmp r3, r1
8000116: d344 bcc.n 80001a2 <__udivsi3+0x9e>
8000118: 0b03 lsrs r3, r0, #12
800011a: 428b cmp r3, r1
800011c: d328 bcc.n 8000170 <__udivsi3+0x6c>
800011e: 0c03 lsrs r3, r0, #16
8000120: 428b cmp r3, r1
8000122: d30d bcc.n 8000140 <__udivsi3+0x3c>
8000124: 22ff movs r2, #255 ; 0xff
8000126: 0209 lsls r1, r1, #8
8000128: ba12 rev r2, r2
800012a: 0c03 lsrs r3, r0, #16
800012c: 428b cmp r3, r1
800012e: d302 bcc.n 8000136 <__udivsi3+0x32>
8000130: 1212 asrs r2, r2, #8
8000132: 0209 lsls r1, r1, #8
8000134: d065 beq.n 8000202 <__udivsi3+0xfe>
8000136: 0b03 lsrs r3, r0, #12
8000138: 428b cmp r3, r1
800013a: d319 bcc.n 8000170 <__udivsi3+0x6c>
800013c: e000 b.n 8000140 <__udivsi3+0x3c>
800013e: 0a09 lsrs r1, r1, #8
8000140: 0bc3 lsrs r3, r0, #15
8000142: 428b cmp r3, r1
8000144: d301 bcc.n 800014a <__udivsi3+0x46>
8000146: 03cb lsls r3, r1, #15
8000148: 1ac0 subs r0, r0, r3
800014a: 4152 adcs r2, r2
800014c: 0b83 lsrs r3, r0, #14
800014e: 428b cmp r3, r1
8000150: d301 bcc.n 8000156 <__udivsi3+0x52>
8000152: 038b lsls r3, r1, #14
8000154: 1ac0 subs r0, r0, r3
8000156: 4152 adcs r2, r2
8000158: 0b43 lsrs r3, r0, #13
800015a: 428b cmp r3, r1
800015c: d301 bcc.n 8000162 <__udivsi3+0x5e>
800015e: 034b lsls r3, r1, #13
8000160: 1ac0 subs r0, r0, r3
8000162: 4152 adcs r2, r2
8000164: 0b03 lsrs r3, r0, #12
8000166: 428b cmp r3, r1
8000168: d301 bcc.n 800016e <__udivsi3+0x6a>
800016a: 030b lsls r3, r1, #12
800016c: 1ac0 subs r0, r0, r3
800016e: 4152 adcs r2, r2
8000170: 0ac3 lsrs r3, r0, #11
8000172: 428b cmp r3, r1
8000174: d301 bcc.n 800017a <__udivsi3+0x76>
8000176: 02cb lsls r3, r1, #11
8000178: 1ac0 subs r0, r0, r3
800017a: 4152 adcs r2, r2
800017c: 0a83 lsrs r3, r0, #10
800017e: 428b cmp r3, r1
8000180: d301 bcc.n 8000186 <__udivsi3+0x82>
8000182: 028b lsls r3, r1, #10
8000184: 1ac0 subs r0, r0, r3
8000186: 4152 adcs r2, r2
8000188: 0a43 lsrs r3, r0, #9
800018a: 428b cmp r3, r1
800018c: d301 bcc.n 8000192 <__udivsi3+0x8e>
800018e: 024b lsls r3, r1, #9
8000190: 1ac0 subs r0, r0, r3
8000192: 4152 adcs r2, r2
8000194: 0a03 lsrs r3, r0, #8
8000196: 428b cmp r3, r1
8000198: d301 bcc.n 800019e <__udivsi3+0x9a>
800019a: 020b lsls r3, r1, #8
800019c: 1ac0 subs r0, r0, r3
800019e: 4152 adcs r2, r2
80001a0: d2cd bcs.n 800013e <__udivsi3+0x3a>
80001a2: 09c3 lsrs r3, r0, #7
80001a4: 428b cmp r3, r1
80001a6: d301 bcc.n 80001ac <__udivsi3+0xa8>
80001a8: 01cb lsls r3, r1, #7
80001aa: 1ac0 subs r0, r0, r3
80001ac: 4152 adcs r2, r2
80001ae: 0983 lsrs r3, r0, #6
80001b0: 428b cmp r3, r1
80001b2: d301 bcc.n 80001b8 <__udivsi3+0xb4>
80001b4: 018b lsls r3, r1, #6
80001b6: 1ac0 subs r0, r0, r3
80001b8: 4152 adcs r2, r2
80001ba: 0943 lsrs r3, r0, #5
80001bc: 428b cmp r3, r1
80001be: d301 bcc.n 80001c4 <__udivsi3+0xc0>
80001c0: 014b lsls r3, r1, #5
80001c2: 1ac0 subs r0, r0, r3
80001c4: 4152 adcs r2, r2
80001c6: 0903 lsrs r3, r0, #4
80001c8: 428b cmp r3, r1
80001ca: d301 bcc.n 80001d0 <__udivsi3+0xcc>
80001cc: 010b lsls r3, r1, #4
80001ce: 1ac0 subs r0, r0, r3
80001d0: 4152 adcs r2, r2
80001d2: 08c3 lsrs r3, r0, #3
80001d4: 428b cmp r3, r1
80001d6: d301 bcc.n 80001dc <__udivsi3+0xd8>
80001d8: 00cb lsls r3, r1, #3
80001da: 1ac0 subs r0, r0, r3
80001dc: 4152 adcs r2, r2
80001de: 0883 lsrs r3, r0, #2
80001e0: 428b cmp r3, r1
80001e2: d301 bcc.n 80001e8 <__udivsi3+0xe4>
80001e4: 008b lsls r3, r1, #2
80001e6: 1ac0 subs r0, r0, r3
80001e8: 4152 adcs r2, r2
80001ea: 0843 lsrs r3, r0, #1
80001ec: 428b cmp r3, r1
80001ee: d301 bcc.n 80001f4 <__udivsi3+0xf0>
80001f0: 004b lsls r3, r1, #1
80001f2: 1ac0 subs r0, r0, r3
80001f4: 4152 adcs r2, r2
80001f6: 1a41 subs r1, r0, r1
80001f8: d200 bcs.n 80001fc <__udivsi3+0xf8>
80001fa: 4601 mov r1, r0
80001fc: 4152 adcs r2, r2
80001fe: 4610 mov r0, r2
8000200: 4770 bx lr
8000202: e7ff b.n 8000204 <__udivsi3+0x100>
8000204: b501 push {r0, lr}
8000206: 2000 movs r0, #0
8000208: f000 f806 bl 8000218 <__aeabi_idiv0>
800020c: bd02 pop {r1, pc}
800020e: 46c0 nop ; (mov r8, r8)
08000210 <__aeabi_uidivmod>:
8000210: 2900 cmp r1, #0
8000212: d0f7 beq.n 8000204 <__udivsi3+0x100>
8000214: e776 b.n 8000104 <__udivsi3>
8000216: 4770 bx lr
08000218 <__aeabi_idiv0>:
8000218: 4770 bx lr
800021a: 46c0 nop ; (mov r8, r8)
0800021c <__aeabi_uldivmod>:
800021c: 2b00 cmp r3, #0
800021e: d111 bne.n 8000244 <__aeabi_uldivmod+0x28>
8000220: 2a00 cmp r2, #0
8000222: d10f bne.n 8000244 <__aeabi_uldivmod+0x28>
8000224: 2900 cmp r1, #0
8000226: d100 bne.n 800022a <__aeabi_uldivmod+0xe>
8000228: 2800 cmp r0, #0
800022a: d002 beq.n 8000232 <__aeabi_uldivmod+0x16>
800022c: 2100 movs r1, #0
800022e: 43c9 mvns r1, r1
8000230: 0008 movs r0, r1
8000232: b407 push {r0, r1, r2}
8000234: 4802 ldr r0, [pc, #8] ; (8000240 <__aeabi_uldivmod+0x24>)
8000236: a102 add r1, pc, #8 ; (adr r1, 8000240 <__aeabi_uldivmod+0x24>)
8000238: 1840 adds r0, r0, r1
800023a: 9002 str r0, [sp, #8]
800023c: bd03 pop {r0, r1, pc}
800023e: 46c0 nop ; (mov r8, r8)
8000240: ffffffd9 .word 0xffffffd9
8000244: b403 push {r0, r1}
8000246: 4668 mov r0, sp
8000248: b501 push {r0, lr}
800024a: 9802 ldr r0, [sp, #8]
800024c: f000 f806 bl 800025c <__udivmoddi4>
8000250: 9b01 ldr r3, [sp, #4]
8000252: 469e mov lr, r3
8000254: b002 add sp, #8
8000256: bc0c pop {r2, r3}
8000258: 4770 bx lr
800025a: 46c0 nop ; (mov r8, r8)
0800025c <__udivmoddi4>:
800025c: b5f0 push {r4, r5, r6, r7, lr}
800025e: 4657 mov r7, sl
8000260: 464e mov r6, r9
8000262: 4645 mov r5, r8
8000264: 46de mov lr, fp
8000266: b5e0 push {r5, r6, r7, lr}
8000268: 0004 movs r4, r0
800026a: 000d movs r5, r1
800026c: 4692 mov sl, r2
800026e: 4699 mov r9, r3
8000270: b083 sub sp, #12
8000272: 428b cmp r3, r1
8000274: d830 bhi.n 80002d8 <__udivmoddi4+0x7c>
8000276: d02d beq.n 80002d4 <__udivmoddi4+0x78>
8000278: 4649 mov r1, r9
800027a: 4650 mov r0, sl
800027c: f000 f8ba bl 80003f4 <__clzdi2>
8000280: 0029 movs r1, r5
8000282: 0006 movs r6, r0
8000284: 0020 movs r0, r4
8000286: f000 f8b5 bl 80003f4 <__clzdi2>
800028a: 1a33 subs r3, r6, r0
800028c: 4698 mov r8, r3
800028e: 3b20 subs r3, #32
8000290: 469b mov fp, r3
8000292: d433 bmi.n 80002fc <__udivmoddi4+0xa0>
8000294: 465a mov r2, fp
8000296: 4653 mov r3, sl
8000298: 4093 lsls r3, r2
800029a: 4642 mov r2, r8
800029c: 001f movs r7, r3
800029e: 4653 mov r3, sl
80002a0: 4093 lsls r3, r2
80002a2: 001e movs r6, r3
80002a4: 42af cmp r7, r5
80002a6: d83a bhi.n 800031e <__udivmoddi4+0xc2>
80002a8: 42af cmp r7, r5
80002aa: d100 bne.n 80002ae <__udivmoddi4+0x52>
80002ac: e078 b.n 80003a0 <__udivmoddi4+0x144>
80002ae: 465b mov r3, fp
80002b0: 1ba4 subs r4, r4, r6
80002b2: 41bd sbcs r5, r7
80002b4: 2b00 cmp r3, #0
80002b6: da00 bge.n 80002ba <__udivmoddi4+0x5e>
80002b8: e075 b.n 80003a6 <__udivmoddi4+0x14a>
80002ba: 2200 movs r2, #0
80002bc: 2300 movs r3, #0
80002be: 9200 str r2, [sp, #0]
80002c0: 9301 str r3, [sp, #4]
80002c2: 2301 movs r3, #1
80002c4: 465a mov r2, fp
80002c6: 4093 lsls r3, r2
80002c8: 9301 str r3, [sp, #4]
80002ca: 2301 movs r3, #1
80002cc: 4642 mov r2, r8
80002ce: 4093 lsls r3, r2
80002d0: 9300 str r3, [sp, #0]
80002d2: e028 b.n 8000326 <__udivmoddi4+0xca>
80002d4: 4282 cmp r2, r0
80002d6: d9cf bls.n 8000278 <__udivmoddi4+0x1c>
80002d8: 2200 movs r2, #0
80002da: 2300 movs r3, #0
80002dc: 9200 str r2, [sp, #0]
80002de: 9301 str r3, [sp, #4]
80002e0: 9b0c ldr r3, [sp, #48] ; 0x30
80002e2: 2b00 cmp r3, #0
80002e4: d001 beq.n 80002ea <__udivmoddi4+0x8e>
80002e6: 601c str r4, [r3, #0]
80002e8: 605d str r5, [r3, #4]
80002ea: 9800 ldr r0, [sp, #0]
80002ec: 9901 ldr r1, [sp, #4]
80002ee: b003 add sp, #12
80002f0: bcf0 pop {r4, r5, r6, r7}
80002f2: 46bb mov fp, r7
80002f4: 46b2 mov sl, r6
80002f6: 46a9 mov r9, r5
80002f8: 46a0 mov r8, r4
80002fa: bdf0 pop {r4, r5, r6, r7, pc}
80002fc: 4642 mov r2, r8
80002fe: 2320 movs r3, #32
8000300: 1a9b subs r3, r3, r2
8000302: 4652 mov r2, sl
8000304: 40da lsrs r2, r3
8000306: 4641 mov r1, r8
8000308: 0013 movs r3, r2
800030a: 464a mov r2, r9
800030c: 408a lsls r2, r1
800030e: 0017 movs r7, r2
8000310: 4642 mov r2, r8
8000312: 431f orrs r7, r3
8000314: 4653 mov r3, sl
8000316: 4093 lsls r3, r2
8000318: 001e movs r6, r3
800031a: 42af cmp r7, r5
800031c: d9c4 bls.n 80002a8 <__udivmoddi4+0x4c>
800031e: 2200 movs r2, #0
8000320: 2300 movs r3, #0
8000322: 9200 str r2, [sp, #0]
8000324: 9301 str r3, [sp, #4]
8000326: 4643 mov r3, r8
8000328: 2b00 cmp r3, #0
800032a: d0d9 beq.n 80002e0 <__udivmoddi4+0x84>
800032c: 07fb lsls r3, r7, #31
800032e: 0872 lsrs r2, r6, #1
8000330: 431a orrs r2, r3
8000332: 4646 mov r6, r8
8000334: 087b lsrs r3, r7, #1
8000336: e00e b.n 8000356 <__udivmoddi4+0xfa>
8000338: 42ab cmp r3, r5
800033a: d101 bne.n 8000340 <__udivmoddi4+0xe4>
800033c: 42a2 cmp r2, r4
800033e: d80c bhi.n 800035a <__udivmoddi4+0xfe>
8000340: 1aa4 subs r4, r4, r2
8000342: 419d sbcs r5, r3
8000344: 2001 movs r0, #1
8000346: 1924 adds r4, r4, r4
8000348: 416d adcs r5, r5
800034a: 2100 movs r1, #0
800034c: 3e01 subs r6, #1
800034e: 1824 adds r4, r4, r0
8000350: 414d adcs r5, r1
8000352: 2e00 cmp r6, #0
8000354: d006 beq.n 8000364 <__udivmoddi4+0x108>
8000356: 42ab cmp r3, r5
8000358: d9ee bls.n 8000338 <__udivmoddi4+0xdc>
800035a: 3e01 subs r6, #1
800035c: 1924 adds r4, r4, r4
800035e: 416d adcs r5, r5
8000360: 2e00 cmp r6, #0
8000362: d1f8 bne.n 8000356 <__udivmoddi4+0xfa>
8000364: 9800 ldr r0, [sp, #0]
8000366: 9901 ldr r1, [sp, #4]
8000368: 465b mov r3, fp
800036a: 1900 adds r0, r0, r4
800036c: 4169 adcs r1, r5
800036e: 2b00 cmp r3, #0
8000370: db24 blt.n 80003bc <__udivmoddi4+0x160>
8000372: 002b movs r3, r5
8000374: 465a mov r2, fp
8000376: 4644 mov r4, r8
8000378: 40d3 lsrs r3, r2
800037a: 002a movs r2, r5
800037c: 40e2 lsrs r2, r4
800037e: 001c movs r4, r3
8000380: 465b mov r3, fp
8000382: 0015 movs r5, r2
8000384: 2b00 cmp r3, #0
8000386: db2a blt.n 80003de <__udivmoddi4+0x182>
8000388: 0026 movs r6, r4
800038a: 409e lsls r6, r3
800038c: 0033 movs r3, r6
800038e: 0026 movs r6, r4
8000390: 4647 mov r7, r8
8000392: 40be lsls r6, r7
8000394: 0032 movs r2, r6
8000396: 1a80 subs r0, r0, r2
8000398: 4199 sbcs r1, r3
800039a: 9000 str r0, [sp, #0]
800039c: 9101 str r1, [sp, #4]
800039e: e79f b.n 80002e0 <__udivmoddi4+0x84>
80003a0: 42a3 cmp r3, r4
80003a2: d8bc bhi.n 800031e <__udivmoddi4+0xc2>
80003a4: e783 b.n 80002ae <__udivmoddi4+0x52>
80003a6: 4642 mov r2, r8
80003a8: 2320 movs r3, #32
80003aa: 2100 movs r1, #0
80003ac: 1a9b subs r3, r3, r2
80003ae: 2200 movs r2, #0
80003b0: 9100 str r1, [sp, #0]
80003b2: 9201 str r2, [sp, #4]
80003b4: 2201 movs r2, #1
80003b6: 40da lsrs r2, r3
80003b8: 9201 str r2, [sp, #4]
80003ba: e786 b.n 80002ca <__udivmoddi4+0x6e>
80003bc: 4642 mov r2, r8
80003be: 2320 movs r3, #32
80003c0: 1a9b subs r3, r3, r2
80003c2: 002a movs r2, r5
80003c4: 4646 mov r6, r8
80003c6: 409a lsls r2, r3
80003c8: 0023 movs r3, r4
80003ca: 40f3 lsrs r3, r6
80003cc: 4644 mov r4, r8
80003ce: 4313 orrs r3, r2
80003d0: 002a movs r2, r5
80003d2: 40e2 lsrs r2, r4
80003d4: 001c movs r4, r3
80003d6: 465b mov r3, fp
80003d8: 0015 movs r5, r2
80003da: 2b00 cmp r3, #0
80003dc: dad4 bge.n 8000388 <__udivmoddi4+0x12c>
80003de: 4642 mov r2, r8
80003e0: 002f movs r7, r5
80003e2: 2320 movs r3, #32
80003e4: 0026 movs r6, r4
80003e6: 4097 lsls r7, r2
80003e8: 1a9b subs r3, r3, r2
80003ea: 40de lsrs r6, r3
80003ec: 003b movs r3, r7
80003ee: 4333 orrs r3, r6
80003f0: e7cd b.n 800038e <__udivmoddi4+0x132>
80003f2: 46c0 nop ; (mov r8, r8)
080003f4 <__clzdi2>:
80003f4: b510 push {r4, lr}
80003f6: 2900 cmp r1, #0
80003f8: d103 bne.n 8000402 <__clzdi2+0xe>
80003fa: f000 f807 bl 800040c <__clzsi2>
80003fe: 3020 adds r0, #32
8000400: e002 b.n 8000408 <__clzdi2+0x14>
8000402: 0008 movs r0, r1
8000404: f000 f802 bl 800040c <__clzsi2>
8000408: bd10 pop {r4, pc}
800040a: 46c0 nop ; (mov r8, r8)
0800040c <__clzsi2>:
800040c: 211c movs r1, #28
800040e: 2301 movs r3, #1
8000410: 041b lsls r3, r3, #16
8000412: 4298 cmp r0, r3
8000414: d301 bcc.n 800041a <__clzsi2+0xe>
8000416: 0c00 lsrs r0, r0, #16
8000418: 3910 subs r1, #16
800041a: 0a1b lsrs r3, r3, #8
800041c: 4298 cmp r0, r3
800041e: d301 bcc.n 8000424 <__clzsi2+0x18>
8000420: 0a00 lsrs r0, r0, #8
8000422: 3908 subs r1, #8
8000424: 091b lsrs r3, r3, #4
8000426: 4298 cmp r0, r3
8000428: d301 bcc.n 800042e <__clzsi2+0x22>
800042a: 0900 lsrs r0, r0, #4
800042c: 3904 subs r1, #4
800042e: a202 add r2, pc, #8 ; (adr r2, 8000438 <__clzsi2+0x2c>)
8000430: 5c10 ldrb r0, [r2, r0]
8000432: 1840 adds r0, r0, r1
8000434: 4770 bx lr
8000436: 46c0 nop ; (mov r8, r8)
8000438: 02020304 .word 0x02020304
800043c: 01010101 .word 0x01010101
...
08000448 <MX_ADC1_Init>:
ADC_HandleTypeDef hadc1;
/* ADC1 init function */
void MX_ADC1_Init(void)
{
8000448: b580 push {r7, lr}
800044a: b084 sub sp, #16
800044c: af00 add r7, sp, #0
/* USER CODE BEGIN ADC1_Init 0 */
/* USER CODE END ADC1_Init 0 */
ADC_ChannelConfTypeDef sConfig = {0};
800044e: 1d3b adds r3, r7, #4
8000450: 0018 movs r0, r3
8000452: 230c movs r3, #12
8000454: 001a movs r2, r3
8000456: 2100 movs r1, #0
8000458: f006 ffa6 bl 80073a8 <memset>
/* USER CODE END ADC1_Init 1 */
/** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion)
*/
hadc1.Instance = ADC1;
800045c: 4b2b ldr r3, [pc, #172] ; (800050c <MX_ADC1_Init+0xc4>)
800045e: 4a2c ldr r2, [pc, #176] ; (8000510 <MX_ADC1_Init+0xc8>)
8000460: 601a str r2, [r3, #0]
hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4;
8000462: 4b2a ldr r3, [pc, #168] ; (800050c <MX_ADC1_Init+0xc4>)
8000464: 2280 movs r2, #128 ; 0x80
8000466: 0612 lsls r2, r2, #24
8000468: 605a str r2, [r3, #4]
hadc1.Init.Resolution = ADC_RESOLUTION_12B;
800046a: 4b28 ldr r3, [pc, #160] ; (800050c <MX_ADC1_Init+0xc4>)
800046c: 2200 movs r2, #0
800046e: 609a str r2, [r3, #8]
hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
8000470: 4b26 ldr r3, [pc, #152] ; (800050c <MX_ADC1_Init+0xc4>)
8000472: 2200 movs r2, #0
8000474: 60da str r2, [r3, #12]
hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;
8000476: 4b25 ldr r3, [pc, #148] ; (800050c <MX_ADC1_Init+0xc4>)
8000478: 2200 movs r2, #0
800047a: 611a str r2, [r3, #16]
hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
800047c: 4b23 ldr r3, [pc, #140] ; (800050c <MX_ADC1_Init+0xc4>)
800047e: 2204 movs r2, #4
8000480: 615a str r2, [r3, #20]
hadc1.Init.LowPowerAutoWait = DISABLE;
8000482: 4b22 ldr r3, [pc, #136] ; (800050c <MX_ADC1_Init+0xc4>)
8000484: 2200 movs r2, #0
8000486: 761a strb r2, [r3, #24]
hadc1.Init.LowPowerAutoPowerOff = DISABLE;
8000488: 4b20 ldr r3, [pc, #128] ; (800050c <MX_ADC1_Init+0xc4>)
800048a: 2200 movs r2, #0
800048c: 765a strb r2, [r3, #25]
hadc1.Init.ContinuousConvMode = DISABLE;
800048e: 4b1f ldr r3, [pc, #124] ; (800050c <MX_ADC1_Init+0xc4>)
8000490: 2200 movs r2, #0
8000492: 769a strb r2, [r3, #26]
hadc1.Init.NbrOfConversion = 1;
8000494: 4b1d ldr r3, [pc, #116] ; (800050c <MX_ADC1_Init+0xc4>)
8000496: 2201 movs r2, #1
8000498: 61da str r2, [r3, #28]
hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
800049a: 4b1c ldr r3, [pc, #112] ; (800050c <MX_ADC1_Init+0xc4>)
800049c: 2200 movs r2, #0
800049e: 625a str r2, [r3, #36] ; 0x24
hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
80004a0: 4b1a ldr r3, [pc, #104] ; (800050c <MX_ADC1_Init+0xc4>)
80004a2: 2200 movs r2, #0
80004a4: 629a str r2, [r3, #40] ; 0x28
hadc1.Init.DMAContinuousRequests = DISABLE;
80004a6: 4b19 ldr r3, [pc, #100] ; (800050c <MX_ADC1_Init+0xc4>)
80004a8: 222c movs r2, #44 ; 0x2c
80004aa: 2100 movs r1, #0
80004ac: 5499 strb r1, [r3, r2]
hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED;
80004ae: 4b17 ldr r3, [pc, #92] ; (800050c <MX_ADC1_Init+0xc4>)
80004b0: 2200 movs r2, #0
80004b2: 631a str r2, [r3, #48] ; 0x30
hadc1.Init.SamplingTimeCommon1 = ADC_SAMPLETIME_19CYCLES_5;
80004b4: 4b15 ldr r3, [pc, #84] ; (800050c <MX_ADC1_Init+0xc4>)
80004b6: 2204 movs r2, #4
80004b8: 635a str r2, [r3, #52] ; 0x34
hadc1.Init.SamplingTimeCommon2 = ADC_SAMPLETIME_19CYCLES_5;
80004ba: 4b14 ldr r3, [pc, #80] ; (800050c <MX_ADC1_Init+0xc4>)
80004bc: 2204 movs r2, #4
80004be: 639a str r2, [r3, #56] ; 0x38
hadc1.Init.OversamplingMode = DISABLE;
80004c0: 4b12 ldr r3, [pc, #72] ; (800050c <MX_ADC1_Init+0xc4>)
80004c2: 223c movs r2, #60 ; 0x3c
80004c4: 2100 movs r1, #0
80004c6: 5499 strb r1, [r3, r2]
hadc1.Init.TriggerFrequencyMode = ADC_TRIGGER_FREQ_HIGH;
80004c8: 4b10 ldr r3, [pc, #64] ; (800050c <MX_ADC1_Init+0xc4>)
80004ca: 2200 movs r2, #0
80004cc: 64da str r2, [r3, #76] ; 0x4c
if (HAL_ADC_Init(&hadc1) != HAL_OK)
80004ce: 4b0f ldr r3, [pc, #60] ; (800050c <MX_ADC1_Init+0xc4>)
80004d0: 0018 movs r0, r3
80004d2: f001 fca9 bl 8001e28 <HAL_ADC_Init>
80004d6: 1e03 subs r3, r0, #0
80004d8: d001 beq.n 80004de <MX_ADC1_Init+0x96>
{
Error_Handler();
80004da: f000 fb82 bl 8000be2 <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_5;
80004de: 1d3b adds r3, r7, #4
80004e0: 4a0c ldr r2, [pc, #48] ; (8000514 <MX_ADC1_Init+0xcc>)
80004e2: 601a str r2, [r3, #0]
sConfig.Rank = ADC_REGULAR_RANK_1;
80004e4: 1d3b adds r3, r7, #4
80004e6: 2200 movs r2, #0
80004e8: 605a str r2, [r3, #4]
sConfig.SamplingTime = ADC_SAMPLINGTIME_COMMON_1;
80004ea: 1d3b adds r3, r7, #4
80004ec: 2200 movs r2, #0
80004ee: 609a str r2, [r3, #8]
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
80004f0: 1d3a adds r2, r7, #4
80004f2: 4b06 ldr r3, [pc, #24] ; (800050c <MX_ADC1_Init+0xc4>)
80004f4: 0011 movs r1, r2
80004f6: 0018 movs r0, r3
80004f8: f001 ffea bl 80024d0 <HAL_ADC_ConfigChannel>
80004fc: 1e03 subs r3, r0, #0
80004fe: d001 beq.n 8000504 <MX_ADC1_Init+0xbc>
{
Error_Handler();
8000500: f000 fb6f bl 8000be2 <Error_Handler>
}
/* USER CODE BEGIN ADC1_Init 2 */
/* USER CODE END ADC1_Init 2 */
}
8000504: 46c0 nop ; (mov r8, r8)
8000506: 46bd mov sp, r7
8000508: b004 add sp, #16
800050a: bd80 pop {r7, pc}
800050c: 20000034 .word 0x20000034
8000510: 40012400 .word 0x40012400
8000514: 14000020 .word 0x14000020
08000518 <HAL_ADC_MspInit>:
void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle)
{
8000518: b590 push {r4, r7, lr}
800051a: b095 sub sp, #84 ; 0x54
800051c: af00 add r7, sp, #0
800051e: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000520: 233c movs r3, #60 ; 0x3c
8000522: 18fb adds r3, r7, r3
8000524: 0018 movs r0, r3
8000526: 2314 movs r3, #20
8000528: 001a movs r2, r3
800052a: 2100 movs r1, #0
800052c: f006 ff3c bl 80073a8 <memset>
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
8000530: 2414 movs r4, #20
8000532: 193b adds r3, r7, r4
8000534: 0018 movs r0, r3
8000536: 2328 movs r3, #40 ; 0x28
8000538: 001a movs r2, r3
800053a: 2100 movs r1, #0
800053c: f006 ff34 bl 80073a8 <memset>
if(adcHandle->Instance==ADC1)
8000540: 687b ldr r3, [r7, #4]
8000542: 681b ldr r3, [r3, #0]
8000544: 4a24 ldr r2, [pc, #144] ; (80005d8 <HAL_ADC_MspInit+0xc0>)
8000546: 4293 cmp r3, r2
8000548: d141 bne.n 80005ce <HAL_ADC_MspInit+0xb6>
/* USER CODE END ADC1_MspInit 0 */
/** Initializes the peripherals clocks
*/
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
800054a: 193b adds r3, r7, r4
800054c: 2280 movs r2, #128 ; 0x80
800054e: 01d2 lsls r2, r2, #7
8000550: 601a str r2, [r3, #0]
PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_SYSCLK;
8000552: 193b adds r3, r7, r4
8000554: 2200 movs r2, #0
8000556: 61da str r2, [r3, #28]
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
8000558: 193b adds r3, r7, r4
800055a: 0018 movs r0, r3
800055c: f003 fe78 bl 8004250 <HAL_RCCEx_PeriphCLKConfig>
8000560: 1e03 subs r3, r0, #0
8000562: d001 beq.n 8000568 <HAL_ADC_MspInit+0x50>
{
Error_Handler();
8000564: f000 fb3d bl 8000be2 <Error_Handler>
}
/* ADC1 clock enable */
__HAL_RCC_ADC_CLK_ENABLE();
8000568: 4b1c ldr r3, [pc, #112] ; (80005dc <HAL_ADC_MspInit+0xc4>)
800056a: 6c1a ldr r2, [r3, #64] ; 0x40
800056c: 4b1b ldr r3, [pc, #108] ; (80005dc <HAL_ADC_MspInit+0xc4>)
800056e: 2180 movs r1, #128 ; 0x80
8000570: 0349 lsls r1, r1, #13
8000572: 430a orrs r2, r1
8000574: 641a str r2, [r3, #64] ; 0x40
8000576: 4b19 ldr r3, [pc, #100] ; (80005dc <HAL_ADC_MspInit+0xc4>)
8000578: 6c1a ldr r2, [r3, #64] ; 0x40
800057a: 2380 movs r3, #128 ; 0x80
800057c: 035b lsls r3, r3, #13
800057e: 4013 ands r3, r2
8000580: 613b str r3, [r7, #16]
8000582: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
8000584: 4b15 ldr r3, [pc, #84] ; (80005dc <HAL_ADC_MspInit+0xc4>)
8000586: 6b5a ldr r2, [r3, #52] ; 0x34
8000588: 4b14 ldr r3, [pc, #80] ; (80005dc <HAL_ADC_MspInit+0xc4>)
800058a: 2101 movs r1, #1
800058c: 430a orrs r2, r1
800058e: 635a str r2, [r3, #52] ; 0x34
8000590: 4b12 ldr r3, [pc, #72] ; (80005dc <HAL_ADC_MspInit+0xc4>)
8000592: 6b5b ldr r3, [r3, #52] ; 0x34
8000594: 2201 movs r2, #1
8000596: 4013 ands r3, r2
8000598: 60fb str r3, [r7, #12]
800059a: 68fb ldr r3, [r7, #12]
/**ADC1 GPIO Configuration
PA5 ------> ADC1_IN5
*/
GPIO_InitStruct.Pin = GPIO_PIN_5;
800059c: 213c movs r1, #60 ; 0x3c
800059e: 187b adds r3, r7, r1
80005a0: 2220 movs r2, #32
80005a2: 601a str r2, [r3, #0]
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
80005a4: 187b adds r3, r7, r1
80005a6: 2203 movs r2, #3
80005a8: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80005aa: 187b adds r3, r7, r1
80005ac: 2200 movs r2, #0
80005ae: 609a str r2, [r3, #8]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
80005b0: 187a adds r2, r7, r1
80005b2: 23a0 movs r3, #160 ; 0xa0
80005b4: 05db lsls r3, r3, #23
80005b6: 0011 movs r1, r2
80005b8: 0018 movs r0, r3
80005ba: f002 ffb7 bl 800352c <HAL_GPIO_Init>
/* ADC1 interrupt Init */
HAL_NVIC_SetPriority(ADC1_IRQn, 0, 0);
80005be: 2200 movs r2, #0
80005c0: 2100 movs r1, #0
80005c2: 200c movs r0, #12
80005c4: f002 fc62 bl 8002e8c <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(ADC1_IRQn);
80005c8: 200c movs r0, #12
80005ca: f002 fc74 bl 8002eb6 <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN ADC1_MspInit 1 */
/* USER CODE END ADC1_MspInit 1 */
}
}
80005ce: 46c0 nop ; (mov r8, r8)
80005d0: 46bd mov sp, r7
80005d2: b015 add sp, #84 ; 0x54
80005d4: bd90 pop {r4, r7, pc}
80005d6: 46c0 nop ; (mov r8, r8)
80005d8: 40012400 .word 0x40012400
80005dc: 40021000 .word 0x40021000
080005e0 <App_Init>:
static void App_UpdateEncoderRegister(void);
static void App_ProcessZeroCommand(void);
static void App_UpdateLed(void);
void App_Init(void)
{
80005e0: b580 push {r7, lr}
80005e2: af00 add r7, sp, #0
/* 上电默认：电机停止 */
HAL_GPIO_WritePin(IO_1_GPIO_Port, IO_1_Pin, GPIO_PIN_RESET);
80005e4: 4b1d ldr r3, [pc, #116] ; (800065c <App_Init+0x7c>)
80005e6: 2200 movs r2, #0
80005e8: 2101 movs r1, #1
80005ea: 0018 movs r0, r3
80005ec: f003 f902 bl 80037f4 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(IO_2_GPIO_Port, IO_2_Pin, GPIO_PIN_RESET);
80005f0: 23a0 movs r3, #160 ; 0xa0
80005f2: 05db lsls r3, r3, #23
80005f4: 2200 movs r2, #0
80005f6: 2180 movs r1, #128 ; 0x80
80005f8: 0018 movs r0, r3
80005fa: f003 f8fb bl 80037f4 <HAL_GPIO_WritePin>
/* 状态灯初始熄灭 */
HAL_GPIO_WritePin(LED_GPIO_Port, LED_Pin, GPIO_PIN_RESET);
80005fe: 2380 movs r3, #128 ; 0x80
8000600: 005b lsls r3, r3, #1
8000602: 4816 ldr r0, [pc, #88] ; (800065c <App_Init+0x7c>)
8000604: 2200 movs r2, #0
8000606: 0019 movs r1, r3
8000608: f003 f8f4 bl 80037f4 <HAL_GPIO_WritePin>
/* 启动编码器读取 */
HAL_TIM_Encoder_Start(&htim2, TIM_CHANNEL_ALL);
800060c: 4b14 ldr r3, [pc, #80] ; (8000660 <App_Init+0x80>)
800060e: 213c movs r1, #60 ; 0x3c
8000610: 0018 movs r0, r3
8000612: f004 f975 bl 8004900 <HAL_TIM_Encoder_Start>
/* 启动 PWM 输出，并按当前寄存器值设置电流限幅占空比 */
HAL_TIM_PWM_Start(&htim3, TIM_CHANNEL_1);
8000616: 4b13 ldr r3, [pc, #76] ; (8000664 <App_Init+0x84>)
8000618: 2100 movs r1, #0
800061a: 0018 movs r0, r3
800061c: f003 ffea bl 80045f4 <HAL_TIM_PWM_Start>
App_SetCurrentLimit(holdingRegisters[3]);
8000620: 4b11 ldr r3, [pc, #68] ; (8000668 <App_Init+0x88>)
8000622: 2206 movs r2, #6
8000624: 5e9b ldrsh r3, [r3, r2]
8000626: b29b uxth r3, r3
8000628: 0018 movs r0, r3
800062a: f000 f8fb bl 8000824 <App_SetCurrentLimit>
/* ADC校准 */
if (HAL_ADCEx_Calibration_Start(&hadc1) != HAL_OK)
800062e: 4b0f ldr r3, [pc, #60] ; (800066c <App_Init+0x8c>)
8000630: 0018 movs r0, r3
8000632: f002 fa89 bl 8002b48 <HAL_ADCEx_Calibration_Start>
8000636: 1e03 subs r3, r0, #0
8000638: d001 beq.n 800063e <App_Init+0x5e>
{
Error_Handler();
800063a: f000 fad2 bl 8000be2 <Error_Handler>
}
/* 启动 ADC 中断采集 */
adcConversionDone = 0;
800063e: 4b0c ldr r3, [pc, #48] ; (8000670 <App_Init+0x90>)
8000640: 2200 movs r2, #0
8000642: 701a strb r2, [r3, #0]
if (HAL_ADC_Start_IT(&hadc1) != HAL_OK)
8000644: 4b09 ldr r3, [pc, #36] ; (800066c <App_Init+0x8c>)
8000646: 0018 movs r0, r3
8000648: f001 fd96 bl 8002178 <HAL_ADC_Start_IT>
800064c: 1e03 subs r3, r0, #0
800064e: d001 beq.n 8000654 <App_Init+0x74>
{
Error_Handler();
8000650: f000 fac7 bl 8000be2 <Error_Handler>
}
}
8000654: 46c0 nop ; (mov r8, r8)
8000656: 46bd mov sp, r7
8000658: bd80 pop {r7, pc}
800065a: 46c0 nop ; (mov r8, r8)
800065c: 50000400 .word 0x50000400
8000660: 200002c8 .word 0x200002c8
8000664: 20000314 .word 0x20000314
8000668: 200000a4 .word 0x200000a4
800066c: 20000034 .word 0x20000034
8000670: 20000098 .word 0x20000098
08000674 <App_Process>:
void App_Process(void)
{
8000674: b580 push {r7, lr}
8000676: af00 add r7, sp, #0
/* 先处理 Modbus 请求，可能更新寄存器 */
Modbus_Process();
8000678: f000 fad8 bl 8000c2c <Modbus_Process>
App_UpdateMotor(); /*控制推杆上升下降包含自动和手动*/
800067c: f000 f822 bl 80006c4 <App_UpdateMotor>
App_SetCurrentLimit(holdingRegisters[3]); /*限制推杆电机电流*/
8000680: 4b0d ldr r3, [pc, #52] ; (80006b8 <App_Process+0x44>)
8000682: 2206 movs r2, #6
8000684: 5e9b ldrsh r3, [r3, r2]
8000686: b29b uxth r3, r3
8000688: 0018 movs r0, r3
800068a: f000 f8cb bl 8000824 <App_SetCurrentLimit>
App_UpdateEncoderRegister(); /*获取定时器2计数值为编码器数值存到寄存器2*/
800068e: f000 f8e5 bl 800085c <App_UpdateEncoderRegister>
App_ProcessZeroCommand();/*设置当前位置为0*/
8000692: f000 f8f7 bl 8000884 <App_ProcessZeroCommand>
App_UpdateLed(); /*指示灯灯光切换*/
8000696: f000 f911 bl 80008bc <App_UpdateLed>
/* ADC 单次转换完成后重新启动下一轮转换 */
if (adcConversionDone != 0)
800069a: 4b08 ldr r3, [pc, #32] ; (80006bc <App_Process+0x48>)
800069c: 781b ldrb r3, [r3, #0]
800069e: b2db uxtb r3, r3
80006a0: 2b00 cmp r3, #0
80006a2: d006 beq.n 80006b2 <App_Process+0x3e>
{
adcConversionDone = 0;
80006a4: 4b05 ldr r3, [pc, #20] ; (80006bc <App_Process+0x48>)
80006a6: 2200 movs r2, #0
80006a8: 701a strb r2, [r3, #0]
HAL_ADC_Start_IT(&hadc1);
80006aa: 4b05 ldr r3, [pc, #20] ; (80006c0 <App_Process+0x4c>)
80006ac: 0018 movs r0, r3
80006ae: f001 fd63 bl 8002178 <HAL_ADC_Start_IT>
}
}
80006b2: 46c0 nop ; (mov r8, r8)
80006b4: 46bd mov sp, r7
80006b6: bd80 pop {r7, pc}
80006b8: 200000a4 .word 0x200000a4
80006bc: 20000098 .word 0x20000098
80006c0: 20000034 .word 0x20000034
080006c4 <App_UpdateMotor>:
static void App_UpdateMotor(void)
{
80006c4: b580 push {r7, lr}
80006c6: b086 sub sp, #24
80006c8: af00 add r7, sp, #0
uint8_t io1 = (holdingRegisters[0] != 0) ? 1U : 0U;
80006ca: 4b52 ldr r3, [pc, #328] ; (8000814 <App_UpdateMotor+0x150>)
80006cc: 2200 movs r2, #0
80006ce: 5e9b ldrsh r3, [r3, r2]
80006d0: 2b00 cmp r3, #0
80006d2: d001 beq.n 80006d8 <App_UpdateMotor+0x14>
80006d4: 2201 movs r2, #1
80006d6: e000 b.n 80006da <App_UpdateMotor+0x16>
80006d8: 2200 movs r2, #0
80006da: 2315 movs r3, #21
80006dc: 18fb adds r3, r7, r3
80006de: 701a strb r2, [r3, #0]
uint8_t io2 = (holdingRegisters[1] != 0) ? 1U : 0U;
80006e0: 4b4c ldr r3, [pc, #304] ; (8000814 <App_UpdateMotor+0x150>)
80006e2: 2202 movs r2, #2
80006e4: 5e9b ldrsh r3, [r3, r2]
80006e6: 2b00 cmp r3, #0
80006e8: d001 beq.n 80006ee <App_UpdateMotor+0x2a>
80006ea: 2201 movs r2, #1
80006ec: e000 b.n 80006f0 <App_UpdateMotor+0x2c>
80006ee: 2200 movs r2, #0
80006f0: 2314 movs r3, #20
80006f2: 18fb adds r3, r7, r3
80006f4: 701a strb r2, [r3, #0]
uint8_t up = 0U;
80006f6: 2317 movs r3, #23
80006f8: 18fb adds r3, r7, r3
80006fa: 2200 movs r2, #0
80006fc: 701a strb r2, [r3, #0]
uint8_t down = 0U;
80006fe: 2116 movs r1, #22
8000700: 187b adds r3, r7, r1
8000702: 2200 movs r2, #0
8000704: 701a strb r2, [r3, #0]
/*自动运行至指定位置,最下面值最大，最上面为0*/
if (holdingRegisters[6] != 0 && holdingRegisters[7] < Encoder_Max)
8000706: 4b43 ldr r3, [pc, #268] ; (8000814 <App_UpdateMotor+0x150>)
8000708: 220c movs r2, #12
800070a: 5e9b ldrsh r3, [r3, r2]
800070c: 2b00 cmp r3, #0
800070e: d028 beq.n 8000762 <App_UpdateMotor+0x9e>
8000710: 4b40 ldr r3, [pc, #256] ; (8000814 <App_UpdateMotor+0x150>)
8000712: 220e movs r2, #14
8000714: 5e9b ldrsh r3, [r3, r2]
8000716: 4a40 ldr r2, [pc, #256] ; (8000818 <App_UpdateMotor+0x154>)
8000718: 4293 cmp r3, r2
800071a: dc22 bgt.n 8000762 <App_UpdateMotor+0x9e>
{
/* 自动定位模式：根据当前编码器值和目标位置决定运行方向 */
int32_t currentPosition = (int16_t)(uint16_t)__HAL_TIM_GET_COUNTER(&htim2);
800071c: 4b3f ldr r3, [pc, #252] ; (800081c <App_UpdateMotor+0x158>)
800071e: 681b ldr r3, [r3, #0]
8000720: 6a5b ldr r3, [r3, #36] ; 0x24
8000722: b21b sxth r3, r3
8000724: 613b str r3, [r7, #16]
int32_t targetPosition = (int16_t)holdingRegisters[7];
8000726: 4b3b ldr r3, [pc, #236] ; (8000814 <App_UpdateMotor+0x150>)
8000728: 220e movs r2, #14
800072a: 5e9b ldrsh r3, [r3, r2]
800072c: 60fb str r3, [r7, #12]
int32_t positionError = targetPosition - currentPosition;
800072e: 68fa ldr r2, [r7, #12]
8000730: 693b ldr r3, [r7, #16]
8000732: 1ad3 subs r3, r2, r3
8000734: 60bb str r3, [r7, #8]
int32_t tolerance = (int32_t)holdingRegisters[AUTO_POSITION_TOLERANCE_REG]; /*寄存器9*/
8000736: 4b37 ldr r3, [pc, #220] ; (8000814 <App_UpdateMotor+0x150>)
8000738: 2212 movs r2, #18
800073a: 5e9b ldrsh r3, [r3, r2]
800073c: 607b str r3, [r7, #4]
if (positionError > tolerance)
800073e: 68ba ldr r2, [r7, #8]
8000740: 687b ldr r3, [r7, #4]
8000742: 429a cmp r2, r3
8000744: dd03 ble.n 800074e <App_UpdateMotor+0x8a>
{
down = 1U;
8000746: 187b adds r3, r7, r1
8000748: 2201 movs r2, #1
800074a: 701a strb r2, [r3, #0]
{
800074c: e02a b.n 80007a4 <App_UpdateMotor+0xe0>
}
else if (positionError < -tolerance)
800074e: 687b ldr r3, [r7, #4]
8000750: 425b negs r3, r3
8000752: 68ba ldr r2, [r7, #8]
8000754: 429a cmp r2, r3
8000756: da25 bge.n 80007a4 <App_UpdateMotor+0xe0>
{
up = 1U;
8000758: 2317 movs r3, #23
800075a: 18fb adds r3, r7, r3
800075c: 2201 movs r2, #1
800075e: 701a strb r2, [r3, #0]
{
8000760: e020 b.n 80007a4 <App_UpdateMotor+0xe0>
}
}
else
{
/* 手动模式：保持原有 holdingRegisters[0]、[1] 控制逻辑 */
up = (io1 != 0 && io2 == 0) ? 1U : 0U;
8000762: 2315 movs r3, #21
8000764: 18fb adds r3, r7, r3
8000766: 781b ldrb r3, [r3, #0]
8000768: 2b00 cmp r3, #0
800076a: d006 beq.n 800077a <App_UpdateMotor+0xb6>
800076c: 2314 movs r3, #20
800076e: 18fb adds r3, r7, r3
8000770: 781b ldrb r3, [r3, #0]
8000772: 2b00 cmp r3, #0
8000774: d101 bne.n 800077a <App_UpdateMotor+0xb6>
8000776: 2201 movs r2, #1
8000778: e000 b.n 800077c <App_UpdateMotor+0xb8>
800077a: 2200 movs r2, #0
800077c: 2317 movs r3, #23
800077e: 18fb adds r3, r7, r3
8000780: 701a strb r2, [r3, #0]
down = (io1 == 0 && io2 != 0) ? 1U : 0U;
8000782: 2315 movs r3, #21
8000784: 18fb adds r3, r7, r3
8000786: 781b ldrb r3, [r3, #0]
8000788: 2b00 cmp r3, #0
800078a: d106 bne.n 800079a <App_UpdateMotor+0xd6>
800078c: 2314 movs r3, #20
800078e: 18fb adds r3, r7, r3
8000790: 781b ldrb r3, [r3, #0]
8000792: 2b00 cmp r3, #0
8000794: d001 beq.n 800079a <App_UpdateMotor+0xd6>
8000796: 2201 movs r2, #1
8000798: e000 b.n 800079c <App_UpdateMotor+0xd8>
800079a: 2200 movs r2, #0
800079c: 2316 movs r3, #22
800079e: 18fb adds r3, r7, r3
80007a0: 701a strb r2, [r3, #0]
80007a2: e000 b.n 80007a6 <App_UpdateMotor+0xe2>
{
80007a4: 46c0 nop ; (mov r8, r8)
}
if (up != 0)
80007a6: 2317 movs r3, #23
80007a8: 18fb adds r3, r7, r3
80007aa: 781b ldrb r3, [r3, #0]
80007ac: 2b00 cmp r3, #0
80007ae: d00d beq.n 80007cc <App_UpdateMotor+0x108>
{
/* 正转：IO_1 高，IO_2 低 */
HAL_GPIO_WritePin(IO_1_GPIO_Port, IO_1_Pin, GPIO_PIN_RESET);
80007b0: 4b1b ldr r3, [pc, #108] ; (8000820 <App_UpdateMotor+0x15c>)
80007b2: 2200 movs r2, #0
80007b4: 2101 movs r1, #1
80007b6: 0018 movs r0, r3
80007b8: f003 f81c bl 80037f4 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(IO_2_GPIO_Port, IO_2_Pin, GPIO_PIN_SET);
80007bc: 23a0 movs r3, #160 ; 0xa0
80007be: 05db lsls r3, r3, #23
80007c0: 2201 movs r2, #1
80007c2: 2180 movs r1, #128 ; 0x80
80007c4: 0018 movs r0, r3
80007c6: f003 f815 bl 80037f4 <HAL_GPIO_WritePin>
{
/* 停止：两路都低 */
HAL_GPIO_WritePin(IO_1_GPIO_Port, IO_1_Pin, GPIO_PIN_RESET);
HAL_GPIO_WritePin(IO_2_GPIO_Port, IO_2_Pin, GPIO_PIN_RESET);
}
}
80007ca: e01f b.n 800080c <App_UpdateMotor+0x148>
else if (down != 0)
80007cc: 2316 movs r3, #22
80007ce: 18fb adds r3, r7, r3
80007d0: 781b ldrb r3, [r3, #0]
80007d2: 2b00 cmp r3, #0
80007d4: d00d beq.n 80007f2 <App_UpdateMotor+0x12e>
HAL_GPIO_WritePin(IO_1_GPIO_Port, IO_1_Pin, GPIO_PIN_SET);
80007d6: 4b12 ldr r3, [pc, #72] ; (8000820 <App_UpdateMotor+0x15c>)
80007d8: 2201 movs r2, #1
80007da: 2101 movs r1, #1
80007dc: 0018 movs r0, r3
80007de: f003 f809 bl 80037f4 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(IO_2_GPIO_Port, IO_2_Pin, GPIO_PIN_RESET);
80007e2: 23a0 movs r3, #160 ; 0xa0
80007e4: 05db lsls r3, r3, #23
80007e6: 2200 movs r2, #0
80007e8: 2180 movs r1, #128 ; 0x80
80007ea: 0018 movs r0, r3
80007ec: f003 f802 bl 80037f4 <HAL_GPIO_WritePin>
}
80007f0: e00c b.n 800080c <App_UpdateMotor+0x148>
HAL_GPIO_WritePin(IO_1_GPIO_Port, IO_1_Pin, GPIO_PIN_RESET);
80007f2: 4b0b ldr r3, [pc, #44] ; (8000820 <App_UpdateMotor+0x15c>)
80007f4: 2200 movs r2, #0
80007f6: 2101 movs r1, #1
80007f8: 0018 movs r0, r3
80007fa: f002 fffb bl 80037f4 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(IO_2_GPIO_Port, IO_2_Pin, GPIO_PIN_RESET);
80007fe: 23a0 movs r3, #160 ; 0xa0
8000800: 05db lsls r3, r3, #23
8000802: 2200 movs r2, #0
8000804: 2180 movs r1, #128 ; 0x80
8000806: 0018 movs r0, r3
8000808: f002 fff4 bl 80037f4 <HAL_GPIO_WritePin>
}
800080c: 46c0 nop ; (mov r8, r8)
800080e: 46bd mov sp, r7
8000810: b006 add sp, #24
8000812: bd80 pop {r7, pc}
8000814: 200000a4 .word 0x200000a4
8000818: 00001067 .word 0x00001067
800081c: 200002c8 .word 0x200002c8
8000820: 50000400 .word 0x50000400
08000824 <App_SetCurrentLimit>:
static void App_SetCurrentLimit(uint16_t duty)
{
8000824: b580 push {r7, lr}
8000826: b082 sub sp, #8
8000828: af00 add r7, sp, #0
800082a: 0002 movs r2, r0
800082c: 1dbb adds r3, r7, #6
800082e: 801a strh r2, [r3, #0]
if (duty < PWM_DUTY_MIN || duty > PWM_DUTY_MAX)
8000830: 1dbb adds r3, r7, #6
8000832: 881b ldrh r3, [r3, #0]
8000834: 2b00 cmp r3, #0
8000836: d003 beq.n 8000840 <App_SetCurrentLimit+0x1c>
8000838: 1dbb adds r3, r7, #6
800083a: 881b ldrh r3, [r3, #0]
800083c: 2b63 cmp r3, #99 ; 0x63
800083e: d902 bls.n 8000846 <App_SetCurrentLimit+0x22>
{
duty = PWM_DUTY_DEFAULT;
8000840: 1dbb adds r3, r7, #6
8000842: 2263 movs r2, #99 ; 0x63
8000844: 801a strh r2, [r3, #0]
}
__HAL_TIM_SET_COMPARE(&htim3, TIM_CHANNEL_1, duty);
8000846: 4b04 ldr r3, [pc, #16] ; (8000858 <App_SetCurrentLimit+0x34>)
8000848: 681b ldr r3, [r3, #0]
800084a: 1dba adds r2, r7, #6
800084c: 8812 ldrh r2, [r2, #0]
800084e: 635a str r2, [r3, #52] ; 0x34
}
8000850: 46c0 nop ; (mov r8, r8)
8000852: 46bd mov sp, r7
8000854: b002 add sp, #8
8000856: bd80 pop {r7, pc}
8000858: 20000314 .word 0x20000314
0800085c <App_UpdateEncoderRegister>:
static void App_UpdateEncoderRegister(void)
{
800085c: b580 push {r7, lr}
800085e: b082 sub sp, #8
8000860: af00 add r7, sp, #0
int32_t enc = (int32_t)__HAL_TIM_GET_COUNTER(&htim2);
8000862: 4b06 ldr r3, [pc, #24] ; (800087c <App_UpdateEncoderRegister+0x20>)
8000864: 681b ldr r3, [r3, #0]
8000866: 6a5b ldr r3, [r3, #36] ; 0x24
8000868: 607b str r3, [r7, #4]
//holdingRegisters[2] = (uint16_t)(int16_t)enc;
holdingRegisters[2] = (int16_t)enc;
800086a: 687b ldr r3, [r7, #4]
800086c: b21a sxth r2, r3
800086e: 4b04 ldr r3, [pc, #16] ; (8000880 <App_UpdateEncoderRegister+0x24>)
8000870: 809a strh r2, [r3, #4]
}
8000872: 46c0 nop ; (mov r8, r8)
8000874: 46bd mov sp, r7
8000876: b002 add sp, #8
8000878: bd80 pop {r7, pc}
800087a: 46c0 nop ; (mov r8, r8)
800087c: 200002c8 .word 0x200002c8
8000880: 200000a4 .word 0x200000a4
08000884 <App_ProcessZeroCommand>:
static void App_ProcessZeroCommand(void)
{
8000884: b580 push {r7, lr}
8000886: af00 add r7, sp, #0
if (holdingRegisters[5] != lastRegister5)
8000888: 4b09 ldr r3, [pc, #36] ; (80008b0 <App_ProcessZeroCommand+0x2c>)
800088a: 220a movs r2, #10
800088c: 5e9a ldrsh r2, [r3, r2]
800088e: 4b09 ldr r3, [pc, #36] ; (80008b4 <App_ProcessZeroCommand+0x30>)
8000890: 2100 movs r1, #0
8000892: 5e5b ldrsh r3, [r3, r1]
8000894: 429a cmp r2, r3
8000896: d008 beq.n 80008aa <App_ProcessZeroCommand+0x26>
{
lastRegister5 = holdingRegisters[5];
8000898: 4b05 ldr r3, [pc, #20] ; (80008b0 <App_ProcessZeroCommand+0x2c>)
800089a: 220a movs r2, #10
800089c: 5e9a ldrsh r2, [r3, r2]
800089e: 4b05 ldr r3, [pc, #20] ; (80008b4 <App_ProcessZeroCommand+0x30>)
80008a0: 801a strh r2, [r3, #0]
__HAL_TIM_SET_COUNTER(&htim2, 0);
80008a2: 4b05 ldr r3, [pc, #20] ; (80008b8 <App_ProcessZeroCommand+0x34>)
80008a4: 681b ldr r3, [r3, #0]
80008a6: 2200 movs r2, #0
80008a8: 625a str r2, [r3, #36] ; 0x24
}
}
80008aa: 46c0 nop ; (mov r8, r8)
80008ac: 46bd mov sp, r7
80008ae: bd80 pop {r7, pc}
80008b0: 200000a4 .word 0x200000a4
80008b4: 2000009a .word 0x2000009a
80008b8: 200002c8 .word 0x200002c8
080008bc <App_UpdateLed>:
static void App_UpdateLed(void)
{
80008bc: b580 push {r7, lr}
80008be: b086 sub sp, #24
80008c0: af00 add r7, sp, #0
static uint32_t lastToggle = 0;
static GPIO_PinState ledState = GPIO_PIN_RESET;
uint8_t io1 = (holdingRegisters[0] != 0) ? 1U : 0U;
80008c2: 4b34 ldr r3, [pc, #208] ; (8000994 <App_UpdateLed+0xd8>)
80008c4: 2200 movs r2, #0
80008c6: 5e9b ldrsh r3, [r3, r2]
80008c8: 2b00 cmp r3, #0
80008ca: d001 beq.n 80008d0 <App_UpdateLed+0x14>
80008cc: 2201 movs r2, #1
80008ce: e000 b.n 80008d2 <App_UpdateLed+0x16>
80008d0: 2200 movs r2, #0
80008d2: 230f movs r3, #15
80008d4: 18fb adds r3, r7, r3
80008d6: 701a strb r2, [r3, #0]
uint8_t io2 = (holdingRegisters[1] != 0) ? 1U : 0U;
80008d8: 4b2e ldr r3, [pc, #184] ; (8000994 <App_UpdateLed+0xd8>)
80008da: 2202 movs r2, #2
80008dc: 5e9b ldrsh r3, [r3, r2]
80008de: 2b00 cmp r3, #0
80008e0: d001 beq.n 80008e6 <App_UpdateLed+0x2a>
80008e2: 2201 movs r2, #1
80008e4: e000 b.n 80008e8 <App_UpdateLed+0x2c>
80008e6: 2200 movs r2, #0
80008e8: 210e movs r1, #14
80008ea: 187b adds r3, r7, r1
80008ec: 701a strb r2, [r3, #0]
uint32_t onTime;
uint32_t offTime;
uint32_t period;
uint32_t elapsed;
if (io1 != 0 && io2 == 0)
80008ee: 230f movs r3, #15
80008f0: 18fb adds r3, r7, r3
80008f2: 781b ldrb r3, [r3, #0]
80008f4: 2b00 cmp r3, #0
80008f6: d009 beq.n 800090c <App_UpdateLed+0x50>
80008f8: 187b adds r3, r7, r1
80008fa: 781b ldrb r3, [r3, #0]
80008fc: 2b00 cmp r3, #0
80008fe: d105 bne.n 800090c <App_UpdateLed+0x50>
{
onTime = LED_ON_FORWARD_MS;
8000900: 23c8 movs r3, #200 ; 0xc8
8000902: 009b lsls r3, r3, #2
8000904: 617b str r3, [r7, #20]
offTime = LED_OFF_FORWARD_MS;
8000906: 23c8 movs r3, #200 ; 0xc8
8000908: 613b str r3, [r7, #16]
800090a: e015 b.n 8000938 <App_UpdateLed+0x7c>
}
else if (io1 == 0 && io2 != 0)
800090c: 230f movs r3, #15
800090e: 18fb adds r3, r7, r3
8000910: 781b ldrb r3, [r3, #0]
8000912: 2b00 cmp r3, #0
8000914: d10a bne.n 800092c <App_UpdateLed+0x70>
8000916: 230e movs r3, #14
8000918: 18fb adds r3, r7, r3
800091a: 781b ldrb r3, [r3, #0]
800091c: 2b00 cmp r3, #0
800091e: d005 beq.n 800092c <App_UpdateLed+0x70>
{
onTime = LED_ON_REVERSE_MS;
8000920: 23c8 movs r3, #200 ; 0xc8
8000922: 617b str r3, [r7, #20]
offTime = LED_OFF_REVERSE_MS;
8000924: 23c8 movs r3, #200 ; 0xc8
8000926: 009b lsls r3, r3, #2
8000928: 613b str r3, [r7, #16]
800092a: e005 b.n 8000938 <App_UpdateLed+0x7c>
}
else
{
onTime = LED_ON_STOP_MS;
800092c: 23fa movs r3, #250 ; 0xfa
800092e: 005b lsls r3, r3, #1
8000930: 617b str r3, [r7, #20]
offTime = LED_OFF_STOP_MS;
8000932: 23fa movs r3, #250 ; 0xfa
8000934: 005b lsls r3, r3, #1
8000936: 613b str r3, [r7, #16]
}
period = (ledState == GPIO_PIN_SET) ? onTime : offTime;
8000938: 4b17 ldr r3, [pc, #92] ; (8000998 <App_UpdateLed+0xdc>)
800093a: 781b ldrb r3, [r3, #0]
800093c: 2b01 cmp r3, #1
800093e: d101 bne.n 8000944 <App_UpdateLed+0x88>
8000940: 697b ldr r3, [r7, #20]
8000942: e000 b.n 8000946 <App_UpdateLed+0x8a>
8000944: 693b ldr r3, [r7, #16]
8000946: 60bb str r3, [r7, #8]
elapsed = HAL_GetTick() - lastToggle;
8000948: f001 f900 bl 8001b4c <HAL_GetTick>
800094c: 0002 movs r2, r0
800094e: 4b13 ldr r3, [pc, #76] ; (800099c <App_UpdateLed+0xe0>)
8000950: 681b ldr r3, [r3, #0]
8000952: 1ad3 subs r3, r2, r3
8000954: 607b str r3, [r7, #4]
if (elapsed >= period)
8000956: 687a ldr r2, [r7, #4]
8000958: 68bb ldr r3, [r7, #8]
800095a: 429a cmp r2, r3
800095c: d315 bcc.n 800098a <App_UpdateLed+0xce>
{
ledState = (ledState == GPIO_PIN_SET) ? GPIO_PIN_RESET : GPIO_PIN_SET;
800095e: 4b0e ldr r3, [pc, #56] ; (8000998 <App_UpdateLed+0xdc>)
8000960: 781b ldrb r3, [r3, #0]
8000962: 3b01 subs r3, #1
8000964: 1e5a subs r2, r3, #1
8000966: 4193 sbcs r3, r2
8000968: b2db uxtb r3, r3
800096a: 001a movs r2, r3
800096c: 4b0a ldr r3, [pc, #40] ; (8000998 <App_UpdateLed+0xdc>)
800096e: 701a strb r2, [r3, #0]
HAL_GPIO_WritePin(LED_GPIO_Port, LED_Pin, ledState);
8000970: 4b09 ldr r3, [pc, #36] ; (8000998 <App_UpdateLed+0xdc>)
8000972: 781a ldrb r2, [r3, #0]
8000974: 2380 movs r3, #128 ; 0x80
8000976: 005b lsls r3, r3, #1
8000978: 4809 ldr r0, [pc, #36] ; (80009a0 <App_UpdateLed+0xe4>)
800097a: 0019 movs r1, r3
800097c: f002 ff3a bl 80037f4 <HAL_GPIO_WritePin>
lastToggle = HAL_GetTick();
8000980: f001 f8e4 bl 8001b4c <HAL_GetTick>
8000984: 0002 movs r2, r0
8000986: 4b05 ldr r3, [pc, #20] ; (800099c <App_UpdateLed+0xe0>)
8000988: 601a str r2, [r3, #0]
}
}
800098a: 46c0 nop ; (mov r8, r8)
800098c: 46bd mov sp, r7
800098e: b006 add sp, #24
8000990: bd80 pop {r7, pc}
8000992: 46c0 nop ; (mov r8, r8)
8000994: 200000a4 .word 0x200000a4
8000998: 2000009c .word 0x2000009c
800099c: 200000a0 .word 0x200000a0
80009a0: 50000400 .word 0x50000400
080009a4 <HAL_ADC_ConvCpltCallback>:
/* ADC 转换完成中断回调：把采样电压换算为电流（mA） */
void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc)
{
80009a4: b580 push {r7, lr}
80009a6: b086 sub sp, #24
80009a8: af00 add r7, sp, #0
80009aa: 6078 str r0, [r7, #4]
if (hadc->Instance != ADC1)
80009ac: 687b ldr r3, [r7, #4]
80009ae: 681b ldr r3, [r3, #0]
80009b0: 4a16 ldr r2, [pc, #88] ; (8000a0c <HAL_ADC_ConvCpltCallback+0x68>)
80009b2: 4293 cmp r3, r2
80009b4: d126 bne.n 8000a04 <HAL_ADC_ConvCpltCallback+0x60>
{
return;
}
uint32_t raw = HAL_ADC_GetValue(&hadc1);
80009b6: 4b16 ldr r3, [pc, #88] ; (8000a10 <HAL_ADC_ConvCpltCallback+0x6c>)
80009b8: 0018 movs r0, r3
80009ba: f001 fc55 bl 8002268 <HAL_ADC_GetValue>
80009be: 0003 movs r3, r0
80009c0: 613b str r3, [r7, #16]
uint32_t voltage_mv = (raw * ADC_REFERENCE_MV) / ADC_MAX_CODE;
80009c2: 693b ldr r3, [r7, #16]
80009c4: 4a13 ldr r2, [pc, #76] ; (8000a14 <HAL_ADC_ConvCpltCallback+0x70>)
80009c6: 4353 muls r3, r2
80009c8: 4913 ldr r1, [pc, #76] ; (8000a18 <HAL_ADC_ConvCpltCallback+0x74>)
80009ca: 0018 movs r0, r3
80009cc: f7ff fb9a bl 8000104 <__udivsi3>
80009d0: 0003 movs r3, r0
80009d2: 60fb str r3, [r7, #12]
uint16_t current_ma = (uint16_t)voltage_mv;
80009d4: 2116 movs r1, #22
80009d6: 187b adds r3, r7, r1
80009d8: 68fa ldr r2, [r7, #12]
80009da: 801a strh r2, [r3, #0]
if (current_ma > CURRENT_MAX_MA)
80009dc: 187b adds r3, r7, r1
80009de: 881a ldrh r2, [r3, #0]
80009e0: 23fa movs r3, #250 ; 0xfa
80009e2: 00db lsls r3, r3, #3
80009e4: 429a cmp r2, r3
80009e6: d903 bls.n 80009f0 <HAL_ADC_ConvCpltCallback+0x4c>
{
current_ma = CURRENT_MAX_MA;
80009e8: 187b adds r3, r7, r1
80009ea: 22fa movs r2, #250 ; 0xfa
80009ec: 00d2 lsls r2, r2, #3
80009ee: 801a strh r2, [r3, #0]
}
holdingRegisters[4] = current_ma;
80009f0: 2316 movs r3, #22
80009f2: 18fb adds r3, r7, r3
80009f4: 2200 movs r2, #0
80009f6: 5e9a ldrsh r2, [r3, r2]
80009f8: 4b08 ldr r3, [pc, #32] ; (8000a1c <HAL_ADC_ConvCpltCallback+0x78>)
80009fa: 811a strh r2, [r3, #8]
adcConversionDone = 1;
80009fc: 4b08 ldr r3, [pc, #32] ; (8000a20 <HAL_ADC_ConvCpltCallback+0x7c>)
80009fe: 2201 movs r2, #1
8000a00: 701a strb r2, [r3, #0]
8000a02: e000 b.n 8000a06 <HAL_ADC_ConvCpltCallback+0x62>
return;
8000a04: 46c0 nop ; (mov r8, r8)
}
8000a06: 46bd mov sp, r7
8000a08: b006 add sp, #24
8000a0a: bd80 pop {r7, pc}
8000a0c: 40012400 .word 0x40012400
8000a10: 20000034 .word 0x20000034
8000a14: 00000ce4 .word 0x00000ce4
8000a18: 00000fff .word 0x00000fff
8000a1c: 200000a4 .word 0x200000a4
8000a20: 20000098 .word 0x20000098
08000a24 <MX_DMA_Init>:
/**
* Enable DMA controller clock
*/
void MX_DMA_Init(void)
{
8000a24: b580 push {r7, lr}
8000a26: b082 sub sp, #8
8000a28: af00 add r7, sp, #0
/* DMA controller clock enable */
__HAL_RCC_DMA1_CLK_ENABLE();
8000a2a: 4b0c ldr r3, [pc, #48] ; (8000a5c <MX_DMA_Init+0x38>)
8000a2c: 6b9a ldr r2, [r3, #56] ; 0x38
8000a2e: 4b0b ldr r3, [pc, #44] ; (8000a5c <MX_DMA_Init+0x38>)
8000a30: 2101 movs r1, #1
8000a32: 430a orrs r2, r1
8000a34: 639a str r2, [r3, #56] ; 0x38
8000a36: 4b09 ldr r3, [pc, #36] ; (8000a5c <MX_DMA_Init+0x38>)
8000a38: 6b9b ldr r3, [r3, #56] ; 0x38
8000a3a: 2201 movs r2, #1
8000a3c: 4013 ands r3, r2
8000a3e: 607b str r3, [r7, #4]
8000a40: 687b ldr r3, [r7, #4]
/* DMA interrupt init */
/* DMA1_Channel1_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
8000a42: 2200 movs r2, #0
8000a44: 2100 movs r1, #0
8000a46: 2009 movs r0, #9
8000a48: f002 fa20 bl 8002e8c <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
8000a4c: 2009 movs r0, #9
8000a4e: f002 fa32 bl 8002eb6 <HAL_NVIC_EnableIRQ>
}
8000a52: 46c0 nop ; (mov r8, r8)
8000a54: 46bd mov sp, r7
8000a56: b002 add sp, #8
8000a58: bd80 pop {r7, pc}
8000a5a: 46c0 nop ; (mov r8, r8)
8000a5c: 40021000 .word 0x40021000
08000a60 <MX_GPIO_Init>:
* Output
* EVENT_OUT
* EXTI
*/
void MX_GPIO_Init(void)
{
8000a60: b590 push {r4, r7, lr}
8000a62: b089 sub sp, #36 ; 0x24
8000a64: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000a66: 240c movs r4, #12
8000a68: 193b adds r3, r7, r4
8000a6a: 0018 movs r0, r3
8000a6c: 2314 movs r3, #20
8000a6e: 001a movs r2, r3
8000a70: 2100 movs r1, #0
8000a72: f006 fc99 bl 80073a8 <memset>
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOA_CLK_ENABLE();
8000a76: 4b28 ldr r3, [pc, #160] ; (8000b18 <MX_GPIO_Init+0xb8>)
8000a78: 6b5a ldr r2, [r3, #52] ; 0x34
8000a7a: 4b27 ldr r3, [pc, #156] ; (8000b18 <MX_GPIO_Init+0xb8>)
8000a7c: 2101 movs r1, #1
8000a7e: 430a orrs r2, r1
8000a80: 635a str r2, [r3, #52] ; 0x34
8000a82: 4b25 ldr r3, [pc, #148] ; (8000b18 <MX_GPIO_Init+0xb8>)
8000a84: 6b5b ldr r3, [r3, #52] ; 0x34
8000a86: 2201 movs r2, #1
8000a88: 4013 ands r3, r2
8000a8a: 60bb str r3, [r7, #8]
8000a8c: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOB_CLK_ENABLE();
8000a8e: 4b22 ldr r3, [pc, #136] ; (8000b18 <MX_GPIO_Init+0xb8>)
8000a90: 6b5a ldr r2, [r3, #52] ; 0x34
8000a92: 4b21 ldr r3, [pc, #132] ; (8000b18 <MX_GPIO_Init+0xb8>)
8000a94: 2102 movs r1, #2
8000a96: 430a orrs r2, r1
8000a98: 635a str r2, [r3, #52] ; 0x34
8000a9a: 4b1f ldr r3, [pc, #124] ; (8000b18 <MX_GPIO_Init+0xb8>)
8000a9c: 6b5b ldr r3, [r3, #52] ; 0x34
8000a9e: 2202 movs r2, #2
8000aa0: 4013 ands r3, r2
8000aa2: 607b str r3, [r7, #4]
8000aa4: 687b ldr r3, [r7, #4]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOA, DIR_Pin|IO_2_Pin, GPIO_PIN_RESET);
8000aa6: 23a0 movs r3, #160 ; 0xa0
8000aa8: 05db lsls r3, r3, #23
8000aaa: 2200 movs r2, #0
8000aac: 2190 movs r1, #144 ; 0x90
8000aae: 0018 movs r0, r3
8000ab0: f002 fea0 bl 80037f4 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOB, IO_1_Pin|LED_Pin, GPIO_PIN_RESET);
8000ab4: 2302 movs r3, #2
8000ab6: 33ff adds r3, #255 ; 0xff
8000ab8: 4818 ldr r0, [pc, #96] ; (8000b1c <MX_GPIO_Init+0xbc>)
8000aba: 2200 movs r2, #0
8000abc: 0019 movs r1, r3
8000abe: f002 fe99 bl 80037f4 <HAL_GPIO_WritePin>
/*Configure GPIO pins : PAPin PAPin */
GPIO_InitStruct.Pin = DIR_Pin|IO_2_Pin;
8000ac2: 193b adds r3, r7, r4
8000ac4: 2290 movs r2, #144 ; 0x90
8000ac6: 601a str r2, [r3, #0]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000ac8: 193b adds r3, r7, r4
8000aca: 2201 movs r2, #1
8000acc: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000ace: 193b adds r3, r7, r4
8000ad0: 2200 movs r2, #0
8000ad2: 609a str r2, [r3, #8]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000ad4: 193b adds r3, r7, r4
8000ad6: 2200 movs r2, #0
8000ad8: 60da str r2, [r3, #12]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000ada: 193a adds r2, r7, r4
8000adc: 23a0 movs r3, #160 ; 0xa0
8000ade: 05db lsls r3, r3, #23
8000ae0: 0011 movs r1, r2
8000ae2: 0018 movs r0, r3
8000ae4: f002 fd22 bl 800352c <HAL_GPIO_Init>
/*Configure GPIO pins : PBPin PBPin */
GPIO_InitStruct.Pin = IO_1_Pin|LED_Pin;
8000ae8: 0021 movs r1, r4
8000aea: 187b adds r3, r7, r1
8000aec: 2202 movs r2, #2
8000aee: 32ff adds r2, #255 ; 0xff
8000af0: 601a str r2, [r3, #0]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000af2: 187b adds r3, r7, r1
8000af4: 2201 movs r2, #1
8000af6: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000af8: 187b adds r3, r7, r1
8000afa: 2200 movs r2, #0
8000afc: 609a str r2, [r3, #8]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000afe: 187b adds r3, r7, r1
8000b00: 2200 movs r2, #0
8000b02: 60da str r2, [r3, #12]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8000b04: 187b adds r3, r7, r1
8000b06: 4a05 ldr r2, [pc, #20] ; (8000b1c <MX_GPIO_Init+0xbc>)
8000b08: 0019 movs r1, r3
8000b0a: 0010 movs r0, r2
8000b0c: f002 fd0e bl 800352c <HAL_GPIO_Init>
}
8000b10: 46c0 nop ; (mov r8, r8)
8000b12: 46bd mov sp, r7
8000b14: b009 add sp, #36 ; 0x24
8000b16: bd90 pop {r4, r7, pc}
8000b18: 40021000 .word 0x40021000
8000b1c: 50000400 .word 0x50000400
08000b20 <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
8000b20: b580 push {r7, lr}
8000b22: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
8000b24: f000 ff96 bl 8001a54 <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
8000b28: f000 f813 bl 8000b52 <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
8000b2c: f7ff ff98 bl 8000a60 <MX_GPIO_Init>
MX_TIM3_Init();
8000b30: f000 fdb0 bl 8001694 <MX_TIM3_Init>
MX_DMA_Init();
8000b34: f7ff ff76 bl 8000a24 <MX_DMA_Init>
MX_TIM2_Init();
8000b38: f000 fd4a bl 80015d0 <MX_TIM2_Init>
MX_ADC1_Init();
8000b3c: f7ff fc84 bl 8000448 <MX_ADC1_Init>
MX_USART2_UART_Init();
8000b40: f000 feaa bl 8001898 <MX_USART2_UART_Init>
/* USER CODE BEGIN 2 */
App_Init();
8000b44: f7ff fd4c bl 80005e0 <App_Init>
Modbus_Init();
8000b48: f000 f850 bl 8000bec <Modbus_Init>
while (1)
{
/* USER CODE END WHILE */
/* USER CODE BEGIN 3 */
App_Process();
8000b4c: f7ff fd92 bl 8000674 <App_Process>
8000b50: e7fc b.n 8000b4c <main+0x2c>
08000b52 <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
8000b52: b590 push {r4, r7, lr}
8000b54: b093 sub sp, #76 ; 0x4c
8000b56: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
8000b58: 2410 movs r4, #16
8000b5a: 193b adds r3, r7, r4
8000b5c: 0018 movs r0, r3
8000b5e: 2338 movs r3, #56 ; 0x38
8000b60: 001a movs r2, r3
8000b62: 2100 movs r1, #0
8000b64: f006 fc20 bl 80073a8 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
8000b68: 003b movs r3, r7
8000b6a: 0018 movs r0, r3
8000b6c: 2310 movs r3, #16
8000b6e: 001a movs r2, r3
8000b70: 2100 movs r1, #0
8000b72: f006 fc19 bl 80073a8 <memset>
/** Configure the main internal regulator output voltage
*/
HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
8000b76: 2380 movs r3, #128 ; 0x80
8000b78: 009b lsls r3, r3, #2
8000b7a: 0018 movs r0, r3
8000b7c: f002 fe58 bl 8003830 <HAL_PWREx_ControlVoltageScaling>
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
8000b80: 193b adds r3, r7, r4
8000b82: 2202 movs r2, #2
8000b84: 601a str r2, [r3, #0]
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
8000b86: 193b adds r3, r7, r4
8000b88: 2280 movs r2, #128 ; 0x80
8000b8a: 0052 lsls r2, r2, #1
8000b8c: 60da str r2, [r3, #12]
RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1;
8000b8e: 193b adds r3, r7, r4
8000b90: 2200 movs r2, #0
8000b92: 611a str r2, [r3, #16]
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
8000b94: 193b adds r3, r7, r4
8000b96: 2240 movs r2, #64 ; 0x40
8000b98: 615a str r2, [r3, #20]
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
8000b9a: 193b adds r3, r7, r4
8000b9c: 2200 movs r2, #0
8000b9e: 61da str r2, [r3, #28]
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
8000ba0: 193b adds r3, r7, r4
8000ba2: 0018 movs r0, r3
8000ba4: f002 fe90 bl 80038c8 <HAL_RCC_OscConfig>
8000ba8: 1e03 subs r3, r0, #0
8000baa: d001 beq.n 8000bb0 <SystemClock_Config+0x5e>
{
Error_Handler();
8000bac: f000 f819 bl 8000be2 <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
8000bb0: 003b movs r3, r7
8000bb2: 2207 movs r2, #7
8000bb4: 601a str r2, [r3, #0]
|RCC_CLOCKTYPE_PCLK1;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
8000bb6: 003b movs r3, r7
8000bb8: 2200 movs r2, #0
8000bba: 605a str r2, [r3, #4]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
8000bbc: 003b movs r3, r7
8000bbe: 2200 movs r2, #0
8000bc0: 609a str r2, [r3, #8]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
8000bc2: 003b movs r3, r7
8000bc4: 2200 movs r2, #0
8000bc6: 60da str r2, [r3, #12]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
8000bc8: 003b movs r3, r7
8000bca: 2100 movs r1, #0
8000bcc: 0018 movs r0, r3
8000bce: f003 f995 bl 8003efc <HAL_RCC_ClockConfig>
8000bd2: 1e03 subs r3, r0, #0
8000bd4: d001 beq.n 8000bda <SystemClock_Config+0x88>
{
Error_Handler();
8000bd6: f000 f804 bl 8000be2 <Error_Handler>
}
}
8000bda: 46c0 nop ; (mov r8, r8)
8000bdc: 46bd mov sp, r7
8000bde: b013 add sp, #76 ; 0x4c
8000be0: bd90 pop {r4, r7, pc}
08000be2 <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
8000be2: b580 push {r7, lr}
8000be4: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
8000be6: b672 cpsid i
}
8000be8: 46c0 nop ; (mov r8, r8)
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
8000bea: e7fe b.n 8000bea <Error_Handler+0x8>
08000bec <Modbus_Init>:
void Modbus_SendExceptionResponse(uint8_t exceptionCode);
uint16_t CalculateCRC(uint8_t *data, uint8_t length);
/* 初始化函数 */
void Modbus_Init(void)
{
8000bec: b580 push {r7, lr}
8000bee: af00 add r7, sp, #0
HAL_GPIO_WritePin(DIR_GPIO_Port, DIR_Pin, GPIO_PIN_RESET); // 设置 RS485 为接收模式
8000bf0: 23a0 movs r3, #160 ; 0xa0
8000bf2: 05db lsls r3, r3, #23
8000bf4: 2200 movs r2, #0
8000bf6: 2110 movs r1, #16
8000bf8: 0018 movs r0, r3
8000bfa: f002 fdfb bl 80037f4 <HAL_GPIO_WritePin>
modbusBufferIndex = 0; // 清空接收索引
8000bfe: 4b07 ldr r3, [pc, #28] ; (8000c1c <Modbus_Init+0x30>)
8000c00: 2200 movs r2, #0
8000c02: 801a strh r2, [r3, #0]
messageComplete = false; // 清除帧完成标志
8000c04: 4b06 ldr r3, [pc, #24] ; (8000c20 <Modbus_Init+0x34>)
8000c06: 2200 movs r2, #0
8000c08: 701a strb r2, [r3, #0]
HAL_UART_Receive_IT(&huart2, &rxByte, 1); // 接收到固定变量，而不是直接接收进缓冲区
8000c0a: 4906 ldr r1, [pc, #24] ; (8000c24 <Modbus_Init+0x38>)
8000c0c: 4b06 ldr r3, [pc, #24] ; (8000c28 <Modbus_Init+0x3c>)
8000c0e: 2201 movs r2, #1
8000c10: 0018 movs r0, r3
8000c12: f004 fc0d bl 8005430 <HAL_UART_Receive_IT>
}
8000c16: 46c0 nop ; (mov r8, r8)
8000c18: 46bd mov sp, r7
8000c1a: bd80 pop {r7, pc}
8000c1c: 200001b8 .word 0x200001b8
8000c20: 200001c0 .word 0x200001c0
8000c24: 200002c4 .word 0x200002c4
8000c28: 20000360 .word 0x20000360
08000c2c <Modbus_Process>:
// HAL_UART_Receive_IT(&huart2, (uint8_t *)&modbusBuffer[modbusBufferIndex], 1);
//}
/* Modbus处理函数 - 应在主循环中调用 */
void Modbus_Process(void)
{
8000c2c: b590 push {r4, r7, lr}
8000c2e: b085 sub sp, #20
8000c30: af00 add r7, sp, #0
uint16_t startAddress = 0;
8000c32: 230e movs r3, #14
8000c34: 18fb adds r3, r7, r3
8000c36: 2200 movs r2, #0
8000c38: 801a strh r2, [r3, #0]
uint16_t registerCount = 0;
8000c3a: 230c movs r3, #12
8000c3c: 18fb adds r3, r7, r3
8000c3e: 2200 movs r2, #0
8000c40: 801a strh r2, [r3, #0]
uint16_t value = 0;
8000c42: 230a movs r3, #10
8000c44: 18fb adds r3, r7, r3
8000c46: 2200 movs r2, #0
8000c48: 801a strh r2, [r3, #0]
uint8_t byteCount = 0;
8000c4a: 2309 movs r3, #9
8000c4c: 18fb adds r3, r7, r3
8000c4e: 2200 movs r2, #0
8000c50: 701a strb r2, [r3, #0]
uint16_t crcReceived;
uint16_t crcCalculated;
if (modbusBufferIndex > 0 && (HAL_GetTick() - lastByteTime) > MODBUS_TIMEOUT_MS)
8000c52: 4b7c ldr r3, [pc, #496] ; (8000e44 <Modbus_Process+0x218>)
8000c54: 881b ldrh r3, [r3, #0]
8000c56: 2b00 cmp r3, #0
8000c58: d00a beq.n 8000c70 <Modbus_Process+0x44>
8000c5a: f000 ff77 bl 8001b4c <HAL_GetTick>
8000c5e: 0002 movs r2, r0
8000c60: 4b79 ldr r3, [pc, #484] ; (8000e48 <Modbus_Process+0x21c>)
8000c62: 681b ldr r3, [r3, #0]
8000c64: 1ad3 subs r3, r2, r3
8000c66: 2b14 cmp r3, #20
8000c68: d902 bls.n 8000c70 <Modbus_Process+0x44>
{
/* 超时，标记消息完成 */
messageComplete = true;
8000c6a: 4b78 ldr r3, [pc, #480] ; (8000e4c <Modbus_Process+0x220>)
8000c6c: 2201 movs r2, #1
8000c6e: 701a strb r2, [r3, #0]
}
if (!messageComplete)
8000c70: 4b76 ldr r3, [pc, #472] ; (8000e4c <Modbus_Process+0x220>)
8000c72: 781b ldrb r3, [r3, #0]
8000c74: 2201 movs r2, #1
8000c76: 4053 eors r3, r2
8000c78: b2db uxtb r3, r3
8000c7a: 2b00 cmp r3, #0
8000c7c: d000 beq.n 8000c80 <Modbus_Process+0x54>
8000c7e: e0dd b.n 8000e3c <Modbus_Process+0x210>
{
return;
}
/* 一个有效的 RTU 帧至少包含：地址 + 功能码 + 2 字节 CRC */
if (modbusBufferIndex < 4)
8000c80: 4b70 ldr r3, [pc, #448] ; (8000e44 <Modbus_Process+0x218>)
8000c82: 881b ldrh r3, [r3, #0]
8000c84: 2b03 cmp r3, #3
8000c86: d806 bhi.n 8000c96 <Modbus_Process+0x6a>
{
modbusBufferIndex = 0;
8000c88: 4b6e ldr r3, [pc, #440] ; (8000e44 <Modbus_Process+0x218>)
8000c8a: 2200 movs r2, #0
8000c8c: 801a strh r2, [r3, #0]
messageComplete = false;
8000c8e: 4b6f ldr r3, [pc, #444] ; (8000e4c <Modbus_Process+0x220>)
8000c90: 2200 movs r2, #0
8000c92: 701a strb r2, [r3, #0]
return;
8000c94: e0d3 b.n 8000e3e <Modbus_Process+0x212>
}
crcReceived = (uint16_t)((modbusBuffer[modbusBufferIndex - 1] << 8) |
8000c96: 4b6b ldr r3, [pc, #428] ; (8000e44 <Modbus_Process+0x218>)
8000c98: 881b ldrh r3, [r3, #0]
8000c9a: 3b01 subs r3, #1
8000c9c: 4a6c ldr r2, [pc, #432] ; (8000e50 <Modbus_Process+0x224>)
8000c9e: 5cd3 ldrb r3, [r2, r3]
8000ca0: 021b lsls r3, r3, #8
8000ca2: b21a sxth r2, r3
modbusBuffer[modbusBufferIndex - 2]);
8000ca4: 4b67 ldr r3, [pc, #412] ; (8000e44 <Modbus_Process+0x218>)
8000ca6: 881b ldrh r3, [r3, #0]
8000ca8: 3b02 subs r3, #2
8000caa: 4969 ldr r1, [pc, #420] ; (8000e50 <Modbus_Process+0x224>)
8000cac: 5ccb ldrb r3, [r1, r3]
8000cae: b21b sxth r3, r3
crcReceived = (uint16_t)((modbusBuffer[modbusBufferIndex - 1] << 8) |
8000cb0: 4313 orrs r3, r2
8000cb2: b21a sxth r2, r3
8000cb4: 1dbb adds r3, r7, #6
8000cb6: 801a strh r2, [r3, #0]
crcCalculated = CalculateCRC(modbusBuffer, (uint8_t)(modbusBufferIndex - 2));
8000cb8: 4b62 ldr r3, [pc, #392] ; (8000e44 <Modbus_Process+0x218>)
8000cba: 881b ldrh r3, [r3, #0]
8000cbc: b2db uxtb r3, r3
8000cbe: 3b02 subs r3, #2
8000cc0: b2da uxtb r2, r3
8000cc2: 1d3c adds r4, r7, #4
8000cc4: 4b62 ldr r3, [pc, #392] ; (8000e50 <Modbus_Process+0x224>)
8000cc6: 0011 movs r1, r2
8000cc8: 0018 movs r0, r3
8000cca: f000 fb4f bl 800136c <CalculateCRC>
8000cce: 0003 movs r3, r0
8000cd0: 8023 strh r3, [r4, #0]
if (MODBUS_CRC_OFF == 1 || crcReceived == crcCalculated)
8000cd2: 1dba adds r2, r7, #6
8000cd4: 1d3b adds r3, r7, #4
8000cd6: 8812 ldrh r2, [r2, #0]
8000cd8: 881b ldrh r3, [r3, #0]
8000cda: 429a cmp r2, r3
8000cdc: d000 beq.n 8000ce0 <Modbus_Process+0xb4>
8000cde: e09f b.n 8000e20 <Modbus_Process+0x1f4>
{
if (modbusBuffer[0] == MODBUS_SLAVE_ADDRESS) /*ID 0x42*/
8000ce0: 4b5b ldr r3, [pc, #364] ; (8000e50 <Modbus_Process+0x224>)
8000ce2: 781b ldrb r3, [r3, #0]
8000ce4: 2b42 cmp r3, #66 ; 0x42
8000ce6: d000 beq.n 8000cea <Modbus_Process+0xbe>
8000ce8: e09a b.n 8000e20 <Modbus_Process+0x1f4>
{
switch (modbusBuffer[1])
8000cea: 4b59 ldr r3, [pc, #356] ; (8000e50 <Modbus_Process+0x224>)
8000cec: 785b ldrb r3, [r3, #1]
8000cee: 2b10 cmp r3, #16
8000cf0: d051 beq.n 8000d96 <Modbus_Process+0x16a>
8000cf2: dd00 ble.n 8000cf6 <Modbus_Process+0xca>
8000cf4: e090 b.n 8000e18 <Modbus_Process+0x1ec>
8000cf6: 2b03 cmp r3, #3
8000cf8: d002 beq.n 8000d00 <Modbus_Process+0xd4>
8000cfa: 2b06 cmp r3, #6
8000cfc: d026 beq.n 8000d4c <Modbus_Process+0x120>
8000cfe: e08b b.n 8000e18 <Modbus_Process+0x1ec>
{
case MODBUS_FUNCTION_CODE_03:
if (modbusBufferIndex >= 8)
8000d00: 4b50 ldr r3, [pc, #320] ; (8000e44 <Modbus_Process+0x218>)
8000d02: 881b ldrh r3, [r3, #0]
8000d04: 2b07 cmp r3, #7
8000d06: d800 bhi.n 8000d0a <Modbus_Process+0xde>
8000d08: e08c b.n 8000e24 <Modbus_Process+0x1f8>
{
startAddress = (uint16_t)((modbusBuffer[2] << 8) | modbusBuffer[3]);
8000d0a: 4b51 ldr r3, [pc, #324] ; (8000e50 <Modbus_Process+0x224>)
8000d0c: 789b ldrb r3, [r3, #2]
8000d0e: 021b lsls r3, r3, #8
8000d10: b21a sxth r2, r3
8000d12: 4b4f ldr r3, [pc, #316] ; (8000e50 <Modbus_Process+0x224>)
8000d14: 78db ldrb r3, [r3, #3]
8000d16: b21b sxth r3, r3
8000d18: 4313 orrs r3, r2
8000d1a: b21a sxth r2, r3
8000d1c: 210e movs r1, #14
8000d1e: 187b adds r3, r7, r1
8000d20: 801a strh r2, [r3, #0]
registerCount = (uint16_t)((modbusBuffer[4] << 8) | modbusBuffer[5]);
8000d22: 4b4b ldr r3, [pc, #300] ; (8000e50 <Modbus_Process+0x224>)
8000d24: 791b ldrb r3, [r3, #4]
8000d26: 021b lsls r3, r3, #8
8000d28: b21a sxth r2, r3
8000d2a: 4b49 ldr r3, [pc, #292] ; (8000e50 <Modbus_Process+0x224>)
8000d2c: 795b ldrb r3, [r3, #5]
8000d2e: b21b sxth r3, r3
8000d30: 4313 orrs r3, r2
8000d32: b21a sxth r2, r3
8000d34: 200c movs r0, #12
8000d36: 183b adds r3, r7, r0
8000d38: 801a strh r2, [r3, #0]
Modbus_HandleFunction03(startAddress, registerCount);
8000d3a: 183b adds r3, r7, r0
8000d3c: 881a ldrh r2, [r3, #0]
8000d3e: 187b adds r3, r7, r1
8000d40: 881b ldrh r3, [r3, #0]
8000d42: 0011 movs r1, r2
8000d44: 0018 movs r0, r3
8000d46: f000 f887 bl 8000e58 <Modbus_HandleFunction03>
}
break;
8000d4a: e06b b.n 8000e24 <Modbus_Process+0x1f8>
case MODBUS_FUNCTION_CODE_06:
if (modbusBufferIndex >= 8)
8000d4c: 4b3d ldr r3, [pc, #244] ; (8000e44 <Modbus_Process+0x218>)
8000d4e: 881b ldrh r3, [r3, #0]
8000d50: 2b07 cmp r3, #7
8000d52: d969 bls.n 8000e28 <Modbus_Process+0x1fc>
{
startAddress = (uint16_t)((modbusBuffer[2] << 8) | modbusBuffer[3]);
8000d54: 4b3e ldr r3, [pc, #248] ; (8000e50 <Modbus_Process+0x224>)
8000d56: 789b ldrb r3, [r3, #2]
8000d58: 021b lsls r3, r3, #8
8000d5a: b21a sxth r2, r3
8000d5c: 4b3c ldr r3, [pc, #240] ; (8000e50 <Modbus_Process+0x224>)
8000d5e: 78db ldrb r3, [r3, #3]
8000d60: b21b sxth r3, r3
8000d62: 4313 orrs r3, r2
8000d64: b21a sxth r2, r3
8000d66: 210e movs r1, #14
8000d68: 187b adds r3, r7, r1
8000d6a: 801a strh r2, [r3, #0]
value = (uint16_t)((modbusBuffer[4] << 8) | modbusBuffer[5]);
8000d6c: 4b38 ldr r3, [pc, #224] ; (8000e50 <Modbus_Process+0x224>)
8000d6e: 791b ldrb r3, [r3, #4]
8000d70: 021b lsls r3, r3, #8
8000d72: b21a sxth r2, r3
8000d74: 4b36 ldr r3, [pc, #216] ; (8000e50 <Modbus_Process+0x224>)
8000d76: 795b ldrb r3, [r3, #5]
8000d78: b21b sxth r3, r3
8000d7a: 4313 orrs r3, r2
8000d7c: b21a sxth r2, r3
8000d7e: 200a movs r0, #10
8000d80: 183b adds r3, r7, r0
8000d82: 801a strh r2, [r3, #0]
Modbus_HandleFunction06(startAddress, value);
8000d84: 183b adds r3, r7, r0
8000d86: 881a ldrh r2, [r3, #0]
8000d88: 187b adds r3, r7, r1
8000d8a: 881b ldrh r3, [r3, #0]
8000d8c: 0011 movs r1, r2
8000d8e: 0018 movs r0, r3
8000d90: f000 f90c bl 8000fac <Modbus_HandleFunction06>
}
break;
8000d94: e048 b.n 8000e28 <Modbus_Process+0x1fc>
case MODBUS_FUNCTION_CODE_10:
if (modbusBufferIndex >= 9)
8000d96: 4b2b ldr r3, [pc, #172] ; (8000e44 <Modbus_Process+0x218>)
8000d98: 881b ldrh r3, [r3, #0]
8000d9a: 2b08 cmp r3, #8
8000d9c: d946 bls.n 8000e2c <Modbus_Process+0x200>
{
startAddress = (uint16_t)((modbusBuffer[2] << 8) | modbusBuffer[3]);
8000d9e: 4b2c ldr r3, [pc, #176] ; (8000e50 <Modbus_Process+0x224>)
8000da0: 789b ldrb r3, [r3, #2]
8000da2: 021b lsls r3, r3, #8
8000da4: b21a sxth r2, r3
8000da6: 4b2a ldr r3, [pc, #168] ; (8000e50 <Modbus_Process+0x224>)
8000da8: 78db ldrb r3, [r3, #3]
8000daa: b21b sxth r3, r3
8000dac: 4313 orrs r3, r2
8000dae: b21a sxth r2, r3
8000db0: 240e movs r4, #14
8000db2: 193b adds r3, r7, r4
8000db4: 801a strh r2, [r3, #0]
registerCount = (uint16_t)((modbusBuffer[4] << 8) | modbusBuffer[5]);
8000db6: 4b26 ldr r3, [pc, #152] ; (8000e50 <Modbus_Process+0x224>)
8000db8: 791b ldrb r3, [r3, #4]
8000dba: 021b lsls r3, r3, #8
8000dbc: b21a sxth r2, r3
8000dbe: 4b24 ldr r3, [pc, #144] ; (8000e50 <Modbus_Process+0x224>)
8000dc0: 795b ldrb r3, [r3, #5]
8000dc2: b21b sxth r3, r3
8000dc4: 4313 orrs r3, r2
8000dc6: b21a sxth r2, r3
8000dc8: 210c movs r1, #12
8000dca: 187b adds r3, r7, r1
8000dcc: 801a strh r2, [r3, #0]
byteCount = modbusBuffer[6];
8000dce: 2009 movs r0, #9
8000dd0: 183b adds r3, r7, r0
8000dd2: 4a1f ldr r2, [pc, #124] ; (8000e50 <Modbus_Process+0x224>)
8000dd4: 7992 ldrb r2, [r2, #6]
8000dd6: 701a strb r2, [r3, #0]
/* 检查数据长度是否正确 */
if (byteCount == (uint8_t)(registerCount * 2U) &&
8000dd8: 187b adds r3, r7, r1
8000dda: 881b ldrh r3, [r3, #0]
8000ddc: b2db uxtb r3, r3
8000dde: 18db adds r3, r3, r3
8000de0: b2db uxtb r3, r3
8000de2: 183a adds r2, r7, r0
8000de4: 7812 ldrb r2, [r2, #0]
8000de6: 429a cmp r2, r3
8000de8: d112 bne.n 8000e10 <Modbus_Process+0x1e4>
(modbusBufferIndex - 2U) >= (uint16_t)(7U + byteCount))
8000dea: 4b16 ldr r3, [pc, #88] ; (8000e44 <Modbus_Process+0x218>)
8000dec: 881b ldrh r3, [r3, #0]
8000dee: 3b02 subs r3, #2
8000df0: 183a adds r2, r7, r0
8000df2: 7812 ldrb r2, [r2, #0]
8000df4: b292 uxth r2, r2
8000df6: 3207 adds r2, #7
8000df8: b292 uxth r2, r2
if (byteCount == (uint8_t)(registerCount * 2U) &&
8000dfa: 4293 cmp r3, r2
8000dfc: d308 bcc.n 8000e10 <Modbus_Process+0x1e4>
{
Modbus_HandleFunction10(startAddress, registerCount, &modbusBuffer[7]);
8000dfe: 4a15 ldr r2, [pc, #84] ; (8000e54 <Modbus_Process+0x228>)
8000e00: 187b adds r3, r7, r1
8000e02: 8819 ldrh r1, [r3, #0]
8000e04: 193b adds r3, r7, r4
8000e06: 881b ldrh r3, [r3, #0]
8000e08: 0018 movs r0, r3
8000e0a: f000 f981 bl 8001110 <Modbus_HandleFunction10>
else
{
Modbus_SendExceptionResponse(0x03);
}
}
break;
8000e0e: e00d b.n 8000e2c <Modbus_Process+0x200>
Modbus_SendExceptionResponse(0x03);
8000e10: 2003 movs r0, #3
8000e12: f000 fa57 bl 80012c4 <Modbus_SendExceptionResponse>
break;
8000e16: e009 b.n 8000e2c <Modbus_Process+0x200>
default:
Modbus_SendExceptionResponse(0x01);
8000e18: 2001 movs r0, #1
8000e1a: f000 fa53 bl 80012c4 <Modbus_SendExceptionResponse>
break;
8000e1e: e006 b.n 8000e2e <Modbus_Process+0x202>
}
}
8000e20: 46c0 nop ; (mov r8, r8)
8000e22: e004 b.n 8000e2e <Modbus_Process+0x202>
break;
8000e24: 46c0 nop ; (mov r8, r8)
8000e26: e002 b.n 8000e2e <Modbus_Process+0x202>
break;
8000e28: 46c0 nop ; (mov r8, r8)
8000e2a: e000 b.n 8000e2e <Modbus_Process+0x202>
break;
8000e2c: 46c0 nop ; (mov r8, r8)
}
/* 重置缓冲区 */
modbusBufferIndex = 0;
8000e2e: 4b05 ldr r3, [pc, #20] ; (8000e44 <Modbus_Process+0x218>)
8000e30: 2200 movs r2, #0
8000e32: 801a strh r2, [r3, #0]
messageComplete = false;
8000e34: 4b05 ldr r3, [pc, #20] ; (8000e4c <Modbus_Process+0x220>)
8000e36: 2200 movs r2, #0
8000e38: 701a strb r2, [r3, #0]
8000e3a: e000 b.n 8000e3e <Modbus_Process+0x212>
return;
8000e3c: 46c0 nop ; (mov r8, r8)
}
8000e3e: 46bd mov sp, r7
8000e40: b005 add sp, #20
8000e42: bd90 pop {r4, r7, pc}
8000e44: 200001b8 .word 0x200001b8
8000e48: 200001bc .word 0x200001bc
8000e4c: 200001c0 .word 0x200001c0
8000e50: 200000b8 .word 0x200000b8
8000e54: 200000bf .word 0x200000bf
08000e58 <Modbus_HandleFunction03>:
/* 处理功能码03 */
void Modbus_HandleFunction03(uint16_t startAddress, uint16_t registerCount)
{
8000e58: b5f0 push {r4, r5, r6, r7, lr}
8000e5a: b087 sub sp, #28
8000e5c: af00 add r7, sp, #0
8000e5e: 0002 movs r2, r0
8000e60: 1dbb adds r3, r7, #6
8000e62: 801a strh r2, [r3, #0]
8000e64: 1d3b adds r3, r7, #4
8000e66: 1c0a adds r2, r1, #0
8000e68: 801a strh r2, [r3, #0]
/* 检查地址和数量是否合法 */
if ((startAddress + registerCount) > (REGISTER_START_ADDRESS + REGISTER_COUNT) ||
8000e6a: 1dbb adds r3, r7, #6
8000e6c: 881a ldrh r2, [r3, #0]
8000e6e: 1d3b adds r3, r7, #4
8000e70: 881b ldrh r3, [r3, #0]
8000e72: 18d3 adds r3, r2, r3
8000e74: 2b0a cmp r3, #10
8000e76: dc03 bgt.n 8000e80 <Modbus_HandleFunction03+0x28>
8000e78: 1d3b adds r3, r7, #4
8000e7a: 881b ldrh r3, [r3, #0]
8000e7c: 2b7d cmp r3, #125 ; 0x7d
8000e7e: d903 bls.n 8000e88 <Modbus_HandleFunction03+0x30>
registerCount > 0x7D)
{
Modbus_SendExceptionResponse(0x02);
8000e80: 2002 movs r0, #2
8000e82: f000 fa1f bl 80012c4 <Modbus_SendExceptionResponse>
return;
8000e86: e089 b.n 8000f9c <Modbus_HandleFunction03+0x144>
}
uint8_t byteCount = (uint8_t)(registerCount * 2U);
8000e88: 1d3b adds r3, r7, #4
8000e8a: 881b ldrh r3, [r3, #0]
8000e8c: b2db uxtb r3, r3
8000e8e: 2413 movs r4, #19
8000e90: 193a adds r2, r7, r4
8000e92: 18db adds r3, r3, r3
8000e94: 7013 strb r3, [r2, #0]
uint8_t index = 0;
8000e96: 2017 movs r0, #23
8000e98: 183b adds r3, r7, r0
8000e9a: 2200 movs r2, #0
8000e9c: 701a strb r2, [r3, #0]
response[index++] = MODBUS_SLAVE_ADDRESS;
8000e9e: 183b adds r3, r7, r0
8000ea0: 781b ldrb r3, [r3, #0]
8000ea2: 183a adds r2, r7, r0
8000ea4: 1c59 adds r1, r3, #1
8000ea6: 7011 strb r1, [r2, #0]
8000ea8: 001a movs r2, r3
8000eaa: 4b3e ldr r3, [pc, #248] ; (8000fa4 <Modbus_HandleFunction03+0x14c>)
8000eac: 2142 movs r1, #66 ; 0x42
8000eae: 5499 strb r1, [r3, r2]
response[index++] = MODBUS_FUNCTION_CODE_03;
8000eb0: 183b adds r3, r7, r0
8000eb2: 781b ldrb r3, [r3, #0]
8000eb4: 183a adds r2, r7, r0
8000eb6: 1c59 adds r1, r3, #1
8000eb8: 7011 strb r1, [r2, #0]
8000eba: 001a movs r2, r3
8000ebc: 4b39 ldr r3, [pc, #228] ; (8000fa4 <Modbus_HandleFunction03+0x14c>)
8000ebe: 2103 movs r1, #3
8000ec0: 5499 strb r1, [r3, r2]
response[index++] = byteCount;
8000ec2: 183b adds r3, r7, r0
8000ec4: 781b ldrb r3, [r3, #0]
8000ec6: 183a adds r2, r7, r0
8000ec8: 1c59 adds r1, r3, #1
8000eca: 7011 strb r1, [r2, #0]
8000ecc: 0019 movs r1, r3
8000ece: 4b35 ldr r3, [pc, #212] ; (8000fa4 <Modbus_HandleFunction03+0x14c>)
8000ed0: 193a adds r2, r7, r4
8000ed2: 7812 ldrb r2, [r2, #0]
8000ed4: 545a strb r2, [r3, r1]
for (uint16_t i = 0; i < registerCount; i++)
8000ed6: 2314 movs r3, #20
8000ed8: 18fb adds r3, r7, r3
8000eda: 2200 movs r2, #0
8000edc: 801a strh r2, [r3, #0]
8000ede: e029 b.n 8000f34 <Modbus_HandleFunction03+0xdc>
{
uint16_t regValue = holdingRegisters[(startAddress - REGISTER_START_ADDRESS) + i];
8000ee0: 1dbb adds r3, r7, #6
8000ee2: 881a ldrh r2, [r3, #0]
8000ee4: 2514 movs r5, #20
8000ee6: 197b adds r3, r7, r5
8000ee8: 881b ldrh r3, [r3, #0]
8000eea: 18d2 adds r2, r2, r3
8000eec: 4b2e ldr r3, [pc, #184] ; (8000fa8 <Modbus_HandleFunction03+0x150>)
8000eee: 0052 lsls r2, r2, #1
8000ef0: 5ed2 ldrsh r2, [r2, r3]
8000ef2: 260e movs r6, #14
8000ef4: 19bb adds r3, r7, r6
8000ef6: 801a strh r2, [r3, #0]
response[index++] = (uint8_t)((regValue >> 8) & 0xFF);
8000ef8: 19bb adds r3, r7, r6
8000efa: 881b ldrh r3, [r3, #0]
8000efc: 0a1b lsrs r3, r3, #8
8000efe: b299 uxth r1, r3
8000f00: 2417 movs r4, #23
8000f02: 193b adds r3, r7, r4
8000f04: 781b ldrb r3, [r3, #0]
8000f06: 193a adds r2, r7, r4
8000f08: 1c58 adds r0, r3, #1
8000f0a: 7010 strb r0, [r2, #0]
8000f0c: 001a movs r2, r3
8000f0e: b2c9 uxtb r1, r1
8000f10: 4b24 ldr r3, [pc, #144] ; (8000fa4 <Modbus_HandleFunction03+0x14c>)
8000f12: 5499 strb r1, [r3, r2]
response[index++] = (uint8_t)(regValue & 0xFF);
8000f14: 193b adds r3, r7, r4
8000f16: 781b ldrb r3, [r3, #0]
8000f18: 193a adds r2, r7, r4
8000f1a: 1c59 adds r1, r3, #1
8000f1c: 7011 strb r1, [r2, #0]
8000f1e: 001a movs r2, r3
8000f20: 19bb adds r3, r7, r6
8000f22: 881b ldrh r3, [r3, #0]
8000f24: b2d9 uxtb r1, r3
8000f26: 4b1f ldr r3, [pc, #124] ; (8000fa4 <Modbus_HandleFunction03+0x14c>)
8000f28: 5499 strb r1, [r3, r2]
for (uint16_t i = 0; i < registerCount; i++)
8000f2a: 197b adds r3, r7, r5
8000f2c: 881a ldrh r2, [r3, #0]
8000f2e: 197b adds r3, r7, r5
8000f30: 3201 adds r2, #1
8000f32: 801a strh r2, [r3, #0]
8000f34: 2314 movs r3, #20
8000f36: 18fa adds r2, r7, r3
8000f38: 1d3b adds r3, r7, #4
8000f3a: 8812 ldrh r2, [r2, #0]
8000f3c: 881b ldrh r3, [r3, #0]
8000f3e: 429a cmp r2, r3
8000f40: d3ce bcc.n 8000ee0 <Modbus_HandleFunction03+0x88>
}
uint16_t crc = CalculateCRC(response, index);
8000f42: 2610 movs r6, #16
8000f44: 19bc adds r4, r7, r6
8000f46: 2517 movs r5, #23
8000f48: 197b adds r3, r7, r5
8000f4a: 781a ldrb r2, [r3, #0]
8000f4c: 4b15 ldr r3, [pc, #84] ; (8000fa4 <Modbus_HandleFunction03+0x14c>)
8000f4e: 0011 movs r1, r2
8000f50: 0018 movs r0, r3
8000f52: f000 fa0b bl 800136c <CalculateCRC>
8000f56: 0003 movs r3, r0
8000f58: 8023 strh r3, [r4, #0]
response[index++] = (uint8_t)(crc & 0xFF);
8000f5a: 0028 movs r0, r5
8000f5c: 183b adds r3, r7, r0
8000f5e: 781b ldrb r3, [r3, #0]
8000f60: 183a adds r2, r7, r0
8000f62: 1c59 adds r1, r3, #1
8000f64: 7011 strb r1, [r2, #0]
8000f66: 001a movs r2, r3
8000f68: 19bb adds r3, r7, r6
8000f6a: 881b ldrh r3, [r3, #0]
8000f6c: b2d9 uxtb r1, r3
8000f6e: 4b0d ldr r3, [pc, #52] ; (8000fa4 <Modbus_HandleFunction03+0x14c>)
8000f70: 5499 strb r1, [r3, r2]
response[index++] = (uint8_t)((crc >> 8) & 0xFF);
8000f72: 19bb adds r3, r7, r6
8000f74: 881b ldrh r3, [r3, #0]
8000f76: 0a1b lsrs r3, r3, #8
8000f78: b299 uxth r1, r3
8000f7a: 183b adds r3, r7, r0
8000f7c: 781b ldrb r3, [r3, #0]
8000f7e: 0004 movs r4, r0
8000f80: 183a adds r2, r7, r0
8000f82: 1c58 adds r0, r3, #1
8000f84: 7010 strb r0, [r2, #0]
8000f86: 001a movs r2, r3
8000f88: b2c9 uxtb r1, r1
8000f8a: 4b06 ldr r3, [pc, #24] ; (8000fa4 <Modbus_HandleFunction03+0x14c>)
8000f8c: 5499 strb r1, [r3, r2]
Modbus_SendResponse(response, index);
8000f8e: 193b adds r3, r7, r4
8000f90: 781a ldrb r2, [r3, #0]
8000f92: 4b04 ldr r3, [pc, #16] ; (8000fa4 <Modbus_HandleFunction03+0x14c>)
8000f94: 0011 movs r1, r2
8000f96: 0018 movs r0, r3
8000f98: f000 f9cc bl 8001334 <Modbus_SendResponse>
}
8000f9c: 46bd mov sp, r7
8000f9e: b007 add sp, #28
8000fa0: bdf0 pop {r4, r5, r6, r7, pc}
8000fa2: 46c0 nop ; (mov r8, r8)
8000fa4: 200001c4 .word 0x200001c4
8000fa8: 200000a4 .word 0x200000a4
08000fac <Modbus_HandleFunction06>:
/* 处理功能码06 */
void Modbus_HandleFunction06(uint16_t registerAddress, uint16_t value)
{
8000fac: b5f0 push {r4, r5, r6, r7, lr}
8000fae: b085 sub sp, #20
8000fb0: af00 add r7, sp, #0
8000fb2: 0002 movs r2, r0
8000fb4: 1dbb adds r3, r7, #6
8000fb6: 801a strh r2, [r3, #0]
8000fb8: 1d3b adds r3, r7, #4
8000fba: 1c0a adds r2, r1, #0
8000fbc: 801a strh r2, [r3, #0]
/* 检查地址是否合法 */
if (registerAddress >= (REGISTER_START_ADDRESS + REGISTER_COUNT))
8000fbe: 1dbb adds r3, r7, #6
8000fc0: 881b ldrh r3, [r3, #0]
8000fc2: 2b09 cmp r3, #9
8000fc4: d903 bls.n 8000fce <Modbus_HandleFunction06+0x22>
{
Modbus_SendExceptionResponse(0x02);
8000fc6: 2002 movs r0, #2
8000fc8: f000 f97c bl 80012c4 <Modbus_SendExceptionResponse>
return;
8000fcc: e096 b.n 80010fc <Modbus_HandleFunction06+0x150>
}
uint16_t regIndex = registerAddress - REGISTER_START_ADDRESS;
8000fce: 210c movs r1, #12
8000fd0: 187b adds r3, r7, r1
8000fd2: 1dba adds r2, r7, #6
8000fd4: 8812 ldrh r2, [r2, #0]
8000fd6: 801a strh r2, [r3, #0]
uint16_t responseValue = holdingRegisters[regIndex];
8000fd8: 187b adds r3, r7, r1
8000fda: 881a ldrh r2, [r3, #0]
8000fdc: 4b49 ldr r3, [pc, #292] ; (8001104 <Modbus_HandleFunction06+0x158>)
8000fde: 0052 lsls r2, r2, #1
8000fe0: 5ed2 ldrsh r2, [r2, r3]
8000fe2: 200e movs r0, #14
8000fe4: 183b adds r3, r7, r0
8000fe6: 801a strh r2, [r3, #0]
/* 只有可写寄存器才更新值 */
if (registerWritable[regIndex] == 1)
8000fe8: 187b adds r3, r7, r1
8000fea: 881b ldrh r3, [r3, #0]
8000fec: 4a46 ldr r2, [pc, #280] ; (8001108 <Modbus_HandleFunction06+0x15c>)
8000fee: 5cd3 ldrb r3, [r2, r3]
8000ff0: 2b01 cmp r3, #1
8000ff2: d10b bne.n 800100c <Modbus_HandleFunction06+0x60>
{
holdingRegisters[regIndex] = value;
8000ff4: 187b adds r3, r7, r1
8000ff6: 881a ldrh r2, [r3, #0]
8000ff8: 1d3b adds r3, r7, #4
8000ffa: 2100 movs r1, #0
8000ffc: 5e59 ldrsh r1, [r3, r1]
8000ffe: 4b41 ldr r3, [pc, #260] ; (8001104 <Modbus_HandleFunction06+0x158>)
8001000: 0052 lsls r2, r2, #1
8001002: 52d1 strh r1, [r2, r3]
responseValue = value;
8001004: 183b adds r3, r7, r0
8001006: 1d3a adds r2, r7, #4
8001008: 8812 ldrh r2, [r2, #0]
800100a: 801a strh r2, [r3, #0]
}
/* 准备响应帧 - 功能码06的响应是原请求帧的原样返回 */
uint8_t index = 0;
800100c: 200b movs r0, #11
800100e: 183b adds r3, r7, r0
8001010: 2200 movs r2, #0
8001012: 701a strb r2, [r3, #0]
response[index++] = MODBUS_SLAVE_ADDRESS;
8001014: 183b adds r3, r7, r0
8001016: 781b ldrb r3, [r3, #0]
8001018: 183a adds r2, r7, r0
800101a: 1c59 adds r1, r3, #1
800101c: 7011 strb r1, [r2, #0]
800101e: 001a movs r2, r3
8001020: 4b3a ldr r3, [pc, #232] ; (800110c <Modbus_HandleFunction06+0x160>)
8001022: 2142 movs r1, #66 ; 0x42
8001024: 5499 strb r1, [r3, r2]
response[index++] = MODBUS_FUNCTION_CODE_06;
8001026: 183b adds r3, r7, r0
8001028: 781b ldrb r3, [r3, #0]
800102a: 183a adds r2, r7, r0
800102c: 1c59 adds r1, r3, #1
800102e: 7011 strb r1, [r2, #0]
8001030: 001a movs r2, r3
8001032: 4b36 ldr r3, [pc, #216] ; (800110c <Modbus_HandleFunction06+0x160>)
8001034: 2106 movs r1, #6
8001036: 5499 strb r1, [r3, r2]
response[index++] = (uint8_t)((registerAddress >> 8) & 0xFF);
8001038: 1dbb adds r3, r7, #6
800103a: 881b ldrh r3, [r3, #0]
800103c: 0a1b lsrs r3, r3, #8
800103e: b299 uxth r1, r3
8001040: 183b adds r3, r7, r0
8001042: 781b ldrb r3, [r3, #0]
8001044: 0004 movs r4, r0
8001046: 183a adds r2, r7, r0
8001048: 1c58 adds r0, r3, #1
800104a: 7010 strb r0, [r2, #0]
800104c: 001a movs r2, r3
800104e: b2c9 uxtb r1, r1
8001050: 4b2e ldr r3, [pc, #184] ; (800110c <Modbus_HandleFunction06+0x160>)
8001052: 5499 strb r1, [r3, r2]
response[index++] = (uint8_t)(registerAddress & 0xFF);
8001054: 0020 movs r0, r4
8001056: 183b adds r3, r7, r0
8001058: 781b ldrb r3, [r3, #0]
800105a: 183a adds r2, r7, r0
800105c: 1c59 adds r1, r3, #1
800105e: 7011 strb r1, [r2, #0]
8001060: 001a movs r2, r3
8001062: 1dbb adds r3, r7, #6
8001064: 881b ldrh r3, [r3, #0]
8001066: b2d9 uxtb r1, r3
8001068: 4b28 ldr r3, [pc, #160] ; (800110c <Modbus_HandleFunction06+0x160>)
800106a: 5499 strb r1, [r3, r2]
response[index++] = (uint8_t)((responseValue >> 8) & 0xFF);
800106c: 250e movs r5, #14
800106e: 197b adds r3, r7, r5
8001070: 881b ldrh r3, [r3, #0]
8001072: 0a1b lsrs r3, r3, #8
8001074: b299 uxth r1, r3
8001076: 183b adds r3, r7, r0
8001078: 781b ldrb r3, [r3, #0]
800107a: 0004 movs r4, r0
800107c: 183a adds r2, r7, r0
800107e: 1c58 adds r0, r3, #1
8001080: 7010 strb r0, [r2, #0]
8001082: 001a movs r2, r3
8001084: b2c9 uxtb r1, r1
8001086: 4b21 ldr r3, [pc, #132] ; (800110c <Modbus_HandleFunction06+0x160>)
8001088: 5499 strb r1, [r3, r2]
response[index++] = (uint8_t)(responseValue & 0xFF);
800108a: 0020 movs r0, r4
800108c: 183b adds r3, r7, r0
800108e: 781b ldrb r3, [r3, #0]
8001090: 183a adds r2, r7, r0
8001092: 1c59 adds r1, r3, #1
8001094: 7011 strb r1, [r2, #0]
8001096: 001a movs r2, r3
8001098: 197b adds r3, r7, r5
800109a: 881b ldrh r3, [r3, #0]
800109c: b2d9 uxtb r1, r3
800109e: 4b1b ldr r3, [pc, #108] ; (800110c <Modbus_HandleFunction06+0x160>)
80010a0: 5499 strb r1, [r3, r2]
/* 计算CRC并添加到响应帧 */
uint16_t crc = CalculateCRC(response, index);
80010a2: 2608 movs r6, #8
80010a4: 19bc adds r4, r7, r6
80010a6: 0005 movs r5, r0
80010a8: 183b adds r3, r7, r0
80010aa: 781a ldrb r2, [r3, #0]
80010ac: 4b17 ldr r3, [pc, #92] ; (800110c <Modbus_HandleFunction06+0x160>)
80010ae: 0011 movs r1, r2
80010b0: 0018 movs r0, r3
80010b2: f000 f95b bl 800136c <CalculateCRC>
80010b6: 0003 movs r3, r0
80010b8: 8023 strh r3, [r4, #0]
response[index++] = (uint8_t)(crc & 0xFF);
80010ba: 0028 movs r0, r5
80010bc: 183b adds r3, r7, r0
80010be: 781b ldrb r3, [r3, #0]
80010c0: 183a adds r2, r7, r0
80010c2: 1c59 adds r1, r3, #1
80010c4: 7011 strb r1, [r2, #0]
80010c6: 001a movs r2, r3
80010c8: 19bb adds r3, r7, r6
80010ca: 881b ldrh r3, [r3, #0]
80010cc: b2d9 uxtb r1, r3
80010ce: 4b0f ldr r3, [pc, #60] ; (800110c <Modbus_HandleFunction06+0x160>)
80010d0: 5499 strb r1, [r3, r2]
response[index++] = (uint8_t)((crc >> 8) & 0xFF);
80010d2: 19bb adds r3, r7, r6
80010d4: 881b ldrh r3, [r3, #0]
80010d6: 0a1b lsrs r3, r3, #8
80010d8: b299 uxth r1, r3
80010da: 183b adds r3, r7, r0
80010dc: 781b ldrb r3, [r3, #0]
80010de: 0004 movs r4, r0
80010e0: 183a adds r2, r7, r0
80010e2: 1c58 adds r0, r3, #1
80010e4: 7010 strb r0, [r2, #0]
80010e6: 001a movs r2, r3
80010e8: b2c9 uxtb r1, r1
80010ea: 4b08 ldr r3, [pc, #32] ; (800110c <Modbus_HandleFunction06+0x160>)
80010ec: 5499 strb r1, [r3, r2]
/* 发送响应 */
Modbus_SendResponse(response, index);
80010ee: 193b adds r3, r7, r4
80010f0: 781a ldrb r2, [r3, #0]
80010f2: 4b06 ldr r3, [pc, #24] ; (800110c <Modbus_HandleFunction06+0x160>)
80010f4: 0011 movs r1, r2
80010f6: 0018 movs r0, r3
80010f8: f000 f91c bl 8001334 <Modbus_SendResponse>
}
80010fc: 46bd mov sp, r7
80010fe: b005 add sp, #20
8001100: bdf0 pop {r4, r5, r6, r7, pc}
8001102: 46c0 nop ; (mov r8, r8)
8001104: 200000a4 .word 0x200000a4
8001108: 20000000 .word 0x20000000
800110c: 200001c4 .word 0x200001c4
08001110 <Modbus_HandleFunction10>:
/* 处理功能码0x10 */
void Modbus_HandleFunction10(uint16_t startAddress, uint16_t registerCount, uint8_t *data)
{
8001110: b5f0 push {r4, r5, r6, r7, lr}
8001112: b087 sub sp, #28
8001114: af00 add r7, sp, #0
8001116: 603a str r2, [r7, #0]
8001118: 1dbb adds r3, r7, #6
800111a: 1c02 adds r2, r0, #0
800111c: 801a strh r2, [r3, #0]
800111e: 1d3b adds r3, r7, #4
8001120: 1c0a adds r2, r1, #0
8001122: 801a strh r2, [r3, #0]
/* 检查地址和数量是否合法 */
if ((startAddress + registerCount) > (REGISTER_START_ADDRESS + REGISTER_COUNT) ||
8001124: 1dbb adds r3, r7, #6
8001126: 881a ldrh r2, [r3, #0]
8001128: 1d3b adds r3, r7, #4
800112a: 881b ldrh r3, [r3, #0]
800112c: 18d3 adds r3, r2, r3
800112e: 2b0a cmp r3, #10
8001130: dc07 bgt.n 8001142 <Modbus_HandleFunction10+0x32>
8001132: 1d3b adds r3, r7, #4
8001134: 881b ldrh r3, [r3, #0]
8001136: 2b00 cmp r3, #0
8001138: d003 beq.n 8001142 <Modbus_HandleFunction10+0x32>
registerCount == 0 || registerCount > 0x7B)
800113a: 1d3b adds r3, r7, #4
800113c: 881b ldrh r3, [r3, #0]
800113e: 2b7b cmp r3, #123 ; 0x7b
8001140: d903 bls.n 800114a <Modbus_HandleFunction10+0x3a>
{
Modbus_SendExceptionResponse(0x02);
8001142: 2002 movs r0, #2
8001144: f000 f8be bl 80012c4 <Modbus_SendExceptionResponse>
return;
8001148: e0b3 b.n 80012b2 <Modbus_HandleFunction10+0x1a2>
}
/* 处理每个寄存器 */
for (uint16_t i = 0; i < registerCount; i++)
800114a: 2316 movs r3, #22
800114c: 18fb adds r3, r7, r3
800114e: 2200 movs r2, #0
8001150: 801a strh r2, [r3, #0]
8001152: e030 b.n 80011b6 <Modbus_HandleFunction10+0xa6>
{
uint16_t regIndex = (startAddress - REGISTER_START_ADDRESS) + i;
8001154: 2010 movs r0, #16
8001156: 183b adds r3, r7, r0
8001158: 1db9 adds r1, r7, #6
800115a: 2416 movs r4, #22
800115c: 193a adds r2, r7, r4
800115e: 8809 ldrh r1, [r1, #0]
8001160: 8812 ldrh r2, [r2, #0]
8001162: 188a adds r2, r1, r2
8001164: 801a strh r2, [r3, #0]
int16_t value = (int16_t)((data[i * 2] << 8) | data[i * 2 + 1]);
8001166: 193b adds r3, r7, r4
8001168: 881b ldrh r3, [r3, #0]
800116a: 005b lsls r3, r3, #1
800116c: 001a movs r2, r3
800116e: 683b ldr r3, [r7, #0]
8001170: 189b adds r3, r3, r2
8001172: 781b ldrb r3, [r3, #0]
8001174: 021b lsls r3, r3, #8
8001176: b219 sxth r1, r3
8001178: 193b adds r3, r7, r4
800117a: 881b ldrh r3, [r3, #0]
800117c: 005b lsls r3, r3, #1
800117e: 3301 adds r3, #1
8001180: 683a ldr r2, [r7, #0]
8001182: 18d3 adds r3, r2, r3
8001184: 781b ldrb r3, [r3, #0]
8001186: b21a sxth r2, r3
8001188: 240e movs r4, #14
800118a: 193b adds r3, r7, r4
800118c: 430a orrs r2, r1
800118e: 801a strh r2, [r3, #0]
/* 只有可写寄存器才更新值 */
if (registerWritable[regIndex] == 1)
8001190: 183b adds r3, r7, r0
8001192: 881b ldrh r3, [r3, #0]
8001194: 4a48 ldr r2, [pc, #288] ; (80012b8 <Modbus_HandleFunction10+0x1a8>)
8001196: 5cd3 ldrb r3, [r2, r3]
8001198: 2b01 cmp r3, #1
800119a: d106 bne.n 80011aa <Modbus_HandleFunction10+0x9a>
{
holdingRegisters[regIndex] = value;
800119c: 183b adds r3, r7, r0
800119e: 881a ldrh r2, [r3, #0]
80011a0: 4b46 ldr r3, [pc, #280] ; (80012bc <Modbus_HandleFunction10+0x1ac>)
80011a2: 0052 lsls r2, r2, #1
80011a4: 1939 adds r1, r7, r4
80011a6: 8809 ldrh r1, [r1, #0]
80011a8: 52d1 strh r1, [r2, r3]
for (uint16_t i = 0; i < registerCount; i++)
80011aa: 2116 movs r1, #22
80011ac: 187b adds r3, r7, r1
80011ae: 881a ldrh r2, [r3, #0]
80011b0: 187b adds r3, r7, r1
80011b2: 3201 adds r2, #1
80011b4: 801a strh r2, [r3, #0]
80011b6: 2316 movs r3, #22
80011b8: 18fa adds r2, r7, r3
80011ba: 1d3b adds r3, r7, #4
80011bc: 8812 ldrh r2, [r2, #0]
80011be: 881b ldrh r3, [r3, #0]
80011c0: 429a cmp r2, r3
80011c2: d3c7 bcc.n 8001154 <Modbus_HandleFunction10+0x44>
}
}
/* 准备响应帧 - 功能码0x10的响应包含起始地址和写入数量 */
uint8_t index = 0;
80011c4: 2015 movs r0, #21
80011c6: 183b adds r3, r7, r0
80011c8: 2200 movs r2, #0
80011ca: 701a strb r2, [r3, #0]
response[index++] = MODBUS_SLAVE_ADDRESS;
80011cc: 183b adds r3, r7, r0
80011ce: 781b ldrb r3, [r3, #0]
80011d0: 183a adds r2, r7, r0
80011d2: 1c59 adds r1, r3, #1
80011d4: 7011 strb r1, [r2, #0]
80011d6: 001a movs r2, r3
80011d8: 4b39 ldr r3, [pc, #228] ; (80012c0 <Modbus_HandleFunction10+0x1b0>)
80011da: 2142 movs r1, #66 ; 0x42
80011dc: 5499 strb r1, [r3, r2]
response[index++] = MODBUS_FUNCTION_CODE_10;
80011de: 183b adds r3, r7, r0
80011e0: 781b ldrb r3, [r3, #0]
80011e2: 183a adds r2, r7, r0
80011e4: 1c59 adds r1, r3, #1
80011e6: 7011 strb r1, [r2, #0]
80011e8: 001a movs r2, r3
80011ea: 4b35 ldr r3, [pc, #212] ; (80012c0 <Modbus_HandleFunction10+0x1b0>)
80011ec: 2110 movs r1, #16
80011ee: 5499 strb r1, [r3, r2]
response[index++] = (uint8_t)((startAddress >> 8) & 0xFF);
80011f0: 1dbb adds r3, r7, #6
80011f2: 881b ldrh r3, [r3, #0]
80011f4: 0a1b lsrs r3, r3, #8
80011f6: b299 uxth r1, r3
80011f8: 183b adds r3, r7, r0
80011fa: 781b ldrb r3, [r3, #0]
80011fc: 0004 movs r4, r0
80011fe: 183a adds r2, r7, r0
8001200: 1c58 adds r0, r3, #1
8001202: 7010 strb r0, [r2, #0]
8001204: 001a movs r2, r3
8001206: b2c9 uxtb r1, r1
8001208: 4b2d ldr r3, [pc, #180] ; (80012c0 <Modbus_HandleFunction10+0x1b0>)
800120a: 5499 strb r1, [r3, r2]
response[index++] = (uint8_t)(startAddress & 0xFF);
800120c: 0020 movs r0, r4
800120e: 183b adds r3, r7, r0
8001210: 781b ldrb r3, [r3, #0]
8001212: 183a adds r2, r7, r0
8001214: 1c59 adds r1, r3, #1
8001216: 7011 strb r1, [r2, #0]
8001218: 001a movs r2, r3
800121a: 1dbb adds r3, r7, #6
800121c: 881b ldrh r3, [r3, #0]
800121e: b2d9 uxtb r1, r3
8001220: 4b27 ldr r3, [pc, #156] ; (80012c0 <Modbus_HandleFunction10+0x1b0>)
8001222: 5499 strb r1, [r3, r2]
response[index++] = (uint8_t)((registerCount >> 8) & 0xFF);
8001224: 1d3b adds r3, r7, #4
8001226: 881b ldrh r3, [r3, #0]
8001228: 0a1b lsrs r3, r3, #8
800122a: b299 uxth r1, r3
800122c: 183b adds r3, r7, r0
800122e: 781b ldrb r3, [r3, #0]
8001230: 0004 movs r4, r0
8001232: 183a adds r2, r7, r0
8001234: 1c58 adds r0, r3, #1
8001236: 7010 strb r0, [r2, #0]
8001238: 001a movs r2, r3
800123a: b2c9 uxtb r1, r1
800123c: 4b20 ldr r3, [pc, #128] ; (80012c0 <Modbus_HandleFunction10+0x1b0>)
800123e: 5499 strb r1, [r3, r2]
response[index++] = (uint8_t)(registerCount & 0xFF);
8001240: 0020 movs r0, r4
8001242: 183b adds r3, r7, r0
8001244: 781b ldrb r3, [r3, #0]
8001246: 183a adds r2, r7, r0
8001248: 1c59 adds r1, r3, #1
800124a: 7011 strb r1, [r2, #0]
800124c: 001a movs r2, r3
800124e: 1d3b adds r3, r7, #4
8001250: 881b ldrh r3, [r3, #0]
8001252: b2d9 uxtb r1, r3
8001254: 4b1a ldr r3, [pc, #104] ; (80012c0 <Modbus_HandleFunction10+0x1b0>)
8001256: 5499 strb r1, [r3, r2]
/* 计算CRC并添加到响应帧 */
uint16_t crc = CalculateCRC(response, index);
8001258: 2612 movs r6, #18
800125a: 19bc adds r4, r7, r6
800125c: 0005 movs r5, r0
800125e: 183b adds r3, r7, r0
8001260: 781a ldrb r2, [r3, #0]
8001262: 4b17 ldr r3, [pc, #92] ; (80012c0 <Modbus_HandleFunction10+0x1b0>)
8001264: 0011 movs r1, r2
8001266: 0018 movs r0, r3
8001268: f000 f880 bl 800136c <CalculateCRC>
800126c: 0003 movs r3, r0
800126e: 8023 strh r3, [r4, #0]
response[index++] = (uint8_t)(crc & 0xFF);
8001270: 0028 movs r0, r5
8001272: 183b adds r3, r7, r0
8001274: 781b ldrb r3, [r3, #0]
8001276: 183a adds r2, r7, r0
8001278: 1c59 adds r1, r3, #1
800127a: 7011 strb r1, [r2, #0]
800127c: 001a movs r2, r3
800127e: 19bb adds r3, r7, r6
8001280: 881b ldrh r3, [r3, #0]
8001282: b2d9 uxtb r1, r3
8001284: 4b0e ldr r3, [pc, #56] ; (80012c0 <Modbus_HandleFunction10+0x1b0>)
8001286: 5499 strb r1, [r3, r2]
response[index++] = (uint8_t)((crc >> 8) & 0xFF);
8001288: 19bb adds r3, r7, r6
800128a: 881b ldrh r3, [r3, #0]
800128c: 0a1b lsrs r3, r3, #8
800128e: b299 uxth r1, r3
8001290: 183b adds r3, r7, r0
8001292: 781b ldrb r3, [r3, #0]
8001294: 0004 movs r4, r0
8001296: 183a adds r2, r7, r0
8001298: 1c58 adds r0, r3, #1
800129a: 7010 strb r0, [r2, #0]
800129c: 001a movs r2, r3
800129e: b2c9 uxtb r1, r1
80012a0: 4b07 ldr r3, [pc, #28] ; (80012c0 <Modbus_HandleFunction10+0x1b0>)
80012a2: 5499 strb r1, [r3, r2]
/* 发送响应 */
Modbus_SendResponse(response, index);
80012a4: 193b adds r3, r7, r4
80012a6: 781a ldrb r2, [r3, #0]
80012a8: 4b05 ldr r3, [pc, #20] ; (80012c0 <Modbus_HandleFunction10+0x1b0>)
80012aa: 0011 movs r1, r2
80012ac: 0018 movs r0, r3
80012ae: f000 f841 bl 8001334 <Modbus_SendResponse>
}
80012b2: 46bd mov sp, r7
80012b4: b007 add sp, #28
80012b6: bdf0 pop {r4, r5, r6, r7, pc}
80012b8: 20000000 .word 0x20000000
80012bc: 200000a4 .word 0x200000a4
80012c0: 200001c4 .word 0x200001c4
080012c4 <Modbus_SendExceptionResponse>:
/* 发送异常响应 */
void Modbus_SendExceptionResponse(uint8_t exceptionCode)
{
80012c4: b5b0 push {r4, r5, r7, lr}
80012c6: b084 sub sp, #16
80012c8: af00 add r7, sp, #0
80012ca: 0002 movs r2, r0
80012cc: 1dfb adds r3, r7, #7
80012ce: 701a strb r2, [r3, #0]
response[0] = MODBUS_SLAVE_ADDRESS;
80012d0: 4b16 ldr r3, [pc, #88] ; (800132c <Modbus_SendExceptionResponse+0x68>)
80012d2: 2242 movs r2, #66 ; 0x42
80012d4: 701a strb r2, [r3, #0]
response[1] = modbusBuffer[1] | 0x80;
80012d6: 4b16 ldr r3, [pc, #88] ; (8001330 <Modbus_SendExceptionResponse+0x6c>)
80012d8: 785b ldrb r3, [r3, #1]
80012da: 2280 movs r2, #128 ; 0x80
80012dc: 4252 negs r2, r2
80012de: 4313 orrs r3, r2
80012e0: b2da uxtb r2, r3
80012e2: 4b12 ldr r3, [pc, #72] ; (800132c <Modbus_SendExceptionResponse+0x68>)
80012e4: 705a strb r2, [r3, #1]
response[2] = exceptionCode;
80012e6: 4b11 ldr r3, [pc, #68] ; (800132c <Modbus_SendExceptionResponse+0x68>)
80012e8: 1dfa adds r2, r7, #7
80012ea: 7812 ldrb r2, [r2, #0]
80012ec: 709a strb r2, [r3, #2]
uint16_t crc = CalculateCRC(response, 3);
80012ee: 250e movs r5, #14
80012f0: 197c adds r4, r7, r5
80012f2: 4b0e ldr r3, [pc, #56] ; (800132c <Modbus_SendExceptionResponse+0x68>)
80012f4: 2103 movs r1, #3
80012f6: 0018 movs r0, r3
80012f8: f000 f838 bl 800136c <CalculateCRC>
80012fc: 0003 movs r3, r0
80012fe: 8023 strh r3, [r4, #0]
response[3] = (uint8_t)(crc & 0xFF);
8001300: 0029 movs r1, r5
8001302: 187b adds r3, r7, r1
8001304: 881b ldrh r3, [r3, #0]
8001306: b2da uxtb r2, r3
8001308: 4b08 ldr r3, [pc, #32] ; (800132c <Modbus_SendExceptionResponse+0x68>)
800130a: 70da strb r2, [r3, #3]
response[4] = (uint8_t)((crc >> 8) & 0xFF);
800130c: 187b adds r3, r7, r1
800130e: 881b ldrh r3, [r3, #0]
8001310: 0a1b lsrs r3, r3, #8
8001312: b29b uxth r3, r3
8001314: b2da uxtb r2, r3
8001316: 4b05 ldr r3, [pc, #20] ; (800132c <Modbus_SendExceptionResponse+0x68>)
8001318: 711a strb r2, [r3, #4]
Modbus_SendResponse(response, 5);
800131a: 4b04 ldr r3, [pc, #16] ; (800132c <Modbus_SendExceptionResponse+0x68>)
800131c: 2105 movs r1, #5
800131e: 0018 movs r0, r3
8001320: f000 f808 bl 8001334 <Modbus_SendResponse>
}
8001324: 46c0 nop ; (mov r8, r8)
8001326: 46bd mov sp, r7
8001328: b004 add sp, #16
800132a: bdb0 pop {r4, r5, r7, pc}
800132c: 200001c4 .word 0x200001c4
8001330: 200000b8 .word 0x200000b8
08001334 <Modbus_SendResponse>:
/* 发送响应 */
void Modbus_SendResponse(uint8_t *data, uint8_t length)
{
8001334: b580 push {r7, lr}
8001336: b082 sub sp, #8
8001338: af00 add r7, sp, #0
800133a: 6078 str r0, [r7, #4]
800133c: 000a movs r2, r1
800133e: 1cfb adds r3, r7, #3
8001340: 701a strb r2, [r3, #0]
/* 使能RS485发送 */
HAL_GPIO_WritePin(DIR_GPIO_Port, DIR_Pin, GPIO_PIN_SET);
8001342: 23a0 movs r3, #160 ; 0xa0
8001344: 05db lsls r3, r3, #23
8001346: 2201 movs r2, #1
8001348: 2110 movs r1, #16
800134a: 0018 movs r0, r3
800134c: f002 fa52 bl 80037f4 <HAL_GPIO_WritePin>
/* DMA 发送数据，发送完成后在 HAL_UART_TxCpltCallback 中切回接收 */
HAL_UART_Transmit_DMA(&huart2, data, length);
8001350: 1cfb adds r3, r7, #3
8001352: 781b ldrb r3, [r3, #0]
8001354: b29a uxth r2, r3
8001356: 6879 ldr r1, [r7, #4]
8001358: 4b03 ldr r3, [pc, #12] ; (8001368 <Modbus_SendResponse+0x34>)
800135a: 0018 movs r0, r3
800135c: f004 f8d2 bl 8005504 <HAL_UART_Transmit_DMA>
}
8001360: 46c0 nop ; (mov r8, r8)
8001362: 46bd mov sp, r7
8001364: b002 add sp, #8
8001366: bd80 pop {r7, pc}
8001368: 20000360 .word 0x20000360
0800136c <CalculateCRC>:
/* CRC计算 */
uint16_t CalculateCRC(uint8_t *data, uint8_t length)
{
800136c: b580 push {r7, lr}
800136e: b084 sub sp, #16
8001370: af00 add r7, sp, #0
8001372: 6078 str r0, [r7, #4]
8001374: 000a movs r2, r1
8001376: 1cfb adds r3, r7, #3
8001378: 701a strb r2, [r3, #0]
uint16_t crc = 0xFFFF;
800137a: 230e movs r3, #14
800137c: 18fb adds r3, r7, r3
800137e: 2201 movs r2, #1
8001380: 4252 negs r2, r2
8001382: 801a strh r2, [r3, #0]
for (uint8_t i = 0; i < length; i++)
8001384: 230d movs r3, #13
8001386: 18fb adds r3, r7, r3
8001388: 2200 movs r2, #0
800138a: 701a strb r2, [r3, #0]
800138c: e03a b.n 8001404 <CalculateCRC+0x98>
{
crc ^= (uint16_t)data[i];
800138e: 230d movs r3, #13
8001390: 18fb adds r3, r7, r3
8001392: 781b ldrb r3, [r3, #0]
8001394: 687a ldr r2, [r7, #4]
8001396: 18d3 adds r3, r2, r3
8001398: 781b ldrb r3, [r3, #0]
800139a: b299 uxth r1, r3
800139c: 220e movs r2, #14
800139e: 18bb adds r3, r7, r2
80013a0: 18ba adds r2, r7, r2
80013a2: 8812 ldrh r2, [r2, #0]
80013a4: 404a eors r2, r1
80013a6: 801a strh r2, [r3, #0]
for (uint8_t j = 0; j < 8; j++)
80013a8: 230c movs r3, #12
80013aa: 18fb adds r3, r7, r3
80013ac: 2200 movs r2, #0
80013ae: 701a strb r2, [r3, #0]
80013b0: e01d b.n 80013ee <CalculateCRC+0x82>
{
if ((crc & 0x0001) != 0)
80013b2: 210e movs r1, #14
80013b4: 187b adds r3, r7, r1
80013b6: 881b ldrh r3, [r3, #0]
80013b8: 2201 movs r2, #1
80013ba: 4013 ands r3, r2
80013bc: d00b beq.n 80013d6 <CalculateCRC+0x6a>
{
crc >>= 1;
80013be: 187b adds r3, r7, r1
80013c0: 187a adds r2, r7, r1
80013c2: 8812 ldrh r2, [r2, #0]
80013c4: 0852 lsrs r2, r2, #1
80013c6: 801a strh r2, [r3, #0]
crc ^= 0xA001;
80013c8: 187b adds r3, r7, r1
80013ca: 187a adds r2, r7, r1
80013cc: 8812 ldrh r2, [r2, #0]
80013ce: 4914 ldr r1, [pc, #80] ; (8001420 <CalculateCRC+0xb4>)
80013d0: 404a eors r2, r1
80013d2: 801a strh r2, [r3, #0]
80013d4: e005 b.n 80013e2 <CalculateCRC+0x76>
}
else
{
crc >>= 1;
80013d6: 220e movs r2, #14
80013d8: 18bb adds r3, r7, r2
80013da: 18ba adds r2, r7, r2
80013dc: 8812 ldrh r2, [r2, #0]
80013de: 0852 lsrs r2, r2, #1
80013e0: 801a strh r2, [r3, #0]
for (uint8_t j = 0; j < 8; j++)
80013e2: 210c movs r1, #12
80013e4: 187b adds r3, r7, r1
80013e6: 781a ldrb r2, [r3, #0]
80013e8: 187b adds r3, r7, r1
80013ea: 3201 adds r2, #1
80013ec: 701a strb r2, [r3, #0]
80013ee: 230c movs r3, #12
80013f0: 18fb adds r3, r7, r3
80013f2: 781b ldrb r3, [r3, #0]
80013f4: 2b07 cmp r3, #7
80013f6: d9dc bls.n 80013b2 <CalculateCRC+0x46>
for (uint8_t i = 0; i < length; i++)
80013f8: 210d movs r1, #13
80013fa: 187b adds r3, r7, r1
80013fc: 781a ldrb r2, [r3, #0]
80013fe: 187b adds r3, r7, r1
8001400: 3201 adds r2, #1
8001402: 701a strb r2, [r3, #0]
8001404: 230d movs r3, #13
8001406: 18fa adds r2, r7, r3
8001408: 1cfb adds r3, r7, #3
800140a: 7812 ldrb r2, [r2, #0]
800140c: 781b ldrb r3, [r3, #0]
800140e: 429a cmp r2, r3
8001410: d3bd bcc.n 800138e <CalculateCRC+0x22>
}
}
}
return crc;
8001412: 230e movs r3, #14
8001414: 18fb adds r3, r7, r3
8001416: 881b ldrh r3, [r3, #0]
}
8001418: 0018 movs r0, r3
800141a: 46bd mov sp, r7
800141c: b004 add sp, #16
800141e: bd80 pop {r7, pc}
8001420: ffffa001 .word 0xffffa001
08001424 <HAL_UART_RxCpltCallback>:
/* UART接收中断回调函数 */
void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
{
8001424: b580 push {r7, lr}
8001426: b082 sub sp, #8
8001428: af00 add r7, sp, #0
800142a: 6078 str r0, [r7, #4]
if (huart != &huart2) // 忽略其他串口
800142c: 687a ldr r2, [r7, #4]
800142e: 4b14 ldr r3, [pc, #80] ; (8001480 <HAL_UART_RxCpltCallback+0x5c>)
8001430: 429a cmp r2, r3
8001432: d121 bne.n 8001478 <HAL_UART_RxCpltCallback+0x54>
return;
lastByteTime = HAL_GetTick(); // 更新最近一次接收时间
8001434: f000 fb8a bl 8001b4c <HAL_GetTick>
8001438: 0002 movs r2, r0
800143a: 4b12 ldr r3, [pc, #72] ; (8001484 <HAL_UART_RxCpltCallback+0x60>)
800143c: 601a str r2, [r3, #0]
if (modbusBufferIndex < MODBUS_BUFFER_SIZE) // 检查缓冲区是否还有空间
800143e: 4b12 ldr r3, [pc, #72] ; (8001488 <HAL_UART_RxCpltCallback+0x64>)
8001440: 881b ldrh r3, [r3, #0]
8001442: 2bff cmp r3, #255 ; 0xff
8001444: d80b bhi.n 800145e <HAL_UART_RxCpltCallback+0x3a>
{
modbusBuffer[modbusBufferIndex++] = rxByte; // 将收到的字节复制到正确的位置
8001446: 4b10 ldr r3, [pc, #64] ; (8001488 <HAL_UART_RxCpltCallback+0x64>)
8001448: 881b ldrh r3, [r3, #0]
800144a: 1c5a adds r2, r3, #1
800144c: b291 uxth r1, r2
800144e: 4a0e ldr r2, [pc, #56] ; (8001488 <HAL_UART_RxCpltCallback+0x64>)
8001450: 8011 strh r1, [r2, #0]
8001452: 001a movs r2, r3
8001454: 4b0d ldr r3, [pc, #52] ; (800148c <HAL_UART_RxCpltCallback+0x68>)
8001456: 7819 ldrb r1, [r3, #0]
8001458: 4b0d ldr r3, [pc, #52] ; (8001490 <HAL_UART_RxCpltCallback+0x6c>)
800145a: 5499 strb r1, [r3, r2]
800145c: e005 b.n 800146a <HAL_UART_RxCpltCallback+0x46>
}
else
{
modbusBufferIndex = 0; // 缓冲区溢出时丢弃当前帧
800145e: 4b0a ldr r3, [pc, #40] ; (8001488 <HAL_UART_RxCpltCallback+0x64>)
8001460: 2200 movs r2, #0
8001462: 801a strh r2, [r3, #0]
messageComplete = false; // 清除当前帧状态
8001464: 4b0b ldr r3, [pc, #44] ; (8001494 <HAL_UART_RxCpltCallback+0x70>)
8001466: 2200 movs r2, #0
8001468: 701a strb r2, [r3, #0]
}
HAL_UART_Receive_IT(&huart2, &rxByte, 1); // 继续接收下一个字节
800146a: 4908 ldr r1, [pc, #32] ; (800148c <HAL_UART_RxCpltCallback+0x68>)
800146c: 4b04 ldr r3, [pc, #16] ; (8001480 <HAL_UART_RxCpltCallback+0x5c>)
800146e: 2201 movs r2, #1
8001470: 0018 movs r0, r3
8001472: f003 ffdd bl 8005430 <HAL_UART_Receive_IT>
8001476: e000 b.n 800147a <HAL_UART_RxCpltCallback+0x56>
return;
8001478: 46c0 nop ; (mov r8, r8)
}
800147a: 46bd mov sp, r7
800147c: b002 add sp, #8
800147e: bd80 pop {r7, pc}
8001480: 20000360 .word 0x20000360
8001484: 200001bc .word 0x200001bc
8001488: 200001b8 .word 0x200001b8
800148c: 200002c4 .word 0x200002c4
8001490: 200000b8 .word 0x200000b8
8001494: 200001c0 .word 0x200001c0
08001498 <HAL_UART_TxCpltCallback>:
// }
//}
/* UART发送完成回调：切回RS485接收方向 */
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
{
8001498: b580 push {r7, lr}
800149a: b082 sub sp, #8
800149c: af00 add r7, sp, #0
800149e: 6078 str r0, [r7, #4]
if (huart == &huart2)
80014a0: 687a ldr r2, [r7, #4]
80014a2: 4b07 ldr r3, [pc, #28] ; (80014c0 <HAL_UART_TxCpltCallback+0x28>)
80014a4: 429a cmp r2, r3
80014a6: d106 bne.n 80014b6 <HAL_UART_TxCpltCallback+0x1e>
{
HAL_GPIO_WritePin(DIR_GPIO_Port, DIR_Pin, GPIO_PIN_RESET);
80014a8: 23a0 movs r3, #160 ; 0xa0
80014aa: 05db lsls r3, r3, #23
80014ac: 2200 movs r2, #0
80014ae: 2110 movs r1, #16
80014b0: 0018 movs r0, r3
80014b2: f002 f99f bl 80037f4 <HAL_GPIO_WritePin>
}
}
80014b6: 46c0 nop ; (mov r8, r8)
80014b8: 46bd mov sp, r7
80014ba: b002 add sp, #8
80014bc: bd80 pop {r7, pc}
80014be: 46c0 nop ; (mov r8, r8)
80014c0: 20000360 .word 0x20000360
080014c4 <HAL_UART_ErrorCallback>:
/* UART错误回调：重新同步接收 */
void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
{
80014c4: b580 push {r7, lr}
80014c6: b082 sub sp, #8
80014c8: af00 add r7, sp, #0
80014ca: 6078 str r0, [r7, #4]
if (huart == &huart2)
80014cc: 687a ldr r2, [r7, #4]
80014ce: 4b0a ldr r3, [pc, #40] ; (80014f8 <HAL_UART_ErrorCallback+0x34>)
80014d0: 429a cmp r2, r3
80014d2: d10c bne.n 80014ee <HAL_UART_ErrorCallback+0x2a>
{
modbusBufferIndex = 0;
80014d4: 4b09 ldr r3, [pc, #36] ; (80014fc <HAL_UART_ErrorCallback+0x38>)
80014d6: 2200 movs r2, #0
80014d8: 801a strh r2, [r3, #0]
HAL_UART_Receive_IT(&huart2, (uint8_t *)&modbusBuffer[modbusBufferIndex], 1);
80014da: 4b08 ldr r3, [pc, #32] ; (80014fc <HAL_UART_ErrorCallback+0x38>)
80014dc: 881b ldrh r3, [r3, #0]
80014de: 001a movs r2, r3
80014e0: 4b07 ldr r3, [pc, #28] ; (8001500 <HAL_UART_ErrorCallback+0x3c>)
80014e2: 18d1 adds r1, r2, r3
80014e4: 4b04 ldr r3, [pc, #16] ; (80014f8 <HAL_UART_ErrorCallback+0x34>)
80014e6: 2201 movs r2, #1
80014e8: 0018 movs r0, r3
80014ea: f003 ffa1 bl 8005430 <HAL_UART_Receive_IT>
}
}
80014ee: 46c0 nop ; (mov r8, r8)
80014f0: 46bd mov sp, r7
80014f2: b002 add sp, #8
80014f4: bd80 pop {r7, pc}
80014f6: 46c0 nop ; (mov r8, r8)
80014f8: 20000360 .word 0x20000360
80014fc: 200001b8 .word 0x200001b8
8001500: 200000b8 .word 0x200000b8
08001504 <HAL_MspInit>:
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
8001504: b580 push {r7, lr}
8001506: b082 sub sp, #8
8001508: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
800150a: 4b0f ldr r3, [pc, #60] ; (8001548 <HAL_MspInit+0x44>)
800150c: 6c1a ldr r2, [r3, #64] ; 0x40
800150e: 4b0e ldr r3, [pc, #56] ; (8001548 <HAL_MspInit+0x44>)
8001510: 2101 movs r1, #1
8001512: 430a orrs r2, r1
8001514: 641a str r2, [r3, #64] ; 0x40
8001516: 4b0c ldr r3, [pc, #48] ; (8001548 <HAL_MspInit+0x44>)
8001518: 6c1b ldr r3, [r3, #64] ; 0x40
800151a: 2201 movs r2, #1
800151c: 4013 ands r3, r2
800151e: 607b str r3, [r7, #4]
8001520: 687b ldr r3, [r7, #4]
__HAL_RCC_PWR_CLK_ENABLE();
8001522: 4b09 ldr r3, [pc, #36] ; (8001548 <HAL_MspInit+0x44>)
8001524: 6bda ldr r2, [r3, #60] ; 0x3c
8001526: 4b08 ldr r3, [pc, #32] ; (8001548 <HAL_MspInit+0x44>)
8001528: 2180 movs r1, #128 ; 0x80
800152a: 0549 lsls r1, r1, #21
800152c: 430a orrs r2, r1
800152e: 63da str r2, [r3, #60] ; 0x3c
8001530: 4b05 ldr r3, [pc, #20] ; (8001548 <HAL_MspInit+0x44>)
8001532: 6bda ldr r2, [r3, #60] ; 0x3c
8001534: 2380 movs r3, #128 ; 0x80
8001536: 055b lsls r3, r3, #21
8001538: 4013 ands r3, r2
800153a: 603b str r3, [r7, #0]
800153c: 683b ldr r3, [r7, #0]
/* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
800153e: 46c0 nop ; (mov r8, r8)
8001540: 46bd mov sp, r7
8001542: b002 add sp, #8
8001544: bd80 pop {r7, pc}
8001546: 46c0 nop ; (mov r8, r8)
8001548: 40021000 .word 0x40021000
0800154c <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
800154c: b580 push {r7, lr}
800154e: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
8001550: e7fe b.n 8001550 <NMI_Handler+0x4>
08001552 <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
8001552: b580 push {r7, lr}
8001554: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
8001556: e7fe b.n 8001556 <HardFault_Handler+0x4>
08001558 <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
8001558: b580 push {r7, lr}
800155a: af00 add r7, sp, #0
/* USER CODE END SVC_IRQn 0 */
/* USER CODE BEGIN SVC_IRQn 1 */
/* USER CODE END SVC_IRQn 1 */
}
800155c: 46c0 nop ; (mov r8, r8)
800155e: 46bd mov sp, r7
8001560: bd80 pop {r7, pc}
08001562 <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
8001562: b580 push {r7, lr}
8001564: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
8001566: 46c0 nop ; (mov r8, r8)
8001568: 46bd mov sp, r7
800156a: bd80 pop {r7, pc}
0800156c <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
800156c: b580 push {r7, lr}
800156e: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
8001570: f000 fada bl 8001b28 <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
8001574: 46c0 nop ; (mov r8, r8)
8001576: 46bd mov sp, r7
8001578: bd80 pop {r7, pc}
...
0800157c <DMA1_Channel1_IRQHandler>:
/**
* @brief This function handles DMA1 channel 1 interrupt.
*/
void DMA1_Channel1_IRQHandler(void)
{
800157c: b580 push {r7, lr}
800157e: af00 add r7, sp, #0
/* USER CODE BEGIN DMA1_Channel1_IRQn 0 */
/* USER CODE END DMA1_Channel1_IRQn 0 */
HAL_DMA_IRQHandler(&hdma_usart2_tx);
8001580: 4b03 ldr r3, [pc, #12] ; (8001590 <DMA1_Channel1_IRQHandler+0x14>)
8001582: 0018 movs r0, r3
8001584: f001 fe90 bl 80032a8 <HAL_DMA_IRQHandler>
/* USER CODE BEGIN DMA1_Channel1_IRQn 1 */
/* USER CODE END DMA1_Channel1_IRQn 1 */
}
8001588: 46c0 nop ; (mov r8, r8)
800158a: 46bd mov sp, r7
800158c: bd80 pop {r7, pc}
800158e: 46c0 nop ; (mov r8, r8)
8001590: 200003f0 .word 0x200003f0
08001594 <ADC1_IRQHandler>:
/**
* @brief This function handles ADC1 interrupt.
*/
void ADC1_IRQHandler(void)
{
8001594: b580 push {r7, lr}
8001596: af00 add r7, sp, #0
/* USER CODE BEGIN ADC1_IRQn 0 */
/* USER CODE END ADC1_IRQn 0 */
HAL_ADC_IRQHandler(&hadc1);
8001598: 4b03 ldr r3, [pc, #12] ; (80015a8 <ADC1_IRQHandler+0x14>)
800159a: 0018 movs r0, r3
800159c: f000 fe70 bl 8002280 <HAL_ADC_IRQHandler>
/* USER CODE BEGIN ADC1_IRQn 1 */
/* USER CODE END ADC1_IRQn 1 */
}
80015a0: 46c0 nop ; (mov r8, r8)
80015a2: 46bd mov sp, r7
80015a4: bd80 pop {r7, pc}
80015a6: 46c0 nop ; (mov r8, r8)
80015a8: 20000034 .word 0x20000034
080015ac <USART2_IRQHandler>:
/**
* @brief This function handles USART2 global interrupt / USART2 wake-up interrupt through EXTI line 26.
*/
void USART2_IRQHandler(void)
{
80015ac: b580 push {r7, lr}
80015ae: af00 add r7, sp, #0
/* USER CODE BEGIN USART2_IRQn 0 */
/* USER CODE END USART2_IRQn 0 */
HAL_UART_IRQHandler(&huart2);
80015b0: 4b03 ldr r3, [pc, #12] ; (80015c0 <USART2_IRQHandler+0x14>)
80015b2: 0018 movs r0, r3
80015b4: f004 f84c bl 8005650 <HAL_UART_IRQHandler>
/* USER CODE BEGIN USART2_IRQn 1 */
/* USER CODE END USART2_IRQn 1 */
}
80015b8: 46c0 nop ; (mov r8, r8)
80015ba: 46bd mov sp, r7
80015bc: bd80 pop {r7, pc}
80015be: 46c0 nop ; (mov r8, r8)
80015c0: 20000360 .word 0x20000360
080015c4 <SystemInit>:
* @brief Setup the microcontroller system.
* @param None
* @retval None
*/
void SystemInit(void)
{
80015c4: b580 push {r7, lr}
80015c6: af00 add r7, sp, #0
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation */
#endif /* USER_VECT_TAB_ADDRESS */
}
80015c8: 46c0 nop ; (mov r8, r8)
80015ca: 46bd mov sp, r7
80015cc: bd80 pop {r7, pc}
...
080015d0 <MX_TIM2_Init>:
TIM_HandleTypeDef htim2;
TIM_HandleTypeDef htim3;
/* TIM2 init function */
void MX_TIM2_Init(void)
{
80015d0: b590 push {r4, r7, lr}
80015d2: b08d sub sp, #52 ; 0x34
80015d4: af00 add r7, sp, #0
/* USER CODE BEGIN TIM2_Init 0 */
/* USER CODE END TIM2_Init 0 */
TIM_Encoder_InitTypeDef sConfig = {0};
80015d6: 240c movs r4, #12
80015d8: 193b adds r3, r7, r4
80015da: 0018 movs r0, r3
80015dc: 2324 movs r3, #36 ; 0x24
80015de: 001a movs r2, r3
80015e0: 2100 movs r1, #0
80015e2: f005 fee1 bl 80073a8 <memset>
TIM_MasterConfigTypeDef sMasterConfig = {0};
80015e6: 003b movs r3, r7
80015e8: 0018 movs r0, r3
80015ea: 230c movs r3, #12
80015ec: 001a movs r2, r3
80015ee: 2100 movs r1, #0
80015f0: f005 feda bl 80073a8 <memset>
/* USER CODE BEGIN TIM2_Init 1 */
/* USER CODE END TIM2_Init 1 */
htim2.Instance = TIM2;
80015f4: 4b26 ldr r3, [pc, #152] ; (8001690 <MX_TIM2_Init+0xc0>)
80015f6: 2280 movs r2, #128 ; 0x80
80015f8: 05d2 lsls r2, r2, #23
80015fa: 601a str r2, [r3, #0]
htim2.Init.Prescaler = 0;
80015fc: 4b24 ldr r3, [pc, #144] ; (8001690 <MX_TIM2_Init+0xc0>)
80015fe: 2200 movs r2, #0
8001600: 605a str r2, [r3, #4]
htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
8001602: 4b23 ldr r3, [pc, #140] ; (8001690 <MX_TIM2_Init+0xc0>)
8001604: 2200 movs r2, #0
8001606: 609a str r2, [r3, #8]
htim2.Init.Period = 4294967295;
8001608: 4b21 ldr r3, [pc, #132] ; (8001690 <MX_TIM2_Init+0xc0>)
800160a: 2201 movs r2, #1
800160c: 4252 negs r2, r2
800160e: 60da str r2, [r3, #12]
htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
8001610: 4b1f ldr r3, [pc, #124] ; (8001690 <MX_TIM2_Init+0xc0>)
8001612: 2200 movs r2, #0
8001614: 611a str r2, [r3, #16]
htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
8001616: 4b1e ldr r3, [pc, #120] ; (8001690 <MX_TIM2_Init+0xc0>)
8001618: 2200 movs r2, #0
800161a: 619a str r2, [r3, #24]
sConfig.EncoderMode = TIM_ENCODERMODE_TI12;
800161c: 0021 movs r1, r4
800161e: 187b adds r3, r7, r1
8001620: 2203 movs r2, #3
8001622: 601a str r2, [r3, #0]
sConfig.IC1Polarity = TIM_ICPOLARITY_RISING;
8001624: 187b adds r3, r7, r1
8001626: 2200 movs r2, #0
8001628: 605a str r2, [r3, #4]
sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI;
800162a: 187b adds r3, r7, r1
800162c: 2201 movs r2, #1
800162e: 609a str r2, [r3, #8]
sConfig.IC1Prescaler = TIM_ICPSC_DIV1;
8001630: 187b adds r3, r7, r1
8001632: 2200 movs r2, #0
8001634: 60da str r2, [r3, #12]
sConfig.IC1Filter = 5;
8001636: 187b adds r3, r7, r1
8001638: 2205 movs r2, #5
800163a: 611a str r2, [r3, #16]
sConfig.IC2Polarity = TIM_ICPOLARITY_RISING;
800163c: 187b adds r3, r7, r1
800163e: 2200 movs r2, #0
8001640: 615a str r2, [r3, #20]
sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI;
8001642: 187b adds r3, r7, r1
8001644: 2201 movs r2, #1
8001646: 619a str r2, [r3, #24]
sConfig.IC2Prescaler = TIM_ICPSC_DIV1;
8001648: 187b adds r3, r7, r1
800164a: 2200 movs r2, #0
800164c: 61da str r2, [r3, #28]
sConfig.IC2Filter = 5;
800164e: 187b adds r3, r7, r1
8001650: 2205 movs r2, #5
8001652: 621a str r2, [r3, #32]
if (HAL_TIM_Encoder_Init(&htim2, &sConfig) != HAL_OK)
8001654: 187a adds r2, r7, r1
8001656: 4b0e ldr r3, [pc, #56] ; (8001690 <MX_TIM2_Init+0xc0>)
8001658: 0011 movs r1, r2
800165a: 0018 movs r0, r3
800165c: f003 f8a8 bl 80047b0 <HAL_TIM_Encoder_Init>
8001660: 1e03 subs r3, r0, #0
8001662: d001 beq.n 8001668 <MX_TIM2_Init+0x98>
{
Error_Handler();
8001664: f7ff fabd bl 8000be2 <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
8001668: 003b movs r3, r7
800166a: 2200 movs r2, #0
800166c: 601a str r2, [r3, #0]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
800166e: 003b movs r3, r7
8001670: 2200 movs r2, #0
8001672: 609a str r2, [r3, #8]
if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
8001674: 003a movs r2, r7
8001676: 4b06 ldr r3, [pc, #24] ; (8001690 <MX_TIM2_Init+0xc0>)
8001678: 0011 movs r1, r2
800167a: 0018 movs r0, r3
800167c: f003 fe1a bl 80052b4 <HAL_TIMEx_MasterConfigSynchronization>
8001680: 1e03 subs r3, r0, #0
8001682: d001 beq.n 8001688 <MX_TIM2_Init+0xb8>
{
Error_Handler();
8001684: f7ff faad bl 8000be2 <Error_Handler>
}
/* USER CODE BEGIN TIM2_Init 2 */
/* USER CODE END TIM2_Init 2 */
}
8001688: 46c0 nop ; (mov r8, r8)
800168a: 46bd mov sp, r7
800168c: b00d add sp, #52 ; 0x34
800168e: bd90 pop {r4, r7, pc}
8001690: 200002c8 .word 0x200002c8
08001694 <MX_TIM3_Init>:
/* TIM3 init function */
void MX_TIM3_Init(void)
{
8001694: b580 push {r7, lr}
8001696: b08a sub sp, #40 ; 0x28
8001698: af00 add r7, sp, #0
/* USER CODE BEGIN TIM3_Init 0 */
/* USER CODE END TIM3_Init 0 */
TIM_MasterConfigTypeDef sMasterConfig = {0};
800169a: 231c movs r3, #28
800169c: 18fb adds r3, r7, r3
800169e: 0018 movs r0, r3
80016a0: 230c movs r3, #12
80016a2: 001a movs r2, r3
80016a4: 2100 movs r1, #0
80016a6: f005 fe7f bl 80073a8 <memset>
TIM_OC_InitTypeDef sConfigOC = {0};
80016aa: 003b movs r3, r7
80016ac: 0018 movs r0, r3
80016ae: 231c movs r3, #28
80016b0: 001a movs r2, r3
80016b2: 2100 movs r1, #0
80016b4: f005 fe78 bl 80073a8 <memset>
/* USER CODE BEGIN TIM3_Init 1 */
/* USER CODE END TIM3_Init 1 */
htim3.Instance = TIM3;
80016b8: 4b24 ldr r3, [pc, #144] ; (800174c <MX_TIM3_Init+0xb8>)
80016ba: 4a25 ldr r2, [pc, #148] ; (8001750 <MX_TIM3_Init+0xbc>)
80016bc: 601a str r2, [r3, #0]
htim3.Init.Prescaler = 0;
80016be: 4b23 ldr r3, [pc, #140] ; (800174c <MX_TIM3_Init+0xb8>)
80016c0: 2200 movs r2, #0
80016c2: 605a str r2, [r3, #4]
htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
80016c4: 4b21 ldr r3, [pc, #132] ; (800174c <MX_TIM3_Init+0xb8>)
80016c6: 2200 movs r2, #0
80016c8: 609a str r2, [r3, #8]
htim3.Init.Period = 100;
80016ca: 4b20 ldr r3, [pc, #128] ; (800174c <MX_TIM3_Init+0xb8>)
80016cc: 2264 movs r2, #100 ; 0x64
80016ce: 60da str r2, [r3, #12]
htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
80016d0: 4b1e ldr r3, [pc, #120] ; (800174c <MX_TIM3_Init+0xb8>)
80016d2: 2200 movs r2, #0
80016d4: 611a str r2, [r3, #16]
htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE;
80016d6: 4b1d ldr r3, [pc, #116] ; (800174c <MX_TIM3_Init+0xb8>)
80016d8: 2280 movs r2, #128 ; 0x80
80016da: 619a str r2, [r3, #24]
if (HAL_TIM_PWM_Init(&htim3) != HAL_OK)
80016dc: 4b1b ldr r3, [pc, #108] ; (800174c <MX_TIM3_Init+0xb8>)
80016de: 0018 movs r0, r3
80016e0: f002 ff30 bl 8004544 <HAL_TIM_PWM_Init>
80016e4: 1e03 subs r3, r0, #0
80016e6: d001 beq.n 80016ec <MX_TIM3_Init+0x58>
{
Error_Handler();
80016e8: f7ff fa7b bl 8000be2 <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
80016ec: 211c movs r1, #28
80016ee: 187b adds r3, r7, r1
80016f0: 2200 movs r2, #0
80016f2: 601a str r2, [r3, #0]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
80016f4: 187b adds r3, r7, r1
80016f6: 2200 movs r2, #0
80016f8: 609a str r2, [r3, #8]
if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
80016fa: 187a adds r2, r7, r1
80016fc: 4b13 ldr r3, [pc, #76] ; (800174c <MX_TIM3_Init+0xb8>)
80016fe: 0011 movs r1, r2
8001700: 0018 movs r0, r3
8001702: f003 fdd7 bl 80052b4 <HAL_TIMEx_MasterConfigSynchronization>
8001706: 1e03 subs r3, r0, #0
8001708: d001 beq.n 800170e <MX_TIM3_Init+0x7a>
{
Error_Handler();
800170a: f7ff fa6a bl 8000be2 <Error_Handler>
}
sConfigOC.OCMode = TIM_OCMODE_PWM1;
800170e: 003b movs r3, r7
8001710: 2260 movs r2, #96 ; 0x60
8001712: 601a str r2, [r3, #0]
sConfigOC.Pulse = 80;
8001714: 003b movs r3, r7
8001716: 2250 movs r2, #80 ; 0x50
8001718: 605a str r2, [r3, #4]
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
800171a: 003b movs r3, r7
800171c: 2200 movs r2, #0
800171e: 609a str r2, [r3, #8]
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
8001720: 003b movs r3, r7
8001722: 2200 movs r2, #0
8001724: 611a str r2, [r3, #16]
if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
8001726: 0039 movs r1, r7
8001728: 4b08 ldr r3, [pc, #32] ; (800174c <MX_TIM3_Init+0xb8>)
800172a: 2200 movs r2, #0
800172c: 0018 movs r0, r3
800172e: f003 f98b bl 8004a48 <HAL_TIM_PWM_ConfigChannel>
8001732: 1e03 subs r3, r0, #0
8001734: d001 beq.n 800173a <MX_TIM3_Init+0xa6>
{
Error_Handler();
8001736: f7ff fa54 bl 8000be2 <Error_Handler>
}
/* USER CODE BEGIN TIM3_Init 2 */
/* USER CODE END TIM3_Init 2 */
HAL_TIM_MspPostInit(&htim3);
800173a: 4b04 ldr r3, [pc, #16] ; (800174c <MX_TIM3_Init+0xb8>)
800173c: 0018 movs r0, r3
800173e: f000 f86f bl 8001820 <HAL_TIM_MspPostInit>
}
8001742: 46c0 nop ; (mov r8, r8)
8001744: 46bd mov sp, r7
8001746: b00a add sp, #40 ; 0x28
8001748: bd80 pop {r7, pc}
800174a: 46c0 nop ; (mov r8, r8)
800174c: 20000314 .word 0x20000314
8001750: 40000400 .word 0x40000400
08001754 <HAL_TIM_Encoder_MspInit>:
void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef* tim_encoderHandle)
{
8001754: b590 push {r4, r7, lr}
8001756: b08b sub sp, #44 ; 0x2c
8001758: af00 add r7, sp, #0
800175a: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
800175c: 2414 movs r4, #20
800175e: 193b adds r3, r7, r4
8001760: 0018 movs r0, r3
8001762: 2314 movs r3, #20
8001764: 001a movs r2, r3
8001766: 2100 movs r1, #0
8001768: f005 fe1e bl 80073a8 <memset>
if(tim_encoderHandle->Instance==TIM2)
800176c: 687b ldr r3, [r7, #4]
800176e: 681a ldr r2, [r3, #0]
8001770: 2380 movs r3, #128 ; 0x80
8001772: 05db lsls r3, r3, #23
8001774: 429a cmp r2, r3
8001776: d12e bne.n 80017d6 <HAL_TIM_Encoder_MspInit+0x82>
{
/* USER CODE BEGIN TIM2_MspInit 0 */
/* USER CODE END TIM2_MspInit 0 */
/* TIM2 clock enable */
__HAL_RCC_TIM2_CLK_ENABLE();
8001778: 4b19 ldr r3, [pc, #100] ; (80017e0 <HAL_TIM_Encoder_MspInit+0x8c>)
800177a: 6bda ldr r2, [r3, #60] ; 0x3c
800177c: 4b18 ldr r3, [pc, #96] ; (80017e0 <HAL_TIM_Encoder_MspInit+0x8c>)
800177e: 2101 movs r1, #1
8001780: 430a orrs r2, r1
8001782: 63da str r2, [r3, #60] ; 0x3c
8001784: 4b16 ldr r3, [pc, #88] ; (80017e0 <HAL_TIM_Encoder_MspInit+0x8c>)
8001786: 6bdb ldr r3, [r3, #60] ; 0x3c
8001788: 2201 movs r2, #1
800178a: 4013 ands r3, r2
800178c: 613b str r3, [r7, #16]
800178e: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
8001790: 4b13 ldr r3, [pc, #76] ; (80017e0 <HAL_TIM_Encoder_MspInit+0x8c>)
8001792: 6b5a ldr r2, [r3, #52] ; 0x34
8001794: 4b12 ldr r3, [pc, #72] ; (80017e0 <HAL_TIM_Encoder_MspInit+0x8c>)
8001796: 2101 movs r1, #1
8001798: 430a orrs r2, r1
800179a: 635a str r2, [r3, #52] ; 0x34
800179c: 4b10 ldr r3, [pc, #64] ; (80017e0 <HAL_TIM_Encoder_MspInit+0x8c>)
800179e: 6b5b ldr r3, [r3, #52] ; 0x34
80017a0: 2201 movs r2, #1
80017a2: 4013 ands r3, r2
80017a4: 60fb str r3, [r7, #12]
80017a6: 68fb ldr r3, [r7, #12]
/**TIM2 GPIO Configuration
PA0 ------> TIM2_CH1
PA1 ------> TIM2_CH2
*/
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1;
80017a8: 0021 movs r1, r4
80017aa: 187b adds r3, r7, r1
80017ac: 2203 movs r2, #3
80017ae: 601a str r2, [r3, #0]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80017b0: 187b adds r3, r7, r1
80017b2: 2202 movs r2, #2
80017b4: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80017b6: 187b adds r3, r7, r1
80017b8: 2200 movs r2, #0
80017ba: 609a str r2, [r3, #8]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80017bc: 187b adds r3, r7, r1
80017be: 2200 movs r2, #0
80017c0: 60da str r2, [r3, #12]
GPIO_InitStruct.Alternate = GPIO_AF2_TIM2;
80017c2: 187b adds r3, r7, r1
80017c4: 2202 movs r2, #2
80017c6: 611a str r2, [r3, #16]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
80017c8: 187a adds r2, r7, r1
80017ca: 23a0 movs r3, #160 ; 0xa0
80017cc: 05db lsls r3, r3, #23
80017ce: 0011 movs r1, r2
80017d0: 0018 movs r0, r3
80017d2: f001 feab bl 800352c <HAL_GPIO_Init>
/* USER CODE BEGIN TIM2_MspInit 1 */
/* USER CODE END TIM2_MspInit 1 */
}
}
80017d6: 46c0 nop ; (mov r8, r8)
80017d8: 46bd mov sp, r7
80017da: b00b add sp, #44 ; 0x2c
80017dc: bd90 pop {r4, r7, pc}
80017de: 46c0 nop ; (mov r8, r8)
80017e0: 40021000 .word 0x40021000
080017e4 <HAL_TIM_PWM_MspInit>:
void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* tim_pwmHandle)
{
80017e4: b580 push {r7, lr}
80017e6: b084 sub sp, #16
80017e8: af00 add r7, sp, #0
80017ea: 6078 str r0, [r7, #4]
if(tim_pwmHandle->Instance==TIM3)
80017ec: 687b ldr r3, [r7, #4]
80017ee: 681b ldr r3, [r3, #0]
80017f0: 4a09 ldr r2, [pc, #36] ; (8001818 <HAL_TIM_PWM_MspInit+0x34>)
80017f2: 4293 cmp r3, r2
80017f4: d10b bne.n 800180e <HAL_TIM_PWM_MspInit+0x2a>
{
/* USER CODE BEGIN TIM3_MspInit 0 */
/* USER CODE END TIM3_MspInit 0 */
/* TIM3 clock enable */
__HAL_RCC_TIM3_CLK_ENABLE();
80017f6: 4b09 ldr r3, [pc, #36] ; (800181c <HAL_TIM_PWM_MspInit+0x38>)
80017f8: 6bda ldr r2, [r3, #60] ; 0x3c
80017fa: 4b08 ldr r3, [pc, #32] ; (800181c <HAL_TIM_PWM_MspInit+0x38>)
80017fc: 2102 movs r1, #2
80017fe: 430a orrs r2, r1
8001800: 63da str r2, [r3, #60] ; 0x3c
8001802: 4b06 ldr r3, [pc, #24] ; (800181c <HAL_TIM_PWM_MspInit+0x38>)
8001804: 6bdb ldr r3, [r3, #60] ; 0x3c
8001806: 2202 movs r2, #2
8001808: 4013 ands r3, r2
800180a: 60fb str r3, [r7, #12]
800180c: 68fb ldr r3, [r7, #12]
/* USER CODE BEGIN TIM3_MspInit 1 */
/* USER CODE END TIM3_MspInit 1 */
}
}
800180e: 46c0 nop ; (mov r8, r8)
8001810: 46bd mov sp, r7
8001812: b004 add sp, #16
8001814: bd80 pop {r7, pc}
8001816: 46c0 nop ; (mov r8, r8)
8001818: 40000400 .word 0x40000400
800181c: 40021000 .word 0x40021000
08001820 <HAL_TIM_MspPostInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* timHandle)
{
8001820: b590 push {r4, r7, lr}
8001822: b089 sub sp, #36 ; 0x24
8001824: af00 add r7, sp, #0
8001826: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001828: 240c movs r4, #12
800182a: 193b adds r3, r7, r4
800182c: 0018 movs r0, r3
800182e: 2314 movs r3, #20
8001830: 001a movs r2, r3
8001832: 2100 movs r1, #0
8001834: f005 fdb8 bl 80073a8 <memset>
if(timHandle->Instance==TIM3)
8001838: 687b ldr r3, [r7, #4]
800183a: 681b ldr r3, [r3, #0]
800183c: 4a14 ldr r2, [pc, #80] ; (8001890 <HAL_TIM_MspPostInit+0x70>)
800183e: 4293 cmp r3, r2
8001840: d122 bne.n 8001888 <HAL_TIM_MspPostInit+0x68>
{
/* USER CODE BEGIN TIM3_MspPostInit 0 */
/* USER CODE END TIM3_MspPostInit 0 */
__HAL_RCC_GPIOA_CLK_ENABLE();
8001842: 4b14 ldr r3, [pc, #80] ; (8001894 <HAL_TIM_MspPostInit+0x74>)
8001844: 6b5a ldr r2, [r3, #52] ; 0x34
8001846: 4b13 ldr r3, [pc, #76] ; (8001894 <HAL_TIM_MspPostInit+0x74>)
8001848: 2101 movs r1, #1
800184a: 430a orrs r2, r1
800184c: 635a str r2, [r3, #52] ; 0x34
800184e: 4b11 ldr r3, [pc, #68] ; (8001894 <HAL_TIM_MspPostInit+0x74>)
8001850: 6b5b ldr r3, [r3, #52] ; 0x34
8001852: 2201 movs r2, #1
8001854: 4013 ands r3, r2
8001856: 60bb str r3, [r7, #8]
8001858: 68bb ldr r3, [r7, #8]
/**TIM3 GPIO Configuration
PA6 ------> TIM3_CH1
*/
GPIO_InitStruct.Pin = GPIO_PIN_6;
800185a: 0021 movs r1, r4
800185c: 187b adds r3, r7, r1
800185e: 2240 movs r2, #64 ; 0x40
8001860: 601a str r2, [r3, #0]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001862: 187b adds r3, r7, r1
8001864: 2202 movs r2, #2
8001866: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001868: 187b adds r3, r7, r1
800186a: 2200 movs r2, #0
800186c: 609a str r2, [r3, #8]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
800186e: 187b adds r3, r7, r1
8001870: 2200 movs r2, #0
8001872: 60da str r2, [r3, #12]
GPIO_InitStruct.Alternate = GPIO_AF1_TIM3;
8001874: 187b adds r3, r7, r1
8001876: 2201 movs r2, #1
8001878: 611a str r2, [r3, #16]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
800187a: 187a adds r2, r7, r1
800187c: 23a0 movs r3, #160 ; 0xa0
800187e: 05db lsls r3, r3, #23
8001880: 0011 movs r1, r2
8001882: 0018 movs r0, r3
8001884: f001 fe52 bl 800352c <HAL_GPIO_Init>
/* USER CODE BEGIN TIM3_MspPostInit 1 */
/* USER CODE END TIM3_MspPostInit 1 */
}
}
8001888: 46c0 nop ; (mov r8, r8)
800188a: 46bd mov sp, r7
800188c: b009 add sp, #36 ; 0x24
800188e: bd90 pop {r4, r7, pc}
8001890: 40000400 .word 0x40000400
8001894: 40021000 .word 0x40021000
08001898 <MX_USART2_UART_Init>:
DMA_HandleTypeDef hdma_usart2_tx;
/* USART2 init function */
void MX_USART2_UART_Init(void)
{
8001898: b580 push {r7, lr}
800189a: af00 add r7, sp, #0
/* USER CODE END USART2_Init 0 */
/* USER CODE BEGIN USART2_Init 1 */
/* USER CODE END USART2_Init 1 */
huart2.Instance = USART2;
800189c: 4b16 ldr r3, [pc, #88] ; (80018f8 <MX_USART2_UART_Init+0x60>)
800189e: 4a17 ldr r2, [pc, #92] ; (80018fc <MX_USART2_UART_Init+0x64>)
80018a0: 601a str r2, [r3, #0]
huart2.Init.BaudRate = 115200;
80018a2: 4b15 ldr r3, [pc, #84] ; (80018f8 <MX_USART2_UART_Init+0x60>)
80018a4: 22e1 movs r2, #225 ; 0xe1
80018a6: 0252 lsls r2, r2, #9
80018a8: 605a str r2, [r3, #4]
huart2.Init.WordLength = UART_WORDLENGTH_8B;
80018aa: 4b13 ldr r3, [pc, #76] ; (80018f8 <MX_USART2_UART_Init+0x60>)
80018ac: 2200 movs r2, #0
80018ae: 609a str r2, [r3, #8]
huart2.Init.StopBits = UART_STOPBITS_1;
80018b0: 4b11 ldr r3, [pc, #68] ; (80018f8 <MX_USART2_UART_Init+0x60>)
80018b2: 2200 movs r2, #0
80018b4: 60da str r2, [r3, #12]
huart2.Init.Parity = UART_PARITY_NONE;
80018b6: 4b10 ldr r3, [pc, #64] ; (80018f8 <MX_USART2_UART_Init+0x60>)
80018b8: 2200 movs r2, #0
80018ba: 611a str r2, [r3, #16]
huart2.Init.Mode = UART_MODE_TX_RX;
80018bc: 4b0e ldr r3, [pc, #56] ; (80018f8 <MX_USART2_UART_Init+0x60>)
80018be: 220c movs r2, #12
80018c0: 615a str r2, [r3, #20]
huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
80018c2: 4b0d ldr r3, [pc, #52] ; (80018f8 <MX_USART2_UART_Init+0x60>)
80018c4: 2200 movs r2, #0
80018c6: 619a str r2, [r3, #24]
huart2.Init.OverSampling = UART_OVERSAMPLING_16;
80018c8: 4b0b ldr r3, [pc, #44] ; (80018f8 <MX_USART2_UART_Init+0x60>)
80018ca: 2200 movs r2, #0
80018cc: 61da str r2, [r3, #28]
huart2.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
80018ce: 4b0a ldr r3, [pc, #40] ; (80018f8 <MX_USART2_UART_Init+0x60>)
80018d0: 2200 movs r2, #0
80018d2: 621a str r2, [r3, #32]
huart2.Init.ClockPrescaler = UART_PRESCALER_DIV1;
80018d4: 4b08 ldr r3, [pc, #32] ; (80018f8 <MX_USART2_UART_Init+0x60>)
80018d6: 2200 movs r2, #0
80018d8: 625a str r2, [r3, #36] ; 0x24
huart2.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
80018da: 4b07 ldr r3, [pc, #28] ; (80018f8 <MX_USART2_UART_Init+0x60>)
80018dc: 2200 movs r2, #0
80018de: 629a str r2, [r3, #40] ; 0x28
if (HAL_UART_Init(&huart2) != HAL_OK)
80018e0: 4b05 ldr r3, [pc, #20] ; (80018f8 <MX_USART2_UART_Init+0x60>)
80018e2: 0018 movs r0, r3
80018e4: f003 fd4e bl 8005384 <HAL_UART_Init>
80018e8: 1e03 subs r3, r0, #0
80018ea: d001 beq.n 80018f0 <MX_USART2_UART_Init+0x58>
{
Error_Handler();
80018ec: f7ff f979 bl 8000be2 <Error_Handler>
}
/* USER CODE BEGIN USART2_Init 2 */
/* USER CODE END USART2_Init 2 */
}
80018f0: 46c0 nop ; (mov r8, r8)
80018f2: 46bd mov sp, r7
80018f4: bd80 pop {r7, pc}
80018f6: 46c0 nop ; (mov r8, r8)
80018f8: 20000360 .word 0x20000360
80018fc: 40004400 .word 0x40004400
08001900 <HAL_UART_MspInit>:
void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle)
{
8001900: b590 push {r4, r7, lr}
8001902: b08b sub sp, #44 ; 0x2c
8001904: af00 add r7, sp, #0
8001906: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001908: 2414 movs r4, #20
800190a: 193b adds r3, r7, r4
800190c: 0018 movs r0, r3
800190e: 2314 movs r3, #20
8001910: 001a movs r2, r3
8001912: 2100 movs r1, #0
8001914: f005 fd48 bl 80073a8 <memset>
if(uartHandle->Instance==USART2)
8001918: 687b ldr r3, [r7, #4]
800191a: 681b ldr r3, [r3, #0]
800191c: 4a34 ldr r2, [pc, #208] ; (80019f0 <HAL_UART_MspInit+0xf0>)
800191e: 4293 cmp r3, r2
8001920: d161 bne.n 80019e6 <HAL_UART_MspInit+0xe6>
{
/* USER CODE BEGIN USART2_MspInit 0 */
/* USER CODE END USART2_MspInit 0 */
/* USART2 clock enable */
__HAL_RCC_USART2_CLK_ENABLE();
8001922: 4b34 ldr r3, [pc, #208] ; (80019f4 <HAL_UART_MspInit+0xf4>)
8001924: 6bda ldr r2, [r3, #60] ; 0x3c
8001926: 4b33 ldr r3, [pc, #204] ; (80019f4 <HAL_UART_MspInit+0xf4>)
8001928: 2180 movs r1, #128 ; 0x80
800192a: 0289 lsls r1, r1, #10
800192c: 430a orrs r2, r1
800192e: 63da str r2, [r3, #60] ; 0x3c
8001930: 4b30 ldr r3, [pc, #192] ; (80019f4 <HAL_UART_MspInit+0xf4>)
8001932: 6bda ldr r2, [r3, #60] ; 0x3c
8001934: 2380 movs r3, #128 ; 0x80
8001936: 029b lsls r3, r3, #10
8001938: 4013 ands r3, r2
800193a: 613b str r3, [r7, #16]
800193c: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
800193e: 4b2d ldr r3, [pc, #180] ; (80019f4 <HAL_UART_MspInit+0xf4>)
8001940: 6b5a ldr r2, [r3, #52] ; 0x34
8001942: 4b2c ldr r3, [pc, #176] ; (80019f4 <HAL_UART_MspInit+0xf4>)
8001944: 2101 movs r1, #1
8001946: 430a orrs r2, r1
8001948: 635a str r2, [r3, #52] ; 0x34
800194a: 4b2a ldr r3, [pc, #168] ; (80019f4 <HAL_UART_MspInit+0xf4>)
800194c: 6b5b ldr r3, [r3, #52] ; 0x34
800194e: 2201 movs r2, #1
8001950: 4013 ands r3, r2
8001952: 60fb str r3, [r7, #12]
8001954: 68fb ldr r3, [r7, #12]
/**USART2 GPIO Configuration
PA2 ------> USART2_TX
PA3 ------> USART2_RX
*/
GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3;
8001956: 0021 movs r1, r4
8001958: 187b adds r3, r7, r1
800195a: 220c movs r2, #12
800195c: 601a str r2, [r3, #0]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800195e: 187b adds r3, r7, r1
8001960: 2202 movs r2, #2
8001962: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001964: 187b adds r3, r7, r1
8001966: 2200 movs r2, #0
8001968: 609a str r2, [r3, #8]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
800196a: 187b adds r3, r7, r1
800196c: 2200 movs r2, #0
800196e: 60da str r2, [r3, #12]
GPIO_InitStruct.Alternate = GPIO_AF1_USART2;
8001970: 187b adds r3, r7, r1
8001972: 2201 movs r2, #1
8001974: 611a str r2, [r3, #16]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8001976: 187a adds r2, r7, r1
8001978: 23a0 movs r3, #160 ; 0xa0
800197a: 05db lsls r3, r3, #23
800197c: 0011 movs r1, r2
800197e: 0018 movs r0, r3
8001980: f001 fdd4 bl 800352c <HAL_GPIO_Init>
/* USART2 DMA Init */
/* USART2_TX Init */
hdma_usart2_tx.Instance = DMA1_Channel1;
8001984: 4b1c ldr r3, [pc, #112] ; (80019f8 <HAL_UART_MspInit+0xf8>)
8001986: 4a1d ldr r2, [pc, #116] ; (80019fc <HAL_UART_MspInit+0xfc>)
8001988: 601a str r2, [r3, #0]
hdma_usart2_tx.Init.Request = DMA_REQUEST_USART2_TX;
800198a: 4b1b ldr r3, [pc, #108] ; (80019f8 <HAL_UART_MspInit+0xf8>)
800198c: 2235 movs r2, #53 ; 0x35
800198e: 605a str r2, [r3, #4]
hdma_usart2_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
8001990: 4b19 ldr r3, [pc, #100] ; (80019f8 <HAL_UART_MspInit+0xf8>)
8001992: 2210 movs r2, #16
8001994: 609a str r2, [r3, #8]
hdma_usart2_tx.Init.PeriphInc = DMA_PINC_DISABLE;
8001996: 4b18 ldr r3, [pc, #96] ; (80019f8 <HAL_UART_MspInit+0xf8>)
8001998: 2200 movs r2, #0
800199a: 60da str r2, [r3, #12]
hdma_usart2_tx.Init.MemInc = DMA_MINC_ENABLE;
800199c: 4b16 ldr r3, [pc, #88] ; (80019f8 <HAL_UART_MspInit+0xf8>)
800199e: 2280 movs r2, #128 ; 0x80
80019a0: 611a str r2, [r3, #16]
hdma_usart2_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
80019a2: 4b15 ldr r3, [pc, #84] ; (80019f8 <HAL_UART_MspInit+0xf8>)
80019a4: 2200 movs r2, #0
80019a6: 615a str r2, [r3, #20]
hdma_usart2_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
80019a8: 4b13 ldr r3, [pc, #76] ; (80019f8 <HAL_UART_MspInit+0xf8>)
80019aa: 2200 movs r2, #0
80019ac: 619a str r2, [r3, #24]
hdma_usart2_tx.Init.Mode = DMA_NORMAL;
80019ae: 4b12 ldr r3, [pc, #72] ; (80019f8 <HAL_UART_MspInit+0xf8>)
80019b0: 2200 movs r2, #0
80019b2: 61da str r2, [r3, #28]
hdma_usart2_tx.Init.Priority = DMA_PRIORITY_LOW;
80019b4: 4b10 ldr r3, [pc, #64] ; (80019f8 <HAL_UART_MspInit+0xf8>)
80019b6: 2200 movs r2, #0
80019b8: 621a str r2, [r3, #32]
if (HAL_DMA_Init(&hdma_usart2_tx) != HAL_OK)
80019ba: 4b0f ldr r3, [pc, #60] ; (80019f8 <HAL_UART_MspInit+0xf8>)
80019bc: 0018 movs r0, r3
80019be: f001 fa97 bl 8002ef0 <HAL_DMA_Init>
80019c2: 1e03 subs r3, r0, #0
80019c4: d001 beq.n 80019ca <HAL_UART_MspInit+0xca>
{
Error_Handler();
80019c6: f7ff f90c bl 8000be2 <Error_Handler>
}
__HAL_LINKDMA(uartHandle,hdmatx,hdma_usart2_tx);
80019ca: 687b ldr r3, [r7, #4]
80019cc: 4a0a ldr r2, [pc, #40] ; (80019f8 <HAL_UART_MspInit+0xf8>)
80019ce: 679a str r2, [r3, #120] ; 0x78
80019d0: 4b09 ldr r3, [pc, #36] ; (80019f8 <HAL_UART_MspInit+0xf8>)
80019d2: 687a ldr r2, [r7, #4]
80019d4: 629a str r2, [r3, #40] ; 0x28
/* USART2 interrupt Init */
HAL_NVIC_SetPriority(USART2_IRQn, 0, 0);
80019d6: 2200 movs r2, #0
80019d8: 2100 movs r1, #0
80019da: 201c movs r0, #28
80019dc: f001 fa56 bl 8002e8c <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(USART2_IRQn);
80019e0: 201c movs r0, #28
80019e2: f001 fa68 bl 8002eb6 <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN USART2_MspInit 1 */
/* USER CODE END USART2_MspInit 1 */
}
}
80019e6: 46c0 nop ; (mov r8, r8)
80019e8: 46bd mov sp, r7
80019ea: b00b add sp, #44 ; 0x2c
80019ec: bd90 pop {r4, r7, pc}
80019ee: 46c0 nop ; (mov r8, r8)
80019f0: 40004400 .word 0x40004400
80019f4: 40021000 .word 0x40021000
80019f8: 200003f0 .word 0x200003f0
80019fc: 40020008 .word 0x40020008
08001a00 <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
8001a00: 480d ldr r0, [pc, #52] ; (8001a38 <LoopForever+0x2>)
mov sp, r0 /* set stack pointer */
8001a02: 4685 mov sp, r0
/* Call the clock system initialization function.*/
bl SystemInit
8001a04: f7ff fdde bl 80015c4 <SystemInit>
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
8001a08: 480c ldr r0, [pc, #48] ; (8001a3c <LoopForever+0x6>)
ldr r1, =_edata
8001a0a: 490d ldr r1, [pc, #52] ; (8001a40 <LoopForever+0xa>)
ldr r2, =_sidata
8001a0c: 4a0d ldr r2, [pc, #52] ; (8001a44 <LoopForever+0xe>)
movs r3, #0
8001a0e: 2300 movs r3, #0
b LoopCopyDataInit
8001a10: e002 b.n 8001a18 <LoopCopyDataInit>
08001a12 <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
8001a12: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
8001a14: 50c4 str r4, [r0, r3]
adds r3, r3, #4
8001a16: 3304 adds r3, #4
08001a18 <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
8001a18: 18c4 adds r4, r0, r3
cmp r4, r1
8001a1a: 428c cmp r4, r1
bcc CopyDataInit
8001a1c: d3f9 bcc.n 8001a12 <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
8001a1e: 4a0a ldr r2, [pc, #40] ; (8001a48 <LoopForever+0x12>)
ldr r4, =_ebss
8001a20: 4c0a ldr r4, [pc, #40] ; (8001a4c <LoopForever+0x16>)
movs r3, #0
8001a22: 2300 movs r3, #0
b LoopFillZerobss
8001a24: e001 b.n 8001a2a <LoopFillZerobss>
08001a26 <FillZerobss>:
FillZerobss:
str r3, [r2]
8001a26: 6013 str r3, [r2, #0]
adds r2, r2, #4
8001a28: 3204 adds r2, #4
08001a2a <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
8001a2a: 42a2 cmp r2, r4
bcc FillZerobss
8001a2c: d3fb bcc.n 8001a26 <FillZerobss>
/* Call static constructors */
bl __libc_init_array
8001a2e: f005 fc97 bl 8007360 <__libc_init_array>
/* Call the application s entry point.*/
bl main
8001a32: f7ff f875 bl 8000b20 <main>
08001a36 <LoopForever>:
LoopForever:
b LoopForever
8001a36: e7fe b.n 8001a36 <LoopForever>
ldr r0, =_estack
8001a38: 20002000 .word 0x20002000
ldr r0, =_sdata
8001a3c: 20000000 .word 0x20000000
ldr r1, =_edata
8001a40: 20000018 .word 0x20000018
ldr r2, =_sidata
8001a44: 080074ac .word 0x080074ac
ldr r2, =_sbss
8001a48: 20000018 .word 0x20000018
ldr r4, =_ebss
8001a4c: 20000450 .word 0x20000450
08001a50 <DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler>:
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8001a50: e7fe b.n 8001a50 <DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler>
...
08001a54 <HAL_Init>:
* each 1ms in the SysTick_Handler() interrupt handler.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
8001a54: b580 push {r7, lr}
8001a56: b082 sub sp, #8
8001a58: af00 add r7, sp, #0
HAL_StatusTypeDef status = HAL_OK;
8001a5a: 1dfb adds r3, r7, #7
8001a5c: 2200 movs r2, #0
8001a5e: 701a strb r2, [r3, #0]
#if (INSTRUCTION_CACHE_ENABLE == 0U)
__HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
#endif /* INSTRUCTION_CACHE_ENABLE */
#if (PREFETCH_ENABLE != 0U)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
8001a60: 4b0b ldr r3, [pc, #44] ; (8001a90 <HAL_Init+0x3c>)
8001a62: 681a ldr r2, [r3, #0]
8001a64: 4b0a ldr r3, [pc, #40] ; (8001a90 <HAL_Init+0x3c>)
8001a66: 2180 movs r1, #128 ; 0x80
8001a68: 0049 lsls r1, r1, #1
8001a6a: 430a orrs r2, r1
8001a6c: 601a str r2, [r3, #0]
#endif /* PREFETCH_ENABLE */
/* Use SysTick as time base source and configure 1ms tick (default clock after Reset is HSI) */
if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
8001a6e: 2003 movs r0, #3
8001a70: f000 f810 bl 8001a94 <HAL_InitTick>
8001a74: 1e03 subs r3, r0, #0
8001a76: d003 beq.n 8001a80 <HAL_Init+0x2c>
{
status = HAL_ERROR;
8001a78: 1dfb adds r3, r7, #7
8001a7a: 2201 movs r2, #1
8001a7c: 701a strb r2, [r3, #0]
8001a7e: e001 b.n 8001a84 <HAL_Init+0x30>
}
else
{
/* Init the low level hardware */
HAL_MspInit();
8001a80: f7ff fd40 bl 8001504 <HAL_MspInit>
}
/* Return function status */
return status;
8001a84: 1dfb adds r3, r7, #7
8001a86: 781b ldrb r3, [r3, #0]
}
8001a88: 0018 movs r0, r3
8001a8a: 46bd mov sp, r7
8001a8c: b002 add sp, #8
8001a8e: bd80 pop {r7, pc}
8001a90: 40022000 .word 0x40022000
08001a94 <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
8001a94: b590 push {r4, r7, lr}
8001a96: b085 sub sp, #20
8001a98: af00 add r7, sp, #0
8001a9a: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
8001a9c: 230f movs r3, #15
8001a9e: 18fb adds r3, r7, r3
8001aa0: 2200 movs r2, #0
8001aa2: 701a strb r2, [r3, #0]
/* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that doesn't take the value zero)*/
if ((uint32_t)uwTickFreq != 0U)
8001aa4: 4b1d ldr r3, [pc, #116] ; (8001b1c <HAL_InitTick+0x88>)
8001aa6: 781b ldrb r3, [r3, #0]
8001aa8: 2b00 cmp r3, #0
8001aaa: d02b beq.n 8001b04 <HAL_InitTick+0x70>
{
/*Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U /(uint32_t)uwTickFreq)) == 0U)
8001aac: 4b1c ldr r3, [pc, #112] ; (8001b20 <HAL_InitTick+0x8c>)
8001aae: 681c ldr r4, [r3, #0]
8001ab0: 4b1a ldr r3, [pc, #104] ; (8001b1c <HAL_InitTick+0x88>)
8001ab2: 781b ldrb r3, [r3, #0]
8001ab4: 0019 movs r1, r3
8001ab6: 23fa movs r3, #250 ; 0xfa
8001ab8: 0098 lsls r0, r3, #2
8001aba: f7fe fb23 bl 8000104 <__udivsi3>
8001abe: 0003 movs r3, r0
8001ac0: 0019 movs r1, r3
8001ac2: 0020 movs r0, r4
8001ac4: f7fe fb1e bl 8000104 <__udivsi3>
8001ac8: 0003 movs r3, r0
8001aca: 0018 movs r0, r3
8001acc: f001 fa03 bl 8002ed6 <HAL_SYSTICK_Config>
8001ad0: 1e03 subs r3, r0, #0
8001ad2: d112 bne.n 8001afa <HAL_InitTick+0x66>
{
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
8001ad4: 687b ldr r3, [r7, #4]
8001ad6: 2b03 cmp r3, #3
8001ad8: d80a bhi.n 8001af0 <HAL_InitTick+0x5c>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
8001ada: 6879 ldr r1, [r7, #4]
8001adc: 2301 movs r3, #1
8001ade: 425b negs r3, r3
8001ae0: 2200 movs r2, #0
8001ae2: 0018 movs r0, r3
8001ae4: f001 f9d2 bl 8002e8c <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
8001ae8: 4b0e ldr r3, [pc, #56] ; (8001b24 <HAL_InitTick+0x90>)
8001aea: 687a ldr r2, [r7, #4]
8001aec: 601a str r2, [r3, #0]
8001aee: e00d b.n 8001b0c <HAL_InitTick+0x78>
}
else
{
status = HAL_ERROR;
8001af0: 230f movs r3, #15
8001af2: 18fb adds r3, r7, r3
8001af4: 2201 movs r2, #1
8001af6: 701a strb r2, [r3, #0]
8001af8: e008 b.n 8001b0c <HAL_InitTick+0x78>
}
}
else
{
status = HAL_ERROR;
8001afa: 230f movs r3, #15
8001afc: 18fb adds r3, r7, r3
8001afe: 2201 movs r2, #1
8001b00: 701a strb r2, [r3, #0]
8001b02: e003 b.n 8001b0c <HAL_InitTick+0x78>
}
}
else
{
status = HAL_ERROR;
8001b04: 230f movs r3, #15
8001b06: 18fb adds r3, r7, r3
8001b08: 2201 movs r2, #1
8001b0a: 701a strb r2, [r3, #0]
}
/* Return function status */
return status;
8001b0c: 230f movs r3, #15
8001b0e: 18fb adds r3, r7, r3
8001b10: 781b ldrb r3, [r3, #0]
}
8001b12: 0018 movs r0, r3
8001b14: 46bd mov sp, r7
8001b16: b005 add sp, #20
8001b18: bd90 pop {r4, r7, pc}
8001b1a: 46c0 nop ; (mov r8, r8)
8001b1c: 20000014 .word 0x20000014
8001b20: 2000000c .word 0x2000000c
8001b24: 20000010 .word 0x20000010
08001b28 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
8001b28: b580 push {r7, lr}
8001b2a: af00 add r7, sp, #0
uwTick += (uint32_t)uwTickFreq;
8001b2c: 4b05 ldr r3, [pc, #20] ; (8001b44 <HAL_IncTick+0x1c>)
8001b2e: 781b ldrb r3, [r3, #0]
8001b30: 001a movs r2, r3
8001b32: 4b05 ldr r3, [pc, #20] ; (8001b48 <HAL_IncTick+0x20>)
8001b34: 681b ldr r3, [r3, #0]
8001b36: 18d2 adds r2, r2, r3
8001b38: 4b03 ldr r3, [pc, #12] ; (8001b48 <HAL_IncTick+0x20>)
8001b3a: 601a str r2, [r3, #0]
}
8001b3c: 46c0 nop ; (mov r8, r8)
8001b3e: 46bd mov sp, r7
8001b40: bd80 pop {r7, pc}
8001b42: 46c0 nop ; (mov r8, r8)
8001b44: 20000014 .word 0x20000014
8001b48: 2000044c .word 0x2000044c
08001b4c <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
8001b4c: b580 push {r7, lr}
8001b4e: af00 add r7, sp, #0
return uwTick;
8001b50: 4b02 ldr r3, [pc, #8] ; (8001b5c <HAL_GetTick+0x10>)
8001b52: 681b ldr r3, [r3, #0]
}
8001b54: 0018 movs r0, r3
8001b56: 46bd mov sp, r7
8001b58: bd80 pop {r7, pc}
8001b5a: 46c0 nop ; (mov r8, r8)
8001b5c: 2000044c .word 0x2000044c
08001b60 <LL_ADC_SetCommonPathInternalCh>:
* @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
* @arg @ref LL_ADC_PATH_INTERNAL_VBAT
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
{
8001b60: b580 push {r7, lr}
8001b62: b082 sub sp, #8
8001b64: af00 add r7, sp, #0
8001b66: 6078 str r0, [r7, #4]
8001b68: 6039 str r1, [r7, #0]
MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal);
8001b6a: 687b ldr r3, [r7, #4]
8001b6c: 681b ldr r3, [r3, #0]
8001b6e: 4a05 ldr r2, [pc, #20] ; (8001b84 <LL_ADC_SetCommonPathInternalCh+0x24>)
8001b70: 401a ands r2, r3
8001b72: 683b ldr r3, [r7, #0]
8001b74: 431a orrs r2, r3
8001b76: 687b ldr r3, [r7, #4]
8001b78: 601a str r2, [r3, #0]
}
8001b7a: 46c0 nop ; (mov r8, r8)
8001b7c: 46bd mov sp, r7
8001b7e: b002 add sp, #8
8001b80: bd80 pop {r7, pc}
8001b82: 46c0 nop ; (mov r8, r8)
8001b84: fe3fffff .word 0xfe3fffff
08001b88 <LL_ADC_GetCommonPathInternalCh>:
* @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
* @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
* @arg @ref LL_ADC_PATH_INTERNAL_VBAT
*/
__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
{
8001b88: b580 push {r7, lr}
8001b8a: b082 sub sp, #8
8001b8c: af00 add r7, sp, #0
8001b8e: 6078 str r0, [r7, #4]
return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN));
8001b90: 687b ldr r3, [r7, #4]
8001b92: 681a ldr r2, [r3, #0]
8001b94: 23e0 movs r3, #224 ; 0xe0
8001b96: 045b lsls r3, r3, #17
8001b98: 4013 ands r3, r2
}
8001b9a: 0018 movs r0, r3
8001b9c: 46bd mov sp, r7
8001b9e: b002 add sp, #8
8001ba0: bd80 pop {r7, pc}
08001ba2 <LL_ADC_SetSamplingTimeCommonChannels>:
* @arg @ref LL_ADC_SAMPLINGTIME_160CYCLES_5
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uint32_t SamplingTimeY,
uint32_t SamplingTime)
{
8001ba2: b580 push {r7, lr}
8001ba4: b084 sub sp, #16
8001ba6: af00 add r7, sp, #0
8001ba8: 60f8 str r0, [r7, #12]
8001baa: 60b9 str r1, [r7, #8]
8001bac: 607a str r2, [r7, #4]
MODIFY_REG(ADCx->SMPR,
8001bae: 68fb ldr r3, [r7, #12]
8001bb0: 695b ldr r3, [r3, #20]
8001bb2: 68ba ldr r2, [r7, #8]
8001bb4: 2104 movs r1, #4
8001bb6: 400a ands r2, r1
8001bb8: 2107 movs r1, #7
8001bba: 4091 lsls r1, r2
8001bbc: 000a movs r2, r1
8001bbe: 43d2 mvns r2, r2
8001bc0: 401a ands r2, r3
8001bc2: 68bb ldr r3, [r7, #8]
8001bc4: 2104 movs r1, #4
8001bc6: 400b ands r3, r1
8001bc8: 6879 ldr r1, [r7, #4]
8001bca: 4099 lsls r1, r3
8001bcc: 000b movs r3, r1
8001bce: 431a orrs r2, r3
8001bd0: 68fb ldr r3, [r7, #12]
8001bd2: 615a str r2, [r3, #20]
ADC_SMPR_SMP1 << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK),
SamplingTime << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK));
}
8001bd4: 46c0 nop ; (mov r8, r8)
8001bd6: 46bd mov sp, r7
8001bd8: b004 add sp, #16
8001bda: bd80 pop {r7, pc}
08001bdc <LL_ADC_GetSamplingTimeCommonChannels>:
* @arg @ref LL_ADC_SAMPLINGTIME_39CYCLES_5
* @arg @ref LL_ADC_SAMPLINGTIME_79CYCLES_5
* @arg @ref LL_ADC_SAMPLINGTIME_160CYCLES_5
*/
__STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uint32_t SamplingTimeY)
{
8001bdc: b580 push {r7, lr}
8001bde: b082 sub sp, #8
8001be0: af00 add r7, sp, #0
8001be2: 6078 str r0, [r7, #4]
8001be4: 6039 str r1, [r7, #0]
return (uint32_t)((READ_BIT(ADCx->SMPR, ADC_SMPR_SMP1 << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK)))
8001be6: 687b ldr r3, [r7, #4]
8001be8: 695b ldr r3, [r3, #20]
8001bea: 683a ldr r2, [r7, #0]
8001bec: 2104 movs r1, #4
8001bee: 400a ands r2, r1
8001bf0: 2107 movs r1, #7
8001bf2: 4091 lsls r1, r2
8001bf4: 000a movs r2, r1
8001bf6: 401a ands r2, r3
>> (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK));
8001bf8: 683b ldr r3, [r7, #0]
8001bfa: 2104 movs r1, #4
8001bfc: 400b ands r3, r1
return (uint32_t)((READ_BIT(ADCx->SMPR, ADC_SMPR_SMP1 << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK)))
8001bfe: 40da lsrs r2, r3
8001c00: 0013 movs r3, r2
}
8001c02: 0018 movs r0, r3
8001c04: 46bd mov sp, r7
8001c06: b002 add sp, #8
8001c08: bd80 pop {r7, pc}
08001c0a <LL_ADC_REG_IsTriggerSourceSWStart>:
* @param ADCx ADC instance
* @retval Value "0" if trigger source external trigger
* Value "1" if trigger source SW start.
*/
__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
{
8001c0a: b580 push {r7, lr}
8001c0c: b082 sub sp, #8
8001c0e: af00 add r7, sp, #0
8001c10: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN)) ? 1UL : 0UL);
8001c12: 687b ldr r3, [r7, #4]
8001c14: 68da ldr r2, [r3, #12]
8001c16: 23c0 movs r3, #192 ; 0xc0
8001c18: 011b lsls r3, r3, #4
8001c1a: 4013 ands r3, r2
8001c1c: d101 bne.n 8001c22 <LL_ADC_REG_IsTriggerSourceSWStart+0x18>
8001c1e: 2301 movs r3, #1
8001c20: e000 b.n 8001c24 <LL_ADC_REG_IsTriggerSourceSWStart+0x1a>
8001c22: 2300 movs r3, #0
}
8001c24: 0018 movs r0, r3
8001c26: 46bd mov sp, r7
8001c28: b002 add sp, #8
8001c2a: bd80 pop {r7, pc}
08001c2c <LL_ADC_REG_SetSequencerRanks>:
* only if sequencer is set in mode "not fully configurable",
* refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
* @retval None
*/
__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
{
8001c2c: b580 push {r7, lr}
8001c2e: b084 sub sp, #16
8001c30: af00 add r7, sp, #0
8001c32: 60f8 str r0, [r7, #12]
8001c34: 60b9 str r1, [r7, #8]
8001c36: 607a str r2, [r7, #4]
/* Set bits with content of parameter "Channel" with bits position */
/* in register depending on parameter "Rank". */
/* Parameters "Rank" and "Channel" are used with masks because containing */
/* other bits reserved for other purpose. */
MODIFY_REG(ADCx->CHSELR,
8001c38: 68fb ldr r3, [r7, #12]
8001c3a: 6a9b ldr r3, [r3, #40] ; 0x28
8001c3c: 68ba ldr r2, [r7, #8]
8001c3e: 211f movs r1, #31
8001c40: 400a ands r2, r1
8001c42: 210f movs r1, #15
8001c44: 4091 lsls r1, r2
8001c46: 000a movs r2, r1
8001c48: 43d2 mvns r2, r2
8001c4a: 401a ands r2, r3
8001c4c: 687b ldr r3, [r7, #4]
8001c4e: 0e9b lsrs r3, r3, #26
8001c50: 210f movs r1, #15
8001c52: 4019 ands r1, r3
8001c54: 68bb ldr r3, [r7, #8]
8001c56: 201f movs r0, #31
8001c58: 4003 ands r3, r0
8001c5a: 4099 lsls r1, r3
8001c5c: 000b movs r3, r1
8001c5e: 431a orrs r2, r3
8001c60: 68fb ldr r3, [r7, #12]
8001c62: 629a str r2, [r3, #40] ; 0x28
ADC_CHSELR_SQ1 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
((Channel & ADC_CHANNEL_ID_NUMBER_MASK_SEQ) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
}
8001c64: 46c0 nop ; (mov r8, r8)
8001c66: 46bd mov sp, r7
8001c68: b004 add sp, #16
8001c6a: bd80 pop {r7, pc}
08001c6c <LL_ADC_REG_SetSequencerChAdd>:
* only if sequencer is set in mode "not fully configurable",
* refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
* @retval None
*/
__STATIC_INLINE void LL_ADC_REG_SetSequencerChAdd(ADC_TypeDef *ADCx, uint32_t Channel)
{
8001c6c: b580 push {r7, lr}
8001c6e: b082 sub sp, #8
8001c70: af00 add r7, sp, #0
8001c72: 6078 str r0, [r7, #4]
8001c74: 6039 str r1, [r7, #0]
/* Parameter "Channel" is used with masks because containing */
/* other bits reserved for other purpose. */
SET_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
8001c76: 687b ldr r3, [r7, #4]
8001c78: 6a9a ldr r2, [r3, #40] ; 0x28
8001c7a: 683b ldr r3, [r7, #0]
8001c7c: 035b lsls r3, r3, #13
8001c7e: 0b5b lsrs r3, r3, #13
8001c80: 431a orrs r2, r3
8001c82: 687b ldr r3, [r7, #4]
8001c84: 629a str r2, [r3, #40] ; 0x28
}
8001c86: 46c0 nop ; (mov r8, r8)
8001c88: 46bd mov sp, r7
8001c8a: b002 add sp, #8
8001c8c: bd80 pop {r7, pc}
08001c8e <LL_ADC_REG_SetSequencerChRem>:
* only if sequencer is set in mode "not fully configurable",
* refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
* @retval None
*/
__STATIC_INLINE void LL_ADC_REG_SetSequencerChRem(ADC_TypeDef *ADCx, uint32_t Channel)
{
8001c8e: b580 push {r7, lr}
8001c90: b082 sub sp, #8
8001c92: af00 add r7, sp, #0
8001c94: 6078 str r0, [r7, #4]
8001c96: 6039 str r1, [r7, #0]
/* Parameter "Channel" is used with masks because containing */
/* other bits reserved for other purpose. */
CLEAR_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
8001c98: 687b ldr r3, [r7, #4]
8001c9a: 6a9b ldr r3, [r3, #40] ; 0x28
8001c9c: 683a ldr r2, [r7, #0]
8001c9e: 0352 lsls r2, r2, #13
8001ca0: 0b52 lsrs r2, r2, #13
8001ca2: 43d2 mvns r2, r2
8001ca4: 401a ands r2, r3
8001ca6: 687b ldr r3, [r7, #4]
8001ca8: 629a str r2, [r3, #40] ; 0x28
}
8001caa: 46c0 nop ; (mov r8, r8)
8001cac: 46bd mov sp, r7
8001cae: b002 add sp, #8
8001cb0: bd80 pop {r7, pc}
08001cb2 <LL_ADC_REG_GetDMATransfer>:
* @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
* @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
* @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
*/
__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
{
8001cb2: b580 push {r7, lr}
8001cb4: b082 sub sp, #8
8001cb6: af00 add r7, sp, #0
8001cb8: 6078 str r0, [r7, #4]
return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG));
8001cba: 687b ldr r3, [r7, #4]
8001cbc: 68db ldr r3, [r3, #12]
8001cbe: 2203 movs r2, #3
8001cc0: 4013 ands r3, r2
}
8001cc2: 0018 movs r0, r3
8001cc4: 46bd mov sp, r7
8001cc6: b002 add sp, #8
8001cc8: bd80 pop {r7, pc}
...
08001ccc <LL_ADC_SetChannelSamplingTime>:
* @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1
* @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTimeY)
{
8001ccc: b580 push {r7, lr}
8001cce: b084 sub sp, #16
8001cd0: af00 add r7, sp, #0
8001cd2: 60f8 str r0, [r7, #12]
8001cd4: 60b9 str r1, [r7, #8]
8001cd6: 607a str r2, [r7, #4]
/* Parameter "Channel" is used with masks because containing */
/* other bits reserved for other purpose. */
MODIFY_REG(ADCx->SMPR,
8001cd8: 68fb ldr r3, [r7, #12]
8001cda: 695b ldr r3, [r3, #20]
8001cdc: 68ba ldr r2, [r7, #8]
8001cde: 0212 lsls r2, r2, #8
8001ce0: 43d2 mvns r2, r2
8001ce2: 401a ands r2, r3
8001ce4: 68bb ldr r3, [r7, #8]
8001ce6: 021b lsls r3, r3, #8
8001ce8: 6879 ldr r1, [r7, #4]
8001cea: 400b ands r3, r1
8001cec: 4904 ldr r1, [pc, #16] ; (8001d00 <LL_ADC_SetChannelSamplingTime+0x34>)
8001cee: 400b ands r3, r1
8001cf0: 431a orrs r2, r3
8001cf2: 68fb ldr r3, [r7, #12]
8001cf4: 615a str r2, [r3, #20]
(Channel << ADC_SMPR_SMPSEL0_BITOFFSET_POS),
(Channel << ADC_SMPR_SMPSEL0_BITOFFSET_POS) & (SamplingTimeY & ADC_SAMPLING_TIME_CH_MASK)
);
}
8001cf6: 46c0 nop ; (mov r8, r8)
8001cf8: 46bd mov sp, r7
8001cfa: b004 add sp, #16
8001cfc: bd80 pop {r7, pc}
8001cfe: 46c0 nop ; (mov r8, r8)
8001d00: 07ffff00 .word 0x07ffff00
08001d04 <LL_ADC_EnableInternalRegulator>:
* @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
{
8001d04: b580 push {r7, lr}
8001d06: b082 sub sp, #8
8001d08: af00 add r7, sp, #0
8001d0a: 6078 str r0, [r7, #4]
/* Note: Write register with some additional bits forced to state reset */
/* instead of modifying only the selected bit for this function, */
/* to not interfere with bits with HW property "rs". */
MODIFY_REG(ADCx->CR,
8001d0c: 687b ldr r3, [r7, #4]
8001d0e: 689b ldr r3, [r3, #8]
8001d10: 4a05 ldr r2, [pc, #20] ; (8001d28 <LL_ADC_EnableInternalRegulator+0x24>)
8001d12: 4013 ands r3, r2
8001d14: 2280 movs r2, #128 ; 0x80
8001d16: 0552 lsls r2, r2, #21
8001d18: 431a orrs r2, r3
8001d1a: 687b ldr r3, [r7, #4]
8001d1c: 609a str r2, [r3, #8]
ADC_CR_BITS_PROPERTY_RS,
ADC_CR_ADVREGEN);
}
8001d1e: 46c0 nop ; (mov r8, r8)
8001d20: 46bd mov sp, r7
8001d22: b002 add sp, #8
8001d24: bd80 pop {r7, pc}
8001d26: 46c0 nop ; (mov r8, r8)
8001d28: 6fffffe8 .word 0x6fffffe8
08001d2c <LL_ADC_IsInternalRegulatorEnabled>:
* @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled
* @param ADCx ADC instance
* @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
*/
__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx)
{
8001d2c: b580 push {r7, lr}
8001d2e: b082 sub sp, #8
8001d30: af00 add r7, sp, #0
8001d32: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
8001d34: 687b ldr r3, [r7, #4]
8001d36: 689a ldr r2, [r3, #8]
8001d38: 2380 movs r3, #128 ; 0x80
8001d3a: 055b lsls r3, r3, #21
8001d3c: 401a ands r2, r3
8001d3e: 2380 movs r3, #128 ; 0x80
8001d40: 055b lsls r3, r3, #21
8001d42: 429a cmp r2, r3
8001d44: d101 bne.n 8001d4a <LL_ADC_IsInternalRegulatorEnabled+0x1e>
8001d46: 2301 movs r3, #1
8001d48: e000 b.n 8001d4c <LL_ADC_IsInternalRegulatorEnabled+0x20>
8001d4a: 2300 movs r3, #0
}
8001d4c: 0018 movs r0, r3
8001d4e: 46bd mov sp, r7
8001d50: b002 add sp, #8
8001d52: bd80 pop {r7, pc}
08001d54 <LL_ADC_Enable>:
* @rmtoll CR ADEN LL_ADC_Enable
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
{
8001d54: b580 push {r7, lr}
8001d56: b082 sub sp, #8
8001d58: af00 add r7, sp, #0
8001d5a: 6078 str r0, [r7, #4]
/* Note: Write register with some additional bits forced to state reset */
/* instead of modifying only the selected bit for this function, */
/* to not interfere with bits with HW property "rs". */
MODIFY_REG(ADCx->CR,
8001d5c: 687b ldr r3, [r7, #4]
8001d5e: 689b ldr r3, [r3, #8]
8001d60: 4a04 ldr r2, [pc, #16] ; (8001d74 <LL_ADC_Enable+0x20>)
8001d62: 4013 ands r3, r2
8001d64: 2201 movs r2, #1
8001d66: 431a orrs r2, r3
8001d68: 687b ldr r3, [r7, #4]
8001d6a: 609a str r2, [r3, #8]
ADC_CR_BITS_PROPERTY_RS,
ADC_CR_ADEN);
}
8001d6c: 46c0 nop ; (mov r8, r8)
8001d6e: 46bd mov sp, r7
8001d70: b002 add sp, #8
8001d72: bd80 pop {r7, pc}
8001d74: 7fffffe8 .word 0x7fffffe8
08001d78 <LL_ADC_Disable>:
* @rmtoll CR ADDIS LL_ADC_Disable
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
{
8001d78: b580 push {r7, lr}
8001d7a: b082 sub sp, #8
8001d7c: af00 add r7, sp, #0
8001d7e: 6078 str r0, [r7, #4]
/* Note: Write register with some additional bits forced to state reset */
/* instead of modifying only the selected bit for this function, */
/* to not interfere with bits with HW property "rs". */
MODIFY_REG(ADCx->CR,
8001d80: 687b ldr r3, [r7, #4]
8001d82: 689b ldr r3, [r3, #8]
8001d84: 4a04 ldr r2, [pc, #16] ; (8001d98 <LL_ADC_Disable+0x20>)
8001d86: 4013 ands r3, r2
8001d88: 2202 movs r2, #2
8001d8a: 431a orrs r2, r3
8001d8c: 687b ldr r3, [r7, #4]
8001d8e: 609a str r2, [r3, #8]
ADC_CR_BITS_PROPERTY_RS,
ADC_CR_ADDIS);
}
8001d90: 46c0 nop ; (mov r8, r8)
8001d92: 46bd mov sp, r7
8001d94: b002 add sp, #8
8001d96: bd80 pop {r7, pc}
8001d98: 7fffffe8 .word 0x7fffffe8
08001d9c <LL_ADC_IsEnabled>:
* @rmtoll CR ADEN LL_ADC_IsEnabled
* @param ADCx ADC instance
* @retval 0: ADC is disabled, 1: ADC is enabled.
*/
__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
{
8001d9c: b580 push {r7, lr}
8001d9e: b082 sub sp, #8
8001da0: af00 add r7, sp, #0
8001da2: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
8001da4: 687b ldr r3, [r7, #4]
8001da6: 689b ldr r3, [r3, #8]
8001da8: 2201 movs r2, #1
8001daa: 4013 ands r3, r2
8001dac: 2b01 cmp r3, #1
8001dae: d101 bne.n 8001db4 <LL_ADC_IsEnabled+0x18>
8001db0: 2301 movs r3, #1
8001db2: e000 b.n 8001db6 <LL_ADC_IsEnabled+0x1a>
8001db4: 2300 movs r3, #0
}
8001db6: 0018 movs r0, r3
8001db8: 46bd mov sp, r7
8001dba: b002 add sp, #8
8001dbc: bd80 pop {r7, pc}
08001dbe <LL_ADC_IsDisableOngoing>:
* @rmtoll CR ADDIS LL_ADC_IsDisableOngoing
* @param ADCx ADC instance
* @retval 0: no ADC disable command on going.
*/
__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx)
{
8001dbe: b580 push {r7, lr}
8001dc0: b082 sub sp, #8
8001dc2: af00 add r7, sp, #0
8001dc4: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);
8001dc6: 687b ldr r3, [r7, #4]
8001dc8: 689b ldr r3, [r3, #8]
8001dca: 2202 movs r2, #2
8001dcc: 4013 ands r3, r2
8001dce: 2b02 cmp r3, #2
8001dd0: d101 bne.n 8001dd6 <LL_ADC_IsDisableOngoing+0x18>
8001dd2: 2301 movs r3, #1
8001dd4: e000 b.n 8001dd8 <LL_ADC_IsDisableOngoing+0x1a>
8001dd6: 2300 movs r3, #0
}
8001dd8: 0018 movs r0, r3
8001dda: 46bd mov sp, r7
8001ddc: b002 add sp, #8
8001dde: bd80 pop {r7, pc}
08001de0 <LL_ADC_REG_StartConversion>:
* @rmtoll CR ADSTART LL_ADC_REG_StartConversion
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
{
8001de0: b580 push {r7, lr}
8001de2: b082 sub sp, #8
8001de4: af00 add r7, sp, #0
8001de6: 6078 str r0, [r7, #4]
/* Note: Write register with some additional bits forced to state reset */
/* instead of modifying only the selected bit for this function, */
/* to not interfere with bits with HW property "rs". */
MODIFY_REG(ADCx->CR,
8001de8: 687b ldr r3, [r7, #4]
8001dea: 689b ldr r3, [r3, #8]
8001dec: 4a04 ldr r2, [pc, #16] ; (8001e00 <LL_ADC_REG_StartConversion+0x20>)
8001dee: 4013 ands r3, r2
8001df0: 2204 movs r2, #4
8001df2: 431a orrs r2, r3
8001df4: 687b ldr r3, [r7, #4]
8001df6: 609a str r2, [r3, #8]
ADC_CR_BITS_PROPERTY_RS,
ADC_CR_ADSTART);
}
8001df8: 46c0 nop ; (mov r8, r8)
8001dfa: 46bd mov sp, r7
8001dfc: b002 add sp, #8
8001dfe: bd80 pop {r7, pc}
8001e00: 7fffffe8 .word 0x7fffffe8
08001e04 <LL_ADC_REG_IsConversionOngoing>:
* @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing
* @param ADCx ADC instance
* @retval 0: no conversion is on going on ADC group regular.
*/
__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx)
{
8001e04: b580 push {r7, lr}
8001e06: b082 sub sp, #8
8001e08: af00 add r7, sp, #0
8001e0a: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
8001e0c: 687b ldr r3, [r7, #4]
8001e0e: 689b ldr r3, [r3, #8]
8001e10: 2204 movs r2, #4
8001e12: 4013 ands r3, r2
8001e14: 2b04 cmp r3, #4
8001e16: d101 bne.n 8001e1c <LL_ADC_REG_IsConversionOngoing+0x18>
8001e18: 2301 movs r3, #1
8001e1a: e000 b.n 8001e1e <LL_ADC_REG_IsConversionOngoing+0x1a>
8001e1c: 2300 movs r3, #0
}
8001e1e: 0018 movs r0, r3
8001e20: 46bd mov sp, r7
8001e22: b002 add sp, #8
8001e24: bd80 pop {r7, pc}
...
08001e28 <HAL_ADC_Init>:
* of structure "ADC_InitTypeDef".
* @param hadc ADC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
{
8001e28: b580 push {r7, lr}
8001e2a: b088 sub sp, #32
8001e2c: af00 add r7, sp, #0
8001e2e: 6078 str r0, [r7, #4]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
8001e30: 231f movs r3, #31
8001e32: 18fb adds r3, r7, r3
8001e34: 2200 movs r2, #0
8001e36: 701a strb r2, [r3, #0]
uint32_t tmpCFGR1 = 0UL;
8001e38: 2300 movs r3, #0
8001e3a: 61bb str r3, [r7, #24]
uint32_t tmpCFGR2 = 0UL;
8001e3c: 2300 movs r3, #0
8001e3e: 617b str r3, [r7, #20]
uint32_t tmp_adc_reg_is_conversion_on_going;
__IO uint32_t wait_loop_index = 0UL;
8001e40: 2300 movs r3, #0
8001e42: 60fb str r3, [r7, #12]
/* Check ADC handle */
if (hadc == NULL)
8001e44: 687b ldr r3, [r7, #4]
8001e46: 2b00 cmp r3, #0
8001e48: d101 bne.n 8001e4e <HAL_ADC_Init+0x26>
{
return HAL_ERROR;
8001e4a: 2301 movs r3, #1
8001e4c: e17f b.n 800214e <HAL_ADC_Init+0x326>
/* continuous mode is disabled. */
assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE)));
/* Actions performed only if ADC is coming from state reset: */
/* - Initialization of ADC MSP */
if (hadc->State == HAL_ADC_STATE_RESET)
8001e4e: 687b ldr r3, [r7, #4]
8001e50: 6d9b ldr r3, [r3, #88] ; 0x58
8001e52: 2b00 cmp r3, #0
8001e54: d10a bne.n 8001e6c <HAL_ADC_Init+0x44>
/* Init the low level hardware */
hadc->MspInitCallback(hadc);
#else
/* Init the low level hardware */
HAL_ADC_MspInit(hadc);
8001e56: 687b ldr r3, [r7, #4]
8001e58: 0018 movs r0, r3
8001e5a: f7fe fb5d bl 8000518 <HAL_ADC_MspInit>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Set ADC error code to none */
ADC_CLEAR_ERRORCODE(hadc);
8001e5e: 687b ldr r3, [r7, #4]
8001e60: 2200 movs r2, #0
8001e62: 65da str r2, [r3, #92] ; 0x5c
/* Initialize Lock */
hadc->Lock = HAL_UNLOCKED;
8001e64: 687b ldr r3, [r7, #4]
8001e66: 2254 movs r2, #84 ; 0x54
8001e68: 2100 movs r1, #0
8001e6a: 5499 strb r1, [r3, r2]
}
if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
8001e6c: 687b ldr r3, [r7, #4]
8001e6e: 681b ldr r3, [r3, #0]
8001e70: 0018 movs r0, r3
8001e72: f7ff ff5b bl 8001d2c <LL_ADC_IsInternalRegulatorEnabled>
8001e76: 1e03 subs r3, r0, #0
8001e78: d115 bne.n 8001ea6 <HAL_ADC_Init+0x7e>
{
/* Enable ADC internal voltage regulator */
LL_ADC_EnableInternalRegulator(hadc->Instance);
8001e7a: 687b ldr r3, [r7, #4]
8001e7c: 681b ldr r3, [r3, #0]
8001e7e: 0018 movs r0, r3
8001e80: f7ff ff40 bl 8001d04 <LL_ADC_EnableInternalRegulator>
/* Delay for ADC stabilization time */
/* Wait loop initialization and execution */
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */
wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
8001e84: 4bb4 ldr r3, [pc, #720] ; (8002158 <HAL_ADC_Init+0x330>)
8001e86: 681b ldr r3, [r3, #0]
8001e88: 49b4 ldr r1, [pc, #720] ; (800215c <HAL_ADC_Init+0x334>)
8001e8a: 0018 movs r0, r3
8001e8c: f7fe f93a bl 8000104 <__udivsi3>
8001e90: 0003 movs r3, r0
8001e92: 3301 adds r3, #1
8001e94: 005b lsls r3, r3, #1
8001e96: 60fb str r3, [r7, #12]
while (wait_loop_index != 0UL)
8001e98: e002 b.n 8001ea0 <HAL_ADC_Init+0x78>
{
wait_loop_index--;
8001e9a: 68fb ldr r3, [r7, #12]
8001e9c: 3b01 subs r3, #1
8001e9e: 60fb str r3, [r7, #12]
while (wait_loop_index != 0UL)
8001ea0: 68fb ldr r3, [r7, #12]
8001ea2: 2b00 cmp r3, #0
8001ea4: d1f9 bne.n 8001e9a <HAL_ADC_Init+0x72>
}
/* Verification that ADC voltage regulator is correctly enabled, whether */
/* or not ADC is coming from state reset (if any potential problem of */
/* clocking, voltage regulator would not be enabled). */
if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
8001ea6: 687b ldr r3, [r7, #4]
8001ea8: 681b ldr r3, [r3, #0]
8001eaa: 0018 movs r0, r3
8001eac: f7ff ff3e bl 8001d2c <LL_ADC_IsInternalRegulatorEnabled>
8001eb0: 1e03 subs r3, r0, #0
8001eb2: d10f bne.n 8001ed4 <HAL_ADC_Init+0xac>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
8001eb4: 687b ldr r3, [r7, #4]
8001eb6: 6d9b ldr r3, [r3, #88] ; 0x58
8001eb8: 2210 movs r2, #16
8001eba: 431a orrs r2, r3
8001ebc: 687b ldr r3, [r7, #4]
8001ebe: 659a str r2, [r3, #88] ; 0x58
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8001ec0: 687b ldr r3, [r7, #4]
8001ec2: 6ddb ldr r3, [r3, #92] ; 0x5c
8001ec4: 2201 movs r2, #1
8001ec6: 431a orrs r2, r3
8001ec8: 687b ldr r3, [r7, #4]
8001eca: 65da str r2, [r3, #92] ; 0x5c
tmp_hal_status = HAL_ERROR;
8001ecc: 231f movs r3, #31
8001ece: 18fb adds r3, r7, r3
8001ed0: 2201 movs r2, #1
8001ed2: 701a strb r2, [r3, #0]
/* Configuration of ADC parameters if previous preliminary actions are */
/* correctly completed and if there is no conversion on going on regular */
/* group (ADC may already be enabled at this point if HAL_ADC_Init() is */
/* called to update a parameter on the fly). */
tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
8001ed4: 687b ldr r3, [r7, #4]
8001ed6: 681b ldr r3, [r3, #0]
8001ed8: 0018 movs r0, r3
8001eda: f7ff ff93 bl 8001e04 <LL_ADC_REG_IsConversionOngoing>
8001ede: 0003 movs r3, r0
8001ee0: 613b str r3, [r7, #16]
if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
8001ee2: 687b ldr r3, [r7, #4]
8001ee4: 6d9b ldr r3, [r3, #88] ; 0x58
8001ee6: 2210 movs r2, #16
8001ee8: 4013 ands r3, r2
8001eea: d000 beq.n 8001eee <HAL_ADC_Init+0xc6>
8001eec: e122 b.n 8002134 <HAL_ADC_Init+0x30c>
&& (tmp_adc_reg_is_conversion_on_going == 0UL)
8001eee: 693b ldr r3, [r7, #16]
8001ef0: 2b00 cmp r3, #0
8001ef2: d000 beq.n 8001ef6 <HAL_ADC_Init+0xce>
8001ef4: e11e b.n 8002134 <HAL_ADC_Init+0x30c>
)
{
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
8001ef6: 687b ldr r3, [r7, #4]
8001ef8: 6d9b ldr r3, [r3, #88] ; 0x58
8001efa: 4a99 ldr r2, [pc, #612] ; (8002160 <HAL_ADC_Init+0x338>)
8001efc: 4013 ands r3, r2
8001efe: 2202 movs r2, #2
8001f00: 431a orrs r2, r3
8001f02: 687b ldr r3, [r7, #4]
8001f04: 659a str r2, [r3, #88] ; 0x58
/* - DMA continuous request */
/* - Trigger frequency mode */
/* Note: If low power mode AutoPowerOff is enabled, ADC enable */
/* and disable phases are performed automatically by hardware */
/* (in this case, flag ADC_FLAG_RDY is not set). */
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
8001f06: 687b ldr r3, [r7, #4]
8001f08: 681b ldr r3, [r3, #0]
8001f0a: 0018 movs r0, r3
8001f0c: f7ff ff46 bl 8001d9c <LL_ADC_IsEnabled>
8001f10: 1e03 subs r3, r0, #0
8001f12: d000 beq.n 8001f16 <HAL_ADC_Init+0xee>
8001f14: e0ad b.n 8002072 <HAL_ADC_Init+0x24a>
/* without needing to reconfigure all other ADC groups/channels */
/* parameters): */
/* - internal measurement paths (VrefInt, ...) */
/* (set into HAL_ADC_ConfigChannel() ) */
tmpCFGR1 |= (hadc->Init.Resolution |
8001f16: 687b ldr r3, [r7, #4]
8001f18: 689a ldr r2, [r3, #8]
ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
8001f1a: 687b ldr r3, [r7, #4]
8001f1c: 7e1b ldrb r3, [r3, #24]
8001f1e: 039b lsls r3, r3, #14
tmpCFGR1 |= (hadc->Init.Resolution |
8001f20: 431a orrs r2, r3
ADC_CFGR1_AUTOOFF((uint32_t)hadc->Init.LowPowerAutoPowerOff) |
8001f22: 687b ldr r3, [r7, #4]
8001f24: 7e5b ldrb r3, [r3, #25]
8001f26: 03db lsls r3, r3, #15
ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
8001f28: 431a orrs r2, r3
ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
8001f2a: 687b ldr r3, [r7, #4]
8001f2c: 7e9b ldrb r3, [r3, #26]
8001f2e: 035b lsls r3, r3, #13
ADC_CFGR1_AUTOOFF((uint32_t)hadc->Init.LowPowerAutoPowerOff) |
8001f30: 431a orrs r2, r3
ADC_CFGR1_OVERRUN(hadc->Init.Overrun) |
8001f32: 687b ldr r3, [r7, #4]
8001f34: 6b1b ldr r3, [r3, #48] ; 0x30
8001f36: 2b00 cmp r3, #0
8001f38: d002 beq.n 8001f40 <HAL_ADC_Init+0x118>
8001f3a: 2380 movs r3, #128 ; 0x80
8001f3c: 015b lsls r3, r3, #5
8001f3e: e000 b.n 8001f42 <HAL_ADC_Init+0x11a>
8001f40: 2300 movs r3, #0
ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
8001f42: 431a orrs r2, r3
hadc->Init.DataAlign |
8001f44: 687b ldr r3, [r7, #4]
8001f46: 68db ldr r3, [r3, #12]
ADC_CFGR1_OVERRUN(hadc->Init.Overrun) |
8001f48: 431a orrs r2, r3
ADC_SCAN_SEQ_MODE(hadc->Init.ScanConvMode) |
8001f4a: 687b ldr r3, [r7, #4]
8001f4c: 691b ldr r3, [r3, #16]
8001f4e: 2b00 cmp r3, #0
8001f50: da04 bge.n 8001f5c <HAL_ADC_Init+0x134>
8001f52: 687b ldr r3, [r7, #4]
8001f54: 691b ldr r3, [r3, #16]
8001f56: 005b lsls r3, r3, #1
8001f58: 085b lsrs r3, r3, #1
8001f5a: e001 b.n 8001f60 <HAL_ADC_Init+0x138>
8001f5c: 2380 movs r3, #128 ; 0x80
8001f5e: 039b lsls r3, r3, #14
hadc->Init.DataAlign |
8001f60: 431a orrs r2, r3
ADC_CFGR1_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests));
8001f62: 687b ldr r3, [r7, #4]
8001f64: 212c movs r1, #44 ; 0x2c
8001f66: 5c5b ldrb r3, [r3, r1]
8001f68: 005b lsls r3, r3, #1
ADC_SCAN_SEQ_MODE(hadc->Init.ScanConvMode) |
8001f6a: 4313 orrs r3, r2
tmpCFGR1 |= (hadc->Init.Resolution |
8001f6c: 69ba ldr r2, [r7, #24]
8001f6e: 4313 orrs r3, r2
8001f70: 61bb str r3, [r7, #24]
/* Update setting of discontinuous mode only if continuous mode is disabled */
if (hadc->Init.DiscontinuousConvMode == ENABLE)
8001f72: 687b ldr r3, [r7, #4]
8001f74: 2220 movs r2, #32
8001f76: 5c9b ldrb r3, [r3, r2]
8001f78: 2b01 cmp r3, #1
8001f7a: d115 bne.n 8001fa8 <HAL_ADC_Init+0x180>
{
if (hadc->Init.ContinuousConvMode == DISABLE)
8001f7c: 687b ldr r3, [r7, #4]
8001f7e: 7e9b ldrb r3, [r3, #26]
8001f80: 2b00 cmp r3, #0
8001f82: d105 bne.n 8001f90 <HAL_ADC_Init+0x168>
{
/* Enable the selected ADC group regular discontinuous mode */
tmpCFGR1 |= ADC_CFGR1_DISCEN;
8001f84: 69bb ldr r3, [r7, #24]
8001f86: 2280 movs r2, #128 ; 0x80
8001f88: 0252 lsls r2, r2, #9
8001f8a: 4313 orrs r3, r2
8001f8c: 61bb str r3, [r7, #24]
8001f8e: e00b b.n 8001fa8 <HAL_ADC_Init+0x180>
/* ADC regular group discontinuous was intended to be enabled, */
/* but ADC regular group modes continuous and sequencer discontinuous */
/* cannot be enabled simultaneously. */
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
8001f90: 687b ldr r3, [r7, #4]
8001f92: 6d9b ldr r3, [r3, #88] ; 0x58
8001f94: 2220 movs r2, #32
8001f96: 431a orrs r2, r3
8001f98: 687b ldr r3, [r7, #4]
8001f9a: 659a str r2, [r3, #88] ; 0x58
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8001f9c: 687b ldr r3, [r7, #4]
8001f9e: 6ddb ldr r3, [r3, #92] ; 0x5c
8001fa0: 2201 movs r2, #1
8001fa2: 431a orrs r2, r3
8001fa4: 687b ldr r3, [r7, #4]
8001fa6: 65da str r2, [r3, #92] ; 0x5c
/* Enable external trigger if trigger selection is different of software */
/* start. */
/* Note: This configuration keeps the hardware feature of parameter */
/* ExternalTrigConvEdge "trigger edge none" equivalent to */
/* software start. */
if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
8001fa8: 687b ldr r3, [r7, #4]
8001faa: 6a5b ldr r3, [r3, #36] ; 0x24
8001fac: 2b00 cmp r3, #0
8001fae: d00a beq.n 8001fc6 <HAL_ADC_Init+0x19e>
{
tmpCFGR1 |= ((hadc->Init.ExternalTrigConv & ADC_CFGR1_EXTSEL) |
8001fb0: 687b ldr r3, [r7, #4]
8001fb2: 6a5a ldr r2, [r3, #36] ; 0x24
8001fb4: 23e0 movs r3, #224 ; 0xe0
8001fb6: 005b lsls r3, r3, #1
8001fb8: 401a ands r2, r3
hadc->Init.ExternalTrigConvEdge);
8001fba: 687b ldr r3, [r7, #4]
8001fbc: 6a9b ldr r3, [r3, #40] ; 0x28
tmpCFGR1 |= ((hadc->Init.ExternalTrigConv & ADC_CFGR1_EXTSEL) |
8001fbe: 4313 orrs r3, r2
8001fc0: 69ba ldr r2, [r7, #24]
8001fc2: 4313 orrs r3, r2
8001fc4: 61bb str r3, [r7, #24]
}
/* Update ADC configuration register with previous settings */
MODIFY_REG(hadc->Instance->CFGR1,
8001fc6: 687b ldr r3, [r7, #4]
8001fc8: 681b ldr r3, [r3, #0]
8001fca: 68db ldr r3, [r3, #12]
8001fcc: 4a65 ldr r2, [pc, #404] ; (8002164 <HAL_ADC_Init+0x33c>)
8001fce: 4013 ands r3, r2
8001fd0: 0019 movs r1, r3
8001fd2: 687b ldr r3, [r7, #4]
8001fd4: 681b ldr r3, [r3, #0]
8001fd6: 69ba ldr r2, [r7, #24]
8001fd8: 430a orrs r2, r1
8001fda: 60da str r2, [r3, #12]
ADC_CFGR1_ALIGN |
ADC_CFGR1_SCANDIR |
ADC_CFGR1_DMACFG,
tmpCFGR1);
tmpCFGR2 |= ((hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) |
8001fdc: 687b ldr r3, [r7, #4]
8001fde: 685b ldr r3, [r3, #4]
8001fe0: 0f9b lsrs r3, r3, #30
8001fe2: 079a lsls r2, r3, #30
hadc->Init.TriggerFrequencyMode
8001fe4: 687b ldr r3, [r7, #4]
8001fe6: 6cdb ldr r3, [r3, #76] ; 0x4c
tmpCFGR2 |= ((hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) |
8001fe8: 4313 orrs r3, r2
8001fea: 697a ldr r2, [r7, #20]
8001fec: 4313 orrs r3, r2
8001fee: 617b str r3, [r7, #20]
);
if (hadc->Init.OversamplingMode == ENABLE)
8001ff0: 687b ldr r3, [r7, #4]
8001ff2: 223c movs r2, #60 ; 0x3c
8001ff4: 5c9b ldrb r3, [r3, r2]
8001ff6: 2b01 cmp r3, #1
8001ff8: d111 bne.n 800201e <HAL_ADC_Init+0x1f6>
{
tmpCFGR2 |= (ADC_CFGR2_OVSE |
(hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) |
8001ffa: 687b ldr r3, [r7, #4]
8001ffc: 685b ldr r3, [r3, #4]
8001ffe: 0f9b lsrs r3, r3, #30
8002000: 079a lsls r2, r3, #30
hadc->Init.Oversampling.Ratio |
8002002: 687b ldr r3, [r7, #4]
8002004: 6c1b ldr r3, [r3, #64] ; 0x40
(hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) |
8002006: 431a orrs r2, r3
hadc->Init.Oversampling.RightBitShift |
8002008: 687b ldr r3, [r7, #4]
800200a: 6c5b ldr r3, [r3, #68] ; 0x44
hadc->Init.Oversampling.Ratio |
800200c: 431a orrs r2, r3
hadc->Init.Oversampling.TriggeredMode
800200e: 687b ldr r3, [r7, #4]
8002010: 6c9b ldr r3, [r3, #72] ; 0x48
hadc->Init.Oversampling.RightBitShift |
8002012: 431a orrs r2, r3
tmpCFGR2 |= (ADC_CFGR2_OVSE |
8002014: 697b ldr r3, [r7, #20]
8002016: 4313 orrs r3, r2
8002018: 2201 movs r2, #1
800201a: 4313 orrs r3, r2
800201c: 617b str r3, [r7, #20]
);
}
MODIFY_REG(hadc->Instance->CFGR2,
800201e: 687b ldr r3, [r7, #4]
8002020: 681b ldr r3, [r3, #0]
8002022: 691b ldr r3, [r3, #16]
8002024: 4a50 ldr r2, [pc, #320] ; (8002168 <HAL_ADC_Init+0x340>)
8002026: 4013 ands r3, r2
8002028: 0019 movs r1, r3
800202a: 687b ldr r3, [r7, #4]
800202c: 681b ldr r3, [r3, #0]
800202e: 697a ldr r2, [r7, #20]
8002030: 430a orrs r2, r1
8002032: 611a str r2, [r3, #16]
ADC_CFGR2_TOVS,
tmpCFGR2);
/* Configuration of ADC clock mode: asynchronous clock source */
/* with selectable prescaler. */
if (((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV1) &&
8002034: 687b ldr r3, [r7, #4]
8002036: 685a ldr r2, [r3, #4]
8002038: 23c0 movs r3, #192 ; 0xc0
800203a: 061b lsls r3, r3, #24
800203c: 429a cmp r2, r3
800203e: d018 beq.n 8002072 <HAL_ADC_Init+0x24a>
((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV2) &&
8002040: 687b ldr r3, [r7, #4]
8002042: 685a ldr r2, [r3, #4]
if (((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV1) &&
8002044: 2380 movs r3, #128 ; 0x80
8002046: 05db lsls r3, r3, #23
8002048: 429a cmp r2, r3
800204a: d012 beq.n 8002072 <HAL_ADC_Init+0x24a>
((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV4))
800204c: 687b ldr r3, [r7, #4]
800204e: 685a ldr r2, [r3, #4]
((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV2) &&
8002050: 2380 movs r3, #128 ; 0x80
8002052: 061b lsls r3, r3, #24
8002054: 429a cmp r2, r3
8002056: d00c beq.n 8002072 <HAL_ADC_Init+0x24a>
{
MODIFY_REG(ADC1_COMMON->CCR,
8002058: 4b44 ldr r3, [pc, #272] ; (800216c <HAL_ADC_Init+0x344>)
800205a: 681b ldr r3, [r3, #0]
800205c: 4a44 ldr r2, [pc, #272] ; (8002170 <HAL_ADC_Init+0x348>)
800205e: 4013 ands r3, r2
8002060: 0019 movs r1, r3
8002062: 687b ldr r3, [r7, #4]
8002064: 685a ldr r2, [r3, #4]
8002066: 23f0 movs r3, #240 ; 0xf0
8002068: 039b lsls r3, r3, #14
800206a: 401a ands r2, r3
800206c: 4b3f ldr r3, [pc, #252] ; (800216c <HAL_ADC_Init+0x344>)
800206e: 430a orrs r2, r1
8002070: 601a str r2, [r3, #0]
hadc->Init.ClockPrescaler & ADC_CCR_PRESC);
}
}
/* Channel sampling time configuration */
LL_ADC_SetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_1, hadc->Init.SamplingTimeCommon1);
8002072: 687b ldr r3, [r7, #4]
8002074: 6818 ldr r0, [r3, #0]
8002076: 687b ldr r3, [r7, #4]
8002078: 6b5b ldr r3, [r3, #52] ; 0x34
800207a: 001a movs r2, r3
800207c: 2100 movs r1, #0
800207e: f7ff fd90 bl 8001ba2 <LL_ADC_SetSamplingTimeCommonChannels>
LL_ADC_SetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_2, hadc->Init.SamplingTimeCommon2);
8002082: 687b ldr r3, [r7, #4]
8002084: 6818 ldr r0, [r3, #0]
8002086: 687b ldr r3, [r7, #4]
8002088: 6b9b ldr r3, [r3, #56] ; 0x38
800208a: 493a ldr r1, [pc, #232] ; (8002174 <HAL_ADC_Init+0x34c>)
800208c: 001a movs r2, r3
800208e: f7ff fd88 bl 8001ba2 <LL_ADC_SetSamplingTimeCommonChannels>
/* emulated by software for alignment over all STM32 devices. */
/* - if scan mode is enabled, regular channels sequence length is set to */
/* parameter "NbrOfConversion". */
/* Channels must be configured into each rank using function */
/* "HAL_ADC_ConfigChannel()". */
if (hadc->Init.ScanConvMode == ADC_SCAN_DISABLE)
8002092: 687b ldr r3, [r7, #4]
8002094: 691b ldr r3, [r3, #16]
8002096: 2b00 cmp r3, #0
8002098: d109 bne.n 80020ae <HAL_ADC_Init+0x286>
{
/* Set sequencer scan length by clearing ranks above rank 1 */
/* and do not modify rank 1 value. */
SET_BIT(hadc->Instance->CHSELR,
800209a: 687b ldr r3, [r7, #4]
800209c: 681b ldr r3, [r3, #0]
800209e: 6a9a ldr r2, [r3, #40] ; 0x28
80020a0: 687b ldr r3, [r7, #4]
80020a2: 681b ldr r3, [r3, #0]
80020a4: 2110 movs r1, #16
80020a6: 4249 negs r1, r1
80020a8: 430a orrs r2, r1
80020aa: 629a str r2, [r3, #40] ; 0x28
80020ac: e018 b.n 80020e0 <HAL_ADC_Init+0x2b8>
ADC_CHSELR_SQ2_TO_SQ8);
}
else if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
80020ae: 687b ldr r3, [r7, #4]
80020b0: 691a ldr r2, [r3, #16]
80020b2: 2380 movs r3, #128 ; 0x80
80020b4: 039b lsls r3, r3, #14
80020b6: 429a cmp r2, r3
80020b8: d112 bne.n 80020e0 <HAL_ADC_Init+0x2b8>
/* therefore after the first call of "HAL_ADC_Init()", */
/* each rank corresponding to parameter "NbrOfConversion" */
/* must be set using "HAL_ADC_ConfigChannel()". */
/* - Set sequencer scan length by clearing ranks above maximum rank */
/* and do not modify other ranks value. */
MODIFY_REG(hadc->Instance->CHSELR,
80020ba: 687b ldr r3, [r7, #4]
80020bc: 681b ldr r3, [r3, #0]
80020be: 6a9b ldr r3, [r3, #40] ; 0x28
80020c0: 687b ldr r3, [r7, #4]
80020c2: 69db ldr r3, [r3, #28]
80020c4: 3b01 subs r3, #1
80020c6: 009b lsls r3, r3, #2
80020c8: 221c movs r2, #28
80020ca: 4013 ands r3, r2
80020cc: 2210 movs r2, #16
80020ce: 4252 negs r2, r2
80020d0: 409a lsls r2, r3
80020d2: 0011 movs r1, r2
80020d4: 687b ldr r3, [r7, #4]
80020d6: 6e1a ldr r2, [r3, #96] ; 0x60
80020d8: 687b ldr r3, [r7, #4]
80020da: 681b ldr r3, [r3, #0]
80020dc: 430a orrs r2, r1
80020de: 629a str r2, [r3, #40] ; 0x28
);
}
/* Check back that ADC registers have effectively been configured to */
/* ensure of no potential problem of ADC core peripheral clocking. */
if(LL_ADC_GetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_1)
80020e0: 687b ldr r3, [r7, #4]
80020e2: 681b ldr r3, [r3, #0]
80020e4: 2100 movs r1, #0
80020e6: 0018 movs r0, r3
80020e8: f7ff fd78 bl 8001bdc <LL_ADC_GetSamplingTimeCommonChannels>
80020ec: 0002 movs r2, r0
== hadc->Init.SamplingTimeCommon1)
80020ee: 687b ldr r3, [r7, #4]
80020f0: 6b5b ldr r3, [r3, #52] ; 0x34
if(LL_ADC_GetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_1)
80020f2: 429a cmp r2, r3
80020f4: d10b bne.n 800210e <HAL_ADC_Init+0x2e6>
{
/* Set ADC error code to none */
ADC_CLEAR_ERRORCODE(hadc);
80020f6: 687b ldr r3, [r7, #4]
80020f8: 2200 movs r2, #0
80020fa: 65da str r2, [r3, #92] ; 0x5c
/* Set the ADC state */
ADC_STATE_CLR_SET(hadc->State,
80020fc: 687b ldr r3, [r7, #4]
80020fe: 6d9b ldr r3, [r3, #88] ; 0x58
8002100: 2203 movs r2, #3
8002102: 4393 bics r3, r2
8002104: 2201 movs r2, #1
8002106: 431a orrs r2, r3
8002108: 687b ldr r3, [r7, #4]
800210a: 659a str r2, [r3, #88] ; 0x58
if(LL_ADC_GetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_1)
800210c: e01c b.n 8002148 <HAL_ADC_Init+0x320>
HAL_ADC_STATE_READY);
}
else
{
/* Update ADC state machine to error */
ADC_STATE_CLR_SET(hadc->State,
800210e: 687b ldr r3, [r7, #4]
8002110: 6d9b ldr r3, [r3, #88] ; 0x58
8002112: 2212 movs r2, #18
8002114: 4393 bics r3, r2
8002116: 2210 movs r2, #16
8002118: 431a orrs r2, r3
800211a: 687b ldr r3, [r7, #4]
800211c: 659a str r2, [r3, #88] ; 0x58
HAL_ADC_STATE_BUSY_INTERNAL,
HAL_ADC_STATE_ERROR_INTERNAL);
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
800211e: 687b ldr r3, [r7, #4]
8002120: 6ddb ldr r3, [r3, #92] ; 0x5c
8002122: 2201 movs r2, #1
8002124: 431a orrs r2, r3
8002126: 687b ldr r3, [r7, #4]
8002128: 65da str r2, [r3, #92] ; 0x5c
tmp_hal_status = HAL_ERROR;
800212a: 231f movs r3, #31
800212c: 18fb adds r3, r7, r3
800212e: 2201 movs r2, #1
8002130: 701a strb r2, [r3, #0]
if(LL_ADC_GetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_1)
8002132: e009 b.n 8002148 <HAL_ADC_Init+0x320>
}
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
8002134: 687b ldr r3, [r7, #4]
8002136: 6d9b ldr r3, [r3, #88] ; 0x58
8002138: 2210 movs r2, #16
800213a: 431a orrs r2, r3
800213c: 687b ldr r3, [r7, #4]
800213e: 659a str r2, [r3, #88] ; 0x58
tmp_hal_status = HAL_ERROR;
8002140: 231f movs r3, #31
8002142: 18fb adds r3, r7, r3
8002144: 2201 movs r2, #1
8002146: 701a strb r2, [r3, #0]
}
return tmp_hal_status;
8002148: 231f movs r3, #31
800214a: 18fb adds r3, r7, r3
800214c: 781b ldrb r3, [r3, #0]
}
800214e: 0018 movs r0, r3
8002150: 46bd mov sp, r7
8002152: b008 add sp, #32
8002154: bd80 pop {r7, pc}
8002156: 46c0 nop ; (mov r8, r8)
8002158: 2000000c .word 0x2000000c
800215c: 00030d40 .word 0x00030d40
8002160: fffffefd .word 0xfffffefd
8002164: fffe0201 .word 0xfffe0201
8002168: 1ffffc02 .word 0x1ffffc02
800216c: 40012708 .word 0x40012708
8002170: ffc3ffff .word 0xffc3ffff
8002174: 07ffff04 .word 0x07ffff04
08002178 <HAL_ADC_Start_IT>:
* before calling HAL_ADC_Start_IT().
* @param hadc ADC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc)
{
8002178: b5b0 push {r4, r5, r7, lr}
800217a: b084 sub sp, #16
800217c: af00 add r7, sp, #0
800217e: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
/* Perform ADC enable and conversion start if no conversion is on going */
if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
8002180: 687b ldr r3, [r7, #4]
8002182: 681b ldr r3, [r3, #0]
8002184: 0018 movs r0, r3
8002186: f7ff fe3d bl 8001e04 <LL_ADC_REG_IsConversionOngoing>
800218a: 1e03 subs r3, r0, #0
800218c: d15f bne.n 800224e <HAL_ADC_Start_IT+0xd6>
{
__HAL_LOCK(hadc);
800218e: 687b ldr r3, [r7, #4]
8002190: 2254 movs r2, #84 ; 0x54
8002192: 5c9b ldrb r3, [r3, r2]
8002194: 2b01 cmp r3, #1
8002196: d101 bne.n 800219c <HAL_ADC_Start_IT+0x24>
8002198: 2302 movs r3, #2
800219a: e05f b.n 800225c <HAL_ADC_Start_IT+0xe4>
800219c: 687b ldr r3, [r7, #4]
800219e: 2254 movs r2, #84 ; 0x54
80021a0: 2101 movs r1, #1
80021a2: 5499 strb r1, [r3, r2]
/* Enable the ADC peripheral */
tmp_hal_status = ADC_Enable(hadc);
80021a4: 250f movs r5, #15
80021a6: 197c adds r4, r7, r5
80021a8: 687b ldr r3, [r7, #4]
80021aa: 0018 movs r0, r3
80021ac: f000 fb68 bl 8002880 <ADC_Enable>
80021b0: 0003 movs r3, r0
80021b2: 7023 strb r3, [r4, #0]
/* Start conversion if ADC is effectively enabled */
if (tmp_hal_status == HAL_OK)
80021b4: 197b adds r3, r7, r5
80021b6: 781b ldrb r3, [r3, #0]
80021b8: 2b00 cmp r3, #0
80021ba: d143 bne.n 8002244 <HAL_ADC_Start_IT+0xcc>
{
/* Set ADC state */
/* - Clear state bitfield related to regular group conversion results */
/* - Set state bitfield related to regular operation */
ADC_STATE_CLR_SET(hadc->State,
80021bc: 687b ldr r3, [r7, #4]
80021be: 6d9b ldr r3, [r3, #88] ; 0x58
80021c0: 4a28 ldr r2, [pc, #160] ; (8002264 <HAL_ADC_Start_IT+0xec>)
80021c2: 4013 ands r3, r2
80021c4: 2280 movs r2, #128 ; 0x80
80021c6: 0052 lsls r2, r2, #1
80021c8: 431a orrs r2, r3
80021ca: 687b ldr r3, [r7, #4]
80021cc: 659a str r2, [r3, #88] ; 0x58
HAL_ADC_STATE_REG_BUSY);
/* Set ADC error code */
/* Reset all ADC error code fields */
ADC_CLEAR_ERRORCODE(hadc);
80021ce: 687b ldr r3, [r7, #4]
80021d0: 2200 movs r2, #0
80021d2: 65da str r2, [r3, #92] ; 0x5c
/* Clear ADC group regular conversion flag and overrun flag */
/* (To ensure of no unknown state from potential previous ADC operations) */
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
80021d4: 687b ldr r3, [r7, #4]
80021d6: 681b ldr r3, [r3, #0]
80021d8: 221c movs r2, #28
80021da: 601a str r2, [r3, #0]
/* Process unlocked */
/* Unlock before starting ADC conversions: in case of potential */
/* interruption, to let the process to ADC IRQ Handler. */
__HAL_UNLOCK(hadc);
80021dc: 687b ldr r3, [r7, #4]
80021de: 2254 movs r2, #84 ; 0x54
80021e0: 2100 movs r1, #0
80021e2: 5499 strb r1, [r3, r2]
/* Disable all interruptions before enabling the desired ones */
__HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
80021e4: 687b ldr r3, [r7, #4]
80021e6: 681b ldr r3, [r3, #0]
80021e8: 685a ldr r2, [r3, #4]
80021ea: 687b ldr r3, [r7, #4]
80021ec: 681b ldr r3, [r3, #0]
80021ee: 211c movs r1, #28
80021f0: 438a bics r2, r1
80021f2: 605a str r2, [r3, #4]
/* Enable ADC end of conversion interrupt */
switch (hadc->Init.EOCSelection)
80021f4: 687b ldr r3, [r7, #4]
80021f6: 695b ldr r3, [r3, #20]
80021f8: 2b08 cmp r3, #8
80021fa: d108 bne.n 800220e <HAL_ADC_Start_IT+0x96>
{
case ADC_EOC_SEQ_CONV:
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOS);
80021fc: 687b ldr r3, [r7, #4]
80021fe: 681b ldr r3, [r3, #0]
8002200: 685a ldr r2, [r3, #4]
8002202: 687b ldr r3, [r7, #4]
8002204: 681b ldr r3, [r3, #0]
8002206: 2108 movs r1, #8
8002208: 430a orrs r2, r1
800220a: 605a str r2, [r3, #4]
break;
800220c: e008 b.n 8002220 <HAL_ADC_Start_IT+0xa8>
/* case ADC_EOC_SINGLE_CONV */
default:
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
800220e: 687b ldr r3, [r7, #4]
8002210: 681b ldr r3, [r3, #0]
8002212: 685a ldr r2, [r3, #4]
8002214: 687b ldr r3, [r7, #4]
8002216: 681b ldr r3, [r3, #0]
8002218: 2104 movs r1, #4
800221a: 430a orrs r2, r1
800221c: 605a str r2, [r3, #4]
break;
800221e: 46c0 nop ; (mov r8, r8)
/* Enable ADC overrun interrupt */
/* If hadc->Init.Overrun is set to ADC_OVR_DATA_PRESERVED, only then is
ADC_IT_OVR enabled; otherwise data overwrite is considered as normal
behavior and no CPU time is lost for a non-processed interruption */
if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
8002220: 687b ldr r3, [r7, #4]
8002222: 6b1b ldr r3, [r3, #48] ; 0x30
8002224: 2b00 cmp r3, #0
8002226: d107 bne.n 8002238 <HAL_ADC_Start_IT+0xc0>
{
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
8002228: 687b ldr r3, [r7, #4]
800222a: 681b ldr r3, [r3, #0]
800222c: 685a ldr r2, [r3, #4]
800222e: 687b ldr r3, [r7, #4]
8002230: 681b ldr r3, [r3, #0]
8002232: 2110 movs r1, #16
8002234: 430a orrs r2, r1
8002236: 605a str r2, [r3, #4]
/* Enable conversion of regular group. */
/* If software start has been selected, conversion starts immediately. */
/* If external trigger has been selected, conversion will start at next */
/* trigger event. */
/* Start ADC group regular conversion */
LL_ADC_REG_StartConversion(hadc->Instance);
8002238: 687b ldr r3, [r7, #4]
800223a: 681b ldr r3, [r3, #0]
800223c: 0018 movs r0, r3
800223e: f7ff fdcf bl 8001de0 <LL_ADC_REG_StartConversion>
8002242: e008 b.n 8002256 <HAL_ADC_Start_IT+0xde>
}
else
{
__HAL_UNLOCK(hadc);
8002244: 687b ldr r3, [r7, #4]
8002246: 2254 movs r2, #84 ; 0x54
8002248: 2100 movs r1, #0
800224a: 5499 strb r1, [r3, r2]
800224c: e003 b.n 8002256 <HAL_ADC_Start_IT+0xde>
}
}
else
{
tmp_hal_status = HAL_BUSY;
800224e: 230f movs r3, #15
8002250: 18fb adds r3, r7, r3
8002252: 2202 movs r2, #2
8002254: 701a strb r2, [r3, #0]
}
return tmp_hal_status;
8002256: 230f movs r3, #15
8002258: 18fb adds r3, r7, r3
800225a: 781b ldrb r3, [r3, #0]
}
800225c: 0018 movs r0, r3
800225e: 46bd mov sp, r7
8002260: b004 add sp, #16
8002262: bdb0 pop {r4, r5, r7, pc}
8002264: fffff0fe .word 0xfffff0fe
08002268 <HAL_ADC_GetValue>:
* or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
* @param hadc ADC handle
* @retval ADC group regular conversion data
*/
uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc)
{
8002268: b580 push {r7, lr}
800226a: b082 sub sp, #8
800226c: af00 add r7, sp, #0
800226e: 6078 str r0, [r7, #4]
/* Note: EOC flag is not cleared here by software because automatically */
/* cleared by hardware when reading register DR. */
/* Return ADC converted value */
return hadc->Instance->DR;
8002270: 687b ldr r3, [r7, #4]
8002272: 681b ldr r3, [r3, #0]
8002274: 6c1b ldr r3, [r3, #64] ; 0x40
}
8002276: 0018 movs r0, r3
8002278: 46bd mov sp, r7
800227a: b002 add sp, #8
800227c: bd80 pop {r7, pc}
...
08002280 <HAL_ADC_IRQHandler>:
* @brief Handle ADC interrupt request.
* @param hadc ADC handle
* @retval None
*/
void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc)
{
8002280: b580 push {r7, lr}
8002282: b086 sub sp, #24
8002284: af00 add r7, sp, #0
8002286: 6078 str r0, [r7, #4]
uint32_t overrun_error = 0UL; /* flag set if overrun occurrence has to be considered as an error */
8002288: 2300 movs r3, #0
800228a: 617b str r3, [r7, #20]
uint32_t tmp_isr = hadc->Instance->ISR;
800228c: 687b ldr r3, [r7, #4]
800228e: 681b ldr r3, [r3, #0]
8002290: 681b ldr r3, [r3, #0]
8002292: 613b str r3, [r7, #16]
uint32_t tmp_ier = hadc->Instance->IER;
8002294: 687b ldr r3, [r7, #4]
8002296: 681b ldr r3, [r3, #0]
8002298: 685b ldr r3, [r3, #4]
800229a: 60fb str r3, [r7, #12]
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
/* ========== Check End of Sampling flag for ADC group regular ========== */
if (((tmp_isr & ADC_FLAG_EOSMP) == ADC_FLAG_EOSMP) && ((tmp_ier & ADC_IT_EOSMP) == ADC_IT_EOSMP))
800229c: 693b ldr r3, [r7, #16]
800229e: 2202 movs r2, #2
80022a0: 4013 ands r3, r2
80022a2: d017 beq.n 80022d4 <HAL_ADC_IRQHandler+0x54>
80022a4: 68fb ldr r3, [r7, #12]
80022a6: 2202 movs r2, #2
80022a8: 4013 ands r3, r2
80022aa: d013 beq.n 80022d4 <HAL_ADC_IRQHandler+0x54>
{
/* Update state machine on end of sampling status if not in error state */
if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
80022ac: 687b ldr r3, [r7, #4]
80022ae: 6d9b ldr r3, [r3, #88] ; 0x58
80022b0: 2210 movs r2, #16
80022b2: 4013 ands r3, r2
80022b4: d106 bne.n 80022c4 <HAL_ADC_IRQHandler+0x44>
{
/* Set ADC state */
SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
80022b6: 687b ldr r3, [r7, #4]
80022b8: 6d9b ldr r3, [r3, #88] ; 0x58
80022ba: 2280 movs r2, #128 ; 0x80
80022bc: 0112 lsls r2, r2, #4
80022be: 431a orrs r2, r3
80022c0: 687b ldr r3, [r7, #4]
80022c2: 659a str r2, [r3, #88] ; 0x58
/* End Of Sampling callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->EndOfSamplingCallback(hadc);
#else
HAL_ADCEx_EndOfSamplingCallback(hadc);
80022c4: 687b ldr r3, [r7, #4]
80022c6: 0018 movs r0, r3
80022c8: f000 fd24 bl 8002d14 <HAL_ADCEx_EndOfSamplingCallback>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Clear regular group conversion flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
80022cc: 687b ldr r3, [r7, #4]
80022ce: 681b ldr r3, [r3, #0]
80022d0: 2202 movs r2, #2
80022d2: 601a str r2, [r3, #0]
}
/* ====== Check ADC group regular end of unitary conversion sequence conversions ===== */
if ((((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) ||
80022d4: 693b ldr r3, [r7, #16]
80022d6: 2204 movs r2, #4
80022d8: 4013 ands r3, r2
80022da: d003 beq.n 80022e4 <HAL_ADC_IRQHandler+0x64>
80022dc: 68fb ldr r3, [r7, #12]
80022de: 2204 movs r2, #4
80022e0: 4013 ands r3, r2
80022e2: d107 bne.n 80022f4 <HAL_ADC_IRQHandler+0x74>
(((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS)))
80022e4: 693b ldr r3, [r7, #16]
80022e6: 2208 movs r2, #8
80022e8: 4013 ands r3, r2
if ((((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) ||
80022ea: d04d beq.n 8002388 <HAL_ADC_IRQHandler+0x108>
(((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS)))
80022ec: 68fb ldr r3, [r7, #12]
80022ee: 2208 movs r2, #8
80022f0: 4013 ands r3, r2
80022f2: d049 beq.n 8002388 <HAL_ADC_IRQHandler+0x108>
{
/* Update state machine on conversion status if not in error state */
if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
80022f4: 687b ldr r3, [r7, #4]
80022f6: 6d9b ldr r3, [r3, #88] ; 0x58
80022f8: 2210 movs r2, #16
80022fa: 4013 ands r3, r2
80022fc: d106 bne.n 800230c <HAL_ADC_IRQHandler+0x8c>
{
/* Set ADC state */
SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
80022fe: 687b ldr r3, [r7, #4]
8002300: 6d9b ldr r3, [r3, #88] ; 0x58
8002302: 2280 movs r2, #128 ; 0x80
8002304: 0092 lsls r2, r2, #2
8002306: 431a orrs r2, r3
8002308: 687b ldr r3, [r7, #4]
800230a: 659a str r2, [r3, #88] ; 0x58
}
/* Determine whether any further conversion upcoming on group regular */
/* by external trigger, continuous mode or scan sequence on going */
/* to disable interruption. */
if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
800230c: 687b ldr r3, [r7, #4]
800230e: 681b ldr r3, [r3, #0]
8002310: 0018 movs r0, r3
8002312: f7ff fc7a bl 8001c0a <LL_ADC_REG_IsTriggerSourceSWStart>
8002316: 1e03 subs r3, r0, #0
8002318: d02e beq.n 8002378 <HAL_ADC_IRQHandler+0xf8>
&& (hadc->Init.ContinuousConvMode == DISABLE)
800231a: 687b ldr r3, [r7, #4]
800231c: 7e9b ldrb r3, [r3, #26]
800231e: 2b00 cmp r3, #0
8002320: d12a bne.n 8002378 <HAL_ADC_IRQHandler+0xf8>
)
{
/* If End of Sequence is reached, disable interrupts */
if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
8002322: 687b ldr r3, [r7, #4]
8002324: 681b ldr r3, [r3, #0]
8002326: 681b ldr r3, [r3, #0]
8002328: 2208 movs r2, #8
800232a: 4013 ands r3, r2
800232c: 2b08 cmp r3, #8
800232e: d123 bne.n 8002378 <HAL_ADC_IRQHandler+0xf8>
{
/* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
/* ADSTART==0 (no conversion on going) */
if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
8002330: 687b ldr r3, [r7, #4]
8002332: 681b ldr r3, [r3, #0]
8002334: 0018 movs r0, r3
8002336: f7ff fd65 bl 8001e04 <LL_ADC_REG_IsConversionOngoing>
800233a: 1e03 subs r3, r0, #0
800233c: d110 bne.n 8002360 <HAL_ADC_IRQHandler+0xe0>
{
/* Disable ADC end of single conversion interrupt on group regular */
/* Note: Overrun interrupt was enabled with EOC interrupt in */
/* HAL_Start_IT(), but is not disabled here because can be used */
/* by overrun IRQ process below. */
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
800233e: 687b ldr r3, [r7, #4]
8002340: 681b ldr r3, [r3, #0]
8002342: 685a ldr r2, [r3, #4]
8002344: 687b ldr r3, [r7, #4]
8002346: 681b ldr r3, [r3, #0]
8002348: 210c movs r1, #12
800234a: 438a bics r2, r1
800234c: 605a str r2, [r3, #4]
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
800234e: 687b ldr r3, [r7, #4]
8002350: 6d9b ldr r3, [r3, #88] ; 0x58
8002352: 4a56 ldr r2, [pc, #344] ; (80024ac <HAL_ADC_IRQHandler+0x22c>)
8002354: 4013 ands r3, r2
8002356: 2201 movs r2, #1
8002358: 431a orrs r2, r3
800235a: 687b ldr r3, [r7, #4]
800235c: 659a str r2, [r3, #88] ; 0x58
800235e: e00b b.n 8002378 <HAL_ADC_IRQHandler+0xf8>
HAL_ADC_STATE_READY);
}
else
{
/* Change ADC state to error state */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
8002360: 687b ldr r3, [r7, #4]
8002362: 6d9b ldr r3, [r3, #88] ; 0x58
8002364: 2220 movs r2, #32
8002366: 431a orrs r2, r3
8002368: 687b ldr r3, [r7, #4]
800236a: 659a str r2, [r3, #88] ; 0x58
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
800236c: 687b ldr r3, [r7, #4]
800236e: 6ddb ldr r3, [r3, #92] ; 0x5c
8002370: 2201 movs r2, #1
8002372: 431a orrs r2, r3
8002374: 687b ldr r3, [r7, #4]
8002376: 65da str r2, [r3, #92] ; 0x5c
/* possibility to use: */
/* " if ( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->ConvCpltCallback(hadc);
#else
HAL_ADC_ConvCpltCallback(hadc);
8002378: 687b ldr r3, [r7, #4]
800237a: 0018 movs r0, r3
800237c: f7fe fb12 bl 80009a4 <HAL_ADC_ConvCpltCallback>
/* Clear regular group conversion flag */
/* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */
/* conversion flags clear induces the release of the preserved data.*/
/* Therefore, if the preserved data value is needed, it must be */
/* read preliminarily into HAL_ADC_ConvCpltCallback(). */
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
8002380: 687b ldr r3, [r7, #4]
8002382: 681b ldr r3, [r3, #0]
8002384: 220c movs r2, #12
8002386: 601a str r2, [r3, #0]
}
/* ========== Check Analog watchdog 1 flag ========== */
if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1))
8002388: 693b ldr r3, [r7, #16]
800238a: 2280 movs r2, #128 ; 0x80
800238c: 4013 ands r3, r2
800238e: d012 beq.n 80023b6 <HAL_ADC_IRQHandler+0x136>
8002390: 68fb ldr r3, [r7, #12]
8002392: 2280 movs r2, #128 ; 0x80
8002394: 4013 ands r3, r2
8002396: d00e beq.n 80023b6 <HAL_ADC_IRQHandler+0x136>
{
/* Set ADC state */
SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
8002398: 687b ldr r3, [r7, #4]
800239a: 6d9b ldr r3, [r3, #88] ; 0x58
800239c: 2280 movs r2, #128 ; 0x80
800239e: 0252 lsls r2, r2, #9
80023a0: 431a orrs r2, r3
80023a2: 687b ldr r3, [r7, #4]
80023a4: 659a str r2, [r3, #88] ; 0x58
/* Level out of window 1 callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->LevelOutOfWindowCallback(hadc);
#else
HAL_ADC_LevelOutOfWindowCallback(hadc);
80023a6: 687b ldr r3, [r7, #4]
80023a8: 0018 movs r0, r3
80023aa: f000 f881 bl 80024b0 <HAL_ADC_LevelOutOfWindowCallback>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Clear ADC analog watchdog flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
80023ae: 687b ldr r3, [r7, #4]
80023b0: 681b ldr r3, [r3, #0]
80023b2: 2280 movs r2, #128 ; 0x80
80023b4: 601a str r2, [r3, #0]
}
/* ========== Check analog watchdog 2 flag ========== */
if (((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) && ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2))
80023b6: 693a ldr r2, [r7, #16]
80023b8: 2380 movs r3, #128 ; 0x80
80023ba: 005b lsls r3, r3, #1
80023bc: 4013 ands r3, r2
80023be: d014 beq.n 80023ea <HAL_ADC_IRQHandler+0x16a>
80023c0: 68fa ldr r2, [r7, #12]
80023c2: 2380 movs r3, #128 ; 0x80
80023c4: 005b lsls r3, r3, #1
80023c6: 4013 ands r3, r2
80023c8: d00f beq.n 80023ea <HAL_ADC_IRQHandler+0x16a>
{
/* Set ADC state */
SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
80023ca: 687b ldr r3, [r7, #4]
80023cc: 6d9b ldr r3, [r3, #88] ; 0x58
80023ce: 2280 movs r2, #128 ; 0x80
80023d0: 0292 lsls r2, r2, #10
80023d2: 431a orrs r2, r3
80023d4: 687b ldr r3, [r7, #4]
80023d6: 659a str r2, [r3, #88] ; 0x58
/* Level out of window 2 callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->LevelOutOfWindow2Callback(hadc);
#else
HAL_ADCEx_LevelOutOfWindow2Callback(hadc);
80023d8: 687b ldr r3, [r7, #4]
80023da: 0018 movs r0, r3
80023dc: f000 fc8a bl 8002cf4 <HAL_ADCEx_LevelOutOfWindow2Callback>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Clear ADC analog watchdog flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
80023e0: 687b ldr r3, [r7, #4]
80023e2: 681b ldr r3, [r3, #0]
80023e4: 2280 movs r2, #128 ; 0x80
80023e6: 0052 lsls r2, r2, #1
80023e8: 601a str r2, [r3, #0]
}
/* ========== Check analog watchdog 3 flag ========== */
if (((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3))
80023ea: 693a ldr r2, [r7, #16]
80023ec: 2380 movs r3, #128 ; 0x80
80023ee: 009b lsls r3, r3, #2
80023f0: 4013 ands r3, r2
80023f2: d014 beq.n 800241e <HAL_ADC_IRQHandler+0x19e>
80023f4: 68fa ldr r2, [r7, #12]
80023f6: 2380 movs r3, #128 ; 0x80
80023f8: 009b lsls r3, r3, #2
80023fa: 4013 ands r3, r2
80023fc: d00f beq.n 800241e <HAL_ADC_IRQHandler+0x19e>
{
/* Set ADC state */
SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
80023fe: 687b ldr r3, [r7, #4]
8002400: 6d9b ldr r3, [r3, #88] ; 0x58
8002402: 2280 movs r2, #128 ; 0x80
8002404: 02d2 lsls r2, r2, #11
8002406: 431a orrs r2, r3
8002408: 687b ldr r3, [r7, #4]
800240a: 659a str r2, [r3, #88] ; 0x58
/* Level out of window 3 callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->LevelOutOfWindow3Callback(hadc);
#else
HAL_ADCEx_LevelOutOfWindow3Callback(hadc);
800240c: 687b ldr r3, [r7, #4]
800240e: 0018 movs r0, r3
8002410: f000 fc78 bl 8002d04 <HAL_ADCEx_LevelOutOfWindow3Callback>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Clear ADC analog watchdog flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
8002414: 687b ldr r3, [r7, #4]
8002416: 681b ldr r3, [r3, #0]
8002418: 2280 movs r2, #128 ; 0x80
800241a: 0092 lsls r2, r2, #2
800241c: 601a str r2, [r3, #0]
}
/* ========== Check Overrun flag ========== */
if (((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) && ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR))
800241e: 693b ldr r3, [r7, #16]
8002420: 2210 movs r2, #16
8002422: 4013 ands r3, r2
8002424: d02b beq.n 800247e <HAL_ADC_IRQHandler+0x1fe>
8002426: 68fb ldr r3, [r7, #12]
8002428: 2210 movs r2, #16
800242a: 4013 ands r3, r2
800242c: d027 beq.n 800247e <HAL_ADC_IRQHandler+0x1fe>
/* overrun event is not considered as an error. */
/* (cf ref manual "Managing conversions without using the DMA and without */
/* overrun ") */
/* Exception for usage with DMA overrun event always considered as an */
/* error. */
if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
800242e: 687b ldr r3, [r7, #4]
8002430: 6b1b ldr r3, [r3, #48] ; 0x30
8002432: 2b00 cmp r3, #0
8002434: d102 bne.n 800243c <HAL_ADC_IRQHandler+0x1bc>
{
overrun_error = 1UL;
8002436: 2301 movs r3, #1
8002438: 617b str r3, [r7, #20]
800243a: e008 b.n 800244e <HAL_ADC_IRQHandler+0x1ce>
}
else
{
/* Check DMA configuration */
if (LL_ADC_REG_GetDMATransfer(hadc->Instance) != LL_ADC_REG_DMA_TRANSFER_NONE)
800243c: 687b ldr r3, [r7, #4]
800243e: 681b ldr r3, [r3, #0]
8002440: 0018 movs r0, r3
8002442: f7ff fc36 bl 8001cb2 <LL_ADC_REG_GetDMATransfer>
8002446: 1e03 subs r3, r0, #0
8002448: d001 beq.n 800244e <HAL_ADC_IRQHandler+0x1ce>
{
overrun_error = 1UL;
800244a: 2301 movs r3, #1
800244c: 617b str r3, [r7, #20]
}
}
if (overrun_error == 1UL)
800244e: 697b ldr r3, [r7, #20]
8002450: 2b01 cmp r3, #1
8002452: d110 bne.n 8002476 <HAL_ADC_IRQHandler+0x1f6>
{
/* Change ADC state to error state */
SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
8002454: 687b ldr r3, [r7, #4]
8002456: 6d9b ldr r3, [r3, #88] ; 0x58
8002458: 2280 movs r2, #128 ; 0x80
800245a: 00d2 lsls r2, r2, #3
800245c: 431a orrs r2, r3
800245e: 687b ldr r3, [r7, #4]
8002460: 659a str r2, [r3, #88] ; 0x58
/* Set ADC error code to overrun */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
8002462: 687b ldr r3, [r7, #4]
8002464: 6ddb ldr r3, [r3, #92] ; 0x5c
8002466: 2202 movs r2, #2
8002468: 431a orrs r2, r3
800246a: 687b ldr r3, [r7, #4]
800246c: 65da str r2, [r3, #92] ; 0x5c
/* Therefore, old ADC conversion data can be retrieved in */
/* function "HAL_ADC_ErrorCallback()". */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->ErrorCallback(hadc);
#else
HAL_ADC_ErrorCallback(hadc);
800246e: 687b ldr r3, [r7, #4]
8002470: 0018 movs r0, r3
8002472: f000 f825 bl 80024c0 <HAL_ADC_ErrorCallback>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
}
/* Clear ADC overrun flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
8002476: 687b ldr r3, [r7, #4]
8002478: 681b ldr r3, [r3, #0]
800247a: 2210 movs r2, #16
800247c: 601a str r2, [r3, #0]
}
/* ========== Check channel configuration ready flag ========== */
if (((tmp_isr & ADC_FLAG_CCRDY) == ADC_FLAG_CCRDY) && ((tmp_ier & ADC_IT_CCRDY) == ADC_IT_CCRDY))
800247e: 693a ldr r2, [r7, #16]
8002480: 2380 movs r3, #128 ; 0x80
8002482: 019b lsls r3, r3, #6
8002484: 4013 ands r3, r2
8002486: d00d beq.n 80024a4 <HAL_ADC_IRQHandler+0x224>
8002488: 68fa ldr r2, [r7, #12]
800248a: 2380 movs r3, #128 ; 0x80
800248c: 019b lsls r3, r3, #6
800248e: 4013 ands r3, r2
8002490: d008 beq.n 80024a4 <HAL_ADC_IRQHandler+0x224>
{
/* Channel configuration ready callback */
HAL_ADCEx_ChannelConfigReadyCallback(hadc);
8002492: 687b ldr r3, [r7, #4]
8002494: 0018 movs r0, r3
8002496: f000 fc45 bl 8002d24 <HAL_ADCEx_ChannelConfigReadyCallback>
/* Clear ADC analog watchdog flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_CCRDY);
800249a: 687b ldr r3, [r7, #4]
800249c: 681b ldr r3, [r3, #0]
800249e: 2280 movs r2, #128 ; 0x80
80024a0: 0192 lsls r2, r2, #6
80024a2: 601a str r2, [r3, #0]
}
}
80024a4: 46c0 nop ; (mov r8, r8)
80024a6: 46bd mov sp, r7
80024a8: b006 add sp, #24
80024aa: bd80 pop {r7, pc}
80024ac: fffffefe .word 0xfffffefe
080024b0 <HAL_ADC_LevelOutOfWindowCallback>:
* @brief Analog watchdog 1 callback in non-blocking mode.
* @param hadc ADC handle
* @retval None
*/
__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc)
{
80024b0: b580 push {r7, lr}
80024b2: b082 sub sp, #8
80024b4: af00 add r7, sp, #0
80024b6: 6078 str r0, [r7, #4]
UNUSED(hadc);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file.
*/
}
80024b8: 46c0 nop ; (mov r8, r8)
80024ba: 46bd mov sp, r7
80024bc: b002 add sp, #8
80024be: bd80 pop {r7, pc}
080024c0 <HAL_ADC_ErrorCallback>:
* (this function is also clearing overrun flag)
* @param hadc ADC handle
* @retval None
*/
__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
{
80024c0: b580 push {r7, lr}
80024c2: b082 sub sp, #8
80024c4: af00 add r7, sp, #0
80024c6: 6078 str r0, [r7, #4]
UNUSED(hadc);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_ADC_ErrorCallback must be implemented in the user file.
*/
}
80024c8: 46c0 nop ; (mov r8, r8)
80024ca: 46bd mov sp, r7
80024cc: b002 add sp, #8
80024ce: bd80 pop {r7, pc}
080024d0 <HAL_ADC_ConfigChannel>:
* @param hadc ADC handle
* @param pConfig Structure of ADC channel assigned to ADC group regular.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *pConfig)
{
80024d0: b580 push {r7, lr}
80024d2: b086 sub sp, #24
80024d4: af00 add r7, sp, #0
80024d6: 6078 str r0, [r7, #4]
80024d8: 6039 str r1, [r7, #0]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
80024da: 2317 movs r3, #23
80024dc: 18fb adds r3, r7, r3
80024de: 2200 movs r2, #0
80024e0: 701a strb r2, [r3, #0]
uint32_t tmp_config_internal_channel;
__IO uint32_t wait_loop_index = 0UL;
80024e2: 2300 movs r3, #0
80024e4: 60fb str r3, [r7, #12]
assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
assert_param(IS_ADC_REGULAR_RANK(pConfig->Rank));
}
__HAL_LOCK(hadc);
80024e6: 687b ldr r3, [r7, #4]
80024e8: 2254 movs r2, #84 ; 0x54
80024ea: 5c9b ldrb r3, [r3, r2]
80024ec: 2b01 cmp r3, #1
80024ee: d101 bne.n 80024f4 <HAL_ADC_ConfigChannel+0x24>
80024f0: 2302 movs r3, #2
80024f2: e1c0 b.n 8002876 <HAL_ADC_ConfigChannel+0x3a6>
80024f4: 687b ldr r3, [r7, #4]
80024f6: 2254 movs r2, #84 ; 0x54
80024f8: 2101 movs r1, #1
80024fa: 5499 strb r1, [r3, r2]
/* Parameters that can be updated when ADC is disabled or enabled without */
/* conversion on going on regular group: */
/* - Channel number */
/* - Channel sampling time */
/* - Management of internal measurement channels: VrefInt/TempSensor/Vbat */
if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
80024fc: 687b ldr r3, [r7, #4]
80024fe: 681b ldr r3, [r3, #0]
8002500: 0018 movs r0, r3
8002502: f7ff fc7f bl 8001e04 <LL_ADC_REG_IsConversionOngoing>
8002506: 1e03 subs r3, r0, #0
8002508: d000 beq.n 800250c <HAL_ADC_ConfigChannel+0x3c>
800250a: e1a3 b.n 8002854 <HAL_ADC_ConfigChannel+0x384>
/* If sequencer set to not fully configurable with channel rank set to */
/* none, remove the channel from the sequencer. */
/* Otherwise (sequencer set to fully configurable or to to not fully */
/* configurable with channel rank to be set), configure the selected */
/* channel. */
if (pConfig->Rank != ADC_RANK_NONE)
800250c: 683b ldr r3, [r7, #0]
800250e: 685b ldr r3, [r3, #4]
8002510: 2b02 cmp r3, #2
8002512: d100 bne.n 8002516 <HAL_ADC_ConfigChannel+0x46>
8002514: e143 b.n 800279e <HAL_ADC_ConfigChannel+0x2ce>
/* Note: ADC channel configuration requires few ADC clock cycles */
/* to be ready. Processing of ADC settings in this function */
/* induce that a specific wait time is not necessary. */
/* For more details on ADC channel configuration ready, */
/* refer to function "LL_ADC_IsActiveFlag_CCRDY()". */
if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) ||
8002516: 687b ldr r3, [r7, #4]
8002518: 691a ldr r2, [r3, #16]
800251a: 2380 movs r3, #128 ; 0x80
800251c: 061b lsls r3, r3, #24
800251e: 429a cmp r2, r3
8002520: d004 beq.n 800252c <HAL_ADC_ConfigChannel+0x5c>
(hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED_BACKWARD))
8002522: 687b ldr r3, [r7, #4]
8002524: 691b ldr r3, [r3, #16]
if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) ||
8002526: 4ac1 ldr r2, [pc, #772] ; (800282c <HAL_ADC_ConfigChannel+0x35c>)
8002528: 4293 cmp r3, r2
800252a: d108 bne.n 800253e <HAL_ADC_ConfigChannel+0x6e>
{
/* Sequencer set to not fully configurable: */
/* Set the channel by enabling the corresponding bitfield. */
LL_ADC_REG_SetSequencerChAdd(hadc->Instance, pConfig->Channel);
800252c: 687b ldr r3, [r7, #4]
800252e: 681a ldr r2, [r3, #0]
8002530: 683b ldr r3, [r7, #0]
8002532: 681b ldr r3, [r3, #0]
8002534: 0019 movs r1, r3
8002536: 0010 movs r0, r2
8002538: f7ff fb98 bl 8001c6c <LL_ADC_REG_SetSequencerChAdd>
800253c: e0c9 b.n 80026d2 <HAL_ADC_ConfigChannel+0x202>
{
/* Sequencer set to fully configurable: */
/* Set the channel by entering it into the selected rank. */
/* Memorize the channel set into variable in HAL ADC handle */
MODIFY_REG(hadc->ADCGroupRegularSequencerRanks,
800253e: 687b ldr r3, [r7, #4]
8002540: 6e1a ldr r2, [r3, #96] ; 0x60
8002542: 683b ldr r3, [r7, #0]
8002544: 685b ldr r3, [r3, #4]
8002546: 211f movs r1, #31
8002548: 400b ands r3, r1
800254a: 210f movs r1, #15
800254c: 4099 lsls r1, r3
800254e: 000b movs r3, r1
8002550: 43db mvns r3, r3
8002552: 4013 ands r3, r2
8002554: 0019 movs r1, r3
8002556: 683b ldr r3, [r7, #0]
8002558: 681b ldr r3, [r3, #0]
800255a: 035b lsls r3, r3, #13
800255c: 0b5b lsrs r3, r3, #13
800255e: d105 bne.n 800256c <HAL_ADC_ConfigChannel+0x9c>
8002560: 683b ldr r3, [r7, #0]
8002562: 681b ldr r3, [r3, #0]
8002564: 0e9b lsrs r3, r3, #26
8002566: 221f movs r2, #31
8002568: 4013 ands r3, r2
800256a: e098 b.n 800269e <HAL_ADC_ConfigChannel+0x1ce>
800256c: 683b ldr r3, [r7, #0]
800256e: 681b ldr r3, [r3, #0]
8002570: 2201 movs r2, #1
8002572: 4013 ands r3, r2
8002574: d000 beq.n 8002578 <HAL_ADC_ConfigChannel+0xa8>
8002576: e091 b.n 800269c <HAL_ADC_ConfigChannel+0x1cc>
8002578: 683b ldr r3, [r7, #0]
800257a: 681b ldr r3, [r3, #0]
800257c: 2202 movs r2, #2
800257e: 4013 ands r3, r2
8002580: d000 beq.n 8002584 <HAL_ADC_ConfigChannel+0xb4>
8002582: e089 b.n 8002698 <HAL_ADC_ConfigChannel+0x1c8>
8002584: 683b ldr r3, [r7, #0]
8002586: 681b ldr r3, [r3, #0]
8002588: 2204 movs r2, #4
800258a: 4013 ands r3, r2
800258c: d000 beq.n 8002590 <HAL_ADC_ConfigChannel+0xc0>
800258e: e081 b.n 8002694 <HAL_ADC_ConfigChannel+0x1c4>
8002590: 683b ldr r3, [r7, #0]
8002592: 681b ldr r3, [r3, #0]
8002594: 2208 movs r2, #8
8002596: 4013 ands r3, r2
8002598: d000 beq.n 800259c <HAL_ADC_ConfigChannel+0xcc>
800259a: e079 b.n 8002690 <HAL_ADC_ConfigChannel+0x1c0>
800259c: 683b ldr r3, [r7, #0]
800259e: 681b ldr r3, [r3, #0]
80025a0: 2210 movs r2, #16
80025a2: 4013 ands r3, r2
80025a4: d000 beq.n 80025a8 <HAL_ADC_ConfigChannel+0xd8>
80025a6: e071 b.n 800268c <HAL_ADC_ConfigChannel+0x1bc>
80025a8: 683b ldr r3, [r7, #0]
80025aa: 681b ldr r3, [r3, #0]
80025ac: 2220 movs r2, #32
80025ae: 4013 ands r3, r2
80025b0: d000 beq.n 80025b4 <HAL_ADC_ConfigChannel+0xe4>
80025b2: e069 b.n 8002688 <HAL_ADC_ConfigChannel+0x1b8>
80025b4: 683b ldr r3, [r7, #0]
80025b6: 681b ldr r3, [r3, #0]
80025b8: 2240 movs r2, #64 ; 0x40
80025ba: 4013 ands r3, r2
80025bc: d000 beq.n 80025c0 <HAL_ADC_ConfigChannel+0xf0>
80025be: e061 b.n 8002684 <HAL_ADC_ConfigChannel+0x1b4>
80025c0: 683b ldr r3, [r7, #0]
80025c2: 681b ldr r3, [r3, #0]
80025c4: 2280 movs r2, #128 ; 0x80
80025c6: 4013 ands r3, r2
80025c8: d000 beq.n 80025cc <HAL_ADC_ConfigChannel+0xfc>
80025ca: e059 b.n 8002680 <HAL_ADC_ConfigChannel+0x1b0>
80025cc: 683b ldr r3, [r7, #0]
80025ce: 681a ldr r2, [r3, #0]
80025d0: 2380 movs r3, #128 ; 0x80
80025d2: 005b lsls r3, r3, #1
80025d4: 4013 ands r3, r2
80025d6: d151 bne.n 800267c <HAL_ADC_ConfigChannel+0x1ac>
80025d8: 683b ldr r3, [r7, #0]
80025da: 681a ldr r2, [r3, #0]
80025dc: 2380 movs r3, #128 ; 0x80
80025de: 009b lsls r3, r3, #2
80025e0: 4013 ands r3, r2
80025e2: d149 bne.n 8002678 <HAL_ADC_ConfigChannel+0x1a8>
80025e4: 683b ldr r3, [r7, #0]
80025e6: 681a ldr r2, [r3, #0]
80025e8: 2380 movs r3, #128 ; 0x80
80025ea: 00db lsls r3, r3, #3
80025ec: 4013 ands r3, r2
80025ee: d141 bne.n 8002674 <HAL_ADC_ConfigChannel+0x1a4>
80025f0: 683b ldr r3, [r7, #0]
80025f2: 681a ldr r2, [r3, #0]
80025f4: 2380 movs r3, #128 ; 0x80
80025f6: 011b lsls r3, r3, #4
80025f8: 4013 ands r3, r2
80025fa: d139 bne.n 8002670 <HAL_ADC_ConfigChannel+0x1a0>
80025fc: 683b ldr r3, [r7, #0]
80025fe: 681a ldr r2, [r3, #0]
8002600: 2380 movs r3, #128 ; 0x80
8002602: 015b lsls r3, r3, #5
8002604: 4013 ands r3, r2
8002606: d131 bne.n 800266c <HAL_ADC_ConfigChannel+0x19c>
8002608: 683b ldr r3, [r7, #0]
800260a: 681a ldr r2, [r3, #0]
800260c: 2380 movs r3, #128 ; 0x80
800260e: 019b lsls r3, r3, #6
8002610: 4013 ands r3, r2
8002612: d129 bne.n 8002668 <HAL_ADC_ConfigChannel+0x198>
8002614: 683b ldr r3, [r7, #0]
8002616: 681a ldr r2, [r3, #0]
8002618: 2380 movs r3, #128 ; 0x80
800261a: 01db lsls r3, r3, #7
800261c: 4013 ands r3, r2
800261e: d121 bne.n 8002664 <HAL_ADC_ConfigChannel+0x194>
8002620: 683b ldr r3, [r7, #0]
8002622: 681a ldr r2, [r3, #0]
8002624: 2380 movs r3, #128 ; 0x80
8002626: 021b lsls r3, r3, #8
8002628: 4013 ands r3, r2
800262a: d119 bne.n 8002660 <HAL_ADC_ConfigChannel+0x190>
800262c: 683b ldr r3, [r7, #0]
800262e: 681a ldr r2, [r3, #0]
8002630: 2380 movs r3, #128 ; 0x80
8002632: 025b lsls r3, r3, #9
8002634: 4013 ands r3, r2
8002636: d111 bne.n 800265c <HAL_ADC_ConfigChannel+0x18c>
8002638: 683b ldr r3, [r7, #0]
800263a: 681a ldr r2, [r3, #0]
800263c: 2380 movs r3, #128 ; 0x80
800263e: 029b lsls r3, r3, #10
8002640: 4013 ands r3, r2
8002642: d109 bne.n 8002658 <HAL_ADC_ConfigChannel+0x188>
8002644: 683b ldr r3, [r7, #0]
8002646: 681a ldr r2, [r3, #0]
8002648: 2380 movs r3, #128 ; 0x80
800264a: 02db lsls r3, r3, #11
800264c: 4013 ands r3, r2
800264e: d001 beq.n 8002654 <HAL_ADC_ConfigChannel+0x184>
8002650: 2312 movs r3, #18
8002652: e024 b.n 800269e <HAL_ADC_ConfigChannel+0x1ce>
8002654: 2300 movs r3, #0
8002656: e022 b.n 800269e <HAL_ADC_ConfigChannel+0x1ce>
8002658: 2311 movs r3, #17
800265a: e020 b.n 800269e <HAL_ADC_ConfigChannel+0x1ce>
800265c: 2310 movs r3, #16
800265e: e01e b.n 800269e <HAL_ADC_ConfigChannel+0x1ce>
8002660: 230f movs r3, #15
8002662: e01c b.n 800269e <HAL_ADC_ConfigChannel+0x1ce>
8002664: 230e movs r3, #14
8002666: e01a b.n 800269e <HAL_ADC_ConfigChannel+0x1ce>
8002668: 230d movs r3, #13
800266a: e018 b.n 800269e <HAL_ADC_ConfigChannel+0x1ce>
800266c: 230c movs r3, #12
800266e: e016 b.n 800269e <HAL_ADC_ConfigChannel+0x1ce>
8002670: 230b movs r3, #11
8002672: e014 b.n 800269e <HAL_ADC_ConfigChannel+0x1ce>
8002674: 230a movs r3, #10
8002676: e012 b.n 800269e <HAL_ADC_ConfigChannel+0x1ce>
8002678: 2309 movs r3, #9
800267a: e010 b.n 800269e <HAL_ADC_ConfigChannel+0x1ce>
800267c: 2308 movs r3, #8
800267e: e00e b.n 800269e <HAL_ADC_ConfigChannel+0x1ce>
8002680: 2307 movs r3, #7
8002682: e00c b.n 800269e <HAL_ADC_ConfigChannel+0x1ce>
8002684: 2306 movs r3, #6
8002686: e00a b.n 800269e <HAL_ADC_ConfigChannel+0x1ce>
8002688: 2305 movs r3, #5
800268a: e008 b.n 800269e <HAL_ADC_ConfigChannel+0x1ce>
800268c: 2304 movs r3, #4
800268e: e006 b.n 800269e <HAL_ADC_ConfigChannel+0x1ce>
8002690: 2303 movs r3, #3
8002692: e004 b.n 800269e <HAL_ADC_ConfigChannel+0x1ce>
8002694: 2302 movs r3, #2
8002696: e002 b.n 800269e <HAL_ADC_ConfigChannel+0x1ce>
8002698: 2301 movs r3, #1
800269a: e000 b.n 800269e <HAL_ADC_ConfigChannel+0x1ce>
800269c: 2300 movs r3, #0
800269e: 683a ldr r2, [r7, #0]
80026a0: 6852 ldr r2, [r2, #4]
80026a2: 201f movs r0, #31
80026a4: 4002 ands r2, r0
80026a6: 4093 lsls r3, r2
80026a8: 000a movs r2, r1
80026aa: 431a orrs r2, r3
80026ac: 687b ldr r3, [r7, #4]
80026ae: 661a str r2, [r3, #96] ; 0x60
/* If the selected rank is below ADC group regular sequencer length, */
/* apply the configuration in ADC register. */
/* Note: Otherwise, configuration is not applied. */
/* To apply it, parameter'NbrOfConversion' must be increased. */
if (((pConfig->Rank >> 2UL) + 1UL) <= hadc->Init.NbrOfConversion)
80026b0: 683b ldr r3, [r7, #0]
80026b2: 685b ldr r3, [r3, #4]
80026b4: 089b lsrs r3, r3, #2
80026b6: 1c5a adds r2, r3, #1
80026b8: 687b ldr r3, [r7, #4]
80026ba: 69db ldr r3, [r3, #28]
80026bc: 429a cmp r2, r3
80026be: d808 bhi.n 80026d2 <HAL_ADC_ConfigChannel+0x202>
{
LL_ADC_REG_SetSequencerRanks(hadc->Instance, pConfig->Rank, pConfig->Channel);
80026c0: 687b ldr r3, [r7, #4]
80026c2: 6818 ldr r0, [r3, #0]
80026c4: 683b ldr r3, [r7, #0]
80026c6: 6859 ldr r1, [r3, #4]
80026c8: 683b ldr r3, [r7, #0]
80026ca: 681b ldr r3, [r3, #0]
80026cc: 001a movs r2, r3
80026ce: f7ff faad bl 8001c2c <LL_ADC_REG_SetSequencerRanks>
}
}
/* Set sampling time of the selected ADC channel */
LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfig->Channel, pConfig->SamplingTime);
80026d2: 687b ldr r3, [r7, #4]
80026d4: 6818 ldr r0, [r3, #0]
80026d6: 683b ldr r3, [r7, #0]
80026d8: 6819 ldr r1, [r3, #0]
80026da: 683b ldr r3, [r7, #0]
80026dc: 689b ldr r3, [r3, #8]
80026de: 001a movs r2, r3
80026e0: f7ff faf4 bl 8001ccc <LL_ADC_SetChannelSamplingTime>
/* internal measurement paths enable: If internal channel selected, */
/* enable dedicated internal buffers and path. */
/* Note: these internal measurement paths can be disabled using */
/* HAL_ADC_DeInit() or removing the channel from sequencer with */
/* channel configuration parameter "Rank". */
if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfig->Channel))
80026e4: 683b ldr r3, [r7, #0]
80026e6: 681b ldr r3, [r3, #0]
80026e8: 2b00 cmp r3, #0
80026ea: db00 blt.n 80026ee <HAL_ADC_ConfigChannel+0x21e>
80026ec: e0bc b.n 8002868 <HAL_ADC_ConfigChannel+0x398>
{
tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
80026ee: 4b50 ldr r3, [pc, #320] ; (8002830 <HAL_ADC_ConfigChannel+0x360>)
80026f0: 0018 movs r0, r3
80026f2: f7ff fa49 bl 8001b88 <LL_ADC_GetCommonPathInternalCh>
80026f6: 0003 movs r3, r0
80026f8: 613b str r3, [r7, #16]
/* If the requested internal measurement path has already been enabled, */
/* bypass the configuration processing. */
if ((pConfig->Channel == ADC_CHANNEL_TEMPSENSOR) &&
80026fa: 683b ldr r3, [r7, #0]
80026fc: 681b ldr r3, [r3, #0]
80026fe: 4a4d ldr r2, [pc, #308] ; (8002834 <HAL_ADC_ConfigChannel+0x364>)
8002700: 4293 cmp r3, r2
8002702: d122 bne.n 800274a <HAL_ADC_ConfigChannel+0x27a>
((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
8002704: 693a ldr r2, [r7, #16]
8002706: 2380 movs r3, #128 ; 0x80
8002708: 041b lsls r3, r3, #16
800270a: 4013 ands r3, r2
if ((pConfig->Channel == ADC_CHANNEL_TEMPSENSOR) &&
800270c: d11d bne.n 800274a <HAL_ADC_ConfigChannel+0x27a>
{
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
800270e: 693b ldr r3, [r7, #16]
8002710: 2280 movs r2, #128 ; 0x80
8002712: 0412 lsls r2, r2, #16
8002714: 4313 orrs r3, r2
8002716: 4a46 ldr r2, [pc, #280] ; (8002830 <HAL_ADC_ConfigChannel+0x360>)
8002718: 0019 movs r1, r3
800271a: 0010 movs r0, r2
800271c: f7ff fa20 bl 8001b60 <LL_ADC_SetCommonPathInternalCh>
/* Delay for temperature sensor stabilization time */
/* Wait loop initialization and execution */
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */
wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
8002720: 4b45 ldr r3, [pc, #276] ; (8002838 <HAL_ADC_ConfigChannel+0x368>)
8002722: 681b ldr r3, [r3, #0]
8002724: 4945 ldr r1, [pc, #276] ; (800283c <HAL_ADC_ConfigChannel+0x36c>)
8002726: 0018 movs r0, r3
8002728: f7fd fcec bl 8000104 <__udivsi3>
800272c: 0003 movs r3, r0
800272e: 1c5a adds r2, r3, #1
8002730: 0013 movs r3, r2
8002732: 005b lsls r3, r3, #1
8002734: 189b adds r3, r3, r2
8002736: 009b lsls r3, r3, #2
8002738: 60fb str r3, [r7, #12]
while (wait_loop_index != 0UL)
800273a: e002 b.n 8002742 <HAL_ADC_ConfigChannel+0x272>
{
wait_loop_index--;
800273c: 68fb ldr r3, [r7, #12]
800273e: 3b01 subs r3, #1
8002740: 60fb str r3, [r7, #12]
while (wait_loop_index != 0UL)
8002742: 68fb ldr r3, [r7, #12]
8002744: 2b00 cmp r3, #0
8002746: d1f9 bne.n 800273c <HAL_ADC_ConfigChannel+0x26c>
if ((pConfig->Channel == ADC_CHANNEL_TEMPSENSOR) &&
8002748: e08e b.n 8002868 <HAL_ADC_ConfigChannel+0x398>
}
}
else if ((pConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
800274a: 683b ldr r3, [r7, #0]
800274c: 681b ldr r3, [r3, #0]
800274e: 4a3c ldr r2, [pc, #240] ; (8002840 <HAL_ADC_ConfigChannel+0x370>)
8002750: 4293 cmp r3, r2
8002752: d10e bne.n 8002772 <HAL_ADC_ConfigChannel+0x2a2>
8002754: 693a ldr r2, [r7, #16]
8002756: 2380 movs r3, #128 ; 0x80
8002758: 045b lsls r3, r3, #17
800275a: 4013 ands r3, r2
800275c: d109 bne.n 8002772 <HAL_ADC_ConfigChannel+0x2a2>
{
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
800275e: 693b ldr r3, [r7, #16]
8002760: 2280 movs r2, #128 ; 0x80
8002762: 0452 lsls r2, r2, #17
8002764: 4313 orrs r3, r2
8002766: 4a32 ldr r2, [pc, #200] ; (8002830 <HAL_ADC_ConfigChannel+0x360>)
8002768: 0019 movs r1, r3
800276a: 0010 movs r0, r2
800276c: f7ff f9f8 bl 8001b60 <LL_ADC_SetCommonPathInternalCh>
8002770: e07a b.n 8002868 <HAL_ADC_ConfigChannel+0x398>
LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
}
else if ((pConfig->Channel == ADC_CHANNEL_VREFINT) &&
8002772: 683b ldr r3, [r7, #0]
8002774: 681b ldr r3, [r3, #0]
8002776: 4a33 ldr r2, [pc, #204] ; (8002844 <HAL_ADC_ConfigChannel+0x374>)
8002778: 4293 cmp r3, r2
800277a: d000 beq.n 800277e <HAL_ADC_ConfigChannel+0x2ae>
800277c: e074 b.n 8002868 <HAL_ADC_ConfigChannel+0x398>
((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
800277e: 693a ldr r2, [r7, #16]
8002780: 2380 movs r3, #128 ; 0x80
8002782: 03db lsls r3, r3, #15
8002784: 4013 ands r3, r2
else if ((pConfig->Channel == ADC_CHANNEL_VREFINT) &&
8002786: d000 beq.n 800278a <HAL_ADC_ConfigChannel+0x2ba>
8002788: e06e b.n 8002868 <HAL_ADC_ConfigChannel+0x398>
{
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
800278a: 693b ldr r3, [r7, #16]
800278c: 2280 movs r2, #128 ; 0x80
800278e: 03d2 lsls r2, r2, #15
8002790: 4313 orrs r3, r2
8002792: 4a27 ldr r2, [pc, #156] ; (8002830 <HAL_ADC_ConfigChannel+0x360>)
8002794: 0019 movs r1, r3
8002796: 0010 movs r0, r2
8002798: f7ff f9e2 bl 8001b60 <LL_ADC_SetCommonPathInternalCh>
800279c: e064 b.n 8002868 <HAL_ADC_ConfigChannel+0x398>
/* Regular sequencer configuration */
/* Note: Case of sequencer set to fully configurable: */
/* Sequencer rank cannot be disabled, only affected to */
/* another channel. */
/* To remove a rank, use parameter 'NbrOfConversion". */
if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) ||
800279e: 687b ldr r3, [r7, #4]
80027a0: 691a ldr r2, [r3, #16]
80027a2: 2380 movs r3, #128 ; 0x80
80027a4: 061b lsls r3, r3, #24
80027a6: 429a cmp r2, r3
80027a8: d004 beq.n 80027b4 <HAL_ADC_ConfigChannel+0x2e4>
(hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED_BACKWARD))
80027aa: 687b ldr r3, [r7, #4]
80027ac: 691b ldr r3, [r3, #16]
if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) ||
80027ae: 4a1f ldr r2, [pc, #124] ; (800282c <HAL_ADC_ConfigChannel+0x35c>)
80027b0: 4293 cmp r3, r2
80027b2: d107 bne.n 80027c4 <HAL_ADC_ConfigChannel+0x2f4>
{
/* Sequencer set to not fully configurable: */
/* Reset the channel by disabling the corresponding bitfield. */
LL_ADC_REG_SetSequencerChRem(hadc->Instance, pConfig->Channel);
80027b4: 687b ldr r3, [r7, #4]
80027b6: 681a ldr r2, [r3, #0]
80027b8: 683b ldr r3, [r7, #0]
80027ba: 681b ldr r3, [r3, #0]
80027bc: 0019 movs r1, r3
80027be: 0010 movs r0, r2
80027c0: f7ff fa65 bl 8001c8e <LL_ADC_REG_SetSequencerChRem>
}
/* Management of internal measurement channels: Vbat/VrefInt/TempSensor. */
/* If internal channel selected, enable dedicated internal buffers and */
/* paths. */
if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfig->Channel))
80027c4: 683b ldr r3, [r7, #0]
80027c6: 681b ldr r3, [r3, #0]
80027c8: 2b00 cmp r3, #0
80027ca: da4d bge.n 8002868 <HAL_ADC_ConfigChannel+0x398>
{
tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
80027cc: 4b18 ldr r3, [pc, #96] ; (8002830 <HAL_ADC_ConfigChannel+0x360>)
80027ce: 0018 movs r0, r3
80027d0: f7ff f9da bl 8001b88 <LL_ADC_GetCommonPathInternalCh>
80027d4: 0003 movs r3, r0
80027d6: 613b str r3, [r7, #16]
if (pConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
80027d8: 683b ldr r3, [r7, #0]
80027da: 681b ldr r3, [r3, #0]
80027dc: 4a15 ldr r2, [pc, #84] ; (8002834 <HAL_ADC_ConfigChannel+0x364>)
80027de: 4293 cmp r3, r2
80027e0: d108 bne.n 80027f4 <HAL_ADC_ConfigChannel+0x324>
{
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
80027e2: 693b ldr r3, [r7, #16]
80027e4: 4a18 ldr r2, [pc, #96] ; (8002848 <HAL_ADC_ConfigChannel+0x378>)
80027e6: 4013 ands r3, r2
80027e8: 4a11 ldr r2, [pc, #68] ; (8002830 <HAL_ADC_ConfigChannel+0x360>)
80027ea: 0019 movs r1, r3
80027ec: 0010 movs r0, r2
80027ee: f7ff f9b7 bl 8001b60 <LL_ADC_SetCommonPathInternalCh>
80027f2: e039 b.n 8002868 <HAL_ADC_ConfigChannel+0x398>
~LL_ADC_PATH_INTERNAL_TEMPSENSOR & tmp_config_internal_channel);
}
else if (pConfig->Channel == ADC_CHANNEL_VBAT)
80027f4: 683b ldr r3, [r7, #0]
80027f6: 681b ldr r3, [r3, #0]
80027f8: 4a11 ldr r2, [pc, #68] ; (8002840 <HAL_ADC_ConfigChannel+0x370>)
80027fa: 4293 cmp r3, r2
80027fc: d108 bne.n 8002810 <HAL_ADC_ConfigChannel+0x340>
{
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
80027fe: 693b ldr r3, [r7, #16]
8002800: 4a12 ldr r2, [pc, #72] ; (800284c <HAL_ADC_ConfigChannel+0x37c>)
8002802: 4013 ands r3, r2
8002804: 4a0a ldr r2, [pc, #40] ; (8002830 <HAL_ADC_ConfigChannel+0x360>)
8002806: 0019 movs r1, r3
8002808: 0010 movs r0, r2
800280a: f7ff f9a9 bl 8001b60 <LL_ADC_SetCommonPathInternalCh>
800280e: e02b b.n 8002868 <HAL_ADC_ConfigChannel+0x398>
~LL_ADC_PATH_INTERNAL_VBAT & tmp_config_internal_channel);
}
else if (pConfig->Channel == ADC_CHANNEL_VREFINT)
8002810: 683b ldr r3, [r7, #0]
8002812: 681b ldr r3, [r3, #0]
8002814: 4a0b ldr r2, [pc, #44] ; (8002844 <HAL_ADC_ConfigChannel+0x374>)
8002816: 4293 cmp r3, r2
8002818: d126 bne.n 8002868 <HAL_ADC_ConfigChannel+0x398>
{
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
800281a: 693b ldr r3, [r7, #16]
800281c: 4a0c ldr r2, [pc, #48] ; (8002850 <HAL_ADC_ConfigChannel+0x380>)
800281e: 4013 ands r3, r2
8002820: 4a03 ldr r2, [pc, #12] ; (8002830 <HAL_ADC_ConfigChannel+0x360>)
8002822: 0019 movs r1, r3
8002824: 0010 movs r0, r2
8002826: f7ff f99b bl 8001b60 <LL_ADC_SetCommonPathInternalCh>
800282a: e01d b.n 8002868 <HAL_ADC_ConfigChannel+0x398>
800282c: 80000004 .word 0x80000004
8002830: 40012708 .word 0x40012708
8002834: b0001000 .word 0xb0001000
8002838: 2000000c .word 0x2000000c
800283c: 00030d40 .word 0x00030d40
8002840: b8004000 .word 0xb8004000
8002844: b4002000 .word 0xb4002000
8002848: ff7fffff .word 0xff7fffff
800284c: feffffff .word 0xfeffffff
8002850: ffbfffff .word 0xffbfffff
/* channel could be done on neither of the channel configuration structure */
/* parameters. */
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
8002854: 687b ldr r3, [r7, #4]
8002856: 6d9b ldr r3, [r3, #88] ; 0x58
8002858: 2220 movs r2, #32
800285a: 431a orrs r2, r3
800285c: 687b ldr r3, [r7, #4]
800285e: 659a str r2, [r3, #88] ; 0x58
tmp_hal_status = HAL_ERROR;
8002860: 2317 movs r3, #23
8002862: 18fb adds r3, r7, r3
8002864: 2201 movs r2, #1
8002866: 701a strb r2, [r3, #0]
}
__HAL_UNLOCK(hadc);
8002868: 687b ldr r3, [r7, #4]
800286a: 2254 movs r2, #84 ; 0x54
800286c: 2100 movs r1, #0
800286e: 5499 strb r1, [r3, r2]
return tmp_hal_status;
8002870: 2317 movs r3, #23
8002872: 18fb adds r3, r7, r3
8002874: 781b ldrb r3, [r3, #0]
}
8002876: 0018 movs r0, r3
8002878: 46bd mov sp, r7
800287a: b006 add sp, #24
800287c: bd80 pop {r7, pc}
800287e: 46c0 nop ; (mov r8, r8)
08002880 <ADC_Enable>:
* and voltage regulator must be enabled (done into HAL_ADC_Init()).
* @param hadc ADC handle
* @retval HAL status.
*/
HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc)
{
8002880: b580 push {r7, lr}
8002882: b084 sub sp, #16
8002884: af00 add r7, sp, #0
8002886: 6078 str r0, [r7, #4]
uint32_t tickstart;
__IO uint32_t wait_loop_index = 0UL;
8002888: 2300 movs r3, #0
800288a: 60bb str r3, [r7, #8]
/* ADC enable and wait for ADC ready (in case of ADC is disabled or */
/* enabling phase not yet completed: flag ADC ready not yet set). */
/* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
/* causes: ADC clock not running, ...). */
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
800288c: 687b ldr r3, [r7, #4]
800288e: 681b ldr r3, [r3, #0]
8002890: 0018 movs r0, r3
8002892: f7ff fa83 bl 8001d9c <LL_ADC_IsEnabled>
8002896: 1e03 subs r3, r0, #0
8002898: d000 beq.n 800289c <ADC_Enable+0x1c>
800289a: e069 b.n 8002970 <ADC_Enable+0xf0>
{
/* Check if conditions to enable the ADC are fulfilled */
if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL)
800289c: 687b ldr r3, [r7, #4]
800289e: 681b ldr r3, [r3, #0]
80028a0: 689b ldr r3, [r3, #8]
80028a2: 4a36 ldr r2, [pc, #216] ; (800297c <ADC_Enable+0xfc>)
80028a4: 4013 ands r3, r2
80028a6: d00d beq.n 80028c4 <ADC_Enable+0x44>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
80028a8: 687b ldr r3, [r7, #4]
80028aa: 6d9b ldr r3, [r3, #88] ; 0x58
80028ac: 2210 movs r2, #16
80028ae: 431a orrs r2, r3
80028b0: 687b ldr r3, [r7, #4]
80028b2: 659a str r2, [r3, #88] ; 0x58
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
80028b4: 687b ldr r3, [r7, #4]
80028b6: 6ddb ldr r3, [r3, #92] ; 0x5c
80028b8: 2201 movs r2, #1
80028ba: 431a orrs r2, r3
80028bc: 687b ldr r3, [r7, #4]
80028be: 65da str r2, [r3, #92] ; 0x5c
return HAL_ERROR;
80028c0: 2301 movs r3, #1
80028c2: e056 b.n 8002972 <ADC_Enable+0xf2>
}
/* Enable the ADC peripheral */
LL_ADC_Enable(hadc->Instance);
80028c4: 687b ldr r3, [r7, #4]
80028c6: 681b ldr r3, [r3, #0]
80028c8: 0018 movs r0, r3
80028ca: f7ff fa43 bl 8001d54 <LL_ADC_Enable>
if ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_TEMPSENSOR) != 0UL)
80028ce: 4b2c ldr r3, [pc, #176] ; (8002980 <ADC_Enable+0x100>)
80028d0: 0018 movs r0, r3
80028d2: f7ff f959 bl 8001b88 <LL_ADC_GetCommonPathInternalCh>
80028d6: 0002 movs r2, r0
80028d8: 2380 movs r3, #128 ; 0x80
80028da: 041b lsls r3, r3, #16
80028dc: 4013 ands r3, r2
80028de: d00f beq.n 8002900 <ADC_Enable+0x80>
/* Delay for temperature sensor buffer stabilization time */
/* Wait loop initialization and execution */
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */
wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
80028e0: 4b28 ldr r3, [pc, #160] ; (8002984 <ADC_Enable+0x104>)
80028e2: 681b ldr r3, [r3, #0]
80028e4: 4928 ldr r1, [pc, #160] ; (8002988 <ADC_Enable+0x108>)
80028e6: 0018 movs r0, r3
80028e8: f7fd fc0c bl 8000104 <__udivsi3>
80028ec: 0003 movs r3, r0
80028ee: 3301 adds r3, #1
80028f0: 60bb str r3, [r7, #8]
while (wait_loop_index != 0UL)
80028f2: e002 b.n 80028fa <ADC_Enable+0x7a>
{
wait_loop_index--;
80028f4: 68bb ldr r3, [r7, #8]
80028f6: 3b01 subs r3, #1
80028f8: 60bb str r3, [r7, #8]
while (wait_loop_index != 0UL)
80028fa: 68bb ldr r3, [r7, #8]
80028fc: 2b00 cmp r3, #0
80028fe: d1f9 bne.n 80028f4 <ADC_Enable+0x74>
}
}
/* If low power mode AutoPowerOff is enabled, power-on/off phases are */
/* performed automatically by hardware and flag ADC ready is not set. */
if (hadc->Init.LowPowerAutoPowerOff != ENABLE)
8002900: 687b ldr r3, [r7, #4]
8002902: 7e5b ldrb r3, [r3, #25]
8002904: 2b01 cmp r3, #1
8002906: d033 beq.n 8002970 <ADC_Enable+0xf0>
{
/* Wait for ADC effectively enabled */
tickstart = HAL_GetTick();
8002908: f7ff f920 bl 8001b4c <HAL_GetTick>
800290c: 0003 movs r3, r0
800290e: 60fb str r3, [r7, #12]
while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
8002910: e027 b.n 8002962 <ADC_Enable+0xe2>
The workaround is to continue setting ADEN until ADRDY is becomes 1.
Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this
4 ADC clock cycle duration */
/* Note: Test of ADC enabled required due to hardware constraint to */
/* not enable ADC if already enabled. */
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
8002912: 687b ldr r3, [r7, #4]
8002914: 681b ldr r3, [r3, #0]
8002916: 0018 movs r0, r3
8002918: f7ff fa40 bl 8001d9c <LL_ADC_IsEnabled>
800291c: 1e03 subs r3, r0, #0
800291e: d104 bne.n 800292a <ADC_Enable+0xaa>
{
LL_ADC_Enable(hadc->Instance);
8002920: 687b ldr r3, [r7, #4]
8002922: 681b ldr r3, [r3, #0]
8002924: 0018 movs r0, r3
8002926: f7ff fa15 bl 8001d54 <LL_ADC_Enable>
}
if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
800292a: f7ff f90f bl 8001b4c <HAL_GetTick>
800292e: 0002 movs r2, r0
8002930: 68fb ldr r3, [r7, #12]
8002932: 1ad3 subs r3, r2, r3
8002934: 2b02 cmp r3, #2
8002936: d914 bls.n 8002962 <ADC_Enable+0xe2>
{
/* New check to avoid false timeout detection in case of preemption */
if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
8002938: 687b ldr r3, [r7, #4]
800293a: 681b ldr r3, [r3, #0]
800293c: 681b ldr r3, [r3, #0]
800293e: 2201 movs r2, #1
8002940: 4013 ands r3, r2
8002942: 2b01 cmp r3, #1
8002944: d00d beq.n 8002962 <ADC_Enable+0xe2>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
8002946: 687b ldr r3, [r7, #4]
8002948: 6d9b ldr r3, [r3, #88] ; 0x58
800294a: 2210 movs r2, #16
800294c: 431a orrs r2, r3
800294e: 687b ldr r3, [r7, #4]
8002950: 659a str r2, [r3, #88] ; 0x58
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8002952: 687b ldr r3, [r7, #4]
8002954: 6ddb ldr r3, [r3, #92] ; 0x5c
8002956: 2201 movs r2, #1
8002958: 431a orrs r2, r3
800295a: 687b ldr r3, [r7, #4]
800295c: 65da str r2, [r3, #92] ; 0x5c
return HAL_ERROR;
800295e: 2301 movs r3, #1
8002960: e007 b.n 8002972 <ADC_Enable+0xf2>
while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
8002962: 687b ldr r3, [r7, #4]
8002964: 681b ldr r3, [r3, #0]
8002966: 681b ldr r3, [r3, #0]
8002968: 2201 movs r2, #1
800296a: 4013 ands r3, r2
800296c: 2b01 cmp r3, #1
800296e: d1d0 bne.n 8002912 <ADC_Enable+0x92>
}
}
}
/* Return HAL status */
return HAL_OK;
8002970: 2300 movs r3, #0
}
8002972: 0018 movs r0, r3
8002974: 46bd mov sp, r7
8002976: b004 add sp, #16
8002978: bd80 pop {r7, pc}
800297a: 46c0 nop ; (mov r8, r8)
800297c: 80000017 .word 0x80000017
8002980: 40012708 .word 0x40012708
8002984: 2000000c .word 0x2000000c
8002988: 00030d40 .word 0x00030d40
0800298c <ADC_Disable>:
* stopped.
* @param hadc ADC handle
* @retval HAL status.
*/
HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc)
{
800298c: b580 push {r7, lr}
800298e: b084 sub sp, #16
8002990: af00 add r7, sp, #0
8002992: 6078 str r0, [r7, #4]
uint32_t tickstart;
const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(hadc->Instance);
8002994: 687b ldr r3, [r7, #4]
8002996: 681b ldr r3, [r3, #0]
8002998: 0018 movs r0, r3
800299a: f7ff fa10 bl 8001dbe <LL_ADC_IsDisableOngoing>
800299e: 0003 movs r3, r0
80029a0: 60fb str r3, [r7, #12]
/* Verification if ADC is not already disabled: */
/* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */
/* disabled. */
if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL)
80029a2: 687b ldr r3, [r7, #4]
80029a4: 681b ldr r3, [r3, #0]
80029a6: 0018 movs r0, r3
80029a8: f7ff f9f8 bl 8001d9c <LL_ADC_IsEnabled>
80029ac: 1e03 subs r3, r0, #0
80029ae: d046 beq.n 8002a3e <ADC_Disable+0xb2>
&& (tmp_adc_is_disable_on_going == 0UL)
80029b0: 68fb ldr r3, [r7, #12]
80029b2: 2b00 cmp r3, #0
80029b4: d143 bne.n 8002a3e <ADC_Disable+0xb2>
)
{
/* Check if conditions to disable the ADC are fulfilled */
if ((hadc->Instance->CR & (ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN)
80029b6: 687b ldr r3, [r7, #4]
80029b8: 681b ldr r3, [r3, #0]
80029ba: 689b ldr r3, [r3, #8]
80029bc: 2205 movs r2, #5
80029be: 4013 ands r3, r2
80029c0: 2b01 cmp r3, #1
80029c2: d10d bne.n 80029e0 <ADC_Disable+0x54>
{
/* Disable the ADC peripheral */
LL_ADC_Disable(hadc->Instance);
80029c4: 687b ldr r3, [r7, #4]
80029c6: 681b ldr r3, [r3, #0]
80029c8: 0018 movs r0, r3
80029ca: f7ff f9d5 bl 8001d78 <LL_ADC_Disable>
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY));
80029ce: 687b ldr r3, [r7, #4]
80029d0: 681b ldr r3, [r3, #0]
80029d2: 2203 movs r2, #3
80029d4: 601a str r2, [r3, #0]
return HAL_ERROR;
}
/* Wait for ADC effectively disabled */
/* Get tick count */
tickstart = HAL_GetTick();
80029d6: f7ff f8b9 bl 8001b4c <HAL_GetTick>
80029da: 0003 movs r3, r0
80029dc: 60bb str r3, [r7, #8]
while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
80029de: e028 b.n 8002a32 <ADC_Disable+0xa6>
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
80029e0: 687b ldr r3, [r7, #4]
80029e2: 6d9b ldr r3, [r3, #88] ; 0x58
80029e4: 2210 movs r2, #16
80029e6: 431a orrs r2, r3
80029e8: 687b ldr r3, [r7, #4]
80029ea: 659a str r2, [r3, #88] ; 0x58
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
80029ec: 687b ldr r3, [r7, #4]
80029ee: 6ddb ldr r3, [r3, #92] ; 0x5c
80029f0: 2201 movs r2, #1
80029f2: 431a orrs r2, r3
80029f4: 687b ldr r3, [r7, #4]
80029f6: 65da str r2, [r3, #92] ; 0x5c
return HAL_ERROR;
80029f8: 2301 movs r3, #1
80029fa: e021 b.n 8002a40 <ADC_Disable+0xb4>
{
if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
80029fc: f7ff f8a6 bl 8001b4c <HAL_GetTick>
8002a00: 0002 movs r2, r0
8002a02: 68bb ldr r3, [r7, #8]
8002a04: 1ad3 subs r3, r2, r3
8002a06: 2b02 cmp r3, #2
8002a08: d913 bls.n 8002a32 <ADC_Disable+0xa6>
{
/* New check to avoid false timeout detection in case of preemption */
if ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
8002a0a: 687b ldr r3, [r7, #4]
8002a0c: 681b ldr r3, [r3, #0]
8002a0e: 689b ldr r3, [r3, #8]
8002a10: 2201 movs r2, #1
8002a12: 4013 ands r3, r2
8002a14: d00d beq.n 8002a32 <ADC_Disable+0xa6>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
8002a16: 687b ldr r3, [r7, #4]
8002a18: 6d9b ldr r3, [r3, #88] ; 0x58
8002a1a: 2210 movs r2, #16
8002a1c: 431a orrs r2, r3
8002a1e: 687b ldr r3, [r7, #4]
8002a20: 659a str r2, [r3, #88] ; 0x58
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8002a22: 687b ldr r3, [r7, #4]
8002a24: 6ddb ldr r3, [r3, #92] ; 0x5c
8002a26: 2201 movs r2, #1
8002a28: 431a orrs r2, r3
8002a2a: 687b ldr r3, [r7, #4]
8002a2c: 65da str r2, [r3, #92] ; 0x5c
return HAL_ERROR;
8002a2e: 2301 movs r3, #1
8002a30: e006 b.n 8002a40 <ADC_Disable+0xb4>
while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
8002a32: 687b ldr r3, [r7, #4]
8002a34: 681b ldr r3, [r3, #0]
8002a36: 689b ldr r3, [r3, #8]
8002a38: 2201 movs r2, #1
8002a3a: 4013 ands r3, r2
8002a3c: d1de bne.n 80029fc <ADC_Disable+0x70>
}
}
}
/* Return HAL status */
return HAL_OK;
8002a3e: 2300 movs r3, #0
}
8002a40: 0018 movs r0, r3
8002a42: 46bd mov sp, r7
8002a44: b004 add sp, #16
8002a46: bd80 pop {r7, pc}
08002a48 <LL_ADC_SetCalibrationFactor>:
{
8002a48: b580 push {r7, lr}
8002a4a: b082 sub sp, #8
8002a4c: af00 add r7, sp, #0
8002a4e: 6078 str r0, [r7, #4]
8002a50: 6039 str r1, [r7, #0]
MODIFY_REG(ADCx->CALFACT,
8002a52: 687b ldr r3, [r7, #4]
8002a54: 22b4 movs r2, #180 ; 0xb4
8002a56: 589b ldr r3, [r3, r2]
8002a58: 227f movs r2, #127 ; 0x7f
8002a5a: 4393 bics r3, r2
8002a5c: 001a movs r2, r3
8002a5e: 683b ldr r3, [r7, #0]
8002a60: 431a orrs r2, r3
8002a62: 687b ldr r3, [r7, #4]
8002a64: 21b4 movs r1, #180 ; 0xb4
8002a66: 505a str r2, [r3, r1]
}
8002a68: 46c0 nop ; (mov r8, r8)
8002a6a: 46bd mov sp, r7
8002a6c: b002 add sp, #8
8002a6e: bd80 pop {r7, pc}
08002a70 <LL_ADC_GetCalibrationFactor>:
{
8002a70: b580 push {r7, lr}
8002a72: b082 sub sp, #8
8002a74: af00 add r7, sp, #0
8002a76: 6078 str r0, [r7, #4]
return (uint32_t)(READ_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT));
8002a78: 687b ldr r3, [r7, #4]
8002a7a: 22b4 movs r2, #180 ; 0xb4
8002a7c: 589b ldr r3, [r3, r2]
8002a7e: 227f movs r2, #127 ; 0x7f
8002a80: 4013 ands r3, r2
}
8002a82: 0018 movs r0, r3
8002a84: 46bd mov sp, r7
8002a86: b002 add sp, #8
8002a88: bd80 pop {r7, pc}
...
08002a8c <LL_ADC_Enable>:
{
8002a8c: b580 push {r7, lr}
8002a8e: b082 sub sp, #8
8002a90: af00 add r7, sp, #0
8002a92: 6078 str r0, [r7, #4]
MODIFY_REG(ADCx->CR,
8002a94: 687b ldr r3, [r7, #4]
8002a96: 689b ldr r3, [r3, #8]
8002a98: 4a04 ldr r2, [pc, #16] ; (8002aac <LL_ADC_Enable+0x20>)
8002a9a: 4013 ands r3, r2
8002a9c: 2201 movs r2, #1
8002a9e: 431a orrs r2, r3
8002aa0: 687b ldr r3, [r7, #4]
8002aa2: 609a str r2, [r3, #8]
}
8002aa4: 46c0 nop ; (mov r8, r8)
8002aa6: 46bd mov sp, r7
8002aa8: b002 add sp, #8
8002aaa: bd80 pop {r7, pc}
8002aac: 7fffffe8 .word 0x7fffffe8
08002ab0 <LL_ADC_Disable>:
{
8002ab0: b580 push {r7, lr}
8002ab2: b082 sub sp, #8
8002ab4: af00 add r7, sp, #0
8002ab6: 6078 str r0, [r7, #4]
MODIFY_REG(ADCx->CR,
8002ab8: 687b ldr r3, [r7, #4]
8002aba: 689b ldr r3, [r3, #8]
8002abc: 4a04 ldr r2, [pc, #16] ; (8002ad0 <LL_ADC_Disable+0x20>)
8002abe: 4013 ands r3, r2
8002ac0: 2202 movs r2, #2
8002ac2: 431a orrs r2, r3
8002ac4: 687b ldr r3, [r7, #4]
8002ac6: 609a str r2, [r3, #8]
}
8002ac8: 46c0 nop ; (mov r8, r8)
8002aca: 46bd mov sp, r7
8002acc: b002 add sp, #8
8002ace: bd80 pop {r7, pc}
8002ad0: 7fffffe8 .word 0x7fffffe8
08002ad4 <LL_ADC_IsEnabled>:
{
8002ad4: b580 push {r7, lr}
8002ad6: b082 sub sp, #8
8002ad8: af00 add r7, sp, #0
8002ada: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
8002adc: 687b ldr r3, [r7, #4]
8002ade: 689b ldr r3, [r3, #8]
8002ae0: 2201 movs r2, #1
8002ae2: 4013 ands r3, r2
8002ae4: 2b01 cmp r3, #1
8002ae6: d101 bne.n 8002aec <LL_ADC_IsEnabled+0x18>
8002ae8: 2301 movs r3, #1
8002aea: e000 b.n 8002aee <LL_ADC_IsEnabled+0x1a>
8002aec: 2300 movs r3, #0
}
8002aee: 0018 movs r0, r3
8002af0: 46bd mov sp, r7
8002af2: b002 add sp, #8
8002af4: bd80 pop {r7, pc}
...
08002af8 <LL_ADC_StartCalibration>:
{
8002af8: b580 push {r7, lr}
8002afa: b082 sub sp, #8
8002afc: af00 add r7, sp, #0
8002afe: 6078 str r0, [r7, #4]
MODIFY_REG(ADCx->CR,
8002b00: 687b ldr r3, [r7, #4]
8002b02: 689b ldr r3, [r3, #8]
8002b04: 4a05 ldr r2, [pc, #20] ; (8002b1c <LL_ADC_StartCalibration+0x24>)
8002b06: 4013 ands r3, r2
8002b08: 2280 movs r2, #128 ; 0x80
8002b0a: 0612 lsls r2, r2, #24
8002b0c: 431a orrs r2, r3
8002b0e: 687b ldr r3, [r7, #4]
8002b10: 609a str r2, [r3, #8]
}
8002b12: 46c0 nop ; (mov r8, r8)
8002b14: 46bd mov sp, r7
8002b16: b002 add sp, #8
8002b18: bd80 pop {r7, pc}
8002b1a: 46c0 nop ; (mov r8, r8)
8002b1c: 7fffffe8 .word 0x7fffffe8
08002b20 <LL_ADC_IsCalibrationOnGoing>:
{
8002b20: b580 push {r7, lr}
8002b22: b082 sub sp, #8
8002b24: af00 add r7, sp, #0
8002b26: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL);
8002b28: 687b ldr r3, [r7, #4]
8002b2a: 689b ldr r3, [r3, #8]
8002b2c: 0fdb lsrs r3, r3, #31
8002b2e: 07da lsls r2, r3, #31
8002b30: 2380 movs r3, #128 ; 0x80
8002b32: 061b lsls r3, r3, #24
8002b34: 429a cmp r2, r3
8002b36: d101 bne.n 8002b3c <LL_ADC_IsCalibrationOnGoing+0x1c>
8002b38: 2301 movs r3, #1
8002b3a: e000 b.n 8002b3e <LL_ADC_IsCalibrationOnGoing+0x1e>
8002b3c: 2300 movs r3, #0
}
8002b3e: 0018 movs r0, r3
8002b40: 46bd mov sp, r7
8002b42: b002 add sp, #8
8002b44: bd80 pop {r7, pc}
...
08002b48 <HAL_ADCEx_Calibration_Start>:
* HAL_ADC_GetValue() (value on 7 bits: from DR[6;0]).
* @param hadc ADC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc)
{
8002b48: b590 push {r4, r7, lr}
8002b4a: b089 sub sp, #36 ; 0x24
8002b4c: af00 add r7, sp, #0
8002b4e: 6078 str r0, [r7, #4]
HAL_StatusTypeDef tmp_hal_status;
__IO uint32_t wait_loop_index = 0UL;
8002b50: 2300 movs r3, #0
8002b52: 60bb str r3, [r7, #8]
uint32_t backup_setting_cfgr1;
uint32_t calibration_index;
uint32_t calibration_factor_accumulated = 0;
8002b54: 2300 movs r3, #0
8002b56: 61bb str r3, [r7, #24]
uint32_t tickstart;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
__HAL_LOCK(hadc);
8002b58: 687b ldr r3, [r7, #4]
8002b5a: 2254 movs r2, #84 ; 0x54
8002b5c: 5c9b ldrb r3, [r3, r2]
8002b5e: 2b01 cmp r3, #1
8002b60: d101 bne.n 8002b66 <HAL_ADCEx_Calibration_Start+0x1e>
8002b62: 2302 movs r3, #2
8002b64: e0ba b.n 8002cdc <HAL_ADCEx_Calibration_Start+0x194>
8002b66: 687b ldr r3, [r7, #4]
8002b68: 2254 movs r2, #84 ; 0x54
8002b6a: 2101 movs r1, #1
8002b6c: 5499 strb r1, [r3, r2]
/* Calibration prerequisite: ADC must be disabled. */
/* Disable the ADC (if not already disabled) */
tmp_hal_status = ADC_Disable(hadc);
8002b6e: 2317 movs r3, #23
8002b70: 18fc adds r4, r7, r3
8002b72: 687b ldr r3, [r7, #4]
8002b74: 0018 movs r0, r3
8002b76: f7ff ff09 bl 800298c <ADC_Disable>
8002b7a: 0003 movs r3, r0
8002b7c: 7023 strb r3, [r4, #0]
/* Check if ADC is effectively disabled */
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
8002b7e: 687b ldr r3, [r7, #4]
8002b80: 681b ldr r3, [r3, #0]
8002b82: 0018 movs r0, r3
8002b84: f7ff ffa6 bl 8002ad4 <LL_ADC_IsEnabled>
8002b88: 1e03 subs r3, r0, #0
8002b8a: d000 beq.n 8002b8e <HAL_ADCEx_Calibration_Start+0x46>
8002b8c: e099 b.n 8002cc2 <HAL_ADCEx_Calibration_Start+0x17a>
{
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
8002b8e: 687b ldr r3, [r7, #4]
8002b90: 6d9b ldr r3, [r3, #88] ; 0x58
8002b92: 4a54 ldr r2, [pc, #336] ; (8002ce4 <HAL_ADCEx_Calibration_Start+0x19c>)
8002b94: 4013 ands r3, r2
8002b96: 2202 movs r2, #2
8002b98: 431a orrs r2, r3
8002b9a: 687b ldr r3, [r7, #4]
8002b9c: 659a str r2, [r3, #88] ; 0x58
/* Note: Specificity of this STM32 series: Calibration factor is */
/* available in data register and also transferred by DMA. */
/* To not insert ADC calibration factor among ADC conversion data */
/* in array variable, DMA transfer must be disabled during */
/* calibration. */
backup_setting_cfgr1 = READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG | ADC_CFGR1_AUTOFF);
8002b9e: 687b ldr r3, [r7, #4]
8002ba0: 681b ldr r3, [r3, #0]
8002ba2: 68db ldr r3, [r3, #12]
8002ba4: 4a50 ldr r2, [pc, #320] ; (8002ce8 <HAL_ADCEx_Calibration_Start+0x1a0>)
8002ba6: 4013 ands r3, r2
8002ba8: 613b str r3, [r7, #16]
CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG | ADC_CFGR1_AUTOFF);
8002baa: 687b ldr r3, [r7, #4]
8002bac: 681b ldr r3, [r3, #0]
8002bae: 68da ldr r2, [r3, #12]
8002bb0: 687b ldr r3, [r7, #4]
8002bb2: 681b ldr r3, [r3, #0]
8002bb4: 494d ldr r1, [pc, #308] ; (8002cec <HAL_ADCEx_Calibration_Start+0x1a4>)
8002bb6: 400a ands r2, r1
8002bb8: 60da str r2, [r3, #12]
/* ADC calibration procedure */
/* Note: Perform an averaging of 8 calibrations for optimized accuracy */
for (calibration_index = 0UL; calibration_index < 8UL; calibration_index++)
8002bba: 2300 movs r3, #0
8002bbc: 61fb str r3, [r7, #28]
8002bbe: e02d b.n 8002c1c <HAL_ADCEx_Calibration_Start+0xd4>
{
/* Start ADC calibration */
LL_ADC_StartCalibration(hadc->Instance);
8002bc0: 687b ldr r3, [r7, #4]
8002bc2: 681b ldr r3, [r3, #0]
8002bc4: 0018 movs r0, r3
8002bc6: f7ff ff97 bl 8002af8 <LL_ADC_StartCalibration>
/* Wait for calibration completion */
while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL)
8002bca: e014 b.n 8002bf6 <HAL_ADCEx_Calibration_Start+0xae>
{
wait_loop_index++;
8002bcc: 68bb ldr r3, [r7, #8]
8002bce: 3301 adds r3, #1
8002bd0: 60bb str r3, [r7, #8]
if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT)
8002bd2: 68bb ldr r3, [r7, #8]
8002bd4: 4a46 ldr r2, [pc, #280] ; (8002cf0 <HAL_ADCEx_Calibration_Start+0x1a8>)
8002bd6: 4293 cmp r3, r2
8002bd8: d90d bls.n 8002bf6 <HAL_ADCEx_Calibration_Start+0xae>
{
/* Update ADC state machine to error */
ADC_STATE_CLR_SET(hadc->State,
8002bda: 687b ldr r3, [r7, #4]
8002bdc: 6d9b ldr r3, [r3, #88] ; 0x58
8002bde: 2212 movs r2, #18
8002be0: 4393 bics r3, r2
8002be2: 2210 movs r2, #16
8002be4: 431a orrs r2, r3
8002be6: 687b ldr r3, [r7, #4]
8002be8: 659a str r2, [r3, #88] ; 0x58
HAL_ADC_STATE_BUSY_INTERNAL,
HAL_ADC_STATE_ERROR_INTERNAL);
__HAL_UNLOCK(hadc);
8002bea: 687b ldr r3, [r7, #4]
8002bec: 2254 movs r2, #84 ; 0x54
8002bee: 2100 movs r1, #0
8002bf0: 5499 strb r1, [r3, r2]
return HAL_ERROR;
8002bf2: 2301 movs r3, #1
8002bf4: e072 b.n 8002cdc <HAL_ADCEx_Calibration_Start+0x194>
while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL)
8002bf6: 687b ldr r3, [r7, #4]
8002bf8: 681b ldr r3, [r3, #0]
8002bfa: 0018 movs r0, r3
8002bfc: f7ff ff90 bl 8002b20 <LL_ADC_IsCalibrationOnGoing>
8002c00: 1e03 subs r3, r0, #0
8002c02: d1e3 bne.n 8002bcc <HAL_ADCEx_Calibration_Start+0x84>
}
}
calibration_factor_accumulated += LL_ADC_GetCalibrationFactor(hadc->Instance);
8002c04: 687b ldr r3, [r7, #4]
8002c06: 681b ldr r3, [r3, #0]
8002c08: 0018 movs r0, r3
8002c0a: f7ff ff31 bl 8002a70 <LL_ADC_GetCalibrationFactor>
8002c0e: 0002 movs r2, r0
8002c10: 69bb ldr r3, [r7, #24]
8002c12: 189b adds r3, r3, r2
8002c14: 61bb str r3, [r7, #24]
for (calibration_index = 0UL; calibration_index < 8UL; calibration_index++)
8002c16: 69fb ldr r3, [r7, #28]
8002c18: 3301 adds r3, #1
8002c1a: 61fb str r3, [r7, #28]
8002c1c: 69fb ldr r3, [r7, #28]
8002c1e: 2b07 cmp r3, #7
8002c20: d9ce bls.n 8002bc0 <HAL_ADCEx_Calibration_Start+0x78>
}
/* Compute average */
calibration_factor_accumulated /= calibration_index;
8002c22: 69f9 ldr r1, [r7, #28]
8002c24: 69b8 ldr r0, [r7, #24]
8002c26: f7fd fa6d bl 8000104 <__udivsi3>
8002c2a: 0003 movs r3, r0
8002c2c: 61bb str r3, [r7, #24]
/* Apply calibration factor */
LL_ADC_Enable(hadc->Instance);
8002c2e: 687b ldr r3, [r7, #4]
8002c30: 681b ldr r3, [r3, #0]
8002c32: 0018 movs r0, r3
8002c34: f7ff ff2a bl 8002a8c <LL_ADC_Enable>
LL_ADC_SetCalibrationFactor(hadc->Instance, calibration_factor_accumulated);
8002c38: 687b ldr r3, [r7, #4]
8002c3a: 681b ldr r3, [r3, #0]
8002c3c: 69ba ldr r2, [r7, #24]
8002c3e: 0011 movs r1, r2
8002c40: 0018 movs r0, r3
8002c42: f7ff ff01 bl 8002a48 <LL_ADC_SetCalibrationFactor>
LL_ADC_Disable(hadc->Instance);
8002c46: 687b ldr r3, [r7, #4]
8002c48: 681b ldr r3, [r3, #0]
8002c4a: 0018 movs r0, r3
8002c4c: f7ff ff30 bl 8002ab0 <LL_ADC_Disable>
/* Wait for ADC effectively disabled before changing configuration */
/* Get tick count */
tickstart = HAL_GetTick();
8002c50: f7fe ff7c bl 8001b4c <HAL_GetTick>
8002c54: 0003 movs r3, r0
8002c56: 60fb str r3, [r7, #12]
while (LL_ADC_IsEnabled(hadc->Instance) != 0UL)
8002c58: e01b b.n 8002c92 <HAL_ADCEx_Calibration_Start+0x14a>
{
if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
8002c5a: f7fe ff77 bl 8001b4c <HAL_GetTick>
8002c5e: 0002 movs r2, r0
8002c60: 68fb ldr r3, [r7, #12]
8002c62: 1ad3 subs r3, r2, r3
8002c64: 2b02 cmp r3, #2
8002c66: d914 bls.n 8002c92 <HAL_ADCEx_Calibration_Start+0x14a>
{
/* New check to avoid false timeout detection in case of preemption */
if (LL_ADC_IsEnabled(hadc->Instance) != 0UL)
8002c68: 687b ldr r3, [r7, #4]
8002c6a: 681b ldr r3, [r3, #0]
8002c6c: 0018 movs r0, r3
8002c6e: f7ff ff31 bl 8002ad4 <LL_ADC_IsEnabled>
8002c72: 1e03 subs r3, r0, #0
8002c74: d00d beq.n 8002c92 <HAL_ADCEx_Calibration_Start+0x14a>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
8002c76: 687b ldr r3, [r7, #4]
8002c78: 6d9b ldr r3, [r3, #88] ; 0x58
8002c7a: 2210 movs r2, #16
8002c7c: 431a orrs r2, r3
8002c7e: 687b ldr r3, [r7, #4]
8002c80: 659a str r2, [r3, #88] ; 0x58
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8002c82: 687b ldr r3, [r7, #4]
8002c84: 6ddb ldr r3, [r3, #92] ; 0x5c
8002c86: 2201 movs r2, #1
8002c88: 431a orrs r2, r3
8002c8a: 687b ldr r3, [r7, #4]
8002c8c: 65da str r2, [r3, #92] ; 0x5c
return HAL_ERROR;
8002c8e: 2301 movs r3, #1
8002c90: e024 b.n 8002cdc <HAL_ADCEx_Calibration_Start+0x194>
while (LL_ADC_IsEnabled(hadc->Instance) != 0UL)
8002c92: 687b ldr r3, [r7, #4]
8002c94: 681b ldr r3, [r3, #0]
8002c96: 0018 movs r0, r3
8002c98: f7ff ff1c bl 8002ad4 <LL_ADC_IsEnabled>
8002c9c: 1e03 subs r3, r0, #0
8002c9e: d1dc bne.n 8002c5a <HAL_ADCEx_Calibration_Start+0x112>
}
}
}
/* Restore configuration after calibration */
SET_BIT(hadc->Instance->CFGR1, backup_setting_cfgr1);
8002ca0: 687b ldr r3, [r7, #4]
8002ca2: 681b ldr r3, [r3, #0]
8002ca4: 68d9 ldr r1, [r3, #12]
8002ca6: 687b ldr r3, [r7, #4]
8002ca8: 681b ldr r3, [r3, #0]
8002caa: 693a ldr r2, [r7, #16]
8002cac: 430a orrs r2, r1
8002cae: 60da str r2, [r3, #12]
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
8002cb0: 687b ldr r3, [r7, #4]
8002cb2: 6d9b ldr r3, [r3, #88] ; 0x58
8002cb4: 2203 movs r2, #3
8002cb6: 4393 bics r3, r2
8002cb8: 2201 movs r2, #1
8002cba: 431a orrs r2, r3
8002cbc: 687b ldr r3, [r7, #4]
8002cbe: 659a str r2, [r3, #88] ; 0x58
8002cc0: e005 b.n 8002cce <HAL_ADCEx_Calibration_Start+0x186>
HAL_ADC_STATE_BUSY_INTERNAL,
HAL_ADC_STATE_READY);
}
else
{
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
8002cc2: 687b ldr r3, [r7, #4]
8002cc4: 6d9b ldr r3, [r3, #88] ; 0x58
8002cc6: 2210 movs r2, #16
8002cc8: 431a orrs r2, r3
8002cca: 687b ldr r3, [r7, #4]
8002ccc: 659a str r2, [r3, #88] ; 0x58
/* Note: No need to update variable "tmp_hal_status" here: already set */
/* to state "HAL_ERROR" by function disabling the ADC. */
}
__HAL_UNLOCK(hadc);
8002cce: 687b ldr r3, [r7, #4]
8002cd0: 2254 movs r2, #84 ; 0x54
8002cd2: 2100 movs r1, #0
8002cd4: 5499 strb r1, [r3, r2]
return tmp_hal_status;
8002cd6: 2317 movs r3, #23
8002cd8: 18fb adds r3, r7, r3
8002cda: 781b ldrb r3, [r3, #0]
}
8002cdc: 0018 movs r0, r3
8002cde: 46bd mov sp, r7
8002ce0: b009 add sp, #36 ; 0x24
8002ce2: bd90 pop {r4, r7, pc}
8002ce4: fffffefd .word 0xfffffefd
8002ce8: 00008003 .word 0x00008003
8002cec: ffff7ffc .word 0xffff7ffc
8002cf0: 0002f1ff .word 0x0002f1ff
08002cf4 <HAL_ADCEx_LevelOutOfWindow2Callback>:
* @brief Analog watchdog 2 callback in non-blocking mode.
* @param hadc ADC handle
* @retval None
*/
__weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc)
{
8002cf4: b580 push {r7, lr}
8002cf6: b082 sub sp, #8
8002cf8: af00 add r7, sp, #0
8002cfa: 6078 str r0, [r7, #4]
UNUSED(hadc);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_ADCEx_LevelOutOfWindow2Callback must be implemented in the user file.
*/
}
8002cfc: 46c0 nop ; (mov r8, r8)
8002cfe: 46bd mov sp, r7
8002d00: b002 add sp, #8
8002d02: bd80 pop {r7, pc}
08002d04 <HAL_ADCEx_LevelOutOfWindow3Callback>:
* @brief Analog watchdog 3 callback in non-blocking mode.
* @param hadc ADC handle
* @retval None
*/
__weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc)
{
8002d04: b580 push {r7, lr}
8002d06: b082 sub sp, #8
8002d08: af00 add r7, sp, #0
8002d0a: 6078 str r0, [r7, #4]
UNUSED(hadc);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_ADCEx_LevelOutOfWindow3Callback must be implemented in the user file.
*/
}
8002d0c: 46c0 nop ; (mov r8, r8)
8002d0e: 46bd mov sp, r7
8002d10: b002 add sp, #8
8002d12: bd80 pop {r7, pc}
08002d14 <HAL_ADCEx_EndOfSamplingCallback>:
* @brief End Of Sampling callback in non-blocking mode.
* @param hadc ADC handle
* @retval None
*/
__weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc)
{
8002d14: b580 push {r7, lr}
8002d16: b082 sub sp, #8
8002d18: af00 add r7, sp, #0
8002d1a: 6078 str r0, [r7, #4]
UNUSED(hadc);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_ADCEx_EndOfSamplingCallback must be implemented in the user file.
*/
}
8002d1c: 46c0 nop ; (mov r8, r8)
8002d1e: 46bd mov sp, r7
8002d20: b002 add sp, #8
8002d22: bd80 pop {r7, pc}
08002d24 <HAL_ADCEx_ChannelConfigReadyCallback>:
* @brief ADC channel configuration ready callback in non-blocking mode.
* @param hadc ADC handle
* @retval None
*/
__weak void HAL_ADCEx_ChannelConfigReadyCallback(ADC_HandleTypeDef *hadc)
{
8002d24: b580 push {r7, lr}
8002d26: b082 sub sp, #8
8002d28: af00 add r7, sp, #0
8002d2a: 6078 str r0, [r7, #4]
UNUSED(hadc);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_ADCEx_ChannelConfigReadyCallback must be implemented in the user file.
*/
}
8002d2c: 46c0 nop ; (mov r8, r8)
8002d2e: 46bd mov sp, r7
8002d30: b002 add sp, #8
8002d32: bd80 pop {r7, pc}
08002d34 <__NVIC_EnableIRQ>:
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
8002d34: b580 push {r7, lr}
8002d36: b082 sub sp, #8
8002d38: af00 add r7, sp, #0
8002d3a: 0002 movs r2, r0
8002d3c: 1dfb adds r3, r7, #7
8002d3e: 701a strb r2, [r3, #0]
if ((int32_t)(IRQn) >= 0)
8002d40: 1dfb adds r3, r7, #7
8002d42: 781b ldrb r3, [r3, #0]
8002d44: 2b7f cmp r3, #127 ; 0x7f
8002d46: d809 bhi.n 8002d5c <__NVIC_EnableIRQ+0x28>
{
__COMPILER_BARRIER();
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
8002d48: 1dfb adds r3, r7, #7
8002d4a: 781b ldrb r3, [r3, #0]
8002d4c: 001a movs r2, r3
8002d4e: 231f movs r3, #31
8002d50: 401a ands r2, r3
8002d52: 4b04 ldr r3, [pc, #16] ; (8002d64 <__NVIC_EnableIRQ+0x30>)
8002d54: 2101 movs r1, #1
8002d56: 4091 lsls r1, r2
8002d58: 000a movs r2, r1
8002d5a: 601a str r2, [r3, #0]
__COMPILER_BARRIER();
}
}
8002d5c: 46c0 nop ; (mov r8, r8)
8002d5e: 46bd mov sp, r7
8002d60: b002 add sp, #8
8002d62: bd80 pop {r7, pc}
8002d64: e000e100 .word 0xe000e100
08002d68 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
8002d68: b590 push {r4, r7, lr}
8002d6a: b083 sub sp, #12
8002d6c: af00 add r7, sp, #0
8002d6e: 0002 movs r2, r0
8002d70: 6039 str r1, [r7, #0]
8002d72: 1dfb adds r3, r7, #7
8002d74: 701a strb r2, [r3, #0]
if ((int32_t)(IRQn) >= 0)
8002d76: 1dfb adds r3, r7, #7
8002d78: 781b ldrb r3, [r3, #0]
8002d7a: 2b7f cmp r3, #127 ; 0x7f
8002d7c: d828 bhi.n 8002dd0 <__NVIC_SetPriority+0x68>
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
8002d7e: 4a2f ldr r2, [pc, #188] ; (8002e3c <__NVIC_SetPriority+0xd4>)
8002d80: 1dfb adds r3, r7, #7
8002d82: 781b ldrb r3, [r3, #0]
8002d84: b25b sxtb r3, r3
8002d86: 089b lsrs r3, r3, #2
8002d88: 33c0 adds r3, #192 ; 0xc0
8002d8a: 009b lsls r3, r3, #2
8002d8c: 589b ldr r3, [r3, r2]
8002d8e: 1dfa adds r2, r7, #7
8002d90: 7812 ldrb r2, [r2, #0]
8002d92: 0011 movs r1, r2
8002d94: 2203 movs r2, #3
8002d96: 400a ands r2, r1
8002d98: 00d2 lsls r2, r2, #3
8002d9a: 21ff movs r1, #255 ; 0xff
8002d9c: 4091 lsls r1, r2
8002d9e: 000a movs r2, r1
8002da0: 43d2 mvns r2, r2
8002da2: 401a ands r2, r3
8002da4: 0011 movs r1, r2
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
8002da6: 683b ldr r3, [r7, #0]
8002da8: 019b lsls r3, r3, #6
8002daa: 22ff movs r2, #255 ; 0xff
8002dac: 401a ands r2, r3
8002dae: 1dfb adds r3, r7, #7
8002db0: 781b ldrb r3, [r3, #0]
8002db2: 0018 movs r0, r3
8002db4: 2303 movs r3, #3
8002db6: 4003 ands r3, r0
8002db8: 00db lsls r3, r3, #3
8002dba: 409a lsls r2, r3
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
8002dbc: 481f ldr r0, [pc, #124] ; (8002e3c <__NVIC_SetPriority+0xd4>)
8002dbe: 1dfb adds r3, r7, #7
8002dc0: 781b ldrb r3, [r3, #0]
8002dc2: b25b sxtb r3, r3
8002dc4: 089b lsrs r3, r3, #2
8002dc6: 430a orrs r2, r1
8002dc8: 33c0 adds r3, #192 ; 0xc0
8002dca: 009b lsls r3, r3, #2
8002dcc: 501a str r2, [r3, r0]
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
8002dce: e031 b.n 8002e34 <__NVIC_SetPriority+0xcc>
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
8002dd0: 4a1b ldr r2, [pc, #108] ; (8002e40 <__NVIC_SetPriority+0xd8>)
8002dd2: 1dfb adds r3, r7, #7
8002dd4: 781b ldrb r3, [r3, #0]
8002dd6: 0019 movs r1, r3
8002dd8: 230f movs r3, #15
8002dda: 400b ands r3, r1
8002ddc: 3b08 subs r3, #8
8002dde: 089b lsrs r3, r3, #2
8002de0: 3306 adds r3, #6
8002de2: 009b lsls r3, r3, #2
8002de4: 18d3 adds r3, r2, r3
8002de6: 3304 adds r3, #4
8002de8: 681b ldr r3, [r3, #0]
8002dea: 1dfa adds r2, r7, #7
8002dec: 7812 ldrb r2, [r2, #0]
8002dee: 0011 movs r1, r2
8002df0: 2203 movs r2, #3
8002df2: 400a ands r2, r1
8002df4: 00d2 lsls r2, r2, #3
8002df6: 21ff movs r1, #255 ; 0xff
8002df8: 4091 lsls r1, r2
8002dfa: 000a movs r2, r1
8002dfc: 43d2 mvns r2, r2
8002dfe: 401a ands r2, r3
8002e00: 0011 movs r1, r2
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
8002e02: 683b ldr r3, [r7, #0]
8002e04: 019b lsls r3, r3, #6
8002e06: 22ff movs r2, #255 ; 0xff
8002e08: 401a ands r2, r3
8002e0a: 1dfb adds r3, r7, #7
8002e0c: 781b ldrb r3, [r3, #0]
8002e0e: 0018 movs r0, r3
8002e10: 2303 movs r3, #3
8002e12: 4003 ands r3, r0
8002e14: 00db lsls r3, r3, #3
8002e16: 409a lsls r2, r3
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
8002e18: 4809 ldr r0, [pc, #36] ; (8002e40 <__NVIC_SetPriority+0xd8>)
8002e1a: 1dfb adds r3, r7, #7
8002e1c: 781b ldrb r3, [r3, #0]
8002e1e: 001c movs r4, r3
8002e20: 230f movs r3, #15
8002e22: 4023 ands r3, r4
8002e24: 3b08 subs r3, #8
8002e26: 089b lsrs r3, r3, #2
8002e28: 430a orrs r2, r1
8002e2a: 3306 adds r3, #6
8002e2c: 009b lsls r3, r3, #2
8002e2e: 18c3 adds r3, r0, r3
8002e30: 3304 adds r3, #4
8002e32: 601a str r2, [r3, #0]
}
8002e34: 46c0 nop ; (mov r8, r8)
8002e36: 46bd mov sp, r7
8002e38: b003 add sp, #12
8002e3a: bd90 pop {r4, r7, pc}
8002e3c: e000e100 .word 0xe000e100
8002e40: e000ed00 .word 0xe000ed00
08002e44 <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
8002e44: b580 push {r7, lr}
8002e46: b082 sub sp, #8
8002e48: af00 add r7, sp, #0
8002e4a: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
8002e4c: 687b ldr r3, [r7, #4]
8002e4e: 1e5a subs r2, r3, #1
8002e50: 2380 movs r3, #128 ; 0x80
8002e52: 045b lsls r3, r3, #17
8002e54: 429a cmp r2, r3
8002e56: d301 bcc.n 8002e5c <SysTick_Config+0x18>
{
return (1UL); /* Reload value impossible */
8002e58: 2301 movs r3, #1
8002e5a: e010 b.n 8002e7e <SysTick_Config+0x3a>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
8002e5c: 4b0a ldr r3, [pc, #40] ; (8002e88 <SysTick_Config+0x44>)
8002e5e: 687a ldr r2, [r7, #4]
8002e60: 3a01 subs r2, #1
8002e62: 605a str r2, [r3, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
8002e64: 2301 movs r3, #1
8002e66: 425b negs r3, r3
8002e68: 2103 movs r1, #3
8002e6a: 0018 movs r0, r3
8002e6c: f7ff ff7c bl 8002d68 <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
8002e70: 4b05 ldr r3, [pc, #20] ; (8002e88 <SysTick_Config+0x44>)
8002e72: 2200 movs r2, #0
8002e74: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
8002e76: 4b04 ldr r3, [pc, #16] ; (8002e88 <SysTick_Config+0x44>)
8002e78: 2207 movs r2, #7
8002e7a: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
8002e7c: 2300 movs r3, #0
}
8002e7e: 0018 movs r0, r3
8002e80: 46bd mov sp, r7
8002e82: b002 add sp, #8
8002e84: bd80 pop {r7, pc}
8002e86: 46c0 nop ; (mov r8, r8)
8002e88: e000e010 .word 0xe000e010
08002e8c <HAL_NVIC_SetPriority>:
* with stm32g0xx devices, this parameter is a dummy value and it is ignored, because
* no subpriority supported in Cortex M0+ based products.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
8002e8c: b580 push {r7, lr}
8002e8e: b084 sub sp, #16
8002e90: af00 add r7, sp, #0
8002e92: 60b9 str r1, [r7, #8]
8002e94: 607a str r2, [r7, #4]
8002e96: 210f movs r1, #15
8002e98: 187b adds r3, r7, r1
8002e9a: 1c02 adds r2, r0, #0
8002e9c: 701a strb r2, [r3, #0]
/* Prevent unused argument(s) compilation warning */
UNUSED(SubPriority);
/* Check the parameters */
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
NVIC_SetPriority(IRQn, PreemptPriority);
8002e9e: 68ba ldr r2, [r7, #8]
8002ea0: 187b adds r3, r7, r1
8002ea2: 781b ldrb r3, [r3, #0]
8002ea4: b25b sxtb r3, r3
8002ea6: 0011 movs r1, r2
8002ea8: 0018 movs r0, r3
8002eaa: f7ff ff5d bl 8002d68 <__NVIC_SetPriority>
}
8002eae: 46c0 nop ; (mov r8, r8)
8002eb0: 46bd mov sp, r7
8002eb2: b004 add sp, #16
8002eb4: bd80 pop {r7, pc}
08002eb6 <HAL_NVIC_EnableIRQ>:
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g0xxxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
8002eb6: b580 push {r7, lr}
8002eb8: b082 sub sp, #8
8002eba: af00 add r7, sp, #0
8002ebc: 0002 movs r2, r0
8002ebe: 1dfb adds r3, r7, #7
8002ec0: 701a strb r2, [r3, #0]
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
8002ec2: 1dfb adds r3, r7, #7
8002ec4: 781b ldrb r3, [r3, #0]
8002ec6: b25b sxtb r3, r3
8002ec8: 0018 movs r0, r3
8002eca: f7ff ff33 bl 8002d34 <__NVIC_EnableIRQ>
}
8002ece: 46c0 nop ; (mov r8, r8)
8002ed0: 46bd mov sp, r7
8002ed2: b002 add sp, #8
8002ed4: bd80 pop {r7, pc}
08002ed6 <HAL_SYSTICK_Config>:
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
8002ed6: b580 push {r7, lr}
8002ed8: b082 sub sp, #8
8002eda: af00 add r7, sp, #0
8002edc: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
8002ede: 687b ldr r3, [r7, #4]
8002ee0: 0018 movs r0, r3
8002ee2: f7ff ffaf bl 8002e44 <SysTick_Config>
8002ee6: 0003 movs r3, r0
}
8002ee8: 0018 movs r0, r3
8002eea: 46bd mov sp, r7
8002eec: b002 add sp, #8
8002eee: bd80 pop {r7, pc}
08002ef0 <HAL_DMA_Init>:
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
{
8002ef0: b580 push {r7, lr}
8002ef2: b082 sub sp, #8
8002ef4: af00 add r7, sp, #0
8002ef6: 6078 str r0, [r7, #4]
/* Check the DMA handle allocation */
if (hdma == NULL)
8002ef8: 687b ldr r3, [r7, #4]
8002efa: 2b00 cmp r3, #0
8002efc: d101 bne.n 8002f02 <HAL_DMA_Init+0x12>
{
return HAL_ERROR;
8002efe: 2301 movs r3, #1
8002f00: e077 b.n 8002ff2 <HAL_DMA_Init+0x102>
/* DMA2 */
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U;
hdma->DmaBaseAddress = DMA2;
}
#else
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
8002f02: 687b ldr r3, [r7, #4]
8002f04: 681b ldr r3, [r3, #0]
8002f06: 4a3d ldr r2, [pc, #244] ; (8002ffc <HAL_DMA_Init+0x10c>)
8002f08: 4694 mov ip, r2
8002f0a: 4463 add r3, ip
8002f0c: 2114 movs r1, #20
8002f0e: 0018 movs r0, r3
8002f10: f7fd f8f8 bl 8000104 <__udivsi3>
8002f14: 0003 movs r3, r0
8002f16: 009a lsls r2, r3, #2
8002f18: 687b ldr r3, [r7, #4]
8002f1a: 641a str r2, [r3, #64] ; 0x40
#endif /* DMA2 */
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
8002f1c: 687b ldr r3, [r7, #4]
8002f1e: 2225 movs r2, #37 ; 0x25
8002f20: 2102 movs r1, #2
8002f22: 5499 strb r1, [r3, r2]
/* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */
CLEAR_BIT(hdma->Instance->CCR, (DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \
8002f24: 687b ldr r3, [r7, #4]
8002f26: 681b ldr r3, [r3, #0]
8002f28: 681a ldr r2, [r3, #0]
8002f2a: 687b ldr r3, [r7, #4]
8002f2c: 681b ldr r3, [r3, #0]
8002f2e: 4934 ldr r1, [pc, #208] ; (8003000 <HAL_DMA_Init+0x110>)
8002f30: 400a ands r2, r1
8002f32: 601a str r2, [r3, #0]
DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \
DMA_CCR_DIR | DMA_CCR_MEM2MEM));
/* Set the DMA Channel configuration */
SET_BIT(hdma->Instance->CCR, (hdma->Init.Direction | \
8002f34: 687b ldr r3, [r7, #4]
8002f36: 681b ldr r3, [r3, #0]
8002f38: 6819 ldr r1, [r3, #0]
8002f3a: 687b ldr r3, [r7, #4]
8002f3c: 689a ldr r2, [r3, #8]
8002f3e: 687b ldr r3, [r7, #4]
8002f40: 68db ldr r3, [r3, #12]
8002f42: 431a orrs r2, r3
8002f44: 687b ldr r3, [r7, #4]
8002f46: 691b ldr r3, [r3, #16]
8002f48: 431a orrs r2, r3
8002f4a: 687b ldr r3, [r7, #4]
8002f4c: 695b ldr r3, [r3, #20]
8002f4e: 431a orrs r2, r3
8002f50: 687b ldr r3, [r7, #4]
8002f52: 699b ldr r3, [r3, #24]
8002f54: 431a orrs r2, r3
8002f56: 687b ldr r3, [r7, #4]
8002f58: 69db ldr r3, [r3, #28]
8002f5a: 431a orrs r2, r3
8002f5c: 687b ldr r3, [r7, #4]
8002f5e: 6a1b ldr r3, [r3, #32]
8002f60: 431a orrs r2, r3
8002f62: 687b ldr r3, [r7, #4]
8002f64: 681b ldr r3, [r3, #0]
8002f66: 430a orrs r2, r1
8002f68: 601a str r2, [r3, #0]
hdma->Init.Mode | hdma->Init.Priority));
/* Initialize parameters for DMAMUX channel :
DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask
*/
DMA_CalcDMAMUXChannelBaseAndMask(hdma);
8002f6a: 687b ldr r3, [r7, #4]
8002f6c: 0018 movs r0, r3
8002f6e: f000 fa8d bl 800348c <DMA_CalcDMAMUXChannelBaseAndMask>
if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
8002f72: 687b ldr r3, [r7, #4]
8002f74: 689a ldr r2, [r3, #8]
8002f76: 2380 movs r3, #128 ; 0x80
8002f78: 01db lsls r3, r3, #7
8002f7a: 429a cmp r2, r3
8002f7c: d102 bne.n 8002f84 <HAL_DMA_Init+0x94>
{
/* if memory to memory force the request to 0*/
hdma->Init.Request = DMA_REQUEST_MEM2MEM;
8002f7e: 687b ldr r3, [r7, #4]
8002f80: 2200 movs r2, #0
8002f82: 605a str r2, [r3, #4]
}
/* Set peripheral request to DMAMUX channel */
hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID);
8002f84: 687b ldr r3, [r7, #4]
8002f86: 685a ldr r2, [r3, #4]
8002f88: 687b ldr r3, [r7, #4]
8002f8a: 6c5b ldr r3, [r3, #68] ; 0x44
8002f8c: 213f movs r1, #63 ; 0x3f
8002f8e: 400a ands r2, r1
8002f90: 601a str r2, [r3, #0]
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
8002f92: 687b ldr r3, [r7, #4]
8002f94: 6c9b ldr r3, [r3, #72] ; 0x48
8002f96: 687a ldr r2, [r7, #4]
8002f98: 6cd2 ldr r2, [r2, #76] ; 0x4c
8002f9a: 605a str r2, [r3, #4]
if (((hdma->Init.Request > 0UL) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3)))
8002f9c: 687b ldr r3, [r7, #4]
8002f9e: 685b ldr r3, [r3, #4]
8002fa0: 2b00 cmp r3, #0
8002fa2: d011 beq.n 8002fc8 <HAL_DMA_Init+0xd8>
8002fa4: 687b ldr r3, [r7, #4]
8002fa6: 685b ldr r3, [r3, #4]
8002fa8: 2b04 cmp r3, #4
8002faa: d80d bhi.n 8002fc8 <HAL_DMA_Init+0xd8>
{
/* Initialize parameters for DMAMUX request generator :
DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask
*/
DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
8002fac: 687b ldr r3, [r7, #4]
8002fae: 0018 movs r0, r3
8002fb0: f000 fa98 bl 80034e4 <DMA_CalcDMAMUXRequestGenBaseAndMask>
/* Reset the DMAMUX request generator register*/
hdma->DMAmuxRequestGen->RGCR = 0U;
8002fb4: 687b ldr r3, [r7, #4]
8002fb6: 6d1b ldr r3, [r3, #80] ; 0x50
8002fb8: 2200 movs r2, #0
8002fba: 601a str r2, [r3, #0]
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
8002fbc: 687b ldr r3, [r7, #4]
8002fbe: 6d5b ldr r3, [r3, #84] ; 0x54
8002fc0: 687a ldr r2, [r7, #4]
8002fc2: 6d92 ldr r2, [r2, #88] ; 0x58
8002fc4: 605a str r2, [r3, #4]
8002fc6: e008 b.n 8002fda <HAL_DMA_Init+0xea>
}
else
{
hdma->DMAmuxRequestGen = 0U;
8002fc8: 687b ldr r3, [r7, #4]
8002fca: 2200 movs r2, #0
8002fcc: 651a str r2, [r3, #80] ; 0x50
hdma->DMAmuxRequestGenStatus = 0U;
8002fce: 687b ldr r3, [r7, #4]
8002fd0: 2200 movs r2, #0
8002fd2: 655a str r2, [r3, #84] ; 0x54
hdma->DMAmuxRequestGenStatusMask = 0U;
8002fd4: 687b ldr r3, [r7, #4]
8002fd6: 2200 movs r2, #0
8002fd8: 659a str r2, [r3, #88] ; 0x58
}
/* Initialize the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
8002fda: 687b ldr r3, [r7, #4]
8002fdc: 2200 movs r2, #0
8002fde: 63da str r2, [r3, #60] ; 0x3c
/* Initialize the DMA state*/
hdma->State = HAL_DMA_STATE_READY;
8002fe0: 687b ldr r3, [r7, #4]
8002fe2: 2225 movs r2, #37 ; 0x25
8002fe4: 2101 movs r1, #1
8002fe6: 5499 strb r1, [r3, r2]
/* Release Lock */
__HAL_UNLOCK(hdma);
8002fe8: 687b ldr r3, [r7, #4]
8002fea: 2224 movs r2, #36 ; 0x24
8002fec: 2100 movs r1, #0
8002fee: 5499 strb r1, [r3, r2]
return HAL_OK;
8002ff0: 2300 movs r3, #0
}
8002ff2: 0018 movs r0, r3
8002ff4: 46bd mov sp, r7
8002ff6: b002 add sp, #8
8002ff8: bd80 pop {r7, pc}
8002ffa: 46c0 nop ; (mov r8, r8)
8002ffc: bffdfff8 .word 0xbffdfff8
8003000: ffff800f .word 0xffff800f
08003004 <HAL_DMA_Start_IT>:
* @param DataLength The length of data to be transferred from source to destination
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress,
uint32_t DataLength)
{
8003004: b580 push {r7, lr}
8003006: b086 sub sp, #24
8003008: af00 add r7, sp, #0
800300a: 60f8 str r0, [r7, #12]
800300c: 60b9 str r1, [r7, #8]
800300e: 607a str r2, [r7, #4]
8003010: 603b str r3, [r7, #0]
HAL_StatusTypeDef status = HAL_OK;
8003012: 2317 movs r3, #23
8003014: 18fb adds r3, r7, r3
8003016: 2200 movs r2, #0
8003018: 701a strb r2, [r3, #0]
/* Check the parameters */
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
/* Process locked */
__HAL_LOCK(hdma);
800301a: 68fb ldr r3, [r7, #12]
800301c: 2224 movs r2, #36 ; 0x24
800301e: 5c9b ldrb r3, [r3, r2]
8003020: 2b01 cmp r3, #1
8003022: d101 bne.n 8003028 <HAL_DMA_Start_IT+0x24>
8003024: 2302 movs r3, #2
8003026: e06f b.n 8003108 <HAL_DMA_Start_IT+0x104>
8003028: 68fb ldr r3, [r7, #12]
800302a: 2224 movs r2, #36 ; 0x24
800302c: 2101 movs r1, #1
800302e: 5499 strb r1, [r3, r2]
if (hdma->State == HAL_DMA_STATE_READY)
8003030: 68fb ldr r3, [r7, #12]
8003032: 2225 movs r2, #37 ; 0x25
8003034: 5c9b ldrb r3, [r3, r2]
8003036: b2db uxtb r3, r3
8003038: 2b01 cmp r3, #1
800303a: d157 bne.n 80030ec <HAL_DMA_Start_IT+0xe8>
{
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
800303c: 68fb ldr r3, [r7, #12]
800303e: 2225 movs r2, #37 ; 0x25
8003040: 2102 movs r1, #2
8003042: 5499 strb r1, [r3, r2]
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
8003044: 68fb ldr r3, [r7, #12]
8003046: 2200 movs r2, #0
8003048: 63da str r2, [r3, #60] ; 0x3c
/* Disable the peripheral */
__HAL_DMA_DISABLE(hdma);
800304a: 68fb ldr r3, [r7, #12]
800304c: 681b ldr r3, [r3, #0]
800304e: 681a ldr r2, [r3, #0]
8003050: 68fb ldr r3, [r7, #12]
8003052: 681b ldr r3, [r3, #0]
8003054: 2101 movs r1, #1
8003056: 438a bics r2, r1
8003058: 601a str r2, [r3, #0]
/* Configure the source, destination address and the data length & clear flags*/
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
800305a: 683b ldr r3, [r7, #0]
800305c: 687a ldr r2, [r7, #4]
800305e: 68b9 ldr r1, [r7, #8]
8003060: 68f8 ldr r0, [r7, #12]
8003062: f000 f9d3 bl 800340c <DMA_SetConfig>
/* Enable the transfer complete interrupt */
/* Enable the transfer Error interrupt */
if (NULL != hdma->XferHalfCpltCallback)
8003066: 68fb ldr r3, [r7, #12]
8003068: 6b1b ldr r3, [r3, #48] ; 0x30
800306a: 2b00 cmp r3, #0
800306c: d008 beq.n 8003080 <HAL_DMA_Start_IT+0x7c>
{
/* Enable the Half transfer complete interrupt as well */
__HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
800306e: 68fb ldr r3, [r7, #12]
8003070: 681b ldr r3, [r3, #0]
8003072: 681a ldr r2, [r3, #0]
8003074: 68fb ldr r3, [r7, #12]
8003076: 681b ldr r3, [r3, #0]
8003078: 210e movs r1, #14
800307a: 430a orrs r2, r1
800307c: 601a str r2, [r3, #0]
800307e: e00f b.n 80030a0 <HAL_DMA_Start_IT+0x9c>
}
else
{
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
8003080: 68fb ldr r3, [r7, #12]
8003082: 681b ldr r3, [r3, #0]
8003084: 681a ldr r2, [r3, #0]
8003086: 68fb ldr r3, [r7, #12]
8003088: 681b ldr r3, [r3, #0]
800308a: 2104 movs r1, #4
800308c: 438a bics r2, r1
800308e: 601a str r2, [r3, #0]
__HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
8003090: 68fb ldr r3, [r7, #12]
8003092: 681b ldr r3, [r3, #0]
8003094: 681a ldr r2, [r3, #0]
8003096: 68fb ldr r3, [r7, #12]
8003098: 681b ldr r3, [r3, #0]
800309a: 210a movs r1, #10
800309c: 430a orrs r2, r1
800309e: 601a str r2, [r3, #0]
}
/* Check if DMAMUX Synchronization is enabled*/
if ((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
80030a0: 68fb ldr r3, [r7, #12]
80030a2: 6c5b ldr r3, [r3, #68] ; 0x44
80030a4: 681a ldr r2, [r3, #0]
80030a6: 2380 movs r3, #128 ; 0x80
80030a8: 025b lsls r3, r3, #9
80030aa: 4013 ands r3, r2
80030ac: d008 beq.n 80030c0 <HAL_DMA_Start_IT+0xbc>
{
/* Enable DMAMUX sync overrun IT*/
hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
80030ae: 68fb ldr r3, [r7, #12]
80030b0: 6c5b ldr r3, [r3, #68] ; 0x44
80030b2: 681a ldr r2, [r3, #0]
80030b4: 68fb ldr r3, [r7, #12]
80030b6: 6c5b ldr r3, [r3, #68] ; 0x44
80030b8: 2180 movs r1, #128 ; 0x80
80030ba: 0049 lsls r1, r1, #1
80030bc: 430a orrs r2, r1
80030be: 601a str r2, [r3, #0]
}
if (hdma->DMAmuxRequestGen != 0U)
80030c0: 68fb ldr r3, [r7, #12]
80030c2: 6d1b ldr r3, [r3, #80] ; 0x50
80030c4: 2b00 cmp r3, #0
80030c6: d008 beq.n 80030da <HAL_DMA_Start_IT+0xd6>
{
/* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/
/* enable the request gen overrun IT*/
hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
80030c8: 68fb ldr r3, [r7, #12]
80030ca: 6d1b ldr r3, [r3, #80] ; 0x50
80030cc: 681a ldr r2, [r3, #0]
80030ce: 68fb ldr r3, [r7, #12]
80030d0: 6d1b ldr r3, [r3, #80] ; 0x50
80030d2: 2180 movs r1, #128 ; 0x80
80030d4: 0049 lsls r1, r1, #1
80030d6: 430a orrs r2, r1
80030d8: 601a str r2, [r3, #0]
}
/* Enable the Peripheral */
__HAL_DMA_ENABLE(hdma);
80030da: 68fb ldr r3, [r7, #12]
80030dc: 681b ldr r3, [r3, #0]
80030de: 681a ldr r2, [r3, #0]
80030e0: 68fb ldr r3, [r7, #12]
80030e2: 681b ldr r3, [r3, #0]
80030e4: 2101 movs r1, #1
80030e6: 430a orrs r2, r1
80030e8: 601a str r2, [r3, #0]
80030ea: e00a b.n 8003102 <HAL_DMA_Start_IT+0xfe>
}
else
{
/* Change the error code */
hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
80030ec: 68fb ldr r3, [r7, #12]
80030ee: 2280 movs r2, #128 ; 0x80
80030f0: 63da str r2, [r3, #60] ; 0x3c
/* Process Unlocked */
__HAL_UNLOCK(hdma);
80030f2: 68fb ldr r3, [r7, #12]
80030f4: 2224 movs r2, #36 ; 0x24
80030f6: 2100 movs r1, #0
80030f8: 5499 strb r1, [r3, r2]
/* Return error status */
status = HAL_ERROR;
80030fa: 2317 movs r3, #23
80030fc: 18fb adds r3, r7, r3
80030fe: 2201 movs r2, #1
8003100: 701a strb r2, [r3, #0]
}
return status;
8003102: 2317 movs r3, #23
8003104: 18fb adds r3, r7, r3
8003106: 781b ldrb r3, [r3, #0]
}
8003108: 0018 movs r0, r3
800310a: 46bd mov sp, r7
800310c: b006 add sp, #24
800310e: bd80 pop {r7, pc}
08003110 <HAL_DMA_Abort>:
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
{
8003110: b580 push {r7, lr}
8003112: b082 sub sp, #8
8003114: af00 add r7, sp, #0
8003116: 6078 str r0, [r7, #4]
/* Check the DMA peripheral handle */
if (NULL == hdma)
8003118: 687b ldr r3, [r7, #4]
800311a: 2b00 cmp r3, #0
800311c: d101 bne.n 8003122 <HAL_DMA_Abort+0x12>
{
return HAL_ERROR;
800311e: 2301 movs r3, #1
8003120: e050 b.n 80031c4 <HAL_DMA_Abort+0xb4>
}
/* Check the DMA peripheral state */
if (hdma->State != HAL_DMA_STATE_BUSY)
8003122: 687b ldr r3, [r7, #4]
8003124: 2225 movs r2, #37 ; 0x25
8003126: 5c9b ldrb r3, [r3, r2]
8003128: b2db uxtb r3, r3
800312a: 2b02 cmp r3, #2
800312c: d008 beq.n 8003140 <HAL_DMA_Abort+0x30>
{
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
800312e: 687b ldr r3, [r7, #4]
8003130: 2204 movs r2, #4
8003132: 63da str r2, [r3, #60] ; 0x3c
/* Process Unlocked */
__HAL_UNLOCK(hdma);
8003134: 687b ldr r3, [r7, #4]
8003136: 2224 movs r2, #36 ; 0x24
8003138: 2100 movs r1, #0
800313a: 5499 strb r1, [r3, r2]
return HAL_ERROR;
800313c: 2301 movs r3, #1
800313e: e041 b.n 80031c4 <HAL_DMA_Abort+0xb4>
}
else
{
/* Disable DMA IT */
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
8003140: 687b ldr r3, [r7, #4]
8003142: 681b ldr r3, [r3, #0]
8003144: 681a ldr r2, [r3, #0]
8003146: 687b ldr r3, [r7, #4]
8003148: 681b ldr r3, [r3, #0]
800314a: 210e movs r1, #14
800314c: 438a bics r2, r1
800314e: 601a str r2, [r3, #0]
/* disable the DMAMUX sync overrun IT*/
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
8003150: 687b ldr r3, [r7, #4]
8003152: 6c5b ldr r3, [r3, #68] ; 0x44
8003154: 681a ldr r2, [r3, #0]
8003156: 687b ldr r3, [r7, #4]
8003158: 6c5b ldr r3, [r3, #68] ; 0x44
800315a: 491c ldr r1, [pc, #112] ; (80031cc <HAL_DMA_Abort+0xbc>)
800315c: 400a ands r2, r1
800315e: 601a str r2, [r3, #0]
/* Disable the channel */
__HAL_DMA_DISABLE(hdma);
8003160: 687b ldr r3, [r7, #4]
8003162: 681b ldr r3, [r3, #0]
8003164: 681a ldr r2, [r3, #0]
8003166: 687b ldr r3, [r7, #4]
8003168: 681b ldr r3, [r3, #0]
800316a: 2101 movs r1, #1
800316c: 438a bics r2, r1
800316e: 601a str r2, [r3, #0]
/* Clear all flags */
#if defined(DMA2)
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
#else
__HAL_DMA_CLEAR_FLAG(hdma, ((DMA_FLAG_GI1) << (hdma->ChannelIndex & 0x1CU)));
8003170: 4b17 ldr r3, [pc, #92] ; (80031d0 <HAL_DMA_Abort+0xc0>)
8003172: 6859 ldr r1, [r3, #4]
8003174: 687b ldr r3, [r7, #4]
8003176: 6c1b ldr r3, [r3, #64] ; 0x40
8003178: 221c movs r2, #28
800317a: 4013 ands r3, r2
800317c: 2201 movs r2, #1
800317e: 409a lsls r2, r3
8003180: 4b13 ldr r3, [pc, #76] ; (80031d0 <HAL_DMA_Abort+0xc0>)
8003182: 430a orrs r2, r1
8003184: 605a str r2, [r3, #4]
#endif /* DMA2 */
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
8003186: 687b ldr r3, [r7, #4]
8003188: 6c9b ldr r3, [r3, #72] ; 0x48
800318a: 687a ldr r2, [r7, #4]
800318c: 6cd2 ldr r2, [r2, #76] ; 0x4c
800318e: 605a str r2, [r3, #4]
if (hdma->DMAmuxRequestGen != 0U)
8003190: 687b ldr r3, [r7, #4]
8003192: 6d1b ldr r3, [r3, #80] ; 0x50
8003194: 2b00 cmp r3, #0
8003196: d00c beq.n 80031b2 <HAL_DMA_Abort+0xa2>
{
/* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
/* disable the request gen overrun IT*/
hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
8003198: 687b ldr r3, [r7, #4]
800319a: 6d1b ldr r3, [r3, #80] ; 0x50
800319c: 681a ldr r2, [r3, #0]
800319e: 687b ldr r3, [r7, #4]
80031a0: 6d1b ldr r3, [r3, #80] ; 0x50
80031a2: 490a ldr r1, [pc, #40] ; (80031cc <HAL_DMA_Abort+0xbc>)
80031a4: 400a ands r2, r1
80031a6: 601a str r2, [r3, #0]
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
80031a8: 687b ldr r3, [r7, #4]
80031aa: 6d5b ldr r3, [r3, #84] ; 0x54
80031ac: 687a ldr r2, [r7, #4]
80031ae: 6d92 ldr r2, [r2, #88] ; 0x58
80031b0: 605a str r2, [r3, #4]
}
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
80031b2: 687b ldr r3, [r7, #4]
80031b4: 2225 movs r2, #37 ; 0x25
80031b6: 2101 movs r1, #1
80031b8: 5499 strb r1, [r3, r2]
/* Process Unlocked */
__HAL_UNLOCK(hdma);
80031ba: 687b ldr r3, [r7, #4]
80031bc: 2224 movs r2, #36 ; 0x24
80031be: 2100 movs r1, #0
80031c0: 5499 strb r1, [r3, r2]
}
return HAL_OK;
80031c2: 2300 movs r3, #0
}
80031c4: 0018 movs r0, r3
80031c6: 46bd mov sp, r7
80031c8: b002 add sp, #8
80031ca: bd80 pop {r7, pc}
80031cc: fffffeff .word 0xfffffeff
80031d0: 40020000 .word 0x40020000
080031d4 <HAL_DMA_Abort_IT>:
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
{
80031d4: b580 push {r7, lr}
80031d6: b084 sub sp, #16
80031d8: af00 add r7, sp, #0
80031da: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
80031dc: 210f movs r1, #15
80031de: 187b adds r3, r7, r1
80031e0: 2200 movs r2, #0
80031e2: 701a strb r2, [r3, #0]
if (hdma->State != HAL_DMA_STATE_BUSY)
80031e4: 687b ldr r3, [r7, #4]
80031e6: 2225 movs r2, #37 ; 0x25
80031e8: 5c9b ldrb r3, [r3, r2]
80031ea: b2db uxtb r3, r3
80031ec: 2b02 cmp r3, #2
80031ee: d006 beq.n 80031fe <HAL_DMA_Abort_IT+0x2a>
{
/* no transfer ongoing */
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
80031f0: 687b ldr r3, [r7, #4]
80031f2: 2204 movs r2, #4
80031f4: 63da str r2, [r3, #60] ; 0x3c
status = HAL_ERROR;
80031f6: 187b adds r3, r7, r1
80031f8: 2201 movs r2, #1
80031fa: 701a strb r2, [r3, #0]
80031fc: e049 b.n 8003292 <HAL_DMA_Abort_IT+0xbe>
}
else
{
/* Disable DMA IT */
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
80031fe: 687b ldr r3, [r7, #4]
8003200: 681b ldr r3, [r3, #0]
8003202: 681a ldr r2, [r3, #0]
8003204: 687b ldr r3, [r7, #4]
8003206: 681b ldr r3, [r3, #0]
8003208: 210e movs r1, #14
800320a: 438a bics r2, r1
800320c: 601a str r2, [r3, #0]
/* Disable the channel */
__HAL_DMA_DISABLE(hdma);
800320e: 687b ldr r3, [r7, #4]
8003210: 681b ldr r3, [r3, #0]
8003212: 681a ldr r2, [r3, #0]
8003214: 687b ldr r3, [r7, #4]
8003216: 681b ldr r3, [r3, #0]
8003218: 2101 movs r1, #1
800321a: 438a bics r2, r1
800321c: 601a str r2, [r3, #0]
/* disable the DMAMUX sync overrun IT*/
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
800321e: 687b ldr r3, [r7, #4]
8003220: 6c5b ldr r3, [r3, #68] ; 0x44
8003222: 681a ldr r2, [r3, #0]
8003224: 687b ldr r3, [r7, #4]
8003226: 6c5b ldr r3, [r3, #68] ; 0x44
8003228: 491d ldr r1, [pc, #116] ; (80032a0 <HAL_DMA_Abort_IT+0xcc>)
800322a: 400a ands r2, r1
800322c: 601a str r2, [r3, #0]
/* Clear all flags */
#if defined(DMA2)
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
#else
__HAL_DMA_CLEAR_FLAG(hdma, ((DMA_FLAG_GI1) << (hdma->ChannelIndex & 0x1CU)));
800322e: 4b1d ldr r3, [pc, #116] ; (80032a4 <HAL_DMA_Abort_IT+0xd0>)
8003230: 6859 ldr r1, [r3, #4]
8003232: 687b ldr r3, [r7, #4]
8003234: 6c1b ldr r3, [r3, #64] ; 0x40
8003236: 221c movs r2, #28
8003238: 4013 ands r3, r2
800323a: 2201 movs r2, #1
800323c: 409a lsls r2, r3
800323e: 4b19 ldr r3, [pc, #100] ; (80032a4 <HAL_DMA_Abort_IT+0xd0>)
8003240: 430a orrs r2, r1
8003242: 605a str r2, [r3, #4]
#endif /* DMA2 */
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
8003244: 687b ldr r3, [r7, #4]
8003246: 6c9b ldr r3, [r3, #72] ; 0x48
8003248: 687a ldr r2, [r7, #4]
800324a: 6cd2 ldr r2, [r2, #76] ; 0x4c
800324c: 605a str r2, [r3, #4]
if (hdma->DMAmuxRequestGen != 0U)
800324e: 687b ldr r3, [r7, #4]
8003250: 6d1b ldr r3, [r3, #80] ; 0x50
8003252: 2b00 cmp r3, #0
8003254: d00c beq.n 8003270 <HAL_DMA_Abort_IT+0x9c>
{
/* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
/* disable the request gen overrun IT*/
hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
8003256: 687b ldr r3, [r7, #4]
8003258: 6d1b ldr r3, [r3, #80] ; 0x50
800325a: 681a ldr r2, [r3, #0]
800325c: 687b ldr r3, [r7, #4]
800325e: 6d1b ldr r3, [r3, #80] ; 0x50
8003260: 490f ldr r1, [pc, #60] ; (80032a0 <HAL_DMA_Abort_IT+0xcc>)
8003262: 400a ands r2, r1
8003264: 601a str r2, [r3, #0]
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
8003266: 687b ldr r3, [r7, #4]
8003268: 6d5b ldr r3, [r3, #84] ; 0x54
800326a: 687a ldr r2, [r7, #4]
800326c: 6d92 ldr r2, [r2, #88] ; 0x58
800326e: 605a str r2, [r3, #4]
}
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
8003270: 687b ldr r3, [r7, #4]
8003272: 2225 movs r2, #37 ; 0x25
8003274: 2101 movs r1, #1
8003276: 5499 strb r1, [r3, r2]
/* Process Unlocked */
__HAL_UNLOCK(hdma);
8003278: 687b ldr r3, [r7, #4]
800327a: 2224 movs r2, #36 ; 0x24
800327c: 2100 movs r1, #0
800327e: 5499 strb r1, [r3, r2]
/* Call User Abort callback */
if (hdma->XferAbortCallback != NULL)
8003280: 687b ldr r3, [r7, #4]
8003282: 6b9b ldr r3, [r3, #56] ; 0x38
8003284: 2b00 cmp r3, #0
8003286: d004 beq.n 8003292 <HAL_DMA_Abort_IT+0xbe>
{
hdma->XferAbortCallback(hdma);
8003288: 687b ldr r3, [r7, #4]
800328a: 6b9b ldr r3, [r3, #56] ; 0x38
800328c: 687a ldr r2, [r7, #4]
800328e: 0010 movs r0, r2
8003290: 4798 blx r3
}
}
return status;
8003292: 230f movs r3, #15
8003294: 18fb adds r3, r7, r3
8003296: 781b ldrb r3, [r3, #0]
}
8003298: 0018 movs r0, r3
800329a: 46bd mov sp, r7
800329c: b004 add sp, #16
800329e: bd80 pop {r7, pc}
80032a0: fffffeff .word 0xfffffeff
80032a4: 40020000 .word 0x40020000
080032a8 <HAL_DMA_IRQHandler>:
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval None
*/
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
{
80032a8: b580 push {r7, lr}
80032aa: b084 sub sp, #16
80032ac: af00 add r7, sp, #0
80032ae: 6078 str r0, [r7, #4]
#if defined(DMA2)
uint32_t flag_it = hdma->DmaBaseAddress->ISR;
#else
uint32_t flag_it = DMA1->ISR;
80032b0: 4b55 ldr r3, [pc, #340] ; (8003408 <HAL_DMA_IRQHandler+0x160>)
80032b2: 681b ldr r3, [r3, #0]
80032b4: 60fb str r3, [r7, #12]
#endif /* DMA2 */
uint32_t source_it = hdma->Instance->CCR;
80032b6: 687b ldr r3, [r7, #4]
80032b8: 681b ldr r3, [r3, #0]
80032ba: 681b ldr r3, [r3, #0]
80032bc: 60bb str r3, [r7, #8]
/* Half Transfer Complete Interrupt management ******************************/
if (((flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_HT) != 0U))
80032be: 687b ldr r3, [r7, #4]
80032c0: 6c1b ldr r3, [r3, #64] ; 0x40
80032c2: 221c movs r2, #28
80032c4: 4013 ands r3, r2
80032c6: 2204 movs r2, #4
80032c8: 409a lsls r2, r3
80032ca: 0013 movs r3, r2
80032cc: 68fa ldr r2, [r7, #12]
80032ce: 4013 ands r3, r2
80032d0: d027 beq.n 8003322 <HAL_DMA_IRQHandler+0x7a>
80032d2: 68bb ldr r3, [r7, #8]
80032d4: 2204 movs r2, #4
80032d6: 4013 ands r3, r2
80032d8: d023 beq.n 8003322 <HAL_DMA_IRQHandler+0x7a>
{
/* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
80032da: 687b ldr r3, [r7, #4]
80032dc: 681b ldr r3, [r3, #0]
80032de: 681b ldr r3, [r3, #0]
80032e0: 2220 movs r2, #32
80032e2: 4013 ands r3, r2
80032e4: d107 bne.n 80032f6 <HAL_DMA_IRQHandler+0x4e>
{
/* Disable the half transfer interrupt */
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
80032e6: 687b ldr r3, [r7, #4]
80032e8: 681b ldr r3, [r3, #0]
80032ea: 681a ldr r2, [r3, #0]
80032ec: 687b ldr r3, [r7, #4]
80032ee: 681b ldr r3, [r3, #0]
80032f0: 2104 movs r1, #4
80032f2: 438a bics r2, r1
80032f4: 601a str r2, [r3, #0]
}
/* Clear the half transfer complete flag */
#if defined(DMA2)
hdma->DmaBaseAddress->IFCR = DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1CU);
#else
__HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU)));
80032f6: 4b44 ldr r3, [pc, #272] ; (8003408 <HAL_DMA_IRQHandler+0x160>)
80032f8: 6859 ldr r1, [r3, #4]
80032fa: 687b ldr r3, [r7, #4]
80032fc: 6c1b ldr r3, [r3, #64] ; 0x40
80032fe: 221c movs r2, #28
8003300: 4013 ands r3, r2
8003302: 2204 movs r2, #4
8003304: 409a lsls r2, r3
8003306: 4b40 ldr r3, [pc, #256] ; (8003408 <HAL_DMA_IRQHandler+0x160>)
8003308: 430a orrs r2, r1
800330a: 605a str r2, [r3, #4]
#endif /* DMA2 */
/* DMA peripheral state is not updated in Half Transfer */
/* but in Transfer Complete case */
if (hdma->XferHalfCpltCallback != NULL)
800330c: 687b ldr r3, [r7, #4]
800330e: 6b1b ldr r3, [r3, #48] ; 0x30
8003310: 2b00 cmp r3, #0
8003312: d100 bne.n 8003316 <HAL_DMA_IRQHandler+0x6e>
8003314: e073 b.n 80033fe <HAL_DMA_IRQHandler+0x156>
{
/* Half transfer callback */
hdma->XferHalfCpltCallback(hdma);
8003316: 687b ldr r3, [r7, #4]
8003318: 6b1b ldr r3, [r3, #48] ; 0x30
800331a: 687a ldr r2, [r7, #4]
800331c: 0010 movs r0, r2
800331e: 4798 blx r3
if (hdma->XferHalfCpltCallback != NULL)
8003320: e06d b.n 80033fe <HAL_DMA_IRQHandler+0x156>
}
}
/* Transfer Complete Interrupt management ***********************************/
else if ((0U != (flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU)))) && (0U != (source_it & DMA_IT_TC)))
8003322: 687b ldr r3, [r7, #4]
8003324: 6c1b ldr r3, [r3, #64] ; 0x40
8003326: 221c movs r2, #28
8003328: 4013 ands r3, r2
800332a: 2202 movs r2, #2
800332c: 409a lsls r2, r3
800332e: 0013 movs r3, r2
8003330: 68fa ldr r2, [r7, #12]
8003332: 4013 ands r3, r2
8003334: d02e beq.n 8003394 <HAL_DMA_IRQHandler+0xec>
8003336: 68bb ldr r3, [r7, #8]
8003338: 2202 movs r2, #2
800333a: 4013 ands r3, r2
800333c: d02a beq.n 8003394 <HAL_DMA_IRQHandler+0xec>
{
if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
800333e: 687b ldr r3, [r7, #4]
8003340: 681b ldr r3, [r3, #0]
8003342: 681b ldr r3, [r3, #0]
8003344: 2220 movs r2, #32
8003346: 4013 ands r3, r2
8003348: d10b bne.n 8003362 <HAL_DMA_IRQHandler+0xba>
{
/* Disable the transfer complete and error interrupt */
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
800334a: 687b ldr r3, [r7, #4]
800334c: 681b ldr r3, [r3, #0]
800334e: 681a ldr r2, [r3, #0]
8003350: 687b ldr r3, [r7, #4]
8003352: 681b ldr r3, [r3, #0]
8003354: 210a movs r1, #10
8003356: 438a bics r2, r1
8003358: 601a str r2, [r3, #0]
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
800335a: 687b ldr r3, [r7, #4]
800335c: 2225 movs r2, #37 ; 0x25
800335e: 2101 movs r1, #1
8003360: 5499 strb r1, [r3, r2]
}
/* Clear the transfer complete flag */
__HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU)));
8003362: 4b29 ldr r3, [pc, #164] ; (8003408 <HAL_DMA_IRQHandler+0x160>)
8003364: 6859 ldr r1, [r3, #4]
8003366: 687b ldr r3, [r7, #4]
8003368: 6c1b ldr r3, [r3, #64] ; 0x40
800336a: 221c movs r2, #28
800336c: 4013 ands r3, r2
800336e: 2202 movs r2, #2
8003370: 409a lsls r2, r3
8003372: 4b25 ldr r3, [pc, #148] ; (8003408 <HAL_DMA_IRQHandler+0x160>)
8003374: 430a orrs r2, r1
8003376: 605a str r2, [r3, #4]
/* Process Unlocked */
__HAL_UNLOCK(hdma);
8003378: 687b ldr r3, [r7, #4]
800337a: 2224 movs r2, #36 ; 0x24
800337c: 2100 movs r1, #0
800337e: 5499 strb r1, [r3, r2]
if (hdma->XferCpltCallback != NULL)
8003380: 687b ldr r3, [r7, #4]
8003382: 6adb ldr r3, [r3, #44] ; 0x2c
8003384: 2b00 cmp r3, #0
8003386: d03a beq.n 80033fe <HAL_DMA_IRQHandler+0x156>
{
/* Transfer complete callback */
hdma->XferCpltCallback(hdma);
8003388: 687b ldr r3, [r7, #4]
800338a: 6adb ldr r3, [r3, #44] ; 0x2c
800338c: 687a ldr r2, [r7, #4]
800338e: 0010 movs r0, r2
8003390: 4798 blx r3
if (hdma->XferCpltCallback != NULL)
8003392: e034 b.n 80033fe <HAL_DMA_IRQHandler+0x156>
}
}
/* Transfer Error Interrupt management **************************************/
else if (((flag_it & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_TE) != 0U))
8003394: 687b ldr r3, [r7, #4]
8003396: 6c1b ldr r3, [r3, #64] ; 0x40
8003398: 221c movs r2, #28
800339a: 4013 ands r3, r2
800339c: 2208 movs r2, #8
800339e: 409a lsls r2, r3
80033a0: 0013 movs r3, r2
80033a2: 68fa ldr r2, [r7, #12]
80033a4: 4013 ands r3, r2
80033a6: d02b beq.n 8003400 <HAL_DMA_IRQHandler+0x158>
80033a8: 68bb ldr r3, [r7, #8]
80033aa: 2208 movs r2, #8
80033ac: 4013 ands r3, r2
80033ae: d027 beq.n 8003400 <HAL_DMA_IRQHandler+0x158>
{
/* When a DMA transfer error occurs */
/* A hardware clear of its EN bits is performed */
/* Disable ALL DMA IT */
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
80033b0: 687b ldr r3, [r7, #4]
80033b2: 681b ldr r3, [r3, #0]
80033b4: 681a ldr r2, [r3, #0]
80033b6: 687b ldr r3, [r7, #4]
80033b8: 681b ldr r3, [r3, #0]
80033ba: 210e movs r1, #14
80033bc: 438a bics r2, r1
80033be: 601a str r2, [r3, #0]
/* Clear all flags */
#if defined(DMA2)
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
#else
__HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_GI1 << (hdma->ChannelIndex & 0x1CU)));
80033c0: 4b11 ldr r3, [pc, #68] ; (8003408 <HAL_DMA_IRQHandler+0x160>)
80033c2: 6859 ldr r1, [r3, #4]
80033c4: 687b ldr r3, [r7, #4]
80033c6: 6c1b ldr r3, [r3, #64] ; 0x40
80033c8: 221c movs r2, #28
80033ca: 4013 ands r3, r2
80033cc: 2201 movs r2, #1
80033ce: 409a lsls r2, r3
80033d0: 4b0d ldr r3, [pc, #52] ; (8003408 <HAL_DMA_IRQHandler+0x160>)
80033d2: 430a orrs r2, r1
80033d4: 605a str r2, [r3, #4]
#endif /* DMA2 */
/* Update error code */
hdma->ErrorCode = HAL_DMA_ERROR_TE;
80033d6: 687b ldr r3, [r7, #4]
80033d8: 2201 movs r2, #1
80033da: 63da str r2, [r3, #60] ; 0x3c
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
80033dc: 687b ldr r3, [r7, #4]
80033de: 2225 movs r2, #37 ; 0x25
80033e0: 2101 movs r1, #1
80033e2: 5499 strb r1, [r3, r2]
/* Process Unlocked */
__HAL_UNLOCK(hdma);
80033e4: 687b ldr r3, [r7, #4]
80033e6: 2224 movs r2, #36 ; 0x24
80033e8: 2100 movs r1, #0
80033ea: 5499 strb r1, [r3, r2]
if (hdma->XferErrorCallback != NULL)
80033ec: 687b ldr r3, [r7, #4]
80033ee: 6b5b ldr r3, [r3, #52] ; 0x34
80033f0: 2b00 cmp r3, #0
80033f2: d005 beq.n 8003400 <HAL_DMA_IRQHandler+0x158>
{
/* Transfer error callback */
hdma->XferErrorCallback(hdma);
80033f4: 687b ldr r3, [r7, #4]
80033f6: 6b5b ldr r3, [r3, #52] ; 0x34
80033f8: 687a ldr r2, [r7, #4]
80033fa: 0010 movs r0, r2
80033fc: 4798 blx r3
}
else
{
/* Nothing To Do */
}
return;
80033fe: 46c0 nop ; (mov r8, r8)
8003400: 46c0 nop ; (mov r8, r8)
}
8003402: 46bd mov sp, r7
8003404: b004 add sp, #16
8003406: bd80 pop {r7, pc}
8003408: 40020000 .word 0x40020000
0800340c <DMA_SetConfig>:
* @param DstAddress The destination memory Buffer address
* @param DataLength The length of data to be transferred from source to destination
* @retval HAL status
*/
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
800340c: b580 push {r7, lr}
800340e: b084 sub sp, #16
8003410: af00 add r7, sp, #0
8003412: 60f8 str r0, [r7, #12]
8003414: 60b9 str r1, [r7, #8]
8003416: 607a str r2, [r7, #4]
8003418: 603b str r3, [r7, #0]
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
800341a: 68fb ldr r3, [r7, #12]
800341c: 6c9b ldr r3, [r3, #72] ; 0x48
800341e: 68fa ldr r2, [r7, #12]
8003420: 6cd2 ldr r2, [r2, #76] ; 0x4c
8003422: 605a str r2, [r3, #4]
if (hdma->DMAmuxRequestGen != 0U)
8003424: 68fb ldr r3, [r7, #12]
8003426: 6d1b ldr r3, [r3, #80] ; 0x50
8003428: 2b00 cmp r3, #0
800342a: d004 beq.n 8003436 <DMA_SetConfig+0x2a>
{
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
800342c: 68fb ldr r3, [r7, #12]
800342e: 6d5b ldr r3, [r3, #84] ; 0x54
8003430: 68fa ldr r2, [r7, #12]
8003432: 6d92 ldr r2, [r2, #88] ; 0x58
8003434: 605a str r2, [r3, #4]
/* Clear all flags */
#if defined(DMA2)
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
#else
__HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_GI1 << (hdma->ChannelIndex & 0x1CU)));
8003436: 4b14 ldr r3, [pc, #80] ; (8003488 <DMA_SetConfig+0x7c>)
8003438: 6859 ldr r1, [r3, #4]
800343a: 68fb ldr r3, [r7, #12]
800343c: 6c1b ldr r3, [r3, #64] ; 0x40
800343e: 221c movs r2, #28
8003440: 4013 ands r3, r2
8003442: 2201 movs r2, #1
8003444: 409a lsls r2, r3
8003446: 4b10 ldr r3, [pc, #64] ; (8003488 <DMA_SetConfig+0x7c>)
8003448: 430a orrs r2, r1
800344a: 605a str r2, [r3, #4]
#endif /* DMA2 */
/* Configure DMA Channel data length */
hdma->Instance->CNDTR = DataLength;
800344c: 68fb ldr r3, [r7, #12]
800344e: 681b ldr r3, [r3, #0]
8003450: 683a ldr r2, [r7, #0]
8003452: 605a str r2, [r3, #4]
/* Memory to Peripheral */
if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
8003454: 68fb ldr r3, [r7, #12]
8003456: 689b ldr r3, [r3, #8]
8003458: 2b10 cmp r3, #16
800345a: d108 bne.n 800346e <DMA_SetConfig+0x62>
{
/* Configure DMA Channel destination address */
hdma->Instance->CPAR = DstAddress;
800345c: 68fb ldr r3, [r7, #12]
800345e: 681b ldr r3, [r3, #0]
8003460: 687a ldr r2, [r7, #4]
8003462: 609a str r2, [r3, #8]
/* Configure DMA Channel source address */
hdma->Instance->CMAR = SrcAddress;
8003464: 68fb ldr r3, [r7, #12]
8003466: 681b ldr r3, [r3, #0]
8003468: 68ba ldr r2, [r7, #8]
800346a: 60da str r2, [r3, #12]
hdma->Instance->CPAR = SrcAddress;
/* Configure DMA Channel destination address */
hdma->Instance->CMAR = DstAddress;
}
}
800346c: e007 b.n 800347e <DMA_SetConfig+0x72>
hdma->Instance->CPAR = SrcAddress;
800346e: 68fb ldr r3, [r7, #12]
8003470: 681b ldr r3, [r3, #0]
8003472: 68ba ldr r2, [r7, #8]
8003474: 609a str r2, [r3, #8]
hdma->Instance->CMAR = DstAddress;
8003476: 68fb ldr r3, [r7, #12]
8003478: 681b ldr r3, [r3, #0]
800347a: 687a ldr r2, [r7, #4]
800347c: 60da str r2, [r3, #12]
}
800347e: 46c0 nop ; (mov r8, r8)
8003480: 46bd mov sp, r7
8003482: b004 add sp, #16
8003484: bd80 pop {r7, pc}
8003486: 46c0 nop ; (mov r8, r8)
8003488: 40020000 .word 0x40020000
0800348c <DMA_CalcDMAMUXChannelBaseAndMask>:
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval None
*/
static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma)
{
800348c: b580 push {r7, lr}
800348e: b084 sub sp, #16
8003490: af00 add r7, sp, #0
8003492: 6078 str r0, [r7, #4]
/* Prepare channel_number used for DMAmuxChannelStatusMask computation */
channel_number = (((((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U) + 7U);
}
#else
/* Associate a DMA Channel to a DMAMUX channel */
hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX1_Channel0 + ((hdma->ChannelIndex >> 2U) * ((uint32_t)DMAMUX1_Channel1 - (uint32_t)DMAMUX1_Channel0)));
8003494: 687b ldr r3, [r7, #4]
8003496: 6c1b ldr r3, [r3, #64] ; 0x40
8003498: 089b lsrs r3, r3, #2
800349a: 4a10 ldr r2, [pc, #64] ; (80034dc <DMA_CalcDMAMUXChannelBaseAndMask+0x50>)
800349c: 4694 mov ip, r2
800349e: 4463 add r3, ip
80034a0: 009b lsls r3, r3, #2
80034a2: 001a movs r2, r3
80034a4: 687b ldr r3, [r7, #4]
80034a6: 645a str r2, [r3, #68] ; 0x44
/* Prepare channel_number used for DMAmuxChannelStatusMask computation */
channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U;
80034a8: 687b ldr r3, [r7, #4]
80034aa: 681b ldr r3, [r3, #0]
80034ac: 001a movs r2, r3
80034ae: 23ff movs r3, #255 ; 0xff
80034b0: 4013 ands r3, r2
80034b2: 3b08 subs r3, #8
80034b4: 2114 movs r1, #20
80034b6: 0018 movs r0, r3
80034b8: f7fc fe24 bl 8000104 <__udivsi3>
80034bc: 0003 movs r3, r0
80034be: 60fb str r3, [r7, #12]
#endif /* DMA2 */
/* Initialize the field DMAmuxChannelStatus to DMAMUX1_ChannelStatus base */
hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus;
80034c0: 687b ldr r3, [r7, #4]
80034c2: 4a07 ldr r2, [pc, #28] ; (80034e0 <DMA_CalcDMAMUXChannelBaseAndMask+0x54>)
80034c4: 649a str r2, [r3, #72] ; 0x48
/* Initialize the field DMAmuxChannelStatusMask with the corresponding index of the DMAMUX channel selected for the current ChannelIndex */
hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1FU);
80034c6: 68fb ldr r3, [r7, #12]
80034c8: 221f movs r2, #31
80034ca: 4013 ands r3, r2
80034cc: 2201 movs r2, #1
80034ce: 409a lsls r2, r3
80034d0: 687b ldr r3, [r7, #4]
80034d2: 64da str r2, [r3, #76] ; 0x4c
}
80034d4: 46c0 nop ; (mov r8, r8)
80034d6: 46bd mov sp, r7
80034d8: b004 add sp, #16
80034da: bd80 pop {r7, pc}
80034dc: 10008200 .word 0x10008200
80034e0: 40020880 .word 0x40020880
080034e4 <DMA_CalcDMAMUXRequestGenBaseAndMask>:
* the configuration information for the specified DMA Channel.
* @retval None
*/
static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma)
{
80034e4: b580 push {r7, lr}
80034e6: b084 sub sp, #16
80034e8: af00 add r7, sp, #0
80034ea: 6078 str r0, [r7, #4]
uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID;
80034ec: 687b ldr r3, [r7, #4]
80034ee: 685b ldr r3, [r3, #4]
80034f0: 223f movs r2, #63 ; 0x3f
80034f2: 4013 ands r3, r2
80034f4: 60fb str r3, [r7, #12]
/* DMA Channels are connected to DMAMUX1 request generator blocks*/
hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U)));
80034f6: 68fb ldr r3, [r7, #12]
80034f8: 4a0a ldr r2, [pc, #40] ; (8003524 <DMA_CalcDMAMUXRequestGenBaseAndMask+0x40>)
80034fa: 4694 mov ip, r2
80034fc: 4463 add r3, ip
80034fe: 009b lsls r3, r3, #2
8003500: 001a movs r2, r3
8003502: 687b ldr r3, [r7, #4]
8003504: 651a str r2, [r3, #80] ; 0x50
hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus;
8003506: 687b ldr r3, [r7, #4]
8003508: 4a07 ldr r2, [pc, #28] ; (8003528 <DMA_CalcDMAMUXRequestGenBaseAndMask+0x44>)
800350a: 655a str r2, [r3, #84] ; 0x54
/* here "Request" is either DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR3, i.e. <= 4*/
hdma->DMAmuxRequestGenStatusMask = 1UL << ((request - 1U) & 0x3U);
800350c: 68fb ldr r3, [r7, #12]
800350e: 3b01 subs r3, #1
8003510: 2203 movs r2, #3
8003512: 4013 ands r3, r2
8003514: 2201 movs r2, #1
8003516: 409a lsls r2, r3
8003518: 687b ldr r3, [r7, #4]
800351a: 659a str r2, [r3, #88] ; 0x58
}
800351c: 46c0 nop ; (mov r8, r8)
800351e: 46bd mov sp, r7
8003520: b004 add sp, #16
8003522: bd80 pop {r7, pc}
8003524: 1000823f .word 0x1000823f
8003528: 40020940 .word 0x40020940
0800352c <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
800352c: b580 push {r7, lr}
800352e: b086 sub sp, #24
8003530: af00 add r7, sp, #0
8003532: 6078 str r0, [r7, #4]
8003534: 6039 str r1, [r7, #0]
uint32_t position = 0x00u;
8003536: 2300 movs r3, #0
8003538: 617b str r3, [r7, #20]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0x00u)
800353a: e147 b.n 80037cc <HAL_GPIO_Init+0x2a0>
{
/* Get current io position */
iocurrent = (GPIO_Init->Pin) & (1uL << position);
800353c: 683b ldr r3, [r7, #0]
800353e: 681b ldr r3, [r3, #0]
8003540: 2101 movs r1, #1
8003542: 697a ldr r2, [r7, #20]
8003544: 4091 lsls r1, r2
8003546: 000a movs r2, r1
8003548: 4013 ands r3, r2
800354a: 60fb str r3, [r7, #12]
if (iocurrent != 0x00u)
800354c: 68fb ldr r3, [r7, #12]
800354e: 2b00 cmp r3, #0
8003550: d100 bne.n 8003554 <HAL_GPIO_Init+0x28>
8003552: e138 b.n 80037c6 <HAL_GPIO_Init+0x29a>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
8003554: 683b ldr r3, [r7, #0]
8003556: 685b ldr r3, [r3, #4]
8003558: 2203 movs r2, #3
800355a: 4013 ands r3, r2
800355c: 2b01 cmp r3, #1
800355e: d005 beq.n 800356c <HAL_GPIO_Init+0x40>
8003560: 683b ldr r3, [r7, #0]
8003562: 685b ldr r3, [r3, #4]
8003564: 2203 movs r2, #3
8003566: 4013 ands r3, r2
8003568: 2b02 cmp r3, #2
800356a: d130 bne.n 80035ce <HAL_GPIO_Init+0xa2>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
800356c: 687b ldr r3, [r7, #4]
800356e: 689b ldr r3, [r3, #8]
8003570: 613b str r3, [r7, #16]
temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));
8003572: 697b ldr r3, [r7, #20]
8003574: 005b lsls r3, r3, #1
8003576: 2203 movs r2, #3
8003578: 409a lsls r2, r3
800357a: 0013 movs r3, r2
800357c: 43da mvns r2, r3
800357e: 693b ldr r3, [r7, #16]
8003580: 4013 ands r3, r2
8003582: 613b str r3, [r7, #16]
temp |= (GPIO_Init->Speed << (position * 2u));
8003584: 683b ldr r3, [r7, #0]
8003586: 68da ldr r2, [r3, #12]
8003588: 697b ldr r3, [r7, #20]
800358a: 005b lsls r3, r3, #1
800358c: 409a lsls r2, r3
800358e: 0013 movs r3, r2
8003590: 693a ldr r2, [r7, #16]
8003592: 4313 orrs r3, r2
8003594: 613b str r3, [r7, #16]
GPIOx->OSPEEDR = temp;
8003596: 687b ldr r3, [r7, #4]
8003598: 693a ldr r2, [r7, #16]
800359a: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
800359c: 687b ldr r3, [r7, #4]
800359e: 685b ldr r3, [r3, #4]
80035a0: 613b str r3, [r7, #16]
temp &= ~(GPIO_OTYPER_OT0 << position) ;
80035a2: 2201 movs r2, #1
80035a4: 697b ldr r3, [r7, #20]
80035a6: 409a lsls r2, r3
80035a8: 0013 movs r3, r2
80035aa: 43da mvns r2, r3
80035ac: 693b ldr r3, [r7, #16]
80035ae: 4013 ands r3, r2
80035b0: 613b str r3, [r7, #16]
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
80035b2: 683b ldr r3, [r7, #0]
80035b4: 685b ldr r3, [r3, #4]
80035b6: 091b lsrs r3, r3, #4
80035b8: 2201 movs r2, #1
80035ba: 401a ands r2, r3
80035bc: 697b ldr r3, [r7, #20]
80035be: 409a lsls r2, r3
80035c0: 0013 movs r3, r2
80035c2: 693a ldr r2, [r7, #16]
80035c4: 4313 orrs r3, r2
80035c6: 613b str r3, [r7, #16]
GPIOx->OTYPER = temp;
80035c8: 687b ldr r3, [r7, #4]
80035ca: 693a ldr r2, [r7, #16]
80035cc: 605a str r2, [r3, #4]
}
if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
80035ce: 683b ldr r3, [r7, #0]
80035d0: 685b ldr r3, [r3, #4]
80035d2: 2203 movs r2, #3
80035d4: 4013 ands r3, r2
80035d6: 2b03 cmp r3, #3
80035d8: d017 beq.n 800360a <HAL_GPIO_Init+0xde>
{
/* Check the Pull parameter */
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
80035da: 687b ldr r3, [r7, #4]
80035dc: 68db ldr r3, [r3, #12]
80035de: 613b str r3, [r7, #16]
temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2u));
80035e0: 697b ldr r3, [r7, #20]
80035e2: 005b lsls r3, r3, #1
80035e4: 2203 movs r2, #3
80035e6: 409a lsls r2, r3
80035e8: 0013 movs r3, r2
80035ea: 43da mvns r2, r3
80035ec: 693b ldr r3, [r7, #16]
80035ee: 4013 ands r3, r2
80035f0: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Pull) << (position * 2u));
80035f2: 683b ldr r3, [r7, #0]
80035f4: 689a ldr r2, [r3, #8]
80035f6: 697b ldr r3, [r7, #20]
80035f8: 005b lsls r3, r3, #1
80035fa: 409a lsls r2, r3
80035fc: 0013 movs r3, r2
80035fe: 693a ldr r2, [r7, #16]
8003600: 4313 orrs r3, r2
8003602: 613b str r3, [r7, #16]
GPIOx->PUPDR = temp;
8003604: 687b ldr r3, [r7, #4]
8003606: 693a ldr r2, [r7, #16]
8003608: 60da str r2, [r3, #12]
}
/* In case of Alternate function mode selection */
if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
800360a: 683b ldr r3, [r7, #0]
800360c: 685b ldr r3, [r3, #4]
800360e: 2203 movs r2, #3
8003610: 4013 ands r3, r2
8003612: 2b02 cmp r3, #2
8003614: d123 bne.n 800365e <HAL_GPIO_Init+0x132>
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3u];
8003616: 697b ldr r3, [r7, #20]
8003618: 08da lsrs r2, r3, #3
800361a: 687b ldr r3, [r7, #4]
800361c: 3208 adds r2, #8
800361e: 0092 lsls r2, r2, #2
8003620: 58d3 ldr r3, [r2, r3]
8003622: 613b str r3, [r7, #16]
temp &= ~(0xFu << ((position & 0x07u) * 4u));
8003624: 697b ldr r3, [r7, #20]
8003626: 2207 movs r2, #7
8003628: 4013 ands r3, r2
800362a: 009b lsls r3, r3, #2
800362c: 220f movs r2, #15
800362e: 409a lsls r2, r3
8003630: 0013 movs r3, r2
8003632: 43da mvns r2, r3
8003634: 693b ldr r3, [r7, #16]
8003636: 4013 ands r3, r2
8003638: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
800363a: 683b ldr r3, [r7, #0]
800363c: 691a ldr r2, [r3, #16]
800363e: 697b ldr r3, [r7, #20]
8003640: 2107 movs r1, #7
8003642: 400b ands r3, r1
8003644: 009b lsls r3, r3, #2
8003646: 409a lsls r2, r3
8003648: 0013 movs r3, r2
800364a: 693a ldr r2, [r7, #16]
800364c: 4313 orrs r3, r2
800364e: 613b str r3, [r7, #16]
GPIOx->AFR[position >> 3u] = temp;
8003650: 697b ldr r3, [r7, #20]
8003652: 08da lsrs r2, r3, #3
8003654: 687b ldr r3, [r7, #4]
8003656: 3208 adds r2, #8
8003658: 0092 lsls r2, r2, #2
800365a: 6939 ldr r1, [r7, #16]
800365c: 50d1 str r1, [r2, r3]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
800365e: 687b ldr r3, [r7, #4]
8003660: 681b ldr r3, [r3, #0]
8003662: 613b str r3, [r7, #16]
temp &= ~(GPIO_MODER_MODE0 << (position * 2u));
8003664: 697b ldr r3, [r7, #20]
8003666: 005b lsls r3, r3, #1
8003668: 2203 movs r2, #3
800366a: 409a lsls r2, r3
800366c: 0013 movs r3, r2
800366e: 43da mvns r2, r3
8003670: 693b ldr r3, [r7, #16]
8003672: 4013 ands r3, r2
8003674: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
8003676: 683b ldr r3, [r7, #0]
8003678: 685b ldr r3, [r3, #4]
800367a: 2203 movs r2, #3
800367c: 401a ands r2, r3
800367e: 697b ldr r3, [r7, #20]
8003680: 005b lsls r3, r3, #1
8003682: 409a lsls r2, r3
8003684: 0013 movs r3, r2
8003686: 693a ldr r2, [r7, #16]
8003688: 4313 orrs r3, r2
800368a: 613b str r3, [r7, #16]
GPIOx->MODER = temp;
800368c: 687b ldr r3, [r7, #4]
800368e: 693a ldr r2, [r7, #16]
8003690: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
8003692: 683b ldr r3, [r7, #0]
8003694: 685a ldr r2, [r3, #4]
8003696: 23c0 movs r3, #192 ; 0xc0
8003698: 029b lsls r3, r3, #10
800369a: 4013 ands r3, r2
800369c: d100 bne.n 80036a0 <HAL_GPIO_Init+0x174>
800369e: e092 b.n 80037c6 <HAL_GPIO_Init+0x29a>
{
temp = EXTI->EXTICR[position >> 2u];
80036a0: 4a50 ldr r2, [pc, #320] ; (80037e4 <HAL_GPIO_Init+0x2b8>)
80036a2: 697b ldr r3, [r7, #20]
80036a4: 089b lsrs r3, r3, #2
80036a6: 3318 adds r3, #24
80036a8: 009b lsls r3, r3, #2
80036aa: 589b ldr r3, [r3, r2]
80036ac: 613b str r3, [r7, #16]
temp &= ~(0x0FuL << (8u * (position & 0x03u)));
80036ae: 697b ldr r3, [r7, #20]
80036b0: 2203 movs r2, #3
80036b2: 4013 ands r3, r2
80036b4: 00db lsls r3, r3, #3
80036b6: 220f movs r2, #15
80036b8: 409a lsls r2, r3
80036ba: 0013 movs r3, r2
80036bc: 43da mvns r2, r3
80036be: 693b ldr r3, [r7, #16]
80036c0: 4013 ands r3, r2
80036c2: 613b str r3, [r7, #16]
temp |= (GPIO_GET_INDEX(GPIOx) << (8u * (position & 0x03u)));
80036c4: 687a ldr r2, [r7, #4]
80036c6: 23a0 movs r3, #160 ; 0xa0
80036c8: 05db lsls r3, r3, #23
80036ca: 429a cmp r2, r3
80036cc: d013 beq.n 80036f6 <HAL_GPIO_Init+0x1ca>
80036ce: 687b ldr r3, [r7, #4]
80036d0: 4a45 ldr r2, [pc, #276] ; (80037e8 <HAL_GPIO_Init+0x2bc>)
80036d2: 4293 cmp r3, r2
80036d4: d00d beq.n 80036f2 <HAL_GPIO_Init+0x1c6>
80036d6: 687b ldr r3, [r7, #4]
80036d8: 4a44 ldr r2, [pc, #272] ; (80037ec <HAL_GPIO_Init+0x2c0>)
80036da: 4293 cmp r3, r2
80036dc: d007 beq.n 80036ee <HAL_GPIO_Init+0x1c2>
80036de: 687b ldr r3, [r7, #4]
80036e0: 4a43 ldr r2, [pc, #268] ; (80037f0 <HAL_GPIO_Init+0x2c4>)
80036e2: 4293 cmp r3, r2
80036e4: d101 bne.n 80036ea <HAL_GPIO_Init+0x1be>
80036e6: 2303 movs r3, #3
80036e8: e006 b.n 80036f8 <HAL_GPIO_Init+0x1cc>
80036ea: 2305 movs r3, #5
80036ec: e004 b.n 80036f8 <HAL_GPIO_Init+0x1cc>
80036ee: 2302 movs r3, #2
80036f0: e002 b.n 80036f8 <HAL_GPIO_Init+0x1cc>
80036f2: 2301 movs r3, #1
80036f4: e000 b.n 80036f8 <HAL_GPIO_Init+0x1cc>
80036f6: 2300 movs r3, #0
80036f8: 697a ldr r2, [r7, #20]
80036fa: 2103 movs r1, #3
80036fc: 400a ands r2, r1
80036fe: 00d2 lsls r2, r2, #3
8003700: 4093 lsls r3, r2
8003702: 693a ldr r2, [r7, #16]
8003704: 4313 orrs r3, r2
8003706: 613b str r3, [r7, #16]
EXTI->EXTICR[position >> 2u] = temp;
8003708: 4936 ldr r1, [pc, #216] ; (80037e4 <HAL_GPIO_Init+0x2b8>)
800370a: 697b ldr r3, [r7, #20]
800370c: 089b lsrs r3, r3, #2
800370e: 3318 adds r3, #24
8003710: 009b lsls r3, r3, #2
8003712: 693a ldr r2, [r7, #16]
8003714: 505a str r2, [r3, r1]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR1;
8003716: 4b33 ldr r3, [pc, #204] ; (80037e4 <HAL_GPIO_Init+0x2b8>)
8003718: 681b ldr r3, [r3, #0]
800371a: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
800371c: 68fb ldr r3, [r7, #12]
800371e: 43da mvns r2, r3
8003720: 693b ldr r3, [r7, #16]
8003722: 4013 ands r3, r2
8003724: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
8003726: 683b ldr r3, [r7, #0]
8003728: 685a ldr r2, [r3, #4]
800372a: 2380 movs r3, #128 ; 0x80
800372c: 035b lsls r3, r3, #13
800372e: 4013 ands r3, r2
8003730: d003 beq.n 800373a <HAL_GPIO_Init+0x20e>
{
temp |= iocurrent;
8003732: 693a ldr r2, [r7, #16]
8003734: 68fb ldr r3, [r7, #12]
8003736: 4313 orrs r3, r2
8003738: 613b str r3, [r7, #16]
}
EXTI->RTSR1 = temp;
800373a: 4b2a ldr r3, [pc, #168] ; (80037e4 <HAL_GPIO_Init+0x2b8>)
800373c: 693a ldr r2, [r7, #16]
800373e: 601a str r2, [r3, #0]
temp = EXTI->FTSR1;
8003740: 4b28 ldr r3, [pc, #160] ; (80037e4 <HAL_GPIO_Init+0x2b8>)
8003742: 685b ldr r3, [r3, #4]
8003744: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8003746: 68fb ldr r3, [r7, #12]
8003748: 43da mvns r2, r3
800374a: 693b ldr r3, [r7, #16]
800374c: 4013 ands r3, r2
800374e: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
8003750: 683b ldr r3, [r7, #0]
8003752: 685a ldr r2, [r3, #4]
8003754: 2380 movs r3, #128 ; 0x80
8003756: 039b lsls r3, r3, #14
8003758: 4013 ands r3, r2
800375a: d003 beq.n 8003764 <HAL_GPIO_Init+0x238>
{
temp |= iocurrent;
800375c: 693a ldr r2, [r7, #16]
800375e: 68fb ldr r3, [r7, #12]
8003760: 4313 orrs r3, r2
8003762: 613b str r3, [r7, #16]
}
EXTI->FTSR1 = temp;
8003764: 4b1f ldr r3, [pc, #124] ; (80037e4 <HAL_GPIO_Init+0x2b8>)
8003766: 693a ldr r2, [r7, #16]
8003768: 605a str r2, [r3, #4]
/* Clear EXTI line configuration */
temp = EXTI->EMR1;
800376a: 4a1e ldr r2, [pc, #120] ; (80037e4 <HAL_GPIO_Init+0x2b8>)
800376c: 2384 movs r3, #132 ; 0x84
800376e: 58d3 ldr r3, [r2, r3]
8003770: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8003772: 68fb ldr r3, [r7, #12]
8003774: 43da mvns r2, r3
8003776: 693b ldr r3, [r7, #16]
8003778: 4013 ands r3, r2
800377a: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
800377c: 683b ldr r3, [r7, #0]
800377e: 685a ldr r2, [r3, #4]
8003780: 2380 movs r3, #128 ; 0x80
8003782: 029b lsls r3, r3, #10
8003784: 4013 ands r3, r2
8003786: d003 beq.n 8003790 <HAL_GPIO_Init+0x264>
{
temp |= iocurrent;
8003788: 693a ldr r2, [r7, #16]
800378a: 68fb ldr r3, [r7, #12]
800378c: 4313 orrs r3, r2
800378e: 613b str r3, [r7, #16]
}
EXTI->EMR1 = temp;
8003790: 4914 ldr r1, [pc, #80] ; (80037e4 <HAL_GPIO_Init+0x2b8>)
8003792: 2284 movs r2, #132 ; 0x84
8003794: 693b ldr r3, [r7, #16]
8003796: 508b str r3, [r1, r2]
temp = EXTI->IMR1;
8003798: 4a12 ldr r2, [pc, #72] ; (80037e4 <HAL_GPIO_Init+0x2b8>)
800379a: 2380 movs r3, #128 ; 0x80
800379c: 58d3 ldr r3, [r2, r3]
800379e: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
80037a0: 68fb ldr r3, [r7, #12]
80037a2: 43da mvns r2, r3
80037a4: 693b ldr r3, [r7, #16]
80037a6: 4013 ands r3, r2
80037a8: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & EXTI_IT) != 0x00u)
80037aa: 683b ldr r3, [r7, #0]
80037ac: 685a ldr r2, [r3, #4]
80037ae: 2380 movs r3, #128 ; 0x80
80037b0: 025b lsls r3, r3, #9
80037b2: 4013 ands r3, r2
80037b4: d003 beq.n 80037be <HAL_GPIO_Init+0x292>
{
temp |= iocurrent;
80037b6: 693a ldr r2, [r7, #16]
80037b8: 68fb ldr r3, [r7, #12]
80037ba: 4313 orrs r3, r2
80037bc: 613b str r3, [r7, #16]
}
EXTI->IMR1 = temp;
80037be: 4909 ldr r1, [pc, #36] ; (80037e4 <HAL_GPIO_Init+0x2b8>)
80037c0: 2280 movs r2, #128 ; 0x80
80037c2: 693b ldr r3, [r7, #16]
80037c4: 508b str r3, [r1, r2]
}
}
position++;
80037c6: 697b ldr r3, [r7, #20]
80037c8: 3301 adds r3, #1
80037ca: 617b str r3, [r7, #20]
while (((GPIO_Init->Pin) >> position) != 0x00u)
80037cc: 683b ldr r3, [r7, #0]
80037ce: 681a ldr r2, [r3, #0]
80037d0: 697b ldr r3, [r7, #20]
80037d2: 40da lsrs r2, r3
80037d4: 1e13 subs r3, r2, #0
80037d6: d000 beq.n 80037da <HAL_GPIO_Init+0x2ae>
80037d8: e6b0 b.n 800353c <HAL_GPIO_Init+0x10>
}
}
80037da: 46c0 nop ; (mov r8, r8)
80037dc: 46c0 nop ; (mov r8, r8)
80037de: 46bd mov sp, r7
80037e0: b006 add sp, #24
80037e2: bd80 pop {r7, pc}
80037e4: 40021800 .word 0x40021800
80037e8: 50000400 .word 0x50000400
80037ec: 50000800 .word 0x50000800
80037f0: 50000c00 .word 0x50000c00
080037f4 <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
80037f4: b580 push {r7, lr}
80037f6: b082 sub sp, #8
80037f8: af00 add r7, sp, #0
80037fa: 6078 str r0, [r7, #4]
80037fc: 0008 movs r0, r1
80037fe: 0011 movs r1, r2
8003800: 1cbb adds r3, r7, #2
8003802: 1c02 adds r2, r0, #0
8003804: 801a strh r2, [r3, #0]
8003806: 1c7b adds r3, r7, #1
8003808: 1c0a adds r2, r1, #0
800380a: 701a strb r2, [r3, #0]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if (PinState != GPIO_PIN_RESET)
800380c: 1c7b adds r3, r7, #1
800380e: 781b ldrb r3, [r3, #0]
8003810: 2b00 cmp r3, #0
8003812: d004 beq.n 800381e <HAL_GPIO_WritePin+0x2a>
{
GPIOx->BSRR = (uint32_t)GPIO_Pin;
8003814: 1cbb adds r3, r7, #2
8003816: 881a ldrh r2, [r3, #0]
8003818: 687b ldr r3, [r7, #4]
800381a: 619a str r2, [r3, #24]
}
else
{
GPIOx->BRR = (uint32_t)GPIO_Pin;
}
}
800381c: e003 b.n 8003826 <HAL_GPIO_WritePin+0x32>
GPIOx->BRR = (uint32_t)GPIO_Pin;
800381e: 1cbb adds r3, r7, #2
8003820: 881a ldrh r2, [r3, #0]
8003822: 687b ldr r3, [r7, #4]
8003824: 629a str r2, [r3, #40] ; 0x28
}
8003826: 46c0 nop ; (mov r8, r8)
8003828: 46bd mov sp, r7
800382a: b002 add sp, #8
800382c: bd80 pop {r7, pc}
...
08003830 <HAL_PWREx_ControlVoltageScaling>:
* cleared before returning the status. If the flag is not cleared within
* 6 microseconds, HAL_TIMEOUT status is reported.
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
{
8003830: b580 push {r7, lr}
8003832: b084 sub sp, #16
8003834: af00 add r7, sp, #0
8003836: 6078 str r0, [r7, #4]
uint32_t wait_loop_index;
assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
/* Modify voltage scaling range */
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling);
8003838: 4b19 ldr r3, [pc, #100] ; (80038a0 <HAL_PWREx_ControlVoltageScaling+0x70>)
800383a: 681b ldr r3, [r3, #0]
800383c: 4a19 ldr r2, [pc, #100] ; (80038a4 <HAL_PWREx_ControlVoltageScaling+0x74>)
800383e: 4013 ands r3, r2
8003840: 0019 movs r1, r3
8003842: 4b17 ldr r3, [pc, #92] ; (80038a0 <HAL_PWREx_ControlVoltageScaling+0x70>)
8003844: 687a ldr r2, [r7, #4]
8003846: 430a orrs r2, r1
8003848: 601a str r2, [r3, #0]
/* In case of Range 1 selected, we need to ensure that main regulator reaches new value */
if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)
800384a: 687a ldr r2, [r7, #4]
800384c: 2380 movs r3, #128 ; 0x80
800384e: 009b lsls r3, r3, #2
8003850: 429a cmp r2, r3
8003852: d11f bne.n 8003894 <HAL_PWREx_ControlVoltageScaling+0x64>
{
/* Set timeout value */
wait_loop_index = ((PWR_VOSF_SETTING_DELAY_6_US * SystemCoreClock) / 1000000U) + 1U;
8003854: 4b14 ldr r3, [pc, #80] ; (80038a8 <HAL_PWREx_ControlVoltageScaling+0x78>)
8003856: 681a ldr r2, [r3, #0]
8003858: 0013 movs r3, r2
800385a: 005b lsls r3, r3, #1
800385c: 189b adds r3, r3, r2
800385e: 005b lsls r3, r3, #1
8003860: 4912 ldr r1, [pc, #72] ; (80038ac <HAL_PWREx_ControlVoltageScaling+0x7c>)
8003862: 0018 movs r0, r3
8003864: f7fc fc4e bl 8000104 <__udivsi3>
8003868: 0003 movs r3, r0
800386a: 3301 adds r3, #1
800386c: 60fb str r3, [r7, #12]
/* Wait until VOSF is reset */
while (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
800386e: e008 b.n 8003882 <HAL_PWREx_ControlVoltageScaling+0x52>
{
if (wait_loop_index != 0U)
8003870: 68fb ldr r3, [r7, #12]
8003872: 2b00 cmp r3, #0
8003874: d003 beq.n 800387e <HAL_PWREx_ControlVoltageScaling+0x4e>
{
wait_loop_index--;
8003876: 68fb ldr r3, [r7, #12]
8003878: 3b01 subs r3, #1
800387a: 60fb str r3, [r7, #12]
800387c: e001 b.n 8003882 <HAL_PWREx_ControlVoltageScaling+0x52>
}
else
{
return HAL_TIMEOUT;
800387e: 2303 movs r3, #3
8003880: e009 b.n 8003896 <HAL_PWREx_ControlVoltageScaling+0x66>
while (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
8003882: 4b07 ldr r3, [pc, #28] ; (80038a0 <HAL_PWREx_ControlVoltageScaling+0x70>)
8003884: 695a ldr r2, [r3, #20]
8003886: 2380 movs r3, #128 ; 0x80
8003888: 00db lsls r3, r3, #3
800388a: 401a ands r2, r3
800388c: 2380 movs r3, #128 ; 0x80
800388e: 00db lsls r3, r3, #3
8003890: 429a cmp r2, r3
8003892: d0ed beq.n 8003870 <HAL_PWREx_ControlVoltageScaling+0x40>
}
}
}
return HAL_OK;
8003894: 2300 movs r3, #0
}
8003896: 0018 movs r0, r3
8003898: 46bd mov sp, r7
800389a: b004 add sp, #16
800389c: bd80 pop {r7, pc}
800389e: 46c0 nop ; (mov r8, r8)
80038a0: 40007000 .word 0x40007000
80038a4: fffff9ff .word 0xfffff9ff
80038a8: 2000000c .word 0x2000000c
80038ac: 000f4240 .word 0x000f4240
080038b0 <LL_RCC_GetAPB1Prescaler>:
* @arg @ref LL_RCC_APB1_DIV_4
* @arg @ref LL_RCC_APB1_DIV_8
* @arg @ref LL_RCC_APB1_DIV_16
*/
__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
{
80038b0: b580 push {r7, lr}
80038b2: af00 add r7, sp, #0
return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE));
80038b4: 4b03 ldr r3, [pc, #12] ; (80038c4 <LL_RCC_GetAPB1Prescaler+0x14>)
80038b6: 689a ldr r2, [r3, #8]
80038b8: 23e0 movs r3, #224 ; 0xe0
80038ba: 01db lsls r3, r3, #7
80038bc: 4013 ands r3, r2
}
80038be: 0018 movs r0, r3
80038c0: 46bd mov sp, r7
80038c2: bd80 pop {r7, pc}
80038c4: 40021000 .word 0x40021000
080038c8 <HAL_RCC_OscConfig>:
* supported by this function. User should request a transition to LSE Off
* first and then to LSE On or LSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
80038c8: b580 push {r7, lr}
80038ca: b088 sub sp, #32
80038cc: af00 add r7, sp, #0
80038ce: 6078 str r0, [r7, #4]
uint32_t tickstart;
uint32_t temp_sysclksrc;
uint32_t temp_pllckcfg;
/* Check Null pointer */
if (RCC_OscInitStruct == NULL)
80038d0: 687b ldr r3, [r7, #4]
80038d2: 2b00 cmp r3, #0
80038d4: d101 bne.n 80038da <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
80038d6: 2301 movs r3, #1
80038d8: e2fe b.n 8003ed8 <HAL_RCC_OscConfig+0x610>
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
80038da: 687b ldr r3, [r7, #4]
80038dc: 681b ldr r3, [r3, #0]
80038de: 2201 movs r2, #1
80038e0: 4013 ands r3, r2
80038e2: d100 bne.n 80038e6 <HAL_RCC_OscConfig+0x1e>
80038e4: e07c b.n 80039e0 <HAL_RCC_OscConfig+0x118>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
80038e6: 4bc3 ldr r3, [pc, #780] ; (8003bf4 <HAL_RCC_OscConfig+0x32c>)
80038e8: 689b ldr r3, [r3, #8]
80038ea: 2238 movs r2, #56 ; 0x38
80038ec: 4013 ands r3, r2
80038ee: 61bb str r3, [r7, #24]
temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE();
80038f0: 4bc0 ldr r3, [pc, #768] ; (8003bf4 <HAL_RCC_OscConfig+0x32c>)
80038f2: 68db ldr r3, [r3, #12]
80038f4: 2203 movs r2, #3
80038f6: 4013 ands r3, r2
80038f8: 617b str r3, [r7, #20]
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
if (((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_pllckcfg == RCC_PLLSOURCE_HSE))
80038fa: 69bb ldr r3, [r7, #24]
80038fc: 2b10 cmp r3, #16
80038fe: d102 bne.n 8003906 <HAL_RCC_OscConfig+0x3e>
8003900: 697b ldr r3, [r7, #20]
8003902: 2b03 cmp r3, #3
8003904: d002 beq.n 800390c <HAL_RCC_OscConfig+0x44>
|| (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSE))
8003906: 69bb ldr r3, [r7, #24]
8003908: 2b08 cmp r3, #8
800390a: d10b bne.n 8003924 <HAL_RCC_OscConfig+0x5c>
{
if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
800390c: 4bb9 ldr r3, [pc, #740] ; (8003bf4 <HAL_RCC_OscConfig+0x32c>)
800390e: 681a ldr r2, [r3, #0]
8003910: 2380 movs r3, #128 ; 0x80
8003912: 029b lsls r3, r3, #10
8003914: 4013 ands r3, r2
8003916: d062 beq.n 80039de <HAL_RCC_OscConfig+0x116>
8003918: 687b ldr r3, [r7, #4]
800391a: 685b ldr r3, [r3, #4]
800391c: 2b00 cmp r3, #0
800391e: d15e bne.n 80039de <HAL_RCC_OscConfig+0x116>
{
return HAL_ERROR;
8003920: 2301 movs r3, #1
8003922: e2d9 b.n 8003ed8 <HAL_RCC_OscConfig+0x610>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
8003924: 687b ldr r3, [r7, #4]
8003926: 685a ldr r2, [r3, #4]
8003928: 2380 movs r3, #128 ; 0x80
800392a: 025b lsls r3, r3, #9
800392c: 429a cmp r2, r3
800392e: d107 bne.n 8003940 <HAL_RCC_OscConfig+0x78>
8003930: 4bb0 ldr r3, [pc, #704] ; (8003bf4 <HAL_RCC_OscConfig+0x32c>)
8003932: 681a ldr r2, [r3, #0]
8003934: 4baf ldr r3, [pc, #700] ; (8003bf4 <HAL_RCC_OscConfig+0x32c>)
8003936: 2180 movs r1, #128 ; 0x80
8003938: 0249 lsls r1, r1, #9
800393a: 430a orrs r2, r1
800393c: 601a str r2, [r3, #0]
800393e: e020 b.n 8003982 <HAL_RCC_OscConfig+0xba>
8003940: 687b ldr r3, [r7, #4]
8003942: 685a ldr r2, [r3, #4]
8003944: 23a0 movs r3, #160 ; 0xa0
8003946: 02db lsls r3, r3, #11
8003948: 429a cmp r2, r3
800394a: d10e bne.n 800396a <HAL_RCC_OscConfig+0xa2>
800394c: 4ba9 ldr r3, [pc, #676] ; (8003bf4 <HAL_RCC_OscConfig+0x32c>)
800394e: 681a ldr r2, [r3, #0]
8003950: 4ba8 ldr r3, [pc, #672] ; (8003bf4 <HAL_RCC_OscConfig+0x32c>)
8003952: 2180 movs r1, #128 ; 0x80
8003954: 02c9 lsls r1, r1, #11
8003956: 430a orrs r2, r1
8003958: 601a str r2, [r3, #0]
800395a: 4ba6 ldr r3, [pc, #664] ; (8003bf4 <HAL_RCC_OscConfig+0x32c>)
800395c: 681a ldr r2, [r3, #0]
800395e: 4ba5 ldr r3, [pc, #660] ; (8003bf4 <HAL_RCC_OscConfig+0x32c>)
8003960: 2180 movs r1, #128 ; 0x80
8003962: 0249 lsls r1, r1, #9
8003964: 430a orrs r2, r1
8003966: 601a str r2, [r3, #0]
8003968: e00b b.n 8003982 <HAL_RCC_OscConfig+0xba>
800396a: 4ba2 ldr r3, [pc, #648] ; (8003bf4 <HAL_RCC_OscConfig+0x32c>)
800396c: 681a ldr r2, [r3, #0]
800396e: 4ba1 ldr r3, [pc, #644] ; (8003bf4 <HAL_RCC_OscConfig+0x32c>)
8003970: 49a1 ldr r1, [pc, #644] ; (8003bf8 <HAL_RCC_OscConfig+0x330>)
8003972: 400a ands r2, r1
8003974: 601a str r2, [r3, #0]
8003976: 4b9f ldr r3, [pc, #636] ; (8003bf4 <HAL_RCC_OscConfig+0x32c>)
8003978: 681a ldr r2, [r3, #0]
800397a: 4b9e ldr r3, [pc, #632] ; (8003bf4 <HAL_RCC_OscConfig+0x32c>)
800397c: 499f ldr r1, [pc, #636] ; (8003bfc <HAL_RCC_OscConfig+0x334>)
800397e: 400a ands r2, r1
8003980: 601a str r2, [r3, #0]
/* Check the HSE State */
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
8003982: 687b ldr r3, [r7, #4]
8003984: 685b ldr r3, [r3, #4]
8003986: 2b00 cmp r3, #0
8003988: d014 beq.n 80039b4 <HAL_RCC_OscConfig+0xec>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
800398a: f7fe f8df bl 8001b4c <HAL_GetTick>
800398e: 0003 movs r3, r0
8003990: 613b str r3, [r7, #16]
/* Wait till HSE is ready */
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
8003992: e008 b.n 80039a6 <HAL_RCC_OscConfig+0xde>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
8003994: f7fe f8da bl 8001b4c <HAL_GetTick>
8003998: 0002 movs r2, r0
800399a: 693b ldr r3, [r7, #16]
800399c: 1ad3 subs r3, r2, r3
800399e: 2b64 cmp r3, #100 ; 0x64
80039a0: d901 bls.n 80039a6 <HAL_RCC_OscConfig+0xde>
{
return HAL_TIMEOUT;
80039a2: 2303 movs r3, #3
80039a4: e298 b.n 8003ed8 <HAL_RCC_OscConfig+0x610>
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
80039a6: 4b93 ldr r3, [pc, #588] ; (8003bf4 <HAL_RCC_OscConfig+0x32c>)
80039a8: 681a ldr r2, [r3, #0]
80039aa: 2380 movs r3, #128 ; 0x80
80039ac: 029b lsls r3, r3, #10
80039ae: 4013 ands r3, r2
80039b0: d0f0 beq.n 8003994 <HAL_RCC_OscConfig+0xcc>
80039b2: e015 b.n 80039e0 <HAL_RCC_OscConfig+0x118>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
80039b4: f7fe f8ca bl 8001b4c <HAL_GetTick>
80039b8: 0003 movs r3, r0
80039ba: 613b str r3, [r7, #16]
/* Wait till HSE is disabled */
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
80039bc: e008 b.n 80039d0 <HAL_RCC_OscConfig+0x108>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
80039be: f7fe f8c5 bl 8001b4c <HAL_GetTick>
80039c2: 0002 movs r2, r0
80039c4: 693b ldr r3, [r7, #16]
80039c6: 1ad3 subs r3, r2, r3
80039c8: 2b64 cmp r3, #100 ; 0x64
80039ca: d901 bls.n 80039d0 <HAL_RCC_OscConfig+0x108>
{
return HAL_TIMEOUT;
80039cc: 2303 movs r3, #3
80039ce: e283 b.n 8003ed8 <HAL_RCC_OscConfig+0x610>
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
80039d0: 4b88 ldr r3, [pc, #544] ; (8003bf4 <HAL_RCC_OscConfig+0x32c>)
80039d2: 681a ldr r2, [r3, #0]
80039d4: 2380 movs r3, #128 ; 0x80
80039d6: 029b lsls r3, r3, #10
80039d8: 4013 ands r3, r2
80039da: d1f0 bne.n 80039be <HAL_RCC_OscConfig+0xf6>
80039dc: e000 b.n 80039e0 <HAL_RCC_OscConfig+0x118>
if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
80039de: 46c0 nop ; (mov r8, r8)
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
80039e0: 687b ldr r3, [r7, #4]
80039e2: 681b ldr r3, [r3, #0]
80039e4: 2202 movs r2, #2
80039e6: 4013 ands r3, r2
80039e8: d100 bne.n 80039ec <HAL_RCC_OscConfig+0x124>
80039ea: e099 b.n 8003b20 <HAL_RCC_OscConfig+0x258>
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
assert_param(IS_RCC_HSIDIV(RCC_OscInitStruct->HSIDiv));
/* Check if HSI16 is used as system clock or as PLL source when PLL is selected as system clock */
temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
80039ec: 4b81 ldr r3, [pc, #516] ; (8003bf4 <HAL_RCC_OscConfig+0x32c>)
80039ee: 689b ldr r3, [r3, #8]
80039f0: 2238 movs r2, #56 ; 0x38
80039f2: 4013 ands r3, r2
80039f4: 61bb str r3, [r7, #24]
temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE();
80039f6: 4b7f ldr r3, [pc, #508] ; (8003bf4 <HAL_RCC_OscConfig+0x32c>)
80039f8: 68db ldr r3, [r3, #12]
80039fa: 2203 movs r2, #3
80039fc: 4013 ands r3, r2
80039fe: 617b str r3, [r7, #20]
if (((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_pllckcfg == RCC_PLLSOURCE_HSI))
8003a00: 69bb ldr r3, [r7, #24]
8003a02: 2b10 cmp r3, #16
8003a04: d102 bne.n 8003a0c <HAL_RCC_OscConfig+0x144>
8003a06: 697b ldr r3, [r7, #20]
8003a08: 2b02 cmp r3, #2
8003a0a: d002 beq.n 8003a12 <HAL_RCC_OscConfig+0x14a>
|| (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI))
8003a0c: 69bb ldr r3, [r7, #24]
8003a0e: 2b00 cmp r3, #0
8003a10: d135 bne.n 8003a7e <HAL_RCC_OscConfig+0x1b6>
{
/* When HSI is used as system clock or as PLL input clock it can not be disabled */
if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
8003a12: 4b78 ldr r3, [pc, #480] ; (8003bf4 <HAL_RCC_OscConfig+0x32c>)
8003a14: 681a ldr r2, [r3, #0]
8003a16: 2380 movs r3, #128 ; 0x80
8003a18: 00db lsls r3, r3, #3
8003a1a: 4013 ands r3, r2
8003a1c: d005 beq.n 8003a2a <HAL_RCC_OscConfig+0x162>
8003a1e: 687b ldr r3, [r7, #4]
8003a20: 68db ldr r3, [r3, #12]
8003a22: 2b00 cmp r3, #0
8003a24: d101 bne.n 8003a2a <HAL_RCC_OscConfig+0x162>
{
return HAL_ERROR;
8003a26: 2301 movs r3, #1
8003a28: e256 b.n 8003ed8 <HAL_RCC_OscConfig+0x610>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8003a2a: 4b72 ldr r3, [pc, #456] ; (8003bf4 <HAL_RCC_OscConfig+0x32c>)
8003a2c: 685b ldr r3, [r3, #4]
8003a2e: 4a74 ldr r2, [pc, #464] ; (8003c00 <HAL_RCC_OscConfig+0x338>)
8003a30: 4013 ands r3, r2
8003a32: 0019 movs r1, r3
8003a34: 687b ldr r3, [r7, #4]
8003a36: 695b ldr r3, [r3, #20]
8003a38: 021a lsls r2, r3, #8
8003a3a: 4b6e ldr r3, [pc, #440] ; (8003bf4 <HAL_RCC_OscConfig+0x32c>)
8003a3c: 430a orrs r2, r1
8003a3e: 605a str r2, [r3, #4]
if (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI)
8003a40: 69bb ldr r3, [r7, #24]
8003a42: 2b00 cmp r3, #0
8003a44: d112 bne.n 8003a6c <HAL_RCC_OscConfig+0x1a4>
{
/* Adjust the HSI16 division factor */
__HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv);
8003a46: 4b6b ldr r3, [pc, #428] ; (8003bf4 <HAL_RCC_OscConfig+0x32c>)
8003a48: 681b ldr r3, [r3, #0]
8003a4a: 4a6e ldr r2, [pc, #440] ; (8003c04 <HAL_RCC_OscConfig+0x33c>)
8003a4c: 4013 ands r3, r2
8003a4e: 0019 movs r1, r3
8003a50: 687b ldr r3, [r7, #4]
8003a52: 691a ldr r2, [r3, #16]
8003a54: 4b67 ldr r3, [pc, #412] ; (8003bf4 <HAL_RCC_OscConfig+0x32c>)
8003a56: 430a orrs r2, r1
8003a58: 601a str r2, [r3, #0]
/* Update the SystemCoreClock global variable with HSISYS value */
SystemCoreClock = (HSI_VALUE / (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos)));
8003a5a: 4b66 ldr r3, [pc, #408] ; (8003bf4 <HAL_RCC_OscConfig+0x32c>)
8003a5c: 681b ldr r3, [r3, #0]
8003a5e: 0adb lsrs r3, r3, #11
8003a60: 2207 movs r2, #7
8003a62: 4013 ands r3, r2
8003a64: 4a68 ldr r2, [pc, #416] ; (8003c08 <HAL_RCC_OscConfig+0x340>)
8003a66: 40da lsrs r2, r3
8003a68: 4b68 ldr r3, [pc, #416] ; (8003c0c <HAL_RCC_OscConfig+0x344>)
8003a6a: 601a str r2, [r3, #0]
}
/* Adapt Systick interrupt period */
if (HAL_InitTick(uwTickPrio) != HAL_OK)
8003a6c: 4b68 ldr r3, [pc, #416] ; (8003c10 <HAL_RCC_OscConfig+0x348>)
8003a6e: 681b ldr r3, [r3, #0]
8003a70: 0018 movs r0, r3
8003a72: f7fe f80f bl 8001a94 <HAL_InitTick>
8003a76: 1e03 subs r3, r0, #0
8003a78: d051 beq.n 8003b1e <HAL_RCC_OscConfig+0x256>
{
return HAL_ERROR;
8003a7a: 2301 movs r3, #1
8003a7c: e22c b.n 8003ed8 <HAL_RCC_OscConfig+0x610>
}
}
else
{
/* Check the HSI State */
if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
8003a7e: 687b ldr r3, [r7, #4]
8003a80: 68db ldr r3, [r3, #12]
8003a82: 2b00 cmp r3, #0
8003a84: d030 beq.n 8003ae8 <HAL_RCC_OscConfig+0x220>
{
/* Configure the HSI16 division factor */
__HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv);
8003a86: 4b5b ldr r3, [pc, #364] ; (8003bf4 <HAL_RCC_OscConfig+0x32c>)
8003a88: 681b ldr r3, [r3, #0]
8003a8a: 4a5e ldr r2, [pc, #376] ; (8003c04 <HAL_RCC_OscConfig+0x33c>)
8003a8c: 4013 ands r3, r2
8003a8e: 0019 movs r1, r3
8003a90: 687b ldr r3, [r7, #4]
8003a92: 691a ldr r2, [r3, #16]
8003a94: 4b57 ldr r3, [pc, #348] ; (8003bf4 <HAL_RCC_OscConfig+0x32c>)
8003a96: 430a orrs r2, r1
8003a98: 601a str r2, [r3, #0]
/* Enable the Internal High Speed oscillator (HSI16). */
__HAL_RCC_HSI_ENABLE();
8003a9a: 4b56 ldr r3, [pc, #344] ; (8003bf4 <HAL_RCC_OscConfig+0x32c>)
8003a9c: 681a ldr r2, [r3, #0]
8003a9e: 4b55 ldr r3, [pc, #340] ; (8003bf4 <HAL_RCC_OscConfig+0x32c>)
8003aa0: 2180 movs r1, #128 ; 0x80
8003aa2: 0049 lsls r1, r1, #1
8003aa4: 430a orrs r2, r1
8003aa6: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003aa8: f7fe f850 bl 8001b4c <HAL_GetTick>
8003aac: 0003 movs r3, r0
8003aae: 613b str r3, [r7, #16]
/* Wait till HSI is ready */
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
8003ab0: e008 b.n 8003ac4 <HAL_RCC_OscConfig+0x1fc>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
8003ab2: f7fe f84b bl 8001b4c <HAL_GetTick>
8003ab6: 0002 movs r2, r0
8003ab8: 693b ldr r3, [r7, #16]
8003aba: 1ad3 subs r3, r2, r3
8003abc: 2b02 cmp r3, #2
8003abe: d901 bls.n 8003ac4 <HAL_RCC_OscConfig+0x1fc>
{
return HAL_TIMEOUT;
8003ac0: 2303 movs r3, #3
8003ac2: e209 b.n 8003ed8 <HAL_RCC_OscConfig+0x610>
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
8003ac4: 4b4b ldr r3, [pc, #300] ; (8003bf4 <HAL_RCC_OscConfig+0x32c>)
8003ac6: 681a ldr r2, [r3, #0]
8003ac8: 2380 movs r3, #128 ; 0x80
8003aca: 00db lsls r3, r3, #3
8003acc: 4013 ands r3, r2
8003ace: d0f0 beq.n 8003ab2 <HAL_RCC_OscConfig+0x1ea>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8003ad0: 4b48 ldr r3, [pc, #288] ; (8003bf4 <HAL_RCC_OscConfig+0x32c>)
8003ad2: 685b ldr r3, [r3, #4]
8003ad4: 4a4a ldr r2, [pc, #296] ; (8003c00 <HAL_RCC_OscConfig+0x338>)
8003ad6: 4013 ands r3, r2
8003ad8: 0019 movs r1, r3
8003ada: 687b ldr r3, [r7, #4]
8003adc: 695b ldr r3, [r3, #20]
8003ade: 021a lsls r2, r3, #8
8003ae0: 4b44 ldr r3, [pc, #272] ; (8003bf4 <HAL_RCC_OscConfig+0x32c>)
8003ae2: 430a orrs r2, r1
8003ae4: 605a str r2, [r3, #4]
8003ae6: e01b b.n 8003b20 <HAL_RCC_OscConfig+0x258>
}
else
{
/* Disable the Internal High Speed oscillator (HSI16). */
__HAL_RCC_HSI_DISABLE();
8003ae8: 4b42 ldr r3, [pc, #264] ; (8003bf4 <HAL_RCC_OscConfig+0x32c>)
8003aea: 681a ldr r2, [r3, #0]
8003aec: 4b41 ldr r3, [pc, #260] ; (8003bf4 <HAL_RCC_OscConfig+0x32c>)
8003aee: 4949 ldr r1, [pc, #292] ; (8003c14 <HAL_RCC_OscConfig+0x34c>)
8003af0: 400a ands r2, r1
8003af2: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003af4: f7fe f82a bl 8001b4c <HAL_GetTick>
8003af8: 0003 movs r3, r0
8003afa: 613b str r3, [r7, #16]
/* Wait till HSI is disabled */
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
8003afc: e008 b.n 8003b10 <HAL_RCC_OscConfig+0x248>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
8003afe: f7fe f825 bl 8001b4c <HAL_GetTick>
8003b02: 0002 movs r2, r0
8003b04: 693b ldr r3, [r7, #16]
8003b06: 1ad3 subs r3, r2, r3
8003b08: 2b02 cmp r3, #2
8003b0a: d901 bls.n 8003b10 <HAL_RCC_OscConfig+0x248>
{
return HAL_TIMEOUT;
8003b0c: 2303 movs r3, #3
8003b0e: e1e3 b.n 8003ed8 <HAL_RCC_OscConfig+0x610>
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
8003b10: 4b38 ldr r3, [pc, #224] ; (8003bf4 <HAL_RCC_OscConfig+0x32c>)
8003b12: 681a ldr r2, [r3, #0]
8003b14: 2380 movs r3, #128 ; 0x80
8003b16: 00db lsls r3, r3, #3
8003b18: 4013 ands r3, r2
8003b1a: d1f0 bne.n 8003afe <HAL_RCC_OscConfig+0x236>
8003b1c: e000 b.n 8003b20 <HAL_RCC_OscConfig+0x258>
if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
8003b1e: 46c0 nop ; (mov r8, r8)
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
8003b20: 687b ldr r3, [r7, #4]
8003b22: 681b ldr r3, [r3, #0]
8003b24: 2208 movs r2, #8
8003b26: 4013 ands r3, r2
8003b28: d047 beq.n 8003bba <HAL_RCC_OscConfig+0x2f2>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check if LSI is used as system clock */
if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSI)
8003b2a: 4b32 ldr r3, [pc, #200] ; (8003bf4 <HAL_RCC_OscConfig+0x32c>)
8003b2c: 689b ldr r3, [r3, #8]
8003b2e: 2238 movs r2, #56 ; 0x38
8003b30: 4013 ands r3, r2
8003b32: 2b18 cmp r3, #24
8003b34: d10a bne.n 8003b4c <HAL_RCC_OscConfig+0x284>
{
/* When LSI is used as system clock it will not be disabled */
if ((((RCC->CSR) & RCC_CSR_LSIRDY) != 0U) && (RCC_OscInitStruct->LSIState == RCC_LSI_OFF))
8003b36: 4b2f ldr r3, [pc, #188] ; (8003bf4 <HAL_RCC_OscConfig+0x32c>)
8003b38: 6e1b ldr r3, [r3, #96] ; 0x60
8003b3a: 2202 movs r2, #2
8003b3c: 4013 ands r3, r2
8003b3e: d03c beq.n 8003bba <HAL_RCC_OscConfig+0x2f2>
8003b40: 687b ldr r3, [r7, #4]
8003b42: 699b ldr r3, [r3, #24]
8003b44: 2b00 cmp r3, #0
8003b46: d138 bne.n 8003bba <HAL_RCC_OscConfig+0x2f2>
{
return HAL_ERROR;
8003b48: 2301 movs r3, #1
8003b4a: e1c5 b.n 8003ed8 <HAL_RCC_OscConfig+0x610>
}
}
else
{
/* Check the LSI State */
if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
8003b4c: 687b ldr r3, [r7, #4]
8003b4e: 699b ldr r3, [r3, #24]
8003b50: 2b00 cmp r3, #0
8003b52: d019 beq.n 8003b88 <HAL_RCC_OscConfig+0x2c0>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
8003b54: 4b27 ldr r3, [pc, #156] ; (8003bf4 <HAL_RCC_OscConfig+0x32c>)
8003b56: 6e1a ldr r2, [r3, #96] ; 0x60
8003b58: 4b26 ldr r3, [pc, #152] ; (8003bf4 <HAL_RCC_OscConfig+0x32c>)
8003b5a: 2101 movs r1, #1
8003b5c: 430a orrs r2, r1
8003b5e: 661a str r2, [r3, #96] ; 0x60
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003b60: f7fd fff4 bl 8001b4c <HAL_GetTick>
8003b64: 0003 movs r3, r0
8003b66: 613b str r3, [r7, #16]
/* Wait till LSI is ready */
while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
8003b68: e008 b.n 8003b7c <HAL_RCC_OscConfig+0x2b4>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
8003b6a: f7fd ffef bl 8001b4c <HAL_GetTick>
8003b6e: 0002 movs r2, r0
8003b70: 693b ldr r3, [r7, #16]
8003b72: 1ad3 subs r3, r2, r3
8003b74: 2b02 cmp r3, #2
8003b76: d901 bls.n 8003b7c <HAL_RCC_OscConfig+0x2b4>
{
return HAL_TIMEOUT;
8003b78: 2303 movs r3, #3
8003b7a: e1ad b.n 8003ed8 <HAL_RCC_OscConfig+0x610>
while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
8003b7c: 4b1d ldr r3, [pc, #116] ; (8003bf4 <HAL_RCC_OscConfig+0x32c>)
8003b7e: 6e1b ldr r3, [r3, #96] ; 0x60
8003b80: 2202 movs r2, #2
8003b82: 4013 ands r3, r2
8003b84: d0f1 beq.n 8003b6a <HAL_RCC_OscConfig+0x2a2>
8003b86: e018 b.n 8003bba <HAL_RCC_OscConfig+0x2f2>
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
8003b88: 4b1a ldr r3, [pc, #104] ; (8003bf4 <HAL_RCC_OscConfig+0x32c>)
8003b8a: 6e1a ldr r2, [r3, #96] ; 0x60
8003b8c: 4b19 ldr r3, [pc, #100] ; (8003bf4 <HAL_RCC_OscConfig+0x32c>)
8003b8e: 2101 movs r1, #1
8003b90: 438a bics r2, r1
8003b92: 661a str r2, [r3, #96] ; 0x60
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003b94: f7fd ffda bl 8001b4c <HAL_GetTick>
8003b98: 0003 movs r3, r0
8003b9a: 613b str r3, [r7, #16]
/* Wait till LSI is disabled */
while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
8003b9c: e008 b.n 8003bb0 <HAL_RCC_OscConfig+0x2e8>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
8003b9e: f7fd ffd5 bl 8001b4c <HAL_GetTick>
8003ba2: 0002 movs r2, r0
8003ba4: 693b ldr r3, [r7, #16]
8003ba6: 1ad3 subs r3, r2, r3
8003ba8: 2b02 cmp r3, #2
8003baa: d901 bls.n 8003bb0 <HAL_RCC_OscConfig+0x2e8>
{
return HAL_TIMEOUT;
8003bac: 2303 movs r3, #3
8003bae: e193 b.n 8003ed8 <HAL_RCC_OscConfig+0x610>
while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
8003bb0: 4b10 ldr r3, [pc, #64] ; (8003bf4 <HAL_RCC_OscConfig+0x32c>)
8003bb2: 6e1b ldr r3, [r3, #96] ; 0x60
8003bb4: 2202 movs r2, #2
8003bb6: 4013 ands r3, r2
8003bb8: d1f1 bne.n 8003b9e <HAL_RCC_OscConfig+0x2d6>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
8003bba: 687b ldr r3, [r7, #4]
8003bbc: 681b ldr r3, [r3, #0]
8003bbe: 2204 movs r2, #4
8003bc0: 4013 ands r3, r2
8003bc2: d100 bne.n 8003bc6 <HAL_RCC_OscConfig+0x2fe>
8003bc4: e0c6 b.n 8003d54 <HAL_RCC_OscConfig+0x48c>
{
FlagStatus pwrclkchanged = RESET;
8003bc6: 231f movs r3, #31
8003bc8: 18fb adds r3, r7, r3
8003bca: 2200 movs r2, #0
8003bcc: 701a strb r2, [r3, #0]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* When the LSE is used as system clock, it is not allowed disable it */
if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSE)
8003bce: 4b09 ldr r3, [pc, #36] ; (8003bf4 <HAL_RCC_OscConfig+0x32c>)
8003bd0: 689b ldr r3, [r3, #8]
8003bd2: 2238 movs r2, #56 ; 0x38
8003bd4: 4013 ands r3, r2
8003bd6: 2b20 cmp r3, #32
8003bd8: d11e bne.n 8003c18 <HAL_RCC_OscConfig+0x350>
{
if ((((RCC->BDCR) & RCC_BDCR_LSERDY) != 0U) && (RCC_OscInitStruct->LSEState == RCC_LSE_OFF))
8003bda: 4b06 ldr r3, [pc, #24] ; (8003bf4 <HAL_RCC_OscConfig+0x32c>)
8003bdc: 6ddb ldr r3, [r3, #92] ; 0x5c
8003bde: 2202 movs r2, #2
8003be0: 4013 ands r3, r2
8003be2: d100 bne.n 8003be6 <HAL_RCC_OscConfig+0x31e>
8003be4: e0b6 b.n 8003d54 <HAL_RCC_OscConfig+0x48c>
8003be6: 687b ldr r3, [r7, #4]
8003be8: 689b ldr r3, [r3, #8]
8003bea: 2b00 cmp r3, #0
8003bec: d000 beq.n 8003bf0 <HAL_RCC_OscConfig+0x328>
8003bee: e0b1 b.n 8003d54 <HAL_RCC_OscConfig+0x48c>
{
return HAL_ERROR;
8003bf0: 2301 movs r3, #1
8003bf2: e171 b.n 8003ed8 <HAL_RCC_OscConfig+0x610>
8003bf4: 40021000 .word 0x40021000
8003bf8: fffeffff .word 0xfffeffff
8003bfc: fffbffff .word 0xfffbffff
8003c00: ffff80ff .word 0xffff80ff
8003c04: ffffc7ff .word 0xffffc7ff
8003c08: 00f42400 .word 0x00f42400
8003c0c: 2000000c .word 0x2000000c
8003c10: 20000010 .word 0x20000010
8003c14: fffffeff .word 0xfffffeff
}
else
{
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if (__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U)
8003c18: 4bb1 ldr r3, [pc, #708] ; (8003ee0 <HAL_RCC_OscConfig+0x618>)
8003c1a: 6bda ldr r2, [r3, #60] ; 0x3c
8003c1c: 2380 movs r3, #128 ; 0x80
8003c1e: 055b lsls r3, r3, #21
8003c20: 4013 ands r3, r2
8003c22: d101 bne.n 8003c28 <HAL_RCC_OscConfig+0x360>
8003c24: 2301 movs r3, #1
8003c26: e000 b.n 8003c2a <HAL_RCC_OscConfig+0x362>
8003c28: 2300 movs r3, #0
8003c2a: 2b00 cmp r3, #0
8003c2c: d011 beq.n 8003c52 <HAL_RCC_OscConfig+0x38a>
{
__HAL_RCC_PWR_CLK_ENABLE();
8003c2e: 4bac ldr r3, [pc, #688] ; (8003ee0 <HAL_RCC_OscConfig+0x618>)
8003c30: 6bda ldr r2, [r3, #60] ; 0x3c
8003c32: 4bab ldr r3, [pc, #684] ; (8003ee0 <HAL_RCC_OscConfig+0x618>)
8003c34: 2180 movs r1, #128 ; 0x80
8003c36: 0549 lsls r1, r1, #21
8003c38: 430a orrs r2, r1
8003c3a: 63da str r2, [r3, #60] ; 0x3c
8003c3c: 4ba8 ldr r3, [pc, #672] ; (8003ee0 <HAL_RCC_OscConfig+0x618>)
8003c3e: 6bda ldr r2, [r3, #60] ; 0x3c
8003c40: 2380 movs r3, #128 ; 0x80
8003c42: 055b lsls r3, r3, #21
8003c44: 4013 ands r3, r2
8003c46: 60fb str r3, [r7, #12]
8003c48: 68fb ldr r3, [r7, #12]
pwrclkchanged = SET;
8003c4a: 231f movs r3, #31
8003c4c: 18fb adds r3, r7, r3
8003c4e: 2201 movs r2, #1
8003c50: 701a strb r2, [r3, #0]
}
if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
8003c52: 4ba4 ldr r3, [pc, #656] ; (8003ee4 <HAL_RCC_OscConfig+0x61c>)
8003c54: 681a ldr r2, [r3, #0]
8003c56: 2380 movs r3, #128 ; 0x80
8003c58: 005b lsls r3, r3, #1
8003c5a: 4013 ands r3, r2
8003c5c: d11a bne.n 8003c94 <HAL_RCC_OscConfig+0x3cc>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR1, PWR_CR1_DBP);
8003c5e: 4ba1 ldr r3, [pc, #644] ; (8003ee4 <HAL_RCC_OscConfig+0x61c>)
8003c60: 681a ldr r2, [r3, #0]
8003c62: 4ba0 ldr r3, [pc, #640] ; (8003ee4 <HAL_RCC_OscConfig+0x61c>)
8003c64: 2180 movs r1, #128 ; 0x80
8003c66: 0049 lsls r1, r1, #1
8003c68: 430a orrs r2, r1
8003c6a: 601a str r2, [r3, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
8003c6c: f7fd ff6e bl 8001b4c <HAL_GetTick>
8003c70: 0003 movs r3, r0
8003c72: 613b str r3, [r7, #16]
while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
8003c74: e008 b.n 8003c88 <HAL_RCC_OscConfig+0x3c0>
{
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8003c76: f7fd ff69 bl 8001b4c <HAL_GetTick>
8003c7a: 0002 movs r2, r0
8003c7c: 693b ldr r3, [r7, #16]
8003c7e: 1ad3 subs r3, r2, r3
8003c80: 2b02 cmp r3, #2
8003c82: d901 bls.n 8003c88 <HAL_RCC_OscConfig+0x3c0>
{
return HAL_TIMEOUT;
8003c84: 2303 movs r3, #3
8003c86: e127 b.n 8003ed8 <HAL_RCC_OscConfig+0x610>
while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
8003c88: 4b96 ldr r3, [pc, #600] ; (8003ee4 <HAL_RCC_OscConfig+0x61c>)
8003c8a: 681a ldr r2, [r3, #0]
8003c8c: 2380 movs r3, #128 ; 0x80
8003c8e: 005b lsls r3, r3, #1
8003c90: 4013 ands r3, r2
8003c92: d0f0 beq.n 8003c76 <HAL_RCC_OscConfig+0x3ae>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
8003c94: 687b ldr r3, [r7, #4]
8003c96: 689b ldr r3, [r3, #8]
8003c98: 2b01 cmp r3, #1
8003c9a: d106 bne.n 8003caa <HAL_RCC_OscConfig+0x3e2>
8003c9c: 4b90 ldr r3, [pc, #576] ; (8003ee0 <HAL_RCC_OscConfig+0x618>)
8003c9e: 6dda ldr r2, [r3, #92] ; 0x5c
8003ca0: 4b8f ldr r3, [pc, #572] ; (8003ee0 <HAL_RCC_OscConfig+0x618>)
8003ca2: 2101 movs r1, #1
8003ca4: 430a orrs r2, r1
8003ca6: 65da str r2, [r3, #92] ; 0x5c
8003ca8: e01c b.n 8003ce4 <HAL_RCC_OscConfig+0x41c>
8003caa: 687b ldr r3, [r7, #4]
8003cac: 689b ldr r3, [r3, #8]
8003cae: 2b05 cmp r3, #5
8003cb0: d10c bne.n 8003ccc <HAL_RCC_OscConfig+0x404>
8003cb2: 4b8b ldr r3, [pc, #556] ; (8003ee0 <HAL_RCC_OscConfig+0x618>)
8003cb4: 6dda ldr r2, [r3, #92] ; 0x5c
8003cb6: 4b8a ldr r3, [pc, #552] ; (8003ee0 <HAL_RCC_OscConfig+0x618>)
8003cb8: 2104 movs r1, #4
8003cba: 430a orrs r2, r1
8003cbc: 65da str r2, [r3, #92] ; 0x5c
8003cbe: 4b88 ldr r3, [pc, #544] ; (8003ee0 <HAL_RCC_OscConfig+0x618>)
8003cc0: 6dda ldr r2, [r3, #92] ; 0x5c
8003cc2: 4b87 ldr r3, [pc, #540] ; (8003ee0 <HAL_RCC_OscConfig+0x618>)
8003cc4: 2101 movs r1, #1
8003cc6: 430a orrs r2, r1
8003cc8: 65da str r2, [r3, #92] ; 0x5c
8003cca: e00b b.n 8003ce4 <HAL_RCC_OscConfig+0x41c>
8003ccc: 4b84 ldr r3, [pc, #528] ; (8003ee0 <HAL_RCC_OscConfig+0x618>)
8003cce: 6dda ldr r2, [r3, #92] ; 0x5c
8003cd0: 4b83 ldr r3, [pc, #524] ; (8003ee0 <HAL_RCC_OscConfig+0x618>)
8003cd2: 2101 movs r1, #1
8003cd4: 438a bics r2, r1
8003cd6: 65da str r2, [r3, #92] ; 0x5c
8003cd8: 4b81 ldr r3, [pc, #516] ; (8003ee0 <HAL_RCC_OscConfig+0x618>)
8003cda: 6dda ldr r2, [r3, #92] ; 0x5c
8003cdc: 4b80 ldr r3, [pc, #512] ; (8003ee0 <HAL_RCC_OscConfig+0x618>)
8003cde: 2104 movs r1, #4
8003ce0: 438a bics r2, r1
8003ce2: 65da str r2, [r3, #92] ; 0x5c
/* Check the LSE State */
if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
8003ce4: 687b ldr r3, [r7, #4]
8003ce6: 689b ldr r3, [r3, #8]
8003ce8: 2b00 cmp r3, #0
8003cea: d014 beq.n 8003d16 <HAL_RCC_OscConfig+0x44e>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003cec: f7fd ff2e bl 8001b4c <HAL_GetTick>
8003cf0: 0003 movs r3, r0
8003cf2: 613b str r3, [r7, #16]
/* Wait till LSE is ready */
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
8003cf4: e009 b.n 8003d0a <HAL_RCC_OscConfig+0x442>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8003cf6: f7fd ff29 bl 8001b4c <HAL_GetTick>
8003cfa: 0002 movs r2, r0
8003cfc: 693b ldr r3, [r7, #16]
8003cfe: 1ad3 subs r3, r2, r3
8003d00: 4a79 ldr r2, [pc, #484] ; (8003ee8 <HAL_RCC_OscConfig+0x620>)
8003d02: 4293 cmp r3, r2
8003d04: d901 bls.n 8003d0a <HAL_RCC_OscConfig+0x442>
{
return HAL_TIMEOUT;
8003d06: 2303 movs r3, #3
8003d08: e0e6 b.n 8003ed8 <HAL_RCC_OscConfig+0x610>
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
8003d0a: 4b75 ldr r3, [pc, #468] ; (8003ee0 <HAL_RCC_OscConfig+0x618>)
8003d0c: 6ddb ldr r3, [r3, #92] ; 0x5c
8003d0e: 2202 movs r2, #2
8003d10: 4013 ands r3, r2
8003d12: d0f0 beq.n 8003cf6 <HAL_RCC_OscConfig+0x42e>
8003d14: e013 b.n 8003d3e <HAL_RCC_OscConfig+0x476>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003d16: f7fd ff19 bl 8001b4c <HAL_GetTick>
8003d1a: 0003 movs r3, r0
8003d1c: 613b str r3, [r7, #16]
/* Wait till LSE is disabled */
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
8003d1e: e009 b.n 8003d34 <HAL_RCC_OscConfig+0x46c>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8003d20: f7fd ff14 bl 8001b4c <HAL_GetTick>
8003d24: 0002 movs r2, r0
8003d26: 693b ldr r3, [r7, #16]
8003d28: 1ad3 subs r3, r2, r3
8003d2a: 4a6f ldr r2, [pc, #444] ; (8003ee8 <HAL_RCC_OscConfig+0x620>)
8003d2c: 4293 cmp r3, r2
8003d2e: d901 bls.n 8003d34 <HAL_RCC_OscConfig+0x46c>
{
return HAL_TIMEOUT;
8003d30: 2303 movs r3, #3
8003d32: e0d1 b.n 8003ed8 <HAL_RCC_OscConfig+0x610>
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
8003d34: 4b6a ldr r3, [pc, #424] ; (8003ee0 <HAL_RCC_OscConfig+0x618>)
8003d36: 6ddb ldr r3, [r3, #92] ; 0x5c
8003d38: 2202 movs r2, #2
8003d3a: 4013 ands r3, r2
8003d3c: d1f0 bne.n 8003d20 <HAL_RCC_OscConfig+0x458>
}
}
}
/* Restore clock configuration if changed */
if (pwrclkchanged == SET)
8003d3e: 231f movs r3, #31
8003d40: 18fb adds r3, r7, r3
8003d42: 781b ldrb r3, [r3, #0]
8003d44: 2b01 cmp r3, #1
8003d46: d105 bne.n 8003d54 <HAL_RCC_OscConfig+0x48c>
{
__HAL_RCC_PWR_CLK_DISABLE();
8003d48: 4b65 ldr r3, [pc, #404] ; (8003ee0 <HAL_RCC_OscConfig+0x618>)
8003d4a: 6bda ldr r2, [r3, #60] ; 0x3c
8003d4c: 4b64 ldr r3, [pc, #400] ; (8003ee0 <HAL_RCC_OscConfig+0x618>)
8003d4e: 4967 ldr r1, [pc, #412] ; (8003eec <HAL_RCC_OscConfig+0x624>)
8003d50: 400a ands r2, r1
8003d52: 63da str r2, [r3, #60] ; 0x3c
#endif /* RCC_HSI48_SUPPORT */
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE)
8003d54: 687b ldr r3, [r7, #4]
8003d56: 69db ldr r3, [r3, #28]
8003d58: 2b00 cmp r3, #0
8003d5a: d100 bne.n 8003d5e <HAL_RCC_OscConfig+0x496>
8003d5c: e0bb b.n 8003ed6 <HAL_RCC_OscConfig+0x60e>
{
/* Check if the PLL is used as system clock or not */
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
8003d5e: 4b60 ldr r3, [pc, #384] ; (8003ee0 <HAL_RCC_OscConfig+0x618>)
8003d60: 689b ldr r3, [r3, #8]
8003d62: 2238 movs r2, #56 ; 0x38
8003d64: 4013 ands r3, r2
8003d66: 2b10 cmp r3, #16
8003d68: d100 bne.n 8003d6c <HAL_RCC_OscConfig+0x4a4>
8003d6a: e07b b.n 8003e64 <HAL_RCC_OscConfig+0x59c>
{
if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON)
8003d6c: 687b ldr r3, [r7, #4]
8003d6e: 69db ldr r3, [r3, #28]
8003d70: 2b02 cmp r3, #2
8003d72: d156 bne.n 8003e22 <HAL_RCC_OscConfig+0x55a>
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
#endif /* RCC_PLLQ_SUPPORT */
assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8003d74: 4b5a ldr r3, [pc, #360] ; (8003ee0 <HAL_RCC_OscConfig+0x618>)
8003d76: 681a ldr r2, [r3, #0]
8003d78: 4b59 ldr r3, [pc, #356] ; (8003ee0 <HAL_RCC_OscConfig+0x618>)
8003d7a: 495d ldr r1, [pc, #372] ; (8003ef0 <HAL_RCC_OscConfig+0x628>)
8003d7c: 400a ands r2, r1
8003d7e: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003d80: f7fd fee4 bl 8001b4c <HAL_GetTick>
8003d84: 0003 movs r3, r0
8003d86: 613b str r3, [r7, #16]
/* Wait till PLL is ready */
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
8003d88: e008 b.n 8003d9c <HAL_RCC_OscConfig+0x4d4>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8003d8a: f7fd fedf bl 8001b4c <HAL_GetTick>
8003d8e: 0002 movs r2, r0
8003d90: 693b ldr r3, [r7, #16]
8003d92: 1ad3 subs r3, r2, r3
8003d94: 2b02 cmp r3, #2
8003d96: d901 bls.n 8003d9c <HAL_RCC_OscConfig+0x4d4>
{
return HAL_TIMEOUT;
8003d98: 2303 movs r3, #3
8003d9a: e09d b.n 8003ed8 <HAL_RCC_OscConfig+0x610>
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
8003d9c: 4b50 ldr r3, [pc, #320] ; (8003ee0 <HAL_RCC_OscConfig+0x618>)
8003d9e: 681a ldr r2, [r3, #0]
8003da0: 2380 movs r3, #128 ; 0x80
8003da2: 049b lsls r3, r3, #18
8003da4: 4013 ands r3, r2
8003da6: d1f0 bne.n 8003d8a <HAL_RCC_OscConfig+0x4c2>
}
}
/* Configure the main PLL clock source, multiplication and division factors. */
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
8003da8: 4b4d ldr r3, [pc, #308] ; (8003ee0 <HAL_RCC_OscConfig+0x618>)
8003daa: 68db ldr r3, [r3, #12]
8003dac: 4a51 ldr r2, [pc, #324] ; (8003ef4 <HAL_RCC_OscConfig+0x62c>)
8003dae: 4013 ands r3, r2
8003db0: 0019 movs r1, r3
8003db2: 687b ldr r3, [r7, #4]
8003db4: 6a1a ldr r2, [r3, #32]
8003db6: 687b ldr r3, [r7, #4]
8003db8: 6a5b ldr r3, [r3, #36] ; 0x24
8003dba: 431a orrs r2, r3
8003dbc: 687b ldr r3, [r7, #4]
8003dbe: 6a9b ldr r3, [r3, #40] ; 0x28
8003dc0: 021b lsls r3, r3, #8
8003dc2: 431a orrs r2, r3
8003dc4: 687b ldr r3, [r7, #4]
8003dc6: 6adb ldr r3, [r3, #44] ; 0x2c
8003dc8: 431a orrs r2, r3
8003dca: 687b ldr r3, [r7, #4]
8003dcc: 6b1b ldr r3, [r3, #48] ; 0x30
8003dce: 431a orrs r2, r3
8003dd0: 687b ldr r3, [r7, #4]
8003dd2: 6b5b ldr r3, [r3, #52] ; 0x34
8003dd4: 431a orrs r2, r3
8003dd6: 4b42 ldr r3, [pc, #264] ; (8003ee0 <HAL_RCC_OscConfig+0x618>)
8003dd8: 430a orrs r2, r1
8003dda: 60da str r2, [r3, #12]
RCC_OscInitStruct->PLL.PLLQ,
#endif /* RCC_PLLQ_SUPPORT */
RCC_OscInitStruct->PLL.PLLR);
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
8003ddc: 4b40 ldr r3, [pc, #256] ; (8003ee0 <HAL_RCC_OscConfig+0x618>)
8003dde: 681a ldr r2, [r3, #0]
8003de0: 4b3f ldr r3, [pc, #252] ; (8003ee0 <HAL_RCC_OscConfig+0x618>)
8003de2: 2180 movs r1, #128 ; 0x80
8003de4: 0449 lsls r1, r1, #17
8003de6: 430a orrs r2, r1
8003de8: 601a str r2, [r3, #0]
/* Enable PLLR Clock output. */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLRCLK);
8003dea: 4b3d ldr r3, [pc, #244] ; (8003ee0 <HAL_RCC_OscConfig+0x618>)
8003dec: 68da ldr r2, [r3, #12]
8003dee: 4b3c ldr r3, [pc, #240] ; (8003ee0 <HAL_RCC_OscConfig+0x618>)
8003df0: 2180 movs r1, #128 ; 0x80
8003df2: 0549 lsls r1, r1, #21
8003df4: 430a orrs r2, r1
8003df6: 60da str r2, [r3, #12]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003df8: f7fd fea8 bl 8001b4c <HAL_GetTick>
8003dfc: 0003 movs r3, r0
8003dfe: 613b str r3, [r7, #16]
/* Wait till PLL is ready */
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
8003e00: e008 b.n 8003e14 <HAL_RCC_OscConfig+0x54c>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8003e02: f7fd fea3 bl 8001b4c <HAL_GetTick>
8003e06: 0002 movs r2, r0
8003e08: 693b ldr r3, [r7, #16]
8003e0a: 1ad3 subs r3, r2, r3
8003e0c: 2b02 cmp r3, #2
8003e0e: d901 bls.n 8003e14 <HAL_RCC_OscConfig+0x54c>
{
return HAL_TIMEOUT;
8003e10: 2303 movs r3, #3
8003e12: e061 b.n 8003ed8 <HAL_RCC_OscConfig+0x610>
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
8003e14: 4b32 ldr r3, [pc, #200] ; (8003ee0 <HAL_RCC_OscConfig+0x618>)
8003e16: 681a ldr r2, [r3, #0]
8003e18: 2380 movs r3, #128 ; 0x80
8003e1a: 049b lsls r3, r3, #18
8003e1c: 4013 ands r3, r2
8003e1e: d0f0 beq.n 8003e02 <HAL_RCC_OscConfig+0x53a>
8003e20: e059 b.n 8003ed6 <HAL_RCC_OscConfig+0x60e>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8003e22: 4b2f ldr r3, [pc, #188] ; (8003ee0 <HAL_RCC_OscConfig+0x618>)
8003e24: 681a ldr r2, [r3, #0]
8003e26: 4b2e ldr r3, [pc, #184] ; (8003ee0 <HAL_RCC_OscConfig+0x618>)
8003e28: 4931 ldr r1, [pc, #196] ; (8003ef0 <HAL_RCC_OscConfig+0x628>)
8003e2a: 400a ands r2, r1
8003e2c: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003e2e: f7fd fe8d bl 8001b4c <HAL_GetTick>
8003e32: 0003 movs r3, r0
8003e34: 613b str r3, [r7, #16]
/* Wait till PLL is disabled */
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
8003e36: e008 b.n 8003e4a <HAL_RCC_OscConfig+0x582>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8003e38: f7fd fe88 bl 8001b4c <HAL_GetTick>
8003e3c: 0002 movs r2, r0
8003e3e: 693b ldr r3, [r7, #16]
8003e40: 1ad3 subs r3, r2, r3
8003e42: 2b02 cmp r3, #2
8003e44: d901 bls.n 8003e4a <HAL_RCC_OscConfig+0x582>
{
return HAL_TIMEOUT;
8003e46: 2303 movs r3, #3
8003e48: e046 b.n 8003ed8 <HAL_RCC_OscConfig+0x610>
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
8003e4a: 4b25 ldr r3, [pc, #148] ; (8003ee0 <HAL_RCC_OscConfig+0x618>)
8003e4c: 681a ldr r2, [r3, #0]
8003e4e: 2380 movs r3, #128 ; 0x80
8003e50: 049b lsls r3, r3, #18
8003e52: 4013 ands r3, r2
8003e54: d1f0 bne.n 8003e38 <HAL_RCC_OscConfig+0x570>
}
}
/* Unselect main PLL clock source and disable main PLL outputs to save power */
#if defined(RCC_PLLQ_SUPPORT)
RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLPEN | RCC_PLLCFGR_PLLQEN | RCC_PLLCFGR_PLLREN);
8003e56: 4b22 ldr r3, [pc, #136] ; (8003ee0 <HAL_RCC_OscConfig+0x618>)
8003e58: 68da ldr r2, [r3, #12]
8003e5a: 4b21 ldr r3, [pc, #132] ; (8003ee0 <HAL_RCC_OscConfig+0x618>)
8003e5c: 4926 ldr r1, [pc, #152] ; (8003ef8 <HAL_RCC_OscConfig+0x630>)
8003e5e: 400a ands r2, r1
8003e60: 60da str r2, [r3, #12]
8003e62: e038 b.n 8003ed6 <HAL_RCC_OscConfig+0x60e>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
8003e64: 687b ldr r3, [r7, #4]
8003e66: 69db ldr r3, [r3, #28]
8003e68: 2b01 cmp r3, #1
8003e6a: d101 bne.n 8003e70 <HAL_RCC_OscConfig+0x5a8>
{
return HAL_ERROR;
8003e6c: 2301 movs r3, #1
8003e6e: e033 b.n 8003ed8 <HAL_RCC_OscConfig+0x610>
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
temp_pllckcfg = RCC->PLLCFGR;
8003e70: 4b1b ldr r3, [pc, #108] ; (8003ee0 <HAL_RCC_OscConfig+0x618>)
8003e72: 68db ldr r3, [r3, #12]
8003e74: 617b str r3, [r7, #20]
if ((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8003e76: 697b ldr r3, [r7, #20]
8003e78: 2203 movs r2, #3
8003e7a: 401a ands r2, r3
8003e7c: 687b ldr r3, [r7, #4]
8003e7e: 6a1b ldr r3, [r3, #32]
8003e80: 429a cmp r2, r3
8003e82: d126 bne.n 8003ed2 <HAL_RCC_OscConfig+0x60a>
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
8003e84: 697b ldr r3, [r7, #20]
8003e86: 2270 movs r2, #112 ; 0x70
8003e88: 401a ands r2, r3
8003e8a: 687b ldr r3, [r7, #4]
8003e8c: 6a5b ldr r3, [r3, #36] ; 0x24
if ((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8003e8e: 429a cmp r2, r3
8003e90: d11f bne.n 8003ed2 <HAL_RCC_OscConfig+0x60a>
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
8003e92: 697a ldr r2, [r7, #20]
8003e94: 23fe movs r3, #254 ; 0xfe
8003e96: 01db lsls r3, r3, #7
8003e98: 401a ands r2, r3
8003e9a: 687b ldr r3, [r7, #4]
8003e9c: 6a9b ldr r3, [r3, #40] ; 0x28
8003e9e: 021b lsls r3, r3, #8
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
8003ea0: 429a cmp r2, r3
8003ea2: d116 bne.n 8003ed2 <HAL_RCC_OscConfig+0x60a>
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) ||
8003ea4: 697a ldr r2, [r7, #20]
8003ea6: 23f8 movs r3, #248 ; 0xf8
8003ea8: 039b lsls r3, r3, #14
8003eaa: 401a ands r2, r3
8003eac: 687b ldr r3, [r7, #4]
8003eae: 6adb ldr r3, [r3, #44] ; 0x2c
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
8003eb0: 429a cmp r2, r3
8003eb2: d10e bne.n 8003ed2 <HAL_RCC_OscConfig+0x60a>
#if defined (RCC_PLLQ_SUPPORT)
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ) ||
8003eb4: 697a ldr r2, [r7, #20]
8003eb6: 23e0 movs r3, #224 ; 0xe0
8003eb8: 051b lsls r3, r3, #20
8003eba: 401a ands r2, r3
8003ebc: 687b ldr r3, [r7, #4]
8003ebe: 6b1b ldr r3, [r3, #48] ; 0x30
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) ||
8003ec0: 429a cmp r2, r3
8003ec2: d106 bne.n 8003ed2 <HAL_RCC_OscConfig+0x60a>
#endif /* RCC_PLLQ_SUPPORT */
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLR) != RCC_OscInitStruct->PLL.PLLR))
8003ec4: 697b ldr r3, [r7, #20]
8003ec6: 0f5b lsrs r3, r3, #29
8003ec8: 075a lsls r2, r3, #29
8003eca: 687b ldr r3, [r7, #4]
8003ecc: 6b5b ldr r3, [r3, #52] ; 0x34
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ) ||
8003ece: 429a cmp r2, r3
8003ed0: d001 beq.n 8003ed6 <HAL_RCC_OscConfig+0x60e>
{
return HAL_ERROR;
8003ed2: 2301 movs r3, #1
8003ed4: e000 b.n 8003ed8 <HAL_RCC_OscConfig+0x610>
}
}
}
}
return HAL_OK;
8003ed6: 2300 movs r3, #0
}
8003ed8: 0018 movs r0, r3
8003eda: 46bd mov sp, r7
8003edc: b008 add sp, #32
8003ede: bd80 pop {r7, pc}
8003ee0: 40021000 .word 0x40021000
8003ee4: 40007000 .word 0x40007000
8003ee8: 00001388 .word 0x00001388
8003eec: efffffff .word 0xefffffff
8003ef0: feffffff .word 0xfeffffff
8003ef4: 11c1808c .word 0x11c1808c
8003ef8: eefefffc .word 0xeefefffc
08003efc <HAL_RCC_ClockConfig>:
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
* (for more details refer to section above "Initialization/de-initialization functions")
* @retval None
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
8003efc: b580 push {r7, lr}
8003efe: b084 sub sp, #16
8003f00: af00 add r7, sp, #0
8003f02: 6078 str r0, [r7, #4]
8003f04: 6039 str r1, [r7, #0]
uint32_t tickstart;
/* Check Null pointer */
if (RCC_ClkInitStruct == NULL)
8003f06: 687b ldr r3, [r7, #4]
8003f08: 2b00 cmp r3, #0
8003f0a: d101 bne.n 8003f10 <HAL_RCC_ClockConfig+0x14>
{
return HAL_ERROR;
8003f0c: 2301 movs r3, #1
8003f0e: e0e9 b.n 80040e4 <HAL_RCC_ClockConfig+0x1e8>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the FLASH clock
(HCLK) and the supply voltage of the device. */
/* Increasing the number of wait states because of higher CPU frequency */
if (FLatency > __HAL_FLASH_GET_LATENCY())
8003f10: 4b76 ldr r3, [pc, #472] ; (80040ec <HAL_RCC_ClockConfig+0x1f0>)
8003f12: 681b ldr r3, [r3, #0]
8003f14: 2207 movs r2, #7
8003f16: 4013 ands r3, r2
8003f18: 683a ldr r2, [r7, #0]
8003f1a: 429a cmp r2, r3
8003f1c: d91e bls.n 8003f5c <HAL_RCC_ClockConfig+0x60>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8003f1e: 4b73 ldr r3, [pc, #460] ; (80040ec <HAL_RCC_ClockConfig+0x1f0>)
8003f20: 681b ldr r3, [r3, #0]
8003f22: 2207 movs r2, #7
8003f24: 4393 bics r3, r2
8003f26: 0019 movs r1, r3
8003f28: 4b70 ldr r3, [pc, #448] ; (80040ec <HAL_RCC_ClockConfig+0x1f0>)
8003f2a: 683a ldr r2, [r7, #0]
8003f2c: 430a orrs r2, r1
8003f2e: 601a str r2, [r3, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by polling the FLASH_ACR register */
tickstart = HAL_GetTick();
8003f30: f7fd fe0c bl 8001b4c <HAL_GetTick>
8003f34: 0003 movs r3, r0
8003f36: 60fb str r3, [r7, #12]
while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
8003f38: e009 b.n 8003f4e <HAL_RCC_ClockConfig+0x52>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
8003f3a: f7fd fe07 bl 8001b4c <HAL_GetTick>
8003f3e: 0002 movs r2, r0
8003f40: 68fb ldr r3, [r7, #12]
8003f42: 1ad3 subs r3, r2, r3
8003f44: 4a6a ldr r2, [pc, #424] ; (80040f0 <HAL_RCC_ClockConfig+0x1f4>)
8003f46: 4293 cmp r3, r2
8003f48: d901 bls.n 8003f4e <HAL_RCC_ClockConfig+0x52>
{
return HAL_TIMEOUT;
8003f4a: 2303 movs r3, #3
8003f4c: e0ca b.n 80040e4 <HAL_RCC_ClockConfig+0x1e8>
while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
8003f4e: 4b67 ldr r3, [pc, #412] ; (80040ec <HAL_RCC_ClockConfig+0x1f0>)
8003f50: 681b ldr r3, [r3, #0]
8003f52: 2207 movs r2, #7
8003f54: 4013 ands r3, r2
8003f56: 683a ldr r2, [r7, #0]
8003f58: 429a cmp r2, r3
8003f5a: d1ee bne.n 8003f3a <HAL_RCC_ClockConfig+0x3e>
}
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
8003f5c: 687b ldr r3, [r7, #4]
8003f5e: 681b ldr r3, [r3, #0]
8003f60: 2202 movs r2, #2
8003f62: 4013 ands r3, r2
8003f64: d015 beq.n 8003f92 <HAL_RCC_ClockConfig+0x96>
{
/* Set the highest APB divider in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8003f66: 687b ldr r3, [r7, #4]
8003f68: 681b ldr r3, [r3, #0]
8003f6a: 2204 movs r2, #4
8003f6c: 4013 ands r3, r2
8003f6e: d006 beq.n 8003f7e <HAL_RCC_ClockConfig+0x82>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_HCLK_DIV16);
8003f70: 4b60 ldr r3, [pc, #384] ; (80040f4 <HAL_RCC_ClockConfig+0x1f8>)
8003f72: 689a ldr r2, [r3, #8]
8003f74: 4b5f ldr r3, [pc, #380] ; (80040f4 <HAL_RCC_ClockConfig+0x1f8>)
8003f76: 21e0 movs r1, #224 ; 0xe0
8003f78: 01c9 lsls r1, r1, #7
8003f7a: 430a orrs r2, r1
8003f7c: 609a str r2, [r3, #8]
}
/* Set the new HCLK clock divider */
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8003f7e: 4b5d ldr r3, [pc, #372] ; (80040f4 <HAL_RCC_ClockConfig+0x1f8>)
8003f80: 689b ldr r3, [r3, #8]
8003f82: 4a5d ldr r2, [pc, #372] ; (80040f8 <HAL_RCC_ClockConfig+0x1fc>)
8003f84: 4013 ands r3, r2
8003f86: 0019 movs r1, r3
8003f88: 687b ldr r3, [r7, #4]
8003f8a: 689a ldr r2, [r3, #8]
8003f8c: 4b59 ldr r3, [pc, #356] ; (80040f4 <HAL_RCC_ClockConfig+0x1f8>)
8003f8e: 430a orrs r2, r1
8003f90: 609a str r2, [r3, #8]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
8003f92: 687b ldr r3, [r7, #4]
8003f94: 681b ldr r3, [r3, #0]
8003f96: 2201 movs r2, #1
8003f98: 4013 ands r3, r2
8003f9a: d057 beq.n 800404c <HAL_RCC_ClockConfig+0x150>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
8003f9c: 687b ldr r3, [r7, #4]
8003f9e: 685b ldr r3, [r3, #4]
8003fa0: 2b01 cmp r3, #1
8003fa2: d107 bne.n 8003fb4 <HAL_RCC_ClockConfig+0xb8>
{
/* Check the HSE ready flag */
if (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
8003fa4: 4b53 ldr r3, [pc, #332] ; (80040f4 <HAL_RCC_ClockConfig+0x1f8>)
8003fa6: 681a ldr r2, [r3, #0]
8003fa8: 2380 movs r3, #128 ; 0x80
8003faa: 029b lsls r3, r3, #10
8003fac: 4013 ands r3, r2
8003fae: d12b bne.n 8004008 <HAL_RCC_ClockConfig+0x10c>
{
return HAL_ERROR;
8003fb0: 2301 movs r3, #1
8003fb2: e097 b.n 80040e4 <HAL_RCC_ClockConfig+0x1e8>
}
}
/* PLL is selected as System Clock Source */
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
8003fb4: 687b ldr r3, [r7, #4]
8003fb6: 685b ldr r3, [r3, #4]
8003fb8: 2b02 cmp r3, #2
8003fba: d107 bne.n 8003fcc <HAL_RCC_ClockConfig+0xd0>
{
/* Check the PLL ready flag */
if (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
8003fbc: 4b4d ldr r3, [pc, #308] ; (80040f4 <HAL_RCC_ClockConfig+0x1f8>)
8003fbe: 681a ldr r2, [r3, #0]
8003fc0: 2380 movs r3, #128 ; 0x80
8003fc2: 049b lsls r3, r3, #18
8003fc4: 4013 ands r3, r2
8003fc6: d11f bne.n 8004008 <HAL_RCC_ClockConfig+0x10c>
{
return HAL_ERROR;
8003fc8: 2301 movs r3, #1
8003fca: e08b b.n 80040e4 <HAL_RCC_ClockConfig+0x1e8>
}
}
/* HSI is selected as System Clock Source */
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)
8003fcc: 687b ldr r3, [r7, #4]
8003fce: 685b ldr r3, [r3, #4]
8003fd0: 2b00 cmp r3, #0
8003fd2: d107 bne.n 8003fe4 <HAL_RCC_ClockConfig+0xe8>
{
/* Check the HSI ready flag */
if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
8003fd4: 4b47 ldr r3, [pc, #284] ; (80040f4 <HAL_RCC_ClockConfig+0x1f8>)
8003fd6: 681a ldr r2, [r3, #0]
8003fd8: 2380 movs r3, #128 ; 0x80
8003fda: 00db lsls r3, r3, #3
8003fdc: 4013 ands r3, r2
8003fde: d113 bne.n 8004008 <HAL_RCC_ClockConfig+0x10c>
{
return HAL_ERROR;
8003fe0: 2301 movs r3, #1
8003fe2: e07f b.n 80040e4 <HAL_RCC_ClockConfig+0x1e8>
}
}
/* LSI is selected as System Clock Source */
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_LSI)
8003fe4: 687b ldr r3, [r7, #4]
8003fe6: 685b ldr r3, [r3, #4]
8003fe8: 2b03 cmp r3, #3
8003fea: d106 bne.n 8003ffa <HAL_RCC_ClockConfig+0xfe>
{
/* Check the LSI ready flag */
if (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
8003fec: 4b41 ldr r3, [pc, #260] ; (80040f4 <HAL_RCC_ClockConfig+0x1f8>)
8003fee: 6e1b ldr r3, [r3, #96] ; 0x60
8003ff0: 2202 movs r2, #2
8003ff2: 4013 ands r3, r2
8003ff4: d108 bne.n 8004008 <HAL_RCC_ClockConfig+0x10c>
{
return HAL_ERROR;
8003ff6: 2301 movs r3, #1
8003ff8: e074 b.n 80040e4 <HAL_RCC_ClockConfig+0x1e8>
}
/* LSE is selected as System Clock Source */
else
{
/* Check the LSE ready flag */
if (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
8003ffa: 4b3e ldr r3, [pc, #248] ; (80040f4 <HAL_RCC_ClockConfig+0x1f8>)
8003ffc: 6ddb ldr r3, [r3, #92] ; 0x5c
8003ffe: 2202 movs r2, #2
8004000: 4013 ands r3, r2
8004002: d101 bne.n 8004008 <HAL_RCC_ClockConfig+0x10c>
{
return HAL_ERROR;
8004004: 2301 movs r3, #1
8004006: e06d b.n 80040e4 <HAL_RCC_ClockConfig+0x1e8>
}
}
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
8004008: 4b3a ldr r3, [pc, #232] ; (80040f4 <HAL_RCC_ClockConfig+0x1f8>)
800400a: 689b ldr r3, [r3, #8]
800400c: 2207 movs r2, #7
800400e: 4393 bics r3, r2
8004010: 0019 movs r1, r3
8004012: 687b ldr r3, [r7, #4]
8004014: 685a ldr r2, [r3, #4]
8004016: 4b37 ldr r3, [pc, #220] ; (80040f4 <HAL_RCC_ClockConfig+0x1f8>)
8004018: 430a orrs r2, r1
800401a: 609a str r2, [r3, #8]
/* Get Start Tick*/
tickstart = HAL_GetTick();
800401c: f7fd fd96 bl 8001b4c <HAL_GetTick>
8004020: 0003 movs r3, r0
8004022: 60fb str r3, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8004024: e009 b.n 800403a <HAL_RCC_ClockConfig+0x13e>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
8004026: f7fd fd91 bl 8001b4c <HAL_GetTick>
800402a: 0002 movs r2, r0
800402c: 68fb ldr r3, [r7, #12]
800402e: 1ad3 subs r3, r2, r3
8004030: 4a2f ldr r2, [pc, #188] ; (80040f0 <HAL_RCC_ClockConfig+0x1f4>)
8004032: 4293 cmp r3, r2
8004034: d901 bls.n 800403a <HAL_RCC_ClockConfig+0x13e>
{
return HAL_TIMEOUT;
8004036: 2303 movs r3, #3
8004038: e054 b.n 80040e4 <HAL_RCC_ClockConfig+0x1e8>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
800403a: 4b2e ldr r3, [pc, #184] ; (80040f4 <HAL_RCC_ClockConfig+0x1f8>)
800403c: 689b ldr r3, [r3, #8]
800403e: 2238 movs r2, #56 ; 0x38
8004040: 401a ands r2, r3
8004042: 687b ldr r3, [r7, #4]
8004044: 685b ldr r3, [r3, #4]
8004046: 00db lsls r3, r3, #3
8004048: 429a cmp r2, r3
800404a: d1ec bne.n 8004026 <HAL_RCC_ClockConfig+0x12a>
}
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if (FLatency < __HAL_FLASH_GET_LATENCY())
800404c: 4b27 ldr r3, [pc, #156] ; (80040ec <HAL_RCC_ClockConfig+0x1f0>)
800404e: 681b ldr r3, [r3, #0]
8004050: 2207 movs r2, #7
8004052: 4013 ands r3, r2
8004054: 683a ldr r2, [r7, #0]
8004056: 429a cmp r2, r3
8004058: d21e bcs.n 8004098 <HAL_RCC_ClockConfig+0x19c>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
800405a: 4b24 ldr r3, [pc, #144] ; (80040ec <HAL_RCC_ClockConfig+0x1f0>)
800405c: 681b ldr r3, [r3, #0]
800405e: 2207 movs r2, #7
8004060: 4393 bics r3, r2
8004062: 0019 movs r1, r3
8004064: 4b21 ldr r3, [pc, #132] ; (80040ec <HAL_RCC_ClockConfig+0x1f0>)
8004066: 683a ldr r2, [r7, #0]
8004068: 430a orrs r2, r1
800406a: 601a str r2, [r3, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by polling the FLASH_ACR register */
tickstart = HAL_GetTick();
800406c: f7fd fd6e bl 8001b4c <HAL_GetTick>
8004070: 0003 movs r3, r0
8004072: 60fb str r3, [r7, #12]
while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
8004074: e009 b.n 800408a <HAL_RCC_ClockConfig+0x18e>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
8004076: f7fd fd69 bl 8001b4c <HAL_GetTick>
800407a: 0002 movs r2, r0
800407c: 68fb ldr r3, [r7, #12]
800407e: 1ad3 subs r3, r2, r3
8004080: 4a1b ldr r2, [pc, #108] ; (80040f0 <HAL_RCC_ClockConfig+0x1f4>)
8004082: 4293 cmp r3, r2
8004084: d901 bls.n 800408a <HAL_RCC_ClockConfig+0x18e>
{
return HAL_TIMEOUT;
8004086: 2303 movs r3, #3
8004088: e02c b.n 80040e4 <HAL_RCC_ClockConfig+0x1e8>
while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
800408a: 4b18 ldr r3, [pc, #96] ; (80040ec <HAL_RCC_ClockConfig+0x1f0>)
800408c: 681b ldr r3, [r3, #0]
800408e: 2207 movs r2, #7
8004090: 4013 ands r3, r2
8004092: 683a ldr r2, [r7, #0]
8004094: 429a cmp r2, r3
8004096: d1ee bne.n 8004076 <HAL_RCC_ClockConfig+0x17a>
}
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8004098: 687b ldr r3, [r7, #4]
800409a: 681b ldr r3, [r3, #0]
800409c: 2204 movs r2, #4
800409e: 4013 ands r3, r2
80040a0: d009 beq.n 80040b6 <HAL_RCC_ClockConfig+0x1ba>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider);
80040a2: 4b14 ldr r3, [pc, #80] ; (80040f4 <HAL_RCC_ClockConfig+0x1f8>)
80040a4: 689b ldr r3, [r3, #8]
80040a6: 4a15 ldr r2, [pc, #84] ; (80040fc <HAL_RCC_ClockConfig+0x200>)
80040a8: 4013 ands r3, r2
80040aa: 0019 movs r1, r3
80040ac: 687b ldr r3, [r7, #4]
80040ae: 68da ldr r2, [r3, #12]
80040b0: 4b10 ldr r3, [pc, #64] ; (80040f4 <HAL_RCC_ClockConfig+0x1f8>)
80040b2: 430a orrs r2, r1
80040b4: 609a str r2, [r3, #8]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]) & 0x1FU));
80040b6: f000 f829 bl 800410c <HAL_RCC_GetSysClockFreq>
80040ba: 0001 movs r1, r0
80040bc: 4b0d ldr r3, [pc, #52] ; (80040f4 <HAL_RCC_ClockConfig+0x1f8>)
80040be: 689b ldr r3, [r3, #8]
80040c0: 0a1b lsrs r3, r3, #8
80040c2: 220f movs r2, #15
80040c4: 401a ands r2, r3
80040c6: 4b0e ldr r3, [pc, #56] ; (8004100 <HAL_RCC_ClockConfig+0x204>)
80040c8: 0092 lsls r2, r2, #2
80040ca: 58d3 ldr r3, [r2, r3]
80040cc: 221f movs r2, #31
80040ce: 4013 ands r3, r2
80040d0: 000a movs r2, r1
80040d2: 40da lsrs r2, r3
80040d4: 4b0b ldr r3, [pc, #44] ; (8004104 <HAL_RCC_ClockConfig+0x208>)
80040d6: 601a str r2, [r3, #0]
/* Configure the source of time base considering new system clocks settings*/
return HAL_InitTick(uwTickPrio);
80040d8: 4b0b ldr r3, [pc, #44] ; (8004108 <HAL_RCC_ClockConfig+0x20c>)
80040da: 681b ldr r3, [r3, #0]
80040dc: 0018 movs r0, r3
80040de: f7fd fcd9 bl 8001a94 <HAL_InitTick>
80040e2: 0003 movs r3, r0
}
80040e4: 0018 movs r0, r3
80040e6: 46bd mov sp, r7
80040e8: b004 add sp, #16
80040ea: bd80 pop {r7, pc}
80040ec: 40022000 .word 0x40022000
80040f0: 00001388 .word 0x00001388
80040f4: 40021000 .word 0x40021000
80040f8: fffff0ff .word 0xfffff0ff
80040fc: ffff8fff .word 0xffff8fff
8004100: 080073d0 .word 0x080073d0
8004104: 2000000c .word 0x2000000c
8004108: 20000010 .word 0x20000010
0800410c <HAL_RCC_GetSysClockFreq>:
*
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
800410c: b580 push {r7, lr}
800410e: b086 sub sp, #24
8004110: af00 add r7, sp, #0
uint32_t pllvco, pllsource, pllr, pllm, hsidiv;
uint32_t sysclockfreq;
if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
8004112: 4b3c ldr r3, [pc, #240] ; (8004204 <HAL_RCC_GetSysClockFreq+0xf8>)
8004114: 689b ldr r3, [r3, #8]
8004116: 2238 movs r2, #56 ; 0x38
8004118: 4013 ands r3, r2
800411a: d10f bne.n 800413c <HAL_RCC_GetSysClockFreq+0x30>
{
/* HSISYS can be derived for HSI16 */
hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos));
800411c: 4b39 ldr r3, [pc, #228] ; (8004204 <HAL_RCC_GetSysClockFreq+0xf8>)
800411e: 681b ldr r3, [r3, #0]
8004120: 0adb lsrs r3, r3, #11
8004122: 2207 movs r2, #7
8004124: 4013 ands r3, r2
8004126: 2201 movs r2, #1
8004128: 409a lsls r2, r3
800412a: 0013 movs r3, r2
800412c: 603b str r3, [r7, #0]
/* HSI used as system clock source */
sysclockfreq = (HSI_VALUE / hsidiv);
800412e: 6839 ldr r1, [r7, #0]
8004130: 4835 ldr r0, [pc, #212] ; (8004208 <HAL_RCC_GetSysClockFreq+0xfc>)
8004132: f7fb ffe7 bl 8000104 <__udivsi3>
8004136: 0003 movs r3, r0
8004138: 613b str r3, [r7, #16]
800413a: e05d b.n 80041f8 <HAL_RCC_GetSysClockFreq+0xec>
}
else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
800413c: 4b31 ldr r3, [pc, #196] ; (8004204 <HAL_RCC_GetSysClockFreq+0xf8>)
800413e: 689b ldr r3, [r3, #8]
8004140: 2238 movs r2, #56 ; 0x38
8004142: 4013 ands r3, r2
8004144: 2b08 cmp r3, #8
8004146: d102 bne.n 800414e <HAL_RCC_GetSysClockFreq+0x42>
{
/* HSE used as system clock source */
sysclockfreq = HSE_VALUE;
8004148: 4b30 ldr r3, [pc, #192] ; (800420c <HAL_RCC_GetSysClockFreq+0x100>)
800414a: 613b str r3, [r7, #16]
800414c: e054 b.n 80041f8 <HAL_RCC_GetSysClockFreq+0xec>
}
else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK)
800414e: 4b2d ldr r3, [pc, #180] ; (8004204 <HAL_RCC_GetSysClockFreq+0xf8>)
8004150: 689b ldr r3, [r3, #8]
8004152: 2238 movs r2, #56 ; 0x38
8004154: 4013 ands r3, r2
8004156: 2b10 cmp r3, #16
8004158: d138 bne.n 80041cc <HAL_RCC_GetSysClockFreq+0xc0>
/* PLL used as system clock source */
/* PLL_VCO = ((HSE_VALUE or HSI_VALUE)/ PLLM) * PLLN
SYSCLK = PLL_VCO / PLLR
*/
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
800415a: 4b2a ldr r3, [pc, #168] ; (8004204 <HAL_RCC_GetSysClockFreq+0xf8>)
800415c: 68db ldr r3, [r3, #12]
800415e: 2203 movs r2, #3
8004160: 4013 ands r3, r2
8004162: 60fb str r3, [r7, #12]
pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
8004164: 4b27 ldr r3, [pc, #156] ; (8004204 <HAL_RCC_GetSysClockFreq+0xf8>)
8004166: 68db ldr r3, [r3, #12]
8004168: 091b lsrs r3, r3, #4
800416a: 2207 movs r2, #7
800416c: 4013 ands r3, r2
800416e: 3301 adds r3, #1
8004170: 60bb str r3, [r7, #8]
switch (pllsource)
8004172: 68fb ldr r3, [r7, #12]
8004174: 2b03 cmp r3, #3
8004176: d10d bne.n 8004194 <HAL_RCC_GetSysClockFreq+0x88>
{
case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
8004178: 68b9 ldr r1, [r7, #8]
800417a: 4824 ldr r0, [pc, #144] ; (800420c <HAL_RCC_GetSysClockFreq+0x100>)
800417c: f7fb ffc2 bl 8000104 <__udivsi3>
8004180: 0003 movs r3, r0
8004182: 0019 movs r1, r3
8004184: 4b1f ldr r3, [pc, #124] ; (8004204 <HAL_RCC_GetSysClockFreq+0xf8>)
8004186: 68db ldr r3, [r3, #12]
8004188: 0a1b lsrs r3, r3, #8
800418a: 227f movs r2, #127 ; 0x7f
800418c: 4013 ands r3, r2
800418e: 434b muls r3, r1
8004190: 617b str r3, [r7, #20]
break;
8004192: e00d b.n 80041b0 <HAL_RCC_GetSysClockFreq+0xa4>
case RCC_PLLSOURCE_HSI: /* HSI16 used as PLL clock source */
default: /* HSI16 used as PLL clock source */
pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos) ;
8004194: 68b9 ldr r1, [r7, #8]
8004196: 481c ldr r0, [pc, #112] ; (8004208 <HAL_RCC_GetSysClockFreq+0xfc>)
8004198: f7fb ffb4 bl 8000104 <__udivsi3>
800419c: 0003 movs r3, r0
800419e: 0019 movs r1, r3
80041a0: 4b18 ldr r3, [pc, #96] ; (8004204 <HAL_RCC_GetSysClockFreq+0xf8>)
80041a2: 68db ldr r3, [r3, #12]
80041a4: 0a1b lsrs r3, r3, #8
80041a6: 227f movs r2, #127 ; 0x7f
80041a8: 4013 ands r3, r2
80041aa: 434b muls r3, r1
80041ac: 617b str r3, [r7, #20]
break;
80041ae: 46c0 nop ; (mov r8, r8)
}
pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U);
80041b0: 4b14 ldr r3, [pc, #80] ; (8004204 <HAL_RCC_GetSysClockFreq+0xf8>)
80041b2: 68db ldr r3, [r3, #12]
80041b4: 0f5b lsrs r3, r3, #29
80041b6: 2207 movs r2, #7
80041b8: 4013 ands r3, r2
80041ba: 3301 adds r3, #1
80041bc: 607b str r3, [r7, #4]
sysclockfreq = pllvco / pllr;
80041be: 6879 ldr r1, [r7, #4]
80041c0: 6978 ldr r0, [r7, #20]
80041c2: f7fb ff9f bl 8000104 <__udivsi3>
80041c6: 0003 movs r3, r0
80041c8: 613b str r3, [r7, #16]
80041ca: e015 b.n 80041f8 <HAL_RCC_GetSysClockFreq+0xec>
}
else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSE)
80041cc: 4b0d ldr r3, [pc, #52] ; (8004204 <HAL_RCC_GetSysClockFreq+0xf8>)
80041ce: 689b ldr r3, [r3, #8]
80041d0: 2238 movs r2, #56 ; 0x38
80041d2: 4013 ands r3, r2
80041d4: 2b20 cmp r3, #32
80041d6: d103 bne.n 80041e0 <HAL_RCC_GetSysClockFreq+0xd4>
{
/* LSE used as system clock source */
sysclockfreq = LSE_VALUE;
80041d8: 2380 movs r3, #128 ; 0x80
80041da: 021b lsls r3, r3, #8
80041dc: 613b str r3, [r7, #16]
80041de: e00b b.n 80041f8 <HAL_RCC_GetSysClockFreq+0xec>
}
else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSI)
80041e0: 4b08 ldr r3, [pc, #32] ; (8004204 <HAL_RCC_GetSysClockFreq+0xf8>)
80041e2: 689b ldr r3, [r3, #8]
80041e4: 2238 movs r2, #56 ; 0x38
80041e6: 4013 ands r3, r2
80041e8: 2b18 cmp r3, #24
80041ea: d103 bne.n 80041f4 <HAL_RCC_GetSysClockFreq+0xe8>
{
/* LSI used as system clock source */
sysclockfreq = LSI_VALUE;
80041ec: 23fa movs r3, #250 ; 0xfa
80041ee: 01db lsls r3, r3, #7
80041f0: 613b str r3, [r7, #16]
80041f2: e001 b.n 80041f8 <HAL_RCC_GetSysClockFreq+0xec>
}
else
{
sysclockfreq = 0U;
80041f4: 2300 movs r3, #0
80041f6: 613b str r3, [r7, #16]
}
return sysclockfreq;
80041f8: 693b ldr r3, [r7, #16]
}
80041fa: 0018 movs r0, r3
80041fc: 46bd mov sp, r7
80041fe: b006 add sp, #24
8004200: bd80 pop {r7, pc}
8004202: 46c0 nop ; (mov r8, r8)
8004204: 40021000 .word 0x40021000
8004208: 00f42400 .word 0x00f42400
800420c: 007a1200 .word 0x007a1200
08004210 <HAL_RCC_GetHCLKFreq>:
*
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
* @retval HCLK frequency in Hz
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
8004210: b580 push {r7, lr}
8004212: af00 add r7, sp, #0
return SystemCoreClock;
8004214: 4b02 ldr r3, [pc, #8] ; (8004220 <HAL_RCC_GetHCLKFreq+0x10>)
8004216: 681b ldr r3, [r3, #0]
}
8004218: 0018 movs r0, r3
800421a: 46bd mov sp, r7
800421c: bd80 pop {r7, pc}
800421e: 46c0 nop ; (mov r8, r8)
8004220: 2000000c .word 0x2000000c
08004224 <HAL_RCC_GetPCLK1Freq>:
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK1 frequency in Hz
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
8004224: b5b0 push {r4, r5, r7, lr}
8004226: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return ((uint32_t)(__LL_RCC_CALC_PCLK1_FREQ(HAL_RCC_GetHCLKFreq(), LL_RCC_GetAPB1Prescaler())));
8004228: f7ff fff2 bl 8004210 <HAL_RCC_GetHCLKFreq>
800422c: 0004 movs r4, r0
800422e: f7ff fb3f bl 80038b0 <LL_RCC_GetAPB1Prescaler>
8004232: 0003 movs r3, r0
8004234: 0b1a lsrs r2, r3, #12
8004236: 4b05 ldr r3, [pc, #20] ; (800424c <HAL_RCC_GetPCLK1Freq+0x28>)
8004238: 0092 lsls r2, r2, #2
800423a: 58d3 ldr r3, [r2, r3]
800423c: 221f movs r2, #31
800423e: 4013 ands r3, r2
8004240: 40dc lsrs r4, r3
8004242: 0023 movs r3, r4
}
8004244: 0018 movs r0, r3
8004246: 46bd mov sp, r7
8004248: bdb0 pop {r4, r5, r7, pc}
800424a: 46c0 nop ; (mov r8, r8)
800424c: 08007410 .word 0x08007410
08004250 <HAL_RCCEx_PeriphCLKConfig>:
* the RTC clock source: in this case the access to Backup domain is enabled.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
8004250: b580 push {r7, lr}
8004252: b086 sub sp, #24
8004254: af00 add r7, sp, #0
8004256: 6078 str r0, [r7, #4]
uint32_t tmpregister;
uint32_t tickstart;
HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
8004258: 2313 movs r3, #19
800425a: 18fb adds r3, r7, r3
800425c: 2200 movs r2, #0
800425e: 701a strb r2, [r3, #0]
HAL_StatusTypeDef status = HAL_OK; /* Final status */
8004260: 2312 movs r3, #18
8004262: 18fb adds r3, r7, r3
8004264: 2200 movs r2, #0
8004266: 701a strb r2, [r3, #0]
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
/*-------------------------- RTC clock source configuration ----------------------*/
if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
8004268: 687b ldr r3, [r7, #4]
800426a: 681a ldr r2, [r3, #0]
800426c: 2380 movs r3, #128 ; 0x80
800426e: 029b lsls r3, r3, #10
8004270: 4013 ands r3, r2
8004272: d100 bne.n 8004276 <HAL_RCCEx_PeriphCLKConfig+0x26>
8004274: e0a3 b.n 80043be <HAL_RCCEx_PeriphCLKConfig+0x16e>
{
FlagStatus pwrclkchanged = RESET;
8004276: 2011 movs r0, #17
8004278: 183b adds r3, r7, r0
800427a: 2200 movs r2, #0
800427c: 701a strb r2, [r3, #0]
/* Check for RTC Parameters used to output RTCCLK */
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
/* Enable Power Clock */
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
800427e: 4ba5 ldr r3, [pc, #660] ; (8004514 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
8004280: 6bda ldr r2, [r3, #60] ; 0x3c
8004282: 2380 movs r3, #128 ; 0x80
8004284: 055b lsls r3, r3, #21
8004286: 4013 ands r3, r2
8004288: d110 bne.n 80042ac <HAL_RCCEx_PeriphCLKConfig+0x5c>
{
__HAL_RCC_PWR_CLK_ENABLE();
800428a: 4ba2 ldr r3, [pc, #648] ; (8004514 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
800428c: 6bda ldr r2, [r3, #60] ; 0x3c
800428e: 4ba1 ldr r3, [pc, #644] ; (8004514 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
8004290: 2180 movs r1, #128 ; 0x80
8004292: 0549 lsls r1, r1, #21
8004294: 430a orrs r2, r1
8004296: 63da str r2, [r3, #60] ; 0x3c
8004298: 4b9e ldr r3, [pc, #632] ; (8004514 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
800429a: 6bda ldr r2, [r3, #60] ; 0x3c
800429c: 2380 movs r3, #128 ; 0x80
800429e: 055b lsls r3, r3, #21
80042a0: 4013 ands r3, r2
80042a2: 60bb str r3, [r7, #8]
80042a4: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
80042a6: 183b adds r3, r7, r0
80042a8: 2201 movs r2, #1
80042aa: 701a strb r2, [r3, #0]
}
/* Enable write access to Backup domain */
SET_BIT(PWR->CR1, PWR_CR1_DBP);
80042ac: 4b9a ldr r3, [pc, #616] ; (8004518 <HAL_RCCEx_PeriphCLKConfig+0x2c8>)
80042ae: 681a ldr r2, [r3, #0]
80042b0: 4b99 ldr r3, [pc, #612] ; (8004518 <HAL_RCCEx_PeriphCLKConfig+0x2c8>)
80042b2: 2180 movs r1, #128 ; 0x80
80042b4: 0049 lsls r1, r1, #1
80042b6: 430a orrs r2, r1
80042b8: 601a str r2, [r3, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
80042ba: f7fd fc47 bl 8001b4c <HAL_GetTick>
80042be: 0003 movs r3, r0
80042c0: 60fb str r3, [r7, #12]
while ((PWR->CR1 & PWR_CR1_DBP) == 0U)
80042c2: e00b b.n 80042dc <HAL_RCCEx_PeriphCLKConfig+0x8c>
{
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
80042c4: f7fd fc42 bl 8001b4c <HAL_GetTick>
80042c8: 0002 movs r2, r0
80042ca: 68fb ldr r3, [r7, #12]
80042cc: 1ad3 subs r3, r2, r3
80042ce: 2b02 cmp r3, #2
80042d0: d904 bls.n 80042dc <HAL_RCCEx_PeriphCLKConfig+0x8c>
{
ret = HAL_TIMEOUT;
80042d2: 2313 movs r3, #19
80042d4: 18fb adds r3, r7, r3
80042d6: 2203 movs r2, #3
80042d8: 701a strb r2, [r3, #0]
break;
80042da: e005 b.n 80042e8 <HAL_RCCEx_PeriphCLKConfig+0x98>
while ((PWR->CR1 & PWR_CR1_DBP) == 0U)
80042dc: 4b8e ldr r3, [pc, #568] ; (8004518 <HAL_RCCEx_PeriphCLKConfig+0x2c8>)
80042de: 681a ldr r2, [r3, #0]
80042e0: 2380 movs r3, #128 ; 0x80
80042e2: 005b lsls r3, r3, #1
80042e4: 4013 ands r3, r2
80042e6: d0ed beq.n 80042c4 <HAL_RCCEx_PeriphCLKConfig+0x74>
}
}
if (ret == HAL_OK)
80042e8: 2313 movs r3, #19
80042ea: 18fb adds r3, r7, r3
80042ec: 781b ldrb r3, [r3, #0]
80042ee: 2b00 cmp r3, #0
80042f0: d154 bne.n 800439c <HAL_RCCEx_PeriphCLKConfig+0x14c>
{
/* Reset the Backup domain only if the RTC Clock source selection is modified from default */
tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL);
80042f2: 4b88 ldr r3, [pc, #544] ; (8004514 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
80042f4: 6dda ldr r2, [r3, #92] ; 0x5c
80042f6: 23c0 movs r3, #192 ; 0xc0
80042f8: 009b lsls r3, r3, #2
80042fa: 4013 ands r3, r2
80042fc: 617b str r3, [r7, #20]
/* Reset the Backup domain only if the RTC Clock source selection is modified */
if ((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection))
80042fe: 697b ldr r3, [r7, #20]
8004300: 2b00 cmp r3, #0
8004302: d019 beq.n 8004338 <HAL_RCCEx_PeriphCLKConfig+0xe8>
8004304: 687b ldr r3, [r7, #4]
8004306: 6a5b ldr r3, [r3, #36] ; 0x24
8004308: 697a ldr r2, [r7, #20]
800430a: 429a cmp r2, r3
800430c: d014 beq.n 8004338 <HAL_RCCEx_PeriphCLKConfig+0xe8>
{
/* Store the content of BDCR register before the reset of Backup Domain */
tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
800430e: 4b81 ldr r3, [pc, #516] ; (8004514 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
8004310: 6ddb ldr r3, [r3, #92] ; 0x5c
8004312: 4a82 ldr r2, [pc, #520] ; (800451c <HAL_RCCEx_PeriphCLKConfig+0x2cc>)
8004314: 4013 ands r3, r2
8004316: 617b str r3, [r7, #20]
/* RTC Clock selection can be changed only if the Backup Domain is reset */
__HAL_RCC_BACKUPRESET_FORCE();
8004318: 4b7e ldr r3, [pc, #504] ; (8004514 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
800431a: 6dda ldr r2, [r3, #92] ; 0x5c
800431c: 4b7d ldr r3, [pc, #500] ; (8004514 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
800431e: 2180 movs r1, #128 ; 0x80
8004320: 0249 lsls r1, r1, #9
8004322: 430a orrs r2, r1
8004324: 65da str r2, [r3, #92] ; 0x5c
__HAL_RCC_BACKUPRESET_RELEASE();
8004326: 4b7b ldr r3, [pc, #492] ; (8004514 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
8004328: 6dda ldr r2, [r3, #92] ; 0x5c
800432a: 4b7a ldr r3, [pc, #488] ; (8004514 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
800432c: 497c ldr r1, [pc, #496] ; (8004520 <HAL_RCCEx_PeriphCLKConfig+0x2d0>)
800432e: 400a ands r2, r1
8004330: 65da str r2, [r3, #92] ; 0x5c
/* Restore the Content of BDCR register */
RCC->BDCR = tmpregister;
8004332: 4b78 ldr r3, [pc, #480] ; (8004514 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
8004334: 697a ldr r2, [r7, #20]
8004336: 65da str r2, [r3, #92] ; 0x5c
}
/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON))
8004338: 697b ldr r3, [r7, #20]
800433a: 2201 movs r2, #1
800433c: 4013 ands r3, r2
800433e: d016 beq.n 800436e <HAL_RCCEx_PeriphCLKConfig+0x11e>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8004340: f7fd fc04 bl 8001b4c <HAL_GetTick>
8004344: 0003 movs r3, r0
8004346: 60fb str r3, [r7, #12]
/* Wait till LSE is ready */
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
8004348: e00c b.n 8004364 <HAL_RCCEx_PeriphCLKConfig+0x114>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
800434a: f7fd fbff bl 8001b4c <HAL_GetTick>
800434e: 0002 movs r2, r0
8004350: 68fb ldr r3, [r7, #12]
8004352: 1ad3 subs r3, r2, r3
8004354: 4a73 ldr r2, [pc, #460] ; (8004524 <HAL_RCCEx_PeriphCLKConfig+0x2d4>)
8004356: 4293 cmp r3, r2
8004358: d904 bls.n 8004364 <HAL_RCCEx_PeriphCLKConfig+0x114>
{
ret = HAL_TIMEOUT;
800435a: 2313 movs r3, #19
800435c: 18fb adds r3, r7, r3
800435e: 2203 movs r2, #3
8004360: 701a strb r2, [r3, #0]
break;
8004362: e004 b.n 800436e <HAL_RCCEx_PeriphCLKConfig+0x11e>
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
8004364: 4b6b ldr r3, [pc, #428] ; (8004514 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
8004366: 6ddb ldr r3, [r3, #92] ; 0x5c
8004368: 2202 movs r2, #2
800436a: 4013 ands r3, r2
800436c: d0ed beq.n 800434a <HAL_RCCEx_PeriphCLKConfig+0xfa>
}
}
}
if (ret == HAL_OK)
800436e: 2313 movs r3, #19
8004370: 18fb adds r3, r7, r3
8004372: 781b ldrb r3, [r3, #0]
8004374: 2b00 cmp r3, #0
8004376: d10a bne.n 800438e <HAL_RCCEx_PeriphCLKConfig+0x13e>
{
/* Apply new RTC clock source selection */
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
8004378: 4b66 ldr r3, [pc, #408] ; (8004514 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
800437a: 6ddb ldr r3, [r3, #92] ; 0x5c
800437c: 4a67 ldr r2, [pc, #412] ; (800451c <HAL_RCCEx_PeriphCLKConfig+0x2cc>)
800437e: 4013 ands r3, r2
8004380: 0019 movs r1, r3
8004382: 687b ldr r3, [r7, #4]
8004384: 6a5a ldr r2, [r3, #36] ; 0x24
8004386: 4b63 ldr r3, [pc, #396] ; (8004514 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
8004388: 430a orrs r2, r1
800438a: 65da str r2, [r3, #92] ; 0x5c
800438c: e00c b.n 80043a8 <HAL_RCCEx_PeriphCLKConfig+0x158>
}
else
{
/* set overall return value */
status = ret;
800438e: 2312 movs r3, #18
8004390: 18fb adds r3, r7, r3
8004392: 2213 movs r2, #19
8004394: 18ba adds r2, r7, r2
8004396: 7812 ldrb r2, [r2, #0]
8004398: 701a strb r2, [r3, #0]
800439a: e005 b.n 80043a8 <HAL_RCCEx_PeriphCLKConfig+0x158>
}
}
else
{
/* set overall return value */
status = ret;
800439c: 2312 movs r3, #18
800439e: 18fb adds r3, r7, r3
80043a0: 2213 movs r2, #19
80043a2: 18ba adds r2, r7, r2
80043a4: 7812 ldrb r2, [r2, #0]
80043a6: 701a strb r2, [r3, #0]
}
/* Restore clock configuration if changed */
if (pwrclkchanged == SET)
80043a8: 2311 movs r3, #17
80043aa: 18fb adds r3, r7, r3
80043ac: 781b ldrb r3, [r3, #0]
80043ae: 2b01 cmp r3, #1
80043b0: d105 bne.n 80043be <HAL_RCCEx_PeriphCLKConfig+0x16e>
{
__HAL_RCC_PWR_CLK_DISABLE();
80043b2: 4b58 ldr r3, [pc, #352] ; (8004514 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
80043b4: 6bda ldr r2, [r3, #60] ; 0x3c
80043b6: 4b57 ldr r3, [pc, #348] ; (8004514 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
80043b8: 495b ldr r1, [pc, #364] ; (8004528 <HAL_RCCEx_PeriphCLKConfig+0x2d8>)
80043ba: 400a ands r2, r1
80043bc: 63da str r2, [r3, #60] ; 0x3c
}
}
/*-------------------------- USART1 clock source configuration -------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
80043be: 687b ldr r3, [r7, #4]
80043c0: 681b ldr r3, [r3, #0]
80043c2: 2201 movs r2, #1
80043c4: 4013 ands r3, r2
80043c6: d009 beq.n 80043dc <HAL_RCCEx_PeriphCLKConfig+0x18c>
{
/* Check the parameters */
assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
/* Configure the USART1 clock source */
__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
80043c8: 4b52 ldr r3, [pc, #328] ; (8004514 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
80043ca: 6d5b ldr r3, [r3, #84] ; 0x54
80043cc: 2203 movs r2, #3
80043ce: 4393 bics r3, r2
80043d0: 0019 movs r1, r3
80043d2: 687b ldr r3, [r7, #4]
80043d4: 685a ldr r2, [r3, #4]
80043d6: 4b4f ldr r3, [pc, #316] ; (8004514 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
80043d8: 430a orrs r2, r1
80043da: 655a str r2, [r3, #84] ; 0x54
}
#endif /* RCC_CCIPR_USART3SEL */
#if defined(LPUART1)
/*-------------------------- LPUART1 clock source configuration ------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
80043dc: 687b ldr r3, [r7, #4]
80043de: 681b ldr r3, [r3, #0]
80043e0: 2210 movs r2, #16
80043e2: 4013 ands r3, r2
80043e4: d009 beq.n 80043fa <HAL_RCCEx_PeriphCLKConfig+0x1aa>
{
/* Check the parameters */
assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));
/* Configure the LPUART1 clock source */
__HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
80043e6: 4b4b ldr r3, [pc, #300] ; (8004514 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
80043e8: 6d5b ldr r3, [r3, #84] ; 0x54
80043ea: 4a50 ldr r2, [pc, #320] ; (800452c <HAL_RCCEx_PeriphCLKConfig+0x2dc>)
80043ec: 4013 ands r3, r2
80043ee: 0019 movs r1, r3
80043f0: 687b ldr r3, [r7, #4]
80043f2: 689a ldr r2, [r3, #8]
80043f4: 4b47 ldr r3, [pc, #284] ; (8004514 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
80043f6: 430a orrs r2, r1
80043f8: 655a str r2, [r3, #84] ; 0x54
}
#endif /* LPUART2 */
#if defined(RCC_CCIPR_LPTIM1SEL)
/*-------------------------- LPTIM1 clock source configuration -------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1))
80043fa: 687b ldr r3, [r7, #4]
80043fc: 681a ldr r2, [r3, #0]
80043fe: 2380 movs r3, #128 ; 0x80
8004400: 009b lsls r3, r3, #2
8004402: 4013 ands r3, r2
8004404: d009 beq.n 800441a <HAL_RCCEx_PeriphCLKConfig+0x1ca>
{
assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection));
__HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
8004406: 4b43 ldr r3, [pc, #268] ; (8004514 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
8004408: 6d5b ldr r3, [r3, #84] ; 0x54
800440a: 4a49 ldr r2, [pc, #292] ; (8004530 <HAL_RCCEx_PeriphCLKConfig+0x2e0>)
800440c: 4013 ands r3, r2
800440e: 0019 movs r1, r3
8004410: 687b ldr r3, [r7, #4]
8004412: 695a ldr r2, [r3, #20]
8004414: 4b3f ldr r3, [pc, #252] ; (8004514 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
8004416: 430a orrs r2, r1
8004418: 655a str r2, [r3, #84] ; 0x54
}
#endif /* RCC_CCIPR_LPTIM1SEL */
#if defined(RCC_CCIPR_LPTIM2SEL)
/*-------------------------- LPTIM2 clock source configuration -------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2))
800441a: 687b ldr r3, [r7, #4]
800441c: 681a ldr r2, [r3, #0]
800441e: 2380 movs r3, #128 ; 0x80
8004420: 00db lsls r3, r3, #3
8004422: 4013 ands r3, r2
8004424: d009 beq.n 800443a <HAL_RCCEx_PeriphCLKConfig+0x1ea>
{
assert_param(IS_RCC_LPTIM2CLKSOURCE(PeriphClkInit->Lptim2ClockSelection));
__HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);
8004426: 4b3b ldr r3, [pc, #236] ; (8004514 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
8004428: 6d5b ldr r3, [r3, #84] ; 0x54
800442a: 4a42 ldr r2, [pc, #264] ; (8004534 <HAL_RCCEx_PeriphCLKConfig+0x2e4>)
800442c: 4013 ands r3, r2
800442e: 0019 movs r1, r3
8004430: 687b ldr r3, [r7, #4]
8004432: 699a ldr r2, [r3, #24]
8004434: 4b37 ldr r3, [pc, #220] ; (8004514 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
8004436: 430a orrs r2, r1
8004438: 655a str r2, [r3, #84] ; 0x54
}
#endif /* RCC_CCIPR_LPTIM2SEL */
/*-------------------------- I2C1 clock source configuration ---------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
800443a: 687b ldr r3, [r7, #4]
800443c: 681b ldr r3, [r3, #0]
800443e: 2220 movs r2, #32
8004440: 4013 ands r3, r2
8004442: d009 beq.n 8004458 <HAL_RCCEx_PeriphCLKConfig+0x208>
{
/* Check the parameters */
assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
/* Configure the I2C1 clock source */
__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
8004444: 4b33 ldr r3, [pc, #204] ; (8004514 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
8004446: 6d5b ldr r3, [r3, #84] ; 0x54
8004448: 4a3b ldr r2, [pc, #236] ; (8004538 <HAL_RCCEx_PeriphCLKConfig+0x2e8>)
800444a: 4013 ands r3, r2
800444c: 0019 movs r1, r3
800444e: 687b ldr r3, [r7, #4]
8004450: 68da ldr r2, [r3, #12]
8004452: 4b30 ldr r3, [pc, #192] ; (8004514 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
8004454: 430a orrs r2, r1
8004456: 655a str r2, [r3, #84] ; 0x54
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLQCLK);
}
}
#endif /* RNG */
/*-------------------------- ADC clock source configuration ----------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
8004458: 687b ldr r3, [r7, #4]
800445a: 681a ldr r2, [r3, #0]
800445c: 2380 movs r3, #128 ; 0x80
800445e: 01db lsls r3, r3, #7
8004460: 4013 ands r3, r2
8004462: d015 beq.n 8004490 <HAL_RCCEx_PeriphCLKConfig+0x240>
{
/* Check the parameters */
assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection));
/* Configure the ADC interface clock source */
__HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
8004464: 4b2b ldr r3, [pc, #172] ; (8004514 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
8004466: 6d5b ldr r3, [r3, #84] ; 0x54
8004468: 009b lsls r3, r3, #2
800446a: 0899 lsrs r1, r3, #2
800446c: 687b ldr r3, [r7, #4]
800446e: 69da ldr r2, [r3, #28]
8004470: 4b28 ldr r3, [pc, #160] ; (8004514 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
8004472: 430a orrs r2, r1
8004474: 655a str r2, [r3, #84] ; 0x54
if (PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLADC)
8004476: 687b ldr r3, [r7, #4]
8004478: 69da ldr r2, [r3, #28]
800447a: 2380 movs r3, #128 ; 0x80
800447c: 05db lsls r3, r3, #23
800447e: 429a cmp r2, r3
8004480: d106 bne.n 8004490 <HAL_RCCEx_PeriphCLKConfig+0x240>
{
/* Enable PLLPCLK output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLPCLK);
8004482: 4b24 ldr r3, [pc, #144] ; (8004514 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
8004484: 68da ldr r2, [r3, #12]
8004486: 4b23 ldr r3, [pc, #140] ; (8004514 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
8004488: 2180 movs r1, #128 ; 0x80
800448a: 0249 lsls r1, r1, #9
800448c: 430a orrs r2, r1
800448e: 60da str r2, [r3, #12]
}
#endif /* CEC */
#if defined(RCC_CCIPR_TIM1SEL)
/*-------------------------- TIM1 clock source configuration ---------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1)
8004490: 687b ldr r3, [r7, #4]
8004492: 681a ldr r2, [r3, #0]
8004494: 2380 movs r3, #128 ; 0x80
8004496: 039b lsls r3, r3, #14
8004498: 4013 ands r3, r2
800449a: d016 beq.n 80044ca <HAL_RCCEx_PeriphCLKConfig+0x27a>
{
/* Check the parameters */
assert_param(IS_RCC_TIM1CLKSOURCE(PeriphClkInit->Tim1ClockSelection));
/* Configure the TIM1 clock source */
__HAL_RCC_TIM1_CONFIG(PeriphClkInit->Tim1ClockSelection);
800449c: 4b1d ldr r3, [pc, #116] ; (8004514 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
800449e: 6d5b ldr r3, [r3, #84] ; 0x54
80044a0: 4a26 ldr r2, [pc, #152] ; (800453c <HAL_RCCEx_PeriphCLKConfig+0x2ec>)
80044a2: 4013 ands r3, r2
80044a4: 0019 movs r1, r3
80044a6: 687b ldr r3, [r7, #4]
80044a8: 6a1a ldr r2, [r3, #32]
80044aa: 4b1a ldr r3, [pc, #104] ; (8004514 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
80044ac: 430a orrs r2, r1
80044ae: 655a str r2, [r3, #84] ; 0x54
if (PeriphClkInit->Tim1ClockSelection == RCC_TIM1CLKSOURCE_PLL)
80044b0: 687b ldr r3, [r7, #4]
80044b2: 6a1a ldr r2, [r3, #32]
80044b4: 2380 movs r3, #128 ; 0x80
80044b6: 03db lsls r3, r3, #15
80044b8: 429a cmp r2, r3
80044ba: d106 bne.n 80044ca <HAL_RCCEx_PeriphCLKConfig+0x27a>
{
/* Enable PLLQCLK output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLQCLK);
80044bc: 4b15 ldr r3, [pc, #84] ; (8004514 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
80044be: 68da ldr r2, [r3, #12]
80044c0: 4b14 ldr r3, [pc, #80] ; (8004514 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
80044c2: 2180 movs r1, #128 ; 0x80
80044c4: 0449 lsls r1, r1, #17
80044c6: 430a orrs r2, r1
80044c8: 60da str r2, [r3, #12]
}
}
#endif /* RCC_CCIPR_TIM15SEL */
/*-------------------------- I2S1 clock source configuration ---------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1)
80044ca: 687b ldr r3, [r7, #4]
80044cc: 681a ldr r2, [r3, #0]
80044ce: 2380 movs r3, #128 ; 0x80
80044d0: 011b lsls r3, r3, #4
80044d2: 4013 ands r3, r2
80044d4: d016 beq.n 8004504 <HAL_RCCEx_PeriphCLKConfig+0x2b4>
{
/* Check the parameters */
assert_param(IS_RCC_I2S1CLKSOURCE(PeriphClkInit->I2s1ClockSelection));
/* Configure the I2S1 clock source */
__HAL_RCC_I2S1_CONFIG(PeriphClkInit->I2s1ClockSelection);
80044d6: 4b0f ldr r3, [pc, #60] ; (8004514 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
80044d8: 6d5b ldr r3, [r3, #84] ; 0x54
80044da: 4a19 ldr r2, [pc, #100] ; (8004540 <HAL_RCCEx_PeriphCLKConfig+0x2f0>)
80044dc: 4013 ands r3, r2
80044de: 0019 movs r1, r3
80044e0: 687b ldr r3, [r7, #4]
80044e2: 691a ldr r2, [r3, #16]
80044e4: 4b0b ldr r3, [pc, #44] ; (8004514 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
80044e6: 430a orrs r2, r1
80044e8: 655a str r2, [r3, #84] ; 0x54
if (PeriphClkInit->I2s1ClockSelection == RCC_I2S1CLKSOURCE_PLL)
80044ea: 687b ldr r3, [r7, #4]
80044ec: 691a ldr r2, [r3, #16]
80044ee: 2380 movs r3, #128 ; 0x80
80044f0: 01db lsls r3, r3, #7
80044f2: 429a cmp r2, r3
80044f4: d106 bne.n 8004504 <HAL_RCCEx_PeriphCLKConfig+0x2b4>
{
/* Enable PLLPCLK output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLPCLK);
80044f6: 4b07 ldr r3, [pc, #28] ; (8004514 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
80044f8: 68da ldr r2, [r3, #12]
80044fa: 4b06 ldr r3, [pc, #24] ; (8004514 <HAL_RCCEx_PeriphCLKConfig+0x2c4>)
80044fc: 2180 movs r1, #128 ; 0x80
80044fe: 0249 lsls r1, r1, #9
8004500: 430a orrs r2, r1
8004502: 60da str r2, [r3, #12]
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLQCLK);
}
}
#endif /* FDCAN1 || FDCAN2 */
return status;
8004504: 2312 movs r3, #18
8004506: 18fb adds r3, r7, r3
8004508: 781b ldrb r3, [r3, #0]
}
800450a: 0018 movs r0, r3
800450c: 46bd mov sp, r7
800450e: b006 add sp, #24
8004510: bd80 pop {r7, pc}
8004512: 46c0 nop ; (mov r8, r8)
8004514: 40021000 .word 0x40021000
8004518: 40007000 .word 0x40007000
800451c: fffffcff .word 0xfffffcff
8004520: fffeffff .word 0xfffeffff
8004524: 00001388 .word 0x00001388
8004528: efffffff .word 0xefffffff
800452c: fffff3ff .word 0xfffff3ff
8004530: fff3ffff .word 0xfff3ffff
8004534: ffcfffff .word 0xffcfffff
8004538: ffffcfff .word 0xffffcfff
800453c: ffbfffff .word 0xffbfffff
8004540: ffff3fff .word 0xffff3fff
08004544 <HAL_TIM_PWM_Init>:
* Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
* @param htim TIM PWM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
{
8004544: b580 push {r7, lr}
8004546: b082 sub sp, #8
8004548: af00 add r7, sp, #0
800454a: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
800454c: 687b ldr r3, [r7, #4]
800454e: 2b00 cmp r3, #0
8004550: d101 bne.n 8004556 <HAL_TIM_PWM_Init+0x12>
{
return HAL_ERROR;
8004552: 2301 movs r3, #1
8004554: e04a b.n 80045ec <HAL_TIM_PWM_Init+0xa8>
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
8004556: 687b ldr r3, [r7, #4]
8004558: 223d movs r2, #61 ; 0x3d
800455a: 5c9b ldrb r3, [r3, r2]
800455c: b2db uxtb r3, r3
800455e: 2b00 cmp r3, #0
8004560: d107 bne.n 8004572 <HAL_TIM_PWM_Init+0x2e>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
8004562: 687b ldr r3, [r7, #4]
8004564: 223c movs r2, #60 ; 0x3c
8004566: 2100 movs r1, #0
8004568: 5499 strb r1, [r3, r2]
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->PWM_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_PWM_MspInit(htim);
800456a: 687b ldr r3, [r7, #4]
800456c: 0018 movs r0, r3
800456e: f7fd f939 bl 80017e4 <HAL_TIM_PWM_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8004572: 687b ldr r3, [r7, #4]
8004574: 223d movs r2, #61 ; 0x3d
8004576: 2102 movs r1, #2
8004578: 5499 strb r1, [r3, r2]
/* Init the base time for the PWM */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
800457a: 687b ldr r3, [r7, #4]
800457c: 681a ldr r2, [r3, #0]
800457e: 687b ldr r3, [r7, #4]
8004580: 3304 adds r3, #4
8004582: 0019 movs r1, r3
8004584: 0010 movs r0, r2
8004586: f000 fb5f bl 8004c48 <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
800458a: 687b ldr r3, [r7, #4]
800458c: 2248 movs r2, #72 ; 0x48
800458e: 2101 movs r1, #1
8004590: 5499 strb r1, [r3, r2]
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8004592: 687b ldr r3, [r7, #4]
8004594: 223e movs r2, #62 ; 0x3e
8004596: 2101 movs r1, #1
8004598: 5499 strb r1, [r3, r2]
800459a: 687b ldr r3, [r7, #4]
800459c: 223f movs r2, #63 ; 0x3f
800459e: 2101 movs r1, #1
80045a0: 5499 strb r1, [r3, r2]
80045a2: 687b ldr r3, [r7, #4]
80045a4: 2240 movs r2, #64 ; 0x40
80045a6: 2101 movs r1, #1
80045a8: 5499 strb r1, [r3, r2]
80045aa: 687b ldr r3, [r7, #4]
80045ac: 2241 movs r2, #65 ; 0x41
80045ae: 2101 movs r1, #1
80045b0: 5499 strb r1, [r3, r2]
80045b2: 687b ldr r3, [r7, #4]
80045b4: 2242 movs r2, #66 ; 0x42
80045b6: 2101 movs r1, #1
80045b8: 5499 strb r1, [r3, r2]
80045ba: 687b ldr r3, [r7, #4]
80045bc: 2243 movs r2, #67 ; 0x43
80045be: 2101 movs r1, #1
80045c0: 5499 strb r1, [r3, r2]
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
80045c2: 687b ldr r3, [r7, #4]
80045c4: 2244 movs r2, #68 ; 0x44
80045c6: 2101 movs r1, #1
80045c8: 5499 strb r1, [r3, r2]
80045ca: 687b ldr r3, [r7, #4]
80045cc: 2245 movs r2, #69 ; 0x45
80045ce: 2101 movs r1, #1
80045d0: 5499 strb r1, [r3, r2]
80045d2: 687b ldr r3, [r7, #4]
80045d4: 2246 movs r2, #70 ; 0x46
80045d6: 2101 movs r1, #1
80045d8: 5499 strb r1, [r3, r2]
80045da: 687b ldr r3, [r7, #4]
80045dc: 2247 movs r2, #71 ; 0x47
80045de: 2101 movs r1, #1
80045e0: 5499 strb r1, [r3, r2]
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
80045e2: 687b ldr r3, [r7, #4]
80045e4: 223d movs r2, #61 ; 0x3d
80045e6: 2101 movs r1, #1
80045e8: 5499 strb r1, [r3, r2]
return HAL_OK;
80045ea: 2300 movs r3, #0
}
80045ec: 0018 movs r0, r3
80045ee: 46bd mov sp, r7
80045f0: b002 add sp, #8
80045f2: bd80 pop {r7, pc}
080045f4 <HAL_TIM_PWM_Start>:
* @arg TIM_CHANNEL_5: TIM Channel 5 selected
* @arg TIM_CHANNEL_6: TIM Channel 6 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
80045f4: b580 push {r7, lr}
80045f6: b084 sub sp, #16
80045f8: af00 add r7, sp, #0
80045fa: 6078 str r0, [r7, #4]
80045fc: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
/* Check the TIM channel state */
if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
80045fe: 683b ldr r3, [r7, #0]
8004600: 2b00 cmp r3, #0
8004602: d108 bne.n 8004616 <HAL_TIM_PWM_Start+0x22>
8004604: 687b ldr r3, [r7, #4]
8004606: 223e movs r2, #62 ; 0x3e
8004608: 5c9b ldrb r3, [r3, r2]
800460a: b2db uxtb r3, r3
800460c: 3b01 subs r3, #1
800460e: 1e5a subs r2, r3, #1
8004610: 4193 sbcs r3, r2
8004612: b2db uxtb r3, r3
8004614: e037 b.n 8004686 <HAL_TIM_PWM_Start+0x92>
8004616: 683b ldr r3, [r7, #0]
8004618: 2b04 cmp r3, #4
800461a: d108 bne.n 800462e <HAL_TIM_PWM_Start+0x3a>
800461c: 687b ldr r3, [r7, #4]
800461e: 223f movs r2, #63 ; 0x3f
8004620: 5c9b ldrb r3, [r3, r2]
8004622: b2db uxtb r3, r3
8004624: 3b01 subs r3, #1
8004626: 1e5a subs r2, r3, #1
8004628: 4193 sbcs r3, r2
800462a: b2db uxtb r3, r3
800462c: e02b b.n 8004686 <HAL_TIM_PWM_Start+0x92>
800462e: 683b ldr r3, [r7, #0]
8004630: 2b08 cmp r3, #8
8004632: d108 bne.n 8004646 <HAL_TIM_PWM_Start+0x52>
8004634: 687b ldr r3, [r7, #4]
8004636: 2240 movs r2, #64 ; 0x40
8004638: 5c9b ldrb r3, [r3, r2]
800463a: b2db uxtb r3, r3
800463c: 3b01 subs r3, #1
800463e: 1e5a subs r2, r3, #1
8004640: 4193 sbcs r3, r2
8004642: b2db uxtb r3, r3
8004644: e01f b.n 8004686 <HAL_TIM_PWM_Start+0x92>
8004646: 683b ldr r3, [r7, #0]
8004648: 2b0c cmp r3, #12
800464a: d108 bne.n 800465e <HAL_TIM_PWM_Start+0x6a>
800464c: 687b ldr r3, [r7, #4]
800464e: 2241 movs r2, #65 ; 0x41
8004650: 5c9b ldrb r3, [r3, r2]
8004652: b2db uxtb r3, r3
8004654: 3b01 subs r3, #1
8004656: 1e5a subs r2, r3, #1
8004658: 4193 sbcs r3, r2
800465a: b2db uxtb r3, r3
800465c: e013 b.n 8004686 <HAL_TIM_PWM_Start+0x92>
800465e: 683b ldr r3, [r7, #0]
8004660: 2b10 cmp r3, #16
8004662: d108 bne.n 8004676 <HAL_TIM_PWM_Start+0x82>
8004664: 687b ldr r3, [r7, #4]
8004666: 2242 movs r2, #66 ; 0x42
8004668: 5c9b ldrb r3, [r3, r2]
800466a: b2db uxtb r3, r3
800466c: 3b01 subs r3, #1
800466e: 1e5a subs r2, r3, #1
8004670: 4193 sbcs r3, r2
8004672: b2db uxtb r3, r3
8004674: e007 b.n 8004686 <HAL_TIM_PWM_Start+0x92>
8004676: 687b ldr r3, [r7, #4]
8004678: 2243 movs r2, #67 ; 0x43
800467a: 5c9b ldrb r3, [r3, r2]
800467c: b2db uxtb r3, r3
800467e: 3b01 subs r3, #1
8004680: 1e5a subs r2, r3, #1
8004682: 4193 sbcs r3, r2
8004684: b2db uxtb r3, r3
8004686: 2b00 cmp r3, #0
8004688: d001 beq.n 800468e <HAL_TIM_PWM_Start+0x9a>
{
return HAL_ERROR;
800468a: 2301 movs r3, #1
800468c: e081 b.n 8004792 <HAL_TIM_PWM_Start+0x19e>
}
/* Set the TIM channel state */
TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
800468e: 683b ldr r3, [r7, #0]
8004690: 2b00 cmp r3, #0
8004692: d104 bne.n 800469e <HAL_TIM_PWM_Start+0xaa>
8004694: 687b ldr r3, [r7, #4]
8004696: 223e movs r2, #62 ; 0x3e
8004698: 2102 movs r1, #2
800469a: 5499 strb r1, [r3, r2]
800469c: e023 b.n 80046e6 <HAL_TIM_PWM_Start+0xf2>
800469e: 683b ldr r3, [r7, #0]
80046a0: 2b04 cmp r3, #4
80046a2: d104 bne.n 80046ae <HAL_TIM_PWM_Start+0xba>
80046a4: 687b ldr r3, [r7, #4]
80046a6: 223f movs r2, #63 ; 0x3f
80046a8: 2102 movs r1, #2
80046aa: 5499 strb r1, [r3, r2]
80046ac: e01b b.n 80046e6 <HAL_TIM_PWM_Start+0xf2>
80046ae: 683b ldr r3, [r7, #0]
80046b0: 2b08 cmp r3, #8
80046b2: d104 bne.n 80046be <HAL_TIM_PWM_Start+0xca>
80046b4: 687b ldr r3, [r7, #4]
80046b6: 2240 movs r2, #64 ; 0x40
80046b8: 2102 movs r1, #2
80046ba: 5499 strb r1, [r3, r2]
80046bc: e013 b.n 80046e6 <HAL_TIM_PWM_Start+0xf2>
80046be: 683b ldr r3, [r7, #0]
80046c0: 2b0c cmp r3, #12
80046c2: d104 bne.n 80046ce <HAL_TIM_PWM_Start+0xda>
80046c4: 687b ldr r3, [r7, #4]
80046c6: 2241 movs r2, #65 ; 0x41
80046c8: 2102 movs r1, #2
80046ca: 5499 strb r1, [r3, r2]
80046cc: e00b b.n 80046e6 <HAL_TIM_PWM_Start+0xf2>
80046ce: 683b ldr r3, [r7, #0]
80046d0: 2b10 cmp r3, #16
80046d2: d104 bne.n 80046de <HAL_TIM_PWM_Start+0xea>
80046d4: 687b ldr r3, [r7, #4]
80046d6: 2242 movs r2, #66 ; 0x42
80046d8: 2102 movs r1, #2
80046da: 5499 strb r1, [r3, r2]
80046dc: e003 b.n 80046e6 <HAL_TIM_PWM_Start+0xf2>
80046de: 687b ldr r3, [r7, #4]
80046e0: 2243 movs r2, #67 ; 0x43
80046e2: 2102 movs r1, #2
80046e4: 5499 strb r1, [r3, r2]
/* Enable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
80046e6: 687b ldr r3, [r7, #4]
80046e8: 681b ldr r3, [r3, #0]
80046ea: 6839 ldr r1, [r7, #0]
80046ec: 2201 movs r2, #1
80046ee: 0018 movs r0, r3
80046f0: f000 fdbc bl 800526c <TIM_CCxChannelCmd>
if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
80046f4: 687b ldr r3, [r7, #4]
80046f6: 681b ldr r3, [r3, #0]
80046f8: 4a28 ldr r2, [pc, #160] ; (800479c <HAL_TIM_PWM_Start+0x1a8>)
80046fa: 4293 cmp r3, r2
80046fc: d009 beq.n 8004712 <HAL_TIM_PWM_Start+0x11e>
80046fe: 687b ldr r3, [r7, #4]
8004700: 681b ldr r3, [r3, #0]
8004702: 4a27 ldr r2, [pc, #156] ; (80047a0 <HAL_TIM_PWM_Start+0x1ac>)
8004704: 4293 cmp r3, r2
8004706: d004 beq.n 8004712 <HAL_TIM_PWM_Start+0x11e>
8004708: 687b ldr r3, [r7, #4]
800470a: 681b ldr r3, [r3, #0]
800470c: 4a25 ldr r2, [pc, #148] ; (80047a4 <HAL_TIM_PWM_Start+0x1b0>)
800470e: 4293 cmp r3, r2
8004710: d101 bne.n 8004716 <HAL_TIM_PWM_Start+0x122>
8004712: 2301 movs r3, #1
8004714: e000 b.n 8004718 <HAL_TIM_PWM_Start+0x124>
8004716: 2300 movs r3, #0
8004718: 2b00 cmp r3, #0
800471a: d008 beq.n 800472e <HAL_TIM_PWM_Start+0x13a>
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
800471c: 687b ldr r3, [r7, #4]
800471e: 681b ldr r3, [r3, #0]
8004720: 6c5a ldr r2, [r3, #68] ; 0x44
8004722: 687b ldr r3, [r7, #4]
8004724: 681b ldr r3, [r3, #0]
8004726: 2180 movs r1, #128 ; 0x80
8004728: 0209 lsls r1, r1, #8
800472a: 430a orrs r2, r1
800472c: 645a str r2, [r3, #68] ; 0x44
}
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
800472e: 687b ldr r3, [r7, #4]
8004730: 681b ldr r3, [r3, #0]
8004732: 4a1a ldr r2, [pc, #104] ; (800479c <HAL_TIM_PWM_Start+0x1a8>)
8004734: 4293 cmp r3, r2
8004736: d00a beq.n 800474e <HAL_TIM_PWM_Start+0x15a>
8004738: 687b ldr r3, [r7, #4]
800473a: 681a ldr r2, [r3, #0]
800473c: 2380 movs r3, #128 ; 0x80
800473e: 05db lsls r3, r3, #23
8004740: 429a cmp r2, r3
8004742: d004 beq.n 800474e <HAL_TIM_PWM_Start+0x15a>
8004744: 687b ldr r3, [r7, #4]
8004746: 681b ldr r3, [r3, #0]
8004748: 4a17 ldr r2, [pc, #92] ; (80047a8 <HAL_TIM_PWM_Start+0x1b4>)
800474a: 4293 cmp r3, r2
800474c: d116 bne.n 800477c <HAL_TIM_PWM_Start+0x188>
{
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
800474e: 687b ldr r3, [r7, #4]
8004750: 681b ldr r3, [r3, #0]
8004752: 689b ldr r3, [r3, #8]
8004754: 4a15 ldr r2, [pc, #84] ; (80047ac <HAL_TIM_PWM_Start+0x1b8>)
8004756: 4013 ands r3, r2
8004758: 60fb str r3, [r7, #12]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
800475a: 68fb ldr r3, [r7, #12]
800475c: 2b06 cmp r3, #6
800475e: d016 beq.n 800478e <HAL_TIM_PWM_Start+0x19a>
8004760: 68fa ldr r2, [r7, #12]
8004762: 2380 movs r3, #128 ; 0x80
8004764: 025b lsls r3, r3, #9
8004766: 429a cmp r2, r3
8004768: d011 beq.n 800478e <HAL_TIM_PWM_Start+0x19a>
{
__HAL_TIM_ENABLE(htim);
800476a: 687b ldr r3, [r7, #4]
800476c: 681b ldr r3, [r3, #0]
800476e: 681a ldr r2, [r3, #0]
8004770: 687b ldr r3, [r7, #4]
8004772: 681b ldr r3, [r3, #0]
8004774: 2101 movs r1, #1
8004776: 430a orrs r2, r1
8004778: 601a str r2, [r3, #0]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
800477a: e008 b.n 800478e <HAL_TIM_PWM_Start+0x19a>
}
}
else
{
__HAL_TIM_ENABLE(htim);
800477c: 687b ldr r3, [r7, #4]
800477e: 681b ldr r3, [r3, #0]
8004780: 681a ldr r2, [r3, #0]
8004782: 687b ldr r3, [r7, #4]
8004784: 681b ldr r3, [r3, #0]
8004786: 2101 movs r1, #1
8004788: 430a orrs r2, r1
800478a: 601a str r2, [r3, #0]
800478c: e000 b.n 8004790 <HAL_TIM_PWM_Start+0x19c>
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
800478e: 46c0 nop ; (mov r8, r8)
}
/* Return function status */
return HAL_OK;
8004790: 2300 movs r3, #0
}
8004792: 0018 movs r0, r3
8004794: 46bd mov sp, r7
8004796: b004 add sp, #16
8004798: bd80 pop {r7, pc}
800479a: 46c0 nop ; (mov r8, r8)
800479c: 40012c00 .word 0x40012c00
80047a0: 40014400 .word 0x40014400
80047a4: 40014800 .word 0x40014800
80047a8: 40000400 .word 0x40000400
80047ac: 00010007 .word 0x00010007
080047b0 <HAL_TIM_Encoder_Init>:
* @param htim TIM Encoder Interface handle
* @param sConfig TIM Encoder Interface configuration structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
{
80047b0: b580 push {r7, lr}
80047b2: b086 sub sp, #24
80047b4: af00 add r7, sp, #0
80047b6: 6078 str r0, [r7, #4]
80047b8: 6039 str r1, [r7, #0]
uint32_t tmpsmcr;
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Check the TIM handle allocation */
if (htim == NULL)
80047ba: 687b ldr r3, [r7, #4]
80047bc: 2b00 cmp r3, #0
80047be: d101 bne.n 80047c4 <HAL_TIM_Encoder_Init+0x14>
{
return HAL_ERROR;
80047c0: 2301 movs r3, #1
80047c2: e090 b.n 80048e6 <HAL_TIM_Encoder_Init+0x136>
assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
if (htim->State == HAL_TIM_STATE_RESET)
80047c4: 687b ldr r3, [r7, #4]
80047c6: 223d movs r2, #61 ; 0x3d
80047c8: 5c9b ldrb r3, [r3, r2]
80047ca: b2db uxtb r3, r3
80047cc: 2b00 cmp r3, #0
80047ce: d107 bne.n 80047e0 <HAL_TIM_Encoder_Init+0x30>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
80047d0: 687b ldr r3, [r7, #4]
80047d2: 223c movs r2, #60 ; 0x3c
80047d4: 2100 movs r1, #0
80047d6: 5499 strb r1, [r3, r2]
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->Encoder_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_Encoder_MspInit(htim);
80047d8: 687b ldr r3, [r7, #4]
80047da: 0018 movs r0, r3
80047dc: f7fc ffba bl 8001754 <HAL_TIM_Encoder_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
80047e0: 687b ldr r3, [r7, #4]
80047e2: 223d movs r2, #61 ; 0x3d
80047e4: 2102 movs r1, #2
80047e6: 5499 strb r1, [r3, r2]
/* Reset the SMS and ECE bits */
htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
80047e8: 687b ldr r3, [r7, #4]
80047ea: 681b ldr r3, [r3, #0]
80047ec: 689a ldr r2, [r3, #8]
80047ee: 687b ldr r3, [r7, #4]
80047f0: 681b ldr r3, [r3, #0]
80047f2: 493f ldr r1, [pc, #252] ; (80048f0 <HAL_TIM_Encoder_Init+0x140>)
80047f4: 400a ands r2, r1
80047f6: 609a str r2, [r3, #8]
/* Configure the Time base in the Encoder Mode */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
80047f8: 687b ldr r3, [r7, #4]
80047fa: 681a ldr r2, [r3, #0]
80047fc: 687b ldr r3, [r7, #4]
80047fe: 3304 adds r3, #4
8004800: 0019 movs r1, r3
8004802: 0010 movs r0, r2
8004804: f000 fa20 bl 8004c48 <TIM_Base_SetConfig>
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
8004808: 687b ldr r3, [r7, #4]
800480a: 681b ldr r3, [r3, #0]
800480c: 689b ldr r3, [r3, #8]
800480e: 617b str r3, [r7, #20]
/* Get the TIMx CCMR1 register value */
tmpccmr1 = htim->Instance->CCMR1;
8004810: 687b ldr r3, [r7, #4]
8004812: 681b ldr r3, [r3, #0]
8004814: 699b ldr r3, [r3, #24]
8004816: 613b str r3, [r7, #16]
/* Get the TIMx CCER register value */
tmpccer = htim->Instance->CCER;
8004818: 687b ldr r3, [r7, #4]
800481a: 681b ldr r3, [r3, #0]
800481c: 6a1b ldr r3, [r3, #32]
800481e: 60fb str r3, [r7, #12]
/* Set the encoder Mode */
tmpsmcr |= sConfig->EncoderMode;
8004820: 683b ldr r3, [r7, #0]
8004822: 681b ldr r3, [r3, #0]
8004824: 697a ldr r2, [r7, #20]
8004826: 4313 orrs r3, r2
8004828: 617b str r3, [r7, #20]
/* Select the Capture Compare 1 and the Capture Compare 2 as input */
tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
800482a: 693b ldr r3, [r7, #16]
800482c: 4a31 ldr r2, [pc, #196] ; (80048f4 <HAL_TIM_Encoder_Init+0x144>)
800482e: 4013 ands r3, r2
8004830: 613b str r3, [r7, #16]
tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
8004832: 683b ldr r3, [r7, #0]
8004834: 689a ldr r2, [r3, #8]
8004836: 683b ldr r3, [r7, #0]
8004838: 699b ldr r3, [r3, #24]
800483a: 021b lsls r3, r3, #8
800483c: 4313 orrs r3, r2
800483e: 693a ldr r2, [r7, #16]
8004840: 4313 orrs r3, r2
8004842: 613b str r3, [r7, #16]
/* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
8004844: 693b ldr r3, [r7, #16]
8004846: 4a2c ldr r2, [pc, #176] ; (80048f8 <HAL_TIM_Encoder_Init+0x148>)
8004848: 4013 ands r3, r2
800484a: 613b str r3, [r7, #16]
tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
800484c: 693b ldr r3, [r7, #16]
800484e: 4a2b ldr r2, [pc, #172] ; (80048fc <HAL_TIM_Encoder_Init+0x14c>)
8004850: 4013 ands r3, r2
8004852: 613b str r3, [r7, #16]
tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
8004854: 683b ldr r3, [r7, #0]
8004856: 68da ldr r2, [r3, #12]
8004858: 683b ldr r3, [r7, #0]
800485a: 69db ldr r3, [r3, #28]
800485c: 021b lsls r3, r3, #8
800485e: 4313 orrs r3, r2
8004860: 693a ldr r2, [r7, #16]
8004862: 4313 orrs r3, r2
8004864: 613b str r3, [r7, #16]
tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
8004866: 683b ldr r3, [r7, #0]
8004868: 691b ldr r3, [r3, #16]
800486a: 011a lsls r2, r3, #4
800486c: 683b ldr r3, [r7, #0]
800486e: 6a1b ldr r3, [r3, #32]
8004870: 031b lsls r3, r3, #12
8004872: 4313 orrs r3, r2
8004874: 693a ldr r2, [r7, #16]
8004876: 4313 orrs r3, r2
8004878: 613b str r3, [r7, #16]
/* Set the TI1 and the TI2 Polarities */
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
800487a: 68fb ldr r3, [r7, #12]
800487c: 2222 movs r2, #34 ; 0x22
800487e: 4393 bics r3, r2
8004880: 60fb str r3, [r7, #12]
tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
8004882: 68fb ldr r3, [r7, #12]
8004884: 2288 movs r2, #136 ; 0x88
8004886: 4393 bics r3, r2
8004888: 60fb str r3, [r7, #12]
tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
800488a: 683b ldr r3, [r7, #0]
800488c: 685a ldr r2, [r3, #4]
800488e: 683b ldr r3, [r7, #0]
8004890: 695b ldr r3, [r3, #20]
8004892: 011b lsls r3, r3, #4
8004894: 4313 orrs r3, r2
8004896: 68fa ldr r2, [r7, #12]
8004898: 4313 orrs r3, r2
800489a: 60fb str r3, [r7, #12]
/* Write to TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
800489c: 687b ldr r3, [r7, #4]
800489e: 681b ldr r3, [r3, #0]
80048a0: 697a ldr r2, [r7, #20]
80048a2: 609a str r2, [r3, #8]
/* Write to TIMx CCMR1 */
htim->Instance->CCMR1 = tmpccmr1;
80048a4: 687b ldr r3, [r7, #4]
80048a6: 681b ldr r3, [r3, #0]
80048a8: 693a ldr r2, [r7, #16]
80048aa: 619a str r2, [r3, #24]
/* Write to TIMx CCER */
htim->Instance->CCER = tmpccer;
80048ac: 687b ldr r3, [r7, #4]
80048ae: 681b ldr r3, [r3, #0]
80048b0: 68fa ldr r2, [r7, #12]
80048b2: 621a str r2, [r3, #32]
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
80048b4: 687b ldr r3, [r7, #4]
80048b6: 2248 movs r2, #72 ; 0x48
80048b8: 2101 movs r1, #1
80048ba: 5499 strb r1, [r3, r2]
/* Set the TIM channels state */
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
80048bc: 687b ldr r3, [r7, #4]
80048be: 223e movs r2, #62 ; 0x3e
80048c0: 2101 movs r1, #1
80048c2: 5499 strb r1, [r3, r2]
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
80048c4: 687b ldr r3, [r7, #4]
80048c6: 223f movs r2, #63 ; 0x3f
80048c8: 2101 movs r1, #1
80048ca: 5499 strb r1, [r3, r2]
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
80048cc: 687b ldr r3, [r7, #4]
80048ce: 2244 movs r2, #68 ; 0x44
80048d0: 2101 movs r1, #1
80048d2: 5499 strb r1, [r3, r2]
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
80048d4: 687b ldr r3, [r7, #4]
80048d6: 2245 movs r2, #69 ; 0x45
80048d8: 2101 movs r1, #1
80048da: 5499 strb r1, [r3, r2]
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
80048dc: 687b ldr r3, [r7, #4]
80048de: 223d movs r2, #61 ; 0x3d
80048e0: 2101 movs r1, #1
80048e2: 5499 strb r1, [r3, r2]
return HAL_OK;
80048e4: 2300 movs r3, #0
}
80048e6: 0018 movs r0, r3
80048e8: 46bd mov sp, r7
80048ea: b006 add sp, #24
80048ec: bd80 pop {r7, pc}
80048ee: 46c0 nop ; (mov r8, r8)
80048f0: fffebff8 .word 0xfffebff8
80048f4: fffffcfc .word 0xfffffcfc
80048f8: fffff3f3 .word 0xfffff3f3
80048fc: ffff0f0f .word 0xffff0f0f
08004900 <HAL_TIM_Encoder_Start>:
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
8004900: b590 push {r4, r7, lr}
8004902: b085 sub sp, #20
8004904: af00 add r7, sp, #0
8004906: 6078 str r0, [r7, #4]
8004908: 6039 str r1, [r7, #0]
HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
800490a: 200f movs r0, #15
800490c: 183b adds r3, r7, r0
800490e: 687a ldr r2, [r7, #4]
8004910: 213e movs r1, #62 ; 0x3e
8004912: 5c52 ldrb r2, [r2, r1]
8004914: 701a strb r2, [r3, #0]
HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
8004916: 230e movs r3, #14
8004918: 18fb adds r3, r7, r3
800491a: 687a ldr r2, [r7, #4]
800491c: 213f movs r1, #63 ; 0x3f
800491e: 5c52 ldrb r2, [r2, r1]
8004920: 701a strb r2, [r3, #0]
HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
8004922: 240d movs r4, #13
8004924: 193b adds r3, r7, r4
8004926: 687a ldr r2, [r7, #4]
8004928: 2144 movs r1, #68 ; 0x44
800492a: 5c52 ldrb r2, [r2, r1]
800492c: 701a strb r2, [r3, #0]
HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
800492e: 230c movs r3, #12
8004930: 18fb adds r3, r7, r3
8004932: 687a ldr r2, [r7, #4]
8004934: 2145 movs r1, #69 ; 0x45
8004936: 5c52 ldrb r2, [r2, r1]
8004938: 701a strb r2, [r3, #0]
/* Check the parameters */
assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
/* Set the TIM channel(s) state */
if (Channel == TIM_CHANNEL_1)
800493a: 683b ldr r3, [r7, #0]
800493c: 2b00 cmp r3, #0
800493e: d112 bne.n 8004966 <HAL_TIM_Encoder_Start+0x66>
{
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
8004940: 183b adds r3, r7, r0
8004942: 781b ldrb r3, [r3, #0]
8004944: 2b01 cmp r3, #1
8004946: d103 bne.n 8004950 <HAL_TIM_Encoder_Start+0x50>
|| (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
8004948: 193b adds r3, r7, r4
800494a: 781b ldrb r3, [r3, #0]
800494c: 2b01 cmp r3, #1
800494e: d001 beq.n 8004954 <HAL_TIM_Encoder_Start+0x54>
{
return HAL_ERROR;
8004950: 2301 movs r3, #1
8004952: e075 b.n 8004a40 <HAL_TIM_Encoder_Start+0x140>
}
else
{
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
8004954: 687b ldr r3, [r7, #4]
8004956: 223e movs r2, #62 ; 0x3e
8004958: 2102 movs r1, #2
800495a: 5499 strb r1, [r3, r2]
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
800495c: 687b ldr r3, [r7, #4]
800495e: 2244 movs r2, #68 ; 0x44
8004960: 2102 movs r1, #2
8004962: 5499 strb r1, [r3, r2]
8004964: e03d b.n 80049e2 <HAL_TIM_Encoder_Start+0xe2>
}
}
else if (Channel == TIM_CHANNEL_2)
8004966: 683b ldr r3, [r7, #0]
8004968: 2b04 cmp r3, #4
800496a: d114 bne.n 8004996 <HAL_TIM_Encoder_Start+0x96>
{
if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
800496c: 230e movs r3, #14
800496e: 18fb adds r3, r7, r3
8004970: 781b ldrb r3, [r3, #0]
8004972: 2b01 cmp r3, #1
8004974: d104 bne.n 8004980 <HAL_TIM_Encoder_Start+0x80>
|| (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
8004976: 230c movs r3, #12
8004978: 18fb adds r3, r7, r3
800497a: 781b ldrb r3, [r3, #0]
800497c: 2b01 cmp r3, #1
800497e: d001 beq.n 8004984 <HAL_TIM_Encoder_Start+0x84>
{
return HAL_ERROR;
8004980: 2301 movs r3, #1
8004982: e05d b.n 8004a40 <HAL_TIM_Encoder_Start+0x140>
}
else
{
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
8004984: 687b ldr r3, [r7, #4]
8004986: 223f movs r2, #63 ; 0x3f
8004988: 2102 movs r1, #2
800498a: 5499 strb r1, [r3, r2]
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
800498c: 687b ldr r3, [r7, #4]
800498e: 2245 movs r2, #69 ; 0x45
8004990: 2102 movs r1, #2
8004992: 5499 strb r1, [r3, r2]
8004994: e025 b.n 80049e2 <HAL_TIM_Encoder_Start+0xe2>
}
}
else
{
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
8004996: 230f movs r3, #15
8004998: 18fb adds r3, r7, r3
800499a: 781b ldrb r3, [r3, #0]
800499c: 2b01 cmp r3, #1
800499e: d10e bne.n 80049be <HAL_TIM_Encoder_Start+0xbe>
|| (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
80049a0: 230e movs r3, #14
80049a2: 18fb adds r3, r7, r3
80049a4: 781b ldrb r3, [r3, #0]
80049a6: 2b01 cmp r3, #1
80049a8: d109 bne.n 80049be <HAL_TIM_Encoder_Start+0xbe>
|| (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
80049aa: 230d movs r3, #13
80049ac: 18fb adds r3, r7, r3
80049ae: 781b ldrb r3, [r3, #0]
80049b0: 2b01 cmp r3, #1
80049b2: d104 bne.n 80049be <HAL_TIM_Encoder_Start+0xbe>
|| (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
80049b4: 230c movs r3, #12
80049b6: 18fb adds r3, r7, r3
80049b8: 781b ldrb r3, [r3, #0]
80049ba: 2b01 cmp r3, #1
80049bc: d001 beq.n 80049c2 <HAL_TIM_Encoder_Start+0xc2>
{
return HAL_ERROR;
80049be: 2301 movs r3, #1
80049c0: e03e b.n 8004a40 <HAL_TIM_Encoder_Start+0x140>
}
else
{
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
80049c2: 687b ldr r3, [r7, #4]
80049c4: 223e movs r2, #62 ; 0x3e
80049c6: 2102 movs r1, #2
80049c8: 5499 strb r1, [r3, r2]
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
80049ca: 687b ldr r3, [r7, #4]
80049cc: 223f movs r2, #63 ; 0x3f
80049ce: 2102 movs r1, #2
80049d0: 5499 strb r1, [r3, r2]
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
80049d2: 687b ldr r3, [r7, #4]
80049d4: 2244 movs r2, #68 ; 0x44
80049d6: 2102 movs r1, #2
80049d8: 5499 strb r1, [r3, r2]
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
80049da: 687b ldr r3, [r7, #4]
80049dc: 2245 movs r2, #69 ; 0x45
80049de: 2102 movs r1, #2
80049e0: 5499 strb r1, [r3, r2]
}
}
/* Enable the encoder interface channels */
switch (Channel)
80049e2: 683b ldr r3, [r7, #0]
80049e4: 2b00 cmp r3, #0
80049e6: d003 beq.n 80049f0 <HAL_TIM_Encoder_Start+0xf0>
80049e8: 683b ldr r3, [r7, #0]
80049ea: 2b04 cmp r3, #4
80049ec: d008 beq.n 8004a00 <HAL_TIM_Encoder_Start+0x100>
80049ee: e00f b.n 8004a10 <HAL_TIM_Encoder_Start+0x110>
{
case TIM_CHANNEL_1:
{
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
80049f0: 687b ldr r3, [r7, #4]
80049f2: 681b ldr r3, [r3, #0]
80049f4: 2201 movs r2, #1
80049f6: 2100 movs r1, #0
80049f8: 0018 movs r0, r3
80049fa: f000 fc37 bl 800526c <TIM_CCxChannelCmd>
break;
80049fe: e016 b.n 8004a2e <HAL_TIM_Encoder_Start+0x12e>
}
case TIM_CHANNEL_2:
{
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
8004a00: 687b ldr r3, [r7, #4]
8004a02: 681b ldr r3, [r3, #0]
8004a04: 2201 movs r2, #1
8004a06: 2104 movs r1, #4
8004a08: 0018 movs r0, r3
8004a0a: f000 fc2f bl 800526c <TIM_CCxChannelCmd>
break;
8004a0e: e00e b.n 8004a2e <HAL_TIM_Encoder_Start+0x12e>
}
default :
{
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
8004a10: 687b ldr r3, [r7, #4]
8004a12: 681b ldr r3, [r3, #0]
8004a14: 2201 movs r2, #1
8004a16: 2100 movs r1, #0
8004a18: 0018 movs r0, r3
8004a1a: f000 fc27 bl 800526c <TIM_CCxChannelCmd>
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
8004a1e: 687b ldr r3, [r7, #4]
8004a20: 681b ldr r3, [r3, #0]
8004a22: 2201 movs r2, #1
8004a24: 2104 movs r1, #4
8004a26: 0018 movs r0, r3
8004a28: f000 fc20 bl 800526c <TIM_CCxChannelCmd>
break;
8004a2c: 46c0 nop ; (mov r8, r8)
}
}
/* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
8004a2e: 687b ldr r3, [r7, #4]
8004a30: 681b ldr r3, [r3, #0]
8004a32: 681a ldr r2, [r3, #0]
8004a34: 687b ldr r3, [r7, #4]
8004a36: 681b ldr r3, [r3, #0]
8004a38: 2101 movs r1, #1
8004a3a: 430a orrs r2, r1
8004a3c: 601a str r2, [r3, #0]
/* Return function status */
return HAL_OK;
8004a3e: 2300 movs r3, #0
}
8004a40: 0018 movs r0, r3
8004a42: 46bd mov sp, r7
8004a44: b005 add sp, #20
8004a46: bd90 pop {r4, r7, pc}
08004a48 <HAL_TIM_PWM_ConfigChannel>:
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
const TIM_OC_InitTypeDef *sConfig,
uint32_t Channel)
{
8004a48: b580 push {r7, lr}
8004a4a: b086 sub sp, #24
8004a4c: af00 add r7, sp, #0
8004a4e: 60f8 str r0, [r7, #12]
8004a50: 60b9 str r1, [r7, #8]
8004a52: 607a str r2, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
8004a54: 2317 movs r3, #23
8004a56: 18fb adds r3, r7, r3
8004a58: 2200 movs r2, #0
8004a5a: 701a strb r2, [r3, #0]
assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
/* Process Locked */
__HAL_LOCK(htim);
8004a5c: 68fb ldr r3, [r7, #12]
8004a5e: 223c movs r2, #60 ; 0x3c
8004a60: 5c9b ldrb r3, [r3, r2]
8004a62: 2b01 cmp r3, #1
8004a64: d101 bne.n 8004a6a <HAL_TIM_PWM_ConfigChannel+0x22>
8004a66: 2302 movs r3, #2
8004a68: e0e5 b.n 8004c36 <HAL_TIM_PWM_ConfigChannel+0x1ee>
8004a6a: 68fb ldr r3, [r7, #12]
8004a6c: 223c movs r2, #60 ; 0x3c
8004a6e: 2101 movs r1, #1
8004a70: 5499 strb r1, [r3, r2]
switch (Channel)
8004a72: 687b ldr r3, [r7, #4]
8004a74: 2b14 cmp r3, #20
8004a76: d900 bls.n 8004a7a <HAL_TIM_PWM_ConfigChannel+0x32>
8004a78: e0d1 b.n 8004c1e <HAL_TIM_PWM_ConfigChannel+0x1d6>
8004a7a: 687b ldr r3, [r7, #4]
8004a7c: 009a lsls r2, r3, #2
8004a7e: 4b70 ldr r3, [pc, #448] ; (8004c40 <HAL_TIM_PWM_ConfigChannel+0x1f8>)
8004a80: 18d3 adds r3, r2, r3
8004a82: 681b ldr r3, [r3, #0]
8004a84: 469f mov pc, r3
{
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
/* Configure the Channel 1 in PWM mode */
TIM_OC1_SetConfig(htim->Instance, sConfig);
8004a86: 68fb ldr r3, [r7, #12]
8004a88: 681b ldr r3, [r3, #0]
8004a8a: 68ba ldr r2, [r7, #8]
8004a8c: 0011 movs r1, r2
8004a8e: 0018 movs r0, r3
8004a90: f000 f950 bl 8004d34 <TIM_OC1_SetConfig>
/* Set the Preload enable bit for channel1 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
8004a94: 68fb ldr r3, [r7, #12]
8004a96: 681b ldr r3, [r3, #0]
8004a98: 699a ldr r2, [r3, #24]
8004a9a: 68fb ldr r3, [r7, #12]
8004a9c: 681b ldr r3, [r3, #0]
8004a9e: 2108 movs r1, #8
8004aa0: 430a orrs r2, r1
8004aa2: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
8004aa4: 68fb ldr r3, [r7, #12]
8004aa6: 681b ldr r3, [r3, #0]
8004aa8: 699a ldr r2, [r3, #24]
8004aaa: 68fb ldr r3, [r7, #12]
8004aac: 681b ldr r3, [r3, #0]
8004aae: 2104 movs r1, #4
8004ab0: 438a bics r2, r1
8004ab2: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode;
8004ab4: 68fb ldr r3, [r7, #12]
8004ab6: 681b ldr r3, [r3, #0]
8004ab8: 6999 ldr r1, [r3, #24]
8004aba: 68bb ldr r3, [r7, #8]
8004abc: 691a ldr r2, [r3, #16]
8004abe: 68fb ldr r3, [r7, #12]
8004ac0: 681b ldr r3, [r3, #0]
8004ac2: 430a orrs r2, r1
8004ac4: 619a str r2, [r3, #24]
break;
8004ac6: e0af b.n 8004c28 <HAL_TIM_PWM_ConfigChannel+0x1e0>
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
/* Configure the Channel 2 in PWM mode */
TIM_OC2_SetConfig(htim->Instance, sConfig);
8004ac8: 68fb ldr r3, [r7, #12]
8004aca: 681b ldr r3, [r3, #0]
8004acc: 68ba ldr r2, [r7, #8]
8004ace: 0011 movs r1, r2
8004ad0: 0018 movs r0, r3
8004ad2: f000 f9af bl 8004e34 <TIM_OC2_SetConfig>
/* Set the Preload enable bit for channel2 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
8004ad6: 68fb ldr r3, [r7, #12]
8004ad8: 681b ldr r3, [r3, #0]
8004ada: 699a ldr r2, [r3, #24]
8004adc: 68fb ldr r3, [r7, #12]
8004ade: 681b ldr r3, [r3, #0]
8004ae0: 2180 movs r1, #128 ; 0x80
8004ae2: 0109 lsls r1, r1, #4
8004ae4: 430a orrs r2, r1
8004ae6: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
8004ae8: 68fb ldr r3, [r7, #12]
8004aea: 681b ldr r3, [r3, #0]
8004aec: 699a ldr r2, [r3, #24]
8004aee: 68fb ldr r3, [r7, #12]
8004af0: 681b ldr r3, [r3, #0]
8004af2: 4954 ldr r1, [pc, #336] ; (8004c44 <HAL_TIM_PWM_ConfigChannel+0x1fc>)
8004af4: 400a ands r2, r1
8004af6: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
8004af8: 68fb ldr r3, [r7, #12]
8004afa: 681b ldr r3, [r3, #0]
8004afc: 6999 ldr r1, [r3, #24]
8004afe: 68bb ldr r3, [r7, #8]
8004b00: 691b ldr r3, [r3, #16]
8004b02: 021a lsls r2, r3, #8
8004b04: 68fb ldr r3, [r7, #12]
8004b06: 681b ldr r3, [r3, #0]
8004b08: 430a orrs r2, r1
8004b0a: 619a str r2, [r3, #24]
break;
8004b0c: e08c b.n 8004c28 <HAL_TIM_PWM_ConfigChannel+0x1e0>
{
/* Check the parameters */
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
/* Configure the Channel 3 in PWM mode */
TIM_OC3_SetConfig(htim->Instance, sConfig);
8004b0e: 68fb ldr r3, [r7, #12]
8004b10: 681b ldr r3, [r3, #0]
8004b12: 68ba ldr r2, [r7, #8]
8004b14: 0011 movs r1, r2
8004b16: 0018 movs r0, r3
8004b18: f000 fa0a bl 8004f30 <TIM_OC3_SetConfig>
/* Set the Preload enable bit for channel3 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
8004b1c: 68fb ldr r3, [r7, #12]
8004b1e: 681b ldr r3, [r3, #0]
8004b20: 69da ldr r2, [r3, #28]
8004b22: 68fb ldr r3, [r7, #12]
8004b24: 681b ldr r3, [r3, #0]
8004b26: 2108 movs r1, #8
8004b28: 430a orrs r2, r1
8004b2a: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
8004b2c: 68fb ldr r3, [r7, #12]
8004b2e: 681b ldr r3, [r3, #0]
8004b30: 69da ldr r2, [r3, #28]
8004b32: 68fb ldr r3, [r7, #12]
8004b34: 681b ldr r3, [r3, #0]
8004b36: 2104 movs r1, #4
8004b38: 438a bics r2, r1
8004b3a: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode;
8004b3c: 68fb ldr r3, [r7, #12]
8004b3e: 681b ldr r3, [r3, #0]
8004b40: 69d9 ldr r1, [r3, #28]
8004b42: 68bb ldr r3, [r7, #8]
8004b44: 691a ldr r2, [r3, #16]
8004b46: 68fb ldr r3, [r7, #12]
8004b48: 681b ldr r3, [r3, #0]
8004b4a: 430a orrs r2, r1
8004b4c: 61da str r2, [r3, #28]
break;
8004b4e: e06b b.n 8004c28 <HAL_TIM_PWM_ConfigChannel+0x1e0>
{
/* Check the parameters */
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
/* Configure the Channel 4 in PWM mode */
TIM_OC4_SetConfig(htim->Instance, sConfig);
8004b50: 68fb ldr r3, [r7, #12]
8004b52: 681b ldr r3, [r3, #0]
8004b54: 68ba ldr r2, [r7, #8]
8004b56: 0011 movs r1, r2
8004b58: 0018 movs r0, r3
8004b5a: f000 fa6b bl 8005034 <TIM_OC4_SetConfig>
/* Set the Preload enable bit for channel4 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
8004b5e: 68fb ldr r3, [r7, #12]
8004b60: 681b ldr r3, [r3, #0]
8004b62: 69da ldr r2, [r3, #28]
8004b64: 68fb ldr r3, [r7, #12]
8004b66: 681b ldr r3, [r3, #0]
8004b68: 2180 movs r1, #128 ; 0x80
8004b6a: 0109 lsls r1, r1, #4
8004b6c: 430a orrs r2, r1
8004b6e: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
8004b70: 68fb ldr r3, [r7, #12]
8004b72: 681b ldr r3, [r3, #0]
8004b74: 69da ldr r2, [r3, #28]
8004b76: 68fb ldr r3, [r7, #12]
8004b78: 681b ldr r3, [r3, #0]
8004b7a: 4932 ldr r1, [pc, #200] ; (8004c44 <HAL_TIM_PWM_ConfigChannel+0x1fc>)
8004b7c: 400a ands r2, r1
8004b7e: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
8004b80: 68fb ldr r3, [r7, #12]
8004b82: 681b ldr r3, [r3, #0]
8004b84: 69d9 ldr r1, [r3, #28]
8004b86: 68bb ldr r3, [r7, #8]
8004b88: 691b ldr r3, [r3, #16]
8004b8a: 021a lsls r2, r3, #8
8004b8c: 68fb ldr r3, [r7, #12]
8004b8e: 681b ldr r3, [r3, #0]
8004b90: 430a orrs r2, r1
8004b92: 61da str r2, [r3, #28]
break;
8004b94: e048 b.n 8004c28 <HAL_TIM_PWM_ConfigChannel+0x1e0>
{
/* Check the parameters */
assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
/* Configure the Channel 5 in PWM mode */
TIM_OC5_SetConfig(htim->Instance, sConfig);
8004b96: 68fb ldr r3, [r7, #12]
8004b98: 681b ldr r3, [r3, #0]
8004b9a: 68ba ldr r2, [r7, #8]
8004b9c: 0011 movs r1, r2
8004b9e: 0018 movs r0, r3
8004ba0: f000 faac bl 80050fc <TIM_OC5_SetConfig>
/* Set the Preload enable bit for channel5*/
htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
8004ba4: 68fb ldr r3, [r7, #12]
8004ba6: 681b ldr r3, [r3, #0]
8004ba8: 6d5a ldr r2, [r3, #84] ; 0x54
8004baa: 68fb ldr r3, [r7, #12]
8004bac: 681b ldr r3, [r3, #0]
8004bae: 2108 movs r1, #8
8004bb0: 430a orrs r2, r1
8004bb2: 655a str r2, [r3, #84] ; 0x54
/* Configure the Output Fast mode */
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
8004bb4: 68fb ldr r3, [r7, #12]
8004bb6: 681b ldr r3, [r3, #0]
8004bb8: 6d5a ldr r2, [r3, #84] ; 0x54
8004bba: 68fb ldr r3, [r7, #12]
8004bbc: 681b ldr r3, [r3, #0]
8004bbe: 2104 movs r1, #4
8004bc0: 438a bics r2, r1
8004bc2: 655a str r2, [r3, #84] ; 0x54
htim->Instance->CCMR3 |= sConfig->OCFastMode;
8004bc4: 68fb ldr r3, [r7, #12]
8004bc6: 681b ldr r3, [r3, #0]
8004bc8: 6d59 ldr r1, [r3, #84] ; 0x54
8004bca: 68bb ldr r3, [r7, #8]
8004bcc: 691a ldr r2, [r3, #16]
8004bce: 68fb ldr r3, [r7, #12]
8004bd0: 681b ldr r3, [r3, #0]
8004bd2: 430a orrs r2, r1
8004bd4: 655a str r2, [r3, #84] ; 0x54
break;
8004bd6: e027 b.n 8004c28 <HAL_TIM_PWM_ConfigChannel+0x1e0>
{
/* Check the parameters */
assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
/* Configure the Channel 6 in PWM mode */
TIM_OC6_SetConfig(htim->Instance, sConfig);
8004bd8: 68fb ldr r3, [r7, #12]
8004bda: 681b ldr r3, [r3, #0]
8004bdc: 68ba ldr r2, [r7, #8]
8004bde: 0011 movs r1, r2
8004be0: 0018 movs r0, r3
8004be2: f000 fae5 bl 80051b0 <TIM_OC6_SetConfig>
/* Set the Preload enable bit for channel6 */
htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
8004be6: 68fb ldr r3, [r7, #12]
8004be8: 681b ldr r3, [r3, #0]
8004bea: 6d5a ldr r2, [r3, #84] ; 0x54
8004bec: 68fb ldr r3, [r7, #12]
8004bee: 681b ldr r3, [r3, #0]
8004bf0: 2180 movs r1, #128 ; 0x80
8004bf2: 0109 lsls r1, r1, #4
8004bf4: 430a orrs r2, r1
8004bf6: 655a str r2, [r3, #84] ; 0x54
/* Configure the Output Fast mode */
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
8004bf8: 68fb ldr r3, [r7, #12]
8004bfa: 681b ldr r3, [r3, #0]
8004bfc: 6d5a ldr r2, [r3, #84] ; 0x54
8004bfe: 68fb ldr r3, [r7, #12]
8004c00: 681b ldr r3, [r3, #0]
8004c02: 4910 ldr r1, [pc, #64] ; (8004c44 <HAL_TIM_PWM_ConfigChannel+0x1fc>)
8004c04: 400a ands r2, r1
8004c06: 655a str r2, [r3, #84] ; 0x54
htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
8004c08: 68fb ldr r3, [r7, #12]
8004c0a: 681b ldr r3, [r3, #0]
8004c0c: 6d59 ldr r1, [r3, #84] ; 0x54
8004c0e: 68bb ldr r3, [r7, #8]
8004c10: 691b ldr r3, [r3, #16]
8004c12: 021a lsls r2, r3, #8
8004c14: 68fb ldr r3, [r7, #12]
8004c16: 681b ldr r3, [r3, #0]
8004c18: 430a orrs r2, r1
8004c1a: 655a str r2, [r3, #84] ; 0x54
break;
8004c1c: e004 b.n 8004c28 <HAL_TIM_PWM_ConfigChannel+0x1e0>
}
default:
status = HAL_ERROR;
8004c1e: 2317 movs r3, #23
8004c20: 18fb adds r3, r7, r3
8004c22: 2201 movs r2, #1
8004c24: 701a strb r2, [r3, #0]
break;
8004c26: 46c0 nop ; (mov r8, r8)
}
__HAL_UNLOCK(htim);
8004c28: 68fb ldr r3, [r7, #12]
8004c2a: 223c movs r2, #60 ; 0x3c
8004c2c: 2100 movs r1, #0
8004c2e: 5499 strb r1, [r3, r2]
return status;
8004c30: 2317 movs r3, #23
8004c32: 18fb adds r3, r7, r3
8004c34: 781b ldrb r3, [r3, #0]
}
8004c36: 0018 movs r0, r3
8004c38: 46bd mov sp, r7
8004c3a: b006 add sp, #24
8004c3c: bd80 pop {r7, pc}
8004c3e: 46c0 nop ; (mov r8, r8)
8004c40: 08007430 .word 0x08007430
8004c44: fffffbff .word 0xfffffbff
08004c48 <TIM_Base_SetConfig>:
* @param TIMx TIM peripheral
* @param Structure TIM Base configuration structure
* @retval None
*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
{
8004c48: b580 push {r7, lr}
8004c4a: b084 sub sp, #16
8004c4c: af00 add r7, sp, #0
8004c4e: 6078 str r0, [r7, #4]
8004c50: 6039 str r1, [r7, #0]
uint32_t tmpcr1;
tmpcr1 = TIMx->CR1;
8004c52: 687b ldr r3, [r7, #4]
8004c54: 681b ldr r3, [r3, #0]
8004c56: 60fb str r3, [r7, #12]
/* Set TIM Time Base Unit parameters ---------------------------------------*/
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
8004c58: 687b ldr r3, [r7, #4]
8004c5a: 4a30 ldr r2, [pc, #192] ; (8004d1c <TIM_Base_SetConfig+0xd4>)
8004c5c: 4293 cmp r3, r2
8004c5e: d008 beq.n 8004c72 <TIM_Base_SetConfig+0x2a>
8004c60: 687a ldr r2, [r7, #4]
8004c62: 2380 movs r3, #128 ; 0x80
8004c64: 05db lsls r3, r3, #23
8004c66: 429a cmp r2, r3
8004c68: d003 beq.n 8004c72 <TIM_Base_SetConfig+0x2a>
8004c6a: 687b ldr r3, [r7, #4]
8004c6c: 4a2c ldr r2, [pc, #176] ; (8004d20 <TIM_Base_SetConfig+0xd8>)
8004c6e: 4293 cmp r3, r2
8004c70: d108 bne.n 8004c84 <TIM_Base_SetConfig+0x3c>
{
/* Select the Counter Mode */
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
8004c72: 68fb ldr r3, [r7, #12]
8004c74: 2270 movs r2, #112 ; 0x70
8004c76: 4393 bics r3, r2
8004c78: 60fb str r3, [r7, #12]
tmpcr1 |= Structure->CounterMode;
8004c7a: 683b ldr r3, [r7, #0]
8004c7c: 685b ldr r3, [r3, #4]
8004c7e: 68fa ldr r2, [r7, #12]
8004c80: 4313 orrs r3, r2
8004c82: 60fb str r3, [r7, #12]
}
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
8004c84: 687b ldr r3, [r7, #4]
8004c86: 4a25 ldr r2, [pc, #148] ; (8004d1c <TIM_Base_SetConfig+0xd4>)
8004c88: 4293 cmp r3, r2
8004c8a: d014 beq.n 8004cb6 <TIM_Base_SetConfig+0x6e>
8004c8c: 687a ldr r2, [r7, #4]
8004c8e: 2380 movs r3, #128 ; 0x80
8004c90: 05db lsls r3, r3, #23
8004c92: 429a cmp r2, r3
8004c94: d00f beq.n 8004cb6 <TIM_Base_SetConfig+0x6e>
8004c96: 687b ldr r3, [r7, #4]
8004c98: 4a21 ldr r2, [pc, #132] ; (8004d20 <TIM_Base_SetConfig+0xd8>)
8004c9a: 4293 cmp r3, r2
8004c9c: d00b beq.n 8004cb6 <TIM_Base_SetConfig+0x6e>
8004c9e: 687b ldr r3, [r7, #4]
8004ca0: 4a20 ldr r2, [pc, #128] ; (8004d24 <TIM_Base_SetConfig+0xdc>)
8004ca2: 4293 cmp r3, r2
8004ca4: d007 beq.n 8004cb6 <TIM_Base_SetConfig+0x6e>
8004ca6: 687b ldr r3, [r7, #4]
8004ca8: 4a1f ldr r2, [pc, #124] ; (8004d28 <TIM_Base_SetConfig+0xe0>)
8004caa: 4293 cmp r3, r2
8004cac: d003 beq.n 8004cb6 <TIM_Base_SetConfig+0x6e>
8004cae: 687b ldr r3, [r7, #4]
8004cb0: 4a1e ldr r2, [pc, #120] ; (8004d2c <TIM_Base_SetConfig+0xe4>)
8004cb2: 4293 cmp r3, r2
8004cb4: d108 bne.n 8004cc8 <TIM_Base_SetConfig+0x80>
{
/* Set the clock division */
tmpcr1 &= ~TIM_CR1_CKD;
8004cb6: 68fb ldr r3, [r7, #12]
8004cb8: 4a1d ldr r2, [pc, #116] ; (8004d30 <TIM_Base_SetConfig+0xe8>)
8004cba: 4013 ands r3, r2
8004cbc: 60fb str r3, [r7, #12]
tmpcr1 |= (uint32_t)Structure->ClockDivision;
8004cbe: 683b ldr r3, [r7, #0]
8004cc0: 68db ldr r3, [r3, #12]
8004cc2: 68fa ldr r2, [r7, #12]
8004cc4: 4313 orrs r3, r2
8004cc6: 60fb str r3, [r7, #12]
}
/* Set the auto-reload preload */
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
8004cc8: 68fb ldr r3, [r7, #12]
8004cca: 2280 movs r2, #128 ; 0x80
8004ccc: 4393 bics r3, r2
8004cce: 001a movs r2, r3
8004cd0: 683b ldr r3, [r7, #0]
8004cd2: 695b ldr r3, [r3, #20]
8004cd4: 4313 orrs r3, r2
8004cd6: 60fb str r3, [r7, #12]
TIMx->CR1 = tmpcr1;
8004cd8: 687b ldr r3, [r7, #4]
8004cda: 68fa ldr r2, [r7, #12]
8004cdc: 601a str r2, [r3, #0]
/* Set the Autoreload value */
TIMx->ARR = (uint32_t)Structure->Period ;
8004cde: 683b ldr r3, [r7, #0]
8004ce0: 689a ldr r2, [r3, #8]
8004ce2: 687b ldr r3, [r7, #4]
8004ce4: 62da str r2, [r3, #44] ; 0x2c
/* Set the Prescaler value */
TIMx->PSC = Structure->Prescaler;
8004ce6: 683b ldr r3, [r7, #0]
8004ce8: 681a ldr r2, [r3, #0]
8004cea: 687b ldr r3, [r7, #4]
8004cec: 629a str r2, [r3, #40] ; 0x28
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
8004cee: 687b ldr r3, [r7, #4]
8004cf0: 4a0a ldr r2, [pc, #40] ; (8004d1c <TIM_Base_SetConfig+0xd4>)
8004cf2: 4293 cmp r3, r2
8004cf4: d007 beq.n 8004d06 <TIM_Base_SetConfig+0xbe>
8004cf6: 687b ldr r3, [r7, #4]
8004cf8: 4a0b ldr r2, [pc, #44] ; (8004d28 <TIM_Base_SetConfig+0xe0>)
8004cfa: 4293 cmp r3, r2
8004cfc: d003 beq.n 8004d06 <TIM_Base_SetConfig+0xbe>
8004cfe: 687b ldr r3, [r7, #4]
8004d00: 4a0a ldr r2, [pc, #40] ; (8004d2c <TIM_Base_SetConfig+0xe4>)
8004d02: 4293 cmp r3, r2
8004d04: d103 bne.n 8004d0e <TIM_Base_SetConfig+0xc6>
{
/* Set the Repetition Counter value */
TIMx->RCR = Structure->RepetitionCounter;
8004d06: 683b ldr r3, [r7, #0]
8004d08: 691a ldr r2, [r3, #16]
8004d0a: 687b ldr r3, [r7, #4]
8004d0c: 631a str r2, [r3, #48] ; 0x30
}
/* Generate an update event to reload the Prescaler
and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
8004d0e: 687b ldr r3, [r7, #4]
8004d10: 2201 movs r2, #1
8004d12: 615a str r2, [r3, #20]
}
8004d14: 46c0 nop ; (mov r8, r8)
8004d16: 46bd mov sp, r7
8004d18: b004 add sp, #16
8004d1a: bd80 pop {r7, pc}
8004d1c: 40012c00 .word 0x40012c00
8004d20: 40000400 .word 0x40000400
8004d24: 40002000 .word 0x40002000
8004d28: 40014400 .word 0x40014400
8004d2c: 40014800 .word 0x40014800
8004d30: fffffcff .word 0xfffffcff
08004d34 <TIM_OC1_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
8004d34: b580 push {r7, lr}
8004d36: b086 sub sp, #24
8004d38: af00 add r7, sp, #0
8004d3a: 6078 str r0, [r7, #4]
8004d3c: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 1: Reset the CC1E Bit */
TIMx->CCER &= ~TIM_CCER_CC1E;
8004d3e: 687b ldr r3, [r7, #4]
8004d40: 6a1b ldr r3, [r3, #32]
8004d42: 2201 movs r2, #1
8004d44: 4393 bics r3, r2
8004d46: 001a movs r2, r3
8004d48: 687b ldr r3, [r7, #4]
8004d4a: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8004d4c: 687b ldr r3, [r7, #4]
8004d4e: 6a1b ldr r3, [r3, #32]
8004d50: 617b str r3, [r7, #20]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8004d52: 687b ldr r3, [r7, #4]
8004d54: 685b ldr r3, [r3, #4]
8004d56: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
8004d58: 687b ldr r3, [r7, #4]
8004d5a: 699b ldr r3, [r3, #24]
8004d5c: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~TIM_CCMR1_OC1M;
8004d5e: 68fb ldr r3, [r7, #12]
8004d60: 4a2e ldr r2, [pc, #184] ; (8004e1c <TIM_OC1_SetConfig+0xe8>)
8004d62: 4013 ands r3, r2
8004d64: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC1S;
8004d66: 68fb ldr r3, [r7, #12]
8004d68: 2203 movs r2, #3
8004d6a: 4393 bics r3, r2
8004d6c: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
8004d6e: 683b ldr r3, [r7, #0]
8004d70: 681b ldr r3, [r3, #0]
8004d72: 68fa ldr r2, [r7, #12]
8004d74: 4313 orrs r3, r2
8004d76: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC1P;
8004d78: 697b ldr r3, [r7, #20]
8004d7a: 2202 movs r2, #2
8004d7c: 4393 bics r3, r2
8004d7e: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= OC_Config->OCPolarity;
8004d80: 683b ldr r3, [r7, #0]
8004d82: 689b ldr r3, [r3, #8]
8004d84: 697a ldr r2, [r7, #20]
8004d86: 4313 orrs r3, r2
8004d88: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
8004d8a: 687b ldr r3, [r7, #4]
8004d8c: 4a24 ldr r2, [pc, #144] ; (8004e20 <TIM_OC1_SetConfig+0xec>)
8004d8e: 4293 cmp r3, r2
8004d90: d007 beq.n 8004da2 <TIM_OC1_SetConfig+0x6e>
8004d92: 687b ldr r3, [r7, #4]
8004d94: 4a23 ldr r2, [pc, #140] ; (8004e24 <TIM_OC1_SetConfig+0xf0>)
8004d96: 4293 cmp r3, r2
8004d98: d003 beq.n 8004da2 <TIM_OC1_SetConfig+0x6e>
8004d9a: 687b ldr r3, [r7, #4]
8004d9c: 4a22 ldr r2, [pc, #136] ; (8004e28 <TIM_OC1_SetConfig+0xf4>)
8004d9e: 4293 cmp r3, r2
8004da0: d10c bne.n 8004dbc <TIM_OC1_SetConfig+0x88>
{
/* Check parameters */
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC1NP;
8004da2: 697b ldr r3, [r7, #20]
8004da4: 2208 movs r2, #8
8004da6: 4393 bics r3, r2
8004da8: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= OC_Config->OCNPolarity;
8004daa: 683b ldr r3, [r7, #0]
8004dac: 68db ldr r3, [r3, #12]
8004dae: 697a ldr r2, [r7, #20]
8004db0: 4313 orrs r3, r2
8004db2: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC1NE;
8004db4: 697b ldr r3, [r7, #20]
8004db6: 2204 movs r2, #4
8004db8: 4393 bics r3, r2
8004dba: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
8004dbc: 687b ldr r3, [r7, #4]
8004dbe: 4a18 ldr r2, [pc, #96] ; (8004e20 <TIM_OC1_SetConfig+0xec>)
8004dc0: 4293 cmp r3, r2
8004dc2: d007 beq.n 8004dd4 <TIM_OC1_SetConfig+0xa0>
8004dc4: 687b ldr r3, [r7, #4]
8004dc6: 4a17 ldr r2, [pc, #92] ; (8004e24 <TIM_OC1_SetConfig+0xf0>)
8004dc8: 4293 cmp r3, r2
8004dca: d003 beq.n 8004dd4 <TIM_OC1_SetConfig+0xa0>
8004dcc: 687b ldr r3, [r7, #4]
8004dce: 4a16 ldr r2, [pc, #88] ; (8004e28 <TIM_OC1_SetConfig+0xf4>)
8004dd0: 4293 cmp r3, r2
8004dd2: d111 bne.n 8004df8 <TIM_OC1_SetConfig+0xc4>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS1;
8004dd4: 693b ldr r3, [r7, #16]
8004dd6: 4a15 ldr r2, [pc, #84] ; (8004e2c <TIM_OC1_SetConfig+0xf8>)
8004dd8: 4013 ands r3, r2
8004dda: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS1N;
8004ddc: 693b ldr r3, [r7, #16]
8004dde: 4a14 ldr r2, [pc, #80] ; (8004e30 <TIM_OC1_SetConfig+0xfc>)
8004de0: 4013 ands r3, r2
8004de2: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= OC_Config->OCIdleState;
8004de4: 683b ldr r3, [r7, #0]
8004de6: 695b ldr r3, [r3, #20]
8004de8: 693a ldr r2, [r7, #16]
8004dea: 4313 orrs r3, r2
8004dec: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= OC_Config->OCNIdleState;
8004dee: 683b ldr r3, [r7, #0]
8004df0: 699b ldr r3, [r3, #24]
8004df2: 693a ldr r2, [r7, #16]
8004df4: 4313 orrs r3, r2
8004df6: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8004df8: 687b ldr r3, [r7, #4]
8004dfa: 693a ldr r2, [r7, #16]
8004dfc: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
8004dfe: 687b ldr r3, [r7, #4]
8004e00: 68fa ldr r2, [r7, #12]
8004e02: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR1 = OC_Config->Pulse;
8004e04: 683b ldr r3, [r7, #0]
8004e06: 685a ldr r2, [r3, #4]
8004e08: 687b ldr r3, [r7, #4]
8004e0a: 635a str r2, [r3, #52] ; 0x34
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8004e0c: 687b ldr r3, [r7, #4]
8004e0e: 697a ldr r2, [r7, #20]
8004e10: 621a str r2, [r3, #32]
}
8004e12: 46c0 nop ; (mov r8, r8)
8004e14: 46bd mov sp, r7
8004e16: b006 add sp, #24
8004e18: bd80 pop {r7, pc}
8004e1a: 46c0 nop ; (mov r8, r8)
8004e1c: fffeff8f .word 0xfffeff8f
8004e20: 40012c00 .word 0x40012c00
8004e24: 40014400 .word 0x40014400
8004e28: 40014800 .word 0x40014800
8004e2c: fffffeff .word 0xfffffeff
8004e30: fffffdff .word 0xfffffdff
08004e34 <TIM_OC2_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
8004e34: b580 push {r7, lr}
8004e36: b086 sub sp, #24
8004e38: af00 add r7, sp, #0
8004e3a: 6078 str r0, [r7, #4]
8004e3c: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
8004e3e: 687b ldr r3, [r7, #4]
8004e40: 6a1b ldr r3, [r3, #32]
8004e42: 2210 movs r2, #16
8004e44: 4393 bics r3, r2
8004e46: 001a movs r2, r3
8004e48: 687b ldr r3, [r7, #4]
8004e4a: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8004e4c: 687b ldr r3, [r7, #4]
8004e4e: 6a1b ldr r3, [r3, #32]
8004e50: 617b str r3, [r7, #20]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8004e52: 687b ldr r3, [r7, #4]
8004e54: 685b ldr r3, [r3, #4]
8004e56: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
8004e58: 687b ldr r3, [r7, #4]
8004e5a: 699b ldr r3, [r3, #24]
8004e5c: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR1_OC2M;
8004e5e: 68fb ldr r3, [r7, #12]
8004e60: 4a2c ldr r2, [pc, #176] ; (8004f14 <TIM_OC2_SetConfig+0xe0>)
8004e62: 4013 ands r3, r2
8004e64: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC2S;
8004e66: 68fb ldr r3, [r7, #12]
8004e68: 4a2b ldr r2, [pc, #172] ; (8004f18 <TIM_OC2_SetConfig+0xe4>)
8004e6a: 4013 ands r3, r2
8004e6c: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
8004e6e: 683b ldr r3, [r7, #0]
8004e70: 681b ldr r3, [r3, #0]
8004e72: 021b lsls r3, r3, #8
8004e74: 68fa ldr r2, [r7, #12]
8004e76: 4313 orrs r3, r2
8004e78: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC2P;
8004e7a: 697b ldr r3, [r7, #20]
8004e7c: 2220 movs r2, #32
8004e7e: 4393 bics r3, r2
8004e80: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 4U);
8004e82: 683b ldr r3, [r7, #0]
8004e84: 689b ldr r3, [r3, #8]
8004e86: 011b lsls r3, r3, #4
8004e88: 697a ldr r2, [r7, #20]
8004e8a: 4313 orrs r3, r2
8004e8c: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
8004e8e: 687b ldr r3, [r7, #4]
8004e90: 4a22 ldr r2, [pc, #136] ; (8004f1c <TIM_OC2_SetConfig+0xe8>)
8004e92: 4293 cmp r3, r2
8004e94: d10d bne.n 8004eb2 <TIM_OC2_SetConfig+0x7e>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC2NP;
8004e96: 697b ldr r3, [r7, #20]
8004e98: 2280 movs r2, #128 ; 0x80
8004e9a: 4393 bics r3, r2
8004e9c: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 4U);
8004e9e: 683b ldr r3, [r7, #0]
8004ea0: 68db ldr r3, [r3, #12]
8004ea2: 011b lsls r3, r3, #4
8004ea4: 697a ldr r2, [r7, #20]
8004ea6: 4313 orrs r3, r2
8004ea8: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC2NE;
8004eaa: 697b ldr r3, [r7, #20]
8004eac: 2240 movs r2, #64 ; 0x40
8004eae: 4393 bics r3, r2
8004eb0: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
8004eb2: 687b ldr r3, [r7, #4]
8004eb4: 4a19 ldr r2, [pc, #100] ; (8004f1c <TIM_OC2_SetConfig+0xe8>)
8004eb6: 4293 cmp r3, r2
8004eb8: d007 beq.n 8004eca <TIM_OC2_SetConfig+0x96>
8004eba: 687b ldr r3, [r7, #4]
8004ebc: 4a18 ldr r2, [pc, #96] ; (8004f20 <TIM_OC2_SetConfig+0xec>)
8004ebe: 4293 cmp r3, r2
8004ec0: d003 beq.n 8004eca <TIM_OC2_SetConfig+0x96>
8004ec2: 687b ldr r3, [r7, #4]
8004ec4: 4a17 ldr r2, [pc, #92] ; (8004f24 <TIM_OC2_SetConfig+0xf0>)
8004ec6: 4293 cmp r3, r2
8004ec8: d113 bne.n 8004ef2 <TIM_OC2_SetConfig+0xbe>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS2;
8004eca: 693b ldr r3, [r7, #16]
8004ecc: 4a16 ldr r2, [pc, #88] ; (8004f28 <TIM_OC2_SetConfig+0xf4>)
8004ece: 4013 ands r3, r2
8004ed0: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS2N;
8004ed2: 693b ldr r3, [r7, #16]
8004ed4: 4a15 ldr r2, [pc, #84] ; (8004f2c <TIM_OC2_SetConfig+0xf8>)
8004ed6: 4013 ands r3, r2
8004ed8: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 2U);
8004eda: 683b ldr r3, [r7, #0]
8004edc: 695b ldr r3, [r3, #20]
8004ede: 009b lsls r3, r3, #2
8004ee0: 693a ldr r2, [r7, #16]
8004ee2: 4313 orrs r3, r2
8004ee4: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 2U);
8004ee6: 683b ldr r3, [r7, #0]
8004ee8: 699b ldr r3, [r3, #24]
8004eea: 009b lsls r3, r3, #2
8004eec: 693a ldr r2, [r7, #16]
8004eee: 4313 orrs r3, r2
8004ef0: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8004ef2: 687b ldr r3, [r7, #4]
8004ef4: 693a ldr r2, [r7, #16]
8004ef6: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
8004ef8: 687b ldr r3, [r7, #4]
8004efa: 68fa ldr r2, [r7, #12]
8004efc: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR2 = OC_Config->Pulse;
8004efe: 683b ldr r3, [r7, #0]
8004f00: 685a ldr r2, [r3, #4]
8004f02: 687b ldr r3, [r7, #4]
8004f04: 639a str r2, [r3, #56] ; 0x38
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8004f06: 687b ldr r3, [r7, #4]
8004f08: 697a ldr r2, [r7, #20]
8004f0a: 621a str r2, [r3, #32]
}
8004f0c: 46c0 nop ; (mov r8, r8)
8004f0e: 46bd mov sp, r7
8004f10: b006 add sp, #24
8004f12: bd80 pop {r7, pc}
8004f14: feff8fff .word 0xfeff8fff
8004f18: fffffcff .word 0xfffffcff
8004f1c: 40012c00 .word 0x40012c00
8004f20: 40014400 .word 0x40014400
8004f24: 40014800 .word 0x40014800
8004f28: fffffbff .word 0xfffffbff
8004f2c: fffff7ff .word 0xfffff7ff
08004f30 <TIM_OC3_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
8004f30: b580 push {r7, lr}
8004f32: b086 sub sp, #24
8004f34: af00 add r7, sp, #0
8004f36: 6078 str r0, [r7, #4]
8004f38: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 3: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC3E;
8004f3a: 687b ldr r3, [r7, #4]
8004f3c: 6a1b ldr r3, [r3, #32]
8004f3e: 4a33 ldr r2, [pc, #204] ; (800500c <TIM_OC3_SetConfig+0xdc>)
8004f40: 401a ands r2, r3
8004f42: 687b ldr r3, [r7, #4]
8004f44: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8004f46: 687b ldr r3, [r7, #4]
8004f48: 6a1b ldr r3, [r3, #32]
8004f4a: 617b str r3, [r7, #20]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8004f4c: 687b ldr r3, [r7, #4]
8004f4e: 685b ldr r3, [r3, #4]
8004f50: 613b str r3, [r7, #16]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
8004f52: 687b ldr r3, [r7, #4]
8004f54: 69db ldr r3, [r3, #28]
8004f56: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC3M;
8004f58: 68fb ldr r3, [r7, #12]
8004f5a: 4a2d ldr r2, [pc, #180] ; (8005010 <TIM_OC3_SetConfig+0xe0>)
8004f5c: 4013 ands r3, r2
8004f5e: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC3S;
8004f60: 68fb ldr r3, [r7, #12]
8004f62: 2203 movs r2, #3
8004f64: 4393 bics r3, r2
8004f66: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
8004f68: 683b ldr r3, [r7, #0]
8004f6a: 681b ldr r3, [r3, #0]
8004f6c: 68fa ldr r2, [r7, #12]
8004f6e: 4313 orrs r3, r2
8004f70: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC3P;
8004f72: 697b ldr r3, [r7, #20]
8004f74: 4a27 ldr r2, [pc, #156] ; (8005014 <TIM_OC3_SetConfig+0xe4>)
8004f76: 4013 ands r3, r2
8004f78: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 8U);
8004f7a: 683b ldr r3, [r7, #0]
8004f7c: 689b ldr r3, [r3, #8]
8004f7e: 021b lsls r3, r3, #8
8004f80: 697a ldr r2, [r7, #20]
8004f82: 4313 orrs r3, r2
8004f84: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
8004f86: 687b ldr r3, [r7, #4]
8004f88: 4a23 ldr r2, [pc, #140] ; (8005018 <TIM_OC3_SetConfig+0xe8>)
8004f8a: 4293 cmp r3, r2
8004f8c: d10d bne.n 8004faa <TIM_OC3_SetConfig+0x7a>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC3NP;
8004f8e: 697b ldr r3, [r7, #20]
8004f90: 4a22 ldr r2, [pc, #136] ; (800501c <TIM_OC3_SetConfig+0xec>)
8004f92: 4013 ands r3, r2
8004f94: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 8U);
8004f96: 683b ldr r3, [r7, #0]
8004f98: 68db ldr r3, [r3, #12]
8004f9a: 021b lsls r3, r3, #8
8004f9c: 697a ldr r2, [r7, #20]
8004f9e: 4313 orrs r3, r2
8004fa0: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC3NE;
8004fa2: 697b ldr r3, [r7, #20]
8004fa4: 4a1e ldr r2, [pc, #120] ; (8005020 <TIM_OC3_SetConfig+0xf0>)
8004fa6: 4013 ands r3, r2
8004fa8: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
8004faa: 687b ldr r3, [r7, #4]
8004fac: 4a1a ldr r2, [pc, #104] ; (8005018 <TIM_OC3_SetConfig+0xe8>)
8004fae: 4293 cmp r3, r2
8004fb0: d007 beq.n 8004fc2 <TIM_OC3_SetConfig+0x92>
8004fb2: 687b ldr r3, [r7, #4]
8004fb4: 4a1b ldr r2, [pc, #108] ; (8005024 <TIM_OC3_SetConfig+0xf4>)
8004fb6: 4293 cmp r3, r2
8004fb8: d003 beq.n 8004fc2 <TIM_OC3_SetConfig+0x92>
8004fba: 687b ldr r3, [r7, #4]
8004fbc: 4a1a ldr r2, [pc, #104] ; (8005028 <TIM_OC3_SetConfig+0xf8>)
8004fbe: 4293 cmp r3, r2
8004fc0: d113 bne.n 8004fea <TIM_OC3_SetConfig+0xba>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS3;
8004fc2: 693b ldr r3, [r7, #16]
8004fc4: 4a19 ldr r2, [pc, #100] ; (800502c <TIM_OC3_SetConfig+0xfc>)
8004fc6: 4013 ands r3, r2
8004fc8: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS3N;
8004fca: 693b ldr r3, [r7, #16]
8004fcc: 4a18 ldr r2, [pc, #96] ; (8005030 <TIM_OC3_SetConfig+0x100>)
8004fce: 4013 ands r3, r2
8004fd0: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 4U);
8004fd2: 683b ldr r3, [r7, #0]
8004fd4: 695b ldr r3, [r3, #20]
8004fd6: 011b lsls r3, r3, #4
8004fd8: 693a ldr r2, [r7, #16]
8004fda: 4313 orrs r3, r2
8004fdc: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 4U);
8004fde: 683b ldr r3, [r7, #0]
8004fe0: 699b ldr r3, [r3, #24]
8004fe2: 011b lsls r3, r3, #4
8004fe4: 693a ldr r2, [r7, #16]
8004fe6: 4313 orrs r3, r2
8004fe8: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8004fea: 687b ldr r3, [r7, #4]
8004fec: 693a ldr r2, [r7, #16]
8004fee: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
8004ff0: 687b ldr r3, [r7, #4]
8004ff2: 68fa ldr r2, [r7, #12]
8004ff4: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR3 = OC_Config->Pulse;
8004ff6: 683b ldr r3, [r7, #0]
8004ff8: 685a ldr r2, [r3, #4]
8004ffa: 687b ldr r3, [r7, #4]
8004ffc: 63da str r2, [r3, #60] ; 0x3c
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8004ffe: 687b ldr r3, [r7, #4]
8005000: 697a ldr r2, [r7, #20]
8005002: 621a str r2, [r3, #32]
}
8005004: 46c0 nop ; (mov r8, r8)
8005006: 46bd mov sp, r7
8005008: b006 add sp, #24
800500a: bd80 pop {r7, pc}
800500c: fffffeff .word 0xfffffeff
8005010: fffeff8f .word 0xfffeff8f
8005014: fffffdff .word 0xfffffdff
8005018: 40012c00 .word 0x40012c00
800501c: fffff7ff .word 0xfffff7ff
8005020: fffffbff .word 0xfffffbff
8005024: 40014400 .word 0x40014400
8005028: 40014800 .word 0x40014800
800502c: ffffefff .word 0xffffefff
8005030: ffffdfff .word 0xffffdfff
08005034 <TIM_OC4_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
8005034: b580 push {r7, lr}
8005036: b086 sub sp, #24
8005038: af00 add r7, sp, #0
800503a: 6078 str r0, [r7, #4]
800503c: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 4: Reset the CC4E Bit */
TIMx->CCER &= ~TIM_CCER_CC4E;
800503e: 687b ldr r3, [r7, #4]
8005040: 6a1b ldr r3, [r3, #32]
8005042: 4a26 ldr r2, [pc, #152] ; (80050dc <TIM_OC4_SetConfig+0xa8>)
8005044: 401a ands r2, r3
8005046: 687b ldr r3, [r7, #4]
8005048: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
800504a: 687b ldr r3, [r7, #4]
800504c: 6a1b ldr r3, [r3, #32]
800504e: 613b str r3, [r7, #16]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8005050: 687b ldr r3, [r7, #4]
8005052: 685b ldr r3, [r3, #4]
8005054: 617b str r3, [r7, #20]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
8005056: 687b ldr r3, [r7, #4]
8005058: 69db ldr r3, [r3, #28]
800505a: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC4M;
800505c: 68fb ldr r3, [r7, #12]
800505e: 4a20 ldr r2, [pc, #128] ; (80050e0 <TIM_OC4_SetConfig+0xac>)
8005060: 4013 ands r3, r2
8005062: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC4S;
8005064: 68fb ldr r3, [r7, #12]
8005066: 4a1f ldr r2, [pc, #124] ; (80050e4 <TIM_OC4_SetConfig+0xb0>)
8005068: 4013 ands r3, r2
800506a: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
800506c: 683b ldr r3, [r7, #0]
800506e: 681b ldr r3, [r3, #0]
8005070: 021b lsls r3, r3, #8
8005072: 68fa ldr r2, [r7, #12]
8005074: 4313 orrs r3, r2
8005076: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC4P;
8005078: 693b ldr r3, [r7, #16]
800507a: 4a1b ldr r2, [pc, #108] ; (80050e8 <TIM_OC4_SetConfig+0xb4>)
800507c: 4013 ands r3, r2
800507e: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 12U);
8005080: 683b ldr r3, [r7, #0]
8005082: 689b ldr r3, [r3, #8]
8005084: 031b lsls r3, r3, #12
8005086: 693a ldr r2, [r7, #16]
8005088: 4313 orrs r3, r2
800508a: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
800508c: 687b ldr r3, [r7, #4]
800508e: 4a17 ldr r2, [pc, #92] ; (80050ec <TIM_OC4_SetConfig+0xb8>)
8005090: 4293 cmp r3, r2
8005092: d007 beq.n 80050a4 <TIM_OC4_SetConfig+0x70>
8005094: 687b ldr r3, [r7, #4]
8005096: 4a16 ldr r2, [pc, #88] ; (80050f0 <TIM_OC4_SetConfig+0xbc>)
8005098: 4293 cmp r3, r2
800509a: d003 beq.n 80050a4 <TIM_OC4_SetConfig+0x70>
800509c: 687b ldr r3, [r7, #4]
800509e: 4a15 ldr r2, [pc, #84] ; (80050f4 <TIM_OC4_SetConfig+0xc0>)
80050a0: 4293 cmp r3, r2
80050a2: d109 bne.n 80050b8 <TIM_OC4_SetConfig+0x84>
{
/* Check parameters */
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS4;
80050a4: 697b ldr r3, [r7, #20]
80050a6: 4a14 ldr r2, [pc, #80] ; (80050f8 <TIM_OC4_SetConfig+0xc4>)
80050a8: 4013 ands r3, r2
80050aa: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 6U);
80050ac: 683b ldr r3, [r7, #0]
80050ae: 695b ldr r3, [r3, #20]
80050b0: 019b lsls r3, r3, #6
80050b2: 697a ldr r2, [r7, #20]
80050b4: 4313 orrs r3, r2
80050b6: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
80050b8: 687b ldr r3, [r7, #4]
80050ba: 697a ldr r2, [r7, #20]
80050bc: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
80050be: 687b ldr r3, [r7, #4]
80050c0: 68fa ldr r2, [r7, #12]
80050c2: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR4 = OC_Config->Pulse;
80050c4: 683b ldr r3, [r7, #0]
80050c6: 685a ldr r2, [r3, #4]
80050c8: 687b ldr r3, [r7, #4]
80050ca: 641a str r2, [r3, #64] ; 0x40
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
80050cc: 687b ldr r3, [r7, #4]
80050ce: 693a ldr r2, [r7, #16]
80050d0: 621a str r2, [r3, #32]
}
80050d2: 46c0 nop ; (mov r8, r8)
80050d4: 46bd mov sp, r7
80050d6: b006 add sp, #24
80050d8: bd80 pop {r7, pc}
80050da: 46c0 nop ; (mov r8, r8)
80050dc: ffffefff .word 0xffffefff
80050e0: feff8fff .word 0xfeff8fff
80050e4: fffffcff .word 0xfffffcff
80050e8: ffffdfff .word 0xffffdfff
80050ec: 40012c00 .word 0x40012c00
80050f0: 40014400 .word 0x40014400
80050f4: 40014800 .word 0x40014800
80050f8: ffffbfff .word 0xffffbfff
080050fc <TIM_OC5_SetConfig>:
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
const TIM_OC_InitTypeDef *OC_Config)
{
80050fc: b580 push {r7, lr}
80050fe: b086 sub sp, #24
8005100: af00 add r7, sp, #0
8005102: 6078 str r0, [r7, #4]
8005104: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the output: Reset the CCxE Bit */
TIMx->CCER &= ~TIM_CCER_CC5E;
8005106: 687b ldr r3, [r7, #4]
8005108: 6a1b ldr r3, [r3, #32]
800510a: 4a23 ldr r2, [pc, #140] ; (8005198 <TIM_OC5_SetConfig+0x9c>)
800510c: 401a ands r2, r3
800510e: 687b ldr r3, [r7, #4]
8005110: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8005112: 687b ldr r3, [r7, #4]
8005114: 6a1b ldr r3, [r3, #32]
8005116: 613b str r3, [r7, #16]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8005118: 687b ldr r3, [r7, #4]
800511a: 685b ldr r3, [r3, #4]
800511c: 617b str r3, [r7, #20]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR3;
800511e: 687b ldr r3, [r7, #4]
8005120: 6d5b ldr r3, [r3, #84] ; 0x54
8005122: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~(TIM_CCMR3_OC5M);
8005124: 68fb ldr r3, [r7, #12]
8005126: 4a1d ldr r2, [pc, #116] ; (800519c <TIM_OC5_SetConfig+0xa0>)
8005128: 4013 ands r3, r2
800512a: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
800512c: 683b ldr r3, [r7, #0]
800512e: 681b ldr r3, [r3, #0]
8005130: 68fa ldr r2, [r7, #12]
8005132: 4313 orrs r3, r2
8005134: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC5P;
8005136: 693b ldr r3, [r7, #16]
8005138: 4a19 ldr r2, [pc, #100] ; (80051a0 <TIM_OC5_SetConfig+0xa4>)
800513a: 4013 ands r3, r2
800513c: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 16U);
800513e: 683b ldr r3, [r7, #0]
8005140: 689b ldr r3, [r3, #8]
8005142: 041b lsls r3, r3, #16
8005144: 693a ldr r2, [r7, #16]
8005146: 4313 orrs r3, r2
8005148: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
800514a: 687b ldr r3, [r7, #4]
800514c: 4a15 ldr r2, [pc, #84] ; (80051a4 <TIM_OC5_SetConfig+0xa8>)
800514e: 4293 cmp r3, r2
8005150: d007 beq.n 8005162 <TIM_OC5_SetConfig+0x66>
8005152: 687b ldr r3, [r7, #4]
8005154: 4a14 ldr r2, [pc, #80] ; (80051a8 <TIM_OC5_SetConfig+0xac>)
8005156: 4293 cmp r3, r2
8005158: d003 beq.n 8005162 <TIM_OC5_SetConfig+0x66>
800515a: 687b ldr r3, [r7, #4]
800515c: 4a13 ldr r2, [pc, #76] ; (80051ac <TIM_OC5_SetConfig+0xb0>)
800515e: 4293 cmp r3, r2
8005160: d109 bne.n 8005176 <TIM_OC5_SetConfig+0x7a>
{
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS5;
8005162: 697b ldr r3, [r7, #20]
8005164: 4a0c ldr r2, [pc, #48] ; (8005198 <TIM_OC5_SetConfig+0x9c>)
8005166: 4013 ands r3, r2
8005168: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 8U);
800516a: 683b ldr r3, [r7, #0]
800516c: 695b ldr r3, [r3, #20]
800516e: 021b lsls r3, r3, #8
8005170: 697a ldr r2, [r7, #20]
8005172: 4313 orrs r3, r2
8005174: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8005176: 687b ldr r3, [r7, #4]
8005178: 697a ldr r2, [r7, #20]
800517a: 605a str r2, [r3, #4]
/* Write to TIMx CCMR3 */
TIMx->CCMR3 = tmpccmrx;
800517c: 687b ldr r3, [r7, #4]
800517e: 68fa ldr r2, [r7, #12]
8005180: 655a str r2, [r3, #84] ; 0x54
/* Set the Capture Compare Register value */
TIMx->CCR5 = OC_Config->Pulse;
8005182: 683b ldr r3, [r7, #0]
8005184: 685a ldr r2, [r3, #4]
8005186: 687b ldr r3, [r7, #4]
8005188: 659a str r2, [r3, #88] ; 0x58
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
800518a: 687b ldr r3, [r7, #4]
800518c: 693a ldr r2, [r7, #16]
800518e: 621a str r2, [r3, #32]
}
8005190: 46c0 nop ; (mov r8, r8)
8005192: 46bd mov sp, r7
8005194: b006 add sp, #24
8005196: bd80 pop {r7, pc}
8005198: fffeffff .word 0xfffeffff
800519c: fffeff8f .word 0xfffeff8f
80051a0: fffdffff .word 0xfffdffff
80051a4: 40012c00 .word 0x40012c00
80051a8: 40014400 .word 0x40014400
80051ac: 40014800 .word 0x40014800
080051b0 <TIM_OC6_SetConfig>:
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
const TIM_OC_InitTypeDef *OC_Config)
{
80051b0: b580 push {r7, lr}
80051b2: b086 sub sp, #24
80051b4: af00 add r7, sp, #0
80051b6: 6078 str r0, [r7, #4]
80051b8: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the output: Reset the CCxE Bit */
TIMx->CCER &= ~TIM_CCER_CC6E;
80051ba: 687b ldr r3, [r7, #4]
80051bc: 6a1b ldr r3, [r3, #32]
80051be: 4a24 ldr r2, [pc, #144] ; (8005250 <TIM_OC6_SetConfig+0xa0>)
80051c0: 401a ands r2, r3
80051c2: 687b ldr r3, [r7, #4]
80051c4: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
80051c6: 687b ldr r3, [r7, #4]
80051c8: 6a1b ldr r3, [r3, #32]
80051ca: 613b str r3, [r7, #16]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
80051cc: 687b ldr r3, [r7, #4]
80051ce: 685b ldr r3, [r3, #4]
80051d0: 617b str r3, [r7, #20]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR3;
80051d2: 687b ldr r3, [r7, #4]
80051d4: 6d5b ldr r3, [r3, #84] ; 0x54
80051d6: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~(TIM_CCMR3_OC6M);
80051d8: 68fb ldr r3, [r7, #12]
80051da: 4a1e ldr r2, [pc, #120] ; (8005254 <TIM_OC6_SetConfig+0xa4>)
80051dc: 4013 ands r3, r2
80051de: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
80051e0: 683b ldr r3, [r7, #0]
80051e2: 681b ldr r3, [r3, #0]
80051e4: 021b lsls r3, r3, #8
80051e6: 68fa ldr r2, [r7, #12]
80051e8: 4313 orrs r3, r2
80051ea: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= (uint32_t)~TIM_CCER_CC6P;
80051ec: 693b ldr r3, [r7, #16]
80051ee: 4a1a ldr r2, [pc, #104] ; (8005258 <TIM_OC6_SetConfig+0xa8>)
80051f0: 4013 ands r3, r2
80051f2: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 20U);
80051f4: 683b ldr r3, [r7, #0]
80051f6: 689b ldr r3, [r3, #8]
80051f8: 051b lsls r3, r3, #20
80051fa: 693a ldr r2, [r7, #16]
80051fc: 4313 orrs r3, r2
80051fe: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
8005200: 687b ldr r3, [r7, #4]
8005202: 4a16 ldr r2, [pc, #88] ; (800525c <TIM_OC6_SetConfig+0xac>)
8005204: 4293 cmp r3, r2
8005206: d007 beq.n 8005218 <TIM_OC6_SetConfig+0x68>
8005208: 687b ldr r3, [r7, #4]
800520a: 4a15 ldr r2, [pc, #84] ; (8005260 <TIM_OC6_SetConfig+0xb0>)
800520c: 4293 cmp r3, r2
800520e: d003 beq.n 8005218 <TIM_OC6_SetConfig+0x68>
8005210: 687b ldr r3, [r7, #4]
8005212: 4a14 ldr r2, [pc, #80] ; (8005264 <TIM_OC6_SetConfig+0xb4>)
8005214: 4293 cmp r3, r2
8005216: d109 bne.n 800522c <TIM_OC6_SetConfig+0x7c>
{
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS6;
8005218: 697b ldr r3, [r7, #20]
800521a: 4a13 ldr r2, [pc, #76] ; (8005268 <TIM_OC6_SetConfig+0xb8>)
800521c: 4013 ands r3, r2
800521e: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 10U);
8005220: 683b ldr r3, [r7, #0]
8005222: 695b ldr r3, [r3, #20]
8005224: 029b lsls r3, r3, #10
8005226: 697a ldr r2, [r7, #20]
8005228: 4313 orrs r3, r2
800522a: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
800522c: 687b ldr r3, [r7, #4]
800522e: 697a ldr r2, [r7, #20]
8005230: 605a str r2, [r3, #4]
/* Write to TIMx CCMR3 */
TIMx->CCMR3 = tmpccmrx;
8005232: 687b ldr r3, [r7, #4]
8005234: 68fa ldr r2, [r7, #12]
8005236: 655a str r2, [r3, #84] ; 0x54
/* Set the Capture Compare Register value */
TIMx->CCR6 = OC_Config->Pulse;
8005238: 683b ldr r3, [r7, #0]
800523a: 685a ldr r2, [r3, #4]
800523c: 687b ldr r3, [r7, #4]
800523e: 65da str r2, [r3, #92] ; 0x5c
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8005240: 687b ldr r3, [r7, #4]
8005242: 693a ldr r2, [r7, #16]
8005244: 621a str r2, [r3, #32]
}
8005246: 46c0 nop ; (mov r8, r8)
8005248: 46bd mov sp, r7
800524a: b006 add sp, #24
800524c: bd80 pop {r7, pc}
800524e: 46c0 nop ; (mov r8, r8)
8005250: ffefffff .word 0xffefffff
8005254: feff8fff .word 0xfeff8fff
8005258: ffdfffff .word 0xffdfffff
800525c: 40012c00 .word 0x40012c00
8005260: 40014400 .word 0x40014400
8005264: 40014800 .word 0x40014800
8005268: fffbffff .word 0xfffbffff
0800526c <TIM_CCxChannelCmd>:
* @param ChannelState specifies the TIM Channel CCxE bit new state.
* This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
* @retval None
*/
void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
{
800526c: b580 push {r7, lr}
800526e: b086 sub sp, #24
8005270: af00 add r7, sp, #0
8005272: 60f8 str r0, [r7, #12]
8005274: 60b9 str r1, [r7, #8]
8005276: 607a str r2, [r7, #4]
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(TIMx));
assert_param(IS_TIM_CHANNELS(Channel));
tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
8005278: 68bb ldr r3, [r7, #8]
800527a: 221f movs r2, #31
800527c: 4013 ands r3, r2
800527e: 2201 movs r2, #1
8005280: 409a lsls r2, r3
8005282: 0013 movs r3, r2
8005284: 617b str r3, [r7, #20]
/* Reset the CCxE Bit */
TIMx->CCER &= ~tmp;
8005286: 68fb ldr r3, [r7, #12]
8005288: 6a1b ldr r3, [r3, #32]
800528a: 697a ldr r2, [r7, #20]
800528c: 43d2 mvns r2, r2
800528e: 401a ands r2, r3
8005290: 68fb ldr r3, [r7, #12]
8005292: 621a str r2, [r3, #32]
/* Set or reset the CCxE Bit */
TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
8005294: 68fb ldr r3, [r7, #12]
8005296: 6a1a ldr r2, [r3, #32]
8005298: 68bb ldr r3, [r7, #8]
800529a: 211f movs r1, #31
800529c: 400b ands r3, r1
800529e: 6879 ldr r1, [r7, #4]
80052a0: 4099 lsls r1, r3
80052a2: 000b movs r3, r1
80052a4: 431a orrs r2, r3
80052a6: 68fb ldr r3, [r7, #12]
80052a8: 621a str r2, [r3, #32]
}
80052aa: 46c0 nop ; (mov r8, r8)
80052ac: 46bd mov sp, r7
80052ae: b006 add sp, #24
80052b0: bd80 pop {r7, pc}
...
080052b4 <HAL_TIMEx_MasterConfigSynchronization>:
* mode.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
const TIM_MasterConfigTypeDef *sMasterConfig)
{
80052b4: b580 push {r7, lr}
80052b6: b084 sub sp, #16
80052b8: af00 add r7, sp, #0
80052ba: 6078 str r0, [r7, #4]
80052bc: 6039 str r1, [r7, #0]
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
/* Check input state */
__HAL_LOCK(htim);
80052be: 687b ldr r3, [r7, #4]
80052c0: 223c movs r2, #60 ; 0x3c
80052c2: 5c9b ldrb r3, [r3, r2]
80052c4: 2b01 cmp r3, #1
80052c6: d101 bne.n 80052cc <HAL_TIMEx_MasterConfigSynchronization+0x18>
80052c8: 2302 movs r3, #2
80052ca: e050 b.n 800536e <HAL_TIMEx_MasterConfigSynchronization+0xba>
80052cc: 687b ldr r3, [r7, #4]
80052ce: 223c movs r2, #60 ; 0x3c
80052d0: 2101 movs r1, #1
80052d2: 5499 strb r1, [r3, r2]
/* Change the handler state */
htim->State = HAL_TIM_STATE_BUSY;
80052d4: 687b ldr r3, [r7, #4]
80052d6: 223d movs r2, #61 ; 0x3d
80052d8: 2102 movs r1, #2
80052da: 5499 strb r1, [r3, r2]
/* Get the TIMx CR2 register value */
tmpcr2 = htim->Instance->CR2;
80052dc: 687b ldr r3, [r7, #4]
80052de: 681b ldr r3, [r3, #0]
80052e0: 685b ldr r3, [r3, #4]
80052e2: 60fb str r3, [r7, #12]
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
80052e4: 687b ldr r3, [r7, #4]
80052e6: 681b ldr r3, [r3, #0]
80052e8: 689b ldr r3, [r3, #8]
80052ea: 60bb str r3, [r7, #8]
/* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
80052ec: 687b ldr r3, [r7, #4]
80052ee: 681b ldr r3, [r3, #0]
80052f0: 4a21 ldr r2, [pc, #132] ; (8005378 <HAL_TIMEx_MasterConfigSynchronization+0xc4>)
80052f2: 4293 cmp r3, r2
80052f4: d108 bne.n 8005308 <HAL_TIMEx_MasterConfigSynchronization+0x54>
{
/* Check the parameters */
assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
/* Clear the MMS2 bits */
tmpcr2 &= ~TIM_CR2_MMS2;
80052f6: 68fb ldr r3, [r7, #12]
80052f8: 4a20 ldr r2, [pc, #128] ; (800537c <HAL_TIMEx_MasterConfigSynchronization+0xc8>)
80052fa: 4013 ands r3, r2
80052fc: 60fb str r3, [r7, #12]
/* Select the TRGO2 source*/
tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
80052fe: 683b ldr r3, [r7, #0]
8005300: 685b ldr r3, [r3, #4]
8005302: 68fa ldr r2, [r7, #12]
8005304: 4313 orrs r3, r2
8005306: 60fb str r3, [r7, #12]
}
/* Reset the MMS Bits */
tmpcr2 &= ~TIM_CR2_MMS;
8005308: 68fb ldr r3, [r7, #12]
800530a: 2270 movs r2, #112 ; 0x70
800530c: 4393 bics r3, r2
800530e: 60fb str r3, [r7, #12]
/* Select the TRGO source */
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
8005310: 683b ldr r3, [r7, #0]
8005312: 681b ldr r3, [r3, #0]
8005314: 68fa ldr r2, [r7, #12]
8005316: 4313 orrs r3, r2
8005318: 60fb str r3, [r7, #12]
/* Update TIMx CR2 */
htim->Instance->CR2 = tmpcr2;
800531a: 687b ldr r3, [r7, #4]
800531c: 681b ldr r3, [r3, #0]
800531e: 68fa ldr r2, [r7, #12]
8005320: 605a str r2, [r3, #4]
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
8005322: 687b ldr r3, [r7, #4]
8005324: 681b ldr r3, [r3, #0]
8005326: 4a14 ldr r2, [pc, #80] ; (8005378 <HAL_TIMEx_MasterConfigSynchronization+0xc4>)
8005328: 4293 cmp r3, r2
800532a: d00a beq.n 8005342 <HAL_TIMEx_MasterConfigSynchronization+0x8e>
800532c: 687b ldr r3, [r7, #4]
800532e: 681a ldr r2, [r3, #0]
8005330: 2380 movs r3, #128 ; 0x80
8005332: 05db lsls r3, r3, #23
8005334: 429a cmp r2, r3
8005336: d004 beq.n 8005342 <HAL_TIMEx_MasterConfigSynchronization+0x8e>
8005338: 687b ldr r3, [r7, #4]
800533a: 681b ldr r3, [r3, #0]
800533c: 4a10 ldr r2, [pc, #64] ; (8005380 <HAL_TIMEx_MasterConfigSynchronization+0xcc>)
800533e: 4293 cmp r3, r2
8005340: d10c bne.n 800535c <HAL_TIMEx_MasterConfigSynchronization+0xa8>
{
/* Reset the MSM Bit */
tmpsmcr &= ~TIM_SMCR_MSM;
8005342: 68bb ldr r3, [r7, #8]
8005344: 2280 movs r2, #128 ; 0x80
8005346: 4393 bics r3, r2
8005348: 60bb str r3, [r7, #8]
/* Set master mode */
tmpsmcr |= sMasterConfig->MasterSlaveMode;
800534a: 683b ldr r3, [r7, #0]
800534c: 689b ldr r3, [r3, #8]
800534e: 68ba ldr r2, [r7, #8]
8005350: 4313 orrs r3, r2
8005352: 60bb str r3, [r7, #8]
/* Update TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
8005354: 687b ldr r3, [r7, #4]
8005356: 681b ldr r3, [r3, #0]
8005358: 68ba ldr r2, [r7, #8]
800535a: 609a str r2, [r3, #8]
}
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
800535c: 687b ldr r3, [r7, #4]
800535e: 223d movs r2, #61 ; 0x3d
8005360: 2101 movs r1, #1
8005362: 5499 strb r1, [r3, r2]
__HAL_UNLOCK(htim);
8005364: 687b ldr r3, [r7, #4]
8005366: 223c movs r2, #60 ; 0x3c
8005368: 2100 movs r1, #0
800536a: 5499 strb r1, [r3, r2]
return HAL_OK;
800536c: 2300 movs r3, #0
}
800536e: 0018 movs r0, r3
8005370: 46bd mov sp, r7
8005372: b004 add sp, #16
8005374: bd80 pop {r7, pc}
8005376: 46c0 nop ; (mov r8, r8)
8005378: 40012c00 .word 0x40012c00
800537c: ff0fffff .word 0xff0fffff
8005380: 40000400 .word 0x40000400
08005384 <HAL_UART_Init>:
* parameters in the UART_InitTypeDef and initialize the associated handle.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
8005384: b580 push {r7, lr}
8005386: b082 sub sp, #8
8005388: af00 add r7, sp, #0
800538a: 6078 str r0, [r7, #4]
/* Check the UART handle allocation */
if (huart == NULL)
800538c: 687b ldr r3, [r7, #4]
800538e: 2b00 cmp r3, #0
8005390: d101 bne.n 8005396 <HAL_UART_Init+0x12>
{
return HAL_ERROR;
8005392: 2301 movs r3, #1
8005394: e046 b.n 8005424 <HAL_UART_Init+0xa0>
{
/* Check the parameters */
assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
}
if (huart->gState == HAL_UART_STATE_RESET)
8005396: 687b ldr r3, [r7, #4]
8005398: 2284 movs r2, #132 ; 0x84
800539a: 589b ldr r3, [r3, r2]
800539c: 2b00 cmp r3, #0
800539e: d107 bne.n 80053b0 <HAL_UART_Init+0x2c>
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
80053a0: 687b ldr r3, [r7, #4]
80053a2: 2280 movs r2, #128 ; 0x80
80053a4: 2100 movs r1, #0
80053a6: 5499 strb r1, [r3, r2]
/* Init the low level hardware */
huart->MspInitCallback(huart);
#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
80053a8: 687b ldr r3, [r7, #4]
80053aa: 0018 movs r0, r3
80053ac: f7fc faa8 bl 8001900 <HAL_UART_MspInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
80053b0: 687b ldr r3, [r7, #4]
80053b2: 2284 movs r2, #132 ; 0x84
80053b4: 2124 movs r1, #36 ; 0x24
80053b6: 5099 str r1, [r3, r2]
__HAL_UART_DISABLE(huart);
80053b8: 687b ldr r3, [r7, #4]
80053ba: 681b ldr r3, [r3, #0]
80053bc: 681a ldr r2, [r3, #0]
80053be: 687b ldr r3, [r7, #4]
80053c0: 681b ldr r3, [r3, #0]
80053c2: 2101 movs r1, #1
80053c4: 438a bics r2, r1
80053c6: 601a str r2, [r3, #0]
/* Set the UART Communication parameters */
if (UART_SetConfig(huart) == HAL_ERROR)
80053c8: 687b ldr r3, [r7, #4]
80053ca: 0018 movs r0, r3
80053cc: f000 fc6e bl 8005cac <UART_SetConfig>
80053d0: 0003 movs r3, r0
80053d2: 2b01 cmp r3, #1
80053d4: d101 bne.n 80053da <HAL_UART_Init+0x56>
{
return HAL_ERROR;
80053d6: 2301 movs r3, #1
80053d8: e024 b.n 8005424 <HAL_UART_Init+0xa0>
}
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
80053da: 687b ldr r3, [r7, #4]
80053dc: 6a9b ldr r3, [r3, #40] ; 0x28
80053de: 2b00 cmp r3, #0
80053e0: d003 beq.n 80053ea <HAL_UART_Init+0x66>
{
UART_AdvFeatureConfig(huart);
80053e2: 687b ldr r3, [r7, #4]
80053e4: 0018 movs r0, r3
80053e6: f000 fed9 bl 800619c <UART_AdvFeatureConfig>
}
/* In asynchronous mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
80053ea: 687b ldr r3, [r7, #4]
80053ec: 681b ldr r3, [r3, #0]
80053ee: 685a ldr r2, [r3, #4]
80053f0: 687b ldr r3, [r7, #4]
80053f2: 681b ldr r3, [r3, #0]
80053f4: 490d ldr r1, [pc, #52] ; (800542c <HAL_UART_Init+0xa8>)
80053f6: 400a ands r2, r1
80053f8: 605a str r2, [r3, #4]
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
80053fa: 687b ldr r3, [r7, #4]
80053fc: 681b ldr r3, [r3, #0]
80053fe: 689a ldr r2, [r3, #8]
8005400: 687b ldr r3, [r7, #4]
8005402: 681b ldr r3, [r3, #0]
8005404: 212a movs r1, #42 ; 0x2a
8005406: 438a bics r2, r1
8005408: 609a str r2, [r3, #8]
__HAL_UART_ENABLE(huart);
800540a: 687b ldr r3, [r7, #4]
800540c: 681b ldr r3, [r3, #0]
800540e: 681a ldr r2, [r3, #0]
8005410: 687b ldr r3, [r7, #4]
8005412: 681b ldr r3, [r3, #0]
8005414: 2101 movs r1, #1
8005416: 430a orrs r2, r1
8005418: 601a str r2, [r3, #0]
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
return (UART_CheckIdleState(huart));
800541a: 687b ldr r3, [r7, #4]
800541c: 0018 movs r0, r3
800541e: f000 ff71 bl 8006304 <UART_CheckIdleState>
8005422: 0003 movs r3, r0
}
8005424: 0018 movs r0, r3
8005426: 46bd mov sp, r7
8005428: b002 add sp, #8
800542a: bd80 pop {r7, pc}
800542c: ffffb7ff .word 0xffffb7ff
08005430 <HAL_UART_Receive_IT>:
* @param pData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{
8005430: b580 push {r7, lr}
8005432: b088 sub sp, #32
8005434: af00 add r7, sp, #0
8005436: 60f8 str r0, [r7, #12]
8005438: 60b9 str r1, [r7, #8]
800543a: 1dbb adds r3, r7, #6
800543c: 801a strh r2, [r3, #0]
/* Check that a Rx process is not already ongoing */
if (huart->RxState == HAL_UART_STATE_READY)
800543e: 68fb ldr r3, [r7, #12]
8005440: 2288 movs r2, #136 ; 0x88
8005442: 589b ldr r3, [r3, r2]
8005444: 2b20 cmp r3, #32
8005446: d155 bne.n 80054f4 <HAL_UART_Receive_IT+0xc4>
{
if ((pData == NULL) || (Size == 0U))
8005448: 68bb ldr r3, [r7, #8]
800544a: 2b00 cmp r3, #0
800544c: d003 beq.n 8005456 <HAL_UART_Receive_IT+0x26>
800544e: 1dbb adds r3, r7, #6
8005450: 881b ldrh r3, [r3, #0]
8005452: 2b00 cmp r3, #0
8005454: d101 bne.n 800545a <HAL_UART_Receive_IT+0x2a>
{
return HAL_ERROR;
8005456: 2301 movs r3, #1
8005458: e04d b.n 80054f6 <HAL_UART_Receive_IT+0xc6>
}
/* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
should be aligned on a u16 frontier, as data to be received from RDR will be
handled through a u16 cast. */
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
800545a: 68fb ldr r3, [r7, #12]
800545c: 689a ldr r2, [r3, #8]
800545e: 2380 movs r3, #128 ; 0x80
8005460: 015b lsls r3, r3, #5
8005462: 429a cmp r2, r3
8005464: d109 bne.n 800547a <HAL_UART_Receive_IT+0x4a>
8005466: 68fb ldr r3, [r7, #12]
8005468: 691b ldr r3, [r3, #16]
800546a: 2b00 cmp r3, #0
800546c: d105 bne.n 800547a <HAL_UART_Receive_IT+0x4a>
{
if ((((uint32_t)pData) & 1U) != 0U)
800546e: 68bb ldr r3, [r7, #8]
8005470: 2201 movs r2, #1
8005472: 4013 ands r3, r2
8005474: d001 beq.n 800547a <HAL_UART_Receive_IT+0x4a>
{
return HAL_ERROR;
8005476: 2301 movs r3, #1
8005478: e03d b.n 80054f6 <HAL_UART_Receive_IT+0xc6>
}
}
__HAL_LOCK(huart);
800547a: 68fb ldr r3, [r7, #12]
800547c: 2280 movs r2, #128 ; 0x80
800547e: 5c9b ldrb r3, [r3, r2]
8005480: 2b01 cmp r3, #1
8005482: d101 bne.n 8005488 <HAL_UART_Receive_IT+0x58>
8005484: 2302 movs r3, #2
8005486: e036 b.n 80054f6 <HAL_UART_Receive_IT+0xc6>
8005488: 68fb ldr r3, [r7, #12]
800548a: 2280 movs r2, #128 ; 0x80
800548c: 2101 movs r1, #1
800548e: 5499 strb r1, [r3, r2]
/* Set Reception type to Standard reception */
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8005490: 68fb ldr r3, [r7, #12]
8005492: 2200 movs r2, #0
8005494: 66da str r2, [r3, #108] ; 0x6c
if (!(IS_LPUART_INSTANCE(huart->Instance)))
8005496: 68fb ldr r3, [r7, #12]
8005498: 681b ldr r3, [r3, #0]
800549a: 4a19 ldr r2, [pc, #100] ; (8005500 <HAL_UART_Receive_IT+0xd0>)
800549c: 4293 cmp r3, r2
800549e: d020 beq.n 80054e2 <HAL_UART_Receive_IT+0xb2>
{
/* Check that USART RTOEN bit is set */
if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
80054a0: 68fb ldr r3, [r7, #12]
80054a2: 681b ldr r3, [r3, #0]
80054a4: 685a ldr r2, [r3, #4]
80054a6: 2380 movs r3, #128 ; 0x80
80054a8: 041b lsls r3, r3, #16
80054aa: 4013 ands r3, r2
80054ac: d019 beq.n 80054e2 <HAL_UART_Receive_IT+0xb2>
*/
__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
80054ae: f3ef 8310 mrs r3, PRIMASK
80054b2: 613b str r3, [r7, #16]
return(result);
80054b4: 693b ldr r3, [r7, #16]
{
/* Enable the UART Receiver Timeout Interrupt */
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
80054b6: 61fb str r3, [r7, #28]
80054b8: 2301 movs r3, #1
80054ba: 617b str r3, [r7, #20]
\details Assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80054bc: 697b ldr r3, [r7, #20]
80054be: f383 8810 msr PRIMASK, r3
}
80054c2: 46c0 nop ; (mov r8, r8)
80054c4: 68fb ldr r3, [r7, #12]
80054c6: 681b ldr r3, [r3, #0]
80054c8: 681a ldr r2, [r3, #0]
80054ca: 68fb ldr r3, [r7, #12]
80054cc: 681b ldr r3, [r3, #0]
80054ce: 2180 movs r1, #128 ; 0x80
80054d0: 04c9 lsls r1, r1, #19
80054d2: 430a orrs r2, r1
80054d4: 601a str r2, [r3, #0]
80054d6: 69fb ldr r3, [r7, #28]
80054d8: 61bb str r3, [r7, #24]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80054da: 69bb ldr r3, [r7, #24]
80054dc: f383 8810 msr PRIMASK, r3
}
80054e0: 46c0 nop ; (mov r8, r8)
}
}
return (UART_Start_Receive_IT(huart, pData, Size));
80054e2: 1dbb adds r3, r7, #6
80054e4: 881a ldrh r2, [r3, #0]
80054e6: 68b9 ldr r1, [r7, #8]
80054e8: 68fb ldr r3, [r7, #12]
80054ea: 0018 movs r0, r3
80054ec: f001 f81c bl 8006528 <UART_Start_Receive_IT>
80054f0: 0003 movs r3, r0
80054f2: e000 b.n 80054f6 <HAL_UART_Receive_IT+0xc6>
}
else
{
return HAL_BUSY;
80054f4: 2302 movs r3, #2
}
}
80054f6: 0018 movs r0, r3
80054f8: 46bd mov sp, r7
80054fa: b008 add sp, #32
80054fc: bd80 pop {r7, pc}
80054fe: 46c0 nop ; (mov r8, r8)
8005500: 40008000 .word 0x40008000
08005504 <HAL_UART_Transmit_DMA>:
* @param pData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size)
{
8005504: b580 push {r7, lr}
8005506: b088 sub sp, #32
8005508: af00 add r7, sp, #0
800550a: 60f8 str r0, [r7, #12]
800550c: 60b9 str r1, [r7, #8]
800550e: 1dbb adds r3, r7, #6
8005510: 801a strh r2, [r3, #0]
/* Check that a Tx process is not already ongoing */
if (huart->gState == HAL_UART_STATE_READY)
8005512: 68fb ldr r3, [r7, #12]
8005514: 2284 movs r2, #132 ; 0x84
8005516: 589b ldr r3, [r3, r2]
8005518: 2b20 cmp r3, #32
800551a: d000 beq.n 800551e <HAL_UART_Transmit_DMA+0x1a>
800551c: e08c b.n 8005638 <HAL_UART_Transmit_DMA+0x134>
{
if ((pData == NULL) || (Size == 0U))
800551e: 68bb ldr r3, [r7, #8]
8005520: 2b00 cmp r3, #0
8005522: d003 beq.n 800552c <HAL_UART_Transmit_DMA+0x28>
8005524: 1dbb adds r3, r7, #6
8005526: 881b ldrh r3, [r3, #0]
8005528: 2b00 cmp r3, #0
800552a: d101 bne.n 8005530 <HAL_UART_Transmit_DMA+0x2c>
{
return HAL_ERROR;
800552c: 2301 movs r3, #1
800552e: e084 b.n 800563a <HAL_UART_Transmit_DMA+0x136>
}
/* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
should be aligned on a u16 frontier, as data copy into TDR will be
handled by DMA from a u16 frontier. */
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
8005530: 68fb ldr r3, [r7, #12]
8005532: 689a ldr r2, [r3, #8]
8005534: 2380 movs r3, #128 ; 0x80
8005536: 015b lsls r3, r3, #5
8005538: 429a cmp r2, r3
800553a: d109 bne.n 8005550 <HAL_UART_Transmit_DMA+0x4c>
800553c: 68fb ldr r3, [r7, #12]
800553e: 691b ldr r3, [r3, #16]
8005540: 2b00 cmp r3, #0
8005542: d105 bne.n 8005550 <HAL_UART_Transmit_DMA+0x4c>
{
if ((((uint32_t)pData) & 1U) != 0U)
8005544: 68bb ldr r3, [r7, #8]
8005546: 2201 movs r2, #1
8005548: 4013 ands r3, r2
800554a: d001 beq.n 8005550 <HAL_UART_Transmit_DMA+0x4c>
{
return HAL_ERROR;
800554c: 2301 movs r3, #1
800554e: e074 b.n 800563a <HAL_UART_Transmit_DMA+0x136>
}
}
__HAL_LOCK(huart);
8005550: 68fb ldr r3, [r7, #12]
8005552: 2280 movs r2, #128 ; 0x80
8005554: 5c9b ldrb r3, [r3, r2]
8005556: 2b01 cmp r3, #1
8005558: d101 bne.n 800555e <HAL_UART_Transmit_DMA+0x5a>
800555a: 2302 movs r3, #2
800555c: e06d b.n 800563a <HAL_UART_Transmit_DMA+0x136>
800555e: 68fb ldr r3, [r7, #12]
8005560: 2280 movs r2, #128 ; 0x80
8005562: 2101 movs r1, #1
8005564: 5499 strb r1, [r3, r2]
huart->pTxBuffPtr = pData;
8005566: 68fb ldr r3, [r7, #12]
8005568: 68ba ldr r2, [r7, #8]
800556a: 651a str r2, [r3, #80] ; 0x50
huart->TxXferSize = Size;
800556c: 68fb ldr r3, [r7, #12]
800556e: 1dba adds r2, r7, #6
8005570: 2154 movs r1, #84 ; 0x54
8005572: 8812 ldrh r2, [r2, #0]
8005574: 525a strh r2, [r3, r1]
huart->TxXferCount = Size;
8005576: 68fb ldr r3, [r7, #12]
8005578: 1dba adds r2, r7, #6
800557a: 2156 movs r1, #86 ; 0x56
800557c: 8812 ldrh r2, [r2, #0]
800557e: 525a strh r2, [r3, r1]
huart->ErrorCode = HAL_UART_ERROR_NONE;
8005580: 68fb ldr r3, [r7, #12]
8005582: 228c movs r2, #140 ; 0x8c
8005584: 2100 movs r1, #0
8005586: 5099 str r1, [r3, r2]
huart->gState = HAL_UART_STATE_BUSY_TX;
8005588: 68fb ldr r3, [r7, #12]
800558a: 2284 movs r2, #132 ; 0x84
800558c: 2121 movs r1, #33 ; 0x21
800558e: 5099 str r1, [r3, r2]
if (huart->hdmatx != NULL)
8005590: 68fb ldr r3, [r7, #12]
8005592: 6f9b ldr r3, [r3, #120] ; 0x78
8005594: 2b00 cmp r3, #0
8005596: d02c beq.n 80055f2 <HAL_UART_Transmit_DMA+0xee>
{
/* Set the UART DMA transfer complete callback */
huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
8005598: 68fb ldr r3, [r7, #12]
800559a: 6f9b ldr r3, [r3, #120] ; 0x78
800559c: 4a29 ldr r2, [pc, #164] ; (8005644 <HAL_UART_Transmit_DMA+0x140>)
800559e: 62da str r2, [r3, #44] ; 0x2c
/* Set the UART DMA Half transfer complete callback */
huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
80055a0: 68fb ldr r3, [r7, #12]
80055a2: 6f9b ldr r3, [r3, #120] ; 0x78
80055a4: 4a28 ldr r2, [pc, #160] ; (8005648 <HAL_UART_Transmit_DMA+0x144>)
80055a6: 631a str r2, [r3, #48] ; 0x30
/* Set the DMA error callback */
huart->hdmatx->XferErrorCallback = UART_DMAError;
80055a8: 68fb ldr r3, [r7, #12]
80055aa: 6f9b ldr r3, [r3, #120] ; 0x78
80055ac: 4a27 ldr r2, [pc, #156] ; (800564c <HAL_UART_Transmit_DMA+0x148>)
80055ae: 635a str r2, [r3, #52] ; 0x34
/* Set the DMA abort callback */
huart->hdmatx->XferAbortCallback = NULL;
80055b0: 68fb ldr r3, [r7, #12]
80055b2: 6f9b ldr r3, [r3, #120] ; 0x78
80055b4: 2200 movs r2, #0
80055b6: 639a str r2, [r3, #56] ; 0x38
/* Enable the UART transmit DMA channel */
if (HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, Size) != HAL_OK)
80055b8: 68fb ldr r3, [r7, #12]
80055ba: 6f98 ldr r0, [r3, #120] ; 0x78
80055bc: 68fb ldr r3, [r7, #12]
80055be: 6d1b ldr r3, [r3, #80] ; 0x50
80055c0: 0019 movs r1, r3
80055c2: 68fb ldr r3, [r7, #12]
80055c4: 681b ldr r3, [r3, #0]
80055c6: 3328 adds r3, #40 ; 0x28
80055c8: 001a movs r2, r3
80055ca: 1dbb adds r3, r7, #6
80055cc: 881b ldrh r3, [r3, #0]
80055ce: f7fd fd19 bl 8003004 <HAL_DMA_Start_IT>
80055d2: 1e03 subs r3, r0, #0
80055d4: d00d beq.n 80055f2 <HAL_UART_Transmit_DMA+0xee>
{
/* Set error code to DMA */
huart->ErrorCode = HAL_UART_ERROR_DMA;
80055d6: 68fb ldr r3, [r7, #12]
80055d8: 228c movs r2, #140 ; 0x8c
80055da: 2110 movs r1, #16
80055dc: 5099 str r1, [r3, r2]
__HAL_UNLOCK(huart);
80055de: 68fb ldr r3, [r7, #12]
80055e0: 2280 movs r2, #128 ; 0x80
80055e2: 2100 movs r1, #0
80055e4: 5499 strb r1, [r3, r2]
/* Restore huart->gState to ready */
huart->gState = HAL_UART_STATE_READY;
80055e6: 68fb ldr r3, [r7, #12]
80055e8: 2284 movs r2, #132 ; 0x84
80055ea: 2120 movs r1, #32
80055ec: 5099 str r1, [r3, r2]
return HAL_ERROR;
80055ee: 2301 movs r3, #1
80055f0: e023 b.n 800563a <HAL_UART_Transmit_DMA+0x136>
}
}
/* Clear the TC flag in the ICR register */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
80055f2: 68fb ldr r3, [r7, #12]
80055f4: 681b ldr r3, [r3, #0]
80055f6: 2240 movs r2, #64 ; 0x40
80055f8: 621a str r2, [r3, #32]
__HAL_UNLOCK(huart);
80055fa: 68fb ldr r3, [r7, #12]
80055fc: 2280 movs r2, #128 ; 0x80
80055fe: 2100 movs r1, #0
8005600: 5499 strb r1, [r3, r2]
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8005602: f3ef 8310 mrs r3, PRIMASK
8005606: 613b str r3, [r7, #16]
return(result);
8005608: 693b ldr r3, [r7, #16]
/* Enable the DMA transfer for transmit request by setting the DMAT bit
in the UART CR3 register */
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
800560a: 61fb str r3, [r7, #28]
800560c: 2301 movs r3, #1
800560e: 617b str r3, [r7, #20]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8005610: 697b ldr r3, [r7, #20]
8005612: f383 8810 msr PRIMASK, r3
}
8005616: 46c0 nop ; (mov r8, r8)
8005618: 68fb ldr r3, [r7, #12]
800561a: 681b ldr r3, [r3, #0]
800561c: 689a ldr r2, [r3, #8]
800561e: 68fb ldr r3, [r7, #12]
8005620: 681b ldr r3, [r3, #0]
8005622: 2180 movs r1, #128 ; 0x80
8005624: 430a orrs r2, r1
8005626: 609a str r2, [r3, #8]
8005628: 69fb ldr r3, [r7, #28]
800562a: 61bb str r3, [r7, #24]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
800562c: 69bb ldr r3, [r7, #24]
800562e: f383 8810 msr PRIMASK, r3
}
8005632: 46c0 nop ; (mov r8, r8)
return HAL_OK;
8005634: 2300 movs r3, #0
8005636: e000 b.n 800563a <HAL_UART_Transmit_DMA+0x136>
}
else
{
return HAL_BUSY;
8005638: 2302 movs r3, #2
}
}
800563a: 0018 movs r0, r3
800563c: 46bd mov sp, r7
800563e: b008 add sp, #32
8005640: bd80 pop {r7, pc}
8005642: 46c0 nop ; (mov r8, r8)
8005644: 080068cd .word 0x080068cd
8005648: 08006965 .word 0x08006965
800564c: 08006983 .word 0x08006983
08005650 <HAL_UART_IRQHandler>:
* @brief Handle UART interrupt request.
* @param huart UART handle.
* @retval None
*/
void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
{
8005650: b5b0 push {r4, r5, r7, lr}
8005652: b0aa sub sp, #168 ; 0xa8
8005654: af00 add r7, sp, #0
8005656: 6078 str r0, [r7, #4]
uint32_t isrflags = READ_REG(huart->Instance->ISR);
8005658: 687b ldr r3, [r7, #4]
800565a: 681b ldr r3, [r3, #0]
800565c: 69db ldr r3, [r3, #28]
800565e: 22a4 movs r2, #164 ; 0xa4
8005660: 18b9 adds r1, r7, r2
8005662: 600b str r3, [r1, #0]
uint32_t cr1its = READ_REG(huart->Instance->CR1);
8005664: 687b ldr r3, [r7, #4]
8005666: 681b ldr r3, [r3, #0]
8005668: 681b ldr r3, [r3, #0]
800566a: 20a0 movs r0, #160 ; 0xa0
800566c: 1839 adds r1, r7, r0
800566e: 600b str r3, [r1, #0]
uint32_t cr3its = READ_REG(huart->Instance->CR3);
8005670: 687b ldr r3, [r7, #4]
8005672: 681b ldr r3, [r3, #0]
8005674: 689b ldr r3, [r3, #8]
8005676: 249c movs r4, #156 ; 0x9c
8005678: 1939 adds r1, r7, r4
800567a: 600b str r3, [r1, #0]
uint32_t errorflags;
uint32_t errorcode;
/* If no error occurs */
errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
800567c: 0011 movs r1, r2
800567e: 18bb adds r3, r7, r2
8005680: 681b ldr r3, [r3, #0]
8005682: 4aa0 ldr r2, [pc, #640] ; (8005904 <HAL_UART_IRQHandler+0x2b4>)
8005684: 4013 ands r3, r2
8005686: 2298 movs r2, #152 ; 0x98
8005688: 18bd adds r5, r7, r2
800568a: 602b str r3, [r5, #0]
if (errorflags == 0U)
800568c: 18bb adds r3, r7, r2
800568e: 681b ldr r3, [r3, #0]
8005690: 2b00 cmp r3, #0
8005692: d11a bne.n 80056ca <HAL_UART_IRQHandler+0x7a>
{
/* UART in mode Receiver ---------------------------------------------------*/
if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
8005694: 187b adds r3, r7, r1
8005696: 681b ldr r3, [r3, #0]
8005698: 2220 movs r2, #32
800569a: 4013 ands r3, r2
800569c: d015 beq.n 80056ca <HAL_UART_IRQHandler+0x7a>
&& (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
800569e: 183b adds r3, r7, r0
80056a0: 681b ldr r3, [r3, #0]
80056a2: 2220 movs r2, #32
80056a4: 4013 ands r3, r2
80056a6: d105 bne.n 80056b4 <HAL_UART_IRQHandler+0x64>
|| ((cr3its & USART_CR3_RXFTIE) != 0U)))
80056a8: 193b adds r3, r7, r4
80056aa: 681a ldr r2, [r3, #0]
80056ac: 2380 movs r3, #128 ; 0x80
80056ae: 055b lsls r3, r3, #21
80056b0: 4013 ands r3, r2
80056b2: d00a beq.n 80056ca <HAL_UART_IRQHandler+0x7a>
{
if (huart->RxISR != NULL)
80056b4: 687b ldr r3, [r7, #4]
80056b6: 6f1b ldr r3, [r3, #112] ; 0x70
80056b8: 2b00 cmp r3, #0
80056ba: d100 bne.n 80056be <HAL_UART_IRQHandler+0x6e>
80056bc: e2cf b.n 8005c5e <HAL_UART_IRQHandler+0x60e>
{
huart->RxISR(huart);
80056be: 687b ldr r3, [r7, #4]
80056c0: 6f1b ldr r3, [r3, #112] ; 0x70
80056c2: 687a ldr r2, [r7, #4]
80056c4: 0010 movs r0, r2
80056c6: 4798 blx r3
}
return;
80056c8: e2c9 b.n 8005c5e <HAL_UART_IRQHandler+0x60e>
}
}
/* If some errors occur */
if ((errorflags != 0U)
80056ca: 2398 movs r3, #152 ; 0x98
80056cc: 18fb adds r3, r7, r3
80056ce: 681b ldr r3, [r3, #0]
80056d0: 2b00 cmp r3, #0
80056d2: d100 bne.n 80056d6 <HAL_UART_IRQHandler+0x86>
80056d4: e11e b.n 8005914 <HAL_UART_IRQHandler+0x2c4>
&& ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)
80056d6: 239c movs r3, #156 ; 0x9c
80056d8: 18fb adds r3, r7, r3
80056da: 681b ldr r3, [r3, #0]
80056dc: 4a8a ldr r2, [pc, #552] ; (8005908 <HAL_UART_IRQHandler+0x2b8>)
80056de: 4013 ands r3, r2
80056e0: d106 bne.n 80056f0 <HAL_UART_IRQHandler+0xa0>
|| ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U))))
80056e2: 23a0 movs r3, #160 ; 0xa0
80056e4: 18fb adds r3, r7, r3
80056e6: 681b ldr r3, [r3, #0]
80056e8: 4a88 ldr r2, [pc, #544] ; (800590c <HAL_UART_IRQHandler+0x2bc>)
80056ea: 4013 ands r3, r2
80056ec: d100 bne.n 80056f0 <HAL_UART_IRQHandler+0xa0>
80056ee: e111 b.n 8005914 <HAL_UART_IRQHandler+0x2c4>
{
/* UART parity error interrupt occurred -------------------------------------*/
if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
80056f0: 23a4 movs r3, #164 ; 0xa4
80056f2: 18fb adds r3, r7, r3
80056f4: 681b ldr r3, [r3, #0]
80056f6: 2201 movs r2, #1
80056f8: 4013 ands r3, r2
80056fa: d012 beq.n 8005722 <HAL_UART_IRQHandler+0xd2>
80056fc: 23a0 movs r3, #160 ; 0xa0
80056fe: 18fb adds r3, r7, r3
8005700: 681a ldr r2, [r3, #0]
8005702: 2380 movs r3, #128 ; 0x80
8005704: 005b lsls r3, r3, #1
8005706: 4013 ands r3, r2
8005708: d00b beq.n 8005722 <HAL_UART_IRQHandler+0xd2>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
800570a: 687b ldr r3, [r7, #4]
800570c: 681b ldr r3, [r3, #0]
800570e: 2201 movs r2, #1
8005710: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_PE;
8005712: 687b ldr r3, [r7, #4]
8005714: 228c movs r2, #140 ; 0x8c
8005716: 589b ldr r3, [r3, r2]
8005718: 2201 movs r2, #1
800571a: 431a orrs r2, r3
800571c: 687b ldr r3, [r7, #4]
800571e: 218c movs r1, #140 ; 0x8c
8005720: 505a str r2, [r3, r1]
}
/* UART frame error interrupt occurred --------------------------------------*/
if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
8005722: 23a4 movs r3, #164 ; 0xa4
8005724: 18fb adds r3, r7, r3
8005726: 681b ldr r3, [r3, #0]
8005728: 2202 movs r2, #2
800572a: 4013 ands r3, r2
800572c: d011 beq.n 8005752 <HAL_UART_IRQHandler+0x102>
800572e: 239c movs r3, #156 ; 0x9c
8005730: 18fb adds r3, r7, r3
8005732: 681b ldr r3, [r3, #0]
8005734: 2201 movs r2, #1
8005736: 4013 ands r3, r2
8005738: d00b beq.n 8005752 <HAL_UART_IRQHandler+0x102>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
800573a: 687b ldr r3, [r7, #4]
800573c: 681b ldr r3, [r3, #0]
800573e: 2202 movs r2, #2
8005740: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_FE;
8005742: 687b ldr r3, [r7, #4]
8005744: 228c movs r2, #140 ; 0x8c
8005746: 589b ldr r3, [r3, r2]
8005748: 2204 movs r2, #4
800574a: 431a orrs r2, r3
800574c: 687b ldr r3, [r7, #4]
800574e: 218c movs r1, #140 ; 0x8c
8005750: 505a str r2, [r3, r1]
}
/* UART noise error interrupt occurred --------------------------------------*/
if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
8005752: 23a4 movs r3, #164 ; 0xa4
8005754: 18fb adds r3, r7, r3
8005756: 681b ldr r3, [r3, #0]
8005758: 2204 movs r2, #4
800575a: 4013 ands r3, r2
800575c: d011 beq.n 8005782 <HAL_UART_IRQHandler+0x132>
800575e: 239c movs r3, #156 ; 0x9c
8005760: 18fb adds r3, r7, r3
8005762: 681b ldr r3, [r3, #0]
8005764: 2201 movs r2, #1
8005766: 4013 ands r3, r2
8005768: d00b beq.n 8005782 <HAL_UART_IRQHandler+0x132>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
800576a: 687b ldr r3, [r7, #4]
800576c: 681b ldr r3, [r3, #0]
800576e: 2204 movs r2, #4
8005770: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_NE;
8005772: 687b ldr r3, [r7, #4]
8005774: 228c movs r2, #140 ; 0x8c
8005776: 589b ldr r3, [r3, r2]
8005778: 2202 movs r2, #2
800577a: 431a orrs r2, r3
800577c: 687b ldr r3, [r7, #4]
800577e: 218c movs r1, #140 ; 0x8c
8005780: 505a str r2, [r3, r1]
}
/* UART Over-Run interrupt occurred -----------------------------------------*/
if (((isrflags & USART_ISR_ORE) != 0U)
8005782: 23a4 movs r3, #164 ; 0xa4
8005784: 18fb adds r3, r7, r3
8005786: 681b ldr r3, [r3, #0]
8005788: 2208 movs r2, #8
800578a: 4013 ands r3, r2
800578c: d017 beq.n 80057be <HAL_UART_IRQHandler+0x16e>
&& (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
800578e: 23a0 movs r3, #160 ; 0xa0
8005790: 18fb adds r3, r7, r3
8005792: 681b ldr r3, [r3, #0]
8005794: 2220 movs r2, #32
8005796: 4013 ands r3, r2
8005798: d105 bne.n 80057a6 <HAL_UART_IRQHandler+0x156>
((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)))
800579a: 239c movs r3, #156 ; 0x9c
800579c: 18fb adds r3, r7, r3
800579e: 681b ldr r3, [r3, #0]
80057a0: 4a59 ldr r2, [pc, #356] ; (8005908 <HAL_UART_IRQHandler+0x2b8>)
80057a2: 4013 ands r3, r2
&& (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
80057a4: d00b beq.n 80057be <HAL_UART_IRQHandler+0x16e>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
80057a6: 687b ldr r3, [r7, #4]
80057a8: 681b ldr r3, [r3, #0]
80057aa: 2208 movs r2, #8
80057ac: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_ORE;
80057ae: 687b ldr r3, [r7, #4]
80057b0: 228c movs r2, #140 ; 0x8c
80057b2: 589b ldr r3, [r3, r2]
80057b4: 2208 movs r2, #8
80057b6: 431a orrs r2, r3
80057b8: 687b ldr r3, [r7, #4]
80057ba: 218c movs r1, #140 ; 0x8c
80057bc: 505a str r2, [r3, r1]
}
/* UART Receiver Timeout interrupt occurred ---------------------------------*/
if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
80057be: 23a4 movs r3, #164 ; 0xa4
80057c0: 18fb adds r3, r7, r3
80057c2: 681a ldr r2, [r3, #0]
80057c4: 2380 movs r3, #128 ; 0x80
80057c6: 011b lsls r3, r3, #4
80057c8: 4013 ands r3, r2
80057ca: d013 beq.n 80057f4 <HAL_UART_IRQHandler+0x1a4>
80057cc: 23a0 movs r3, #160 ; 0xa0
80057ce: 18fb adds r3, r7, r3
80057d0: 681a ldr r2, [r3, #0]
80057d2: 2380 movs r3, #128 ; 0x80
80057d4: 04db lsls r3, r3, #19
80057d6: 4013 ands r3, r2
80057d8: d00c beq.n 80057f4 <HAL_UART_IRQHandler+0x1a4>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
80057da: 687b ldr r3, [r7, #4]
80057dc: 681b ldr r3, [r3, #0]
80057de: 2280 movs r2, #128 ; 0x80
80057e0: 0112 lsls r2, r2, #4
80057e2: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_RTO;
80057e4: 687b ldr r3, [r7, #4]
80057e6: 228c movs r2, #140 ; 0x8c
80057e8: 589b ldr r3, [r3, r2]
80057ea: 2220 movs r2, #32
80057ec: 431a orrs r2, r3
80057ee: 687b ldr r3, [r7, #4]
80057f0: 218c movs r1, #140 ; 0x8c
80057f2: 505a str r2, [r3, r1]
}
/* Call UART Error Call back function if need be ----------------------------*/
if (huart->ErrorCode != HAL_UART_ERROR_NONE)
80057f4: 687b ldr r3, [r7, #4]
80057f6: 228c movs r2, #140 ; 0x8c
80057f8: 589b ldr r3, [r3, r2]
80057fa: 2b00 cmp r3, #0
80057fc: d100 bne.n 8005800 <HAL_UART_IRQHandler+0x1b0>
80057fe: e230 b.n 8005c62 <HAL_UART_IRQHandler+0x612>
{
/* UART in mode Receiver --------------------------------------------------*/
if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
8005800: 23a4 movs r3, #164 ; 0xa4
8005802: 18fb adds r3, r7, r3
8005804: 681b ldr r3, [r3, #0]
8005806: 2220 movs r2, #32
8005808: 4013 ands r3, r2
800580a: d015 beq.n 8005838 <HAL_UART_IRQHandler+0x1e8>
&& (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
800580c: 23a0 movs r3, #160 ; 0xa0
800580e: 18fb adds r3, r7, r3
8005810: 681b ldr r3, [r3, #0]
8005812: 2220 movs r2, #32
8005814: 4013 ands r3, r2
8005816: d106 bne.n 8005826 <HAL_UART_IRQHandler+0x1d6>
|| ((cr3its & USART_CR3_RXFTIE) != 0U)))
8005818: 239c movs r3, #156 ; 0x9c
800581a: 18fb adds r3, r7, r3
800581c: 681a ldr r2, [r3, #0]
800581e: 2380 movs r3, #128 ; 0x80
8005820: 055b lsls r3, r3, #21
8005822: 4013 ands r3, r2
8005824: d008 beq.n 8005838 <HAL_UART_IRQHandler+0x1e8>
{
if (huart->RxISR != NULL)
8005826: 687b ldr r3, [r7, #4]
8005828: 6f1b ldr r3, [r3, #112] ; 0x70
800582a: 2b00 cmp r3, #0
800582c: d004 beq.n 8005838 <HAL_UART_IRQHandler+0x1e8>
{
huart->RxISR(huart);
800582e: 687b ldr r3, [r7, #4]
8005830: 6f1b ldr r3, [r3, #112] ; 0x70
8005832: 687a ldr r2, [r7, #4]
8005834: 0010 movs r0, r2
8005836: 4798 blx r3
/* If Error is to be considered as blocking :
- Receiver Timeout error in Reception
- Overrun error in Reception
- any error occurs in DMA mode reception
*/
errorcode = huart->ErrorCode;
8005838: 687b ldr r3, [r7, #4]
800583a: 228c movs r2, #140 ; 0x8c
800583c: 589b ldr r3, [r3, r2]
800583e: 2194 movs r1, #148 ; 0x94
8005840: 187a adds r2, r7, r1
8005842: 6013 str r3, [r2, #0]
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
8005844: 687b ldr r3, [r7, #4]
8005846: 681b ldr r3, [r3, #0]
8005848: 689b ldr r3, [r3, #8]
800584a: 2240 movs r2, #64 ; 0x40
800584c: 4013 ands r3, r2
800584e: 2b40 cmp r3, #64 ; 0x40
8005850: d004 beq.n 800585c <HAL_UART_IRQHandler+0x20c>
((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U))
8005852: 187b adds r3, r7, r1
8005854: 681b ldr r3, [r3, #0]
8005856: 2228 movs r2, #40 ; 0x28
8005858: 4013 ands r3, r2
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
800585a: d047 beq.n 80058ec <HAL_UART_IRQHandler+0x29c>
{
/* Blocking error : transfer is aborted
Set the UART state ready to be able to start again the process,
Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
UART_EndRxTransfer(huart);
800585c: 687b ldr r3, [r7, #4]
800585e: 0018 movs r0, r3
8005860: f000 ffce bl 8006800 <UART_EndRxTransfer>
/* Abort the UART DMA Rx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
8005864: 687b ldr r3, [r7, #4]
8005866: 681b ldr r3, [r3, #0]
8005868: 689b ldr r3, [r3, #8]
800586a: 2240 movs r2, #64 ; 0x40
800586c: 4013 ands r3, r2
800586e: 2b40 cmp r3, #64 ; 0x40
8005870: d137 bne.n 80058e2 <HAL_UART_IRQHandler+0x292>
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8005872: f3ef 8310 mrs r3, PRIMASK
8005876: 663b str r3, [r7, #96] ; 0x60
return(result);
8005878: 6e3b ldr r3, [r7, #96] ; 0x60
{
/* Disable the UART DMA Rx request if enabled */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
800587a: 2090 movs r0, #144 ; 0x90
800587c: 183a adds r2, r7, r0
800587e: 6013 str r3, [r2, #0]
8005880: 2301 movs r3, #1
8005882: 667b str r3, [r7, #100] ; 0x64
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8005884: 6e7b ldr r3, [r7, #100] ; 0x64
8005886: f383 8810 msr PRIMASK, r3
}
800588a: 46c0 nop ; (mov r8, r8)
800588c: 687b ldr r3, [r7, #4]
800588e: 681b ldr r3, [r3, #0]
8005890: 689a ldr r2, [r3, #8]
8005892: 687b ldr r3, [r7, #4]
8005894: 681b ldr r3, [r3, #0]
8005896: 2140 movs r1, #64 ; 0x40
8005898: 438a bics r2, r1
800589a: 609a str r2, [r3, #8]
800589c: 183b adds r3, r7, r0
800589e: 681b ldr r3, [r3, #0]
80058a0: 66bb str r3, [r7, #104] ; 0x68
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80058a2: 6ebb ldr r3, [r7, #104] ; 0x68
80058a4: f383 8810 msr PRIMASK, r3
}
80058a8: 46c0 nop ; (mov r8, r8)
/* Abort the UART DMA Rx channel */
if (huart->hdmarx != NULL)
80058aa: 687b ldr r3, [r7, #4]
80058ac: 6fdb ldr r3, [r3, #124] ; 0x7c
80058ae: 2b00 cmp r3, #0
80058b0: d012 beq.n 80058d8 <HAL_UART_IRQHandler+0x288>
{
/* Set the UART DMA Abort callback :
will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
80058b2: 687b ldr r3, [r7, #4]
80058b4: 6fdb ldr r3, [r3, #124] ; 0x7c
80058b6: 4a16 ldr r2, [pc, #88] ; (8005910 <HAL_UART_IRQHandler+0x2c0>)
80058b8: 639a str r2, [r3, #56] ; 0x38
/* Abort DMA RX */
if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
80058ba: 687b ldr r3, [r7, #4]
80058bc: 6fdb ldr r3, [r3, #124] ; 0x7c
80058be: 0018 movs r0, r3
80058c0: f7fd fc88 bl 80031d4 <HAL_DMA_Abort_IT>
80058c4: 1e03 subs r3, r0, #0
80058c6: d01a beq.n 80058fe <HAL_UART_IRQHandler+0x2ae>
{
/* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
huart->hdmarx->XferAbortCallback(huart->hdmarx);
80058c8: 687b ldr r3, [r7, #4]
80058ca: 6fdb ldr r3, [r3, #124] ; 0x7c
80058cc: 6b9a ldr r2, [r3, #56] ; 0x38
80058ce: 687b ldr r3, [r7, #4]
80058d0: 6fdb ldr r3, [r3, #124] ; 0x7c
80058d2: 0018 movs r0, r3
80058d4: 4790 blx r2
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
80058d6: e012 b.n 80058fe <HAL_UART_IRQHandler+0x2ae>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
80058d8: 687b ldr r3, [r7, #4]
80058da: 0018 movs r0, r3
80058dc: f7fb fdf2 bl 80014c4 <HAL_UART_ErrorCallback>
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
80058e0: e00d b.n 80058fe <HAL_UART_IRQHandler+0x2ae>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
80058e2: 687b ldr r3, [r7, #4]
80058e4: 0018 movs r0, r3
80058e6: f7fb fded bl 80014c4 <HAL_UART_ErrorCallback>
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
80058ea: e008 b.n 80058fe <HAL_UART_IRQHandler+0x2ae>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
80058ec: 687b ldr r3, [r7, #4]
80058ee: 0018 movs r0, r3
80058f0: f7fb fde8 bl 80014c4 <HAL_UART_ErrorCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
huart->ErrorCode = HAL_UART_ERROR_NONE;
80058f4: 687b ldr r3, [r7, #4]
80058f6: 228c movs r2, #140 ; 0x8c
80058f8: 2100 movs r1, #0
80058fa: 5099 str r1, [r3, r2]
}
}
return;
80058fc: e1b1 b.n 8005c62 <HAL_UART_IRQHandler+0x612>
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
80058fe: 46c0 nop ; (mov r8, r8)
return;
8005900: e1af b.n 8005c62 <HAL_UART_IRQHandler+0x612>
8005902: 46c0 nop ; (mov r8, r8)
8005904: 0000080f .word 0x0000080f
8005908: 10000001 .word 0x10000001
800590c: 04000120 .word 0x04000120
8005910: 08006a09 .word 0x08006a09
} /* End if some error occurs */
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
8005914: 687b ldr r3, [r7, #4]
8005916: 6edb ldr r3, [r3, #108] ; 0x6c
8005918: 2b01 cmp r3, #1
800591a: d000 beq.n 800591e <HAL_UART_IRQHandler+0x2ce>
800591c: e135 b.n 8005b8a <HAL_UART_IRQHandler+0x53a>
&& ((isrflags & USART_ISR_IDLE) != 0U)
800591e: 23a4 movs r3, #164 ; 0xa4
8005920: 18fb adds r3, r7, r3
8005922: 681b ldr r3, [r3, #0]
8005924: 2210 movs r2, #16
8005926: 4013 ands r3, r2
8005928: d100 bne.n 800592c <HAL_UART_IRQHandler+0x2dc>
800592a: e12e b.n 8005b8a <HAL_UART_IRQHandler+0x53a>
&& ((cr1its & USART_ISR_IDLE) != 0U))
800592c: 23a0 movs r3, #160 ; 0xa0
800592e: 18fb adds r3, r7, r3
8005930: 681b ldr r3, [r3, #0]
8005932: 2210 movs r2, #16
8005934: 4013 ands r3, r2
8005936: d100 bne.n 800593a <HAL_UART_IRQHandler+0x2ea>
8005938: e127 b.n 8005b8a <HAL_UART_IRQHandler+0x53a>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
800593a: 687b ldr r3, [r7, #4]
800593c: 681b ldr r3, [r3, #0]
800593e: 2210 movs r2, #16
8005940: 621a str r2, [r3, #32]
/* Check if DMA mode is enabled in UART */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
8005942: 687b ldr r3, [r7, #4]
8005944: 681b ldr r3, [r3, #0]
8005946: 689b ldr r3, [r3, #8]
8005948: 2240 movs r2, #64 ; 0x40
800594a: 4013 ands r3, r2
800594c: 2b40 cmp r3, #64 ; 0x40
800594e: d000 beq.n 8005952 <HAL_UART_IRQHandler+0x302>
8005950: e09e b.n 8005a90 <HAL_UART_IRQHandler+0x440>
{
/* DMA mode enabled */
/* Check received length : If all expected data are received, do nothing,
(DMA cplt callback will be called).
Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx);
8005952: 687b ldr r3, [r7, #4]
8005954: 6fdb ldr r3, [r3, #124] ; 0x7c
8005956: 681b ldr r3, [r3, #0]
8005958: 685a ldr r2, [r3, #4]
800595a: 217e movs r1, #126 ; 0x7e
800595c: 187b adds r3, r7, r1
800595e: 801a strh r2, [r3, #0]
if ((nb_remaining_rx_data > 0U)
8005960: 187b adds r3, r7, r1
8005962: 881b ldrh r3, [r3, #0]
8005964: 2b00 cmp r3, #0
8005966: d100 bne.n 800596a <HAL_UART_IRQHandler+0x31a>
8005968: e17d b.n 8005c66 <HAL_UART_IRQHandler+0x616>
&& (nb_remaining_rx_data < huart->RxXferSize))
800596a: 687b ldr r3, [r7, #4]
800596c: 225c movs r2, #92 ; 0x5c
800596e: 5a9b ldrh r3, [r3, r2]
8005970: 187a adds r2, r7, r1
8005972: 8812 ldrh r2, [r2, #0]
8005974: 429a cmp r2, r3
8005976: d300 bcc.n 800597a <HAL_UART_IRQHandler+0x32a>
8005978: e175 b.n 8005c66 <HAL_UART_IRQHandler+0x616>
{
/* Reception is not complete */
huart->RxXferCount = nb_remaining_rx_data;
800597a: 687b ldr r3, [r7, #4]
800597c: 187a adds r2, r7, r1
800597e: 215e movs r1, #94 ; 0x5e
8005980: 8812 ldrh r2, [r2, #0]
8005982: 525a strh r2, [r3, r1]
/* In Normal mode, end DMA xfer and HAL UART Rx process*/
if (HAL_IS_BIT_CLR(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC))
8005984: 687b ldr r3, [r7, #4]
8005986: 6fdb ldr r3, [r3, #124] ; 0x7c
8005988: 681b ldr r3, [r3, #0]
800598a: 681b ldr r3, [r3, #0]
800598c: 2220 movs r2, #32
800598e: 4013 ands r3, r2
8005990: d16f bne.n 8005a72 <HAL_UART_IRQHandler+0x422>
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8005992: f3ef 8310 mrs r3, PRIMASK
8005996: 633b str r3, [r7, #48] ; 0x30
return(result);
8005998: 6b3b ldr r3, [r7, #48] ; 0x30
{
/* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
800599a: 67bb str r3, [r7, #120] ; 0x78
800599c: 2301 movs r3, #1
800599e: 637b str r3, [r7, #52] ; 0x34
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80059a0: 6b7b ldr r3, [r7, #52] ; 0x34
80059a2: f383 8810 msr PRIMASK, r3
}
80059a6: 46c0 nop ; (mov r8, r8)
80059a8: 687b ldr r3, [r7, #4]
80059aa: 681b ldr r3, [r3, #0]
80059ac: 681a ldr r2, [r3, #0]
80059ae: 687b ldr r3, [r7, #4]
80059b0: 681b ldr r3, [r3, #0]
80059b2: 49b1 ldr r1, [pc, #708] ; (8005c78 <HAL_UART_IRQHandler+0x628>)
80059b4: 400a ands r2, r1
80059b6: 601a str r2, [r3, #0]
80059b8: 6fbb ldr r3, [r7, #120] ; 0x78
80059ba: 63bb str r3, [r7, #56] ; 0x38
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80059bc: 6bbb ldr r3, [r7, #56] ; 0x38
80059be: f383 8810 msr PRIMASK, r3
}
80059c2: 46c0 nop ; (mov r8, r8)
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
80059c4: f3ef 8310 mrs r3, PRIMASK
80059c8: 63fb str r3, [r7, #60] ; 0x3c
return(result);
80059ca: 6bfb ldr r3, [r7, #60] ; 0x3c
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
80059cc: 677b str r3, [r7, #116] ; 0x74
80059ce: 2301 movs r3, #1
80059d0: 643b str r3, [r7, #64] ; 0x40
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80059d2: 6c3b ldr r3, [r7, #64] ; 0x40
80059d4: f383 8810 msr PRIMASK, r3
}
80059d8: 46c0 nop ; (mov r8, r8)
80059da: 687b ldr r3, [r7, #4]
80059dc: 681b ldr r3, [r3, #0]
80059de: 689a ldr r2, [r3, #8]
80059e0: 687b ldr r3, [r7, #4]
80059e2: 681b ldr r3, [r3, #0]
80059e4: 2101 movs r1, #1
80059e6: 438a bics r2, r1
80059e8: 609a str r2, [r3, #8]
80059ea: 6f7b ldr r3, [r7, #116] ; 0x74
80059ec: 647b str r3, [r7, #68] ; 0x44
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80059ee: 6c7b ldr r3, [r7, #68] ; 0x44
80059f0: f383 8810 msr PRIMASK, r3
}
80059f4: 46c0 nop ; (mov r8, r8)
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
80059f6: f3ef 8310 mrs r3, PRIMASK
80059fa: 64bb str r3, [r7, #72] ; 0x48
return(result);
80059fc: 6cbb ldr r3, [r7, #72] ; 0x48
/* Disable the DMA transfer for the receiver request by resetting the DMAR bit
in the UART CR3 register */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
80059fe: 673b str r3, [r7, #112] ; 0x70
8005a00: 2301 movs r3, #1
8005a02: 64fb str r3, [r7, #76] ; 0x4c
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8005a04: 6cfb ldr r3, [r7, #76] ; 0x4c
8005a06: f383 8810 msr PRIMASK, r3
}
8005a0a: 46c0 nop ; (mov r8, r8)
8005a0c: 687b ldr r3, [r7, #4]
8005a0e: 681b ldr r3, [r3, #0]
8005a10: 689a ldr r2, [r3, #8]
8005a12: 687b ldr r3, [r7, #4]
8005a14: 681b ldr r3, [r3, #0]
8005a16: 2140 movs r1, #64 ; 0x40
8005a18: 438a bics r2, r1
8005a1a: 609a str r2, [r3, #8]
8005a1c: 6f3b ldr r3, [r7, #112] ; 0x70
8005a1e: 653b str r3, [r7, #80] ; 0x50
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8005a20: 6d3b ldr r3, [r7, #80] ; 0x50
8005a22: f383 8810 msr PRIMASK, r3
}
8005a26: 46c0 nop ; (mov r8, r8)
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
8005a28: 687b ldr r3, [r7, #4]
8005a2a: 2288 movs r2, #136 ; 0x88
8005a2c: 2120 movs r1, #32
8005a2e: 5099 str r1, [r3, r2]
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8005a30: 687b ldr r3, [r7, #4]
8005a32: 2200 movs r2, #0
8005a34: 66da str r2, [r3, #108] ; 0x6c
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8005a36: f3ef 8310 mrs r3, PRIMASK
8005a3a: 657b str r3, [r7, #84] ; 0x54
return(result);
8005a3c: 6d7b ldr r3, [r7, #84] ; 0x54
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8005a3e: 66fb str r3, [r7, #108] ; 0x6c
8005a40: 2301 movs r3, #1
8005a42: 65bb str r3, [r7, #88] ; 0x58
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8005a44: 6dbb ldr r3, [r7, #88] ; 0x58
8005a46: f383 8810 msr PRIMASK, r3
}
8005a4a: 46c0 nop ; (mov r8, r8)
8005a4c: 687b ldr r3, [r7, #4]
8005a4e: 681b ldr r3, [r3, #0]
8005a50: 681a ldr r2, [r3, #0]
8005a52: 687b ldr r3, [r7, #4]
8005a54: 681b ldr r3, [r3, #0]
8005a56: 2110 movs r1, #16
8005a58: 438a bics r2, r1
8005a5a: 601a str r2, [r3, #0]
8005a5c: 6efb ldr r3, [r7, #108] ; 0x6c
8005a5e: 65fb str r3, [r7, #92] ; 0x5c
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8005a60: 6dfb ldr r3, [r7, #92] ; 0x5c
8005a62: f383 8810 msr PRIMASK, r3
}
8005a66: 46c0 nop ; (mov r8, r8)
/* Last bytes received, so no need as the abort is immediate */
(void)HAL_DMA_Abort(huart->hdmarx);
8005a68: 687b ldr r3, [r7, #4]
8005a6a: 6fdb ldr r3, [r3, #124] ; 0x7c
8005a6c: 0018 movs r0, r3
8005a6e: f7fd fb4f bl 8003110 <HAL_DMA_Abort>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
8005a72: 687b ldr r3, [r7, #4]
8005a74: 225c movs r2, #92 ; 0x5c
8005a76: 5a9a ldrh r2, [r3, r2]
8005a78: 687b ldr r3, [r7, #4]
8005a7a: 215e movs r1, #94 ; 0x5e
8005a7c: 5a5b ldrh r3, [r3, r1]
8005a7e: b29b uxth r3, r3
8005a80: 1ad3 subs r3, r2, r3
8005a82: b29a uxth r2, r3
8005a84: 687b ldr r3, [r7, #4]
8005a86: 0011 movs r1, r2
8005a88: 0018 movs r0, r3
8005a8a: f000 f903 bl 8005c94 <HAL_UARTEx_RxEventCallback>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
return;
8005a8e: e0ea b.n 8005c66 <HAL_UART_IRQHandler+0x616>
else
{
/* DMA mode not enabled */
/* Check received length : If all expected data are received, do nothing.
Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
8005a90: 687b ldr r3, [r7, #4]
8005a92: 225c movs r2, #92 ; 0x5c
8005a94: 5a99 ldrh r1, [r3, r2]
8005a96: 687b ldr r3, [r7, #4]
8005a98: 225e movs r2, #94 ; 0x5e
8005a9a: 5a9b ldrh r3, [r3, r2]
8005a9c: b29a uxth r2, r3
8005a9e: 208e movs r0, #142 ; 0x8e
8005aa0: 183b adds r3, r7, r0
8005aa2: 1a8a subs r2, r1, r2
8005aa4: 801a strh r2, [r3, #0]
if ((huart->RxXferCount > 0U)
8005aa6: 687b ldr r3, [r7, #4]
8005aa8: 225e movs r2, #94 ; 0x5e
8005aaa: 5a9b ldrh r3, [r3, r2]
8005aac: b29b uxth r3, r3
8005aae: 2b00 cmp r3, #0
8005ab0: d100 bne.n 8005ab4 <HAL_UART_IRQHandler+0x464>
8005ab2: e0da b.n 8005c6a <HAL_UART_IRQHandler+0x61a>
&& (nb_rx_data > 0U))
8005ab4: 183b adds r3, r7, r0
8005ab6: 881b ldrh r3, [r3, #0]
8005ab8: 2b00 cmp r3, #0
8005aba: d100 bne.n 8005abe <HAL_UART_IRQHandler+0x46e>
8005abc: e0d5 b.n 8005c6a <HAL_UART_IRQHandler+0x61a>
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8005abe: f3ef 8310 mrs r3, PRIMASK
8005ac2: 60fb str r3, [r7, #12]
return(result);
8005ac4: 68fb ldr r3, [r7, #12]
{
/* Disable the UART Parity Error Interrupt and RXNE interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
8005ac6: 2488 movs r4, #136 ; 0x88
8005ac8: 193a adds r2, r7, r4
8005aca: 6013 str r3, [r2, #0]
8005acc: 2301 movs r3, #1
8005ace: 613b str r3, [r7, #16]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8005ad0: 693b ldr r3, [r7, #16]
8005ad2: f383 8810 msr PRIMASK, r3
}
8005ad6: 46c0 nop ; (mov r8, r8)
8005ad8: 687b ldr r3, [r7, #4]
8005ada: 681b ldr r3, [r3, #0]
8005adc: 681a ldr r2, [r3, #0]
8005ade: 687b ldr r3, [r7, #4]
8005ae0: 681b ldr r3, [r3, #0]
8005ae2: 4966 ldr r1, [pc, #408] ; (8005c7c <HAL_UART_IRQHandler+0x62c>)
8005ae4: 400a ands r2, r1
8005ae6: 601a str r2, [r3, #0]
8005ae8: 193b adds r3, r7, r4
8005aea: 681b ldr r3, [r3, #0]
8005aec: 617b str r3, [r7, #20]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8005aee: 697b ldr r3, [r7, #20]
8005af0: f383 8810 msr PRIMASK, r3
}
8005af4: 46c0 nop ; (mov r8, r8)
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8005af6: f3ef 8310 mrs r3, PRIMASK
8005afa: 61bb str r3, [r7, #24]
return(result);
8005afc: 69bb ldr r3, [r7, #24]
/* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
8005afe: 2484 movs r4, #132 ; 0x84
8005b00: 193a adds r2, r7, r4
8005b02: 6013 str r3, [r2, #0]
8005b04: 2301 movs r3, #1
8005b06: 61fb str r3, [r7, #28]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8005b08: 69fb ldr r3, [r7, #28]
8005b0a: f383 8810 msr PRIMASK, r3
}
8005b0e: 46c0 nop ; (mov r8, r8)
8005b10: 687b ldr r3, [r7, #4]
8005b12: 681b ldr r3, [r3, #0]
8005b14: 689a ldr r2, [r3, #8]
8005b16: 687b ldr r3, [r7, #4]
8005b18: 681b ldr r3, [r3, #0]
8005b1a: 4959 ldr r1, [pc, #356] ; (8005c80 <HAL_UART_IRQHandler+0x630>)
8005b1c: 400a ands r2, r1
8005b1e: 609a str r2, [r3, #8]
8005b20: 193b adds r3, r7, r4
8005b22: 681b ldr r3, [r3, #0]
8005b24: 623b str r3, [r7, #32]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8005b26: 6a3b ldr r3, [r7, #32]
8005b28: f383 8810 msr PRIMASK, r3
}
8005b2c: 46c0 nop ; (mov r8, r8)
/* Rx process is completed, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
8005b2e: 687b ldr r3, [r7, #4]
8005b30: 2288 movs r2, #136 ; 0x88
8005b32: 2120 movs r1, #32
8005b34: 5099 str r1, [r3, r2]
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8005b36: 687b ldr r3, [r7, #4]
8005b38: 2200 movs r2, #0
8005b3a: 66da str r2, [r3, #108] ; 0x6c
/* Clear RxISR function pointer */
huart->RxISR = NULL;
8005b3c: 687b ldr r3, [r7, #4]
8005b3e: 2200 movs r2, #0
8005b40: 671a str r2, [r3, #112] ; 0x70
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8005b42: f3ef 8310 mrs r3, PRIMASK
8005b46: 627b str r3, [r7, #36] ; 0x24
return(result);
8005b48: 6a7b ldr r3, [r7, #36] ; 0x24
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8005b4a: 2480 movs r4, #128 ; 0x80
8005b4c: 193a adds r2, r7, r4
8005b4e: 6013 str r3, [r2, #0]
8005b50: 2301 movs r3, #1
8005b52: 62bb str r3, [r7, #40] ; 0x28
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8005b54: 6abb ldr r3, [r7, #40] ; 0x28
8005b56: f383 8810 msr PRIMASK, r3
}
8005b5a: 46c0 nop ; (mov r8, r8)
8005b5c: 687b ldr r3, [r7, #4]
8005b5e: 681b ldr r3, [r3, #0]
8005b60: 681a ldr r2, [r3, #0]
8005b62: 687b ldr r3, [r7, #4]
8005b64: 681b ldr r3, [r3, #0]
8005b66: 2110 movs r1, #16
8005b68: 438a bics r2, r1
8005b6a: 601a str r2, [r3, #0]
8005b6c: 193b adds r3, r7, r4
8005b6e: 681b ldr r3, [r3, #0]
8005b70: 62fb str r3, [r7, #44] ; 0x2c
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8005b72: 6afb ldr r3, [r7, #44] ; 0x2c
8005b74: f383 8810 msr PRIMASK, r3
}
8005b78: 46c0 nop ; (mov r8, r8)
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx complete callback*/
huart->RxEventCallback(huart, nb_rx_data);
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, nb_rx_data);
8005b7a: 183b adds r3, r7, r0
8005b7c: 881a ldrh r2, [r3, #0]
8005b7e: 687b ldr r3, [r7, #4]
8005b80: 0011 movs r1, r2
8005b82: 0018 movs r0, r3
8005b84: f000 f886 bl 8005c94 <HAL_UARTEx_RxEventCallback>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
return;
8005b88: e06f b.n 8005c6a <HAL_UART_IRQHandler+0x61a>
}
}
/* UART wakeup from Stop mode interrupt occurred ---------------------------*/
if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U))
8005b8a: 23a4 movs r3, #164 ; 0xa4
8005b8c: 18fb adds r3, r7, r3
8005b8e: 681a ldr r2, [r3, #0]
8005b90: 2380 movs r3, #128 ; 0x80
8005b92: 035b lsls r3, r3, #13
8005b94: 4013 ands r3, r2
8005b96: d010 beq.n 8005bba <HAL_UART_IRQHandler+0x56a>
8005b98: 239c movs r3, #156 ; 0x9c
8005b9a: 18fb adds r3, r7, r3
8005b9c: 681a ldr r2, [r3, #0]
8005b9e: 2380 movs r3, #128 ; 0x80
8005ba0: 03db lsls r3, r3, #15
8005ba2: 4013 ands r3, r2
8005ba4: d009 beq.n 8005bba <HAL_UART_IRQHandler+0x56a>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF);
8005ba6: 687b ldr r3, [r7, #4]
8005ba8: 681b ldr r3, [r3, #0]
8005baa: 2280 movs r2, #128 ; 0x80
8005bac: 0352 lsls r2, r2, #13
8005bae: 621a str r2, [r3, #32]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/* Call registered Wakeup Callback */
huart->WakeupCallback(huart);
#else
/* Call legacy weak Wakeup Callback */
HAL_UARTEx_WakeupCallback(huart);
8005bb0: 687b ldr r3, [r7, #4]
8005bb2: 0018 movs r0, r3
8005bb4: f001 fbbc bl 8007330 <HAL_UARTEx_WakeupCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
return;
8005bb8: e05a b.n 8005c70 <HAL_UART_IRQHandler+0x620>
}
/* UART in mode Transmitter ------------------------------------------------*/
if (((isrflags & USART_ISR_TXE_TXFNF) != 0U)
8005bba: 23a4 movs r3, #164 ; 0xa4
8005bbc: 18fb adds r3, r7, r3
8005bbe: 681b ldr r3, [r3, #0]
8005bc0: 2280 movs r2, #128 ; 0x80
8005bc2: 4013 ands r3, r2
8005bc4: d016 beq.n 8005bf4 <HAL_UART_IRQHandler+0x5a4>
&& (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)
8005bc6: 23a0 movs r3, #160 ; 0xa0
8005bc8: 18fb adds r3, r7, r3
8005bca: 681b ldr r3, [r3, #0]
8005bcc: 2280 movs r2, #128 ; 0x80
8005bce: 4013 ands r3, r2
8005bd0: d106 bne.n 8005be0 <HAL_UART_IRQHandler+0x590>
|| ((cr3its & USART_CR3_TXFTIE) != 0U)))
8005bd2: 239c movs r3, #156 ; 0x9c
8005bd4: 18fb adds r3, r7, r3
8005bd6: 681a ldr r2, [r3, #0]
8005bd8: 2380 movs r3, #128 ; 0x80
8005bda: 041b lsls r3, r3, #16
8005bdc: 4013 ands r3, r2
8005bde: d009 beq.n 8005bf4 <HAL_UART_IRQHandler+0x5a4>
{
if (huart->TxISR != NULL)
8005be0: 687b ldr r3, [r7, #4]
8005be2: 6f5b ldr r3, [r3, #116] ; 0x74
8005be4: 2b00 cmp r3, #0
8005be6: d042 beq.n 8005c6e <HAL_UART_IRQHandler+0x61e>
{
huart->TxISR(huart);
8005be8: 687b ldr r3, [r7, #4]
8005bea: 6f5b ldr r3, [r3, #116] ; 0x74
8005bec: 687a ldr r2, [r7, #4]
8005bee: 0010 movs r0, r2
8005bf0: 4798 blx r3
}
return;
8005bf2: e03c b.n 8005c6e <HAL_UART_IRQHandler+0x61e>
}
/* UART in mode Transmitter (transmission end) -----------------------------*/
if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
8005bf4: 23a4 movs r3, #164 ; 0xa4
8005bf6: 18fb adds r3, r7, r3
8005bf8: 681b ldr r3, [r3, #0]
8005bfa: 2240 movs r2, #64 ; 0x40
8005bfc: 4013 ands r3, r2
8005bfe: d00a beq.n 8005c16 <HAL_UART_IRQHandler+0x5c6>
8005c00: 23a0 movs r3, #160 ; 0xa0
8005c02: 18fb adds r3, r7, r3
8005c04: 681b ldr r3, [r3, #0]
8005c06: 2240 movs r2, #64 ; 0x40
8005c08: 4013 ands r3, r2
8005c0a: d004 beq.n 8005c16 <HAL_UART_IRQHandler+0x5c6>
{
UART_EndTransmit_IT(huart);
8005c0c: 687b ldr r3, [r7, #4]
8005c0e: 0018 movs r0, r3
8005c10: f000 ff11 bl 8006a36 <UART_EndTransmit_IT>
return;
8005c14: e02c b.n 8005c70 <HAL_UART_IRQHandler+0x620>
}
/* UART TX Fifo Empty occurred ----------------------------------------------*/
if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U))
8005c16: 23a4 movs r3, #164 ; 0xa4
8005c18: 18fb adds r3, r7, r3
8005c1a: 681a ldr r2, [r3, #0]
8005c1c: 2380 movs r3, #128 ; 0x80
8005c1e: 041b lsls r3, r3, #16
8005c20: 4013 ands r3, r2
8005c22: d00b beq.n 8005c3c <HAL_UART_IRQHandler+0x5ec>
8005c24: 23a0 movs r3, #160 ; 0xa0
8005c26: 18fb adds r3, r7, r3
8005c28: 681a ldr r2, [r3, #0]
8005c2a: 2380 movs r3, #128 ; 0x80
8005c2c: 05db lsls r3, r3, #23
8005c2e: 4013 ands r3, r2
8005c30: d004 beq.n 8005c3c <HAL_UART_IRQHandler+0x5ec>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/* Call registered Tx Fifo Empty Callback */
huart->TxFifoEmptyCallback(huart);
#else
/* Call legacy weak Tx Fifo Empty Callback */
HAL_UARTEx_TxFifoEmptyCallback(huart);
8005c32: 687b ldr r3, [r7, #4]
8005c34: 0018 movs r0, r3
8005c36: f001 fb8b bl 8007350 <HAL_UARTEx_TxFifoEmptyCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
return;
8005c3a: e019 b.n 8005c70 <HAL_UART_IRQHandler+0x620>
}
/* UART RX Fifo Full occurred ----------------------------------------------*/
if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U))
8005c3c: 23a4 movs r3, #164 ; 0xa4
8005c3e: 18fb adds r3, r7, r3
8005c40: 681a ldr r2, [r3, #0]
8005c42: 2380 movs r3, #128 ; 0x80
8005c44: 045b lsls r3, r3, #17
8005c46: 4013 ands r3, r2
8005c48: d012 beq.n 8005c70 <HAL_UART_IRQHandler+0x620>
8005c4a: 23a0 movs r3, #160 ; 0xa0
8005c4c: 18fb adds r3, r7, r3
8005c4e: 681b ldr r3, [r3, #0]
8005c50: 2b00 cmp r3, #0
8005c52: da0d bge.n 8005c70 <HAL_UART_IRQHandler+0x620>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/* Call registered Rx Fifo Full Callback */
huart->RxFifoFullCallback(huart);
#else
/* Call legacy weak Rx Fifo Full Callback */
HAL_UARTEx_RxFifoFullCallback(huart);
8005c54: 687b ldr r3, [r7, #4]
8005c56: 0018 movs r0, r3
8005c58: f001 fb72 bl 8007340 <HAL_UARTEx_RxFifoFullCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
return;
8005c5c: e008 b.n 8005c70 <HAL_UART_IRQHandler+0x620>
return;
8005c5e: 46c0 nop ; (mov r8, r8)
8005c60: e006 b.n 8005c70 <HAL_UART_IRQHandler+0x620>
return;
8005c62: 46c0 nop ; (mov r8, r8)
8005c64: e004 b.n 8005c70 <HAL_UART_IRQHandler+0x620>
return;
8005c66: 46c0 nop ; (mov r8, r8)
8005c68: e002 b.n 8005c70 <HAL_UART_IRQHandler+0x620>
return;
8005c6a: 46c0 nop ; (mov r8, r8)
8005c6c: e000 b.n 8005c70 <HAL_UART_IRQHandler+0x620>
return;
8005c6e: 46c0 nop ; (mov r8, r8)
}
}
8005c70: 46bd mov sp, r7
8005c72: b02a add sp, #168 ; 0xa8
8005c74: bdb0 pop {r4, r5, r7, pc}
8005c76: 46c0 nop ; (mov r8, r8)
8005c78: fffffeff .word 0xfffffeff
8005c7c: fffffedf .word 0xfffffedf
8005c80: effffffe .word 0xeffffffe
08005c84 <HAL_UART_TxHalfCpltCallback>:
* @brief Tx Half Transfer completed callback.
* @param huart UART handle.
* @retval None
*/
__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
{
8005c84: b580 push {r7, lr}
8005c86: b082 sub sp, #8
8005c88: af00 add r7, sp, #0
8005c8a: 6078 str r0, [r7, #4]
UNUSED(huart);
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_UART_TxHalfCpltCallback can be implemented in the user file.
*/
}
8005c8c: 46c0 nop ; (mov r8, r8)
8005c8e: 46bd mov sp, r7
8005c90: b002 add sp, #8
8005c92: bd80 pop {r7, pc}
08005c94 <HAL_UARTEx_RxEventCallback>:
* @param Size Number of data available in application reception buffer (indicates a position in
* reception buffer until which, data are available)
* @retval None
*/
__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size)
{
8005c94: b580 push {r7, lr}
8005c96: b082 sub sp, #8
8005c98: af00 add r7, sp, #0
8005c9a: 6078 str r0, [r7, #4]
8005c9c: 000a movs r2, r1
8005c9e: 1cbb adds r3, r7, #2
8005ca0: 801a strh r2, [r3, #0]
UNUSED(Size);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_UARTEx_RxEventCallback can be implemented in the user file.
*/
}
8005ca2: 46c0 nop ; (mov r8, r8)
8005ca4: 46bd mov sp, r7
8005ca6: b002 add sp, #8
8005ca8: bd80 pop {r7, pc}
...
08005cac <UART_SetConfig>:
* @brief Configure the UART peripheral.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
{
8005cac: b5b0 push {r4, r5, r7, lr}
8005cae: b090 sub sp, #64 ; 0x40
8005cb0: af00 add r7, sp, #0
8005cb2: 6278 str r0, [r7, #36] ; 0x24
uint32_t tmpreg;
uint16_t brrtemp;
UART_ClockSourceTypeDef clocksource;
uint32_t usartdiv;
HAL_StatusTypeDef ret = HAL_OK;
8005cb4: 231a movs r3, #26
8005cb6: 2220 movs r2, #32
8005cb8: 189b adds r3, r3, r2
8005cba: 19db adds r3, r3, r7
8005cbc: 2200 movs r2, #0
8005cbe: 701a strb r2, [r3, #0]
* the UART Word Length, Parity, Mode and oversampling:
* set the M bits according to huart->Init.WordLength value
* set PCE and PS bits according to huart->Init.Parity value
* set TE and RE bits according to huart->Init.Mode value
* set OVER8 bit according to huart->Init.OverSampling value */
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
8005cc0: 6a7b ldr r3, [r7, #36] ; 0x24
8005cc2: 689a ldr r2, [r3, #8]
8005cc4: 6a7b ldr r3, [r7, #36] ; 0x24
8005cc6: 691b ldr r3, [r3, #16]
8005cc8: 431a orrs r2, r3
8005cca: 6a7b ldr r3, [r7, #36] ; 0x24
8005ccc: 695b ldr r3, [r3, #20]
8005cce: 431a orrs r2, r3
8005cd0: 6a7b ldr r3, [r7, #36] ; 0x24
8005cd2: 69db ldr r3, [r3, #28]
8005cd4: 4313 orrs r3, r2
8005cd6: 63fb str r3, [r7, #60] ; 0x3c
MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
8005cd8: 6a7b ldr r3, [r7, #36] ; 0x24
8005cda: 681b ldr r3, [r3, #0]
8005cdc: 681b ldr r3, [r3, #0]
8005cde: 4ac4 ldr r2, [pc, #784] ; (8005ff0 <UART_SetConfig+0x344>)
8005ce0: 4013 ands r3, r2
8005ce2: 0019 movs r1, r3
8005ce4: 6a7b ldr r3, [r7, #36] ; 0x24
8005ce6: 681a ldr r2, [r3, #0]
8005ce8: 6bfb ldr r3, [r7, #60] ; 0x3c
8005cea: 430b orrs r3, r1
8005cec: 6013 str r3, [r2, #0]
/*-------------------------- USART CR2 Configuration -----------------------*/
/* Configure the UART Stop Bits: Set STOP[13:12] bits according
* to huart->Init.StopBits value */
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
8005cee: 6a7b ldr r3, [r7, #36] ; 0x24
8005cf0: 681b ldr r3, [r3, #0]
8005cf2: 685b ldr r3, [r3, #4]
8005cf4: 4abf ldr r2, [pc, #764] ; (8005ff4 <UART_SetConfig+0x348>)
8005cf6: 4013 ands r3, r2
8005cf8: 0018 movs r0, r3
8005cfa: 6a7b ldr r3, [r7, #36] ; 0x24
8005cfc: 68d9 ldr r1, [r3, #12]
8005cfe: 6a7b ldr r3, [r7, #36] ; 0x24
8005d00: 681a ldr r2, [r3, #0]
8005d02: 0003 movs r3, r0
8005d04: 430b orrs r3, r1
8005d06: 6053 str r3, [r2, #4]
/* Configure
* - UART HardWare Flow Control: set CTSE and RTSE bits according
* to huart->Init.HwFlowCtl value
* - one-bit sampling method versus three samples' majority rule according
* to huart->Init.OneBitSampling (not applicable to LPUART) */
tmpreg = (uint32_t)huart->Init.HwFlowCtl;
8005d08: 6a7b ldr r3, [r7, #36] ; 0x24
8005d0a: 699b ldr r3, [r3, #24]
8005d0c: 63fb str r3, [r7, #60] ; 0x3c
if (!(UART_INSTANCE_LOWPOWER(huart)))
8005d0e: 6a7b ldr r3, [r7, #36] ; 0x24
8005d10: 681b ldr r3, [r3, #0]
8005d12: 4ab9 ldr r2, [pc, #740] ; (8005ff8 <UART_SetConfig+0x34c>)
8005d14: 4293 cmp r3, r2
8005d16: d004 beq.n 8005d22 <UART_SetConfig+0x76>
{
tmpreg |= huart->Init.OneBitSampling;
8005d18: 6a7b ldr r3, [r7, #36] ; 0x24
8005d1a: 6a1b ldr r3, [r3, #32]
8005d1c: 6bfa ldr r2, [r7, #60] ; 0x3c
8005d1e: 4313 orrs r3, r2
8005d20: 63fb str r3, [r7, #60] ; 0x3c
}
MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
8005d22: 6a7b ldr r3, [r7, #36] ; 0x24
8005d24: 681b ldr r3, [r3, #0]
8005d26: 689b ldr r3, [r3, #8]
8005d28: 4ab4 ldr r2, [pc, #720] ; (8005ffc <UART_SetConfig+0x350>)
8005d2a: 4013 ands r3, r2
8005d2c: 0019 movs r1, r3
8005d2e: 6a7b ldr r3, [r7, #36] ; 0x24
8005d30: 681a ldr r2, [r3, #0]
8005d32: 6bfb ldr r3, [r7, #60] ; 0x3c
8005d34: 430b orrs r3, r1
8005d36: 6093 str r3, [r2, #8]
/*-------------------------- USART PRESC Configuration -----------------------*/
/* Configure
* - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */
MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
8005d38: 6a7b ldr r3, [r7, #36] ; 0x24
8005d3a: 681b ldr r3, [r3, #0]
8005d3c: 6adb ldr r3, [r3, #44] ; 0x2c
8005d3e: 220f movs r2, #15
8005d40: 4393 bics r3, r2
8005d42: 0018 movs r0, r3
8005d44: 6a7b ldr r3, [r7, #36] ; 0x24
8005d46: 6a59 ldr r1, [r3, #36] ; 0x24
8005d48: 6a7b ldr r3, [r7, #36] ; 0x24
8005d4a: 681a ldr r2, [r3, #0]
8005d4c: 0003 movs r3, r0
8005d4e: 430b orrs r3, r1
8005d50: 62d3 str r3, [r2, #44] ; 0x2c
/*-------------------------- USART BRR Configuration -----------------------*/
UART_GETCLOCKSOURCE(huart, clocksource);
8005d52: 6a7b ldr r3, [r7, #36] ; 0x24
8005d54: 681b ldr r3, [r3, #0]
8005d56: 4aaa ldr r2, [pc, #680] ; (8006000 <UART_SetConfig+0x354>)
8005d58: 4293 cmp r3, r2
8005d5a: d131 bne.n 8005dc0 <UART_SetConfig+0x114>
8005d5c: 4ba9 ldr r3, [pc, #676] ; (8006004 <UART_SetConfig+0x358>)
8005d5e: 6d5b ldr r3, [r3, #84] ; 0x54
8005d60: 2203 movs r2, #3
8005d62: 4013 ands r3, r2
8005d64: 2b03 cmp r3, #3
8005d66: d01d beq.n 8005da4 <UART_SetConfig+0xf8>
8005d68: d823 bhi.n 8005db2 <UART_SetConfig+0x106>
8005d6a: 2b02 cmp r3, #2
8005d6c: d00c beq.n 8005d88 <UART_SetConfig+0xdc>
8005d6e: d820 bhi.n 8005db2 <UART_SetConfig+0x106>
8005d70: 2b00 cmp r3, #0
8005d72: d002 beq.n 8005d7a <UART_SetConfig+0xce>
8005d74: 2b01 cmp r3, #1
8005d76: d00e beq.n 8005d96 <UART_SetConfig+0xea>
8005d78: e01b b.n 8005db2 <UART_SetConfig+0x106>
8005d7a: 231b movs r3, #27
8005d7c: 2220 movs r2, #32
8005d7e: 189b adds r3, r3, r2
8005d80: 19db adds r3, r3, r7
8005d82: 2200 movs r2, #0
8005d84: 701a strb r2, [r3, #0]
8005d86: e071 b.n 8005e6c <UART_SetConfig+0x1c0>
8005d88: 231b movs r3, #27
8005d8a: 2220 movs r2, #32
8005d8c: 189b adds r3, r3, r2
8005d8e: 19db adds r3, r3, r7
8005d90: 2202 movs r2, #2
8005d92: 701a strb r2, [r3, #0]
8005d94: e06a b.n 8005e6c <UART_SetConfig+0x1c0>
8005d96: 231b movs r3, #27
8005d98: 2220 movs r2, #32
8005d9a: 189b adds r3, r3, r2
8005d9c: 19db adds r3, r3, r7
8005d9e: 2204 movs r2, #4
8005da0: 701a strb r2, [r3, #0]
8005da2: e063 b.n 8005e6c <UART_SetConfig+0x1c0>
8005da4: 231b movs r3, #27
8005da6: 2220 movs r2, #32
8005da8: 189b adds r3, r3, r2
8005daa: 19db adds r3, r3, r7
8005dac: 2208 movs r2, #8
8005dae: 701a strb r2, [r3, #0]
8005db0: e05c b.n 8005e6c <UART_SetConfig+0x1c0>
8005db2: 231b movs r3, #27
8005db4: 2220 movs r2, #32
8005db6: 189b adds r3, r3, r2
8005db8: 19db adds r3, r3, r7
8005dba: 2210 movs r2, #16
8005dbc: 701a strb r2, [r3, #0]
8005dbe: e055 b.n 8005e6c <UART_SetConfig+0x1c0>
8005dc0: 6a7b ldr r3, [r7, #36] ; 0x24
8005dc2: 681b ldr r3, [r3, #0]
8005dc4: 4a90 ldr r2, [pc, #576] ; (8006008 <UART_SetConfig+0x35c>)
8005dc6: 4293 cmp r3, r2
8005dc8: d106 bne.n 8005dd8 <UART_SetConfig+0x12c>
8005dca: 231b movs r3, #27
8005dcc: 2220 movs r2, #32
8005dce: 189b adds r3, r3, r2
8005dd0: 19db adds r3, r3, r7
8005dd2: 2200 movs r2, #0
8005dd4: 701a strb r2, [r3, #0]
8005dd6: e049 b.n 8005e6c <UART_SetConfig+0x1c0>
8005dd8: 6a7b ldr r3, [r7, #36] ; 0x24
8005dda: 681b ldr r3, [r3, #0]
8005ddc: 4a86 ldr r2, [pc, #536] ; (8005ff8 <UART_SetConfig+0x34c>)
8005dde: 4293 cmp r3, r2
8005de0: d13e bne.n 8005e60 <UART_SetConfig+0x1b4>
8005de2: 4b88 ldr r3, [pc, #544] ; (8006004 <UART_SetConfig+0x358>)
8005de4: 6d5a ldr r2, [r3, #84] ; 0x54
8005de6: 23c0 movs r3, #192 ; 0xc0
8005de8: 011b lsls r3, r3, #4
8005dea: 4013 ands r3, r2
8005dec: 22c0 movs r2, #192 ; 0xc0
8005dee: 0112 lsls r2, r2, #4
8005df0: 4293 cmp r3, r2
8005df2: d027 beq.n 8005e44 <UART_SetConfig+0x198>
8005df4: 22c0 movs r2, #192 ; 0xc0
8005df6: 0112 lsls r2, r2, #4
8005df8: 4293 cmp r3, r2
8005dfa: d82a bhi.n 8005e52 <UART_SetConfig+0x1a6>
8005dfc: 2280 movs r2, #128 ; 0x80
8005dfe: 0112 lsls r2, r2, #4
8005e00: 4293 cmp r3, r2
8005e02: d011 beq.n 8005e28 <UART_SetConfig+0x17c>
8005e04: 2280 movs r2, #128 ; 0x80
8005e06: 0112 lsls r2, r2, #4
8005e08: 4293 cmp r3, r2
8005e0a: d822 bhi.n 8005e52 <UART_SetConfig+0x1a6>
8005e0c: 2b00 cmp r3, #0
8005e0e: d004 beq.n 8005e1a <UART_SetConfig+0x16e>
8005e10: 2280 movs r2, #128 ; 0x80
8005e12: 00d2 lsls r2, r2, #3
8005e14: 4293 cmp r3, r2
8005e16: d00e beq.n 8005e36 <UART_SetConfig+0x18a>
8005e18: e01b b.n 8005e52 <UART_SetConfig+0x1a6>
8005e1a: 231b movs r3, #27
8005e1c: 2220 movs r2, #32
8005e1e: 189b adds r3, r3, r2
8005e20: 19db adds r3, r3, r7
8005e22: 2200 movs r2, #0
8005e24: 701a strb r2, [r3, #0]
8005e26: e021 b.n 8005e6c <UART_SetConfig+0x1c0>
8005e28: 231b movs r3, #27
8005e2a: 2220 movs r2, #32
8005e2c: 189b adds r3, r3, r2
8005e2e: 19db adds r3, r3, r7
8005e30: 2202 movs r2, #2
8005e32: 701a strb r2, [r3, #0]
8005e34: e01a b.n 8005e6c <UART_SetConfig+0x1c0>
8005e36: 231b movs r3, #27
8005e38: 2220 movs r2, #32
8005e3a: 189b adds r3, r3, r2
8005e3c: 19db adds r3, r3, r7
8005e3e: 2204 movs r2, #4
8005e40: 701a strb r2, [r3, #0]
8005e42: e013 b.n 8005e6c <UART_SetConfig+0x1c0>
8005e44: 231b movs r3, #27
8005e46: 2220 movs r2, #32
8005e48: 189b adds r3, r3, r2
8005e4a: 19db adds r3, r3, r7
8005e4c: 2208 movs r2, #8
8005e4e: 701a strb r2, [r3, #0]
8005e50: e00c b.n 8005e6c <UART_SetConfig+0x1c0>
8005e52: 231b movs r3, #27
8005e54: 2220 movs r2, #32
8005e56: 189b adds r3, r3, r2
8005e58: 19db adds r3, r3, r7
8005e5a: 2210 movs r2, #16
8005e5c: 701a strb r2, [r3, #0]
8005e5e: e005 b.n 8005e6c <UART_SetConfig+0x1c0>
8005e60: 231b movs r3, #27
8005e62: 2220 movs r2, #32
8005e64: 189b adds r3, r3, r2
8005e66: 19db adds r3, r3, r7
8005e68: 2210 movs r2, #16
8005e6a: 701a strb r2, [r3, #0]
/* Check LPUART instance */
if (UART_INSTANCE_LOWPOWER(huart))
8005e6c: 6a7b ldr r3, [r7, #36] ; 0x24
8005e6e: 681b ldr r3, [r3, #0]
8005e70: 4a61 ldr r2, [pc, #388] ; (8005ff8 <UART_SetConfig+0x34c>)
8005e72: 4293 cmp r3, r2
8005e74: d000 beq.n 8005e78 <UART_SetConfig+0x1cc>
8005e76: e092 b.n 8005f9e <UART_SetConfig+0x2f2>
{
/* Retrieve frequency clock */
switch (clocksource)
8005e78: 231b movs r3, #27
8005e7a: 2220 movs r2, #32
8005e7c: 189b adds r3, r3, r2
8005e7e: 19db adds r3, r3, r7
8005e80: 781b ldrb r3, [r3, #0]
8005e82: 2b08 cmp r3, #8
8005e84: d015 beq.n 8005eb2 <UART_SetConfig+0x206>
8005e86: dc18 bgt.n 8005eba <UART_SetConfig+0x20e>
8005e88: 2b04 cmp r3, #4
8005e8a: d00d beq.n 8005ea8 <UART_SetConfig+0x1fc>
8005e8c: dc15 bgt.n 8005eba <UART_SetConfig+0x20e>
8005e8e: 2b00 cmp r3, #0
8005e90: d002 beq.n 8005e98 <UART_SetConfig+0x1ec>
8005e92: 2b02 cmp r3, #2
8005e94: d005 beq.n 8005ea2 <UART_SetConfig+0x1f6>
8005e96: e010 b.n 8005eba <UART_SetConfig+0x20e>
{
case UART_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
8005e98: f7fe f9c4 bl 8004224 <HAL_RCC_GetPCLK1Freq>
8005e9c: 0003 movs r3, r0
8005e9e: 637b str r3, [r7, #52] ; 0x34
break;
8005ea0: e014 b.n 8005ecc <UART_SetConfig+0x220>
case UART_CLOCKSOURCE_HSI:
pclk = (uint32_t) HSI_VALUE;
8005ea2: 4b5a ldr r3, [pc, #360] ; (800600c <UART_SetConfig+0x360>)
8005ea4: 637b str r3, [r7, #52] ; 0x34
break;
8005ea6: e011 b.n 8005ecc <UART_SetConfig+0x220>
case UART_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
8005ea8: f7fe f930 bl 800410c <HAL_RCC_GetSysClockFreq>
8005eac: 0003 movs r3, r0
8005eae: 637b str r3, [r7, #52] ; 0x34
break;
8005eb0: e00c b.n 8005ecc <UART_SetConfig+0x220>
case UART_CLOCKSOURCE_LSE:
pclk = (uint32_t) LSE_VALUE;
8005eb2: 2380 movs r3, #128 ; 0x80
8005eb4: 021b lsls r3, r3, #8
8005eb6: 637b str r3, [r7, #52] ; 0x34
break;
8005eb8: e008 b.n 8005ecc <UART_SetConfig+0x220>
default:
pclk = 0U;
8005eba: 2300 movs r3, #0
8005ebc: 637b str r3, [r7, #52] ; 0x34
ret = HAL_ERROR;
8005ebe: 231a movs r3, #26
8005ec0: 2220 movs r2, #32
8005ec2: 189b adds r3, r3, r2
8005ec4: 19db adds r3, r3, r7
8005ec6: 2201 movs r2, #1
8005ec8: 701a strb r2, [r3, #0]
break;
8005eca: 46c0 nop ; (mov r8, r8)
}
/* If proper clock source reported */
if (pclk != 0U)
8005ecc: 6b7b ldr r3, [r7, #52] ; 0x34
8005ece: 2b00 cmp r3, #0
8005ed0: d100 bne.n 8005ed4 <UART_SetConfig+0x228>
8005ed2: e147 b.n 8006164 <UART_SetConfig+0x4b8>
{
/* Compute clock after Prescaler */
lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]);
8005ed4: 6a7b ldr r3, [r7, #36] ; 0x24
8005ed6: 6a5a ldr r2, [r3, #36] ; 0x24
8005ed8: 4b4d ldr r3, [pc, #308] ; (8006010 <UART_SetConfig+0x364>)
8005eda: 0052 lsls r2, r2, #1
8005edc: 5ad3 ldrh r3, [r2, r3]
8005ede: 0019 movs r1, r3
8005ee0: 6b78 ldr r0, [r7, #52] ; 0x34
8005ee2: f7fa f90f bl 8000104 <__udivsi3>
8005ee6: 0003 movs r3, r0
8005ee8: 62bb str r3, [r7, #40] ; 0x28
/* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */
if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) ||
8005eea: 6a7b ldr r3, [r7, #36] ; 0x24
8005eec: 685a ldr r2, [r3, #4]
8005eee: 0013 movs r3, r2
8005ef0: 005b lsls r3, r3, #1
8005ef2: 189b adds r3, r3, r2
8005ef4: 6aba ldr r2, [r7, #40] ; 0x28
8005ef6: 429a cmp r2, r3
8005ef8: d305 bcc.n 8005f06 <UART_SetConfig+0x25a>
(lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate)))
8005efa: 6a7b ldr r3, [r7, #36] ; 0x24
8005efc: 685b ldr r3, [r3, #4]
8005efe: 031b lsls r3, r3, #12
if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) ||
8005f00: 6aba ldr r2, [r7, #40] ; 0x28
8005f02: 429a cmp r2, r3
8005f04: d906 bls.n 8005f14 <UART_SetConfig+0x268>
{
ret = HAL_ERROR;
8005f06: 231a movs r3, #26
8005f08: 2220 movs r2, #32
8005f0a: 189b adds r3, r3, r2
8005f0c: 19db adds r3, r3, r7
8005f0e: 2201 movs r2, #1
8005f10: 701a strb r2, [r3, #0]
8005f12: e127 b.n 8006164 <UART_SetConfig+0x4b8>
}
else
{
/* Check computed UsartDiv value is in allocated range
(it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */
usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
8005f14: 6b7b ldr r3, [r7, #52] ; 0x34
8005f16: 61bb str r3, [r7, #24]
8005f18: 2300 movs r3, #0
8005f1a: 61fb str r3, [r7, #28]
8005f1c: 6a7b ldr r3, [r7, #36] ; 0x24
8005f1e: 6a5a ldr r2, [r3, #36] ; 0x24
8005f20: 4b3b ldr r3, [pc, #236] ; (8006010 <UART_SetConfig+0x364>)
8005f22: 0052 lsls r2, r2, #1
8005f24: 5ad3 ldrh r3, [r2, r3]
8005f26: 613b str r3, [r7, #16]
8005f28: 2300 movs r3, #0
8005f2a: 617b str r3, [r7, #20]
8005f2c: 693a ldr r2, [r7, #16]
8005f2e: 697b ldr r3, [r7, #20]
8005f30: 69b8 ldr r0, [r7, #24]
8005f32: 69f9 ldr r1, [r7, #28]
8005f34: f7fa f972 bl 800021c <__aeabi_uldivmod>
8005f38: 0002 movs r2, r0
8005f3a: 000b movs r3, r1
8005f3c: 0e11 lsrs r1, r2, #24
8005f3e: 021d lsls r5, r3, #8
8005f40: 430d orrs r5, r1
8005f42: 0214 lsls r4, r2, #8
8005f44: 6a7b ldr r3, [r7, #36] ; 0x24
8005f46: 685b ldr r3, [r3, #4]
8005f48: 085b lsrs r3, r3, #1
8005f4a: 60bb str r3, [r7, #8]
8005f4c: 2300 movs r3, #0
8005f4e: 60fb str r3, [r7, #12]
8005f50: 68b8 ldr r0, [r7, #8]
8005f52: 68f9 ldr r1, [r7, #12]
8005f54: 1900 adds r0, r0, r4
8005f56: 4169 adcs r1, r5
8005f58: 6a7b ldr r3, [r7, #36] ; 0x24
8005f5a: 685b ldr r3, [r3, #4]
8005f5c: 603b str r3, [r7, #0]
8005f5e: 2300 movs r3, #0
8005f60: 607b str r3, [r7, #4]
8005f62: 683a ldr r2, [r7, #0]
8005f64: 687b ldr r3, [r7, #4]
8005f66: f7fa f959 bl 800021c <__aeabi_uldivmod>
8005f6a: 0002 movs r2, r0
8005f6c: 000b movs r3, r1
8005f6e: 0013 movs r3, r2
8005f70: 633b str r3, [r7, #48] ; 0x30
if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))
8005f72: 6b3a ldr r2, [r7, #48] ; 0x30
8005f74: 23c0 movs r3, #192 ; 0xc0
8005f76: 009b lsls r3, r3, #2
8005f78: 429a cmp r2, r3
8005f7a: d309 bcc.n 8005f90 <UART_SetConfig+0x2e4>
8005f7c: 6b3a ldr r2, [r7, #48] ; 0x30
8005f7e: 2380 movs r3, #128 ; 0x80
8005f80: 035b lsls r3, r3, #13
8005f82: 429a cmp r2, r3
8005f84: d204 bcs.n 8005f90 <UART_SetConfig+0x2e4>
{
huart->Instance->BRR = usartdiv;
8005f86: 6a7b ldr r3, [r7, #36] ; 0x24
8005f88: 681b ldr r3, [r3, #0]
8005f8a: 6b3a ldr r2, [r7, #48] ; 0x30
8005f8c: 60da str r2, [r3, #12]
8005f8e: e0e9 b.n 8006164 <UART_SetConfig+0x4b8>
}
else
{
ret = HAL_ERROR;
8005f90: 231a movs r3, #26
8005f92: 2220 movs r2, #32
8005f94: 189b adds r3, r3, r2
8005f96: 19db adds r3, r3, r7
8005f98: 2201 movs r2, #1
8005f9a: 701a strb r2, [r3, #0]
8005f9c: e0e2 b.n 8006164 <UART_SetConfig+0x4b8>
} /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) ||
(lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */
} /* if (pclk != 0) */
}
/* Check UART Over Sampling to set Baud Rate Register */
else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
8005f9e: 6a7b ldr r3, [r7, #36] ; 0x24
8005fa0: 69da ldr r2, [r3, #28]
8005fa2: 2380 movs r3, #128 ; 0x80
8005fa4: 021b lsls r3, r3, #8
8005fa6: 429a cmp r2, r3
8005fa8: d000 beq.n 8005fac <UART_SetConfig+0x300>
8005faa: e083 b.n 80060b4 <UART_SetConfig+0x408>
{
switch (clocksource)
8005fac: 231b movs r3, #27
8005fae: 2220 movs r2, #32
8005fb0: 189b adds r3, r3, r2
8005fb2: 19db adds r3, r3, r7
8005fb4: 781b ldrb r3, [r3, #0]
8005fb6: 2b08 cmp r3, #8
8005fb8: d015 beq.n 8005fe6 <UART_SetConfig+0x33a>
8005fba: dc2b bgt.n 8006014 <UART_SetConfig+0x368>
8005fbc: 2b04 cmp r3, #4
8005fbe: d00d beq.n 8005fdc <UART_SetConfig+0x330>
8005fc0: dc28 bgt.n 8006014 <UART_SetConfig+0x368>
8005fc2: 2b00 cmp r3, #0
8005fc4: d002 beq.n 8005fcc <UART_SetConfig+0x320>
8005fc6: 2b02 cmp r3, #2
8005fc8: d005 beq.n 8005fd6 <UART_SetConfig+0x32a>
8005fca: e023 b.n 8006014 <UART_SetConfig+0x368>
{
case UART_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
8005fcc: f7fe f92a bl 8004224 <HAL_RCC_GetPCLK1Freq>
8005fd0: 0003 movs r3, r0
8005fd2: 637b str r3, [r7, #52] ; 0x34
break;
8005fd4: e027 b.n 8006026 <UART_SetConfig+0x37a>
case UART_CLOCKSOURCE_HSI:
pclk = (uint32_t) HSI_VALUE;
8005fd6: 4b0d ldr r3, [pc, #52] ; (800600c <UART_SetConfig+0x360>)
8005fd8: 637b str r3, [r7, #52] ; 0x34
break;
8005fda: e024 b.n 8006026 <UART_SetConfig+0x37a>
case UART_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
8005fdc: f7fe f896 bl 800410c <HAL_RCC_GetSysClockFreq>
8005fe0: 0003 movs r3, r0
8005fe2: 637b str r3, [r7, #52] ; 0x34
break;
8005fe4: e01f b.n 8006026 <UART_SetConfig+0x37a>
case UART_CLOCKSOURCE_LSE:
pclk = (uint32_t) LSE_VALUE;
8005fe6: 2380 movs r3, #128 ; 0x80
8005fe8: 021b lsls r3, r3, #8
8005fea: 637b str r3, [r7, #52] ; 0x34
break;
8005fec: e01b b.n 8006026 <UART_SetConfig+0x37a>
8005fee: 46c0 nop ; (mov r8, r8)
8005ff0: cfff69f3 .word 0xcfff69f3
8005ff4: ffffcfff .word 0xffffcfff
8005ff8: 40008000 .word 0x40008000
8005ffc: 11fff4ff .word 0x11fff4ff
8006000: 40013800 .word 0x40013800
8006004: 40021000 .word 0x40021000
8006008: 40004400 .word 0x40004400
800600c: 00f42400 .word 0x00f42400
8006010: 08007484 .word 0x08007484
default:
pclk = 0U;
8006014: 2300 movs r3, #0
8006016: 637b str r3, [r7, #52] ; 0x34
ret = HAL_ERROR;
8006018: 231a movs r3, #26
800601a: 2220 movs r2, #32
800601c: 189b adds r3, r3, r2
800601e: 19db adds r3, r3, r7
8006020: 2201 movs r2, #1
8006022: 701a strb r2, [r3, #0]
break;
8006024: 46c0 nop ; (mov r8, r8)
}
/* USARTDIV must be greater than or equal to 0d16 */
if (pclk != 0U)
8006026: 6b7b ldr r3, [r7, #52] ; 0x34
8006028: 2b00 cmp r3, #0
800602a: d100 bne.n 800602e <UART_SetConfig+0x382>
800602c: e09a b.n 8006164 <UART_SetConfig+0x4b8>
{
usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
800602e: 6a7b ldr r3, [r7, #36] ; 0x24
8006030: 6a5a ldr r2, [r3, #36] ; 0x24
8006032: 4b58 ldr r3, [pc, #352] ; (8006194 <UART_SetConfig+0x4e8>)
8006034: 0052 lsls r2, r2, #1
8006036: 5ad3 ldrh r3, [r2, r3]
8006038: 0019 movs r1, r3
800603a: 6b78 ldr r0, [r7, #52] ; 0x34
800603c: f7fa f862 bl 8000104 <__udivsi3>
8006040: 0003 movs r3, r0
8006042: 005a lsls r2, r3, #1
8006044: 6a7b ldr r3, [r7, #36] ; 0x24
8006046: 685b ldr r3, [r3, #4]
8006048: 085b lsrs r3, r3, #1
800604a: 18d2 adds r2, r2, r3
800604c: 6a7b ldr r3, [r7, #36] ; 0x24
800604e: 685b ldr r3, [r3, #4]
8006050: 0019 movs r1, r3
8006052: 0010 movs r0, r2
8006054: f7fa f856 bl 8000104 <__udivsi3>
8006058: 0003 movs r3, r0
800605a: 633b str r3, [r7, #48] ; 0x30
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
800605c: 6b3b ldr r3, [r7, #48] ; 0x30
800605e: 2b0f cmp r3, #15
8006060: d921 bls.n 80060a6 <UART_SetConfig+0x3fa>
8006062: 6b3a ldr r2, [r7, #48] ; 0x30
8006064: 2380 movs r3, #128 ; 0x80
8006066: 025b lsls r3, r3, #9
8006068: 429a cmp r2, r3
800606a: d21c bcs.n 80060a6 <UART_SetConfig+0x3fa>
{
brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
800606c: 6b3b ldr r3, [r7, #48] ; 0x30
800606e: b29a uxth r2, r3
8006070: 200e movs r0, #14
8006072: 2420 movs r4, #32
8006074: 1903 adds r3, r0, r4
8006076: 19db adds r3, r3, r7
8006078: 210f movs r1, #15
800607a: 438a bics r2, r1
800607c: 801a strh r2, [r3, #0]
brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
800607e: 6b3b ldr r3, [r7, #48] ; 0x30
8006080: 085b lsrs r3, r3, #1
8006082: b29b uxth r3, r3
8006084: 2207 movs r2, #7
8006086: 4013 ands r3, r2
8006088: b299 uxth r1, r3
800608a: 1903 adds r3, r0, r4
800608c: 19db adds r3, r3, r7
800608e: 1902 adds r2, r0, r4
8006090: 19d2 adds r2, r2, r7
8006092: 8812 ldrh r2, [r2, #0]
8006094: 430a orrs r2, r1
8006096: 801a strh r2, [r3, #0]
huart->Instance->BRR = brrtemp;
8006098: 6a7b ldr r3, [r7, #36] ; 0x24
800609a: 681b ldr r3, [r3, #0]
800609c: 1902 adds r2, r0, r4
800609e: 19d2 adds r2, r2, r7
80060a0: 8812 ldrh r2, [r2, #0]
80060a2: 60da str r2, [r3, #12]
80060a4: e05e b.n 8006164 <UART_SetConfig+0x4b8>
}
else
{
ret = HAL_ERROR;
80060a6: 231a movs r3, #26
80060a8: 2220 movs r2, #32
80060aa: 189b adds r3, r3, r2
80060ac: 19db adds r3, r3, r7
80060ae: 2201 movs r2, #1
80060b0: 701a strb r2, [r3, #0]
80060b2: e057 b.n 8006164 <UART_SetConfig+0x4b8>
}
}
}
else
{
switch (clocksource)
80060b4: 231b movs r3, #27
80060b6: 2220 movs r2, #32
80060b8: 189b adds r3, r3, r2
80060ba: 19db adds r3, r3, r7
80060bc: 781b ldrb r3, [r3, #0]
80060be: 2b08 cmp r3, #8
80060c0: d015 beq.n 80060ee <UART_SetConfig+0x442>
80060c2: dc18 bgt.n 80060f6 <UART_SetConfig+0x44a>
80060c4: 2b04 cmp r3, #4
80060c6: d00d beq.n 80060e4 <UART_SetConfig+0x438>
80060c8: dc15 bgt.n 80060f6 <UART_SetConfig+0x44a>
80060ca: 2b00 cmp r3, #0
80060cc: d002 beq.n 80060d4 <UART_SetConfig+0x428>
80060ce: 2b02 cmp r3, #2
80060d0: d005 beq.n 80060de <UART_SetConfig+0x432>
80060d2: e010 b.n 80060f6 <UART_SetConfig+0x44a>
{
case UART_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
80060d4: f7fe f8a6 bl 8004224 <HAL_RCC_GetPCLK1Freq>
80060d8: 0003 movs r3, r0
80060da: 637b str r3, [r7, #52] ; 0x34
break;
80060dc: e014 b.n 8006108 <UART_SetConfig+0x45c>
case UART_CLOCKSOURCE_HSI:
pclk = (uint32_t) HSI_VALUE;
80060de: 4b2e ldr r3, [pc, #184] ; (8006198 <UART_SetConfig+0x4ec>)
80060e0: 637b str r3, [r7, #52] ; 0x34
break;
80060e2: e011 b.n 8006108 <UART_SetConfig+0x45c>
case UART_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
80060e4: f7fe f812 bl 800410c <HAL_RCC_GetSysClockFreq>
80060e8: 0003 movs r3, r0
80060ea: 637b str r3, [r7, #52] ; 0x34
break;
80060ec: e00c b.n 8006108 <UART_SetConfig+0x45c>
case UART_CLOCKSOURCE_LSE:
pclk = (uint32_t) LSE_VALUE;
80060ee: 2380 movs r3, #128 ; 0x80
80060f0: 021b lsls r3, r3, #8
80060f2: 637b str r3, [r7, #52] ; 0x34
break;
80060f4: e008 b.n 8006108 <UART_SetConfig+0x45c>
default:
pclk = 0U;
80060f6: 2300 movs r3, #0
80060f8: 637b str r3, [r7, #52] ; 0x34
ret = HAL_ERROR;
80060fa: 231a movs r3, #26
80060fc: 2220 movs r2, #32
80060fe: 189b adds r3, r3, r2
8006100: 19db adds r3, r3, r7
8006102: 2201 movs r2, #1
8006104: 701a strb r2, [r3, #0]
break;
8006106: 46c0 nop ; (mov r8, r8)
}
if (pclk != 0U)
8006108: 6b7b ldr r3, [r7, #52] ; 0x34
800610a: 2b00 cmp r3, #0
800610c: d02a beq.n 8006164 <UART_SetConfig+0x4b8>
{
/* USARTDIV must be greater than or equal to 0d16 */
usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
800610e: 6a7b ldr r3, [r7, #36] ; 0x24
8006110: 6a5a ldr r2, [r3, #36] ; 0x24
8006112: 4b20 ldr r3, [pc, #128] ; (8006194 <UART_SetConfig+0x4e8>)
8006114: 0052 lsls r2, r2, #1
8006116: 5ad3 ldrh r3, [r2, r3]
8006118: 0019 movs r1, r3
800611a: 6b78 ldr r0, [r7, #52] ; 0x34
800611c: f7f9 fff2 bl 8000104 <__udivsi3>
8006120: 0003 movs r3, r0
8006122: 001a movs r2, r3
8006124: 6a7b ldr r3, [r7, #36] ; 0x24
8006126: 685b ldr r3, [r3, #4]
8006128: 085b lsrs r3, r3, #1
800612a: 18d2 adds r2, r2, r3
800612c: 6a7b ldr r3, [r7, #36] ; 0x24
800612e: 685b ldr r3, [r3, #4]
8006130: 0019 movs r1, r3
8006132: 0010 movs r0, r2
8006134: f7f9 ffe6 bl 8000104 <__udivsi3>
8006138: 0003 movs r3, r0
800613a: 633b str r3, [r7, #48] ; 0x30
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
800613c: 6b3b ldr r3, [r7, #48] ; 0x30
800613e: 2b0f cmp r3, #15
8006140: d90a bls.n 8006158 <UART_SetConfig+0x4ac>
8006142: 6b3a ldr r2, [r7, #48] ; 0x30
8006144: 2380 movs r3, #128 ; 0x80
8006146: 025b lsls r3, r3, #9
8006148: 429a cmp r2, r3
800614a: d205 bcs.n 8006158 <UART_SetConfig+0x4ac>
{
huart->Instance->BRR = (uint16_t)usartdiv;
800614c: 6b3b ldr r3, [r7, #48] ; 0x30
800614e: b29a uxth r2, r3
8006150: 6a7b ldr r3, [r7, #36] ; 0x24
8006152: 681b ldr r3, [r3, #0]
8006154: 60da str r2, [r3, #12]
8006156: e005 b.n 8006164 <UART_SetConfig+0x4b8>
}
else
{
ret = HAL_ERROR;
8006158: 231a movs r3, #26
800615a: 2220 movs r2, #32
800615c: 189b adds r3, r3, r2
800615e: 19db adds r3, r3, r7
8006160: 2201 movs r2, #1
8006162: 701a strb r2, [r3, #0]
}
}
}
/* Initialize the number of data to process during RX/TX ISR execution */
huart->NbTxDataToProcess = 1;
8006164: 6a7b ldr r3, [r7, #36] ; 0x24
8006166: 226a movs r2, #106 ; 0x6a
8006168: 2101 movs r1, #1
800616a: 5299 strh r1, [r3, r2]
huart->NbRxDataToProcess = 1;
800616c: 6a7b ldr r3, [r7, #36] ; 0x24
800616e: 2268 movs r2, #104 ; 0x68
8006170: 2101 movs r1, #1
8006172: 5299 strh r1, [r3, r2]
/* Clear ISR function pointers */
huart->RxISR = NULL;
8006174: 6a7b ldr r3, [r7, #36] ; 0x24
8006176: 2200 movs r2, #0
8006178: 671a str r2, [r3, #112] ; 0x70
huart->TxISR = NULL;
800617a: 6a7b ldr r3, [r7, #36] ; 0x24
800617c: 2200 movs r2, #0
800617e: 675a str r2, [r3, #116] ; 0x74
return ret;
8006180: 231a movs r3, #26
8006182: 2220 movs r2, #32
8006184: 189b adds r3, r3, r2
8006186: 19db adds r3, r3, r7
8006188: 781b ldrb r3, [r3, #0]
}
800618a: 0018 movs r0, r3
800618c: 46bd mov sp, r7
800618e: b010 add sp, #64 ; 0x40
8006190: bdb0 pop {r4, r5, r7, pc}
8006192: 46c0 nop ; (mov r8, r8)
8006194: 08007484 .word 0x08007484
8006198: 00f42400 .word 0x00f42400
0800619c <UART_AdvFeatureConfig>:
* @brief Configure the UART peripheral advanced features.
* @param huart UART handle.
* @retval None
*/
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
{
800619c: b580 push {r7, lr}
800619e: b082 sub sp, #8
80061a0: af00 add r7, sp, #0
80061a2: 6078 str r0, [r7, #4]
/* Check whether the set of advanced features to configure is properly set */
assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
/* if required, configure TX pin active level inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
80061a4: 687b ldr r3, [r7, #4]
80061a6: 6a9b ldr r3, [r3, #40] ; 0x28
80061a8: 2201 movs r2, #1
80061aa: 4013 ands r3, r2
80061ac: d00b beq.n 80061c6 <UART_AdvFeatureConfig+0x2a>
{
assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
80061ae: 687b ldr r3, [r7, #4]
80061b0: 681b ldr r3, [r3, #0]
80061b2: 685b ldr r3, [r3, #4]
80061b4: 4a4a ldr r2, [pc, #296] ; (80062e0 <UART_AdvFeatureConfig+0x144>)
80061b6: 4013 ands r3, r2
80061b8: 0019 movs r1, r3
80061ba: 687b ldr r3, [r7, #4]
80061bc: 6ada ldr r2, [r3, #44] ; 0x2c
80061be: 687b ldr r3, [r7, #4]
80061c0: 681b ldr r3, [r3, #0]
80061c2: 430a orrs r2, r1
80061c4: 605a str r2, [r3, #4]
}
/* if required, configure RX pin active level inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
80061c6: 687b ldr r3, [r7, #4]
80061c8: 6a9b ldr r3, [r3, #40] ; 0x28
80061ca: 2202 movs r2, #2
80061cc: 4013 ands r3, r2
80061ce: d00b beq.n 80061e8 <UART_AdvFeatureConfig+0x4c>
{
assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
80061d0: 687b ldr r3, [r7, #4]
80061d2: 681b ldr r3, [r3, #0]
80061d4: 685b ldr r3, [r3, #4]
80061d6: 4a43 ldr r2, [pc, #268] ; (80062e4 <UART_AdvFeatureConfig+0x148>)
80061d8: 4013 ands r3, r2
80061da: 0019 movs r1, r3
80061dc: 687b ldr r3, [r7, #4]
80061de: 6b1a ldr r2, [r3, #48] ; 0x30
80061e0: 687b ldr r3, [r7, #4]
80061e2: 681b ldr r3, [r3, #0]
80061e4: 430a orrs r2, r1
80061e6: 605a str r2, [r3, #4]
}
/* if required, configure data inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
80061e8: 687b ldr r3, [r7, #4]
80061ea: 6a9b ldr r3, [r3, #40] ; 0x28
80061ec: 2204 movs r2, #4
80061ee: 4013 ands r3, r2
80061f0: d00b beq.n 800620a <UART_AdvFeatureConfig+0x6e>
{
assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
80061f2: 687b ldr r3, [r7, #4]
80061f4: 681b ldr r3, [r3, #0]
80061f6: 685b ldr r3, [r3, #4]
80061f8: 4a3b ldr r2, [pc, #236] ; (80062e8 <UART_AdvFeatureConfig+0x14c>)
80061fa: 4013 ands r3, r2
80061fc: 0019 movs r1, r3
80061fe: 687b ldr r3, [r7, #4]
8006200: 6b5a ldr r2, [r3, #52] ; 0x34
8006202: 687b ldr r3, [r7, #4]
8006204: 681b ldr r3, [r3, #0]
8006206: 430a orrs r2, r1
8006208: 605a str r2, [r3, #4]
}
/* if required, configure RX/TX pins swap */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
800620a: 687b ldr r3, [r7, #4]
800620c: 6a9b ldr r3, [r3, #40] ; 0x28
800620e: 2208 movs r2, #8
8006210: 4013 ands r3, r2
8006212: d00b beq.n 800622c <UART_AdvFeatureConfig+0x90>
{
assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
8006214: 687b ldr r3, [r7, #4]
8006216: 681b ldr r3, [r3, #0]
8006218: 685b ldr r3, [r3, #4]
800621a: 4a34 ldr r2, [pc, #208] ; (80062ec <UART_AdvFeatureConfig+0x150>)
800621c: 4013 ands r3, r2
800621e: 0019 movs r1, r3
8006220: 687b ldr r3, [r7, #4]
8006222: 6b9a ldr r2, [r3, #56] ; 0x38
8006224: 687b ldr r3, [r7, #4]
8006226: 681b ldr r3, [r3, #0]
8006228: 430a orrs r2, r1
800622a: 605a str r2, [r3, #4]
}
/* if required, configure RX overrun detection disabling */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
800622c: 687b ldr r3, [r7, #4]
800622e: 6a9b ldr r3, [r3, #40] ; 0x28
8006230: 2210 movs r2, #16
8006232: 4013 ands r3, r2
8006234: d00b beq.n 800624e <UART_AdvFeatureConfig+0xb2>
{
assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
8006236: 687b ldr r3, [r7, #4]
8006238: 681b ldr r3, [r3, #0]
800623a: 689b ldr r3, [r3, #8]
800623c: 4a2c ldr r2, [pc, #176] ; (80062f0 <UART_AdvFeatureConfig+0x154>)
800623e: 4013 ands r3, r2
8006240: 0019 movs r1, r3
8006242: 687b ldr r3, [r7, #4]
8006244: 6bda ldr r2, [r3, #60] ; 0x3c
8006246: 687b ldr r3, [r7, #4]
8006248: 681b ldr r3, [r3, #0]
800624a: 430a orrs r2, r1
800624c: 609a str r2, [r3, #8]
}
/* if required, configure DMA disabling on reception error */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
800624e: 687b ldr r3, [r7, #4]
8006250: 6a9b ldr r3, [r3, #40] ; 0x28
8006252: 2220 movs r2, #32
8006254: 4013 ands r3, r2
8006256: d00b beq.n 8006270 <UART_AdvFeatureConfig+0xd4>
{
assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
8006258: 687b ldr r3, [r7, #4]
800625a: 681b ldr r3, [r3, #0]
800625c: 689b ldr r3, [r3, #8]
800625e: 4a25 ldr r2, [pc, #148] ; (80062f4 <UART_AdvFeatureConfig+0x158>)
8006260: 4013 ands r3, r2
8006262: 0019 movs r1, r3
8006264: 687b ldr r3, [r7, #4]
8006266: 6c1a ldr r2, [r3, #64] ; 0x40
8006268: 687b ldr r3, [r7, #4]
800626a: 681b ldr r3, [r3, #0]
800626c: 430a orrs r2, r1
800626e: 609a str r2, [r3, #8]
}
/* if required, configure auto Baud rate detection scheme */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
8006270: 687b ldr r3, [r7, #4]
8006272: 6a9b ldr r3, [r3, #40] ; 0x28
8006274: 2240 movs r2, #64 ; 0x40
8006276: 4013 ands r3, r2
8006278: d01d beq.n 80062b6 <UART_AdvFeatureConfig+0x11a>
{
assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
800627a: 687b ldr r3, [r7, #4]
800627c: 681b ldr r3, [r3, #0]
800627e: 685b ldr r3, [r3, #4]
8006280: 4a1d ldr r2, [pc, #116] ; (80062f8 <UART_AdvFeatureConfig+0x15c>)
8006282: 4013 ands r3, r2
8006284: 0019 movs r1, r3
8006286: 687b ldr r3, [r7, #4]
8006288: 6c5a ldr r2, [r3, #68] ; 0x44
800628a: 687b ldr r3, [r7, #4]
800628c: 681b ldr r3, [r3, #0]
800628e: 430a orrs r2, r1
8006290: 605a str r2, [r3, #4]
/* set auto Baudrate detection parameters if detection is enabled */
if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
8006292: 687b ldr r3, [r7, #4]
8006294: 6c5a ldr r2, [r3, #68] ; 0x44
8006296: 2380 movs r3, #128 ; 0x80
8006298: 035b lsls r3, r3, #13
800629a: 429a cmp r2, r3
800629c: d10b bne.n 80062b6 <UART_AdvFeatureConfig+0x11a>
{
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
800629e: 687b ldr r3, [r7, #4]
80062a0: 681b ldr r3, [r3, #0]
80062a2: 685b ldr r3, [r3, #4]
80062a4: 4a15 ldr r2, [pc, #84] ; (80062fc <UART_AdvFeatureConfig+0x160>)
80062a6: 4013 ands r3, r2
80062a8: 0019 movs r1, r3
80062aa: 687b ldr r3, [r7, #4]
80062ac: 6c9a ldr r2, [r3, #72] ; 0x48
80062ae: 687b ldr r3, [r7, #4]
80062b0: 681b ldr r3, [r3, #0]
80062b2: 430a orrs r2, r1
80062b4: 605a str r2, [r3, #4]
}
}
/* if required, configure MSB first on communication line */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
80062b6: 687b ldr r3, [r7, #4]
80062b8: 6a9b ldr r3, [r3, #40] ; 0x28
80062ba: 2280 movs r2, #128 ; 0x80
80062bc: 4013 ands r3, r2
80062be: d00b beq.n 80062d8 <UART_AdvFeatureConfig+0x13c>
{
assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
80062c0: 687b ldr r3, [r7, #4]
80062c2: 681b ldr r3, [r3, #0]
80062c4: 685b ldr r3, [r3, #4]
80062c6: 4a0e ldr r2, [pc, #56] ; (8006300 <UART_AdvFeatureConfig+0x164>)
80062c8: 4013 ands r3, r2
80062ca: 0019 movs r1, r3
80062cc: 687b ldr r3, [r7, #4]
80062ce: 6cda ldr r2, [r3, #76] ; 0x4c
80062d0: 687b ldr r3, [r7, #4]
80062d2: 681b ldr r3, [r3, #0]
80062d4: 430a orrs r2, r1
80062d6: 605a str r2, [r3, #4]
}
}
80062d8: 46c0 nop ; (mov r8, r8)
80062da: 46bd mov sp, r7
80062dc: b002 add sp, #8
80062de: bd80 pop {r7, pc}
80062e0: fffdffff .word 0xfffdffff
80062e4: fffeffff .word 0xfffeffff
80062e8: fffbffff .word 0xfffbffff
80062ec: ffff7fff .word 0xffff7fff
80062f0: ffffefff .word 0xffffefff
80062f4: ffffdfff .word 0xffffdfff
80062f8: ffefffff .word 0xffefffff
80062fc: ff9fffff .word 0xff9fffff
8006300: fff7ffff .word 0xfff7ffff
08006304 <UART_CheckIdleState>:
* @brief Check the UART Idle State.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
{
8006304: b580 push {r7, lr}
8006306: b086 sub sp, #24
8006308: af02 add r7, sp, #8
800630a: 6078 str r0, [r7, #4]
uint32_t tickstart;
/* Initialize the UART ErrorCode */
huart->ErrorCode = HAL_UART_ERROR_NONE;
800630c: 687b ldr r3, [r7, #4]
800630e: 228c movs r2, #140 ; 0x8c
8006310: 2100 movs r1, #0
8006312: 5099 str r1, [r3, r2]
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
8006314: f7fb fc1a bl 8001b4c <HAL_GetTick>
8006318: 0003 movs r3, r0
800631a: 60fb str r3, [r7, #12]
/* Check if the Transmitter is enabled */
if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
800631c: 687b ldr r3, [r7, #4]
800631e: 681b ldr r3, [r3, #0]
8006320: 681b ldr r3, [r3, #0]
8006322: 2208 movs r2, #8
8006324: 4013 ands r3, r2
8006326: 2b08 cmp r3, #8
8006328: d10c bne.n 8006344 <UART_CheckIdleState+0x40>
{
/* Wait until TEACK flag is set */
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
800632a: 68fb ldr r3, [r7, #12]
800632c: 2280 movs r2, #128 ; 0x80
800632e: 0391 lsls r1, r2, #14
8006330: 6878 ldr r0, [r7, #4]
8006332: 4a18 ldr r2, [pc, #96] ; (8006394 <UART_CheckIdleState+0x90>)
8006334: 9200 str r2, [sp, #0]
8006336: 2200 movs r2, #0
8006338: f000 f82e bl 8006398 <UART_WaitOnFlagUntilTimeout>
800633c: 1e03 subs r3, r0, #0
800633e: d001 beq.n 8006344 <UART_CheckIdleState+0x40>
{
/* Timeout occurred */
return HAL_TIMEOUT;
8006340: 2303 movs r3, #3
8006342: e023 b.n 800638c <UART_CheckIdleState+0x88>
}
}
/* Check if the Receiver is enabled */
if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
8006344: 687b ldr r3, [r7, #4]
8006346: 681b ldr r3, [r3, #0]
8006348: 681b ldr r3, [r3, #0]
800634a: 2204 movs r2, #4
800634c: 4013 ands r3, r2
800634e: 2b04 cmp r3, #4
8006350: d10c bne.n 800636c <UART_CheckIdleState+0x68>
{
/* Wait until REACK flag is set */
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
8006352: 68fb ldr r3, [r7, #12]
8006354: 2280 movs r2, #128 ; 0x80
8006356: 03d1 lsls r1, r2, #15
8006358: 6878 ldr r0, [r7, #4]
800635a: 4a0e ldr r2, [pc, #56] ; (8006394 <UART_CheckIdleState+0x90>)
800635c: 9200 str r2, [sp, #0]
800635e: 2200 movs r2, #0
8006360: f000 f81a bl 8006398 <UART_WaitOnFlagUntilTimeout>
8006364: 1e03 subs r3, r0, #0
8006366: d001 beq.n 800636c <UART_CheckIdleState+0x68>
{
/* Timeout occurred */
return HAL_TIMEOUT;
8006368: 2303 movs r3, #3
800636a: e00f b.n 800638c <UART_CheckIdleState+0x88>
}
}
/* Initialize the UART State */
huart->gState = HAL_UART_STATE_READY;
800636c: 687b ldr r3, [r7, #4]
800636e: 2284 movs r2, #132 ; 0x84
8006370: 2120 movs r1, #32
8006372: 5099 str r1, [r3, r2]
huart->RxState = HAL_UART_STATE_READY;
8006374: 687b ldr r3, [r7, #4]
8006376: 2288 movs r2, #136 ; 0x88
8006378: 2120 movs r1, #32
800637a: 5099 str r1, [r3, r2]
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
800637c: 687b ldr r3, [r7, #4]
800637e: 2200 movs r2, #0
8006380: 66da str r2, [r3, #108] ; 0x6c
__HAL_UNLOCK(huart);
8006382: 687b ldr r3, [r7, #4]
8006384: 2280 movs r2, #128 ; 0x80
8006386: 2100 movs r1, #0
8006388: 5499 strb r1, [r3, r2]
return HAL_OK;
800638a: 2300 movs r3, #0
}
800638c: 0018 movs r0, r3
800638e: 46bd mov sp, r7
8006390: b004 add sp, #16
8006392: bd80 pop {r7, pc}
8006394: 01ffffff .word 0x01ffffff
08006398 <UART_WaitOnFlagUntilTimeout>:
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
uint32_t Tickstart, uint32_t Timeout)
{
8006398: b580 push {r7, lr}
800639a: b094 sub sp, #80 ; 0x50
800639c: af00 add r7, sp, #0
800639e: 60f8 str r0, [r7, #12]
80063a0: 60b9 str r1, [r7, #8]
80063a2: 603b str r3, [r7, #0]
80063a4: 1dfb adds r3, r7, #7
80063a6: 701a strb r2, [r3, #0]
/* Wait until flag is set */
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
80063a8: e0a7 b.n 80064fa <UART_WaitOnFlagUntilTimeout+0x162>
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
80063aa: 6dbb ldr r3, [r7, #88] ; 0x58
80063ac: 3301 adds r3, #1
80063ae: d100 bne.n 80063b2 <UART_WaitOnFlagUntilTimeout+0x1a>
80063b0: e0a3 b.n 80064fa <UART_WaitOnFlagUntilTimeout+0x162>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
80063b2: f7fb fbcb bl 8001b4c <HAL_GetTick>
80063b6: 0002 movs r2, r0
80063b8: 683b ldr r3, [r7, #0]
80063ba: 1ad3 subs r3, r2, r3
80063bc: 6dba ldr r2, [r7, #88] ; 0x58
80063be: 429a cmp r2, r3
80063c0: d302 bcc.n 80063c8 <UART_WaitOnFlagUntilTimeout+0x30>
80063c2: 6dbb ldr r3, [r7, #88] ; 0x58
80063c4: 2b00 cmp r3, #0
80063c6: d13f bne.n 8006448 <UART_WaitOnFlagUntilTimeout+0xb0>
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
80063c8: f3ef 8310 mrs r3, PRIMASK
80063cc: 62bb str r3, [r7, #40] ; 0x28
return(result);
80063ce: 6abb ldr r3, [r7, #40] ; 0x28
{
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
interrupts for the interrupt process */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE |
80063d0: 647b str r3, [r7, #68] ; 0x44
80063d2: 2301 movs r3, #1
80063d4: 62fb str r3, [r7, #44] ; 0x2c
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80063d6: 6afb ldr r3, [r7, #44] ; 0x2c
80063d8: f383 8810 msr PRIMASK, r3
}
80063dc: 46c0 nop ; (mov r8, r8)
80063de: 68fb ldr r3, [r7, #12]
80063e0: 681b ldr r3, [r3, #0]
80063e2: 681a ldr r2, [r3, #0]
80063e4: 68fb ldr r3, [r7, #12]
80063e6: 681b ldr r3, [r3, #0]
80063e8: 494e ldr r1, [pc, #312] ; (8006524 <UART_WaitOnFlagUntilTimeout+0x18c>)
80063ea: 400a ands r2, r1
80063ec: 601a str r2, [r3, #0]
80063ee: 6c7b ldr r3, [r7, #68] ; 0x44
80063f0: 633b str r3, [r7, #48] ; 0x30
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80063f2: 6b3b ldr r3, [r7, #48] ; 0x30
80063f4: f383 8810 msr PRIMASK, r3
}
80063f8: 46c0 nop ; (mov r8, r8)
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
80063fa: f3ef 8310 mrs r3, PRIMASK
80063fe: 637b str r3, [r7, #52] ; 0x34
return(result);
8006400: 6b7b ldr r3, [r7, #52] ; 0x34
USART_CR1_TXEIE_TXFNFIE));
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
8006402: 643b str r3, [r7, #64] ; 0x40
8006404: 2301 movs r3, #1
8006406: 63bb str r3, [r7, #56] ; 0x38
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006408: 6bbb ldr r3, [r7, #56] ; 0x38
800640a: f383 8810 msr PRIMASK, r3
}
800640e: 46c0 nop ; (mov r8, r8)
8006410: 68fb ldr r3, [r7, #12]
8006412: 681b ldr r3, [r3, #0]
8006414: 689a ldr r2, [r3, #8]
8006416: 68fb ldr r3, [r7, #12]
8006418: 681b ldr r3, [r3, #0]
800641a: 2101 movs r1, #1
800641c: 438a bics r2, r1
800641e: 609a str r2, [r3, #8]
8006420: 6c3b ldr r3, [r7, #64] ; 0x40
8006422: 63fb str r3, [r7, #60] ; 0x3c
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006424: 6bfb ldr r3, [r7, #60] ; 0x3c
8006426: f383 8810 msr PRIMASK, r3
}
800642a: 46c0 nop ; (mov r8, r8)
huart->gState = HAL_UART_STATE_READY;
800642c: 68fb ldr r3, [r7, #12]
800642e: 2284 movs r2, #132 ; 0x84
8006430: 2120 movs r1, #32
8006432: 5099 str r1, [r3, r2]
huart->RxState = HAL_UART_STATE_READY;
8006434: 68fb ldr r3, [r7, #12]
8006436: 2288 movs r2, #136 ; 0x88
8006438: 2120 movs r1, #32
800643a: 5099 str r1, [r3, r2]
__HAL_UNLOCK(huart);
800643c: 68fb ldr r3, [r7, #12]
800643e: 2280 movs r2, #128 ; 0x80
8006440: 2100 movs r1, #0
8006442: 5499 strb r1, [r3, r2]
return HAL_TIMEOUT;
8006444: 2303 movs r3, #3
8006446: e069 b.n 800651c <UART_WaitOnFlagUntilTimeout+0x184>
}
if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U)
8006448: 68fb ldr r3, [r7, #12]
800644a: 681b ldr r3, [r3, #0]
800644c: 681b ldr r3, [r3, #0]
800644e: 2204 movs r2, #4
8006450: 4013 ands r3, r2
8006452: d052 beq.n 80064fa <UART_WaitOnFlagUntilTimeout+0x162>
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
8006454: 68fb ldr r3, [r7, #12]
8006456: 681b ldr r3, [r3, #0]
8006458: 69da ldr r2, [r3, #28]
800645a: 2380 movs r3, #128 ; 0x80
800645c: 011b lsls r3, r3, #4
800645e: 401a ands r2, r3
8006460: 2380 movs r3, #128 ; 0x80
8006462: 011b lsls r3, r3, #4
8006464: 429a cmp r2, r3
8006466: d148 bne.n 80064fa <UART_WaitOnFlagUntilTimeout+0x162>
{
/* Clear Receiver Timeout flag*/
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
8006468: 68fb ldr r3, [r7, #12]
800646a: 681b ldr r3, [r3, #0]
800646c: 2280 movs r2, #128 ; 0x80
800646e: 0112 lsls r2, r2, #4
8006470: 621a str r2, [r3, #32]
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8006472: f3ef 8310 mrs r3, PRIMASK
8006476: 613b str r3, [r7, #16]
return(result);
8006478: 693b ldr r3, [r7, #16]
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
interrupts for the interrupt process */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE |
800647a: 64fb str r3, [r7, #76] ; 0x4c
800647c: 2301 movs r3, #1
800647e: 617b str r3, [r7, #20]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006480: 697b ldr r3, [r7, #20]
8006482: f383 8810 msr PRIMASK, r3
}
8006486: 46c0 nop ; (mov r8, r8)
8006488: 68fb ldr r3, [r7, #12]
800648a: 681b ldr r3, [r3, #0]
800648c: 681a ldr r2, [r3, #0]
800648e: 68fb ldr r3, [r7, #12]
8006490: 681b ldr r3, [r3, #0]
8006492: 4924 ldr r1, [pc, #144] ; (8006524 <UART_WaitOnFlagUntilTimeout+0x18c>)
8006494: 400a ands r2, r1
8006496: 601a str r2, [r3, #0]
8006498: 6cfb ldr r3, [r7, #76] ; 0x4c
800649a: 61bb str r3, [r7, #24]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
800649c: 69bb ldr r3, [r7, #24]
800649e: f383 8810 msr PRIMASK, r3
}
80064a2: 46c0 nop ; (mov r8, r8)
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
80064a4: f3ef 8310 mrs r3, PRIMASK
80064a8: 61fb str r3, [r7, #28]
return(result);
80064aa: 69fb ldr r3, [r7, #28]
USART_CR1_TXEIE_TXFNFIE));
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
80064ac: 64bb str r3, [r7, #72] ; 0x48
80064ae: 2301 movs r3, #1
80064b0: 623b str r3, [r7, #32]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80064b2: 6a3b ldr r3, [r7, #32]
80064b4: f383 8810 msr PRIMASK, r3
}
80064b8: 46c0 nop ; (mov r8, r8)
80064ba: 68fb ldr r3, [r7, #12]
80064bc: 681b ldr r3, [r3, #0]
80064be: 689a ldr r2, [r3, #8]
80064c0: 68fb ldr r3, [r7, #12]
80064c2: 681b ldr r3, [r3, #0]
80064c4: 2101 movs r1, #1
80064c6: 438a bics r2, r1
80064c8: 609a str r2, [r3, #8]
80064ca: 6cbb ldr r3, [r7, #72] ; 0x48
80064cc: 627b str r3, [r7, #36] ; 0x24
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80064ce: 6a7b ldr r3, [r7, #36] ; 0x24
80064d0: f383 8810 msr PRIMASK, r3
}
80064d4: 46c0 nop ; (mov r8, r8)
huart->gState = HAL_UART_STATE_READY;
80064d6: 68fb ldr r3, [r7, #12]
80064d8: 2284 movs r2, #132 ; 0x84
80064da: 2120 movs r1, #32
80064dc: 5099 str r1, [r3, r2]
huart->RxState = HAL_UART_STATE_READY;
80064de: 68fb ldr r3, [r7, #12]
80064e0: 2288 movs r2, #136 ; 0x88
80064e2: 2120 movs r1, #32
80064e4: 5099 str r1, [r3, r2]
huart->ErrorCode = HAL_UART_ERROR_RTO;
80064e6: 68fb ldr r3, [r7, #12]
80064e8: 228c movs r2, #140 ; 0x8c
80064ea: 2120 movs r1, #32
80064ec: 5099 str r1, [r3, r2]
/* Process Unlocked */
__HAL_UNLOCK(huart);
80064ee: 68fb ldr r3, [r7, #12]
80064f0: 2280 movs r2, #128 ; 0x80
80064f2: 2100 movs r1, #0
80064f4: 5499 strb r1, [r3, r2]
return HAL_TIMEOUT;
80064f6: 2303 movs r3, #3
80064f8: e010 b.n 800651c <UART_WaitOnFlagUntilTimeout+0x184>
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
80064fa: 68fb ldr r3, [r7, #12]
80064fc: 681b ldr r3, [r3, #0]
80064fe: 69db ldr r3, [r3, #28]
8006500: 68ba ldr r2, [r7, #8]
8006502: 4013 ands r3, r2
8006504: 68ba ldr r2, [r7, #8]
8006506: 1ad3 subs r3, r2, r3
8006508: 425a negs r2, r3
800650a: 4153 adcs r3, r2
800650c: b2db uxtb r3, r3
800650e: 001a movs r2, r3
8006510: 1dfb adds r3, r7, #7
8006512: 781b ldrb r3, [r3, #0]
8006514: 429a cmp r2, r3
8006516: d100 bne.n 800651a <UART_WaitOnFlagUntilTimeout+0x182>
8006518: e747 b.n 80063aa <UART_WaitOnFlagUntilTimeout+0x12>
}
}
}
}
return HAL_OK;
800651a: 2300 movs r3, #0
}
800651c: 0018 movs r0, r3
800651e: 46bd mov sp, r7
8006520: b014 add sp, #80 ; 0x50
8006522: bd80 pop {r7, pc}
8006524: fffffe5f .word 0xfffffe5f
08006528 <UART_Start_Receive_IT>:
* @param pData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{
8006528: b580 push {r7, lr}
800652a: b098 sub sp, #96 ; 0x60
800652c: af00 add r7, sp, #0
800652e: 60f8 str r0, [r7, #12]
8006530: 60b9 str r1, [r7, #8]
8006532: 1dbb adds r3, r7, #6
8006534: 801a strh r2, [r3, #0]
huart->pRxBuffPtr = pData;
8006536: 68fb ldr r3, [r7, #12]
8006538: 68ba ldr r2, [r7, #8]
800653a: 659a str r2, [r3, #88] ; 0x58
huart->RxXferSize = Size;
800653c: 68fb ldr r3, [r7, #12]
800653e: 1dba adds r2, r7, #6
8006540: 215c movs r1, #92 ; 0x5c
8006542: 8812 ldrh r2, [r2, #0]
8006544: 525a strh r2, [r3, r1]
huart->RxXferCount = Size;
8006546: 68fb ldr r3, [r7, #12]
8006548: 1dba adds r2, r7, #6
800654a: 215e movs r1, #94 ; 0x5e
800654c: 8812 ldrh r2, [r2, #0]
800654e: 525a strh r2, [r3, r1]
huart->RxISR = NULL;
8006550: 68fb ldr r3, [r7, #12]
8006552: 2200 movs r2, #0
8006554: 671a str r2, [r3, #112] ; 0x70
/* Computation of UART mask to apply to RDR register */
UART_MASK_COMPUTATION(huart);
8006556: 68fb ldr r3, [r7, #12]
8006558: 689a ldr r2, [r3, #8]
800655a: 2380 movs r3, #128 ; 0x80
800655c: 015b lsls r3, r3, #5
800655e: 429a cmp r2, r3
8006560: d10d bne.n 800657e <UART_Start_Receive_IT+0x56>
8006562: 68fb ldr r3, [r7, #12]
8006564: 691b ldr r3, [r3, #16]
8006566: 2b00 cmp r3, #0
8006568: d104 bne.n 8006574 <UART_Start_Receive_IT+0x4c>
800656a: 68fb ldr r3, [r7, #12]
800656c: 2260 movs r2, #96 ; 0x60
800656e: 497f ldr r1, [pc, #508] ; (800676c <UART_Start_Receive_IT+0x244>)
8006570: 5299 strh r1, [r3, r2]
8006572: e02e b.n 80065d2 <UART_Start_Receive_IT+0xaa>
8006574: 68fb ldr r3, [r7, #12]
8006576: 2260 movs r2, #96 ; 0x60
8006578: 21ff movs r1, #255 ; 0xff
800657a: 5299 strh r1, [r3, r2]
800657c: e029 b.n 80065d2 <UART_Start_Receive_IT+0xaa>
800657e: 68fb ldr r3, [r7, #12]
8006580: 689b ldr r3, [r3, #8]
8006582: 2b00 cmp r3, #0
8006584: d10d bne.n 80065a2 <UART_Start_Receive_IT+0x7a>
8006586: 68fb ldr r3, [r7, #12]
8006588: 691b ldr r3, [r3, #16]
800658a: 2b00 cmp r3, #0
800658c: d104 bne.n 8006598 <UART_Start_Receive_IT+0x70>
800658e: 68fb ldr r3, [r7, #12]
8006590: 2260 movs r2, #96 ; 0x60
8006592: 21ff movs r1, #255 ; 0xff
8006594: 5299 strh r1, [r3, r2]
8006596: e01c b.n 80065d2 <UART_Start_Receive_IT+0xaa>
8006598: 68fb ldr r3, [r7, #12]
800659a: 2260 movs r2, #96 ; 0x60
800659c: 217f movs r1, #127 ; 0x7f
800659e: 5299 strh r1, [r3, r2]
80065a0: e017 b.n 80065d2 <UART_Start_Receive_IT+0xaa>
80065a2: 68fb ldr r3, [r7, #12]
80065a4: 689a ldr r2, [r3, #8]
80065a6: 2380 movs r3, #128 ; 0x80
80065a8: 055b lsls r3, r3, #21
80065aa: 429a cmp r2, r3
80065ac: d10d bne.n 80065ca <UART_Start_Receive_IT+0xa2>
80065ae: 68fb ldr r3, [r7, #12]
80065b0: 691b ldr r3, [r3, #16]
80065b2: 2b00 cmp r3, #0
80065b4: d104 bne.n 80065c0 <UART_Start_Receive_IT+0x98>
80065b6: 68fb ldr r3, [r7, #12]
80065b8: 2260 movs r2, #96 ; 0x60
80065ba: 217f movs r1, #127 ; 0x7f
80065bc: 5299 strh r1, [r3, r2]
80065be: e008 b.n 80065d2 <UART_Start_Receive_IT+0xaa>
80065c0: 68fb ldr r3, [r7, #12]
80065c2: 2260 movs r2, #96 ; 0x60
80065c4: 213f movs r1, #63 ; 0x3f
80065c6: 5299 strh r1, [r3, r2]
80065c8: e003 b.n 80065d2 <UART_Start_Receive_IT+0xaa>
80065ca: 68fb ldr r3, [r7, #12]
80065cc: 2260 movs r2, #96 ; 0x60
80065ce: 2100 movs r1, #0
80065d0: 5299 strh r1, [r3, r2]
huart->ErrorCode = HAL_UART_ERROR_NONE;
80065d2: 68fb ldr r3, [r7, #12]
80065d4: 228c movs r2, #140 ; 0x8c
80065d6: 2100 movs r1, #0
80065d8: 5099 str r1, [r3, r2]
huart->RxState = HAL_UART_STATE_BUSY_RX;
80065da: 68fb ldr r3, [r7, #12]
80065dc: 2288 movs r2, #136 ; 0x88
80065de: 2122 movs r1, #34 ; 0x22
80065e0: 5099 str r1, [r3, r2]
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
80065e2: f3ef 8310 mrs r3, PRIMASK
80065e6: 643b str r3, [r7, #64] ; 0x40
return(result);
80065e8: 6c3b ldr r3, [r7, #64] ; 0x40
/* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
80065ea: 65fb str r3, [r7, #92] ; 0x5c
80065ec: 2301 movs r3, #1
80065ee: 647b str r3, [r7, #68] ; 0x44
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80065f0: 6c7b ldr r3, [r7, #68] ; 0x44
80065f2: f383 8810 msr PRIMASK, r3
}
80065f6: 46c0 nop ; (mov r8, r8)
80065f8: 68fb ldr r3, [r7, #12]
80065fa: 681b ldr r3, [r3, #0]
80065fc: 689a ldr r2, [r3, #8]
80065fe: 68fb ldr r3, [r7, #12]
8006600: 681b ldr r3, [r3, #0]
8006602: 2101 movs r1, #1
8006604: 430a orrs r2, r1
8006606: 609a str r2, [r3, #8]
8006608: 6dfb ldr r3, [r7, #92] ; 0x5c
800660a: 64bb str r3, [r7, #72] ; 0x48
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
800660c: 6cbb ldr r3, [r7, #72] ; 0x48
800660e: f383 8810 msr PRIMASK, r3
}
8006612: 46c0 nop ; (mov r8, r8)
/* Configure Rx interrupt processing */
if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess))
8006614: 68fb ldr r3, [r7, #12]
8006616: 6e5a ldr r2, [r3, #100] ; 0x64
8006618: 2380 movs r3, #128 ; 0x80
800661a: 059b lsls r3, r3, #22
800661c: 429a cmp r2, r3
800661e: d154 bne.n 80066ca <UART_Start_Receive_IT+0x1a2>
8006620: 68fb ldr r3, [r7, #12]
8006622: 2268 movs r2, #104 ; 0x68
8006624: 5a9b ldrh r3, [r3, r2]
8006626: 1dba adds r2, r7, #6
8006628: 8812 ldrh r2, [r2, #0]
800662a: 429a cmp r2, r3
800662c: d34d bcc.n 80066ca <UART_Start_Receive_IT+0x1a2>
{
/* Set the Rx ISR function pointer according to the data word length */
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
800662e: 68fb ldr r3, [r7, #12]
8006630: 689a ldr r2, [r3, #8]
8006632: 2380 movs r3, #128 ; 0x80
8006634: 015b lsls r3, r3, #5
8006636: 429a cmp r2, r3
8006638: d107 bne.n 800664a <UART_Start_Receive_IT+0x122>
800663a: 68fb ldr r3, [r7, #12]
800663c: 691b ldr r3, [r3, #16]
800663e: 2b00 cmp r3, #0
8006640: d103 bne.n 800664a <UART_Start_Receive_IT+0x122>
{
huart->RxISR = UART_RxISR_16BIT_FIFOEN;
8006642: 68fb ldr r3, [r7, #12]
8006644: 4a4a ldr r2, [pc, #296] ; (8006770 <UART_Start_Receive_IT+0x248>)
8006646: 671a str r2, [r3, #112] ; 0x70
8006648: e002 b.n 8006650 <UART_Start_Receive_IT+0x128>
}
else
{
huart->RxISR = UART_RxISR_8BIT_FIFOEN;
800664a: 68fb ldr r3, [r7, #12]
800664c: 4a49 ldr r2, [pc, #292] ; (8006774 <UART_Start_Receive_IT+0x24c>)
800664e: 671a str r2, [r3, #112] ; 0x70
}
__HAL_UNLOCK(huart);
8006650: 68fb ldr r3, [r7, #12]
8006652: 2280 movs r2, #128 ; 0x80
8006654: 2100 movs r1, #0
8006656: 5499 strb r1, [r3, r2]
/* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */
if (huart->Init.Parity != UART_PARITY_NONE)
8006658: 68fb ldr r3, [r7, #12]
800665a: 691b ldr r3, [r3, #16]
800665c: 2b00 cmp r3, #0
800665e: d019 beq.n 8006694 <UART_Start_Receive_IT+0x16c>
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8006660: f3ef 8310 mrs r3, PRIMASK
8006664: 637b str r3, [r7, #52] ; 0x34
return(result);
8006666: 6b7b ldr r3, [r7, #52] ; 0x34
{
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
8006668: 65bb str r3, [r7, #88] ; 0x58
800666a: 2301 movs r3, #1
800666c: 63bb str r3, [r7, #56] ; 0x38
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
800666e: 6bbb ldr r3, [r7, #56] ; 0x38
8006670: f383 8810 msr PRIMASK, r3
}
8006674: 46c0 nop ; (mov r8, r8)
8006676: 68fb ldr r3, [r7, #12]
8006678: 681b ldr r3, [r3, #0]
800667a: 681a ldr r2, [r3, #0]
800667c: 68fb ldr r3, [r7, #12]
800667e: 681b ldr r3, [r3, #0]
8006680: 2180 movs r1, #128 ; 0x80
8006682: 0049 lsls r1, r1, #1
8006684: 430a orrs r2, r1
8006686: 601a str r2, [r3, #0]
8006688: 6dbb ldr r3, [r7, #88] ; 0x58
800668a: 63fb str r3, [r7, #60] ; 0x3c
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
800668c: 6bfb ldr r3, [r7, #60] ; 0x3c
800668e: f383 8810 msr PRIMASK, r3
}
8006692: 46c0 nop ; (mov r8, r8)
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8006694: f3ef 8310 mrs r3, PRIMASK
8006698: 62bb str r3, [r7, #40] ; 0x28
return(result);
800669a: 6abb ldr r3, [r7, #40] ; 0x28
}
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
800669c: 657b str r3, [r7, #84] ; 0x54
800669e: 2301 movs r3, #1
80066a0: 62fb str r3, [r7, #44] ; 0x2c
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80066a2: 6afb ldr r3, [r7, #44] ; 0x2c
80066a4: f383 8810 msr PRIMASK, r3
}
80066a8: 46c0 nop ; (mov r8, r8)
80066aa: 68fb ldr r3, [r7, #12]
80066ac: 681b ldr r3, [r3, #0]
80066ae: 689a ldr r2, [r3, #8]
80066b0: 68fb ldr r3, [r7, #12]
80066b2: 681b ldr r3, [r3, #0]
80066b4: 2180 movs r1, #128 ; 0x80
80066b6: 0549 lsls r1, r1, #21
80066b8: 430a orrs r2, r1
80066ba: 609a str r2, [r3, #8]
80066bc: 6d7b ldr r3, [r7, #84] ; 0x54
80066be: 633b str r3, [r7, #48] ; 0x30
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80066c0: 6b3b ldr r3, [r7, #48] ; 0x30
80066c2: f383 8810 msr PRIMASK, r3
}
80066c6: 46c0 nop ; (mov r8, r8)
80066c8: e04b b.n 8006762 <UART_Start_Receive_IT+0x23a>
}
else
{
/* Set the Rx ISR function pointer according to the data word length */
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
80066ca: 68fb ldr r3, [r7, #12]
80066cc: 689a ldr r2, [r3, #8]
80066ce: 2380 movs r3, #128 ; 0x80
80066d0: 015b lsls r3, r3, #5
80066d2: 429a cmp r2, r3
80066d4: d107 bne.n 80066e6 <UART_Start_Receive_IT+0x1be>
80066d6: 68fb ldr r3, [r7, #12]
80066d8: 691b ldr r3, [r3, #16]
80066da: 2b00 cmp r3, #0
80066dc: d103 bne.n 80066e6 <UART_Start_Receive_IT+0x1be>
{
huart->RxISR = UART_RxISR_16BIT;
80066de: 68fb ldr r3, [r7, #12]
80066e0: 4a25 ldr r2, [pc, #148] ; (8006778 <UART_Start_Receive_IT+0x250>)
80066e2: 671a str r2, [r3, #112] ; 0x70
80066e4: e002 b.n 80066ec <UART_Start_Receive_IT+0x1c4>
}
else
{
huart->RxISR = UART_RxISR_8BIT;
80066e6: 68fb ldr r3, [r7, #12]
80066e8: 4a24 ldr r2, [pc, #144] ; (800677c <UART_Start_Receive_IT+0x254>)
80066ea: 671a str r2, [r3, #112] ; 0x70
}
__HAL_UNLOCK(huart);
80066ec: 68fb ldr r3, [r7, #12]
80066ee: 2280 movs r2, #128 ; 0x80
80066f0: 2100 movs r1, #0
80066f2: 5499 strb r1, [r3, r2]
/* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
if (huart->Init.Parity != UART_PARITY_NONE)
80066f4: 68fb ldr r3, [r7, #12]
80066f6: 691b ldr r3, [r3, #16]
80066f8: 2b00 cmp r3, #0
80066fa: d019 beq.n 8006730 <UART_Start_Receive_IT+0x208>
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
80066fc: f3ef 8310 mrs r3, PRIMASK
8006700: 61fb str r3, [r7, #28]
return(result);
8006702: 69fb ldr r3, [r7, #28]
{
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
8006704: 64fb str r3, [r7, #76] ; 0x4c
8006706: 2301 movs r3, #1
8006708: 623b str r3, [r7, #32]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
800670a: 6a3b ldr r3, [r7, #32]
800670c: f383 8810 msr PRIMASK, r3
}
8006710: 46c0 nop ; (mov r8, r8)
8006712: 68fb ldr r3, [r7, #12]
8006714: 681b ldr r3, [r3, #0]
8006716: 681a ldr r2, [r3, #0]
8006718: 68fb ldr r3, [r7, #12]
800671a: 681b ldr r3, [r3, #0]
800671c: 2190 movs r1, #144 ; 0x90
800671e: 0049 lsls r1, r1, #1
8006720: 430a orrs r2, r1
8006722: 601a str r2, [r3, #0]
8006724: 6cfb ldr r3, [r7, #76] ; 0x4c
8006726: 627b str r3, [r7, #36] ; 0x24
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006728: 6a7b ldr r3, [r7, #36] ; 0x24
800672a: f383 8810 msr PRIMASK, r3
}
800672e: e018 b.n 8006762 <UART_Start_Receive_IT+0x23a>
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8006730: f3ef 8310 mrs r3, PRIMASK
8006734: 613b str r3, [r7, #16]
return(result);
8006736: 693b ldr r3, [r7, #16]
}
else
{
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
8006738: 653b str r3, [r7, #80] ; 0x50
800673a: 2301 movs r3, #1
800673c: 617b str r3, [r7, #20]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
800673e: 697b ldr r3, [r7, #20]
8006740: f383 8810 msr PRIMASK, r3
}
8006744: 46c0 nop ; (mov r8, r8)
8006746: 68fb ldr r3, [r7, #12]
8006748: 681b ldr r3, [r3, #0]
800674a: 681a ldr r2, [r3, #0]
800674c: 68fb ldr r3, [r7, #12]
800674e: 681b ldr r3, [r3, #0]
8006750: 2120 movs r1, #32
8006752: 430a orrs r2, r1
8006754: 601a str r2, [r3, #0]
8006756: 6d3b ldr r3, [r7, #80] ; 0x50
8006758: 61bb str r3, [r7, #24]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
800675a: 69bb ldr r3, [r7, #24]
800675c: f383 8810 msr PRIMASK, r3
}
8006760: 46c0 nop ; (mov r8, r8)
}
}
return HAL_OK;
8006762: 2300 movs r3, #0
}
8006764: 0018 movs r0, r3
8006766: 46bd mov sp, r7
8006768: b018 add sp, #96 ; 0x60
800676a: bd80 pop {r7, pc}
800676c: 000001ff .word 0x000001ff
8006770: 0800704d .word 0x0800704d
8006774: 08006d69 .word 0x08006d69
8006778: 08006bfd .word 0x08006bfd
800677c: 08006a91 .word 0x08006a91
08006780 <UART_EndTxTransfer>:
* @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
* @param huart UART handle.
* @retval None
*/
static void UART_EndTxTransfer(UART_HandleTypeDef *huart)
{
8006780: b580 push {r7, lr}
8006782: b08a sub sp, #40 ; 0x28
8006784: af00 add r7, sp, #0
8006786: 6078 str r0, [r7, #4]
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8006788: f3ef 8310 mrs r3, PRIMASK
800678c: 60bb str r3, [r7, #8]
return(result);
800678e: 68bb ldr r3, [r7, #8]
/* Disable TXEIE, TCIE, TXFT interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
8006790: 627b str r3, [r7, #36] ; 0x24
8006792: 2301 movs r3, #1
8006794: 60fb str r3, [r7, #12]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006796: 68fb ldr r3, [r7, #12]
8006798: f383 8810 msr PRIMASK, r3
}
800679c: 46c0 nop ; (mov r8, r8)
800679e: 687b ldr r3, [r7, #4]
80067a0: 681b ldr r3, [r3, #0]
80067a2: 681a ldr r2, [r3, #0]
80067a4: 687b ldr r3, [r7, #4]
80067a6: 681b ldr r3, [r3, #0]
80067a8: 21c0 movs r1, #192 ; 0xc0
80067aa: 438a bics r2, r1
80067ac: 601a str r2, [r3, #0]
80067ae: 6a7b ldr r3, [r7, #36] ; 0x24
80067b0: 613b str r3, [r7, #16]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80067b2: 693b ldr r3, [r7, #16]
80067b4: f383 8810 msr PRIMASK, r3
}
80067b8: 46c0 nop ; (mov r8, r8)
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
80067ba: f3ef 8310 mrs r3, PRIMASK
80067be: 617b str r3, [r7, #20]
return(result);
80067c0: 697b ldr r3, [r7, #20]
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE));
80067c2: 623b str r3, [r7, #32]
80067c4: 2301 movs r3, #1
80067c6: 61bb str r3, [r7, #24]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80067c8: 69bb ldr r3, [r7, #24]
80067ca: f383 8810 msr PRIMASK, r3
}
80067ce: 46c0 nop ; (mov r8, r8)
80067d0: 687b ldr r3, [r7, #4]
80067d2: 681b ldr r3, [r3, #0]
80067d4: 689a ldr r2, [r3, #8]
80067d6: 687b ldr r3, [r7, #4]
80067d8: 681b ldr r3, [r3, #0]
80067da: 4908 ldr r1, [pc, #32] ; (80067fc <UART_EndTxTransfer+0x7c>)
80067dc: 400a ands r2, r1
80067de: 609a str r2, [r3, #8]
80067e0: 6a3b ldr r3, [r7, #32]
80067e2: 61fb str r3, [r7, #28]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80067e4: 69fb ldr r3, [r7, #28]
80067e6: f383 8810 msr PRIMASK, r3
}
80067ea: 46c0 nop ; (mov r8, r8)
/* At end of Tx process, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
80067ec: 687b ldr r3, [r7, #4]
80067ee: 2284 movs r2, #132 ; 0x84
80067f0: 2120 movs r1, #32
80067f2: 5099 str r1, [r3, r2]
}
80067f4: 46c0 nop ; (mov r8, r8)
80067f6: 46bd mov sp, r7
80067f8: b00a add sp, #40 ; 0x28
80067fa: bd80 pop {r7, pc}
80067fc: ff7fffff .word 0xff7fffff
08006800 <UART_EndRxTransfer>:
* @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
* @param huart UART handle.
* @retval None
*/
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
{
8006800: b580 push {r7, lr}
8006802: b08e sub sp, #56 ; 0x38
8006804: af00 add r7, sp, #0
8006806: 6078 str r0, [r7, #4]
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8006808: f3ef 8310 mrs r3, PRIMASK
800680c: 617b str r3, [r7, #20]
return(result);
800680e: 697b ldr r3, [r7, #20]
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
8006810: 637b str r3, [r7, #52] ; 0x34
8006812: 2301 movs r3, #1
8006814: 61bb str r3, [r7, #24]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006816: 69bb ldr r3, [r7, #24]
8006818: f383 8810 msr PRIMASK, r3
}
800681c: 46c0 nop ; (mov r8, r8)
800681e: 687b ldr r3, [r7, #4]
8006820: 681b ldr r3, [r3, #0]
8006822: 681a ldr r2, [r3, #0]
8006824: 687b ldr r3, [r7, #4]
8006826: 681b ldr r3, [r3, #0]
8006828: 4926 ldr r1, [pc, #152] ; (80068c4 <UART_EndRxTransfer+0xc4>)
800682a: 400a ands r2, r1
800682c: 601a str r2, [r3, #0]
800682e: 6b7b ldr r3, [r7, #52] ; 0x34
8006830: 61fb str r3, [r7, #28]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006832: 69fb ldr r3, [r7, #28]
8006834: f383 8810 msr PRIMASK, r3
}
8006838: 46c0 nop ; (mov r8, r8)
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
800683a: f3ef 8310 mrs r3, PRIMASK
800683e: 623b str r3, [r7, #32]
return(result);
8006840: 6a3b ldr r3, [r7, #32]
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
8006842: 633b str r3, [r7, #48] ; 0x30
8006844: 2301 movs r3, #1
8006846: 627b str r3, [r7, #36] ; 0x24
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006848: 6a7b ldr r3, [r7, #36] ; 0x24
800684a: f383 8810 msr PRIMASK, r3
}
800684e: 46c0 nop ; (mov r8, r8)
8006850: 687b ldr r3, [r7, #4]
8006852: 681b ldr r3, [r3, #0]
8006854: 689a ldr r2, [r3, #8]
8006856: 687b ldr r3, [r7, #4]
8006858: 681b ldr r3, [r3, #0]
800685a: 491b ldr r1, [pc, #108] ; (80068c8 <UART_EndRxTransfer+0xc8>)
800685c: 400a ands r2, r1
800685e: 609a str r2, [r3, #8]
8006860: 6b3b ldr r3, [r7, #48] ; 0x30
8006862: 62bb str r3, [r7, #40] ; 0x28
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006864: 6abb ldr r3, [r7, #40] ; 0x28
8006866: f383 8810 msr PRIMASK, r3
}
800686a: 46c0 nop ; (mov r8, r8)
/* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
800686c: 687b ldr r3, [r7, #4]
800686e: 6edb ldr r3, [r3, #108] ; 0x6c
8006870: 2b01 cmp r3, #1
8006872: d118 bne.n 80068a6 <UART_EndRxTransfer+0xa6>
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8006874: f3ef 8310 mrs r3, PRIMASK
8006878: 60bb str r3, [r7, #8]
return(result);
800687a: 68bb ldr r3, [r7, #8]
{
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
800687c: 62fb str r3, [r7, #44] ; 0x2c
800687e: 2301 movs r3, #1
8006880: 60fb str r3, [r7, #12]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006882: 68fb ldr r3, [r7, #12]
8006884: f383 8810 msr PRIMASK, r3
}
8006888: 46c0 nop ; (mov r8, r8)
800688a: 687b ldr r3, [r7, #4]
800688c: 681b ldr r3, [r3, #0]
800688e: 681a ldr r2, [r3, #0]
8006890: 687b ldr r3, [r7, #4]
8006892: 681b ldr r3, [r3, #0]
8006894: 2110 movs r1, #16
8006896: 438a bics r2, r1
8006898: 601a str r2, [r3, #0]
800689a: 6afb ldr r3, [r7, #44] ; 0x2c
800689c: 613b str r3, [r7, #16]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
800689e: 693b ldr r3, [r7, #16]
80068a0: f383 8810 msr PRIMASK, r3
}
80068a4: 46c0 nop ; (mov r8, r8)
}
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
80068a6: 687b ldr r3, [r7, #4]
80068a8: 2288 movs r2, #136 ; 0x88
80068aa: 2120 movs r1, #32
80068ac: 5099 str r1, [r3, r2]
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
80068ae: 687b ldr r3, [r7, #4]
80068b0: 2200 movs r2, #0
80068b2: 66da str r2, [r3, #108] ; 0x6c
/* Reset RxIsr function pointer */
huart->RxISR = NULL;
80068b4: 687b ldr r3, [r7, #4]
80068b6: 2200 movs r2, #0
80068b8: 671a str r2, [r3, #112] ; 0x70
}
80068ba: 46c0 nop ; (mov r8, r8)
80068bc: 46bd mov sp, r7
80068be: b00e add sp, #56 ; 0x38
80068c0: bd80 pop {r7, pc}
80068c2: 46c0 nop ; (mov r8, r8)
80068c4: fffffedf .word 0xfffffedf
80068c8: effffffe .word 0xeffffffe
080068cc <UART_DMATransmitCplt>:
* @brief DMA UART transmit process complete callback.
* @param hdma DMA handle.
* @retval None
*/
static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
{
80068cc: b580 push {r7, lr}
80068ce: b08c sub sp, #48 ; 0x30
80068d0: af00 add r7, sp, #0
80068d2: 6078 str r0, [r7, #4]
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
80068d4: 687b ldr r3, [r7, #4]
80068d6: 6a9b ldr r3, [r3, #40] ; 0x28
80068d8: 62fb str r3, [r7, #44] ; 0x2c
/* DMA Normal mode */
if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
80068da: 687b ldr r3, [r7, #4]
80068dc: 681b ldr r3, [r3, #0]
80068de: 681b ldr r3, [r3, #0]
80068e0: 2220 movs r2, #32
80068e2: 4013 ands r3, r2
80068e4: d135 bne.n 8006952 <UART_DMATransmitCplt+0x86>
{
huart->TxXferCount = 0U;
80068e6: 6afb ldr r3, [r7, #44] ; 0x2c
80068e8: 2256 movs r2, #86 ; 0x56
80068ea: 2100 movs r1, #0
80068ec: 5299 strh r1, [r3, r2]
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
80068ee: f3ef 8310 mrs r3, PRIMASK
80068f2: 60fb str r3, [r7, #12]
return(result);
80068f4: 68fb ldr r3, [r7, #12]
/* Disable the DMA transfer for transmit request by resetting the DMAT bit
in the UART CR3 register */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
80068f6: 62bb str r3, [r7, #40] ; 0x28
80068f8: 2301 movs r3, #1
80068fa: 613b str r3, [r7, #16]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80068fc: 693b ldr r3, [r7, #16]
80068fe: f383 8810 msr PRIMASK, r3
}
8006902: 46c0 nop ; (mov r8, r8)
8006904: 6afb ldr r3, [r7, #44] ; 0x2c
8006906: 681b ldr r3, [r3, #0]
8006908: 689a ldr r2, [r3, #8]
800690a: 6afb ldr r3, [r7, #44] ; 0x2c
800690c: 681b ldr r3, [r3, #0]
800690e: 2180 movs r1, #128 ; 0x80
8006910: 438a bics r2, r1
8006912: 609a str r2, [r3, #8]
8006914: 6abb ldr r3, [r7, #40] ; 0x28
8006916: 617b str r3, [r7, #20]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006918: 697b ldr r3, [r7, #20]
800691a: f383 8810 msr PRIMASK, r3
}
800691e: 46c0 nop ; (mov r8, r8)
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8006920: f3ef 8310 mrs r3, PRIMASK
8006924: 61bb str r3, [r7, #24]
return(result);
8006926: 69bb ldr r3, [r7, #24]
/* Enable the UART Transmit Complete Interrupt */
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
8006928: 627b str r3, [r7, #36] ; 0x24
800692a: 2301 movs r3, #1
800692c: 61fb str r3, [r7, #28]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
800692e: 69fb ldr r3, [r7, #28]
8006930: f383 8810 msr PRIMASK, r3
}
8006934: 46c0 nop ; (mov r8, r8)
8006936: 6afb ldr r3, [r7, #44] ; 0x2c
8006938: 681b ldr r3, [r3, #0]
800693a: 681a ldr r2, [r3, #0]
800693c: 6afb ldr r3, [r7, #44] ; 0x2c
800693e: 681b ldr r3, [r3, #0]
8006940: 2140 movs r1, #64 ; 0x40
8006942: 430a orrs r2, r1
8006944: 601a str r2, [r3, #0]
8006946: 6a7b ldr r3, [r7, #36] ; 0x24
8006948: 623b str r3, [r7, #32]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
800694a: 6a3b ldr r3, [r7, #32]
800694c: f383 8810 msr PRIMASK, r3
}
8006950: e004 b.n 800695c <UART_DMATransmitCplt+0x90>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Tx complete callback*/
huart->TxCpltCallback(huart);
#else
/*Call legacy weak Tx complete callback*/
HAL_UART_TxCpltCallback(huart);
8006952: 6afb ldr r3, [r7, #44] ; 0x2c
8006954: 0018 movs r0, r3
8006956: f7fa fd9f bl 8001498 <HAL_UART_TxCpltCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
}
800695a: 46c0 nop ; (mov r8, r8)
800695c: 46c0 nop ; (mov r8, r8)
800695e: 46bd mov sp, r7
8006960: b00c add sp, #48 ; 0x30
8006962: bd80 pop {r7, pc}
08006964 <UART_DMATxHalfCplt>:
* @brief DMA UART transmit process half complete callback.
* @param hdma DMA handle.
* @retval None
*/
static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
{
8006964: b580 push {r7, lr}
8006966: b084 sub sp, #16
8006968: af00 add r7, sp, #0
800696a: 6078 str r0, [r7, #4]
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
800696c: 687b ldr r3, [r7, #4]
800696e: 6a9b ldr r3, [r3, #40] ; 0x28
8006970: 60fb str r3, [r7, #12]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Tx Half complete callback*/
huart->TxHalfCpltCallback(huart);
#else
/*Call legacy weak Tx Half complete callback*/
HAL_UART_TxHalfCpltCallback(huart);
8006972: 68fb ldr r3, [r7, #12]
8006974: 0018 movs r0, r3
8006976: f7ff f985 bl 8005c84 <HAL_UART_TxHalfCpltCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
800697a: 46c0 nop ; (mov r8, r8)
800697c: 46bd mov sp, r7
800697e: b004 add sp, #16
8006980: bd80 pop {r7, pc}
08006982 <UART_DMAError>:
* @brief DMA UART communication error callback.
* @param hdma DMA handle.
* @retval None
*/
static void UART_DMAError(DMA_HandleTypeDef *hdma)
{
8006982: b580 push {r7, lr}
8006984: b086 sub sp, #24
8006986: af00 add r7, sp, #0
8006988: 6078 str r0, [r7, #4]
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
800698a: 687b ldr r3, [r7, #4]
800698c: 6a9b ldr r3, [r3, #40] ; 0x28
800698e: 617b str r3, [r7, #20]
const HAL_UART_StateTypeDef gstate = huart->gState;
8006990: 697b ldr r3, [r7, #20]
8006992: 2284 movs r2, #132 ; 0x84
8006994: 589b ldr r3, [r3, r2]
8006996: 613b str r3, [r7, #16]
const HAL_UART_StateTypeDef rxstate = huart->RxState;
8006998: 697b ldr r3, [r7, #20]
800699a: 2288 movs r2, #136 ; 0x88
800699c: 589b ldr r3, [r3, r2]
800699e: 60fb str r3, [r7, #12]
/* Stop UART DMA Tx request if ongoing */
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
80069a0: 697b ldr r3, [r7, #20]
80069a2: 681b ldr r3, [r3, #0]
80069a4: 689b ldr r3, [r3, #8]
80069a6: 2280 movs r2, #128 ; 0x80
80069a8: 4013 ands r3, r2
80069aa: 2b80 cmp r3, #128 ; 0x80
80069ac: d10a bne.n 80069c4 <UART_DMAError+0x42>
80069ae: 693b ldr r3, [r7, #16]
80069b0: 2b21 cmp r3, #33 ; 0x21
80069b2: d107 bne.n 80069c4 <UART_DMAError+0x42>
(gstate == HAL_UART_STATE_BUSY_TX))
{
huart->TxXferCount = 0U;
80069b4: 697b ldr r3, [r7, #20]
80069b6: 2256 movs r2, #86 ; 0x56
80069b8: 2100 movs r1, #0
80069ba: 5299 strh r1, [r3, r2]
UART_EndTxTransfer(huart);
80069bc: 697b ldr r3, [r7, #20]
80069be: 0018 movs r0, r3
80069c0: f7ff fede bl 8006780 <UART_EndTxTransfer>
}
/* Stop UART DMA Rx request if ongoing */
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
80069c4: 697b ldr r3, [r7, #20]
80069c6: 681b ldr r3, [r3, #0]
80069c8: 689b ldr r3, [r3, #8]
80069ca: 2240 movs r2, #64 ; 0x40
80069cc: 4013 ands r3, r2
80069ce: 2b40 cmp r3, #64 ; 0x40
80069d0: d10a bne.n 80069e8 <UART_DMAError+0x66>
80069d2: 68fb ldr r3, [r7, #12]
80069d4: 2b22 cmp r3, #34 ; 0x22
80069d6: d107 bne.n 80069e8 <UART_DMAError+0x66>
(rxstate == HAL_UART_STATE_BUSY_RX))
{
huart->RxXferCount = 0U;
80069d8: 697b ldr r3, [r7, #20]
80069da: 225e movs r2, #94 ; 0x5e
80069dc: 2100 movs r1, #0
80069de: 5299 strh r1, [r3, r2]
UART_EndRxTransfer(huart);
80069e0: 697b ldr r3, [r7, #20]
80069e2: 0018 movs r0, r3
80069e4: f7ff ff0c bl 8006800 <UART_EndRxTransfer>
}
huart->ErrorCode |= HAL_UART_ERROR_DMA;
80069e8: 697b ldr r3, [r7, #20]
80069ea: 228c movs r2, #140 ; 0x8c
80069ec: 589b ldr r3, [r3, r2]
80069ee: 2210 movs r2, #16
80069f0: 431a orrs r2, r3
80069f2: 697b ldr r3, [r7, #20]
80069f4: 218c movs r1, #140 ; 0x8c
80069f6: 505a str r2, [r3, r1]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
80069f8: 697b ldr r3, [r7, #20]
80069fa: 0018 movs r0, r3
80069fc: f7fa fd62 bl 80014c4 <HAL_UART_ErrorCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
8006a00: 46c0 nop ; (mov r8, r8)
8006a02: 46bd mov sp, r7
8006a04: b006 add sp, #24
8006a06: bd80 pop {r7, pc}
08006a08 <UART_DMAAbortOnError>:
* (To be called at end of DMA Abort procedure following error occurrence).
* @param hdma DMA handle.
* @retval None
*/
static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
{
8006a08: b580 push {r7, lr}
8006a0a: b084 sub sp, #16
8006a0c: af00 add r7, sp, #0
8006a0e: 6078 str r0, [r7, #4]
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
8006a10: 687b ldr r3, [r7, #4]
8006a12: 6a9b ldr r3, [r3, #40] ; 0x28
8006a14: 60fb str r3, [r7, #12]
huart->RxXferCount = 0U;
8006a16: 68fb ldr r3, [r7, #12]
8006a18: 225e movs r2, #94 ; 0x5e
8006a1a: 2100 movs r1, #0
8006a1c: 5299 strh r1, [r3, r2]
huart->TxXferCount = 0U;
8006a1e: 68fb ldr r3, [r7, #12]
8006a20: 2256 movs r2, #86 ; 0x56
8006a22: 2100 movs r1, #0
8006a24: 5299 strh r1, [r3, r2]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
8006a26: 68fb ldr r3, [r7, #12]
8006a28: 0018 movs r0, r3
8006a2a: f7fa fd4b bl 80014c4 <HAL_UART_ErrorCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
8006a2e: 46c0 nop ; (mov r8, r8)
8006a30: 46bd mov sp, r7
8006a32: b004 add sp, #16
8006a34: bd80 pop {r7, pc}
08006a36 <UART_EndTransmit_IT>:
* @param huart pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
static void UART_EndTransmit_IT(UART_HandleTypeDef *huart)
{
8006a36: b580 push {r7, lr}
8006a38: b086 sub sp, #24
8006a3a: af00 add r7, sp, #0
8006a3c: 6078 str r0, [r7, #4]
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8006a3e: f3ef 8310 mrs r3, PRIMASK
8006a42: 60bb str r3, [r7, #8]
return(result);
8006a44: 68bb ldr r3, [r7, #8]
/* Disable the UART Transmit Complete Interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
8006a46: 617b str r3, [r7, #20]
8006a48: 2301 movs r3, #1
8006a4a: 60fb str r3, [r7, #12]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006a4c: 68fb ldr r3, [r7, #12]
8006a4e: f383 8810 msr PRIMASK, r3
}
8006a52: 46c0 nop ; (mov r8, r8)
8006a54: 687b ldr r3, [r7, #4]
8006a56: 681b ldr r3, [r3, #0]
8006a58: 681a ldr r2, [r3, #0]
8006a5a: 687b ldr r3, [r7, #4]
8006a5c: 681b ldr r3, [r3, #0]
8006a5e: 2140 movs r1, #64 ; 0x40
8006a60: 438a bics r2, r1
8006a62: 601a str r2, [r3, #0]
8006a64: 697b ldr r3, [r7, #20]
8006a66: 613b str r3, [r7, #16]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006a68: 693b ldr r3, [r7, #16]
8006a6a: f383 8810 msr PRIMASK, r3
}
8006a6e: 46c0 nop ; (mov r8, r8)
/* Tx process is ended, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
8006a70: 687b ldr r3, [r7, #4]
8006a72: 2284 movs r2, #132 ; 0x84
8006a74: 2120 movs r1, #32
8006a76: 5099 str r1, [r3, r2]
/* Cleat TxISR function pointer */
huart->TxISR = NULL;
8006a78: 687b ldr r3, [r7, #4]
8006a7a: 2200 movs r2, #0
8006a7c: 675a str r2, [r3, #116] ; 0x74
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Tx complete callback*/
huart->TxCpltCallback(huart);
#else
/*Call legacy weak Tx complete callback*/
HAL_UART_TxCpltCallback(huart);
8006a7e: 687b ldr r3, [r7, #4]
8006a80: 0018 movs r0, r3
8006a82: f7fa fd09 bl 8001498 <HAL_UART_TxCpltCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
8006a86: 46c0 nop ; (mov r8, r8)
8006a88: 46bd mov sp, r7
8006a8a: b006 add sp, #24
8006a8c: bd80 pop {r7, pc}
...
08006a90 <UART_RxISR_8BIT>:
* @brief RX interrupt handler for 7 or 8 bits data word length .
* @param huart UART handle.
* @retval None
*/
static void UART_RxISR_8BIT(UART_HandleTypeDef *huart)
{
8006a90: b580 push {r7, lr}
8006a92: b090 sub sp, #64 ; 0x40
8006a94: af00 add r7, sp, #0
8006a96: 6078 str r0, [r7, #4]
uint16_t uhMask = huart->Mask;
8006a98: 203e movs r0, #62 ; 0x3e
8006a9a: 183b adds r3, r7, r0
8006a9c: 687a ldr r2, [r7, #4]
8006a9e: 2160 movs r1, #96 ; 0x60
8006aa0: 5a52 ldrh r2, [r2, r1]
8006aa2: 801a strh r2, [r3, #0]
uint16_t uhdata;
/* Check that a Rx process is ongoing */
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
8006aa4: 687b ldr r3, [r7, #4]
8006aa6: 2288 movs r2, #136 ; 0x88
8006aa8: 589b ldr r3, [r3, r2]
8006aaa: 2b22 cmp r3, #34 ; 0x22
8006aac: d000 beq.n 8006ab0 <UART_RxISR_8BIT+0x20>
8006aae: e097 b.n 8006be0 <UART_RxISR_8BIT+0x150>
{
uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
8006ab0: 687b ldr r3, [r7, #4]
8006ab2: 681b ldr r3, [r3, #0]
8006ab4: 6a5a ldr r2, [r3, #36] ; 0x24
8006ab6: 213c movs r1, #60 ; 0x3c
8006ab8: 187b adds r3, r7, r1
8006aba: 801a strh r2, [r3, #0]
*huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
8006abc: 187b adds r3, r7, r1
8006abe: 881b ldrh r3, [r3, #0]
8006ac0: b2da uxtb r2, r3
8006ac2: 183b adds r3, r7, r0
8006ac4: 881b ldrh r3, [r3, #0]
8006ac6: b2d9 uxtb r1, r3
8006ac8: 687b ldr r3, [r7, #4]
8006aca: 6d9b ldr r3, [r3, #88] ; 0x58
8006acc: 400a ands r2, r1
8006ace: b2d2 uxtb r2, r2
8006ad0: 701a strb r2, [r3, #0]
huart->pRxBuffPtr++;
8006ad2: 687b ldr r3, [r7, #4]
8006ad4: 6d9b ldr r3, [r3, #88] ; 0x58
8006ad6: 1c5a adds r2, r3, #1
8006ad8: 687b ldr r3, [r7, #4]
8006ada: 659a str r2, [r3, #88] ; 0x58
huart->RxXferCount--;
8006adc: 687b ldr r3, [r7, #4]
8006ade: 225e movs r2, #94 ; 0x5e
8006ae0: 5a9b ldrh r3, [r3, r2]
8006ae2: b29b uxth r3, r3
8006ae4: 3b01 subs r3, #1
8006ae6: b299 uxth r1, r3
8006ae8: 687b ldr r3, [r7, #4]
8006aea: 225e movs r2, #94 ; 0x5e
8006aec: 5299 strh r1, [r3, r2]
if (huart->RxXferCount == 0U)
8006aee: 687b ldr r3, [r7, #4]
8006af0: 225e movs r2, #94 ; 0x5e
8006af2: 5a9b ldrh r3, [r3, r2]
8006af4: b29b uxth r3, r3
8006af6: 2b00 cmp r3, #0
8006af8: d000 beq.n 8006afc <UART_RxISR_8BIT+0x6c>
8006afa: e079 b.n 8006bf0 <UART_RxISR_8BIT+0x160>
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8006afc: f3ef 8310 mrs r3, PRIMASK
8006b00: 61bb str r3, [r7, #24]
return(result);
8006b02: 69bb ldr r3, [r7, #24]
{
/* Disable the UART Parity Error Interrupt and RXNE interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
8006b04: 63bb str r3, [r7, #56] ; 0x38
8006b06: 2301 movs r3, #1
8006b08: 61fb str r3, [r7, #28]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006b0a: 69fb ldr r3, [r7, #28]
8006b0c: f383 8810 msr PRIMASK, r3
}
8006b10: 46c0 nop ; (mov r8, r8)
8006b12: 687b ldr r3, [r7, #4]
8006b14: 681b ldr r3, [r3, #0]
8006b16: 681a ldr r2, [r3, #0]
8006b18: 687b ldr r3, [r7, #4]
8006b1a: 681b ldr r3, [r3, #0]
8006b1c: 4936 ldr r1, [pc, #216] ; (8006bf8 <UART_RxISR_8BIT+0x168>)
8006b1e: 400a ands r2, r1
8006b20: 601a str r2, [r3, #0]
8006b22: 6bbb ldr r3, [r7, #56] ; 0x38
8006b24: 623b str r3, [r7, #32]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006b26: 6a3b ldr r3, [r7, #32]
8006b28: f383 8810 msr PRIMASK, r3
}
8006b2c: 46c0 nop ; (mov r8, r8)
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8006b2e: f3ef 8310 mrs r3, PRIMASK
8006b32: 627b str r3, [r7, #36] ; 0x24
return(result);
8006b34: 6a7b ldr r3, [r7, #36] ; 0x24
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
8006b36: 637b str r3, [r7, #52] ; 0x34
8006b38: 2301 movs r3, #1
8006b3a: 62bb str r3, [r7, #40] ; 0x28
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006b3c: 6abb ldr r3, [r7, #40] ; 0x28
8006b3e: f383 8810 msr PRIMASK, r3
}
8006b42: 46c0 nop ; (mov r8, r8)
8006b44: 687b ldr r3, [r7, #4]
8006b46: 681b ldr r3, [r3, #0]
8006b48: 689a ldr r2, [r3, #8]
8006b4a: 687b ldr r3, [r7, #4]
8006b4c: 681b ldr r3, [r3, #0]
8006b4e: 2101 movs r1, #1
8006b50: 438a bics r2, r1
8006b52: 609a str r2, [r3, #8]
8006b54: 6b7b ldr r3, [r7, #52] ; 0x34
8006b56: 62fb str r3, [r7, #44] ; 0x2c
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006b58: 6afb ldr r3, [r7, #44] ; 0x2c
8006b5a: f383 8810 msr PRIMASK, r3
}
8006b5e: 46c0 nop ; (mov r8, r8)
/* Rx process is completed, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
8006b60: 687b ldr r3, [r7, #4]
8006b62: 2288 movs r2, #136 ; 0x88
8006b64: 2120 movs r1, #32
8006b66: 5099 str r1, [r3, r2]
/* Clear RxISR function pointer */
huart->RxISR = NULL;
8006b68: 687b ldr r3, [r7, #4]
8006b6a: 2200 movs r2, #0
8006b6c: 671a str r2, [r3, #112] ; 0x70
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
8006b6e: 687b ldr r3, [r7, #4]
8006b70: 6edb ldr r3, [r3, #108] ; 0x6c
8006b72: 2b01 cmp r3, #1
8006b74: d12f bne.n 8006bd6 <UART_RxISR_8BIT+0x146>
{
/* Set reception type to Standard */
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8006b76: 687b ldr r3, [r7, #4]
8006b78: 2200 movs r2, #0
8006b7a: 66da str r2, [r3, #108] ; 0x6c
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8006b7c: f3ef 8310 mrs r3, PRIMASK
8006b80: 60fb str r3, [r7, #12]
return(result);
8006b82: 68fb ldr r3, [r7, #12]
/* Disable IDLE interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8006b84: 633b str r3, [r7, #48] ; 0x30
8006b86: 2301 movs r3, #1
8006b88: 613b str r3, [r7, #16]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006b8a: 693b ldr r3, [r7, #16]
8006b8c: f383 8810 msr PRIMASK, r3
}
8006b90: 46c0 nop ; (mov r8, r8)
8006b92: 687b ldr r3, [r7, #4]
8006b94: 681b ldr r3, [r3, #0]
8006b96: 681a ldr r2, [r3, #0]
8006b98: 687b ldr r3, [r7, #4]
8006b9a: 681b ldr r3, [r3, #0]
8006b9c: 2110 movs r1, #16
8006b9e: 438a bics r2, r1
8006ba0: 601a str r2, [r3, #0]
8006ba2: 6b3b ldr r3, [r7, #48] ; 0x30
8006ba4: 617b str r3, [r7, #20]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006ba6: 697b ldr r3, [r7, #20]
8006ba8: f383 8810 msr PRIMASK, r3
}
8006bac: 46c0 nop ; (mov r8, r8)
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
8006bae: 687b ldr r3, [r7, #4]
8006bb0: 681b ldr r3, [r3, #0]
8006bb2: 69db ldr r3, [r3, #28]
8006bb4: 2210 movs r2, #16
8006bb6: 4013 ands r3, r2
8006bb8: 2b10 cmp r3, #16
8006bba: d103 bne.n 8006bc4 <UART_RxISR_8BIT+0x134>
{
/* Clear IDLE Flag */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
8006bbc: 687b ldr r3, [r7, #4]
8006bbe: 681b ldr r3, [r3, #0]
8006bc0: 2210 movs r2, #16
8006bc2: 621a str r2, [r3, #32]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize);
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
8006bc4: 687b ldr r3, [r7, #4]
8006bc6: 225c movs r2, #92 ; 0x5c
8006bc8: 5a9a ldrh r2, [r3, r2]
8006bca: 687b ldr r3, [r7, #4]
8006bcc: 0011 movs r1, r2
8006bce: 0018 movs r0, r3
8006bd0: f7ff f860 bl 8005c94 <HAL_UARTEx_RxEventCallback>
else
{
/* Clear RXNE interrupt flag */
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
}
}
8006bd4: e00c b.n 8006bf0 <UART_RxISR_8BIT+0x160>
HAL_UART_RxCpltCallback(huart);
8006bd6: 687b ldr r3, [r7, #4]
8006bd8: 0018 movs r0, r3
8006bda: f7fa fc23 bl 8001424 <HAL_UART_RxCpltCallback>
}
8006bde: e007 b.n 8006bf0 <UART_RxISR_8BIT+0x160>
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
8006be0: 687b ldr r3, [r7, #4]
8006be2: 681b ldr r3, [r3, #0]
8006be4: 699a ldr r2, [r3, #24]
8006be6: 687b ldr r3, [r7, #4]
8006be8: 681b ldr r3, [r3, #0]
8006bea: 2108 movs r1, #8
8006bec: 430a orrs r2, r1
8006bee: 619a str r2, [r3, #24]
}
8006bf0: 46c0 nop ; (mov r8, r8)
8006bf2: 46bd mov sp, r7
8006bf4: b010 add sp, #64 ; 0x40
8006bf6: bd80 pop {r7, pc}
8006bf8: fffffedf .word 0xfffffedf
08006bfc <UART_RxISR_16BIT>:
* interruptions have been enabled by HAL_UART_Receive_IT()
* @param huart UART handle.
* @retval None
*/
static void UART_RxISR_16BIT(UART_HandleTypeDef *huart)
{
8006bfc: b580 push {r7, lr}
8006bfe: b090 sub sp, #64 ; 0x40
8006c00: af00 add r7, sp, #0
8006c02: 6078 str r0, [r7, #4]
uint16_t *tmp;
uint16_t uhMask = huart->Mask;
8006c04: 203e movs r0, #62 ; 0x3e
8006c06: 183b adds r3, r7, r0
8006c08: 687a ldr r2, [r7, #4]
8006c0a: 2160 movs r1, #96 ; 0x60
8006c0c: 5a52 ldrh r2, [r2, r1]
8006c0e: 801a strh r2, [r3, #0]
uint16_t uhdata;
/* Check that a Rx process is ongoing */
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
8006c10: 687b ldr r3, [r7, #4]
8006c12: 2288 movs r2, #136 ; 0x88
8006c14: 589b ldr r3, [r3, r2]
8006c16: 2b22 cmp r3, #34 ; 0x22
8006c18: d000 beq.n 8006c1c <UART_RxISR_16BIT+0x20>
8006c1a: e097 b.n 8006d4c <UART_RxISR_16BIT+0x150>
{
uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
8006c1c: 687b ldr r3, [r7, #4]
8006c1e: 681b ldr r3, [r3, #0]
8006c20: 6a5a ldr r2, [r3, #36] ; 0x24
8006c22: 213c movs r1, #60 ; 0x3c
8006c24: 187b adds r3, r7, r1
8006c26: 801a strh r2, [r3, #0]
tmp = (uint16_t *) huart->pRxBuffPtr ;
8006c28: 687b ldr r3, [r7, #4]
8006c2a: 6d9b ldr r3, [r3, #88] ; 0x58
8006c2c: 63bb str r3, [r7, #56] ; 0x38
*tmp = (uint16_t)(uhdata & uhMask);
8006c2e: 187b adds r3, r7, r1
8006c30: 183a adds r2, r7, r0
8006c32: 881b ldrh r3, [r3, #0]
8006c34: 8812 ldrh r2, [r2, #0]
8006c36: 4013 ands r3, r2
8006c38: b29a uxth r2, r3
8006c3a: 6bbb ldr r3, [r7, #56] ; 0x38
8006c3c: 801a strh r2, [r3, #0]
huart->pRxBuffPtr += 2U;
8006c3e: 687b ldr r3, [r7, #4]
8006c40: 6d9b ldr r3, [r3, #88] ; 0x58
8006c42: 1c9a adds r2, r3, #2
8006c44: 687b ldr r3, [r7, #4]
8006c46: 659a str r2, [r3, #88] ; 0x58
huart->RxXferCount--;
8006c48: 687b ldr r3, [r7, #4]
8006c4a: 225e movs r2, #94 ; 0x5e
8006c4c: 5a9b ldrh r3, [r3, r2]
8006c4e: b29b uxth r3, r3
8006c50: 3b01 subs r3, #1
8006c52: b299 uxth r1, r3
8006c54: 687b ldr r3, [r7, #4]
8006c56: 225e movs r2, #94 ; 0x5e
8006c58: 5299 strh r1, [r3, r2]
if (huart->RxXferCount == 0U)
8006c5a: 687b ldr r3, [r7, #4]
8006c5c: 225e movs r2, #94 ; 0x5e
8006c5e: 5a9b ldrh r3, [r3, r2]
8006c60: b29b uxth r3, r3
8006c62: 2b00 cmp r3, #0
8006c64: d000 beq.n 8006c68 <UART_RxISR_16BIT+0x6c>
8006c66: e079 b.n 8006d5c <UART_RxISR_16BIT+0x160>
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8006c68: f3ef 8310 mrs r3, PRIMASK
8006c6c: 617b str r3, [r7, #20]
return(result);
8006c6e: 697b ldr r3, [r7, #20]
{
/* Disable the UART Parity Error Interrupt and RXNE interrupt*/
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
8006c70: 637b str r3, [r7, #52] ; 0x34
8006c72: 2301 movs r3, #1
8006c74: 61bb str r3, [r7, #24]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006c76: 69bb ldr r3, [r7, #24]
8006c78: f383 8810 msr PRIMASK, r3
}
8006c7c: 46c0 nop ; (mov r8, r8)
8006c7e: 687b ldr r3, [r7, #4]
8006c80: 681b ldr r3, [r3, #0]
8006c82: 681a ldr r2, [r3, #0]
8006c84: 687b ldr r3, [r7, #4]
8006c86: 681b ldr r3, [r3, #0]
8006c88: 4936 ldr r1, [pc, #216] ; (8006d64 <UART_RxISR_16BIT+0x168>)
8006c8a: 400a ands r2, r1
8006c8c: 601a str r2, [r3, #0]
8006c8e: 6b7b ldr r3, [r7, #52] ; 0x34
8006c90: 61fb str r3, [r7, #28]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006c92: 69fb ldr r3, [r7, #28]
8006c94: f383 8810 msr PRIMASK, r3
}
8006c98: 46c0 nop ; (mov r8, r8)
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8006c9a: f3ef 8310 mrs r3, PRIMASK
8006c9e: 623b str r3, [r7, #32]
return(result);
8006ca0: 6a3b ldr r3, [r7, #32]
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
8006ca2: 633b str r3, [r7, #48] ; 0x30
8006ca4: 2301 movs r3, #1
8006ca6: 627b str r3, [r7, #36] ; 0x24
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006ca8: 6a7b ldr r3, [r7, #36] ; 0x24
8006caa: f383 8810 msr PRIMASK, r3
}
8006cae: 46c0 nop ; (mov r8, r8)
8006cb0: 687b ldr r3, [r7, #4]
8006cb2: 681b ldr r3, [r3, #0]
8006cb4: 689a ldr r2, [r3, #8]
8006cb6: 687b ldr r3, [r7, #4]
8006cb8: 681b ldr r3, [r3, #0]
8006cba: 2101 movs r1, #1
8006cbc: 438a bics r2, r1
8006cbe: 609a str r2, [r3, #8]
8006cc0: 6b3b ldr r3, [r7, #48] ; 0x30
8006cc2: 62bb str r3, [r7, #40] ; 0x28
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006cc4: 6abb ldr r3, [r7, #40] ; 0x28
8006cc6: f383 8810 msr PRIMASK, r3
}
8006cca: 46c0 nop ; (mov r8, r8)
/* Rx process is completed, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
8006ccc: 687b ldr r3, [r7, #4]
8006cce: 2288 movs r2, #136 ; 0x88
8006cd0: 2120 movs r1, #32
8006cd2: 5099 str r1, [r3, r2]
/* Clear RxISR function pointer */
huart->RxISR = NULL;
8006cd4: 687b ldr r3, [r7, #4]
8006cd6: 2200 movs r2, #0
8006cd8: 671a str r2, [r3, #112] ; 0x70
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
8006cda: 687b ldr r3, [r7, #4]
8006cdc: 6edb ldr r3, [r3, #108] ; 0x6c
8006cde: 2b01 cmp r3, #1
8006ce0: d12f bne.n 8006d42 <UART_RxISR_16BIT+0x146>
{
/* Set reception type to Standard */
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8006ce2: 687b ldr r3, [r7, #4]
8006ce4: 2200 movs r2, #0
8006ce6: 66da str r2, [r3, #108] ; 0x6c
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8006ce8: f3ef 8310 mrs r3, PRIMASK
8006cec: 60bb str r3, [r7, #8]
return(result);
8006cee: 68bb ldr r3, [r7, #8]
/* Disable IDLE interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8006cf0: 62fb str r3, [r7, #44] ; 0x2c
8006cf2: 2301 movs r3, #1
8006cf4: 60fb str r3, [r7, #12]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006cf6: 68fb ldr r3, [r7, #12]
8006cf8: f383 8810 msr PRIMASK, r3
}
8006cfc: 46c0 nop ; (mov r8, r8)
8006cfe: 687b ldr r3, [r7, #4]
8006d00: 681b ldr r3, [r3, #0]
8006d02: 681a ldr r2, [r3, #0]
8006d04: 687b ldr r3, [r7, #4]
8006d06: 681b ldr r3, [r3, #0]
8006d08: 2110 movs r1, #16
8006d0a: 438a bics r2, r1
8006d0c: 601a str r2, [r3, #0]
8006d0e: 6afb ldr r3, [r7, #44] ; 0x2c
8006d10: 613b str r3, [r7, #16]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006d12: 693b ldr r3, [r7, #16]
8006d14: f383 8810 msr PRIMASK, r3
}
8006d18: 46c0 nop ; (mov r8, r8)
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
8006d1a: 687b ldr r3, [r7, #4]
8006d1c: 681b ldr r3, [r3, #0]
8006d1e: 69db ldr r3, [r3, #28]
8006d20: 2210 movs r2, #16
8006d22: 4013 ands r3, r2
8006d24: 2b10 cmp r3, #16
8006d26: d103 bne.n 8006d30 <UART_RxISR_16BIT+0x134>
{
/* Clear IDLE Flag */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
8006d28: 687b ldr r3, [r7, #4]
8006d2a: 681b ldr r3, [r3, #0]
8006d2c: 2210 movs r2, #16
8006d2e: 621a str r2, [r3, #32]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize);
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
8006d30: 687b ldr r3, [r7, #4]
8006d32: 225c movs r2, #92 ; 0x5c
8006d34: 5a9a ldrh r2, [r3, r2]
8006d36: 687b ldr r3, [r7, #4]
8006d38: 0011 movs r1, r2
8006d3a: 0018 movs r0, r3
8006d3c: f7fe ffaa bl 8005c94 <HAL_UARTEx_RxEventCallback>
else
{
/* Clear RXNE interrupt flag */
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
}
}
8006d40: e00c b.n 8006d5c <UART_RxISR_16BIT+0x160>
HAL_UART_RxCpltCallback(huart);
8006d42: 687b ldr r3, [r7, #4]
8006d44: 0018 movs r0, r3
8006d46: f7fa fb6d bl 8001424 <HAL_UART_RxCpltCallback>
}
8006d4a: e007 b.n 8006d5c <UART_RxISR_16BIT+0x160>
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
8006d4c: 687b ldr r3, [r7, #4]
8006d4e: 681b ldr r3, [r3, #0]
8006d50: 699a ldr r2, [r3, #24]
8006d52: 687b ldr r3, [r7, #4]
8006d54: 681b ldr r3, [r3, #0]
8006d56: 2108 movs r1, #8
8006d58: 430a orrs r2, r1
8006d5a: 619a str r2, [r3, #24]
}
8006d5c: 46c0 nop ; (mov r8, r8)
8006d5e: 46bd mov sp, r7
8006d60: b010 add sp, #64 ; 0x40
8006d62: bd80 pop {r7, pc}
8006d64: fffffedf .word 0xfffffedf
08006d68 <UART_RxISR_8BIT_FIFOEN>:
* interruptions have been enabled by HAL_UART_Receive_IT()
* @param huart UART handle.
* @retval None
*/
static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)
{
8006d68: b580 push {r7, lr}
8006d6a: b09c sub sp, #112 ; 0x70
8006d6c: af00 add r7, sp, #0
8006d6e: 6078 str r0, [r7, #4]
uint16_t uhMask = huart->Mask;
8006d70: 236a movs r3, #106 ; 0x6a
8006d72: 18fb adds r3, r7, r3
8006d74: 687a ldr r2, [r7, #4]
8006d76: 2160 movs r1, #96 ; 0x60
8006d78: 5a52 ldrh r2, [r2, r1]
8006d7a: 801a strh r2, [r3, #0]
uint16_t uhdata;
uint16_t nb_rx_data;
uint16_t rxdatacount;
uint32_t isrflags = READ_REG(huart->Instance->ISR);
8006d7c: 687b ldr r3, [r7, #4]
8006d7e: 681b ldr r3, [r3, #0]
8006d80: 69db ldr r3, [r3, #28]
8006d82: 66fb str r3, [r7, #108] ; 0x6c
uint32_t cr1its = READ_REG(huart->Instance->CR1);
8006d84: 687b ldr r3, [r7, #4]
8006d86: 681b ldr r3, [r3, #0]
8006d88: 681b ldr r3, [r3, #0]
8006d8a: 667b str r3, [r7, #100] ; 0x64
uint32_t cr3its = READ_REG(huart->Instance->CR3);
8006d8c: 687b ldr r3, [r7, #4]
8006d8e: 681b ldr r3, [r3, #0]
8006d90: 689b ldr r3, [r3, #8]
8006d92: 663b str r3, [r7, #96] ; 0x60
/* Check that a Rx process is ongoing */
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
8006d94: 687b ldr r3, [r7, #4]
8006d96: 2288 movs r2, #136 ; 0x88
8006d98: 589b ldr r3, [r3, r2]
8006d9a: 2b22 cmp r3, #34 ; 0x22
8006d9c: d000 beq.n 8006da0 <UART_RxISR_8BIT_FIFOEN+0x38>
8006d9e: e141 b.n 8007024 <UART_RxISR_8BIT_FIFOEN+0x2bc>
{
nb_rx_data = huart->NbRxDataToProcess;
8006da0: 235e movs r3, #94 ; 0x5e
8006da2: 18fb adds r3, r7, r3
8006da4: 687a ldr r2, [r7, #4]
8006da6: 2168 movs r1, #104 ; 0x68
8006da8: 5a52 ldrh r2, [r2, r1]
8006daa: 801a strh r2, [r3, #0]
while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
8006dac: e0e8 b.n 8006f80 <UART_RxISR_8BIT_FIFOEN+0x218>
{
uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
8006dae: 687b ldr r3, [r7, #4]
8006db0: 681b ldr r3, [r3, #0]
8006db2: 6a5a ldr r2, [r3, #36] ; 0x24
8006db4: 215c movs r1, #92 ; 0x5c
8006db6: 187b adds r3, r7, r1
8006db8: 801a strh r2, [r3, #0]
*huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
8006dba: 187b adds r3, r7, r1
8006dbc: 881b ldrh r3, [r3, #0]
8006dbe: b2da uxtb r2, r3
8006dc0: 236a movs r3, #106 ; 0x6a
8006dc2: 18fb adds r3, r7, r3
8006dc4: 881b ldrh r3, [r3, #0]
8006dc6: b2d9 uxtb r1, r3
8006dc8: 687b ldr r3, [r7, #4]
8006dca: 6d9b ldr r3, [r3, #88] ; 0x58
8006dcc: 400a ands r2, r1
8006dce: b2d2 uxtb r2, r2
8006dd0: 701a strb r2, [r3, #0]
huart->pRxBuffPtr++;
8006dd2: 687b ldr r3, [r7, #4]
8006dd4: 6d9b ldr r3, [r3, #88] ; 0x58
8006dd6: 1c5a adds r2, r3, #1
8006dd8: 687b ldr r3, [r7, #4]
8006dda: 659a str r2, [r3, #88] ; 0x58
huart->RxXferCount--;
8006ddc: 687b ldr r3, [r7, #4]
8006dde: 225e movs r2, #94 ; 0x5e
8006de0: 5a9b ldrh r3, [r3, r2]
8006de2: b29b uxth r3, r3
8006de4: 3b01 subs r3, #1
8006de6: b299 uxth r1, r3
8006de8: 687b ldr r3, [r7, #4]
8006dea: 225e movs r2, #94 ; 0x5e
8006dec: 5299 strh r1, [r3, r2]
isrflags = READ_REG(huart->Instance->ISR);
8006dee: 687b ldr r3, [r7, #4]
8006df0: 681b ldr r3, [r3, #0]
8006df2: 69db ldr r3, [r3, #28]
8006df4: 66fb str r3, [r7, #108] ; 0x6c
/* If some non blocking errors occurred */
if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U)
8006df6: 6efb ldr r3, [r7, #108] ; 0x6c
8006df8: 2207 movs r2, #7
8006dfa: 4013 ands r3, r2
8006dfc: d049 beq.n 8006e92 <UART_RxISR_8BIT_FIFOEN+0x12a>
{
/* UART parity error interrupt occurred -------------------------------------*/
if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
8006dfe: 6efb ldr r3, [r7, #108] ; 0x6c
8006e00: 2201 movs r2, #1
8006e02: 4013 ands r3, r2
8006e04: d010 beq.n 8006e28 <UART_RxISR_8BIT_FIFOEN+0xc0>
8006e06: 6e7a ldr r2, [r7, #100] ; 0x64
8006e08: 2380 movs r3, #128 ; 0x80
8006e0a: 005b lsls r3, r3, #1
8006e0c: 4013 ands r3, r2
8006e0e: d00b beq.n 8006e28 <UART_RxISR_8BIT_FIFOEN+0xc0>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
8006e10: 687b ldr r3, [r7, #4]
8006e12: 681b ldr r3, [r3, #0]
8006e14: 2201 movs r2, #1
8006e16: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_PE;
8006e18: 687b ldr r3, [r7, #4]
8006e1a: 228c movs r2, #140 ; 0x8c
8006e1c: 589b ldr r3, [r3, r2]
8006e1e: 2201 movs r2, #1
8006e20: 431a orrs r2, r3
8006e22: 687b ldr r3, [r7, #4]
8006e24: 218c movs r1, #140 ; 0x8c
8006e26: 505a str r2, [r3, r1]
}
/* UART frame error interrupt occurred --------------------------------------*/
if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
8006e28: 6efb ldr r3, [r7, #108] ; 0x6c
8006e2a: 2202 movs r2, #2
8006e2c: 4013 ands r3, r2
8006e2e: d00f beq.n 8006e50 <UART_RxISR_8BIT_FIFOEN+0xe8>
8006e30: 6e3b ldr r3, [r7, #96] ; 0x60
8006e32: 2201 movs r2, #1
8006e34: 4013 ands r3, r2
8006e36: d00b beq.n 8006e50 <UART_RxISR_8BIT_FIFOEN+0xe8>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
8006e38: 687b ldr r3, [r7, #4]
8006e3a: 681b ldr r3, [r3, #0]
8006e3c: 2202 movs r2, #2
8006e3e: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_FE;
8006e40: 687b ldr r3, [r7, #4]
8006e42: 228c movs r2, #140 ; 0x8c
8006e44: 589b ldr r3, [r3, r2]
8006e46: 2204 movs r2, #4
8006e48: 431a orrs r2, r3
8006e4a: 687b ldr r3, [r7, #4]
8006e4c: 218c movs r1, #140 ; 0x8c
8006e4e: 505a str r2, [r3, r1]
}
/* UART noise error interrupt occurred --------------------------------------*/
if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
8006e50: 6efb ldr r3, [r7, #108] ; 0x6c
8006e52: 2204 movs r2, #4
8006e54: 4013 ands r3, r2
8006e56: d00f beq.n 8006e78 <UART_RxISR_8BIT_FIFOEN+0x110>
8006e58: 6e3b ldr r3, [r7, #96] ; 0x60
8006e5a: 2201 movs r2, #1
8006e5c: 4013 ands r3, r2
8006e5e: d00b beq.n 8006e78 <UART_RxISR_8BIT_FIFOEN+0x110>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
8006e60: 687b ldr r3, [r7, #4]
8006e62: 681b ldr r3, [r3, #0]
8006e64: 2204 movs r2, #4
8006e66: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_NE;
8006e68: 687b ldr r3, [r7, #4]
8006e6a: 228c movs r2, #140 ; 0x8c
8006e6c: 589b ldr r3, [r3, r2]
8006e6e: 2202 movs r2, #2
8006e70: 431a orrs r2, r3
8006e72: 687b ldr r3, [r7, #4]
8006e74: 218c movs r1, #140 ; 0x8c
8006e76: 505a str r2, [r3, r1]
}
/* Call UART Error Call back function if need be ----------------------------*/
if (huart->ErrorCode != HAL_UART_ERROR_NONE)
8006e78: 687b ldr r3, [r7, #4]
8006e7a: 228c movs r2, #140 ; 0x8c
8006e7c: 589b ldr r3, [r3, r2]
8006e7e: 2b00 cmp r3, #0
8006e80: d007 beq.n 8006e92 <UART_RxISR_8BIT_FIFOEN+0x12a>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
8006e82: 687b ldr r3, [r7, #4]
8006e84: 0018 movs r0, r3
8006e86: f7fa fb1d bl 80014c4 <HAL_UART_ErrorCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
huart->ErrorCode = HAL_UART_ERROR_NONE;
8006e8a: 687b ldr r3, [r7, #4]
8006e8c: 228c movs r2, #140 ; 0x8c
8006e8e: 2100 movs r1, #0
8006e90: 5099 str r1, [r3, r2]
}
}
if (huart->RxXferCount == 0U)
8006e92: 687b ldr r3, [r7, #4]
8006e94: 225e movs r2, #94 ; 0x5e
8006e96: 5a9b ldrh r3, [r3, r2]
8006e98: b29b uxth r3, r3
8006e9a: 2b00 cmp r3, #0
8006e9c: d170 bne.n 8006f80 <UART_RxISR_8BIT_FIFOEN+0x218>
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8006e9e: f3ef 8310 mrs r3, PRIMASK
8006ea2: 62fb str r3, [r7, #44] ; 0x2c
return(result);
8006ea4: 6afb ldr r3, [r7, #44] ; 0x2c
{
/* Disable the UART Parity Error Interrupt and RXFT interrupt*/
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
8006ea6: 65bb str r3, [r7, #88] ; 0x58
8006ea8: 2301 movs r3, #1
8006eaa: 633b str r3, [r7, #48] ; 0x30
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006eac: 6b3b ldr r3, [r7, #48] ; 0x30
8006eae: f383 8810 msr PRIMASK, r3
}
8006eb2: 46c0 nop ; (mov r8, r8)
8006eb4: 687b ldr r3, [r7, #4]
8006eb6: 681b ldr r3, [r3, #0]
8006eb8: 681a ldr r2, [r3, #0]
8006eba: 687b ldr r3, [r7, #4]
8006ebc: 681b ldr r3, [r3, #0]
8006ebe: 495f ldr r1, [pc, #380] ; (800703c <UART_RxISR_8BIT_FIFOEN+0x2d4>)
8006ec0: 400a ands r2, r1
8006ec2: 601a str r2, [r3, #0]
8006ec4: 6dbb ldr r3, [r7, #88] ; 0x58
8006ec6: 637b str r3, [r7, #52] ; 0x34
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006ec8: 6b7b ldr r3, [r7, #52] ; 0x34
8006eca: f383 8810 msr PRIMASK, r3
}
8006ece: 46c0 nop ; (mov r8, r8)
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8006ed0: f3ef 8310 mrs r3, PRIMASK
8006ed4: 63bb str r3, [r7, #56] ; 0x38
return(result);
8006ed6: 6bbb ldr r3, [r7, #56] ; 0x38
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error)
and RX FIFO Threshold interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
8006ed8: 657b str r3, [r7, #84] ; 0x54
8006eda: 2301 movs r3, #1
8006edc: 63fb str r3, [r7, #60] ; 0x3c
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006ede: 6bfb ldr r3, [r7, #60] ; 0x3c
8006ee0: f383 8810 msr PRIMASK, r3
}
8006ee4: 46c0 nop ; (mov r8, r8)
8006ee6: 687b ldr r3, [r7, #4]
8006ee8: 681b ldr r3, [r3, #0]
8006eea: 689a ldr r2, [r3, #8]
8006eec: 687b ldr r3, [r7, #4]
8006eee: 681b ldr r3, [r3, #0]
8006ef0: 4953 ldr r1, [pc, #332] ; (8007040 <UART_RxISR_8BIT_FIFOEN+0x2d8>)
8006ef2: 400a ands r2, r1
8006ef4: 609a str r2, [r3, #8]
8006ef6: 6d7b ldr r3, [r7, #84] ; 0x54
8006ef8: 643b str r3, [r7, #64] ; 0x40
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006efa: 6c3b ldr r3, [r7, #64] ; 0x40
8006efc: f383 8810 msr PRIMASK, r3
}
8006f00: 46c0 nop ; (mov r8, r8)
/* Rx process is completed, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
8006f02: 687b ldr r3, [r7, #4]
8006f04: 2288 movs r2, #136 ; 0x88
8006f06: 2120 movs r1, #32
8006f08: 5099 str r1, [r3, r2]
/* Clear RxISR function pointer */
huart->RxISR = NULL;
8006f0a: 687b ldr r3, [r7, #4]
8006f0c: 2200 movs r2, #0
8006f0e: 671a str r2, [r3, #112] ; 0x70
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
8006f10: 687b ldr r3, [r7, #4]
8006f12: 6edb ldr r3, [r3, #108] ; 0x6c
8006f14: 2b01 cmp r3, #1
8006f16: d12f bne.n 8006f78 <UART_RxISR_8BIT_FIFOEN+0x210>
{
/* Set reception type to Standard */
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8006f18: 687b ldr r3, [r7, #4]
8006f1a: 2200 movs r2, #0
8006f1c: 66da str r2, [r3, #108] ; 0x6c
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8006f1e: f3ef 8310 mrs r3, PRIMASK
8006f22: 623b str r3, [r7, #32]
return(result);
8006f24: 6a3b ldr r3, [r7, #32]
/* Disable IDLE interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8006f26: 653b str r3, [r7, #80] ; 0x50
8006f28: 2301 movs r3, #1
8006f2a: 627b str r3, [r7, #36] ; 0x24
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006f2c: 6a7b ldr r3, [r7, #36] ; 0x24
8006f2e: f383 8810 msr PRIMASK, r3
}
8006f32: 46c0 nop ; (mov r8, r8)
8006f34: 687b ldr r3, [r7, #4]
8006f36: 681b ldr r3, [r3, #0]
8006f38: 681a ldr r2, [r3, #0]
8006f3a: 687b ldr r3, [r7, #4]
8006f3c: 681b ldr r3, [r3, #0]
8006f3e: 2110 movs r1, #16
8006f40: 438a bics r2, r1
8006f42: 601a str r2, [r3, #0]
8006f44: 6d3b ldr r3, [r7, #80] ; 0x50
8006f46: 62bb str r3, [r7, #40] ; 0x28
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006f48: 6abb ldr r3, [r7, #40] ; 0x28
8006f4a: f383 8810 msr PRIMASK, r3
}
8006f4e: 46c0 nop ; (mov r8, r8)
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
8006f50: 687b ldr r3, [r7, #4]
8006f52: 681b ldr r3, [r3, #0]
8006f54: 69db ldr r3, [r3, #28]
8006f56: 2210 movs r2, #16
8006f58: 4013 ands r3, r2
8006f5a: 2b10 cmp r3, #16
8006f5c: d103 bne.n 8006f66 <UART_RxISR_8BIT_FIFOEN+0x1fe>
{
/* Clear IDLE Flag */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
8006f5e: 687b ldr r3, [r7, #4]
8006f60: 681b ldr r3, [r3, #0]
8006f62: 2210 movs r2, #16
8006f64: 621a str r2, [r3, #32]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize);
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
8006f66: 687b ldr r3, [r7, #4]
8006f68: 225c movs r2, #92 ; 0x5c
8006f6a: 5a9a ldrh r2, [r3, r2]
8006f6c: 687b ldr r3, [r7, #4]
8006f6e: 0011 movs r1, r2
8006f70: 0018 movs r0, r3
8006f72: f7fe fe8f bl 8005c94 <HAL_UARTEx_RxEventCallback>
8006f76: e003 b.n 8006f80 <UART_RxISR_8BIT_FIFOEN+0x218>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx complete callback*/
huart->RxCpltCallback(huart);
#else
/*Call legacy weak Rx complete callback*/
HAL_UART_RxCpltCallback(huart);
8006f78: 687b ldr r3, [r7, #4]
8006f7a: 0018 movs r0, r3
8006f7c: f7fa fa52 bl 8001424 <HAL_UART_RxCpltCallback>
while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
8006f80: 235e movs r3, #94 ; 0x5e
8006f82: 18fb adds r3, r7, r3
8006f84: 881b ldrh r3, [r3, #0]
8006f86: 2b00 cmp r3, #0
8006f88: d004 beq.n 8006f94 <UART_RxISR_8BIT_FIFOEN+0x22c>
8006f8a: 6efb ldr r3, [r7, #108] ; 0x6c
8006f8c: 2220 movs r2, #32
8006f8e: 4013 ands r3, r2
8006f90: d000 beq.n 8006f94 <UART_RxISR_8BIT_FIFOEN+0x22c>
8006f92: e70c b.n 8006dae <UART_RxISR_8BIT_FIFOEN+0x46>
/* When remaining number of bytes to receive is less than the RX FIFO
threshold, next incoming frames are processed as if FIFO mode was
disabled (i.e. one interrupt per received frame).
*/
rxdatacount = huart->RxXferCount;
8006f94: 204e movs r0, #78 ; 0x4e
8006f96: 183b adds r3, r7, r0
8006f98: 687a ldr r2, [r7, #4]
8006f9a: 215e movs r1, #94 ; 0x5e
8006f9c: 5a52 ldrh r2, [r2, r1]
8006f9e: 801a strh r2, [r3, #0]
if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
8006fa0: 0001 movs r1, r0
8006fa2: 187b adds r3, r7, r1
8006fa4: 881b ldrh r3, [r3, #0]
8006fa6: 2b00 cmp r3, #0
8006fa8: d044 beq.n 8007034 <UART_RxISR_8BIT_FIFOEN+0x2cc>
8006faa: 687b ldr r3, [r7, #4]
8006fac: 2268 movs r2, #104 ; 0x68
8006fae: 5a9b ldrh r3, [r3, r2]
8006fb0: 187a adds r2, r7, r1
8006fb2: 8812 ldrh r2, [r2, #0]
8006fb4: 429a cmp r2, r3
8006fb6: d23d bcs.n 8007034 <UART_RxISR_8BIT_FIFOEN+0x2cc>
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8006fb8: f3ef 8310 mrs r3, PRIMASK
8006fbc: 60bb str r3, [r7, #8]
return(result);
8006fbe: 68bb ldr r3, [r7, #8]
{
/* Disable the UART RXFT interrupt*/
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
8006fc0: 64bb str r3, [r7, #72] ; 0x48
8006fc2: 2301 movs r3, #1
8006fc4: 60fb str r3, [r7, #12]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006fc6: 68fb ldr r3, [r7, #12]
8006fc8: f383 8810 msr PRIMASK, r3
}
8006fcc: 46c0 nop ; (mov r8, r8)
8006fce: 687b ldr r3, [r7, #4]
8006fd0: 681b ldr r3, [r3, #0]
8006fd2: 689a ldr r2, [r3, #8]
8006fd4: 687b ldr r3, [r7, #4]
8006fd6: 681b ldr r3, [r3, #0]
8006fd8: 491a ldr r1, [pc, #104] ; (8007044 <UART_RxISR_8BIT_FIFOEN+0x2dc>)
8006fda: 400a ands r2, r1
8006fdc: 609a str r2, [r3, #8]
8006fde: 6cbb ldr r3, [r7, #72] ; 0x48
8006fe0: 613b str r3, [r7, #16]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006fe2: 693b ldr r3, [r7, #16]
8006fe4: f383 8810 msr PRIMASK, r3
}
8006fe8: 46c0 nop ; (mov r8, r8)
/* Update the RxISR function pointer */
huart->RxISR = UART_RxISR_8BIT;
8006fea: 687b ldr r3, [r7, #4]
8006fec: 4a16 ldr r2, [pc, #88] ; (8007048 <UART_RxISR_8BIT_FIFOEN+0x2e0>)
8006fee: 671a str r2, [r3, #112] ; 0x70
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8006ff0: f3ef 8310 mrs r3, PRIMASK
8006ff4: 617b str r3, [r7, #20]
return(result);
8006ff6: 697b ldr r3, [r7, #20]
/* Enable the UART Data Register Not Empty interrupt */
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
8006ff8: 647b str r3, [r7, #68] ; 0x44
8006ffa: 2301 movs r3, #1
8006ffc: 61bb str r3, [r7, #24]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8006ffe: 69bb ldr r3, [r7, #24]
8007000: f383 8810 msr PRIMASK, r3
}
8007004: 46c0 nop ; (mov r8, r8)
8007006: 687b ldr r3, [r7, #4]
8007008: 681b ldr r3, [r3, #0]
800700a: 681a ldr r2, [r3, #0]
800700c: 687b ldr r3, [r7, #4]
800700e: 681b ldr r3, [r3, #0]
8007010: 2120 movs r1, #32
8007012: 430a orrs r2, r1
8007014: 601a str r2, [r3, #0]
8007016: 6c7b ldr r3, [r7, #68] ; 0x44
8007018: 61fb str r3, [r7, #28]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
800701a: 69fb ldr r3, [r7, #28]
800701c: f383 8810 msr PRIMASK, r3
}
8007020: 46c0 nop ; (mov r8, r8)
else
{
/* Clear RXNE interrupt flag */
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
}
}
8007022: e007 b.n 8007034 <UART_RxISR_8BIT_FIFOEN+0x2cc>
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
8007024: 687b ldr r3, [r7, #4]
8007026: 681b ldr r3, [r3, #0]
8007028: 699a ldr r2, [r3, #24]
800702a: 687b ldr r3, [r7, #4]
800702c: 681b ldr r3, [r3, #0]
800702e: 2108 movs r1, #8
8007030: 430a orrs r2, r1
8007032: 619a str r2, [r3, #24]
}
8007034: 46c0 nop ; (mov r8, r8)
8007036: 46bd mov sp, r7
8007038: b01c add sp, #112 ; 0x70
800703a: bd80 pop {r7, pc}
800703c: fffffeff .word 0xfffffeff
8007040: effffffe .word 0xeffffffe
8007044: efffffff .word 0xefffffff
8007048: 08006a91 .word 0x08006a91
0800704c <UART_RxISR_16BIT_FIFOEN>:
* interruptions have been enabled by HAL_UART_Receive_IT()
* @param huart UART handle.
* @retval None
*/
static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
{
800704c: b580 push {r7, lr}
800704e: b09e sub sp, #120 ; 0x78
8007050: af00 add r7, sp, #0
8007052: 6078 str r0, [r7, #4]
uint16_t *tmp;
uint16_t uhMask = huart->Mask;
8007054: 2372 movs r3, #114 ; 0x72
8007056: 18fb adds r3, r7, r3
8007058: 687a ldr r2, [r7, #4]
800705a: 2160 movs r1, #96 ; 0x60
800705c: 5a52 ldrh r2, [r2, r1]
800705e: 801a strh r2, [r3, #0]
uint16_t uhdata;
uint16_t nb_rx_data;
uint16_t rxdatacount;
uint32_t isrflags = READ_REG(huart->Instance->ISR);
8007060: 687b ldr r3, [r7, #4]
8007062: 681b ldr r3, [r3, #0]
8007064: 69db ldr r3, [r3, #28]
8007066: 677b str r3, [r7, #116] ; 0x74
uint32_t cr1its = READ_REG(huart->Instance->CR1);
8007068: 687b ldr r3, [r7, #4]
800706a: 681b ldr r3, [r3, #0]
800706c: 681b ldr r3, [r3, #0]
800706e: 66fb str r3, [r7, #108] ; 0x6c
uint32_t cr3its = READ_REG(huart->Instance->CR3);
8007070: 687b ldr r3, [r7, #4]
8007072: 681b ldr r3, [r3, #0]
8007074: 689b ldr r3, [r3, #8]
8007076: 66bb str r3, [r7, #104] ; 0x68
/* Check that a Rx process is ongoing */
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
8007078: 687b ldr r3, [r7, #4]
800707a: 2288 movs r2, #136 ; 0x88
800707c: 589b ldr r3, [r3, r2]
800707e: 2b22 cmp r3, #34 ; 0x22
8007080: d000 beq.n 8007084 <UART_RxISR_16BIT_FIFOEN+0x38>
8007082: e141 b.n 8007308 <UART_RxISR_16BIT_FIFOEN+0x2bc>
{
nb_rx_data = huart->NbRxDataToProcess;
8007084: 2366 movs r3, #102 ; 0x66
8007086: 18fb adds r3, r7, r3
8007088: 687a ldr r2, [r7, #4]
800708a: 2168 movs r1, #104 ; 0x68
800708c: 5a52 ldrh r2, [r2, r1]
800708e: 801a strh r2, [r3, #0]
while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
8007090: e0e8 b.n 8007264 <UART_RxISR_16BIT_FIFOEN+0x218>
{
uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
8007092: 687b ldr r3, [r7, #4]
8007094: 681b ldr r3, [r3, #0]
8007096: 6a5a ldr r2, [r3, #36] ; 0x24
8007098: 2164 movs r1, #100 ; 0x64
800709a: 187b adds r3, r7, r1
800709c: 801a strh r2, [r3, #0]
tmp = (uint16_t *) huart->pRxBuffPtr ;
800709e: 687b ldr r3, [r7, #4]
80070a0: 6d9b ldr r3, [r3, #88] ; 0x58
80070a2: 663b str r3, [r7, #96] ; 0x60
*tmp = (uint16_t)(uhdata & uhMask);
80070a4: 187b adds r3, r7, r1
80070a6: 2272 movs r2, #114 ; 0x72
80070a8: 18ba adds r2, r7, r2
80070aa: 881b ldrh r3, [r3, #0]
80070ac: 8812 ldrh r2, [r2, #0]
80070ae: 4013 ands r3, r2
80070b0: b29a uxth r2, r3
80070b2: 6e3b ldr r3, [r7, #96] ; 0x60
80070b4: 801a strh r2, [r3, #0]
huart->pRxBuffPtr += 2U;
80070b6: 687b ldr r3, [r7, #4]
80070b8: 6d9b ldr r3, [r3, #88] ; 0x58
80070ba: 1c9a adds r2, r3, #2
80070bc: 687b ldr r3, [r7, #4]
80070be: 659a str r2, [r3, #88] ; 0x58
huart->RxXferCount--;
80070c0: 687b ldr r3, [r7, #4]
80070c2: 225e movs r2, #94 ; 0x5e
80070c4: 5a9b ldrh r3, [r3, r2]
80070c6: b29b uxth r3, r3
80070c8: 3b01 subs r3, #1
80070ca: b299 uxth r1, r3
80070cc: 687b ldr r3, [r7, #4]
80070ce: 225e movs r2, #94 ; 0x5e
80070d0: 5299 strh r1, [r3, r2]
isrflags = READ_REG(huart->Instance->ISR);
80070d2: 687b ldr r3, [r7, #4]
80070d4: 681b ldr r3, [r3, #0]
80070d6: 69db ldr r3, [r3, #28]
80070d8: 677b str r3, [r7, #116] ; 0x74
/* If some non blocking errors occurred */
if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U)
80070da: 6f7b ldr r3, [r7, #116] ; 0x74
80070dc: 2207 movs r2, #7
80070de: 4013 ands r3, r2
80070e0: d049 beq.n 8007176 <UART_RxISR_16BIT_FIFOEN+0x12a>
{
/* UART parity error interrupt occurred -------------------------------------*/
if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
80070e2: 6f7b ldr r3, [r7, #116] ; 0x74
80070e4: 2201 movs r2, #1
80070e6: 4013 ands r3, r2
80070e8: d010 beq.n 800710c <UART_RxISR_16BIT_FIFOEN+0xc0>
80070ea: 6efa ldr r2, [r7, #108] ; 0x6c
80070ec: 2380 movs r3, #128 ; 0x80
80070ee: 005b lsls r3, r3, #1
80070f0: 4013 ands r3, r2
80070f2: d00b beq.n 800710c <UART_RxISR_16BIT_FIFOEN+0xc0>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
80070f4: 687b ldr r3, [r7, #4]
80070f6: 681b ldr r3, [r3, #0]
80070f8: 2201 movs r2, #1
80070fa: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_PE;
80070fc: 687b ldr r3, [r7, #4]
80070fe: 228c movs r2, #140 ; 0x8c
8007100: 589b ldr r3, [r3, r2]
8007102: 2201 movs r2, #1
8007104: 431a orrs r2, r3
8007106: 687b ldr r3, [r7, #4]
8007108: 218c movs r1, #140 ; 0x8c
800710a: 505a str r2, [r3, r1]
}
/* UART frame error interrupt occurred --------------------------------------*/
if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
800710c: 6f7b ldr r3, [r7, #116] ; 0x74
800710e: 2202 movs r2, #2
8007110: 4013 ands r3, r2
8007112: d00f beq.n 8007134 <UART_RxISR_16BIT_FIFOEN+0xe8>
8007114: 6ebb ldr r3, [r7, #104] ; 0x68
8007116: 2201 movs r2, #1
8007118: 4013 ands r3, r2
800711a: d00b beq.n 8007134 <UART_RxISR_16BIT_FIFOEN+0xe8>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
800711c: 687b ldr r3, [r7, #4]
800711e: 681b ldr r3, [r3, #0]
8007120: 2202 movs r2, #2
8007122: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_FE;
8007124: 687b ldr r3, [r7, #4]
8007126: 228c movs r2, #140 ; 0x8c
8007128: 589b ldr r3, [r3, r2]
800712a: 2204 movs r2, #4
800712c: 431a orrs r2, r3
800712e: 687b ldr r3, [r7, #4]
8007130: 218c movs r1, #140 ; 0x8c
8007132: 505a str r2, [r3, r1]
}
/* UART noise error interrupt occurred --------------------------------------*/
if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
8007134: 6f7b ldr r3, [r7, #116] ; 0x74
8007136: 2204 movs r2, #4
8007138: 4013 ands r3, r2
800713a: d00f beq.n 800715c <UART_RxISR_16BIT_FIFOEN+0x110>
800713c: 6ebb ldr r3, [r7, #104] ; 0x68
800713e: 2201 movs r2, #1
8007140: 4013 ands r3, r2
8007142: d00b beq.n 800715c <UART_RxISR_16BIT_FIFOEN+0x110>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
8007144: 687b ldr r3, [r7, #4]
8007146: 681b ldr r3, [r3, #0]
8007148: 2204 movs r2, #4
800714a: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_NE;
800714c: 687b ldr r3, [r7, #4]
800714e: 228c movs r2, #140 ; 0x8c
8007150: 589b ldr r3, [r3, r2]
8007152: 2202 movs r2, #2
8007154: 431a orrs r2, r3
8007156: 687b ldr r3, [r7, #4]
8007158: 218c movs r1, #140 ; 0x8c
800715a: 505a str r2, [r3, r1]
}
/* Call UART Error Call back function if need be ----------------------------*/
if (huart->ErrorCode != HAL_UART_ERROR_NONE)
800715c: 687b ldr r3, [r7, #4]
800715e: 228c movs r2, #140 ; 0x8c
8007160: 589b ldr r3, [r3, r2]
8007162: 2b00 cmp r3, #0
8007164: d007 beq.n 8007176 <UART_RxISR_16BIT_FIFOEN+0x12a>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
8007166: 687b ldr r3, [r7, #4]
8007168: 0018 movs r0, r3
800716a: f7fa f9ab bl 80014c4 <HAL_UART_ErrorCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
huart->ErrorCode = HAL_UART_ERROR_NONE;
800716e: 687b ldr r3, [r7, #4]
8007170: 228c movs r2, #140 ; 0x8c
8007172: 2100 movs r1, #0
8007174: 5099 str r1, [r3, r2]
}
}
if (huart->RxXferCount == 0U)
8007176: 687b ldr r3, [r7, #4]
8007178: 225e movs r2, #94 ; 0x5e
800717a: 5a9b ldrh r3, [r3, r2]
800717c: b29b uxth r3, r3
800717e: 2b00 cmp r3, #0
8007180: d170 bne.n 8007264 <UART_RxISR_16BIT_FIFOEN+0x218>
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8007182: f3ef 8310 mrs r3, PRIMASK
8007186: 633b str r3, [r7, #48] ; 0x30
return(result);
8007188: 6b3b ldr r3, [r7, #48] ; 0x30
{
/* Disable the UART Parity Error Interrupt and RXFT interrupt*/
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
800718a: 65fb str r3, [r7, #92] ; 0x5c
800718c: 2301 movs r3, #1
800718e: 637b str r3, [r7, #52] ; 0x34
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8007190: 6b7b ldr r3, [r7, #52] ; 0x34
8007192: f383 8810 msr PRIMASK, r3
}
8007196: 46c0 nop ; (mov r8, r8)
8007198: 687b ldr r3, [r7, #4]
800719a: 681b ldr r3, [r3, #0]
800719c: 681a ldr r2, [r3, #0]
800719e: 687b ldr r3, [r7, #4]
80071a0: 681b ldr r3, [r3, #0]
80071a2: 495f ldr r1, [pc, #380] ; (8007320 <UART_RxISR_16BIT_FIFOEN+0x2d4>)
80071a4: 400a ands r2, r1
80071a6: 601a str r2, [r3, #0]
80071a8: 6dfb ldr r3, [r7, #92] ; 0x5c
80071aa: 63bb str r3, [r7, #56] ; 0x38
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80071ac: 6bbb ldr r3, [r7, #56] ; 0x38
80071ae: f383 8810 msr PRIMASK, r3
}
80071b2: 46c0 nop ; (mov r8, r8)
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
80071b4: f3ef 8310 mrs r3, PRIMASK
80071b8: 63fb str r3, [r7, #60] ; 0x3c
return(result);
80071ba: 6bfb ldr r3, [r7, #60] ; 0x3c
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error)
and RX FIFO Threshold interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
80071bc: 65bb str r3, [r7, #88] ; 0x58
80071be: 2301 movs r3, #1
80071c0: 643b str r3, [r7, #64] ; 0x40
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80071c2: 6c3b ldr r3, [r7, #64] ; 0x40
80071c4: f383 8810 msr PRIMASK, r3
}
80071c8: 46c0 nop ; (mov r8, r8)
80071ca: 687b ldr r3, [r7, #4]
80071cc: 681b ldr r3, [r3, #0]
80071ce: 689a ldr r2, [r3, #8]
80071d0: 687b ldr r3, [r7, #4]
80071d2: 681b ldr r3, [r3, #0]
80071d4: 4953 ldr r1, [pc, #332] ; (8007324 <UART_RxISR_16BIT_FIFOEN+0x2d8>)
80071d6: 400a ands r2, r1
80071d8: 609a str r2, [r3, #8]
80071da: 6dbb ldr r3, [r7, #88] ; 0x58
80071dc: 647b str r3, [r7, #68] ; 0x44
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80071de: 6c7b ldr r3, [r7, #68] ; 0x44
80071e0: f383 8810 msr PRIMASK, r3
}
80071e4: 46c0 nop ; (mov r8, r8)
/* Rx process is completed, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
80071e6: 687b ldr r3, [r7, #4]
80071e8: 2288 movs r2, #136 ; 0x88
80071ea: 2120 movs r1, #32
80071ec: 5099 str r1, [r3, r2]
/* Clear RxISR function pointer */
huart->RxISR = NULL;
80071ee: 687b ldr r3, [r7, #4]
80071f0: 2200 movs r2, #0
80071f2: 671a str r2, [r3, #112] ; 0x70
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
80071f4: 687b ldr r3, [r7, #4]
80071f6: 6edb ldr r3, [r3, #108] ; 0x6c
80071f8: 2b01 cmp r3, #1
80071fa: d12f bne.n 800725c <UART_RxISR_16BIT_FIFOEN+0x210>
{
/* Set reception type to Standard */
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
80071fc: 687b ldr r3, [r7, #4]
80071fe: 2200 movs r2, #0
8007200: 66da str r2, [r3, #108] ; 0x6c
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8007202: f3ef 8310 mrs r3, PRIMASK
8007206: 627b str r3, [r7, #36] ; 0x24
return(result);
8007208: 6a7b ldr r3, [r7, #36] ; 0x24
/* Disable IDLE interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
800720a: 657b str r3, [r7, #84] ; 0x54
800720c: 2301 movs r3, #1
800720e: 62bb str r3, [r7, #40] ; 0x28
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8007210: 6abb ldr r3, [r7, #40] ; 0x28
8007212: f383 8810 msr PRIMASK, r3
}
8007216: 46c0 nop ; (mov r8, r8)
8007218: 687b ldr r3, [r7, #4]
800721a: 681b ldr r3, [r3, #0]
800721c: 681a ldr r2, [r3, #0]
800721e: 687b ldr r3, [r7, #4]
8007220: 681b ldr r3, [r3, #0]
8007222: 2110 movs r1, #16
8007224: 438a bics r2, r1
8007226: 601a str r2, [r3, #0]
8007228: 6d7b ldr r3, [r7, #84] ; 0x54
800722a: 62fb str r3, [r7, #44] ; 0x2c
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
800722c: 6afb ldr r3, [r7, #44] ; 0x2c
800722e: f383 8810 msr PRIMASK, r3
}
8007232: 46c0 nop ; (mov r8, r8)
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
8007234: 687b ldr r3, [r7, #4]
8007236: 681b ldr r3, [r3, #0]
8007238: 69db ldr r3, [r3, #28]
800723a: 2210 movs r2, #16
800723c: 4013 ands r3, r2
800723e: 2b10 cmp r3, #16
8007240: d103 bne.n 800724a <UART_RxISR_16BIT_FIFOEN+0x1fe>
{
/* Clear IDLE Flag */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
8007242: 687b ldr r3, [r7, #4]
8007244: 681b ldr r3, [r3, #0]
8007246: 2210 movs r2, #16
8007248: 621a str r2, [r3, #32]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize);
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
800724a: 687b ldr r3, [r7, #4]
800724c: 225c movs r2, #92 ; 0x5c
800724e: 5a9a ldrh r2, [r3, r2]
8007250: 687b ldr r3, [r7, #4]
8007252: 0011 movs r1, r2
8007254: 0018 movs r0, r3
8007256: f7fe fd1d bl 8005c94 <HAL_UARTEx_RxEventCallback>
800725a: e003 b.n 8007264 <UART_RxISR_16BIT_FIFOEN+0x218>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx complete callback*/
huart->RxCpltCallback(huart);
#else
/*Call legacy weak Rx complete callback*/
HAL_UART_RxCpltCallback(huart);
800725c: 687b ldr r3, [r7, #4]
800725e: 0018 movs r0, r3
8007260: f7fa f8e0 bl 8001424 <HAL_UART_RxCpltCallback>
while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
8007264: 2366 movs r3, #102 ; 0x66
8007266: 18fb adds r3, r7, r3
8007268: 881b ldrh r3, [r3, #0]
800726a: 2b00 cmp r3, #0
800726c: d004 beq.n 8007278 <UART_RxISR_16BIT_FIFOEN+0x22c>
800726e: 6f7b ldr r3, [r7, #116] ; 0x74
8007270: 2220 movs r2, #32
8007272: 4013 ands r3, r2
8007274: d000 beq.n 8007278 <UART_RxISR_16BIT_FIFOEN+0x22c>
8007276: e70c b.n 8007092 <UART_RxISR_16BIT_FIFOEN+0x46>
/* When remaining number of bytes to receive is less than the RX FIFO
threshold, next incoming frames are processed as if FIFO mode was
disabled (i.e. one interrupt per received frame).
*/
rxdatacount = huart->RxXferCount;
8007278: 2052 movs r0, #82 ; 0x52
800727a: 183b adds r3, r7, r0
800727c: 687a ldr r2, [r7, #4]
800727e: 215e movs r1, #94 ; 0x5e
8007280: 5a52 ldrh r2, [r2, r1]
8007282: 801a strh r2, [r3, #0]
if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
8007284: 0001 movs r1, r0
8007286: 187b adds r3, r7, r1
8007288: 881b ldrh r3, [r3, #0]
800728a: 2b00 cmp r3, #0
800728c: d044 beq.n 8007318 <UART_RxISR_16BIT_FIFOEN+0x2cc>
800728e: 687b ldr r3, [r7, #4]
8007290: 2268 movs r2, #104 ; 0x68
8007292: 5a9b ldrh r3, [r3, r2]
8007294: 187a adds r2, r7, r1
8007296: 8812 ldrh r2, [r2, #0]
8007298: 429a cmp r2, r3
800729a: d23d bcs.n 8007318 <UART_RxISR_16BIT_FIFOEN+0x2cc>
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
800729c: f3ef 8310 mrs r3, PRIMASK
80072a0: 60fb str r3, [r7, #12]
return(result);
80072a2: 68fb ldr r3, [r7, #12]
{
/* Disable the UART RXFT interrupt*/
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
80072a4: 64fb str r3, [r7, #76] ; 0x4c
80072a6: 2301 movs r3, #1
80072a8: 613b str r3, [r7, #16]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80072aa: 693b ldr r3, [r7, #16]
80072ac: f383 8810 msr PRIMASK, r3
}
80072b0: 46c0 nop ; (mov r8, r8)
80072b2: 687b ldr r3, [r7, #4]
80072b4: 681b ldr r3, [r3, #0]
80072b6: 689a ldr r2, [r3, #8]
80072b8: 687b ldr r3, [r7, #4]
80072ba: 681b ldr r3, [r3, #0]
80072bc: 491a ldr r1, [pc, #104] ; (8007328 <UART_RxISR_16BIT_FIFOEN+0x2dc>)
80072be: 400a ands r2, r1
80072c0: 609a str r2, [r3, #8]
80072c2: 6cfb ldr r3, [r7, #76] ; 0x4c
80072c4: 617b str r3, [r7, #20]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80072c6: 697b ldr r3, [r7, #20]
80072c8: f383 8810 msr PRIMASK, r3
}
80072cc: 46c0 nop ; (mov r8, r8)
/* Update the RxISR function pointer */
huart->RxISR = UART_RxISR_16BIT;
80072ce: 687b ldr r3, [r7, #4]
80072d0: 4a16 ldr r2, [pc, #88] ; (800732c <UART_RxISR_16BIT_FIFOEN+0x2e0>)
80072d2: 671a str r2, [r3, #112] ; 0x70
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
80072d4: f3ef 8310 mrs r3, PRIMASK
80072d8: 61bb str r3, [r7, #24]
return(result);
80072da: 69bb ldr r3, [r7, #24]
/* Enable the UART Data Register Not Empty interrupt */
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
80072dc: 64bb str r3, [r7, #72] ; 0x48
80072de: 2301 movs r3, #1
80072e0: 61fb str r3, [r7, #28]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80072e2: 69fb ldr r3, [r7, #28]
80072e4: f383 8810 msr PRIMASK, r3
}
80072e8: 46c0 nop ; (mov r8, r8)
80072ea: 687b ldr r3, [r7, #4]
80072ec: 681b ldr r3, [r3, #0]
80072ee: 681a ldr r2, [r3, #0]
80072f0: 687b ldr r3, [r7, #4]
80072f2: 681b ldr r3, [r3, #0]
80072f4: 2120 movs r1, #32
80072f6: 430a orrs r2, r1
80072f8: 601a str r2, [r3, #0]
80072fa: 6cbb ldr r3, [r7, #72] ; 0x48
80072fc: 623b str r3, [r7, #32]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80072fe: 6a3b ldr r3, [r7, #32]
8007300: f383 8810 msr PRIMASK, r3
}
8007304: 46c0 nop ; (mov r8, r8)
else
{
/* Clear RXNE interrupt flag */
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
}
}
8007306: e007 b.n 8007318 <UART_RxISR_16BIT_FIFOEN+0x2cc>
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
8007308: 687b ldr r3, [r7, #4]
800730a: 681b ldr r3, [r3, #0]
800730c: 699a ldr r2, [r3, #24]
800730e: 687b ldr r3, [r7, #4]
8007310: 681b ldr r3, [r3, #0]
8007312: 2108 movs r1, #8
8007314: 430a orrs r2, r1
8007316: 619a str r2, [r3, #24]
}
8007318: 46c0 nop ; (mov r8, r8)
800731a: 46bd mov sp, r7
800731c: b01e add sp, #120 ; 0x78
800731e: bd80 pop {r7, pc}
8007320: fffffeff .word 0xfffffeff
8007324: effffffe .word 0xeffffffe
8007328: efffffff .word 0xefffffff
800732c: 08006bfd .word 0x08006bfd
08007330 <HAL_UARTEx_WakeupCallback>:
* @brief UART wakeup from Stop mode callback.
* @param huart UART handle.
* @retval None
*/
__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
{
8007330: b580 push {r7, lr}
8007332: b082 sub sp, #8
8007334: af00 add r7, sp, #0
8007336: 6078 str r0, [r7, #4]
UNUSED(huart);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_UARTEx_WakeupCallback can be implemented in the user file.
*/
}
8007338: 46c0 nop ; (mov r8, r8)
800733a: 46bd mov sp, r7
800733c: b002 add sp, #8
800733e: bd80 pop {r7, pc}
08007340 <HAL_UARTEx_RxFifoFullCallback>:
* @brief UART RX Fifo full callback.
* @param huart UART handle.
* @retval None
*/
__weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart)
{
8007340: b580 push {r7, lr}
8007342: b082 sub sp, #8
8007344: af00 add r7, sp, #0
8007346: 6078 str r0, [r7, #4]
UNUSED(huart);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file.
*/
}
8007348: 46c0 nop ; (mov r8, r8)
800734a: 46bd mov sp, r7
800734c: b002 add sp, #8
800734e: bd80 pop {r7, pc}
08007350 <HAL_UARTEx_TxFifoEmptyCallback>:
* @brief UART TX Fifo empty callback.
* @param huart UART handle.
* @retval None
*/
__weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart)
{
8007350: b580 push {r7, lr}
8007352: b082 sub sp, #8
8007354: af00 add r7, sp, #0
8007356: 6078 str r0, [r7, #4]
UNUSED(huart);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file.
*/
}
8007358: 46c0 nop ; (mov r8, r8)
800735a: 46bd mov sp, r7
800735c: b002 add sp, #8
800735e: bd80 pop {r7, pc}
08007360 <__libc_init_array>:
8007360: b570 push {r4, r5, r6, lr}
8007362: 2600 movs r6, #0
8007364: 4d0c ldr r5, [pc, #48] ; (8007398 <__libc_init_array+0x38>)
8007366: 4c0d ldr r4, [pc, #52] ; (800739c <__libc_init_array+0x3c>)
8007368: 1b64 subs r4, r4, r5
800736a: 10a4 asrs r4, r4, #2
800736c: 42a6 cmp r6, r4
800736e: d109 bne.n 8007384 <__libc_init_array+0x24>
8007370: 2600 movs r6, #0
8007372: f000 f821 bl 80073b8 <_init>
8007376: 4d0a ldr r5, [pc, #40] ; (80073a0 <__libc_init_array+0x40>)
8007378: 4c0a ldr r4, [pc, #40] ; (80073a4 <__libc_init_array+0x44>)
800737a: 1b64 subs r4, r4, r5
800737c: 10a4 asrs r4, r4, #2
800737e: 42a6 cmp r6, r4
8007380: d105 bne.n 800738e <__libc_init_array+0x2e>
8007382: bd70 pop {r4, r5, r6, pc}
8007384: 00b3 lsls r3, r6, #2
8007386: 58eb ldr r3, [r5, r3]
8007388: 4798 blx r3
800738a: 3601 adds r6, #1
800738c: e7ee b.n 800736c <__libc_init_array+0xc>
800738e: 00b3 lsls r3, r6, #2
8007390: 58eb ldr r3, [r5, r3]
8007392: 4798 blx r3
8007394: 3601 adds r6, #1
8007396: e7f2 b.n 800737e <__libc_init_array+0x1e>
8007398: 080074a4 .word 0x080074a4
800739c: 080074a4 .word 0x080074a4
80073a0: 080074a4 .word 0x080074a4
80073a4: 080074a8 .word 0x080074a8
080073a8 <memset>:
80073a8: 0003 movs r3, r0
80073aa: 1882 adds r2, r0, r2
80073ac: 4293 cmp r3, r2
80073ae: d100 bne.n 80073b2 <memset+0xa>
80073b0: 4770 bx lr
80073b2: 7019 strb r1, [r3, #0]
80073b4: 3301 adds r3, #1
80073b6: e7f9 b.n 80073ac <memset+0x4>
080073b8 <_init>:
80073b8: b5f8 push {r3, r4, r5, r6, r7, lr}
80073ba: 46c0 nop ; (mov r8, r8)
80073bc: bcf8 pop {r3, r4, r5, r6, r7}
80073be: bc08 pop {r3}
80073c0: 469e mov lr, r3
80073c2: 4770 bx lr
080073c4 <_fini>:
80073c4: b5f8 push {r3, r4, r5, r6, r7, lr}
80073c6: 46c0 nop ; (mov r8, r8)
80073c8: bcf8 pop {r3, r4, r5, r6, r7}
80073ca: bc08 pop {r3}
80073cc: 469e mov lr, r3
80073ce: 4770 bx lr