freeRTOS下单字节中断接收性能不好，改为DMA+idlle方式

CMakePresets.json

@@ -30,6 +30,7 @@
         "MEM_POOL_TOTAL_SIZE": "46*1024",
         "IOC_100PIN": true,
         "USE_UART": true,
+        "CONFIG_UART_IT_IDLEDMA": true,
         "BUILD_RBCORE": "ON",
         "USE_CAN": true
       }

Core/Inc/stm32h7xx_it.h

@@ -56,6 +56,7 @@ void DMA1_Stream0_IRQHandler(void);
 void DMA1_Stream1_IRQHandler(void);
 void DMA1_Stream2_IRQHandler(void);
 void DMA1_Stream3_IRQHandler(void);
+void DMA1_Stream4_IRQHandler(void);
 void DMA1_Stream5_IRQHandler(void);
 void DMA1_Stream6_IRQHandler(void);
 void FDCAN1_IT0_IRQHandler(void);
@@ -69,8 +70,14 @@ void TIM8_UP_TIM13_IRQHandler(void);
 void DMA1_Stream7_IRQHandler(void);
 void UART4_IRQHandler(void);
 void UART5_IRQHandler(void);
+void DMA2_Stream0_IRQHandler(void);
+void DMA2_Stream1_IRQHandler(void);
+void DMA2_Stream2_IRQHandler(void);
+void DMA2_Stream3_IRQHandler(void);
+void DMA2_Stream4_IRQHandler(void);
 void ETH_IRQHandler(void);
 void ETH_WKUP_IRQHandler(void);
+void DMA2_Stream5_IRQHandler(void);
 void USART6_IRQHandler(void);
 void UART7_IRQHandler(void);
 void I2C4_EV_IRQHandler(void);

Core/Src/dma.c

@@ -41,6 +41,7 @@ void MX_DMA_Init(void)
 
   /* DMA controller clock enable */
   __HAL_RCC_DMA1_CLK_ENABLE();
+  __HAL_RCC_DMA2_CLK_ENABLE();
 
   /* DMA interrupt init */
   /* DMA1_Stream0_IRQn interrupt configuration */
@@ -55,6 +56,9 @@ void MX_DMA_Init(void)
   /* DMA1_Stream3_IRQn interrupt configuration */
   HAL_NVIC_SetPriority(DMA1_Stream3_IRQn, 5, 0);
   HAL_NVIC_EnableIRQ(DMA1_Stream3_IRQn);
+  /* DMA1_Stream4_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Stream4_IRQn, 5, 0);
+  HAL_NVIC_EnableIRQ(DMA1_Stream4_IRQn);
   /* DMA1_Stream5_IRQn interrupt configuration */
   HAL_NVIC_SetPriority(DMA1_Stream5_IRQn, 5, 0);
   HAL_NVIC_EnableIRQ(DMA1_Stream5_IRQn);
@@ -64,6 +68,24 @@ void MX_DMA_Init(void)
   /* DMA1_Stream7_IRQn interrupt configuration */
   HAL_NVIC_SetPriority(DMA1_Stream7_IRQn, 5, 0);
   HAL_NVIC_EnableIRQ(DMA1_Stream7_IRQn);
+  /* DMA2_Stream0_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA2_Stream0_IRQn, 5, 0);
+  HAL_NVIC_EnableIRQ(DMA2_Stream0_IRQn);
+  /* DMA2_Stream1_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA2_Stream1_IRQn, 5, 0);
+  HAL_NVIC_EnableIRQ(DMA2_Stream1_IRQn);
+  /* DMA2_Stream2_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA2_Stream2_IRQn, 5, 0);
+  HAL_NVIC_EnableIRQ(DMA2_Stream2_IRQn);
+  /* DMA2_Stream3_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA2_Stream3_IRQn, 5, 0);
+  HAL_NVIC_EnableIRQ(DMA2_Stream3_IRQn);
+  /* DMA2_Stream4_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA2_Stream4_IRQn, 5, 0);
+  HAL_NVIC_EnableIRQ(DMA2_Stream4_IRQn);
+  /* DMA2_Stream5_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA2_Stream5_IRQn, 5, 0);
+  HAL_NVIC_EnableIRQ(DMA2_Stream5_IRQn);
 
 }
 

Core/Src/stm32h7xx_it.c

@@ -22,6 +22,7 @@
 #include "stm32h7xx_it.h"
 /* Private includes ----------------------------------------------------------*/
 /* USER CODE BEGIN Includes */
+#include "drv_interface.h"
 /* USER CODE END Includes */
 
 /* Private typedef -----------------------------------------------------------*/
@@ -60,12 +61,19 @@ extern FDCAN_HandleTypeDef hfdcan1;
 extern FDCAN_HandleTypeDef hfdcan2;
 extern I2C_HandleTypeDef hi2c4;
 extern DMA_HandleTypeDef hdma_uart4_tx;
+extern DMA_HandleTypeDef hdma_uart4_rx;
 extern DMA_HandleTypeDef hdma_uart5_tx;
+extern DMA_HandleTypeDef hdma_uart5_rx;
 extern DMA_HandleTypeDef hdma_uart7_tx;
+extern DMA_HandleTypeDef hdma_uart7_rx;
 extern DMA_HandleTypeDef hdma_usart1_tx;
+extern DMA_HandleTypeDef hdma_usart1_rx;
 extern DMA_HandleTypeDef hdma_usart2_tx;
+extern DMA_HandleTypeDef hdma_usart2_rx;
 extern DMA_HandleTypeDef hdma_usart3_tx;
+extern DMA_HandleTypeDef hdma_usart3_rx;
 extern DMA_HandleTypeDef hdma_usart6_tx;
+extern DMA_HandleTypeDef hdma_usart6_rx;
 extern UART_HandleTypeDef hlpuart1;
 extern UART_HandleTypeDef huart4;
 extern UART_HandleTypeDef huart5;
@@ -79,7 +87,7 @@ extern TIM_HandleTypeDef htim8;
 extern TIM_HandleTypeDef htim3;
 
 /* USER CODE BEGIN EV */
-
+extern TComCtrl *g_ptUartCtrl;
 /* USER CODE END EV */
 
 /******************************************************************************/
@@ -237,6 +245,20 @@ void DMA1_Stream3_IRQHandler(void)
   /* USER CODE END DMA1_Stream3_IRQn 1 */
 }
 
+/**
+  * @brief This function handles DMA1 stream4 global interrupt.
+  */
+void DMA1_Stream4_IRQHandler(void)
+{
+  /* USER CODE BEGIN DMA1_Stream4_IRQn 0 */
+
+  /* USER CODE END DMA1_Stream4_IRQn 0 */
+  HAL_DMA_IRQHandler(&hdma_uart4_rx);
+  /* USER CODE BEGIN DMA1_Stream4_IRQn 1 */
+
+  /* USER CODE END DMA1_Stream4_IRQn 1 */
+}
+
 /**
   * @brief This function handles DMA1 stream5 global interrupt.
   */
@@ -327,7 +349,7 @@ void TIM3_IRQHandler(void)
 void USART1_IRQHandler(void)
 {
   /* USER CODE BEGIN USART1_IRQn 0 */
-
+  UART_DMA_RX_IRQHandler(g_ptRS485_1);
   /* USER CODE END USART1_IRQn 0 */
   HAL_UART_IRQHandler(&huart1);
   /* USER CODE BEGIN USART1_IRQn 1 */
@@ -341,7 +363,7 @@ void USART1_IRQHandler(void)
 void USART2_IRQHandler(void)
 {
   /* USER CODE BEGIN USART2_IRQn 0 */
-
+  UART_DMA_RX_IRQHandler(g_ptLTE_7S0);
   /* USER CODE END USART2_IRQn 0 */
   HAL_UART_IRQHandler(&huart2);
   /* USER CODE BEGIN USART2_IRQn 1 */
@@ -355,7 +377,11 @@ void USART2_IRQHandler(void)
 void USART3_IRQHandler(void)
 {
   /* USER CODE BEGIN USART3_IRQn 0 */
-
+#ifdef USE_PRINT
+  UART_DMA_RX_IRQHandler(g_ptUartCtrl);
+#else
+  UART_DMA_RX_IRQHandler(g_ptRS485_2);
+#endif
   /* USER CODE END USART3_IRQn 0 */
   HAL_UART_IRQHandler(&huart3);
   /* USER CODE BEGIN USART3_IRQn 1 */
@@ -397,7 +423,7 @@ void DMA1_Stream7_IRQHandler(void)
 void UART4_IRQHandler(void)
 {
   /* USER CODE BEGIN UART4_IRQn 0 */
-
+  UART_DMA_RX_IRQHandler(g_ptInterCall);
   /* USER CODE END UART4_IRQn 0 */
   HAL_UART_IRQHandler(&huart4);
   /* USER CODE BEGIN UART4_IRQn 1 */
@@ -411,7 +437,7 @@ void UART4_IRQHandler(void)
 void UART5_IRQHandler(void)
 {
   /* USER CODE BEGIN UART5_IRQn 0 */
-
+  UART_DMA_RX_IRQHandler(g_ptE28_SBUS);
   /* USER CODE END UART5_IRQn 0 */
   HAL_UART_IRQHandler(&huart5);
   /* USER CODE BEGIN UART5_IRQn 1 */
@@ -419,6 +445,76 @@ void UART5_IRQHandler(void)
   /* USER CODE END UART5_IRQn 1 */
 }
 
+/**
+  * @brief This function handles DMA2 stream0 global interrupt.
+  */
+void DMA2_Stream0_IRQHandler(void)
+{
+  /* USER CODE BEGIN DMA2_Stream0_IRQn 0 */
+
+  /* USER CODE END DMA2_Stream0_IRQn 0 */
+  HAL_DMA_IRQHandler(&hdma_uart5_rx);
+  /* USER CODE BEGIN DMA2_Stream0_IRQn 1 */
+
+  /* USER CODE END DMA2_Stream0_IRQn 1 */
+}
+
+/**
+  * @brief This function handles DMA2 stream1 global interrupt.
+  */
+void DMA2_Stream1_IRQHandler(void)
+{
+  /* USER CODE BEGIN DMA2_Stream1_IRQn 0 */
+
+  /* USER CODE END DMA2_Stream1_IRQn 0 */
+  HAL_DMA_IRQHandler(&hdma_uart7_rx);
+  /* USER CODE BEGIN DMA2_Stream1_IRQn 1 */
+
+  /* USER CODE END DMA2_Stream1_IRQn 1 */
+}
+
+/**
+  * @brief This function handles DMA2 stream2 global interrupt.
+  */
+void DMA2_Stream2_IRQHandler(void)
+{
+  /* USER CODE BEGIN DMA2_Stream2_IRQn 0 */
+
+  /* USER CODE END DMA2_Stream2_IRQn 0 */
+  HAL_DMA_IRQHandler(&hdma_usart1_rx);
+  /* USER CODE BEGIN DMA2_Stream2_IRQn 1 */
+
+  /* USER CODE END DMA2_Stream2_IRQn 1 */
+}
+
+/**
+  * @brief This function handles DMA2 stream3 global interrupt.
+  */
+void DMA2_Stream3_IRQHandler(void)
+{
+  /* USER CODE BEGIN DMA2_Stream3_IRQn 0 */
+
+  /* USER CODE END DMA2_Stream3_IRQn 0 */
+  HAL_DMA_IRQHandler(&hdma_usart2_rx);
+  /* USER CODE BEGIN DMA2_Stream3_IRQn 1 */
+
+  /* USER CODE END DMA2_Stream3_IRQn 1 */
+}
+
+/**
+  * @brief This function handles DMA2 stream4 global interrupt.
+  */
+void DMA2_Stream4_IRQHandler(void)
+{
+  /* USER CODE BEGIN DMA2_Stream4_IRQn 0 */
+
+  /* USER CODE END DMA2_Stream4_IRQn 0 */
+  HAL_DMA_IRQHandler(&hdma_usart3_rx);
+  /* USER CODE BEGIN DMA2_Stream4_IRQn 1 */
+
+  /* USER CODE END DMA2_Stream4_IRQn 1 */
+}
+
 /**
   * @brief This function handles Ethernet global interrupt.
   */
@@ -447,13 +543,27 @@ void ETH_WKUP_IRQHandler(void)
   /* USER CODE END ETH_WKUP_IRQn 1 */
 }
 
+/**
+  * @brief This function handles DMA2 stream5 global interrupt.
+  */
+void DMA2_Stream5_IRQHandler(void)
+{
+  /* USER CODE BEGIN DMA2_Stream5_IRQn 0 */
+
+  /* USER CODE END DMA2_Stream5_IRQn 0 */
+  HAL_DMA_IRQHandler(&hdma_usart6_rx);
+  /* USER CODE BEGIN DMA2_Stream5_IRQn 1 */
+
+  /* USER CODE END DMA2_Stream5_IRQn 1 */
+}
+
 /**
   * @brief This function handles USART6 global interrupt.
   */
 void USART6_IRQHandler(void)
 {
   /* USER CODE BEGIN USART6_IRQn 0 */
-
+  UART_DMA_RX_IRQHandler(g_ptRS485_3);
   /* USER CODE END USART6_IRQn 0 */
   HAL_UART_IRQHandler(&huart6);
   /* USER CODE BEGIN USART6_IRQn 1 */
@@ -467,7 +577,7 @@ void USART6_IRQHandler(void)
 void UART7_IRQHandler(void)
 {
   /* USER CODE BEGIN UART7_IRQn 0 */
-
+  UART_DMA_RX_IRQHandler(g_ptRS485_4);
   /* USER CODE END UART7_IRQn 0 */
   HAL_UART_IRQHandler(&huart7);
   /* USER CODE BEGIN UART7_IRQn 1 */

Core/Src/usart.c

@@ -33,12 +33,19 @@ UART_HandleTypeDef huart2;
 UART_HandleTypeDef huart3;
 UART_HandleTypeDef huart6;
 DMA_HandleTypeDef hdma_uart4_tx;
+DMA_HandleTypeDef hdma_uart4_rx;
 DMA_HandleTypeDef hdma_uart5_tx;
+DMA_HandleTypeDef hdma_uart5_rx;
 DMA_HandleTypeDef hdma_uart7_tx;
+DMA_HandleTypeDef hdma_uart7_rx;
 DMA_HandleTypeDef hdma_usart1_tx;
+DMA_HandleTypeDef hdma_usart1_rx;
 DMA_HandleTypeDef hdma_usart2_tx;
+DMA_HandleTypeDef hdma_usart2_rx;
 DMA_HandleTypeDef hdma_usart3_tx;
+DMA_HandleTypeDef hdma_usart3_rx;
 DMA_HandleTypeDef hdma_usart6_tx;
+DMA_HandleTypeDef hdma_usart6_rx;
 
 /* LPUART1 init function */
 
@@ -504,6 +511,24 @@ void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle)
 
     __HAL_LINKDMA(uartHandle,hdmatx,hdma_uart4_tx);
 
+    /* UART4_RX Init */
+    hdma_uart4_rx.Instance = DMA1_Stream4;
+    hdma_uart4_rx.Init.Request = DMA_REQUEST_UART4_RX;
+    hdma_uart4_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
+    hdma_uart4_rx.Init.PeriphInc = DMA_PINC_DISABLE;
+    hdma_uart4_rx.Init.MemInc = DMA_MINC_ENABLE;
+    hdma_uart4_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+    hdma_uart4_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+    hdma_uart4_rx.Init.Mode = DMA_CIRCULAR;
+    hdma_uart4_rx.Init.Priority = DMA_PRIORITY_LOW;
+    hdma_uart4_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
+    if (HAL_DMA_Init(&hdma_uart4_rx) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    __HAL_LINKDMA(uartHandle,hdmarx,hdma_uart4_rx);
+
     /* UART4 interrupt Init */
     HAL_NVIC_SetPriority(UART4_IRQn, 5, 0);
     HAL_NVIC_EnableIRQ(UART4_IRQn);
@@ -568,6 +593,24 @@ void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle)
 
     __HAL_LINKDMA(uartHandle,hdmatx,hdma_uart5_tx);
 
+    /* UART5_RX Init */
+    hdma_uart5_rx.Instance = DMA2_Stream0;
+    hdma_uart5_rx.Init.Request = DMA_REQUEST_UART5_RX;
+    hdma_uart5_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
+    hdma_uart5_rx.Init.PeriphInc = DMA_PINC_DISABLE;
+    hdma_uart5_rx.Init.MemInc = DMA_MINC_ENABLE;
+    hdma_uart5_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+    hdma_uart5_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+    hdma_uart5_rx.Init.Mode = DMA_CIRCULAR;
+    hdma_uart5_rx.Init.Priority = DMA_PRIORITY_LOW;
+    hdma_uart5_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
+    if (HAL_DMA_Init(&hdma_uart5_rx) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    __HAL_LINKDMA(uartHandle,hdmarx,hdma_uart5_rx);
+
     /* UART5 interrupt Init */
     HAL_NVIC_SetPriority(UART5_IRQn, 5, 0);
     HAL_NVIC_EnableIRQ(UART5_IRQn);
@@ -631,6 +674,24 @@ void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle)
 
     __HAL_LINKDMA(uartHandle,hdmatx,hdma_uart7_tx);
 
+    /* UART7_RX Init */
+    hdma_uart7_rx.Instance = DMA2_Stream1;
+    hdma_uart7_rx.Init.Request = DMA_REQUEST_UART7_RX;
+    hdma_uart7_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
+    hdma_uart7_rx.Init.PeriphInc = DMA_PINC_DISABLE;
+    hdma_uart7_rx.Init.MemInc = DMA_MINC_ENABLE;
+    hdma_uart7_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+    hdma_uart7_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+    hdma_uart7_rx.Init.Mode = DMA_CIRCULAR;
+    hdma_uart7_rx.Init.Priority = DMA_PRIORITY_LOW;
+    hdma_uart7_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
+    if (HAL_DMA_Init(&hdma_uart7_rx) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    __HAL_LINKDMA(uartHandle,hdmarx,hdma_uart7_rx);
+
     /* UART7 interrupt Init */
     HAL_NVIC_SetPriority(UART7_IRQn, 5, 0);
     HAL_NVIC_EnableIRQ(UART7_IRQn);
@@ -697,6 +758,24 @@ void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle)
 
     __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart1_tx);
 
+    /* USART1_RX Init */
+    hdma_usart1_rx.Instance = DMA2_Stream2;
+    hdma_usart1_rx.Init.Request = DMA_REQUEST_USART1_RX;
+    hdma_usart1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
+    hdma_usart1_rx.Init.PeriphInc = DMA_PINC_DISABLE;
+    hdma_usart1_rx.Init.MemInc = DMA_MINC_ENABLE;
+    hdma_usart1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+    hdma_usart1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+    hdma_usart1_rx.Init.Mode = DMA_CIRCULAR;
+    hdma_usart1_rx.Init.Priority = DMA_PRIORITY_LOW;
+    hdma_usart1_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
+    if (HAL_DMA_Init(&hdma_usart1_rx) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    __HAL_LINKDMA(uartHandle,hdmarx,hdma_usart1_rx);
+
     /* USART1 interrupt Init */
     HAL_NVIC_SetPriority(USART1_IRQn, 5, 0);
     HAL_NVIC_EnableIRQ(USART1_IRQn);
@@ -760,6 +839,24 @@ void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle)
 
     __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart2_tx);
 
+    /* USART2_RX Init */
+    hdma_usart2_rx.Instance = DMA2_Stream3;
+    hdma_usart2_rx.Init.Request = DMA_REQUEST_USART2_RX;
+    hdma_usart2_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
+    hdma_usart2_rx.Init.PeriphInc = DMA_PINC_DISABLE;
+    hdma_usart2_rx.Init.MemInc = DMA_MINC_ENABLE;
+    hdma_usart2_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+    hdma_usart2_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+    hdma_usart2_rx.Init.Mode = DMA_CIRCULAR;
+    hdma_usart2_rx.Init.Priority = DMA_PRIORITY_LOW;
+    hdma_usart2_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
+    if (HAL_DMA_Init(&hdma_usart2_rx) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    __HAL_LINKDMA(uartHandle,hdmarx,hdma_usart2_rx);
+
     /* USART2 interrupt Init */
     HAL_NVIC_SetPriority(USART2_IRQn, 5, 0);
     HAL_NVIC_EnableIRQ(USART2_IRQn);
@@ -823,6 +920,24 @@ void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle)
 
     __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart3_tx);
 
+    /* USART3_RX Init */
+    hdma_usart3_rx.Instance = DMA2_Stream4;
+    hdma_usart3_rx.Init.Request = DMA_REQUEST_USART3_RX;
+    hdma_usart3_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
+    hdma_usart3_rx.Init.PeriphInc = DMA_PINC_DISABLE;
+    hdma_usart3_rx.Init.MemInc = DMA_MINC_ENABLE;
+    hdma_usart3_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+    hdma_usart3_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+    hdma_usart3_rx.Init.Mode = DMA_CIRCULAR;
+    hdma_usart3_rx.Init.Priority = DMA_PRIORITY_LOW;
+    hdma_usart3_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
+    if (HAL_DMA_Init(&hdma_usart3_rx) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    __HAL_LINKDMA(uartHandle,hdmarx,hdma_usart3_rx);
+
     /* USART3 interrupt Init */
     HAL_NVIC_SetPriority(USART3_IRQn, 5, 0);
     HAL_NVIC_EnableIRQ(USART3_IRQn);
@@ -886,6 +1001,24 @@ void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle)
 
     __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart6_tx);
 
+    /* USART6_RX Init */
+    hdma_usart6_rx.Instance = DMA2_Stream5;
+    hdma_usart6_rx.Init.Request = DMA_REQUEST_USART6_RX;
+    hdma_usart6_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
+    hdma_usart6_rx.Init.PeriphInc = DMA_PINC_DISABLE;
+    hdma_usart6_rx.Init.MemInc = DMA_MINC_ENABLE;
+    hdma_usart6_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+    hdma_usart6_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+    hdma_usart6_rx.Init.Mode = DMA_CIRCULAR;
+    hdma_usart6_rx.Init.Priority = DMA_PRIORITY_LOW;
+    hdma_usart6_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
+    if (HAL_DMA_Init(&hdma_usart6_rx) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    __HAL_LINKDMA(uartHandle,hdmarx,hdma_usart6_rx);
+
     /* USART6 interrupt Init */
     HAL_NVIC_SetPriority(USART6_IRQn, 5, 0);
     HAL_NVIC_EnableIRQ(USART6_IRQn);
@@ -934,6 +1067,7 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle)
 
     /* UART4 DMA DeInit */
     HAL_DMA_DeInit(uartHandle->hdmatx);
+    HAL_DMA_DeInit(uartHandle->hdmarx);
 
     /* UART4 interrupt Deinit */
     HAL_NVIC_DisableIRQ(UART4_IRQn);
@@ -959,6 +1093,7 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle)
 
     /* UART5 DMA DeInit */
     HAL_DMA_DeInit(uartHandle->hdmatx);
+    HAL_DMA_DeInit(uartHandle->hdmarx);
 
     /* UART5 interrupt Deinit */
     HAL_NVIC_DisableIRQ(UART5_IRQn);
@@ -982,6 +1117,7 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle)
 
     /* UART7 DMA DeInit */
     HAL_DMA_DeInit(uartHandle->hdmatx);
+    HAL_DMA_DeInit(uartHandle->hdmarx);
 
     /* UART7 interrupt Deinit */
     HAL_NVIC_DisableIRQ(UART7_IRQn);
@@ -1005,6 +1141,7 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle)
 
     /* USART1 DMA DeInit */
     HAL_DMA_DeInit(uartHandle->hdmatx);
+    HAL_DMA_DeInit(uartHandle->hdmarx);
 
     /* USART1 interrupt Deinit */
     HAL_NVIC_DisableIRQ(USART1_IRQn);
@@ -1028,6 +1165,7 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle)
 
     /* USART2 DMA DeInit */
     HAL_DMA_DeInit(uartHandle->hdmatx);
+    HAL_DMA_DeInit(uartHandle->hdmarx);
 
     /* USART2 interrupt Deinit */
     HAL_NVIC_DisableIRQ(USART2_IRQn);
@@ -1051,6 +1189,7 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle)
 
     /* USART3 DMA DeInit */
     HAL_DMA_DeInit(uartHandle->hdmatx);
+    HAL_DMA_DeInit(uartHandle->hdmarx);
 
     /* USART3 interrupt Deinit */
     HAL_NVIC_DisableIRQ(USART3_IRQn);
@@ -1074,6 +1213,7 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle)
 
     /* USART6 DMA DeInit */
     HAL_DMA_DeInit(uartHandle->hdmatx);
+    HAL_DMA_DeInit(uartHandle->hdmarx);
 
     /* USART6 interrupt Deinit */
     HAL_NVIC_DisableIRQ(USART6_IRQn);

robot

@@ -1 +1 @@
-Subproject commit c5cc930fea45f1c004e5b9d8466c8c2ff5173858
+Subproject commit 07ad6cb9308feb5b96ee8c341b0de719a7d87cea

robot_h743.ioc

@@ -46,12 +46,37 @@ CORTEX_M7.TypeExtField-Cortex_Memory_Protection_Unit_Region1_Settings=MPU_TEX_LE
 CORTEX_M7.TypeExtField-Cortex_Memory_Protection_Unit_Region2_Settings=MPU_TEX_LEVEL1
 Dma.Request0=UART4_TX
 Dma.Request1=USART1_TX
+Dma.Request10=USART1_RX
+Dma.Request11=USART2_RX
+Dma.Request12=USART3_RX
+Dma.Request13=USART6_RX
 Dma.Request2=UART5_TX
 Dma.Request3=USART2_TX
 Dma.Request4=USART3_TX
 Dma.Request5=USART6_TX
 Dma.Request6=UART7_TX
-Dma.RequestsNb=7
+Dma.Request7=UART4_RX
+Dma.Request8=UART5_RX
+Dma.Request9=UART7_RX
+Dma.RequestsNb=14
+Dma.UART4_RX.7.Direction=DMA_PERIPH_TO_MEMORY
+Dma.UART4_RX.7.EventEnable=DISABLE
+Dma.UART4_RX.7.FIFOMode=DMA_FIFOMODE_DISABLE
+Dma.UART4_RX.7.Instance=DMA1_Stream4
+Dma.UART4_RX.7.MemDataAlignment=DMA_MDATAALIGN_BYTE
+Dma.UART4_RX.7.MemInc=DMA_MINC_ENABLE
+Dma.UART4_RX.7.Mode=DMA_CIRCULAR
+Dma.UART4_RX.7.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
+Dma.UART4_RX.7.PeriphInc=DMA_PINC_DISABLE
+Dma.UART4_RX.7.Polarity=HAL_DMAMUX_REQ_GEN_RISING
+Dma.UART4_RX.7.Priority=DMA_PRIORITY_LOW
+Dma.UART4_RX.7.RequestNumber=1
+Dma.UART4_RX.7.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
+Dma.UART4_RX.7.SignalID=NONE
+Dma.UART4_RX.7.SyncEnable=DISABLE
+Dma.UART4_RX.7.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
+Dma.UART4_RX.7.SyncRequestNumber=1
+Dma.UART4_RX.7.SyncSignalID=NONE
 Dma.UART4_TX.0.Direction=DMA_MEMORY_TO_PERIPH
 Dma.UART4_TX.0.EventEnable=DISABLE
 Dma.UART4_TX.0.FIFOMode=DMA_FIFOMODE_ENABLE
@@ -73,6 +98,24 @@ Dma.UART4_TX.0.SyncEnable=DISABLE
 Dma.UART4_TX.0.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
 Dma.UART4_TX.0.SyncRequestNumber=1
 Dma.UART4_TX.0.SyncSignalID=NONE
+Dma.UART5_RX.8.Direction=DMA_PERIPH_TO_MEMORY
+Dma.UART5_RX.8.EventEnable=DISABLE
+Dma.UART5_RX.8.FIFOMode=DMA_FIFOMODE_DISABLE
+Dma.UART5_RX.8.Instance=DMA2_Stream0
+Dma.UART5_RX.8.MemDataAlignment=DMA_MDATAALIGN_BYTE
+Dma.UART5_RX.8.MemInc=DMA_MINC_ENABLE
+Dma.UART5_RX.8.Mode=DMA_CIRCULAR
+Dma.UART5_RX.8.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
+Dma.UART5_RX.8.PeriphInc=DMA_PINC_DISABLE
+Dma.UART5_RX.8.Polarity=HAL_DMAMUX_REQ_GEN_RISING
+Dma.UART5_RX.8.Priority=DMA_PRIORITY_LOW
+Dma.UART5_RX.8.RequestNumber=1
+Dma.UART5_RX.8.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
+Dma.UART5_RX.8.SignalID=NONE
+Dma.UART5_RX.8.SyncEnable=DISABLE
+Dma.UART5_RX.8.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
+Dma.UART5_RX.8.SyncRequestNumber=1
+Dma.UART5_RX.8.SyncSignalID=NONE
 Dma.UART5_TX.2.Direction=DMA_MEMORY_TO_PERIPH
 Dma.UART5_TX.2.EventEnable=DISABLE
 Dma.UART5_TX.2.FIFOMode=DMA_FIFOMODE_DISABLE
@@ -91,6 +134,24 @@ Dma.UART5_TX.2.SyncEnable=DISABLE
 Dma.UART5_TX.2.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
 Dma.UART5_TX.2.SyncRequestNumber=1
 Dma.UART5_TX.2.SyncSignalID=NONE
+Dma.UART7_RX.9.Direction=DMA_PERIPH_TO_MEMORY
+Dma.UART7_RX.9.EventEnable=DISABLE
+Dma.UART7_RX.9.FIFOMode=DMA_FIFOMODE_DISABLE
+Dma.UART7_RX.9.Instance=DMA2_Stream1
+Dma.UART7_RX.9.MemDataAlignment=DMA_MDATAALIGN_BYTE
+Dma.UART7_RX.9.MemInc=DMA_MINC_ENABLE
+Dma.UART7_RX.9.Mode=DMA_CIRCULAR
+Dma.UART7_RX.9.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
+Dma.UART7_RX.9.PeriphInc=DMA_PINC_DISABLE
+Dma.UART7_RX.9.Polarity=HAL_DMAMUX_REQ_GEN_RISING
+Dma.UART7_RX.9.Priority=DMA_PRIORITY_LOW
+Dma.UART7_RX.9.RequestNumber=1
+Dma.UART7_RX.9.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
+Dma.UART7_RX.9.SignalID=NONE
+Dma.UART7_RX.9.SyncEnable=DISABLE
+Dma.UART7_RX.9.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
+Dma.UART7_RX.9.SyncRequestNumber=1
+Dma.UART7_RX.9.SyncSignalID=NONE
 Dma.UART7_TX.6.Direction=DMA_MEMORY_TO_PERIPH
 Dma.UART7_TX.6.EventEnable=DISABLE
 Dma.UART7_TX.6.FIFOMode=DMA_FIFOMODE_DISABLE
@@ -109,6 +170,24 @@ Dma.UART7_TX.6.SyncEnable=DISABLE
 Dma.UART7_TX.6.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
 Dma.UART7_TX.6.SyncRequestNumber=1
 Dma.UART7_TX.6.SyncSignalID=NONE
+Dma.USART1_RX.10.Direction=DMA_PERIPH_TO_MEMORY
+Dma.USART1_RX.10.EventEnable=DISABLE
+Dma.USART1_RX.10.FIFOMode=DMA_FIFOMODE_DISABLE
+Dma.USART1_RX.10.Instance=DMA2_Stream2
+Dma.USART1_RX.10.MemDataAlignment=DMA_MDATAALIGN_BYTE
+Dma.USART1_RX.10.MemInc=DMA_MINC_ENABLE
+Dma.USART1_RX.10.Mode=DMA_CIRCULAR
+Dma.USART1_RX.10.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
+Dma.USART1_RX.10.PeriphInc=DMA_PINC_DISABLE
+Dma.USART1_RX.10.Polarity=HAL_DMAMUX_REQ_GEN_RISING
+Dma.USART1_RX.10.Priority=DMA_PRIORITY_LOW
+Dma.USART1_RX.10.RequestNumber=1
+Dma.USART1_RX.10.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
+Dma.USART1_RX.10.SignalID=NONE
+Dma.USART1_RX.10.SyncEnable=DISABLE
+Dma.USART1_RX.10.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
+Dma.USART1_RX.10.SyncRequestNumber=1
+Dma.USART1_RX.10.SyncSignalID=NONE
 Dma.USART1_TX.1.Direction=DMA_MEMORY_TO_PERIPH
 Dma.USART1_TX.1.EventEnable=DISABLE
 Dma.USART1_TX.1.FIFOMode=DMA_FIFOMODE_ENABLE
@@ -130,6 +209,24 @@ Dma.USART1_TX.1.SyncEnable=DISABLE
 Dma.USART1_TX.1.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
 Dma.USART1_TX.1.SyncRequestNumber=1
 Dma.USART1_TX.1.SyncSignalID=NONE
+Dma.USART2_RX.11.Direction=DMA_PERIPH_TO_MEMORY
+Dma.USART2_RX.11.EventEnable=DISABLE
+Dma.USART2_RX.11.FIFOMode=DMA_FIFOMODE_DISABLE
+Dma.USART2_RX.11.Instance=DMA2_Stream3
+Dma.USART2_RX.11.MemDataAlignment=DMA_MDATAALIGN_BYTE
+Dma.USART2_RX.11.MemInc=DMA_MINC_ENABLE
+Dma.USART2_RX.11.Mode=DMA_CIRCULAR
+Dma.USART2_RX.11.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
+Dma.USART2_RX.11.PeriphInc=DMA_PINC_DISABLE
+Dma.USART2_RX.11.Polarity=HAL_DMAMUX_REQ_GEN_RISING
+Dma.USART2_RX.11.Priority=DMA_PRIORITY_LOW
+Dma.USART2_RX.11.RequestNumber=1
+Dma.USART2_RX.11.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
+Dma.USART2_RX.11.SignalID=NONE
+Dma.USART2_RX.11.SyncEnable=DISABLE
+Dma.USART2_RX.11.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
+Dma.USART2_RX.11.SyncRequestNumber=1
+Dma.USART2_RX.11.SyncSignalID=NONE
 Dma.USART2_TX.3.Direction=DMA_MEMORY_TO_PERIPH
 Dma.USART2_TX.3.EventEnable=DISABLE
 Dma.USART2_TX.3.FIFOMode=DMA_FIFOMODE_DISABLE
@@ -148,6 +245,24 @@ Dma.USART2_TX.3.SyncEnable=DISABLE
 Dma.USART2_TX.3.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
 Dma.USART2_TX.3.SyncRequestNumber=1
 Dma.USART2_TX.3.SyncSignalID=NONE
+Dma.USART3_RX.12.Direction=DMA_PERIPH_TO_MEMORY
+Dma.USART3_RX.12.EventEnable=DISABLE
+Dma.USART3_RX.12.FIFOMode=DMA_FIFOMODE_DISABLE
+Dma.USART3_RX.12.Instance=DMA2_Stream4
+Dma.USART3_RX.12.MemDataAlignment=DMA_MDATAALIGN_BYTE
+Dma.USART3_RX.12.MemInc=DMA_MINC_ENABLE
+Dma.USART3_RX.12.Mode=DMA_CIRCULAR
+Dma.USART3_RX.12.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
+Dma.USART3_RX.12.PeriphInc=DMA_PINC_DISABLE
+Dma.USART3_RX.12.Polarity=HAL_DMAMUX_REQ_GEN_RISING
+Dma.USART3_RX.12.Priority=DMA_PRIORITY_LOW
+Dma.USART3_RX.12.RequestNumber=1
+Dma.USART3_RX.12.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
+Dma.USART3_RX.12.SignalID=NONE
+Dma.USART3_RX.12.SyncEnable=DISABLE
+Dma.USART3_RX.12.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
+Dma.USART3_RX.12.SyncRequestNumber=1
+Dma.USART3_RX.12.SyncSignalID=NONE
 Dma.USART3_TX.4.Direction=DMA_MEMORY_TO_PERIPH
 Dma.USART3_TX.4.EventEnable=DISABLE
 Dma.USART3_TX.4.FIFOMode=DMA_FIFOMODE_DISABLE
@@ -166,6 +281,24 @@ Dma.USART3_TX.4.SyncEnable=DISABLE
 Dma.USART3_TX.4.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
 Dma.USART3_TX.4.SyncRequestNumber=1
 Dma.USART3_TX.4.SyncSignalID=NONE
+Dma.USART6_RX.13.Direction=DMA_PERIPH_TO_MEMORY
+Dma.USART6_RX.13.EventEnable=DISABLE
+Dma.USART6_RX.13.FIFOMode=DMA_FIFOMODE_DISABLE
+Dma.USART6_RX.13.Instance=DMA2_Stream5
+Dma.USART6_RX.13.MemDataAlignment=DMA_MDATAALIGN_BYTE
+Dma.USART6_RX.13.MemInc=DMA_MINC_ENABLE
+Dma.USART6_RX.13.Mode=DMA_CIRCULAR
+Dma.USART6_RX.13.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
+Dma.USART6_RX.13.PeriphInc=DMA_PINC_DISABLE
+Dma.USART6_RX.13.Polarity=HAL_DMAMUX_REQ_GEN_RISING
+Dma.USART6_RX.13.Priority=DMA_PRIORITY_LOW
+Dma.USART6_RX.13.RequestNumber=1
+Dma.USART6_RX.13.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
+Dma.USART6_RX.13.SignalID=NONE
+Dma.USART6_RX.13.SyncEnable=DISABLE
+Dma.USART6_RX.13.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
+Dma.USART6_RX.13.SyncRequestNumber=1
+Dma.USART6_RX.13.SyncSignalID=NONE
 Dma.USART6_TX.5.Direction=DMA_MEMORY_TO_PERIPH
 Dma.USART6_TX.5.EventEnable=DISABLE
 Dma.USART6_TX.5.FIFOMode=DMA_FIFOMODE_DISABLE
@@ -377,9 +510,16 @@ NVIC.DMA1_Stream0_IRQn=true\:5\:0\:true\:false\:true\:true\:false\:true\:true
 NVIC.DMA1_Stream1_IRQn=true\:5\:0\:true\:false\:true\:true\:false\:true\:true
 NVIC.DMA1_Stream2_IRQn=true\:5\:0\:true\:false\:true\:true\:false\:true\:true
 NVIC.DMA1_Stream3_IRQn=true\:5\:0\:true\:false\:true\:true\:false\:true\:true
+NVIC.DMA1_Stream4_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
 NVIC.DMA1_Stream5_IRQn=true\:5\:0\:true\:false\:true\:true\:false\:true\:true
 NVIC.DMA1_Stream6_IRQn=true\:5\:0\:true\:false\:true\:true\:false\:true\:true
 NVIC.DMA1_Stream7_IRQn=true\:5\:0\:true\:false\:true\:true\:false\:true\:true
+NVIC.DMA2_Stream0_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
+NVIC.DMA2_Stream1_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
+NVIC.DMA2_Stream2_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
+NVIC.DMA2_Stream3_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
+NVIC.DMA2_Stream4_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
+NVIC.DMA2_Stream5_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
 NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
 NVIC.ETH_IRQn=true\:5\:0\:true\:false\:true\:true\:true\:true\:true
 NVIC.ETH_WKUP_IRQn=true\:5\:0\:true\:false\:true\:true\:true\:true\:true