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调整优先级

main
Lizongdi 1 day ago
parent
3e966e60b4
commit
b19bfb5c80
7 changed files with 42 additions and 42 deletions
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  1. 2
      Core/Inc/stm32h7xx_hal_conf.h
  2. 14
      Core/Src/dma.c
  3. 4
      Core/Src/fdcan.c
  4. 4
      Core/Src/tim.c
  5. 16
      Core/Src/usart.c
  6. 2
      LWIP/Target/ethernetif.c
  7. 42
      robot_old.ioc

2
Core/Inc/stm32h7xx_hal_conf.h
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@ -165,7 +165,7 @@
* @brief This is the HAL system configuration section * @brief This is the HAL system configuration section
*/ */
#define VDD_VALUE (3300UL) /*!< Value of VDD in mv */ #define VDD_VALUE (3300UL) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY (15UL) /*!< tick interrupt priority */ #define TICK_INT_PRIORITY (0UL) /*!< tick interrupt priority */
#define USE_RTOS 0 #define USE_RTOS 0
#define USE_SD_TRANSCEIVER 0U /*!< use uSD Transceiver */ #define USE_SD_TRANSCEIVER 0U /*!< use uSD Transceiver */
#define USE_SPI_CRC 0U /*!< use CRC in SPI */ #define USE_SPI_CRC 0U /*!< use CRC in SPI */

14
Core/Src/dma.c
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@ -44,25 +44,25 @@ void MX_DMA_Init(void)
/* DMA interrupt init */ /* DMA interrupt init */
/* DMA1_Stream0_IRQn interrupt configuration */ /* DMA1_Stream0_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 5, 0); HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 3, 0);
HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn); HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn);
/* DMA1_Stream1_IRQn interrupt configuration */ /* DMA1_Stream1_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DMA1_Stream1_IRQn, 5, 0); HAL_NVIC_SetPriority(DMA1_Stream1_IRQn, 3, 0);
HAL_NVIC_EnableIRQ(DMA1_Stream1_IRQn); HAL_NVIC_EnableIRQ(DMA1_Stream1_IRQn);
/* DMA1_Stream2_IRQn interrupt configuration */ /* DMA1_Stream2_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DMA1_Stream2_IRQn, 5, 0); HAL_NVIC_SetPriority(DMA1_Stream2_IRQn, 3, 0);
HAL_NVIC_EnableIRQ(DMA1_Stream2_IRQn); HAL_NVIC_EnableIRQ(DMA1_Stream2_IRQn);
/* DMA1_Stream3_IRQn interrupt configuration */ /* DMA1_Stream3_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DMA1_Stream3_IRQn, 5, 0); HAL_NVIC_SetPriority(DMA1_Stream3_IRQn, 3, 0);
HAL_NVIC_EnableIRQ(DMA1_Stream3_IRQn); HAL_NVIC_EnableIRQ(DMA1_Stream3_IRQn);
/* DMA1_Stream5_IRQn interrupt configuration */ /* DMA1_Stream5_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DMA1_Stream5_IRQn, 5, 0); HAL_NVIC_SetPriority(DMA1_Stream5_IRQn, 3, 0);
HAL_NVIC_EnableIRQ(DMA1_Stream5_IRQn); HAL_NVIC_EnableIRQ(DMA1_Stream5_IRQn);
/* DMA1_Stream6_IRQn interrupt configuration */ /* DMA1_Stream6_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DMA1_Stream6_IRQn, 5, 0); HAL_NVIC_SetPriority(DMA1_Stream6_IRQn, 3, 0);
HAL_NVIC_EnableIRQ(DMA1_Stream6_IRQn); HAL_NVIC_EnableIRQ(DMA1_Stream6_IRQn);
/* DMA1_Stream7_IRQn interrupt configuration */ /* DMA1_Stream7_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DMA1_Stream7_IRQn, 5, 0); HAL_NVIC_SetPriority(DMA1_Stream7_IRQn, 3, 0);
HAL_NVIC_EnableIRQ(DMA1_Stream7_IRQn); HAL_NVIC_EnableIRQ(DMA1_Stream7_IRQn);
} }

4
Core/Src/fdcan.c
View File

@ -165,7 +165,7 @@ void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef* fdcanHandle)
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
/* FDCAN1 interrupt Init */ /* FDCAN1 interrupt Init */
HAL_NVIC_SetPriority(FDCAN1_IT0_IRQn, 5, 0); HAL_NVIC_SetPriority(FDCAN1_IT0_IRQn, 2, 0);
HAL_NVIC_EnableIRQ(FDCAN1_IT0_IRQn); HAL_NVIC_EnableIRQ(FDCAN1_IT0_IRQn);
/* USER CODE BEGIN FDCAN1_MspInit 1 */ /* USER CODE BEGIN FDCAN1_MspInit 1 */
@ -205,7 +205,7 @@ void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef* fdcanHandle)
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
/* FDCAN2 interrupt Init */ /* FDCAN2 interrupt Init */
HAL_NVIC_SetPriority(FDCAN2_IT0_IRQn, 5, 0); HAL_NVIC_SetPriority(FDCAN2_IT0_IRQn, 2, 0);
HAL_NVIC_EnableIRQ(FDCAN2_IT0_IRQn); HAL_NVIC_EnableIRQ(FDCAN2_IT0_IRQn);
/* USER CODE BEGIN FDCAN2_MspInit 1 */ /* USER CODE BEGIN FDCAN2_MspInit 1 */

4
Core/Src/tim.c
View File

@ -124,7 +124,7 @@ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle)
__HAL_RCC_TIM1_CLK_ENABLE(); __HAL_RCC_TIM1_CLK_ENABLE();
/* TIM1 interrupt Init */ /* TIM1 interrupt Init */
HAL_NVIC_SetPriority(TIM1_UP_IRQn, 5, 0); HAL_NVIC_SetPriority(TIM1_UP_IRQn, 1, 0);
HAL_NVIC_EnableIRQ(TIM1_UP_IRQn); HAL_NVIC_EnableIRQ(TIM1_UP_IRQn);
/* USER CODE BEGIN TIM1_MspInit 1 */ /* USER CODE BEGIN TIM1_MspInit 1 */
@ -139,7 +139,7 @@ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle)
__HAL_RCC_TIM8_CLK_ENABLE(); __HAL_RCC_TIM8_CLK_ENABLE();
/* TIM8 interrupt Init */ /* TIM8 interrupt Init */
HAL_NVIC_SetPriority(TIM8_UP_TIM13_IRQn, 5, 0); HAL_NVIC_SetPriority(TIM8_UP_TIM13_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(TIM8_UP_TIM13_IRQn); HAL_NVIC_EnableIRQ(TIM8_UP_TIM13_IRQn);
/* USER CODE BEGIN TIM8_MspInit 1 */ /* USER CODE BEGIN TIM8_MspInit 1 */

16
Core/Src/usart.c
View File

@ -439,7 +439,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle)
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
/* LPUART1 interrupt Init */ /* LPUART1 interrupt Init */
HAL_NVIC_SetPriority(LPUART1_IRQn, 5, 0); HAL_NVIC_SetPriority(LPUART1_IRQn, 4, 0);
HAL_NVIC_EnableIRQ(LPUART1_IRQn); HAL_NVIC_EnableIRQ(LPUART1_IRQn);
/* USER CODE BEGIN LPUART1_MspInit 1 */ /* USER CODE BEGIN LPUART1_MspInit 1 */
@ -505,7 +505,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle)
__HAL_LINKDMA(uartHandle,hdmatx,hdma_uart4_tx); __HAL_LINKDMA(uartHandle,hdmatx,hdma_uart4_tx);
/* UART4 interrupt Init */ /* UART4 interrupt Init */
HAL_NVIC_SetPriority(UART4_IRQn, 5, 0); HAL_NVIC_SetPriority(UART4_IRQn, 4, 0);
HAL_NVIC_EnableIRQ(UART4_IRQn); HAL_NVIC_EnableIRQ(UART4_IRQn);
/* USER CODE BEGIN UART4_MspInit 1 */ /* USER CODE BEGIN UART4_MspInit 1 */
@ -569,7 +569,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle)
__HAL_LINKDMA(uartHandle,hdmatx,hdma_uart5_tx); __HAL_LINKDMA(uartHandle,hdmatx,hdma_uart5_tx);
/* UART5 interrupt Init */ /* UART5 interrupt Init */
HAL_NVIC_SetPriority(UART5_IRQn, 5, 0); HAL_NVIC_SetPriority(UART5_IRQn, 4, 0);
HAL_NVIC_EnableIRQ(UART5_IRQn); HAL_NVIC_EnableIRQ(UART5_IRQn);
/* USER CODE BEGIN UART5_MspInit 1 */ /* USER CODE BEGIN UART5_MspInit 1 */
@ -632,7 +632,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle)
__HAL_LINKDMA(uartHandle,hdmatx,hdma_uart7_tx); __HAL_LINKDMA(uartHandle,hdmatx,hdma_uart7_tx);
/* UART7 interrupt Init */ /* UART7 interrupt Init */
HAL_NVIC_SetPriority(UART7_IRQn, 5, 0); HAL_NVIC_SetPriority(UART7_IRQn, 4, 0);
HAL_NVIC_EnableIRQ(UART7_IRQn); HAL_NVIC_EnableIRQ(UART7_IRQn);
/* USER CODE BEGIN UART7_MspInit 1 */ /* USER CODE BEGIN UART7_MspInit 1 */
@ -698,7 +698,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle)
__HAL_LINKDMA(uartHandle,hdmatx,hdma_usart1_tx); __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart1_tx);
/* USART1 interrupt Init */ /* USART1 interrupt Init */
HAL_NVIC_SetPriority(USART1_IRQn, 5, 0); HAL_NVIC_SetPriority(USART1_IRQn, 4, 0);
HAL_NVIC_EnableIRQ(USART1_IRQn); HAL_NVIC_EnableIRQ(USART1_IRQn);
/* USER CODE BEGIN USART1_MspInit 1 */ /* USER CODE BEGIN USART1_MspInit 1 */
@ -761,7 +761,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle)
__HAL_LINKDMA(uartHandle,hdmatx,hdma_usart2_tx); __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart2_tx);
/* USART2 interrupt Init */ /* USART2 interrupt Init */
HAL_NVIC_SetPriority(USART2_IRQn, 5, 0); HAL_NVIC_SetPriority(USART2_IRQn, 4, 0);
HAL_NVIC_EnableIRQ(USART2_IRQn); HAL_NVIC_EnableIRQ(USART2_IRQn);
/* USER CODE BEGIN USART2_MspInit 1 */ /* USER CODE BEGIN USART2_MspInit 1 */
@ -824,7 +824,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle)
__HAL_LINKDMA(uartHandle,hdmatx,hdma_usart3_tx); __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart3_tx);
/* USART3 interrupt Init */ /* USART3 interrupt Init */
HAL_NVIC_SetPriority(USART3_IRQn, 0, 0); HAL_NVIC_SetPriority(USART3_IRQn, 4, 0);
HAL_NVIC_EnableIRQ(USART3_IRQn); HAL_NVIC_EnableIRQ(USART3_IRQn);
/* USER CODE BEGIN USART3_MspInit 1 */ /* USER CODE BEGIN USART3_MspInit 1 */
@ -887,7 +887,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle)
__HAL_LINKDMA(uartHandle,hdmatx,hdma_usart6_tx); __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart6_tx);
/* USART6 interrupt Init */ /* USART6 interrupt Init */
HAL_NVIC_SetPriority(USART6_IRQn, 5, 0); HAL_NVIC_SetPriority(USART6_IRQn, 4, 0);
HAL_NVIC_EnableIRQ(USART6_IRQn); HAL_NVIC_EnableIRQ(USART6_IRQn);
/* USER CODE BEGIN USART6_MspInit 1 */ /* USER CODE BEGIN USART6_MspInit 1 */

2
LWIP/Target/ethernetif.c
View File

@ -523,7 +523,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* ethHandle)
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
/* Peripheral interrupt init */ /* Peripheral interrupt init */
HAL_NVIC_SetPriority(ETH_IRQn, 5, 0); HAL_NVIC_SetPriority(ETH_IRQn, 4, 0);
HAL_NVIC_EnableIRQ(ETH_IRQn); HAL_NVIC_EnableIRQ(ETH_IRQn);
HAL_NVIC_SetPriority(ETH_WKUP_IRQn, 5, 0); HAL_NVIC_SetPriority(ETH_WKUP_IRQn, 5, 0);
HAL_NVIC_EnableIRQ(ETH_WKUP_IRQn); HAL_NVIC_EnableIRQ(ETH_WKUP_IRQn);

42
robot_old.ioc
View File

@ -355,38 +355,38 @@ Mcu.UserName=STM32H743VGTx
MxCube.Version=6.17.0 MxCube.Version=6.17.0
MxDb.Version=DB.6.0.170 MxDb.Version=DB.6.0.170
NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.DMA1_Stream0_IRQn=true\:5\:0\:true\:false\:true\:false\:true\:true NVIC.DMA1_Stream0_IRQn=true\:3\:0\:true\:false\:true\:false\:true\:true
NVIC.DMA1_Stream1_IRQn=true\:5\:0\:true\:false\:true\:false\:true\:true NVIC.DMA1_Stream1_IRQn=true\:3\:0\:true\:false\:true\:false\:true\:true
NVIC.DMA1_Stream2_IRQn=true\:5\:0\:true\:false\:true\:false\:true\:true NVIC.DMA1_Stream2_IRQn=true\:3\:0\:true\:false\:true\:false\:true\:true
NVIC.DMA1_Stream3_IRQn=true\:5\:0\:true\:false\:true\:false\:true\:true NVIC.DMA1_Stream3_IRQn=true\:3\:0\:true\:false\:true\:false\:true\:true
NVIC.DMA1_Stream5_IRQn=true\:5\:0\:true\:false\:true\:false\:true\:true NVIC.DMA1_Stream5_IRQn=true\:3\:0\:true\:false\:true\:false\:true\:true
NVIC.DMA1_Stream6_IRQn=true\:5\:0\:true\:false\:true\:false\:true\:true NVIC.DMA1_Stream6_IRQn=true\:3\:0\:true\:false\:true\:false\:true\:true
NVIC.DMA1_Stream7_IRQn=true\:5\:0\:true\:false\:true\:false\:true\:true NVIC.DMA1_Stream7_IRQn=true\:3\:0\:true\:false\:true\:false\:true\:true
NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.ETH_IRQn=true\:5\:0\:true\:false\:true\:true\:true\:true NVIC.ETH_IRQn=true\:4\:0\:true\:false\:true\:true\:true\:true
NVIC.ETH_WKUP_IRQn=true\:5\:0\:true\:false\:true\:true\:true\:true NVIC.ETH_WKUP_IRQn=true\:5\:0\:true\:false\:true\:true\:true\:true
NVIC.FDCAN1_IT0_IRQn=true\:5\:0\:true\:false\:true\:true\:true\:true NVIC.FDCAN1_IT0_IRQn=true\:2\:0\:true\:false\:true\:true\:true\:true
NVIC.FDCAN2_IT0_IRQn=true\:5\:0\:true\:false\:true\:true\:true\:true NVIC.FDCAN2_IT0_IRQn=true\:2\:0\:true\:false\:true\:true\:true\:true
NVIC.ForceEnableDMAVector=true NVIC.ForceEnableDMAVector=true
NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.I2C4_ER_IRQn=true\:15\:0\:true\:false\:true\:true\:true\:true NVIC.I2C4_ER_IRQn=true\:15\:0\:true\:false\:true\:true\:true\:true
NVIC.I2C4_EV_IRQn=true\:15\:0\:true\:false\:true\:true\:true\:true NVIC.I2C4_EV_IRQn=true\:15\:0\:true\:false\:true\:true\:true\:true
NVIC.LPUART1_IRQn=true\:5\:0\:true\:false\:true\:true\:true\:true NVIC.LPUART1_IRQn=true\:4\:0\:true\:false\:true\:true\:true\:true
NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:false NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:false
NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.SysTick_IRQn=true\:15\:0\:true\:false\:true\:false\:true\:false NVIC.SysTick_IRQn=true\:0\:0\:true\:false\:true\:false\:true\:false
NVIC.TIM1_UP_IRQn=true\:5\:0\:true\:false\:true\:true\:true\:true NVIC.TIM1_UP_IRQn=true\:1\:0\:true\:false\:true\:true\:true\:true
NVIC.TIM8_UP_TIM13_IRQn=true\:5\:0\:true\:false\:true\:true\:true\:true NVIC.TIM8_UP_TIM13_IRQn=true\:0\:0\:true\:false\:true\:true\:true\:true
NVIC.UART4_IRQn=true\:5\:0\:true\:false\:true\:true\:true\:true NVIC.UART4_IRQn=true\:4\:0\:true\:false\:true\:true\:true\:true
NVIC.UART5_IRQn=true\:5\:0\:true\:false\:true\:true\:true\:true NVIC.UART5_IRQn=true\:4\:0\:true\:false\:true\:true\:true\:true
NVIC.UART7_IRQn=true\:5\:0\:true\:false\:true\:true\:true\:true NVIC.UART7_IRQn=true\:4\:0\:true\:false\:true\:true\:true\:true
NVIC.USART1_IRQn=true\:5\:0\:true\:false\:true\:true\:true\:true NVIC.USART1_IRQn=true\:4\:0\:true\:false\:true\:true\:true\:true
NVIC.USART2_IRQn=true\:5\:0\:true\:false\:true\:true\:true\:true NVIC.USART2_IRQn=true\:4\:0\:true\:false\:true\:true\:true\:true
NVIC.USART3_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true NVIC.USART3_IRQn=true\:4\:0\:true\:false\:true\:true\:true\:true
NVIC.USART6_IRQn=true\:5\:0\:true\:false\:true\:true\:true\:true NVIC.USART6_IRQn=true\:4\:0\:true\:false\:true\:true\:true\:true
NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
PA0.GPIOParameters=GPIO_Label,PinAttribute PA0.GPIOParameters=GPIO_Label,PinAttribute
PA0.GPIO_Label=OUT_2 PA0.GPIO_Label=OUT_2

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